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x86: re-work operand swapping for XOP shift/rotate insns
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e6123d0c
JB		 12020-07-08 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
4 Vex_2src_2): Delete.
5 (OP_VexW, VexW): New.
6 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
7 for shifts and rotates by register.
8
93abb146
JB		 92020-07-08 Jan Beulich <jbeulich@suse.com>
10
11 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
12 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
13 OP_EX_VexReg): Delete.
14 (OP_VexI4, VexI4): New.
15 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
16 (prefix_table): ... here.
17 (print_insn): Drop setting of vex_w_done.
18
b13b1bc0
JB		 192020-07-08 Jan Beulich <jbeulich@suse.com>
20
21 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
22 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
23 (xop_table): Replace operands of 4-operand insns.
24 (OP_REG_VexI4): Move VEX.W based operand swaping here.
25
f337259f
CZ		 262020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
27
28 * arc-opc.c (insert_rbd): New function.
29 (RBD): Define.
30 (RBDdup): Likewise.
31 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
32 instructions.
33
931452b6
JB		 342020-07-07 Jan Beulich <jbeulich@suse.com>
35
36 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
37 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
38 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
39 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
40 Delete.
41 (putop): Handle "BW".
42 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
43 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
44 and 0F3A3F ...
45 * i386-dis-evex-prefix.h: ... here.
46
b5b098c2
JB		 472020-07-06 Jan Beulich <jbeulich@suse.com>
48
49 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
50 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
51 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
52 VEX_W_0FXOP_09_83): New enumerators.
53 (xop_table): Reference the above.
54 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
55 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
56 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
57 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
58
21a3faeb
JB		 592020-07-06 Jan Beulich <jbeulich@suse.com>
60
61 * i386-dis.c (EVEX_W_0F3838_P_1,
62 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
63 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
64 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
65 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
66 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
67 (putop): Centralize management of last[]. Delete SAVE_LAST.
68 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
69 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
70 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
71 * i386-dis-evex-prefix.h: here.
72
bc152a17
JB		 732020-07-06 Jan Beulich <jbeulich@suse.com>
74
75 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
76 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
77 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
78 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
79 enumerators.
80 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
81 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
82 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
83 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
84 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
85 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
86 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
87 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
88 these, respectively.
89 * i386-dis-evex-len.h: Adjust comments.
90 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
91 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
92 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
93 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
94 MOD_EVEX_0F385B_P_2_W_1 table entries.
95 * i386-dis-evex-w.h: Reference mod_table[] for
96 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
97 EVEX_W_0F385B_P_2.
98
c82a99a0
JB		 992020-07-06 Jan Beulich <jbeulich@suse.com>
100
101 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
102 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
103 EXymm.
104 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
105 Likewise. Mark 256-bit entries invalid.
106
fedfb81e
JB		 1072020-07-06 Jan Beulich <jbeulich@suse.com>
108
109 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
110 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
111 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
112 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
113 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
114 PREFIX_EVEX_0F382B): Delete.
115 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
116 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
117 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
118 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
119 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
120 to ...
121 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
122 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
123 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
124 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
125 respectively.
126 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
127 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
128 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
129 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
130 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
131 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
132 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
133 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
134 PREFIX_EVEX_0F382B): Remove table entries.
135 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
136 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
137 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
138
3a57774c
JB		 1392020-07-06 Jan Beulich <jbeulich@suse.com>
140
141 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
142 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
143 enumerators.
144 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
145 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
146 EVEX_LEN_0F3A01_P_2_W_1 table entries.
147 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
148 entries.
149
e74d9fa9
JB		 1502020-07-06 Jan Beulich <jbeulich@suse.com>
151
152 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
153 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
154 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
155 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
156 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
157 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
158 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
159 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
160 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
161 entries.
162
6431c801
JB		 1632020-07-06 Jan Beulich <jbeulich@suse.com>
164
165 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
166 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
167 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
168 respectively.
169 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
170 entries.
171 * i386-dis-evex.h (evex_table): Reference VEX table entry for
172 opcode 0F3A1D.
173 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
174 entry.
175 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
176
6df22cf6
JB		 1772020-07-06 Jan Beulich <jbeulich@suse.com>
178
179 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
180 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
181 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
182 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
183 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
184 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
185 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
186 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
187 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
188 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
189 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
190 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
191 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
192 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
193 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
194 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
195 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
196 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
197 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
198 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
199 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
200 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
201 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
202 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
203 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
204 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
205 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
206 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
207 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
208 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
209 (prefix_table): Add EXxEVexR to FMA table entries.
210 (OP_Rounding): Move abort() invocation.
211 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
212 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
213 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
214 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
215 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
216 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
217 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
218 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
219 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
220 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
221 0F3ACE, 0F3ACF.
222 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
223 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
224 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
225 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
226 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
227 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
228 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
229 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
230 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
231 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
232 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
233 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
234 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
235 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
236 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
237 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
238 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
239 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
240 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
241 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
242 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
243 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
244 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
245 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
246 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
247 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
248 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
249 Delete table entries.
250 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
251 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
252 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
253 Likewise.
254
39e0f456
JB		 2552020-07-06 Jan Beulich <jbeulich@suse.com>
256
257 * i386-dis.c (EXqScalarS): Delete.
258 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
259 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
260
5b872f7d
JB		 2612020-07-06 Jan Beulich <jbeulich@suse.com>
262
263 * i386-dis.c (safe-ctype.h): Include.
264 (EXdScalar, EXqScalar): Delete.
265 (d_scalar_mode, q_scalar_mode): Delete.
266 (prefix_table, vex_len_table): Use EXxmm_md in place of
267 EXdScalar and EXxmm_mq in place of EXqScalar.
268 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
269 d_scalar_mode and q_scalar_mode.
270 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
271 (vmovsd): Use EXxmm_mq.
272
ddc73fa9
NC		 2732020-07-06 Yuri Chornoivan <yurchor@ukr.net>
274
275 PR 26204
276 * arc-dis.c: Fix spelling mistake.
277 * po/opcodes.pot: Regenerate.
278
17550be7
NC		 2792020-07-06 Nick Clifton <nickc@redhat.com>
280
281 * po/pt_BR.po: Updated Brazilian Portugugese translation.
282 * po/uk.po: Updated Ukranian translation.
283
b19d852d
NC		 2842020-07-04 Nick Clifton <nickc@redhat.com>
285
286 * configure: Regenerate.
287 * po/opcodes.pot: Regenerate.
288
b115b9fd
NC		 2892020-07-04 Nick Clifton <nickc@redhat.com>
290
291 Binutils 2.35 branch created.
292
c2ecccb3
L		 2932020-07-02 H.J. Lu <hongjiu.lu@intel.com>
294
295 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
296 * i386-opc.h (VexSwapSources): New.
297 (i386_opcode_modifier): Add vexswapsources.
298 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
299 with two source operands swapped.
300 * i386-tbl.h: Regenerated.
301
08ccfccf
NC		 3022020-06-30 Nelson Chu <nelson.chu@sifive.com>
303
304 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
305 unprivileged CSR can also be initialized.
306
279edac5
AM		 3072020-06-29 Alan Modra <amodra@gmail.com>
308
309 * arm-dis.c: Use C style comments.
310 * cr16-opc.c: Likewise.
311 * ft32-dis.c: Likewise.
312 * moxie-opc.c: Likewise.
313 * tic54x-dis.c: Likewise.
314 * s12z-opc.c: Remove useless comment.
315 * xgate-dis.c: Likewise.
316
e978ad62
L		 3172020-06-26 H.J. Lu <hongjiu.lu@intel.com>
318
319 * i386-opc.tbl: Add a blank line.
320
63112cd6
L		 3212020-06-26 H.J. Lu <hongjiu.lu@intel.com>
322
323 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
324 (VecSIB128): Renamed to ...
325 (VECSIB128): This.
326 (VecSIB256): Renamed to ...
327 (VECSIB256): This.
328 (VecSIB512): Renamed to ...
329 (VECSIB512): This.
330 (VecSIB): Renamed to ...
331 (SIB): This.
332 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 333 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 334 (VecSIB256): Likewise.
335 (VecSIB512): Likewise.
79b32e73 336 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 337 and VecSIB512, respectively.
338
d1c36125
JB		 3392020-06-26 Jan Beulich <jbeulich@suse.com>
340
341 * i386-dis.c: Adjust description of I macro.
342 (x86_64_table): Drop use of I.
343 (float_mem): Replace use of I.
344 (putop): Remove handling of I. Adjust setting/clearing of "alt".
345
2a1bb84c
JB		 3462020-06-26 Jan Beulich <jbeulich@suse.com>
347
348 * i386-dis.c: (print_insn): Avoid straight assignment to
349 priv.orig_sizeflag when processing -M sub-options.
350
8f570d62
JB		 3512020-06-25 Jan Beulich <jbeulich@suse.com>
352
353 * i386-dis.c: Adjust description of J macro.
354 (dis386, x86_64_table, mod_table): Replace J.
355 (putop): Remove handling of J.
356
464dc4af
JB		 3572020-06-25 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
360
589958d6
JB		 3612020-06-25 Jan Beulich <jbeulich@suse.com>
362
363 * i386-dis.c: Adjust description of "LQ" macro.
364 (dis386_twobyte): Use LQ for sysret.
365 (putop): Adjust handling of LQ.
366
39ff0b81
NC		 3672020-06-22 Nelson Chu <nelson.chu@sifive.com>
368
369 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
370 * riscv-dis.c: Include elfxx-riscv.h.
371
d27c357a
JB		 3722020-06-18 H.J. Lu <hongjiu.lu@intel.com>
373
374 * i386-dis.c (prefix_table): Revert the last vmgexit change.
375
6fde587f
CL		 3762020-06-17 Lili Cui <lili.cui@intel.com>
377
378 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
379
efe30057
L		 3802020-06-14 H.J. Lu <hongjiu.lu@intel.com>
381
382 PR gas/26115
383 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
384 * i386-opc.tbl: Likewise.
385 * i386-tbl.h: Regenerated.
386
d8af286f
NC		 3872020-06-12 Nelson Chu <nelson.chu@sifive.com>
388
389 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
390
14962256
AC		 3912020-06-11 Alex Coplan <alex.coplan@arm.com>
392
393 * aarch64-opc.c (SYSREG): New macro for describing system registers.
394 (SR_CORE): Likewise.
395 (SR_FEAT): Likewise.
396 (SR_RNG): Likewise.
397 (SR_V8_1): Likewise.
398 (SR_V8_2): Likewise.
399 (SR_V8_3): Likewise.
400 (SR_V8_4): Likewise.
401 (SR_PAN): Likewise.
402 (SR_RAS): Likewise.
403 (SR_SSBS): Likewise.
404 (SR_SVE): Likewise.
405 (SR_ID_PFR2): Likewise.
406 (SR_PROFILE): Likewise.
407 (SR_MEMTAG): Likewise.
408 (SR_SCXTNUM): Likewise.
409 (aarch64_sys_regs): Refactor to store feature information in the table.
410 (aarch64_sys_reg_supported_p): Collapse logic for system registers
411 that now describe their own features.
412 (aarch64_pstatefield_supported_p): Likewise.
413
f9630fa6
L		 4142020-06-09 H.J. Lu <hongjiu.lu@intel.com>
415
416 * i386-dis.c (prefix_table): Fix a typo in comments.
417
73239888
JB		 4182020-06-09 Jan Beulich <jbeulich@suse.com>
419
420 * i386-dis.c (rex_ignored): Delete.
421 (ckprefix): Drop rex_ignored initialization.
422 (get_valid_dis386): Drop setting of rex_ignored.
423 (print_insn): Drop checking of rex_ignored. Don't record data
424 size prefix as used with VEX-and-alike encodings.
425
18897deb
JB		 4262020-06-09 Jan Beulich <jbeulich@suse.com>
427
428 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
429 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
430 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
431 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
432 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
433 VEX_0F12, and VEX_0F16.
434 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
435 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
436 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
437 from movlps and movhlps. New MOD_0F12_PREFIX_2,
438 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
439 MOD_VEX_0F16_PREFIX_2 entries.
440
97e6786a
JB		 4412020-06-09 Jan Beulich <jbeulich@suse.com>
442
443 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
444 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
445 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
446 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
447 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
448 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
449 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
450 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
451 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
452 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
453 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
454 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
455 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
456 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
457 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
458 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
459 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
460 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
461 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
462 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
463 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
464 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
465 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
466 EVEX_W_0FC6_P_2): Delete.
467 (print_insn): Add EVEX.W vs embedded prefix consistency check
468 to prefix validation.
469 * i386-dis-evex.h (evex_table): Don't further descend for
470 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
471 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
472 and 0F2B.
473 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
474 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
475 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
476 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
477 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
478 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
479 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
480 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
481 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
482 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
483 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
484 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
485 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
486 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
487 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
488 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
489 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
490 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
491 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
492 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
493 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
494 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
495 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
496 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
497 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
498 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
499 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
500
bf926894
JB		 5012020-06-09 Jan Beulich <jbeulich@suse.com>
502
503 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
504 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
505 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
506 vmovmskpX.
507 (print_insn): Drop pointless check against bad_opcode. Split
508 prefix validation into legacy and VEX-and-alike parts.
509 (putop): Re-work 'X' macro handling.
510
a5aaedb9
JB		 5112020-06-09 Jan Beulich <jbeulich@suse.com>
512
513 * i386-dis.c (MOD_0F51): Rename to ...
514 (MOD_0F50): ... this.
515
26417f19
AC		 5162020-06-08 Alex Coplan <alex.coplan@arm.com>
517
518 * arm-dis.c (arm_opcodes): Add dfb.
519 (thumb32_opcodes): Add dfb.
520
8a6fb3f9
JB		 5212020-06-08 Jan Beulich <jbeulich@suse.com>
522
523 * i386-opc.h (reg_entry): Const-qualify reg_name field.
524
1424c35d
AM		 5252020-06-06 Alan Modra <amodra@gmail.com>
526
527 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
528
d3d1cc7b
AM		 5292020-06-05 Alan Modra <amodra@gmail.com>
530
531 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
532 size is large enough.
533
d8740be1
JM		 5342020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
535
536 * disassemble.c (disassemble_init_for_target): Set endian_code for
537 bpf targets.
538 * bpf-desc.c: Regenerate.
539 * bpf-opc.c: Likewise.
540 * bpf-dis.c: Likewise.
541
e9bffec9
JM		 5422020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
543
544 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
545 (cgen_put_insn_value): Likewise.
546 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
547 * cgen-dis.in (print_insn): Likewise.
548 * cgen-ibld.in (insert_1): Likewise.
549 (insert_1): Likewise.
550 (insert_insn_normal): Likewise.
551 (extract_1): Likewise.
552 * bpf-dis.c: Regenerate.
553 * bpf-ibld.c: Likewise.
554 * bpf-ibld.c: Likewise.
555 * cgen-dis.in: Likewise.
556 * cgen-ibld.in: Likewise.
557 * cgen-opc.c: Likewise.
558 * epiphany-dis.c: Likewise.
559 * epiphany-ibld.c: Likewise.
560 * fr30-dis.c: Likewise.
561 * fr30-ibld.c: Likewise.
562 * frv-dis.c: Likewise.
563 * frv-ibld.c: Likewise.
564 * ip2k-dis.c: Likewise.
565 * ip2k-ibld.c: Likewise.
566 * iq2000-dis.c: Likewise.
567 * iq2000-ibld.c: Likewise.
568 * lm32-dis.c: Likewise.
569 * lm32-ibld.c: Likewise.
570 * m32c-dis.c: Likewise.
571 * m32c-ibld.c: Likewise.
572 * m32r-dis.c: Likewise.
573 * m32r-ibld.c: Likewise.
574 * mep-dis.c: Likewise.
575 * mep-ibld.c: Likewise.
576 * mt-dis.c: Likewise.
577 * mt-ibld.c: Likewise.
578 * or1k-dis.c: Likewise.
579 * or1k-ibld.c: Likewise.
580 * xc16x-dis.c: Likewise.
581 * xc16x-ibld.c: Likewise.
582 * xstormy16-dis.c: Likewise.
583 * xstormy16-ibld.c: Likewise.
584
b3db6d07
JM		 5852020-06-04 Jose E. Marchesi <jemarch@gnu.org>
586
587 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
588 (print_insn_): Handle instruction endian.
589 * bpf-dis.c: Regenerate.
590 * bpf-desc.c: Regenerate.
591 * epiphany-dis.c: Likewise.
592 * epiphany-desc.c: Likewise.
593 * fr30-dis.c: Likewise.
594 * fr30-desc.c: Likewise.
595 * frv-dis.c: Likewise.
596 * frv-desc.c: Likewise.
597 * ip2k-dis.c: Likewise.
598 * ip2k-desc.c: Likewise.
599 * iq2000-dis.c: Likewise.
600 * iq2000-desc.c: Likewise.
601 * lm32-dis.c: Likewise.
602 * lm32-desc.c: Likewise.
603 * m32c-dis.c: Likewise.
604 * m32c-desc.c: Likewise.
605 * m32r-dis.c: Likewise.
606 * m32r-desc.c: Likewise.
607 * mep-dis.c: Likewise.
608 * mep-desc.c: Likewise.
609 * mt-dis.c: Likewise.
610 * mt-desc.c: Likewise.
611 * or1k-dis.c: Likewise.
612 * or1k-desc.c: Likewise.
613 * xc16x-dis.c: Likewise.
614 * xc16x-desc.c: Likewise.
615 * xstormy16-dis.c: Likewise.
616 * xstormy16-desc.c: Likewise.
617
4ee4189f
NC		 6182020-06-03 Nick Clifton <nickc@redhat.com>
619
620 * po/sr.po: Updated Serbian translation.
621
44730156
NC		 6222020-06-03 Nelson Chu <nelson.chu@sifive.com>
623
624 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
625 (riscv_get_priv_spec_class): Likewise.
626
3c3d0376
AM		 6272020-06-01 Alan Modra <amodra@gmail.com>
628
629 * bpf-desc.c: Regenerate.
630
78c1c354
JM		 6312020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
632 David Faust <david.faust@oracle.com>
633
634 * bpf-desc.c: Regenerate.
635 * bpf-opc.h: Likewise.
636 * bpf-opc.c: Likewise.
637 * bpf-dis.c: Likewise.
638
efcf5fb5
AM		 6392020-05-28 Alan Modra <amodra@gmail.com>
640
641 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
642 values.
643
ab382d64
AM		 6442020-05-28 Alan Modra <amodra@gmail.com>
645
646 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
647 immediates.
648 (print_insn_ns32k): Revert last change.
649
151f5de4
NC		 6502020-05-28 Nick Clifton <nickc@redhat.com>
651
652 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
653 static.
654
25e1eca8
SL		 6552020-05-26 Sandra Loosemore <sandra@codesourcery.com>
656
657 Fix extraction of signed constants in nios2 disassembler (again).
658
659 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
660 extractions of signed fields.
661
57b17940
SSF		 6622020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
663
664 * s390-opc.txt: Relocate vector load/store instructions with
665 additional alignment parameter and change architecture level
666 constraint from z14 to z13.
667
d96bf37b
AM		 6682020-05-21 Alan Modra <amodra@gmail.com>
669
670 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
671 * sparc-dis.c: Likewise.
672 * tic4x-dis.c: Likewise.
673 * xtensa-dis.c: Likewise.
674 * bpf-desc.c: Regenerate.
675 * epiphany-desc.c: Regenerate.
676 * fr30-desc.c: Regenerate.
677 * frv-desc.c: Regenerate.
678 * ip2k-desc.c: Regenerate.
679 * iq2000-desc.c: Regenerate.
680 * lm32-desc.c: Regenerate.
681 * m32c-desc.c: Regenerate.
682 * m32r-desc.c: Regenerate.
683 * mep-asm.c: Regenerate.
684 * mep-desc.c: Regenerate.
685 * mt-desc.c: Regenerate.
686 * or1k-desc.c: Regenerate.
687 * xc16x-desc.c: Regenerate.
688 * xstormy16-desc.c: Regenerate.
689
8f595e9b
NC		 6902020-05-20 Nelson Chu <nelson.chu@sifive.com>
691
692 * riscv-opc.c (riscv_ext_version_table): The table used to store
693 all information about the supported spec and the corresponding ISA
694 versions. Currently, only Zicsr is supported to verify the
695 correctness of Z sub extension settings. Others will be supported
696 in the future patches.
697 (struct isa_spec_t, isa_specs): List for all supported ISA spec
698 classes and the corresponding strings.
699 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
700 spec class by giving a ISA spec string.
701 * riscv-opc.c (struct priv_spec_t): New structure.
702 (struct priv_spec_t priv_specs): List for all supported privilege spec
703 classes and the corresponding strings.
704 (riscv_get_priv_spec_class): New function. Get the corresponding
705 privilege spec class by giving a spec string.
706 (riscv_get_priv_spec_name): New function. Get the corresponding
707 privilege spec string by giving a CSR version class.
708 * riscv-dis.c: Updated since DECLARE_CSR is changed.
709 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
710 according to the chosen version. Build a hash table riscv_csr_hash to
711 store the valid CSR for the chosen pirv verison. Dump the direct
712 CSR address rather than it's name if it is invalid.
713 (parse_riscv_dis_option_without_args): New function. Parse the options
714 without arguments.
715 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
716 parse the options without arguments first, and then handle the options
717 with arguments. Add the new option -Mpriv-spec, which has argument.
718 * riscv-dis.c (print_riscv_disassembler_options): Add description
719 about the new OBJDUMP option.
720
3d205eb4
PB		 7212020-05-19 Peter Bergner <bergner@linux.ibm.com>
722
723 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
724 WC values on POWER10 sync, dcbf and wait instructions.
725 (insert_pl, extract_pl): New functions.
726 (L2OPT, LS, WC): Use insert_ls and extract_ls.
727 (LS3): New , 3-bit L for sync.
728 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
729 (SC2, PL): New, 2-bit SC and PL for sync and wait.
730 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
731 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
732 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
733 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
734 <wait>: Enable PL operand on POWER10.
735 <dcbf>: Enable L3OPT operand on POWER10.
736 <sync>: Enable SC2 operand on POWER10.
737
a501eb44
SH		 7382020-05-19 Stafford Horne <shorne@gmail.com>
739
740 PR 25184
741 * or1k-asm.c: Regenerate.
742 * or1k-desc.c: Regenerate.
743 * or1k-desc.h: Regenerate.
744 * or1k-dis.c: Regenerate.
745 * or1k-ibld.c: Regenerate.
746 * or1k-opc.c: Regenerate.
747 * or1k-opc.h: Regenerate.
748 * or1k-opinst.c: Regenerate.
749
3b646889
AM		 7502020-05-11 Alan Modra <amodra@gmail.com>
751
752 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
753 xsmaxcqp, xsmincqp.
754
9cc4ce88
AM		 7552020-05-11 Alan Modra <amodra@gmail.com>
756
757 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
758 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
759
5d57bc3f
AM		 7602020-05-11 Alan Modra <amodra@gmail.com>
761
762 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
763
66ef5847
AM		 7642020-05-11 Alan Modra <amodra@gmail.com>
765
766 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
767 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
768
4f3e9537
PB		 7692020-05-11 Peter Bergner <bergner@linux.ibm.com>
770
771 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
772 mnemonics.
773
ec40e91c
AM		 7742020-05-11 Alan Modra <amodra@gmail.com>
775
776 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
777 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
778 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
779 (prefix_opcodes): Add xxeval.
780
d7e97a76
AM		 7812020-05-11 Alan Modra <amodra@gmail.com>
782
783 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
784 xxgenpcvwm, xxgenpcvdm.
785
fdefed7c
AM		 7862020-05-11 Alan Modra <amodra@gmail.com>
787
788 * ppc-opc.c (MP, VXVAM_MASK): Define.
789 (VXVAPS_MASK): Use VXVA_MASK.
790 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
791 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
792 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
793 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
794
aa3c112f
AM		 7952020-05-11 Alan Modra <amodra@gmail.com>
796 Peter Bergner <bergner@linux.ibm.com>
797
798 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
799 New functions.
800 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
801 YMSK2, XA6a, XA6ap, XB6a entries.
802 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
803 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
804 (PPCVSX4): Define.
805 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
806 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
807 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
808 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
809 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
810 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
811 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
812 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
813 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
814 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
815 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
816 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
817 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
818 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
819
6edbfd3b
AM		 8202020-05-11 Alan Modra <amodra@gmail.com>
821
822 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
823 (insert_xts, extract_xts): New functions.
824 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
825 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
826 (VXRC_MASK, VXSH_MASK): Define.
827 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
828 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
829 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
830 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
831 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
832 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
833 xxblendvh, xxblendvw, xxblendvd, xxpermx.
834
c7d7aea2
AM		 8352020-05-11 Alan Modra <amodra@gmail.com>
836
837 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
838 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
839 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
840 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
841 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
842
94ba9882
AM		 8432020-05-11 Alan Modra <amodra@gmail.com>
844
845 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
846 (XTP, DQXP, DQXP_MASK): Define.
847 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
848 (prefix_opcodes): Add plxvp and pstxvp.
849
f4791f1a
AM		 8502020-05-11 Alan Modra <amodra@gmail.com>
851
852 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
853 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
854 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
855
3ff0a5ba
PB		 8562020-05-11 Peter Bergner <bergner@linux.ibm.com>
857
858 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
859
afef4fe9
PB		 8602020-05-11 Peter Bergner <bergner@linux.ibm.com>
861
862 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
863 (L1OPT): Define.
864 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
865
1224c05d
PB		 8662020-05-11 Peter Bergner <bergner@linux.ibm.com>
867
868 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
869
6bbb0c05
AM		 8702020-05-11 Alan Modra <amodra@gmail.com>
871
872 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
873
7c1f4227
AM		 8742020-05-11 Alan Modra <amodra@gmail.com>
875
876 * ppc-dis.c (ppc_opts): Add "power10" entry.
877 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
878 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
879
73199c2b
NC		 8802020-05-11 Nick Clifton <nickc@redhat.com>
881
882 * po/fr.po: Updated French translation.
883
09c1e68a
AC		 8842020-04-30 Alex Coplan <alex.coplan@arm.com>
885
886 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
887 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
888 (operand_general_constraint_met_p): validate
889 AARCH64_OPND_UNDEFINED.
890 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
891 for FLD_imm16_2.
892 * aarch64-asm-2.c: Regenerated.
893 * aarch64-dis-2.c: Regenerated.
894 * aarch64-opc-2.c: Regenerated.
895
9654d51a
NC		 8962020-04-29 Nick Clifton <nickc@redhat.com>
897
898 PR 22699
899 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
900 and SETRC insns.
901
c2e71e57
NC		 9022020-04-29 Nick Clifton <nickc@redhat.com>
903
904 * po/sv.po: Updated Swedish translation.
905
5c936ef5
NC		 9062020-04-29 Nick Clifton <nickc@redhat.com>
907
908 PR 22699
909 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
910 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
911 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
912 IMM0_8U case.
913
bb2a1453
AS		 9142020-04-21 Andreas Schwab <schwab@linux-m68k.org>
915
916 PR 25848
917 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
918 cmpi only on m68020up and cpu32.
919
c2e5c986
SD		 9202020-04-20 Sudakshina Das <sudi.das@arm.com>
921
922 * aarch64-asm.c (aarch64_ins_none): New.
923 * aarch64-asm.h (ins_none): New declaration.
924 * aarch64-dis.c (aarch64_ext_none): New.
925 * aarch64-dis.h (ext_none): New declaration.
926 * aarch64-opc.c (aarch64_print_operand): Update case for
927 AARCH64_OPND_BARRIER_PSB.
928 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
929 (AARCH64_OPERANDS): Update inserter/extracter for
930 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
931 * aarch64-asm-2.c: Regenerated.
932 * aarch64-dis-2.c: Regenerated.
933 * aarch64-opc-2.c: Regenerated.
934
8a6e1d1d
SD		 9352020-04-20 Sudakshina Das <sudi.das@arm.com>
936
937 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
938 (aarch64_feature_ras, RAS): Likewise.
939 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
940 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
941 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
942 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
943 * aarch64-asm-2.c: Regenerated.
944 * aarch64-dis-2.c: Regenerated.
945 * aarch64-opc-2.c: Regenerated.
946
e409955d
FS		 9472020-04-17 Fredrik Strupe <fredrik@strupe.net>
948
949 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
950 (print_insn_neon): Support disassembly of conditional
951 instructions.
952
c54a9b56
DF		 9532020-02-16 David Faust <david.faust@oracle.com>
954
955 * bpf-desc.c: Regenerate.
956 * bpf-desc.h: Likewise.
957 * bpf-opc.c: Regenerate.
958 * bpf-opc.h: Likewise.
959
bb651e8b
CL		 9602020-04-07 Lili Cui <lili.cui@intel.com>
961
962 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
963 (prefix_table): New instructions (see prefixes above).
964 (rm_table): Likewise
965 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
966 CPU_ANY_TSXLDTRK_FLAGS.
967 (cpu_flags): Add CpuTSXLDTRK.
968 * i386-opc.h (enum): Add CpuTSXLDTRK.
969 (i386_cpu_flags): Add cputsxldtrk.
970 * i386-opc.tbl: Add XSUSPLDTRK insns.
971 * i386-init.h: Regenerate.
972 * i386-tbl.h: Likewise.
973
4b27d27c
L		 9742020-04-02 Lili Cui <lili.cui@intel.com>
975
976 * i386-dis.c (prefix_table): New instructions serialize.
977 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
978 CPU_ANY_SERIALIZE_FLAGS.
979 (cpu_flags): Add CpuSERIALIZE.
980 * i386-opc.h (enum): Add CpuSERIALIZE.
981 (i386_cpu_flags): Add cpuserialize.
982 * i386-opc.tbl: Add SERIALIZE insns.
983 * i386-init.h: Regenerate.
984 * i386-tbl.h: Likewise.
985
832a5807
AM		 9862020-03-26 Alan Modra <amodra@gmail.com>
987
988 * disassemble.h (opcodes_assert): Declare.
989 (OPCODES_ASSERT): Define.
990 * disassemble.c: Don't include assert.h. Include opintl.h.
991 (opcodes_assert): New function.
992 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
993 (bfd_h8_disassemble): Reduce size of data array. Correctly
994 calculate maxlen. Omit insn decoding when insn length exceeds
995 maxlen. Exit from nibble loop when looking for E, before
996 accessing next data byte. Move processing of E outside loop.
997 Replace tests of maxlen in loop with assertions.
998
4c4addbe
AM		 9992020-03-26 Alan Modra <amodra@gmail.com>
1000
1001 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1002
a18cd0ca
AM		 10032020-03-25 Alan Modra <amodra@gmail.com>
1004
1005 * z80-dis.c (suffix): Init mybuf.
1006
57cb32b3
AM		 10072020-03-22 Alan Modra <amodra@gmail.com>
1008
1009 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1010 successflly read from section.
1011
beea5cc1
AM		 10122020-03-22 Alan Modra <amodra@gmail.com>
1013
1014 * arc-dis.c (find_format): Use ISO C string concatenation rather
1015 than line continuation within a string. Don't access needs_limm
1016 before testing opcode != NULL.
1017
03704c77
AM		 10182020-03-22 Alan Modra <amodra@gmail.com>
1019
1020 * ns32k-dis.c (print_insn_arg): Update comment.
1021 (print_insn_ns32k): Reduce size of index_offset array, and
1022 initialize, passing -1 to print_insn_arg for args that are not
1023 an index. Don't exit arg loop early. Abort on bad arg number.
1024
d1023b5d
AM		 10252020-03-22 Alan Modra <amodra@gmail.com>
1026
1027 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1028 * s12z-opc.c: Formatting.
1029 (operands_f): Return an int.
1030 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1031 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1032 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1033 (exg_sex_discrim): Likewise.
1034 (create_immediate_operand, create_bitfield_operand),
1035 (create_register_operand_with_size, create_register_all_operand),
1036 (create_register_all16_operand, create_simple_memory_operand),
1037 (create_memory_operand, create_memory_auto_operand): Don't
1038 segfault on malloc failure.
1039 (z_ext24_decode): Return an int status, negative on fail, zero
1040 on success.
1041 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1042 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1043 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1044 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1045 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1046 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1047 (loop_primitive_decode, shift_decode, psh_pul_decode),
1048 (bit_field_decode): Similarly.
1049 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1050 to return value, update callers.
1051 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1052 Don't segfault on NULL operand.
1053 (decode_operation): Return OP_INVALID on first fail.
1054 (decode_s12z): Check all reads, returning -1 on fail.
1055
340f3ac8
AM		 10562020-03-20 Alan Modra <amodra@gmail.com>
1057
1058 * metag-dis.c (print_insn_metag): Don't ignore status from
1059 read_memory_func.
1060
fe90ae8a
AM		 10612020-03-20 Alan Modra <amodra@gmail.com>
1062
1063 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1064 Initialize parts of buffer not written when handling a possible
1065 2-byte insn at end of section. Don't attempt decoding of such
1066 an insn by the 4-byte machinery.
1067
833d919c
AM		 10682020-03-20 Alan Modra <amodra@gmail.com>
1069
1070 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1071 partially filled buffer. Prevent lookup of 4-byte insns when
1072 only VLE 2-byte insns are possible due to section size. Print
1073 ".word" rather than ".long" for 2-byte leftovers.
1074
327ef784
NC		 10752020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1076
1077 PR 25641
1078 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1079
1673df32
JB		 10802020-03-13 Jan Beulich <jbeulich@suse.com>
1081
1082 * i386-dis.c (X86_64_0D): Rename to ...
1083 (X86_64_0E): ... this.
1084
384f3689
L		 10852020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1086
1087 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1088 * Makefile.in: Regenerated.
1089
865e2027
JB		 10902020-03-09 Jan Beulich <jbeulich@suse.com>
1091
1092 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1093 3-operand pseudos.
1094 * i386-tbl.h: Re-generate.
1095
2f13234b
JB		 10962020-03-09 Jan Beulich <jbeulich@suse.com>
1097
1098 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1099 vprot*, vpsha*, and vpshl*.
1100 * i386-tbl.h: Re-generate.
1101
3fabc179
JB		 11022020-03-09 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1105 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1106 * i386-tbl.h: Re-generate.
1107
3677e4c1
JB		 11082020-03-09 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1111 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1112 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1113 * i386-tbl.h: Re-generate.
1114
4c4898e8
JB		 11152020-03-09 Jan Beulich <jbeulich@suse.com>
1116
1117 * i386-gen.c (struct template_arg, struct template_instance,
1118 struct template_param, struct template, templates,
1119 parse_template, expand_templates): New.
1120 (process_i386_opcodes): Various local variables moved to
1121 expand_templates. Call parse_template and expand_templates.
1122 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1123 * i386-tbl.h: Re-generate.
1124
bc49bfd8
JB		 11252020-03-06 Jan Beulich <jbeulich@suse.com>
1126
1127 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1128 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1129 register and memory source templates. Replace VexW= by VexW*
1130 where applicable.
1131 * i386-tbl.h: Re-generate.
1132
4873e243
JB		 11332020-03-06 Jan Beulich <jbeulich@suse.com>
1134
1135 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1136 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1137 * i386-tbl.h: Re-generate.
1138
672a349b
JB		 11392020-03-06 Jan Beulich <jbeulich@suse.com>
1140
1141 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1142 * i386-tbl.h: Re-generate.
1143
4ed21b58
JB		 11442020-03-06 Jan Beulich <jbeulich@suse.com>
1145
1146 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1147 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1148 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1149 VexW0 on SSE2AVX variants.
1150 (vmovq): Drop NoRex64 from XMM/XMM variants.
1151 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1152 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1153 applicable use VexW0.
1154 * i386-tbl.h: Re-generate.
1155
643bb870
JB		 11562020-03-06 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1159 * i386-opc.h (Rex64): Delete.
1160 (struct i386_opcode_modifier): Remove rex64 field.
1161 * i386-opc.tbl (crc32): Drop Rex64.
1162 Replace Rex64 with Size64 everywhere else.
1163 * i386-tbl.h: Re-generate.
1164
a23b33b3
JB		 11652020-03-06 Jan Beulich <jbeulich@suse.com>
1166
1167 * i386-dis.c (OP_E_memory): Exclude recording of used address
1168 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1169 addressed memory operands for MPX insns.
1170
a0497384
JB		 11712020-03-06 Jan Beulich <jbeulich@suse.com>
1172
1173 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1174 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1175 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1176 (ptwrite): Split into non-64-bit and 64-bit forms.
1177 * i386-tbl.h: Re-generate.
1178
b630c145
JB		 11792020-03-06 Jan Beulich <jbeulich@suse.com>
1180
1181 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1182 template.
1183 * i386-tbl.h: Re-generate.
1184
a847e322
JB		 11852020-03-04 Jan Beulich <jbeulich@suse.com>
1186
1187 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1188 (prefix_table): Move vmmcall here. Add vmgexit.
1189 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1190 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1191 (cpu_flags): Add CpuSEV_ES entry.
1192 * i386-opc.h (CpuSEV_ES): New.
1193 (union i386_cpu_flags): Add cpusev_es field.
1194 * i386-opc.tbl (vmgexit): New.
1195 * i386-init.h, i386-tbl.h: Re-generate.
1196
3cd7f3e3
L		 11972020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1198
1199 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1200 with MnemonicSize.
1201 * i386-opc.h (IGNORESIZE): New.
1202 (DEFAULTSIZE): Likewise.
1203 (IgnoreSize): Removed.
1204 (DefaultSize): Likewise.
1205 (MnemonicSize): New.
1206 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1207 mnemonicsize.
1208 * i386-opc.tbl (IgnoreSize): New.
1209 (DefaultSize): Likewise.
1210 * i386-tbl.h: Regenerated.
1211
b8ba1385
SB		 12122020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1213
1214 PR 25627
1215 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1216 instructions.
1217
10d97a0f
L		 12182020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1219
1220 PR gas/25622
1221 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1222 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1223 * i386-tbl.h: Regenerated.
1224
dc1e8a47
AM		 12252020-02-26 Alan Modra <amodra@gmail.com>
1226
1227 * aarch64-asm.c: Indent labels correctly.
1228 * aarch64-dis.c: Likewise.
1229 * aarch64-gen.c: Likewise.
1230 * aarch64-opc.c: Likewise.
1231 * alpha-dis.c: Likewise.
1232 * i386-dis.c: Likewise.
1233 * nds32-asm.c: Likewise.
1234 * nfp-dis.c: Likewise.
1235 * visium-dis.c: Likewise.
1236
265b4673
CZ		 12372020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1238
1239 * arc-regs.h (int_vector_base): Make it available for all ARC
1240 CPUs.
1241
bd0cf5a6
NC		 12422020-02-20 Nelson Chu <nelson.chu@sifive.com>
1243
1244 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1245 changed.
1246
fa164239
JW		 12472020-02-19 Nelson Chu <nelson.chu@sifive.com>
1248
1249 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1250 c.mv/c.li if rs1 is zero.
1251
272a84b1
L		 12522020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1255 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1256 CPU_POPCNT_FLAGS.
1257 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1258 * i386-opc.h (CpuABM): Removed.
1259 (CpuPOPCNT): New.
1260 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1261 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1262 popcnt. Remove CpuABM from lzcnt.
1263 * i386-init.h: Regenerated.
1264 * i386-tbl.h: Likewise.
1265
1f730c46
JB		 12662020-02-17 Jan Beulich <jbeulich@suse.com>
1267
1268 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1269 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1270 VexW1 instead of open-coding them.
1271 * i386-tbl.h: Re-generate.
1272
c8f8eebc
JB		 12732020-02-17 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-opc.tbl (AddrPrefixOpReg): Define.
1276 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1277 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1278 templates. Drop NoRex64.
1279 * i386-tbl.h: Re-generate.
1280
b9915cbc
JB		 12812020-02-17 Jan Beulich <jbeulich@suse.com>
1282
1283 PR gas/6518
1284 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1285 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1286 into Intel syntax instance (with Unpsecified) and AT&T one
1287 (without).
1288 (vcvtneps2bf16): Likewise, along with folding the two so far
1289 separate ones.
1290 * i386-tbl.h: Re-generate.
1291
ce504911
L		 12922020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1293
1294 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1295 CPU_ANY_SSE4A_FLAGS.
1296
dabec65d
AM		 12972020-02-17 Alan Modra <amodra@gmail.com>
1298
1299 * i386-gen.c (cpu_flag_init): Correct last change.
1300
af5c13b0
L		 13012020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1302
1303 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1304 CPU_ANY_SSE4_FLAGS.
1305
6867aac0
L		 13062020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1307
1308 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1309 (movzx): Likewise.
1310
65fca059
JB		 13112020-02-14 Jan Beulich <jbeulich@suse.com>
1312
1313 PR gas/25438
1314 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1315 destination for Cpu64-only variant.
1316 (movzx): Fold patterns.
1317 * i386-tbl.h: Re-generate.
1318
7deea9aa
JB		 13192020-02-13 Jan Beulich <jbeulich@suse.com>
1320
1321 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1322 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1323 CPU_ANY_SSE4_FLAGS entry.
1324 * i386-init.h: Re-generate.
1325
6c0946d0
JB		 13262020-02-12 Jan Beulich <jbeulich@suse.com>
1327
1328 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1329 with Unspecified, making the present one AT&T syntax only.
1330 * i386-tbl.h: Re-generate.
1331
ddb56fe6
JB		 13322020-02-12 Jan Beulich <jbeulich@suse.com>
1333
1334 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1335 * i386-tbl.h: Re-generate.
1336
5990e377
JB		 13372020-02-12 Jan Beulich <jbeulich@suse.com>
1338
1339 PR gas/24546
1340 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1341 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1342 Amd64 and Intel64 templates.
1343 (call, jmp): Likewise for far indirect variants. Dro
1344 Unspecified.
1345 * i386-tbl.h: Re-generate.
1346
50128d0c
JB		 13472020-02-11 Jan Beulich <jbeulich@suse.com>
1348
1349 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1350 * i386-opc.h (ShortForm): Delete.
1351 (struct i386_opcode_modifier): Remove shortform field.
1352 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1353 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1354 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1355 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1356 Drop ShortForm.
1357 * i386-tbl.h: Re-generate.
1358
1e05b5c4
JB		 13592020-02-11 Jan Beulich <jbeulich@suse.com>
1360
1361 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1362 fucompi): Drop ShortForm from operand-less templates.
1363 * i386-tbl.h: Re-generate.
1364
2f5dd314
AM		 13652020-02-11 Alan Modra <amodra@gmail.com>
1366
1367 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1368 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1369 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1370 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1371 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1372
5aae9ae9
MM		 13732020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1374
1375 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1376 (cde_opcodes): Add VCX* instructions.
1377
4934a27c
MM		 13782020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1379 Matthew Malcomson <matthew.malcomson@arm.com>
1380
1381 * arm-dis.c (struct cdeopcode32): New.
1382 (CDE_OPCODE): New macro.
1383 (cde_opcodes): New disassembly table.
1384 (regnames): New option to table.
1385 (cde_coprocs): New global variable.
1386 (print_insn_cde): New
1387 (print_insn_thumb32): Use print_insn_cde.
1388 (parse_arm_disassembler_options): Parse coprocN args.
1389
4b5aaf5f
L		 13902020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1391
1392 PR gas/25516
1393 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1394 with ISA64.
1395 * i386-opc.h (AMD64): Removed.
1396 (Intel64): Likewose.
1397 (AMD64): New.
1398 (INTEL64): Likewise.
1399 (INTEL64ONLY): Likewise.
1400 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1401 * i386-opc.tbl (Amd64): New.
1402 (Intel64): Likewise.
1403 (Intel64Only): Likewise.
1404 Replace AMD64 with Amd64. Update sysenter/sysenter with
1405 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1406 * i386-tbl.h: Regenerated.
1407
9fc0b501
SB		 14082020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1409
1410 PR 25469
1411 * z80-dis.c: Add support for GBZ80 opcodes.
1412
c5d7be0c
AM		 14132020-02-04 Alan Modra <amodra@gmail.com>
1414
1415 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1416
44e4546f
AM		 14172020-02-03 Alan Modra <amodra@gmail.com>
1418
1419 * m32c-ibld.c: Regenerate.
1420
b2b1453a
AM		 14212020-02-01 Alan Modra <amodra@gmail.com>
1422
1423 * frv-ibld.c: Regenerate.
1424
4102be5c
JB		 14252020-01-31 Jan Beulich <jbeulich@suse.com>
1426
1427 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1428 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1429 (OP_E_memory): Replace xmm_mdq_mode case label by
1430 vex_scalar_w_dq_mode one.
1431 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1432
825bd36c
JB		 14332020-01-31 Jan Beulich <jbeulich@suse.com>
1434
1435 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1436 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1437 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1438 (intel_operand_size): Drop vex_w_dq_mode case label.
1439
c3036ed0
RS		 14402020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1441
1442 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1443 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1444
0c115f84
AM		 14452020-01-30 Alan Modra <amodra@gmail.com>
1446
1447 * m32c-ibld.c: Regenerate.
1448
bd434cc4
JM		 14492020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1450
1451 * bpf-opc.c: Regenerate.
1452
aeab2b26
JB		 14532020-01-30 Jan Beulich <jbeulich@suse.com>
1454
1455 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1456 (dis386): Use them to replace C2/C3 table entries.
1457 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1458 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1459 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1460 * i386-tbl.h: Re-generate.
1461
62b3f548
JB		 14622020-01-30 Jan Beulich <jbeulich@suse.com>
1463
1464 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1465 forms.
1466 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1467 DefaultSize.
1468 * i386-tbl.h: Re-generate.
1469
1bd8ae10
AM		 14702020-01-30 Alan Modra <amodra@gmail.com>
1471
1472 * tic4x-dis.c (tic4x_dp): Make unsigned.
1473
bc31405e
L		 14742020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1475 Jan Beulich <jbeulich@suse.com>
1476
1477 PR binutils/25445
1478 * i386-dis.c (MOVSXD_Fixup): New function.
1479 (movsxd_mode): New enum.
1480 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1481 (intel_operand_size): Handle movsxd_mode.
1482 (OP_E_register): Likewise.
1483 (OP_G): Likewise.
1484 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1485 register on movsxd. Add movsxd with 16-bit destination register
1486 for AMD64 and Intel64 ISAs.
1487 * i386-tbl.h: Regenerated.
1488
7568c93b
TC		 14892020-01-27 Tamar Christina <tamar.christina@arm.com>
1490
1491 PR 25403
1492 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1493 * aarch64-asm-2.c: Regenerate
1494 * aarch64-dis-2.c: Likewise.
1495 * aarch64-opc-2.c: Likewise.
1496
c006a730
JB		 14972020-01-21 Jan Beulich <jbeulich@suse.com>
1498
1499 * i386-opc.tbl (sysret): Drop DefaultSize.
1500 * i386-tbl.h: Re-generate.
1501
c906a69a
JB		 15022020-01-21 Jan Beulich <jbeulich@suse.com>
1503
1504 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1505 Dword.
1506 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1507 * i386-tbl.h: Re-generate.
1508
26916852
NC		 15092020-01-20 Nick Clifton <nickc@redhat.com>
1510
1511 * po/de.po: Updated German translation.
1512 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1513 * po/uk.po: Updated Ukranian translation.
1514
4d6cbb64
AM		 15152020-01-20 Alan Modra <amodra@gmail.com>
1516
1517 * hppa-dis.c (fput_const): Remove useless cast.
1518
2bddb71a
AM		 15192020-01-20 Alan Modra <amodra@gmail.com>
1520
1521 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1522
1b1bb2c6
NC		 15232020-01-18 Nick Clifton <nickc@redhat.com>
1524
1525 * configure: Regenerate.
1526 * po/opcodes.pot: Regenerate.
1527
ae774686
NC		 15282020-01-18 Nick Clifton <nickc@redhat.com>
1529
1530 Binutils 2.34 branch created.
1531
07f1f3aa
CB		 15322020-01-17 Christian Biesinger <cbiesinger@google.com>
1533
1534 * opintl.h: Fix spelling error (seperate).
1535
42e04b36
L		 15362020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1537
1538 * i386-opc.tbl: Add {vex} pseudo prefix.
1539 * i386-tbl.h: Regenerated.
1540
2da2eaf4
AV		 15412020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1542
1543 PR 25376
1544 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1545 (neon_opcodes): Likewise.
1546 (select_arm_features): Make sure we enable MVE bits when selecting
1547 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1548 any architecture.
1549
d0849eed
JB		 15502020-01-16 Jan Beulich <jbeulich@suse.com>
1551
1552 * i386-opc.tbl: Drop stale comment from XOP section.
1553
9cf70a44
JB		 15542020-01-16 Jan Beulich <jbeulich@suse.com>
1555
1556 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1557 (extractps): Add VexWIG to SSE2AVX forms.
1558 * i386-tbl.h: Re-generate.
1559
4814632e
JB		 15602020-01-16 Jan Beulich <jbeulich@suse.com>
1561
1562 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1563 Size64 from and use VexW1 on SSE2AVX forms.
1564 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1565 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1566 * i386-tbl.h: Re-generate.
1567
aad09917
AM		 15682020-01-15 Alan Modra <amodra@gmail.com>
1569
1570 * tic4x-dis.c (tic4x_version): Make unsigned long.
1571 (optab, optab_special, registernames): New file scope vars.
1572 (tic4x_print_register): Set up registernames rather than
1573 malloc'd registertable.
1574 (tic4x_disassemble): Delete optable and optable_special. Use
1575 optab and optab_special instead. Throw away old optab,
1576 optab_special and registernames when info->mach changes.
1577
7a6bf3be
SB		 15782020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1579
1580 PR 25377
1581 * z80-dis.c (suffix): Use .db instruction to generate double
1582 prefix.
1583
ca1eaac0
AM		 15842020-01-14 Alan Modra <amodra@gmail.com>
1585
1586 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1587 values to unsigned before shifting.
1588
1d67fe3b
TT		 15892020-01-13 Thomas Troeger <tstroege@gmx.de>
1590
1591 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1592 flow instructions.
1593 (print_insn_thumb16, print_insn_thumb32): Likewise.
1594 (print_insn): Initialize the insn info.
1595 * i386-dis.c (print_insn): Initialize the insn info fields, and
1596 detect jumps.
1597
5e4f7e05
CZ		 15982012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1599
1600 * arc-opc.c (C_NE): Make it required.
1601
b9fe6b8a
CZ		 16022012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1603
1604 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1605 reserved register name.
1606
90dee485
AM		 16072020-01-13 Alan Modra <amodra@gmail.com>
1608
1609 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1610 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1611
febda64f
AM		 16122020-01-13 Alan Modra <amodra@gmail.com>
1613
1614 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1615 result of wasm_read_leb128 in a uint64_t and check that bits
1616 are not lost when copying to other locals. Use uint32_t for
1617 most locals. Use PRId64 when printing int64_t.
1618
df08b588
AM		 16192020-01-13 Alan Modra <amodra@gmail.com>
1620
1621 * score-dis.c: Formatting.
1622 * score7-dis.c: Formatting.
1623
b2c759ce
AM		 16242020-01-13 Alan Modra <amodra@gmail.com>
1625
1626 * score-dis.c (print_insn_score48): Use unsigned variables for
1627 unsigned values. Don't left shift negative values.
1628 (print_insn_score32): Likewise.
1629 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1630
5496abe1
AM		 16312020-01-13 Alan Modra <amodra@gmail.com>
1632
1633 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1634
202e762b
AM		 16352020-01-13 Alan Modra <amodra@gmail.com>
1636
1637 * fr30-ibld.c: Regenerate.
1638
7ef412cf
AM		 16392020-01-13 Alan Modra <amodra@gmail.com>
1640
1641 * xgate-dis.c (print_insn): Don't left shift signed value.
1642 (ripBits): Formatting, use 1u.
1643
7f578b95
AM		 16442020-01-10 Alan Modra <amodra@gmail.com>
1645
1646 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1647 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1648
441af85b
AM		 16492020-01-10 Alan Modra <amodra@gmail.com>
1650
1651 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1652 and XRREG value earlier to avoid a shift with negative exponent.
1653 * m10200-dis.c (disassemble): Similarly.
1654
bce58db4
NC		 16552020-01-09 Nick Clifton <nickc@redhat.com>
1656
1657 PR 25224
1658 * z80-dis.c (ld_ii_ii): Use correct cast.
1659
40c75bc8
SB		 16602020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1661
1662 PR 25224
1663 * z80-dis.c (ld_ii_ii): Use character constant when checking
1664 opcode byte value.
1665
d835a58b
JB		 16662020-01-09 Jan Beulich <jbeulich@suse.com>
1667
1668 * i386-dis.c (SEP_Fixup): New.
1669 (SEP): Define.
1670 (dis386_twobyte): Use it for sysenter/sysexit.
1671 (enum x86_64_isa): Change amd64 enumerator to value 1.
1672 (OP_J): Compare isa64 against intel64 instead of amd64.
1673 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1674 forms.
1675 * i386-tbl.h: Re-generate.
1676
030a2e78
AM		 16772020-01-08 Alan Modra <amodra@gmail.com>
1678
1679 * z8k-dis.c: Include libiberty.h
1680 (instr_data_s): Make max_fetched unsigned.
1681 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1682 Don't exceed byte_info bounds.
1683 (output_instr): Make num_bytes unsigned.
1684 (unpack_instr): Likewise for nibl_count and loop.
1685 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1686 idx unsigned.
1687 * z8k-opc.h: Regenerate.
1688
bb82aefe
SV		 16892020-01-07 Shahab Vahedi <shahab@synopsys.com>
1690
1691 * arc-tbl.h (llock): Use 'LLOCK' as class.
1692 (llockd): Likewise.
1693 (scond): Use 'SCOND' as class.
1694 (scondd): Likewise.
1695 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1696 (scondd): Likewise.
1697
cc6aa1a6
AM		 16982020-01-06 Alan Modra <amodra@gmail.com>
1699
1700 * m32c-ibld.c: Regenerate.
1701
660e62b1
AM		 17022020-01-06 Alan Modra <amodra@gmail.com>
1703
1704 PR 25344
1705 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1706 Peek at next byte to prevent recursion on repeated prefix bytes.
1707 Ensure uninitialised "mybuf" is not accessed.
1708 (print_insn_z80): Don't zero n_fetch and n_used here,..
1709 (print_insn_z80_buf): ..do it here instead.
1710
c9ae58fe
AM		 17112020-01-04 Alan Modra <amodra@gmail.com>
1712
1713 * m32r-ibld.c: Regenerate.
1714
5f57d4ec
AM		 17152020-01-04 Alan Modra <amodra@gmail.com>
1716
1717 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1718
2c5c1196
AM		 17192020-01-04 Alan Modra <amodra@gmail.com>
1720
1721 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1722
2e98c6c5
AM		 17232020-01-04 Alan Modra <amodra@gmail.com>
1724
1725 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1726
567dfba2
JB		 17272020-01-03 Jan Beulich <jbeulich@suse.com>
1728
5437a02a
JB		 1729 * aarch64-tbl.h (aarch64_opcode_table): Use
1730 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1731
17322020-01-03 Jan Beulich <jbeulich@suse.com>
1733
1734 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1735 forms of SUDOT and USDOT.
1736
8c45011a
JB		 17372020-01-03 Jan Beulich <jbeulich@suse.com>
1738
5437a02a 1739 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1740 uzip{1,2}.
1741 * opcodes/aarch64-dis-2.c: Re-generate.
1742
f4950f76
JB		 17432020-01-03 Jan Beulich <jbeulich@suse.com>
1744
5437a02a 1745 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1746 FMMLA encoding.
1747 * opcodes/aarch64-dis-2.c: Re-generate.
1748
6655dba2
SB		 17492020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1750
1751 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1752
b14ce8bf
AM		 17532020-01-01 Alan Modra <amodra@gmail.com>
1754
1755 Update year range in copyright notice of all files.
1756
0b114740 1757For older changes see ChangeLog-2019
3499769a 1758\f
0b114740 1759Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1760
1761Copying and distribution of this file, with or without modification,
1762are permitted in any medium without royalty provided the copyright
1763notice and this notice are preserved.
1764
1765Local Variables:
1766mode: change-log
1767left-margin: 8
1768fill-column: 74
1769version-control: never
1770End:
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