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* config/tc-mips.c (mips_after_parse_args): New function.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
ba46ddd0
CD		 12002-06-04 Chris Demetriou <cgd@broadcom.com>
2 Ed Satterthwaite <ehs@broadcom.com>
3
4 * cp1.c (Infinity): Remove.
5 * sim-main.h (Infinity): Likewise.
6
7 * cp1.c (fp_unary, fp_binary): New functions.
8 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
9 (fp_sqrt): New functions, implemented in terms of the above.
10 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
11 (Recip, SquareRoot): Remove (replaced by functions above).
12 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
13 (fp_recip, fp_sqrt): New prototypes.
14 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
15 (Recip, SquareRoot): Replace prototypes with #defines which
16 invoke the functions above.
17
18d8a52d
CD		 182002-06-03 Chris Demetriou <cgd@broadcom.com>
19
20 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
21 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
22 file, remove PARAMS from prototypes.
23 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
24 simulator state arguments.
25 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
26 pass simulator state arguments.
27 * cp1.c (SD): Redefine as CPU_STATE(cpu).
28 (store_fpr, convert): Remove 'sd' argument.
29 (value_fpr): Likewise. Convert to use 'SD' instead.
30
0f154cbd
CD		 312002-06-03 Chris Demetriou <cgd@broadcom.com>
32
33 * cp1.c (Min, Max): Remove #if 0'd functions.
34 * sim-main.h (Min, Max): Remove.
35
e80fc152
CD		 362002-06-03 Chris Demetriou <cgd@broadcom.com>
37
38 * cp1.c: fix formatting of switch case and default labels.
39 * interp.c: Likewise.
40 * sim-main.c: Likewise.
41
bad673a9
CD		 422002-06-03 Chris Demetriou <cgd@broadcom.com>
43
44 * cp1.c: Clean up comments which describe FP formats.
45 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
46
7cbea089
CD		 472002-06-03 Chris Demetriou <cgd@broadcom.com>
48 Ed Satterthwaite <ehs@broadcom.com>
49
50 * configure.in (mipsisa64sb1*-*-*): New target for supporting
51 Broadcom SiByte SB-1 processor configurations.
52 * configure: Regenerate.
53 * sb1.igen: New file.
54 * mips.igen: Include sb1.igen.
55 (sb1): New model.
56 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
57 * mdmx.igen: Add "sb1" model to all appropriate functions and
58 instructions.
59 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
60 (ob_func, ob_acc): Reference the above.
61 (qh_acc): Adjust to keep the same size as ob_acc.
62 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
63 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
64
909daa82
CD		 652002-06-03 Chris Demetriou <cgd@broadcom.com>
66
67 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
68
f4f1b9f1
CD		 692002-06-02 Chris Demetriou <cgd@broadcom.com>
70 Ed Satterthwaite <ehs@broadcom.com>
71
72 * mips.igen (mdmx): New (pseudo-)model.
73 * mdmx.c, mdmx.igen: New files.
74 * Makefile.in (SIM_OBJS): Add mdmx.o.
75 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
76 New typedefs.
77 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
78 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
79 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
80 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
81 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
82 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
83 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
84 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
85 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
86 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
87 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
88 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
89 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
90 (qh_fmtsel): New macros.
91 (_sim_cpu): New member "acc".
92 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
93 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
94
5accf1ff
CD		 952002-05-01 Chris Demetriou <cgd@broadcom.com>
96
97 * interp.c: Use 'deprecated' rather than 'depreciated.'
98 * sim-main.h: Likewise.
99
402586aa
CD		 1002002-05-01 Chris Demetriou <cgd@broadcom.com>
101
102 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
103 which wouldn't compile anyway.
104 * sim-main.h (unpredictable_action): New function prototype.
105 (Unpredictable): Define to call igen function unpredictable().
106 (NotWordValue): New macro to call igen function not_word_value().
107 (UndefinedResult): Remove.
108 * interp.c (undefined_result): Remove.
109 (unpredictable_action): New function.
110 * mips.igen (not_word_value, unpredictable): New functions.
111 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
112 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
113 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
114 NotWordValue() to check for unpredictable inputs, then
115 Unpredictable() to handle them.
116
c9b9995a
CD		 1172002-02-24 Chris Demetriou <cgd@broadcom.com>
118
119 * mips.igen: Fix formatting of calls to Unpredictable().
120
e1015982
AC		 1212002-04-20 Andrew Cagney <ac131313@redhat.com>
122
123 * interp.c (sim_open): Revert previous change.
124
b882a66b
AO		 1252002-04-18 Alexandre Oliva <aoliva@redhat.com>
126
127 * interp.c (sim_open): Disable chunk of code that wrote code in
128 vector table entries.
129
c429b7dd
CD		 1302002-03-19 Chris Demetriou <cgd@broadcom.com>
131
132 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
133 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
134 unused definitions.
135
37d146fa
CD		 1362002-03-19 Chris Demetriou <cgd@broadcom.com>
137
138 * cp1.c: Fix many formatting issues.
139
07892c0b
CD		 1402002-03-19 Chris G. Demetriou <cgd@broadcom.com>
141
142 * cp1.c (fpu_format_name): New function to replace...
143 (DOFMT): This. Delete, and update all callers.
144 (fpu_rounding_mode_name): New function to replace...
145 (RMMODE): This. Delete, and update all callers.
146
487f79b7
CD		 1472002-03-19 Chris G. Demetriou <cgd@broadcom.com>
148
149 * interp.c: Move FPU support routines from here to...
150 * cp1.c: Here. New file.
151 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
152 (cp1.o): New target.
153
1e799e28
CD		 1542002-03-12 Chris Demetriou <cgd@broadcom.com>
155
156 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
157 * mips.igen (mips32, mips64): New models, add to all instructions
158 and functions as appropriate.
159 (loadstore_ea, check_u64): New variant for model mips64.
160 (check_fmt_p): New variant for models mipsV and mips64, remove
161 mipsV model marking fro other variant.
162 (SLL) Rename to...
163 (SLLa) this.
164 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
165 for mips32 and mips64.
166 (DCLO, DCLZ): New instructions for mips64.
167
82f728db
CD		 1682002-03-07 Chris Demetriou <cgd@broadcom.com>
169
170 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
171 immediate or code as a hex value with the "%#lx" format.
172 (ANDI): Likewise, and fix printed instruction name.
173
b96e7ef1
CD		 1742002-03-05 Chris Demetriou <cgd@broadcom.com>
175
176 * sim-main.h (UndefinedResult, Unpredictable): New macros
177 which currently do nothing.
178
d35d4f70
CD		 1792002-03-05 Chris Demetriou <cgd@broadcom.com>
180
181 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
182 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
183 (status_CU3): New definitions.
184
185 * sim-main.h (ExceptionCause): Add new values for MIPS32
186 and MIPS64: MDMX, MCheck, CacheErr. Update comments
187 for DebugBreakPoint and NMIReset to note their status in
188 MIPS32 and MIPS64.
189 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
190 (SignalExceptionCacheErr): New exception macros.
191
3ad6f714
CD		 1922002-03-05 Chris Demetriou <cgd@broadcom.com>
193
194 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
195 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
196 is always enabled.
197 (SignalExceptionCoProcessorUnusable): Take as argument the
198 unusable coprocessor number.
199
86b77b47
CD		 2002002-03-05 Chris Demetriou <cgd@broadcom.com>
201
202 * mips.igen: Fix formatting of all SignalException calls.
203
97a88e93 2042002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 205
206 * sim-main.h (SIGNEXTEND): Remove.
207
97a88e93 2082002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 209
210 * mips.igen: Remove gencode comment from top of file, fix
211 spelling in another comment.
212
97a88e93 2132002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 214
215 * mips.igen (check_fmt, check_fmt_p): New functions to check
216 whether specific floating point formats are usable.
217 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
218 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
219 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
220 Use the new functions.
221 (do_c_cond_fmt): Remove format checks...
222 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
223
97a88e93 2242002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 225
226 * mips.igen: Fix formatting of check_fpu calls.
227
41774c9d
CD		 2282002-03-03 Chris Demetriou <cgd@broadcom.com>
229
230 * mips.igen (FLOOR.L.fmt): Store correct destination register.
231
4a0bd876
CD		 2322002-03-03 Chris Demetriou <cgd@broadcom.com>
233
234 * mips.igen: Remove whitespace at end of lines.
235
09297648
CD		 2362002-03-02 Chris Demetriou <cgd@broadcom.com>
237
238 * mips.igen (loadstore_ea): New function to do effective
239 address calculations.
240 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
241 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
242 CACHE): Use loadstore_ea to do effective address computations.
243
043b7057
CD		 2442002-03-02 Chris Demetriou <cgd@broadcom.com>
245
246 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
247 * mips.igen (LL, CxC1, MxC1): Likewise.
248
c1e8ada4
CD		 2492002-03-02 Chris Demetriou <cgd@broadcom.com>
250
251 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
252 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
253 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
254 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
255 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
256 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
257 Don't split opcode fields by hand, use the opcode field values
258 provided by igen.
259
3e1dca16
CD		 2602002-03-01 Chris Demetriou <cgd@broadcom.com>
261
262 * mips.igen (do_divu): Fix spacing.
263
264 * mips.igen (do_dsllv): Move to be right before DSLLV,
265 to match the rest of the do_<shift> functions.
266
fff8d27d
CD		 2672002-03-01 Chris Demetriou <cgd@broadcom.com>
268
269 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
270 DSRL32, do_dsrlv): Trace inputs and results.
271
0d3e762b
CD		 2722002-03-01 Chris Demetriou <cgd@broadcom.com>
273
274 * mips.igen (CACHE): Provide instruction-printing string.
275
276 * interp.c (signal_exception): Comment tokens after #endif.
277
eb5fcf93
CD		 2782002-02-28 Chris Demetriou <cgd@broadcom.com>
279
280 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
281 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
282 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
283 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
284 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
285 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
286 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
287 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
288
bb22bd7d
CD		 2892002-02-28 Chris Demetriou <cgd@broadcom.com>
290
291 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
292 instruction-printing string.
293 (LWU): Use '64' as the filter flag.
294
91a177cf
CD		 2952002-02-28 Chris Demetriou <cgd@broadcom.com>
296
297 * mips.igen (SDXC1): Fix instruction-printing string.
298
387f484a
CD		 2992002-02-28 Chris Demetriou <cgd@broadcom.com>
300
301 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
302 filter flags "32,f".
303
3d81f391
CD		 3042002-02-27 Chris Demetriou <cgd@broadcom.com>
305
306 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
307 as the filter flag.
308
af5107af
CD		 3092002-02-27 Chris Demetriou <cgd@broadcom.com>
310
311 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
312 add a comma) so that it more closely match the MIPS ISA
313 documentation opcode partitioning.
314 (PREF): Put useful names on opcode fields, and include
315 instruction-printing string.
316
ca971540
CD		 3172002-02-27 Chris Demetriou <cgd@broadcom.com>
318
319 * mips.igen (check_u64): New function which in the future will
320 check whether 64-bit instructions are usable and signal an
321 exception if not. Currently a no-op.
322 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
323 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
324 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
325 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
326
327 * mips.igen (check_fpu): New function which in the future will
328 check whether FPU instructions are usable and signal an exception
329 if not. Currently a no-op.
330 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
331 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
332 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
333 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
334 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
335 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
336 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
337 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
338
1c47a468
CD		 3392002-02-27 Chris Demetriou <cgd@broadcom.com>
340
341 * mips.igen (do_load_left, do_load_right): Move to be immediately
342 following do_load.
343 (do_store_left, do_store_right): Move to be immediately following
344 do_store.
345
603a98e7
CD		 3462002-02-27 Chris Demetriou <cgd@broadcom.com>
347
348 * mips.igen (mipsV): New model name. Also, add it to
349 all instructions and functions where it is appropriate.
350
c5d00cc7
CD		 3512002-02-18 Chris Demetriou <cgd@broadcom.com>
352
353 * mips.igen: For all functions and instructions, list model
354 names that support that instruction one per line.
355
074e9cb8
CD		 3562002-02-11 Chris Demetriou <cgd@broadcom.com>
357
358 * mips.igen: Add some additional comments about supported
359 models, and about which instructions go where.
360 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
361 order as is used in the rest of the file.
362
9805e229
CD		 3632002-02-11 Chris Demetriou <cgd@broadcom.com>
364
365 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
366 indicating that ALU32_END or ALU64_END are there to check
367 for overflow.
368 (DADD): Likewise, but also remove previous comment about
369 overflow checking.
370
f701dad2
CD		 3712002-02-10 Chris Demetriou <cgd@broadcom.com>
372
373 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
374 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
375 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
376 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
377 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
378 fields (i.e., add and move commas) so that they more closely
379 match the MIPS ISA documentation opcode partitioning.
380
3812002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 382
383 * mips.igen (ADDI): Print immediate value.
384 (BREAK): Print code.
385 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
386 (SLL): Print "nop" specially, and don't run the code
387 that does the shift for the "nop" case.
388
9e52972e
FF		 3892001-11-17 Fred Fish <fnf@redhat.com>
390
391 * sim-main.h (float_operation): Move enum declaration outside
392 of _sim_cpu struct declaration.
393
c0efbca4
JB		 3942001-04-12 Jim Blandy <jimb@redhat.com>
395
396 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
397 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
398 set of the FCSR.
399 * sim-main.h (COCIDX): Remove definition; this isn't supported by
400 PENDING_FILL, and you can get the intended effect gracefully by
401 calling PENDING_SCHED directly.
402
fb891446
BE		 4032001-02-23 Ben Elliston <bje@redhat.com>
404
405 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
406 already defined elsewhere.
407
8030f857
BE		 4082001-02-19 Ben Elliston <bje@redhat.com>
409
410 * sim-main.h (sim_monitor): Return an int.
411 * interp.c (sim_monitor): Add return values.
412 (signal_exception): Handle error conditions from sim_monitor.
413
56b48a7a
CD		 4142001-02-08 Ben Elliston <bje@redhat.com>
415
416 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
417 (store_memory): Likewise, pass cia to sim_core_write*.
418
d3ee60d9
FCE		 4192000-10-19 Frank Ch. Eigler <fche@redhat.com>
420
421 On advice from Chris G. Demetriou <cgd@sibyte.com>:
422 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
423
071da002
AC		 424Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
425
426 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
427 * Makefile.in: Don't delete *.igen when cleaning directory.
428
a28c02cd
AC		 429Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
430
431 * m16.igen (break): Call SignalException not sim_engine_halt.
432
80ee11fa
AC		 433Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
434
435 From Jason Eckhardt:
436 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
437
673388c0
AC		 438Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
439
440 * mips.igen (MxC1, DMxC1): Fix printf formatting.
441
4c0deff4
NC		 4422000-05-24 Michael Hayes <mhayes@cygnus.com>
443
444 * mips.igen (do_dmultx): Fix typo.
445
eb2d80b4
AC		 446Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
447
448 * configure: Regenerated to track ../common/aclocal.m4 changes.
449
dd37a34b
AC		 450Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
451
452 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
453
4c0deff4
NC		 4542000-04-12 Frank Ch. Eigler <fche@redhat.com>
455
456 * sim-main.h (GPR_CLEAR): Define macro.
457
e30db738
AC		 458Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
459
460 * interp.c (decode_coproc): Output long using %lx and not %s.
461
cb7450ea
FCE		 4622000-03-21 Frank Ch. Eigler <fche@redhat.com>
463
464 * interp.c (sim_open): Sort & extend dummy memory regions for
465 --board=jmr3904 for eCos.
466
a3027dd7
FCE		 4672000-03-02 Frank Ch. Eigler <fche@redhat.com>
468
469 * configure: Regenerated.
470
471Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
472
473 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
474 calls, conditional on the simulator being in verbose mode.
475
dfcd3bfb
JM		 476Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
477
478 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
479 cache don't get ReservedInstruction traps.
480
c2d11a7d
JM		 4811999-11-29 Mark Salter <msalter@cygnus.com>
482
483 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
484 to clear status bits in sdisr register. This is how the hardware works.
485
486 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
487 being used by cygmon.
488
4ce44c66
JM		 4891999-11-11 Andrew Haley <aph@cygnus.com>
490
491 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
492 instructions.
493
cff3e48b
JM		 494Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
495
496 * mips.igen (MULT): Correct previous mis-applied patch.
497
d4f3574e
SS		 498Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
499
500 * mips.igen (delayslot32): Handle sequence like
501 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
502 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
503 (MULT): Actually pass the third register...
504
5051999-09-03 Mark Salter <msalter@cygnus.com>
506
507 * interp.c (sim_open): Added more memory aliases for additional
508 hardware being touched by cygmon on jmr3904 board.
509
510Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
511
512 * configure: Regenerated to track ../common/aclocal.m4 changes.
513
a0b3c4fd
JM		 514Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
515
516 * interp.c (sim_store_register): Handle case where client - GDB -
517 specifies that a 4 byte register is 8 bytes in size.
518 (sim_fetch_register): Ditto.
519
adf40b2e
JM		 5201999-07-14 Frank Ch. Eigler <fche@cygnus.com>
521
522 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
523 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
524 (idt_monitor_base): Base address for IDT monitor traps.
525 (pmon_monitor_base): Ditto for PMON.
526 (lsipmon_monitor_base): Ditto for LSI PMON.
527 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
528 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
529 (sim_firmware_command): New function.
530 (mips_option_handler): Call it for OPTION_FIRMWARE.
531 (sim_open): Allocate memory for idt_monitor region. If "--board"
532 option was given, add no monitor by default. Add BREAK hooks only if
533 monitors are also there.
534
43e526b9
JM		 535Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
536
537 * interp.c (sim_monitor): Flush output before reading input.
538
539Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
540
541 * tconfig.in (SIM_HANDLES_LMA): Always define.
542
543Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
544
545 From Mark Salter <msalter@cygnus.com>:
546 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
547 (sim_open): Add setup for BSP board.
548
9846de1b
JM		 549Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
550
551 * mips.igen (MULT, MULTU): Add syntax for two operand version.
552 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
553 them as unimplemented.
554
cd0fc7c3
SS		 5551999-05-08 Felix Lee <flee@cygnus.com>
556
557 * configure: Regenerated to track ../common/aclocal.m4 changes.
558
7a292a7a
SS		 5591999-04-21 Frank Ch. Eigler <fche@cygnus.com>
560
561 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
562
563Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
564
565 * configure.in: Any mips64vr5*-*-* target should have
566 -DTARGET_ENABLE_FR=1.
567 (default_endian): Any mips64vr*el-*-* target should default to
568 LITTLE_ENDIAN.
569 * configure: Re-generate.
570
5711999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
572
573 * mips.igen (ldl): Extend from _16_, not 32.
574
575Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
576
577 * interp.c (sim_store_register): Force registers written to by GDB
578 into an un-interpreted state.
579
c906108c
SS		 5801999-02-05 Frank Ch. Eigler <fche@cygnus.com>
581
582 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
583 CPU, start periodic background I/O polls.
584 (tx3904sio_poll): New function: periodic I/O poller.
585
5861998-12-30 Frank Ch. Eigler <fche@cygnus.com>
587
588 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
589
590Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
591
592 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
593 case statement.
594
5951998-12-29 Frank Ch. Eigler <fche@cygnus.com>
596
597 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
598 (load_word): Call SIM_CORE_SIGNAL hook on error.
599 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
600 starting. For exception dispatching, pass PC instead of NULL_CIA.
601 (decode_coproc): Use COP0_BADVADDR to store faulting address.
602 * sim-main.h (COP0_BADVADDR): Define.
603 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
604 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
605 (_sim_cpu): Add exc_* fields to store register value snapshots.
606 * mips.igen (*): Replace memory-related SignalException* calls
607 with references to SIM_CORE_SIGNAL hook.
608
609 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
610 fix.
611 * sim-main.c (*): Minor warning cleanups.
612
6131998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
614
615 * m16.igen (DADDIU5): Correct type-o.
616
617Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
618
619 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
620 variables.
621
622Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
623
624 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
625 to include path.
626 (interp.o): Add dependency on itable.h
627 (oengine.c, gencode): Delete remaining references.
628 (BUILT_SRC_FROM_GEN): Clean up.
629
6301998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
631
632 * vr4run.c: New.
633 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
634 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
635 tmp-run-hack) : New.
636 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
637 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
638 Drop the "64" qualifier to get the HACK generator working.
639 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
640 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
641 qualifier to get the hack generator working.
642 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
643 (DSLL): Use do_dsll.
644 (DSLLV): Use do_dsllv.
645 (DSRA): Use do_dsra.
646 (DSRL): Use do_dsrl.
647 (DSRLV): Use do_dsrlv.
648 (BC1): Move *vr4100 to get the HACK generator working.
649 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
650 get the HACK generator working.
651 (MACC) Rename to get the HACK generator working.
652 (DMACC,MACCS,DMACCS): Add the 64.
653
6541998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
655
656 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
657 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
658
6591998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
660
661 * mips/interp.c (DEBUG): Cleanups.
662
6631998-12-10 Frank Ch. Eigler <fche@cygnus.com>
664
665 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
666 (tx3904sio_tickle): fflush after a stdout character output.
667
6681998-12-03 Frank Ch. Eigler <fche@cygnus.com>
669
670 * interp.c (sim_close): Uninstall modules.
671
672Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
673
674 * sim-main.h, interp.c (sim_monitor): Change to global
675 function.
676
677Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
678
679 * configure.in (vr4100): Only include vr4100 instructions in
680 simulator.
681 * configure: Re-generate.
682 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
683
684Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
685
686 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
687 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
688 true alternative.
689
690 * configure.in (sim_default_gen, sim_use_gen): Replace with
691 sim_gen.
692 (--enable-sim-igen): Delete config option. Always using IGEN.
693 * configure: Re-generate.
694
695 * Makefile.in (gencode): Kill, kill, kill.
696 * gencode.c: Ditto.
697
698Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
699
700 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
701 bit mips16 igen simulator.
702 * configure: Re-generate.
703
704 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
705 as part of vr4100 ISA.
706 * vr.igen: Mark all instructions as 64 bit only.
707
708Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
709
710 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
711 Pacify GCC.
712
713Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
714
715 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
716 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
717 * configure: Re-generate.
718
719 * m16.igen (BREAK): Define breakpoint instruction.
720 (JALX32): Mark instruction as mips16 and not r3900.
721 * mips.igen (C.cond.fmt): Fix typo in instruction format.
722
723 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
724
725Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
726
727 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
728 insn as a debug breakpoint.
729
730 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
731 pending.slot_size.
732 (PENDING_SCHED): Clean up trace statement.
733 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
734 (PENDING_FILL): Delay write by only one cycle.
735 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
736
737 * sim-main.c (pending_tick): Clean up trace statements. Add trace
738 of pending writes.
739 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
740 32 & 64.
741 (pending_tick): Move incrementing of index to FOR statement.
742 (pending_tick): Only update PENDING_OUT after a write has occured.
743
744 * configure.in: Add explicit mips-lsi-* target. Use gencode to
745 build simulator.
746 * configure: Re-generate.
747
748 * interp.c (sim_engine_run OLD): Delete explicit call to
749 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
750
751Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
752
753 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
754 interrupt level number to match changed SignalExceptionInterrupt
755 macro.
756
757Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
758
759 * interp.c: #include "itable.h" if WITH_IGEN.
760 (get_insn_name): New function.
761 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
762 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
763
764Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
765
766 * configure: Rebuilt to inhale new common/aclocal.m4.
767
768Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
769
770 * dv-tx3904sio.c: Include sim-assert.h.
771
772Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
773
774 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
775 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
776 Reorganize target-specific sim-hardware checks.
777 * configure: rebuilt.
778 * interp.c (sim_open): For tx39 target boards, set
779 OPERATING_ENVIRONMENT, add tx3904sio devices.
780 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
781 ROM executables. Install dv-sockser into sim-modules list.
782
783 * dv-tx3904irc.c: Compiler warning clean-up.
784 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
785 frequent hw-trace messages.
786
787Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
788
789 * vr.igen (MulAcc): Identify as a vr4100 specific function.
790
791Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
792
793 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
794
795 * vr.igen: New file.
796 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
797 * mips.igen: Define vr4100 model. Include vr.igen.
798Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
799
800 * mips.igen (check_mf_hilo): Correct check.
801
802Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
803
804 * sim-main.h (interrupt_event): Add prototype.
805
806 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
807 register_ptr, register_value.
808 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
809
810 * sim-main.h (tracefh): Make extern.
811
812Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
813
814 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
815 Reduce unnecessarily high timer event frequency.
816 * dv-tx3904cpu.c: Ditto for interrupt event.
817
818Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
819
820 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
821 to allay warnings.
822 (interrupt_event): Made non-static.
823
824 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
825 interchange of configuration values for external vs. internal
826 clock dividers.
827
828Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
829
830 * mips.igen (BREAK): Moved code to here for
831 simulator-reserved break instructions.
832 * gencode.c (build_instruction): Ditto.
833 * interp.c (signal_exception): Code moved from here. Non-
834 reserved instructions now use exception vector, rather
835 than halting sim.
836 * sim-main.h: Moved magic constants to here.
837
838Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
839
840 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
841 register upon non-zero interrupt event level, clear upon zero
842 event value.
843 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
844 by passing zero event value.
845 (*_io_{read,write}_buffer): Endianness fixes.
846 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
847 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
848
849 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
850 serial I/O and timer module at base address 0xFFFF0000.
851
852Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
853
854 * mips.igen (SWC1) : Correct the handling of ReverseEndian
855 and BigEndianCPU.
856
857Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
858
859 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
860 parts.
861 * configure: Update.
862
863Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
864
865 * dv-tx3904tmr.c: New file - implements tx3904 timer.
866 * dv-tx3904{irc,cpu}.c: Mild reformatting.
867 * configure.in: Include tx3904tmr in hw_device list.
868 * configure: Rebuilt.
869 * interp.c (sim_open): Instantiate three timer instances.
870 Fix address typo of tx3904irc instance.
871
872Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
873
874 * interp.c (signal_exception): SystemCall exception now uses
875 the exception vector.
876
877Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
878
879 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
880 to allay warnings.
881
882Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
883
884 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
885
886Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
887
888 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
889
890 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
891 sim-main.h. Declare a struct hw_descriptor instead of struct
892 hw_device_descriptor.
893
894Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
895
896 * mips.igen (do_store_left, do_load_left): Compute nr of left and
897 right bits and then re-align left hand bytes to correct byte
898 lanes. Fix incorrect computation in do_store_left when loading
899 bytes from second word.
900
901Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
902
903 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
904 * interp.c (sim_open): Only create a device tree when HW is
905 enabled.
906
907 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
908 * interp.c (signal_exception): Ditto.
909
910Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
911
912 * gencode.c: Mark BEGEZALL as LIKELY.
913
914Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
915
916 * sim-main.h (ALU32_END): Sign extend 32 bit results.
917 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
918
919Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
920
921 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
922 modules. Recognize TX39 target with "mips*tx39" pattern.
923 * configure: Rebuilt.
924 * sim-main.h (*): Added many macros defining bits in
925 TX39 control registers.
926 (SignalInterrupt): Send actual PC instead of NULL.
927 (SignalNMIReset): New exception type.
928 * interp.c (board): New variable for future use to identify
929 a particular board being simulated.
930 (mips_option_handler,mips_options): Added "--board" option.
931 (interrupt_event): Send actual PC.
932 (sim_open): Make memory layout conditional on board setting.
933 (signal_exception): Initial implementation of hardware interrupt
934 handling. Accept another break instruction variant for simulator
935 exit.
936 (decode_coproc): Implement RFE instruction for TX39.
937 (mips.igen): Decode RFE instruction as such.
938 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
939 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
940 bbegin to implement memory map.
941 * dv-tx3904cpu.c: New file.
942 * dv-tx3904irc.c: New file.
943
944Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
945
946 * mips.igen (check_mt_hilo): Create a separate r3900 version.
947
948Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
949
950 * tx.igen (madd,maddu): Replace calls to check_op_hilo
951 with calls to check_div_hilo.
952
953Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
954
955 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
956 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
957 Add special r3900 version of do_mult_hilo.
958 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
959 with calls to check_mult_hilo.
960 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
961 with calls to check_div_hilo.
962
963Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
964
965 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
966 Document a replacement.
967
968Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
969
970 * interp.c (sim_monitor): Make mon_printf work.
971
972Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
973
974 * sim-main.h (INSN_NAME): New arg `cpu'.
975
976Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
977
978 * configure: Regenerated to track ../common/aclocal.m4 changes.
979
980Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
981
982 * configure: Regenerated to track ../common/aclocal.m4 changes.
983 * config.in: Ditto.
984
985Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
986
987 * acconfig.h: New file.
988 * configure.in: Reverted change of Apr 24; use sinclude again.
989
990Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
991
992 * configure: Regenerated to track ../common/aclocal.m4 changes.
993 * config.in: Ditto.
994
995Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
996
997 * configure.in: Don't call sinclude.
998
999Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1000
1001 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1002
1003Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1004
1005 * mips.igen (ERET): Implement.
1006
1007 * interp.c (decode_coproc): Return sign-extended EPC.
1008
1009 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1010
1011 * interp.c (signal_exception): Do not ignore Trap.
1012 (signal_exception): On TRAP, restart at exception address.
1013 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1014 (signal_exception): Update.
1015 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1016 so that TRAP instructions are caught.
1017
1018Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1019
1020 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1021 contains HI/LO access history.
1022 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1023 (HIACCESS, LOACCESS): Delete, replace with
1024 (HIHISTORY, LOHISTORY): New macros.
1025 (CHECKHILO): Delete all, moved to mips.igen
1026
1027 * gencode.c (build_instruction): Do not generate checks for
1028 correct HI/LO register usage.
1029
1030 * interp.c (old_engine_run): Delete checks for correct HI/LO
1031 register usage.
1032
1033 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1034 check_mf_cycles): New functions.
1035 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1036 do_divu, domultx, do_mult, do_multu): Use.
1037
1038 * tx.igen ("madd", "maddu"): Use.
1039
1040Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041
1042 * mips.igen (DSRAV): Use function do_dsrav.
1043 (SRAV): Use new function do_srav.
1044
1045 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1046 (B): Sign extend 11 bit immediate.
1047 (EXT-B*): Shift 16 bit immediate left by 1.
1048 (ADDIU*): Don't sign extend immediate value.
1049
1050Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1051
1052 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1053
1054 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1055 functions.
1056
1057 * mips.igen (delayslot32, nullify_next_insn): New functions.
1058 (m16.igen): Always include.
1059 (do_*): Add more tracing.
1060
1061 * m16.igen (delayslot16): Add NIA argument, could be called by a
1062 32 bit MIPS16 instruction.
1063
1064 * interp.c (ifetch16): Move function from here.
1065 * sim-main.c (ifetch16): To here.
1066
1067 * sim-main.c (ifetch16, ifetch32): Update to match current
1068 implementations of LH, LW.
1069 (signal_exception): Don't print out incorrect hex value of illegal
1070 instruction.
1071
1072Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1073
1074 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1075 instruction.
1076
1077 * m16.igen: Implement MIPS16 instructions.
1078
1079 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1080 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1081 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1082 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1083 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1084 bodies of corresponding code from 32 bit insn to these. Also used
1085 by MIPS16 versions of functions.
1086
1087 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1088 (IMEM16): Drop NR argument from macro.
1089
1090Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * Makefile.in (SIM_OBJS): Add sim-main.o.
1093
1094 * sim-main.h (address_translation, load_memory, store_memory,
1095 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1096 as INLINE_SIM_MAIN.
1097 (pr_addr, pr_uword64): Declare.
1098 (sim-main.c): Include when H_REVEALS_MODULE_P.
1099
1100 * interp.c (address_translation, load_memory, store_memory,
1101 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1102 from here.
1103 * sim-main.c: To here. Fix compilation problems.
1104
1105 * configure.in: Enable inlining.
1106 * configure: Re-config.
1107
1108Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1109
1110 * configure: Regenerated to track ../common/aclocal.m4 changes.
1111
1112Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * mips.igen: Include tx.igen.
1115 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1116 * tx.igen: New file, contains MADD and MADDU.
1117
1118 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1119 the hardwired constant `7'.
1120 (store_memory): Ditto.
1121 (LOADDRMASK): Move definition to sim-main.h.
1122
1123 mips.igen (MTC0): Enable for r3900.
1124 (ADDU): Add trace.
1125
1126 mips.igen (do_load_byte): Delete.
1127 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1128 do_store_right): New functions.
1129 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1130
1131 configure.in: Let the tx39 use igen again.
1132 configure: Update.
1133
1134Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1135
1136 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1137 not an address sized quantity. Return zero for cache sizes.
1138
1139Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1140
1141 * mips.igen (r3900): r3900 does not support 64 bit integer
1142 operations.
1143
1144Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1145
1146 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1147 than igen one.
1148 * configure : Rebuild.
1149
1150Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1151
1152 * configure: Regenerated to track ../common/aclocal.m4 changes.
1153
1154Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155
1156 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1157
1158Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1159
1160 * configure: Regenerated to track ../common/aclocal.m4 changes.
1161 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1162
1163Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1164
1165 * configure: Regenerated to track ../common/aclocal.m4 changes.
1166
1167Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1168
1169 * interp.c (Max, Min): Comment out functions. Not yet used.
1170
1171Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * configure: Regenerated to track ../common/aclocal.m4 changes.
1174
1175Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1176
1177 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1178 configurable settings for stand-alone simulator.
1179
1180 * configure.in: Added X11 search, just in case.
1181
1182 * configure: Regenerated.
1183
1184Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * interp.c (sim_write, sim_read, load_memory, store_memory):
1187 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1188
1189Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1190
1191 * sim-main.h (GETFCC): Return an unsigned value.
1192
1193Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1196 (DADD): Result destination is RD not RT.
1197
1198Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1199
1200 * sim-main.h (HIACCESS, LOACCESS): Always define.
1201
1202 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1203
1204 * interp.c (sim_info): Delete.
1205
1206Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1207
1208 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1209 (mips_option_handler): New argument `cpu'.
1210 (sim_open): Update call to sim_add_option_table.
1211
1212Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 * mips.igen (CxC1): Add tracing.
1215
1216Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * sim-main.h (Max, Min): Declare.
1219
1220 * interp.c (Max, Min): New functions.
1221
1222 * mips.igen (BC1): Add tracing.
1223
1224Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1225
1226 * interp.c Added memory map for stack in vr4100
1227
1228Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1229
1230 * interp.c (load_memory): Add missing "break"'s.
1231
1232Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1233
1234 * interp.c (sim_store_register, sim_fetch_register): Pass in
1235 length parameter. Return -1.
1236
1237Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1238
1239 * interp.c: Added hardware init hook, fixed warnings.
1240
1241Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1242
1243 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1244
1245Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1246
1247 * interp.c (ifetch16): New function.
1248
1249 * sim-main.h (IMEM32): Rename IMEM.
1250 (IMEM16_IMMED): Define.
1251 (IMEM16): Define.
1252 (DELAY_SLOT): Update.
1253
1254 * m16run.c (sim_engine_run): New file.
1255
1256 * m16.igen: All instructions except LB.
1257 (LB): Call do_load_byte.
1258 * mips.igen (do_load_byte): New function.
1259 (LB): Call do_load_byte.
1260
1261 * mips.igen: Move spec for insn bit size and high bit from here.
1262 * Makefile.in (tmp-igen, tmp-m16): To here.
1263
1264 * m16.dc: New file, decode mips16 instructions.
1265
1266 * Makefile.in (SIM_NO_ALL): Define.
1267 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1268
1269Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1270
1271 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1272 point unit to 32 bit registers.
1273 * configure: Re-generate.
1274
1275Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1276
1277 * configure.in (sim_use_gen): Make IGEN the default simulator
1278 generator for generic 32 and 64 bit mips targets.
1279 * configure: Re-generate.
1280
1281Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1284 bitsize.
1285
1286 * interp.c (sim_fetch_register, sim_store_register): Read/write
1287 FGR from correct location.
1288 (sim_open): Set size of FGR's according to
1289 WITH_TARGET_FLOATING_POINT_BITSIZE.
1290
1291 * sim-main.h (FGR): Store floating point registers in a separate
1292 array.
1293
1294Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * configure: Regenerated to track ../common/aclocal.m4 changes.
1297
1298Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1301
1302 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1303
1304 * interp.c (pending_tick): New function. Deliver pending writes.
1305
1306 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1307 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1308 it can handle mixed sized quantites and single bits.
1309
1310Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1311
1312 * interp.c (oengine.h): Do not include when building with IGEN.
1313 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1314 (sim_info): Ditto for PROCESSOR_64BIT.
1315 (sim_monitor): Replace ut_reg with unsigned_word.
1316 (*): Ditto for t_reg.
1317 (LOADDRMASK): Define.
1318 (sim_open): Remove defunct check that host FP is IEEE compliant,
1319 using software to emulate floating point.
1320 (value_fpr, ...): Always compile, was conditional on HASFPU.
1321
1322Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1323
1324 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1325 size.
1326
1327 * interp.c (SD, CPU): Define.
1328 (mips_option_handler): Set flags in each CPU.
1329 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1330 (sim_close): Do not clear STATE, deleted anyway.
1331 (sim_write, sim_read): Assume CPU zero's vm should be used for
1332 data transfers.
1333 (sim_create_inferior): Set the PC for all processors.
1334 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1335 argument.
1336 (mips16_entry): Pass correct nr of args to store_word, load_word.
1337 (ColdReset): Cold reset all cpu's.
1338 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1339 (sim_monitor, load_memory, store_memory, signal_exception): Use
1340 `CPU' instead of STATE_CPU.
1341
1342
1343 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1344 SD or CPU_.
1345
1346 * sim-main.h (signal_exception): Add sim_cpu arg.
1347 (SignalException*): Pass both SD and CPU to signal_exception.
1348 * interp.c (signal_exception): Update.
1349
1350 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1351 Ditto
1352 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1353 address_translation): Ditto
1354 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1355
1356Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * configure: Regenerated to track ../common/aclocal.m4 changes.
1359
1360Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1363
1364 * mips.igen (model): Map processor names onto BFD name.
1365
1366 * sim-main.h (CPU_CIA): Delete.
1367 (SET_CIA, GET_CIA): Define
1368
1369Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1370
1371 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1372 regiser.
1373
1374 * configure.in (default_endian): Configure a big-endian simulator
1375 by default.
1376 * configure: Re-generate.
1377
1378Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1379
1380 * configure: Regenerated to track ../common/aclocal.m4 changes.
1381
1382Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1383
1384 * interp.c (sim_monitor): Handle Densan monitor outbyte
1385 and inbyte functions.
1386
13871997-12-29 Felix Lee <flee@cygnus.com>
1388
1389 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1390
1391Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1392
1393 * Makefile.in (tmp-igen): Arrange for $zero to always be
1394 reset to zero after every instruction.
1395
1396Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1397
1398 * configure: Regenerated to track ../common/aclocal.m4 changes.
1399 * config.in: Ditto.
1400
1401Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1402
1403 * mips.igen (MSUB): Fix to work like MADD.
1404 * gencode.c (MSUB): Similarly.
1405
1406Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1407
1408 * configure: Regenerated to track ../common/aclocal.m4 changes.
1409
1410Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1413
1414Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * sim-main.h (sim-fpu.h): Include.
1417
1418 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1419 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1420 using host independant sim_fpu module.
1421
1422Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1423
1424 * interp.c (signal_exception): Report internal errors with SIGABRT
1425 not SIGQUIT.
1426
1427 * sim-main.h (C0_CONFIG): New register.
1428 (signal.h): No longer include.
1429
1430 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1431
1432Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1433
1434 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1435
1436Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * mips.igen: Tag vr5000 instructions.
1439 (ANDI): Was missing mipsIV model, fix assembler syntax.
1440 (do_c_cond_fmt): New function.
1441 (C.cond.fmt): Handle mips I-III which do not support CC field
1442 separatly.
1443 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1444 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1445 in IV3.2 spec.
1446 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1447 vr5000 which saves LO in a GPR separatly.
1448
1449 * configure.in (enable-sim-igen): For vr5000, select vr5000
1450 specific instructions.
1451 * configure: Re-generate.
1452
1453Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1456
1457 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1458 fmt_uninterpreted_64 bit cases to switch. Convert to
1459 fmt_formatted,
1460
1461 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1462
1463 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1464 as specified in IV3.2 spec.
1465 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1466
1467Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1470 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1471 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1472 PENDING_FILL versions of instructions. Simplify.
1473 (X): New function.
1474 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1475 instructions.
1476 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1477 a signed value.
1478 (MTHI, MFHI): Disable code checking HI-LO.
1479
1480 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1481 global.
1482 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1483
1484Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1485
1486 * gencode.c (build_mips16_operands): Replace IPC with cia.
1487
1488 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1489 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1490 IPC to `cia'.
1491 (UndefinedResult): Replace function with macro/function
1492 combination.
1493 (sim_engine_run): Don't save PC in IPC.
1494
1495 * sim-main.h (IPC): Delete.
1496
1497
1498 * interp.c (signal_exception, store_word, load_word,
1499 address_translation, load_memory, store_memory, cache_op,
1500 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1501 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1502 current instruction address - cia - argument.
1503 (sim_read, sim_write): Call address_translation directly.
1504 (sim_engine_run): Rename variable vaddr to cia.
1505 (signal_exception): Pass cia to sim_monitor
1506
1507 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1508 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1509 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1510
1511 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1512 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1513 SIM_ASSERT.
1514
1515 * interp.c (signal_exception): Pass restart address to
1516 sim_engine_restart.
1517
1518 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1519 idecode.o): Add dependency.
1520
1521 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1522 Delete definitions
1523 (DELAY_SLOT): Update NIA not PC with branch address.
1524 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1525
1526 * mips.igen: Use CIA not PC in branch calculations.
1527 (illegal): Call SignalException.
1528 (BEQ, ADDIU): Fix assembler.
1529
1530Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * m16.igen (JALX): Was missing.
1533
1534 * configure.in (enable-sim-igen): New configuration option.
1535 * configure: Re-generate.
1536
1537 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1538
1539 * interp.c (load_memory, store_memory): Delete parameter RAW.
1540 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1541 bypassing {load,store}_memory.
1542
1543 * sim-main.h (ByteSwapMem): Delete definition.
1544
1545 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1546
1547 * interp.c (sim_do_command, sim_commands): Delete mips specific
1548 commands. Handled by module sim-options.
1549
1550 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1551 (WITH_MODULO_MEMORY): Define.
1552
1553 * interp.c (sim_info): Delete code printing memory size.
1554
1555 * interp.c (mips_size): Nee sim_size, delete function.
1556 (power2): Delete.
1557 (monitor, monitor_base, monitor_size): Delete global variables.
1558 (sim_open, sim_close): Delete code creating monitor and other
1559 memory regions. Use sim-memopts module, via sim_do_commandf, to
1560 manage memory regions.
1561 (load_memory, store_memory): Use sim-core for memory model.
1562
1563 * interp.c (address_translation): Delete all memory map code
1564 except line forcing 32 bit addresses.
1565
1566Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1567
1568 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1569 trace options.
1570
1571 * interp.c (logfh, logfile): Delete globals.
1572 (sim_open, sim_close): Delete code opening & closing log file.
1573 (mips_option_handler): Delete -l and -n options.
1574 (OPTION mips_options): Ditto.
1575
1576 * interp.c (OPTION mips_options): Rename option trace to dinero.
1577 (mips_option_handler): Update.
1578
1579Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1580
1581 * interp.c (fetch_str): New function.
1582 (sim_monitor): Rewrite using sim_read & sim_write.
1583 (sim_open): Check magic number.
1584 (sim_open): Write monitor vectors into memory using sim_write.
1585 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1586 (sim_read, sim_write): Simplify - transfer data one byte at a
1587 time.
1588 (load_memory, store_memory): Clarify meaning of parameter RAW.
1589
1590 * sim-main.h (isHOST): Defete definition.
1591 (isTARGET): Mark as depreciated.
1592 (address_translation): Delete parameter HOST.
1593
1594 * interp.c (address_translation): Delete parameter HOST.
1595
1596Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1597
1598 * mips.igen:
1599
1600 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1601 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1602
1603Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604
1605 * mips.igen: Add model filter field to records.
1606
1607Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1610
1611 interp.c (sim_engine_run): Do not compile function sim_engine_run
1612 when WITH_IGEN == 1.
1613
1614 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1615 target architecture.
1616
1617 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1618 igen. Replace with configuration variables sim_igen_flags /
1619 sim_m16_flags.
1620
1621 * m16.igen: New file. Copy mips16 insns here.
1622 * mips.igen: From here.
1623
1624Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1627 to top.
1628 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1629
1630Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1631
1632 * gencode.c (build_instruction): Follow sim_write's lead in using
1633 BigEndianMem instead of !ByteSwapMem.
1634
1635Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636
1637 * configure.in (sim_gen): Dependent on target, select type of
1638 generator. Always select old style generator.
1639
1640 configure: Re-generate.
1641
1642 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1643 targets.
1644 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1645 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1646 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1647 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1648 SIM_@sim_gen@_*, set by autoconf.
1649
1650Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1651
1652 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1653
1654 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1655 CURRENT_FLOATING_POINT instead.
1656
1657 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1658 (address_translation): Raise exception InstructionFetch when
1659 translation fails and isINSTRUCTION.
1660
1661 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1662 sim_engine_run): Change type of of vaddr and paddr to
1663 address_word.
1664 (address_translation, prefetch, load_memory, store_memory,
1665 cache_op): Change type of vAddr and pAddr to address_word.
1666
1667 * gencode.c (build_instruction): Change type of vaddr and paddr to
1668 address_word.
1669
1670Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1671
1672 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1673 macro to obtain result of ALU op.
1674
1675Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * interp.c (sim_info): Call profile_print.
1678
1679Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1680
1681 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1682
1683 * sim-main.h (WITH_PROFILE): Do not define, defined in
1684 common/sim-config.h. Use sim-profile module.
1685 (simPROFILE): Delete defintion.
1686
1687 * interp.c (PROFILE): Delete definition.
1688 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1689 (sim_close): Delete code writing profile histogram.
1690 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1691 Delete.
1692 (sim_engine_run): Delete code profiling the PC.
1693
1694Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1697
1698 * interp.c (sim_monitor): Make register pointers of type
1699 unsigned_word*.
1700
1701 * sim-main.h: Make registers of type unsigned_word not
1702 signed_word.
1703
1704Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1705
1706 * interp.c (sync_operation): Rename from SyncOperation, make
1707 global, add SD argument.
1708 (prefetch): Rename from Prefetch, make global, add SD argument.
1709 (decode_coproc): Make global.
1710
1711 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1712
1713 * gencode.c (build_instruction): Generate DecodeCoproc not
1714 decode_coproc calls.
1715
1716 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1717 (SizeFGR): Move to sim-main.h
1718 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1719 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1720 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1721 sim-main.h.
1722 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1723 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1724 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1725 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1726 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1727 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1728
1729 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1730 exception.
1731 (sim-alu.h): Include.
1732 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1733 (sim_cia): Typedef to instruction_address.
1734
1735Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * Makefile.in (interp.o): Rename generated file engine.c to
1738 oengine.c.
1739
1740 * interp.c: Update.
1741
1742Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1745
1746Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1747
1748 * gencode.c (build_instruction): For "FPSQRT", output correct
1749 number of arguments to Recip.
1750
1751Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * Makefile.in (interp.o): Depends on sim-main.h
1754
1755 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1756
1757 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1758 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1759 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1760 STATE, DSSTATE): Define
1761 (GPR, FGRIDX, ..): Define.
1762
1763 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1764 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1765 (GPR, FGRIDX, ...): Delete macros.
1766
1767 * interp.c: Update names to match defines from sim-main.h
1768
1769Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1770
1771 * interp.c (sim_monitor): Add SD argument.
1772 (sim_warning): Delete. Replace calls with calls to
1773 sim_io_eprintf.
1774 (sim_error): Delete. Replace calls with sim_io_error.
1775 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1776 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1777 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1778 argument.
1779 (mips_size): Rename from sim_size. Add SD argument.
1780
1781 * interp.c (simulator): Delete global variable.
1782 (callback): Delete global variable.
1783 (mips_option_handler, sim_open, sim_write, sim_read,
1784 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1785 sim_size,sim_monitor): Use sim_io_* not callback->*.
1786 (sim_open): ZALLOC simulator struct.
1787 (PROFILE): Do not define.
1788
1789Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1790
1791 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1792 support.h with corresponding code.
1793
1794 * sim-main.h (word64, uword64), support.h: Move definition to
1795 sim-main.h.
1796 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1797
1798 * support.h: Delete
1799 * Makefile.in: Update dependencies
1800 * interp.c: Do not include.
1801
1802Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1803
1804 * interp.c (address_translation, load_memory, store_memory,
1805 cache_op): Rename to from AddressTranslation et.al., make global,
1806 add SD argument
1807
1808 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1809 CacheOp): Define.
1810
1811 * interp.c (SignalException): Rename to signal_exception, make
1812 global.
1813
1814 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1815
1816 * sim-main.h (SignalException, SignalExceptionInterrupt,
1817 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1818 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1819 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1820 Define.
1821
1822 * interp.c, support.h: Use.
1823
1824Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1827 to value_fpr / store_fpr. Add SD argument.
1828 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1829 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1830
1831 * sim-main.h (ValueFPR, StoreFPR): Define.
1832
1833Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * interp.c (sim_engine_run): Check consistency between configure
1836 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1837 and HASFPU.
1838
1839 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1840 (mips_fpu): Configure WITH_FLOATING_POINT.
1841 (mips_endian): Configure WITH_TARGET_ENDIAN.
1842 * configure: Update.
1843
1844Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1845
1846 * configure: Regenerated to track ../common/aclocal.m4 changes.
1847
1848Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1849
1850 * configure: Regenerated.
1851
1852Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1853
1854 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1855
1856Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 * gencode.c (print_igen_insn_models): Assume certain architectures
1859 include all mips* instructions.
1860 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1861 instruction.
1862
1863 * Makefile.in (tmp.igen): Add target. Generate igen input from
1864 gencode file.
1865
1866 * gencode.c (FEATURE_IGEN): Define.
1867 (main): Add --igen option. Generate output in igen format.
1868 (process_instructions): Format output according to igen option.
1869 (print_igen_insn_format): New function.
1870 (print_igen_insn_models): New function.
1871 (process_instructions): Only issue warnings and ignore
1872 instructions when no FEATURE_IGEN.
1873
1874Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875
1876 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1877 MIPS targets.
1878
1879Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * configure: Regenerated to track ../common/aclocal.m4 changes.
1882
1883Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1886 SIM_RESERVED_BITS): Delete, moved to common.
1887 (SIM_EXTRA_CFLAGS): Update.
1888
1889Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * configure.in: Configure non-strict memory alignment.
1892 * configure: Regenerated to track ../common/aclocal.m4 changes.
1893
1894Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * configure: Regenerated to track ../common/aclocal.m4 changes.
1897
1898Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1899
1900 * gencode.c (SDBBP,DERET): Added (3900) insns.
1901 (RFE): Turn on for 3900.
1902 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1903 (dsstate): Made global.
1904 (SUBTARGET_R3900): Added.
1905 (CANCELDELAYSLOT): New.
1906 (SignalException): Ignore SystemCall rather than ignore and
1907 terminate. Add DebugBreakPoint handling.
1908 (decode_coproc): New insns RFE, DERET; and new registers Debug
1909 and DEPC protected by SUBTARGET_R3900.
1910 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1911 bits explicitly.
1912 * Makefile.in,configure.in: Add mips subtarget option.
1913 * configure: Update.
1914
1915Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1916
1917 * gencode.c: Add r3900 (tx39).
1918
1919
1920Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1921
1922 * gencode.c (build_instruction): Don't need to subtract 4 for
1923 JALR, just 2.
1924
1925Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1926
1927 * interp.c: Correct some HASFPU problems.
1928
1929Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1930
1931 * configure: Regenerated to track ../common/aclocal.m4 changes.
1932
1933Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * interp.c (mips_options): Fix samples option short form, should
1936 be `x'.
1937
1938Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1939
1940 * interp.c (sim_info): Enable info code. Was just returning.
1941
1942Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1943
1944 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1945 MFC0.
1946
1947Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1950 constants.
1951 (build_instruction): Ditto for LL.
1952
1953Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1954
1955 * configure: Regenerated to track ../common/aclocal.m4 changes.
1956
1957Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1958
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1960 * config.in: Ditto.
1961
1962Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * interp.c (sim_open): Add call to sim_analyze_program, update
1965 call to sim_config.
1966
1967Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1968
1969 * interp.c (sim_kill): Delete.
1970 (sim_create_inferior): Add ABFD argument. Set PC from same.
1971 (sim_load): Move code initializing trap handlers from here.
1972 (sim_open): To here.
1973 (sim_load): Delete, use sim-hload.c.
1974
1975 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1976
1977Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1978
1979 * configure: Regenerated to track ../common/aclocal.m4 changes.
1980 * config.in: Ditto.
1981
1982Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * interp.c (sim_open): Add ABFD argument.
1985 (sim_load): Move call to sim_config from here.
1986 (sim_open): To here. Check return status.
1987
1988Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1989
1990 * gencode.c (build_instruction): Two arg MADD should
1991 not assign result to $0.
1992
1993Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1994
1995 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1996 * sim/mips/configure.in: Regenerate.
1997
1998Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1999
2000 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2001 signed8, unsigned8 et.al. types.
2002
2003 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2004 hosts when selecting subreg.
2005
2006Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2007
2008 * interp.c (sim_engine_run): Reset the ZERO register to zero
2009 regardless of FEATURE_WARN_ZERO.
2010 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2011
2012Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2015 (SignalException): For BreakPoints ignore any mode bits and just
2016 save the PC.
2017 (SignalException): Always set the CAUSE register.
2018
2019Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2020
2021 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2022 exception has been taken.
2023
2024 * interp.c: Implement the ERET and mt/f sr instructions.
2025
2026Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2027
2028 * interp.c (SignalException): Don't bother restarting an
2029 interrupt.
2030
2031Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * interp.c (SignalException): Really take an interrupt.
2034 (interrupt_event): Only deliver interrupts when enabled.
2035
2036Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2037
2038 * interp.c (sim_info): Only print info when verbose.
2039 (sim_info) Use sim_io_printf for output.
2040
2041Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2044 mips architectures.
2045
2046Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2047
2048 * interp.c (sim_do_command): Check for common commands if a
2049 simulator specific command fails.
2050
2051Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2052
2053 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2054 and simBE when DEBUG is defined.
2055
2056Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2057
2058 * interp.c (interrupt_event): New function. Pass exception event
2059 onto exception handler.
2060
2061 * configure.in: Check for stdlib.h.
2062 * configure: Regenerate.
2063
2064 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2065 variable declaration.
2066 (build_instruction): Initialize memval1.
2067 (build_instruction): Add UNUSED attribute to byte, bigend,
2068 reverse.
2069 (build_operands): Ditto.
2070
2071 * interp.c: Fix GCC warnings.
2072 (sim_get_quit_code): Delete.
2073
2074 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2075 * Makefile.in: Ditto.
2076 * configure: Re-generate.
2077
2078 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2079
2080Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2081
2082 * interp.c (mips_option_handler): New function parse argumes using
2083 sim-options.
2084 (myname): Replace with STATE_MY_NAME.
2085 (sim_open): Delete check for host endianness - performed by
2086 sim_config.
2087 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2088 (sim_open): Move much of the initialization from here.
2089 (sim_load): To here. After the image has been loaded and
2090 endianness set.
2091 (sim_open): Move ColdReset from here.
2092 (sim_create_inferior): To here.
2093 (sim_open): Make FP check less dependant on host endianness.
2094
2095 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2096 run.
2097 * interp.c (sim_set_callbacks): Delete.
2098
2099 * interp.c (membank, membank_base, membank_size): Replace with
2100 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2101 (sim_open): Remove call to callback->init. gdb/run do this.
2102
2103 * interp.c: Update
2104
2105 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2106
2107 * interp.c (big_endian_p): Delete, replaced by
2108 current_target_byte_order.
2109
2110Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * interp.c (host_read_long, host_read_word, host_swap_word,
2113 host_swap_long): Delete. Using common sim-endian.
2114 (sim_fetch_register, sim_store_register): Use H2T.
2115 (pipeline_ticks): Delete. Handled by sim-events.
2116 (sim_info): Update.
2117 (sim_engine_run): Update.
2118
2119Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2122 reason from here.
2123 (SignalException): To here. Signal using sim_engine_halt.
2124 (sim_stop_reason): Delete, moved to common.
2125
2126Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2127
2128 * interp.c (sim_open): Add callback argument.
2129 (sim_set_callbacks): Delete SIM_DESC argument.
2130 (sim_size): Ditto.
2131
2132Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2133
2134 * Makefile.in (SIM_OBJS): Add common modules.
2135
2136 * interp.c (sim_set_callbacks): Also set SD callback.
2137 (set_endianness, xfer_*, swap_*): Delete.
2138 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2139 Change to functions using sim-endian macros.
2140 (control_c, sim_stop): Delete, use common version.
2141 (simulate): Convert into.
2142 (sim_engine_run): This function.
2143 (sim_resume): Delete.
2144
2145 * interp.c (simulation): New variable - the simulator object.
2146 (sim_kind): Delete global - merged into simulation.
2147 (sim_load): Cleanup. Move PC assignment from here.
2148 (sim_create_inferior): To here.
2149
2150 * sim-main.h: New file.
2151 * interp.c (sim-main.h): Include.
2152
2153Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2154
2155 * configure: Regenerated to track ../common/aclocal.m4 changes.
2156
2157Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2158
2159 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2160
2161Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2162
2163 * gencode.c (build_instruction): DIV instructions: check
2164 for division by zero and integer overflow before using
2165 host's division operation.
2166
2167Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2168
2169 * Makefile.in (SIM_OBJS): Add sim-load.o.
2170 * interp.c: #include bfd.h.
2171 (target_byte_order): Delete.
2172 (sim_kind, myname, big_endian_p): New static locals.
2173 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2174 after argument parsing. Recognize -E arg, set endianness accordingly.
2175 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2176 load file into simulator. Set PC from bfd.
2177 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2178 (set_endianness): Use big_endian_p instead of target_byte_order.
2179
2180Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2181
2182 * interp.c (sim_size): Delete prototype - conflicts with
2183 definition in remote-sim.h. Correct definition.
2184
2185Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2186
2187 * configure: Regenerated to track ../common/aclocal.m4 changes.
2188 * config.in: Ditto.
2189
2190Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2191
2192 * interp.c (sim_open): New arg `kind'.
2193
2194 * configure: Regenerated to track ../common/aclocal.m4 changes.
2195
2196Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2197
2198 * configure: Regenerated to track ../common/aclocal.m4 changes.
2199
2200Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2201
2202 * interp.c (sim_open): Set optind to 0 before calling getopt.
2203
2204Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2205
2206 * configure: Regenerated to track ../common/aclocal.m4 changes.
2207
2208Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2209
2210 * interp.c : Replace uses of pr_addr with pr_uword64
2211 where the bit length is always 64 independent of SIM_ADDR.
2212 (pr_uword64) : added.
2213
2214Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2215
2216 * configure: Re-generate.
2217
2218Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2219
2220 * configure: Regenerate to track ../common/aclocal.m4 changes.
2221
2222Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2223
2224 * interp.c (sim_open): New SIM_DESC result. Argument is now
2225 in argv form.
2226 (other sim_*): New SIM_DESC argument.
2227
2228Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2229
2230 * interp.c: Fix printing of addresses for non-64-bit targets.
2231 (pr_addr): Add function to print address based on size.
2232
2233Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2234
2235 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2236
2237Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2238
2239 * gencode.c (build_mips16_operands): Correct computation of base
2240 address for extended PC relative instruction.
2241
2242Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2243
2244 * interp.c (mips16_entry): Add support for floating point cases.
2245 (SignalException): Pass floating point cases to mips16_entry.
2246 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2247 registers.
2248 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2249 or fmt_word.
2250 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2251 and then set the state to fmt_uninterpreted.
2252 (COP_SW): Temporarily set the state to fmt_word while calling
2253 ValueFPR.
2254
2255Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2256
2257 * gencode.c (build_instruction): The high order may be set in the
2258 comparison flags at any ISA level, not just ISA 4.
2259
2260Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2261
2262 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2263 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2264 * configure.in: sinclude ../common/aclocal.m4.
2265 * configure: Regenerated.
2266
2267Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2268
2269 * configure: Rebuild after change to aclocal.m4.
2270
2271Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2272
2273 * configure configure.in Makefile.in: Update to new configure
2274 scheme which is more compatible with WinGDB builds.
2275 * configure.in: Improve comment on how to run autoconf.
2276 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2277 * Makefile.in: Use autoconf substitution to install common
2278 makefile fragment.
2279
2280Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2281
2282 * gencode.c (build_instruction): Use BigEndianCPU instead of
2283 ByteSwapMem.
2284
2285Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2286
2287 * interp.c (sim_monitor): Make output to stdout visible in
2288 wingdb's I/O log window.
2289
2290Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2291
2292 * support.h: Undo previous change to SIGTRAP
2293 and SIGQUIT values.
2294
2295Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2296
2297 * interp.c (store_word, load_word): New static functions.
2298 (mips16_entry): New static function.
2299 (SignalException): Look for mips16 entry and exit instructions.
2300 (simulate): Use the correct index when setting fpr_state after
2301 doing a pending move.
2302
2303Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2304
2305 * interp.c: Fix byte-swapping code throughout to work on
2306 both little- and big-endian hosts.
2307
2308Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2309
2310 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2311 with gdb/config/i386/xm-windows.h.
2312
2313Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2314
2315 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2316 that messes up arithmetic shifts.
2317
2318Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2319
2320 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2321 SIGTRAP and SIGQUIT for _WIN32.
2322
2323Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2324
2325 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2326 force a 64 bit multiplication.
2327 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2328 destination register is 0, since that is the default mips16 nop
2329 instruction.
2330
2331Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2332
2333 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2334 (build_endian_shift): Don't check proc64.
2335 (build_instruction): Always set memval to uword64. Cast op2 to
2336 uword64 when shifting it left in memory instructions. Always use
2337 the same code for stores--don't special case proc64.
2338
2339 * gencode.c (build_mips16_operands): Fix base PC value for PC
2340 relative operands.
2341 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2342 jal instruction.
2343 * interp.c (simJALDELAYSLOT): Define.
2344 (JALDELAYSLOT): Define.
2345 (INDELAYSLOT, INJALDELAYSLOT): Define.
2346 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2347
2348Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2349
2350 * interp.c (sim_open): add flush_cache as a PMON routine
2351 (sim_monitor): handle flush_cache by ignoring it
2352
2353Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2354
2355 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2356 BigEndianMem.
2357 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2358 (BigEndianMem): Rename to ByteSwapMem and change sense.
2359 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2360 BigEndianMem references to !ByteSwapMem.
2361 (set_endianness): New function, with prototype.
2362 (sim_open): Call set_endianness.
2363 (sim_info): Use simBE instead of BigEndianMem.
2364 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2365 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2366 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2367 ifdefs, keeping the prototype declaration.
2368 (swap_word): Rewrite correctly.
2369 (ColdReset): Delete references to CONFIG. Delete endianness related
2370 code; moved to set_endianness.
2371
2372Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2373
2374 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2375 * interp.c (CHECKHILO): Define away.
2376 (simSIGINT): New macro.
2377 (membank_size): Increase from 1MB to 2MB.
2378 (control_c): New function.
2379 (sim_resume): Rename parameter signal to signal_number. Add local
2380 variable prev. Call signal before and after simulate.
2381 (sim_stop_reason): Add simSIGINT support.
2382 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2383 functions always.
2384 (sim_warning): Delete call to SignalException. Do call printf_filtered
2385 if logfh is NULL.
2386 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2387 a call to sim_warning.
2388
2389Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2390
2391 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2392 16 bit instructions.
2393
2394Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2395
2396 Add support for mips16 (16 bit MIPS implementation):
2397 * gencode.c (inst_type): Add mips16 instruction encoding types.
2398 (GETDATASIZEINSN): Define.
2399 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2400 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2401 mtlo.
2402 (MIPS16_DECODE): New table, for mips16 instructions.
2403 (bitmap_val): New static function.
2404 (struct mips16_op): Define.
2405 (mips16_op_table): New table, for mips16 operands.
2406 (build_mips16_operands): New static function.
2407 (process_instructions): If PC is odd, decode a mips16
2408 instruction. Break out instruction handling into new
2409 build_instruction function.
2410 (build_instruction): New static function, broken out of
2411 process_instructions. Check modifiers rather than flags for SHIFT
2412 bit count and m[ft]{hi,lo} direction.
2413 (usage): Pass program name to fprintf.
2414 (main): Remove unused variable this_option_optind. Change
2415 ``*loptarg++'' to ``loptarg++''.
2416 (my_strtoul): Parenthesize && within ||.
2417 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2418 (simulate): If PC is odd, fetch a 16 bit instruction, and
2419 increment PC by 2 rather than 4.
2420 * configure.in: Add case for mips16*-*-*.
2421 * configure: Rebuild.
2422
2423Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2424
2425 * interp.c: Allow -t to enable tracing in standalone simulator.
2426 Fix garbage output in trace file and error messages.
2427
2428Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2429
2430 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2431 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2432 * configure.in: Simplify using macros in ../common/aclocal.m4.
2433 * configure: Regenerated.
2434 * tconfig.in: New file.
2435
2436Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2437
2438 * interp.c: Fix bugs in 64-bit port.
2439 Use ansi function declarations for msvc compiler.
2440 Initialize and test file pointer in trace code.
2441 Prevent duplicate definition of LAST_EMED_REGNUM.
2442
2443Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2444
2445 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2446
2447Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2448
2449 * interp.c (SignalException): Check for explicit terminating
2450 breakpoint value.
2451 * gencode.c: Pass instruction value through SignalException()
2452 calls for Trap, Breakpoint and Syscall.
2453
2454Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2455
2456 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2457 only used on those hosts that provide it.
2458 * configure.in: Add sqrt() to list of functions to be checked for.
2459 * config.in: Re-generated.
2460 * configure: Re-generated.
2461
2462Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2463
2464 * gencode.c (process_instructions): Call build_endian_shift when
2465 expanding STORE RIGHT, to fix swr.
2466 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2467 clear the high bits.
2468 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2469 Fix float to int conversions to produce signed values.
2470
2471Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2472
2473 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2474 (process_instructions): Correct handling of nor instruction.
2475 Correct shift count for 32 bit shift instructions. Correct sign
2476 extension for arithmetic shifts to not shift the number of bits in
2477 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2478 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2479 Fix madd.
2480 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2481 It's OK to have a mult follow a mult. What's not OK is to have a
2482 mult follow an mfhi.
2483 (Convert): Comment out incorrect rounding code.
2484
2485Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2486
2487 * interp.c (sim_monitor): Improved monitor printf
2488 simulation. Tidied up simulator warnings, and added "--log" option
2489 for directing warning message output.
2490 * gencode.c: Use sim_warning() rather than WARNING macro.
2491
2492Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2493
2494 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2495 getopt1.o, rather than on gencode.c. Link objects together.
2496 Don't link against -liberty.
2497 (gencode.o, getopt.o, getopt1.o): New targets.
2498 * gencode.c: Include <ctype.h> and "ansidecl.h".
2499 (AND): Undefine after including "ansidecl.h".
2500 (ULONG_MAX): Define if not defined.
2501 (OP_*): Don't define macros; now defined in opcode/mips.h.
2502 (main): Call my_strtoul rather than strtoul.
2503 (my_strtoul): New static function.
2504
2505Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2506
2507 * gencode.c (process_instructions): Generate word64 and uword64
2508 instead of `long long' and `unsigned long long' data types.
2509 * interp.c: #include sysdep.h to get signals, and define default
2510 for SIGBUS.
2511 * (Convert): Work around for Visual-C++ compiler bug with type
2512 conversion.
2513 * support.h: Make things compile under Visual-C++ by using
2514 __int64 instead of `long long'. Change many refs to long long
2515 into word64/uword64 typedefs.
2516
2517Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2518
2519 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2520 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2521 (docdir): Removed.
2522 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2523 (AC_PROG_INSTALL): Added.
2524 (AC_PROG_CC): Moved to before configure.host call.
2525 * configure: Rebuilt.
2526
2527Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2528
2529 * configure.in: Define @SIMCONF@ depending on mips target.
2530 * configure: Rebuild.
2531 * Makefile.in (run): Add @SIMCONF@ to control simulator
2532 construction.
2533 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2534 * interp.c: Remove some debugging, provide more detailed error
2535 messages, update memory accesses to use LOADDRMASK.
2536
2537Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2538
2539 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2540 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2541 stamp-h.
2542 * configure: Rebuild.
2543 * config.in: New file, generated by autoheader.
2544 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2545 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2546 HAVE_ANINT and HAVE_AINT, as appropriate.
2547 * Makefile.in (run): Use @LIBS@ rather than -lm.
2548 (interp.o): Depend upon config.h.
2549 (Makefile): Just rebuild Makefile.
2550 (clean): Remove stamp-h.
2551 (mostlyclean): Make the same as clean, not as distclean.
2552 (config.h, stamp-h): New targets.
2553
2554Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2555
2556 * interp.c (ColdReset): Fix boolean test. Make all simulator
2557 globals static.
2558
2559Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2560
2561 * interp.c (xfer_direct_word, xfer_direct_long,
2562 swap_direct_word, swap_direct_long, xfer_big_word,
2563 xfer_big_long, xfer_little_word, xfer_little_long,
2564 swap_word,swap_long): Added.
2565 * interp.c (ColdReset): Provide function indirection to
2566 host<->simulated_target transfer routines.
2567 * interp.c (sim_store_register, sim_fetch_register): Updated to
2568 make use of indirected transfer routines.
2569
2570Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2571
2572 * gencode.c (process_instructions): Ensure FP ABS instruction
2573 recognised.
2574 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2575 system call support.
2576
2577Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2578
2579 * interp.c (sim_do_command): Complain if callback structure not
2580 initialised.
2581
2582Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2583
2584 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2585 support for Sun hosts.
2586 * Makefile.in (gencode): Ensure the host compiler and libraries
2587 used for cross-hosted build.
2588
2589Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2590
2591 * interp.c, gencode.c: Some more (TODO) tidying.
2592
2593Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2594
2595 * gencode.c, interp.c: Replaced explicit long long references with
2596 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2597 * support.h (SET64LO, SET64HI): Macros added.
2598
2599Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2600
2601 * configure: Regenerate with autoconf 2.7.
2602
2603Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2604
2605 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2606 * support.h: Remove superfluous "1" from #if.
2607 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2608
2609Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2610
2611 * interp.c (StoreFPR): Control UndefinedResult() call on
2612 WARN_RESULT manifest.
2613
2614Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2615
2616 * gencode.c: Tidied instruction decoding, and added FP instruction
2617 support.
2618
2619 * interp.c: Added dineroIII, and BSD profiling support. Also
2620 run-time FP handling.
2621
2622Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2623
2624 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2625 gencode.c, interp.c, support.h: created.
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