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x86: drop dead code from OP_IMREG()
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e8b5d5f9
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
4 CH, DH, BH, AX, DX): Delete.
5 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
6 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
7 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
8
260cd341
LC		 92020-07-10 Lili Cui <lili.cui@intel.com>
10
11 * i386-dis.c (TMM): New.
12 (EXtmm): Likewise.
13 (VexTmm): Likewise.
14 (MVexSIBMEM): Likewise.
15 (tmm_mode): Likewise.
16 (vex_sibmem_mode): Likewise.
17 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
18 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
19 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
20 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
21 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
22 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
23 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
24 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
25 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
26 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
27 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
28 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
29 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
30 (PREFIX_VEX_0F3849_X86_64): Likewise.
31 (PREFIX_VEX_0F384B_X86_64): Likewise.
32 (PREFIX_VEX_0F385C_X86_64): Likewise.
33 (PREFIX_VEX_0F385E_X86_64): Likewise.
34 (X86_64_VEX_0F3849): Likewise.
35 (X86_64_VEX_0F384B): Likewise.
36 (X86_64_VEX_0F385C): Likewise.
37 (X86_64_VEX_0F385E): Likewise.
38 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
39 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
40 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
41 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
42 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
43 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
44 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
45 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
46 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
47 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
48 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
49 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
50 (VEX_W_0F3849_X86_64_P_0): Likewise.
51 (VEX_W_0F3849_X86_64_P_2): Likewise.
52 (VEX_W_0F3849_X86_64_P_3): Likewise.
53 (VEX_W_0F384B_X86_64_P_1): Likewise.
54 (VEX_W_0F384B_X86_64_P_2): Likewise.
55 (VEX_W_0F384B_X86_64_P_3): Likewise.
56 (VEX_W_0F385C_X86_64_P_1): Likewise.
57 (VEX_W_0F385E_X86_64_P_0): Likewise.
58 (VEX_W_0F385E_X86_64_P_1): Likewise.
59 (VEX_W_0F385E_X86_64_P_2): Likewise.
60 (VEX_W_0F385E_X86_64_P_3): Likewise.
61 (names_tmm): Likewise.
62 (att_names_tmm): Likewise.
63 (intel_operand_size): Handle void_mode.
64 (OP_XMM): Handle tmm_mode.
65 (OP_EX): Likewise.
66 (OP_VEX): Likewise.
67 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
68 CpuAMX_BF16 and CpuAMX_TILE.
69 (operand_type_shorthands): Add RegTMM.
70 (operand_type_init): Likewise.
71 (operand_types): Add Tmmword.
72 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
73 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
74 * i386-opc.h (CpuAMX_INT8): New.
75 (CpuAMX_BF16): Likewise.
76 (CpuAMX_TILE): Likewise.
77 (SIBMEM): Likewise.
78 (Tmmword): Likewise.
79 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
80 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
81 (i386_operand_type): Add tmmword.
82 * i386-opc.tbl: Add AMX instructions.
83 * i386-reg.tbl: Add AMX registers.
84 * i386-init.h: Regenerated.
85 * i386-tbl.h: Likewise.
86
467bbef0
JB		 872020-07-08 Jan Beulich <jbeulich@suse.com>
88
89 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
90 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
91 Rename to ...
92 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
93 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
94 respectively.
95 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
96 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
97 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
98 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
99 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
100 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
101 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
102 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
103 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
104 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
105 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
106 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
107 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
108 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
109 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
110 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
111 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
112 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
113 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
114 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
115 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
116 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
117 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
118 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
119 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
120 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
121 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
122 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
123 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
124 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
125 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
126 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
127 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
128 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
129 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
130 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
131 (reg_table): Re-order XOP entries. Adjust their operands.
132 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
133 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
134 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
135 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
136 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
137 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
138 entries by references ...
139 (vex_len_table): ... to resepctive new entries here. For several
140 new and existing entries reference ...
141 (vex_w_table): ... new entries here.
142 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
143
6384fd9e
JB		 1442020-07-08 Jan Beulich <jbeulich@suse.com>
145
146 * i386-dis.c (XMVexScalarI4): Define.
147 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
148 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
149 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
150 (vex_len_table): Move scalar FMA4 entries ...
151 (prefix_table): ... here.
152 (OP_REG_VexI4): Handle scalar_mode.
153 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
154 * i386-tbl.h: Re-generate.
155
e6123d0c
JB		 1562020-07-08 Jan Beulich <jbeulich@suse.com>
157
158 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
159 Vex_2src_2): Delete.
160 (OP_VexW, VexW): New.
161 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
162 for shifts and rotates by register.
163
93abb146
JB		 1642020-07-08 Jan Beulich <jbeulich@suse.com>
165
166 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
167 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
168 OP_EX_VexReg): Delete.
169 (OP_VexI4, VexI4): New.
170 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
171 (prefix_table): ... here.
172 (print_insn): Drop setting of vex_w_done.
173
b13b1bc0
JB		 1742020-07-08 Jan Beulich <jbeulich@suse.com>
175
176 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
177 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
178 (xop_table): Replace operands of 4-operand insns.
179 (OP_REG_VexI4): Move VEX.W based operand swaping here.
180
f337259f
CZ		 1812020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
182
183 * arc-opc.c (insert_rbd): New function.
184 (RBD): Define.
185 (RBDdup): Likewise.
186 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
187 instructions.
188
931452b6
JB		 1892020-07-07 Jan Beulich <jbeulich@suse.com>
190
191 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
192 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
193 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
194 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
195 Delete.
196 (putop): Handle "BW".
197 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
198 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
199 and 0F3A3F ...
200 * i386-dis-evex-prefix.h: ... here.
201
b5b098c2
JB		 2022020-07-06 Jan Beulich <jbeulich@suse.com>
203
204 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
205 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
206 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
207 VEX_W_0FXOP_09_83): New enumerators.
208 (xop_table): Reference the above.
209 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
210 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
211 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
212 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
213
21a3faeb
JB		 2142020-07-06 Jan Beulich <jbeulich@suse.com>
215
216 * i386-dis.c (EVEX_W_0F3838_P_1,
217 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
218 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
219 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
220 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
221 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
222 (putop): Centralize management of last[]. Delete SAVE_LAST.
223 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
224 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
225 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
226 * i386-dis-evex-prefix.h: here.
227
bc152a17
JB		 2282020-07-06 Jan Beulich <jbeulich@suse.com>
229
230 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
231 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
232 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
233 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
234 enumerators.
235 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
236 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
237 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
238 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
239 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
240 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
241 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
242 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
243 these, respectively.
244 * i386-dis-evex-len.h: Adjust comments.
245 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
246 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
247 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
248 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
249 MOD_EVEX_0F385B_P_2_W_1 table entries.
250 * i386-dis-evex-w.h: Reference mod_table[] for
251 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
252 EVEX_W_0F385B_P_2.
253
c82a99a0
JB		 2542020-07-06 Jan Beulich <jbeulich@suse.com>
255
256 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
257 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
258 EXymm.
259 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
260 Likewise. Mark 256-bit entries invalid.
261
fedfb81e
JB		 2622020-07-06 Jan Beulich <jbeulich@suse.com>
263
264 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
265 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
266 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
267 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
268 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
269 PREFIX_EVEX_0F382B): Delete.
270 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
271 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
272 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
273 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
274 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
275 to ...
276 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
277 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
278 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
279 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
280 respectively.
281 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
282 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
283 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
284 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
285 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
286 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
287 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
288 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
289 PREFIX_EVEX_0F382B): Remove table entries.
290 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
291 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
292 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
293
3a57774c
JB		 2942020-07-06 Jan Beulich <jbeulich@suse.com>
295
296 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
297 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
298 enumerators.
299 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
300 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
301 EVEX_LEN_0F3A01_P_2_W_1 table entries.
302 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
303 entries.
304
e74d9fa9
JB		 3052020-07-06 Jan Beulich <jbeulich@suse.com>
306
307 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
308 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
309 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
310 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
311 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
312 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
313 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
314 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
315 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
316 entries.
317
6431c801
JB		 3182020-07-06 Jan Beulich <jbeulich@suse.com>
319
320 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
321 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
322 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
323 respectively.
324 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
325 entries.
326 * i386-dis-evex.h (evex_table): Reference VEX table entry for
327 opcode 0F3A1D.
328 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
329 entry.
330 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
331
6df22cf6
JB		 3322020-07-06 Jan Beulich <jbeulich@suse.com>
333
334 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
335 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
336 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
337 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
338 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
339 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
340 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
341 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
342 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
343 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
344 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
345 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
346 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
347 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
348 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
349 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
350 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
351 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
352 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
353 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
354 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
355 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
356 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
357 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
358 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
359 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
360 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
361 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
362 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
363 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
364 (prefix_table): Add EXxEVexR to FMA table entries.
365 (OP_Rounding): Move abort() invocation.
366 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
367 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
368 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
369 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
370 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
371 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
372 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
373 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
374 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
375 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
376 0F3ACE, 0F3ACF.
377 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
378 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
379 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
380 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
381 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
382 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
383 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
384 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
385 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
386 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
387 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
388 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
389 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
390 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
391 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
392 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
393 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
394 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
395 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
396 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
397 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
398 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
399 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
400 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
401 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
402 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
403 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
404 Delete table entries.
405 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
406 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
407 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
408 Likewise.
409
39e0f456
JB		 4102020-07-06 Jan Beulich <jbeulich@suse.com>
411
412 * i386-dis.c (EXqScalarS): Delete.
413 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
414 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
415
5b872f7d
JB		 4162020-07-06 Jan Beulich <jbeulich@suse.com>
417
418 * i386-dis.c (safe-ctype.h): Include.
419 (EXdScalar, EXqScalar): Delete.
420 (d_scalar_mode, q_scalar_mode): Delete.
421 (prefix_table, vex_len_table): Use EXxmm_md in place of
422 EXdScalar and EXxmm_mq in place of EXqScalar.
423 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
424 d_scalar_mode and q_scalar_mode.
425 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
426 (vmovsd): Use EXxmm_mq.
427
ddc73fa9
NC		 4282020-07-06 Yuri Chornoivan <yurchor@ukr.net>
429
430 PR 26204
431 * arc-dis.c: Fix spelling mistake.
432 * po/opcodes.pot: Regenerate.
433
17550be7
NC		 4342020-07-06 Nick Clifton <nickc@redhat.com>
435
436 * po/pt_BR.po: Updated Brazilian Portugugese translation.
437 * po/uk.po: Updated Ukranian translation.
438
b19d852d
NC		 4392020-07-04 Nick Clifton <nickc@redhat.com>
440
441 * configure: Regenerate.
442 * po/opcodes.pot: Regenerate.
443
b115b9fd
NC		 4442020-07-04 Nick Clifton <nickc@redhat.com>
445
446 Binutils 2.35 branch created.
447
c2ecccb3
L		 4482020-07-02 H.J. Lu <hongjiu.lu@intel.com>
449
450 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
451 * i386-opc.h (VexSwapSources): New.
452 (i386_opcode_modifier): Add vexswapsources.
453 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
454 with two source operands swapped.
455 * i386-tbl.h: Regenerated.
456
08ccfccf
NC		 4572020-06-30 Nelson Chu <nelson.chu@sifive.com>
458
459 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
460 unprivileged CSR can also be initialized.
461
279edac5
AM		 4622020-06-29 Alan Modra <amodra@gmail.com>
463
464 * arm-dis.c: Use C style comments.
465 * cr16-opc.c: Likewise.
466 * ft32-dis.c: Likewise.
467 * moxie-opc.c: Likewise.
468 * tic54x-dis.c: Likewise.
469 * s12z-opc.c: Remove useless comment.
470 * xgate-dis.c: Likewise.
471
e978ad62
L		 4722020-06-26 H.J. Lu <hongjiu.lu@intel.com>
473
474 * i386-opc.tbl: Add a blank line.
475
63112cd6
L		 4762020-06-26 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
479 (VecSIB128): Renamed to ...
480 (VECSIB128): This.
481 (VecSIB256): Renamed to ...
482 (VECSIB256): This.
483 (VecSIB512): Renamed to ...
484 (VECSIB512): This.
485 (VecSIB): Renamed to ...
486 (SIB): This.
487 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 488 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 489 (VecSIB256): Likewise.
490 (VecSIB512): Likewise.
79b32e73 491 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 492 and VecSIB512, respectively.
493
d1c36125
JB		 4942020-06-26 Jan Beulich <jbeulich@suse.com>
495
496 * i386-dis.c: Adjust description of I macro.
497 (x86_64_table): Drop use of I.
498 (float_mem): Replace use of I.
499 (putop): Remove handling of I. Adjust setting/clearing of "alt".
500
2a1bb84c
JB		 5012020-06-26 Jan Beulich <jbeulich@suse.com>
502
503 * i386-dis.c: (print_insn): Avoid straight assignment to
504 priv.orig_sizeflag when processing -M sub-options.
505
8f570d62
JB		 5062020-06-25 Jan Beulich <jbeulich@suse.com>
507
508 * i386-dis.c: Adjust description of J macro.
509 (dis386, x86_64_table, mod_table): Replace J.
510 (putop): Remove handling of J.
511
464dc4af
JB		 5122020-06-25 Jan Beulich <jbeulich@suse.com>
513
514 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
515
589958d6
JB		 5162020-06-25 Jan Beulich <jbeulich@suse.com>
517
518 * i386-dis.c: Adjust description of "LQ" macro.
519 (dis386_twobyte): Use LQ for sysret.
520 (putop): Adjust handling of LQ.
521
39ff0b81
NC		 5222020-06-22 Nelson Chu <nelson.chu@sifive.com>
523
524 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
525 * riscv-dis.c: Include elfxx-riscv.h.
526
d27c357a
JB		 5272020-06-18 H.J. Lu <hongjiu.lu@intel.com>
528
529 * i386-dis.c (prefix_table): Revert the last vmgexit change.
530
6fde587f
CL		 5312020-06-17 Lili Cui <lili.cui@intel.com>
532
533 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
534
efe30057
L		 5352020-06-14 H.J. Lu <hongjiu.lu@intel.com>
536
537 PR gas/26115
538 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
539 * i386-opc.tbl: Likewise.
540 * i386-tbl.h: Regenerated.
541
d8af286f
NC		 5422020-06-12 Nelson Chu <nelson.chu@sifive.com>
543
544 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
545
14962256
AC		 5462020-06-11 Alex Coplan <alex.coplan@arm.com>
547
548 * aarch64-opc.c (SYSREG): New macro for describing system registers.
549 (SR_CORE): Likewise.
550 (SR_FEAT): Likewise.
551 (SR_RNG): Likewise.
552 (SR_V8_1): Likewise.
553 (SR_V8_2): Likewise.
554 (SR_V8_3): Likewise.
555 (SR_V8_4): Likewise.
556 (SR_PAN): Likewise.
557 (SR_RAS): Likewise.
558 (SR_SSBS): Likewise.
559 (SR_SVE): Likewise.
560 (SR_ID_PFR2): Likewise.
561 (SR_PROFILE): Likewise.
562 (SR_MEMTAG): Likewise.
563 (SR_SCXTNUM): Likewise.
564 (aarch64_sys_regs): Refactor to store feature information in the table.
565 (aarch64_sys_reg_supported_p): Collapse logic for system registers
566 that now describe their own features.
567 (aarch64_pstatefield_supported_p): Likewise.
568
f9630fa6
L		 5692020-06-09 H.J. Lu <hongjiu.lu@intel.com>
570
571 * i386-dis.c (prefix_table): Fix a typo in comments.
572
73239888
JB		 5732020-06-09 Jan Beulich <jbeulich@suse.com>
574
575 * i386-dis.c (rex_ignored): Delete.
576 (ckprefix): Drop rex_ignored initialization.
577 (get_valid_dis386): Drop setting of rex_ignored.
578 (print_insn): Drop checking of rex_ignored. Don't record data
579 size prefix as used with VEX-and-alike encodings.
580
18897deb
JB		 5812020-06-09 Jan Beulich <jbeulich@suse.com>
582
583 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
584 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
585 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
586 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
587 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
588 VEX_0F12, and VEX_0F16.
589 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
590 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
591 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
592 from movlps and movhlps. New MOD_0F12_PREFIX_2,
593 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
594 MOD_VEX_0F16_PREFIX_2 entries.
595
97e6786a
JB		 5962020-06-09 Jan Beulich <jbeulich@suse.com>
597
598 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
599 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
600 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
601 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
602 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
603 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
604 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
605 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
606 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
607 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
608 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
609 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
610 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
611 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
612 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
613 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
614 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
615 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
616 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
617 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
618 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
619 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
620 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
621 EVEX_W_0FC6_P_2): Delete.
622 (print_insn): Add EVEX.W vs embedded prefix consistency check
623 to prefix validation.
624 * i386-dis-evex.h (evex_table): Don't further descend for
625 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
626 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
627 and 0F2B.
628 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
629 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
630 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
631 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
632 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
633 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
634 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
635 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
636 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
637 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
638 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
639 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
640 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
641 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
642 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
643 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
644 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
645 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
646 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
647 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
648 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
649 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
650 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
651 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
652 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
653 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
654 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
655
bf926894
JB		 6562020-06-09 Jan Beulich <jbeulich@suse.com>
657
658 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
659 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
660 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
661 vmovmskpX.
662 (print_insn): Drop pointless check against bad_opcode. Split
663 prefix validation into legacy and VEX-and-alike parts.
664 (putop): Re-work 'X' macro handling.
665
a5aaedb9
JB		 6662020-06-09 Jan Beulich <jbeulich@suse.com>
667
668 * i386-dis.c (MOD_0F51): Rename to ...
669 (MOD_0F50): ... this.
670
26417f19
AC		 6712020-06-08 Alex Coplan <alex.coplan@arm.com>
672
673 * arm-dis.c (arm_opcodes): Add dfb.
674 (thumb32_opcodes): Add dfb.
675
8a6fb3f9
JB		 6762020-06-08 Jan Beulich <jbeulich@suse.com>
677
678 * i386-opc.h (reg_entry): Const-qualify reg_name field.
679
1424c35d
AM		 6802020-06-06 Alan Modra <amodra@gmail.com>
681
682 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
683
d3d1cc7b
AM		 6842020-06-05 Alan Modra <amodra@gmail.com>
685
686 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
687 size is large enough.
688
d8740be1
JM		 6892020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
690
691 * disassemble.c (disassemble_init_for_target): Set endian_code for
692 bpf targets.
693 * bpf-desc.c: Regenerate.
694 * bpf-opc.c: Likewise.
695 * bpf-dis.c: Likewise.
696
e9bffec9
JM		 6972020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
698
699 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
700 (cgen_put_insn_value): Likewise.
701 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
702 * cgen-dis.in (print_insn): Likewise.
703 * cgen-ibld.in (insert_1): Likewise.
704 (insert_1): Likewise.
705 (insert_insn_normal): Likewise.
706 (extract_1): Likewise.
707 * bpf-dis.c: Regenerate.
708 * bpf-ibld.c: Likewise.
709 * bpf-ibld.c: Likewise.
710 * cgen-dis.in: Likewise.
711 * cgen-ibld.in: Likewise.
712 * cgen-opc.c: Likewise.
713 * epiphany-dis.c: Likewise.
714 * epiphany-ibld.c: Likewise.
715 * fr30-dis.c: Likewise.
716 * fr30-ibld.c: Likewise.
717 * frv-dis.c: Likewise.
718 * frv-ibld.c: Likewise.
719 * ip2k-dis.c: Likewise.
720 * ip2k-ibld.c: Likewise.
721 * iq2000-dis.c: Likewise.
722 * iq2000-ibld.c: Likewise.
723 * lm32-dis.c: Likewise.
724 * lm32-ibld.c: Likewise.
725 * m32c-dis.c: Likewise.
726 * m32c-ibld.c: Likewise.
727 * m32r-dis.c: Likewise.
728 * m32r-ibld.c: Likewise.
729 * mep-dis.c: Likewise.
730 * mep-ibld.c: Likewise.
731 * mt-dis.c: Likewise.
732 * mt-ibld.c: Likewise.
733 * or1k-dis.c: Likewise.
734 * or1k-ibld.c: Likewise.
735 * xc16x-dis.c: Likewise.
736 * xc16x-ibld.c: Likewise.
737 * xstormy16-dis.c: Likewise.
738 * xstormy16-ibld.c: Likewise.
739
b3db6d07
JM		 7402020-06-04 Jose E. Marchesi <jemarch@gnu.org>
741
742 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
743 (print_insn_): Handle instruction endian.
744 * bpf-dis.c: Regenerate.
745 * bpf-desc.c: Regenerate.
746 * epiphany-dis.c: Likewise.
747 * epiphany-desc.c: Likewise.
748 * fr30-dis.c: Likewise.
749 * fr30-desc.c: Likewise.
750 * frv-dis.c: Likewise.
751 * frv-desc.c: Likewise.
752 * ip2k-dis.c: Likewise.
753 * ip2k-desc.c: Likewise.
754 * iq2000-dis.c: Likewise.
755 * iq2000-desc.c: Likewise.
756 * lm32-dis.c: Likewise.
757 * lm32-desc.c: Likewise.
758 * m32c-dis.c: Likewise.
759 * m32c-desc.c: Likewise.
760 * m32r-dis.c: Likewise.
761 * m32r-desc.c: Likewise.
762 * mep-dis.c: Likewise.
763 * mep-desc.c: Likewise.
764 * mt-dis.c: Likewise.
765 * mt-desc.c: Likewise.
766 * or1k-dis.c: Likewise.
767 * or1k-desc.c: Likewise.
768 * xc16x-dis.c: Likewise.
769 * xc16x-desc.c: Likewise.
770 * xstormy16-dis.c: Likewise.
771 * xstormy16-desc.c: Likewise.
772
4ee4189f
NC		 7732020-06-03 Nick Clifton <nickc@redhat.com>
774
775 * po/sr.po: Updated Serbian translation.
776
44730156
NC		 7772020-06-03 Nelson Chu <nelson.chu@sifive.com>
778
779 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
780 (riscv_get_priv_spec_class): Likewise.
781
3c3d0376
AM		 7822020-06-01 Alan Modra <amodra@gmail.com>
783
784 * bpf-desc.c: Regenerate.
785
78c1c354
JM		 7862020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
787 David Faust <david.faust@oracle.com>
788
789 * bpf-desc.c: Regenerate.
790 * bpf-opc.h: Likewise.
791 * bpf-opc.c: Likewise.
792 * bpf-dis.c: Likewise.
793
efcf5fb5
AM		 7942020-05-28 Alan Modra <amodra@gmail.com>
795
796 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
797 values.
798
ab382d64
AM		 7992020-05-28 Alan Modra <amodra@gmail.com>
800
801 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
802 immediates.
803 (print_insn_ns32k): Revert last change.
804
151f5de4
NC		 8052020-05-28 Nick Clifton <nickc@redhat.com>
806
807 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
808 static.
809
25e1eca8
SL		 8102020-05-26 Sandra Loosemore <sandra@codesourcery.com>
811
812 Fix extraction of signed constants in nios2 disassembler (again).
813
814 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
815 extractions of signed fields.
816
57b17940
SSF		 8172020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
818
819 * s390-opc.txt: Relocate vector load/store instructions with
820 additional alignment parameter and change architecture level
821 constraint from z14 to z13.
822
d96bf37b
AM		 8232020-05-21 Alan Modra <amodra@gmail.com>
824
825 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
826 * sparc-dis.c: Likewise.
827 * tic4x-dis.c: Likewise.
828 * xtensa-dis.c: Likewise.
829 * bpf-desc.c: Regenerate.
830 * epiphany-desc.c: Regenerate.
831 * fr30-desc.c: Regenerate.
832 * frv-desc.c: Regenerate.
833 * ip2k-desc.c: Regenerate.
834 * iq2000-desc.c: Regenerate.
835 * lm32-desc.c: Regenerate.
836 * m32c-desc.c: Regenerate.
837 * m32r-desc.c: Regenerate.
838 * mep-asm.c: Regenerate.
839 * mep-desc.c: Regenerate.
840 * mt-desc.c: Regenerate.
841 * or1k-desc.c: Regenerate.
842 * xc16x-desc.c: Regenerate.
843 * xstormy16-desc.c: Regenerate.
844
8f595e9b
NC		 8452020-05-20 Nelson Chu <nelson.chu@sifive.com>
846
847 * riscv-opc.c (riscv_ext_version_table): The table used to store
848 all information about the supported spec and the corresponding ISA
849 versions. Currently, only Zicsr is supported to verify the
850 correctness of Z sub extension settings. Others will be supported
851 in the future patches.
852 (struct isa_spec_t, isa_specs): List for all supported ISA spec
853 classes and the corresponding strings.
854 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
855 spec class by giving a ISA spec string.
856 * riscv-opc.c (struct priv_spec_t): New structure.
857 (struct priv_spec_t priv_specs): List for all supported privilege spec
858 classes and the corresponding strings.
859 (riscv_get_priv_spec_class): New function. Get the corresponding
860 privilege spec class by giving a spec string.
861 (riscv_get_priv_spec_name): New function. Get the corresponding
862 privilege spec string by giving a CSR version class.
863 * riscv-dis.c: Updated since DECLARE_CSR is changed.
864 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
865 according to the chosen version. Build a hash table riscv_csr_hash to
866 store the valid CSR for the chosen pirv verison. Dump the direct
867 CSR address rather than it's name if it is invalid.
868 (parse_riscv_dis_option_without_args): New function. Parse the options
869 without arguments.
870 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
871 parse the options without arguments first, and then handle the options
872 with arguments. Add the new option -Mpriv-spec, which has argument.
873 * riscv-dis.c (print_riscv_disassembler_options): Add description
874 about the new OBJDUMP option.
875
3d205eb4
PB		 8762020-05-19 Peter Bergner <bergner@linux.ibm.com>
877
878 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
879 WC values on POWER10 sync, dcbf and wait instructions.
880 (insert_pl, extract_pl): New functions.
881 (L2OPT, LS, WC): Use insert_ls and extract_ls.
882 (LS3): New , 3-bit L for sync.
883 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
884 (SC2, PL): New, 2-bit SC and PL for sync and wait.
885 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
886 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
887 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
888 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
889 <wait>: Enable PL operand on POWER10.
890 <dcbf>: Enable L3OPT operand on POWER10.
891 <sync>: Enable SC2 operand on POWER10.
892
a501eb44
SH		 8932020-05-19 Stafford Horne <shorne@gmail.com>
894
895 PR 25184
896 * or1k-asm.c: Regenerate.
897 * or1k-desc.c: Regenerate.
898 * or1k-desc.h: Regenerate.
899 * or1k-dis.c: Regenerate.
900 * or1k-ibld.c: Regenerate.
901 * or1k-opc.c: Regenerate.
902 * or1k-opc.h: Regenerate.
903 * or1k-opinst.c: Regenerate.
904
3b646889
AM		 9052020-05-11 Alan Modra <amodra@gmail.com>
906
907 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
908 xsmaxcqp, xsmincqp.
909
9cc4ce88
AM		 9102020-05-11 Alan Modra <amodra@gmail.com>
911
912 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
913 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
914
5d57bc3f
AM		 9152020-05-11 Alan Modra <amodra@gmail.com>
916
917 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
918
66ef5847
AM		 9192020-05-11 Alan Modra <amodra@gmail.com>
920
921 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
922 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
923
4f3e9537
PB		 9242020-05-11 Peter Bergner <bergner@linux.ibm.com>
925
926 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
927 mnemonics.
928
ec40e91c
AM		 9292020-05-11 Alan Modra <amodra@gmail.com>
930
931 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
932 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
933 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
934 (prefix_opcodes): Add xxeval.
935
d7e97a76
AM		 9362020-05-11 Alan Modra <amodra@gmail.com>
937
938 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
939 xxgenpcvwm, xxgenpcvdm.
940
fdefed7c
AM		 9412020-05-11 Alan Modra <amodra@gmail.com>
942
943 * ppc-opc.c (MP, VXVAM_MASK): Define.
944 (VXVAPS_MASK): Use VXVA_MASK.
945 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
946 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
947 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
948 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
949
aa3c112f
AM		 9502020-05-11 Alan Modra <amodra@gmail.com>
951 Peter Bergner <bergner@linux.ibm.com>
952
953 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
954 New functions.
955 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
956 YMSK2, XA6a, XA6ap, XB6a entries.
957 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
958 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
959 (PPCVSX4): Define.
960 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
961 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
962 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
963 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
964 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
965 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
966 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
967 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
968 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
969 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
970 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
971 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
972 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
973 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
974
6edbfd3b
AM		 9752020-05-11 Alan Modra <amodra@gmail.com>
976
977 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
978 (insert_xts, extract_xts): New functions.
979 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
980 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
981 (VXRC_MASK, VXSH_MASK): Define.
982 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
983 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
984 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
985 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
986 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
987 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
988 xxblendvh, xxblendvw, xxblendvd, xxpermx.
989
c7d7aea2
AM		 9902020-05-11 Alan Modra <amodra@gmail.com>
991
992 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
993 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
994 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
995 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
996 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
997
94ba9882
AM		 9982020-05-11 Alan Modra <amodra@gmail.com>
999
1000 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1001 (XTP, DQXP, DQXP_MASK): Define.
1002 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1003 (prefix_opcodes): Add plxvp and pstxvp.
1004
f4791f1a
AM		 10052020-05-11 Alan Modra <amodra@gmail.com>
1006
1007 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1008 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1009 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1010
3ff0a5ba
PB		 10112020-05-11 Peter Bergner <bergner@linux.ibm.com>
1012
1013 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1014
afef4fe9
PB		 10152020-05-11 Peter Bergner <bergner@linux.ibm.com>
1016
1017 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1018 (L1OPT): Define.
1019 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1020
1224c05d
PB		 10212020-05-11 Peter Bergner <bergner@linux.ibm.com>
1022
1023 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1024
6bbb0c05
AM		 10252020-05-11 Alan Modra <amodra@gmail.com>
1026
1027 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1028
7c1f4227
AM		 10292020-05-11 Alan Modra <amodra@gmail.com>
1030
1031 * ppc-dis.c (ppc_opts): Add "power10" entry.
1032 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1033 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1034
73199c2b
NC		 10352020-05-11 Nick Clifton <nickc@redhat.com>
1036
1037 * po/fr.po: Updated French translation.
1038
09c1e68a
AC		 10392020-04-30 Alex Coplan <alex.coplan@arm.com>
1040
1041 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1042 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1043 (operand_general_constraint_met_p): validate
1044 AARCH64_OPND_UNDEFINED.
1045 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1046 for FLD_imm16_2.
1047 * aarch64-asm-2.c: Regenerated.
1048 * aarch64-dis-2.c: Regenerated.
1049 * aarch64-opc-2.c: Regenerated.
1050
9654d51a
NC		 10512020-04-29 Nick Clifton <nickc@redhat.com>
1052
1053 PR 22699
1054 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1055 and SETRC insns.
1056
c2e71e57
NC		 10572020-04-29 Nick Clifton <nickc@redhat.com>
1058
1059 * po/sv.po: Updated Swedish translation.
1060
5c936ef5
NC		 10612020-04-29 Nick Clifton <nickc@redhat.com>
1062
1063 PR 22699
1064 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1065 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1066 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1067 IMM0_8U case.
1068
bb2a1453
AS		 10692020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1070
1071 PR 25848
1072 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1073 cmpi only on m68020up and cpu32.
1074
c2e5c986
SD		 10752020-04-20 Sudakshina Das <sudi.das@arm.com>
1076
1077 * aarch64-asm.c (aarch64_ins_none): New.
1078 * aarch64-asm.h (ins_none): New declaration.
1079 * aarch64-dis.c (aarch64_ext_none): New.
1080 * aarch64-dis.h (ext_none): New declaration.
1081 * aarch64-opc.c (aarch64_print_operand): Update case for
1082 AARCH64_OPND_BARRIER_PSB.
1083 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1084 (AARCH64_OPERANDS): Update inserter/extracter for
1085 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1086 * aarch64-asm-2.c: Regenerated.
1087 * aarch64-dis-2.c: Regenerated.
1088 * aarch64-opc-2.c: Regenerated.
1089
8a6e1d1d
SD		 10902020-04-20 Sudakshina Das <sudi.das@arm.com>
1091
1092 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1093 (aarch64_feature_ras, RAS): Likewise.
1094 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1095 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1096 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1097 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1098 * aarch64-asm-2.c: Regenerated.
1099 * aarch64-dis-2.c: Regenerated.
1100 * aarch64-opc-2.c: Regenerated.
1101
e409955d
FS		 11022020-04-17 Fredrik Strupe <fredrik@strupe.net>
1103
1104 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1105 (print_insn_neon): Support disassembly of conditional
1106 instructions.
1107
c54a9b56
DF		 11082020-02-16 David Faust <david.faust@oracle.com>
1109
1110 * bpf-desc.c: Regenerate.
1111 * bpf-desc.h: Likewise.
1112 * bpf-opc.c: Regenerate.
1113 * bpf-opc.h: Likewise.
1114
bb651e8b
CL		 11152020-04-07 Lili Cui <lili.cui@intel.com>
1116
1117 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1118 (prefix_table): New instructions (see prefixes above).
1119 (rm_table): Likewise
1120 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1121 CPU_ANY_TSXLDTRK_FLAGS.
1122 (cpu_flags): Add CpuTSXLDTRK.
1123 * i386-opc.h (enum): Add CpuTSXLDTRK.
1124 (i386_cpu_flags): Add cputsxldtrk.
1125 * i386-opc.tbl: Add XSUSPLDTRK insns.
1126 * i386-init.h: Regenerate.
1127 * i386-tbl.h: Likewise.
1128
4b27d27c
L		 11292020-04-02 Lili Cui <lili.cui@intel.com>
1130
1131 * i386-dis.c (prefix_table): New instructions serialize.
1132 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1133 CPU_ANY_SERIALIZE_FLAGS.
1134 (cpu_flags): Add CpuSERIALIZE.
1135 * i386-opc.h (enum): Add CpuSERIALIZE.
1136 (i386_cpu_flags): Add cpuserialize.
1137 * i386-opc.tbl: Add SERIALIZE insns.
1138 * i386-init.h: Regenerate.
1139 * i386-tbl.h: Likewise.
1140
832a5807
AM		 11412020-03-26 Alan Modra <amodra@gmail.com>
1142
1143 * disassemble.h (opcodes_assert): Declare.
1144 (OPCODES_ASSERT): Define.
1145 * disassemble.c: Don't include assert.h. Include opintl.h.
1146 (opcodes_assert): New function.
1147 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1148 (bfd_h8_disassemble): Reduce size of data array. Correctly
1149 calculate maxlen. Omit insn decoding when insn length exceeds
1150 maxlen. Exit from nibble loop when looking for E, before
1151 accessing next data byte. Move processing of E outside loop.
1152 Replace tests of maxlen in loop with assertions.
1153
4c4addbe
AM		 11542020-03-26 Alan Modra <amodra@gmail.com>
1155
1156 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1157
a18cd0ca
AM		 11582020-03-25 Alan Modra <amodra@gmail.com>
1159
1160 * z80-dis.c (suffix): Init mybuf.
1161
57cb32b3
AM		 11622020-03-22 Alan Modra <amodra@gmail.com>
1163
1164 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1165 successflly read from section.
1166
beea5cc1
AM		 11672020-03-22 Alan Modra <amodra@gmail.com>
1168
1169 * arc-dis.c (find_format): Use ISO C string concatenation rather
1170 than line continuation within a string. Don't access needs_limm
1171 before testing opcode != NULL.
1172
03704c77
AM		 11732020-03-22 Alan Modra <amodra@gmail.com>
1174
1175 * ns32k-dis.c (print_insn_arg): Update comment.
1176 (print_insn_ns32k): Reduce size of index_offset array, and
1177 initialize, passing -1 to print_insn_arg for args that are not
1178 an index. Don't exit arg loop early. Abort on bad arg number.
1179
d1023b5d
AM		 11802020-03-22 Alan Modra <amodra@gmail.com>
1181
1182 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1183 * s12z-opc.c: Formatting.
1184 (operands_f): Return an int.
1185 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1186 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1187 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1188 (exg_sex_discrim): Likewise.
1189 (create_immediate_operand, create_bitfield_operand),
1190 (create_register_operand_with_size, create_register_all_operand),
1191 (create_register_all16_operand, create_simple_memory_operand),
1192 (create_memory_operand, create_memory_auto_operand): Don't
1193 segfault on malloc failure.
1194 (z_ext24_decode): Return an int status, negative on fail, zero
1195 on success.
1196 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1197 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1198 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1199 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1200 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1201 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1202 (loop_primitive_decode, shift_decode, psh_pul_decode),
1203 (bit_field_decode): Similarly.
1204 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1205 to return value, update callers.
1206 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1207 Don't segfault on NULL operand.
1208 (decode_operation): Return OP_INVALID on first fail.
1209 (decode_s12z): Check all reads, returning -1 on fail.
1210
340f3ac8
AM		 12112020-03-20 Alan Modra <amodra@gmail.com>
1212
1213 * metag-dis.c (print_insn_metag): Don't ignore status from
1214 read_memory_func.
1215
fe90ae8a
AM		 12162020-03-20 Alan Modra <amodra@gmail.com>
1217
1218 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1219 Initialize parts of buffer not written when handling a possible
1220 2-byte insn at end of section. Don't attempt decoding of such
1221 an insn by the 4-byte machinery.
1222
833d919c
AM		 12232020-03-20 Alan Modra <amodra@gmail.com>
1224
1225 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1226 partially filled buffer. Prevent lookup of 4-byte insns when
1227 only VLE 2-byte insns are possible due to section size. Print
1228 ".word" rather than ".long" for 2-byte leftovers.
1229
327ef784
NC		 12302020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1231
1232 PR 25641
1233 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1234
1673df32
JB		 12352020-03-13 Jan Beulich <jbeulich@suse.com>
1236
1237 * i386-dis.c (X86_64_0D): Rename to ...
1238 (X86_64_0E): ... this.
1239
384f3689
L		 12402020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1241
1242 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1243 * Makefile.in: Regenerated.
1244
865e2027
JB		 12452020-03-09 Jan Beulich <jbeulich@suse.com>
1246
1247 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1248 3-operand pseudos.
1249 * i386-tbl.h: Re-generate.
1250
2f13234b
JB		 12512020-03-09 Jan Beulich <jbeulich@suse.com>
1252
1253 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1254 vprot*, vpsha*, and vpshl*.
1255 * i386-tbl.h: Re-generate.
1256
3fabc179
JB		 12572020-03-09 Jan Beulich <jbeulich@suse.com>
1258
1259 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1260 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1261 * i386-tbl.h: Re-generate.
1262
3677e4c1
JB		 12632020-03-09 Jan Beulich <jbeulich@suse.com>
1264
1265 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1266 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1267 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1268 * i386-tbl.h: Re-generate.
1269
4c4898e8
JB		 12702020-03-09 Jan Beulich <jbeulich@suse.com>
1271
1272 * i386-gen.c (struct template_arg, struct template_instance,
1273 struct template_param, struct template, templates,
1274 parse_template, expand_templates): New.
1275 (process_i386_opcodes): Various local variables moved to
1276 expand_templates. Call parse_template and expand_templates.
1277 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1278 * i386-tbl.h: Re-generate.
1279
bc49bfd8
JB		 12802020-03-06 Jan Beulich <jbeulich@suse.com>
1281
1282 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1283 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1284 register and memory source templates. Replace VexW= by VexW*
1285 where applicable.
1286 * i386-tbl.h: Re-generate.
1287
4873e243
JB		 12882020-03-06 Jan Beulich <jbeulich@suse.com>
1289
1290 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1291 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1292 * i386-tbl.h: Re-generate.
1293
672a349b
JB		 12942020-03-06 Jan Beulich <jbeulich@suse.com>
1295
1296 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1297 * i386-tbl.h: Re-generate.
1298
4ed21b58
JB		 12992020-03-06 Jan Beulich <jbeulich@suse.com>
1300
1301 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1302 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1303 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1304 VexW0 on SSE2AVX variants.
1305 (vmovq): Drop NoRex64 from XMM/XMM variants.
1306 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1307 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1308 applicable use VexW0.
1309 * i386-tbl.h: Re-generate.
1310
643bb870
JB		 13112020-03-06 Jan Beulich <jbeulich@suse.com>
1312
1313 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1314 * i386-opc.h (Rex64): Delete.
1315 (struct i386_opcode_modifier): Remove rex64 field.
1316 * i386-opc.tbl (crc32): Drop Rex64.
1317 Replace Rex64 with Size64 everywhere else.
1318 * i386-tbl.h: Re-generate.
1319
a23b33b3
JB		 13202020-03-06 Jan Beulich <jbeulich@suse.com>
1321
1322 * i386-dis.c (OP_E_memory): Exclude recording of used address
1323 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1324 addressed memory operands for MPX insns.
1325
a0497384
JB		 13262020-03-06 Jan Beulich <jbeulich@suse.com>
1327
1328 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1329 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1330 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1331 (ptwrite): Split into non-64-bit and 64-bit forms.
1332 * i386-tbl.h: Re-generate.
1333
b630c145
JB		 13342020-03-06 Jan Beulich <jbeulich@suse.com>
1335
1336 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1337 template.
1338 * i386-tbl.h: Re-generate.
1339
a847e322
JB		 13402020-03-04 Jan Beulich <jbeulich@suse.com>
1341
1342 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1343 (prefix_table): Move vmmcall here. Add vmgexit.
1344 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1345 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1346 (cpu_flags): Add CpuSEV_ES entry.
1347 * i386-opc.h (CpuSEV_ES): New.
1348 (union i386_cpu_flags): Add cpusev_es field.
1349 * i386-opc.tbl (vmgexit): New.
1350 * i386-init.h, i386-tbl.h: Re-generate.
1351
3cd7f3e3
L		 13522020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1353
1354 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1355 with MnemonicSize.
1356 * i386-opc.h (IGNORESIZE): New.
1357 (DEFAULTSIZE): Likewise.
1358 (IgnoreSize): Removed.
1359 (DefaultSize): Likewise.
1360 (MnemonicSize): New.
1361 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1362 mnemonicsize.
1363 * i386-opc.tbl (IgnoreSize): New.
1364 (DefaultSize): Likewise.
1365 * i386-tbl.h: Regenerated.
1366
b8ba1385
SB		 13672020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1368
1369 PR 25627
1370 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1371 instructions.
1372
10d97a0f
L		 13732020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1374
1375 PR gas/25622
1376 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1377 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1378 * i386-tbl.h: Regenerated.
1379
dc1e8a47
AM		 13802020-02-26 Alan Modra <amodra@gmail.com>
1381
1382 * aarch64-asm.c: Indent labels correctly.
1383 * aarch64-dis.c: Likewise.
1384 * aarch64-gen.c: Likewise.
1385 * aarch64-opc.c: Likewise.
1386 * alpha-dis.c: Likewise.
1387 * i386-dis.c: Likewise.
1388 * nds32-asm.c: Likewise.
1389 * nfp-dis.c: Likewise.
1390 * visium-dis.c: Likewise.
1391
265b4673
CZ		 13922020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1393
1394 * arc-regs.h (int_vector_base): Make it available for all ARC
1395 CPUs.
1396
bd0cf5a6
NC		 13972020-02-20 Nelson Chu <nelson.chu@sifive.com>
1398
1399 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1400 changed.
1401
fa164239
JW		 14022020-02-19 Nelson Chu <nelson.chu@sifive.com>
1403
1404 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1405 c.mv/c.li if rs1 is zero.
1406
272a84b1
L		 14072020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1408
1409 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1410 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1411 CPU_POPCNT_FLAGS.
1412 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1413 * i386-opc.h (CpuABM): Removed.
1414 (CpuPOPCNT): New.
1415 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1416 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1417 popcnt. Remove CpuABM from lzcnt.
1418 * i386-init.h: Regenerated.
1419 * i386-tbl.h: Likewise.
1420
1f730c46
JB		 14212020-02-17 Jan Beulich <jbeulich@suse.com>
1422
1423 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1424 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1425 VexW1 instead of open-coding them.
1426 * i386-tbl.h: Re-generate.
1427
c8f8eebc
JB		 14282020-02-17 Jan Beulich <jbeulich@suse.com>
1429
1430 * i386-opc.tbl (AddrPrefixOpReg): Define.
1431 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1432 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1433 templates. Drop NoRex64.
1434 * i386-tbl.h: Re-generate.
1435
b9915cbc
JB		 14362020-02-17 Jan Beulich <jbeulich@suse.com>
1437
1438 PR gas/6518
1439 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1440 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1441 into Intel syntax instance (with Unpsecified) and AT&T one
1442 (without).
1443 (vcvtneps2bf16): Likewise, along with folding the two so far
1444 separate ones.
1445 * i386-tbl.h: Re-generate.
1446
ce504911
L		 14472020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1448
1449 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1450 CPU_ANY_SSE4A_FLAGS.
1451
dabec65d
AM		 14522020-02-17 Alan Modra <amodra@gmail.com>
1453
1454 * i386-gen.c (cpu_flag_init): Correct last change.
1455
af5c13b0
L		 14562020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1457
1458 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1459 CPU_ANY_SSE4_FLAGS.
1460
6867aac0
L		 14612020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1462
1463 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1464 (movzx): Likewise.
1465
65fca059
JB		 14662020-02-14 Jan Beulich <jbeulich@suse.com>
1467
1468 PR gas/25438
1469 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1470 destination for Cpu64-only variant.
1471 (movzx): Fold patterns.
1472 * i386-tbl.h: Re-generate.
1473
7deea9aa
JB		 14742020-02-13 Jan Beulich <jbeulich@suse.com>
1475
1476 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1477 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1478 CPU_ANY_SSE4_FLAGS entry.
1479 * i386-init.h: Re-generate.
1480
6c0946d0
JB		 14812020-02-12 Jan Beulich <jbeulich@suse.com>
1482
1483 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1484 with Unspecified, making the present one AT&T syntax only.
1485 * i386-tbl.h: Re-generate.
1486
ddb56fe6
JB		 14872020-02-12 Jan Beulich <jbeulich@suse.com>
1488
1489 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1490 * i386-tbl.h: Re-generate.
1491
5990e377
JB		 14922020-02-12 Jan Beulich <jbeulich@suse.com>
1493
1494 PR gas/24546
1495 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1496 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1497 Amd64 and Intel64 templates.
1498 (call, jmp): Likewise for far indirect variants. Dro
1499 Unspecified.
1500 * i386-tbl.h: Re-generate.
1501
50128d0c
JB		 15022020-02-11 Jan Beulich <jbeulich@suse.com>
1503
1504 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1505 * i386-opc.h (ShortForm): Delete.
1506 (struct i386_opcode_modifier): Remove shortform field.
1507 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1508 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1509 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1510 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1511 Drop ShortForm.
1512 * i386-tbl.h: Re-generate.
1513
1e05b5c4
JB		 15142020-02-11 Jan Beulich <jbeulich@suse.com>
1515
1516 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1517 fucompi): Drop ShortForm from operand-less templates.
1518 * i386-tbl.h: Re-generate.
1519
2f5dd314
AM		 15202020-02-11 Alan Modra <amodra@gmail.com>
1521
1522 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1523 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1524 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1525 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1526 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1527
5aae9ae9
MM		 15282020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1529
1530 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1531 (cde_opcodes): Add VCX* instructions.
1532
4934a27c
MM		 15332020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1534 Matthew Malcomson <matthew.malcomson@arm.com>
1535
1536 * arm-dis.c (struct cdeopcode32): New.
1537 (CDE_OPCODE): New macro.
1538 (cde_opcodes): New disassembly table.
1539 (regnames): New option to table.
1540 (cde_coprocs): New global variable.
1541 (print_insn_cde): New
1542 (print_insn_thumb32): Use print_insn_cde.
1543 (parse_arm_disassembler_options): Parse coprocN args.
1544
4b5aaf5f
L		 15452020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1546
1547 PR gas/25516
1548 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1549 with ISA64.
1550 * i386-opc.h (AMD64): Removed.
1551 (Intel64): Likewose.
1552 (AMD64): New.
1553 (INTEL64): Likewise.
1554 (INTEL64ONLY): Likewise.
1555 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1556 * i386-opc.tbl (Amd64): New.
1557 (Intel64): Likewise.
1558 (Intel64Only): Likewise.
1559 Replace AMD64 with Amd64. Update sysenter/sysenter with
1560 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1561 * i386-tbl.h: Regenerated.
1562
9fc0b501
SB		 15632020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1564
1565 PR 25469
1566 * z80-dis.c: Add support for GBZ80 opcodes.
1567
c5d7be0c
AM		 15682020-02-04 Alan Modra <amodra@gmail.com>
1569
1570 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1571
44e4546f
AM		 15722020-02-03 Alan Modra <amodra@gmail.com>
1573
1574 * m32c-ibld.c: Regenerate.
1575
b2b1453a
AM		 15762020-02-01 Alan Modra <amodra@gmail.com>
1577
1578 * frv-ibld.c: Regenerate.
1579
4102be5c
JB		 15802020-01-31 Jan Beulich <jbeulich@suse.com>
1581
1582 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1583 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1584 (OP_E_memory): Replace xmm_mdq_mode case label by
1585 vex_scalar_w_dq_mode one.
1586 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1587
825bd36c
JB		 15882020-01-31 Jan Beulich <jbeulich@suse.com>
1589
1590 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1591 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1592 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1593 (intel_operand_size): Drop vex_w_dq_mode case label.
1594
c3036ed0
RS		 15952020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1596
1597 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1598 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1599
0c115f84
AM		 16002020-01-30 Alan Modra <amodra@gmail.com>
1601
1602 * m32c-ibld.c: Regenerate.
1603
bd434cc4
JM		 16042020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1605
1606 * bpf-opc.c: Regenerate.
1607
aeab2b26
JB		 16082020-01-30 Jan Beulich <jbeulich@suse.com>
1609
1610 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1611 (dis386): Use them to replace C2/C3 table entries.
1612 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1613 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1614 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1615 * i386-tbl.h: Re-generate.
1616
62b3f548
JB		 16172020-01-30 Jan Beulich <jbeulich@suse.com>
1618
1619 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1620 forms.
1621 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1622 DefaultSize.
1623 * i386-tbl.h: Re-generate.
1624
1bd8ae10
AM		 16252020-01-30 Alan Modra <amodra@gmail.com>
1626
1627 * tic4x-dis.c (tic4x_dp): Make unsigned.
1628
bc31405e
L		 16292020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1630 Jan Beulich <jbeulich@suse.com>
1631
1632 PR binutils/25445
1633 * i386-dis.c (MOVSXD_Fixup): New function.
1634 (movsxd_mode): New enum.
1635 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1636 (intel_operand_size): Handle movsxd_mode.
1637 (OP_E_register): Likewise.
1638 (OP_G): Likewise.
1639 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1640 register on movsxd. Add movsxd with 16-bit destination register
1641 for AMD64 and Intel64 ISAs.
1642 * i386-tbl.h: Regenerated.
1643
7568c93b
TC		 16442020-01-27 Tamar Christina <tamar.christina@arm.com>
1645
1646 PR 25403
1647 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1648 * aarch64-asm-2.c: Regenerate
1649 * aarch64-dis-2.c: Likewise.
1650 * aarch64-opc-2.c: Likewise.
1651
c006a730
JB		 16522020-01-21 Jan Beulich <jbeulich@suse.com>
1653
1654 * i386-opc.tbl (sysret): Drop DefaultSize.
1655 * i386-tbl.h: Re-generate.
1656
c906a69a
JB		 16572020-01-21 Jan Beulich <jbeulich@suse.com>
1658
1659 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1660 Dword.
1661 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1662 * i386-tbl.h: Re-generate.
1663
26916852
NC		 16642020-01-20 Nick Clifton <nickc@redhat.com>
1665
1666 * po/de.po: Updated German translation.
1667 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1668 * po/uk.po: Updated Ukranian translation.
1669
4d6cbb64
AM		 16702020-01-20 Alan Modra <amodra@gmail.com>
1671
1672 * hppa-dis.c (fput_const): Remove useless cast.
1673
2bddb71a
AM		 16742020-01-20 Alan Modra <amodra@gmail.com>
1675
1676 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1677
1b1bb2c6
NC		 16782020-01-18 Nick Clifton <nickc@redhat.com>
1679
1680 * configure: Regenerate.
1681 * po/opcodes.pot: Regenerate.
1682
ae774686
NC		 16832020-01-18 Nick Clifton <nickc@redhat.com>
1684
1685 Binutils 2.34 branch created.
1686
07f1f3aa
CB		 16872020-01-17 Christian Biesinger <cbiesinger@google.com>
1688
1689 * opintl.h: Fix spelling error (seperate).
1690
42e04b36
L		 16912020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1692
1693 * i386-opc.tbl: Add {vex} pseudo prefix.
1694 * i386-tbl.h: Regenerated.
1695
2da2eaf4
AV		 16962020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1697
1698 PR 25376
1699 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1700 (neon_opcodes): Likewise.
1701 (select_arm_features): Make sure we enable MVE bits when selecting
1702 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1703 any architecture.
1704
d0849eed
JB		 17052020-01-16 Jan Beulich <jbeulich@suse.com>
1706
1707 * i386-opc.tbl: Drop stale comment from XOP section.
1708
9cf70a44
JB		 17092020-01-16 Jan Beulich <jbeulich@suse.com>
1710
1711 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1712 (extractps): Add VexWIG to SSE2AVX forms.
1713 * i386-tbl.h: Re-generate.
1714
4814632e
JB		 17152020-01-16 Jan Beulich <jbeulich@suse.com>
1716
1717 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1718 Size64 from and use VexW1 on SSE2AVX forms.
1719 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1720 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1721 * i386-tbl.h: Re-generate.
1722
aad09917
AM		 17232020-01-15 Alan Modra <amodra@gmail.com>
1724
1725 * tic4x-dis.c (tic4x_version): Make unsigned long.
1726 (optab, optab_special, registernames): New file scope vars.
1727 (tic4x_print_register): Set up registernames rather than
1728 malloc'd registertable.
1729 (tic4x_disassemble): Delete optable and optable_special. Use
1730 optab and optab_special instead. Throw away old optab,
1731 optab_special and registernames when info->mach changes.
1732
7a6bf3be
SB		 17332020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1734
1735 PR 25377
1736 * z80-dis.c (suffix): Use .db instruction to generate double
1737 prefix.
1738
ca1eaac0
AM		 17392020-01-14 Alan Modra <amodra@gmail.com>
1740
1741 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1742 values to unsigned before shifting.
1743
1d67fe3b
TT		 17442020-01-13 Thomas Troeger <tstroege@gmx.de>
1745
1746 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1747 flow instructions.
1748 (print_insn_thumb16, print_insn_thumb32): Likewise.
1749 (print_insn): Initialize the insn info.
1750 * i386-dis.c (print_insn): Initialize the insn info fields, and
1751 detect jumps.
1752
5e4f7e05
CZ		 17532012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1754
1755 * arc-opc.c (C_NE): Make it required.
1756
b9fe6b8a
CZ		 17572012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1758
1759 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1760 reserved register name.
1761
90dee485
AM		 17622020-01-13 Alan Modra <amodra@gmail.com>
1763
1764 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1765 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1766
febda64f
AM		 17672020-01-13 Alan Modra <amodra@gmail.com>
1768
1769 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1770 result of wasm_read_leb128 in a uint64_t and check that bits
1771 are not lost when copying to other locals. Use uint32_t for
1772 most locals. Use PRId64 when printing int64_t.
1773
df08b588
AM		 17742020-01-13 Alan Modra <amodra@gmail.com>
1775
1776 * score-dis.c: Formatting.
1777 * score7-dis.c: Formatting.
1778
b2c759ce
AM		 17792020-01-13 Alan Modra <amodra@gmail.com>
1780
1781 * score-dis.c (print_insn_score48): Use unsigned variables for
1782 unsigned values. Don't left shift negative values.
1783 (print_insn_score32): Likewise.
1784 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1785
5496abe1
AM		 17862020-01-13 Alan Modra <amodra@gmail.com>
1787
1788 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1789
202e762b
AM		 17902020-01-13 Alan Modra <amodra@gmail.com>
1791
1792 * fr30-ibld.c: Regenerate.
1793
7ef412cf
AM		 17942020-01-13 Alan Modra <amodra@gmail.com>
1795
1796 * xgate-dis.c (print_insn): Don't left shift signed value.
1797 (ripBits): Formatting, use 1u.
1798
7f578b95
AM		 17992020-01-10 Alan Modra <amodra@gmail.com>
1800
1801 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1802 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1803
441af85b
AM		 18042020-01-10 Alan Modra <amodra@gmail.com>
1805
1806 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1807 and XRREG value earlier to avoid a shift with negative exponent.
1808 * m10200-dis.c (disassemble): Similarly.
1809
bce58db4
NC		 18102020-01-09 Nick Clifton <nickc@redhat.com>
1811
1812 PR 25224
1813 * z80-dis.c (ld_ii_ii): Use correct cast.
1814
40c75bc8
SB		 18152020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1816
1817 PR 25224
1818 * z80-dis.c (ld_ii_ii): Use character constant when checking
1819 opcode byte value.
1820
d835a58b
JB		 18212020-01-09 Jan Beulich <jbeulich@suse.com>
1822
1823 * i386-dis.c (SEP_Fixup): New.
1824 (SEP): Define.
1825 (dis386_twobyte): Use it for sysenter/sysexit.
1826 (enum x86_64_isa): Change amd64 enumerator to value 1.
1827 (OP_J): Compare isa64 against intel64 instead of amd64.
1828 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1829 forms.
1830 * i386-tbl.h: Re-generate.
1831
030a2e78
AM		 18322020-01-08 Alan Modra <amodra@gmail.com>
1833
1834 * z8k-dis.c: Include libiberty.h
1835 (instr_data_s): Make max_fetched unsigned.
1836 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1837 Don't exceed byte_info bounds.
1838 (output_instr): Make num_bytes unsigned.
1839 (unpack_instr): Likewise for nibl_count and loop.
1840 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1841 idx unsigned.
1842 * z8k-opc.h: Regenerate.
1843
bb82aefe
SV		 18442020-01-07 Shahab Vahedi <shahab@synopsys.com>
1845
1846 * arc-tbl.h (llock): Use 'LLOCK' as class.
1847 (llockd): Likewise.
1848 (scond): Use 'SCOND' as class.
1849 (scondd): Likewise.
1850 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1851 (scondd): Likewise.
1852
cc6aa1a6
AM		 18532020-01-06 Alan Modra <amodra@gmail.com>
1854
1855 * m32c-ibld.c: Regenerate.
1856
660e62b1
AM		 18572020-01-06 Alan Modra <amodra@gmail.com>
1858
1859 PR 25344
1860 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1861 Peek at next byte to prevent recursion on repeated prefix bytes.
1862 Ensure uninitialised "mybuf" is not accessed.
1863 (print_insn_z80): Don't zero n_fetch and n_used here,..
1864 (print_insn_z80_buf): ..do it here instead.
1865
c9ae58fe
AM		 18662020-01-04 Alan Modra <amodra@gmail.com>
1867
1868 * m32r-ibld.c: Regenerate.
1869
5f57d4ec
AM		 18702020-01-04 Alan Modra <amodra@gmail.com>
1871
1872 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1873
2c5c1196
AM		 18742020-01-04 Alan Modra <amodra@gmail.com>
1875
1876 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1877
2e98c6c5
AM		 18782020-01-04 Alan Modra <amodra@gmail.com>
1879
1880 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1881
567dfba2
JB		 18822020-01-03 Jan Beulich <jbeulich@suse.com>
1883
5437a02a
JB		 1884 * aarch64-tbl.h (aarch64_opcode_table): Use
1885 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1886
18872020-01-03 Jan Beulich <jbeulich@suse.com>
1888
1889 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1890 forms of SUDOT and USDOT.
1891
8c45011a
JB		 18922020-01-03 Jan Beulich <jbeulich@suse.com>
1893
5437a02a 1894 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1895 uzip{1,2}.
1896 * opcodes/aarch64-dis-2.c: Re-generate.
1897
f4950f76
JB		 18982020-01-03 Jan Beulich <jbeulich@suse.com>
1899
5437a02a 1900 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1901 FMMLA encoding.
1902 * opcodes/aarch64-dis-2.c: Re-generate.
1903
6655dba2
SB		 19042020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1905
1906 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1907
b14ce8bf
AM		 19082020-01-01 Alan Modra <amodra@gmail.com>
1909
1910 Update year range in copyright notice of all files.
1911
0b114740 1912For older changes see ChangeLog-2019
3499769a 1913\f
0b114740 1914Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1915
1916Copying and distribution of this file, with or without modification,
1917are permitted in any medium without royalty provided the copyright
1918notice and this notice are preserved.
1919
1920Local Variables:
1921mode: change-log
1922left-margin: 8
1923fill-column: 74
1924version-control: never
1925End:
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