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b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
da4339ed 2 Copyright 1994-2013 Free Software Foundation, Inc.
b99bd4ef
NC		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC		 6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC		 8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC		 14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC		 19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC		 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC		 31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b
RE		 34#include "opcode/arm.h"
35
b99bd4ef
NC		 36#ifdef OBJ_ELF
37#include "elf/arm.h"
a394c00f 38#include "dw2gencfi.h"
b99bd4ef
NC		 39#endif
40
f0927246
NC		 41#include "dwarf2dbg.h"
42
7ed4c4c5
NC		 43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
c19d1205
ZW		 51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
7ed4c4c5 55 /* The segment containing the function. */
c19d1205
ZW		 56 segT saved_seg;
57 subsegT saved_subseg;
7ed4c4c5
NC		 58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
c19d1205
ZW		 60 int opcode_count;
61 int opcode_alloc;
7ed4c4c5 62 /* The number of bytes pushed to the stack. */
c19d1205 63 offsetT frame_size;
7ed4c4c5
NC		 64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
c19d1205 67 offsetT pending_offset;
7ed4c4c5 68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW		 69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
7ed4c4c5 72 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 73 unsigned fp_used:1;
7ed4c4c5 74 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 75 unsigned sp_restored:1;
7ed4c4c5
NC		 76} unwind;
77
8b1ad454
NC		 78#endif /* OBJ_ELF */
79
4962c51a
MS		 80/* Results from operand parsing worker functions. */
81
82typedef enum
83{
84 PARSE_OPERAND_SUCCESS,
85 PARSE_OPERAND_FAIL,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87} parse_operand_result;
88
33a392fb
PB		 89enum arm_float_abi
90{
91 ARM_FLOAT_ABI_HARD,
92 ARM_FLOAT_ABI_SOFTFP,
93 ARM_FLOAT_ABI_SOFT
94};
95
c19d1205 96/* Types of processor to assemble for. */
b99bd4ef 97#ifndef CPU_DEFAULT
8a59fff3 98/* The code that was here used to select a default CPU depending on compiler
fa94de6b 99 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD		 100 changing gas' default behaviour depending upon the build host.
101
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
b99bd4ef
NC		 104#endif
105
106#ifndef FPU_DEFAULT
c820d418
MM		 107# ifdef TE_LINUX
108# define FPU_DEFAULT FPU_ARCH_FPA
109# elif defined (TE_NetBSD)
110# ifdef OBJ_ELF
111# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
112# else
113 /* Legacy a.out format. */
114# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
115# endif
4e7fd91e
PB		 116# elif defined (TE_VXWORKS)
117# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM		 118# else
119 /* For backwards compatibility, default to FPA. */
120# define FPU_DEFAULT FPU_ARCH_FPA
121# endif
122#endif /* ifndef FPU_DEFAULT */
b99bd4ef 123
c19d1205 124#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 125
e74cfd16
PB		 126static arm_feature_set cpu_variant;
127static arm_feature_set arm_arch_used;
128static arm_feature_set thumb_arch_used;
b99bd4ef 129
b99bd4ef 130/* Flags stored in private area of BFD structure. */
c19d1205
ZW		 131static int uses_apcs_26 = FALSE;
132static int atpcs = FALSE;
b34976b6
AM		 133static int support_interwork = FALSE;
134static int uses_apcs_float = FALSE;
c19d1205 135static int pic_code = FALSE;
845b51d6 136static int fix_v4bx = FALSE;
278df34e
NS		 137/* Warn on using deprecated features. */
138static int warn_on_deprecated = TRUE;
139
03b1477f
RE		 140
141/* Variables that we set while parsing command-line options. Once all
142 options have been read we re-process these values to set the real
143 assembly flags. */
e74cfd16
PB		 144static const arm_feature_set *legacy_cpu = NULL;
145static const arm_feature_set *legacy_fpu = NULL;
146
147static const arm_feature_set *mcpu_cpu_opt = NULL;
148static const arm_feature_set *mcpu_fpu_opt = NULL;
149static const arm_feature_set *march_cpu_opt = NULL;
150static const arm_feature_set *march_fpu_opt = NULL;
151static const arm_feature_set *mfpu_opt = NULL;
7a1d4c38 152static const arm_feature_set *object_arch = NULL;
e74cfd16
PB		 153
154/* Constants for known architecture features. */
155static const arm_feature_set fpu_default = FPU_DEFAULT;
156static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
157static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
5287ad62
JB		 158static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
159static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
e74cfd16
PB		 160static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
161static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
162static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
163static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
164
165#ifdef CPU_DEFAULT
166static const arm_feature_set cpu_default = CPU_DEFAULT;
167#endif
168
169static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
170static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
171static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
172static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
173static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
174static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
175static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
176static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
177static const arm_feature_set arm_ext_v4t_5 =
178 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
179static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
180static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
181static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
182static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
183static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
184static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
e74cfd16 185static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
b2a5fbdc 186static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
62b3e311 187static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
9e3c6df6 188static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
7e806470
PB		 189static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
190static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
62b3e311
PB		 191static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
192static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
193static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
194static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
9e3c6df6 195static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
bca38921 196static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
7e806470 197static const arm_feature_set arm_ext_m =
b2a5fbdc 198 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
60e5ef9f 199static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
f4c65163 200static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
b2a5fbdc 201static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
eea54501 202static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
90ec0d68 203static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
e74cfd16
PB		 204
205static const arm_feature_set arm_arch_any = ARM_ANY;
206static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
207static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
208static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
251665fc 209static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
e74cfd16 210
2d447fca
JM		 211static const arm_feature_set arm_cext_iwmmxt2 =
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
e74cfd16
PB		 213static const arm_feature_set arm_cext_iwmmxt =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
215static const arm_feature_set arm_cext_xscale =
216 ARM_FEATURE (0, ARM_CEXT_XSCALE);
217static const arm_feature_set arm_cext_maverick =
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
219static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
220static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
221static const arm_feature_set fpu_vfp_ext_v1xd =
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
223static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
224static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
62f3b8c8 225static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
5287ad62 226static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
b1cc4aeb
PB		 227static const arm_feature_set fpu_vfp_ext_d32 =
228 ARM_FEATURE (0, FPU_VFP_EXT_D32);
5287ad62
JB		 229static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
230static const arm_feature_set fpu_vfp_v3_or_neon_ext =
231 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
62f3b8c8
PB		 232static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
233static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
234static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
bca38921
MGD		 235static const arm_feature_set fpu_vfp_ext_armv8 =
236 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
237static const arm_feature_set fpu_neon_ext_armv8 =
238 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
239static const arm_feature_set fpu_crypto_ext_armv8 =
240 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
dd5181d5
KT		 241static const arm_feature_set crc_ext_armv8 =
242 ARM_FEATURE (0, CRC_EXT_ARMV8);
e74cfd16 243
33a392fb 244static int mfloat_abi_opt = -1;
e74cfd16
PB		 245/* Record user cpu selection for object attributes. */
246static arm_feature_set selected_cpu = ARM_ARCH_NONE;
ee065d83
PB		 247/* Must be long enough to hold any of the names in arm_cpus. */
248static char selected_cpu_name[16];
8d67f500
NC		 249
250/* Return if no cpu was selected on command-line. */
251static bfd_boolean
252no_cpu_selected (void)
253{
254 return selected_cpu.core == arm_arch_none.core
255 && selected_cpu.coproc == arm_arch_none.coproc;
256}
257
7cc69913 258#ifdef OBJ_ELF
deeaaff8
DJ		 259# ifdef EABI_DEFAULT
260static int meabi_flags = EABI_DEFAULT;
261# else
d507cf36 262static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 263# endif
e1da3f5b 264
ee3c0378
AS		 265static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
266
e1da3f5b 267bfd_boolean
5f4273c7 268arm_is_eabi (void)
e1da3f5b
PB		 269{
270 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
271}
7cc69913 272#endif
b99bd4ef 273
b99bd4ef 274#ifdef OBJ_ELF
c19d1205 275/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC		 276symbolS * GOT_symbol;
277#endif
278
b99bd4ef
NC		 279/* 0: assemble for ARM,
280 1: assemble for Thumb,
281 2: assemble for Thumb even though target CPU does not support thumb
282 instructions. */
283static int thumb_mode = 0;
8dc2430f
NC		 284/* A value distinct from the possible values for thumb_mode that we
285 can use to record whether thumb_mode has been copied into the
286 tc_frag_data field of a frag. */
287#define MODE_RECORDED (1 << 4)
b99bd4ef 288
e07e6e58
NC		 289/* Specifies the intrinsic IT insn behavior mode. */
290enum implicit_it_mode
291{
292 IMPLICIT_IT_MODE_NEVER = 0x00,
293 IMPLICIT_IT_MODE_ARM = 0x01,
294 IMPLICIT_IT_MODE_THUMB = 0x02,
295 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
296};
297static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
298
c19d1205
ZW		 299/* If unified_syntax is true, we are processing the new unified
300 ARM/Thumb syntax. Important differences from the old ARM mode:
301
302 - Immediate operands do not require a # prefix.
303 - Conditional affixes always appear at the end of the
304 instruction. (For backward compatibility, those instructions
305 that formerly had them in the middle, continue to accept them
306 there.)
307 - The IT instruction may appear, and if it does is validated
308 against subsequent conditional affixes. It does not generate
309 machine code.
310
311 Important differences from the old Thumb mode:
312
313 - Immediate operands do not require a # prefix.
314 - Most of the V6T2 instructions are only available in unified mode.
315 - The .N and .W suffixes are recognized and honored (it is an error
316 if they cannot be honored).
317 - All instructions set the flags if and only if they have an 's' affix.
318 - Conditional affixes may be used. They are validated against
319 preceding IT instructions. Unlike ARM mode, you cannot use a
320 conditional affix except in the scope of an IT instruction. */
321
322static bfd_boolean unified_syntax = FALSE;
b99bd4ef 323
bacebabc
RM		 324/* An immediate operand can start with #, and ld*, st*, pld operands
325 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM		 326 before a [, which can appear as the first operand for pld.
327 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
328const char arm_symbol_chars[] = "#[]{}";
bacebabc 329
5287ad62
JB		 330enum neon_el_type
331{
dcbf9037 332 NT_invtype,
5287ad62
JB		 333 NT_untyped,
334 NT_integer,
335 NT_float,
336 NT_poly,
337 NT_signed,
dcbf9037 338 NT_unsigned
5287ad62
JB		 339};
340
341struct neon_type_el
342{
343 enum neon_el_type type;
344 unsigned size;
345};
346
347#define NEON_MAX_TYPE_ELS 4
348
349struct neon_type
350{
351 struct neon_type_el el[NEON_MAX_TYPE_ELS];
352 unsigned elems;
353};
354
e07e6e58
NC		 355enum it_instruction_type
356{
357 OUTSIDE_IT_INSN,
358 INSIDE_IT_INSN,
359 INSIDE_IT_LAST_INSN,
360 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 361 if inside, should be the last one. */
e07e6e58 362 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 363 i.e. BKPT and NOP. */
e07e6e58
NC		 364 IT_INSN /* The IT insn has been parsed. */
365};
366
ad6cec43
MGD		 367/* The maximum number of operands we need. */
368#define ARM_IT_MAX_OPERANDS 6
369
b99bd4ef
NC		 370struct arm_it
371{
c19d1205 372 const char * error;
b99bd4ef 373 unsigned long instruction;
c19d1205
ZW		 374 int size;
375 int size_req;
376 int cond;
037e8744
JB		 377 /* "uncond_value" is set to the value in place of the conditional field in
378 unconditional versions of the instruction, or -1 if nothing is
379 appropriate. */
380 int uncond_value;
5287ad62 381 struct neon_type vectype;
88714cb8
DG		 382 /* This does not indicate an actual NEON instruction, only that
383 the mnemonic accepts neon-style type suffixes. */
384 int is_neon;
0110f2b8
PB		 385 /* Set to the opcode if the instruction needs relaxation.
386 Zero if the instruction is not relaxed. */
387 unsigned long relax;
b99bd4ef
NC		 388 struct
389 {
390 bfd_reloc_code_real_type type;
c19d1205
ZW		 391 expressionS exp;
392 int pc_rel;
b99bd4ef 393 } reloc;
b99bd4ef 394
e07e6e58
NC		 395 enum it_instruction_type it_insn_type;
396
c19d1205
ZW		 397 struct
398 {
399 unsigned reg;
ca3f61f7 400 signed int imm;
dcbf9037 401 struct neon_type_el vectype;
ca3f61f7
NC		 402 unsigned present : 1; /* Operand present. */
403 unsigned isreg : 1; /* Operand was a register. */
404 unsigned immisreg : 1; /* .imm field is a second register. */
5287ad62
JB		 405 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
406 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 407 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB		 408 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
409 instructions. This allows us to disambiguate ARM <-> vector insns. */
410 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 411 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5287ad62 412 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
037e8744 413 unsigned issingle : 1; /* Operand is VFP single-precision register. */
ca3f61f7
NC		 414 unsigned hasreloc : 1; /* Operand has relocation suffix. */
415 unsigned writeback : 1; /* Operand has trailing ! */
416 unsigned preind : 1; /* Preindexed address. */
417 unsigned postind : 1; /* Postindexed address. */
418 unsigned negative : 1; /* Index register was negated. */
419 unsigned shifted : 1; /* Shift applied to operation. */
420 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 421 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC		 422};
423
c19d1205 424static struct arm_it inst;
b99bd4ef
NC		 425
426#define NUM_FLOAT_VALS 8
427
05d2d07e 428const char * fp_const[] =
b99bd4ef
NC		 429{
430 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
431};
432
c19d1205 433/* Number of littlenums required to hold an extended precision number. */
b99bd4ef
NC		 434#define MAX_LITTLENUMS 6
435
436LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
437
438#define FAIL (-1)
439#define SUCCESS (0)
440
441#define SUFF_S 1
442#define SUFF_D 2
443#define SUFF_E 3
444#define SUFF_P 4
445
c19d1205
ZW		 446#define CP_T_X 0x00008000
447#define CP_T_Y 0x00400000
b99bd4ef 448
c19d1205
ZW		 449#define CONDS_BIT 0x00100000
450#define LOAD_BIT 0x00100000
b99bd4ef
NC		 451
452#define DOUBLE_LOAD_FLAG 0x00000001
453
454struct asm_cond
455{
d3ce72d0 456 const char * template_name;
c921be7d 457 unsigned long value;
b99bd4ef
NC		 458};
459
c19d1205 460#define COND_ALWAYS 0xE
b99bd4ef 461
b99bd4ef
NC		 462struct asm_psr
463{
d3ce72d0 464 const char * template_name;
c921be7d 465 unsigned long field;
b99bd4ef
NC		 466};
467
62b3e311
PB		 468struct asm_barrier_opt
469{
e797f7e0
MGD		 470 const char * template_name;
471 unsigned long value;
472 const arm_feature_set arch;
62b3e311
PB		 473};
474
2d2255b5 475/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC		 476#define SPSR_BIT (1 << 22)
477
c19d1205
ZW		 478/* The individual PSR flag bits. */
479#define PSR_c (1 << 16)
480#define PSR_x (1 << 17)
481#define PSR_s (1 << 18)
482#define PSR_f (1 << 19)
b99bd4ef 483
c19d1205 484struct reloc_entry
bfae80f2 485{
c921be7d
NC		 486 char * name;
487 bfd_reloc_code_real_type reloc;
bfae80f2
RE		 488};
489
5287ad62 490enum vfp_reg_pos
bfae80f2 491{
5287ad62
JB		 492 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
493 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE		 494};
495
496enum vfp_ldstm_type
497{
498 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
499};
500
dcbf9037
JB		 501/* Bits for DEFINED field in neon_typed_alias. */
502#define NTA_HASTYPE 1
503#define NTA_HASINDEX 2
504
505struct neon_typed_alias
506{
c921be7d
NC		 507 unsigned char defined;
508 unsigned char index;
509 struct neon_type_el eltype;
dcbf9037
JB		 510};
511
c19d1205
ZW		 512/* ARM register categories. This includes coprocessor numbers and various
513 architecture extensions' registers. */
514enum arm_reg_type
bfae80f2 515{
c19d1205
ZW		 516 REG_TYPE_RN,
517 REG_TYPE_CP,
518 REG_TYPE_CN,
519 REG_TYPE_FN,
520 REG_TYPE_VFS,
521 REG_TYPE_VFD,
5287ad62 522 REG_TYPE_NQ,
037e8744 523 REG_TYPE_VFSD,
5287ad62 524 REG_TYPE_NDQ,
037e8744 525 REG_TYPE_NSDQ,
c19d1205
ZW		 526 REG_TYPE_VFC,
527 REG_TYPE_MVF,
528 REG_TYPE_MVD,
529 REG_TYPE_MVFX,
530 REG_TYPE_MVDX,
531 REG_TYPE_MVAX,
532 REG_TYPE_DSPSC,
533 REG_TYPE_MMXWR,
534 REG_TYPE_MMXWC,
535 REG_TYPE_MMXWCG,
536 REG_TYPE_XSCALE,
90ec0d68 537 REG_TYPE_RNB
bfae80f2
RE		 538};
539
dcbf9037
JB		 540/* Structure for a hash table entry for a register.
541 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
542 information which states whether a vector type or index is specified (for a
543 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE		 544struct reg_entry
545{
c921be7d 546 const char * name;
90ec0d68 547 unsigned int number;
c921be7d
NC		 548 unsigned char type;
549 unsigned char builtin;
550 struct neon_typed_alias * neon;
6c43fab6
RE		 551};
552
c19d1205 553/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 554const char * const reg_expected_msgs[] =
c19d1205
ZW		 555{
556 N_("ARM register expected"),
557 N_("bad or missing co-processor number"),
558 N_("co-processor register expected"),
559 N_("FPA register expected"),
560 N_("VFP single precision register expected"),
5287ad62
JB		 561 N_("VFP/Neon double precision register expected"),
562 N_("Neon quad precision register expected"),
037e8744 563 N_("VFP single or double precision register expected"),
5287ad62 564 N_("Neon double or quad precision register expected"),
037e8744 565 N_("VFP single, double or Neon quad precision register expected"),
c19d1205
ZW		 566 N_("VFP system register expected"),
567 N_("Maverick MVF register expected"),
568 N_("Maverick MVD register expected"),
569 N_("Maverick MVFX register expected"),
570 N_("Maverick MVDX register expected"),
571 N_("Maverick MVAX register expected"),
572 N_("Maverick DSPSC register expected"),
573 N_("iWMMXt data register expected"),
574 N_("iWMMXt control register expected"),
575 N_("iWMMXt scalar register expected"),
576 N_("XScale accumulator register expected"),
6c43fab6
RE		 577};
578
c19d1205 579/* Some well known registers that we refer to directly elsewhere. */
bd340a04 580#define REG_R12 12
c19d1205
ZW		 581#define REG_SP 13
582#define REG_LR 14
583#define REG_PC 15
404ff6b5 584
b99bd4ef
NC		 585/* ARM instructions take 4bytes in the object file, Thumb instructions
586 take 2: */
c19d1205 587#define INSN_SIZE 4
b99bd4ef
NC		 588
589struct asm_opcode
590{
591 /* Basic string to match. */
d3ce72d0 592 const char * template_name;
c19d1205
ZW		 593
594 /* Parameters to instruction. */
5be8be5d 595 unsigned int operands[8];
c19d1205
ZW		 596
597 /* Conditional tag - see opcode_lookup. */
598 unsigned int tag : 4;
b99bd4ef
NC		 599
600 /* Basic instruction code. */
c19d1205 601 unsigned int avalue : 28;
b99bd4ef 602
c19d1205
ZW		 603 /* Thumb-format instruction code. */
604 unsigned int tvalue;
b99bd4ef 605
90e4755a 606 /* Which architecture variant provides this instruction. */
c921be7d
NC		 607 const arm_feature_set * avariant;
608 const arm_feature_set * tvariant;
c19d1205
ZW		 609
610 /* Function to call to encode instruction in ARM format. */
611 void (* aencode) (void);
b99bd4ef 612
c19d1205
ZW		 613 /* Function to call to encode instruction in Thumb format. */
614 void (* tencode) (void);
b99bd4ef
NC		 615};
616
a737bd4d
NC		 617/* Defines for various bits that we will want to toggle. */
618#define INST_IMMEDIATE 0x02000000
619#define OFFSET_REG 0x02000000
c19d1205 620#define HWOFFSET_IMM 0x00400000
a737bd4d
NC		 621#define SHIFT_BY_REG 0x00000010
622#define PRE_INDEX 0x01000000
623#define INDEX_UP 0x00800000
624#define WRITE_BACK 0x00200000
625#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 626#define CPSI_MMOD 0x00020000
90e4755a 627
a737bd4d
NC		 628#define LITERAL_MASK 0xf000f000
629#define OPCODE_MASK 0xfe1fffff
630#define V4_STR_BIT 0x00000020
90e4755a 631
efd81785
PB		 632#define T2_SUBS_PC_LR 0xf3de8f00
633
a737bd4d 634#define DATA_OP_SHIFT 21
90e4755a 635
ef8d22e6
PB		 636#define T2_OPCODE_MASK 0xfe1fffff
637#define T2_DATA_OP_SHIFT 21
638
6530b175
NC		 639#define A_COND_MASK 0xf0000000
640#define A_PUSH_POP_OP_MASK 0x0fff0000
641
642/* Opcodes for pushing/poping registers to/from the stack. */
643#define A1_OPCODE_PUSH 0x092d0000
644#define A2_OPCODE_PUSH 0x052d0004
645#define A2_OPCODE_POP 0x049d0004
646
a737bd4d
NC		 647/* Codes to distinguish the arithmetic instructions. */
648#define OPCODE_AND 0
649#define OPCODE_EOR 1
650#define OPCODE_SUB 2
651#define OPCODE_RSB 3
652#define OPCODE_ADD 4
653#define OPCODE_ADC 5
654#define OPCODE_SBC 6
655#define OPCODE_RSC 7
656#define OPCODE_TST 8
657#define OPCODE_TEQ 9
658#define OPCODE_CMP 10
659#define OPCODE_CMN 11
660#define OPCODE_ORR 12
661#define OPCODE_MOV 13
662#define OPCODE_BIC 14
663#define OPCODE_MVN 15
90e4755a 664
ef8d22e6
PB		 665#define T2_OPCODE_AND 0
666#define T2_OPCODE_BIC 1
667#define T2_OPCODE_ORR 2
668#define T2_OPCODE_ORN 3
669#define T2_OPCODE_EOR 4
670#define T2_OPCODE_ADD 8
671#define T2_OPCODE_ADC 10
672#define T2_OPCODE_SBC 11
673#define T2_OPCODE_SUB 13
674#define T2_OPCODE_RSB 14
675
a737bd4d
NC		 676#define T_OPCODE_MUL 0x4340
677#define T_OPCODE_TST 0x4200
678#define T_OPCODE_CMN 0x42c0
679#define T_OPCODE_NEG 0x4240
680#define T_OPCODE_MVN 0x43c0
90e4755a 681
a737bd4d
NC		 682#define T_OPCODE_ADD_R3 0x1800
683#define T_OPCODE_SUB_R3 0x1a00
684#define T_OPCODE_ADD_HI 0x4400
685#define T_OPCODE_ADD_ST 0xb000
686#define T_OPCODE_SUB_ST 0xb080
687#define T_OPCODE_ADD_SP 0xa800
688#define T_OPCODE_ADD_PC 0xa000
689#define T_OPCODE_ADD_I8 0x3000
690#define T_OPCODE_SUB_I8 0x3800
691#define T_OPCODE_ADD_I3 0x1c00
692#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 693
a737bd4d
NC		 694#define T_OPCODE_ASR_R 0x4100
695#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW		 696#define T_OPCODE_LSR_R 0x40c0
697#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC		 698#define T_OPCODE_ASR_I 0x1000
699#define T_OPCODE_LSL_I 0x0000
700#define T_OPCODE_LSR_I 0x0800
b99bd4ef 701
a737bd4d
NC		 702#define T_OPCODE_MOV_I8 0x2000
703#define T_OPCODE_CMP_I8 0x2800
704#define T_OPCODE_CMP_LR 0x4280
705#define T_OPCODE_MOV_HR 0x4600
706#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 707
a737bd4d
NC		 708#define T_OPCODE_LDR_PC 0x4800
709#define T_OPCODE_LDR_SP 0x9800
710#define T_OPCODE_STR_SP 0x9000
711#define T_OPCODE_LDR_IW 0x6800
712#define T_OPCODE_STR_IW 0x6000
713#define T_OPCODE_LDR_IH 0x8800
714#define T_OPCODE_STR_IH 0x8000
715#define T_OPCODE_LDR_IB 0x7800
716#define T_OPCODE_STR_IB 0x7000
717#define T_OPCODE_LDR_RW 0x5800
718#define T_OPCODE_STR_RW 0x5000
719#define T_OPCODE_LDR_RH 0x5a00
720#define T_OPCODE_STR_RH 0x5200
721#define T_OPCODE_LDR_RB 0x5c00
722#define T_OPCODE_STR_RB 0x5400
c9b604bd 723
a737bd4d
NC		 724#define T_OPCODE_PUSH 0xb400
725#define T_OPCODE_POP 0xbc00
b99bd4ef 726
2fc8bdac 727#define T_OPCODE_BRANCH 0xe000
b99bd4ef 728
a737bd4d 729#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 730#define THUMB_PP_PC_LR 0x0100
c19d1205 731#define THUMB_LOAD_BIT 0x0800
53365c0d 732#define THUMB2_LOAD_BIT 0x00100000
c19d1205
ZW		 733
734#define BAD_ARGS _("bad arguments to instruction")
fdfde340 735#define BAD_SP _("r13 not allowed here")
c19d1205
ZW		 736#define BAD_PC _("r15 not allowed here")
737#define BAD_COND _("instruction cannot be conditional")
738#define BAD_OVERLAP _("registers may not be the same")
739#define BAD_HIREG _("lo register required")
740#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
01cfc07f 741#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
dfa9f0d5
PB		 742#define BAD_BRANCH _("branch must be last instruction in IT block")
743#define BAD_NOT_IT _("instruction not allowed in IT block")
037e8744 744#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58
NC		 745#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
746#define BAD_IT_COND _("incorrect condition in IT block")
747#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 748#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG		 749#define BAD_PC_ADDRESSING \
750 _("cannot use register index with PC-relative addressing")
751#define BAD_PC_WRITEBACK \
752 _("cannot use writeback with PC-relative addressing")
08f10d51 753#define BAD_RANGE _("branch out of range")
dd5181d5 754#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
c19d1205 755
c921be7d
NC		 756static struct hash_control * arm_ops_hsh;
757static struct hash_control * arm_cond_hsh;
758static struct hash_control * arm_shift_hsh;
759static struct hash_control * arm_psr_hsh;
760static struct hash_control * arm_v7m_psr_hsh;
761static struct hash_control * arm_reg_hsh;
762static struct hash_control * arm_reloc_hsh;
763static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 764
b99bd4ef
NC		 765/* Stuff needed to resolve the label ambiguity
766 As:
767 ...
768 label: <insn>
769 may differ from:
770 ...
771 label:
5f4273c7 772 <insn> */
b99bd4ef
NC		 773
774symbolS * last_label_seen;
b34976b6 775static int label_is_thumb_function_name = FALSE;
e07e6e58 776
3d0c9500
NC		 777/* Literal pool structure. Held on a per-section
778 and per-sub-section basis. */
a737bd4d 779
c19d1205 780#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 781typedef struct literal_pool
b99bd4ef 782{
c921be7d
NC		 783 expressionS literals [MAX_LITERAL_POOL_SIZE];
784 unsigned int next_free_entry;
785 unsigned int id;
786 symbolS * symbol;
787 segT section;
788 subsegT sub_section;
a8040cf2
NC		 789#ifdef OBJ_ELF
790 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
791#endif
c921be7d 792 struct literal_pool * next;
3d0c9500 793} literal_pool;
b99bd4ef 794
3d0c9500
NC		 795/* Pointer to a linked list of literal pools. */
796literal_pool * list_of_pools = NULL;
e27ec89e 797
e07e6e58
NC		 798#ifdef OBJ_ELF
799# define now_it seg_info (now_seg)->tc_segment_info_data.current_it
800#else
801static struct current_it now_it;
802#endif
803
804static inline int
805now_it_compatible (int cond)
806{
807 return (cond & ~1) == (now_it.cc & ~1);
808}
809
810static inline int
811conditional_insn (void)
812{
813 return inst.cond != COND_ALWAYS;
814}
815
816static int in_it_block (void);
817
818static int handle_it_state (void);
819
820static void force_automatic_it_block_close (void);
821
c921be7d
NC		 822static void it_fsm_post_encode (void);
823
e07e6e58
NC		 824#define set_it_insn_type(type) \
825 do \
826 { \
827 inst.it_insn_type = type; \
828 if (handle_it_state () == FAIL) \
477330fc 829 return; \
e07e6e58
NC		 830 } \
831 while (0)
832
c921be7d
NC		 833#define set_it_insn_type_nonvoid(type, failret) \
834 do \
835 { \
836 inst.it_insn_type = type; \
837 if (handle_it_state () == FAIL) \
477330fc 838 return failret; \
c921be7d
NC		 839 } \
840 while(0)
841
e07e6e58
NC		 842#define set_it_insn_type_last() \
843 do \
844 { \
845 if (inst.cond == COND_ALWAYS) \
477330fc 846 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 847 else \
477330fc 848 set_it_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC		 849 } \
850 while (0)
851
c19d1205 852/* Pure syntax. */
b99bd4ef 853
c19d1205
ZW		 854/* This array holds the chars that always start a comment. If the
855 pre-processor is disabled, these aren't very useful. */
856const char comment_chars[] = "@";
3d0c9500 857
c19d1205
ZW		 858/* This array holds the chars that only start a comment at the beginning of
859 a line. If the line seems to have the form '# 123 filename'
860 .line and .file directives will appear in the pre-processed output. */
861/* Note that input_file.c hand checks for '#' at the beginning of the
862 first line of the input file. This is because the compiler outputs
863 #NO_APP at the beginning of its output. */
864/* Also note that comments like this one will always work. */
865const char line_comment_chars[] = "#";
3d0c9500 866
c19d1205 867const char line_separator_chars[] = ";";
b99bd4ef 868
c19d1205
ZW		 869/* Chars that can be used to separate mant
870 from exp in floating point numbers. */
871const char EXP_CHARS[] = "eE";
3d0c9500 872
c19d1205
ZW		 873/* Chars that mean this number is a floating point constant. */
874/* As in 0f12.456 */
875/* or 0d1.2345e12 */
b99bd4ef 876
c19d1205 877const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 878
c19d1205
ZW		 879/* Prefix characters that indicate the start of an immediate
880 value. */
881#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 882
c19d1205
ZW		 883/* Separator character handling. */
884
885#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
886
887static inline int
888skip_past_char (char ** str, char c)
889{
8ab8155f
NC		 890 /* PR gas/14987: Allow for whitespace before the expected character. */
891 skip_whitespace (*str);
427d0db6 892
c19d1205
ZW		 893 if (**str == c)
894 {
895 (*str)++;
896 return SUCCESS;
3d0c9500 897 }
c19d1205
ZW		 898 else
899 return FAIL;
900}
c921be7d 901
c19d1205 902#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 903
c19d1205
ZW		 904/* Arithmetic expressions (possibly involving symbols). */
905
906/* Return TRUE if anything in the expression is a bignum. */
907
908static int
909walk_no_bignums (symbolS * sp)
910{
911 if (symbol_get_value_expression (sp)->X_op == O_big)
912 return 1;
913
914 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 915 {
c19d1205
ZW		 916 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
917 || (symbol_get_value_expression (sp)->X_op_symbol
918 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC		 919 }
920
c19d1205 921 return 0;
3d0c9500
NC		 922}
923
c19d1205
ZW		 924static int in_my_get_expression = 0;
925
926/* Third argument to my_get_expression. */
927#define GE_NO_PREFIX 0
928#define GE_IMM_PREFIX 1
929#define GE_OPT_PREFIX 2
5287ad62
JB		 930/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
931 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
932#define GE_OPT_PREFIX_BIG 3
a737bd4d 933
b99bd4ef 934static int
c19d1205 935my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 936{
c19d1205
ZW		 937 char * save_in;
938 segT seg;
b99bd4ef 939
c19d1205
ZW		 940 /* In unified syntax, all prefixes are optional. */
941 if (unified_syntax)
5287ad62 942 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 943 : GE_OPT_PREFIX;
b99bd4ef 944
c19d1205 945 switch (prefix_mode)
b99bd4ef 946 {
c19d1205
ZW		 947 case GE_NO_PREFIX: break;
948 case GE_IMM_PREFIX:
949 if (!is_immediate_prefix (**str))
950 {
951 inst.error = _("immediate expression requires a # prefix");
952 return FAIL;
953 }
954 (*str)++;
955 break;
956 case GE_OPT_PREFIX:
5287ad62 957 case GE_OPT_PREFIX_BIG:
c19d1205
ZW		 958 if (is_immediate_prefix (**str))
959 (*str)++;
960 break;
961 default: abort ();
962 }
b99bd4ef 963
c19d1205 964 memset (ep, 0, sizeof (expressionS));
b99bd4ef 965
c19d1205
ZW		 966 save_in = input_line_pointer;
967 input_line_pointer = *str;
968 in_my_get_expression = 1;
969 seg = expression (ep);
970 in_my_get_expression = 0;
971
f86adc07 972 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 973 {
f86adc07 974 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW		 975 *str = input_line_pointer;
976 input_line_pointer = save_in;
977 if (inst.error == NULL)
f86adc07
NS		 978 inst.error = (ep->X_op == O_absent
979 ? _("missing expression") :_("bad expression"));
c19d1205
ZW		 980 return 1;
981 }
b99bd4ef 982
c19d1205
ZW		 983#ifdef OBJ_AOUT
984 if (seg != absolute_section
985 && seg != text_section
986 && seg != data_section
987 && seg != bss_section
988 && seg != undefined_section)
989 {
990 inst.error = _("bad segment");
991 *str = input_line_pointer;
992 input_line_pointer = save_in;
993 return 1;
b99bd4ef 994 }
87975d2a
AM		 995#else
996 (void) seg;
c19d1205 997#endif
b99bd4ef 998
c19d1205
ZW		 999 /* Get rid of any bignums now, so that we don't generate an error for which
1000 we can't establish a line number later on. Big numbers are never valid
1001 in instructions, which is where this routine is always called. */
5287ad62
JB		 1002 if (prefix_mode != GE_OPT_PREFIX_BIG
1003 && (ep->X_op == O_big
477330fc 1004 || (ep->X_add_symbol
5287ad62 1005 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1006 || (ep->X_op_symbol
5287ad62 1007 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW		 1008 {
1009 inst.error = _("invalid constant");
1010 *str = input_line_pointer;
1011 input_line_pointer = save_in;
1012 return 1;
1013 }
b99bd4ef 1014
c19d1205
ZW		 1015 *str = input_line_pointer;
1016 input_line_pointer = save_in;
1017 return 0;
b99bd4ef
NC		 1018}
1019
c19d1205
ZW		 1020/* Turn a string in input_line_pointer into a floating point constant
1021 of type TYPE, and store the appropriate bytes in *LITP. The number
1022 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1023 returned, or NULL on OK.
b99bd4ef 1024
c19d1205
ZW		 1025 Note that fp constants aren't represent in the normal way on the ARM.
1026 In big endian mode, things are as expected. However, in little endian
1027 mode fp constants are big-endian word-wise, and little-endian byte-wise
1028 within the words. For example, (double) 1.1 in big endian mode is
1029 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1030 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1031
c19d1205 1032 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1033
c19d1205
ZW		 1034char *
1035md_atof (int type, char * litP, int * sizeP)
1036{
1037 int prec;
1038 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1039 char *t;
1040 int i;
b99bd4ef 1041
c19d1205
ZW		 1042 switch (type)
1043 {
1044 case 'f':
1045 case 'F':
1046 case 's':
1047 case 'S':
1048 prec = 2;
1049 break;
b99bd4ef 1050
c19d1205
ZW		 1051 case 'd':
1052 case 'D':
1053 case 'r':
1054 case 'R':
1055 prec = 4;
1056 break;
b99bd4ef 1057
c19d1205
ZW		 1058 case 'x':
1059 case 'X':
499ac353 1060 prec = 5;
c19d1205 1061 break;
b99bd4ef 1062
c19d1205
ZW		 1063 case 'p':
1064 case 'P':
499ac353 1065 prec = 5;
c19d1205 1066 break;
a737bd4d 1067
c19d1205
ZW		 1068 default:
1069 *sizeP = 0;
499ac353 1070 return _("Unrecognized or unsupported floating point constant");
c19d1205 1071 }
b99bd4ef 1072
c19d1205
ZW		 1073 t = atof_ieee (input_line_pointer, type, words);
1074 if (t)
1075 input_line_pointer = t;
499ac353 1076 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1077
c19d1205
ZW		 1078 if (target_big_endian)
1079 {
1080 for (i = 0; i < prec; i++)
1081 {
499ac353
NC		 1082 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1083 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1084 }
1085 }
1086 else
1087 {
e74cfd16 1088 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
c19d1205
ZW		 1089 for (i = prec - 1; i >= 0; i--)
1090 {
499ac353
NC		 1091 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1092 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1093 }
1094 else
1095 /* For a 4 byte float the order of elements in `words' is 1 0.
1096 For an 8 byte float the order is 1 0 3 2. */
1097 for (i = 0; i < prec; i += 2)
1098 {
499ac353
NC		 1099 md_number_to_chars (litP, (valueT) words[i + 1],
1100 sizeof (LITTLENUM_TYPE));
1101 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1102 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1103 litP += 2 * sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1104 }
1105 }
b99bd4ef 1106
499ac353 1107 return NULL;
c19d1205 1108}
b99bd4ef 1109
c19d1205
ZW		 1110/* We handle all bad expressions here, so that we can report the faulty
1111 instruction in the error message. */
1112void
91d6fa6a 1113md_operand (expressionS * exp)
c19d1205
ZW		 1114{
1115 if (in_my_get_expression)
91d6fa6a 1116 exp->X_op = O_illegal;
b99bd4ef
NC		 1117}
1118
c19d1205 1119/* Immediate values. */
b99bd4ef 1120
c19d1205
ZW		 1121/* Generic immediate-value read function for use in directives.
1122 Accepts anything that 'expression' can fold to a constant.
1123 *val receives the number. */
1124#ifdef OBJ_ELF
1125static int
1126immediate_for_directive (int *val)
b99bd4ef 1127{
c19d1205
ZW		 1128 expressionS exp;
1129 exp.X_op = O_illegal;
b99bd4ef 1130
c19d1205
ZW		 1131 if (is_immediate_prefix (*input_line_pointer))
1132 {
1133 input_line_pointer++;
1134 expression (&exp);
1135 }
b99bd4ef 1136
c19d1205
ZW		 1137 if (exp.X_op != O_constant)
1138 {
1139 as_bad (_("expected #constant"));
1140 ignore_rest_of_line ();
1141 return FAIL;
1142 }
1143 *val = exp.X_add_number;
1144 return SUCCESS;
b99bd4ef 1145}
c19d1205 1146#endif
b99bd4ef 1147
c19d1205 1148/* Register parsing. */
b99bd4ef 1149
c19d1205
ZW		 1150/* Generic register parser. CCP points to what should be the
1151 beginning of a register name. If it is indeed a valid register
1152 name, advance CCP over it and return the reg_entry structure;
1153 otherwise return NULL. Does not issue diagnostics. */
1154
1155static struct reg_entry *
1156arm_reg_parse_multi (char **ccp)
b99bd4ef 1157{
c19d1205
ZW		 1158 char *start = *ccp;
1159 char *p;
1160 struct reg_entry *reg;
b99bd4ef 1161
477330fc
RM		 1162 skip_whitespace (start);
1163
c19d1205
ZW		 1164#ifdef REGISTER_PREFIX
1165 if (*start != REGISTER_PREFIX)
01cfc07f 1166 return NULL;
c19d1205
ZW		 1167 start++;
1168#endif
1169#ifdef OPTIONAL_REGISTER_PREFIX
1170 if (*start == OPTIONAL_REGISTER_PREFIX)
1171 start++;
1172#endif
b99bd4ef 1173
c19d1205
ZW		 1174 p = start;
1175 if (!ISALPHA (*p) || !is_name_beginner (*p))
1176 return NULL;
b99bd4ef 1177
c19d1205
ZW		 1178 do
1179 p++;
1180 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1181
1182 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1183
1184 if (!reg)
1185 return NULL;
1186
1187 *ccp = p;
1188 return reg;
b99bd4ef
NC		 1189}
1190
1191static int
dcbf9037 1192arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1193 enum arm_reg_type type)
b99bd4ef 1194{
c19d1205
ZW		 1195 /* Alternative syntaxes are accepted for a few register classes. */
1196 switch (type)
1197 {
1198 case REG_TYPE_MVF:
1199 case REG_TYPE_MVD:
1200 case REG_TYPE_MVFX:
1201 case REG_TYPE_MVDX:
1202 /* Generic coprocessor register names are allowed for these. */
79134647 1203 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW		 1204 return reg->number;
1205 break;
69b97547 1206
c19d1205
ZW		 1207 case REG_TYPE_CP:
1208 /* For backward compatibility, a bare number is valid here. */
1209 {
1210 unsigned long processor = strtoul (start, ccp, 10);
1211 if (*ccp != start && processor <= 15)
1212 return processor;
1213 }
6057a28f 1214
c19d1205
ZW		 1215 case REG_TYPE_MMXWC:
1216 /* WC includes WCG. ??? I'm not sure this is true for all
1217 instructions that take WC registers. */
79134647 1218 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1219 return reg->number;
6057a28f 1220 break;
c19d1205 1221
6057a28f 1222 default:
c19d1205 1223 break;
6057a28f
NC		 1224 }
1225
dcbf9037
JB		 1226 return FAIL;
1227}
1228
1229/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1230 return value is the register number or FAIL. */
1231
1232static int
1233arm_reg_parse (char **ccp, enum arm_reg_type type)
1234{
1235 char *start = *ccp;
1236 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1237 int ret;
1238
1239 /* Do not allow a scalar (reg+index) to parse as a register. */
1240 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1241 return FAIL;
1242
1243 if (reg && reg->type == type)
1244 return reg->number;
1245
1246 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1247 return ret;
1248
c19d1205
ZW		 1249 *ccp = start;
1250 return FAIL;
1251}
69b97547 1252
dcbf9037
JB		 1253/* Parse a Neon type specifier. *STR should point at the leading '.'
1254 character. Does no verification at this stage that the type fits the opcode
1255 properly. E.g.,
1256
1257 .i32.i32.s16
1258 .s32.f32
1259 .u16
1260
1261 Can all be legally parsed by this function.
1262
1263 Fills in neon_type struct pointer with parsed information, and updates STR
1264 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1265 type, FAIL if not. */
1266
1267static int
1268parse_neon_type (struct neon_type *type, char **str)
1269{
1270 char *ptr = *str;
1271
1272 if (type)
1273 type->elems = 0;
1274
1275 while (type->elems < NEON_MAX_TYPE_ELS)
1276 {
1277 enum neon_el_type thistype = NT_untyped;
1278 unsigned thissize = -1u;
1279
1280 if (*ptr != '.')
1281 break;
1282
1283 ptr++;
1284
1285 /* Just a size without an explicit type. */
1286 if (ISDIGIT (*ptr))
1287 goto parsesize;
1288
1289 switch (TOLOWER (*ptr))
1290 {
1291 case 'i': thistype = NT_integer; break;
1292 case 'f': thistype = NT_float; break;
1293 case 'p': thistype = NT_poly; break;
1294 case 's': thistype = NT_signed; break;
1295 case 'u': thistype = NT_unsigned; break;
477330fc
RM		 1296 case 'd':
1297 thistype = NT_float;
1298 thissize = 64;
1299 ptr++;
1300 goto done;
dcbf9037
JB		 1301 default:
1302 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1303 return FAIL;
1304 }
1305
1306 ptr++;
1307
1308 /* .f is an abbreviation for .f32. */
1309 if (thistype == NT_float && !ISDIGIT (*ptr))
1310 thissize = 32;
1311 else
1312 {
1313 parsesize:
1314 thissize = strtoul (ptr, &ptr, 10);
1315
1316 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM		 1317 && thissize != 64)
1318 {
1319 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB		 1320 return FAIL;
1321 }
1322 }
1323
037e8744 1324 done:
dcbf9037 1325 if (type)
477330fc
RM		 1326 {
1327 type->el[type->elems].type = thistype;
dcbf9037
JB		 1328 type->el[type->elems].size = thissize;
1329 type->elems++;
1330 }
1331 }
1332
1333 /* Empty/missing type is not a successful parse. */
1334 if (type->elems == 0)
1335 return FAIL;
1336
1337 *str = ptr;
1338
1339 return SUCCESS;
1340}
1341
1342/* Errors may be set multiple times during parsing or bit encoding
1343 (particularly in the Neon bits), but usually the earliest error which is set
1344 will be the most meaningful. Avoid overwriting it with later (cascading)
1345 errors by calling this function. */
1346
1347static void
1348first_error (const char *err)
1349{
1350 if (!inst.error)
1351 inst.error = err;
1352}
1353
1354/* Parse a single type, e.g. ".s32", leading period included. */
1355static int
1356parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1357{
1358 char *str = *ccp;
1359 struct neon_type optype;
1360
1361 if (*str == '.')
1362 {
1363 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM		 1364 {
1365 if (optype.elems == 1)
1366 *vectype = optype.el[0];
1367 else
1368 {
1369 first_error (_("only one type should be specified for operand"));
1370 return FAIL;
1371 }
1372 }
dcbf9037 1373 else
477330fc
RM		 1374 {
1375 first_error (_("vector type expected"));
1376 return FAIL;
1377 }
dcbf9037
JB		 1378 }
1379 else
1380 return FAIL;
5f4273c7 1381
dcbf9037 1382 *ccp = str;
5f4273c7 1383
dcbf9037
JB		 1384 return SUCCESS;
1385}
1386
1387/* Special meanings for indices (which have a range of 0-7), which will fit into
1388 a 4-bit integer. */
1389
1390#define NEON_ALL_LANES 15
1391#define NEON_INTERLEAVE_LANES 14
1392
1393/* Parse either a register or a scalar, with an optional type. Return the
1394 register number, and optionally fill in the actual type of the register
1395 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1396 type/index information in *TYPEINFO. */
1397
1398static int
1399parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM		 1400 enum arm_reg_type *rtype,
1401 struct neon_typed_alias *typeinfo)
dcbf9037
JB		 1402{
1403 char *str = *ccp;
1404 struct reg_entry *reg = arm_reg_parse_multi (&str);
1405 struct neon_typed_alias atype;
1406 struct neon_type_el parsetype;
1407
1408 atype.defined = 0;
1409 atype.index = -1;
1410 atype.eltype.type = NT_invtype;
1411 atype.eltype.size = -1;
1412
1413 /* Try alternate syntax for some types of register. Note these are mutually
1414 exclusive with the Neon syntax extensions. */
1415 if (reg == NULL)
1416 {
1417 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1418 if (altreg != FAIL)
477330fc 1419 *ccp = str;
dcbf9037 1420 if (typeinfo)
477330fc 1421 *typeinfo = atype;
dcbf9037
JB		 1422 return altreg;
1423 }
1424
037e8744
JB		 1425 /* Undo polymorphism when a set of register types may be accepted. */
1426 if ((type == REG_TYPE_NDQ
1427 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1428 || (type == REG_TYPE_VFSD
477330fc 1429 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1430 || (type == REG_TYPE_NSDQ
477330fc
RM		 1431 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1432 || reg->type == REG_TYPE_NQ))
f512f76f
NC		 1433 || (type == REG_TYPE_MMXWC
1434 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1435 type = (enum arm_reg_type) reg->type;
dcbf9037
JB		 1436
1437 if (type != reg->type)
1438 return FAIL;
1439
1440 if (reg->neon)
1441 atype = *reg->neon;
5f4273c7 1442
dcbf9037
JB		 1443 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1444 {
1445 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM		 1446 {
1447 first_error (_("can't redefine type for operand"));
1448 return FAIL;
1449 }
dcbf9037
JB		 1450 atype.defined |= NTA_HASTYPE;
1451 atype.eltype = parsetype;
1452 }
5f4273c7 1453
dcbf9037
JB		 1454 if (skip_past_char (&str, '[') == SUCCESS)
1455 {
1456 if (type != REG_TYPE_VFD)
477330fc
RM		 1457 {
1458 first_error (_("only D registers may be indexed"));
1459 return FAIL;
1460 }
5f4273c7 1461
dcbf9037 1462 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 1463 {
1464 first_error (_("can't change index for operand"));
1465 return FAIL;
1466 }
dcbf9037
JB		 1467
1468 atype.defined |= NTA_HASINDEX;
1469
1470 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1471 atype.index = NEON_ALL_LANES;
dcbf9037 1472 else
477330fc
RM		 1473 {
1474 expressionS exp;
dcbf9037 1475
477330fc 1476 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1477
477330fc
RM		 1478 if (exp.X_op != O_constant)
1479 {
1480 first_error (_("constant expression required"));
1481 return FAIL;
1482 }
dcbf9037 1483
477330fc
RM		 1484 if (skip_past_char (&str, ']') == FAIL)
1485 return FAIL;
dcbf9037 1486
477330fc
RM		 1487 atype.index = exp.X_add_number;
1488 }
dcbf9037 1489 }
5f4273c7 1490
dcbf9037
JB		 1491 if (typeinfo)
1492 *typeinfo = atype;
5f4273c7 1493
dcbf9037
JB		 1494 if (rtype)
1495 *rtype = type;
5f4273c7 1496
dcbf9037 1497 *ccp = str;
5f4273c7 1498
dcbf9037
JB		 1499 return reg->number;
1500}
1501
1502/* Like arm_reg_parse, but allow allow the following extra features:
1503 - If RTYPE is non-zero, return the (possibly restricted) type of the
1504 register (e.g. Neon double or quad reg when either has been requested).
1505 - If this is a Neon vector type with additional type information, fill
1506 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1507 This function will fault on encountering a scalar. */
dcbf9037
JB		 1508
1509static int
1510arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1511 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB		 1512{
1513 struct neon_typed_alias atype;
1514 char *str = *ccp;
1515 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1516
1517 if (reg == FAIL)
1518 return FAIL;
1519
0855e32b
NS		 1520 /* Do not allow regname(... to parse as a register. */
1521 if (*str == '(')
1522 return FAIL;
1523
dcbf9037
JB		 1524 /* Do not allow a scalar (reg+index) to parse as a register. */
1525 if ((atype.defined & NTA_HASINDEX) != 0)
1526 {
1527 first_error (_("register operand expected, but got scalar"));
1528 return FAIL;
1529 }
1530
1531 if (vectype)
1532 *vectype = atype.eltype;
1533
1534 *ccp = str;
1535
1536 return reg;
1537}
1538
1539#define NEON_SCALAR_REG(X) ((X) >> 4)
1540#define NEON_SCALAR_INDEX(X) ((X) & 15)
1541
5287ad62
JB		 1542/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1543 have enough information to be able to do a good job bounds-checking. So, we
1544 just do easy checks here, and do further checks later. */
1545
1546static int
dcbf9037 1547parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
5287ad62 1548{
dcbf9037 1549 int reg;
5287ad62 1550 char *str = *ccp;
dcbf9037 1551 struct neon_typed_alias atype;
5f4273c7 1552
dcbf9037 1553 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
5f4273c7 1554
dcbf9037 1555 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1556 return FAIL;
5f4273c7 1557
dcbf9037 1558 if (atype.index == NEON_ALL_LANES)
5287ad62 1559 {
dcbf9037 1560 first_error (_("scalar must have an index"));
5287ad62
JB		 1561 return FAIL;
1562 }
dcbf9037 1563 else if (atype.index >= 64 / elsize)
5287ad62 1564 {
dcbf9037 1565 first_error (_("scalar index out of range"));
5287ad62
JB		 1566 return FAIL;
1567 }
5f4273c7 1568
dcbf9037
JB		 1569 if (type)
1570 *type = atype.eltype;
5f4273c7 1571
5287ad62 1572 *ccp = str;
5f4273c7 1573
dcbf9037 1574 return reg * 16 + atype.index;
5287ad62
JB		 1575}
1576
c19d1205 1577/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1578
c19d1205
ZW		 1579static long
1580parse_reg_list (char ** strp)
1581{
1582 char * str = * strp;
1583 long range = 0;
1584 int another_range;
a737bd4d 1585
c19d1205
ZW		 1586 /* We come back here if we get ranges concatenated by '+' or '|'. */
1587 do
6057a28f 1588 {
477330fc
RM		 1589 skip_whitespace (str);
1590
c19d1205 1591 another_range = 0;
a737bd4d 1592
c19d1205
ZW		 1593 if (*str == '{')
1594 {
1595 int in_range = 0;
1596 int cur_reg = -1;
a737bd4d 1597
c19d1205
ZW		 1598 str++;
1599 do
1600 {
1601 int reg;
6057a28f 1602
dcbf9037 1603 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
c19d1205 1604 {
dcbf9037 1605 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
c19d1205
ZW		 1606 return FAIL;
1607 }
a737bd4d 1608
c19d1205
ZW		 1609 if (in_range)
1610 {
1611 int i;
a737bd4d 1612
c19d1205
ZW		 1613 if (reg <= cur_reg)
1614 {
dcbf9037 1615 first_error (_("bad range in register list"));
c19d1205
ZW		 1616 return FAIL;
1617 }
40a18ebd 1618
c19d1205
ZW		 1619 for (i = cur_reg + 1; i < reg; i++)
1620 {
1621 if (range & (1 << i))
1622 as_tsktsk
1623 (_("Warning: duplicated register (r%d) in register list"),
1624 i);
1625 else
1626 range |= 1 << i;
1627 }
1628 in_range = 0;
1629 }
a737bd4d 1630
c19d1205
ZW		 1631 if (range & (1 << reg))
1632 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1633 reg);
1634 else if (reg <= cur_reg)
1635 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1636
c19d1205
ZW		 1637 range |= 1 << reg;
1638 cur_reg = reg;
1639 }
1640 while (skip_past_comma (&str) != FAIL
1641 || (in_range = 1, *str++ == '-'));
1642 str--;
a737bd4d 1643
d996d970 1644 if (skip_past_char (&str, '}') == FAIL)
c19d1205 1645 {
dcbf9037 1646 first_error (_("missing `}'"));
c19d1205
ZW		 1647 return FAIL;
1648 }
1649 }
1650 else
1651 {
91d6fa6a 1652 expressionS exp;
40a18ebd 1653
91d6fa6a 1654 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1655 return FAIL;
40a18ebd 1656
91d6fa6a 1657 if (exp.X_op == O_constant)
c19d1205 1658 {
91d6fa6a
NC		 1659 if (exp.X_add_number
1660 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW		 1661 {
1662 inst.error = _("invalid register mask");
1663 return FAIL;
1664 }
a737bd4d 1665
91d6fa6a 1666 if ((range & exp.X_add_number) != 0)
c19d1205 1667 {
91d6fa6a 1668 int regno = range & exp.X_add_number;
a737bd4d 1669
c19d1205
ZW		 1670 regno &= -regno;
1671 regno = (1 << regno) - 1;
1672 as_tsktsk
1673 (_("Warning: duplicated register (r%d) in register list"),
1674 regno);
1675 }
a737bd4d 1676
91d6fa6a 1677 range |= exp.X_add_number;
c19d1205
ZW		 1678 }
1679 else
1680 {
1681 if (inst.reloc.type != 0)
1682 {
1683 inst.error = _("expression too complex");
1684 return FAIL;
1685 }
a737bd4d 1686
91d6fa6a 1687 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
c19d1205
ZW		 1688 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1689 inst.reloc.pc_rel = 0;
1690 }
1691 }
a737bd4d 1692
c19d1205
ZW		 1693 if (*str == '|' || *str == '+')
1694 {
1695 str++;
1696 another_range = 1;
1697 }
a737bd4d 1698 }
c19d1205 1699 while (another_range);
a737bd4d 1700
c19d1205
ZW		 1701 *strp = str;
1702 return range;
a737bd4d
NC		 1703}
1704
5287ad62
JB		 1705/* Types of registers in a list. */
1706
1707enum reg_list_els
1708{
1709 REGLIST_VFP_S,
1710 REGLIST_VFP_D,
1711 REGLIST_NEON_D
1712};
1713
c19d1205
ZW		 1714/* Parse a VFP register list. If the string is invalid return FAIL.
1715 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB		 1716 register. Parses registers of type ETYPE.
1717 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1718 - Q registers can be used to specify pairs of D registers
1719 - { } can be omitted from around a singleton register list
477330fc
RM		 1720 FIXME: This is not implemented, as it would require backtracking in
1721 some cases, e.g.:
1722 vtbl.8 d3,d4,d5
1723 This could be done (the meaning isn't really ambiguous), but doesn't
1724 fit in well with the current parsing framework.
dcbf9037
JB		 1725 - 32 D registers may be used (also true for VFPv3).
1726 FIXME: Types are ignored in these register lists, which is probably a
1727 bug. */
6057a28f 1728
c19d1205 1729static int
037e8744 1730parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
6057a28f 1731{
037e8744 1732 char *str = *ccp;
c19d1205
ZW		 1733 int base_reg;
1734 int new_base;
21d799b5 1735 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 1736 int max_regs = 0;
c19d1205
ZW		 1737 int count = 0;
1738 int warned = 0;
1739 unsigned long mask = 0;
a737bd4d 1740 int i;
6057a28f 1741
477330fc 1742 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB		 1743 {
1744 inst.error = _("expecting {");
1745 return FAIL;
1746 }
6057a28f 1747
5287ad62 1748 switch (etype)
c19d1205 1749 {
5287ad62 1750 case REGLIST_VFP_S:
c19d1205
ZW		 1751 regtype = REG_TYPE_VFS;
1752 max_regs = 32;
5287ad62 1753 break;
5f4273c7 1754
5287ad62
JB		 1755 case REGLIST_VFP_D:
1756 regtype = REG_TYPE_VFD;
b7fc2769 1757 break;
5f4273c7 1758
b7fc2769
JB		 1759 case REGLIST_NEON_D:
1760 regtype = REG_TYPE_NDQ;
1761 break;
1762 }
1763
1764 if (etype != REGLIST_VFP_S)
1765 {
b1cc4aeb
PB		 1766 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1767 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 1768 {
1769 max_regs = 32;
1770 if (thumb_mode)
1771 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1772 fpu_vfp_ext_d32);
1773 else
1774 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1775 fpu_vfp_ext_d32);
1776 }
5287ad62 1777 else
477330fc 1778 max_regs = 16;
c19d1205 1779 }
6057a28f 1780
c19d1205 1781 base_reg = max_regs;
a737bd4d 1782
c19d1205
ZW		 1783 do
1784 {
5287ad62 1785 int setmask = 1, addregs = 1;
dcbf9037 1786
037e8744 1787 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 1788
c19d1205 1789 if (new_base == FAIL)
a737bd4d 1790 {
dcbf9037 1791 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW		 1792 return FAIL;
1793 }
5f4273c7 1794
b7fc2769 1795 if (new_base >= max_regs)
477330fc
RM		 1796 {
1797 first_error (_("register out of range in list"));
1798 return FAIL;
1799 }
5f4273c7 1800
5287ad62
JB		 1801 /* Note: a value of 2 * n is returned for the register Q<n>. */
1802 if (regtype == REG_TYPE_NQ)
477330fc
RM		 1803 {
1804 setmask = 3;
1805 addregs = 2;
1806 }
5287ad62 1807
c19d1205
ZW		 1808 if (new_base < base_reg)
1809 base_reg = new_base;
a737bd4d 1810
5287ad62 1811 if (mask & (setmask << new_base))
c19d1205 1812 {
dcbf9037 1813 first_error (_("invalid register list"));
c19d1205 1814 return FAIL;
a737bd4d 1815 }
a737bd4d 1816
c19d1205
ZW		 1817 if ((mask >> new_base) != 0 && ! warned)
1818 {
1819 as_tsktsk (_("register list not in ascending order"));
1820 warned = 1;
1821 }
0bbf2aa4 1822
5287ad62
JB		 1823 mask |= setmask << new_base;
1824 count += addregs;
0bbf2aa4 1825
037e8744 1826 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW		 1827 {
1828 int high_range;
0bbf2aa4 1829
037e8744 1830 str++;
0bbf2aa4 1831
037e8744 1832 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 1833 == FAIL)
c19d1205
ZW		 1834 {
1835 inst.error = gettext (reg_expected_msgs[regtype]);
1836 return FAIL;
1837 }
0bbf2aa4 1838
477330fc
RM		 1839 if (high_range >= max_regs)
1840 {
1841 first_error (_("register out of range in list"));
1842 return FAIL;
1843 }
b7fc2769 1844
477330fc
RM		 1845 if (regtype == REG_TYPE_NQ)
1846 high_range = high_range + 1;
5287ad62 1847
c19d1205
ZW		 1848 if (high_range <= new_base)
1849 {
1850 inst.error = _("register range not in ascending order");
1851 return FAIL;
1852 }
0bbf2aa4 1853
5287ad62 1854 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 1855 {
5287ad62 1856 if (mask & (setmask << new_base))
0bbf2aa4 1857 {
c19d1205
ZW		 1858 inst.error = _("invalid register list");
1859 return FAIL;
0bbf2aa4 1860 }
c19d1205 1861
5287ad62
JB		 1862 mask |= setmask << new_base;
1863 count += addregs;
0bbf2aa4 1864 }
0bbf2aa4 1865 }
0bbf2aa4 1866 }
037e8744 1867 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 1868
037e8744 1869 str++;
0bbf2aa4 1870
c19d1205
ZW		 1871 /* Sanity check -- should have raised a parse error above. */
1872 if (count == 0 || count > max_regs)
1873 abort ();
1874
1875 *pbase = base_reg;
1876
1877 /* Final test -- the registers must be consecutive. */
1878 mask >>= base_reg;
1879 for (i = 0; i < count; i++)
1880 {
1881 if ((mask & (1u << i)) == 0)
1882 {
1883 inst.error = _("non-contiguous register range");
1884 return FAIL;
1885 }
1886 }
1887
037e8744
JB		 1888 *ccp = str;
1889
c19d1205 1890 return count;
b99bd4ef
NC		 1891}
1892
dcbf9037
JB		 1893/* True if two alias types are the same. */
1894
c921be7d 1895static bfd_boolean
dcbf9037
JB		 1896neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1897{
1898 if (!a && !b)
c921be7d 1899 return TRUE;
5f4273c7 1900
dcbf9037 1901 if (!a || !b)
c921be7d 1902 return FALSE;
dcbf9037
JB		 1903
1904 if (a->defined != b->defined)
c921be7d 1905 return FALSE;
5f4273c7 1906
dcbf9037
JB		 1907 if ((a->defined & NTA_HASTYPE) != 0
1908 && (a->eltype.type != b->eltype.type
477330fc 1909 || a->eltype.size != b->eltype.size))
c921be7d 1910 return FALSE;
dcbf9037
JB		 1911
1912 if ((a->defined & NTA_HASINDEX) != 0
1913 && (a->index != b->index))
c921be7d 1914 return FALSE;
5f4273c7 1915
c921be7d 1916 return TRUE;
dcbf9037
JB		 1917}
1918
5287ad62
JB		 1919/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1920 The base register is put in *PBASE.
dcbf9037 1921 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB		 1922 the return value.
1923 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB		 1924 Bits [6:5] encode the list length (minus one).
1925 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 1926
5287ad62 1927#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 1928#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB		 1929#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1930
1931static int
dcbf9037 1932parse_neon_el_struct_list (char **str, unsigned *pbase,
477330fc 1933 struct neon_type_el *eltype)
5287ad62
JB		 1934{
1935 char *ptr = *str;
1936 int base_reg = -1;
1937 int reg_incr = -1;
1938 int count = 0;
1939 int lane = -1;
1940 int leading_brace = 0;
1941 enum arm_reg_type rtype = REG_TYPE_NDQ;
20203fb9
NC		 1942 const char *const incr_error = _("register stride must be 1 or 2");
1943 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 1944 struct neon_typed_alias firsttype;
5f4273c7 1945
5287ad62
JB		 1946 if (skip_past_char (&ptr, '{') == SUCCESS)
1947 leading_brace = 1;
5f4273c7 1948
5287ad62
JB		 1949 do
1950 {
dcbf9037
JB		 1951 struct neon_typed_alias atype;
1952 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1953
5287ad62 1954 if (getreg == FAIL)
477330fc
RM		 1955 {
1956 first_error (_(reg_expected_msgs[rtype]));
1957 return FAIL;
1958 }
5f4273c7 1959
5287ad62 1960 if (base_reg == -1)
477330fc
RM		 1961 {
1962 base_reg = getreg;
1963 if (rtype == REG_TYPE_NQ)
1964 {
1965 reg_incr = 1;
1966 }
1967 firsttype = atype;
1968 }
5287ad62 1969 else if (reg_incr == -1)
477330fc
RM		 1970 {
1971 reg_incr = getreg - base_reg;
1972 if (reg_incr < 1 || reg_incr > 2)
1973 {
1974 first_error (_(incr_error));
1975 return FAIL;
1976 }
1977 }
5287ad62 1978 else if (getreg != base_reg + reg_incr * count)
477330fc
RM		 1979 {
1980 first_error (_(incr_error));
1981 return FAIL;
1982 }
dcbf9037 1983
c921be7d 1984 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM		 1985 {
1986 first_error (_(type_error));
1987 return FAIL;
1988 }
5f4273c7 1989
5287ad62 1990 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 1991 modes. */
5287ad62 1992 if (ptr[0] == '-')
477330fc
RM		 1993 {
1994 struct neon_typed_alias htype;
1995 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
1996 if (lane == -1)
1997 lane = NEON_INTERLEAVE_LANES;
1998 else if (lane != NEON_INTERLEAVE_LANES)
1999 {
2000 first_error (_(type_error));
2001 return FAIL;
2002 }
2003 if (reg_incr == -1)
2004 reg_incr = 1;
2005 else if (reg_incr != 1)
2006 {
2007 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2008 return FAIL;
2009 }
2010 ptr++;
2011 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2012 if (hireg == FAIL)
2013 {
2014 first_error (_(reg_expected_msgs[rtype]));
2015 return FAIL;
2016 }
2017 if (! neon_alias_types_same (&htype, &firsttype))
2018 {
2019 first_error (_(type_error));
2020 return FAIL;
2021 }
2022 count += hireg + dregs - getreg;
2023 continue;
2024 }
5f4273c7 2025
5287ad62
JB		 2026 /* If we're using Q registers, we can't use [] or [n] syntax. */
2027 if (rtype == REG_TYPE_NQ)
477330fc
RM		 2028 {
2029 count += 2;
2030 continue;
2031 }
5f4273c7 2032
dcbf9037 2033 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 2034 {
2035 if (lane == -1)
2036 lane = atype.index;
2037 else if (lane != atype.index)
2038 {
2039 first_error (_(type_error));
2040 return FAIL;
2041 }
2042 }
5287ad62 2043 else if (lane == -1)
477330fc 2044 lane = NEON_INTERLEAVE_LANES;
5287ad62 2045 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM		 2046 {
2047 first_error (_(type_error));
2048 return FAIL;
2049 }
5287ad62
JB		 2050 count++;
2051 }
2052 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2053
5287ad62
JB		 2054 /* No lane set by [x]. We must be interleaving structures. */
2055 if (lane == -1)
2056 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2057
5287ad62
JB		 2058 /* Sanity check. */
2059 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2060 || (count > 1 && reg_incr == -1))
2061 {
dcbf9037 2062 first_error (_("error parsing element/structure list"));
5287ad62
JB		 2063 return FAIL;
2064 }
2065
2066 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2067 {
dcbf9037 2068 first_error (_("expected }"));
5287ad62
JB		 2069 return FAIL;
2070 }
5f4273c7 2071
5287ad62
JB		 2072 if (reg_incr == -1)
2073 reg_incr = 1;
2074
dcbf9037
JB		 2075 if (eltype)
2076 *eltype = firsttype.eltype;
2077
5287ad62
JB		 2078 *pbase = base_reg;
2079 *str = ptr;
5f4273c7 2080
5287ad62
JB		 2081 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2082}
2083
c19d1205
ZW		 2084/* Parse an explicit relocation suffix on an expression. This is
2085 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2086 arm_reloc_hsh contains no entries, so this function can only
2087 succeed if there is no () after the word. Returns -1 on error,
2088 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2089
c19d1205
ZW		 2090static int
2091parse_reloc (char **str)
b99bd4ef 2092{
c19d1205
ZW		 2093 struct reloc_entry *r;
2094 char *p, *q;
b99bd4ef 2095
c19d1205
ZW		 2096 if (**str != '(')
2097 return BFD_RELOC_UNUSED;
b99bd4ef 2098
c19d1205
ZW		 2099 p = *str + 1;
2100 q = p;
2101
2102 while (*q && *q != ')' && *q != ',')
2103 q++;
2104 if (*q != ')')
2105 return -1;
2106
21d799b5
NC		 2107 if ((r = (struct reloc_entry *)
2108 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW		 2109 return -1;
2110
2111 *str = q + 1;
2112 return r->reloc;
b99bd4ef
NC		 2113}
2114
c19d1205
ZW		 2115/* Directives: register aliases. */
2116
dcbf9037 2117static struct reg_entry *
90ec0d68 2118insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2119{
d3ce72d0 2120 struct reg_entry *new_reg;
c19d1205 2121 const char *name;
b99bd4ef 2122
d3ce72d0 2123 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2124 {
d3ce72d0 2125 if (new_reg->builtin)
c19d1205 2126 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2127
c19d1205
ZW		 2128 /* Only warn about a redefinition if it's not defined as the
2129 same register. */
d3ce72d0 2130 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2131 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2132
d929913e 2133 return NULL;
c19d1205 2134 }
b99bd4ef 2135
c19d1205 2136 name = xstrdup (str);
d3ce72d0 2137 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
b99bd4ef 2138
d3ce72d0
NC		 2139 new_reg->name = name;
2140 new_reg->number = number;
2141 new_reg->type = type;
2142 new_reg->builtin = FALSE;
2143 new_reg->neon = NULL;
b99bd4ef 2144
d3ce72d0 2145 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2146 abort ();
5f4273c7 2147
d3ce72d0 2148 return new_reg;
dcbf9037
JB		 2149}
2150
2151static void
2152insert_neon_reg_alias (char *str, int number, int type,
477330fc 2153 struct neon_typed_alias *atype)
dcbf9037
JB		 2154{
2155 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2156
dcbf9037
JB		 2157 if (!reg)
2158 {
2159 first_error (_("attempt to redefine typed alias"));
2160 return;
2161 }
5f4273c7 2162
dcbf9037
JB		 2163 if (atype)
2164 {
21d799b5 2165 reg->neon = (struct neon_typed_alias *)
477330fc 2166 xmalloc (sizeof (struct neon_typed_alias));
dcbf9037
JB		 2167 *reg->neon = *atype;
2168 }
c19d1205 2169}
b99bd4ef 2170
c19d1205 2171/* Look for the .req directive. This is of the form:
b99bd4ef 2172
c19d1205 2173 new_register_name .req existing_register_name
b99bd4ef 2174
c19d1205 2175 If we find one, or if it looks sufficiently like one that we want to
d929913e 2176 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2177
d929913e 2178static bfd_boolean
c19d1205
ZW		 2179create_register_alias (char * newname, char *p)
2180{
2181 struct reg_entry *old;
2182 char *oldname, *nbuf;
2183 size_t nlen;
b99bd4ef 2184
c19d1205
ZW		 2185 /* The input scrubber ensures that whitespace after the mnemonic is
2186 collapsed to single spaces. */
2187 oldname = p;
2188 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2189 return FALSE;
b99bd4ef 2190
c19d1205
ZW		 2191 oldname += 6;
2192 if (*oldname == '\0')
d929913e 2193 return FALSE;
b99bd4ef 2194
21d799b5 2195 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2196 if (!old)
b99bd4ef 2197 {
c19d1205 2198 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2199 return TRUE;
b99bd4ef
NC		 2200 }
2201
c19d1205
ZW		 2202 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2203 the desired alias name, and p points to its end. If not, then
2204 the desired alias name is in the global original_case_string. */
2205#ifdef TC_CASE_SENSITIVE
2206 nlen = p - newname;
2207#else
2208 newname = original_case_string;
2209 nlen = strlen (newname);
2210#endif
b99bd4ef 2211
21d799b5 2212 nbuf = (char *) alloca (nlen + 1);
c19d1205
ZW		 2213 memcpy (nbuf, newname, nlen);
2214 nbuf[nlen] = '\0';
b99bd4ef 2215
c19d1205
ZW		 2216 /* Create aliases under the new name as stated; an all-lowercase
2217 version of the new name; and an all-uppercase version of the new
2218 name. */
d929913e
NC		 2219 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2220 {
2221 for (p = nbuf; *p; p++)
2222 *p = TOUPPER (*p);
c19d1205 2223
d929913e
NC		 2224 if (strncmp (nbuf, newname, nlen))
2225 {
2226 /* If this attempt to create an additional alias fails, do not bother
2227 trying to create the all-lower case alias. We will fail and issue
2228 a second, duplicate error message. This situation arises when the
2229 programmer does something like:
2230 foo .req r0
2231 Foo .req r1
2232 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2233 the artificial FOO alias because it has already been created by the
d929913e
NC		 2234 first .req. */
2235 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2236 return TRUE;
2237 }
c19d1205 2238
d929913e
NC		 2239 for (p = nbuf; *p; p++)
2240 *p = TOLOWER (*p);
c19d1205 2241
d929913e
NC		 2242 if (strncmp (nbuf, newname, nlen))
2243 insert_reg_alias (nbuf, old->number, old->type);
2244 }
c19d1205 2245
d929913e 2246 return TRUE;
b99bd4ef
NC		 2247}
2248
dcbf9037
JB		 2249/* Create a Neon typed/indexed register alias using directives, e.g.:
2250 X .dn d5.s32[1]
2251 Y .qn 6.s16
2252 Z .dn d7
2253 T .dn Z[0]
2254 These typed registers can be used instead of the types specified after the
2255 Neon mnemonic, so long as all operands given have types. Types can also be
2256 specified directly, e.g.:
5f4273c7 2257 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2258
c921be7d 2259static bfd_boolean
dcbf9037
JB		 2260create_neon_reg_alias (char *newname, char *p)
2261{
2262 enum arm_reg_type basetype;
2263 struct reg_entry *basereg;
2264 struct reg_entry mybasereg;
2265 struct neon_type ntype;
2266 struct neon_typed_alias typeinfo;
12d6b0b7 2267 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2268 int namelen;
5f4273c7 2269
dcbf9037
JB		 2270 typeinfo.defined = 0;
2271 typeinfo.eltype.type = NT_invtype;
2272 typeinfo.eltype.size = -1;
2273 typeinfo.index = -1;
5f4273c7 2274
dcbf9037 2275 nameend = p;
5f4273c7 2276
dcbf9037
JB		 2277 if (strncmp (p, " .dn ", 5) == 0)
2278 basetype = REG_TYPE_VFD;
2279 else if (strncmp (p, " .qn ", 5) == 0)
2280 basetype = REG_TYPE_NQ;
2281 else
c921be7d 2282 return FALSE;
5f4273c7 2283
dcbf9037 2284 p += 5;
5f4273c7 2285
dcbf9037 2286 if (*p == '\0')
c921be7d 2287 return FALSE;
5f4273c7 2288
dcbf9037
JB		 2289 basereg = arm_reg_parse_multi (&p);
2290
2291 if (basereg && basereg->type != basetype)
2292 {
2293 as_bad (_("bad type for register"));
c921be7d 2294 return FALSE;
dcbf9037
JB		 2295 }
2296
2297 if (basereg == NULL)
2298 {
2299 expressionS exp;
2300 /* Try parsing as an integer. */
2301 my_get_expression (&exp, &p, GE_NO_PREFIX);
2302 if (exp.X_op != O_constant)
477330fc
RM		 2303 {
2304 as_bad (_("expression must be constant"));
2305 return FALSE;
2306 }
dcbf9037
JB		 2307 basereg = &mybasereg;
2308 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2309 : exp.X_add_number;
dcbf9037
JB		 2310 basereg->neon = 0;
2311 }
2312
2313 if (basereg->neon)
2314 typeinfo = *basereg->neon;
2315
2316 if (parse_neon_type (&ntype, &p) == SUCCESS)
2317 {
2318 /* We got a type. */
2319 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM		 2320 {
2321 as_bad (_("can't redefine the type of a register alias"));
2322 return FALSE;
2323 }
5f4273c7 2324
dcbf9037
JB		 2325 typeinfo.defined |= NTA_HASTYPE;
2326 if (ntype.elems != 1)
477330fc
RM		 2327 {
2328 as_bad (_("you must specify a single type only"));
2329 return FALSE;
2330 }
dcbf9037
JB		 2331 typeinfo.eltype = ntype.el[0];
2332 }
5f4273c7 2333
dcbf9037
JB		 2334 if (skip_past_char (&p, '[') == SUCCESS)
2335 {
2336 expressionS exp;
2337 /* We got a scalar index. */
5f4273c7 2338
dcbf9037 2339 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM		 2340 {
2341 as_bad (_("can't redefine the index of a scalar alias"));
2342 return FALSE;
2343 }
5f4273c7 2344
dcbf9037 2345 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2346
dcbf9037 2347 if (exp.X_op != O_constant)
477330fc
RM		 2348 {
2349 as_bad (_("scalar index must be constant"));
2350 return FALSE;
2351 }
5f4273c7 2352
dcbf9037
JB		 2353 typeinfo.defined |= NTA_HASINDEX;
2354 typeinfo.index = exp.X_add_number;
5f4273c7 2355
dcbf9037 2356 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM		 2357 {
2358 as_bad (_("expecting ]"));
2359 return FALSE;
2360 }
dcbf9037
JB		 2361 }
2362
15735687
NS		 2363 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2364 the desired alias name, and p points to its end. If not, then
2365 the desired alias name is in the global original_case_string. */
2366#ifdef TC_CASE_SENSITIVE
dcbf9037 2367 namelen = nameend - newname;
15735687
NS		 2368#else
2369 newname = original_case_string;
2370 namelen = strlen (newname);
2371#endif
2372
21d799b5 2373 namebuf = (char *) alloca (namelen + 1);
dcbf9037
JB		 2374 strncpy (namebuf, newname, namelen);
2375 namebuf[namelen] = '\0';
5f4273c7 2376
dcbf9037 2377 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2378 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2379
dcbf9037
JB		 2380 /* Insert name in all uppercase. */
2381 for (p = namebuf; *p; p++)
2382 *p = TOUPPER (*p);
5f4273c7 2383
dcbf9037
JB		 2384 if (strncmp (namebuf, newname, namelen))
2385 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2386 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2387
dcbf9037
JB		 2388 /* Insert name in all lowercase. */
2389 for (p = namebuf; *p; p++)
2390 *p = TOLOWER (*p);
5f4273c7 2391
dcbf9037
JB		 2392 if (strncmp (namebuf, newname, namelen))
2393 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2394 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2395
c921be7d 2396 return TRUE;
dcbf9037
JB		 2397}
2398
c19d1205
ZW		 2399/* Should never be called, as .req goes between the alias and the
2400 register name, not at the beginning of the line. */
c921be7d 2401
b99bd4ef 2402static void
c19d1205 2403s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2404{
c19d1205
ZW		 2405 as_bad (_("invalid syntax for .req directive"));
2406}
b99bd4ef 2407
dcbf9037
JB		 2408static void
2409s_dn (int a ATTRIBUTE_UNUSED)
2410{
2411 as_bad (_("invalid syntax for .dn directive"));
2412}
2413
2414static void
2415s_qn (int a ATTRIBUTE_UNUSED)
2416{
2417 as_bad (_("invalid syntax for .qn directive"));
2418}
2419
c19d1205
ZW		 2420/* The .unreq directive deletes an alias which was previously defined
2421 by .req. For example:
b99bd4ef 2422
c19d1205
ZW		 2423 my_alias .req r11
2424 .unreq my_alias */
b99bd4ef
NC		 2425
2426static void
c19d1205 2427s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2428{
c19d1205
ZW		 2429 char * name;
2430 char saved_char;
b99bd4ef 2431
c19d1205
ZW		 2432 name = input_line_pointer;
2433
2434 while (*input_line_pointer != 0
2435 && *input_line_pointer != ' '
2436 && *input_line_pointer != '\n')
2437 ++input_line_pointer;
2438
2439 saved_char = *input_line_pointer;
2440 *input_line_pointer = 0;
2441
2442 if (!*name)
2443 as_bad (_("invalid syntax for .unreq directive"));
2444 else
2445 {
21d799b5 2446 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2447 name);
c19d1205
ZW		 2448
2449 if (!reg)
2450 as_bad (_("unknown register alias '%s'"), name);
2451 else if (reg->builtin)
a1727c1a 2452 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW		 2453 name);
2454 else
2455 {
d929913e
NC		 2456 char * p;
2457 char * nbuf;
2458
db0bc284 2459 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2460 free ((char *) reg->name);
477330fc
RM		 2461 if (reg->neon)
2462 free (reg->neon);
c19d1205 2463 free (reg);
d929913e
NC		 2464
2465 /* Also locate the all upper case and all lower case versions.
2466 Do not complain if we cannot find one or the other as it
2467 was probably deleted above. */
5f4273c7 2468
d929913e
NC		 2469 nbuf = strdup (name);
2470 for (p = nbuf; *p; p++)
2471 *p = TOUPPER (*p);
21d799b5 2472 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2473 if (reg)
2474 {
db0bc284 2475 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2476 free ((char *) reg->name);
2477 if (reg->neon)
2478 free (reg->neon);
2479 free (reg);
2480 }
2481
2482 for (p = nbuf; *p; p++)
2483 *p = TOLOWER (*p);
21d799b5 2484 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2485 if (reg)
2486 {
db0bc284 2487 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2488 free ((char *) reg->name);
2489 if (reg->neon)
2490 free (reg->neon);
2491 free (reg);
2492 }
2493
2494 free (nbuf);
c19d1205
ZW		 2495 }
2496 }
b99bd4ef 2497
c19d1205 2498 *input_line_pointer = saved_char;
b99bd4ef
NC		 2499 demand_empty_rest_of_line ();
2500}
2501
c19d1205
ZW		 2502/* Directives: Instruction set selection. */
2503
2504#ifdef OBJ_ELF
2505/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2506 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2507 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2508 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2509
cd000bff
DJ		 2510/* Create a new mapping symbol for the transition to STATE. */
2511
2512static void
2513make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2514{
a737bd4d 2515 symbolS * symbolP;
c19d1205
ZW		 2516 const char * symname;
2517 int type;
b99bd4ef 2518
c19d1205 2519 switch (state)
b99bd4ef 2520 {
c19d1205
ZW		 2521 case MAP_DATA:
2522 symname = "$d";
2523 type = BSF_NO_FLAGS;
2524 break;
2525 case MAP_ARM:
2526 symname = "$a";
2527 type = BSF_NO_FLAGS;
2528 break;
2529 case MAP_THUMB:
2530 symname = "$t";
2531 type = BSF_NO_FLAGS;
2532 break;
c19d1205
ZW		 2533 default:
2534 abort ();
2535 }
2536
cd000bff 2537 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW		 2538 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2539
2540 switch (state)
2541 {
2542 case MAP_ARM:
2543 THUMB_SET_FUNC (symbolP, 0);
2544 ARM_SET_THUMB (symbolP, 0);
2545 ARM_SET_INTERWORK (symbolP, support_interwork);
2546 break;
2547
2548 case MAP_THUMB:
2549 THUMB_SET_FUNC (symbolP, 1);
2550 ARM_SET_THUMB (symbolP, 1);
2551 ARM_SET_INTERWORK (symbolP, support_interwork);
2552 break;
2553
2554 case MAP_DATA:
2555 default:
cd000bff
DJ		 2556 break;
2557 }
2558
2559 /* Save the mapping symbols for future reference. Also check that
2560 we do not place two mapping symbols at the same offset within a
2561 frag. We'll handle overlap between frags in
2de7820f
JZ		 2562 check_mapping_symbols.
2563
2564 If .fill or other data filling directive generates zero sized data,
2565 the mapping symbol for the following code will have the same value
2566 as the one generated for the data filling directive. In this case,
2567 we replace the old symbol with the new one at the same address. */
cd000bff
DJ		 2568 if (value == 0)
2569 {
2de7820f
JZ		 2570 if (frag->tc_frag_data.first_map != NULL)
2571 {
2572 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2573 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2574 }
cd000bff
DJ		 2575 frag->tc_frag_data.first_map = symbolP;
2576 }
2577 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ		 2578 {
2579 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ		 2580 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2581 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2582 }
cd000bff
DJ		 2583 frag->tc_frag_data.last_map = symbolP;
2584}
2585
2586/* We must sometimes convert a region marked as code to data during
2587 code alignment, if an odd number of bytes have to be padded. The
2588 code mapping symbol is pushed to an aligned address. */
2589
2590static void
2591insert_data_mapping_symbol (enum mstate state,
2592 valueT value, fragS *frag, offsetT bytes)
2593{
2594 /* If there was already a mapping symbol, remove it. */
2595 if (frag->tc_frag_data.last_map != NULL
2596 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2597 {
2598 symbolS *symp = frag->tc_frag_data.last_map;
2599
2600 if (value == 0)
2601 {
2602 know (frag->tc_frag_data.first_map == symp);
2603 frag->tc_frag_data.first_map = NULL;
2604 }
2605 frag->tc_frag_data.last_map = NULL;
2606 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2607 }
cd000bff
DJ		 2608
2609 make_mapping_symbol (MAP_DATA, value, frag);
2610 make_mapping_symbol (state, value + bytes, frag);
2611}
2612
2613static void mapping_state_2 (enum mstate state, int max_chars);
2614
2615/* Set the mapping state to STATE. Only call this when about to
2616 emit some STATE bytes to the file. */
2617
2618void
2619mapping_state (enum mstate state)
2620{
940b5ce0
DJ		 2621 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2622
cd000bff
DJ		 2623#define TRANSITION(from, to) (mapstate == (from) && state == (to))
2624
2625 if (mapstate == state)
2626 /* The mapping symbol has already been emitted.
2627 There is nothing else to do. */
2628 return;
49c62a33
NC		 2629
2630 if (state == MAP_ARM || state == MAP_THUMB)
2631 /* PR gas/12931
2632 All ARM instructions require 4-byte alignment.
2633 (Almost) all Thumb instructions require 2-byte alignment.
2634
2635 When emitting instructions into any section, mark the section
2636 appropriately.
2637
2638 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2639 but themselves require 2-byte alignment; this applies to some
2640 PC- relative forms. However, these cases will invovle implicit
2641 literal pool generation or an explicit .align >=2, both of
2642 which will cause the section to me marked with sufficient
2643 alignment. Thus, we don't handle those cases here. */
2644 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2645
2646 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
cd000bff
DJ		 2647 /* This case will be evaluated later in the next else. */
2648 return;
2649 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
477330fc 2650 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
cd000bff
DJ		 2651 {
2652 /* Only add the symbol if the offset is > 0:
477330fc
RM		 2653 if we're at the first frag, check it's size > 0;
2654 if we're not at the first frag, then for sure
2655 the offset is > 0. */
cd000bff
DJ		 2656 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2657 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2658
2659 if (add_symbol)
477330fc 2660 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
cd000bff
DJ		 2661 }
2662
2663 mapping_state_2 (state, 0);
2664#undef TRANSITION
2665}
2666
2667/* Same as mapping_state, but MAX_CHARS bytes have already been
2668 allocated. Put the mapping symbol that far back. */
2669
2670static void
2671mapping_state_2 (enum mstate state, int max_chars)
2672{
940b5ce0
DJ		 2673 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2674
2675 if (!SEG_NORMAL (now_seg))
2676 return;
2677
cd000bff
DJ		 2678 if (mapstate == state)
2679 /* The mapping symbol has already been emitted.
2680 There is nothing else to do. */
2681 return;
2682
cd000bff
DJ		 2683 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2684 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205
ZW		 2685}
2686#else
d3106081
NS		 2687#define mapping_state(x) ((void)0)
2688#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW		 2689#endif
2690
2691/* Find the real, Thumb encoded start of a Thumb function. */
2692
4343666d 2693#ifdef OBJ_COFF
c19d1205
ZW		 2694static symbolS *
2695find_real_start (symbolS * symbolP)
2696{
2697 char * real_start;
2698 const char * name = S_GET_NAME (symbolP);
2699 symbolS * new_target;
2700
2701 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2702#define STUB_NAME ".real_start_of"
2703
2704 if (name == NULL)
2705 abort ();
2706
37f6032b
ZW		 2707 /* The compiler may generate BL instructions to local labels because
2708 it needs to perform a branch to a far away location. These labels
2709 do not have a corresponding ".real_start_of" label. We check
2710 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2711 the ".real_start_of" convention for nonlocal branches. */
2712 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW		 2713 return symbolP;
2714
37f6032b 2715 real_start = ACONCAT ((STUB_NAME, name, NULL));
c19d1205
ZW		 2716 new_target = symbol_find (real_start);
2717
2718 if (new_target == NULL)
2719 {
bd3ba5d1 2720 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW		 2721 new_target = symbolP;
2722 }
2723
c19d1205
ZW		 2724 return new_target;
2725}
4343666d 2726#endif
c19d1205
ZW		 2727
2728static void
2729opcode_select (int width)
2730{
2731 switch (width)
2732 {
2733 case 16:
2734 if (! thumb_mode)
2735 {
e74cfd16 2736 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW		 2737 as_bad (_("selected processor does not support THUMB opcodes"));
2738
2739 thumb_mode = 1;
2740 /* No need to force the alignment, since we will have been
2741 coming from ARM mode, which is word-aligned. */
2742 record_alignment (now_seg, 1);
2743 }
c19d1205
ZW		 2744 break;
2745
2746 case 32:
2747 if (thumb_mode)
2748 {
e74cfd16 2749 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW		 2750 as_bad (_("selected processor does not support ARM opcodes"));
2751
2752 thumb_mode = 0;
2753
2754 if (!need_pass_2)
2755 frag_align (2, 0, 0);
2756
2757 record_alignment (now_seg, 1);
2758 }
c19d1205
ZW		 2759 break;
2760
2761 default:
2762 as_bad (_("invalid instruction size selected (%d)"), width);
2763 }
2764}
2765
2766static void
2767s_arm (int ignore ATTRIBUTE_UNUSED)
2768{
2769 opcode_select (32);
2770 demand_empty_rest_of_line ();
2771}
2772
2773static void
2774s_thumb (int ignore ATTRIBUTE_UNUSED)
2775{
2776 opcode_select (16);
2777 demand_empty_rest_of_line ();
2778}
2779
2780static void
2781s_code (int unused ATTRIBUTE_UNUSED)
2782{
2783 int temp;
2784
2785 temp = get_absolute_expression ();
2786 switch (temp)
2787 {
2788 case 16:
2789 case 32:
2790 opcode_select (temp);
2791 break;
2792
2793 default:
2794 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2795 }
2796}
2797
2798static void
2799s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2800{
2801 /* If we are not already in thumb mode go into it, EVEN if
2802 the target processor does not support thumb instructions.
2803 This is used by gcc/config/arm/lib1funcs.asm for example
2804 to compile interworking support functions even if the
2805 target processor should not support interworking. */
2806 if (! thumb_mode)
2807 {
2808 thumb_mode = 2;
2809 record_alignment (now_seg, 1);
2810 }
2811
2812 demand_empty_rest_of_line ();
2813}
2814
2815static void
2816s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2817{
2818 s_thumb (0);
2819
2820 /* The following label is the name/address of the start of a Thumb function.
2821 We need to know this for the interworking support. */
2822 label_is_thumb_function_name = TRUE;
2823}
2824
2825/* Perform a .set directive, but also mark the alias as
2826 being a thumb function. */
2827
2828static void
2829s_thumb_set (int equiv)
2830{
2831 /* XXX the following is a duplicate of the code for s_set() in read.c
2832 We cannot just call that code as we need to get at the symbol that
2833 is created. */
2834 char * name;
2835 char delim;
2836 char * end_name;
2837 symbolS * symbolP;
2838
2839 /* Especial apologies for the random logic:
2840 This just grew, and could be parsed much more simply!
2841 Dean - in haste. */
2842 name = input_line_pointer;
2843 delim = get_symbol_end ();
2844 end_name = input_line_pointer;
2845 *end_name = delim;
2846
2847 if (*input_line_pointer != ',')
2848 {
2849 *end_name = 0;
2850 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC		 2851 *end_name = delim;
2852 ignore_rest_of_line ();
2853 return;
2854 }
2855
2856 input_line_pointer++;
2857 *end_name = 0;
2858
2859 if (name[0] == '.' && name[1] == '\0')
2860 {
2861 /* XXX - this should not happen to .thumb_set. */
2862 abort ();
2863 }
2864
2865 if ((symbolP = symbol_find (name)) == NULL
2866 && (symbolP = md_undefined_symbol (name)) == NULL)
2867 {
2868#ifndef NO_LISTING
2869 /* When doing symbol listings, play games with dummy fragments living
2870 outside the normal fragment chain to record the file and line info
c19d1205 2871 for this symbol. */
b99bd4ef
NC		 2872 if (listing & LISTING_SYMBOLS)
2873 {
2874 extern struct list_info_struct * listing_tail;
21d799b5 2875 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC		 2876
2877 memset (dummy_frag, 0, sizeof (fragS));
2878 dummy_frag->fr_type = rs_fill;
2879 dummy_frag->line = listing_tail;
2880 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2881 dummy_frag->fr_symbol = symbolP;
2882 }
2883 else
2884#endif
2885 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2886
2887#ifdef OBJ_COFF
2888 /* "set" symbols are local unless otherwise specified. */
2889 SF_SET_LOCAL (symbolP);
2890#endif /* OBJ_COFF */
2891 } /* Make a new symbol. */
2892
2893 symbol_table_insert (symbolP);
2894
2895 * end_name = delim;
2896
2897 if (equiv
2898 && S_IS_DEFINED (symbolP)
2899 && S_GET_SEGMENT (symbolP) != reg_section)
2900 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2901
2902 pseudo_set (symbolP);
2903
2904 demand_empty_rest_of_line ();
2905
c19d1205 2906 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC		 2907
2908 THUMB_SET_FUNC (symbolP, 1);
2909 ARM_SET_THUMB (symbolP, 1);
2910#if defined OBJ_ELF || defined OBJ_COFF
2911 ARM_SET_INTERWORK (symbolP, support_interwork);
2912#endif
2913}
2914
c19d1205 2915/* Directives: Mode selection. */
b99bd4ef 2916
c19d1205
ZW		 2917/* .syntax [unified|divided] - choose the new unified syntax
2918 (same for Arm and Thumb encoding, modulo slight differences in what
2919 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 2920static void
c19d1205 2921s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2922{
c19d1205
ZW		 2923 char *name, delim;
2924
2925 name = input_line_pointer;
2926 delim = get_symbol_end ();
2927
2928 if (!strcasecmp (name, "unified"))
2929 unified_syntax = TRUE;
2930 else if (!strcasecmp (name, "divided"))
2931 unified_syntax = FALSE;
2932 else
2933 {
2934 as_bad (_("unrecognized syntax mode \"%s\""), name);
2935 return;
2936 }
2937 *input_line_pointer = delim;
b99bd4ef
NC		 2938 demand_empty_rest_of_line ();
2939}
2940
c19d1205
ZW		 2941/* Directives: sectioning and alignment. */
2942
2943/* Same as s_align_ptwo but align 0 => align 2. */
2944
b99bd4ef 2945static void
c19d1205 2946s_align (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2947{
a737bd4d 2948 int temp;
dce323d1 2949 bfd_boolean fill_p;
c19d1205
ZW		 2950 long temp_fill;
2951 long max_alignment = 15;
b99bd4ef
NC		 2952
2953 temp = get_absolute_expression ();
c19d1205
ZW		 2954 if (temp > max_alignment)
2955 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2956 else if (temp < 0)
b99bd4ef 2957 {
c19d1205
ZW		 2958 as_bad (_("alignment negative. 0 assumed."));
2959 temp = 0;
2960 }
b99bd4ef 2961
c19d1205
ZW		 2962 if (*input_line_pointer == ',')
2963 {
2964 input_line_pointer++;
2965 temp_fill = get_absolute_expression ();
dce323d1 2966 fill_p = TRUE;
b99bd4ef 2967 }
c19d1205 2968 else
dce323d1
PB		 2969 {
2970 fill_p = FALSE;
2971 temp_fill = 0;
2972 }
b99bd4ef 2973
c19d1205
ZW		 2974 if (!temp)
2975 temp = 2;
b99bd4ef 2976
c19d1205
ZW		 2977 /* Only make a frag if we HAVE to. */
2978 if (temp && !need_pass_2)
dce323d1
PB		 2979 {
2980 if (!fill_p && subseg_text_p (now_seg))
2981 frag_align_code (temp, 0);
2982 else
2983 frag_align (temp, (int) temp_fill, 0);
2984 }
c19d1205
ZW		 2985 demand_empty_rest_of_line ();
2986
2987 record_alignment (now_seg, temp);
b99bd4ef
NC		 2988}
2989
c19d1205
ZW		 2990static void
2991s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 2992{
c19d1205
ZW		 2993 /* We don't support putting frags in the BSS segment, we fake it by
2994 marking in_bss, then looking at s_skip for clues. */
2995 subseg_set (bss_section, 0);
2996 demand_empty_rest_of_line ();
cd000bff
DJ		 2997
2998#ifdef md_elf_section_change_hook
2999 md_elf_section_change_hook ();
3000#endif
c19d1205 3001}
b99bd4ef 3002
c19d1205
ZW		 3003static void
3004s_even (int ignore ATTRIBUTE_UNUSED)
3005{
3006 /* Never make frag if expect extra pass. */
3007 if (!need_pass_2)
3008 frag_align (1, 0, 0);
b99bd4ef 3009
c19d1205 3010 record_alignment (now_seg, 1);
b99bd4ef 3011
c19d1205 3012 demand_empty_rest_of_line ();
b99bd4ef
NC		 3013}
3014
c19d1205 3015/* Directives: Literal pools. */
a737bd4d 3016
c19d1205
ZW		 3017static literal_pool *
3018find_literal_pool (void)
a737bd4d 3019{
c19d1205 3020 literal_pool * pool;
a737bd4d 3021
c19d1205 3022 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3023 {
c19d1205
ZW		 3024 if (pool->section == now_seg
3025 && pool->sub_section == now_subseg)
3026 break;
a737bd4d
NC		 3027 }
3028
c19d1205 3029 return pool;
a737bd4d
NC		 3030}
3031
c19d1205
ZW		 3032static literal_pool *
3033find_or_make_literal_pool (void)
a737bd4d 3034{
c19d1205
ZW		 3035 /* Next literal pool ID number. */
3036 static unsigned int latest_pool_num = 1;
3037 literal_pool * pool;
a737bd4d 3038
c19d1205 3039 pool = find_literal_pool ();
a737bd4d 3040
c19d1205 3041 if (pool == NULL)
a737bd4d 3042 {
c19d1205 3043 /* Create a new pool. */
21d799b5 3044 pool = (literal_pool *) xmalloc (sizeof (* pool));
c19d1205
ZW		 3045 if (! pool)
3046 return NULL;
a737bd4d 3047
c19d1205
ZW		 3048 pool->next_free_entry = 0;
3049 pool->section = now_seg;
3050 pool->sub_section = now_subseg;
3051 pool->next = list_of_pools;
3052 pool->symbol = NULL;
3053
3054 /* Add it to the list. */
3055 list_of_pools = pool;
a737bd4d 3056 }
a737bd4d 3057
c19d1205
ZW		 3058 /* New pools, and emptied pools, will have a NULL symbol. */
3059 if (pool->symbol == NULL)
a737bd4d 3060 {
c19d1205
ZW		 3061 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3062 (valueT) 0, &zero_address_frag);
3063 pool->id = latest_pool_num ++;
a737bd4d
NC		 3064 }
3065
c19d1205
ZW		 3066 /* Done. */
3067 return pool;
a737bd4d
NC		 3068}
3069
c19d1205 3070/* Add the literal in the global 'inst'
5f4273c7 3071 structure to the relevant literal pool. */
b99bd4ef
NC		 3072
3073static int
c19d1205 3074add_to_lit_pool (void)
b99bd4ef 3075{
c19d1205
ZW		 3076 literal_pool * pool;
3077 unsigned int entry;
b99bd4ef 3078
c19d1205
ZW		 3079 pool = find_or_make_literal_pool ();
3080
3081 /* Check if this literal value is already in the pool. */
3082 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3083 {
c19d1205
ZW		 3084 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3085 && (inst.reloc.exp.X_op == O_constant)
3086 && (pool->literals[entry].X_add_number
3087 == inst.reloc.exp.X_add_number)
3088 && (pool->literals[entry].X_unsigned
3089 == inst.reloc.exp.X_unsigned))
3090 break;
3091
3092 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3093 && (inst.reloc.exp.X_op == O_symbol)
3094 && (pool->literals[entry].X_add_number
3095 == inst.reloc.exp.X_add_number)
3096 && (pool->literals[entry].X_add_symbol
3097 == inst.reloc.exp.X_add_symbol)
3098 && (pool->literals[entry].X_op_symbol
3099 == inst.reloc.exp.X_op_symbol))
3100 break;
b99bd4ef
NC		 3101 }
3102
c19d1205
ZW		 3103 /* Do we need to create a new entry? */
3104 if (entry == pool->next_free_entry)
3105 {
3106 if (entry >= MAX_LITERAL_POOL_SIZE)
3107 {
3108 inst.error = _("literal pool overflow");
3109 return FAIL;
3110 }
3111
3112 pool->literals[entry] = inst.reloc.exp;
a8040cf2
NC		 3113#ifdef OBJ_ELF
3114 /* PR ld/12974: Record the location of the first source line to reference
3115 this entry in the literal pool. If it turns out during linking that the
3116 symbol does not exist we will be able to give an accurate line number for
3117 the (first use of the) missing reference. */
3118 if (debug_type == DEBUG_DWARF2)
3119 dwarf2_where (pool->locs + entry);
3120#endif
c19d1205
ZW		 3121 pool->next_free_entry += 1;
3122 }
b99bd4ef 3123
c19d1205
ZW		 3124 inst.reloc.exp.X_op = O_symbol;
3125 inst.reloc.exp.X_add_number = ((int) entry) * 4;
3126 inst.reloc.exp.X_add_symbol = pool->symbol;
b99bd4ef 3127
c19d1205 3128 return SUCCESS;
b99bd4ef
NC		 3129}
3130
c19d1205
ZW		 3131/* Can't use symbol_new here, so have to create a symbol and then at
3132 a later date assign it a value. Thats what these functions do. */
e16bb312 3133
c19d1205
ZW		 3134static void
3135symbol_locate (symbolS * symbolP,
3136 const char * name, /* It is copied, the caller can modify. */
3137 segT segment, /* Segment identifier (SEG_<something>). */
3138 valueT valu, /* Symbol value. */
3139 fragS * frag) /* Associated fragment. */
3140{
3141 unsigned int name_length;
3142 char * preserved_copy_of_name;
e16bb312 3143
c19d1205
ZW		 3144 name_length = strlen (name) + 1; /* +1 for \0. */
3145 obstack_grow (&notes, name, name_length);
21d799b5 3146 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3147
c19d1205
ZW		 3148#ifdef tc_canonicalize_symbol_name
3149 preserved_copy_of_name =
3150 tc_canonicalize_symbol_name (preserved_copy_of_name);
3151#endif
b99bd4ef 3152
c19d1205 3153 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3154
c19d1205
ZW		 3155 S_SET_SEGMENT (symbolP, segment);
3156 S_SET_VALUE (symbolP, valu);
3157 symbol_clear_list_pointers (symbolP);
b99bd4ef 3158
c19d1205 3159 symbol_set_frag (symbolP, frag);
b99bd4ef 3160
c19d1205
ZW		 3161 /* Link to end of symbol chain. */
3162 {
3163 extern int symbol_table_frozen;
b99bd4ef 3164
c19d1205
ZW		 3165 if (symbol_table_frozen)
3166 abort ();
3167 }
b99bd4ef 3168
c19d1205 3169 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3170
c19d1205 3171 obj_symbol_new_hook (symbolP);
b99bd4ef 3172
c19d1205
ZW		 3173#ifdef tc_symbol_new_hook
3174 tc_symbol_new_hook (symbolP);
3175#endif
3176
3177#ifdef DEBUG_SYMS
3178 verify_symbol_chain (symbol_rootP, symbol_lastP);
3179#endif /* DEBUG_SYMS */
b99bd4ef
NC		 3180}
3181
b99bd4ef 3182
c19d1205
ZW		 3183static void
3184s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3185{
c19d1205
ZW		 3186 unsigned int entry;
3187 literal_pool * pool;
3188 char sym_name[20];
b99bd4ef 3189
c19d1205
ZW		 3190 pool = find_literal_pool ();
3191 if (pool == NULL
3192 || pool->symbol == NULL
3193 || pool->next_free_entry == 0)
3194 return;
b99bd4ef 3195
c19d1205 3196 mapping_state (MAP_DATA);
b99bd4ef 3197
c19d1205
ZW		 3198 /* Align pool as you have word accesses.
3199 Only make a frag if we have to. */
3200 if (!need_pass_2)
3201 frag_align (2, 0, 0);
b99bd4ef 3202
c19d1205 3203 record_alignment (now_seg, 2);
b99bd4ef 3204
c19d1205 3205 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3206
c19d1205
ZW		 3207 symbol_locate (pool->symbol, sym_name, now_seg,
3208 (valueT) frag_now_fix (), frag_now);
3209 symbol_table_insert (pool->symbol);
b99bd4ef 3210
c19d1205 3211 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3212
c19d1205
ZW		 3213#if defined OBJ_COFF || defined OBJ_ELF
3214 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3215#endif
6c43fab6 3216
c19d1205 3217 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC		 3218 {
3219#ifdef OBJ_ELF
3220 if (debug_type == DEBUG_DWARF2)
3221 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3222#endif
3223 /* First output the expression in the instruction to the pool. */
3224 emit_expr (&(pool->literals[entry]), 4); /* .word */
3225 }
b99bd4ef 3226
c19d1205
ZW		 3227 /* Mark the pool as empty. */
3228 pool->next_free_entry = 0;
3229 pool->symbol = NULL;
b99bd4ef
NC		 3230}
3231
c19d1205
ZW		 3232#ifdef OBJ_ELF
3233/* Forward declarations for functions below, in the MD interface
3234 section. */
3235static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3236static valueT create_unwind_entry (int);
3237static void start_unwind_section (const segT, int);
3238static void add_unwind_opcode (valueT, int);
3239static void flush_pending_unwind (void);
b99bd4ef 3240
c19d1205 3241/* Directives: Data. */
b99bd4ef 3242
c19d1205
ZW		 3243static void
3244s_arm_elf_cons (int nbytes)
3245{
3246 expressionS exp;
b99bd4ef 3247
c19d1205
ZW		 3248#ifdef md_flush_pending_output
3249 md_flush_pending_output ();
3250#endif
b99bd4ef 3251
c19d1205 3252 if (is_it_end_of_statement ())
b99bd4ef 3253 {
c19d1205
ZW		 3254 demand_empty_rest_of_line ();
3255 return;
b99bd4ef
NC		 3256 }
3257
c19d1205
ZW		 3258#ifdef md_cons_align
3259 md_cons_align (nbytes);
3260#endif
b99bd4ef 3261
c19d1205
ZW		 3262 mapping_state (MAP_DATA);
3263 do
b99bd4ef 3264 {
c19d1205
ZW		 3265 int reloc;
3266 char *base = input_line_pointer;
b99bd4ef 3267
c19d1205 3268 expression (& exp);
b99bd4ef 3269
c19d1205
ZW		 3270 if (exp.X_op != O_symbol)
3271 emit_expr (&exp, (unsigned int) nbytes);
3272 else
3273 {
3274 char *before_reloc = input_line_pointer;
3275 reloc = parse_reloc (&input_line_pointer);
3276 if (reloc == -1)
3277 {
3278 as_bad (_("unrecognized relocation suffix"));
3279 ignore_rest_of_line ();
3280 return;
3281 }
3282 else if (reloc == BFD_RELOC_UNUSED)
3283 emit_expr (&exp, (unsigned int) nbytes);
3284 else
3285 {
21d799b5 3286 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM		 3287 bfd_reloc_type_lookup (stdoutput,
3288 (bfd_reloc_code_real_type) reloc);
c19d1205 3289 int size = bfd_get_reloc_size (howto);
b99bd4ef 3290
2fc8bdac
ZW		 3291 if (reloc == BFD_RELOC_ARM_PLT32)
3292 {
3293 as_bad (_("(plt) is only valid on branch targets"));
3294 reloc = BFD_RELOC_UNUSED;
3295 size = 0;
3296 }
3297
c19d1205 3298 if (size > nbytes)
2fc8bdac 3299 as_bad (_("%s relocations do not fit in %d bytes"),
c19d1205
ZW		 3300 howto->name, nbytes);
3301 else
3302 {
3303 /* We've parsed an expression stopping at O_symbol.
3304 But there may be more expression left now that we
3305 have parsed the relocation marker. Parse it again.
3306 XXX Surely there is a cleaner way to do this. */
3307 char *p = input_line_pointer;
3308 int offset;
21d799b5 3309 char *save_buf = (char *) alloca (input_line_pointer - base);
c19d1205
ZW		 3310 memcpy (save_buf, base, input_line_pointer - base);
3311 memmove (base + (input_line_pointer - before_reloc),
3312 base, before_reloc - base);
3313
3314 input_line_pointer = base + (input_line_pointer-before_reloc);
3315 expression (&exp);
3316 memcpy (base, save_buf, p - base);
3317
3318 offset = nbytes - size;
3319 p = frag_more ((int) nbytes);
3320 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3321 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
c19d1205
ZW		 3322 }
3323 }
3324 }
b99bd4ef 3325 }
c19d1205 3326 while (*input_line_pointer++ == ',');
b99bd4ef 3327
c19d1205
ZW		 3328 /* Put terminator back into stream. */
3329 input_line_pointer --;
3330 demand_empty_rest_of_line ();
b99bd4ef
NC		 3331}
3332
c921be7d
NC		 3333/* Emit an expression containing a 32-bit thumb instruction.
3334 Implementation based on put_thumb32_insn. */
3335
3336static void
3337emit_thumb32_expr (expressionS * exp)
3338{
3339 expressionS exp_high = *exp;
3340
3341 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3342 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3343 exp->X_add_number &= 0xffff;
3344 emit_expr (exp, (unsigned int) THUMB_SIZE);
3345}
3346
3347/* Guess the instruction size based on the opcode. */
3348
3349static int
3350thumb_insn_size (int opcode)
3351{
3352 if ((unsigned int) opcode < 0xe800u)
3353 return 2;
3354 else if ((unsigned int) opcode >= 0xe8000000u)
3355 return 4;
3356 else
3357 return 0;
3358}
3359
3360static bfd_boolean
3361emit_insn (expressionS *exp, int nbytes)
3362{
3363 int size = 0;
3364
3365 if (exp->X_op == O_constant)
3366 {
3367 size = nbytes;
3368
3369 if (size == 0)
3370 size = thumb_insn_size (exp->X_add_number);
3371
3372 if (size != 0)
3373 {
3374 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3375 {
3376 as_bad (_(".inst.n operand too big. "\
3377 "Use .inst.w instead"));
3378 size = 0;
3379 }
3380 else
3381 {
3382 if (now_it.state == AUTOMATIC_IT_BLOCK)
3383 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3384 else
3385 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3386
3387 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3388 emit_thumb32_expr (exp);
3389 else
3390 emit_expr (exp, (unsigned int) size);
3391
3392 it_fsm_post_encode ();
3393 }
3394 }
3395 else
3396 as_bad (_("cannot determine Thumb instruction size. " \
3397 "Use .inst.n/.inst.w instead"));
3398 }
3399 else
3400 as_bad (_("constant expression required"));
3401
3402 return (size != 0);
3403}
3404
3405/* Like s_arm_elf_cons but do not use md_cons_align and
3406 set the mapping state to MAP_ARM/MAP_THUMB. */
3407
3408static void
3409s_arm_elf_inst (int nbytes)
3410{
3411 if (is_it_end_of_statement ())
3412 {
3413 demand_empty_rest_of_line ();
3414 return;
3415 }
3416
3417 /* Calling mapping_state () here will not change ARM/THUMB,
3418 but will ensure not to be in DATA state. */
3419
3420 if (thumb_mode)
3421 mapping_state (MAP_THUMB);
3422 else
3423 {
3424 if (nbytes != 0)
3425 {
3426 as_bad (_("width suffixes are invalid in ARM mode"));
3427 ignore_rest_of_line ();
3428 return;
3429 }
3430
3431 nbytes = 4;
3432
3433 mapping_state (MAP_ARM);
3434 }
3435
3436 do
3437 {
3438 expressionS exp;
3439
3440 expression (& exp);
3441
3442 if (! emit_insn (& exp, nbytes))
3443 {
3444 ignore_rest_of_line ();
3445 return;
3446 }
3447 }
3448 while (*input_line_pointer++ == ',');
3449
3450 /* Put terminator back into stream. */
3451 input_line_pointer --;
3452 demand_empty_rest_of_line ();
3453}
b99bd4ef 3454
c19d1205 3455/* Parse a .rel31 directive. */
b99bd4ef 3456
c19d1205
ZW		 3457static void
3458s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3459{
3460 expressionS exp;
3461 char *p;
3462 valueT highbit;
b99bd4ef 3463
c19d1205
ZW		 3464 highbit = 0;
3465 if (*input_line_pointer == '1')
3466 highbit = 0x80000000;
3467 else if (*input_line_pointer != '0')
3468 as_bad (_("expected 0 or 1"));
b99bd4ef 3469
c19d1205
ZW		 3470 input_line_pointer++;
3471 if (*input_line_pointer != ',')
3472 as_bad (_("missing comma"));
3473 input_line_pointer++;
b99bd4ef 3474
c19d1205
ZW		 3475#ifdef md_flush_pending_output
3476 md_flush_pending_output ();
3477#endif
b99bd4ef 3478
c19d1205
ZW		 3479#ifdef md_cons_align
3480 md_cons_align (4);
3481#endif
b99bd4ef 3482
c19d1205 3483 mapping_state (MAP_DATA);
b99bd4ef 3484
c19d1205 3485 expression (&exp);
b99bd4ef 3486
c19d1205
ZW		 3487 p = frag_more (4);
3488 md_number_to_chars (p, highbit, 4);
3489 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3490 BFD_RELOC_ARM_PREL31);
b99bd4ef 3491
c19d1205 3492 demand_empty_rest_of_line ();
b99bd4ef
NC		 3493}
3494
c19d1205 3495/* Directives: AEABI stack-unwind tables. */
b99bd4ef 3496
c19d1205 3497/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 3498
c19d1205
ZW		 3499static void
3500s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3501{
3502 demand_empty_rest_of_line ();
921e5f0a
PB		 3503 if (unwind.proc_start)
3504 {
c921be7d 3505 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB		 3506 return;
3507 }
3508
c19d1205
ZW		 3509 /* Mark the start of the function. */
3510 unwind.proc_start = expr_build_dot ();
b99bd4ef 3511
c19d1205
ZW		 3512 /* Reset the rest of the unwind info. */
3513 unwind.opcode_count = 0;
3514 unwind.table_entry = NULL;
3515 unwind.personality_routine = NULL;
3516 unwind.personality_index = -1;
3517 unwind.frame_size = 0;
3518 unwind.fp_offset = 0;
fdfde340 3519 unwind.fp_reg = REG_SP;
c19d1205
ZW		 3520 unwind.fp_used = 0;
3521 unwind.sp_restored = 0;
3522}
b99bd4ef 3523
b99bd4ef 3524
c19d1205
ZW		 3525/* Parse a handlerdata directive. Creates the exception handling table entry
3526 for the function. */
b99bd4ef 3527
c19d1205
ZW		 3528static void
3529s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3530{
3531 demand_empty_rest_of_line ();
921e5f0a 3532 if (!unwind.proc_start)
c921be7d 3533 as_bad (MISSING_FNSTART);
921e5f0a 3534
c19d1205 3535 if (unwind.table_entry)
6decc662 3536 as_bad (_("duplicate .handlerdata directive"));
f02232aa 3537
c19d1205
ZW		 3538 create_unwind_entry (1);
3539}
a737bd4d 3540
c19d1205 3541/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 3542
c19d1205
ZW		 3543static void
3544s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3545{
3546 long where;
3547 char *ptr;
3548 valueT val;
940b5ce0 3549 unsigned int marked_pr_dependency;
f02232aa 3550
c19d1205 3551 demand_empty_rest_of_line ();
f02232aa 3552
921e5f0a
PB		 3553 if (!unwind.proc_start)
3554 {
c921be7d 3555 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB		 3556 return;
3557 }
3558
c19d1205
ZW		 3559 /* Add eh table entry. */
3560 if (unwind.table_entry == NULL)
3561 val = create_unwind_entry (0);
3562 else
3563 val = 0;
f02232aa 3564
c19d1205
ZW		 3565 /* Add index table entry. This is two words. */
3566 start_unwind_section (unwind.saved_seg, 1);
3567 frag_align (2, 0, 0);
3568 record_alignment (now_seg, 2);
b99bd4ef 3569
c19d1205 3570 ptr = frag_more (8);
5011093d 3571 memset (ptr, 0, 8);
c19d1205 3572 where = frag_now_fix () - 8;
f02232aa 3573
c19d1205
ZW		 3574 /* Self relative offset of the function start. */
3575 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3576 BFD_RELOC_ARM_PREL31);
f02232aa 3577
c19d1205
ZW		 3578 /* Indicate dependency on EHABI-defined personality routines to the
3579 linker, if it hasn't been done already. */
940b5ce0
DJ		 3580 marked_pr_dependency
3581 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW		 3582 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3583 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3584 {
5f4273c7
NC		 3585 static const char *const name[] =
3586 {
3587 "__aeabi_unwind_cpp_pr0",
3588 "__aeabi_unwind_cpp_pr1",
3589 "__aeabi_unwind_cpp_pr2"
3590 };
c19d1205
ZW		 3591 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3592 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 3593 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 3594 |= 1 << unwind.personality_index;
c19d1205 3595 }
f02232aa 3596
c19d1205
ZW		 3597 if (val)
3598 /* Inline exception table entry. */
3599 md_number_to_chars (ptr + 4, val, 4);
3600 else
3601 /* Self relative offset of the table entry. */
3602 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3603 BFD_RELOC_ARM_PREL31);
f02232aa 3604
c19d1205
ZW		 3605 /* Restore the original section. */
3606 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB		 3607
3608 unwind.proc_start = NULL;
c19d1205 3609}
f02232aa 3610
f02232aa 3611
c19d1205 3612/* Parse an unwind_cantunwind directive. */
b99bd4ef 3613
c19d1205
ZW		 3614static void
3615s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3616{
3617 demand_empty_rest_of_line ();
921e5f0a 3618 if (!unwind.proc_start)
c921be7d 3619 as_bad (MISSING_FNSTART);
921e5f0a 3620
c19d1205
ZW		 3621 if (unwind.personality_routine || unwind.personality_index != -1)
3622 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 3623
c19d1205
ZW		 3624 unwind.personality_index = -2;
3625}
b99bd4ef 3626
b99bd4ef 3627
c19d1205 3628/* Parse a personalityindex directive. */
b99bd4ef 3629
c19d1205
ZW		 3630static void
3631s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3632{
3633 expressionS exp;
b99bd4ef 3634
921e5f0a 3635 if (!unwind.proc_start)
c921be7d 3636 as_bad (MISSING_FNSTART);
921e5f0a 3637
c19d1205
ZW		 3638 if (unwind.personality_routine || unwind.personality_index != -1)
3639 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 3640
c19d1205 3641 expression (&exp);
b99bd4ef 3642
c19d1205
ZW		 3643 if (exp.X_op != O_constant
3644 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 3645 {
c19d1205
ZW		 3646 as_bad (_("bad personality routine number"));
3647 ignore_rest_of_line ();
3648 return;
b99bd4ef
NC		 3649 }
3650
c19d1205 3651 unwind.personality_index = exp.X_add_number;
b99bd4ef 3652
c19d1205
ZW		 3653 demand_empty_rest_of_line ();
3654}
e16bb312 3655
e16bb312 3656
c19d1205 3657/* Parse a personality directive. */
e16bb312 3658
c19d1205
ZW		 3659static void
3660s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3661{
3662 char *name, *p, c;
a737bd4d 3663
921e5f0a 3664 if (!unwind.proc_start)
c921be7d 3665 as_bad (MISSING_FNSTART);
921e5f0a 3666
c19d1205
ZW		 3667 if (unwind.personality_routine || unwind.personality_index != -1)
3668 as_bad (_("duplicate .personality directive"));
a737bd4d 3669
c19d1205
ZW		 3670 name = input_line_pointer;
3671 c = get_symbol_end ();
3672 p = input_line_pointer;
3673 unwind.personality_routine = symbol_find_or_make (name);
3674 *p = c;
3675 demand_empty_rest_of_line ();
3676}
e16bb312 3677
e16bb312 3678
c19d1205 3679/* Parse a directive saving core registers. */
e16bb312 3680
c19d1205
ZW		 3681static void
3682s_arm_unwind_save_core (void)
e16bb312 3683{
c19d1205
ZW		 3684 valueT op;
3685 long range;
3686 int n;
e16bb312 3687
c19d1205
ZW		 3688 range = parse_reg_list (&input_line_pointer);
3689 if (range == FAIL)
e16bb312 3690 {
c19d1205
ZW		 3691 as_bad (_("expected register list"));
3692 ignore_rest_of_line ();
3693 return;
3694 }
e16bb312 3695
c19d1205 3696 demand_empty_rest_of_line ();
e16bb312 3697
c19d1205
ZW		 3698 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3699 into .unwind_save {..., sp...}. We aren't bothered about the value of
3700 ip because it is clobbered by calls. */
3701 if (unwind.sp_restored && unwind.fp_reg == 12
3702 && (range & 0x3000) == 0x1000)
3703 {
3704 unwind.opcode_count--;
3705 unwind.sp_restored = 0;
3706 range = (range | 0x2000) & ~0x1000;
3707 unwind.pending_offset = 0;
3708 }
e16bb312 3709
01ae4198
DJ		 3710 /* Pop r4-r15. */
3711 if (range & 0xfff0)
c19d1205 3712 {
01ae4198
DJ		 3713 /* See if we can use the short opcodes. These pop a block of up to 8
3714 registers starting with r4, plus maybe r14. */
3715 for (n = 0; n < 8; n++)
3716 {
3717 /* Break at the first non-saved register. */
3718 if ((range & (1 << (n + 4))) == 0)
3719 break;
3720 }
3721 /* See if there are any other bits set. */
3722 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3723 {
3724 /* Use the long form. */
3725 op = 0x8000 | ((range >> 4) & 0xfff);
3726 add_unwind_opcode (op, 2);
3727 }
0dd132b6 3728 else
01ae4198
DJ		 3729 {
3730 /* Use the short form. */
3731 if (range & 0x4000)
3732 op = 0xa8; /* Pop r14. */
3733 else
3734 op = 0xa0; /* Do not pop r14. */
3735 op |= (n - 1);
3736 add_unwind_opcode (op, 1);
3737 }
c19d1205 3738 }
0dd132b6 3739
c19d1205
ZW		 3740 /* Pop r0-r3. */
3741 if (range & 0xf)
3742 {
3743 op = 0xb100 | (range & 0xf);
3744 add_unwind_opcode (op, 2);
0dd132b6
NC		 3745 }
3746
c19d1205
ZW		 3747 /* Record the number of bytes pushed. */
3748 for (n = 0; n < 16; n++)
3749 {
3750 if (range & (1 << n))
3751 unwind.frame_size += 4;
3752 }
0dd132b6
NC		 3753}
3754
c19d1205
ZW		 3755
3756/* Parse a directive saving FPA registers. */
b99bd4ef
NC		 3757
3758static void
c19d1205 3759s_arm_unwind_save_fpa (int reg)
b99bd4ef 3760{
c19d1205
ZW		 3761 expressionS exp;
3762 int num_regs;
3763 valueT op;
b99bd4ef 3764
c19d1205
ZW		 3765 /* Get Number of registers to transfer. */
3766 if (skip_past_comma (&input_line_pointer) != FAIL)
3767 expression (&exp);
3768 else
3769 exp.X_op = O_illegal;
b99bd4ef 3770
c19d1205 3771 if (exp.X_op != O_constant)
b99bd4ef 3772 {
c19d1205
ZW		 3773 as_bad (_("expected , <constant>"));
3774 ignore_rest_of_line ();
b99bd4ef
NC		 3775 return;
3776 }
3777
c19d1205
ZW		 3778 num_regs = exp.X_add_number;
3779
3780 if (num_regs < 1 || num_regs > 4)
b99bd4ef 3781 {
c19d1205
ZW		 3782 as_bad (_("number of registers must be in the range [1:4]"));
3783 ignore_rest_of_line ();
b99bd4ef
NC		 3784 return;
3785 }
3786
c19d1205 3787 demand_empty_rest_of_line ();
b99bd4ef 3788
c19d1205
ZW		 3789 if (reg == 4)
3790 {
3791 /* Short form. */
3792 op = 0xb4 | (num_regs - 1);
3793 add_unwind_opcode (op, 1);
3794 }
b99bd4ef
NC		 3795 else
3796 {
c19d1205
ZW		 3797 /* Long form. */
3798 op = 0xc800 | (reg << 4) | (num_regs - 1);
3799 add_unwind_opcode (op, 2);
b99bd4ef 3800 }
c19d1205 3801 unwind.frame_size += num_regs * 12;
b99bd4ef
NC		 3802}
3803
c19d1205 3804
fa073d69
MS		 3805/* Parse a directive saving VFP registers for ARMv6 and above. */
3806
3807static void
3808s_arm_unwind_save_vfp_armv6 (void)
3809{
3810 int count;
3811 unsigned int start;
3812 valueT op;
3813 int num_vfpv3_regs = 0;
3814 int num_regs_below_16;
3815
3816 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
3817 if (count == FAIL)
3818 {
3819 as_bad (_("expected register list"));
3820 ignore_rest_of_line ();
3821 return;
3822 }
3823
3824 demand_empty_rest_of_line ();
3825
3826 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3827 than FSTMX/FLDMX-style ones). */
3828
3829 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3830 if (start >= 16)
3831 num_vfpv3_regs = count;
3832 else if (start + count > 16)
3833 num_vfpv3_regs = start + count - 16;
3834
3835 if (num_vfpv3_regs > 0)
3836 {
3837 int start_offset = start > 16 ? start - 16 : 0;
3838 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
3839 add_unwind_opcode (op, 2);
3840 }
3841
3842 /* Generate opcode for registers numbered in the range 0 .. 15. */
3843 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 3844 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS		 3845 if (num_regs_below_16 > 0)
3846 {
3847 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
3848 add_unwind_opcode (op, 2);
3849 }
3850
3851 unwind.frame_size += count * 8;
3852}
3853
3854
3855/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC		 3856
3857static void
c19d1205 3858s_arm_unwind_save_vfp (void)
b99bd4ef 3859{
c19d1205 3860 int count;
ca3f61f7 3861 unsigned int reg;
c19d1205 3862 valueT op;
b99bd4ef 3863
5287ad62 3864 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
c19d1205 3865 if (count == FAIL)
b99bd4ef 3866 {
c19d1205
ZW		 3867 as_bad (_("expected register list"));
3868 ignore_rest_of_line ();
b99bd4ef
NC		 3869 return;
3870 }
3871
c19d1205 3872 demand_empty_rest_of_line ();
b99bd4ef 3873
c19d1205 3874 if (reg == 8)
b99bd4ef 3875 {
c19d1205
ZW		 3876 /* Short form. */
3877 op = 0xb8 | (count - 1);
3878 add_unwind_opcode (op, 1);
b99bd4ef 3879 }
c19d1205 3880 else
b99bd4ef 3881 {
c19d1205
ZW		 3882 /* Long form. */
3883 op = 0xb300 | (reg << 4) | (count - 1);
3884 add_unwind_opcode (op, 2);
b99bd4ef 3885 }
c19d1205
ZW		 3886 unwind.frame_size += count * 8 + 4;
3887}
b99bd4ef 3888
b99bd4ef 3889
c19d1205
ZW		 3890/* Parse a directive saving iWMMXt data registers. */
3891
3892static void
3893s_arm_unwind_save_mmxwr (void)
3894{
3895 int reg;
3896 int hi_reg;
3897 int i;
3898 unsigned mask = 0;
3899 valueT op;
b99bd4ef 3900
c19d1205
ZW		 3901 if (*input_line_pointer == '{')
3902 input_line_pointer++;
b99bd4ef 3903
c19d1205 3904 do
b99bd4ef 3905 {
dcbf9037 3906 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 3907
c19d1205 3908 if (reg == FAIL)
b99bd4ef 3909 {
9b7132d3 3910 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 3911 goto error;
b99bd4ef
NC		 3912 }
3913
c19d1205
ZW		 3914 if (mask >> reg)
3915 as_tsktsk (_("register list not in ascending order"));
3916 mask |= 1 << reg;
b99bd4ef 3917
c19d1205
ZW		 3918 if (*input_line_pointer == '-')
3919 {
3920 input_line_pointer++;
dcbf9037 3921 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW		 3922 if (hi_reg == FAIL)
3923 {
9b7132d3 3924 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW		 3925 goto error;
3926 }
3927 else if (reg >= hi_reg)
3928 {
3929 as_bad (_("bad register range"));
3930 goto error;
3931 }
3932 for (; reg < hi_reg; reg++)
3933 mask |= 1 << reg;
3934 }
3935 }
3936 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 3937
d996d970 3938 skip_past_char (&input_line_pointer, '}');
b99bd4ef 3939
c19d1205 3940 demand_empty_rest_of_line ();
b99bd4ef 3941
708587a4 3942 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 3943 the list. */
3944 flush_pending_unwind ();
b99bd4ef 3945
c19d1205 3946 for (i = 0; i < 16; i++)
b99bd4ef 3947 {
c19d1205
ZW		 3948 if (mask & (1 << i))
3949 unwind.frame_size += 8;
b99bd4ef
NC		 3950 }
3951
c19d1205
ZW		 3952 /* Attempt to combine with a previous opcode. We do this because gcc
3953 likes to output separate unwind directives for a single block of
3954 registers. */
3955 if (unwind.opcode_count > 0)
b99bd4ef 3956 {
c19d1205
ZW		 3957 i = unwind.opcodes[unwind.opcode_count - 1];
3958 if ((i & 0xf8) == 0xc0)
3959 {
3960 i &= 7;
3961 /* Only merge if the blocks are contiguous. */
3962 if (i < 6)
3963 {
3964 if ((mask & 0xfe00) == (1 << 9))
3965 {
3966 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
3967 unwind.opcode_count--;
3968 }
3969 }
3970 else if (i == 6 && unwind.opcode_count >= 2)
3971 {
3972 i = unwind.opcodes[unwind.opcode_count - 2];
3973 reg = i >> 4;
3974 i &= 0xf;
b99bd4ef 3975
c19d1205
ZW		 3976 op = 0xffff << (reg - 1);
3977 if (reg > 0
87a1fd79 3978 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW		 3979 {
3980 op = (1 << (reg + i + 1)) - 1;
3981 op &= ~((1 << reg) - 1);
3982 mask |= op;
3983 unwind.opcode_count -= 2;
3984 }
3985 }
3986 }
b99bd4ef
NC		 3987 }
3988
c19d1205
ZW		 3989 hi_reg = 15;
3990 /* We want to generate opcodes in the order the registers have been
3991 saved, ie. descending order. */
3992 for (reg = 15; reg >= -1; reg--)
b99bd4ef 3993 {
c19d1205
ZW		 3994 /* Save registers in blocks. */
3995 if (reg < 0
3996 || !(mask & (1 << reg)))
3997 {
3998 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 3999 preceding block. */
c19d1205
ZW		 4000 if (reg != hi_reg)
4001 {
4002 if (reg == 9)
4003 {
4004 /* Short form. */
4005 op = 0xc0 | (hi_reg - 10);
4006 add_unwind_opcode (op, 1);
4007 }
4008 else
4009 {
4010 /* Long form. */
4011 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4012 add_unwind_opcode (op, 2);
4013 }
4014 }
4015 hi_reg = reg - 1;
4016 }
b99bd4ef
NC		 4017 }
4018
c19d1205
ZW		 4019 return;
4020error:
4021 ignore_rest_of_line ();
b99bd4ef
NC		 4022}
4023
4024static void
c19d1205 4025s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4026{
c19d1205
ZW		 4027 int reg;
4028 int hi_reg;
4029 unsigned mask = 0;
4030 valueT op;
b99bd4ef 4031
c19d1205
ZW		 4032 if (*input_line_pointer == '{')
4033 input_line_pointer++;
b99bd4ef 4034
477330fc
RM		 4035 skip_whitespace (input_line_pointer);
4036
c19d1205 4037 do
b99bd4ef 4038 {
dcbf9037 4039 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4040
c19d1205
ZW		 4041 if (reg == FAIL)
4042 {
9b7132d3 4043 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4044 goto error;
4045 }
b99bd4ef 4046
c19d1205
ZW		 4047 reg -= 8;
4048 if (mask >> reg)
4049 as_tsktsk (_("register list not in ascending order"));
4050 mask |= 1 << reg;
b99bd4ef 4051
c19d1205
ZW		 4052 if (*input_line_pointer == '-')
4053 {
4054 input_line_pointer++;
dcbf9037 4055 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW		 4056 if (hi_reg == FAIL)
4057 {
9b7132d3 4058 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4059 goto error;
4060 }
4061 else if (reg >= hi_reg)
4062 {
4063 as_bad (_("bad register range"));
4064 goto error;
4065 }
4066 for (; reg < hi_reg; reg++)
4067 mask |= 1 << reg;
4068 }
b99bd4ef 4069 }
c19d1205 4070 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4071
d996d970 4072 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4073
c19d1205
ZW		 4074 demand_empty_rest_of_line ();
4075
708587a4 4076 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4077 the list. */
4078 flush_pending_unwind ();
b99bd4ef 4079
c19d1205 4080 for (reg = 0; reg < 16; reg++)
b99bd4ef 4081 {
c19d1205
ZW		 4082 if (mask & (1 << reg))
4083 unwind.frame_size += 4;
b99bd4ef 4084 }
c19d1205
ZW		 4085 op = 0xc700 | mask;
4086 add_unwind_opcode (op, 2);
4087 return;
4088error:
4089 ignore_rest_of_line ();
b99bd4ef
NC		 4090}
4091
c19d1205 4092
fa073d69
MS		 4093/* Parse an unwind_save directive.
4094 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4095
b99bd4ef 4096static void
fa073d69 4097s_arm_unwind_save (int arch_v6)
b99bd4ef 4098{
c19d1205
ZW		 4099 char *peek;
4100 struct reg_entry *reg;
4101 bfd_boolean had_brace = FALSE;
b99bd4ef 4102
921e5f0a 4103 if (!unwind.proc_start)
c921be7d 4104 as_bad (MISSING_FNSTART);
921e5f0a 4105
c19d1205
ZW		 4106 /* Figure out what sort of save we have. */
4107 peek = input_line_pointer;
b99bd4ef 4108
c19d1205 4109 if (*peek == '{')
b99bd4ef 4110 {
c19d1205
ZW		 4111 had_brace = TRUE;
4112 peek++;
b99bd4ef
NC		 4113 }
4114
c19d1205 4115 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4116
c19d1205 4117 if (!reg)
b99bd4ef 4118 {
c19d1205
ZW		 4119 as_bad (_("register expected"));
4120 ignore_rest_of_line ();
b99bd4ef
NC		 4121 return;
4122 }
4123
c19d1205 4124 switch (reg->type)
b99bd4ef 4125 {
c19d1205
ZW		 4126 case REG_TYPE_FN:
4127 if (had_brace)
4128 {
4129 as_bad (_("FPA .unwind_save does not take a register list"));
4130 ignore_rest_of_line ();
4131 return;
4132 }
93ac2687 4133 input_line_pointer = peek;
c19d1205 4134 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4135 return;
c19d1205
ZW		 4136
4137 case REG_TYPE_RN: s_arm_unwind_save_core (); return;
fa073d69
MS		 4138 case REG_TYPE_VFD:
4139 if (arch_v6)
477330fc 4140 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4141 else
477330fc 4142 s_arm_unwind_save_vfp ();
fa073d69 4143 return;
c19d1205
ZW		 4144 case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return;
4145 case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return;
4146
4147 default:
4148 as_bad (_(".unwind_save does not support this kind of register"));
4149 ignore_rest_of_line ();
b99bd4ef 4150 }
c19d1205 4151}
b99bd4ef 4152
b99bd4ef 4153
c19d1205
ZW		 4154/* Parse an unwind_movsp directive. */
4155
4156static void
4157s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4158{
4159 int reg;
4160 valueT op;
4fa3602b 4161 int offset;
c19d1205 4162
921e5f0a 4163 if (!unwind.proc_start)
c921be7d 4164 as_bad (MISSING_FNSTART);
921e5f0a 4165
dcbf9037 4166 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4167 if (reg == FAIL)
b99bd4ef 4168 {
9b7132d3 4169 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4170 ignore_rest_of_line ();
b99bd4ef
NC		 4171 return;
4172 }
4fa3602b
PB		 4173
4174 /* Optional constant. */
4175 if (skip_past_comma (&input_line_pointer) != FAIL)
4176 {
4177 if (immediate_for_directive (&offset) == FAIL)
4178 return;
4179 }
4180 else
4181 offset = 0;
4182
c19d1205 4183 demand_empty_rest_of_line ();
b99bd4ef 4184
c19d1205 4185 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4186 {
c19d1205 4187 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC		 4188 return;
4189 }
4190
c19d1205
ZW		 4191 if (unwind.fp_reg != REG_SP)
4192 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4193
c19d1205
ZW		 4194 /* Generate opcode to restore the value. */
4195 op = 0x90 | reg;
4196 add_unwind_opcode (op, 1);
4197
4198 /* Record the information for later. */
4199 unwind.fp_reg = reg;
4fa3602b 4200 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4201 unwind.sp_restored = 1;
b05fe5cf
ZW		 4202}
4203
c19d1205
ZW		 4204/* Parse an unwind_pad directive. */
4205
b05fe5cf 4206static void
c19d1205 4207s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4208{
c19d1205 4209 int offset;
b05fe5cf 4210
921e5f0a 4211 if (!unwind.proc_start)
c921be7d 4212 as_bad (MISSING_FNSTART);
921e5f0a 4213
c19d1205
ZW		 4214 if (immediate_for_directive (&offset) == FAIL)
4215 return;
b99bd4ef 4216
c19d1205
ZW		 4217 if (offset & 3)
4218 {
4219 as_bad (_("stack increment must be multiple of 4"));
4220 ignore_rest_of_line ();
4221 return;
4222 }
b99bd4ef 4223
c19d1205
ZW		 4224 /* Don't generate any opcodes, just record the details for later. */
4225 unwind.frame_size += offset;
4226 unwind.pending_offset += offset;
4227
4228 demand_empty_rest_of_line ();
4229}
4230
4231/* Parse an unwind_setfp directive. */
4232
4233static void
4234s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4235{
c19d1205
ZW		 4236 int sp_reg;
4237 int fp_reg;
4238 int offset;
4239
921e5f0a 4240 if (!unwind.proc_start)
c921be7d 4241 as_bad (MISSING_FNSTART);
921e5f0a 4242
dcbf9037 4243 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW		 4244 if (skip_past_comma (&input_line_pointer) == FAIL)
4245 sp_reg = FAIL;
4246 else
dcbf9037 4247 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4248
c19d1205
ZW		 4249 if (fp_reg == FAIL || sp_reg == FAIL)
4250 {
4251 as_bad (_("expected <reg>, <reg>"));
4252 ignore_rest_of_line ();
4253 return;
4254 }
b99bd4ef 4255
c19d1205
ZW		 4256 /* Optional constant. */
4257 if (skip_past_comma (&input_line_pointer) != FAIL)
4258 {
4259 if (immediate_for_directive (&offset) == FAIL)
4260 return;
4261 }
4262 else
4263 offset = 0;
a737bd4d 4264
c19d1205 4265 demand_empty_rest_of_line ();
a737bd4d 4266
fdfde340 4267 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4268 {
c19d1205
ZW		 4269 as_bad (_("register must be either sp or set by a previous"
4270 "unwind_movsp directive"));
4271 return;
a737bd4d
NC		 4272 }
4273
c19d1205
ZW		 4274 /* Don't generate any opcodes, just record the information for later. */
4275 unwind.fp_reg = fp_reg;
4276 unwind.fp_used = 1;
fdfde340 4277 if (sp_reg == REG_SP)
c19d1205
ZW		 4278 unwind.fp_offset = unwind.frame_size - offset;
4279 else
4280 unwind.fp_offset -= offset;
a737bd4d
NC		 4281}
4282
c19d1205
ZW		 4283/* Parse an unwind_raw directive. */
4284
4285static void
4286s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4287{
c19d1205 4288 expressionS exp;
708587a4 4289 /* This is an arbitrary limit. */
c19d1205
ZW		 4290 unsigned char op[16];
4291 int count;
a737bd4d 4292
921e5f0a 4293 if (!unwind.proc_start)
c921be7d 4294 as_bad (MISSING_FNSTART);
921e5f0a 4295
c19d1205
ZW		 4296 expression (&exp);
4297 if (exp.X_op == O_constant
4298 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4299 {
c19d1205
ZW		 4300 unwind.frame_size += exp.X_add_number;
4301 expression (&exp);
4302 }
4303 else
4304 exp.X_op = O_illegal;
a737bd4d 4305
c19d1205
ZW		 4306 if (exp.X_op != O_constant)
4307 {
4308 as_bad (_("expected <offset>, <opcode>"));
4309 ignore_rest_of_line ();
4310 return;
4311 }
a737bd4d 4312
c19d1205 4313 count = 0;
a737bd4d 4314
c19d1205
ZW		 4315 /* Parse the opcode. */
4316 for (;;)
4317 {
4318 if (count >= 16)
4319 {
4320 as_bad (_("unwind opcode too long"));
4321 ignore_rest_of_line ();
a737bd4d 4322 }
c19d1205 4323 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4324 {
c19d1205
ZW		 4325 as_bad (_("invalid unwind opcode"));
4326 ignore_rest_of_line ();
4327 return;
a737bd4d 4328 }
c19d1205 4329 op[count++] = exp.X_add_number;
a737bd4d 4330
c19d1205
ZW		 4331 /* Parse the next byte. */
4332 if (skip_past_comma (&input_line_pointer) == FAIL)
4333 break;
a737bd4d 4334
c19d1205
ZW		 4335 expression (&exp);
4336 }
b99bd4ef 4337
c19d1205
ZW		 4338 /* Add the opcode bytes in reverse order. */
4339 while (count--)
4340 add_unwind_opcode (op[count], 1);
b99bd4ef 4341
c19d1205 4342 demand_empty_rest_of_line ();
b99bd4ef 4343}
ee065d83
PB		 4344
4345
4346/* Parse a .eabi_attribute directive. */
4347
4348static void
4349s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4350{
0420f52b 4351 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378
AS		 4352
4353 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4354 attributes_set_explicitly[tag] = 1;
ee065d83
PB		 4355}
4356
0855e32b
NS		 4357/* Emit a tls fix for the symbol. */
4358
4359static void
4360s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4361{
4362 char *p;
4363 expressionS exp;
4364#ifdef md_flush_pending_output
4365 md_flush_pending_output ();
4366#endif
4367
4368#ifdef md_cons_align
4369 md_cons_align (4);
4370#endif
4371
4372 /* Since we're just labelling the code, there's no need to define a
4373 mapping symbol. */
4374 expression (&exp);
4375 p = obstack_next_free (&frchain_now->frch_obstack);
4376 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4377 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4378 : BFD_RELOC_ARM_TLS_DESCSEQ);
4379}
cdf9ccec 4380#endif /* OBJ_ELF */
0855e32b 4381
ee065d83 4382static void s_arm_arch (int);
7a1d4c38 4383static void s_arm_object_arch (int);
ee065d83
PB		 4384static void s_arm_cpu (int);
4385static void s_arm_fpu (int);
69133863 4386static void s_arm_arch_extension (int);
b99bd4ef 4387
f0927246
NC		 4388#ifdef TE_PE
4389
4390static void
5f4273c7 4391pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC		 4392{
4393 expressionS exp;
4394
4395 do
4396 {
4397 expression (&exp);
4398 if (exp.X_op == O_symbol)
4399 exp.X_op = O_secrel;
4400
4401 emit_expr (&exp, 4);
4402 }
4403 while (*input_line_pointer++ == ',');
4404
4405 input_line_pointer--;
4406 demand_empty_rest_of_line ();
4407}
4408#endif /* TE_PE */
4409
c19d1205
ZW		 4410/* This table describes all the machine specific pseudo-ops the assembler
4411 has to support. The fields are:
4412 pseudo-op name without dot
4413 function to call to execute this pseudo-op
4414 Integer arg to pass to the function. */
b99bd4ef 4415
c19d1205 4416const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4417{
c19d1205
ZW		 4418 /* Never called because '.req' does not start a line. */
4419 { "req", s_req, 0 },
dcbf9037
JB		 4420 /* Following two are likewise never called. */
4421 { "dn", s_dn, 0 },
4422 { "qn", s_qn, 0 },
c19d1205
ZW		 4423 { "unreq", s_unreq, 0 },
4424 { "bss", s_bss, 0 },
4425 { "align", s_align, 0 },
4426 { "arm", s_arm, 0 },
4427 { "thumb", s_thumb, 0 },
4428 { "code", s_code, 0 },
4429 { "force_thumb", s_force_thumb, 0 },
4430 { "thumb_func", s_thumb_func, 0 },
4431 { "thumb_set", s_thumb_set, 0 },
4432 { "even", s_even, 0 },
4433 { "ltorg", s_ltorg, 0 },
4434 { "pool", s_ltorg, 0 },
4435 { "syntax", s_syntax, 0 },
8463be01
PB		 4436 { "cpu", s_arm_cpu, 0 },
4437 { "arch", s_arm_arch, 0 },
7a1d4c38 4438 { "object_arch", s_arm_object_arch, 0 },
8463be01 4439 { "fpu", s_arm_fpu, 0 },
69133863 4440 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 4441#ifdef OBJ_ELF
c921be7d
NC		 4442 { "word", s_arm_elf_cons, 4 },
4443 { "long", s_arm_elf_cons, 4 },
4444 { "inst.n", s_arm_elf_inst, 2 },
4445 { "inst.w", s_arm_elf_inst, 4 },
4446 { "inst", s_arm_elf_inst, 0 },
4447 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW		 4448 { "fnstart", s_arm_unwind_fnstart, 0 },
4449 { "fnend", s_arm_unwind_fnend, 0 },
4450 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4451 { "personality", s_arm_unwind_personality, 0 },
4452 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4453 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4454 { "save", s_arm_unwind_save, 0 },
fa073d69 4455 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW		 4456 { "movsp", s_arm_unwind_movsp, 0 },
4457 { "pad", s_arm_unwind_pad, 0 },
4458 { "setfp", s_arm_unwind_setfp, 0 },
4459 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 4460 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 4461 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW		 4462#else
4463 { "word", cons, 4},
f0927246
NC		 4464
4465 /* These are used for dwarf. */
4466 {"2byte", cons, 2},
4467 {"4byte", cons, 4},
4468 {"8byte", cons, 8},
4469 /* These are used for dwarf2. */
4470 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4471 { "loc", dwarf2_directive_loc, 0 },
4472 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW		 4473#endif
4474 { "extend", float_cons, 'x' },
4475 { "ldouble", float_cons, 'x' },
4476 { "packed", float_cons, 'p' },
f0927246
NC		 4477#ifdef TE_PE
4478 {"secrel32", pe_directive_secrel, 0},
4479#endif
c19d1205
ZW		 4480 { 0, 0, 0 }
4481};
4482\f
4483/* Parser functions used exclusively in instruction operands. */
b99bd4ef 4484
c19d1205
ZW		 4485/* Generic immediate-value read function for use in insn parsing.
4486 STR points to the beginning of the immediate (the leading #);
4487 VAL receives the value; if the value is outside [MIN, MAX]
4488 issue an error. PREFIX_OPT is true if the immediate prefix is
4489 optional. */
b99bd4ef 4490
c19d1205
ZW		 4491static int
4492parse_immediate (char **str, int *val, int min, int max,
4493 bfd_boolean prefix_opt)
4494{
4495 expressionS exp;
4496 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4497 if (exp.X_op != O_constant)
b99bd4ef 4498 {
c19d1205
ZW		 4499 inst.error = _("constant expression required");
4500 return FAIL;
4501 }
b99bd4ef 4502
c19d1205
ZW		 4503 if (exp.X_add_number < min || exp.X_add_number > max)
4504 {
4505 inst.error = _("immediate value out of range");
4506 return FAIL;
4507 }
b99bd4ef 4508
c19d1205
ZW		 4509 *val = exp.X_add_number;
4510 return SUCCESS;
4511}
b99bd4ef 4512
5287ad62 4513/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 4514 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB		 4515 instructions. Puts the result directly in inst.operands[i]. */
4516
4517static int
4518parse_big_immediate (char **str, int i)
4519{
4520 expressionS exp;
4521 char *ptr = *str;
4522
4523 my_get_expression (&exp, &ptr, GE_OPT_PREFIX_BIG);
4524
4525 if (exp.X_op == O_constant)
036dc3f7
PB		 4526 {
4527 inst.operands[i].imm = exp.X_add_number & 0xffffffff;
4528 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4529 O_constant. We have to be careful not to break compilation for
4530 32-bit X_add_number, though. */
58ad575f 4531 if ((exp.X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 4532 {
477330fc 4533 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
036dc3f7
PB		 4534 inst.operands[i].reg = ((exp.X_add_number >> 16) >> 16) & 0xffffffff;
4535 inst.operands[i].regisimm = 1;
4536 }
4537 }
5287ad62 4538 else if (exp.X_op == O_big
95b75c01 4539 && LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 32)
5287ad62
JB		 4540 {
4541 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 4542
5287ad62 4543 /* Bignums have their least significant bits in
477330fc
RM		 4544 generic_bignum[0]. Make sure we put 32 bits in imm and
4545 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 4546 gas_assert (parts != 0);
95b75c01
NC		 4547
4548 /* Make sure that the number is not too big.
4549 PR 11972: Bignums can now be sign-extended to the
4550 size of a .octa so check that the out of range bits
4551 are all zero or all one. */
4552 if (LITTLENUM_NUMBER_OF_BITS * exp.X_add_number > 64)
4553 {
4554 LITTLENUM_TYPE m = -1;
4555
4556 if (generic_bignum[parts * 2] != 0
4557 && generic_bignum[parts * 2] != m)
4558 return FAIL;
4559
4560 for (j = parts * 2 + 1; j < (unsigned) exp.X_add_number; j++)
4561 if (generic_bignum[j] != generic_bignum[j-1])
4562 return FAIL;
4563 }
4564
5287ad62
JB		 4565 inst.operands[i].imm = 0;
4566 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 4567 inst.operands[i].imm |= generic_bignum[idx]
4568 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 4569 inst.operands[i].reg = 0;
4570 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 4571 inst.operands[i].reg |= generic_bignum[idx]
4572 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 4573 inst.operands[i].regisimm = 1;
4574 }
4575 else
4576 return FAIL;
5f4273c7 4577
5287ad62
JB		 4578 *str = ptr;
4579
4580 return SUCCESS;
4581}
4582
c19d1205
ZW		 4583/* Returns the pseudo-register number of an FPA immediate constant,
4584 or FAIL if there isn't a valid constant here. */
b99bd4ef 4585
c19d1205
ZW		 4586static int
4587parse_fpa_immediate (char ** str)
4588{
4589 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4590 char * save_in;
4591 expressionS exp;
4592 int i;
4593 int j;
b99bd4ef 4594
c19d1205
ZW		 4595 /* First try and match exact strings, this is to guarantee
4596 that some formats will work even for cross assembly. */
b99bd4ef 4597
c19d1205
ZW		 4598 for (i = 0; fp_const[i]; i++)
4599 {
4600 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 4601 {
c19d1205 4602 char *start = *str;
b99bd4ef 4603
c19d1205
ZW		 4604 *str += strlen (fp_const[i]);
4605 if (is_end_of_line[(unsigned char) **str])
4606 return i + 8;
4607 *str = start;
4608 }
4609 }
b99bd4ef 4610
c19d1205
ZW		 4611 /* Just because we didn't get a match doesn't mean that the constant
4612 isn't valid, just that it is in a format that we don't
4613 automatically recognize. Try parsing it with the standard
4614 expression routines. */
b99bd4ef 4615
c19d1205 4616 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 4617
c19d1205
ZW		 4618 /* Look for a raw floating point number. */
4619 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4620 && is_end_of_line[(unsigned char) *save_in])
4621 {
4622 for (i = 0; i < NUM_FLOAT_VALS; i++)
4623 {
4624 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 4625 {
c19d1205
ZW		 4626 if (words[j] != fp_values[i][j])
4627 break;
b99bd4ef
NC		 4628 }
4629
c19d1205 4630 if (j == MAX_LITTLENUMS)
b99bd4ef 4631 {
c19d1205
ZW		 4632 *str = save_in;
4633 return i + 8;
b99bd4ef
NC		 4634 }
4635 }
4636 }
b99bd4ef 4637
c19d1205
ZW		 4638 /* Try and parse a more complex expression, this will probably fail
4639 unless the code uses a floating point prefix (eg "0f"). */
4640 save_in = input_line_pointer;
4641 input_line_pointer = *str;
4642 if (expression (&exp) == absolute_section
4643 && exp.X_op == O_big
4644 && exp.X_add_number < 0)
4645 {
4646 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4647 Ditto for 15. */
4648 if (gen_to_words (words, 5, (long) 15) == 0)
4649 {
4650 for (i = 0; i < NUM_FLOAT_VALS; i++)
4651 {
4652 for (j = 0; j < MAX_LITTLENUMS; j++)
4653 {
4654 if (words[j] != fp_values[i][j])
4655 break;
4656 }
b99bd4ef 4657
c19d1205
ZW		 4658 if (j == MAX_LITTLENUMS)
4659 {
4660 *str = input_line_pointer;
4661 input_line_pointer = save_in;
4662 return i + 8;
4663 }
4664 }
4665 }
b99bd4ef
NC		 4666 }
4667
c19d1205
ZW		 4668 *str = input_line_pointer;
4669 input_line_pointer = save_in;
4670 inst.error = _("invalid FPA immediate expression");
4671 return FAIL;
b99bd4ef
NC		 4672}
4673
136da414
JB		 4674/* Returns 1 if a number has "quarter-precision" float format
4675 0baBbbbbbc defgh000 00000000 00000000. */
4676
4677static int
4678is_quarter_float (unsigned imm)
4679{
4680 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4681 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4682}
4683
4684/* Parse an 8-bit "quarter-precision" floating point number of the form:
4685 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB		 4686 The zero and minus-zero cases need special handling, since they can't be
4687 encoded in the "quarter-precision" float format, but can nonetheless be
4688 loaded as integer constants. */
136da414
JB		 4689
4690static unsigned
4691parse_qfloat_immediate (char **ccp, int *immed)
4692{
4693 char *str = *ccp;
c96612cc 4694 char *fpnum;
136da414 4695 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 4696 int found_fpchar = 0;
5f4273c7 4697
136da414 4698 skip_past_char (&str, '#');
5f4273c7 4699
c96612cc
JB		 4700 /* We must not accidentally parse an integer as a floating-point number. Make
4701 sure that the value we parse is not an integer by checking for special
4702 characters '.' or 'e'.
4703 FIXME: This is a horrible hack, but doing better is tricky because type
4704 information isn't in a very usable state at parse time. */
4705 fpnum = str;
4706 skip_whitespace (fpnum);
4707
4708 if (strncmp (fpnum, "0x", 2) == 0)
4709 return FAIL;
4710 else
4711 {
4712 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM		 4713 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
4714 {
4715 found_fpchar = 1;
4716 break;
4717 }
c96612cc
JB		 4718
4719 if (!found_fpchar)
477330fc 4720 return FAIL;
c96612cc 4721 }
5f4273c7 4722
136da414
JB		 4723 if ((str = atof_ieee (str, 's', words)) != NULL)
4724 {
4725 unsigned fpword = 0;
4726 int i;
5f4273c7 4727
136da414
JB		 4728 /* Our FP word must be 32 bits (single-precision FP). */
4729 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM		 4730 {
4731 fpword <<= LITTLENUM_NUMBER_OF_BITS;
4732 fpword |= words[i];
4733 }
5f4273c7 4734
c96612cc 4735 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 4736 *immed = fpword;
136da414 4737 else
477330fc 4738 return FAIL;
136da414
JB		 4739
4740 *ccp = str;
5f4273c7 4741
136da414
JB		 4742 return SUCCESS;
4743 }
5f4273c7 4744
136da414
JB		 4745 return FAIL;
4746}
4747
c19d1205
ZW		 4748/* Shift operands. */
4749enum shift_kind
b99bd4ef 4750{
c19d1205
ZW		 4751 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
4752};
b99bd4ef 4753
c19d1205
ZW		 4754struct asm_shift_name
4755{
4756 const char *name;
4757 enum shift_kind kind;
4758};
b99bd4ef 4759
c19d1205
ZW		 4760/* Third argument to parse_shift. */
4761enum parse_shift_mode
4762{
4763 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
4764 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
4765 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
4766 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
4767 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
4768};
b99bd4ef 4769
c19d1205
ZW		 4770/* Parse a <shift> specifier on an ARM data processing instruction.
4771 This has three forms:
b99bd4ef 4772
c19d1205
ZW		 4773 (LSL|LSR|ASL|ASR|ROR) Rs
4774 (LSL|LSR|ASL|ASR|ROR) #imm
4775 RRX
b99bd4ef 4776
c19d1205
ZW		 4777 Note that ASL is assimilated to LSL in the instruction encoding, and
4778 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 4779
c19d1205
ZW		 4780static int
4781parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 4782{
c19d1205
ZW		 4783 const struct asm_shift_name *shift_name;
4784 enum shift_kind shift;
4785 char *s = *str;
4786 char *p = s;
4787 int reg;
b99bd4ef 4788
c19d1205
ZW		 4789 for (p = *str; ISALPHA (*p); p++)
4790 ;
b99bd4ef 4791
c19d1205 4792 if (p == *str)
b99bd4ef 4793 {
c19d1205
ZW		 4794 inst.error = _("shift expression expected");
4795 return FAIL;
b99bd4ef
NC		 4796 }
4797
21d799b5 4798 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 4799 p - *str);
c19d1205
ZW		 4800
4801 if (shift_name == NULL)
b99bd4ef 4802 {
c19d1205
ZW		 4803 inst.error = _("shift expression expected");
4804 return FAIL;
b99bd4ef
NC		 4805 }
4806
c19d1205 4807 shift = shift_name->kind;
b99bd4ef 4808
c19d1205
ZW		 4809 switch (mode)
4810 {
4811 case NO_SHIFT_RESTRICT:
4812 case SHIFT_IMMEDIATE: break;
b99bd4ef 4813
c19d1205
ZW		 4814 case SHIFT_LSL_OR_ASR_IMMEDIATE:
4815 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
4816 {
4817 inst.error = _("'LSL' or 'ASR' required");
4818 return FAIL;
4819 }
4820 break;
b99bd4ef 4821
c19d1205
ZW		 4822 case SHIFT_LSL_IMMEDIATE:
4823 if (shift != SHIFT_LSL)
4824 {
4825 inst.error = _("'LSL' required");
4826 return FAIL;
4827 }
4828 break;
b99bd4ef 4829
c19d1205
ZW		 4830 case SHIFT_ASR_IMMEDIATE:
4831 if (shift != SHIFT_ASR)
4832 {
4833 inst.error = _("'ASR' required");
4834 return FAIL;
4835 }
4836 break;
b99bd4ef 4837
c19d1205
ZW		 4838 default: abort ();
4839 }
b99bd4ef 4840
c19d1205
ZW		 4841 if (shift != SHIFT_RRX)
4842 {
4843 /* Whitespace can appear here if the next thing is a bare digit. */
4844 skip_whitespace (p);
b99bd4ef 4845
c19d1205 4846 if (mode == NO_SHIFT_RESTRICT
dcbf9037 4847 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 4848 {
4849 inst.operands[i].imm = reg;
4850 inst.operands[i].immisreg = 1;
4851 }
4852 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4853 return FAIL;
4854 }
4855 inst.operands[i].shift_kind = shift;
4856 inst.operands[i].shifted = 1;
4857 *str = p;
4858 return SUCCESS;
b99bd4ef
NC		 4859}
4860
c19d1205 4861/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 4862
c19d1205
ZW		 4863 #<immediate>
4864 #<immediate>, <rotate>
4865 <Rm>
4866 <Rm>, <shift>
b99bd4ef 4867
c19d1205
ZW		 4868 where <shift> is defined by parse_shift above, and <rotate> is a
4869 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 4870 is deferred to md_apply_fix. */
b99bd4ef 4871
c19d1205
ZW		 4872static int
4873parse_shifter_operand (char **str, int i)
4874{
4875 int value;
91d6fa6a 4876 expressionS exp;
b99bd4ef 4877
dcbf9037 4878 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 4879 {
4880 inst.operands[i].reg = value;
4881 inst.operands[i].isreg = 1;
b99bd4ef 4882
c19d1205
ZW		 4883 /* parse_shift will override this if appropriate */
4884 inst.reloc.exp.X_op = O_constant;
4885 inst.reloc.exp.X_add_number = 0;
b99bd4ef 4886
c19d1205
ZW		 4887 if (skip_past_comma (str) == FAIL)
4888 return SUCCESS;
b99bd4ef 4889
c19d1205
ZW		 4890 /* Shift operation on register. */
4891 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC		 4892 }
4893
c19d1205
ZW		 4894 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
4895 return FAIL;
b99bd4ef 4896
c19d1205 4897 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 4898 {
c19d1205 4899 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 4900 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 4901 return FAIL;
b99bd4ef 4902
91d6fa6a 4903 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
c19d1205
ZW		 4904 {
4905 inst.error = _("constant expression expected");
4906 return FAIL;
4907 }
b99bd4ef 4908
91d6fa6a 4909 value = exp.X_add_number;
c19d1205
ZW		 4910 if (value < 0 || value > 30 || value % 2 != 0)
4911 {
4912 inst.error = _("invalid rotation");
4913 return FAIL;
4914 }
4915 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
4916 {
4917 inst.error = _("invalid constant");
4918 return FAIL;
4919 }
09d92015 4920
a415b1cd
JB		 4921 /* Encode as specified. */
4922 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
4923 return SUCCESS;
09d92015
MM		 4924 }
4925
c19d1205
ZW		 4926 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
4927 inst.reloc.pc_rel = 0;
4928 return SUCCESS;
09d92015
MM		 4929}
4930
4962c51a
MS		 4931/* Group relocation information. Each entry in the table contains the
4932 textual name of the relocation as may appear in assembler source
4933 and must end with a colon.
4934 Along with this textual name are the relocation codes to be used if
4935 the corresponding instruction is an ALU instruction (ADD or SUB only),
4936 an LDR, an LDRS, or an LDC. */
4937
4938struct group_reloc_table_entry
4939{
4940 const char *name;
4941 int alu_code;
4942 int ldr_code;
4943 int ldrs_code;
4944 int ldc_code;
4945};
4946
4947typedef enum
4948{
4949 /* Varieties of non-ALU group relocation. */
4950
4951 GROUP_LDR,
4952 GROUP_LDRS,
4953 GROUP_LDC
4954} group_reloc_type;
4955
4956static struct group_reloc_table_entry group_reloc_table[] =
4957 { /* Program counter relative: */
4958 { "pc_g0_nc",
4959 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
4960 0, /* LDR */
4961 0, /* LDRS */
4962 0 }, /* LDC */
4963 { "pc_g0",
4964 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
4965 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
4966 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
4967 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
4968 { "pc_g1_nc",
4969 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
4970 0, /* LDR */
4971 0, /* LDRS */
4972 0 }, /* LDC */
4973 { "pc_g1",
4974 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
4975 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
4976 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
4977 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
4978 { "pc_g2",
4979 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
4980 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
4981 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
4982 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
4983 /* Section base relative */
4984 { "sb_g0_nc",
4985 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
4986 0, /* LDR */
4987 0, /* LDRS */
4988 0 }, /* LDC */
4989 { "sb_g0",
4990 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
4991 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
4992 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
4993 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
4994 { "sb_g1_nc",
4995 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
4996 0, /* LDR */
4997 0, /* LDRS */
4998 0 }, /* LDC */
4999 { "sb_g1",
5000 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5001 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5002 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5003 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5004 { "sb_g2",
5005 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5006 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5007 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5008 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5009
5010/* Given the address of a pointer pointing to the textual name of a group
5011 relocation as may appear in assembler source, attempt to find its details
5012 in group_reloc_table. The pointer will be updated to the character after
5013 the trailing colon. On failure, FAIL will be returned; SUCCESS
5014 otherwise. On success, *entry will be updated to point at the relevant
5015 group_reloc_table entry. */
5016
5017static int
5018find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5019{
5020 unsigned int i;
5021 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5022 {
5023 int length = strlen (group_reloc_table[i].name);
5024
5f4273c7
NC		 5025 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5026 && (*str)[length] == ':')
477330fc
RM		 5027 {
5028 *out = &group_reloc_table[i];
5029 *str += (length + 1);
5030 return SUCCESS;
5031 }
4962c51a
MS		 5032 }
5033
5034 return FAIL;
5035}
5036
5037/* Parse a <shifter_operand> for an ARM data processing instruction
5038 (as for parse_shifter_operand) where group relocations are allowed:
5039
5040 #<immediate>
5041 #<immediate>, <rotate>
5042 #:<group_reloc>:<expression>
5043 <Rm>
5044 <Rm>, <shift>
5045
5046 where <group_reloc> is one of the strings defined in group_reloc_table.
5047 The hashes are optional.
5048
5049 Everything else is as for parse_shifter_operand. */
5050
5051static parse_operand_result
5052parse_shifter_operand_group_reloc (char **str, int i)
5053{
5054 /* Determine if we have the sequence of characters #: or just :
5055 coming next. If we do, then we check for a group relocation.
5056 If we don't, punt the whole lot to parse_shifter_operand. */
5057
5058 if (((*str)[0] == '#' && (*str)[1] == ':')
5059 || (*str)[0] == ':')
5060 {
5061 struct group_reloc_table_entry *entry;
5062
5063 if ((*str)[0] == '#')
477330fc 5064 (*str) += 2;
4962c51a 5065 else
477330fc 5066 (*str)++;
4962c51a
MS		 5067
5068 /* Try to parse a group relocation. Anything else is an error. */
5069 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM		 5070 {
5071 inst.error = _("unknown group relocation");
5072 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5073 }
4962c51a
MS		 5074
5075 /* We now have the group relocation table entry corresponding to
477330fc 5076 the name in the assembler source. Next, we parse the expression. */
4962c51a 5077 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
477330fc 5078 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS		 5079
5080 /* Record the relocation type (always the ALU variant here). */
21d799b5 5081 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
9c2799c2 5082 gas_assert (inst.reloc.type != 0);
4962c51a
MS		 5083
5084 return PARSE_OPERAND_SUCCESS;
5085 }
5086 else
5087 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5088 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS		 5089
5090 /* Never reached. */
5091}
5092
8e560766
MGD		 5093/* Parse a Neon alignment expression. Information is written to
5094 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5095
8e560766
MGD		 5096 align .imm = align << 8, .immisalign=1, .preind=0 */
5097static parse_operand_result
5098parse_neon_alignment (char **str, int i)
5099{
5100 char *p = *str;
5101 expressionS exp;
5102
5103 my_get_expression (&exp, &p, GE_NO_PREFIX);
5104
5105 if (exp.X_op != O_constant)
5106 {
5107 inst.error = _("alignment must be constant");
5108 return PARSE_OPERAND_FAIL;
5109 }
5110
5111 inst.operands[i].imm = exp.X_add_number << 8;
5112 inst.operands[i].immisalign = 1;
5113 /* Alignments are not pre-indexes. */
5114 inst.operands[i].preind = 0;
5115
5116 *str = p;
5117 return PARSE_OPERAND_SUCCESS;
5118}
5119
c19d1205
ZW		 5120/* Parse all forms of an ARM address expression. Information is written
5121 to inst.operands[i] and/or inst.reloc.
09d92015 5122
c19d1205 5123 Preindexed addressing (.preind=1):
09d92015 5124
c19d1205
ZW		 5125 [Rn, #offset] .reg=Rn .reloc.exp=offset
5126 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5127 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5128 .shift_kind=shift .reloc.exp=shift_imm
09d92015 5129
c19d1205 5130 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5131
c19d1205 5132 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5133
c19d1205
ZW		 5134 [Rn], #offset .reg=Rn .reloc.exp=offset
5135 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5136 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5137 .shift_kind=shift .reloc.exp=shift_imm
09d92015 5138
c19d1205 5139 Unindexed addressing (.preind=0, .postind=0):
09d92015 5140
c19d1205 5141 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5142
c19d1205 5143 Other:
09d92015 5144
c19d1205
ZW		 5145 [Rn]{!} shorthand for [Rn,#0]{!}
5146 =immediate .isreg=0 .reloc.exp=immediate
5147 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
09d92015 5148
c19d1205
ZW		 5149 It is the caller's responsibility to check for addressing modes not
5150 supported by the instruction, and to set inst.reloc.type. */
5151
4962c51a
MS		 5152static parse_operand_result
5153parse_address_main (char **str, int i, int group_relocations,
477330fc 5154 group_reloc_type group_type)
09d92015 5155{
c19d1205
ZW		 5156 char *p = *str;
5157 int reg;
09d92015 5158
c19d1205 5159 if (skip_past_char (&p, '[') == FAIL)
09d92015 5160 {
c19d1205
ZW		 5161 if (skip_past_char (&p, '=') == FAIL)
5162 {
974da60d 5163 /* Bare address - translate to PC-relative offset. */
c19d1205
ZW		 5164 inst.reloc.pc_rel = 1;
5165 inst.operands[i].reg = REG_PC;
5166 inst.operands[i].isreg = 1;
5167 inst.operands[i].preind = 1;
5168 }
974da60d 5169 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
09d92015 5170
c19d1205 5171 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
4962c51a 5172 return PARSE_OPERAND_FAIL;
09d92015 5173
c19d1205 5174 *str = p;
4962c51a 5175 return PARSE_OPERAND_SUCCESS;
09d92015
MM		 5176 }
5177
8ab8155f
NC		 5178 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5179 skip_whitespace (p);
5180
dcbf9037 5181 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5182 {
c19d1205 5183 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5184 return PARSE_OPERAND_FAIL;
09d92015 5185 }
c19d1205
ZW		 5186 inst.operands[i].reg = reg;
5187 inst.operands[i].isreg = 1;
09d92015 5188
c19d1205 5189 if (skip_past_comma (&p) == SUCCESS)
09d92015 5190 {
c19d1205 5191 inst.operands[i].preind = 1;
09d92015 5192
c19d1205
ZW		 5193 if (*p == '+') p++;
5194 else if (*p == '-') p++, inst.operands[i].negative = 1;
5195
dcbf9037 5196 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5197 {
c19d1205
ZW		 5198 inst.operands[i].imm = reg;
5199 inst.operands[i].immisreg = 1;
5200
5201 if (skip_past_comma (&p) == SUCCESS)
5202 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5203 return PARSE_OPERAND_FAIL;
c19d1205 5204 }
5287ad62 5205 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD		 5206 {
5207 /* FIXME: '@' should be used here, but it's filtered out by generic
5208 code before we get to see it here. This may be subject to
5209 change. */
5210 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5211
8e560766
MGD		 5212 if (result != PARSE_OPERAND_SUCCESS)
5213 return result;
5214 }
c19d1205
ZW		 5215 else
5216 {
5217 if (inst.operands[i].negative)
5218 {
5219 inst.operands[i].negative = 0;
5220 p--;
5221 }
4962c51a 5222
5f4273c7
NC		 5223 if (group_relocations
5224 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS		 5225 {
5226 struct group_reloc_table_entry *entry;
5227
477330fc
RM		 5228 /* Skip over the #: or : sequence. */
5229 if (*p == '#')
5230 p += 2;
5231 else
5232 p++;
4962c51a
MS		 5233
5234 /* Try to parse a group relocation. Anything else is an
477330fc 5235 error. */
4962c51a
MS		 5236 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5237 {
5238 inst.error = _("unknown group relocation");
5239 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5240 }
5241
5242 /* We now have the group relocation table entry corresponding to
5243 the name in the assembler source. Next, we parse the
477330fc 5244 expression. */
4962c51a
MS		 5245 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5246 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5247
5248 /* Record the relocation type. */
477330fc
RM		 5249 switch (group_type)
5250 {
5251 case GROUP_LDR:
5252 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5253 break;
4962c51a 5254
477330fc
RM		 5255 case GROUP_LDRS:
5256 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5257 break;
4962c51a 5258
477330fc
RM		 5259 case GROUP_LDC:
5260 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5261 break;
4962c51a 5262
477330fc
RM		 5263 default:
5264 gas_assert (0);
5265 }
4962c51a 5266
477330fc 5267 if (inst.reloc.type == 0)
4962c51a
MS		 5268 {
5269 inst.error = _("this group relocation is not allowed on this instruction");
5270 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5271 }
477330fc
RM		 5272 }
5273 else
26d97720
NS		 5274 {
5275 char *q = p;
5276 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5277 return PARSE_OPERAND_FAIL;
5278 /* If the offset is 0, find out if it's a +0 or -0. */
5279 if (inst.reloc.exp.X_op == O_constant
5280 && inst.reloc.exp.X_add_number == 0)
5281 {
5282 skip_whitespace (q);
5283 if (*q == '#')
5284 {
5285 q++;
5286 skip_whitespace (q);
5287 }
5288 if (*q == '-')
5289 inst.operands[i].negative = 1;
5290 }
5291 }
09d92015
MM		 5292 }
5293 }
8e560766
MGD		 5294 else if (skip_past_char (&p, ':') == SUCCESS)
5295 {
5296 /* FIXME: '@' should be used here, but it's filtered out by generic code
5297 before we get to see it here. This may be subject to change. */
5298 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5299
8e560766
MGD		 5300 if (result != PARSE_OPERAND_SUCCESS)
5301 return result;
5302 }
09d92015 5303
c19d1205 5304 if (skip_past_char (&p, ']') == FAIL)
09d92015 5305 {
c19d1205 5306 inst.error = _("']' expected");
4962c51a 5307 return PARSE_OPERAND_FAIL;
09d92015
MM		 5308 }
5309
c19d1205
ZW		 5310 if (skip_past_char (&p, '!') == SUCCESS)
5311 inst.operands[i].writeback = 1;
09d92015 5312
c19d1205 5313 else if (skip_past_comma (&p) == SUCCESS)
09d92015 5314 {
c19d1205
ZW		 5315 if (skip_past_char (&p, '{') == SUCCESS)
5316 {
5317 /* [Rn], {expr} - unindexed, with option */
5318 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 5319 0, 255, TRUE) == FAIL)
4962c51a 5320 return PARSE_OPERAND_FAIL;
09d92015 5321
c19d1205
ZW		 5322 if (skip_past_char (&p, '}') == FAIL)
5323 {
5324 inst.error = _("'}' expected at end of 'option' field");
4962c51a 5325 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5326 }
5327 if (inst.operands[i].preind)
5328 {
5329 inst.error = _("cannot combine index with option");
4962c51a 5330 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5331 }
5332 *str = p;
4962c51a 5333 return PARSE_OPERAND_SUCCESS;
09d92015 5334 }
c19d1205
ZW		 5335 else
5336 {
5337 inst.operands[i].postind = 1;
5338 inst.operands[i].writeback = 1;
09d92015 5339
c19d1205
ZW		 5340 if (inst.operands[i].preind)
5341 {
5342 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 5343 return PARSE_OPERAND_FAIL;
c19d1205 5344 }
09d92015 5345
c19d1205
ZW		 5346 if (*p == '+') p++;
5347 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 5348
dcbf9037 5349 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 5350 {
477330fc
RM		 5351 /* We might be using the immediate for alignment already. If we
5352 are, OR the register number into the low-order bits. */
5353 if (inst.operands[i].immisalign)
5354 inst.operands[i].imm |= reg;
5355 else
5356 inst.operands[i].imm = reg;
c19d1205 5357 inst.operands[i].immisreg = 1;
a737bd4d 5358
c19d1205
ZW		 5359 if (skip_past_comma (&p) == SUCCESS)
5360 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5361 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5362 }
5363 else
5364 {
26d97720 5365 char *q = p;
c19d1205
ZW		 5366 if (inst.operands[i].negative)
5367 {
5368 inst.operands[i].negative = 0;
5369 p--;
5370 }
5371 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4962c51a 5372 return PARSE_OPERAND_FAIL;
26d97720
NS		 5373 /* If the offset is 0, find out if it's a +0 or -0. */
5374 if (inst.reloc.exp.X_op == O_constant
5375 && inst.reloc.exp.X_add_number == 0)
5376 {
5377 skip_whitespace (q);
5378 if (*q == '#')
5379 {
5380 q++;
5381 skip_whitespace (q);
5382 }
5383 if (*q == '-')
5384 inst.operands[i].negative = 1;
5385 }
c19d1205
ZW		 5386 }
5387 }
a737bd4d
NC		 5388 }
5389
c19d1205
ZW		 5390 /* If at this point neither .preind nor .postind is set, we have a
5391 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5392 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5393 {
5394 inst.operands[i].preind = 1;
5395 inst.reloc.exp.X_op = O_constant;
5396 inst.reloc.exp.X_add_number = 0;
5397 }
5398 *str = p;
4962c51a
MS		 5399 return PARSE_OPERAND_SUCCESS;
5400}
5401
5402static int
5403parse_address (char **str, int i)
5404{
21d799b5 5405 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 5406 ? SUCCESS : FAIL;
4962c51a
MS		 5407}
5408
5409static parse_operand_result
5410parse_address_group_reloc (char **str, int i, group_reloc_type type)
5411{
5412 return parse_address_main (str, i, 1, type);
a737bd4d
NC		 5413}
5414
b6895b4f
PB		 5415/* Parse an operand for a MOVW or MOVT instruction. */
5416static int
5417parse_half (char **str)
5418{
5419 char * p;
5f4273c7 5420
b6895b4f
PB		 5421 p = *str;
5422 skip_past_char (&p, '#');
5f4273c7 5423 if (strncasecmp (p, ":lower16:", 9) == 0)
b6895b4f
PB		 5424 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5425 else if (strncasecmp (p, ":upper16:", 9) == 0)
5426 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5427
5428 if (inst.reloc.type != BFD_RELOC_UNUSED)
5429 {
5430 p += 9;
5f4273c7 5431 skip_whitespace (p);
b6895b4f
PB		 5432 }
5433
5434 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5435 return FAIL;
5436
5437 if (inst.reloc.type == BFD_RELOC_UNUSED)
5438 {
5439 if (inst.reloc.exp.X_op != O_constant)
5440 {
5441 inst.error = _("constant expression expected");
5442 return FAIL;
5443 }
5444 if (inst.reloc.exp.X_add_number < 0
5445 || inst.reloc.exp.X_add_number > 0xffff)
5446 {
5447 inst.error = _("immediate value out of range");
5448 return FAIL;
5449 }
5450 }
5451 *str = p;
5452 return SUCCESS;
5453}
5454
c19d1205 5455/* Miscellaneous. */
a737bd4d 5456
c19d1205
ZW		 5457/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5458 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5459static int
d2cd1205 5460parse_psr (char **str, bfd_boolean lhs)
09d92015 5461{
c19d1205
ZW		 5462 char *p;
5463 unsigned long psr_field;
62b3e311
PB		 5464 const struct asm_psr *psr;
5465 char *start;
d2cd1205 5466 bfd_boolean is_apsr = FALSE;
ac7f631b 5467 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 5468
a4482bb6
NC		 5469 /* PR gas/12698: If the user has specified -march=all then m_profile will
5470 be TRUE, but we want to ignore it in this case as we are building for any
5471 CPU type, including non-m variants. */
5472 if (selected_cpu.core == arm_arch_any.core)
5473 m_profile = FALSE;
5474
c19d1205
ZW		 5475 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5476 feature for ease of use and backwards compatibility. */
5477 p = *str;
62b3e311 5478 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB		 5479 {
5480 if (m_profile)
5481 goto unsupported_psr;
fa94de6b 5482
d2cd1205
JB		 5483 psr_field = SPSR_BIT;
5484 }
5485 else if (strncasecmp (p, "CPSR", 4) == 0)
5486 {
5487 if (m_profile)
5488 goto unsupported_psr;
5489
5490 psr_field = 0;
5491 }
5492 else if (strncasecmp (p, "APSR", 4) == 0)
5493 {
5494 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5495 and ARMv7-R architecture CPUs. */
5496 is_apsr = TRUE;
5497 psr_field = 0;
5498 }
5499 else if (m_profile)
62b3e311
PB		 5500 {
5501 start = p;
5502 do
5503 p++;
5504 while (ISALNUM (*p) || *p == '_');
5505
d2cd1205
JB		 5506 if (strncasecmp (start, "iapsr", 5) == 0
5507 || strncasecmp (start, "eapsr", 5) == 0
5508 || strncasecmp (start, "xpsr", 4) == 0
5509 || strncasecmp (start, "psr", 3) == 0)
5510 p = start + strcspn (start, "rR") + 1;
5511
21d799b5 5512 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 5513 p - start);
d2cd1205 5514
62b3e311
PB		 5515 if (!psr)
5516 return FAIL;
09d92015 5517
d2cd1205
JB		 5518 /* If APSR is being written, a bitfield may be specified. Note that
5519 APSR itself is handled above. */
5520 if (psr->field <= 3)
5521 {
5522 psr_field = psr->field;
5523 is_apsr = TRUE;
5524 goto check_suffix;
5525 }
5526
62b3e311 5527 *str = p;
d2cd1205
JB		 5528 /* M-profile MSR instructions have the mask field set to "10", except
5529 *PSR variants which modify APSR, which may use a different mask (and
5530 have been handled already). Do that by setting the PSR_f field
5531 here. */
5532 return psr->field | (lhs ? PSR_f : 0);
62b3e311 5533 }
d2cd1205
JB		 5534 else
5535 goto unsupported_psr;
09d92015 5536
62b3e311 5537 p += 4;
d2cd1205 5538check_suffix:
c19d1205
ZW		 5539 if (*p == '_')
5540 {
5541 /* A suffix follows. */
c19d1205
ZW		 5542 p++;
5543 start = p;
a737bd4d 5544
c19d1205
ZW		 5545 do
5546 p++;
5547 while (ISALNUM (*p) || *p == '_');
a737bd4d 5548
d2cd1205
JB		 5549 if (is_apsr)
5550 {
5551 /* APSR uses a notation for bits, rather than fields. */
5552 unsigned int nzcvq_bits = 0;
5553 unsigned int g_bit = 0;
5554 char *bit;
fa94de6b 5555
d2cd1205
JB		 5556 for (bit = start; bit != p; bit++)
5557 {
5558 switch (TOLOWER (*bit))
477330fc 5559 {
d2cd1205
JB		 5560 case 'n':
5561 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5562 break;
5563
5564 case 'z':
5565 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5566 break;
5567
5568 case 'c':
5569 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5570 break;
5571
5572 case 'v':
5573 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5574 break;
fa94de6b 5575
d2cd1205
JB		 5576 case 'q':
5577 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5578 break;
fa94de6b 5579
d2cd1205
JB		 5580 case 'g':
5581 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5582 break;
fa94de6b 5583
d2cd1205
JB		 5584 default:
5585 inst.error = _("unexpected bit specified after APSR");
5586 return FAIL;
5587 }
5588 }
fa94de6b 5589
d2cd1205
JB		 5590 if (nzcvq_bits == 0x1f)
5591 psr_field |= PSR_f;
fa94de6b 5592
d2cd1205
JB		 5593 if (g_bit == 0x1)
5594 {
5595 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 5596 {
d2cd1205
JB		 5597 inst.error = _("selected processor does not "
5598 "support DSP extension");
5599 return FAIL;
5600 }
5601
5602 psr_field |= PSR_s;
5603 }
fa94de6b 5604
d2cd1205
JB		 5605 if ((nzcvq_bits & 0x20) != 0
5606 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5607 || (g_bit & 0x2) != 0)
5608 {
5609 inst.error = _("bad bitmask specified after APSR");
5610 return FAIL;
5611 }
5612 }
5613 else
477330fc 5614 {
d2cd1205 5615 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 5616 p - start);
d2cd1205 5617 if (!psr)
477330fc 5618 goto error;
a737bd4d 5619
d2cd1205
JB		 5620 psr_field |= psr->field;
5621 }
a737bd4d 5622 }
c19d1205 5623 else
a737bd4d 5624 {
c19d1205
ZW		 5625 if (ISALNUM (*p))
5626 goto error; /* Garbage after "[CS]PSR". */
5627
d2cd1205 5628 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 5629 is deprecated, but allow it anyway. */
d2cd1205
JB		 5630 if (is_apsr && lhs)
5631 {
5632 psr_field |= PSR_f;
5633 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5634 "deprecated"));
5635 }
5636 else if (!m_profile)
5637 /* These bits are never right for M-profile devices: don't set them
5638 (only code paths which read/write APSR reach here). */
5639 psr_field |= (PSR_c | PSR_f);
a737bd4d 5640 }
c19d1205
ZW		 5641 *str = p;
5642 return psr_field;
a737bd4d 5643
d2cd1205
JB		 5644 unsupported_psr:
5645 inst.error = _("selected processor does not support requested special "
5646 "purpose register");
5647 return FAIL;
5648
c19d1205
ZW		 5649 error:
5650 inst.error = _("flag for {c}psr instruction expected");
5651 return FAIL;
a737bd4d
NC		 5652}
5653
c19d1205
ZW		 5654/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5655 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 5656
c19d1205
ZW		 5657static int
5658parse_cps_flags (char **str)
a737bd4d 5659{
c19d1205
ZW		 5660 int val = 0;
5661 int saw_a_flag = 0;
5662 char *s = *str;
a737bd4d 5663
c19d1205
ZW		 5664 for (;;)
5665 switch (*s++)
5666 {
5667 case '\0': case ',':
5668 goto done;
a737bd4d 5669
c19d1205
ZW		 5670 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5671 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5672 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 5673
c19d1205
ZW		 5674 default:
5675 inst.error = _("unrecognized CPS flag");
5676 return FAIL;
5677 }
a737bd4d 5678
c19d1205
ZW		 5679 done:
5680 if (saw_a_flag == 0)
a737bd4d 5681 {
c19d1205
ZW		 5682 inst.error = _("missing CPS flags");
5683 return FAIL;
a737bd4d 5684 }
a737bd4d 5685
c19d1205
ZW		 5686 *str = s - 1;
5687 return val;
a737bd4d
NC		 5688}
5689
c19d1205
ZW		 5690/* Parse an endian specifier ("BE" or "LE", case insensitive);
5691 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC		 5692
5693static int
c19d1205 5694parse_endian_specifier (char **str)
a737bd4d 5695{
c19d1205
ZW		 5696 int little_endian;
5697 char *s = *str;
a737bd4d 5698
c19d1205
ZW		 5699 if (strncasecmp (s, "BE", 2))
5700 little_endian = 0;
5701 else if (strncasecmp (s, "LE", 2))
5702 little_endian = 1;
5703 else
a737bd4d 5704 {
c19d1205 5705 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 5706 return FAIL;
5707 }
5708
c19d1205 5709 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 5710 {
c19d1205 5711 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 5712 return FAIL;
5713 }
5714
c19d1205
ZW		 5715 *str = s + 2;
5716 return little_endian;
5717}
a737bd4d 5718
c19d1205
ZW		 5719/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5720 value suitable for poking into the rotate field of an sxt or sxta
5721 instruction, or FAIL on error. */
5722
5723static int
5724parse_ror (char **str)
5725{
5726 int rot;
5727 char *s = *str;
5728
5729 if (strncasecmp (s, "ROR", 3) == 0)
5730 s += 3;
5731 else
a737bd4d 5732 {
c19d1205 5733 inst.error = _("missing rotation field after comma");
a737bd4d
NC		 5734 return FAIL;
5735 }
c19d1205
ZW		 5736
5737 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
5738 return FAIL;
5739
5740 switch (rot)
a737bd4d 5741 {
c19d1205
ZW		 5742 case 0: *str = s; return 0x0;
5743 case 8: *str = s; return 0x1;
5744 case 16: *str = s; return 0x2;
5745 case 24: *str = s; return 0x3;
5746
5747 default:
5748 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC		 5749 return FAIL;
5750 }
c19d1205 5751}
a737bd4d 5752
c19d1205
ZW		 5753/* Parse a conditional code (from conds[] below). The value returned is in the
5754 range 0 .. 14, or FAIL. */
5755static int
5756parse_cond (char **str)
5757{
c462b453 5758 char *q;
c19d1205 5759 const struct asm_cond *c;
c462b453
PB		 5760 int n;
5761 /* Condition codes are always 2 characters, so matching up to
5762 3 characters is sufficient. */
5763 char cond[3];
a737bd4d 5764
c462b453
PB		 5765 q = *str;
5766 n = 0;
5767 while (ISALPHA (*q) && n < 3)
5768 {
e07e6e58 5769 cond[n] = TOLOWER (*q);
c462b453
PB		 5770 q++;
5771 n++;
5772 }
a737bd4d 5773
21d799b5 5774 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 5775 if (!c)
a737bd4d 5776 {
c19d1205 5777 inst.error = _("condition required");
a737bd4d
NC		 5778 return FAIL;
5779 }
5780
c19d1205
ZW		 5781 *str = q;
5782 return c->value;
5783}
5784
e797f7e0
MGD		 5785/* If the given feature available in the selected CPU, mark it as used.
5786 Returns TRUE iff feature is available. */
5787static bfd_boolean
5788mark_feature_used (const arm_feature_set *feature)
5789{
5790 /* Ensure the option is valid on the current architecture. */
5791 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
5792 return FALSE;
5793
5794 /* Add the appropriate architecture feature for the barrier option used.
5795 */
5796 if (thumb_mode)
5797 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
5798 else
5799 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
5800
5801 return TRUE;
5802}
5803
62b3e311
PB		 5804/* Parse an option for a barrier instruction. Returns the encoding for the
5805 option, or FAIL. */
5806static int
5807parse_barrier (char **str)
5808{
5809 char *p, *q;
5810 const struct asm_barrier_opt *o;
5811
5812 p = q = *str;
5813 while (ISALPHA (*q))
5814 q++;
5815
21d799b5 5816 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 5817 q - p);
62b3e311
PB		 5818 if (!o)
5819 return FAIL;
5820
e797f7e0
MGD		 5821 if (!mark_feature_used (&o->arch))
5822 return FAIL;
5823
62b3e311
PB		 5824 *str = q;
5825 return o->value;
5826}
5827
92e90b6e
PB		 5828/* Parse the operands of a table branch instruction. Similar to a memory
5829 operand. */
5830static int
5831parse_tb (char **str)
5832{
5833 char * p = *str;
5834 int reg;
5835
5836 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB		 5837 {
5838 inst.error = _("'[' expected");
5839 return FAIL;
5840 }
92e90b6e 5841
dcbf9037 5842 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 5843 {
5844 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5845 return FAIL;
5846 }
5847 inst.operands[0].reg = reg;
5848
5849 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB		 5850 {
5851 inst.error = _("',' expected");
5852 return FAIL;
5853 }
5f4273c7 5854
dcbf9037 5855 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 5856 {
5857 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
5858 return FAIL;
5859 }
5860 inst.operands[0].imm = reg;
5861
5862 if (skip_past_comma (&p) == SUCCESS)
5863 {
5864 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
5865 return FAIL;
5866 if (inst.reloc.exp.X_add_number != 1)
5867 {
5868 inst.error = _("invalid shift");
5869 return FAIL;
5870 }
5871 inst.operands[0].shifted = 1;
5872 }
5873
5874 if (skip_past_char (&p, ']') == FAIL)
5875 {
5876 inst.error = _("']' expected");
5877 return FAIL;
5878 }
5879 *str = p;
5880 return SUCCESS;
5881}
5882
5287ad62
JB		 5883/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5884 information on the types the operands can take and how they are encoded.
037e8744
JB		 5885 Up to four operands may be read; this function handles setting the
5886 ".present" field for each read operand itself.
5287ad62
JB		 5887 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5888 else returns FAIL. */
5889
5890static int
5891parse_neon_mov (char **str, int *which_operand)
5892{
5893 int i = *which_operand, val;
5894 enum arm_reg_type rtype;
5895 char *ptr = *str;
dcbf9037 5896 struct neon_type_el optype;
5f4273c7 5897
dcbf9037 5898 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB		 5899 {
5900 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5901 inst.operands[i].reg = val;
5902 inst.operands[i].isscalar = 1;
dcbf9037 5903 inst.operands[i].vectype = optype;
5287ad62
JB		 5904 inst.operands[i++].present = 1;
5905
5906 if (skip_past_comma (&ptr) == FAIL)
477330fc 5907 goto wanted_comma;
5f4273c7 5908
dcbf9037 5909 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 5910 goto wanted_arm;
5f4273c7 5911
5287ad62
JB		 5912 inst.operands[i].reg = val;
5913 inst.operands[i].isreg = 1;
5914 inst.operands[i].present = 1;
5915 }
037e8744 5916 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
477330fc 5917 != FAIL)
5287ad62
JB		 5918 {
5919 /* Cases 0, 1, 2, 3, 5 (D only). */
5920 if (skip_past_comma (&ptr) == FAIL)
477330fc 5921 goto wanted_comma;
5f4273c7 5922
5287ad62
JB		 5923 inst.operands[i].reg = val;
5924 inst.operands[i].isreg = 1;
5925 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB		 5926 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5927 inst.operands[i].isvec = 1;
dcbf9037 5928 inst.operands[i].vectype = optype;
5287ad62
JB		 5929 inst.operands[i++].present = 1;
5930
dcbf9037 5931 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 5932 {
5933 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5934 Case 13: VMOV <Sd>, <Rm> */
5935 inst.operands[i].reg = val;
5936 inst.operands[i].isreg = 1;
5937 inst.operands[i].present = 1;
5938
5939 if (rtype == REG_TYPE_NQ)
5940 {
5941 first_error (_("can't use Neon quad register here"));
5942 return FAIL;
5943 }
5944 else if (rtype != REG_TYPE_VFS)
5945 {
5946 i++;
5947 if (skip_past_comma (&ptr) == FAIL)
5948 goto wanted_comma;
5949 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5950 goto wanted_arm;
5951 inst.operands[i].reg = val;
5952 inst.operands[i].isreg = 1;
5953 inst.operands[i].present = 1;
5954 }
5955 }
037e8744 5956 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
477330fc
RM		 5957 &optype)) != FAIL)
5958 {
5959 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5960 Case 1: VMOV<c><q> <Dd>, <Dm>
5961 Case 8: VMOV.F32 <Sd>, <Sm>
5962 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5963
5964 inst.operands[i].reg = val;
5965 inst.operands[i].isreg = 1;
5966 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
5967 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
5968 inst.operands[i].isvec = 1;
5969 inst.operands[i].vectype = optype;
5970 inst.operands[i].present = 1;
5971
5972 if (skip_past_comma (&ptr) == SUCCESS)
5973 {
5974 /* Case 15. */
5975 i++;
5976
5977 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5978 goto wanted_arm;
5979
5980 inst.operands[i].reg = val;
5981 inst.operands[i].isreg = 1;
5982 inst.operands[i++].present = 1;
5983
5984 if (skip_past_comma (&ptr) == FAIL)
5985 goto wanted_comma;
5986
5987 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
5988 goto wanted_arm;
5989
5990 inst.operands[i].reg = val;
5991 inst.operands[i].isreg = 1;
5992 inst.operands[i].present = 1;
5993 }
5994 }
4641781c 5995 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM		 5996 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5997 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5998 Case 10: VMOV.F32 <Sd>, #<imm>
5999 Case 11: VMOV.F64 <Dd>, #<imm> */
6000 inst.operands[i].immisfloat = 1;
4641781c 6001 else if (parse_big_immediate (&ptr, i) == SUCCESS)
477330fc
RM		 6002 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6003 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6004 ;
5287ad62 6005 else
477330fc
RM		 6006 {
6007 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6008 return FAIL;
6009 }
5287ad62 6010 }
dcbf9037 6011 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB		 6012 {
6013 /* Cases 6, 7. */
6014 inst.operands[i].reg = val;
6015 inst.operands[i].isreg = 1;
6016 inst.operands[i++].present = 1;
5f4273c7 6017
5287ad62 6018 if (skip_past_comma (&ptr) == FAIL)
477330fc 6019 goto wanted_comma;
5f4273c7 6020
dcbf9037 6021 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
477330fc
RM		 6022 {
6023 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6024 inst.operands[i].reg = val;
6025 inst.operands[i].isscalar = 1;
6026 inst.operands[i].present = 1;
6027 inst.operands[i].vectype = optype;
6028 }
dcbf9037 6029 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6030 {
6031 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6032 inst.operands[i].reg = val;
6033 inst.operands[i].isreg = 1;
6034 inst.operands[i++].present = 1;
6035
6036 if (skip_past_comma (&ptr) == FAIL)
6037 goto wanted_comma;
6038
6039 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6040 == FAIL)
6041 {
6042 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6043 return FAIL;
6044 }
6045
6046 inst.operands[i].reg = val;
6047 inst.operands[i].isreg = 1;
6048 inst.operands[i].isvec = 1;
6049 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6050 inst.operands[i].vectype = optype;
6051 inst.operands[i].present = 1;
6052
6053 if (rtype == REG_TYPE_VFS)
6054 {
6055 /* Case 14. */
6056 i++;
6057 if (skip_past_comma (&ptr) == FAIL)
6058 goto wanted_comma;
6059 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6060 &optype)) == FAIL)
6061 {
6062 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6063 return FAIL;
6064 }
6065 inst.operands[i].reg = val;
6066 inst.operands[i].isreg = 1;
6067 inst.operands[i].isvec = 1;
6068 inst.operands[i].issingle = 1;
6069 inst.operands[i].vectype = optype;
6070 inst.operands[i].present = 1;
6071 }
6072 }
037e8744 6073 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM		 6074 != FAIL)
6075 {
6076 /* Case 13. */
6077 inst.operands[i].reg = val;
6078 inst.operands[i].isreg = 1;
6079 inst.operands[i].isvec = 1;
6080 inst.operands[i].issingle = 1;
6081 inst.operands[i].vectype = optype;
6082 inst.operands[i].present = 1;
6083 }
5287ad62
JB		 6084 }
6085 else
6086 {
dcbf9037 6087 first_error (_("parse error"));
5287ad62
JB		 6088 return FAIL;
6089 }
6090
6091 /* Successfully parsed the operands. Update args. */
6092 *which_operand = i;
6093 *str = ptr;
6094 return SUCCESS;
6095
5f4273c7 6096 wanted_comma:
dcbf9037 6097 first_error (_("expected comma"));
5287ad62 6098 return FAIL;
5f4273c7
NC		 6099
6100 wanted_arm:
dcbf9037 6101 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 6102 return FAIL;
5287ad62
JB		 6103}
6104
5be8be5d
DG		 6105/* Use this macro when the operand constraints are different
6106 for ARM and THUMB (e.g. ldrd). */
6107#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6108 ((arm_operand) | ((thumb_operand) << 16))
6109
c19d1205
ZW		 6110/* Matcher codes for parse_operands. */
6111enum operand_parse_code
6112{
6113 OP_stop, /* end of line */
6114
6115 OP_RR, /* ARM register */
6116 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 6117 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 6118 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 6119 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 6120 optional trailing ! */
c19d1205
ZW		 6121 OP_RRw, /* ARM register, not r15, optional trailing ! */
6122 OP_RCP, /* Coprocessor number */
6123 OP_RCN, /* Coprocessor register */
6124 OP_RF, /* FPA register */
6125 OP_RVS, /* VFP single precision register */
5287ad62
JB		 6126 OP_RVD, /* VFP double precision register (0..15) */
6127 OP_RND, /* Neon double precision register (0..31) */
6128 OP_RNQ, /* Neon quad precision register */
037e8744 6129 OP_RVSD, /* VFP single or double precision register */
5287ad62 6130 OP_RNDQ, /* Neon double or quad precision register */
037e8744 6131 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 6132 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW		 6133 OP_RVC, /* VFP control register */
6134 OP_RMF, /* Maverick F register */
6135 OP_RMD, /* Maverick D register */
6136 OP_RMFX, /* Maverick FX register */
6137 OP_RMDX, /* Maverick DX register */
6138 OP_RMAX, /* Maverick AX register */
6139 OP_RMDS, /* Maverick DSPSC register */
6140 OP_RIWR, /* iWMMXt wR register */
6141 OP_RIWC, /* iWMMXt wC register */
6142 OP_RIWG, /* iWMMXt wCG register */
6143 OP_RXA, /* XScale accumulator register */
6144
6145 OP_REGLST, /* ARM register list */
6146 OP_VRSLST, /* VFP single-precision register list */
6147 OP_VRDLST, /* VFP double-precision register list */
037e8744 6148 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB		 6149 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6150 OP_NSTRLST, /* Neon element/structure list */
6151
5287ad62 6152 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 6153 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
5287ad62 6154 OP_RR_RNSC, /* ARM reg or Neon scalar. */
037e8744 6155 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5287ad62
JB		 6156 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6157 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6158 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 6159 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5287ad62 6160 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
2d447fca 6161 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5287ad62
JB		 6162
6163 OP_I0, /* immediate zero */
c19d1205
ZW		 6164 OP_I7, /* immediate value 0 .. 7 */
6165 OP_I15, /* 0 .. 15 */
6166 OP_I16, /* 1 .. 16 */
5287ad62 6167 OP_I16z, /* 0 .. 16 */
c19d1205
ZW		 6168 OP_I31, /* 0 .. 31 */
6169 OP_I31w, /* 0 .. 31, optional trailing ! */
6170 OP_I32, /* 1 .. 32 */
5287ad62
JB		 6171 OP_I32z, /* 0 .. 32 */
6172 OP_I63, /* 0 .. 63 */
c19d1205 6173 OP_I63s, /* -64 .. 63 */
5287ad62
JB		 6174 OP_I64, /* 1 .. 64 */
6175 OP_I64z, /* 0 .. 64 */
c19d1205 6176 OP_I255, /* 0 .. 255 */
c19d1205
ZW		 6177
6178 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6179 OP_I7b, /* 0 .. 7 */
6180 OP_I15b, /* 0 .. 15 */
6181 OP_I31b, /* 0 .. 31 */
6182
6183 OP_SH, /* shifter operand */
4962c51a 6184 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 6185 OP_ADDR, /* Memory address expression (any mode) */
4962c51a
MS		 6186 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6187 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6188 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW		 6189 OP_EXP, /* arbitrary expression */
6190 OP_EXPi, /* same, with optional immediate prefix */
6191 OP_EXPr, /* same, with optional relocation suffix */
b6895b4f 6192 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c19d1205
ZW		 6193
6194 OP_CPSF, /* CPS flags */
6195 OP_ENDI, /* Endianness specifier */
d2cd1205
JB		 6196 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6197 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 6198 OP_COND, /* conditional code */
92e90b6e 6199 OP_TB, /* Table branch. */
c19d1205 6200
037e8744
JB		 6201 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6202
c19d1205
ZW		 6203 OP_RRnpc_I0, /* ARM register or literal 0 */
6204 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6205 OP_RR_EXi, /* ARM register or expression with imm prefix */
6206 OP_RF_IF, /* FPA register or immediate */
6207 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 6208 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW		 6209
6210 /* Optional operands. */
6211 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6212 OP_oI31b, /* 0 .. 31 */
5287ad62 6213 OP_oI32b, /* 1 .. 32 */
5f1af56b 6214 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW		 6215 OP_oIffffb, /* 0 .. 65535 */
6216 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6217
6218 OP_oRR, /* ARM register */
6219 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 6220 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 6221 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB		 6222 OP_oRND, /* Optional Neon double precision register */
6223 OP_oRNQ, /* Optional Neon quad precision register */
6224 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 6225 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
c19d1205
ZW		 6226 OP_oSHll, /* LSL immediate */
6227 OP_oSHar, /* ASR immediate */
6228 OP_oSHllar, /* LSL or ASR immediate */
6229 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 6230 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 6231
5be8be5d
DG		 6232 /* Some pre-defined mixed (ARM/THUMB) operands. */
6233 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6234 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6235 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6236
c19d1205
ZW		 6237 OP_FIRST_OPTIONAL = OP_oI7b
6238};
a737bd4d 6239
c19d1205
ZW		 6240/* Generic instruction operand parser. This does no encoding and no
6241 semantic validation; it merely squirrels values away in the inst
6242 structure. Returns SUCCESS or FAIL depending on whether the
6243 specified grammar matched. */
6244static int
5be8be5d 6245parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 6246{
5be8be5d 6247 unsigned const int *upat = pattern;
c19d1205
ZW		 6248 char *backtrack_pos = 0;
6249 const char *backtrack_error = 0;
99aad254 6250 int i, val = 0, backtrack_index = 0;
5287ad62 6251 enum arm_reg_type rtype;
4962c51a 6252 parse_operand_result result;
5be8be5d 6253 unsigned int op_parse_code;
c19d1205 6254
e07e6e58
NC		 6255#define po_char_or_fail(chr) \
6256 do \
6257 { \
6258 if (skip_past_char (&str, chr) == FAIL) \
477330fc 6259 goto bad_args; \
e07e6e58
NC		 6260 } \
6261 while (0)
c19d1205 6262
e07e6e58
NC		 6263#define po_reg_or_fail(regtype) \
6264 do \
dcbf9037 6265 { \
e07e6e58 6266 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 6267 & inst.operands[i].vectype); \
e07e6e58 6268 if (val == FAIL) \
477330fc
RM		 6269 { \
6270 first_error (_(reg_expected_msgs[regtype])); \
6271 goto failure; \
6272 } \
e07e6e58
NC		 6273 inst.operands[i].reg = val; \
6274 inst.operands[i].isreg = 1; \
6275 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6276 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6277 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM		 6278 || rtype == REG_TYPE_VFD \
6279 || rtype == REG_TYPE_NQ); \
dcbf9037 6280 } \
e07e6e58
NC		 6281 while (0)
6282
6283#define po_reg_or_goto(regtype, label) \
6284 do \
6285 { \
6286 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6287 & inst.operands[i].vectype); \
6288 if (val == FAIL) \
6289 goto label; \
dcbf9037 6290 \
e07e6e58
NC		 6291 inst.operands[i].reg = val; \
6292 inst.operands[i].isreg = 1; \
6293 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6294 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6295 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 6296 || rtype == REG_TYPE_VFD \
e07e6e58
NC		 6297 || rtype == REG_TYPE_NQ); \
6298 } \
6299 while (0)
6300
6301#define po_imm_or_fail(min, max, popt) \
6302 do \
6303 { \
6304 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6305 goto failure; \
6306 inst.operands[i].imm = val; \
6307 } \
6308 while (0)
6309
6310#define po_scalar_or_goto(elsz, label) \
6311 do \
6312 { \
6313 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6314 if (val == FAIL) \
6315 goto label; \
6316 inst.operands[i].reg = val; \
6317 inst.operands[i].isscalar = 1; \
6318 } \
6319 while (0)
6320
6321#define po_misc_or_fail(expr) \
6322 do \
6323 { \
6324 if (expr) \
6325 goto failure; \
6326 } \
6327 while (0)
6328
6329#define po_misc_or_fail_no_backtrack(expr) \
6330 do \
6331 { \
6332 result = expr; \
6333 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6334 backtrack_pos = 0; \
6335 if (result != PARSE_OPERAND_SUCCESS) \
6336 goto failure; \
6337 } \
6338 while (0)
4962c51a 6339
52e7f43d
RE		 6340#define po_barrier_or_imm(str) \
6341 do \
6342 { \
6343 val = parse_barrier (&str); \
ccb84d65
JB		 6344 if (val == FAIL && ! ISALPHA (*str)) \
6345 goto immediate; \
6346 if (val == FAIL \
6347 /* ISB can only take SY as an option. */ \
6348 || ((inst.instruction & 0xf0) == 0x60 \
6349 && val != 0xf)) \
52e7f43d 6350 { \
ccb84d65
JB		 6351 inst.error = _("invalid barrier type"); \
6352 backtrack_pos = 0; \
6353 goto failure; \
52e7f43d
RE		 6354 } \
6355 } \
6356 while (0)
6357
c19d1205
ZW		 6358 skip_whitespace (str);
6359
6360 for (i = 0; upat[i] != OP_stop; i++)
6361 {
5be8be5d
DG		 6362 op_parse_code = upat[i];
6363 if (op_parse_code >= 1<<16)
6364 op_parse_code = thumb ? (op_parse_code >> 16)
6365 : (op_parse_code & ((1<<16)-1));
6366
6367 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW		 6368 {
6369 /* Remember where we are in case we need to backtrack. */
9c2799c2 6370 gas_assert (!backtrack_pos);
c19d1205
ZW		 6371 backtrack_pos = str;
6372 backtrack_error = inst.error;
6373 backtrack_index = i;
6374 }
6375
b6702015 6376 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW		 6377 po_char_or_fail (',');
6378
5be8be5d 6379 switch (op_parse_code)
c19d1205
ZW		 6380 {
6381 /* Registers */
6382 case OP_oRRnpc:
5be8be5d 6383 case OP_oRRnpcsp:
c19d1205 6384 case OP_RRnpc:
5be8be5d 6385 case OP_RRnpcsp:
c19d1205
ZW		 6386 case OP_oRR:
6387 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6388 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6389 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6390 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6391 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6392 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 6393 case OP_oRND:
5287ad62 6394 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB		 6395 case OP_RVC:
6396 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6397 break;
6398 /* Also accept generic coprocessor regs for unknown registers. */
6399 coproc_reg:
6400 po_reg_or_fail (REG_TYPE_CN);
6401 break;
c19d1205
ZW		 6402 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6403 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6404 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6405 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6406 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6407 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6408 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6409 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6410 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6411 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 6412 case OP_oRNQ:
5287ad62 6413 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
477330fc 6414 case OP_oRNDQ:
5287ad62 6415 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
477330fc
RM		 6416 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6417 case OP_oRNSDQ:
6418 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6419
6420 /* Neon scalar. Using an element size of 8 means that some invalid
6421 scalars are accepted here, so deal with those in later code. */
6422 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6423
6424 case OP_RNDQ_I0:
6425 {
6426 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6427 break;
6428 try_imm0:
6429 po_imm_or_fail (0, 0, TRUE);
6430 }
6431 break;
6432
6433 case OP_RVSD_I0:
6434 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6435 break;
6436
6437 case OP_RR_RNSC:
6438 {
6439 po_scalar_or_goto (8, try_rr);
6440 break;
6441 try_rr:
6442 po_reg_or_fail (REG_TYPE_RN);
6443 }
6444 break;
6445
6446 case OP_RNSDQ_RNSC:
6447 {
6448 po_scalar_or_goto (8, try_nsdq);
6449 break;
6450 try_nsdq:
6451 po_reg_or_fail (REG_TYPE_NSDQ);
6452 }
6453 break;
6454
6455 case OP_RNDQ_RNSC:
6456 {
6457 po_scalar_or_goto (8, try_ndq);
6458 break;
6459 try_ndq:
6460 po_reg_or_fail (REG_TYPE_NDQ);
6461 }
6462 break;
6463
6464 case OP_RND_RNSC:
6465 {
6466 po_scalar_or_goto (8, try_vfd);
6467 break;
6468 try_vfd:
6469 po_reg_or_fail (REG_TYPE_VFD);
6470 }
6471 break;
6472
6473 case OP_VMOV:
6474 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6475 not careful then bad things might happen. */
6476 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6477 break;
6478
6479 case OP_RNDQ_Ibig:
6480 {
6481 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6482 break;
6483 try_immbig:
6484 /* There's a possibility of getting a 64-bit immediate here, so
6485 we need special handling. */
6486 if (parse_big_immediate (&str, i) == FAIL)
6487 {
6488 inst.error = _("immediate value is out of range");
6489 goto failure;
6490 }
6491 }
6492 break;
6493
6494 case OP_RNDQ_I63b:
6495 {
6496 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6497 break;
6498 try_shimm:
6499 po_imm_or_fail (0, 63, TRUE);
6500 }
6501 break;
c19d1205
ZW		 6502
6503 case OP_RRnpcb:
6504 po_char_or_fail ('[');
6505 po_reg_or_fail (REG_TYPE_RN);
6506 po_char_or_fail (']');
6507 break;
a737bd4d 6508
55881a11 6509 case OP_RRnpctw:
c19d1205 6510 case OP_RRw:
b6702015 6511 case OP_oRRw:
c19d1205
ZW		 6512 po_reg_or_fail (REG_TYPE_RN);
6513 if (skip_past_char (&str, '!') == SUCCESS)
6514 inst.operands[i].writeback = 1;
6515 break;
6516
6517 /* Immediates */
6518 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6519 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6520 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 6521 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW		 6522 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6523 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 6524 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
c19d1205 6525 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM		 6526 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6527 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6528 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 6529 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW		 6530
6531 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6532 case OP_oI7b:
6533 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6534 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6535 case OP_oI31b:
6536 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM		 6537 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6538 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW		 6539 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6540
6541 /* Immediate variants */
6542 case OP_oI255c:
6543 po_char_or_fail ('{');
6544 po_imm_or_fail (0, 255, TRUE);
6545 po_char_or_fail ('}');
6546 break;
6547
6548 case OP_I31w:
6549 /* The expression parser chokes on a trailing !, so we have
6550 to find it first and zap it. */
6551 {
6552 char *s = str;
6553 while (*s && *s != ',')
6554 s++;
6555 if (s[-1] == '!')
6556 {
6557 s[-1] = '\0';
6558 inst.operands[i].writeback = 1;
6559 }
6560 po_imm_or_fail (0, 31, TRUE);
6561 if (str == s - 1)
6562 str = s;
6563 }
6564 break;
6565
6566 /* Expressions */
6567 case OP_EXPi: EXPi:
6568 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6569 GE_OPT_PREFIX));
6570 break;
6571
6572 case OP_EXP:
6573 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6574 GE_NO_PREFIX));
6575 break;
6576
6577 case OP_EXPr: EXPr:
6578 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6579 GE_NO_PREFIX));
6580 if (inst.reloc.exp.X_op == O_symbol)
a737bd4d 6581 {
c19d1205
ZW		 6582 val = parse_reloc (&str);
6583 if (val == -1)
6584 {
6585 inst.error = _("unrecognized relocation suffix");
6586 goto failure;
6587 }
6588 else if (val != BFD_RELOC_UNUSED)
6589 {
6590 inst.operands[i].imm = val;
6591 inst.operands[i].hasreloc = 1;
6592 }
a737bd4d 6593 }
c19d1205 6594 break;
a737bd4d 6595
b6895b4f
PB		 6596 /* Operand for MOVW or MOVT. */
6597 case OP_HALF:
6598 po_misc_or_fail (parse_half (&str));
6599 break;
6600
e07e6e58 6601 /* Register or expression. */
c19d1205
ZW		 6602 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6603 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 6604
e07e6e58 6605 /* Register or immediate. */
c19d1205
ZW		 6606 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6607 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 6608
c19d1205
ZW		 6609 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6610 IF:
6611 if (!is_immediate_prefix (*str))
6612 goto bad_args;
6613 str++;
6614 val = parse_fpa_immediate (&str);
6615 if (val == FAIL)
6616 goto failure;
6617 /* FPA immediates are encoded as registers 8-15.
6618 parse_fpa_immediate has already applied the offset. */
6619 inst.operands[i].reg = val;
6620 inst.operands[i].isreg = 1;
6621 break;
09d92015 6622
2d447fca
JM		 6623 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6624 I32z: po_imm_or_fail (0, 32, FALSE); break;
6625
e07e6e58 6626 /* Two kinds of register. */
c19d1205
ZW		 6627 case OP_RIWR_RIWC:
6628 {
6629 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM		 6630 if (!rege
6631 || (rege->type != REG_TYPE_MMXWR
6632 && rege->type != REG_TYPE_MMXWC
6633 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW		 6634 {
6635 inst.error = _("iWMMXt data or control register expected");
6636 goto failure;
6637 }
6638 inst.operands[i].reg = rege->number;
6639 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6640 }
6641 break;
09d92015 6642
41adaa5c
JM		 6643 case OP_RIWC_RIWG:
6644 {
6645 struct reg_entry *rege = arm_reg_parse_multi (&str);
6646 if (!rege
6647 || (rege->type != REG_TYPE_MMXWC
6648 && rege->type != REG_TYPE_MMXWCG))
6649 {
6650 inst.error = _("iWMMXt control register expected");
6651 goto failure;
6652 }
6653 inst.operands[i].reg = rege->number;
6654 inst.operands[i].isreg = 1;
6655 }
6656 break;
6657
c19d1205
ZW		 6658 /* Misc */
6659 case OP_CPSF: val = parse_cps_flags (&str); break;
6660 case OP_ENDI: val = parse_endian_specifier (&str); break;
6661 case OP_oROR: val = parse_ror (&str); break;
c19d1205 6662 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE		 6663 case OP_oBARRIER_I15:
6664 po_barrier_or_imm (str); break;
6665 immediate:
6666 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 6667 goto failure;
52e7f43d 6668 break;
c19d1205 6669
fa94de6b 6670 case OP_wPSR:
d2cd1205 6671 case OP_rPSR:
90ec0d68
MGD		 6672 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6673 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6674 {
6675 inst.error = _("Banked registers are not available with this "
6676 "architecture.");
6677 goto failure;
6678 }
6679 break;
d2cd1205
JB		 6680 try_psr:
6681 val = parse_psr (&str, op_parse_code == OP_wPSR);
6682 break;
037e8744 6683
477330fc
RM		 6684 case OP_APSR_RR:
6685 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6686 break;
6687 try_apsr:
6688 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6689 instruction). */
6690 if (strncasecmp (str, "APSR_", 5) == 0)
6691 {
6692 unsigned found = 0;
6693 str += 5;
6694 while (found < 15)
6695 switch (*str++)
6696 {
6697 case 'c': found = (found & 1) ? 16 : found | 1; break;
6698 case 'n': found = (found & 2) ? 16 : found | 2; break;
6699 case 'z': found = (found & 4) ? 16 : found | 4; break;
6700 case 'v': found = (found & 8) ? 16 : found | 8; break;
6701 default: found = 16;
6702 }
6703 if (found != 15)
6704 goto failure;
6705 inst.operands[i].isvec = 1;
f7c21dc7
NC		 6706 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6707 inst.operands[i].reg = REG_PC;
477330fc
RM		 6708 }
6709 else
6710 goto failure;
6711 break;
037e8744 6712
92e90b6e
PB		 6713 case OP_TB:
6714 po_misc_or_fail (parse_tb (&str));
6715 break;
6716
e07e6e58 6717 /* Register lists. */
c19d1205
ZW		 6718 case OP_REGLST:
6719 val = parse_reg_list (&str);
6720 if (*str == '^')
6721 {
6722 inst.operands[1].writeback = 1;
6723 str++;
6724 }
6725 break;
09d92015 6726
c19d1205 6727 case OP_VRSLST:
5287ad62 6728 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
c19d1205 6729 break;
09d92015 6730
c19d1205 6731 case OP_VRDLST:
5287ad62 6732 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
c19d1205 6733 break;
a737bd4d 6734
477330fc
RM		 6735 case OP_VRSDLST:
6736 /* Allow Q registers too. */
6737 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6738 REGLIST_NEON_D);
6739 if (val == FAIL)
6740 {
6741 inst.error = NULL;
6742 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6743 REGLIST_VFP_S);
6744 inst.operands[i].issingle = 1;
6745 }
6746 break;
6747
6748 case OP_NRDLST:
6749 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
6750 REGLIST_NEON_D);
6751 break;
5287ad62
JB		 6752
6753 case OP_NSTRLST:
477330fc
RM		 6754 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
6755 &inst.operands[i].vectype);
6756 break;
5287ad62 6757
c19d1205
ZW		 6758 /* Addressing modes */
6759 case OP_ADDR:
6760 po_misc_or_fail (parse_address (&str, i));
6761 break;
09d92015 6762
4962c51a
MS		 6763 case OP_ADDRGLDR:
6764 po_misc_or_fail_no_backtrack (
477330fc 6765 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS		 6766 break;
6767
6768 case OP_ADDRGLDRS:
6769 po_misc_or_fail_no_backtrack (
477330fc 6770 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS		 6771 break;
6772
6773 case OP_ADDRGLDC:
6774 po_misc_or_fail_no_backtrack (
477330fc 6775 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS		 6776 break;
6777
c19d1205
ZW		 6778 case OP_SH:
6779 po_misc_or_fail (parse_shifter_operand (&str, i));
6780 break;
09d92015 6781
4962c51a
MS		 6782 case OP_SHG:
6783 po_misc_or_fail_no_backtrack (
477330fc 6784 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS		 6785 break;
6786
c19d1205
ZW		 6787 case OP_oSHll:
6788 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
6789 break;
09d92015 6790
c19d1205
ZW		 6791 case OP_oSHar:
6792 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
6793 break;
09d92015 6794
c19d1205
ZW		 6795 case OP_oSHllar:
6796 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
6797 break;
09d92015 6798
c19d1205 6799 default:
5be8be5d 6800 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 6801 }
09d92015 6802
c19d1205
ZW		 6803 /* Various value-based sanity checks and shared operations. We
6804 do not signal immediate failures for the register constraints;
6805 this allows a syntax error to take precedence. */
5be8be5d 6806 switch (op_parse_code)
c19d1205
ZW		 6807 {
6808 case OP_oRRnpc:
6809 case OP_RRnpc:
6810 case OP_RRnpcb:
6811 case OP_RRw:
b6702015 6812 case OP_oRRw:
c19d1205
ZW		 6813 case OP_RRnpc_I0:
6814 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
6815 inst.error = BAD_PC;
6816 break;
09d92015 6817
5be8be5d
DG		 6818 case OP_oRRnpcsp:
6819 case OP_RRnpcsp:
6820 if (inst.operands[i].isreg)
6821 {
6822 if (inst.operands[i].reg == REG_PC)
6823 inst.error = BAD_PC;
6824 else if (inst.operands[i].reg == REG_SP)
6825 inst.error = BAD_SP;
6826 }
6827 break;
6828
55881a11 6829 case OP_RRnpctw:
fa94de6b
RM		 6830 if (inst.operands[i].isreg
6831 && inst.operands[i].reg == REG_PC
55881a11
MGD		 6832 && (inst.operands[i].writeback || thumb))
6833 inst.error = BAD_PC;
6834 break;
6835
c19d1205
ZW		 6836 case OP_CPSF:
6837 case OP_ENDI:
6838 case OP_oROR:
d2cd1205
JB		 6839 case OP_wPSR:
6840 case OP_rPSR:
c19d1205 6841 case OP_COND:
52e7f43d 6842 case OP_oBARRIER_I15:
c19d1205
ZW		 6843 case OP_REGLST:
6844 case OP_VRSLST:
6845 case OP_VRDLST:
477330fc
RM		 6846 case OP_VRSDLST:
6847 case OP_NRDLST:
6848 case OP_NSTRLST:
c19d1205
ZW		 6849 if (val == FAIL)
6850 goto failure;
6851 inst.operands[i].imm = val;
6852 break;
a737bd4d 6853
c19d1205
ZW		 6854 default:
6855 break;
6856 }
09d92015 6857
c19d1205
ZW		 6858 /* If we get here, this operand was successfully parsed. */
6859 inst.operands[i].present = 1;
6860 continue;
09d92015 6861
c19d1205 6862 bad_args:
09d92015 6863 inst.error = BAD_ARGS;
c19d1205
ZW		 6864
6865 failure:
6866 if (!backtrack_pos)
d252fdde
PB		 6867 {
6868 /* The parse routine should already have set inst.error, but set a
5f4273c7 6869 default here just in case. */
d252fdde
PB		 6870 if (!inst.error)
6871 inst.error = _("syntax error");
6872 return FAIL;
6873 }
c19d1205
ZW		 6874
6875 /* Do not backtrack over a trailing optional argument that
6876 absorbed some text. We will only fail again, with the
6877 'garbage following instruction' error message, which is
6878 probably less helpful than the current one. */
6879 if (backtrack_index == i && backtrack_pos != str
6880 && upat[i+1] == OP_stop)
d252fdde
PB		 6881 {
6882 if (!inst.error)
6883 inst.error = _("syntax error");
6884 return FAIL;
6885 }
c19d1205
ZW		 6886
6887 /* Try again, skipping the optional argument at backtrack_pos. */
6888 str = backtrack_pos;
6889 inst.error = backtrack_error;
6890 inst.operands[backtrack_index].present = 0;
6891 i = backtrack_index;
6892 backtrack_pos = 0;
09d92015 6893 }
09d92015 6894
c19d1205
ZW		 6895 /* Check that we have parsed all the arguments. */
6896 if (*str != '\0' && !inst.error)
6897 inst.error = _("garbage following instruction");
09d92015 6898
c19d1205 6899 return inst.error ? FAIL : SUCCESS;
09d92015
MM		 6900}
6901
c19d1205
ZW		 6902#undef po_char_or_fail
6903#undef po_reg_or_fail
6904#undef po_reg_or_goto
6905#undef po_imm_or_fail
5287ad62 6906#undef po_scalar_or_fail
52e7f43d 6907#undef po_barrier_or_imm
e07e6e58 6908
c19d1205 6909/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC		 6910#define constraint(expr, err) \
6911 do \
c19d1205 6912 { \
e07e6e58
NC		 6913 if (expr) \
6914 { \
6915 inst.error = err; \
6916 return; \
6917 } \
c19d1205 6918 } \
e07e6e58 6919 while (0)
c19d1205 6920
fdfde340
JM		 6921/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6922 instructions are unpredictable if these registers are used. This
6923 is the BadReg predicate in ARM's Thumb-2 documentation. */
6924#define reject_bad_reg(reg) \
6925 do \
6926 if (reg == REG_SP || reg == REG_PC) \
6927 { \
6928 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6929 return; \
6930 } \
6931 while (0)
6932
94206790
MM		 6933/* If REG is R13 (the stack pointer), warn that its use is
6934 deprecated. */
6935#define warn_deprecated_sp(reg) \
6936 do \
6937 if (warn_on_deprecated && reg == REG_SP) \
6938 as_warn (_("use of r13 is deprecated")); \
6939 while (0)
6940
c19d1205
ZW		 6941/* Functions for operand encoding. ARM, then Thumb. */
6942
6943#define rotate_left(v, n) (v << n | v >> (32 - n))
6944
6945/* If VAL can be encoded in the immediate field of an ARM instruction,
6946 return the encoded form. Otherwise, return FAIL. */
6947
6948static unsigned int
6949encode_arm_immediate (unsigned int val)
09d92015 6950{
c19d1205
ZW		 6951 unsigned int a, i;
6952
6953 for (i = 0; i < 32; i += 2)
6954 if ((a = rotate_left (val, i)) <= 0xff)
6955 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
6956
6957 return FAIL;
09d92015
MM		 6958}
6959
c19d1205
ZW		 6960/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6961 return the encoded form. Otherwise, return FAIL. */
6962static unsigned int
6963encode_thumb32_immediate (unsigned int val)
09d92015 6964{
c19d1205 6965 unsigned int a, i;
09d92015 6966
9c3c69f2 6967 if (val <= 0xff)
c19d1205 6968 return val;
a737bd4d 6969
9c3c69f2 6970 for (i = 1; i <= 24; i++)
09d92015 6971 {
9c3c69f2
PB		 6972 a = val >> i;
6973 if ((val & ~(0xff << i)) == 0)
6974 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 6975 }
a737bd4d 6976
c19d1205
ZW		 6977 a = val & 0xff;
6978 if (val == ((a << 16) | a))
6979 return 0x100 | a;
6980 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
6981 return 0x300 | a;
09d92015 6982
c19d1205
ZW		 6983 a = val & 0xff00;
6984 if (val == ((a << 16) | a))
6985 return 0x200 | (a >> 8);
a737bd4d 6986
c19d1205 6987 return FAIL;
09d92015 6988}
5287ad62 6989/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM		 6990
6991static void
5287ad62
JB		 6992encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
6993{
6994 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
6995 && reg > 15)
6996 {
b1cc4aeb 6997 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 6998 {
6999 if (thumb_mode)
7000 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7001 fpu_vfp_ext_d32);
7002 else
7003 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7004 fpu_vfp_ext_d32);
7005 }
5287ad62 7006 else
477330fc
RM		 7007 {
7008 first_error (_("D register out of range for selected VFP version"));
7009 return;
7010 }
5287ad62
JB		 7011 }
7012
c19d1205 7013 switch (pos)
09d92015 7014 {
c19d1205
ZW		 7015 case VFP_REG_Sd:
7016 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7017 break;
7018
7019 case VFP_REG_Sn:
7020 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7021 break;
7022
7023 case VFP_REG_Sm:
7024 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7025 break;
7026
5287ad62
JB		 7027 case VFP_REG_Dd:
7028 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7029 break;
5f4273c7 7030
5287ad62
JB		 7031 case VFP_REG_Dn:
7032 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7033 break;
5f4273c7 7034
5287ad62
JB		 7035 case VFP_REG_Dm:
7036 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7037 break;
7038
c19d1205
ZW		 7039 default:
7040 abort ();
09d92015 7041 }
09d92015
MM		 7042}
7043
c19d1205 7044/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 7045 if any, is handled by md_apply_fix. */
09d92015 7046static void
c19d1205 7047encode_arm_shift (int i)
09d92015 7048{
c19d1205
ZW		 7049 if (inst.operands[i].shift_kind == SHIFT_RRX)
7050 inst.instruction |= SHIFT_ROR << 5;
7051 else
09d92015 7052 {
c19d1205
ZW		 7053 inst.instruction |= inst.operands[i].shift_kind << 5;
7054 if (inst.operands[i].immisreg)
7055 {
7056 inst.instruction |= SHIFT_BY_REG;
7057 inst.instruction |= inst.operands[i].imm << 8;
7058 }
7059 else
7060 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 7061 }
c19d1205 7062}
09d92015 7063
c19d1205
ZW		 7064static void
7065encode_arm_shifter_operand (int i)
7066{
7067 if (inst.operands[i].isreg)
09d92015 7068 {
c19d1205
ZW		 7069 inst.instruction |= inst.operands[i].reg;
7070 encode_arm_shift (i);
09d92015 7071 }
c19d1205 7072 else
a415b1cd
JB		 7073 {
7074 inst.instruction |= INST_IMMEDIATE;
7075 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7076 inst.instruction |= inst.operands[i].imm;
7077 }
09d92015
MM		 7078}
7079
c19d1205 7080/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 7081static void
c19d1205 7082encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 7083{
2b2f5df9
NC		 7084 /* PR 14260:
7085 Generate an error if the operand is not a register. */
7086 constraint (!inst.operands[i].isreg,
7087 _("Instruction does not support =N addresses"));
7088
c19d1205 7089 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 7090
c19d1205 7091 if (inst.operands[i].preind)
09d92015 7092 {
c19d1205
ZW		 7093 if (is_t)
7094 {
7095 inst.error = _("instruction does not accept preindexed addressing");
7096 return;
7097 }
7098 inst.instruction |= PRE_INDEX;
7099 if (inst.operands[i].writeback)
7100 inst.instruction |= WRITE_BACK;
09d92015 7101
c19d1205
ZW		 7102 }
7103 else if (inst.operands[i].postind)
7104 {
9c2799c2 7105 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 7106 if (is_t)
7107 inst.instruction |= WRITE_BACK;
7108 }
7109 else /* unindexed - only for coprocessor */
09d92015 7110 {
c19d1205 7111 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM		 7112 return;
7113 }
7114
c19d1205
ZW		 7115 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7116 && (((inst.instruction & 0x000f0000) >> 16)
7117 == ((inst.instruction & 0x0000f000) >> 12)))
7118 as_warn ((inst.instruction & LOAD_BIT)
7119 ? _("destination register same as write-back base")
7120 : _("source register same as write-back base"));
09d92015
MM		 7121}
7122
c19d1205
ZW		 7123/* inst.operands[i] was set up by parse_address. Encode it into an
7124 ARM-format mode 2 load or store instruction. If is_t is true,
7125 reject forms that cannot be used with a T instruction (i.e. not
7126 post-indexed). */
a737bd4d 7127static void
c19d1205 7128encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 7129{
5be8be5d
DG		 7130 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7131
c19d1205 7132 encode_arm_addr_mode_common (i, is_t);
a737bd4d 7133
c19d1205 7134 if (inst.operands[i].immisreg)
09d92015 7135 {
5be8be5d
DG		 7136 constraint ((inst.operands[i].imm == REG_PC
7137 || (is_pc && inst.operands[i].writeback)),
7138 BAD_PC_ADDRESSING);
c19d1205
ZW		 7139 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7140 inst.instruction |= inst.operands[i].imm;
7141 if (!inst.operands[i].negative)
7142 inst.instruction |= INDEX_UP;
7143 if (inst.operands[i].shifted)
7144 {
7145 if (inst.operands[i].shift_kind == SHIFT_RRX)
7146 inst.instruction |= SHIFT_ROR << 5;
7147 else
7148 {
7149 inst.instruction |= inst.operands[i].shift_kind << 5;
7150 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7151 }
7152 }
09d92015 7153 }
c19d1205 7154 else /* immediate offset in inst.reloc */
09d92015 7155 {
5be8be5d
DG		 7156 if (is_pc && !inst.reloc.pc_rel)
7157 {
7158 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ		 7159
7160 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7161 cannot use PC in addressing.
7162 PC cannot be used in writeback addressing, either. */
7163 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 7164 BAD_PC_ADDRESSING);
23a10334 7165
dc5ec521 7166 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ		 7167 if (warn_on_deprecated
7168 && !is_load
7169 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7170 as_warn (_("use of PC in this instruction is deprecated"));
5be8be5d
DG		 7171 }
7172
c19d1205 7173 if (inst.reloc.type == BFD_RELOC_UNUSED)
26d97720
NS		 7174 {
7175 /* Prefer + for zero encoded value. */
7176 if (!inst.operands[i].negative)
7177 inst.instruction |= INDEX_UP;
7178 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7179 }
09d92015 7180 }
09d92015
MM		 7181}
7182
c19d1205
ZW		 7183/* inst.operands[i] was set up by parse_address. Encode it into an
7184 ARM-format mode 3 load or store instruction. Reject forms that
7185 cannot be used with such instructions. If is_t is true, reject
7186 forms that cannot be used with a T instruction (i.e. not
7187 post-indexed). */
7188static void
7189encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 7190{
c19d1205 7191 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 7192 {
c19d1205
ZW		 7193 inst.error = _("instruction does not accept scaled register index");
7194 return;
09d92015 7195 }
a737bd4d 7196
c19d1205 7197 encode_arm_addr_mode_common (i, is_t);
a737bd4d 7198
c19d1205
ZW		 7199 if (inst.operands[i].immisreg)
7200 {
5be8be5d 7201 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 7202 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 7203 BAD_PC_ADDRESSING);
eb9f3f00
JB		 7204 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7205 BAD_PC_WRITEBACK);
c19d1205
ZW		 7206 inst.instruction |= inst.operands[i].imm;
7207 if (!inst.operands[i].negative)
7208 inst.instruction |= INDEX_UP;
7209 }
7210 else /* immediate offset in inst.reloc */
7211 {
5be8be5d
DG		 7212 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7213 && inst.operands[i].writeback),
7214 BAD_PC_WRITEBACK);
c19d1205
ZW		 7215 inst.instruction |= HWOFFSET_IMM;
7216 if (inst.reloc.type == BFD_RELOC_UNUSED)
26d97720
NS		 7217 {
7218 /* Prefer + for zero encoded value. */
7219 if (!inst.operands[i].negative)
7220 inst.instruction |= INDEX_UP;
7221
7222 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7223 }
c19d1205 7224 }
a737bd4d
NC		 7225}
7226
c19d1205
ZW		 7227/* inst.operands[i] was set up by parse_address. Encode it into an
7228 ARM-format instruction. Reject all forms which cannot be encoded
7229 into a coprocessor load/store instruction. If wb_ok is false,
7230 reject use of writeback; if unind_ok is false, reject use of
7231 unindexed addressing. If reloc_override is not 0, use it instead
4962c51a
MS		 7232 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7233 (in which case it is preserved). */
09d92015 7234
c19d1205
ZW		 7235static int
7236encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
09d92015 7237{
c19d1205 7238 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 7239
9c2799c2 7240 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
09d92015 7241
c19d1205 7242 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
09d92015 7243 {
9c2799c2 7244 gas_assert (!inst.operands[i].writeback);
c19d1205
ZW		 7245 if (!unind_ok)
7246 {
7247 inst.error = _("instruction does not support unindexed addressing");
7248 return FAIL;
7249 }
7250 inst.instruction |= inst.operands[i].imm;
7251 inst.instruction |= INDEX_UP;
7252 return SUCCESS;
09d92015 7253 }
a737bd4d 7254
c19d1205
ZW		 7255 if (inst.operands[i].preind)
7256 inst.instruction |= PRE_INDEX;
a737bd4d 7257
c19d1205 7258 if (inst.operands[i].writeback)
09d92015 7259 {
c19d1205
ZW		 7260 if (inst.operands[i].reg == REG_PC)
7261 {
7262 inst.error = _("pc may not be used with write-back");
7263 return FAIL;
7264 }
7265 if (!wb_ok)
7266 {
7267 inst.error = _("instruction does not support writeback");
7268 return FAIL;
7269 }
7270 inst.instruction |= WRITE_BACK;
09d92015 7271 }
a737bd4d 7272
c19d1205 7273 if (reloc_override)
21d799b5 7274 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
4962c51a 7275 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
477330fc
RM		 7276 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7277 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
4962c51a
MS		 7278 {
7279 if (thumb_mode)
477330fc 7280 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
4962c51a 7281 else
477330fc 7282 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
4962c51a
MS		 7283 }
7284
26d97720
NS		 7285 /* Prefer + for zero encoded value. */
7286 if (!inst.operands[i].negative)
7287 inst.instruction |= INDEX_UP;
7288
c19d1205
ZW		 7289 return SUCCESS;
7290}
a737bd4d 7291
c19d1205
ZW		 7292/* inst.reloc.exp describes an "=expr" load pseudo-operation.
7293 Determine whether it can be performed with a move instruction; if
7294 it can, convert inst.instruction to that move instruction and
c921be7d
NC		 7295 return TRUE; if it can't, convert inst.instruction to a literal-pool
7296 load and return FALSE. If this is not a valid thing to do in the
7297 current context, set inst.error and return TRUE.
a737bd4d 7298
c19d1205
ZW		 7299 inst.operands[i] describes the destination register. */
7300
c921be7d 7301static bfd_boolean
c19d1205
ZW		 7302move_or_literal_pool (int i, bfd_boolean thumb_p, bfd_boolean mode_3)
7303{
53365c0d
PB		 7304 unsigned long tbit;
7305
7306 if (thumb_p)
7307 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7308 else
7309 tbit = LOAD_BIT;
7310
7311 if ((inst.instruction & tbit) == 0)
09d92015 7312 {
c19d1205 7313 inst.error = _("invalid pseudo operation");
c921be7d 7314 return TRUE;
09d92015 7315 }
c19d1205 7316 if (inst.reloc.exp.X_op != O_constant && inst.reloc.exp.X_op != O_symbol)
09d92015
MM		 7317 {
7318 inst.error = _("constant expression expected");
c921be7d 7319 return TRUE;
09d92015 7320 }
c19d1205 7321 if (inst.reloc.exp.X_op == O_constant)
09d92015 7322 {
c19d1205
ZW		 7323 if (thumb_p)
7324 {
53365c0d 7325 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
c19d1205
ZW		 7326 {
7327 /* This can be done with a mov(1) instruction. */
7328 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7329 inst.instruction |= inst.reloc.exp.X_add_number;
c921be7d 7330 return TRUE;
c19d1205
ZW		 7331 }
7332 }
7333 else
7334 {
7335 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7336 if (value != FAIL)
7337 {
7338 /* This can be done with a mov instruction. */
7339 inst.instruction &= LITERAL_MASK;
7340 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7341 inst.instruction |= value & 0xfff;
c921be7d 7342 return TRUE;
c19d1205 7343 }
09d92015 7344
c19d1205
ZW		 7345 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7346 if (value != FAIL)
7347 {
7348 /* This can be done with a mvn instruction. */
7349 inst.instruction &= LITERAL_MASK;
7350 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7351 inst.instruction |= value & 0xfff;
c921be7d 7352 return TRUE;
c19d1205
ZW		 7353 }
7354 }
09d92015
MM		 7355 }
7356
c19d1205
ZW		 7357 if (add_to_lit_pool () == FAIL)
7358 {
7359 inst.error = _("literal pool insertion failed");
c921be7d 7360 return TRUE;
c19d1205
ZW		 7361 }
7362 inst.operands[1].reg = REG_PC;
7363 inst.operands[1].isreg = 1;
7364 inst.operands[1].preind = 1;
7365 inst.reloc.pc_rel = 1;
7366 inst.reloc.type = (thumb_p
7367 ? BFD_RELOC_ARM_THUMB_OFFSET
7368 : (mode_3
7369 ? BFD_RELOC_ARM_HWLITERAL
7370 : BFD_RELOC_ARM_LITERAL));
c921be7d 7371 return FALSE;
09d92015
MM		 7372}
7373
5f4273c7 7374/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW		 7375 First some generics; their names are taken from the conventional
7376 bit positions for register arguments in ARM format instructions. */
09d92015 7377
a737bd4d 7378static void
c19d1205 7379do_noargs (void)
09d92015 7380{
c19d1205 7381}
a737bd4d 7382
c19d1205
ZW		 7383static void
7384do_rd (void)
7385{
7386 inst.instruction |= inst.operands[0].reg << 12;
7387}
a737bd4d 7388
c19d1205
ZW		 7389static void
7390do_rd_rm (void)
7391{
7392 inst.instruction |= inst.operands[0].reg << 12;
7393 inst.instruction |= inst.operands[1].reg;
7394}
09d92015 7395
9eb6c0f1
MGD		 7396static void
7397do_rm_rn (void)
7398{
7399 inst.instruction |= inst.operands[0].reg;
7400 inst.instruction |= inst.operands[1].reg << 16;
7401}
7402
c19d1205
ZW		 7403static void
7404do_rd_rn (void)
7405{
7406 inst.instruction |= inst.operands[0].reg << 12;
7407 inst.instruction |= inst.operands[1].reg << 16;
7408}
a737bd4d 7409
c19d1205
ZW		 7410static void
7411do_rn_rd (void)
7412{
7413 inst.instruction |= inst.operands[0].reg << 16;
7414 inst.instruction |= inst.operands[1].reg << 12;
7415}
09d92015 7416
59d09be6
MGD		 7417static bfd_boolean
7418check_obsolete (const arm_feature_set *feature, const char *msg)
7419{
7420 if (ARM_CPU_IS_ANY (cpu_variant))
7421 {
7422 as_warn ("%s", msg);
7423 return TRUE;
7424 }
7425 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7426 {
7427 as_bad ("%s", msg);
7428 return TRUE;
7429 }
7430
7431 return FALSE;
7432}
7433
c19d1205
ZW		 7434static void
7435do_rd_rm_rn (void)
7436{
9a64e435 7437 unsigned Rn = inst.operands[2].reg;
708587a4 7438 /* Enforce restrictions on SWP instruction. */
9a64e435 7439 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG		 7440 {
7441 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
7442 _("Rn must not overlap other operands"));
7443
59d09be6
MGD		 7444 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7445 */
7446 if (!check_obsolete (&arm_ext_v8,
7447 _("swp{b} use is obsoleted for ARMv8 and later"))
7448 && warn_on_deprecated
7449 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
7450 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 7451 }
59d09be6 7452
c19d1205
ZW		 7453 inst.instruction |= inst.operands[0].reg << 12;
7454 inst.instruction |= inst.operands[1].reg;
9a64e435 7455 inst.instruction |= Rn << 16;
c19d1205 7456}
09d92015 7457
c19d1205
ZW		 7458static void
7459do_rd_rn_rm (void)
7460{
7461 inst.instruction |= inst.operands[0].reg << 12;
7462 inst.instruction |= inst.operands[1].reg << 16;
7463 inst.instruction |= inst.operands[2].reg;
7464}
a737bd4d 7465
c19d1205
ZW		 7466static void
7467do_rm_rd_rn (void)
7468{
5be8be5d
DG		 7469 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
7470 constraint (((inst.reloc.exp.X_op != O_constant
7471 && inst.reloc.exp.X_op != O_illegal)
7472 || inst.reloc.exp.X_add_number != 0),
7473 BAD_ADDR_MODE);
c19d1205
ZW		 7474 inst.instruction |= inst.operands[0].reg;
7475 inst.instruction |= inst.operands[1].reg << 12;
7476 inst.instruction |= inst.operands[2].reg << 16;
7477}
09d92015 7478
c19d1205
ZW		 7479static void
7480do_imm0 (void)
7481{
7482 inst.instruction |= inst.operands[0].imm;
7483}
09d92015 7484
c19d1205
ZW		 7485static void
7486do_rd_cpaddr (void)
7487{
7488 inst.instruction |= inst.operands[0].reg << 12;
7489 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 7490}
a737bd4d 7491
c19d1205
ZW		 7492/* ARM instructions, in alphabetical order by function name (except
7493 that wrapper functions appear immediately after the function they
7494 wrap). */
09d92015 7495
c19d1205
ZW		 7496/* This is a pseudo-op of the form "adr rd, label" to be converted
7497 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM		 7498
7499static void
c19d1205 7500do_adr (void)
09d92015 7501{
c19d1205 7502 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 7503
c19d1205
ZW		 7504 /* Frag hacking will turn this into a sub instruction if the offset turns
7505 out to be negative. */
7506 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
c19d1205 7507 inst.reloc.pc_rel = 1;
2fc8bdac 7508 inst.reloc.exp.X_add_number -= 8;
c19d1205 7509}
b99bd4ef 7510
c19d1205
ZW		 7511/* This is a pseudo-op of the form "adrl rd, label" to be converted
7512 into a relative address of the form:
7513 add rd, pc, #low(label-.-8)"
7514 add rd, rd, #high(label-.-8)" */
b99bd4ef 7515
c19d1205
ZW		 7516static void
7517do_adrl (void)
7518{
7519 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 7520
c19d1205
ZW		 7521 /* Frag hacking will turn this into a sub instruction if the offset turns
7522 out to be negative. */
7523 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
c19d1205
ZW		 7524 inst.reloc.pc_rel = 1;
7525 inst.size = INSN_SIZE * 2;
2fc8bdac 7526 inst.reloc.exp.X_add_number -= 8;
b99bd4ef
NC		 7527}
7528
b99bd4ef 7529static void
c19d1205 7530do_arit (void)
b99bd4ef 7531{
c19d1205
ZW		 7532 if (!inst.operands[1].present)
7533 inst.operands[1].reg = inst.operands[0].reg;
7534 inst.instruction |= inst.operands[0].reg << 12;
7535 inst.instruction |= inst.operands[1].reg << 16;
7536 encode_arm_shifter_operand (2);
7537}
b99bd4ef 7538
62b3e311
PB		 7539static void
7540do_barrier (void)
7541{
7542 if (inst.operands[0].present)
ccb84d65 7543 inst.instruction |= inst.operands[0].imm;
62b3e311
PB		 7544 else
7545 inst.instruction |= 0xf;
7546}
7547
c19d1205
ZW		 7548static void
7549do_bfc (void)
7550{
7551 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
7552 constraint (msb > 32, _("bit-field extends past end of register"));
7553 /* The instruction encoding stores the LSB and MSB,
7554 not the LSB and width. */
7555 inst.instruction |= inst.operands[0].reg << 12;
7556 inst.instruction |= inst.operands[1].imm << 7;
7557 inst.instruction |= (msb - 1) << 16;
7558}
b99bd4ef 7559
c19d1205
ZW		 7560static void
7561do_bfi (void)
7562{
7563 unsigned int msb;
b99bd4ef 7564
c19d1205
ZW		 7565 /* #0 in second position is alternative syntax for bfc, which is
7566 the same instruction but with REG_PC in the Rm field. */
7567 if (!inst.operands[1].isreg)
7568 inst.operands[1].reg = REG_PC;
b99bd4ef 7569
c19d1205
ZW		 7570 msb = inst.operands[2].imm + inst.operands[3].imm;
7571 constraint (msb > 32, _("bit-field extends past end of register"));
7572 /* The instruction encoding stores the LSB and MSB,
7573 not the LSB and width. */
7574 inst.instruction |= inst.operands[0].reg << 12;
7575 inst.instruction |= inst.operands[1].reg;
7576 inst.instruction |= inst.operands[2].imm << 7;
7577 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC		 7578}
7579
b99bd4ef 7580static void
c19d1205 7581do_bfx (void)
b99bd4ef 7582{
c19d1205
ZW		 7583 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
7584 _("bit-field extends past end of register"));
7585 inst.instruction |= inst.operands[0].reg << 12;
7586 inst.instruction |= inst.operands[1].reg;
7587 inst.instruction |= inst.operands[2].imm << 7;
7588 inst.instruction |= (inst.operands[3].imm - 1) << 16;
7589}
09d92015 7590
c19d1205
ZW		 7591/* ARM V5 breakpoint instruction (argument parse)
7592 BKPT <16 bit unsigned immediate>
7593 Instruction is not conditional.
7594 The bit pattern given in insns[] has the COND_ALWAYS condition,
7595 and it is an error if the caller tried to override that. */
b99bd4ef 7596
c19d1205
ZW		 7597static void
7598do_bkpt (void)
7599{
7600 /* Top 12 of 16 bits to bits 19:8. */
7601 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 7602
c19d1205
ZW		 7603 /* Bottom 4 of 16 bits to bits 3:0. */
7604 inst.instruction |= inst.operands[0].imm & 0xf;
7605}
09d92015 7606
c19d1205
ZW		 7607static void
7608encode_branch (int default_reloc)
7609{
7610 if (inst.operands[0].hasreloc)
7611 {
0855e32b
NS		 7612 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
7613 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
7614 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7615 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
7616 ? BFD_RELOC_ARM_PLT32
7617 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 7618 }
b99bd4ef 7619 else
9ae92b05 7620 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
2fc8bdac 7621 inst.reloc.pc_rel = 1;
b99bd4ef
NC		 7622}
7623
b99bd4ef 7624static void
c19d1205 7625do_branch (void)
b99bd4ef 7626{
39b41c9c
PB		 7627#ifdef OBJ_ELF
7628 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7629 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7630 else
7631#endif
7632 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
7633}
7634
7635static void
7636do_bl (void)
7637{
7638#ifdef OBJ_ELF
7639 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
7640 {
7641 if (inst.cond == COND_ALWAYS)
7642 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
7643 else
7644 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
7645 }
7646 else
7647#endif
7648 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 7649}
b99bd4ef 7650
c19d1205
ZW		 7651/* ARM V5 branch-link-exchange instruction (argument parse)
7652 BLX <target_addr> ie BLX(1)
7653 BLX{<condition>} <Rm> ie BLX(2)
7654 Unfortunately, there are two different opcodes for this mnemonic.
7655 So, the insns[].value is not used, and the code here zaps values
7656 into inst.instruction.
7657 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 7658
c19d1205
ZW		 7659static void
7660do_blx (void)
7661{
7662 if (inst.operands[0].isreg)
b99bd4ef 7663 {
c19d1205
ZW		 7664 /* Arg is a register; the opcode provided by insns[] is correct.
7665 It is not illegal to do "blx pc", just useless. */
7666 if (inst.operands[0].reg == REG_PC)
7667 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 7668
c19d1205
ZW		 7669 inst.instruction |= inst.operands[0].reg;
7670 }
7671 else
b99bd4ef 7672 {
c19d1205 7673 /* Arg is an address; this instruction cannot be executed
267bf995
RR		 7674 conditionally, and the opcode must be adjusted.
7675 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7676 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 7677 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 7678 inst.instruction = 0xfa000000;
267bf995 7679 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 7680 }
c19d1205
ZW		 7681}
7682
7683static void
7684do_bx (void)
7685{
845b51d6
PB		 7686 bfd_boolean want_reloc;
7687
c19d1205
ZW		 7688 if (inst.operands[0].reg == REG_PC)
7689 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 7690
c19d1205 7691 inst.instruction |= inst.operands[0].reg;
845b51d6
PB		 7692 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7693 it is for ARMv4t or earlier. */
7694 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
7695 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
7696 want_reloc = TRUE;
7697
5ad34203 7698#ifdef OBJ_ELF
845b51d6 7699 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 7700#endif
584206db 7701 want_reloc = FALSE;
845b51d6
PB		 7702
7703 if (want_reloc)
7704 inst.reloc.type = BFD_RELOC_ARM_V4BX;
09d92015
MM		 7705}
7706
c19d1205
ZW		 7707
7708/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC		 7709
7710static void
c19d1205 7711do_bxj (void)
a737bd4d 7712{
c19d1205
ZW		 7713 if (inst.operands[0].reg == REG_PC)
7714 as_tsktsk (_("use of r15 in bxj is not really useful"));
7715
7716 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC		 7717}
7718
c19d1205
ZW		 7719/* Co-processor data operation:
7720 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7721 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7722static void
7723do_cdp (void)
7724{
7725 inst.instruction |= inst.operands[0].reg << 8;
7726 inst.instruction |= inst.operands[1].imm << 20;
7727 inst.instruction |= inst.operands[2].reg << 12;
7728 inst.instruction |= inst.operands[3].reg << 16;
7729 inst.instruction |= inst.operands[4].reg;
7730 inst.instruction |= inst.operands[5].imm << 5;
7731}
a737bd4d
NC		 7732
7733static void
c19d1205 7734do_cmp (void)
a737bd4d 7735{
c19d1205
ZW		 7736 inst.instruction |= inst.operands[0].reg << 16;
7737 encode_arm_shifter_operand (1);
a737bd4d
NC		 7738}
7739
c19d1205
ZW		 7740/* Transfer between coprocessor and ARM registers.
7741 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7742 MRC2
7743 MCR{cond}
7744 MCR2
7745
7746 No special properties. */
09d92015 7747
dcbd0d71
MGD		 7748struct deprecated_coproc_regs_s
7749{
7750 unsigned cp;
7751 int opc1;
7752 unsigned crn;
7753 unsigned crm;
7754 int opc2;
7755 arm_feature_set deprecated;
7756 arm_feature_set obsoleted;
7757 const char *dep_msg;
7758 const char *obs_msg;
7759};
7760
7761#define DEPR_ACCESS_V8 \
7762 N_("This coprocessor register access is deprecated in ARMv8")
7763
7764/* Table of all deprecated coprocessor registers. */
7765static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
7766{
7767 {15, 0, 7, 10, 5, /* CP15DMB. */
7768 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7769 DEPR_ACCESS_V8, NULL},
7770 {15, 0, 7, 10, 4, /* CP15DSB. */
7771 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7772 DEPR_ACCESS_V8, NULL},
7773 {15, 0, 7, 5, 4, /* CP15ISB. */
7774 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7775 DEPR_ACCESS_V8, NULL},
7776 {14, 6, 1, 0, 0, /* TEEHBR. */
7777 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7778 DEPR_ACCESS_V8, NULL},
7779 {14, 6, 0, 0, 0, /* TEECR. */
7780 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
7781 DEPR_ACCESS_V8, NULL},
7782};
7783
7784#undef DEPR_ACCESS_V8
7785
7786static const size_t deprecated_coproc_reg_count =
7787 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
7788
09d92015 7789static void
c19d1205 7790do_co_reg (void)
09d92015 7791{
fdfde340 7792 unsigned Rd;
dcbd0d71 7793 size_t i;
fdfde340
JM		 7794
7795 Rd = inst.operands[2].reg;
7796 if (thumb_mode)
7797 {
7798 if (inst.instruction == 0xee000010
7799 || inst.instruction == 0xfe000010)
7800 /* MCR, MCR2 */
7801 reject_bad_reg (Rd);
7802 else
7803 /* MRC, MRC2 */
7804 constraint (Rd == REG_SP, BAD_SP);
7805 }
7806 else
7807 {
7808 /* MCR */
7809 if (inst.instruction == 0xe000010)
7810 constraint (Rd == REG_PC, BAD_PC);
7811 }
7812
dcbd0d71
MGD		 7813 for (i = 0; i < deprecated_coproc_reg_count; ++i)
7814 {
7815 const struct deprecated_coproc_regs_s *r =
7816 deprecated_coproc_regs + i;
7817
7818 if (inst.operands[0].reg == r->cp
7819 && inst.operands[1].imm == r->opc1
7820 && inst.operands[3].reg == r->crn
7821 && inst.operands[4].reg == r->crm
7822 && inst.operands[5].imm == r->opc2)
7823 {
b10bf8c5 7824 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 7825 && warn_on_deprecated
dcbd0d71
MGD		 7826 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
7827 as_warn ("%s", r->dep_msg);
7828 }
7829 }
fdfde340 7830
c19d1205
ZW		 7831 inst.instruction |= inst.operands[0].reg << 8;
7832 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 7833 inst.instruction |= Rd << 12;
c19d1205
ZW		 7834 inst.instruction |= inst.operands[3].reg << 16;
7835 inst.instruction |= inst.operands[4].reg;
7836 inst.instruction |= inst.operands[5].imm << 5;
7837}
09d92015 7838
c19d1205
ZW		 7839/* Transfer between coprocessor register and pair of ARM registers.
7840 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7841 MCRR2
7842 MRRC{cond}
7843 MRRC2
b99bd4ef 7844
c19d1205 7845 Two XScale instructions are special cases of these:
09d92015 7846
c19d1205
ZW		 7847 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7848 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 7849
5f4273c7 7850 Result unpredictable if Rd or Rn is R15. */
a737bd4d 7851
c19d1205
ZW		 7852static void
7853do_co_reg2c (void)
7854{
fdfde340
JM		 7855 unsigned Rd, Rn;
7856
7857 Rd = inst.operands[2].reg;
7858 Rn = inst.operands[3].reg;
7859
7860 if (thumb_mode)
7861 {
7862 reject_bad_reg (Rd);
7863 reject_bad_reg (Rn);
7864 }
7865 else
7866 {
7867 constraint (Rd == REG_PC, BAD_PC);
7868 constraint (Rn == REG_PC, BAD_PC);
7869 }
7870
c19d1205
ZW		 7871 inst.instruction |= inst.operands[0].reg << 8;
7872 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM		 7873 inst.instruction |= Rd << 12;
7874 inst.instruction |= Rn << 16;
c19d1205 7875 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC		 7876}
7877
c19d1205
ZW		 7878static void
7879do_cpsi (void)
7880{
7881 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB		 7882 if (inst.operands[1].present)
7883 {
7884 inst.instruction |= CPSI_MMOD;
7885 inst.instruction |= inst.operands[1].imm;
7886 }
c19d1205 7887}
b99bd4ef 7888
62b3e311
PB		 7889static void
7890do_dbg (void)
7891{
7892 inst.instruction |= inst.operands[0].imm;
7893}
7894
eea54501
MGD		 7895static void
7896do_div (void)
7897{
7898 unsigned Rd, Rn, Rm;
7899
7900 Rd = inst.operands[0].reg;
7901 Rn = (inst.operands[1].present
7902 ? inst.operands[1].reg : Rd);
7903 Rm = inst.operands[2].reg;
7904
7905 constraint ((Rd == REG_PC), BAD_PC);
7906 constraint ((Rn == REG_PC), BAD_PC);
7907 constraint ((Rm == REG_PC), BAD_PC);
7908
7909 inst.instruction |= Rd << 16;
7910 inst.instruction |= Rn << 0;
7911 inst.instruction |= Rm << 8;
7912}
7913
b99bd4ef 7914static void
c19d1205 7915do_it (void)
b99bd4ef 7916{
c19d1205 7917 /* There is no IT instruction in ARM mode. We
e07e6e58
NC		 7918 process it to do the validation as if in
7919 thumb mode, just in case the code gets
7920 assembled for thumb using the unified syntax. */
7921
c19d1205 7922 inst.size = 0;
e07e6e58
NC		 7923 if (unified_syntax)
7924 {
7925 set_it_insn_type (IT_INSN);
7926 now_it.mask = (inst.instruction & 0xf) | 0x10;
7927 now_it.cc = inst.operands[0].imm;
7928 }
09d92015 7929}
b99bd4ef 7930
6530b175
NC		 7931/* If there is only one register in the register list,
7932 then return its register number. Otherwise return -1. */
7933static int
7934only_one_reg_in_list (int range)
7935{
7936 int i = ffs (range) - 1;
7937 return (i > 15 || range != (1 << i)) ? -1 : i;
7938}
7939
09d92015 7940static void
6530b175 7941encode_ldmstm(int from_push_pop_mnem)
ea6ef066 7942{
c19d1205
ZW		 7943 int base_reg = inst.operands[0].reg;
7944 int range = inst.operands[1].imm;
6530b175 7945 int one_reg;
ea6ef066 7946
c19d1205
ZW		 7947 inst.instruction |= base_reg << 16;
7948 inst.instruction |= range;
ea6ef066 7949
c19d1205
ZW		 7950 if (inst.operands[1].writeback)
7951 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 7952
c19d1205 7953 if (inst.operands[0].writeback)
ea6ef066 7954 {
c19d1205
ZW		 7955 inst.instruction |= WRITE_BACK;
7956 /* Check for unpredictable uses of writeback. */
7957 if (inst.instruction & LOAD_BIT)
09d92015 7958 {
c19d1205
ZW		 7959 /* Not allowed in LDM type 2. */
7960 if ((inst.instruction & LDM_TYPE_2_OR_3)
7961 && ((range & (1 << REG_PC)) == 0))
7962 as_warn (_("writeback of base register is UNPREDICTABLE"));
7963 /* Only allowed if base reg not in list for other types. */
7964 else if (range & (1 << base_reg))
7965 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7966 }
7967 else /* STM. */
7968 {
7969 /* Not allowed for type 2. */
7970 if (inst.instruction & LDM_TYPE_2_OR_3)
7971 as_warn (_("writeback of base register is UNPREDICTABLE"));
7972 /* Only allowed if base reg not in list, or first in list. */
7973 else if ((range & (1 << base_reg))
7974 && (range & ((1 << base_reg) - 1)))
7975 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 7976 }
ea6ef066 7977 }
6530b175
NC		 7978
7979 /* If PUSH/POP has only one register, then use the A2 encoding. */
7980 one_reg = only_one_reg_in_list (range);
7981 if (from_push_pop_mnem && one_reg >= 0)
7982 {
7983 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
7984
7985 inst.instruction &= A_COND_MASK;
7986 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
7987 inst.instruction |= one_reg << 12;
7988 }
7989}
7990
7991static void
7992do_ldmstm (void)
7993{
7994 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC		 7995}
7996
c19d1205
ZW		 7997/* ARMv5TE load-consecutive (argument parse)
7998 Mode is like LDRH.
7999
8000 LDRccD R, mode
8001 STRccD R, mode. */
8002
a737bd4d 8003static void
c19d1205 8004do_ldrd (void)
a737bd4d 8005{
c19d1205 8006 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 8007 _("first transfer register must be even"));
c19d1205
ZW		 8008 constraint (inst.operands[1].present
8009 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 8010 _("can only transfer two consecutive registers"));
c19d1205
ZW		 8011 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8012 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 8013
c19d1205
ZW		 8014 if (!inst.operands[1].present)
8015 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 8016
c56791bb
RE		 8017 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8018 register and the first register written; we have to diagnose
8019 overlap between the base and the second register written here. */
ea6ef066 8020
c56791bb
RE		 8021 if (inst.operands[2].reg == inst.operands[1].reg
8022 && (inst.operands[2].writeback || inst.operands[2].postind))
8023 as_warn (_("base register written back, and overlaps "
8024 "second transfer register"));
b05fe5cf 8025
c56791bb
RE		 8026 if (!(inst.instruction & V4_STR_BIT))
8027 {
c19d1205 8028 /* For an index-register load, the index register must not overlap the
c56791bb
RE		 8029 destination (even if not write-back). */
8030 if (inst.operands[2].immisreg
8031 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8032 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8033 as_warn (_("index register overlaps transfer register"));
b05fe5cf 8034 }
c19d1205
ZW		 8035 inst.instruction |= inst.operands[0].reg << 12;
8036 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW		 8037}
8038
8039static void
c19d1205 8040do_ldrex (void)
b05fe5cf 8041{
c19d1205
ZW		 8042 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8043 || inst.operands[1].postind || inst.operands[1].writeback
8044 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC		 8045 || inst.operands[1].negative
8046 /* This can arise if the programmer has written
8047 strex rN, rM, foo
8048 or if they have mistakenly used a register name as the last
8049 operand, eg:
8050 strex rN, rM, rX
8051 It is very difficult to distinguish between these two cases
8052 because "rX" might actually be a label. ie the register
8053 name has been occluded by a symbol of the same name. So we
8054 just generate a general 'bad addressing mode' type error
8055 message and leave it up to the programmer to discover the
8056 true cause and fix their mistake. */
8057 || (inst.operands[1].reg == REG_PC),
8058 BAD_ADDR_MODE);
b05fe5cf 8059
c19d1205
ZW		 8060 constraint (inst.reloc.exp.X_op != O_constant
8061 || inst.reloc.exp.X_add_number != 0,
8062 _("offset must be zero in ARM encoding"));
b05fe5cf 8063
5be8be5d
DG		 8064 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8065
c19d1205
ZW		 8066 inst.instruction |= inst.operands[0].reg << 12;
8067 inst.instruction |= inst.operands[1].reg << 16;
8068 inst.reloc.type = BFD_RELOC_UNUSED;
b05fe5cf
ZW		 8069}
8070
8071static void
c19d1205 8072do_ldrexd (void)
b05fe5cf 8073{
c19d1205
ZW		 8074 constraint (inst.operands[0].reg % 2 != 0,
8075 _("even register required"));
8076 constraint (inst.operands[1].present
8077 && inst.operands[1].reg != inst.operands[0].reg + 1,
8078 _("can only load two consecutive registers"));
8079 /* If op 1 were present and equal to PC, this function wouldn't
8080 have been called in the first place. */
8081 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 8082
c19d1205
ZW		 8083 inst.instruction |= inst.operands[0].reg << 12;
8084 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW		 8085}
8086
1be5fd2e
NC		 8087/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8088 which is not a multiple of four is UNPREDICTABLE. */
8089static void
8090check_ldr_r15_aligned (void)
8091{
8092 constraint (!(inst.operands[1].immisreg)
8093 && (inst.operands[0].reg == REG_PC
8094 && inst.operands[1].reg == REG_PC
8095 && (inst.reloc.exp.X_add_number & 0x3)),
8096 _("ldr to register 15 must be 4-byte alligned"));
8097}
8098
b05fe5cf 8099static void
c19d1205 8100do_ldst (void)
b05fe5cf 8101{
c19d1205
ZW		 8102 inst.instruction |= inst.operands[0].reg << 12;
8103 if (!inst.operands[1].isreg)
8104 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/FALSE))
b05fe5cf 8105 return;
c19d1205 8106 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 8107 check_ldr_r15_aligned ();
b05fe5cf
ZW		 8108}
8109
8110static void
c19d1205 8111do_ldstt (void)
b05fe5cf 8112{
c19d1205
ZW		 8113 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8114 reject [Rn,...]. */
8115 if (inst.operands[1].preind)
b05fe5cf 8116 {
bd3ba5d1
NC		 8117 constraint (inst.reloc.exp.X_op != O_constant
8118 || inst.reloc.exp.X_add_number != 0,
c19d1205 8119 _("this instruction requires a post-indexed address"));
b05fe5cf 8120
c19d1205
ZW		 8121 inst.operands[1].preind = 0;
8122 inst.operands[1].postind = 1;
8123 inst.operands[1].writeback = 1;
b05fe5cf 8124 }
c19d1205
ZW		 8125 inst.instruction |= inst.operands[0].reg << 12;
8126 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8127}
b05fe5cf 8128
c19d1205 8129/* Halfword and signed-byte load/store operations. */
b05fe5cf 8130
c19d1205
ZW		 8131static void
8132do_ldstv4 (void)
8133{
ff4a8d2b 8134 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW		 8135 inst.instruction |= inst.operands[0].reg << 12;
8136 if (!inst.operands[1].isreg)
8137 if (move_or_literal_pool (0, /*thumb_p=*/FALSE, /*mode_3=*/TRUE))
b05fe5cf 8138 return;
c19d1205 8139 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW		 8140}
8141
8142static void
c19d1205 8143do_ldsttv4 (void)
b05fe5cf 8144{
c19d1205
ZW		 8145 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8146 reject [Rn,...]. */
8147 if (inst.operands[1].preind)
b05fe5cf 8148 {
bd3ba5d1
NC		 8149 constraint (inst.reloc.exp.X_op != O_constant
8150 || inst.reloc.exp.X_add_number != 0,
c19d1205 8151 _("this instruction requires a post-indexed address"));
b05fe5cf 8152
c19d1205
ZW		 8153 inst.operands[1].preind = 0;
8154 inst.operands[1].postind = 1;
8155 inst.operands[1].writeback = 1;
b05fe5cf 8156 }
c19d1205
ZW		 8157 inst.instruction |= inst.operands[0].reg << 12;
8158 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8159}
b05fe5cf 8160
c19d1205
ZW		 8161/* Co-processor register load/store.
8162 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8163static void
8164do_lstc (void)
8165{
8166 inst.instruction |= inst.operands[0].reg << 8;
8167 inst.instruction |= inst.operands[1].reg << 12;
8168 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW		 8169}
8170
b05fe5cf 8171static void
c19d1205 8172do_mlas (void)
b05fe5cf 8173{
8fb9d7b9 8174 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 8175 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 8176 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 8177 && !(inst.instruction & 0x00400000))
8fb9d7b9 8178 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 8179
c19d1205
ZW		 8180 inst.instruction |= inst.operands[0].reg << 16;
8181 inst.instruction |= inst.operands[1].reg;
8182 inst.instruction |= inst.operands[2].reg << 8;
8183 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 8184}
b05fe5cf 8185
c19d1205
ZW		 8186static void
8187do_mov (void)
8188{
8189 inst.instruction |= inst.operands[0].reg << 12;
8190 encode_arm_shifter_operand (1);
8191}
b05fe5cf 8192
c19d1205
ZW		 8193/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8194static void
8195do_mov16 (void)
8196{
b6895b4f
PB		 8197 bfd_vma imm;
8198 bfd_boolean top;
8199
8200 top = (inst.instruction & 0x00400000) != 0;
8201 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8202 _(":lower16: not allowed this instruction"));
8203 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8204 _(":upper16: not allowed instruction"));
c19d1205 8205 inst.instruction |= inst.operands[0].reg << 12;
b6895b4f
PB		 8206 if (inst.reloc.type == BFD_RELOC_UNUSED)
8207 {
8208 imm = inst.reloc.exp.X_add_number;
8209 /* The value is in two pieces: 0:11, 16:19. */
8210 inst.instruction |= (imm & 0x00000fff);
8211 inst.instruction |= (imm & 0x0000f000) << 4;
8212 }
b05fe5cf 8213}
b99bd4ef 8214
037e8744
JB		 8215static void do_vfp_nsyn_opcode (const char *);
8216
8217static int
8218do_vfp_nsyn_mrs (void)
8219{
8220 if (inst.operands[0].isvec)
8221 {
8222 if (inst.operands[1].reg != 1)
477330fc 8223 first_error (_("operand 1 must be FPSCR"));
037e8744
JB		 8224 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8225 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8226 do_vfp_nsyn_opcode ("fmstat");
8227 }
8228 else if (inst.operands[1].isvec)
8229 do_vfp_nsyn_opcode ("fmrx");
8230 else
8231 return FAIL;
5f4273c7 8232
037e8744
JB		 8233 return SUCCESS;
8234}
8235
8236static int
8237do_vfp_nsyn_msr (void)
8238{
8239 if (inst.operands[0].isvec)
8240 do_vfp_nsyn_opcode ("fmxr");
8241 else
8242 return FAIL;
8243
8244 return SUCCESS;
8245}
8246
f7c21dc7
NC		 8247static void
8248do_vmrs (void)
8249{
8250 unsigned Rt = inst.operands[0].reg;
fa94de6b 8251
16d02dc9 8252 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC		 8253 {
8254 inst.error = BAD_SP;
8255 return;
8256 }
8257
8258 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 8259 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC		 8260 {
8261 inst.error = BAD_PC;
8262 return;
8263 }
8264
16d02dc9
JB		 8265 /* If we get through parsing the register name, we just insert the number
8266 generated into the instruction without further validation. */
8267 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC		 8268 inst.instruction |= (Rt << 12);
8269}
8270
8271static void
8272do_vmsr (void)
8273{
8274 unsigned Rt = inst.operands[1].reg;
fa94de6b 8275
f7c21dc7
NC		 8276 if (thumb_mode)
8277 reject_bad_reg (Rt);
8278 else if (Rt == REG_PC)
8279 {
8280 inst.error = BAD_PC;
8281 return;
8282 }
8283
16d02dc9
JB		 8284 /* If we get through parsing the register name, we just insert the number
8285 generated into the instruction without further validation. */
8286 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC		 8287 inst.instruction |= (Rt << 12);
8288}
8289
b99bd4ef 8290static void
c19d1205 8291do_mrs (void)
b99bd4ef 8292{
90ec0d68
MGD		 8293 unsigned br;
8294
037e8744
JB		 8295 if (do_vfp_nsyn_mrs () == SUCCESS)
8296 return;
8297
ff4a8d2b 8298 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 8299 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD		 8300
8301 if (inst.operands[1].isreg)
8302 {
8303 br = inst.operands[1].reg;
8304 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8305 as_bad (_("bad register for mrs"));
8306 }
8307 else
8308 {
8309 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8310 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8311 != (PSR_c|PSR_f),
d2cd1205 8312 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD		 8313 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8314 }
8315
8316 inst.instruction |= br;
c19d1205 8317}
b99bd4ef 8318
c19d1205
ZW		 8319/* Two possible forms:
8320 "{C|S}PSR_<field>, Rm",
8321 "{C|S}PSR_f, #expression". */
b99bd4ef 8322
c19d1205
ZW		 8323static void
8324do_msr (void)
8325{
037e8744
JB		 8326 if (do_vfp_nsyn_msr () == SUCCESS)
8327 return;
8328
c19d1205
ZW		 8329 inst.instruction |= inst.operands[0].imm;
8330 if (inst.operands[1].isreg)
8331 inst.instruction |= inst.operands[1].reg;
8332 else
b99bd4ef 8333 {
c19d1205
ZW		 8334 inst.instruction |= INST_IMMEDIATE;
8335 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8336 inst.reloc.pc_rel = 0;
b99bd4ef 8337 }
b99bd4ef
NC		 8338}
8339
c19d1205
ZW		 8340static void
8341do_mul (void)
a737bd4d 8342{
ff4a8d2b
NC		 8343 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8344
c19d1205
ZW		 8345 if (!inst.operands[2].present)
8346 inst.operands[2].reg = inst.operands[0].reg;
8347 inst.instruction |= inst.operands[0].reg << 16;
8348 inst.instruction |= inst.operands[1].reg;
8349 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 8350
8fb9d7b9
MS		 8351 if (inst.operands[0].reg == inst.operands[1].reg
8352 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8353 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC		 8354}
8355
c19d1205
ZW		 8356/* Long Multiply Parser
8357 UMULL RdLo, RdHi, Rm, Rs
8358 SMULL RdLo, RdHi, Rm, Rs
8359 UMLAL RdLo, RdHi, Rm, Rs
8360 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC		 8361
8362static void
c19d1205 8363do_mull (void)
b99bd4ef 8364{
c19d1205
ZW		 8365 inst.instruction |= inst.operands[0].reg << 12;
8366 inst.instruction |= inst.operands[1].reg << 16;
8367 inst.instruction |= inst.operands[2].reg;
8368 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 8369
682b27ad
PB		 8370 /* rdhi and rdlo must be different. */
8371 if (inst.operands[0].reg == inst.operands[1].reg)
8372 as_tsktsk (_("rdhi and rdlo must be different"));
8373
8374 /* rdhi, rdlo and rm must all be different before armv6. */
8375 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 8376 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 8377 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW		 8378 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8379}
b99bd4ef 8380
c19d1205
ZW		 8381static void
8382do_nop (void)
8383{
e7495e45
NS		 8384 if (inst.operands[0].present
8385 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW		 8386 {
8387 /* Architectural NOP hints are CPSR sets with no bits selected. */
8388 inst.instruction &= 0xf0000000;
e7495e45
NS		 8389 inst.instruction |= 0x0320f000;
8390 if (inst.operands[0].present)
8391 inst.instruction |= inst.operands[0].imm;
c19d1205 8392 }
b99bd4ef
NC		 8393}
8394
c19d1205
ZW		 8395/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8396 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8397 Condition defaults to COND_ALWAYS.
8398 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC		 8399
8400static void
c19d1205 8401do_pkhbt (void)
b99bd4ef 8402{
c19d1205
ZW		 8403 inst.instruction |= inst.operands[0].reg << 12;
8404 inst.instruction |= inst.operands[1].reg << 16;
8405 inst.instruction |= inst.operands[2].reg;
8406 if (inst.operands[3].present)
8407 encode_arm_shift (3);
8408}
b99bd4ef 8409
c19d1205 8410/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 8411
c19d1205
ZW		 8412static void
8413do_pkhtb (void)
8414{
8415 if (!inst.operands[3].present)
b99bd4ef 8416 {
c19d1205
ZW		 8417 /* If the shift specifier is omitted, turn the instruction
8418 into pkhbt rd, rm, rn. */
8419 inst.instruction &= 0xfff00010;
8420 inst.instruction |= inst.operands[0].reg << 12;
8421 inst.instruction |= inst.operands[1].reg;
8422 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 8423 }
8424 else
8425 {
c19d1205
ZW		 8426 inst.instruction |= inst.operands[0].reg << 12;
8427 inst.instruction |= inst.operands[1].reg << 16;
8428 inst.instruction |= inst.operands[2].reg;
8429 encode_arm_shift (3);
b99bd4ef
NC		 8430 }
8431}
8432
c19d1205 8433/* ARMv5TE: Preload-Cache
60e5ef9f 8434 MP Extensions: Preload for write
c19d1205 8435
60e5ef9f 8436 PLD(W) <addr_mode>
c19d1205
ZW		 8437
8438 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC		 8439
8440static void
c19d1205 8441do_pld (void)
b99bd4ef 8442{
c19d1205
ZW		 8443 constraint (!inst.operands[0].isreg,
8444 _("'[' expected after PLD mnemonic"));
8445 constraint (inst.operands[0].postind,
8446 _("post-indexed expression used in preload instruction"));
8447 constraint (inst.operands[0].writeback,
8448 _("writeback used in preload instruction"));
8449 constraint (!inst.operands[0].preind,
8450 _("unindexed addressing used in preload instruction"));
c19d1205
ZW		 8451 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8452}
b99bd4ef 8453
62b3e311
PB		 8454/* ARMv7: PLI <addr_mode> */
8455static void
8456do_pli (void)
8457{
8458 constraint (!inst.operands[0].isreg,
8459 _("'[' expected after PLI mnemonic"));
8460 constraint (inst.operands[0].postind,
8461 _("post-indexed expression used in preload instruction"));
8462 constraint (inst.operands[0].writeback,
8463 _("writeback used in preload instruction"));
8464 constraint (!inst.operands[0].preind,
8465 _("unindexed addressing used in preload instruction"));
8466 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
8467 inst.instruction &= ~PRE_INDEX;
8468}
8469
c19d1205
ZW		 8470static void
8471do_push_pop (void)
8472{
8473 inst.operands[1] = inst.operands[0];
8474 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
8475 inst.operands[0].isreg = 1;
8476 inst.operands[0].writeback = 1;
8477 inst.operands[0].reg = REG_SP;
6530b175 8478 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 8479}
b99bd4ef 8480
c19d1205
ZW		 8481/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8482 word at the specified address and the following word
8483 respectively.
8484 Unconditionally executed.
8485 Error if Rn is R15. */
b99bd4ef 8486
c19d1205
ZW		 8487static void
8488do_rfe (void)
8489{
8490 inst.instruction |= inst.operands[0].reg << 16;
8491 if (inst.operands[0].writeback)
8492 inst.instruction |= WRITE_BACK;
8493}
b99bd4ef 8494
c19d1205 8495/* ARM V6 ssat (argument parse). */
b99bd4ef 8496
c19d1205
ZW		 8497static void
8498do_ssat (void)
8499{
8500 inst.instruction |= inst.operands[0].reg << 12;
8501 inst.instruction |= (inst.operands[1].imm - 1) << 16;
8502 inst.instruction |= inst.operands[2].reg;
b99bd4ef 8503
c19d1205
ZW		 8504 if (inst.operands[3].present)
8505 encode_arm_shift (3);
b99bd4ef
NC		 8506}
8507
c19d1205 8508/* ARM V6 usat (argument parse). */
b99bd4ef
NC		 8509
8510static void
c19d1205 8511do_usat (void)
b99bd4ef 8512{
c19d1205
ZW		 8513 inst.instruction |= inst.operands[0].reg << 12;
8514 inst.instruction |= inst.operands[1].imm << 16;
8515 inst.instruction |= inst.operands[2].reg;
b99bd4ef 8516
c19d1205
ZW		 8517 if (inst.operands[3].present)
8518 encode_arm_shift (3);
b99bd4ef
NC		 8519}
8520
c19d1205 8521/* ARM V6 ssat16 (argument parse). */
09d92015
MM		 8522
8523static void
c19d1205 8524do_ssat16 (void)
09d92015 8525{
c19d1205
ZW		 8526 inst.instruction |= inst.operands[0].reg << 12;
8527 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
8528 inst.instruction |= inst.operands[2].reg;
09d92015
MM		 8529}
8530
c19d1205
ZW		 8531static void
8532do_usat16 (void)
a737bd4d 8533{
c19d1205
ZW		 8534 inst.instruction |= inst.operands[0].reg << 12;
8535 inst.instruction |= inst.operands[1].imm << 16;
8536 inst.instruction |= inst.operands[2].reg;
8537}
a737bd4d 8538
c19d1205
ZW		 8539/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8540 preserving the other bits.
a737bd4d 8541
c19d1205
ZW		 8542 setend <endian_specifier>, where <endian_specifier> is either
8543 BE or LE. */
a737bd4d 8544
c19d1205
ZW		 8545static void
8546do_setend (void)
8547{
12e37cbc
MGD		 8548 if (warn_on_deprecated
8549 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
8550 as_warn (_("setend use is deprecated for ARMv8"));
8551
c19d1205
ZW		 8552 if (inst.operands[0].imm)
8553 inst.instruction |= 0x200;
a737bd4d
NC		 8554}
8555
8556static void
c19d1205 8557do_shift (void)
a737bd4d 8558{
c19d1205
ZW		 8559 unsigned int Rm = (inst.operands[1].present
8560 ? inst.operands[1].reg
8561 : inst.operands[0].reg);
a737bd4d 8562
c19d1205
ZW		 8563 inst.instruction |= inst.operands[0].reg << 12;
8564 inst.instruction |= Rm;
8565 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 8566 {
c19d1205
ZW		 8567 inst.instruction |= inst.operands[2].reg << 8;
8568 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC		 8569 /* PR 12854: Error on extraneous shifts. */
8570 constraint (inst.operands[2].shifted,
8571 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC		 8572 }
8573 else
c19d1205 8574 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC		 8575}
8576
09d92015 8577static void
3eb17e6b 8578do_smc (void)
09d92015 8579{
3eb17e6b 8580 inst.reloc.type = BFD_RELOC_ARM_SMC;
c19d1205 8581 inst.reloc.pc_rel = 0;
09d92015
MM		 8582}
8583
90ec0d68
MGD		 8584static void
8585do_hvc (void)
8586{
8587 inst.reloc.type = BFD_RELOC_ARM_HVC;
8588 inst.reloc.pc_rel = 0;
8589}
8590
09d92015 8591static void
c19d1205 8592do_swi (void)
09d92015 8593{
c19d1205
ZW		 8594 inst.reloc.type = BFD_RELOC_ARM_SWI;
8595 inst.reloc.pc_rel = 0;
09d92015
MM		 8596}
8597
c19d1205
ZW		 8598/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8599 SMLAxy{cond} Rd,Rm,Rs,Rn
8600 SMLAWy{cond} Rd,Rm,Rs,Rn
8601 Error if any register is R15. */
e16bb312 8602
c19d1205
ZW		 8603static void
8604do_smla (void)
e16bb312 8605{
c19d1205
ZW		 8606 inst.instruction |= inst.operands[0].reg << 16;
8607 inst.instruction |= inst.operands[1].reg;
8608 inst.instruction |= inst.operands[2].reg << 8;
8609 inst.instruction |= inst.operands[3].reg << 12;
8610}
a737bd4d 8611
c19d1205
ZW		 8612/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8613 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8614 Error if any register is R15.
8615 Warning if Rdlo == Rdhi. */
a737bd4d 8616
c19d1205
ZW		 8617static void
8618do_smlal (void)
8619{
8620 inst.instruction |= inst.operands[0].reg << 12;
8621 inst.instruction |= inst.operands[1].reg << 16;
8622 inst.instruction |= inst.operands[2].reg;
8623 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 8624
c19d1205
ZW		 8625 if (inst.operands[0].reg == inst.operands[1].reg)
8626 as_tsktsk (_("rdhi and rdlo must be different"));
8627}
a737bd4d 8628
c19d1205
ZW		 8629/* ARM V5E (El Segundo) signed-multiply (argument parse)
8630 SMULxy{cond} Rd,Rm,Rs
8631 Error if any register is R15. */
a737bd4d 8632
c19d1205
ZW		 8633static void
8634do_smul (void)
8635{
8636 inst.instruction |= inst.operands[0].reg << 16;
8637 inst.instruction |= inst.operands[1].reg;
8638 inst.instruction |= inst.operands[2].reg << 8;
8639}
a737bd4d 8640
b6702015
PB		 8641/* ARM V6 srs (argument parse). The variable fields in the encoding are
8642 the same for both ARM and Thumb-2. */
a737bd4d 8643
c19d1205
ZW		 8644static void
8645do_srs (void)
8646{
b6702015
PB		 8647 int reg;
8648
8649 if (inst.operands[0].present)
8650 {
8651 reg = inst.operands[0].reg;
fdfde340 8652 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB		 8653 }
8654 else
fdfde340 8655 reg = REG_SP;
b6702015
PB		 8656
8657 inst.instruction |= reg << 16;
8658 inst.instruction |= inst.operands[1].imm;
8659 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW		 8660 inst.instruction |= WRITE_BACK;
8661}
a737bd4d 8662
c19d1205 8663/* ARM V6 strex (argument parse). */
a737bd4d 8664
c19d1205
ZW		 8665static void
8666do_strex (void)
8667{
8668 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8669 || inst.operands[2].postind || inst.operands[2].writeback
8670 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC		 8671 || inst.operands[2].negative
8672 /* See comment in do_ldrex(). */
8673 || (inst.operands[2].reg == REG_PC),
8674 BAD_ADDR_MODE);
a737bd4d 8675
c19d1205
ZW		 8676 constraint (inst.operands[0].reg == inst.operands[1].reg
8677 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 8678
c19d1205
ZW		 8679 constraint (inst.reloc.exp.X_op != O_constant
8680 || inst.reloc.exp.X_add_number != 0,
8681 _("offset must be zero in ARM encoding"));
a737bd4d 8682
c19d1205
ZW		 8683 inst.instruction |= inst.operands[0].reg << 12;
8684 inst.instruction |= inst.operands[1].reg;
8685 inst.instruction |= inst.operands[2].reg << 16;
8686 inst.reloc.type = BFD_RELOC_UNUSED;
e16bb312
NC		 8687}
8688
877807f8
NC		 8689static void
8690do_t_strexbh (void)
8691{
8692 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
8693 || inst.operands[2].postind || inst.operands[2].writeback
8694 || inst.operands[2].immisreg || inst.operands[2].shifted
8695 || inst.operands[2].negative,
8696 BAD_ADDR_MODE);
8697
8698 constraint (inst.operands[0].reg == inst.operands[1].reg
8699 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8700
8701 do_rm_rd_rn ();
8702}
8703
e16bb312 8704static void
c19d1205 8705do_strexd (void)
e16bb312 8706{
c19d1205
ZW		 8707 constraint (inst.operands[1].reg % 2 != 0,
8708 _("even register required"));
8709 constraint (inst.operands[2].present
8710 && inst.operands[2].reg != inst.operands[1].reg + 1,
8711 _("can only store two consecutive registers"));
8712 /* If op 2 were present and equal to PC, this function wouldn't
8713 have been called in the first place. */
8714 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 8715
c19d1205
ZW		 8716 constraint (inst.operands[0].reg == inst.operands[1].reg
8717 || inst.operands[0].reg == inst.operands[1].reg + 1
8718 || inst.operands[0].reg == inst.operands[3].reg,
8719 BAD_OVERLAP);
e16bb312 8720
c19d1205
ZW		 8721 inst.instruction |= inst.operands[0].reg << 12;
8722 inst.instruction |= inst.operands[1].reg;
8723 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC		 8724}
8725
9eb6c0f1
MGD		 8726/* ARM V8 STRL. */
8727static void
4b8c8c02 8728do_stlex (void)
9eb6c0f1
MGD		 8729{
8730 constraint (inst.operands[0].reg == inst.operands[1].reg
8731 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8732
8733 do_rd_rm_rn ();
8734}
8735
8736static void
4b8c8c02 8737do_t_stlex (void)
9eb6c0f1
MGD		 8738{
8739 constraint (inst.operands[0].reg == inst.operands[1].reg
8740 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
8741
8742 do_rm_rd_rn ();
8743}
8744
c19d1205
ZW		 8745/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8746 extends it to 32-bits, and adds the result to a value in another
8747 register. You can specify a rotation by 0, 8, 16, or 24 bits
8748 before extracting the 16-bit value.
8749 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8750 Condition defaults to COND_ALWAYS.
8751 Error if any register uses R15. */
8752
e16bb312 8753static void
c19d1205 8754do_sxtah (void)
e16bb312 8755{
c19d1205
ZW		 8756 inst.instruction |= inst.operands[0].reg << 12;
8757 inst.instruction |= inst.operands[1].reg << 16;
8758 inst.instruction |= inst.operands[2].reg;
8759 inst.instruction |= inst.operands[3].imm << 10;
8760}
e16bb312 8761
c19d1205 8762/* ARM V6 SXTH.
e16bb312 8763
c19d1205
ZW		 8764 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8765 Condition defaults to COND_ALWAYS.
8766 Error if any register uses R15. */
e16bb312
NC		 8767
8768static void
c19d1205 8769do_sxth (void)
e16bb312 8770{
c19d1205
ZW		 8771 inst.instruction |= inst.operands[0].reg << 12;
8772 inst.instruction |= inst.operands[1].reg;
8773 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 8774}
c19d1205
ZW		 8775\f
8776/* VFP instructions. In a logical order: SP variant first, monad
8777 before dyad, arithmetic then move then load/store. */
e16bb312
NC		 8778
8779static void
c19d1205 8780do_vfp_sp_monadic (void)
e16bb312 8781{
5287ad62
JB		 8782 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8783 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 8784}
8785
8786static void
c19d1205 8787do_vfp_sp_dyadic (void)
e16bb312 8788{
5287ad62
JB		 8789 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8790 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
8791 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 8792}
8793
8794static void
c19d1205 8795do_vfp_sp_compare_z (void)
e16bb312 8796{
5287ad62 8797 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC		 8798}
8799
8800static void
c19d1205 8801do_vfp_dp_sp_cvt (void)
e16bb312 8802{
5287ad62
JB		 8803 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8804 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 8805}
8806
8807static void
c19d1205 8808do_vfp_sp_dp_cvt (void)
e16bb312 8809{
5287ad62
JB		 8810 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
8811 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC		 8812}
8813
8814static void
c19d1205 8815do_vfp_reg_from_sp (void)
e16bb312 8816{
c19d1205 8817 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 8818 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC		 8819}
8820
8821static void
c19d1205 8822do_vfp_reg2_from_sp2 (void)
e16bb312 8823{
c19d1205
ZW		 8824 constraint (inst.operands[2].imm != 2,
8825 _("only two consecutive VFP SP registers allowed here"));
8826 inst.instruction |= inst.operands[0].reg << 12;
8827 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 8828 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 8829}
8830
8831static void
c19d1205 8832do_vfp_sp_from_reg (void)
e16bb312 8833{
5287ad62 8834 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 8835 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC		 8836}
8837
8838static void
c19d1205 8839do_vfp_sp2_from_reg2 (void)
e16bb312 8840{
c19d1205
ZW		 8841 constraint (inst.operands[0].imm != 2,
8842 _("only two consecutive VFP SP registers allowed here"));
5287ad62 8843 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW		 8844 inst.instruction |= inst.operands[1].reg << 12;
8845 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC		 8846}
8847
8848static void
c19d1205 8849do_vfp_sp_ldst (void)
e16bb312 8850{
5287ad62 8851 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 8852 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 8853}
8854
8855static void
c19d1205 8856do_vfp_dp_ldst (void)
e16bb312 8857{
5287ad62 8858 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 8859 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 8860}
8861
c19d1205 8862
e16bb312 8863static void
c19d1205 8864vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 8865{
c19d1205
ZW		 8866 if (inst.operands[0].writeback)
8867 inst.instruction |= WRITE_BACK;
8868 else
8869 constraint (ldstm_type != VFP_LDSTMIA,
8870 _("this addressing mode requires base-register writeback"));
8871 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 8872 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 8873 inst.instruction |= inst.operands[1].imm;
e16bb312
NC		 8874}
8875
8876static void
c19d1205 8877vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 8878{
c19d1205 8879 int count;
e16bb312 8880
c19d1205
ZW		 8881 if (inst.operands[0].writeback)
8882 inst.instruction |= WRITE_BACK;
8883 else
8884 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
8885 _("this addressing mode requires base-register writeback"));
e16bb312 8886
c19d1205 8887 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 8888 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 8889
c19d1205
ZW		 8890 count = inst.operands[1].imm << 1;
8891 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
8892 count += 1;
e16bb312 8893
c19d1205 8894 inst.instruction |= count;
e16bb312
NC		 8895}
8896
8897static void
c19d1205 8898do_vfp_sp_ldstmia (void)
e16bb312 8899{
c19d1205 8900 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 8901}
8902
8903static void
c19d1205 8904do_vfp_sp_ldstmdb (void)
e16bb312 8905{
c19d1205 8906 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 8907}
8908
8909static void
c19d1205 8910do_vfp_dp_ldstmia (void)
e16bb312 8911{
c19d1205 8912 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 8913}
8914
8915static void
c19d1205 8916do_vfp_dp_ldstmdb (void)
e16bb312 8917{
c19d1205 8918 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 8919}
8920
8921static void
c19d1205 8922do_vfp_xp_ldstmia (void)
e16bb312 8923{
c19d1205
ZW		 8924 vfp_dp_ldstm (VFP_LDSTMIAX);
8925}
e16bb312 8926
c19d1205
ZW		 8927static void
8928do_vfp_xp_ldstmdb (void)
8929{
8930 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 8931}
5287ad62
JB		 8932
8933static void
8934do_vfp_dp_rd_rm (void)
8935{
8936 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8937 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
8938}
8939
8940static void
8941do_vfp_dp_rn_rd (void)
8942{
8943 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
8944 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8945}
8946
8947static void
8948do_vfp_dp_rd_rn (void)
8949{
8950 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8951 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8952}
8953
8954static void
8955do_vfp_dp_rd_rn_rm (void)
8956{
8957 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8958 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
8959 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
8960}
8961
8962static void
8963do_vfp_dp_rd (void)
8964{
8965 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
8966}
8967
8968static void
8969do_vfp_dp_rm_rd_rn (void)
8970{
8971 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
8972 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
8973 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
8974}
8975
8976/* VFPv3 instructions. */
8977static void
8978do_vfp_sp_const (void)
8979{
8980 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB		 8981 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8982 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 8983}
8984
8985static void
8986do_vfp_dp_const (void)
8987{
8988 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB		 8989 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
8990 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 8991}
8992
8993static void
8994vfp_conv (int srcsize)
8995{
5f1af56b
MGD		 8996 int immbits = srcsize - inst.operands[1].imm;
8997
fa94de6b
RM		 8998 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
8999 {
5f1af56b 9000 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 9001 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD		 9002 inst.error = _("immediate value out of range, expected range [0, 16]");
9003 return;
9004 }
fa94de6b 9005 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD		 9006 {
9007 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 9008 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD		 9009 inst.error = _("immediate value out of range, expected range [1, 32]");
9010 return;
9011 }
9012
5287ad62
JB		 9013 inst.instruction |= (immbits & 1) << 5;
9014 inst.instruction |= (immbits >> 1);
9015}
9016
9017static void
9018do_vfp_sp_conv_16 (void)
9019{
9020 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9021 vfp_conv (16);
9022}
9023
9024static void
9025do_vfp_dp_conv_16 (void)
9026{
9027 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9028 vfp_conv (16);
9029}
9030
9031static void
9032do_vfp_sp_conv_32 (void)
9033{
9034 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9035 vfp_conv (32);
9036}
9037
9038static void
9039do_vfp_dp_conv_32 (void)
9040{
9041 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9042 vfp_conv (32);
9043}
c19d1205
ZW		 9044\f
9045/* FPA instructions. Also in a logical order. */
e16bb312 9046
c19d1205
ZW		 9047static void
9048do_fpa_cmp (void)
9049{
9050 inst.instruction |= inst.operands[0].reg << 16;
9051 inst.instruction |= inst.operands[1].reg;
9052}
b99bd4ef
NC		 9053
9054static void
c19d1205 9055do_fpa_ldmstm (void)
b99bd4ef 9056{
c19d1205
ZW		 9057 inst.instruction |= inst.operands[0].reg << 12;
9058 switch (inst.operands[1].imm)
9059 {
9060 case 1: inst.instruction |= CP_T_X; break;
9061 case 2: inst.instruction |= CP_T_Y; break;
9062 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9063 case 4: break;
9064 default: abort ();
9065 }
b99bd4ef 9066
c19d1205
ZW		 9067 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9068 {
9069 /* The instruction specified "ea" or "fd", so we can only accept
9070 [Rn]{!}. The instruction does not really support stacking or
9071 unstacking, so we have to emulate these by setting appropriate
9072 bits and offsets. */
9073 constraint (inst.reloc.exp.X_op != O_constant
9074 || inst.reloc.exp.X_add_number != 0,
9075 _("this instruction does not support indexing"));
b99bd4ef 9076
c19d1205
ZW		 9077 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9078 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 9079
c19d1205
ZW		 9080 if (!(inst.instruction & INDEX_UP))
9081 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
b99bd4ef 9082
c19d1205
ZW		 9083 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9084 {
9085 inst.operands[2].preind = 0;
9086 inst.operands[2].postind = 1;
9087 }
9088 }
b99bd4ef 9089
c19d1205 9090 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 9091}
c19d1205
ZW		 9092\f
9093/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 9094
c19d1205
ZW		 9095static void
9096do_iwmmxt_tandorc (void)
9097{
9098 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9099}
b99bd4ef 9100
c19d1205
ZW		 9101static void
9102do_iwmmxt_textrc (void)
9103{
9104 inst.instruction |= inst.operands[0].reg << 12;
9105 inst.instruction |= inst.operands[1].imm;
9106}
b99bd4ef
NC		 9107
9108static void
c19d1205 9109do_iwmmxt_textrm (void)
b99bd4ef 9110{
c19d1205
ZW		 9111 inst.instruction |= inst.operands[0].reg << 12;
9112 inst.instruction |= inst.operands[1].reg << 16;
9113 inst.instruction |= inst.operands[2].imm;
9114}
b99bd4ef 9115
c19d1205
ZW		 9116static void
9117do_iwmmxt_tinsr (void)
9118{
9119 inst.instruction |= inst.operands[0].reg << 16;
9120 inst.instruction |= inst.operands[1].reg << 12;
9121 inst.instruction |= inst.operands[2].imm;
9122}
b99bd4ef 9123
c19d1205
ZW		 9124static void
9125do_iwmmxt_tmia (void)
9126{
9127 inst.instruction |= inst.operands[0].reg << 5;
9128 inst.instruction |= inst.operands[1].reg;
9129 inst.instruction |= inst.operands[2].reg << 12;
9130}
b99bd4ef 9131
c19d1205
ZW		 9132static void
9133do_iwmmxt_waligni (void)
9134{
9135 inst.instruction |= inst.operands[0].reg << 12;
9136 inst.instruction |= inst.operands[1].reg << 16;
9137 inst.instruction |= inst.operands[2].reg;
9138 inst.instruction |= inst.operands[3].imm << 20;
9139}
b99bd4ef 9140
2d447fca
JM		 9141static void
9142do_iwmmxt_wmerge (void)
9143{
9144 inst.instruction |= inst.operands[0].reg << 12;
9145 inst.instruction |= inst.operands[1].reg << 16;
9146 inst.instruction |= inst.operands[2].reg;
9147 inst.instruction |= inst.operands[3].imm << 21;
9148}
9149
c19d1205
ZW		 9150static void
9151do_iwmmxt_wmov (void)
9152{
9153 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9154 inst.instruction |= inst.operands[0].reg << 12;
9155 inst.instruction |= inst.operands[1].reg << 16;
9156 inst.instruction |= inst.operands[1].reg;
9157}
b99bd4ef 9158
c19d1205
ZW		 9159static void
9160do_iwmmxt_wldstbh (void)
9161{
8f06b2d8 9162 int reloc;
c19d1205 9163 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB		 9164 if (thumb_mode)
9165 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9166 else
9167 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9168 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC		 9169}
9170
c19d1205
ZW		 9171static void
9172do_iwmmxt_wldstw (void)
9173{
9174 /* RIWR_RIWC clears .isreg for a control register. */
9175 if (!inst.operands[0].isreg)
9176 {
9177 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9178 inst.instruction |= 0xf0000000;
9179 }
b99bd4ef 9180
c19d1205
ZW		 9181 inst.instruction |= inst.operands[0].reg << 12;
9182 encode_arm_cp_address (1, TRUE, TRUE, 0);
9183}
b99bd4ef
NC		 9184
9185static void
c19d1205 9186do_iwmmxt_wldstd (void)
b99bd4ef 9187{
c19d1205 9188 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM		 9189 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9190 && inst.operands[1].immisreg)
9191 {
9192 inst.instruction &= ~0x1a000ff;
9193 inst.instruction |= (0xf << 28);
9194 if (inst.operands[1].preind)
9195 inst.instruction |= PRE_INDEX;
9196 if (!inst.operands[1].negative)
9197 inst.instruction |= INDEX_UP;
9198 if (inst.operands[1].writeback)
9199 inst.instruction |= WRITE_BACK;
9200 inst.instruction |= inst.operands[1].reg << 16;
9201 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9202 inst.instruction |= inst.operands[1].imm;
9203 }
9204 else
9205 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 9206}
b99bd4ef 9207
c19d1205
ZW		 9208static void
9209do_iwmmxt_wshufh (void)
9210{
9211 inst.instruction |= inst.operands[0].reg << 12;
9212 inst.instruction |= inst.operands[1].reg << 16;
9213 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9214 inst.instruction |= (inst.operands[2].imm & 0x0f);
9215}
b99bd4ef 9216
c19d1205
ZW		 9217static void
9218do_iwmmxt_wzero (void)
9219{
9220 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9221 inst.instruction |= inst.operands[0].reg;
9222 inst.instruction |= inst.operands[0].reg << 12;
9223 inst.instruction |= inst.operands[0].reg << 16;
9224}
2d447fca
JM		 9225
9226static void
9227do_iwmmxt_wrwrwr_or_imm5 (void)
9228{
9229 if (inst.operands[2].isreg)
9230 do_rd_rn_rm ();
9231 else {
9232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9233 _("immediate operand requires iWMMXt2"));
9234 do_rd_rn ();
9235 if (inst.operands[2].imm == 0)
9236 {
9237 switch ((inst.instruction >> 20) & 0xf)
9238 {
9239 case 4:
9240 case 5:
9241 case 6:
5f4273c7 9242 case 7:
2d447fca
JM		 9243 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9244 inst.operands[2].imm = 16;
9245 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9246 break;
9247 case 8:
9248 case 9:
9249 case 10:
9250 case 11:
9251 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9252 inst.operands[2].imm = 32;
9253 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9254 break;
9255 case 12:
9256 case 13:
9257 case 14:
9258 case 15:
9259 {
9260 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9261 unsigned long wrn;
9262 wrn = (inst.instruction >> 16) & 0xf;
9263 inst.instruction &= 0xff0fff0f;
9264 inst.instruction |= wrn;
9265 /* Bail out here; the instruction is now assembled. */
9266 return;
9267 }
9268 }
9269 }
9270 /* Map 32 -> 0, etc. */
9271 inst.operands[2].imm &= 0x1f;
9272 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9273 }
9274}
c19d1205
ZW		 9275\f
9276/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9277 operations first, then control, shift, and load/store. */
b99bd4ef 9278
c19d1205 9279/* Insns like "foo X,Y,Z". */
b99bd4ef 9280
c19d1205
ZW		 9281static void
9282do_mav_triple (void)
9283{
9284 inst.instruction |= inst.operands[0].reg << 16;
9285 inst.instruction |= inst.operands[1].reg;
9286 inst.instruction |= inst.operands[2].reg << 12;
9287}
b99bd4ef 9288
c19d1205
ZW		 9289/* Insns like "foo W,X,Y,Z".
9290 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 9291
c19d1205
ZW		 9292static void
9293do_mav_quad (void)
9294{
9295 inst.instruction |= inst.operands[0].reg << 5;
9296 inst.instruction |= inst.operands[1].reg << 12;
9297 inst.instruction |= inst.operands[2].reg << 16;
9298 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC		 9299}
9300
c19d1205
ZW		 9301/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9302static void
9303do_mav_dspsc (void)
a737bd4d 9304{
c19d1205
ZW		 9305 inst.instruction |= inst.operands[1].reg << 12;
9306}
a737bd4d 9307
c19d1205
ZW		 9308/* Maverick shift immediate instructions.
9309 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9310 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 9311
c19d1205
ZW		 9312static void
9313do_mav_shift (void)
9314{
9315 int imm = inst.operands[2].imm;
a737bd4d 9316
c19d1205
ZW		 9317 inst.instruction |= inst.operands[0].reg << 12;
9318 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 9319
c19d1205
ZW		 9320 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9321 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9322 Bit 4 should be 0. */
9323 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 9324
c19d1205
ZW		 9325 inst.instruction |= imm;
9326}
9327\f
9328/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 9329
c19d1205
ZW		 9330/* Xscale multiply-accumulate (argument parse)
9331 MIAcc acc0,Rm,Rs
9332 MIAPHcc acc0,Rm,Rs
9333 MIAxycc acc0,Rm,Rs. */
a737bd4d 9334
c19d1205
ZW		 9335static void
9336do_xsc_mia (void)
9337{
9338 inst.instruction |= inst.operands[1].reg;
9339 inst.instruction |= inst.operands[2].reg << 12;
9340}
a737bd4d 9341
c19d1205 9342/* Xscale move-accumulator-register (argument parse)
a737bd4d 9343
c19d1205 9344 MARcc acc0,RdLo,RdHi. */
b99bd4ef 9345
c19d1205
ZW		 9346static void
9347do_xsc_mar (void)
9348{
9349 inst.instruction |= inst.operands[1].reg << 12;
9350 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 9351}
9352
c19d1205 9353/* Xscale move-register-accumulator (argument parse)
b99bd4ef 9354
c19d1205 9355 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC		 9356
9357static void
c19d1205 9358do_xsc_mra (void)
b99bd4ef 9359{
c19d1205
ZW		 9360 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9361 inst.instruction |= inst.operands[0].reg << 12;
9362 inst.instruction |= inst.operands[1].reg << 16;
9363}
9364\f
9365/* Encoding functions relevant only to Thumb. */
b99bd4ef 9366
c19d1205
ZW		 9367/* inst.operands[i] is a shifted-register operand; encode
9368 it into inst.instruction in the format used by Thumb32. */
9369
9370static void
9371encode_thumb32_shifted_operand (int i)
9372{
9373 unsigned int value = inst.reloc.exp.X_add_number;
9374 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 9375
9c3c69f2
PB		 9376 constraint (inst.operands[i].immisreg,
9377 _("shift by register not allowed in thumb mode"));
c19d1205
ZW		 9378 inst.instruction |= inst.operands[i].reg;
9379 if (shift == SHIFT_RRX)
9380 inst.instruction |= SHIFT_ROR << 4;
9381 else
b99bd4ef 9382 {
c19d1205
ZW		 9383 constraint (inst.reloc.exp.X_op != O_constant,
9384 _("expression too complex"));
9385
9386 constraint (value > 32
9387 || (value == 32 && (shift == SHIFT_LSL
9388 || shift == SHIFT_ROR)),
9389 _("shift expression is too large"));
9390
9391 if (value == 0)
9392 shift = SHIFT_LSL;
9393 else if (value == 32)
9394 value = 0;
9395
9396 inst.instruction |= shift << 4;
9397 inst.instruction |= (value & 0x1c) << 10;
9398 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 9399 }
c19d1205 9400}
b99bd4ef 9401
b99bd4ef 9402
c19d1205
ZW		 9403/* inst.operands[i] was set up by parse_address. Encode it into a
9404 Thumb32 format load or store instruction. Reject forms that cannot
9405 be used with such instructions. If is_t is true, reject forms that
9406 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG		 9407 that cannot be used with a D instruction. If it is a store insn,
9408 reject PC in Rn. */
b99bd4ef 9409
c19d1205
ZW		 9410static void
9411encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9412{
5be8be5d 9413 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW		 9414
9415 constraint (!inst.operands[i].isreg,
53365c0d 9416 _("Instruction does not support =N addresses"));
b99bd4ef 9417
c19d1205
ZW		 9418 inst.instruction |= inst.operands[i].reg << 16;
9419 if (inst.operands[i].immisreg)
b99bd4ef 9420 {
5be8be5d 9421 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW		 9422 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9423 constraint (inst.operands[i].negative,
9424 _("Thumb does not support negative register indexing"));
9425 constraint (inst.operands[i].postind,
9426 _("Thumb does not support register post-indexing"));
9427 constraint (inst.operands[i].writeback,
9428 _("Thumb does not support register indexing with writeback"));
9429 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9430 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 9431
f40d1643 9432 inst.instruction |= inst.operands[i].imm;
c19d1205 9433 if (inst.operands[i].shifted)
b99bd4ef 9434 {
c19d1205
ZW		 9435 constraint (inst.reloc.exp.X_op != O_constant,
9436 _("expression too complex"));
9c3c69f2
PB		 9437 constraint (inst.reloc.exp.X_add_number < 0
9438 || inst.reloc.exp.X_add_number > 3,
c19d1205 9439 _("shift out of range"));
9c3c69f2 9440 inst.instruction |= inst.reloc.exp.X_add_number << 4;
c19d1205
ZW		 9441 }
9442 inst.reloc.type = BFD_RELOC_UNUSED;
9443 }
9444 else if (inst.operands[i].preind)
9445 {
5be8be5d 9446 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 9447 constraint (is_t && inst.operands[i].writeback,
c19d1205 9448 _("cannot use writeback with this instruction"));
4755303e
WN		 9449 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
9450 BAD_PC_ADDRESSING);
c19d1205
ZW		 9451
9452 if (is_d)
9453 {
9454 inst.instruction |= 0x01000000;
9455 if (inst.operands[i].writeback)
9456 inst.instruction |= 0x00200000;
b99bd4ef 9457 }
c19d1205 9458 else
b99bd4ef 9459 {
c19d1205
ZW		 9460 inst.instruction |= 0x00000c00;
9461 if (inst.operands[i].writeback)
9462 inst.instruction |= 0x00000100;
b99bd4ef 9463 }
c19d1205 9464 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 9465 }
c19d1205 9466 else if (inst.operands[i].postind)
b99bd4ef 9467 {
9c2799c2 9468 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 9469 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
9470 constraint (is_t, _("cannot use post-indexing with this instruction"));
9471
9472 if (is_d)
9473 inst.instruction |= 0x00200000;
9474 else
9475 inst.instruction |= 0x00000900;
9476 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
9477 }
9478 else /* unindexed - only for coprocessor */
9479 inst.error = _("instruction does not accept unindexed addressing");
9480}
9481
9482/* Table of Thumb instructions which exist in both 16- and 32-bit
9483 encodings (the latter only in post-V6T2 cores). The index is the
9484 value used in the insns table below. When there is more than one
9485 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB		 9486 holds variant (1).
9487 Also contains several pseudo-instructions used during relaxation. */
c19d1205 9488#define T16_32_TAB \
21d799b5
NC		 9489 X(_adc, 4140, eb400000), \
9490 X(_adcs, 4140, eb500000), \
9491 X(_add, 1c00, eb000000), \
9492 X(_adds, 1c00, eb100000), \
9493 X(_addi, 0000, f1000000), \
9494 X(_addis, 0000, f1100000), \
9495 X(_add_pc,000f, f20f0000), \
9496 X(_add_sp,000d, f10d0000), \
9497 X(_adr, 000f, f20f0000), \
9498 X(_and, 4000, ea000000), \
9499 X(_ands, 4000, ea100000), \
9500 X(_asr, 1000, fa40f000), \
9501 X(_asrs, 1000, fa50f000), \
9502 X(_b, e000, f000b000), \
9503 X(_bcond, d000, f0008000), \
9504 X(_bic, 4380, ea200000), \
9505 X(_bics, 4380, ea300000), \
9506 X(_cmn, 42c0, eb100f00), \
9507 X(_cmp, 2800, ebb00f00), \
9508 X(_cpsie, b660, f3af8400), \
9509 X(_cpsid, b670, f3af8600), \
9510 X(_cpy, 4600, ea4f0000), \
9511 X(_dec_sp,80dd, f1ad0d00), \
9512 X(_eor, 4040, ea800000), \
9513 X(_eors, 4040, ea900000), \
9514 X(_inc_sp,00dd, f10d0d00), \
9515 X(_ldmia, c800, e8900000), \
9516 X(_ldr, 6800, f8500000), \
9517 X(_ldrb, 7800, f8100000), \
9518 X(_ldrh, 8800, f8300000), \
9519 X(_ldrsb, 5600, f9100000), \
9520 X(_ldrsh, 5e00, f9300000), \
9521 X(_ldr_pc,4800, f85f0000), \
9522 X(_ldr_pc2,4800, f85f0000), \
9523 X(_ldr_sp,9800, f85d0000), \
9524 X(_lsl, 0000, fa00f000), \
9525 X(_lsls, 0000, fa10f000), \
9526 X(_lsr, 0800, fa20f000), \
9527 X(_lsrs, 0800, fa30f000), \
9528 X(_mov, 2000, ea4f0000), \
9529 X(_movs, 2000, ea5f0000), \
9530 X(_mul, 4340, fb00f000), \
9531 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9532 X(_mvn, 43c0, ea6f0000), \
9533 X(_mvns, 43c0, ea7f0000), \
9534 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9535 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9536 X(_orr, 4300, ea400000), \
9537 X(_orrs, 4300, ea500000), \
9538 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9539 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9540 X(_rev, ba00, fa90f080), \
9541 X(_rev16, ba40, fa90f090), \
9542 X(_revsh, bac0, fa90f0b0), \
9543 X(_ror, 41c0, fa60f000), \
9544 X(_rors, 41c0, fa70f000), \
9545 X(_sbc, 4180, eb600000), \
9546 X(_sbcs, 4180, eb700000), \
9547 X(_stmia, c000, e8800000), \
9548 X(_str, 6000, f8400000), \
9549 X(_strb, 7000, f8000000), \
9550 X(_strh, 8000, f8200000), \
9551 X(_str_sp,9000, f84d0000), \
9552 X(_sub, 1e00, eba00000), \
9553 X(_subs, 1e00, ebb00000), \
9554 X(_subi, 8000, f1a00000), \
9555 X(_subis, 8000, f1b00000), \
9556 X(_sxtb, b240, fa4ff080), \
9557 X(_sxth, b200, fa0ff080), \
9558 X(_tst, 4200, ea100f00), \
9559 X(_uxtb, b2c0, fa5ff080), \
9560 X(_uxth, b280, fa1ff080), \
9561 X(_nop, bf00, f3af8000), \
9562 X(_yield, bf10, f3af8001), \
9563 X(_wfe, bf20, f3af8002), \
9564 X(_wfi, bf30, f3af8003), \
53c4b28b
MGD		 9565 X(_sev, bf40, f3af8004), \
9566 X(_sevl, bf50, f3af8005)
c19d1205
ZW		 9567
9568/* To catch errors in encoding functions, the codes are all offset by
9569 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9570 as 16-bit instructions. */
21d799b5 9571#define X(a,b,c) T_MNEM##a
c19d1205
ZW		 9572enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
9573#undef X
9574
9575#define X(a,b,c) 0x##b
9576static const unsigned short thumb_op16[] = { T16_32_TAB };
9577#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9578#undef X
9579
9580#define X(a,b,c) 0x##c
9581static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC		 9582#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9583#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW		 9584#undef X
9585#undef T16_32_TAB
9586
9587/* Thumb instruction encoders, in alphabetical order. */
9588
92e90b6e 9589/* ADDW or SUBW. */
c921be7d 9590
92e90b6e
PB		 9591static void
9592do_t_add_sub_w (void)
9593{
9594 int Rd, Rn;
9595
9596 Rd = inst.operands[0].reg;
9597 Rn = inst.operands[1].reg;
9598
539d4391
NC		 9599 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9600 is the SP-{plus,minus}-immediate form of the instruction. */
9601 if (Rn == REG_SP)
9602 constraint (Rd == REG_PC, BAD_PC);
9603 else
9604 reject_bad_reg (Rd);
fdfde340 9605
92e90b6e
PB		 9606 inst.instruction |= (Rn << 16) | (Rd << 8);
9607 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9608}
9609
c19d1205
ZW		 9610/* Parse an add or subtract instruction. We get here with inst.instruction
9611 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9612
9613static void
9614do_t_add_sub (void)
9615{
9616 int Rd, Rs, Rn;
9617
9618 Rd = inst.operands[0].reg;
9619 Rs = (inst.operands[1].present
9620 ? inst.operands[1].reg /* Rd, Rs, foo */
9621 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9622
e07e6e58
NC		 9623 if (Rd == REG_PC)
9624 set_it_insn_type_last ();
9625
c19d1205
ZW		 9626 if (unified_syntax)
9627 {
0110f2b8
PB		 9628 bfd_boolean flags;
9629 bfd_boolean narrow;
9630 int opcode;
9631
9632 flags = (inst.instruction == T_MNEM_adds
9633 || inst.instruction == T_MNEM_subs);
9634 if (flags)
e07e6e58 9635 narrow = !in_it_block ();
0110f2b8 9636 else
e07e6e58 9637 narrow = in_it_block ();
c19d1205 9638 if (!inst.operands[2].isreg)
b99bd4ef 9639 {
16805f35
PB		 9640 int add;
9641
fdfde340
JM		 9642 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9643
16805f35
PB		 9644 add = (inst.instruction == T_MNEM_add
9645 || inst.instruction == T_MNEM_adds);
0110f2b8
PB		 9646 opcode = 0;
9647 if (inst.size_req != 4)
9648 {
0110f2b8 9649 /* Attempt to use a narrow opcode, with relaxation if
477330fc 9650 appropriate. */
0110f2b8
PB		 9651 if (Rd == REG_SP && Rs == REG_SP && !flags)
9652 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
9653 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
9654 opcode = T_MNEM_add_sp;
9655 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
9656 opcode = T_MNEM_add_pc;
9657 else if (Rd <= 7 && Rs <= 7 && narrow)
9658 {
9659 if (flags)
9660 opcode = add ? T_MNEM_addis : T_MNEM_subis;
9661 else
9662 opcode = add ? T_MNEM_addi : T_MNEM_subi;
9663 }
9664 if (opcode)
9665 {
9666 inst.instruction = THUMB_OP16(opcode);
9667 inst.instruction |= (Rd << 4) | Rs;
9668 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9669 if (inst.size_req != 2)
9670 inst.relax = opcode;
9671 }
9672 else
9673 constraint (inst.size_req == 2, BAD_HIREG);
9674 }
9675 if (inst.size_req == 4
9676 || (inst.size_req != 2 && !opcode))
9677 {
efd81785
PB		 9678 if (Rd == REG_PC)
9679 {
fdfde340 9680 constraint (add, BAD_PC);
efd81785
PB		 9681 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
9682 _("only SUBS PC, LR, #const allowed"));
9683 constraint (inst.reloc.exp.X_op != O_constant,
9684 _("expression too complex"));
9685 constraint (inst.reloc.exp.X_add_number < 0
9686 || inst.reloc.exp.X_add_number > 0xff,
9687 _("immediate value out of range"));
9688 inst.instruction = T2_SUBS_PC_LR
9689 | inst.reloc.exp.X_add_number;
9690 inst.reloc.type = BFD_RELOC_UNUSED;
9691 return;
9692 }
9693 else if (Rs == REG_PC)
16805f35
PB		 9694 {
9695 /* Always use addw/subw. */
9696 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
9697 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
9698 }
9699 else
9700 {
9701 inst.instruction = THUMB_OP32 (inst.instruction);
9702 inst.instruction = (inst.instruction & 0xe1ffffff)
9703 | 0x10000000;
9704 if (flags)
9705 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9706 else
9707 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
9708 }
dc4503c6
PB		 9709 inst.instruction |= Rd << 8;
9710 inst.instruction |= Rs << 16;
0110f2b8 9711 }
b99bd4ef 9712 }
c19d1205
ZW		 9713 else
9714 {
5f4cb198
NC		 9715 unsigned int value = inst.reloc.exp.X_add_number;
9716 unsigned int shift = inst.operands[2].shift_kind;
9717
c19d1205
ZW		 9718 Rn = inst.operands[2].reg;
9719 /* See if we can do this with a 16-bit instruction. */
9720 if (!inst.operands[2].shifted && inst.size_req != 4)
9721 {
e27ec89e
PB		 9722 if (Rd > 7 || Rs > 7 || Rn > 7)
9723 narrow = FALSE;
9724
9725 if (narrow)
c19d1205 9726 {
e27ec89e
PB		 9727 inst.instruction = ((inst.instruction == T_MNEM_adds
9728 || inst.instruction == T_MNEM_add)
c19d1205
ZW		 9729 ? T_OPCODE_ADD_R3
9730 : T_OPCODE_SUB_R3);
9731 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
9732 return;
9733 }
b99bd4ef 9734
7e806470 9735 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 9736 {
7e806470
PB		 9737 /* Thumb-1 cores (except v6-M) require at least one high
9738 register in a narrow non flag setting add. */
9739 if (Rd > 7 || Rn > 7
9740 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
9741 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 9742 {
7e806470
PB		 9743 if (Rd == Rn)
9744 {
9745 Rn = Rs;
9746 Rs = Rd;
9747 }
c19d1205
ZW		 9748 inst.instruction = T_OPCODE_ADD_HI;
9749 inst.instruction |= (Rd & 8) << 4;
9750 inst.instruction |= (Rd & 7);
9751 inst.instruction |= Rn << 3;
9752 return;
9753 }
c19d1205
ZW		 9754 }
9755 }
c921be7d 9756
fdfde340
JM		 9757 constraint (Rd == REG_PC, BAD_PC);
9758 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
9759 constraint (Rs == REG_PC, BAD_PC);
9760 reject_bad_reg (Rn);
9761
c19d1205
ZW		 9762 /* If we get here, it can't be done in 16 bits. */
9763 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
9764 _("shift must be constant"));
9765 inst.instruction = THUMB_OP32 (inst.instruction);
9766 inst.instruction |= Rd << 8;
9767 inst.instruction |= Rs << 16;
5f4cb198
NC		 9768 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
9769 _("shift value over 3 not allowed in thumb mode"));
9770 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
9771 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW		 9772 encode_thumb32_shifted_operand (2);
9773 }
9774 }
9775 else
9776 {
9777 constraint (inst.instruction == T_MNEM_adds
9778 || inst.instruction == T_MNEM_subs,
9779 BAD_THUMB32);
b99bd4ef 9780
c19d1205 9781 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 9782 {
c19d1205
ZW		 9783 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
9784 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
9785 BAD_HIREG);
9786
9787 inst.instruction = (inst.instruction == T_MNEM_add
9788 ? 0x0000 : 0x8000);
9789 inst.instruction |= (Rd << 4) | Rs;
9790 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC		 9791 return;
9792 }
9793
c19d1205
ZW		 9794 Rn = inst.operands[2].reg;
9795 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 9796
c19d1205
ZW		 9797 /* We now have Rd, Rs, and Rn set to registers. */
9798 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 9799 {
c19d1205
ZW		 9800 /* Can't do this for SUB. */
9801 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
9802 inst.instruction = T_OPCODE_ADD_HI;
9803 inst.instruction |= (Rd & 8) << 4;
9804 inst.instruction |= (Rd & 7);
9805 if (Rs == Rd)
9806 inst.instruction |= Rn << 3;
9807 else if (Rn == Rd)
9808 inst.instruction |= Rs << 3;
9809 else
9810 constraint (1, _("dest must overlap one source register"));
9811 }
9812 else
9813 {
9814 inst.instruction = (inst.instruction == T_MNEM_add
9815 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
9816 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 9817 }
b99bd4ef 9818 }
b99bd4ef
NC		 9819}
9820
c19d1205
ZW		 9821static void
9822do_t_adr (void)
9823{
fdfde340
JM		 9824 unsigned Rd;
9825
9826 Rd = inst.operands[0].reg;
9827 reject_bad_reg (Rd);
9828
9829 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB		 9830 {
9831 /* Defer to section relaxation. */
9832 inst.relax = inst.instruction;
9833 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 9834 inst.instruction |= Rd << 4;
0110f2b8
PB		 9835 }
9836 else if (unified_syntax && inst.size_req != 2)
e9f89963 9837 {
0110f2b8 9838 /* Generate a 32-bit opcode. */
e9f89963 9839 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 9840 inst.instruction |= Rd << 8;
e9f89963
PB		 9841 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
9842 inst.reloc.pc_rel = 1;
9843 }
9844 else
9845 {
0110f2b8 9846 /* Generate a 16-bit opcode. */
e9f89963
PB		 9847 inst.instruction = THUMB_OP16 (inst.instruction);
9848 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
9849 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
9850 inst.reloc.pc_rel = 1;
b99bd4ef 9851
fdfde340 9852 inst.instruction |= Rd << 4;
e9f89963 9853 }
c19d1205 9854}
b99bd4ef 9855
c19d1205
ZW		 9856/* Arithmetic instructions for which there is just one 16-bit
9857 instruction encoding, and it allows only two low registers.
9858 For maximal compatibility with ARM syntax, we allow three register
9859 operands even when Thumb-32 instructions are not available, as long
9860 as the first two are identical. For instance, both "sbc r0,r1" and
9861 "sbc r0,r0,r1" are allowed. */
b99bd4ef 9862static void
c19d1205 9863do_t_arit3 (void)
b99bd4ef 9864{
c19d1205 9865 int Rd, Rs, Rn;
b99bd4ef 9866
c19d1205
ZW		 9867 Rd = inst.operands[0].reg;
9868 Rs = (inst.operands[1].present
9869 ? inst.operands[1].reg /* Rd, Rs, foo */
9870 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9871 Rn = inst.operands[2].reg;
b99bd4ef 9872
fdfde340
JM		 9873 reject_bad_reg (Rd);
9874 reject_bad_reg (Rs);
9875 if (inst.operands[2].isreg)
9876 reject_bad_reg (Rn);
9877
c19d1205 9878 if (unified_syntax)
b99bd4ef 9879 {
c19d1205
ZW		 9880 if (!inst.operands[2].isreg)
9881 {
9882 /* For an immediate, we always generate a 32-bit opcode;
9883 section relaxation will shrink it later if possible. */
9884 inst.instruction = THUMB_OP32 (inst.instruction);
9885 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9886 inst.instruction |= Rd << 8;
9887 inst.instruction |= Rs << 16;
9888 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
9889 }
9890 else
9891 {
e27ec89e
PB		 9892 bfd_boolean narrow;
9893
c19d1205 9894 /* See if we can do this with a 16-bit instruction. */
e27ec89e 9895 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 9896 narrow = !in_it_block ();
e27ec89e 9897 else
e07e6e58 9898 narrow = in_it_block ();
e27ec89e
PB		 9899
9900 if (Rd > 7 || Rn > 7 || Rs > 7)
9901 narrow = FALSE;
9902 if (inst.operands[2].shifted)
9903 narrow = FALSE;
9904 if (inst.size_req == 4)
9905 narrow = FALSE;
9906
9907 if (narrow
c19d1205
ZW		 9908 && Rd == Rs)
9909 {
9910 inst.instruction = THUMB_OP16 (inst.instruction);
9911 inst.instruction |= Rd;
9912 inst.instruction |= Rn << 3;
9913 return;
9914 }
b99bd4ef 9915
c19d1205
ZW		 9916 /* If we get here, it can't be done in 16 bits. */
9917 constraint (inst.operands[2].shifted
9918 && inst.operands[2].immisreg,
9919 _("shift must be constant"));
9920 inst.instruction = THUMB_OP32 (inst.instruction);
9921 inst.instruction |= Rd << 8;
9922 inst.instruction |= Rs << 16;
9923 encode_thumb32_shifted_operand (2);
9924 }
a737bd4d 9925 }
c19d1205 9926 else
b99bd4ef 9927 {
c19d1205
ZW		 9928 /* On its face this is a lie - the instruction does set the
9929 flags. However, the only supported mnemonic in this mode
9930 says it doesn't. */
9931 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 9932
c19d1205
ZW		 9933 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
9934 _("unshifted register required"));
9935 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
9936 constraint (Rd != Rs,
9937 _("dest and source1 must be the same register"));
a737bd4d 9938
c19d1205
ZW		 9939 inst.instruction = THUMB_OP16 (inst.instruction);
9940 inst.instruction |= Rd;
9941 inst.instruction |= Rn << 3;
b99bd4ef 9942 }
a737bd4d 9943}
b99bd4ef 9944
c19d1205
ZW		 9945/* Similarly, but for instructions where the arithmetic operation is
9946 commutative, so we can allow either of them to be different from
9947 the destination operand in a 16-bit instruction. For instance, all
9948 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9949 accepted. */
9950static void
9951do_t_arit3c (void)
a737bd4d 9952{
c19d1205 9953 int Rd, Rs, Rn;
b99bd4ef 9954
c19d1205
ZW		 9955 Rd = inst.operands[0].reg;
9956 Rs = (inst.operands[1].present
9957 ? inst.operands[1].reg /* Rd, Rs, foo */
9958 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
9959 Rn = inst.operands[2].reg;
c921be7d 9960
fdfde340
JM		 9961 reject_bad_reg (Rd);
9962 reject_bad_reg (Rs);
9963 if (inst.operands[2].isreg)
9964 reject_bad_reg (Rn);
a737bd4d 9965
c19d1205 9966 if (unified_syntax)
a737bd4d 9967 {
c19d1205 9968 if (!inst.operands[2].isreg)
b99bd4ef 9969 {
c19d1205
ZW		 9970 /* For an immediate, we always generate a 32-bit opcode;
9971 section relaxation will shrink it later if possible. */
9972 inst.instruction = THUMB_OP32 (inst.instruction);
9973 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
9974 inst.instruction |= Rd << 8;
9975 inst.instruction |= Rs << 16;
9976 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 9977 }
c19d1205 9978 else
a737bd4d 9979 {
e27ec89e
PB		 9980 bfd_boolean narrow;
9981
c19d1205 9982 /* See if we can do this with a 16-bit instruction. */
e27ec89e 9983 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 9984 narrow = !in_it_block ();
e27ec89e 9985 else
e07e6e58 9986 narrow = in_it_block ();
e27ec89e
PB		 9987
9988 if (Rd > 7 || Rn > 7 || Rs > 7)
9989 narrow = FALSE;
9990 if (inst.operands[2].shifted)
9991 narrow = FALSE;
9992 if (inst.size_req == 4)
9993 narrow = FALSE;
9994
9995 if (narrow)
a737bd4d 9996 {
c19d1205 9997 if (Rd == Rs)
a737bd4d 9998 {
c19d1205
ZW		 9999 inst.instruction = THUMB_OP16 (inst.instruction);
10000 inst.instruction |= Rd;
10001 inst.instruction |= Rn << 3;
10002 return;
a737bd4d 10003 }
c19d1205 10004 if (Rd == Rn)
a737bd4d 10005 {
c19d1205
ZW		 10006 inst.instruction = THUMB_OP16 (inst.instruction);
10007 inst.instruction |= Rd;
10008 inst.instruction |= Rs << 3;
10009 return;
a737bd4d
NC		 10010 }
10011 }
c19d1205
ZW		 10012
10013 /* If we get here, it can't be done in 16 bits. */
10014 constraint (inst.operands[2].shifted
10015 && inst.operands[2].immisreg,
10016 _("shift must be constant"));
10017 inst.instruction = THUMB_OP32 (inst.instruction);
10018 inst.instruction |= Rd << 8;
10019 inst.instruction |= Rs << 16;
10020 encode_thumb32_shifted_operand (2);
a737bd4d 10021 }
b99bd4ef 10022 }
c19d1205
ZW		 10023 else
10024 {
10025 /* On its face this is a lie - the instruction does set the
10026 flags. However, the only supported mnemonic in this mode
10027 says it doesn't. */
10028 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 10029
c19d1205
ZW		 10030 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10031 _("unshifted register required"));
10032 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10033
10034 inst.instruction = THUMB_OP16 (inst.instruction);
10035 inst.instruction |= Rd;
10036
10037 if (Rd == Rs)
10038 inst.instruction |= Rn << 3;
10039 else if (Rd == Rn)
10040 inst.instruction |= Rs << 3;
10041 else
10042 constraint (1, _("dest must overlap one source register"));
10043 }
a737bd4d
NC		 10044}
10045
c19d1205
ZW		 10046static void
10047do_t_bfc (void)
a737bd4d 10048{
fdfde340 10049 unsigned Rd;
c19d1205
ZW		 10050 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10051 constraint (msb > 32, _("bit-field extends past end of register"));
10052 /* The instruction encoding stores the LSB and MSB,
10053 not the LSB and width. */
fdfde340
JM		 10054 Rd = inst.operands[0].reg;
10055 reject_bad_reg (Rd);
10056 inst.instruction |= Rd << 8;
c19d1205
ZW		 10057 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10058 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10059 inst.instruction |= msb - 1;
b99bd4ef
NC		 10060}
10061
c19d1205
ZW		 10062static void
10063do_t_bfi (void)
b99bd4ef 10064{
fdfde340 10065 int Rd, Rn;
c19d1205 10066 unsigned int msb;
b99bd4ef 10067
fdfde340
JM		 10068 Rd = inst.operands[0].reg;
10069 reject_bad_reg (Rd);
10070
c19d1205
ZW		 10071 /* #0 in second position is alternative syntax for bfc, which is
10072 the same instruction but with REG_PC in the Rm field. */
10073 if (!inst.operands[1].isreg)
fdfde340
JM		 10074 Rn = REG_PC;
10075 else
10076 {
10077 Rn = inst.operands[1].reg;
10078 reject_bad_reg (Rn);
10079 }
b99bd4ef 10080
c19d1205
ZW		 10081 msb = inst.operands[2].imm + inst.operands[3].imm;
10082 constraint (msb > 32, _("bit-field extends past end of register"));
10083 /* The instruction encoding stores the LSB and MSB,
10084 not the LSB and width. */
fdfde340
JM		 10085 inst.instruction |= Rd << 8;
10086 inst.instruction |= Rn << 16;
c19d1205
ZW		 10087 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10088 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10089 inst.instruction |= msb - 1;
b99bd4ef
NC		 10090}
10091
c19d1205
ZW		 10092static void
10093do_t_bfx (void)
b99bd4ef 10094{
fdfde340
JM		 10095 unsigned Rd, Rn;
10096
10097 Rd = inst.operands[0].reg;
10098 Rn = inst.operands[1].reg;
10099
10100 reject_bad_reg (Rd);
10101 reject_bad_reg (Rn);
10102
c19d1205
ZW		 10103 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10104 _("bit-field extends past end of register"));
fdfde340
JM		 10105 inst.instruction |= Rd << 8;
10106 inst.instruction |= Rn << 16;
c19d1205
ZW		 10107 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10108 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10109 inst.instruction |= inst.operands[3].imm - 1;
10110}
b99bd4ef 10111
c19d1205
ZW		 10112/* ARM V5 Thumb BLX (argument parse)
10113 BLX <target_addr> which is BLX(1)
10114 BLX <Rm> which is BLX(2)
10115 Unfortunately, there are two different opcodes for this mnemonic.
10116 So, the insns[].value is not used, and the code here zaps values
10117 into inst.instruction.
b99bd4ef 10118
c19d1205
ZW		 10119 ??? How to take advantage of the additional two bits of displacement
10120 available in Thumb32 mode? Need new relocation? */
b99bd4ef 10121
c19d1205
ZW		 10122static void
10123do_t_blx (void)
10124{
e07e6e58
NC		 10125 set_it_insn_type_last ();
10126
c19d1205 10127 if (inst.operands[0].isreg)
fdfde340
JM		 10128 {
10129 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10130 /* We have a register, so this is BLX(2). */
10131 inst.instruction |= inst.operands[0].reg << 3;
10132 }
b99bd4ef
NC		 10133 else
10134 {
c19d1205 10135 /* No register. This must be BLX(1). */
2fc8bdac 10136 inst.instruction = 0xf000e800;
0855e32b 10137 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC		 10138 }
10139}
10140
c19d1205
ZW		 10141static void
10142do_t_branch (void)
b99bd4ef 10143{
0110f2b8 10144 int opcode;
dfa9f0d5 10145 int cond;
9ae92b05 10146 int reloc;
dfa9f0d5 10147
e07e6e58
NC		 10148 cond = inst.cond;
10149 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10150
10151 if (in_it_block ())
dfa9f0d5
PB		 10152 {
10153 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 10154 branches. */
dfa9f0d5 10155 cond = COND_ALWAYS;
dfa9f0d5
PB		 10156 }
10157 else
10158 cond = inst.cond;
10159
10160 if (cond != COND_ALWAYS)
0110f2b8
PB		 10161 opcode = T_MNEM_bcond;
10162 else
10163 opcode = inst.instruction;
10164
12d6b0b7
RS		 10165 if (unified_syntax
10166 && (inst.size_req == 4
10960bfb
PB		 10167 || (inst.size_req != 2
10168 && (inst.operands[0].hasreloc
10169 || inst.reloc.exp.X_op == O_constant))))
c19d1205 10170 {
0110f2b8 10171 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 10172 if (cond == COND_ALWAYS)
9ae92b05 10173 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW		 10174 else
10175 {
9c2799c2 10176 gas_assert (cond != 0xF);
dfa9f0d5 10177 inst.instruction |= cond << 22;
9ae92b05 10178 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW		 10179 }
10180 }
b99bd4ef
NC		 10181 else
10182 {
0110f2b8 10183 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 10184 if (cond == COND_ALWAYS)
9ae92b05 10185 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 10186 else
b99bd4ef 10187 {
dfa9f0d5 10188 inst.instruction |= cond << 8;
9ae92b05 10189 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 10190 }
0110f2b8
PB		 10191 /* Allow section relaxation. */
10192 if (unified_syntax && inst.size_req != 2)
10193 inst.relax = opcode;
b99bd4ef 10194 }
9ae92b05 10195 inst.reloc.type = reloc;
c19d1205 10196 inst.reloc.pc_rel = 1;
b99bd4ef
NC		 10197}
10198
8884b720 10199/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 10200 between the two is the maximum immediate allowed - which is passed in
8884b720 10201 RANGE. */
b99bd4ef 10202static void
8884b720 10203do_t_bkpt_hlt1 (int range)
b99bd4ef 10204{
dfa9f0d5
PB		 10205 constraint (inst.cond != COND_ALWAYS,
10206 _("instruction is always unconditional"));
c19d1205 10207 if (inst.operands[0].present)
b99bd4ef 10208 {
8884b720 10209 constraint (inst.operands[0].imm > range,
c19d1205
ZW		 10210 _("immediate value out of range"));
10211 inst.instruction |= inst.operands[0].imm;
b99bd4ef 10212 }
8884b720
MGD		 10213
10214 set_it_insn_type (NEUTRAL_IT_INSN);
10215}
10216
10217static void
10218do_t_hlt (void)
10219{
10220 do_t_bkpt_hlt1 (63);
10221}
10222
10223static void
10224do_t_bkpt (void)
10225{
10226 do_t_bkpt_hlt1 (255);
b99bd4ef
NC		 10227}
10228
10229static void
c19d1205 10230do_t_branch23 (void)
b99bd4ef 10231{
e07e6e58 10232 set_it_insn_type_last ();
0855e32b 10233 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 10234
0855e32b
NS		 10235 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10236 this file. We used to simply ignore the PLT reloc type here --
10237 the branch encoding is now needed to deal with TLSCALL relocs.
10238 So if we see a PLT reloc now, put it back to how it used to be to
10239 keep the preexisting behaviour. */
10240 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10241 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 10242
4343666d 10243#if defined(OBJ_COFF)
c19d1205
ZW		 10244 /* If the destination of the branch is a defined symbol which does not have
10245 the THUMB_FUNC attribute, then we must be calling a function which has
10246 the (interfacearm) attribute. We look for the Thumb entry point to that
10247 function and change the branch to refer to that function instead. */
10248 if ( inst.reloc.exp.X_op == O_symbol
10249 && inst.reloc.exp.X_add_symbol != NULL
10250 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10251 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10252 inst.reloc.exp.X_add_symbol =
10253 find_real_start (inst.reloc.exp.X_add_symbol);
4343666d 10254#endif
90e4755a
RE		 10255}
10256
10257static void
c19d1205 10258do_t_bx (void)
90e4755a 10259{
e07e6e58 10260 set_it_insn_type_last ();
c19d1205
ZW		 10261 inst.instruction |= inst.operands[0].reg << 3;
10262 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10263 should cause the alignment to be checked once it is known. This is
10264 because BX PC only works if the instruction is word aligned. */
10265}
90e4755a 10266
c19d1205
ZW		 10267static void
10268do_t_bxj (void)
10269{
fdfde340 10270 int Rm;
90e4755a 10271
e07e6e58 10272 set_it_insn_type_last ();
fdfde340
JM		 10273 Rm = inst.operands[0].reg;
10274 reject_bad_reg (Rm);
10275 inst.instruction |= Rm << 16;
90e4755a
RE		 10276}
10277
10278static void
c19d1205 10279do_t_clz (void)
90e4755a 10280{
fdfde340
JM		 10281 unsigned Rd;
10282 unsigned Rm;
10283
10284 Rd = inst.operands[0].reg;
10285 Rm = inst.operands[1].reg;
10286
10287 reject_bad_reg (Rd);
10288 reject_bad_reg (Rm);
10289
10290 inst.instruction |= Rd << 8;
10291 inst.instruction |= Rm << 16;
10292 inst.instruction |= Rm;
c19d1205 10293}
90e4755a 10294
dfa9f0d5
PB		 10295static void
10296do_t_cps (void)
10297{
e07e6e58 10298 set_it_insn_type (OUTSIDE_IT_INSN);
dfa9f0d5
PB		 10299 inst.instruction |= inst.operands[0].imm;
10300}
10301
c19d1205
ZW		 10302static void
10303do_t_cpsi (void)
10304{
e07e6e58 10305 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205 10306 if (unified_syntax
62b3e311
PB		 10307 && (inst.operands[1].present || inst.size_req == 4)
10308 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 10309 {
c19d1205
ZW		 10310 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10311 inst.instruction = 0xf3af8000;
10312 inst.instruction |= imod << 9;
10313 inst.instruction |= inst.operands[0].imm << 5;
10314 if (inst.operands[1].present)
10315 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 10316 }
c19d1205 10317 else
90e4755a 10318 {
62b3e311
PB		 10319 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10320 && (inst.operands[0].imm & 4),
10321 _("selected processor does not support 'A' form "
10322 "of this instruction"));
10323 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW		 10324 _("Thumb does not support the 2-argument "
10325 "form of this instruction"));
10326 inst.instruction |= inst.operands[0].imm;
90e4755a 10327 }
90e4755a
RE		 10328}
10329
c19d1205
ZW		 10330/* THUMB CPY instruction (argument parse). */
10331
90e4755a 10332static void
c19d1205 10333do_t_cpy (void)
90e4755a 10334{
c19d1205 10335 if (inst.size_req == 4)
90e4755a 10336 {
c19d1205
ZW		 10337 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10338 inst.instruction |= inst.operands[0].reg << 8;
10339 inst.instruction |= inst.operands[1].reg;
90e4755a 10340 }
c19d1205 10341 else
90e4755a 10342 {
c19d1205
ZW		 10343 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10344 inst.instruction |= (inst.operands[0].reg & 0x7);
10345 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 10346 }
90e4755a
RE		 10347}
10348
90e4755a 10349static void
25fe350b 10350do_t_cbz (void)
90e4755a 10351{
e07e6e58 10352 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW		 10353 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10354 inst.instruction |= inst.operands[0].reg;
10355 inst.reloc.pc_rel = 1;
10356 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10357}
90e4755a 10358
62b3e311
PB		 10359static void
10360do_t_dbg (void)
10361{
10362 inst.instruction |= inst.operands[0].imm;
10363}
10364
10365static void
10366do_t_div (void)
10367{
fdfde340
JM		 10368 unsigned Rd, Rn, Rm;
10369
10370 Rd = inst.operands[0].reg;
10371 Rn = (inst.operands[1].present
10372 ? inst.operands[1].reg : Rd);
10373 Rm = inst.operands[2].reg;
10374
10375 reject_bad_reg (Rd);
10376 reject_bad_reg (Rn);
10377 reject_bad_reg (Rm);
10378
10379 inst.instruction |= Rd << 8;
10380 inst.instruction |= Rn << 16;
10381 inst.instruction |= Rm;
62b3e311
PB		 10382}
10383
c19d1205
ZW		 10384static void
10385do_t_hint (void)
10386{
10387 if (unified_syntax && inst.size_req == 4)
10388 inst.instruction = THUMB_OP32 (inst.instruction);
10389 else
10390 inst.instruction = THUMB_OP16 (inst.instruction);
10391}
90e4755a 10392
c19d1205
ZW		 10393static void
10394do_t_it (void)
10395{
10396 unsigned int cond = inst.operands[0].imm;
e27ec89e 10397
e07e6e58
NC		 10398 set_it_insn_type (IT_INSN);
10399 now_it.mask = (inst.instruction & 0xf) | 0x10;
10400 now_it.cc = cond;
5a01bb1d 10401 now_it.warn_deprecated = FALSE;
e27ec89e
PB		 10402
10403 /* If the condition is a negative condition, invert the mask. */
c19d1205 10404 if ((cond & 0x1) == 0x0)
90e4755a 10405 {
c19d1205 10406 unsigned int mask = inst.instruction & 0x000f;
90e4755a 10407
c19d1205 10408 if ((mask & 0x7) == 0)
5a01bb1d
MGD		 10409 {
10410 /* No conversion needed. */
10411 now_it.block_length = 1;
10412 }
c19d1205 10413 else if ((mask & 0x3) == 0)
5a01bb1d
MGD		 10414 {
10415 mask ^= 0x8;
10416 now_it.block_length = 2;
10417 }
e27ec89e 10418 else if ((mask & 0x1) == 0)
5a01bb1d
MGD		 10419 {
10420 mask ^= 0xC;
10421 now_it.block_length = 3;
10422 }
c19d1205 10423 else
5a01bb1d
MGD		 10424 {
10425 mask ^= 0xE;
10426 now_it.block_length = 4;
10427 }
90e4755a 10428
e27ec89e
PB		 10429 inst.instruction &= 0xfff0;
10430 inst.instruction |= mask;
c19d1205 10431 }
90e4755a 10432
c19d1205
ZW		 10433 inst.instruction |= cond << 4;
10434}
90e4755a 10435
3c707909
PB		 10436/* Helper function used for both push/pop and ldm/stm. */
10437static void
10438encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
10439{
10440 bfd_boolean load;
10441
10442 load = (inst.instruction & (1 << 20)) != 0;
10443
10444 if (mask & (1 << 13))
10445 inst.error = _("SP not allowed in register list");
1e5b0379
NC		 10446
10447 if ((mask & (1 << base)) != 0
10448 && writeback)
10449 inst.error = _("having the base register in the register list when "
10450 "using write back is UNPREDICTABLE");
10451
3c707909
PB		 10452 if (load)
10453 {
e07e6e58 10454 if (mask & (1 << 15))
477330fc
RM		 10455 {
10456 if (mask & (1 << 14))
10457 inst.error = _("LR and PC should not both be in register list");
10458 else
10459 set_it_insn_type_last ();
10460 }
3c707909
PB		 10461 }
10462 else
10463 {
10464 if (mask & (1 << 15))
10465 inst.error = _("PC not allowed in register list");
3c707909
PB		 10466 }
10467
10468 if ((mask & (mask - 1)) == 0)
10469 {
10470 /* Single register transfers implemented as str/ldr. */
10471 if (writeback)
10472 {
10473 if (inst.instruction & (1 << 23))
10474 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
10475 else
10476 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
10477 }
10478 else
10479 {
10480 if (inst.instruction & (1 << 23))
10481 inst.instruction = 0x00800000; /* ia -> [base] */
10482 else
10483 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
10484 }
10485
10486 inst.instruction |= 0xf8400000;
10487 if (load)
10488 inst.instruction |= 0x00100000;
10489
5f4273c7 10490 mask = ffs (mask) - 1;
3c707909
PB		 10491 mask <<= 12;
10492 }
10493 else if (writeback)
10494 inst.instruction |= WRITE_BACK;
10495
10496 inst.instruction |= mask;
10497 inst.instruction |= base << 16;
10498}
10499
c19d1205
ZW		 10500static void
10501do_t_ldmstm (void)
10502{
10503 /* This really doesn't seem worth it. */
10504 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
10505 _("expression too complex"));
10506 constraint (inst.operands[1].writeback,
10507 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 10508
c19d1205
ZW		 10509 if (unified_syntax)
10510 {
3c707909
PB		 10511 bfd_boolean narrow;
10512 unsigned mask;
10513
10514 narrow = FALSE;
c19d1205
ZW		 10515 /* See if we can use a 16-bit instruction. */
10516 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
10517 && inst.size_req != 4
3c707909 10518 && !(inst.operands[1].imm & ~0xff))
90e4755a 10519 {
3c707909 10520 mask = 1 << inst.operands[0].reg;
90e4755a 10521
eab4f823 10522 if (inst.operands[0].reg <= 7)
90e4755a 10523 {
3c707909 10524 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD		 10525 ? inst.operands[0].writeback
10526 : (inst.operands[0].writeback
10527 == !(inst.operands[1].imm & mask)))
477330fc 10528 {
eab4f823
MGD		 10529 if (inst.instruction == T_MNEM_stmia
10530 && (inst.operands[1].imm & mask)
10531 && (inst.operands[1].imm & (mask - 1)))
10532 as_warn (_("value stored for r%d is UNKNOWN"),
10533 inst.operands[0].reg);
3c707909 10534
eab4f823
MGD		 10535 inst.instruction = THUMB_OP16 (inst.instruction);
10536 inst.instruction |= inst.operands[0].reg << 8;
10537 inst.instruction |= inst.operands[1].imm;
10538 narrow = TRUE;
10539 }
10540 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10541 {
10542 /* This means 1 register in reg list one of 3 situations:
10543 1. Instruction is stmia, but without writeback.
10544 2. lmdia without writeback, but with Rn not in
477330fc 10545 reglist.
eab4f823
MGD		 10546 3. ldmia with writeback, but with Rn in reglist.
10547 Case 3 is UNPREDICTABLE behaviour, so we handle
10548 case 1 and 2 which can be converted into a 16-bit
10549 str or ldr. The SP cases are handled below. */
10550 unsigned long opcode;
10551 /* First, record an error for Case 3. */
10552 if (inst.operands[1].imm & mask
10553 && inst.operands[0].writeback)
fa94de6b 10554 inst.error =
eab4f823
MGD		 10555 _("having the base register in the register list when "
10556 "using write back is UNPREDICTABLE");
fa94de6b
RM		 10557
10558 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD		 10559 : T_MNEM_ldr);
10560 inst.instruction = THUMB_OP16 (opcode);
10561 inst.instruction |= inst.operands[0].reg << 3;
10562 inst.instruction |= (ffs (inst.operands[1].imm)-1);
10563 narrow = TRUE;
10564 }
90e4755a 10565 }
eab4f823 10566 else if (inst.operands[0] .reg == REG_SP)
90e4755a 10567 {
eab4f823
MGD		 10568 if (inst.operands[0].writeback)
10569 {
fa94de6b 10570 inst.instruction =
eab4f823 10571 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 10572 ? T_MNEM_push : T_MNEM_pop);
eab4f823 10573 inst.instruction |= inst.operands[1].imm;
477330fc 10574 narrow = TRUE;
eab4f823
MGD		 10575 }
10576 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
10577 {
fa94de6b 10578 inst.instruction =
eab4f823 10579 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 10580 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 10581 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 10582 narrow = TRUE;
eab4f823 10583 }
90e4755a 10584 }
3c707909
PB		 10585 }
10586
10587 if (!narrow)
10588 {
c19d1205
ZW		 10589 if (inst.instruction < 0xffff)
10590 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 10591
5f4273c7
NC		 10592 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
10593 inst.operands[0].writeback);
90e4755a
RE		 10594 }
10595 }
c19d1205 10596 else
90e4755a 10597 {
c19d1205
ZW		 10598 constraint (inst.operands[0].reg > 7
10599 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB		 10600 constraint (inst.instruction != T_MNEM_ldmia
10601 && inst.instruction != T_MNEM_stmia,
10602 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 10603 if (inst.instruction == T_MNEM_stmia)
f03698e6 10604 {
c19d1205
ZW		 10605 if (!inst.operands[0].writeback)
10606 as_warn (_("this instruction will write back the base register"));
10607 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
10608 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 10609 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 10610 inst.operands[0].reg);
f03698e6 10611 }
c19d1205 10612 else
90e4755a 10613 {
c19d1205
ZW		 10614 if (!inst.operands[0].writeback
10615 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
10616 as_warn (_("this instruction will write back the base register"));
10617 else if (inst.operands[0].writeback
10618 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
10619 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE		 10620 }
10621
c19d1205
ZW		 10622 inst.instruction = THUMB_OP16 (inst.instruction);
10623 inst.instruction |= inst.operands[0].reg << 8;
10624 inst.instruction |= inst.operands[1].imm;
10625 }
10626}
e28cd48c 10627
c19d1205
ZW		 10628static void
10629do_t_ldrex (void)
10630{
10631 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
10632 || inst.operands[1].postind || inst.operands[1].writeback
10633 || inst.operands[1].immisreg || inst.operands[1].shifted
10634 || inst.operands[1].negative,
01cfc07f 10635 BAD_ADDR_MODE);
e28cd48c 10636
5be8be5d
DG		 10637 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
10638
c19d1205
ZW		 10639 inst.instruction |= inst.operands[0].reg << 12;
10640 inst.instruction |= inst.operands[1].reg << 16;
10641 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
10642}
e28cd48c 10643
c19d1205
ZW		 10644static void
10645do_t_ldrexd (void)
10646{
10647 if (!inst.operands[1].present)
1cac9012 10648 {
c19d1205
ZW		 10649 constraint (inst.operands[0].reg == REG_LR,
10650 _("r14 not allowed as first register "
10651 "when second register is omitted"));
10652 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 10653 }
c19d1205
ZW		 10654 constraint (inst.operands[0].reg == inst.operands[1].reg,
10655 BAD_OVERLAP);
b99bd4ef 10656
c19d1205
ZW		 10657 inst.instruction |= inst.operands[0].reg << 12;
10658 inst.instruction |= inst.operands[1].reg << 8;
10659 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 10660}
10661
10662static void
c19d1205 10663do_t_ldst (void)
b99bd4ef 10664{
0110f2b8
PB		 10665 unsigned long opcode;
10666 int Rn;
10667
e07e6e58
NC		 10668 if (inst.operands[0].isreg
10669 && !inst.operands[0].preind
10670 && inst.operands[0].reg == REG_PC)
10671 set_it_insn_type_last ();
10672
0110f2b8 10673 opcode = inst.instruction;
c19d1205 10674 if (unified_syntax)
b99bd4ef 10675 {
53365c0d
PB		 10676 if (!inst.operands[1].isreg)
10677 {
10678 if (opcode <= 0xffff)
10679 inst.instruction = THUMB_OP32 (opcode);
10680 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10681 return;
10682 }
0110f2b8
PB		 10683 if (inst.operands[1].isreg
10684 && !inst.operands[1].writeback
c19d1205
ZW		 10685 && !inst.operands[1].shifted && !inst.operands[1].postind
10686 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB		 10687 && opcode <= 0xffff
10688 && inst.size_req != 4)
c19d1205 10689 {
0110f2b8
PB		 10690 /* Insn may have a 16-bit form. */
10691 Rn = inst.operands[1].reg;
10692 if (inst.operands[1].immisreg)
10693 {
10694 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 10695 /* [Rn, Rik] */
0110f2b8
PB		 10696 if (Rn <= 7 && inst.operands[1].imm <= 7)
10697 goto op16;
5be8be5d
DG		 10698 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
10699 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB		 10700 }
10701 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
10702 && opcode != T_MNEM_ldrsb)
10703 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
10704 || (Rn == REG_SP && opcode == T_MNEM_str))
10705 {
10706 /* [Rn, #const] */
10707 if (Rn > 7)
10708 {
10709 if (Rn == REG_PC)
10710 {
10711 if (inst.reloc.pc_rel)
10712 opcode = T_MNEM_ldr_pc2;
10713 else
10714 opcode = T_MNEM_ldr_pc;
10715 }
10716 else
10717 {
10718 if (opcode == T_MNEM_ldr)
10719 opcode = T_MNEM_ldr_sp;
10720 else
10721 opcode = T_MNEM_str_sp;
10722 }
10723 inst.instruction = inst.operands[0].reg << 8;
10724 }
10725 else
10726 {
10727 inst.instruction = inst.operands[0].reg;
10728 inst.instruction |= inst.operands[1].reg << 3;
10729 }
10730 inst.instruction |= THUMB_OP16 (opcode);
10731 if (inst.size_req == 2)
10732 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10733 else
10734 inst.relax = opcode;
10735 return;
10736 }
c19d1205 10737 }
0110f2b8 10738 /* Definitely a 32-bit variant. */
5be8be5d 10739
8d67f500
NC		 10740 /* Warning for Erratum 752419. */
10741 if (opcode == T_MNEM_ldr
10742 && inst.operands[0].reg == REG_SP
10743 && inst.operands[1].writeback == 1
10744 && !inst.operands[1].immisreg)
10745 {
10746 if (no_cpu_selected ()
10747 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM		 10748 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
10749 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC		 10750 as_warn (_("This instruction may be unpredictable "
10751 "if executed on M-profile cores "
10752 "with interrupts enabled."));
10753 }
10754
5be8be5d 10755 /* Do some validations regarding addressing modes. */
1be5fd2e 10756 if (inst.operands[1].immisreg)
5be8be5d
DG		 10757 reject_bad_reg (inst.operands[1].imm);
10758
1be5fd2e
NC		 10759 constraint (inst.operands[1].writeback == 1
10760 && inst.operands[0].reg == inst.operands[1].reg,
10761 BAD_OVERLAP);
10762
0110f2b8 10763 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW		 10764 inst.instruction |= inst.operands[0].reg << 12;
10765 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 10766 check_ldr_r15_aligned ();
b99bd4ef
NC		 10767 return;
10768 }
10769
c19d1205
ZW		 10770 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10771
10772 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 10773 {
c19d1205
ZW		 10774 /* Only [Rn,Rm] is acceptable. */
10775 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
10776 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
10777 || inst.operands[1].postind || inst.operands[1].shifted
10778 || inst.operands[1].negative,
10779 _("Thumb does not support this addressing mode"));
10780 inst.instruction = THUMB_OP16 (inst.instruction);
10781 goto op16;
b99bd4ef 10782 }
5f4273c7 10783
c19d1205
ZW		 10784 inst.instruction = THUMB_OP16 (inst.instruction);
10785 if (!inst.operands[1].isreg)
10786 if (move_or_literal_pool (0, /*thumb_p=*/TRUE, /*mode_3=*/FALSE))
10787 return;
b99bd4ef 10788
c19d1205
ZW		 10789 constraint (!inst.operands[1].preind
10790 || inst.operands[1].shifted
10791 || inst.operands[1].writeback,
10792 _("Thumb does not support this addressing mode"));
10793 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 10794 {
c19d1205
ZW		 10795 constraint (inst.instruction & 0x0600,
10796 _("byte or halfword not valid for base register"));
10797 constraint (inst.operands[1].reg == REG_PC
10798 && !(inst.instruction & THUMB_LOAD_BIT),
10799 _("r15 based store not allowed"));
10800 constraint (inst.operands[1].immisreg,
10801 _("invalid base register for register offset"));
b99bd4ef 10802
c19d1205
ZW		 10803 if (inst.operands[1].reg == REG_PC)
10804 inst.instruction = T_OPCODE_LDR_PC;
10805 else if (inst.instruction & THUMB_LOAD_BIT)
10806 inst.instruction = T_OPCODE_LDR_SP;
10807 else
10808 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 10809
c19d1205
ZW		 10810 inst.instruction |= inst.operands[0].reg << 8;
10811 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10812 return;
10813 }
90e4755a 10814
c19d1205
ZW		 10815 constraint (inst.operands[1].reg > 7, BAD_HIREG);
10816 if (!inst.operands[1].immisreg)
10817 {
10818 /* Immediate offset. */
10819 inst.instruction |= inst.operands[0].reg;
10820 inst.instruction |= inst.operands[1].reg << 3;
10821 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
10822 return;
10823 }
90e4755a 10824
c19d1205
ZW		 10825 /* Register offset. */
10826 constraint (inst.operands[1].imm > 7, BAD_HIREG);
10827 constraint (inst.operands[1].negative,
10828 _("Thumb does not support this addressing mode"));
90e4755a 10829
c19d1205
ZW		 10830 op16:
10831 switch (inst.instruction)
10832 {
10833 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
10834 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
10835 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
10836 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
10837 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
10838 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
10839 case 0x5600 /* ldrsb */:
10840 case 0x5e00 /* ldrsh */: break;
10841 default: abort ();
10842 }
90e4755a 10843
c19d1205
ZW		 10844 inst.instruction |= inst.operands[0].reg;
10845 inst.instruction |= inst.operands[1].reg << 3;
10846 inst.instruction |= inst.operands[1].imm << 6;
10847}
90e4755a 10848
c19d1205
ZW		 10849static void
10850do_t_ldstd (void)
10851{
10852 if (!inst.operands[1].present)
b99bd4ef 10853 {
c19d1205
ZW		 10854 inst.operands[1].reg = inst.operands[0].reg + 1;
10855 constraint (inst.operands[0].reg == REG_LR,
10856 _("r14 not allowed here"));
bd340a04 10857 constraint (inst.operands[0].reg == REG_R12,
477330fc 10858 _("r12 not allowed here"));
b99bd4ef 10859 }
bd340a04
MGD		 10860
10861 if (inst.operands[2].writeback
10862 && (inst.operands[0].reg == inst.operands[2].reg
10863 || inst.operands[1].reg == inst.operands[2].reg))
10864 as_warn (_("base register written back, and overlaps "
477330fc 10865 "one of transfer registers"));
bd340a04 10866
c19d1205
ZW		 10867 inst.instruction |= inst.operands[0].reg << 12;
10868 inst.instruction |= inst.operands[1].reg << 8;
10869 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC		 10870}
10871
c19d1205
ZW		 10872static void
10873do_t_ldstt (void)
10874{
10875 inst.instruction |= inst.operands[0].reg << 12;
10876 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
10877}
a737bd4d 10878
b99bd4ef 10879static void
c19d1205 10880do_t_mla (void)
b99bd4ef 10881{
fdfde340 10882 unsigned Rd, Rn, Rm, Ra;
c921be7d 10883
fdfde340
JM		 10884 Rd = inst.operands[0].reg;
10885 Rn = inst.operands[1].reg;
10886 Rm = inst.operands[2].reg;
10887 Ra = inst.operands[3].reg;
10888
10889 reject_bad_reg (Rd);
10890 reject_bad_reg (Rn);
10891 reject_bad_reg (Rm);
10892 reject_bad_reg (Ra);
10893
10894 inst.instruction |= Rd << 8;
10895 inst.instruction |= Rn << 16;
10896 inst.instruction |= Rm;
10897 inst.instruction |= Ra << 12;
c19d1205 10898}
b99bd4ef 10899
c19d1205
ZW		 10900static void
10901do_t_mlal (void)
10902{
fdfde340
JM		 10903 unsigned RdLo, RdHi, Rn, Rm;
10904
10905 RdLo = inst.operands[0].reg;
10906 RdHi = inst.operands[1].reg;
10907 Rn = inst.operands[2].reg;
10908 Rm = inst.operands[3].reg;
10909
10910 reject_bad_reg (RdLo);
10911 reject_bad_reg (RdHi);
10912 reject_bad_reg (Rn);
10913 reject_bad_reg (Rm);
10914
10915 inst.instruction |= RdLo << 12;
10916 inst.instruction |= RdHi << 8;
10917 inst.instruction |= Rn << 16;
10918 inst.instruction |= Rm;
c19d1205 10919}
b99bd4ef 10920
c19d1205
ZW		 10921static void
10922do_t_mov_cmp (void)
10923{
fdfde340
JM		 10924 unsigned Rn, Rm;
10925
10926 Rn = inst.operands[0].reg;
10927 Rm = inst.operands[1].reg;
10928
e07e6e58
NC		 10929 if (Rn == REG_PC)
10930 set_it_insn_type_last ();
10931
c19d1205 10932 if (unified_syntax)
b99bd4ef 10933 {
c19d1205
ZW		 10934 int r0off = (inst.instruction == T_MNEM_mov
10935 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 10936 unsigned long opcode;
3d388997
PB		 10937 bfd_boolean narrow;
10938 bfd_boolean low_regs;
10939
fdfde340 10940 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 10941 opcode = inst.instruction;
e07e6e58 10942 if (in_it_block ())
0110f2b8 10943 narrow = opcode != T_MNEM_movs;
3d388997 10944 else
0110f2b8 10945 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB		 10946 if (inst.size_req == 4
10947 || inst.operands[1].shifted)
10948 narrow = FALSE;
10949
efd81785
PB		 10950 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10951 if (opcode == T_MNEM_movs && inst.operands[1].isreg
10952 && !inst.operands[1].shifted
fdfde340
JM		 10953 && Rn == REG_PC
10954 && Rm == REG_LR)
efd81785
PB		 10955 {
10956 inst.instruction = T2_SUBS_PC_LR;
10957 return;
10958 }
10959
fdfde340
JM		 10960 if (opcode == T_MNEM_cmp)
10961 {
10962 constraint (Rn == REG_PC, BAD_PC);
94206790
MM		 10963 if (narrow)
10964 {
10965 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10966 but valid. */
10967 warn_deprecated_sp (Rm);
10968 /* R15 was documented as a valid choice for Rm in ARMv6,
10969 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10970 tools reject R15, so we do too. */
10971 constraint (Rm == REG_PC, BAD_PC);
10972 }
10973 else
10974 reject_bad_reg (Rm);
fdfde340
JM		 10975 }
10976 else if (opcode == T_MNEM_mov
10977 || opcode == T_MNEM_movs)
10978 {
10979 if (inst.operands[1].isreg)
10980 {
10981 if (opcode == T_MNEM_movs)
10982 {
10983 reject_bad_reg (Rn);
10984 reject_bad_reg (Rm);
10985 }
76fa04a4
MGD		 10986 else if (narrow)
10987 {
10988 /* This is mov.n. */
10989 if ((Rn == REG_SP || Rn == REG_PC)
10990 && (Rm == REG_SP || Rm == REG_PC))
10991 {
10992 as_warn (_("Use of r%u as a source register is "
10993 "deprecated when r%u is the destination "
10994 "register."), Rm, Rn);
10995 }
10996 }
10997 else
10998 {
10999 /* This is mov.w. */
11000 constraint (Rn == REG_PC, BAD_PC);
11001 constraint (Rm == REG_PC, BAD_PC);
11002 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11003 }
fdfde340
JM		 11004 }
11005 else
11006 reject_bad_reg (Rn);
11007 }
11008
c19d1205
ZW		 11009 if (!inst.operands[1].isreg)
11010 {
0110f2b8 11011 /* Immediate operand. */
e07e6e58 11012 if (!in_it_block () && opcode == T_MNEM_mov)
0110f2b8
PB		 11013 narrow = 0;
11014 if (low_regs && narrow)
11015 {
11016 inst.instruction = THUMB_OP16 (opcode);
fdfde340 11017 inst.instruction |= Rn << 8;
0110f2b8
PB		 11018 if (inst.size_req == 2)
11019 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11020 else
11021 inst.relax = opcode;
11022 }
11023 else
11024 {
11025 inst.instruction = THUMB_OP32 (inst.instruction);
11026 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 11027 inst.instruction |= Rn << r0off;
0110f2b8
PB		 11028 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11029 }
c19d1205 11030 }
728ca7c9
PB		 11031 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11032 && (inst.instruction == T_MNEM_mov
11033 || inst.instruction == T_MNEM_movs))
11034 {
11035 /* Register shifts are encoded as separate shift instructions. */
11036 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11037
e07e6e58 11038 if (in_it_block ())
728ca7c9
PB		 11039 narrow = !flags;
11040 else
11041 narrow = flags;
11042
11043 if (inst.size_req == 4)
11044 narrow = FALSE;
11045
11046 if (!low_regs || inst.operands[1].imm > 7)
11047 narrow = FALSE;
11048
fdfde340 11049 if (Rn != Rm)
728ca7c9
PB		 11050 narrow = FALSE;
11051
11052 switch (inst.operands[1].shift_kind)
11053 {
11054 case SHIFT_LSL:
11055 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11056 break;
11057 case SHIFT_ASR:
11058 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11059 break;
11060 case SHIFT_LSR:
11061 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11062 break;
11063 case SHIFT_ROR:
11064 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11065 break;
11066 default:
5f4273c7 11067 abort ();
728ca7c9
PB		 11068 }
11069
11070 inst.instruction = opcode;
11071 if (narrow)
11072 {
fdfde340 11073 inst.instruction |= Rn;
728ca7c9
PB		 11074 inst.instruction |= inst.operands[1].imm << 3;
11075 }
11076 else
11077 {
11078 if (flags)
11079 inst.instruction |= CONDS_BIT;
11080
fdfde340
JM		 11081 inst.instruction |= Rn << 8;
11082 inst.instruction |= Rm << 16;
728ca7c9
PB		 11083 inst.instruction |= inst.operands[1].imm;
11084 }
11085 }
3d388997 11086 else if (!narrow)
c19d1205 11087 {
728ca7c9
PB		 11088 /* Some mov with immediate shift have narrow variants.
11089 Register shifts are handled above. */
11090 if (low_regs && inst.operands[1].shifted
11091 && (inst.instruction == T_MNEM_mov
11092 || inst.instruction == T_MNEM_movs))
11093 {
e07e6e58 11094 if (in_it_block ())
728ca7c9
PB		 11095 narrow = (inst.instruction == T_MNEM_mov);
11096 else
11097 narrow = (inst.instruction == T_MNEM_movs);
11098 }
11099
11100 if (narrow)
11101 {
11102 switch (inst.operands[1].shift_kind)
11103 {
11104 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11105 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11106 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11107 default: narrow = FALSE; break;
11108 }
11109 }
11110
11111 if (narrow)
11112 {
fdfde340
JM		 11113 inst.instruction |= Rn;
11114 inst.instruction |= Rm << 3;
728ca7c9
PB		 11115 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11116 }
11117 else
11118 {
11119 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11120 inst.instruction |= Rn << r0off;
728ca7c9
PB		 11121 encode_thumb32_shifted_operand (1);
11122 }
c19d1205
ZW		 11123 }
11124 else
11125 switch (inst.instruction)
11126 {
11127 case T_MNEM_mov:
837b3435 11128 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD		 11129 results. Don't allow this. */
11130 if (low_regs)
11131 {
11132 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11133 "MOV Rd, Rs with two low registers is not "
11134 "permitted on this architecture");
fa94de6b 11135 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD		 11136 arm_ext_v6);
11137 }
11138
c19d1205 11139 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM		 11140 inst.instruction |= (Rn & 0x8) << 4;
11141 inst.instruction |= (Rn & 0x7);
11142 inst.instruction |= Rm << 3;
c19d1205 11143 break;
b99bd4ef 11144
c19d1205
ZW		 11145 case T_MNEM_movs:
11146 /* We know we have low registers at this point.
941a8a52
MGD		 11147 Generate LSLS Rd, Rs, #0. */
11148 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM		 11149 inst.instruction |= Rn;
11150 inst.instruction |= Rm << 3;
c19d1205
ZW		 11151 break;
11152
11153 case T_MNEM_cmp:
3d388997 11154 if (low_regs)
c19d1205
ZW		 11155 {
11156 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM		 11157 inst.instruction |= Rn;
11158 inst.instruction |= Rm << 3;
c19d1205
ZW		 11159 }
11160 else
11161 {
11162 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM		 11163 inst.instruction |= (Rn & 0x8) << 4;
11164 inst.instruction |= (Rn & 0x7);
11165 inst.instruction |= Rm << 3;
c19d1205
ZW		 11166 }
11167 break;
11168 }
b99bd4ef
NC		 11169 return;
11170 }
11171
c19d1205 11172 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC		 11173
11174 /* PR 10443: Do not silently ignore shifted operands. */
11175 constraint (inst.operands[1].shifted,
11176 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11177
c19d1205 11178 if (inst.operands[1].isreg)
b99bd4ef 11179 {
fdfde340 11180 if (Rn < 8 && Rm < 8)
b99bd4ef 11181 {
c19d1205
ZW		 11182 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11183 since a MOV instruction produces unpredictable results. */
11184 if (inst.instruction == T_OPCODE_MOV_I8)
11185 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 11186 else
c19d1205 11187 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 11188
fdfde340
JM		 11189 inst.instruction |= Rn;
11190 inst.instruction |= Rm << 3;
b99bd4ef
NC		 11191 }
11192 else
11193 {
c19d1205
ZW		 11194 if (inst.instruction == T_OPCODE_MOV_I8)
11195 inst.instruction = T_OPCODE_MOV_HR;
11196 else
11197 inst.instruction = T_OPCODE_CMP_HR;
11198 do_t_cpy ();
b99bd4ef
NC		 11199 }
11200 }
c19d1205 11201 else
b99bd4ef 11202 {
fdfde340 11203 constraint (Rn > 7,
c19d1205 11204 _("only lo regs allowed with immediate"));
fdfde340 11205 inst.instruction |= Rn << 8;
c19d1205
ZW		 11206 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11207 }
11208}
b99bd4ef 11209
c19d1205
ZW		 11210static void
11211do_t_mov16 (void)
11212{
fdfde340 11213 unsigned Rd;
b6895b4f
PB		 11214 bfd_vma imm;
11215 bfd_boolean top;
11216
11217 top = (inst.instruction & 0x00800000) != 0;
11218 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11219 {
11220 constraint (top, _(":lower16: not allowed this instruction"));
11221 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11222 }
11223 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11224 {
11225 constraint (!top, _(":upper16: not allowed this instruction"));
11226 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11227 }
11228
fdfde340
JM		 11229 Rd = inst.operands[0].reg;
11230 reject_bad_reg (Rd);
11231
11232 inst.instruction |= Rd << 8;
b6895b4f
PB		 11233 if (inst.reloc.type == BFD_RELOC_UNUSED)
11234 {
11235 imm = inst.reloc.exp.X_add_number;
11236 inst.instruction |= (imm & 0xf000) << 4;
11237 inst.instruction |= (imm & 0x0800) << 15;
11238 inst.instruction |= (imm & 0x0700) << 4;
11239 inst.instruction |= (imm & 0x00ff);
11240 }
c19d1205 11241}
b99bd4ef 11242
c19d1205
ZW		 11243static void
11244do_t_mvn_tst (void)
11245{
fdfde340 11246 unsigned Rn, Rm;
c921be7d 11247
fdfde340
JM		 11248 Rn = inst.operands[0].reg;
11249 Rm = inst.operands[1].reg;
11250
11251 if (inst.instruction == T_MNEM_cmp
11252 || inst.instruction == T_MNEM_cmn)
11253 constraint (Rn == REG_PC, BAD_PC);
11254 else
11255 reject_bad_reg (Rn);
11256 reject_bad_reg (Rm);
11257
c19d1205
ZW		 11258 if (unified_syntax)
11259 {
11260 int r0off = (inst.instruction == T_MNEM_mvn
11261 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB		 11262 bfd_boolean narrow;
11263
11264 if (inst.size_req == 4
11265 || inst.instruction > 0xffff
11266 || inst.operands[1].shifted
fdfde340 11267 || Rn > 7 || Rm > 7)
3d388997
PB		 11268 narrow = FALSE;
11269 else if (inst.instruction == T_MNEM_cmn)
11270 narrow = TRUE;
11271 else if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 11272 narrow = !in_it_block ();
3d388997 11273 else
e07e6e58 11274 narrow = in_it_block ();
3d388997 11275
c19d1205 11276 if (!inst.operands[1].isreg)
b99bd4ef 11277 {
c19d1205
ZW		 11278 /* For an immediate, we always generate a 32-bit opcode;
11279 section relaxation will shrink it later if possible. */
11280 if (inst.instruction < 0xffff)
11281 inst.instruction = THUMB_OP32 (inst.instruction);
11282 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 11283 inst.instruction |= Rn << r0off;
c19d1205 11284 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11285 }
c19d1205 11286 else
b99bd4ef 11287 {
c19d1205 11288 /* See if we can do this with a 16-bit instruction. */
3d388997 11289 if (narrow)
b99bd4ef 11290 {
c19d1205 11291 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11292 inst.instruction |= Rn;
11293 inst.instruction |= Rm << 3;
b99bd4ef 11294 }
c19d1205 11295 else
b99bd4ef 11296 {
c19d1205
ZW		 11297 constraint (inst.operands[1].shifted
11298 && inst.operands[1].immisreg,
11299 _("shift must be constant"));
11300 if (inst.instruction < 0xffff)
11301 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11302 inst.instruction |= Rn << r0off;
c19d1205 11303 encode_thumb32_shifted_operand (1);
b99bd4ef 11304 }
b99bd4ef
NC		 11305 }
11306 }
11307 else
11308 {
c19d1205
ZW		 11309 constraint (inst.instruction > 0xffff
11310 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11311 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11312 _("unshifted register required"));
fdfde340 11313 constraint (Rn > 7 || Rm > 7,
c19d1205 11314 BAD_HIREG);
b99bd4ef 11315
c19d1205 11316 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11317 inst.instruction |= Rn;
11318 inst.instruction |= Rm << 3;
b99bd4ef 11319 }
b99bd4ef
NC		 11320}
11321
b05fe5cf 11322static void
c19d1205 11323do_t_mrs (void)
b05fe5cf 11324{
fdfde340 11325 unsigned Rd;
037e8744
JB		 11326
11327 if (do_vfp_nsyn_mrs () == SUCCESS)
11328 return;
11329
90ec0d68
MGD		 11330 Rd = inst.operands[0].reg;
11331 reject_bad_reg (Rd);
11332 inst.instruction |= Rd << 8;
11333
11334 if (inst.operands[1].isreg)
62b3e311 11335 {
90ec0d68
MGD		 11336 unsigned br = inst.operands[1].reg;
11337 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11338 as_bad (_("bad register for mrs"));
11339
11340 inst.instruction |= br & (0xf << 16);
11341 inst.instruction |= (br & 0x300) >> 4;
11342 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB		 11343 }
11344 else
11345 {
90ec0d68 11346 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 11347
d2cd1205 11348 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC		 11349 {
11350 /* PR gas/12698: The constraint is only applied for m_profile.
11351 If the user has specified -march=all, we want to ignore it as
11352 we are building for any CPU type, including non-m variants. */
11353 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11354 constraint ((flags != 0) && m_profile, _("selected processor does "
11355 "not support requested special purpose register"));
11356 }
90ec0d68 11357 else
d2cd1205
JB		 11358 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11359 devices). */
11360 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11361 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 11362
90ec0d68
MGD		 11363 inst.instruction |= (flags & SPSR_BIT) >> 2;
11364 inst.instruction |= inst.operands[1].imm & 0xff;
11365 inst.instruction |= 0xf0000;
11366 }
c19d1205 11367}
b05fe5cf 11368
c19d1205
ZW		 11369static void
11370do_t_msr (void)
11371{
62b3e311 11372 int flags;
fdfde340 11373 unsigned Rn;
62b3e311 11374
037e8744
JB		 11375 if (do_vfp_nsyn_msr () == SUCCESS)
11376 return;
11377
c19d1205
ZW		 11378 constraint (!inst.operands[1].isreg,
11379 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD		 11380
11381 if (inst.operands[0].isreg)
11382 flags = (int)(inst.operands[0].reg);
11383 else
11384 flags = inst.operands[0].imm;
11385
d2cd1205 11386 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 11387 {
d2cd1205
JB		 11388 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11389
1a43faaf 11390 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM		 11391 If the user has specified -march=all, we want to ignore it as
11392 we are building for any CPU type, including non-m variants. */
1a43faaf
NC		 11393 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11394 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM		 11395 && (bits & ~(PSR_s | PSR_f)) != 0)
11396 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11397 && bits != PSR_f)) && m_profile,
11398 _("selected processor does not support requested special "
11399 "purpose register"));
62b3e311
PB		 11400 }
11401 else
d2cd1205
JB		 11402 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11403 "requested special purpose register"));
c921be7d 11404
fdfde340
JM		 11405 Rn = inst.operands[1].reg;
11406 reject_bad_reg (Rn);
11407
62b3e311 11408 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD		 11409 inst.instruction |= (flags & 0xf0000) >> 8;
11410 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 11411 inst.instruction |= (flags & 0xff);
fdfde340 11412 inst.instruction |= Rn << 16;
c19d1205 11413}
b05fe5cf 11414
c19d1205
ZW		 11415static void
11416do_t_mul (void)
11417{
17828f45 11418 bfd_boolean narrow;
fdfde340 11419 unsigned Rd, Rn, Rm;
17828f45 11420
c19d1205
ZW		 11421 if (!inst.operands[2].present)
11422 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 11423
fdfde340
JM		 11424 Rd = inst.operands[0].reg;
11425 Rn = inst.operands[1].reg;
11426 Rm = inst.operands[2].reg;
11427
17828f45 11428 if (unified_syntax)
b05fe5cf 11429 {
17828f45 11430 if (inst.size_req == 4
fdfde340
JM		 11431 || (Rd != Rn
11432 && Rd != Rm)
11433 || Rn > 7
11434 || Rm > 7)
17828f45
JM		 11435 narrow = FALSE;
11436 else if (inst.instruction == T_MNEM_muls)
e07e6e58 11437 narrow = !in_it_block ();
17828f45 11438 else
e07e6e58 11439 narrow = in_it_block ();
b05fe5cf 11440 }
c19d1205 11441 else
b05fe5cf 11442 {
17828f45 11443 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 11444 constraint (Rn > 7 || Rm > 7,
c19d1205 11445 BAD_HIREG);
17828f45
JM		 11446 narrow = TRUE;
11447 }
b05fe5cf 11448
17828f45
JM		 11449 if (narrow)
11450 {
11451 /* 16-bit MULS/Conditional MUL. */
c19d1205 11452 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 11453 inst.instruction |= Rd;
b05fe5cf 11454
fdfde340
JM		 11455 if (Rd == Rn)
11456 inst.instruction |= Rm << 3;
11457 else if (Rd == Rm)
11458 inst.instruction |= Rn << 3;
c19d1205
ZW		 11459 else
11460 constraint (1, _("dest must overlap one source register"));
11461 }
17828f45
JM		 11462 else
11463 {
e07e6e58
NC		 11464 constraint (inst.instruction != T_MNEM_mul,
11465 _("Thumb-2 MUL must not set flags"));
17828f45
JM		 11466 /* 32-bit MUL. */
11467 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 11468 inst.instruction |= Rd << 8;
11469 inst.instruction |= Rn << 16;
11470 inst.instruction |= Rm << 0;
11471
11472 reject_bad_reg (Rd);
11473 reject_bad_reg (Rn);
11474 reject_bad_reg (Rm);
17828f45 11475 }
c19d1205 11476}
b05fe5cf 11477
c19d1205
ZW		 11478static void
11479do_t_mull (void)
11480{
fdfde340 11481 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 11482
fdfde340
JM		 11483 RdLo = inst.operands[0].reg;
11484 RdHi = inst.operands[1].reg;
11485 Rn = inst.operands[2].reg;
11486 Rm = inst.operands[3].reg;
11487
11488 reject_bad_reg (RdLo);
11489 reject_bad_reg (RdHi);
11490 reject_bad_reg (Rn);
11491 reject_bad_reg (Rm);
11492
11493 inst.instruction |= RdLo << 12;
11494 inst.instruction |= RdHi << 8;
11495 inst.instruction |= Rn << 16;
11496 inst.instruction |= Rm;
11497
11498 if (RdLo == RdHi)
c19d1205
ZW		 11499 as_tsktsk (_("rdhi and rdlo must be different"));
11500}
b05fe5cf 11501
c19d1205
ZW		 11502static void
11503do_t_nop (void)
11504{
e07e6e58
NC		 11505 set_it_insn_type (NEUTRAL_IT_INSN);
11506
c19d1205
ZW		 11507 if (unified_syntax)
11508 {
11509 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 11510 {
c19d1205
ZW		 11511 inst.instruction = THUMB_OP32 (inst.instruction);
11512 inst.instruction |= inst.operands[0].imm;
11513 }
11514 else
11515 {
bc2d1808
NC		 11516 /* PR9722: Check for Thumb2 availability before
11517 generating a thumb2 nop instruction. */
afa62d5e 11518 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC		 11519 {
11520 inst.instruction = THUMB_OP16 (inst.instruction);
11521 inst.instruction |= inst.operands[0].imm << 4;
11522 }
11523 else
11524 inst.instruction = 0x46c0;
c19d1205
ZW		 11525 }
11526 }
11527 else
11528 {
11529 constraint (inst.operands[0].present,
11530 _("Thumb does not support NOP with hints"));
11531 inst.instruction = 0x46c0;
11532 }
11533}
b05fe5cf 11534
c19d1205
ZW		 11535static void
11536do_t_neg (void)
11537{
11538 if (unified_syntax)
11539 {
3d388997
PB		 11540 bfd_boolean narrow;
11541
11542 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 11543 narrow = !in_it_block ();
3d388997 11544 else
e07e6e58 11545 narrow = in_it_block ();
3d388997
PB		 11546 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11547 narrow = FALSE;
11548 if (inst.size_req == 4)
11549 narrow = FALSE;
11550
11551 if (!narrow)
c19d1205
ZW		 11552 {
11553 inst.instruction = THUMB_OP32 (inst.instruction);
11554 inst.instruction |= inst.operands[0].reg << 8;
11555 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW		 11556 }
11557 else
11558 {
c19d1205
ZW		 11559 inst.instruction = THUMB_OP16 (inst.instruction);
11560 inst.instruction |= inst.operands[0].reg;
11561 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW		 11562 }
11563 }
11564 else
11565 {
c19d1205
ZW		 11566 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
11567 BAD_HIREG);
11568 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
11569
11570 inst.instruction = THUMB_OP16 (inst.instruction);
11571 inst.instruction |= inst.operands[0].reg;
11572 inst.instruction |= inst.operands[1].reg << 3;
11573 }
11574}
11575
1c444d06
JM		 11576static void
11577do_t_orn (void)
11578{
11579 unsigned Rd, Rn;
11580
11581 Rd = inst.operands[0].reg;
11582 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
11583
fdfde340
JM		 11584 reject_bad_reg (Rd);
11585 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11586 reject_bad_reg (Rn);
11587
1c444d06
JM		 11588 inst.instruction |= Rd << 8;
11589 inst.instruction |= Rn << 16;
11590
11591 if (!inst.operands[2].isreg)
11592 {
11593 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11594 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11595 }
11596 else
11597 {
11598 unsigned Rm;
11599
11600 Rm = inst.operands[2].reg;
fdfde340 11601 reject_bad_reg (Rm);
1c444d06
JM		 11602
11603 constraint (inst.operands[2].shifted
11604 && inst.operands[2].immisreg,
11605 _("shift must be constant"));
11606 encode_thumb32_shifted_operand (2);
11607 }
11608}
11609
c19d1205
ZW		 11610static void
11611do_t_pkhbt (void)
11612{
fdfde340
JM		 11613 unsigned Rd, Rn, Rm;
11614
11615 Rd = inst.operands[0].reg;
11616 Rn = inst.operands[1].reg;
11617 Rm = inst.operands[2].reg;
11618
11619 reject_bad_reg (Rd);
11620 reject_bad_reg (Rn);
11621 reject_bad_reg (Rm);
11622
11623 inst.instruction |= Rd << 8;
11624 inst.instruction |= Rn << 16;
11625 inst.instruction |= Rm;
c19d1205
ZW		 11626 if (inst.operands[3].present)
11627 {
11628 unsigned int val = inst.reloc.exp.X_add_number;
11629 constraint (inst.reloc.exp.X_op != O_constant,
11630 _("expression too complex"));
11631 inst.instruction |= (val & 0x1c) << 10;
11632 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 11633 }
c19d1205 11634}
b05fe5cf 11635
c19d1205
ZW		 11636static void
11637do_t_pkhtb (void)
11638{
11639 if (!inst.operands[3].present)
1ef52f49
NC		 11640 {
11641 unsigned Rtmp;
11642
11643 inst.instruction &= ~0x00000020;
11644
11645 /* PR 10168. Swap the Rm and Rn registers. */
11646 Rtmp = inst.operands[1].reg;
11647 inst.operands[1].reg = inst.operands[2].reg;
11648 inst.operands[2].reg = Rtmp;
11649 }
c19d1205 11650 do_t_pkhbt ();
b05fe5cf
ZW		 11651}
11652
c19d1205
ZW		 11653static void
11654do_t_pld (void)
11655{
fdfde340
JM		 11656 if (inst.operands[0].immisreg)
11657 reject_bad_reg (inst.operands[0].imm);
11658
c19d1205
ZW		 11659 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
11660}
b05fe5cf 11661
c19d1205
ZW		 11662static void
11663do_t_push_pop (void)
b99bd4ef 11664{
e9f89963 11665 unsigned mask;
5f4273c7 11666
c19d1205
ZW		 11667 constraint (inst.operands[0].writeback,
11668 _("push/pop do not support {reglist}^"));
11669 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11670 _("expression too complex"));
b99bd4ef 11671
e9f89963
PB		 11672 mask = inst.operands[0].imm;
11673 if ((mask & ~0xff) == 0)
3c707909 11674 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
c19d1205 11675 else if ((inst.instruction == T_MNEM_push
e9f89963 11676 && (mask & ~0xff) == 1 << REG_LR)
c19d1205 11677 || (inst.instruction == T_MNEM_pop
e9f89963 11678 && (mask & ~0xff) == 1 << REG_PC))
b99bd4ef 11679 {
c19d1205
ZW		 11680 inst.instruction = THUMB_OP16 (inst.instruction);
11681 inst.instruction |= THUMB_PP_PC_LR;
3c707909 11682 inst.instruction |= mask & 0xff;
c19d1205
ZW		 11683 }
11684 else if (unified_syntax)
11685 {
3c707909 11686 inst.instruction = THUMB_OP32 (inst.instruction);
5f4273c7 11687 encode_thumb2_ldmstm (13, mask, TRUE);
c19d1205
ZW		 11688 }
11689 else
11690 {
11691 inst.error = _("invalid register list to push/pop instruction");
11692 return;
11693 }
c19d1205 11694}
b99bd4ef 11695
c19d1205
ZW		 11696static void
11697do_t_rbit (void)
11698{
fdfde340
JM		 11699 unsigned Rd, Rm;
11700
11701 Rd = inst.operands[0].reg;
11702 Rm = inst.operands[1].reg;
11703
11704 reject_bad_reg (Rd);
11705 reject_bad_reg (Rm);
11706
11707 inst.instruction |= Rd << 8;
11708 inst.instruction |= Rm << 16;
11709 inst.instruction |= Rm;
c19d1205 11710}
b99bd4ef 11711
c19d1205
ZW		 11712static void
11713do_t_rev (void)
11714{
fdfde340
JM		 11715 unsigned Rd, Rm;
11716
11717 Rd = inst.operands[0].reg;
11718 Rm = inst.operands[1].reg;
11719
11720 reject_bad_reg (Rd);
11721 reject_bad_reg (Rm);
11722
11723 if (Rd <= 7 && Rm <= 7
c19d1205
ZW		 11724 && inst.size_req != 4)
11725 {
11726 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11727 inst.instruction |= Rd;
11728 inst.instruction |= Rm << 3;
c19d1205
ZW		 11729 }
11730 else if (unified_syntax)
11731 {
11732 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 11733 inst.instruction |= Rd << 8;
11734 inst.instruction |= Rm << 16;
11735 inst.instruction |= Rm;
c19d1205
ZW		 11736 }
11737 else
11738 inst.error = BAD_HIREG;
11739}
b99bd4ef 11740
1c444d06
JM		 11741static void
11742do_t_rrx (void)
11743{
11744 unsigned Rd, Rm;
11745
11746 Rd = inst.operands[0].reg;
11747 Rm = inst.operands[1].reg;
11748
fdfde340
JM		 11749 reject_bad_reg (Rd);
11750 reject_bad_reg (Rm);
c921be7d 11751
1c444d06
JM		 11752 inst.instruction |= Rd << 8;
11753 inst.instruction |= Rm;
11754}
11755
c19d1205
ZW		 11756static void
11757do_t_rsb (void)
11758{
fdfde340 11759 unsigned Rd, Rs;
b99bd4ef 11760
c19d1205
ZW		 11761 Rd = inst.operands[0].reg;
11762 Rs = (inst.operands[1].present
11763 ? inst.operands[1].reg /* Rd, Rs, foo */
11764 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 11765
fdfde340
JM		 11766 reject_bad_reg (Rd);
11767 reject_bad_reg (Rs);
11768 if (inst.operands[2].isreg)
11769 reject_bad_reg (inst.operands[2].reg);
11770
c19d1205
ZW		 11771 inst.instruction |= Rd << 8;
11772 inst.instruction |= Rs << 16;
11773 if (!inst.operands[2].isreg)
11774 {
026d3abb
PB		 11775 bfd_boolean narrow;
11776
11777 if ((inst.instruction & 0x00100000) != 0)
e07e6e58 11778 narrow = !in_it_block ();
026d3abb 11779 else
e07e6e58 11780 narrow = in_it_block ();
026d3abb
PB		 11781
11782 if (Rd > 7 || Rs > 7)
11783 narrow = FALSE;
11784
11785 if (inst.size_req == 4 || !unified_syntax)
11786 narrow = FALSE;
11787
11788 if (inst.reloc.exp.X_op != O_constant
11789 || inst.reloc.exp.X_add_number != 0)
11790 narrow = FALSE;
11791
11792 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 11793 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB		 11794 if (narrow)
11795 {
11796 inst.reloc.type = BFD_RELOC_UNUSED;
11797 inst.instruction = THUMB_OP16 (T_MNEM_negs);
11798 inst.instruction |= Rs << 3;
11799 inst.instruction |= Rd;
11800 }
11801 else
11802 {
11803 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11804 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11805 }
c19d1205
ZW		 11806 }
11807 else
11808 encode_thumb32_shifted_operand (2);
11809}
b99bd4ef 11810
c19d1205
ZW		 11811static void
11812do_t_setend (void)
11813{
12e37cbc
MGD		 11814 if (warn_on_deprecated
11815 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11816 as_warn (_("setend use is deprecated for ARMv8"));
11817
e07e6e58 11818 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW		 11819 if (inst.operands[0].imm)
11820 inst.instruction |= 0x8;
11821}
b99bd4ef 11822
c19d1205
ZW		 11823static void
11824do_t_shift (void)
11825{
11826 if (!inst.operands[1].present)
11827 inst.operands[1].reg = inst.operands[0].reg;
11828
11829 if (unified_syntax)
11830 {
3d388997
PB		 11831 bfd_boolean narrow;
11832 int shift_kind;
11833
11834 switch (inst.instruction)
11835 {
11836 case T_MNEM_asr:
11837 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
11838 case T_MNEM_lsl:
11839 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
11840 case T_MNEM_lsr:
11841 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
11842 case T_MNEM_ror:
11843 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
11844 default: abort ();
11845 }
11846
11847 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 11848 narrow = !in_it_block ();
3d388997 11849 else
e07e6e58 11850 narrow = in_it_block ();
3d388997
PB		 11851 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
11852 narrow = FALSE;
11853 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
11854 narrow = FALSE;
11855 if (inst.operands[2].isreg
11856 && (inst.operands[1].reg != inst.operands[0].reg
11857 || inst.operands[2].reg > 7))
11858 narrow = FALSE;
11859 if (inst.size_req == 4)
11860 narrow = FALSE;
11861
fdfde340
JM		 11862 reject_bad_reg (inst.operands[0].reg);
11863 reject_bad_reg (inst.operands[1].reg);
c921be7d 11864
3d388997 11865 if (!narrow)
c19d1205
ZW		 11866 {
11867 if (inst.operands[2].isreg)
b99bd4ef 11868 {
fdfde340 11869 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW		 11870 inst.instruction = THUMB_OP32 (inst.instruction);
11871 inst.instruction |= inst.operands[0].reg << 8;
11872 inst.instruction |= inst.operands[1].reg << 16;
11873 inst.instruction |= inst.operands[2].reg;
94342ec3
NC		 11874
11875 /* PR 12854: Error on extraneous shifts. */
11876 constraint (inst.operands[2].shifted,
11877 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 11878 }
11879 else
11880 {
11881 inst.operands[1].shifted = 1;
3d388997 11882 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW		 11883 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
11884 ? T_MNEM_movs : T_MNEM_mov);
11885 inst.instruction |= inst.operands[0].reg << 8;
11886 encode_thumb32_shifted_operand (1);
11887 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11888 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef
NC		 11889 }
11890 }
11891 else
11892 {
c19d1205 11893 if (inst.operands[2].isreg)
b99bd4ef 11894 {
3d388997 11895 switch (shift_kind)
b99bd4ef 11896 {
3d388997
PB		 11897 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
11898 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
11899 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
11900 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 11901 default: abort ();
b99bd4ef 11902 }
5f4273c7 11903
c19d1205
ZW		 11904 inst.instruction |= inst.operands[0].reg;
11905 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 11906
11907 /* PR 12854: Error on extraneous shifts. */
11908 constraint (inst.operands[2].shifted,
11909 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC		 11910 }
11911 else
11912 {
3d388997 11913 switch (shift_kind)
b99bd4ef 11914 {
3d388997
PB		 11915 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11916 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11917 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 11918 default: abort ();
b99bd4ef 11919 }
c19d1205
ZW		 11920 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11921 inst.instruction |= inst.operands[0].reg;
11922 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 11923 }
11924 }
c19d1205
ZW		 11925 }
11926 else
11927 {
11928 constraint (inst.operands[0].reg > 7
11929 || inst.operands[1].reg > 7, BAD_HIREG);
11930 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 11931
c19d1205
ZW		 11932 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
11933 {
11934 constraint (inst.operands[2].reg > 7, BAD_HIREG);
11935 constraint (inst.operands[0].reg != inst.operands[1].reg,
11936 _("source1 and dest must be same register"));
b99bd4ef 11937
c19d1205
ZW		 11938 switch (inst.instruction)
11939 {
11940 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
11941 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
11942 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
11943 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
11944 default: abort ();
11945 }
5f4273c7 11946
c19d1205
ZW		 11947 inst.instruction |= inst.operands[0].reg;
11948 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 11949
11950 /* PR 12854: Error on extraneous shifts. */
11951 constraint (inst.operands[2].shifted,
11952 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 11953 }
11954 else
b99bd4ef 11955 {
c19d1205
ZW		 11956 switch (inst.instruction)
11957 {
11958 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
11959 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
11960 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
11961 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
11962 default: abort ();
11963 }
11964 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11965 inst.instruction |= inst.operands[0].reg;
11966 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 11967 }
11968 }
b99bd4ef
NC		 11969}
11970
11971static void
c19d1205 11972do_t_simd (void)
b99bd4ef 11973{
fdfde340
JM		 11974 unsigned Rd, Rn, Rm;
11975
11976 Rd = inst.operands[0].reg;
11977 Rn = inst.operands[1].reg;
11978 Rm = inst.operands[2].reg;
11979
11980 reject_bad_reg (Rd);
11981 reject_bad_reg (Rn);
11982 reject_bad_reg (Rm);
11983
11984 inst.instruction |= Rd << 8;
11985 inst.instruction |= Rn << 16;
11986 inst.instruction |= Rm;
c19d1205 11987}
b99bd4ef 11988
03ee1b7f
NC		 11989static void
11990do_t_simd2 (void)
11991{
11992 unsigned Rd, Rn, Rm;
11993
11994 Rd = inst.operands[0].reg;
11995 Rm = inst.operands[1].reg;
11996 Rn = inst.operands[2].reg;
11997
11998 reject_bad_reg (Rd);
11999 reject_bad_reg (Rn);
12000 reject_bad_reg (Rm);
12001
12002 inst.instruction |= Rd << 8;
12003 inst.instruction |= Rn << 16;
12004 inst.instruction |= Rm;
12005}
12006
c19d1205 12007static void
3eb17e6b 12008do_t_smc (void)
c19d1205
ZW		 12009{
12010 unsigned int value = inst.reloc.exp.X_add_number;
f4c65163
MGD		 12011 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12012 _("SMC is not permitted on this architecture"));
c19d1205
ZW		 12013 constraint (inst.reloc.exp.X_op != O_constant,
12014 _("expression too complex"));
12015 inst.reloc.type = BFD_RELOC_UNUSED;
12016 inst.instruction |= (value & 0xf000) >> 12;
12017 inst.instruction |= (value & 0x0ff0);
12018 inst.instruction |= (value & 0x000f) << 16;
24382199
NC		 12019 /* PR gas/15623: SMC instructions must be last in an IT block. */
12020 set_it_insn_type_last ();
c19d1205 12021}
b99bd4ef 12022
90ec0d68
MGD		 12023static void
12024do_t_hvc (void)
12025{
12026 unsigned int value = inst.reloc.exp.X_add_number;
12027
12028 inst.reloc.type = BFD_RELOC_UNUSED;
12029 inst.instruction |= (value & 0x0fff);
12030 inst.instruction |= (value & 0xf000) << 4;
12031}
12032
c19d1205 12033static void
3a21c15a 12034do_t_ssat_usat (int bias)
c19d1205 12035{
fdfde340
JM		 12036 unsigned Rd, Rn;
12037
12038 Rd = inst.operands[0].reg;
12039 Rn = inst.operands[2].reg;
12040
12041 reject_bad_reg (Rd);
12042 reject_bad_reg (Rn);
12043
12044 inst.instruction |= Rd << 8;
3a21c15a 12045 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 12046 inst.instruction |= Rn << 16;
b99bd4ef 12047
c19d1205 12048 if (inst.operands[3].present)
b99bd4ef 12049 {
3a21c15a
NC		 12050 offsetT shift_amount = inst.reloc.exp.X_add_number;
12051
12052 inst.reloc.type = BFD_RELOC_UNUSED;
12053
c19d1205
ZW		 12054 constraint (inst.reloc.exp.X_op != O_constant,
12055 _("expression too complex"));
b99bd4ef 12056
3a21c15a 12057 if (shift_amount != 0)
6189168b 12058 {
3a21c15a
NC		 12059 constraint (shift_amount > 31,
12060 _("shift expression is too large"));
12061
c19d1205 12062 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC		 12063 inst.instruction |= 0x00200000; /* sh bit. */
12064
12065 inst.instruction |= (shift_amount & 0x1c) << 10;
12066 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC		 12067 }
12068 }
b99bd4ef 12069}
c921be7d 12070
3a21c15a
NC		 12071static void
12072do_t_ssat (void)
12073{
12074 do_t_ssat_usat (1);
12075}
b99bd4ef 12076
0dd132b6 12077static void
c19d1205 12078do_t_ssat16 (void)
0dd132b6 12079{
fdfde340
JM		 12080 unsigned Rd, Rn;
12081
12082 Rd = inst.operands[0].reg;
12083 Rn = inst.operands[2].reg;
12084
12085 reject_bad_reg (Rd);
12086 reject_bad_reg (Rn);
12087
12088 inst.instruction |= Rd << 8;
c19d1205 12089 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 12090 inst.instruction |= Rn << 16;
c19d1205 12091}
0dd132b6 12092
c19d1205
ZW		 12093static void
12094do_t_strex (void)
12095{
12096 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12097 || inst.operands[2].postind || inst.operands[2].writeback
12098 || inst.operands[2].immisreg || inst.operands[2].shifted
12099 || inst.operands[2].negative,
01cfc07f 12100 BAD_ADDR_MODE);
0dd132b6 12101
5be8be5d
DG		 12102 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12103
c19d1205
ZW		 12104 inst.instruction |= inst.operands[0].reg << 8;
12105 inst.instruction |= inst.operands[1].reg << 12;
12106 inst.instruction |= inst.operands[2].reg << 16;
12107 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC		 12108}
12109
b99bd4ef 12110static void
c19d1205 12111do_t_strexd (void)
b99bd4ef 12112{
c19d1205
ZW		 12113 if (!inst.operands[2].present)
12114 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 12115
c19d1205
ZW		 12116 constraint (inst.operands[0].reg == inst.operands[1].reg
12117 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 12118 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 12119 BAD_OVERLAP);
b99bd4ef 12120
c19d1205
ZW		 12121 inst.instruction |= inst.operands[0].reg;
12122 inst.instruction |= inst.operands[1].reg << 12;
12123 inst.instruction |= inst.operands[2].reg << 8;
12124 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC		 12125}
12126
12127static void
c19d1205 12128do_t_sxtah (void)
b99bd4ef 12129{
fdfde340
JM		 12130 unsigned Rd, Rn, Rm;
12131
12132 Rd = inst.operands[0].reg;
12133 Rn = inst.operands[1].reg;
12134 Rm = inst.operands[2].reg;
12135
12136 reject_bad_reg (Rd);
12137 reject_bad_reg (Rn);
12138 reject_bad_reg (Rm);
12139
12140 inst.instruction |= Rd << 8;
12141 inst.instruction |= Rn << 16;
12142 inst.instruction |= Rm;
c19d1205
ZW		 12143 inst.instruction |= inst.operands[3].imm << 4;
12144}
b99bd4ef 12145
c19d1205
ZW		 12146static void
12147do_t_sxth (void)
12148{
fdfde340
JM		 12149 unsigned Rd, Rm;
12150
12151 Rd = inst.operands[0].reg;
12152 Rm = inst.operands[1].reg;
12153
12154 reject_bad_reg (Rd);
12155 reject_bad_reg (Rm);
c921be7d
NC		 12156
12157 if (inst.instruction <= 0xffff
12158 && inst.size_req != 4
fdfde340 12159 && Rd <= 7 && Rm <= 7
c19d1205 12160 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 12161 {
c19d1205 12162 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 12163 inst.instruction |= Rd;
12164 inst.instruction |= Rm << 3;
b99bd4ef 12165 }
c19d1205 12166 else if (unified_syntax)
b99bd4ef 12167 {
c19d1205
ZW		 12168 if (inst.instruction <= 0xffff)
12169 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12170 inst.instruction |= Rd << 8;
12171 inst.instruction |= Rm;
c19d1205 12172 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 12173 }
c19d1205 12174 else
b99bd4ef 12175 {
c19d1205
ZW		 12176 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12177 _("Thumb encoding does not support rotation"));
12178 constraint (1, BAD_HIREG);
b99bd4ef 12179 }
c19d1205 12180}
b99bd4ef 12181
c19d1205
ZW		 12182static void
12183do_t_swi (void)
12184{
b2a5fbdc
MGD		 12185 /* We have to do the following check manually as ARM_EXT_OS only applies
12186 to ARM_EXT_V6M. */
12187 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12188 {
ac7f631b
NC		 12189 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12190 /* This only applies to the v6m howver, not later architectures. */
12191 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
b2a5fbdc
MGD		 12192 as_bad (_("SVC is not permitted on this architecture"));
12193 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12194 }
12195
c19d1205
ZW		 12196 inst.reloc.type = BFD_RELOC_ARM_SWI;
12197}
b99bd4ef 12198
92e90b6e
PB		 12199static void
12200do_t_tb (void)
12201{
fdfde340 12202 unsigned Rn, Rm;
92e90b6e
PB		 12203 int half;
12204
12205 half = (inst.instruction & 0x10) != 0;
e07e6e58 12206 set_it_insn_type_last ();
dfa9f0d5
PB		 12207 constraint (inst.operands[0].immisreg,
12208 _("instruction requires register index"));
fdfde340
JM		 12209
12210 Rn = inst.operands[0].reg;
12211 Rm = inst.operands[0].imm;
c921be7d 12212
fdfde340
JM		 12213 constraint (Rn == REG_SP, BAD_SP);
12214 reject_bad_reg (Rm);
12215
92e90b6e
PB		 12216 constraint (!half && inst.operands[0].shifted,
12217 _("instruction does not allow shifted index"));
fdfde340 12218 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB		 12219}
12220
c19d1205
ZW		 12221static void
12222do_t_usat (void)
12223{
3a21c15a 12224 do_t_ssat_usat (0);
b99bd4ef
NC		 12225}
12226
12227static void
c19d1205 12228do_t_usat16 (void)
b99bd4ef 12229{
fdfde340
JM		 12230 unsigned Rd, Rn;
12231
12232 Rd = inst.operands[0].reg;
12233 Rn = inst.operands[2].reg;
12234
12235 reject_bad_reg (Rd);
12236 reject_bad_reg (Rn);
12237
12238 inst.instruction |= Rd << 8;
c19d1205 12239 inst.instruction |= inst.operands[1].imm;
fdfde340 12240 inst.instruction |= Rn << 16;
b99bd4ef 12241}
c19d1205 12242
5287ad62 12243/* Neon instruction encoder helpers. */
5f4273c7 12244
5287ad62 12245/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 12246
5287ad62
JB		 12247/* An "invalid" code for the following tables. */
12248#define N_INV -1u
12249
12250struct neon_tab_entry
b99bd4ef 12251{
5287ad62
JB		 12252 unsigned integer;
12253 unsigned float_or_poly;
12254 unsigned scalar_or_imm;
12255};
5f4273c7 12256
5287ad62
JB		 12257/* Map overloaded Neon opcodes to their respective encodings. */
12258#define NEON_ENC_TAB \
12259 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12260 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12261 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12262 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12263 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12264 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12265 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12266 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12267 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12268 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12269 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12270 /* Register variants of the following two instructions are encoded as
e07e6e58 12271 vcge / vcgt with the operands reversed. */ \
92559b5b
PB		 12272 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12273 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB		 12274 X(vfma, N_INV, 0x0000c10, N_INV), \
12275 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB		 12276 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12277 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12278 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12279 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12280 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12281 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12282 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12283 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12284 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12285 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12286 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12287 X(vshl, 0x0000400, N_INV, 0x0800510), \
12288 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12289 X(vand, 0x0000110, N_INV, 0x0800030), \
12290 X(vbic, 0x0100110, N_INV, 0x0800030), \
12291 X(veor, 0x1000110, N_INV, N_INV), \
12292 X(vorn, 0x0300110, N_INV, 0x0800010), \
12293 X(vorr, 0x0200110, N_INV, 0x0800010), \
12294 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12295 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12296 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12297 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12298 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12299 X(vst1, 0x0000000, 0x0800000, N_INV), \
12300 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12301 X(vst2, 0x0000100, 0x0800100, N_INV), \
12302 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12303 X(vst3, 0x0000200, 0x0800200, N_INV), \
12304 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12305 X(vst4, 0x0000300, 0x0800300, N_INV), \
12306 X(vmovn, 0x1b20200, N_INV, N_INV), \
12307 X(vtrn, 0x1b20080, N_INV, N_INV), \
12308 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB		 12309 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12310 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB		 12311 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12312 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB		 12313 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12314 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB		 12315 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12316 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12317 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD		 12318 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12319 X(vseleq, 0xe000a00, N_INV, N_INV), \
12320 X(vselvs, 0xe100a00, N_INV, N_INV), \
12321 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD		 12322 X(vselgt, 0xe300a00, N_INV, N_INV), \
12323 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 12324 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD		 12325 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12326 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 12327 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 12328 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD		 12329 X(sha3op, 0x2000c00, N_INV, N_INV), \
12330 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12331 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB		 12332
12333enum neon_opc
12334{
12335#define X(OPC,I,F,S) N_MNEM_##OPC
12336NEON_ENC_TAB
12337#undef X
12338};
b99bd4ef 12339
5287ad62
JB		 12340static const struct neon_tab_entry neon_enc_tab[] =
12341{
12342#define X(OPC,I,F,S) { (I), (F), (S) }
12343NEON_ENC_TAB
12344#undef X
12345};
b99bd4ef 12346
88714cb8
DG		 12347/* Do not use these macros; instead, use NEON_ENCODE defined below. */
12348#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12349#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12350#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12351#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12352#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12353#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12354#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12355#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12356#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12357#define NEON_ENC_SINGLE_(X) \
037e8744 12358 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 12359#define NEON_ENC_DOUBLE_(X) \
037e8744 12360 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD		 12361#define NEON_ENC_FPV8_(X) \
12362 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 12363
88714cb8
DG		 12364#define NEON_ENCODE(type, inst) \
12365 do \
12366 { \
12367 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12368 inst.is_neon = 1; \
12369 } \
12370 while (0)
12371
12372#define check_neon_suffixes \
12373 do \
12374 { \
12375 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12376 { \
12377 as_bad (_("invalid neon suffix for non neon instruction")); \
12378 return; \
12379 } \
12380 } \
12381 while (0)
12382
037e8744
JB		 12383/* Define shapes for instruction operands. The following mnemonic characters
12384 are used in this table:
5287ad62 12385
037e8744 12386 F - VFP S<n> register
5287ad62
JB		 12387 D - Neon D<n> register
12388 Q - Neon Q<n> register
12389 I - Immediate
12390 S - Scalar
12391 R - ARM register
12392 L - D<n> register list
5f4273c7 12393
037e8744
JB		 12394 This table is used to generate various data:
12395 - enumerations of the form NS_DDR to be used as arguments to
12396 neon_select_shape.
12397 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 12398 - a table used to drive neon_select_shape. */
b99bd4ef 12399
037e8744
JB		 12400#define NEON_SHAPE_DEF \
12401 X(3, (D, D, D), DOUBLE), \
12402 X(3, (Q, Q, Q), QUAD), \
12403 X(3, (D, D, I), DOUBLE), \
12404 X(3, (Q, Q, I), QUAD), \
12405 X(3, (D, D, S), DOUBLE), \
12406 X(3, (Q, Q, S), QUAD), \
12407 X(2, (D, D), DOUBLE), \
12408 X(2, (Q, Q), QUAD), \
12409 X(2, (D, S), DOUBLE), \
12410 X(2, (Q, S), QUAD), \
12411 X(2, (D, R), DOUBLE), \
12412 X(2, (Q, R), QUAD), \
12413 X(2, (D, I), DOUBLE), \
12414 X(2, (Q, I), QUAD), \
12415 X(3, (D, L, D), DOUBLE), \
12416 X(2, (D, Q), MIXED), \
12417 X(2, (Q, D), MIXED), \
12418 X(3, (D, Q, I), MIXED), \
12419 X(3, (Q, D, I), MIXED), \
12420 X(3, (Q, D, D), MIXED), \
12421 X(3, (D, Q, Q), MIXED), \
12422 X(3, (Q, Q, D), MIXED), \
12423 X(3, (Q, D, S), MIXED), \
12424 X(3, (D, Q, S), MIXED), \
12425 X(4, (D, D, D, I), DOUBLE), \
12426 X(4, (Q, Q, Q, I), QUAD), \
12427 X(2, (F, F), SINGLE), \
12428 X(3, (F, F, F), SINGLE), \
12429 X(2, (F, I), SINGLE), \
12430 X(2, (F, D), MIXED), \
12431 X(2, (D, F), MIXED), \
12432 X(3, (F, F, I), MIXED), \
12433 X(4, (R, R, F, F), SINGLE), \
12434 X(4, (F, F, R, R), SINGLE), \
12435 X(3, (D, R, R), DOUBLE), \
12436 X(3, (R, R, D), DOUBLE), \
12437 X(2, (S, R), SINGLE), \
12438 X(2, (R, S), SINGLE), \
12439 X(2, (F, R), SINGLE), \
12440 X(2, (R, F), SINGLE)
12441
12442#define S2(A,B) NS_##A##B
12443#define S3(A,B,C) NS_##A##B##C
12444#define S4(A,B,C,D) NS_##A##B##C##D
12445
12446#define X(N, L, C) S##N L
12447
5287ad62
JB		 12448enum neon_shape
12449{
037e8744
JB		 12450 NEON_SHAPE_DEF,
12451 NS_NULL
5287ad62 12452};
b99bd4ef 12453
037e8744
JB		 12454#undef X
12455#undef S2
12456#undef S3
12457#undef S4
12458
12459enum neon_shape_class
12460{
12461 SC_SINGLE,
12462 SC_DOUBLE,
12463 SC_QUAD,
12464 SC_MIXED
12465};
12466
12467#define X(N, L, C) SC_##C
12468
12469static enum neon_shape_class neon_shape_class[] =
12470{
12471 NEON_SHAPE_DEF
12472};
12473
12474#undef X
12475
12476enum neon_shape_el
12477{
12478 SE_F,
12479 SE_D,
12480 SE_Q,
12481 SE_I,
12482 SE_S,
12483 SE_R,
12484 SE_L
12485};
12486
12487/* Register widths of above. */
12488static unsigned neon_shape_el_size[] =
12489{
12490 32,
12491 64,
12492 128,
12493 0,
12494 32,
12495 32,
12496 0
12497};
12498
12499struct neon_shape_info
12500{
12501 unsigned els;
12502 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
12503};
12504
12505#define S2(A,B) { SE_##A, SE_##B }
12506#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12507#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12508
12509#define X(N, L, C) { N, S##N L }
12510
12511static struct neon_shape_info neon_shape_tab[] =
12512{
12513 NEON_SHAPE_DEF
12514};
12515
12516#undef X
12517#undef S2
12518#undef S3
12519#undef S4
12520
5287ad62
JB		 12521/* Bit masks used in type checking given instructions.
12522 'N_EQK' means the type must be the same as (or based on in some way) the key
12523 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12524 set, various other bits can be set as well in order to modify the meaning of
12525 the type constraint. */
12526
12527enum neon_type_mask
12528{
8e79c3df
CM		 12529 N_S8 = 0x0000001,
12530 N_S16 = 0x0000002,
12531 N_S32 = 0x0000004,
12532 N_S64 = 0x0000008,
12533 N_U8 = 0x0000010,
12534 N_U16 = 0x0000020,
12535 N_U32 = 0x0000040,
12536 N_U64 = 0x0000080,
12537 N_I8 = 0x0000100,
12538 N_I16 = 0x0000200,
12539 N_I32 = 0x0000400,
12540 N_I64 = 0x0000800,
12541 N_8 = 0x0001000,
12542 N_16 = 0x0002000,
12543 N_32 = 0x0004000,
12544 N_64 = 0x0008000,
12545 N_P8 = 0x0010000,
12546 N_P16 = 0x0020000,
12547 N_F16 = 0x0040000,
12548 N_F32 = 0x0080000,
12549 N_F64 = 0x0100000,
4f51b4bd 12550 N_P64 = 0x0200000,
c921be7d
NC		 12551 N_KEY = 0x1000000, /* Key element (main type specifier). */
12552 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 12553 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 12554 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC		 12555 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
12556 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
12557 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12558 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12559 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12560 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
12561 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 12562 N_UTYP = 0,
4f51b4bd 12563 N_MAX_NONSPECIAL = N_P64
5287ad62
JB		 12564};
12565
dcbf9037
JB		 12566#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12567
5287ad62
JB		 12568#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12569#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12570#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12571#define N_SUF_32 (N_SU_32 | N_F32)
12572#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12573#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12574
12575/* Pass this as the first type argument to neon_check_type to ignore types
12576 altogether. */
12577#define N_IGNORE_TYPE (N_KEY | N_EQK)
12578
037e8744
JB		 12579/* Select a "shape" for the current instruction (describing register types or
12580 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12581 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12582 function of operand parsing, so this function doesn't need to be called.
12583 Shapes should be listed in order of decreasing length. */
5287ad62
JB		 12584
12585static enum neon_shape
037e8744 12586neon_select_shape (enum neon_shape shape, ...)
5287ad62 12587{
037e8744
JB		 12588 va_list ap;
12589 enum neon_shape first_shape = shape;
5287ad62
JB		 12590
12591 /* Fix missing optional operands. FIXME: we don't know at this point how
12592 many arguments we should have, so this makes the assumption that we have
12593 > 1. This is true of all current Neon opcodes, I think, but may not be
12594 true in the future. */
12595 if (!inst.operands[1].present)
12596 inst.operands[1] = inst.operands[0];
12597
037e8744 12598 va_start (ap, shape);
5f4273c7 12599
21d799b5 12600 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB		 12601 {
12602 unsigned j;
12603 int matches = 1;
12604
12605 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM		 12606 {
12607 if (!inst.operands[j].present)
12608 {
12609 matches = 0;
12610 break;
12611 }
12612
12613 switch (neon_shape_tab[shape].el[j])
12614 {
12615 case SE_F:
12616 if (!(inst.operands[j].isreg
12617 && inst.operands[j].isvec
12618 && inst.operands[j].issingle
12619 && !inst.operands[j].isquad))
12620 matches = 0;
12621 break;
12622
12623 case SE_D:
12624 if (!(inst.operands[j].isreg
12625 && inst.operands[j].isvec
12626 && !inst.operands[j].isquad
12627 && !inst.operands[j].issingle))
12628 matches = 0;
12629 break;
12630
12631 case SE_R:
12632 if (!(inst.operands[j].isreg
12633 && !inst.operands[j].isvec))
12634 matches = 0;
12635 break;
12636
12637 case SE_Q:
12638 if (!(inst.operands[j].isreg
12639 && inst.operands[j].isvec
12640 && inst.operands[j].isquad
12641 && !inst.operands[j].issingle))
12642 matches = 0;
12643 break;
12644
12645 case SE_I:
12646 if (!(!inst.operands[j].isreg
12647 && !inst.operands[j].isscalar))
12648 matches = 0;
12649 break;
12650
12651 case SE_S:
12652 if (!(!inst.operands[j].isreg
12653 && inst.operands[j].isscalar))
12654 matches = 0;
12655 break;
12656
12657 case SE_L:
12658 break;
12659 }
3fde54a2
JZ		 12660 if (!matches)
12661 break;
477330fc 12662 }
ad6cec43
MGD		 12663 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
12664 /* We've matched all the entries in the shape table, and we don't
12665 have any left over operands which have not been matched. */
477330fc 12666 break;
037e8744 12667 }
5f4273c7 12668
037e8744 12669 va_end (ap);
5287ad62 12670
037e8744
JB		 12671 if (shape == NS_NULL && first_shape != NS_NULL)
12672 first_error (_("invalid instruction shape"));
5287ad62 12673
037e8744
JB		 12674 return shape;
12675}
5287ad62 12676
037e8744
JB		 12677/* True if SHAPE is predominantly a quadword operation (most of the time, this
12678 means the Q bit should be set). */
12679
12680static int
12681neon_quad (enum neon_shape shape)
12682{
12683 return neon_shape_class[shape] == SC_QUAD;
5287ad62 12684}
037e8744 12685
5287ad62
JB		 12686static void
12687neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 12688 unsigned *g_size)
5287ad62
JB		 12689{
12690 /* Allow modification to be made to types which are constrained to be
12691 based on the key element, based on bits set alongside N_EQK. */
12692 if ((typebits & N_EQK) != 0)
12693 {
12694 if ((typebits & N_HLF) != 0)
12695 *g_size /= 2;
12696 else if ((typebits & N_DBL) != 0)
12697 *g_size *= 2;
12698 if ((typebits & N_SGN) != 0)
12699 *g_type = NT_signed;
12700 else if ((typebits & N_UNS) != 0)
477330fc 12701 *g_type = NT_unsigned;
5287ad62 12702 else if ((typebits & N_INT) != 0)
477330fc 12703 *g_type = NT_integer;
5287ad62 12704 else if ((typebits & N_FLT) != 0)
477330fc 12705 *g_type = NT_float;
dcbf9037 12706 else if ((typebits & N_SIZ) != 0)
477330fc 12707 *g_type = NT_untyped;
5287ad62
JB		 12708 }
12709}
5f4273c7 12710
5287ad62
JB		 12711/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12712 operand type, i.e. the single type specified in a Neon instruction when it
12713 is the only one given. */
12714
12715static struct neon_type_el
12716neon_type_promote (struct neon_type_el *key, unsigned thisarg)
12717{
12718 struct neon_type_el dest = *key;
5f4273c7 12719
9c2799c2 12720 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 12721
5287ad62
JB		 12722 neon_modify_type_size (thisarg, &dest.type, &dest.size);
12723
12724 return dest;
12725}
12726
12727/* Convert Neon type and size into compact bitmask representation. */
12728
12729static enum neon_type_mask
12730type_chk_of_el_type (enum neon_el_type type, unsigned size)
12731{
12732 switch (type)
12733 {
12734 case NT_untyped:
12735 switch (size)
477330fc
RM		 12736 {
12737 case 8: return N_8;
12738 case 16: return N_16;
12739 case 32: return N_32;
12740 case 64: return N_64;
12741 default: ;
12742 }
5287ad62
JB		 12743 break;
12744
12745 case NT_integer:
12746 switch (size)
477330fc
RM		 12747 {
12748 case 8: return N_I8;
12749 case 16: return N_I16;
12750 case 32: return N_I32;
12751 case 64: return N_I64;
12752 default: ;
12753 }
5287ad62
JB		 12754 break;
12755
12756 case NT_float:
037e8744 12757 switch (size)
477330fc 12758 {
8e79c3df 12759 case 16: return N_F16;
477330fc
RM		 12760 case 32: return N_F32;
12761 case 64: return N_F64;
12762 default: ;
12763 }
5287ad62
JB		 12764 break;
12765
12766 case NT_poly:
12767 switch (size)
477330fc
RM		 12768 {
12769 case 8: return N_P8;
12770 case 16: return N_P16;
4f51b4bd 12771 case 64: return N_P64;
477330fc
RM		 12772 default: ;
12773 }
5287ad62
JB		 12774 break;
12775
12776 case NT_signed:
12777 switch (size)
477330fc
RM		 12778 {
12779 case 8: return N_S8;
12780 case 16: return N_S16;
12781 case 32: return N_S32;
12782 case 64: return N_S64;
12783 default: ;
12784 }
5287ad62
JB		 12785 break;
12786
12787 case NT_unsigned:
12788 switch (size)
477330fc
RM		 12789 {
12790 case 8: return N_U8;
12791 case 16: return N_U16;
12792 case 32: return N_U32;
12793 case 64: return N_U64;
12794 default: ;
12795 }
5287ad62
JB		 12796 break;
12797
12798 default: ;
12799 }
5f4273c7 12800
5287ad62
JB		 12801 return N_UTYP;
12802}
12803
12804/* Convert compact Neon bitmask type representation to a type and size. Only
12805 handles the case where a single bit is set in the mask. */
12806
dcbf9037 12807static int
5287ad62 12808el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 12809 enum neon_type_mask mask)
5287ad62 12810{
dcbf9037
JB		 12811 if ((mask & N_EQK) != 0)
12812 return FAIL;
12813
5287ad62
JB		 12814 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
12815 *size = 8;
c70a8987 12816 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
5287ad62 12817 *size = 16;
dcbf9037 12818 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 12819 *size = 32;
4f51b4bd 12820 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 12821 *size = 64;
dcbf9037
JB		 12822 else
12823 return FAIL;
12824
5287ad62
JB		 12825 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
12826 *type = NT_signed;
dcbf9037 12827 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 12828 *type = NT_unsigned;
dcbf9037 12829 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 12830 *type = NT_integer;
dcbf9037 12831 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 12832 *type = NT_untyped;
4f51b4bd 12833 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 12834 *type = NT_poly;
c70a8987 12835 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
5287ad62 12836 *type = NT_float;
dcbf9037
JB		 12837 else
12838 return FAIL;
5f4273c7 12839
dcbf9037 12840 return SUCCESS;
5287ad62
JB		 12841}
12842
12843/* Modify a bitmask of allowed types. This is only needed for type
12844 relaxation. */
12845
12846static unsigned
12847modify_types_allowed (unsigned allowed, unsigned mods)
12848{
12849 unsigned size;
12850 enum neon_el_type type;
12851 unsigned destmask;
12852 int i;
5f4273c7 12853
5287ad62 12854 destmask = 0;
5f4273c7 12855
5287ad62
JB		 12856 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
12857 {
21d799b5 12858 if (el_type_of_type_chk (&type, &size,
477330fc
RM		 12859 (enum neon_type_mask) (allowed & i)) == SUCCESS)
12860 {
12861 neon_modify_type_size (mods, &type, &size);
12862 destmask |= type_chk_of_el_type (type, size);
12863 }
5287ad62 12864 }
5f4273c7 12865
5287ad62
JB		 12866 return destmask;
12867}
12868
12869/* Check type and return type classification.
12870 The manual states (paraphrase): If one datatype is given, it indicates the
12871 type given in:
12872 - the second operand, if there is one
12873 - the operand, if there is no second operand
12874 - the result, if there are no operands.
12875 This isn't quite good enough though, so we use a concept of a "key" datatype
12876 which is set on a per-instruction basis, which is the one which matters when
12877 only one data type is written.
12878 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 12879 Neon instructions should call it before performing bit encoding. */
5287ad62
JB		 12880
12881static struct neon_type_el
12882neon_check_type (unsigned els, enum neon_shape ns, ...)
12883{
12884 va_list ap;
12885 unsigned i, pass, key_el = 0;
12886 unsigned types[NEON_MAX_TYPE_ELS];
12887 enum neon_el_type k_type = NT_invtype;
12888 unsigned k_size = -1u;
12889 struct neon_type_el badtype = {NT_invtype, -1};
12890 unsigned key_allowed = 0;
12891
12892 /* Optional registers in Neon instructions are always (not) in operand 1.
12893 Fill in the missing operand here, if it was omitted. */
12894 if (els > 1 && !inst.operands[1].present)
12895 inst.operands[1] = inst.operands[0];
12896
12897 /* Suck up all the varargs. */
12898 va_start (ap, ns);
12899 for (i = 0; i < els; i++)
12900 {
12901 unsigned thisarg = va_arg (ap, unsigned);
12902 if (thisarg == N_IGNORE_TYPE)
477330fc
RM		 12903 {
12904 va_end (ap);
12905 return badtype;
12906 }
5287ad62
JB		 12907 types[i] = thisarg;
12908 if ((thisarg & N_KEY) != 0)
477330fc 12909 key_el = i;
5287ad62
JB		 12910 }
12911 va_end (ap);
12912
dcbf9037
JB		 12913 if (inst.vectype.elems > 0)
12914 for (i = 0; i < els; i++)
12915 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM		 12916 {
12917 first_error (_("types specified in both the mnemonic and operands"));
12918 return badtype;
12919 }
dcbf9037 12920
5287ad62
JB		 12921 /* Duplicate inst.vectype elements here as necessary.
12922 FIXME: No idea if this is exactly the same as the ARM assembler,
12923 particularly when an insn takes one register and one non-register
12924 operand. */
12925 if (inst.vectype.elems == 1 && els > 1)
12926 {
12927 unsigned j;
12928 inst.vectype.elems = els;
12929 inst.vectype.el[key_el] = inst.vectype.el[0];
12930 for (j = 0; j < els; j++)
477330fc
RM		 12931 if (j != key_el)
12932 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12933 types[j]);
dcbf9037
JB		 12934 }
12935 else if (inst.vectype.elems == 0 && els > 0)
12936 {
12937 unsigned j;
12938 /* No types were given after the mnemonic, so look for types specified
477330fc
RM		 12939 after each operand. We allow some flexibility here; as long as the
12940 "key" operand has a type, we can infer the others. */
dcbf9037 12941 for (j = 0; j < els; j++)
477330fc
RM		 12942 if (inst.operands[j].vectype.type != NT_invtype)
12943 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB		 12944
12945 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM		 12946 {
12947 for (j = 0; j < els; j++)
12948 if (inst.operands[j].vectype.type == NT_invtype)
12949 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
12950 types[j]);
12951 }
dcbf9037 12952 else
477330fc
RM		 12953 {
12954 first_error (_("operand types can't be inferred"));
12955 return badtype;
12956 }
5287ad62
JB		 12957 }
12958 else if (inst.vectype.elems != els)
12959 {
dcbf9037 12960 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB		 12961 return badtype;
12962 }
12963
12964 for (pass = 0; pass < 2; pass++)
12965 {
12966 for (i = 0; i < els; i++)
477330fc
RM		 12967 {
12968 unsigned thisarg = types[i];
12969 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
12970 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
12971 enum neon_el_type g_type = inst.vectype.el[i].type;
12972 unsigned g_size = inst.vectype.el[i].size;
12973
12974 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 12975 integer types if sign-specific variants are unavailable. */
477330fc 12976 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB		 12977 && (types_allowed & N_SU_ALL) == 0)
12978 g_type = NT_integer;
12979
477330fc 12980 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB		 12981 them. Some instructions only care about signs for some element
12982 sizes, so handle that properly. */
477330fc 12983 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD		 12984 && ((g_size == 8 && (types_allowed & N_8) != 0)
12985 || (g_size == 16 && (types_allowed & N_16) != 0)
12986 || (g_size == 32 && (types_allowed & N_32) != 0)
12987 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB		 12988 g_type = NT_untyped;
12989
477330fc
RM		 12990 if (pass == 0)
12991 {
12992 if ((thisarg & N_KEY) != 0)
12993 {
12994 k_type = g_type;
12995 k_size = g_size;
12996 key_allowed = thisarg & ~N_KEY;
12997 }
12998 }
12999 else
13000 {
13001 if ((thisarg & N_VFP) != 0)
13002 {
13003 enum neon_shape_el regshape;
13004 unsigned regwidth, match;
99b253c5
NC		 13005
13006 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13007 if (ns == NS_NULL)
13008 {
13009 first_error (_("invalid instruction shape"));
13010 return badtype;
13011 }
477330fc
RM		 13012 regshape = neon_shape_tab[ns].el[i];
13013 regwidth = neon_shape_el_size[regshape];
13014
13015 /* In VFP mode, operands must match register widths. If we
13016 have a key operand, use its width, else use the width of
13017 the current operand. */
13018 if (k_size != -1u)
13019 match = k_size;
13020 else
13021 match = g_size;
13022
13023 if (regwidth != match)
13024 {
13025 first_error (_("operand size must match register width"));
13026 return badtype;
13027 }
13028 }
13029
13030 if ((thisarg & N_EQK) == 0)
13031 {
13032 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13033
13034 if ((given_type & types_allowed) == 0)
13035 {
13036 first_error (_("bad type in Neon instruction"));
13037 return badtype;
13038 }
13039 }
13040 else
13041 {
13042 enum neon_el_type mod_k_type = k_type;
13043 unsigned mod_k_size = k_size;
13044 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13045 if (g_type != mod_k_type || g_size != mod_k_size)
13046 {
13047 first_error (_("inconsistent types in Neon instruction"));
13048 return badtype;
13049 }
13050 }
13051 }
13052 }
5287ad62
JB		 13053 }
13054
13055 return inst.vectype.el[key_el];
13056}
13057
037e8744 13058/* Neon-style VFP instruction forwarding. */
5287ad62 13059
037e8744
JB		 13060/* Thumb VFP instructions have 0xE in the condition field. */
13061
13062static void
13063do_vfp_cond_or_thumb (void)
5287ad62 13064{
88714cb8
DG		 13065 inst.is_neon = 1;
13066
5287ad62 13067 if (thumb_mode)
037e8744 13068 inst.instruction |= 0xe0000000;
5287ad62 13069 else
037e8744 13070 inst.instruction |= inst.cond << 28;
5287ad62
JB		 13071}
13072
037e8744
JB		 13073/* Look up and encode a simple mnemonic, for use as a helper function for the
13074 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13075 etc. It is assumed that operand parsing has already been done, and that the
13076 operands are in the form expected by the given opcode (this isn't necessarily
13077 the same as the form in which they were parsed, hence some massaging must
13078 take place before this function is called).
13079 Checks current arch version against that in the looked-up opcode. */
5287ad62 13080
037e8744
JB		 13081static void
13082do_vfp_nsyn_opcode (const char *opname)
5287ad62 13083{
037e8744 13084 const struct asm_opcode *opcode;
5f4273c7 13085
21d799b5 13086 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 13087
037e8744
JB		 13088 if (!opcode)
13089 abort ();
5287ad62 13090
037e8744 13091 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM		 13092 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13093 _(BAD_FPU));
5287ad62 13094
88714cb8
DG		 13095 inst.is_neon = 1;
13096
037e8744
JB		 13097 if (thumb_mode)
13098 {
13099 inst.instruction = opcode->tvalue;
13100 opcode->tencode ();
13101 }
13102 else
13103 {
13104 inst.instruction = (inst.cond << 28) | opcode->avalue;
13105 opcode->aencode ();
13106 }
13107}
5287ad62
JB		 13108
13109static void
037e8744 13110do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 13111{
037e8744
JB		 13112 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13113
13114 if (rs == NS_FFF)
13115 {
13116 if (is_add)
477330fc 13117 do_vfp_nsyn_opcode ("fadds");
037e8744 13118 else
477330fc 13119 do_vfp_nsyn_opcode ("fsubs");
037e8744
JB		 13120 }
13121 else
13122 {
13123 if (is_add)
477330fc 13124 do_vfp_nsyn_opcode ("faddd");
037e8744 13125 else
477330fc 13126 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB		 13127 }
13128}
13129
13130/* Check operand types to see if this is a VFP instruction, and if so call
13131 PFN (). */
13132
13133static int
13134try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13135{
13136 enum neon_shape rs;
13137 struct neon_type_el et;
13138
13139 switch (args)
13140 {
13141 case 2:
13142 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13143 et = neon_check_type (2, rs,
477330fc 13144 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
037e8744 13145 break;
5f4273c7 13146
037e8744
JB		 13147 case 3:
13148 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13149 et = neon_check_type (3, rs,
477330fc 13150 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
037e8744
JB		 13151 break;
13152
13153 default:
13154 abort ();
13155 }
13156
13157 if (et.type != NT_invtype)
13158 {
13159 pfn (rs);
13160 return SUCCESS;
13161 }
037e8744 13162
99b253c5 13163 inst.error = NULL;
037e8744
JB		 13164 return FAIL;
13165}
13166
13167static void
13168do_vfp_nsyn_mla_mls (enum neon_shape rs)
13169{
13170 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 13171
037e8744
JB		 13172 if (rs == NS_FFF)
13173 {
13174 if (is_mla)
477330fc 13175 do_vfp_nsyn_opcode ("fmacs");
037e8744 13176 else
477330fc 13177 do_vfp_nsyn_opcode ("fnmacs");
037e8744
JB		 13178 }
13179 else
13180 {
13181 if (is_mla)
477330fc 13182 do_vfp_nsyn_opcode ("fmacd");
037e8744 13183 else
477330fc 13184 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB		 13185 }
13186}
13187
62f3b8c8
PB		 13188static void
13189do_vfp_nsyn_fma_fms (enum neon_shape rs)
13190{
13191 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13192
13193 if (rs == NS_FFF)
13194 {
13195 if (is_fma)
477330fc 13196 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 13197 else
477330fc 13198 do_vfp_nsyn_opcode ("ffnmas");
62f3b8c8
PB		 13199 }
13200 else
13201 {
13202 if (is_fma)
477330fc 13203 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 13204 else
477330fc 13205 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB		 13206 }
13207}
13208
037e8744
JB		 13209static void
13210do_vfp_nsyn_mul (enum neon_shape rs)
13211{
13212 if (rs == NS_FFF)
13213 do_vfp_nsyn_opcode ("fmuls");
13214 else
13215 do_vfp_nsyn_opcode ("fmuld");
13216}
13217
13218static void
13219do_vfp_nsyn_abs_neg (enum neon_shape rs)
13220{
13221 int is_neg = (inst.instruction & 0x80) != 0;
13222 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13223
13224 if (rs == NS_FF)
13225 {
13226 if (is_neg)
477330fc 13227 do_vfp_nsyn_opcode ("fnegs");
037e8744 13228 else
477330fc 13229 do_vfp_nsyn_opcode ("fabss");
037e8744
JB		 13230 }
13231 else
13232 {
13233 if (is_neg)
477330fc 13234 do_vfp_nsyn_opcode ("fnegd");
037e8744 13235 else
477330fc 13236 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB		 13237 }
13238}
13239
13240/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13241 insns belong to Neon, and are handled elsewhere. */
13242
13243static void
13244do_vfp_nsyn_ldm_stm (int is_dbmode)
13245{
13246 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13247 if (is_ldm)
13248 {
13249 if (is_dbmode)
477330fc 13250 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 13251 else
477330fc 13252 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB		 13253 }
13254 else
13255 {
13256 if (is_dbmode)
477330fc 13257 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 13258 else
477330fc 13259 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB		 13260 }
13261}
13262
037e8744
JB		 13263static void
13264do_vfp_nsyn_sqrt (void)
13265{
13266 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13267 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13268
037e8744
JB		 13269 if (rs == NS_FF)
13270 do_vfp_nsyn_opcode ("fsqrts");
13271 else
13272 do_vfp_nsyn_opcode ("fsqrtd");
13273}
13274
13275static void
13276do_vfp_nsyn_div (void)
13277{
13278 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13279 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13280 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13281
037e8744
JB		 13282 if (rs == NS_FFF)
13283 do_vfp_nsyn_opcode ("fdivs");
13284 else
13285 do_vfp_nsyn_opcode ("fdivd");
13286}
13287
13288static void
13289do_vfp_nsyn_nmul (void)
13290{
13291 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13292 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13293 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13294
037e8744
JB		 13295 if (rs == NS_FFF)
13296 {
88714cb8 13297 NEON_ENCODE (SINGLE, inst);
037e8744
JB		 13298 do_vfp_sp_dyadic ();
13299 }
13300 else
13301 {
88714cb8 13302 NEON_ENCODE (DOUBLE, inst);
037e8744
JB		 13303 do_vfp_dp_rd_rn_rm ();
13304 }
13305 do_vfp_cond_or_thumb ();
13306}
13307
13308static void
13309do_vfp_nsyn_cmp (void)
13310{
13311 if (inst.operands[1].isreg)
13312 {
13313 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13314 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13315
037e8744 13316 if (rs == NS_FF)
477330fc
RM		 13317 {
13318 NEON_ENCODE (SINGLE, inst);
13319 do_vfp_sp_monadic ();
13320 }
037e8744 13321 else
477330fc
RM		 13322 {
13323 NEON_ENCODE (DOUBLE, inst);
13324 do_vfp_dp_rd_rm ();
13325 }
037e8744
JB		 13326 }
13327 else
13328 {
13329 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13330 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13331
13332 switch (inst.instruction & 0x0fffffff)
477330fc
RM		 13333 {
13334 case N_MNEM_vcmp:
13335 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13336 break;
13337 case N_MNEM_vcmpe:
13338 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13339 break;
13340 default:
13341 abort ();
13342 }
5f4273c7 13343
037e8744 13344 if (rs == NS_FI)
477330fc
RM		 13345 {
13346 NEON_ENCODE (SINGLE, inst);
13347 do_vfp_sp_compare_z ();
13348 }
037e8744 13349 else
477330fc
RM		 13350 {
13351 NEON_ENCODE (DOUBLE, inst);
13352 do_vfp_dp_rd ();
13353 }
037e8744
JB		 13354 }
13355 do_vfp_cond_or_thumb ();
13356}
13357
13358static void
13359nsyn_insert_sp (void)
13360{
13361 inst.operands[1] = inst.operands[0];
13362 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 13363 inst.operands[0].reg = REG_SP;
037e8744
JB		 13364 inst.operands[0].isreg = 1;
13365 inst.operands[0].writeback = 1;
13366 inst.operands[0].present = 1;
13367}
13368
13369static void
13370do_vfp_nsyn_push (void)
13371{
13372 nsyn_insert_sp ();
13373 if (inst.operands[1].issingle)
13374 do_vfp_nsyn_opcode ("fstmdbs");
13375 else
13376 do_vfp_nsyn_opcode ("fstmdbd");
13377}
13378
13379static void
13380do_vfp_nsyn_pop (void)
13381{
13382 nsyn_insert_sp ();
13383 if (inst.operands[1].issingle)
22b5b651 13384 do_vfp_nsyn_opcode ("fldmias");
037e8744 13385 else
22b5b651 13386 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB		 13387}
13388
13389/* Fix up Neon data-processing instructions, ORing in the correct bits for
13390 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13391
88714cb8
DG		 13392static void
13393neon_dp_fixup (struct arm_it* insn)
037e8744 13394{
88714cb8
DG		 13395 unsigned int i = insn->instruction;
13396 insn->is_neon = 1;
13397
037e8744
JB		 13398 if (thumb_mode)
13399 {
13400 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13401 if (i & (1 << 24))
477330fc 13402 i |= 1 << 28;
5f4273c7 13403
037e8744 13404 i &= ~(1 << 24);
5f4273c7 13405
037e8744
JB		 13406 i |= 0xef000000;
13407 }
13408 else
13409 i |= 0xf2000000;
5f4273c7 13410
88714cb8 13411 insn->instruction = i;
037e8744
JB		 13412}
13413
13414/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13415 (0, 1, 2, 3). */
13416
13417static unsigned
13418neon_logbits (unsigned x)
13419{
13420 return ffs (x) - 4;
13421}
13422
13423#define LOW4(R) ((R) & 0xf)
13424#define HI1(R) (((R) >> 4) & 1)
13425
13426/* Encode insns with bit pattern:
13427
13428 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13429 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 13430
037e8744
JB		 13431 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13432 different meaning for some instruction. */
13433
13434static void
13435neon_three_same (int isquad, int ubit, int size)
13436{
13437 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13438 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13439 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
13440 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
13441 inst.instruction |= LOW4 (inst.operands[2].reg);
13442 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
13443 inst.instruction |= (isquad != 0) << 6;
13444 inst.instruction |= (ubit != 0) << 24;
13445 if (size != -1)
13446 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 13447
88714cb8 13448 neon_dp_fixup (&inst);
037e8744
JB		 13449}
13450
13451/* Encode instructions of the form:
13452
13453 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13454 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB		 13455
13456 Don't write size if SIZE == -1. */
13457
13458static void
13459neon_two_same (int qbit, int ubit, int size)
13460{
13461 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13462 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13463 inst.instruction |= LOW4 (inst.operands[1].reg);
13464 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13465 inst.instruction |= (qbit != 0) << 6;
13466 inst.instruction |= (ubit != 0) << 24;
13467
13468 if (size != -1)
13469 inst.instruction |= neon_logbits (size) << 18;
13470
88714cb8 13471 neon_dp_fixup (&inst);
5287ad62
JB		 13472}
13473
13474/* Neon instruction encoders, in approximate order of appearance. */
13475
13476static void
13477do_neon_dyadic_i_su (void)
13478{
037e8744 13479 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 13480 struct neon_type_el et = neon_check_type (3, rs,
13481 N_EQK, N_EQK, N_SU_32 | N_KEY);
037e8744 13482 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 13483}
13484
13485static void
13486do_neon_dyadic_i64_su (void)
13487{
037e8744 13488 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 13489 struct neon_type_el et = neon_check_type (3, rs,
13490 N_EQK, N_EQK, N_SU_ALL | N_KEY);
037e8744 13491 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 13492}
13493
13494static void
13495neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 13496 unsigned immbits)
5287ad62
JB		 13497{
13498 unsigned size = et.size >> 3;
13499 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13500 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13501 inst.instruction |= LOW4 (inst.operands[1].reg);
13502 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
13503 inst.instruction |= (isquad != 0) << 6;
13504 inst.instruction |= immbits << 16;
13505 inst.instruction |= (size >> 3) << 7;
13506 inst.instruction |= (size & 0x7) << 19;
13507 if (write_ubit)
13508 inst.instruction |= (uval != 0) << 24;
13509
88714cb8 13510 neon_dp_fixup (&inst);
5287ad62
JB		 13511}
13512
13513static void
13514do_neon_shl_imm (void)
13515{
13516 if (!inst.operands[2].isreg)
13517 {
037e8744 13518 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 13519 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
88714cb8 13520 NEON_ENCODE (IMMED, inst);
037e8744 13521 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
5287ad62
JB		 13522 }
13523 else
13524 {
037e8744 13525 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 13526 struct neon_type_el et = neon_check_type (3, rs,
477330fc 13527 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB		 13528 unsigned int tmp;
13529
13530 /* VSHL/VQSHL 3-register variants have syntax such as:
477330fc
RM		 13531 vshl.xx Dd, Dm, Dn
13532 whereas other 3-register operations encoded by neon_three_same have
13533 syntax like:
13534 vadd.xx Dd, Dn, Dm
13535 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13536 here. */
627907b7
JB		 13537 tmp = inst.operands[2].reg;
13538 inst.operands[2].reg = inst.operands[1].reg;
13539 inst.operands[1].reg = tmp;
88714cb8 13540 NEON_ENCODE (INTEGER, inst);
037e8744 13541 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 13542 }
13543}
13544
13545static void
13546do_neon_qshl_imm (void)
13547{
13548 if (!inst.operands[2].isreg)
13549 {
037e8744 13550 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 13551 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
627907b7 13552
88714cb8 13553 NEON_ENCODE (IMMED, inst);
037e8744 13554 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 13555 inst.operands[2].imm);
5287ad62
JB		 13556 }
13557 else
13558 {
037e8744 13559 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 13560 struct neon_type_el et = neon_check_type (3, rs,
477330fc 13561 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB		 13562 unsigned int tmp;
13563
13564 /* See note in do_neon_shl_imm. */
13565 tmp = inst.operands[2].reg;
13566 inst.operands[2].reg = inst.operands[1].reg;
13567 inst.operands[1].reg = tmp;
88714cb8 13568 NEON_ENCODE (INTEGER, inst);
037e8744 13569 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 13570 }
13571}
13572
627907b7
JB		 13573static void
13574do_neon_rshl (void)
13575{
13576 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
13577 struct neon_type_el et = neon_check_type (3, rs,
13578 N_EQK, N_EQK, N_SU_ALL | N_KEY);
13579 unsigned int tmp;
13580
13581 tmp = inst.operands[2].reg;
13582 inst.operands[2].reg = inst.operands[1].reg;
13583 inst.operands[1].reg = tmp;
13584 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
13585}
13586
5287ad62
JB		 13587static int
13588neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
13589{
036dc3f7
PB		 13590 /* Handle .I8 pseudo-instructions. */
13591 if (size == 8)
5287ad62 13592 {
5287ad62 13593 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM		 13594 FIXME is this the intended semantics? There doesn't seem much point in
13595 accepting .I8 if so. */
5287ad62
JB		 13596 immediate |= immediate << 8;
13597 size = 16;
036dc3f7
PB		 13598 }
13599
13600 if (size >= 32)
13601 {
13602 if (immediate == (immediate & 0x000000ff))
13603 {
13604 *immbits = immediate;
13605 return 0x1;
13606 }
13607 else if (immediate == (immediate & 0x0000ff00))
13608 {
13609 *immbits = immediate >> 8;
13610 return 0x3;
13611 }
13612 else if (immediate == (immediate & 0x00ff0000))
13613 {
13614 *immbits = immediate >> 16;
13615 return 0x5;
13616 }
13617 else if (immediate == (immediate & 0xff000000))
13618 {
13619 *immbits = immediate >> 24;
13620 return 0x7;
13621 }
13622 if ((immediate & 0xffff) != (immediate >> 16))
13623 goto bad_immediate;
13624 immediate &= 0xffff;
5287ad62
JB		 13625 }
13626
13627 if (immediate == (immediate & 0x000000ff))
13628 {
13629 *immbits = immediate;
036dc3f7 13630 return 0x9;
5287ad62
JB		 13631 }
13632 else if (immediate == (immediate & 0x0000ff00))
13633 {
13634 *immbits = immediate >> 8;
036dc3f7 13635 return 0xb;
5287ad62
JB		 13636 }
13637
13638 bad_immediate:
dcbf9037 13639 first_error (_("immediate value out of range"));
5287ad62
JB		 13640 return FAIL;
13641}
13642
13643/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13644 A, B, C, D. */
13645
13646static int
13647neon_bits_same_in_bytes (unsigned imm)
13648{
13649 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
477330fc
RM		 13650 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
13651 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
13652 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
5287ad62
JB		 13653}
13654
13655/* For immediate of above form, return 0bABCD. */
13656
13657static unsigned
13658neon_squash_bits (unsigned imm)
13659{
13660 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
477330fc 13661 | ((imm & 0x01000000) >> 21);
5287ad62
JB		 13662}
13663
136da414 13664/* Compress quarter-float representation to 0b...000 abcdefgh. */
5287ad62
JB		 13665
13666static unsigned
13667neon_qfloat_bits (unsigned imm)
13668{
136da414 13669 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
5287ad62
JB		 13670}
13671
13672/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13673 the instruction. *OP is passed as the initial value of the op field, and
13674 may be set to a different value depending on the constant (i.e.
13675 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
5f4273c7 13676 MVN). If the immediate looks like a repeated pattern then also
036dc3f7 13677 try smaller element sizes. */
5287ad62
JB		 13678
13679static int
c96612cc
JB		 13680neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
13681 unsigned *immbits, int *op, int size,
13682 enum neon_el_type type)
5287ad62 13683{
c96612cc
JB		 13684 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13685 float. */
13686 if (type == NT_float && !float_p)
13687 return FAIL;
13688
136da414
JB		 13689 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
13690 {
13691 if (size != 32 || *op == 1)
477330fc 13692 return FAIL;
136da414
JB		 13693 *immbits = neon_qfloat_bits (immlo);
13694 return 0xf;
13695 }
036dc3f7
PB		 13696
13697 if (size == 64)
5287ad62 13698 {
036dc3f7
PB		 13699 if (neon_bits_same_in_bytes (immhi)
13700 && neon_bits_same_in_bytes (immlo))
13701 {
13702 if (*op == 1)
13703 return FAIL;
13704 *immbits = (neon_squash_bits (immhi) << 4)
13705 | neon_squash_bits (immlo);
13706 *op = 1;
13707 return 0xe;
13708 }
13709
13710 if (immhi != immlo)
13711 return FAIL;
5287ad62 13712 }
036dc3f7
PB		 13713
13714 if (size >= 32)
5287ad62 13715 {
036dc3f7
PB		 13716 if (immlo == (immlo & 0x000000ff))
13717 {
13718 *immbits = immlo;
13719 return 0x0;
13720 }
13721 else if (immlo == (immlo & 0x0000ff00))
13722 {
13723 *immbits = immlo >> 8;
13724 return 0x2;
13725 }
13726 else if (immlo == (immlo & 0x00ff0000))
13727 {
13728 *immbits = immlo >> 16;
13729 return 0x4;
13730 }
13731 else if (immlo == (immlo & 0xff000000))
13732 {
13733 *immbits = immlo >> 24;
13734 return 0x6;
13735 }
13736 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
13737 {
13738 *immbits = (immlo >> 8) & 0xff;
13739 return 0xc;
13740 }
13741 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
13742 {
13743 *immbits = (immlo >> 16) & 0xff;
13744 return 0xd;
13745 }
13746
13747 if ((immlo & 0xffff) != (immlo >> 16))
13748 return FAIL;
13749 immlo &= 0xffff;
5287ad62 13750 }
036dc3f7
PB		 13751
13752 if (size >= 16)
5287ad62 13753 {
036dc3f7
PB		 13754 if (immlo == (immlo & 0x000000ff))
13755 {
13756 *immbits = immlo;
13757 return 0x8;
13758 }
13759 else if (immlo == (immlo & 0x0000ff00))
13760 {
13761 *immbits = immlo >> 8;
13762 return 0xa;
13763 }
13764
13765 if ((immlo & 0xff) != (immlo >> 8))
13766 return FAIL;
13767 immlo &= 0xff;
5287ad62 13768 }
036dc3f7
PB		 13769
13770 if (immlo == (immlo & 0x000000ff))
5287ad62 13771 {
036dc3f7
PB		 13772 /* Don't allow MVN with 8-bit immediate. */
13773 if (*op == 1)
13774 return FAIL;
13775 *immbits = immlo;
13776 return 0xe;
5287ad62 13777 }
5287ad62
JB		 13778
13779 return FAIL;
13780}
13781
13782/* Write immediate bits [7:0] to the following locations:
13783
13784 |28/24|23 19|18 16|15 4|3 0|
13785 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13786
13787 This function is used by VMOV/VMVN/VORR/VBIC. */
13788
13789static void
13790neon_write_immbits (unsigned immbits)
13791{
13792 inst.instruction |= immbits & 0xf;
13793 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
13794 inst.instruction |= ((immbits >> 7) & 0x1) << 24;
13795}
13796
13797/* Invert low-order SIZE bits of XHI:XLO. */
13798
13799static void
13800neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
13801{
13802 unsigned immlo = xlo ? *xlo : 0;
13803 unsigned immhi = xhi ? *xhi : 0;
13804
13805 switch (size)
13806 {
13807 case 8:
13808 immlo = (~immlo) & 0xff;
13809 break;
13810
13811 case 16:
13812 immlo = (~immlo) & 0xffff;
13813 break;
13814
13815 case 64:
13816 immhi = (~immhi) & 0xffffffff;
13817 /* fall through. */
13818
13819 case 32:
13820 immlo = (~immlo) & 0xffffffff;
13821 break;
13822
13823 default:
13824 abort ();
13825 }
13826
13827 if (xlo)
13828 *xlo = immlo;
13829
13830 if (xhi)
13831 *xhi = immhi;
13832}
13833
13834static void
13835do_neon_logic (void)
13836{
13837 if (inst.operands[2].present && inst.operands[2].isreg)
13838 {
037e8744 13839 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 13840 neon_check_type (3, rs, N_IGNORE_TYPE);
13841 /* U bit and size field were set as part of the bitmask. */
88714cb8 13842 NEON_ENCODE (INTEGER, inst);
037e8744 13843 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 13844 }
13845 else
13846 {
4316f0d2
DG		 13847 const int three_ops_form = (inst.operands[2].present
13848 && !inst.operands[2].isreg);
13849 const int immoperand = (three_ops_form ? 2 : 1);
13850 enum neon_shape rs = (three_ops_form
13851 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
13852 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
037e8744 13853 struct neon_type_el et = neon_check_type (2, rs,
477330fc 13854 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
21d799b5 13855 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB		 13856 unsigned immbits;
13857 int cmode;
5f4273c7 13858
5287ad62 13859 if (et.type == NT_invtype)
477330fc 13860 return;
5f4273c7 13861
4316f0d2
DG		 13862 if (three_ops_form)
13863 constraint (inst.operands[0].reg != inst.operands[1].reg,
13864 _("first and second operands shall be the same register"));
13865
88714cb8 13866 NEON_ENCODE (IMMED, inst);
5287ad62 13867
4316f0d2 13868 immbits = inst.operands[immoperand].imm;
036dc3f7
PB		 13869 if (et.size == 64)
13870 {
13871 /* .i64 is a pseudo-op, so the immediate must be a repeating
13872 pattern. */
4316f0d2
DG		 13873 if (immbits != (inst.operands[immoperand].regisimm ?
13874 inst.operands[immoperand].reg : 0))
036dc3f7
PB		 13875 {
13876 /* Set immbits to an invalid constant. */
13877 immbits = 0xdeadbeef;
13878 }
13879 }
13880
5287ad62 13881 switch (opcode)
477330fc
RM		 13882 {
13883 case N_MNEM_vbic:
13884 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13885 break;
13886
13887 case N_MNEM_vorr:
13888 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13889 break;
13890
13891 case N_MNEM_vand:
13892 /* Pseudo-instruction for VBIC. */
13893 neon_invert_size (&immbits, 0, et.size);
13894 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13895 break;
13896
13897 case N_MNEM_vorn:
13898 /* Pseudo-instruction for VORR. */
13899 neon_invert_size (&immbits, 0, et.size);
13900 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
13901 break;
13902
13903 default:
13904 abort ();
13905 }
5287ad62
JB		 13906
13907 if (cmode == FAIL)
477330fc 13908 return;
5287ad62 13909
037e8744 13910 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 13911 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
13912 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
13913 inst.instruction |= cmode << 8;
13914 neon_write_immbits (immbits);
5f4273c7 13915
88714cb8 13916 neon_dp_fixup (&inst);
5287ad62
JB		 13917 }
13918}
13919
13920static void
13921do_neon_bitfield (void)
13922{
037e8744 13923 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 13924 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 13925 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 13926}
13927
13928static void
dcbf9037 13929neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 13930 unsigned destbits)
5287ad62 13931{
037e8744 13932 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 13933 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 13934 types | N_KEY);
5287ad62
JB		 13935 if (et.type == NT_float)
13936 {
88714cb8 13937 NEON_ENCODE (FLOAT, inst);
037e8744 13938 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 13939 }
13940 else
13941 {
88714cb8 13942 NEON_ENCODE (INTEGER, inst);
037e8744 13943 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB		 13944 }
13945}
13946
13947static void
13948do_neon_dyadic_if_su (void)
13949{
dcbf9037 13950 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 13951}
13952
13953static void
13954do_neon_dyadic_if_su_d (void)
13955{
13956 /* This version only allow D registers, but that constraint is enforced during
13957 operand parsing so we don't need to do anything extra here. */
dcbf9037 13958 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 13959}
13960
5287ad62
JB		 13961static void
13962do_neon_dyadic_if_i_d (void)
13963{
428e3f1f
PB		 13964 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13965 affected if we specify unsigned args. */
13966 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB		 13967}
13968
037e8744
JB		 13969enum vfp_or_neon_is_neon_bits
13970{
13971 NEON_CHECK_CC = 1,
73924fbc
MGD		 13972 NEON_CHECK_ARCH = 2,
13973 NEON_CHECK_ARCH8 = 4
037e8744
JB		 13974};
13975
13976/* Call this function if an instruction which may have belonged to the VFP or
13977 Neon instruction sets, but turned out to be a Neon instruction (due to the
13978 operand types involved, etc.). We have to check and/or fix-up a couple of
13979 things:
13980
13981 - Make sure the user hasn't attempted to make a Neon instruction
13982 conditional.
13983 - Alter the value in the condition code field if necessary.
13984 - Make sure that the arch supports Neon instructions.
13985
13986 Which of these operations take place depends on bits from enum
13987 vfp_or_neon_is_neon_bits.
13988
13989 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13990 current instruction's condition is COND_ALWAYS, the condition field is
13991 changed to inst.uncond_value. This is necessary because instructions shared
13992 between VFP and Neon may be conditional for the VFP variants only, and the
13993 unconditional Neon version must have, e.g., 0xF in the condition field. */
13994
13995static int
13996vfp_or_neon_is_neon (unsigned check)
13997{
13998 /* Conditions are always legal in Thumb mode (IT blocks). */
13999 if (!thumb_mode && (check & NEON_CHECK_CC))
14000 {
14001 if (inst.cond != COND_ALWAYS)
477330fc
RM		 14002 {
14003 first_error (_(BAD_COND));
14004 return FAIL;
14005 }
037e8744 14006 if (inst.uncond_value != -1)
477330fc 14007 inst.instruction |= inst.uncond_value << 28;
037e8744 14008 }
5f4273c7 14009
037e8744 14010 if ((check & NEON_CHECK_ARCH)
73924fbc
MGD		 14011 && !mark_feature_used (&fpu_neon_ext_v1))
14012 {
14013 first_error (_(BAD_FPU));
14014 return FAIL;
14015 }
14016
14017 if ((check & NEON_CHECK_ARCH8)
14018 && !mark_feature_used (&fpu_neon_ext_armv8))
037e8744
JB		 14019 {
14020 first_error (_(BAD_FPU));
14021 return FAIL;
14022 }
5f4273c7 14023
037e8744
JB		 14024 return SUCCESS;
14025}
14026
5287ad62
JB		 14027static void
14028do_neon_addsub_if_i (void)
14029{
037e8744
JB		 14030 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14031 return;
14032
14033 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14034 return;
14035
5287ad62
JB		 14036 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14037 affected if we specify unsigned args. */
dcbf9037 14038 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB		 14039}
14040
14041/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14042 result to be:
14043 V<op> A,B (A is operand 0, B is operand 2)
14044 to mean:
14045 V<op> A,B,A
14046 not:
14047 V<op> A,B,B
14048 so handle that case specially. */
14049
14050static void
14051neon_exchange_operands (void)
14052{
14053 void *scratch = alloca (sizeof (inst.operands[0]));
14054 if (inst.operands[1].present)
14055 {
14056 /* Swap operands[1] and operands[2]. */
14057 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14058 inst.operands[1] = inst.operands[2];
14059 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14060 }
14061 else
14062 {
14063 inst.operands[1] = inst.operands[2];
14064 inst.operands[2] = inst.operands[0];
14065 }
14066}
14067
14068static void
14069neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14070{
14071 if (inst.operands[2].isreg)
14072 {
14073 if (invert)
477330fc 14074 neon_exchange_operands ();
dcbf9037 14075 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB		 14076 }
14077 else
14078 {
037e8744 14079 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 14080 struct neon_type_el et = neon_check_type (2, rs,
477330fc 14081 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 14082
88714cb8 14083 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 14084 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14085 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14086 inst.instruction |= LOW4 (inst.operands[1].reg);
14087 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14088 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14089 inst.instruction |= (et.type == NT_float) << 10;
14090 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14091
88714cb8 14092 neon_dp_fixup (&inst);
5287ad62
JB		 14093 }
14094}
14095
14096static void
14097do_neon_cmp (void)
14098{
14099 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14100}
14101
14102static void
14103do_neon_cmp_inv (void)
14104{
14105 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14106}
14107
14108static void
14109do_neon_ceq (void)
14110{
14111 neon_compare (N_IF_32, N_IF_32, FALSE);
14112}
14113
14114/* For multiply instructions, we have the possibility of 16-bit or 32-bit
14115 scalars, which are encoded in 5 bits, M : Rm.
14116 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14117 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14118 index in M. */
14119
14120static unsigned
14121neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14122{
dcbf9037
JB		 14123 unsigned regno = NEON_SCALAR_REG (scalar);
14124 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB		 14125
14126 switch (elsize)
14127 {
14128 case 16:
14129 if (regno > 7 || elno > 3)
477330fc 14130 goto bad_scalar;
5287ad62 14131 return regno | (elno << 3);
5f4273c7 14132
5287ad62
JB		 14133 case 32:
14134 if (regno > 15 || elno > 1)
477330fc 14135 goto bad_scalar;
5287ad62
JB		 14136 return regno | (elno << 4);
14137
14138 default:
14139 bad_scalar:
dcbf9037 14140 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB		 14141 }
14142
14143 return 0;
14144}
14145
14146/* Encode multiply / multiply-accumulate scalar instructions. */
14147
14148static void
14149neon_mul_mac (struct neon_type_el et, int ubit)
14150{
dcbf9037
JB		 14151 unsigned scalar;
14152
14153 /* Give a more helpful error message if we have an invalid type. */
14154 if (et.type == NT_invtype)
14155 return;
5f4273c7 14156
dcbf9037 14157 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB		 14158 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14159 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14160 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14161 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14162 inst.instruction |= LOW4 (scalar);
14163 inst.instruction |= HI1 (scalar) << 5;
14164 inst.instruction |= (et.type == NT_float) << 8;
14165 inst.instruction |= neon_logbits (et.size) << 20;
14166 inst.instruction |= (ubit != 0) << 24;
14167
88714cb8 14168 neon_dp_fixup (&inst);
5287ad62
JB		 14169}
14170
14171static void
14172do_neon_mac_maybe_scalar (void)
14173{
037e8744
JB		 14174 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14175 return;
14176
14177 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14178 return;
14179
5287ad62
JB		 14180 if (inst.operands[2].isscalar)
14181 {
037e8744 14182 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 14183 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14184 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
88714cb8 14185 NEON_ENCODE (SCALAR, inst);
037e8744 14186 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 14187 }
14188 else
428e3f1f
PB		 14189 {
14190 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14191 affected if we specify unsigned args. */
14192 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14193 }
5287ad62
JB		 14194}
14195
62f3b8c8
PB		 14196static void
14197do_neon_fmac (void)
14198{
14199 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14200 return;
14201
14202 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14203 return;
14204
14205 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14206}
14207
5287ad62
JB		 14208static void
14209do_neon_tst (void)
14210{
037e8744 14211 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14212 struct neon_type_el et = neon_check_type (3, rs,
14213 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 14214 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 14215}
14216
14217/* VMUL with 3 registers allows the P8 type. The scalar version supports the
14218 same types as the MAC equivalents. The polynomial type for this instruction
14219 is encoded the same as the integer type. */
14220
14221static void
14222do_neon_mul (void)
14223{
037e8744
JB		 14224 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14225 return;
14226
14227 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14228 return;
14229
5287ad62
JB		 14230 if (inst.operands[2].isscalar)
14231 do_neon_mac_maybe_scalar ();
14232 else
dcbf9037 14233 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
5287ad62
JB		 14234}
14235
14236static void
14237do_neon_qdmulh (void)
14238{
14239 if (inst.operands[2].isscalar)
14240 {
037e8744 14241 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 14242 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14243 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 14244 NEON_ENCODE (SCALAR, inst);
037e8744 14245 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 14246 }
14247 else
14248 {
037e8744 14249 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14250 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14251 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 14252 NEON_ENCODE (INTEGER, inst);
5287ad62 14253 /* The U bit (rounding) comes from bit mask. */
037e8744 14254 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 14255 }
14256}
14257
14258static void
14259do_neon_fcmp_absolute (void)
14260{
037e8744 14261 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14262 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14263 /* Size field comes from bit mask. */
037e8744 14264 neon_three_same (neon_quad (rs), 1, -1);
5287ad62
JB		 14265}
14266
14267static void
14268do_neon_fcmp_absolute_inv (void)
14269{
14270 neon_exchange_operands ();
14271 do_neon_fcmp_absolute ();
14272}
14273
14274static void
14275do_neon_step (void)
14276{
037e8744 14277 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14278 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
037e8744 14279 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14280}
14281
14282static void
14283do_neon_abs_neg (void)
14284{
037e8744
JB		 14285 enum neon_shape rs;
14286 struct neon_type_el et;
5f4273c7 14287
037e8744
JB		 14288 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14289 return;
14290
14291 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14292 return;
14293
14294 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14295 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
5f4273c7 14296
5287ad62
JB		 14297 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14298 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14299 inst.instruction |= LOW4 (inst.operands[1].reg);
14300 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14301 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14302 inst.instruction |= (et.type == NT_float) << 10;
14303 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14304
88714cb8 14305 neon_dp_fixup (&inst);
5287ad62
JB		 14306}
14307
14308static void
14309do_neon_sli (void)
14310{
037e8744 14311 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14312 struct neon_type_el et = neon_check_type (2, rs,
14313 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14314 int imm = inst.operands[2].imm;
14315 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 14316 _("immediate out of range for insert"));
037e8744 14317 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14318}
14319
14320static void
14321do_neon_sri (void)
14322{
037e8744 14323 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14324 struct neon_type_el et = neon_check_type (2, rs,
14325 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14326 int imm = inst.operands[2].imm;
14327 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14328 _("immediate out of range for insert"));
037e8744 14329 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB		 14330}
14331
14332static void
14333do_neon_qshlu_imm (void)
14334{
037e8744 14335 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14336 struct neon_type_el et = neon_check_type (2, rs,
14337 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14338 int imm = inst.operands[2].imm;
14339 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 14340 _("immediate out of range for shift"));
5287ad62
JB		 14341 /* Only encodes the 'U present' variant of the instruction.
14342 In this case, signed types have OP (bit 8) set to 0.
14343 Unsigned types have OP set to 1. */
14344 inst.instruction |= (et.type == NT_unsigned) << 8;
14345 /* The rest of the bits are the same as other immediate shifts. */
037e8744 14346 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14347}
14348
14349static void
14350do_neon_qmovn (void)
14351{
14352 struct neon_type_el et = neon_check_type (2, NS_DQ,
14353 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14354 /* Saturating move where operands can be signed or unsigned, and the
14355 destination has the same signedness. */
88714cb8 14356 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14357 if (et.type == NT_unsigned)
14358 inst.instruction |= 0xc0;
14359 else
14360 inst.instruction |= 0x80;
14361 neon_two_same (0, 1, et.size / 2);
14362}
14363
14364static void
14365do_neon_qmovun (void)
14366{
14367 struct neon_type_el et = neon_check_type (2, NS_DQ,
14368 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14369 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 14370 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14371 neon_two_same (0, 1, et.size / 2);
14372}
14373
14374static void
14375do_neon_rshift_sat_narrow (void)
14376{
14377 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14378 or unsigned. If operands are unsigned, results must also be unsigned. */
14379 struct neon_type_el et = neon_check_type (2, NS_DQI,
14380 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14381 int imm = inst.operands[2].imm;
14382 /* This gets the bounds check, size encoding and immediate bits calculation
14383 right. */
14384 et.size /= 2;
5f4273c7 14385
5287ad62
JB		 14386 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14387 VQMOVN.I<size> <Dd>, <Qm>. */
14388 if (imm == 0)
14389 {
14390 inst.operands[2].present = 0;
14391 inst.instruction = N_MNEM_vqmovn;
14392 do_neon_qmovn ();
14393 return;
14394 }
5f4273c7 14395
5287ad62 14396 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14397 _("immediate out of range"));
5287ad62
JB		 14398 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14399}
14400
14401static void
14402do_neon_rshift_sat_narrow_u (void)
14403{
14404 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14405 or unsigned. If operands are unsigned, results must also be unsigned. */
14406 struct neon_type_el et = neon_check_type (2, NS_DQI,
14407 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14408 int imm = inst.operands[2].imm;
14409 /* This gets the bounds check, size encoding and immediate bits calculation
14410 right. */
14411 et.size /= 2;
14412
14413 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14414 VQMOVUN.I<size> <Dd>, <Qm>. */
14415 if (imm == 0)
14416 {
14417 inst.operands[2].present = 0;
14418 inst.instruction = N_MNEM_vqmovun;
14419 do_neon_qmovun ();
14420 return;
14421 }
14422
14423 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14424 _("immediate out of range"));
5287ad62
JB		 14425 /* FIXME: The manual is kind of unclear about what value U should have in
14426 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14427 must be 1. */
14428 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14429}
14430
14431static void
14432do_neon_movn (void)
14433{
14434 struct neon_type_el et = neon_check_type (2, NS_DQ,
14435 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 14436 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14437 neon_two_same (0, 1, et.size / 2);
14438}
14439
14440static void
14441do_neon_rshift_narrow (void)
14442{
14443 struct neon_type_el et = neon_check_type (2, NS_DQI,
14444 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14445 int imm = inst.operands[2].imm;
14446 /* This gets the bounds check, size encoding and immediate bits calculation
14447 right. */
14448 et.size /= 2;
5f4273c7 14449
5287ad62
JB		 14450 /* If immediate is zero then we are a pseudo-instruction for
14451 VMOVN.I<size> <Dd>, <Qm> */
14452 if (imm == 0)
14453 {
14454 inst.operands[2].present = 0;
14455 inst.instruction = N_MNEM_vmovn;
14456 do_neon_movn ();
14457 return;
14458 }
5f4273c7 14459
5287ad62 14460 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14461 _("immediate out of range for narrowing operation"));
5287ad62
JB		 14462 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14463}
14464
14465static void
14466do_neon_shll (void)
14467{
14468 /* FIXME: Type checking when lengthening. */
14469 struct neon_type_el et = neon_check_type (2, NS_QDI,
14470 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14471 unsigned imm = inst.operands[2].imm;
14472
14473 if (imm == et.size)
14474 {
14475 /* Maximum shift variant. */
88714cb8 14476 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14477 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14478 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14479 inst.instruction |= LOW4 (inst.operands[1].reg);
14480 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14481 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14482
88714cb8 14483 neon_dp_fixup (&inst);
5287ad62
JB		 14484 }
14485 else
14486 {
14487 /* A more-specific type check for non-max versions. */
14488 et = neon_check_type (2, NS_QDI,
477330fc 14489 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 14490 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 14491 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14492 }
14493}
14494
037e8744 14495/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB		 14496 the current instruction is. */
14497
6b9a8b67
MGD		 14498#define CVT_FLAVOUR_VAR \
14499 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14500 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14501 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14502 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14503 /* Half-precision conversions. */ \
14504 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14505 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14506 /* VFP instructions. */ \
14507 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14508 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14509 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14510 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14511 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14512 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14513 /* VFP instructions with bitshift. */ \
14514 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14515 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14516 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14517 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14518 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14519 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14520 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14521 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14522
14523#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14524 neon_cvt_flavour_##C,
14525
14526/* The different types of conversions we can do. */
14527enum neon_cvt_flavour
14528{
14529 CVT_FLAVOUR_VAR
14530 neon_cvt_flavour_invalid,
14531 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14532};
14533
14534#undef CVT_VAR
14535
14536static enum neon_cvt_flavour
14537get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 14538{
6b9a8b67
MGD		 14539#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14540 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14541 if (et.type != NT_invtype) \
14542 { \
14543 inst.error = NULL; \
14544 return (neon_cvt_flavour_##C); \
5287ad62 14545 }
6b9a8b67 14546
5287ad62 14547 struct neon_type_el et;
037e8744 14548 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 14549 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB		 14550 /* The instruction versions which take an immediate take one register
14551 argument, which is extended to the width of the full register. Thus the
14552 "source" and "destination" registers must have the same width. Hack that
14553 here by making the size equal to the key (wider, in this case) operand. */
14554 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 14555
6b9a8b67
MGD		 14556 CVT_FLAVOUR_VAR;
14557
14558 return neon_cvt_flavour_invalid;
5287ad62
JB		 14559#undef CVT_VAR
14560}
14561
7e8e6784
MGD		 14562enum neon_cvt_mode
14563{
14564 neon_cvt_mode_a,
14565 neon_cvt_mode_n,
14566 neon_cvt_mode_p,
14567 neon_cvt_mode_m,
14568 neon_cvt_mode_z,
30bdf752
MGD		 14569 neon_cvt_mode_x,
14570 neon_cvt_mode_r
7e8e6784
MGD		 14571};
14572
037e8744
JB		 14573/* Neon-syntax VFP conversions. */
14574
5287ad62 14575static void
6b9a8b67 14576do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 14577{
037e8744 14578 const char *opname = 0;
5f4273c7 14579
037e8744 14580 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
5287ad62 14581 {
037e8744
JB		 14582 /* Conversions with immediate bitshift. */
14583 const char *enc[] =
477330fc 14584 {
6b9a8b67
MGD		 14585#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14586 CVT_FLAVOUR_VAR
14587 NULL
14588#undef CVT_VAR
477330fc 14589 };
037e8744 14590
6b9a8b67 14591 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM		 14592 {
14593 opname = enc[flavour];
14594 constraint (inst.operands[0].reg != inst.operands[1].reg,
14595 _("operands 0 and 1 must be the same register"));
14596 inst.operands[1] = inst.operands[2];
14597 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14598 }
5287ad62
JB		 14599 }
14600 else
14601 {
037e8744
JB		 14602 /* Conversions without bitshift. */
14603 const char *enc[] =
477330fc 14604 {
6b9a8b67
MGD		 14605#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14606 CVT_FLAVOUR_VAR
14607 NULL
14608#undef CVT_VAR
477330fc 14609 };
037e8744 14610
6b9a8b67 14611 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 14612 opname = enc[flavour];
037e8744
JB		 14613 }
14614
14615 if (opname)
14616 do_vfp_nsyn_opcode (opname);
14617}
14618
14619static void
14620do_vfp_nsyn_cvtz (void)
14621{
14622 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
6b9a8b67 14623 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB		 14624 const char *enc[] =
14625 {
6b9a8b67
MGD		 14626#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14627 CVT_FLAVOUR_VAR
14628 NULL
14629#undef CVT_VAR
037e8744
JB		 14630 };
14631
6b9a8b67 14632 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB		 14633 do_vfp_nsyn_opcode (enc[flavour]);
14634}
f31fef98 14635
037e8744 14636static void
bacebabc 14637do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD		 14638 enum neon_cvt_mode mode)
14639{
14640 int sz, op;
14641 int rm;
14642
14643 set_it_insn_type (OUTSIDE_IT_INSN);
14644
14645 switch (flavour)
14646 {
14647 case neon_cvt_flavour_s32_f64:
14648 sz = 1;
14649 op = 0;
14650 break;
14651 case neon_cvt_flavour_s32_f32:
14652 sz = 0;
14653 op = 1;
14654 break;
14655 case neon_cvt_flavour_u32_f64:
14656 sz = 1;
14657 op = 0;
14658 break;
14659 case neon_cvt_flavour_u32_f32:
14660 sz = 0;
14661 op = 0;
14662 break;
14663 default:
14664 first_error (_("invalid instruction shape"));
14665 return;
14666 }
14667
14668 switch (mode)
14669 {
14670 case neon_cvt_mode_a: rm = 0; break;
14671 case neon_cvt_mode_n: rm = 1; break;
14672 case neon_cvt_mode_p: rm = 2; break;
14673 case neon_cvt_mode_m: rm = 3; break;
14674 default: first_error (_("invalid rounding mode")); return;
14675 }
14676
14677 NEON_ENCODE (FPV8, inst);
14678 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
14679 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
14680 inst.instruction |= sz << 8;
14681 inst.instruction |= op << 7;
14682 inst.instruction |= rm << 16;
14683 inst.instruction |= 0xf0000000;
14684 inst.is_neon = TRUE;
14685}
14686
14687static void
14688do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB		 14689{
14690 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
8e79c3df 14691 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
6b9a8b67 14692 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 14693
e3e535bc 14694 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 14695 if (mode == neon_cvt_mode_z
e3e535bc 14696 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
bacebabc
RM		 14697 && (flavour == neon_cvt_flavour_s32_f32
14698 || flavour == neon_cvt_flavour_u32_f32
14699 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 14700 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC		 14701 && (rs == NS_FD || rs == NS_FF))
14702 {
14703 do_vfp_nsyn_cvtz ();
14704 return;
14705 }
14706
037e8744 14707 /* VFP rather than Neon conversions. */
6b9a8b67 14708 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 14709 {
7e8e6784
MGD		 14710 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14711 do_vfp_nsyn_cvt (rs, flavour);
14712 else
14713 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
14714
037e8744
JB		 14715 return;
14716 }
14717
14718 switch (rs)
14719 {
14720 case NS_DDI:
14721 case NS_QQI:
14722 {
477330fc
RM		 14723 unsigned immbits;
14724 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
35997600 14725
477330fc
RM		 14726 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14727 return;
037e8744 14728
477330fc
RM		 14729 /* Fixed-point conversion with #0 immediate is encoded as an
14730 integer conversion. */
14731 if (inst.operands[2].present && inst.operands[2].imm == 0)
14732 goto int_encode;
35997600 14733 immbits = 32 - inst.operands[2].imm;
477330fc
RM		 14734 NEON_ENCODE (IMMED, inst);
14735 if (flavour != neon_cvt_flavour_invalid)
14736 inst.instruction |= enctab[flavour];
14737 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14738 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14739 inst.instruction |= LOW4 (inst.operands[1].reg);
14740 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14741 inst.instruction |= neon_quad (rs) << 6;
14742 inst.instruction |= 1 << 21;
14743 inst.instruction |= immbits << 16;
14744
14745 neon_dp_fixup (&inst);
037e8744
JB		 14746 }
14747 break;
14748
14749 case NS_DD:
14750 case NS_QQ:
7e8e6784
MGD		 14751 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
14752 {
14753 NEON_ENCODE (FLOAT, inst);
14754 set_it_insn_type (OUTSIDE_IT_INSN);
14755
14756 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
14757 return;
14758
14759 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14760 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14761 inst.instruction |= LOW4 (inst.operands[1].reg);
14762 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14763 inst.instruction |= neon_quad (rs) << 6;
14764 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
14765 inst.instruction |= mode << 8;
14766 if (thumb_mode)
14767 inst.instruction |= 0xfc000000;
14768 else
14769 inst.instruction |= 0xf0000000;
14770 }
14771 else
14772 {
037e8744 14773 int_encode:
7e8e6784
MGD		 14774 {
14775 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
037e8744 14776
7e8e6784 14777 NEON_ENCODE (INTEGER, inst);
037e8744 14778
7e8e6784
MGD		 14779 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14780 return;
037e8744 14781
7e8e6784
MGD		 14782 if (flavour != neon_cvt_flavour_invalid)
14783 inst.instruction |= enctab[flavour];
037e8744 14784
7e8e6784
MGD		 14785 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14786 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14787 inst.instruction |= LOW4 (inst.operands[1].reg);
14788 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14789 inst.instruction |= neon_quad (rs) << 6;
14790 inst.instruction |= 2 << 18;
037e8744 14791
7e8e6784
MGD		 14792 neon_dp_fixup (&inst);
14793 }
14794 }
14795 break;
037e8744 14796
8e79c3df
CM		 14797 /* Half-precision conversions for Advanced SIMD -- neon. */
14798 case NS_QD:
14799 case NS_DQ:
14800
14801 if ((rs == NS_DQ)
14802 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
14803 {
14804 as_bad (_("operand size must match register width"));
14805 break;
14806 }
14807
14808 if ((rs == NS_QD)
14809 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
14810 {
14811 as_bad (_("operand size must match register width"));
14812 break;
14813 }
14814
14815 if (rs == NS_DQ)
477330fc 14816 inst.instruction = 0x3b60600;
8e79c3df
CM		 14817 else
14818 inst.instruction = 0x3b60700;
14819
14820 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14821 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14822 inst.instruction |= LOW4 (inst.operands[1].reg);
14823 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 14824 neon_dp_fixup (&inst);
8e79c3df
CM		 14825 break;
14826
037e8744
JB		 14827 default:
14828 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD		 14829 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
14830 do_vfp_nsyn_cvt (rs, flavour);
14831 else
14832 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 14833 }
5287ad62
JB		 14834}
14835
e3e535bc
NC		 14836static void
14837do_neon_cvtr (void)
14838{
7e8e6784 14839 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC		 14840}
14841
14842static void
14843do_neon_cvt (void)
14844{
7e8e6784
MGD		 14845 do_neon_cvt_1 (neon_cvt_mode_z);
14846}
14847
14848static void
14849do_neon_cvta (void)
14850{
14851 do_neon_cvt_1 (neon_cvt_mode_a);
14852}
14853
14854static void
14855do_neon_cvtn (void)
14856{
14857 do_neon_cvt_1 (neon_cvt_mode_n);
14858}
14859
14860static void
14861do_neon_cvtp (void)
14862{
14863 do_neon_cvt_1 (neon_cvt_mode_p);
14864}
14865
14866static void
14867do_neon_cvtm (void)
14868{
14869 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC		 14870}
14871
8e79c3df 14872static void
c70a8987 14873do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 14874{
c70a8987
MGD		 14875 if (is_double)
14876 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 14877
c70a8987
MGD		 14878 encode_arm_vfp_reg (inst.operands[0].reg,
14879 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
14880 encode_arm_vfp_reg (inst.operands[1].reg,
14881 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
14882 inst.instruction |= to ? 0x10000 : 0;
14883 inst.instruction |= t ? 0x80 : 0;
14884 inst.instruction |= is_double ? 0x100 : 0;
14885 do_vfp_cond_or_thumb ();
14886}
8e79c3df 14887
c70a8987
MGD		 14888static void
14889do_neon_cvttb_1 (bfd_boolean t)
14890{
14891 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
8e79c3df 14892
c70a8987
MGD		 14893 if (rs == NS_NULL)
14894 return;
14895 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
14896 {
14897 inst.error = NULL;
14898 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
14899 }
14900 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
14901 {
14902 inst.error = NULL;
14903 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
14904 }
14905 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
14906 {
14907 inst.error = NULL;
14908 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
14909 }
14910 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
14911 {
14912 inst.error = NULL;
14913 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
14914 }
14915 else
14916 return;
14917}
14918
14919static void
14920do_neon_cvtb (void)
14921{
14922 do_neon_cvttb_1 (FALSE);
8e79c3df
CM		 14923}
14924
14925
14926static void
14927do_neon_cvtt (void)
14928{
c70a8987 14929 do_neon_cvttb_1 (TRUE);
8e79c3df
CM		 14930}
14931
5287ad62
JB		 14932static void
14933neon_move_immediate (void)
14934{
037e8744
JB		 14935 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
14936 struct neon_type_el et = neon_check_type (2, rs,
14937 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 14938 unsigned immlo, immhi = 0, immbits;
c96612cc 14939 int op, cmode, float_p;
5287ad62 14940
037e8744 14941 constraint (et.type == NT_invtype,
477330fc 14942 _("operand size must be specified for immediate VMOV"));
037e8744 14943
5287ad62
JB		 14944 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14945 op = (inst.instruction & (1 << 5)) != 0;
14946
14947 immlo = inst.operands[1].imm;
14948 if (inst.operands[1].regisimm)
14949 immhi = inst.operands[1].reg;
14950
14951 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 14952 _("immediate has bits set outside the operand size"));
5287ad62 14953
c96612cc
JB		 14954 float_p = inst.operands[1].immisfloat;
14955
14956 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 14957 et.size, et.type)) == FAIL)
5287ad62
JB		 14958 {
14959 /* Invert relevant bits only. */
14960 neon_invert_size (&immlo, &immhi, et.size);
14961 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM		 14962 with one or the other; those cases are caught by
14963 neon_cmode_for_move_imm. */
5287ad62 14964 op = !op;
c96612cc
JB		 14965 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
14966 &op, et.size, et.type)) == FAIL)
477330fc
RM		 14967 {
14968 first_error (_("immediate out of range"));
14969 return;
14970 }
5287ad62
JB		 14971 }
14972
14973 inst.instruction &= ~(1 << 5);
14974 inst.instruction |= op << 5;
14975
14976 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14977 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 14978 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14979 inst.instruction |= cmode << 8;
14980
14981 neon_write_immbits (immbits);
14982}
14983
14984static void
14985do_neon_mvn (void)
14986{
14987 if (inst.operands[1].isreg)
14988 {
037e8744 14989 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 14990
88714cb8 14991 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14992 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14993 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14994 inst.instruction |= LOW4 (inst.operands[1].reg);
14995 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14996 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14997 }
14998 else
14999 {
88714cb8 15000 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 15001 neon_move_immediate ();
15002 }
15003
88714cb8 15004 neon_dp_fixup (&inst);
5287ad62
JB		 15005}
15006
15007/* Encode instructions of form:
15008
15009 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 15010 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB		 15011
15012static void
15013neon_mixed_length (struct neon_type_el et, unsigned size)
15014{
15015 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15016 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15017 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15018 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15019 inst.instruction |= LOW4 (inst.operands[2].reg);
15020 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15021 inst.instruction |= (et.type == NT_unsigned) << 24;
15022 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 15023
88714cb8 15024 neon_dp_fixup (&inst);
5287ad62
JB		 15025}
15026
15027static void
15028do_neon_dyadic_long (void)
15029{
15030 /* FIXME: Type checking for lengthening op. */
15031 struct neon_type_el et = neon_check_type (3, NS_QDD,
15032 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15033 neon_mixed_length (et, et.size);
15034}
15035
15036static void
15037do_neon_abal (void)
15038{
15039 struct neon_type_el et = neon_check_type (3, NS_QDD,
15040 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15041 neon_mixed_length (et, et.size);
15042}
15043
15044static void
15045neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15046{
15047 if (inst.operands[2].isscalar)
15048 {
dcbf9037 15049 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 15050 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 15051 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 15052 neon_mul_mac (et, et.type == NT_unsigned);
15053 }
15054 else
15055 {
15056 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 15057 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 15058 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 15059 neon_mixed_length (et, et.size);
15060 }
15061}
15062
15063static void
15064do_neon_mac_maybe_scalar_long (void)
15065{
15066 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15067}
15068
15069static void
15070do_neon_dyadic_wide (void)
15071{
15072 struct neon_type_el et = neon_check_type (3, NS_QQD,
15073 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15074 neon_mixed_length (et, et.size);
15075}
15076
15077static void
15078do_neon_dyadic_narrow (void)
15079{
15080 struct neon_type_el et = neon_check_type (3, NS_QDD,
15081 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB		 15082 /* Operand sign is unimportant, and the U bit is part of the opcode,
15083 so force the operand type to integer. */
15084 et.type = NT_integer;
5287ad62
JB		 15085 neon_mixed_length (et, et.size / 2);
15086}
15087
15088static void
15089do_neon_mul_sat_scalar_long (void)
15090{
15091 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15092}
15093
15094static void
15095do_neon_vmull (void)
15096{
15097 if (inst.operands[2].isscalar)
15098 do_neon_mac_maybe_scalar_long ();
15099 else
15100 {
15101 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 15102 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 15103
5287ad62 15104 if (et.type == NT_poly)
477330fc 15105 NEON_ENCODE (POLY, inst);
5287ad62 15106 else
477330fc 15107 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD		 15108
15109 /* For polynomial encoding the U bit must be zero, and the size must
15110 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15111 obviously, as 0b10). */
15112 if (et.size == 64)
15113 {
15114 /* Check we're on the correct architecture. */
15115 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15116 inst.error =
15117 _("Instruction form not available on this architecture.");
15118
15119 et.size = 32;
15120 }
15121
5287ad62
JB		 15122 neon_mixed_length (et, et.size);
15123 }
15124}
15125
15126static void
15127do_neon_ext (void)
15128{
037e8744 15129 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB		 15130 struct neon_type_el et = neon_check_type (3, rs,
15131 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15132 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC		 15133
15134 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15135 _("shift out of range"));
5287ad62
JB		 15136 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15137 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15138 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15139 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15140 inst.instruction |= LOW4 (inst.operands[2].reg);
15141 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 15142 inst.instruction |= neon_quad (rs) << 6;
5287ad62 15143 inst.instruction |= imm << 8;
5f4273c7 15144
88714cb8 15145 neon_dp_fixup (&inst);
5287ad62
JB		 15146}
15147
15148static void
15149do_neon_rev (void)
15150{
037e8744 15151 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15152 struct neon_type_el et = neon_check_type (2, rs,
15153 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15154 unsigned op = (inst.instruction >> 7) & 3;
15155 /* N (width of reversed regions) is encoded as part of the bitmask. We
15156 extract it here to check the elements to be reversed are smaller.
15157 Otherwise we'd get a reserved instruction. */
15158 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
9c2799c2 15159 gas_assert (elsize != 0);
5287ad62 15160 constraint (et.size >= elsize,
477330fc 15161 _("elements must be smaller than reversal region"));
037e8744 15162 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15163}
15164
15165static void
15166do_neon_dup (void)
15167{
15168 if (inst.operands[1].isscalar)
15169 {
037e8744 15170 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 15171 struct neon_type_el et = neon_check_type (2, rs,
477330fc 15172 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 15173 unsigned sizebits = et.size >> 3;
dcbf9037 15174 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 15175 int logsize = neon_logbits (et.size);
dcbf9037 15176 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB		 15177
15178 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 15179 return;
037e8744 15180
88714cb8 15181 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 15182 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15183 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15184 inst.instruction |= LOW4 (dm);
15185 inst.instruction |= HI1 (dm) << 5;
037e8744 15186 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15187 inst.instruction |= x << 17;
15188 inst.instruction |= sizebits << 16;
5f4273c7 15189
88714cb8 15190 neon_dp_fixup (&inst);
5287ad62
JB		 15191 }
15192 else
15193 {
037e8744
JB		 15194 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15195 struct neon_type_el et = neon_check_type (2, rs,
477330fc 15196 N_8 | N_16 | N_32 | N_KEY, N_EQK);
5287ad62 15197 /* Duplicate ARM register to lanes of vector. */
88714cb8 15198 NEON_ENCODE (ARMREG, inst);
5287ad62 15199 switch (et.size)
477330fc
RM		 15200 {
15201 case 8: inst.instruction |= 0x400000; break;
15202 case 16: inst.instruction |= 0x000020; break;
15203 case 32: inst.instruction |= 0x000000; break;
15204 default: break;
15205 }
5287ad62
JB		 15206 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15207 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15208 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 15209 inst.instruction |= neon_quad (rs) << 21;
5287ad62 15210 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 15211 variants, except for the condition field. */
037e8744 15212 do_vfp_cond_or_thumb ();
5287ad62
JB		 15213 }
15214}
15215
15216/* VMOV has particularly many variations. It can be one of:
15217 0. VMOV<c><q> <Qd>, <Qm>
15218 1. VMOV<c><q> <Dd>, <Dm>
15219 (Register operations, which are VORR with Rm = Rn.)
15220 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15221 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15222 (Immediate loads.)
15223 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15224 (ARM register to scalar.)
15225 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15226 (Two ARM registers to vector.)
15227 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15228 (Scalar to ARM register.)
15229 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15230 (Vector to two ARM registers.)
037e8744
JB		 15231 8. VMOV.F32 <Sd>, <Sm>
15232 9. VMOV.F64 <Dd>, <Dm>
15233 (VFP register moves.)
15234 10. VMOV.F32 <Sd>, #imm
15235 11. VMOV.F64 <Dd>, #imm
15236 (VFP float immediate load.)
15237 12. VMOV <Rd>, <Sm>
15238 (VFP single to ARM reg.)
15239 13. VMOV <Sd>, <Rm>
15240 (ARM reg to VFP single.)
15241 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15242 (Two ARM regs to two VFP singles.)
15243 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15244 (Two VFP singles to two ARM regs.)
5f4273c7 15245
037e8744
JB		 15246 These cases can be disambiguated using neon_select_shape, except cases 1/9
15247 and 3/11 which depend on the operand type too.
5f4273c7 15248
5287ad62 15249 All the encoded bits are hardcoded by this function.
5f4273c7 15250
b7fc2769
JB		 15251 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15252 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 15253
5287ad62 15254 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 15255 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB		 15256
15257static void
15258do_neon_mov (void)
15259{
037e8744
JB		 15260 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15261 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15262 NS_NULL);
15263 struct neon_type_el et;
15264 const char *ldconst = 0;
5287ad62 15265
037e8744 15266 switch (rs)
5287ad62 15267 {
037e8744
JB		 15268 case NS_DD: /* case 1/9. */
15269 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15270 /* It is not an error here if no type is given. */
15271 inst.error = NULL;
15272 if (et.type == NT_float && et.size == 64)
477330fc
RM		 15273 {
15274 do_vfp_nsyn_opcode ("fcpyd");
15275 break;
15276 }
037e8744 15277 /* fall through. */
5287ad62 15278
037e8744
JB		 15279 case NS_QQ: /* case 0/1. */
15280 {
477330fc
RM		 15281 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15282 return;
15283 /* The architecture manual I have doesn't explicitly state which
15284 value the U bit should have for register->register moves, but
15285 the equivalent VORR instruction has U = 0, so do that. */
15286 inst.instruction = 0x0200110;
15287 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15288 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15289 inst.instruction |= LOW4 (inst.operands[1].reg);
15290 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15291 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15292 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15293 inst.instruction |= neon_quad (rs) << 6;
15294
15295 neon_dp_fixup (&inst);
037e8744
JB		 15296 }
15297 break;
5f4273c7 15298
037e8744
JB		 15299 case NS_DI: /* case 3/11. */
15300 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15301 inst.error = NULL;
15302 if (et.type == NT_float && et.size == 64)
477330fc
RM		 15303 {
15304 /* case 11 (fconstd). */
15305 ldconst = "fconstd";
15306 goto encode_fconstd;
15307 }
037e8744
JB		 15308 /* fall through. */
15309
15310 case NS_QI: /* case 2/3. */
15311 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
477330fc 15312 return;
037e8744
JB		 15313 inst.instruction = 0x0800010;
15314 neon_move_immediate ();
88714cb8 15315 neon_dp_fixup (&inst);
5287ad62 15316 break;
5f4273c7 15317
037e8744
JB		 15318 case NS_SR: /* case 4. */
15319 {
477330fc
RM		 15320 unsigned bcdebits = 0;
15321 int logsize;
15322 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15323 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 15324
05ac0ffb
JB		 15325 /* .<size> is optional here, defaulting to .32. */
15326 if (inst.vectype.elems == 0
15327 && inst.operands[0].vectype.type == NT_invtype
15328 && inst.operands[1].vectype.type == NT_invtype)
15329 {
15330 inst.vectype.el[0].type = NT_untyped;
15331 inst.vectype.el[0].size = 32;
15332 inst.vectype.elems = 1;
15333 }
15334
477330fc
RM		 15335 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15336 logsize = neon_logbits (et.size);
15337
15338 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15339 _(BAD_FPU));
15340 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15341 && et.size != 32, _(BAD_FPU));
15342 constraint (et.type == NT_invtype, _("bad type for scalar"));
15343 constraint (x >= 64 / et.size, _("scalar index out of range"));
15344
15345 switch (et.size)
15346 {
15347 case 8: bcdebits = 0x8; break;
15348 case 16: bcdebits = 0x1; break;
15349 case 32: bcdebits = 0x0; break;
15350 default: ;
15351 }
15352
15353 bcdebits |= x << logsize;
15354
15355 inst.instruction = 0xe000b10;
15356 do_vfp_cond_or_thumb ();
15357 inst.instruction |= LOW4 (dn) << 16;
15358 inst.instruction |= HI1 (dn) << 7;
15359 inst.instruction |= inst.operands[1].reg << 12;
15360 inst.instruction |= (bcdebits & 3) << 5;
15361 inst.instruction |= (bcdebits >> 2) << 21;
037e8744
JB		 15362 }
15363 break;
5f4273c7 15364
037e8744 15365 case NS_DRR: /* case 5 (fmdrr). */
b7fc2769 15366 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
477330fc 15367 _(BAD_FPU));
b7fc2769 15368
037e8744
JB		 15369 inst.instruction = 0xc400b10;
15370 do_vfp_cond_or_thumb ();
15371 inst.instruction |= LOW4 (inst.operands[0].reg);
15372 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15373 inst.instruction |= inst.operands[1].reg << 12;
15374 inst.instruction |= inst.operands[2].reg << 16;
15375 break;
5f4273c7 15376
037e8744
JB		 15377 case NS_RS: /* case 6. */
15378 {
477330fc
RM		 15379 unsigned logsize;
15380 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15381 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15382 unsigned abcdebits = 0;
037e8744 15383
05ac0ffb
JB		 15384 /* .<dt> is optional here, defaulting to .32. */
15385 if (inst.vectype.elems == 0
15386 && inst.operands[0].vectype.type == NT_invtype
15387 && inst.operands[1].vectype.type == NT_invtype)
15388 {
15389 inst.vectype.el[0].type = NT_untyped;
15390 inst.vectype.el[0].size = 32;
15391 inst.vectype.elems = 1;
15392 }
15393
91d6fa6a
NC		 15394 et = neon_check_type (2, NS_NULL,
15395 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM		 15396 logsize = neon_logbits (et.size);
15397
15398 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15399 _(BAD_FPU));
15400 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15401 && et.size != 32, _(BAD_FPU));
15402 constraint (et.type == NT_invtype, _("bad type for scalar"));
15403 constraint (x >= 64 / et.size, _("scalar index out of range"));
15404
15405 switch (et.size)
15406 {
15407 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15408 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15409 case 32: abcdebits = 0x00; break;
15410 default: ;
15411 }
15412
15413 abcdebits |= x << logsize;
15414 inst.instruction = 0xe100b10;
15415 do_vfp_cond_or_thumb ();
15416 inst.instruction |= LOW4 (dn) << 16;
15417 inst.instruction |= HI1 (dn) << 7;
15418 inst.instruction |= inst.operands[0].reg << 12;
15419 inst.instruction |= (abcdebits & 3) << 5;
15420 inst.instruction |= (abcdebits >> 2) << 21;
037e8744
JB		 15421 }
15422 break;
5f4273c7 15423
037e8744
JB		 15424 case NS_RRD: /* case 7 (fmrrd). */
15425 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
477330fc 15426 _(BAD_FPU));
037e8744
JB		 15427
15428 inst.instruction = 0xc500b10;
15429 do_vfp_cond_or_thumb ();
15430 inst.instruction |= inst.operands[0].reg << 12;
15431 inst.instruction |= inst.operands[1].reg << 16;
15432 inst.instruction |= LOW4 (inst.operands[2].reg);
15433 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15434 break;
5f4273c7 15435
037e8744
JB		 15436 case NS_FF: /* case 8 (fcpys). */
15437 do_vfp_nsyn_opcode ("fcpys");
15438 break;
5f4273c7 15439
037e8744
JB		 15440 case NS_FI: /* case 10 (fconsts). */
15441 ldconst = "fconsts";
15442 encode_fconstd:
15443 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM		 15444 {
15445 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15446 do_vfp_nsyn_opcode (ldconst);
15447 }
5287ad62 15448 else
477330fc 15449 first_error (_("immediate out of range"));
037e8744 15450 break;
5f4273c7 15451
037e8744
JB		 15452 case NS_RF: /* case 12 (fmrs). */
15453 do_vfp_nsyn_opcode ("fmrs");
15454 break;
5f4273c7 15455
037e8744
JB		 15456 case NS_FR: /* case 13 (fmsr). */
15457 do_vfp_nsyn_opcode ("fmsr");
15458 break;
5f4273c7 15459
037e8744
JB		 15460 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15461 (one of which is a list), but we have parsed four. Do some fiddling to
15462 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15463 expect. */
15464 case NS_RRFF: /* case 14 (fmrrs). */
15465 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 15466 _("VFP registers must be adjacent"));
037e8744
JB		 15467 inst.operands[2].imm = 2;
15468 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15469 do_vfp_nsyn_opcode ("fmrrs");
15470 break;
5f4273c7 15471
037e8744
JB		 15472 case NS_FFRR: /* case 15 (fmsrr). */
15473 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 15474 _("VFP registers must be adjacent"));
037e8744
JB		 15475 inst.operands[1] = inst.operands[2];
15476 inst.operands[2] = inst.operands[3];
15477 inst.operands[0].imm = 2;
15478 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15479 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 15480 break;
5f4273c7 15481
4c261dff
NC		 15482 case NS_NULL:
15483 /* neon_select_shape has determined that the instruction
15484 shape is wrong and has already set the error message. */
15485 break;
15486
5287ad62
JB		 15487 default:
15488 abort ();
15489 }
15490}
15491
15492static void
15493do_neon_rshift_round_imm (void)
15494{
037e8744 15495 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 15496 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15497 int imm = inst.operands[2].imm;
15498
15499 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15500 if (imm == 0)
15501 {
15502 inst.operands[2].present = 0;
15503 do_neon_mov ();
15504 return;
15505 }
15506
15507 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 15508 _("immediate out of range for shift"));
037e8744 15509 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 15510 et.size - imm);
5287ad62
JB		 15511}
15512
15513static void
15514do_neon_movl (void)
15515{
15516 struct neon_type_el et = neon_check_type (2, NS_QD,
15517 N_EQK | N_DBL, N_SU_32 | N_KEY);
15518 unsigned sizebits = et.size >> 3;
15519 inst.instruction |= sizebits << 19;
15520 neon_two_same (0, et.type == NT_unsigned, -1);
15521}
15522
15523static void
15524do_neon_trn (void)
15525{
037e8744 15526 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15527 struct neon_type_el et = neon_check_type (2, rs,
15528 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 15529 NEON_ENCODE (INTEGER, inst);
037e8744 15530 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15531}
15532
15533static void
15534do_neon_zip_uzp (void)
15535{
037e8744 15536 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15537 struct neon_type_el et = neon_check_type (2, rs,
15538 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15539 if (rs == NS_DD && et.size == 32)
15540 {
15541 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15542 inst.instruction = N_MNEM_vtrn;
15543 do_neon_trn ();
15544 return;
15545 }
037e8744 15546 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15547}
15548
15549static void
15550do_neon_sat_abs_neg (void)
15551{
037e8744 15552 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15553 struct neon_type_el et = neon_check_type (2, rs,
15554 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 15555 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15556}
15557
15558static void
15559do_neon_pair_long (void)
15560{
037e8744 15561 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15562 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15563 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15564 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 15565 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15566}
15567
15568static void
15569do_neon_recip_est (void)
15570{
037e8744 15571 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15572 struct neon_type_el et = neon_check_type (2, rs,
15573 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15574 inst.instruction |= (et.type == NT_float) << 8;
037e8744 15575 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15576}
15577
15578static void
15579do_neon_cls (void)
15580{
037e8744 15581 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15582 struct neon_type_el et = neon_check_type (2, rs,
15583 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 15584 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15585}
15586
15587static void
15588do_neon_clz (void)
15589{
037e8744 15590 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15591 struct neon_type_el et = neon_check_type (2, rs,
15592 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 15593 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15594}
15595
15596static void
15597do_neon_cnt (void)
15598{
037e8744 15599 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15600 struct neon_type_el et = neon_check_type (2, rs,
15601 N_EQK | N_INT, N_8 | N_KEY);
037e8744 15602 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15603}
15604
15605static void
15606do_neon_swp (void)
15607{
037e8744
JB		 15608 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
15609 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB		 15610}
15611
15612static void
15613do_neon_tbl_tbx (void)
15614{
15615 unsigned listlenbits;
dcbf9037 15616 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 15617
5287ad62
JB		 15618 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
15619 {
dcbf9037 15620 first_error (_("bad list length for table lookup"));
5287ad62
JB		 15621 return;
15622 }
5f4273c7 15623
5287ad62
JB		 15624 listlenbits = inst.operands[1].imm - 1;
15625 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15626 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15627 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15628 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15629 inst.instruction |= LOW4 (inst.operands[2].reg);
15630 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15631 inst.instruction |= listlenbits << 8;
5f4273c7 15632
88714cb8 15633 neon_dp_fixup (&inst);
5287ad62
JB		 15634}
15635
15636static void
15637do_neon_ldm_stm (void)
15638{
15639 /* P, U and L bits are part of bitmask. */
15640 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
15641 unsigned offsetbits = inst.operands[1].imm * 2;
15642
037e8744
JB		 15643 if (inst.operands[1].issingle)
15644 {
15645 do_vfp_nsyn_ldm_stm (is_dbmode);
15646 return;
15647 }
15648
5287ad62 15649 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 15650 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB		 15651
15652 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM		 15653 _("register list must contain at least 1 and at most 16 "
15654 "registers"));
5287ad62
JB		 15655
15656 inst.instruction |= inst.operands[0].reg << 16;
15657 inst.instruction |= inst.operands[0].writeback << 21;
15658 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15659 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
15660
15661 inst.instruction |= offsetbits;
5f4273c7 15662
037e8744 15663 do_vfp_cond_or_thumb ();
5287ad62
JB		 15664}
15665
15666static void
15667do_neon_ldr_str (void)
15668{
5287ad62 15669 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 15670
6844b2c2
MGD		 15671 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15672 And is UNPREDICTABLE in thumb mode. */
fa94de6b 15673 if (!is_ldr
6844b2c2 15674 && inst.operands[1].reg == REG_PC
ba86b375 15675 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 15676 {
94dcf8bf 15677 if (thumb_mode)
6844b2c2 15678 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf
JB		 15679 else if (warn_on_deprecated)
15680 as_warn (_("Use of PC here is deprecated"));
6844b2c2
MGD		 15681 }
15682
037e8744
JB		 15683 if (inst.operands[0].issingle)
15684 {
cd2f129f 15685 if (is_ldr)
477330fc 15686 do_vfp_nsyn_opcode ("flds");
cd2f129f 15687 else
477330fc 15688 do_vfp_nsyn_opcode ("fsts");
5287ad62
JB		 15689 }
15690 else
5287ad62 15691 {
cd2f129f 15692 if (is_ldr)
477330fc 15693 do_vfp_nsyn_opcode ("fldd");
5287ad62 15694 else
477330fc 15695 do_vfp_nsyn_opcode ("fstd");
5287ad62 15696 }
5287ad62
JB		 15697}
15698
15699/* "interleave" version also handles non-interleaving register VLD1/VST1
15700 instructions. */
15701
15702static void
15703do_neon_ld_st_interleave (void)
15704{
037e8744 15705 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 15706 N_8 | N_16 | N_32 | N_64);
5287ad62
JB		 15707 unsigned alignbits = 0;
15708 unsigned idx;
15709 /* The bits in this table go:
15710 0: register stride of one (0) or two (1)
15711 1,2: register list length, minus one (1, 2, 3, 4).
15712 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15713 We use -1 for invalid entries. */
15714 const int typetable[] =
15715 {
15716 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15717 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15718 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15719 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15720 };
15721 int typebits;
15722
dcbf9037
JB		 15723 if (et.type == NT_invtype)
15724 return;
15725
5287ad62
JB		 15726 if (inst.operands[1].immisalign)
15727 switch (inst.operands[1].imm >> 8)
15728 {
15729 case 64: alignbits = 1; break;
15730 case 128:
477330fc 15731 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 15732 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM		 15733 goto bad_alignment;
15734 alignbits = 2;
15735 break;
5287ad62 15736 case 256:
477330fc
RM		 15737 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
15738 goto bad_alignment;
15739 alignbits = 3;
15740 break;
5287ad62
JB		 15741 default:
15742 bad_alignment:
477330fc
RM		 15743 first_error (_("bad alignment"));
15744 return;
5287ad62
JB		 15745 }
15746
15747 inst.instruction |= alignbits << 4;
15748 inst.instruction |= neon_logbits (et.size) << 6;
15749
15750 /* Bits [4:6] of the immediate in a list specifier encode register stride
15751 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15752 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15753 up the right value for "type" in a table based on this value and the given
15754 list style, then stick it back. */
15755 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 15756 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB		 15757
15758 typebits = typetable[idx];
5f4273c7 15759
5287ad62
JB		 15760 constraint (typebits == -1, _("bad list type for instruction"));
15761
15762 inst.instruction &= ~0xf00;
15763 inst.instruction |= typebits << 8;
15764}
15765
15766/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15767 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15768 otherwise. The variable arguments are a list of pairs of legal (size, align)
15769 values, terminated with -1. */
15770
15771static int
15772neon_alignment_bit (int size, int align, int *do_align, ...)
15773{
15774 va_list ap;
15775 int result = FAIL, thissize, thisalign;
5f4273c7 15776
5287ad62
JB		 15777 if (!inst.operands[1].immisalign)
15778 {
15779 *do_align = 0;
15780 return SUCCESS;
15781 }
5f4273c7 15782
5287ad62
JB		 15783 va_start (ap, do_align);
15784
15785 do
15786 {
15787 thissize = va_arg (ap, int);
15788 if (thissize == -1)
477330fc 15789 break;
5287ad62
JB		 15790 thisalign = va_arg (ap, int);
15791
15792 if (size == thissize && align == thisalign)
477330fc 15793 result = SUCCESS;
5287ad62
JB		 15794 }
15795 while (result != SUCCESS);
15796
15797 va_end (ap);
15798
15799 if (result == SUCCESS)
15800 *do_align = 1;
15801 else
dcbf9037 15802 first_error (_("unsupported alignment for instruction"));
5f4273c7 15803
5287ad62
JB		 15804 return result;
15805}
15806
15807static void
15808do_neon_ld_st_lane (void)
15809{
037e8744 15810 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB		 15811 int align_good, do_align = 0;
15812 int logsize = neon_logbits (et.size);
15813 int align = inst.operands[1].imm >> 8;
15814 int n = (inst.instruction >> 8) & 3;
15815 int max_el = 64 / et.size;
5f4273c7 15816
dcbf9037
JB		 15817 if (et.type == NT_invtype)
15818 return;
5f4273c7 15819
5287ad62 15820 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 15821 _("bad list length"));
5287ad62 15822 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 15823 _("scalar index out of range"));
5287ad62 15824 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM		 15825 && et.size == 8,
15826 _("stride of 2 unavailable when element size is 8"));
5f4273c7 15827
5287ad62
JB		 15828 switch (n)
15829 {
15830 case 0: /* VLD1 / VST1. */
15831 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
477330fc 15832 32, 32, -1);
5287ad62 15833 if (align_good == FAIL)
477330fc 15834 return;
5287ad62 15835 if (do_align)
477330fc
RM		 15836 {
15837 unsigned alignbits = 0;
15838 switch (et.size)
15839 {
15840 case 16: alignbits = 0x1; break;
15841 case 32: alignbits = 0x3; break;
15842 default: ;
15843 }
15844 inst.instruction |= alignbits << 4;
15845 }
5287ad62
JB		 15846 break;
15847
15848 case 1: /* VLD2 / VST2. */
15849 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
477330fc 15850 32, 64, -1);
5287ad62 15851 if (align_good == FAIL)
477330fc 15852 return;
5287ad62 15853 if (do_align)
477330fc 15854 inst.instruction |= 1 << 4;
5287ad62
JB		 15855 break;
15856
15857 case 2: /* VLD3 / VST3. */
15858 constraint (inst.operands[1].immisalign,
477330fc 15859 _("can't use alignment with this instruction"));
5287ad62
JB		 15860 break;
15861
15862 case 3: /* VLD4 / VST4. */
15863 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
477330fc 15864 16, 64, 32, 64, 32, 128, -1);
5287ad62 15865 if (align_good == FAIL)
477330fc 15866 return;
5287ad62 15867 if (do_align)
477330fc
RM		 15868 {
15869 unsigned alignbits = 0;
15870 switch (et.size)
15871 {
15872 case 8: alignbits = 0x1; break;
15873 case 16: alignbits = 0x1; break;
15874 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
15875 default: ;
15876 }
15877 inst.instruction |= alignbits << 4;
15878 }
5287ad62
JB		 15879 break;
15880
15881 default: ;
15882 }
15883
15884 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15885 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15886 inst.instruction |= 1 << (4 + logsize);
5f4273c7 15887
5287ad62
JB		 15888 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
15889 inst.instruction |= logsize << 10;
15890}
15891
15892/* Encode single n-element structure to all lanes VLD<n> instructions. */
15893
15894static void
15895do_neon_ld_dup (void)
15896{
037e8744 15897 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB		 15898 int align_good, do_align = 0;
15899
dcbf9037
JB		 15900 if (et.type == NT_invtype)
15901 return;
15902
5287ad62
JB		 15903 switch ((inst.instruction >> 8) & 3)
15904 {
15905 case 0: /* VLD1. */
9c2799c2 15906 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 15907 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
477330fc 15908 &do_align, 16, 16, 32, 32, -1);
5287ad62 15909 if (align_good == FAIL)
477330fc 15910 return;
5287ad62 15911 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM		 15912 {
15913 case 1: break;
15914 case 2: inst.instruction |= 1 << 5; break;
15915 default: first_error (_("bad list length")); return;
15916 }
5287ad62
JB		 15917 inst.instruction |= neon_logbits (et.size) << 6;
15918 break;
15919
15920 case 1: /* VLD2. */
15921 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
477330fc 15922 &do_align, 8, 16, 16, 32, 32, 64, -1);
5287ad62 15923 if (align_good == FAIL)
477330fc 15924 return;
5287ad62 15925 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 15926 _("bad list length"));
5287ad62 15927 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 15928 inst.instruction |= 1 << 5;
5287ad62
JB		 15929 inst.instruction |= neon_logbits (et.size) << 6;
15930 break;
15931
15932 case 2: /* VLD3. */
15933 constraint (inst.operands[1].immisalign,
477330fc 15934 _("can't use alignment with this instruction"));
5287ad62 15935 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 15936 _("bad list length"));
5287ad62 15937 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 15938 inst.instruction |= 1 << 5;
5287ad62
JB		 15939 inst.instruction |= neon_logbits (et.size) << 6;
15940 break;
15941
15942 case 3: /* VLD4. */
15943 {
477330fc
RM		 15944 int align = inst.operands[1].imm >> 8;
15945 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
15946 16, 64, 32, 64, 32, 128, -1);
15947 if (align_good == FAIL)
15948 return;
15949 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
15950 _("bad list length"));
15951 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
15952 inst.instruction |= 1 << 5;
15953 if (et.size == 32 && align == 128)
15954 inst.instruction |= 0x3 << 6;
15955 else
15956 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB		 15957 }
15958 break;
15959
15960 default: ;
15961 }
15962
15963 inst.instruction |= do_align << 4;
15964}
15965
15966/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15967 apart from bits [11:4]. */
15968
15969static void
15970do_neon_ldx_stx (void)
15971{
b1a769ed
DG		 15972 if (inst.operands[1].isreg)
15973 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
15974
5287ad62
JB		 15975 switch (NEON_LANE (inst.operands[0].imm))
15976 {
15977 case NEON_INTERLEAVE_LANES:
88714cb8 15978 NEON_ENCODE (INTERLV, inst);
5287ad62
JB		 15979 do_neon_ld_st_interleave ();
15980 break;
5f4273c7 15981
5287ad62 15982 case NEON_ALL_LANES:
88714cb8 15983 NEON_ENCODE (DUP, inst);
2d51fb74
JB		 15984 if (inst.instruction == N_INV)
15985 {
15986 first_error ("only loads support such operands");
15987 break;
15988 }
5287ad62
JB		 15989 do_neon_ld_dup ();
15990 break;
5f4273c7 15991
5287ad62 15992 default:
88714cb8 15993 NEON_ENCODE (LANE, inst);
5287ad62
JB		 15994 do_neon_ld_st_lane ();
15995 }
15996
15997 /* L bit comes from bit mask. */
15998 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15999 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16000 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 16001
5287ad62
JB		 16002 if (inst.operands[1].postind)
16003 {
16004 int postreg = inst.operands[1].imm & 0xf;
16005 constraint (!inst.operands[1].immisreg,
477330fc 16006 _("post-index must be a register"));
5287ad62 16007 constraint (postreg == 0xd || postreg == 0xf,
477330fc 16008 _("bad register for post-index"));
5287ad62
JB		 16009 inst.instruction |= postreg;
16010 }
16011 else if (inst.operands[1].writeback)
16012 {
16013 inst.instruction |= 0xd;
16014 }
16015 else
5f4273c7
NC		 16016 inst.instruction |= 0xf;
16017
5287ad62
JB		 16018 if (thumb_mode)
16019 inst.instruction |= 0xf9000000;
16020 else
16021 inst.instruction |= 0xf4000000;
16022}
33399f07
MGD		 16023
16024/* FP v8. */
16025static void
16026do_vfp_nsyn_fpv8 (enum neon_shape rs)
16027{
16028 NEON_ENCODE (FPV8, inst);
16029
16030 if (rs == NS_FFF)
16031 do_vfp_sp_dyadic ();
16032 else
16033 do_vfp_dp_rd_rn_rm ();
16034
16035 if (rs == NS_DDD)
16036 inst.instruction |= 0x100;
16037
16038 inst.instruction |= 0xf0000000;
16039}
16040
16041static void
16042do_vsel (void)
16043{
16044 set_it_insn_type (OUTSIDE_IT_INSN);
16045
16046 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16047 first_error (_("invalid instruction shape"));
16048}
16049
73924fbc
MGD		 16050static void
16051do_vmaxnm (void)
16052{
16053 set_it_insn_type (OUTSIDE_IT_INSN);
16054
16055 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16056 return;
16057
16058 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16059 return;
16060
16061 neon_dyadic_misc (NT_untyped, N_F32, 0);
16062}
16063
30bdf752
MGD		 16064static void
16065do_vrint_1 (enum neon_cvt_mode mode)
16066{
16067 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16068 struct neon_type_el et;
16069
16070 if (rs == NS_NULL)
16071 return;
16072
16073 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16074 if (et.type != NT_invtype)
16075 {
16076 /* VFP encodings. */
16077 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16078 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16079 set_it_insn_type (OUTSIDE_IT_INSN);
16080
16081 NEON_ENCODE (FPV8, inst);
16082 if (rs == NS_FF)
16083 do_vfp_sp_monadic ();
16084 else
16085 do_vfp_dp_rd_rm ();
16086
16087 switch (mode)
16088 {
16089 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16090 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16091 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16092 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16093 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16094 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16095 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16096 default: abort ();
16097 }
16098
16099 inst.instruction |= (rs == NS_DD) << 8;
16100 do_vfp_cond_or_thumb ();
16101 }
16102 else
16103 {
16104 /* Neon encodings (or something broken...). */
16105 inst.error = NULL;
16106 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16107
16108 if (et.type == NT_invtype)
16109 return;
16110
16111 set_it_insn_type (OUTSIDE_IT_INSN);
16112 NEON_ENCODE (FLOAT, inst);
16113
16114 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16115 return;
16116
16117 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16118 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16119 inst.instruction |= LOW4 (inst.operands[1].reg);
16120 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16121 inst.instruction |= neon_quad (rs) << 6;
16122 switch (mode)
16123 {
16124 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16125 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16126 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16127 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16128 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16129 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16130 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16131 default: abort ();
16132 }
16133
16134 if (thumb_mode)
16135 inst.instruction |= 0xfc000000;
16136 else
16137 inst.instruction |= 0xf0000000;
16138 }
16139}
16140
16141static void
16142do_vrintx (void)
16143{
16144 do_vrint_1 (neon_cvt_mode_x);
16145}
16146
16147static void
16148do_vrintz (void)
16149{
16150 do_vrint_1 (neon_cvt_mode_z);
16151}
16152
16153static void
16154do_vrintr (void)
16155{
16156 do_vrint_1 (neon_cvt_mode_r);
16157}
16158
16159static void
16160do_vrinta (void)
16161{
16162 do_vrint_1 (neon_cvt_mode_a);
16163}
16164
16165static void
16166do_vrintn (void)
16167{
16168 do_vrint_1 (neon_cvt_mode_n);
16169}
16170
16171static void
16172do_vrintp (void)
16173{
16174 do_vrint_1 (neon_cvt_mode_p);
16175}
16176
16177static void
16178do_vrintm (void)
16179{
16180 do_vrint_1 (neon_cvt_mode_m);
16181}
16182
91ff7894
MGD		 16183/* Crypto v1 instructions. */
16184static void
16185do_crypto_2op_1 (unsigned elttype, int op)
16186{
16187 set_it_insn_type (OUTSIDE_IT_INSN);
16188
16189 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16190 == NT_invtype)
16191 return;
16192
16193 inst.error = NULL;
16194
16195 NEON_ENCODE (INTEGER, inst);
16196 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16197 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16198 inst.instruction |= LOW4 (inst.operands[1].reg);
16199 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16200 if (op != -1)
16201 inst.instruction |= op << 6;
16202
16203 if (thumb_mode)
16204 inst.instruction |= 0xfc000000;
16205 else
16206 inst.instruction |= 0xf0000000;
16207}
16208
48adcd8e
MGD		 16209static void
16210do_crypto_3op_1 (int u, int op)
16211{
16212 set_it_insn_type (OUTSIDE_IT_INSN);
16213
16214 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16215 N_32 | N_UNT | N_KEY).type == NT_invtype)
16216 return;
16217
16218 inst.error = NULL;
16219
16220 NEON_ENCODE (INTEGER, inst);
16221 neon_three_same (1, u, 8 << op);
16222}
16223
91ff7894
MGD		 16224static void
16225do_aese (void)
16226{
16227 do_crypto_2op_1 (N_8, 0);
16228}
16229
16230static void
16231do_aesd (void)
16232{
16233 do_crypto_2op_1 (N_8, 1);
16234}
16235
16236static void
16237do_aesmc (void)
16238{
16239 do_crypto_2op_1 (N_8, 2);
16240}
16241
16242static void
16243do_aesimc (void)
16244{
16245 do_crypto_2op_1 (N_8, 3);
16246}
16247
48adcd8e
MGD		 16248static void
16249do_sha1c (void)
16250{
16251 do_crypto_3op_1 (0, 0);
16252}
16253
16254static void
16255do_sha1p (void)
16256{
16257 do_crypto_3op_1 (0, 1);
16258}
16259
16260static void
16261do_sha1m (void)
16262{
16263 do_crypto_3op_1 (0, 2);
16264}
16265
16266static void
16267do_sha1su0 (void)
16268{
16269 do_crypto_3op_1 (0, 3);
16270}
91ff7894 16271
48adcd8e
MGD		 16272static void
16273do_sha256h (void)
16274{
16275 do_crypto_3op_1 (1, 0);
16276}
16277
16278static void
16279do_sha256h2 (void)
16280{
16281 do_crypto_3op_1 (1, 1);
16282}
16283
16284static void
16285do_sha256su1 (void)
16286{
16287 do_crypto_3op_1 (1, 2);
16288}
3c9017d2
MGD		 16289
16290static void
16291do_sha1h (void)
16292{
16293 do_crypto_2op_1 (N_32, -1);
16294}
16295
16296static void
16297do_sha1su1 (void)
16298{
16299 do_crypto_2op_1 (N_32, 0);
16300}
16301
16302static void
16303do_sha256su0 (void)
16304{
16305 do_crypto_2op_1 (N_32, 1);
16306}
dd5181d5
KT		 16307
16308static void
16309do_crc32_1 (unsigned int poly, unsigned int sz)
16310{
16311 unsigned int Rd = inst.operands[0].reg;
16312 unsigned int Rn = inst.operands[1].reg;
16313 unsigned int Rm = inst.operands[2].reg;
16314
16315 set_it_insn_type (OUTSIDE_IT_INSN);
16316 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16317 inst.instruction |= LOW4 (Rn) << 16;
16318 inst.instruction |= LOW4 (Rm);
16319 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16320 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16321
16322 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16323 as_warn (UNPRED_REG ("r15"));
16324 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16325 as_warn (UNPRED_REG ("r13"));
16326}
16327
16328static void
16329do_crc32b (void)
16330{
16331 do_crc32_1 (0, 0);
16332}
16333
16334static void
16335do_crc32h (void)
16336{
16337 do_crc32_1 (0, 1);
16338}
16339
16340static void
16341do_crc32w (void)
16342{
16343 do_crc32_1 (0, 2);
16344}
16345
16346static void
16347do_crc32cb (void)
16348{
16349 do_crc32_1 (1, 0);
16350}
16351
16352static void
16353do_crc32ch (void)
16354{
16355 do_crc32_1 (1, 1);
16356}
16357
16358static void
16359do_crc32cw (void)
16360{
16361 do_crc32_1 (1, 2);
16362}
16363
5287ad62
JB		 16364\f
16365/* Overall per-instruction processing. */
16366
16367/* We need to be able to fix up arbitrary expressions in some statements.
16368 This is so that we can handle symbols that are an arbitrary distance from
16369 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16370 which returns part of an address in a form which will be valid for
16371 a data instruction. We do this by pushing the expression into a symbol
16372 in the expr_section, and creating a fix for that. */
16373
16374static void
16375fix_new_arm (fragS * frag,
16376 int where,
16377 short int size,
16378 expressionS * exp,
16379 int pc_rel,
16380 int reloc)
16381{
16382 fixS * new_fix;
16383
16384 switch (exp->X_op)
16385 {
16386 case O_constant:
6e7ce2cd
PB		 16387 if (pc_rel)
16388 {
16389 /* Create an absolute valued symbol, so we have something to
477330fc
RM		 16390 refer to in the object file. Unfortunately for us, gas's
16391 generic expression parsing will already have folded out
16392 any use of .set foo/.type foo %function that may have
16393 been used to set type information of the target location,
16394 that's being specified symbolically. We have to presume
16395 the user knows what they are doing. */
6e7ce2cd
PB		 16396 char name[16 + 8];
16397 symbolS *symbol;
16398
16399 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16400
16401 symbol = symbol_find_or_make (name);
16402 S_SET_SEGMENT (symbol, absolute_section);
16403 symbol_set_frag (symbol, &zero_address_frag);
16404 S_SET_VALUE (symbol, exp->X_add_number);
16405 exp->X_op = O_symbol;
16406 exp->X_add_symbol = symbol;
16407 exp->X_add_number = 0;
16408 }
16409 /* FALLTHROUGH */
5287ad62
JB		 16410 case O_symbol:
16411 case O_add:
16412 case O_subtract:
21d799b5 16413 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 16414 (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 16415 break;
16416
16417 default:
21d799b5 16418 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 16419 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 16420 break;
16421 }
16422
16423 /* Mark whether the fix is to a THUMB instruction, or an ARM
16424 instruction. */
16425 new_fix->tc_fix_data = thumb_mode;
16426}
16427
16428/* Create a frg for an instruction requiring relaxation. */
16429static void
16430output_relax_insn (void)
16431{
16432 char * to;
16433 symbolS *sym;
0110f2b8
PB		 16434 int offset;
16435
6e1cb1a6
PB		 16436 /* The size of the instruction is unknown, so tie the debug info to the
16437 start of the instruction. */
16438 dwarf2_emit_insn (0);
6e1cb1a6 16439
0110f2b8
PB		 16440 switch (inst.reloc.exp.X_op)
16441 {
16442 case O_symbol:
16443 sym = inst.reloc.exp.X_add_symbol;
16444 offset = inst.reloc.exp.X_add_number;
16445 break;
16446 case O_constant:
16447 sym = NULL;
16448 offset = inst.reloc.exp.X_add_number;
16449 break;
16450 default:
16451 sym = make_expr_symbol (&inst.reloc.exp);
16452 offset = 0;
16453 break;
16454 }
16455 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16456 inst.relax, sym, offset, NULL/*offset, opcode*/);
16457 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB		 16458}
16459
16460/* Write a 32-bit thumb instruction to buf. */
16461static void
16462put_thumb32_insn (char * buf, unsigned long insn)
16463{
16464 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16465 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16466}
16467
b99bd4ef 16468static void
c19d1205 16469output_inst (const char * str)
b99bd4ef 16470{
c19d1205 16471 char * to = NULL;
b99bd4ef 16472
c19d1205 16473 if (inst.error)
b99bd4ef 16474 {
c19d1205 16475 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC		 16476 return;
16477 }
5f4273c7
NC		 16478 if (inst.relax)
16479 {
16480 output_relax_insn ();
0110f2b8 16481 return;
5f4273c7 16482 }
c19d1205
ZW		 16483 if (inst.size == 0)
16484 return;
b99bd4ef 16485
c19d1205 16486 to = frag_more (inst.size);
8dc2430f
NC		 16487 /* PR 9814: Record the thumb mode into the current frag so that we know
16488 what type of NOP padding to use, if necessary. We override any previous
16489 setting so that if the mode has changed then the NOPS that we use will
16490 match the encoding of the last instruction in the frag. */
cd000bff 16491 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW		 16492
16493 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 16494 {
9c2799c2 16495 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 16496 put_thumb32_insn (to, inst.instruction);
b99bd4ef 16497 }
c19d1205 16498 else if (inst.size > INSN_SIZE)
b99bd4ef 16499 {
9c2799c2 16500 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW		 16501 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16502 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 16503 }
c19d1205
ZW		 16504 else
16505 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 16506
c19d1205
ZW		 16507 if (inst.reloc.type != BFD_RELOC_UNUSED)
16508 fix_new_arm (frag_now, to - frag_now->fr_literal,
16509 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16510 inst.reloc.type);
b99bd4ef 16511
c19d1205 16512 dwarf2_emit_insn (inst.size);
c19d1205 16513}
b99bd4ef 16514
e07e6e58
NC		 16515static char *
16516output_it_inst (int cond, int mask, char * to)
16517{
16518 unsigned long instruction = 0xbf00;
16519
16520 mask &= 0xf;
16521 instruction |= mask;
16522 instruction |= cond << 4;
16523
16524 if (to == NULL)
16525 {
16526 to = frag_more (2);
16527#ifdef OBJ_ELF
16528 dwarf2_emit_insn (2);
16529#endif
16530 }
16531
16532 md_number_to_chars (to, instruction, 2);
16533
16534 return to;
16535}
16536
c19d1205
ZW		 16537/* Tag values used in struct asm_opcode's tag field. */
16538enum opcode_tag
16539{
16540 OT_unconditional, /* Instruction cannot be conditionalized.
16541 The ARM condition field is still 0xE. */
16542 OT_unconditionalF, /* Instruction cannot be conditionalized
16543 and carries 0xF in its ARM condition field. */
16544 OT_csuffix, /* Instruction takes a conditional suffix. */
037e8744 16545 OT_csuffixF, /* Some forms of the instruction take a conditional
477330fc
RM		 16546 suffix, others place 0xF where the condition field
16547 would be. */
c19d1205
ZW		 16548 OT_cinfix3, /* Instruction takes a conditional infix,
16549 beginning at character index 3. (In
16550 unified mode, it becomes a suffix.) */
088fa78e
KH		 16551 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16552 tsts, cmps, cmns, and teqs. */
e3cb604e
PB		 16553 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16554 character index 3, even in unified mode. Used for
16555 legacy instructions where suffix and infix forms
16556 may be ambiguous. */
c19d1205 16557 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 16558 suffix or an infix at character index 3. */
c19d1205
ZW		 16559 OT_odd_infix_unc, /* This is the unconditional variant of an
16560 instruction that takes a conditional infix
16561 at an unusual position. In unified mode,
16562 this variant will accept a suffix. */
16563 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16564 are the conditional variants of instructions that
16565 take conditional infixes in unusual positions.
16566 The infix appears at character index
16567 (tag - OT_odd_infix_0). These are not accepted
16568 in unified mode. */
16569};
b99bd4ef 16570
c19d1205
ZW		 16571/* Subroutine of md_assemble, responsible for looking up the primary
16572 opcode from the mnemonic the user wrote. STR points to the
16573 beginning of the mnemonic.
16574
16575 This is not simply a hash table lookup, because of conditional
16576 variants. Most instructions have conditional variants, which are
16577 expressed with a _conditional affix_ to the mnemonic. If we were
16578 to encode each conditional variant as a literal string in the opcode
16579 table, it would have approximately 20,000 entries.
16580
16581 Most mnemonics take this affix as a suffix, and in unified syntax,
16582 'most' is upgraded to 'all'. However, in the divided syntax, some
16583 instructions take the affix as an infix, notably the s-variants of
16584 the arithmetic instructions. Of those instructions, all but six
16585 have the infix appear after the third character of the mnemonic.
16586
16587 Accordingly, the algorithm for looking up primary opcodes given
16588 an identifier is:
16589
16590 1. Look up the identifier in the opcode table.
16591 If we find a match, go to step U.
16592
16593 2. Look up the last two characters of the identifier in the
16594 conditions table. If we find a match, look up the first N-2
16595 characters of the identifier in the opcode table. If we
16596 find a match, go to step CE.
16597
16598 3. Look up the fourth and fifth characters of the identifier in
16599 the conditions table. If we find a match, extract those
16600 characters from the identifier, and look up the remaining
16601 characters in the opcode table. If we find a match, go
16602 to step CM.
16603
16604 4. Fail.
16605
16606 U. Examine the tag field of the opcode structure, in case this is
16607 one of the six instructions with its conditional infix in an
16608 unusual place. If it is, the tag tells us where to find the
16609 infix; look it up in the conditions table and set inst.cond
16610 accordingly. Otherwise, this is an unconditional instruction.
16611 Again set inst.cond accordingly. Return the opcode structure.
16612
16613 CE. Examine the tag field to make sure this is an instruction that
16614 should receive a conditional suffix. If it is not, fail.
16615 Otherwise, set inst.cond from the suffix we already looked up,
16616 and return the opcode structure.
16617
16618 CM. Examine the tag field to make sure this is an instruction that
16619 should receive a conditional infix after the third character.
16620 If it is not, fail. Otherwise, undo the edits to the current
16621 line of input and proceed as for case CE. */
16622
16623static const struct asm_opcode *
16624opcode_lookup (char **str)
16625{
16626 char *end, *base;
16627 char *affix;
16628 const struct asm_opcode *opcode;
16629 const struct asm_cond *cond;
e3cb604e 16630 char save[2];
c19d1205
ZW		 16631
16632 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 16633 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 16634 for (base = end = *str; *end != '\0'; end++)
721a8186 16635 if (*end == ' ' || *end == '.')
c19d1205 16636 break;
b99bd4ef 16637
c19d1205 16638 if (end == base)
c921be7d 16639 return NULL;
b99bd4ef 16640
5287ad62 16641 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 16642 if (end[0] == '.')
b99bd4ef 16643 {
5287ad62 16644 int offset = 2;
5f4273c7 16645
267d2029 16646 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 16647 use. */
267d2029 16648 if (unified_syntax && end[1] == 'w')
c19d1205 16649 inst.size_req = 4;
267d2029 16650 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW		 16651 inst.size_req = 2;
16652 else
477330fc 16653 offset = 0;
5287ad62
JB		 16654
16655 inst.vectype.elems = 0;
16656
16657 *str = end + offset;
b99bd4ef 16658
5f4273c7 16659 if (end[offset] == '.')
5287ad62 16660 {
267d2029 16661 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM		 16662 non-unified ARM syntax mode). */
16663 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 16664 return NULL;
477330fc 16665 }
5287ad62 16666 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 16667 return NULL;
b99bd4ef 16668 }
c19d1205
ZW		 16669 else
16670 *str = end;
b99bd4ef 16671
c19d1205 16672 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 16673 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 16674 end - base);
c19d1205 16675 if (opcode)
b99bd4ef 16676 {
c19d1205
ZW		 16677 /* step U */
16678 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 16679 {
c19d1205
ZW		 16680 inst.cond = COND_ALWAYS;
16681 return opcode;
b99bd4ef 16682 }
b99bd4ef 16683
278df34e 16684 if (warn_on_deprecated && unified_syntax)
c19d1205
ZW		 16685 as_warn (_("conditional infixes are deprecated in unified syntax"));
16686 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 16687 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 16688 gas_assert (cond);
b99bd4ef 16689
c19d1205
ZW		 16690 inst.cond = cond->value;
16691 return opcode;
16692 }
b99bd4ef 16693
c19d1205
ZW		 16694 /* Cannot have a conditional suffix on a mnemonic of less than two
16695 characters. */
16696 if (end - base < 3)
c921be7d 16697 return NULL;
b99bd4ef 16698
c19d1205
ZW		 16699 /* Look for suffixed mnemonic. */
16700 affix = end - 2;
21d799b5
NC		 16701 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
16702 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 16703 affix - base);
c19d1205
ZW		 16704 if (opcode && cond)
16705 {
16706 /* step CE */
16707 switch (opcode->tag)
16708 {
e3cb604e
PB		 16709 case OT_cinfix3_legacy:
16710 /* Ignore conditional suffixes matched on infix only mnemonics. */
16711 break;
16712
c19d1205 16713 case OT_cinfix3:
088fa78e 16714 case OT_cinfix3_deprecated:
c19d1205
ZW		 16715 case OT_odd_infix_unc:
16716 if (!unified_syntax)
e3cb604e 16717 return 0;
c19d1205
ZW		 16718 /* else fall through */
16719
16720 case OT_csuffix:
477330fc 16721 case OT_csuffixF:
c19d1205
ZW		 16722 case OT_csuf_or_in3:
16723 inst.cond = cond->value;
16724 return opcode;
16725
16726 case OT_unconditional:
16727 case OT_unconditionalF:
dfa9f0d5 16728 if (thumb_mode)
c921be7d 16729 inst.cond = cond->value;
dfa9f0d5
PB		 16730 else
16731 {
c921be7d 16732 /* Delayed diagnostic. */
dfa9f0d5
PB		 16733 inst.error = BAD_COND;
16734 inst.cond = COND_ALWAYS;
16735 }
c19d1205 16736 return opcode;
b99bd4ef 16737
c19d1205 16738 default:
c921be7d 16739 return NULL;
c19d1205
ZW		 16740 }
16741 }
b99bd4ef 16742
c19d1205
ZW		 16743 /* Cannot have a usual-position infix on a mnemonic of less than
16744 six characters (five would be a suffix). */
16745 if (end - base < 6)
c921be7d 16746 return NULL;
b99bd4ef 16747
c19d1205
ZW		 16748 /* Look for infixed mnemonic in the usual position. */
16749 affix = base + 3;
21d799b5 16750 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 16751 if (!cond)
c921be7d 16752 return NULL;
e3cb604e
PB		 16753
16754 memcpy (save, affix, 2);
16755 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 16756 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 16757 (end - base) - 2);
e3cb604e
PB		 16758 memmove (affix + 2, affix, (end - affix) - 2);
16759 memcpy (affix, save, 2);
16760
088fa78e
KH		 16761 if (opcode
16762 && (opcode->tag == OT_cinfix3
16763 || opcode->tag == OT_cinfix3_deprecated
16764 || opcode->tag == OT_csuf_or_in3
16765 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 16766 {
c921be7d 16767 /* Step CM. */
278df34e 16768 if (warn_on_deprecated && unified_syntax
088fa78e
KH		 16769 && (opcode->tag == OT_cinfix3
16770 || opcode->tag == OT_cinfix3_deprecated))
c19d1205
ZW		 16771 as_warn (_("conditional infixes are deprecated in unified syntax"));
16772
16773 inst.cond = cond->value;
16774 return opcode;
b99bd4ef
NC		 16775 }
16776
c921be7d 16777 return NULL;
b99bd4ef
NC		 16778}
16779
e07e6e58
NC		 16780/* This function generates an initial IT instruction, leaving its block
16781 virtually open for the new instructions. Eventually,
16782 the mask will be updated by now_it_add_mask () each time
16783 a new instruction needs to be included in the IT block.
16784 Finally, the block is closed with close_automatic_it_block ().
16785 The block closure can be requested either from md_assemble (),
16786 a tencode (), or due to a label hook. */
16787
16788static void
16789new_automatic_it_block (int cond)
16790{
16791 now_it.state = AUTOMATIC_IT_BLOCK;
16792 now_it.mask = 0x18;
16793 now_it.cc = cond;
16794 now_it.block_length = 1;
cd000bff 16795 mapping_state (MAP_THUMB);
e07e6e58 16796 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
5a01bb1d
MGD		 16797 now_it.warn_deprecated = FALSE;
16798 now_it.insn_cond = TRUE;
e07e6e58
NC		 16799}
16800
16801/* Close an automatic IT block.
16802 See comments in new_automatic_it_block (). */
16803
16804static void
16805close_automatic_it_block (void)
16806{
16807 now_it.mask = 0x10;
16808 now_it.block_length = 0;
16809}
16810
16811/* Update the mask of the current automatically-generated IT
16812 instruction. See comments in new_automatic_it_block (). */
16813
16814static void
16815now_it_add_mask (int cond)
16816{
16817#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
16818#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 16819 | ((bitvalue) << (nbit)))
e07e6e58 16820 const int resulting_bit = (cond & 1);
c921be7d 16821
e07e6e58
NC		 16822 now_it.mask &= 0xf;
16823 now_it.mask = SET_BIT_VALUE (now_it.mask,
477330fc
RM		 16824 resulting_bit,
16825 (5 - now_it.block_length));
e07e6e58 16826 now_it.mask = SET_BIT_VALUE (now_it.mask,
477330fc
RM		 16827 1,
16828 ((5 - now_it.block_length) - 1) );
e07e6e58
NC		 16829 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
16830
16831#undef CLEAR_BIT
16832#undef SET_BIT_VALUE
e07e6e58
NC		 16833}
16834
16835/* The IT blocks handling machinery is accessed through the these functions:
16836 it_fsm_pre_encode () from md_assemble ()
16837 set_it_insn_type () optional, from the tencode functions
16838 set_it_insn_type_last () ditto
16839 in_it_block () ditto
16840 it_fsm_post_encode () from md_assemble ()
16841 force_automatic_it_block_close () from label habdling functions
16842
16843 Rationale:
16844 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM		 16845 initializing the IT insn type with a generic initial value depending
16846 on the inst.condition.
e07e6e58 16847 2) During the tencode function, two things may happen:
477330fc
RM		 16848 a) The tencode function overrides the IT insn type by
16849 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16850 b) The tencode function queries the IT block state by
16851 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16852
16853 Both set_it_insn_type and in_it_block run the internal FSM state
16854 handling function (handle_it_state), because: a) setting the IT insn
16855 type may incur in an invalid state (exiting the function),
16856 and b) querying the state requires the FSM to be updated.
16857 Specifically we want to avoid creating an IT block for conditional
16858 branches, so it_fsm_pre_encode is actually a guess and we can't
16859 determine whether an IT block is required until the tencode () routine
16860 has decided what type of instruction this actually it.
16861 Because of this, if set_it_insn_type and in_it_block have to be used,
16862 set_it_insn_type has to be called first.
16863
16864 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16865 determines the insn IT type depending on the inst.cond code.
16866 When a tencode () routine encodes an instruction that can be
16867 either outside an IT block, or, in the case of being inside, has to be
16868 the last one, set_it_insn_type_last () will determine the proper
16869 IT instruction type based on the inst.cond code. Otherwise,
16870 set_it_insn_type can be called for overriding that logic or
16871 for covering other cases.
16872
16873 Calling handle_it_state () may not transition the IT block state to
16874 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16875 still queried. Instead, if the FSM determines that the state should
16876 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16877 after the tencode () function: that's what it_fsm_post_encode () does.
16878
16879 Since in_it_block () calls the state handling function to get an
16880 updated state, an error may occur (due to invalid insns combination).
16881 In that case, inst.error is set.
16882 Therefore, inst.error has to be checked after the execution of
16883 the tencode () routine.
e07e6e58
NC		 16884
16885 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc
RM		 16886 any pending state change (if any) that didn't take place in
16887 handle_it_state () as explained above. */
e07e6e58
NC		 16888
16889static void
16890it_fsm_pre_encode (void)
16891{
16892 if (inst.cond != COND_ALWAYS)
16893 inst.it_insn_type = INSIDE_IT_INSN;
16894 else
16895 inst.it_insn_type = OUTSIDE_IT_INSN;
16896
16897 now_it.state_handled = 0;
16898}
16899
16900/* IT state FSM handling function. */
16901
16902static int
16903handle_it_state (void)
16904{
16905 now_it.state_handled = 1;
5a01bb1d 16906 now_it.insn_cond = FALSE;
e07e6e58
NC		 16907
16908 switch (now_it.state)
16909 {
16910 case OUTSIDE_IT_BLOCK:
16911 switch (inst.it_insn_type)
16912 {
16913 case OUTSIDE_IT_INSN:
16914 break;
16915
16916 case INSIDE_IT_INSN:
16917 case INSIDE_IT_LAST_INSN:
16918 if (thumb_mode == 0)
16919 {
c921be7d 16920 if (unified_syntax
e07e6e58
NC		 16921 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
16922 as_tsktsk (_("Warning: conditional outside an IT block"\
16923 " for Thumb."));
16924 }
16925 else
16926 {
16927 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
16928 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
16929 {
16930 /* Automatically generate the IT instruction. */
16931 new_automatic_it_block (inst.cond);
16932 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
16933 close_automatic_it_block ();
16934 }
16935 else
16936 {
16937 inst.error = BAD_OUT_IT;
16938 return FAIL;
16939 }
16940 }
16941 break;
16942
16943 case IF_INSIDE_IT_LAST_INSN:
16944 case NEUTRAL_IT_INSN:
16945 break;
16946
16947 case IT_INSN:
16948 now_it.state = MANUAL_IT_BLOCK;
16949 now_it.block_length = 0;
16950 break;
16951 }
16952 break;
16953
16954 case AUTOMATIC_IT_BLOCK:
16955 /* Three things may happen now:
16956 a) We should increment current it block size;
16957 b) We should close current it block (closing insn or 4 insns);
16958 c) We should close current it block and start a new one (due
16959 to incompatible conditions or
16960 4 insns-length block reached). */
16961
16962 switch (inst.it_insn_type)
16963 {
16964 case OUTSIDE_IT_INSN:
16965 /* The closure of the block shall happen immediatelly,
16966 so any in_it_block () call reports the block as closed. */
16967 force_automatic_it_block_close ();
16968 break;
16969
16970 case INSIDE_IT_INSN:
16971 case INSIDE_IT_LAST_INSN:
16972 case IF_INSIDE_IT_LAST_INSN:
16973 now_it.block_length++;
16974
16975 if (now_it.block_length > 4
16976 || !now_it_compatible (inst.cond))
16977 {
16978 force_automatic_it_block_close ();
16979 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
16980 new_automatic_it_block (inst.cond);
16981 }
16982 else
16983 {
5a01bb1d 16984 now_it.insn_cond = TRUE;
e07e6e58
NC		 16985 now_it_add_mask (inst.cond);
16986 }
16987
16988 if (now_it.state == AUTOMATIC_IT_BLOCK
16989 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
16990 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
16991 close_automatic_it_block ();
16992 break;
16993
16994 case NEUTRAL_IT_INSN:
16995 now_it.block_length++;
5a01bb1d 16996 now_it.insn_cond = TRUE;
e07e6e58
NC		 16997
16998 if (now_it.block_length > 4)
16999 force_automatic_it_block_close ();
17000 else
17001 now_it_add_mask (now_it.cc & 1);
17002 break;
17003
17004 case IT_INSN:
17005 close_automatic_it_block ();
17006 now_it.state = MANUAL_IT_BLOCK;
17007 break;
17008 }
17009 break;
17010
17011 case MANUAL_IT_BLOCK:
17012 {
17013 /* Check conditional suffixes. */
17014 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17015 int is_last;
17016 now_it.mask <<= 1;
17017 now_it.mask &= 0x1f;
17018 is_last = (now_it.mask == 0x10);
5a01bb1d 17019 now_it.insn_cond = TRUE;
e07e6e58
NC		 17020
17021 switch (inst.it_insn_type)
17022 {
17023 case OUTSIDE_IT_INSN:
17024 inst.error = BAD_NOT_IT;
17025 return FAIL;
17026
17027 case INSIDE_IT_INSN:
17028 if (cond != inst.cond)
17029 {
17030 inst.error = BAD_IT_COND;
17031 return FAIL;
17032 }
17033 break;
17034
17035 case INSIDE_IT_LAST_INSN:
17036 case IF_INSIDE_IT_LAST_INSN:
17037 if (cond != inst.cond)
17038 {
17039 inst.error = BAD_IT_COND;
17040 return FAIL;
17041 }
17042 if (!is_last)
17043 {
17044 inst.error = BAD_BRANCH;
17045 return FAIL;
17046 }
17047 break;
17048
17049 case NEUTRAL_IT_INSN:
17050 /* The BKPT instruction is unconditional even in an IT block. */
17051 break;
17052
17053 case IT_INSN:
17054 inst.error = BAD_IT_IT;
17055 return FAIL;
17056 }
17057 }
17058 break;
17059 }
17060
17061 return SUCCESS;
17062}
17063
5a01bb1d
MGD		 17064struct depr_insn_mask
17065{
17066 unsigned long pattern;
17067 unsigned long mask;
17068 const char* description;
17069};
17070
17071/* List of 16-bit instruction patterns deprecated in an IT block in
17072 ARMv8. */
17073static const struct depr_insn_mask depr_it_insns[] = {
17074 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17075 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17076 { 0xa000, 0xb800, N_("ADR") },
17077 { 0x4800, 0xf800, N_("Literal loads") },
17078 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17079 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17080 { 0, 0, NULL }
17081};
17082
e07e6e58
NC		 17083static void
17084it_fsm_post_encode (void)
17085{
17086 int is_last;
17087
17088 if (!now_it.state_handled)
17089 handle_it_state ();
17090
5a01bb1d
MGD		 17091 if (now_it.insn_cond
17092 && !now_it.warn_deprecated
17093 && warn_on_deprecated
17094 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17095 {
17096 if (inst.instruction >= 0x10000)
17097 {
0a8897c7 17098 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
5a01bb1d
MGD		 17099 "deprecated in ARMv8"));
17100 now_it.warn_deprecated = TRUE;
17101 }
17102 else
17103 {
17104 const struct depr_insn_mask *p = depr_it_insns;
17105
17106 while (p->mask != 0)
17107 {
17108 if ((inst.instruction & p->mask) == p->pattern)
17109 {
0a8897c7 17110 as_warn (_("IT blocks containing 16-bit Thumb instructions "
5a01bb1d
MGD		 17111 "of the following class are deprecated in ARMv8: "
17112 "%s"), p->description);
17113 now_it.warn_deprecated = TRUE;
17114 break;
17115 }
17116
17117 ++p;
17118 }
17119 }
17120
17121 if (now_it.block_length > 1)
17122 {
0a8897c7
KT		 17123 as_warn (_("IT blocks containing more than one conditional "
17124 "instruction are deprecated in ARMv8"));
5a01bb1d
MGD		 17125 now_it.warn_deprecated = TRUE;
17126 }
17127 }
17128
e07e6e58
NC		 17129 is_last = (now_it.mask == 0x10);
17130 if (is_last)
17131 {
17132 now_it.state = OUTSIDE_IT_BLOCK;
17133 now_it.mask = 0;
17134 }
17135}
17136
17137static void
17138force_automatic_it_block_close (void)
17139{
17140 if (now_it.state == AUTOMATIC_IT_BLOCK)
17141 {
17142 close_automatic_it_block ();
17143 now_it.state = OUTSIDE_IT_BLOCK;
17144 now_it.mask = 0;
17145 }
17146}
17147
17148static int
17149in_it_block (void)
17150{
17151 if (!now_it.state_handled)
17152 handle_it_state ();
17153
17154 return now_it.state != OUTSIDE_IT_BLOCK;
17155}
17156
c19d1205
ZW		 17157void
17158md_assemble (char *str)
b99bd4ef 17159{
c19d1205
ZW		 17160 char *p = str;
17161 const struct asm_opcode * opcode;
b99bd4ef 17162
c19d1205
ZW		 17163 /* Align the previous label if needed. */
17164 if (last_label_seen != NULL)
b99bd4ef 17165 {
c19d1205
ZW		 17166 symbol_set_frag (last_label_seen, frag_now);
17167 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17168 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC		 17169 }
17170
c19d1205
ZW		 17171 memset (&inst, '\0', sizeof (inst));
17172 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 17173
c19d1205
ZW		 17174 opcode = opcode_lookup (&p);
17175 if (!opcode)
b99bd4ef 17176 {
c19d1205 17177 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 17178 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 17179 if (! create_register_alias (str, p)
477330fc 17180 && ! create_neon_reg_alias (str, p))
c19d1205 17181 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 17182
b99bd4ef
NC		 17183 return;
17184 }
17185
278df34e 17186 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
088fa78e
KH		 17187 as_warn (_("s suffix on comparison instruction is deprecated"));
17188
037e8744
JB		 17189 /* The value which unconditional instructions should have in place of the
17190 condition field. */
17191 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17192
c19d1205 17193 if (thumb_mode)
b99bd4ef 17194 {
e74cfd16 17195 arm_feature_set variant;
8f06b2d8
PB		 17196
17197 variant = cpu_variant;
17198 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB		 17199 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17200 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 17201 /* Check that this instruction is supported for this CPU. */
62b3e311
PB		 17202 if (!opcode->tvariant
17203 || (thumb_mode == 1
17204 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 17205 {
bf3eeda7 17206 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
b99bd4ef
NC		 17207 return;
17208 }
c19d1205
ZW		 17209 if (inst.cond != COND_ALWAYS && !unified_syntax
17210 && opcode->tencode != do_t_branch)
b99bd4ef 17211 {
c19d1205 17212 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC		 17213 return;
17214 }
17215
752d5da4 17216 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
076d447c 17217 {
7e806470 17218 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
752d5da4
NC		 17219 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17220 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17221 {
17222 /* Two things are addressed here.
17223 1) Implicit require narrow instructions on Thumb-1.
17224 This avoids relaxation accidentally introducing Thumb-2
17225 instructions.
17226 2) Reject wide instructions in non Thumb-2 cores. */
17227 if (inst.size_req == 0)
17228 inst.size_req = 2;
17229 else if (inst.size_req == 4)
17230 {
bf3eeda7 17231 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
752d5da4
NC		 17232 return;
17233 }
17234 }
076d447c
PB		 17235 }
17236
c19d1205
ZW		 17237 inst.instruction = opcode->tvalue;
17238
5be8be5d 17239 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc
RM		 17240 {
17241 /* Prepare the it_insn_type for those encodings that don't set
17242 it. */
17243 it_fsm_pre_encode ();
c19d1205 17244
477330fc 17245 opcode->tencode ();
e07e6e58 17246
477330fc
RM		 17247 it_fsm_post_encode ();
17248 }
e27ec89e 17249
0110f2b8 17250 if (!(inst.error || inst.relax))
b99bd4ef 17251 {
9c2799c2 17252 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW		 17253 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17254 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 17255 {
c19d1205 17256 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC		 17257 return;
17258 }
17259 }
076d447c
PB		 17260
17261 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 17262 instruction. */
9c2799c2 17263 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 17264
e74cfd16
PB		 17265 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17266 *opcode->tvariant);
ee065d83 17267 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
708587a4 17268 set those bits when Thumb-2 32-bit instructions are seen. ie.
7e806470 17269 anything other than bl/blx and v6-M instructions.
ee065d83 17270 This is overly pessimistic for relaxable instructions. */
7e806470
PB		 17271 if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
17272 || inst.relax)
e07e6e58
NC		 17273 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17274 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
e74cfd16
PB		 17275 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17276 arm_ext_v6t2);
cd000bff 17277
88714cb8
DG		 17278 check_neon_suffixes;
17279
cd000bff 17280 if (!inst.error)
c877a2f2
NC		 17281 {
17282 mapping_state (MAP_THUMB);
17283 }
c19d1205 17284 }
3e9e4fcf 17285 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 17286 {
845b51d6
PB		 17287 bfd_boolean is_bx;
17288
17289 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17290 is_bx = (opcode->aencode == do_bx);
17291
c19d1205 17292 /* Check that this instruction is supported for this CPU. */
845b51d6
PB		 17293 if (!(is_bx && fix_v4bx)
17294 && !(opcode->avariant &&
17295 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 17296 {
bf3eeda7 17297 as_bad (_("selected processor does not support ARM mode `%s'"), str);
c19d1205 17298 return;
b99bd4ef 17299 }
c19d1205 17300 if (inst.size_req)
b99bd4ef 17301 {
c19d1205
ZW		 17302 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17303 return;
b99bd4ef
NC		 17304 }
17305
c19d1205
ZW		 17306 inst.instruction = opcode->avalue;
17307 if (opcode->tag == OT_unconditionalF)
17308 inst.instruction |= 0xF << 28;
17309 else
17310 inst.instruction |= inst.cond << 28;
17311 inst.size = INSN_SIZE;
5be8be5d 17312 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM		 17313 {
17314 it_fsm_pre_encode ();
17315 opcode->aencode ();
17316 it_fsm_post_encode ();
17317 }
ee065d83 17318 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 17319 on a hypothetical non-thumb v5 core. */
845b51d6 17320 if (is_bx)
e74cfd16 17321 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 17322 else
e74cfd16
PB		 17323 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17324 *opcode->avariant);
88714cb8
DG		 17325
17326 check_neon_suffixes;
17327
cd000bff 17328 if (!inst.error)
c877a2f2
NC		 17329 {
17330 mapping_state (MAP_ARM);
17331 }
b99bd4ef 17332 }
3e9e4fcf
JB		 17333 else
17334 {
17335 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17336 "-- `%s'"), str);
17337 return;
17338 }
c19d1205
ZW		 17339 output_inst (str);
17340}
b99bd4ef 17341
e07e6e58
NC		 17342static void
17343check_it_blocks_finished (void)
17344{
17345#ifdef OBJ_ELF
17346 asection *sect;
17347
17348 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17349 if (seg_info (sect)->tc_segment_info_data.current_it.state
17350 == MANUAL_IT_BLOCK)
17351 {
17352 as_warn (_("section '%s' finished with an open IT block."),
17353 sect->name);
17354 }
17355#else
17356 if (now_it.state == MANUAL_IT_BLOCK)
17357 as_warn (_("file finished with an open IT block."));
17358#endif
17359}
17360
c19d1205
ZW		 17361/* Various frobbings of labels and their addresses. */
17362
17363void
17364arm_start_line_hook (void)
17365{
17366 last_label_seen = NULL;
b99bd4ef
NC		 17367}
17368
c19d1205
ZW		 17369void
17370arm_frob_label (symbolS * sym)
b99bd4ef 17371{
c19d1205 17372 last_label_seen = sym;
b99bd4ef 17373
c19d1205 17374 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 17375
c19d1205
ZW		 17376#if defined OBJ_COFF || defined OBJ_ELF
17377 ARM_SET_INTERWORK (sym, support_interwork);
17378#endif
b99bd4ef 17379
e07e6e58
NC		 17380 force_automatic_it_block_close ();
17381
5f4273c7 17382 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW		 17383 as Thumb functions. This is because these labels, whilst
17384 they exist inside Thumb code, are not the entry points for
17385 possible ARM->Thumb calls. Also, these labels can be used
17386 as part of a computed goto or switch statement. eg gcc
17387 can generate code that looks like this:
b99bd4ef 17388
c19d1205
ZW		 17389 ldr r2, [pc, .Laaa]
17390 lsl r3, r3, #2
17391 ldr r2, [r3, r2]
17392 mov pc, r2
b99bd4ef 17393
c19d1205
ZW		 17394 .Lbbb: .word .Lxxx
17395 .Lccc: .word .Lyyy
17396 ..etc...
17397 .Laaa: .word Lbbb
b99bd4ef 17398
c19d1205
ZW		 17399 The first instruction loads the address of the jump table.
17400 The second instruction converts a table index into a byte offset.
17401 The third instruction gets the jump address out of the table.
17402 The fourth instruction performs the jump.
b99bd4ef 17403
c19d1205
ZW		 17404 If the address stored at .Laaa is that of a symbol which has the
17405 Thumb_Func bit set, then the linker will arrange for this address
17406 to have the bottom bit set, which in turn would mean that the
17407 address computation performed by the third instruction would end
17408 up with the bottom bit set. Since the ARM is capable of unaligned
17409 word loads, the instruction would then load the incorrect address
17410 out of the jump table, and chaos would ensue. */
17411 if (label_is_thumb_function_name
17412 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17413 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 17414 {
c19d1205
ZW		 17415 /* When the address of a Thumb function is taken the bottom
17416 bit of that address should be set. This will allow
17417 interworking between Arm and Thumb functions to work
17418 correctly. */
b99bd4ef 17419
c19d1205 17420 THUMB_SET_FUNC (sym, 1);
b99bd4ef 17421
c19d1205 17422 label_is_thumb_function_name = FALSE;
b99bd4ef 17423 }
07a53e5c 17424
07a53e5c 17425 dwarf2_emit_label (sym);
b99bd4ef
NC		 17426}
17427
c921be7d 17428bfd_boolean
c19d1205 17429arm_data_in_code (void)
b99bd4ef 17430{
c19d1205 17431 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 17432 {
c19d1205
ZW		 17433 *input_line_pointer = '/';
17434 input_line_pointer += 5;
17435 *input_line_pointer = 0;
c921be7d 17436 return TRUE;
b99bd4ef
NC		 17437 }
17438
c921be7d 17439 return FALSE;
b99bd4ef
NC		 17440}
17441
c19d1205
ZW		 17442char *
17443arm_canonicalize_symbol_name (char * name)
b99bd4ef 17444{
c19d1205 17445 int len;
b99bd4ef 17446
c19d1205
ZW		 17447 if (thumb_mode && (len = strlen (name)) > 5
17448 && streq (name + len - 5, "/data"))
17449 *(name + len - 5) = 0;
b99bd4ef 17450
c19d1205 17451 return name;
b99bd4ef 17452}
c19d1205
ZW		 17453\f
17454/* Table of all register names defined by default. The user can
17455 define additional names with .req. Note that all register names
17456 should appear in both upper and lowercase variants. Some registers
17457 also have mixed-case names. */
b99bd4ef 17458
dcbf9037 17459#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 17460#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 17461#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW		 17462#define REGSET(p,t) \
17463 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17464 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17465 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17466 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB		 17467#define REGSETH(p,t) \
17468 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17469 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17470 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17471 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17472#define REGSET2(p,t) \
17473 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17474 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17475 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17476 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD		 17477#define SPLRBANK(base,bank,t) \
17478 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17479 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17480 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17481 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17482 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17483 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 17484
c19d1205 17485static const struct reg_entry reg_names[] =
7ed4c4c5 17486{
c19d1205
ZW		 17487 /* ARM integer registers. */
17488 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 17489
c19d1205
ZW		 17490 /* ATPCS synonyms. */
17491 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17492 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17493 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 17494
c19d1205
ZW		 17495 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17496 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17497 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 17498
c19d1205
ZW		 17499 /* Well-known aliases. */
17500 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17501 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17502
17503 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17504 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17505
17506 /* Coprocessor numbers. */
17507 REGSET(p, CP), REGSET(P, CP),
17508
17509 /* Coprocessor register numbers. The "cr" variants are for backward
17510 compatibility. */
17511 REGSET(c, CN), REGSET(C, CN),
17512 REGSET(cr, CN), REGSET(CR, CN),
17513
90ec0d68
MGD		 17514 /* ARM banked registers. */
17515 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17516 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17517 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17518 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17519 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17520 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17521 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17522
17523 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17524 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17525 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17526 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17527 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 17528 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD		 17529 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17530 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17531
17532 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17533 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17534 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17535 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17536 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17537 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17538 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 17539 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD		 17540 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17541
c19d1205
ZW		 17542 /* FPA registers. */
17543 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17544 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17545
17546 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17547 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17548
17549 /* VFP SP registers. */
5287ad62
JB		 17550 REGSET(s,VFS), REGSET(S,VFS),
17551 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW		 17552
17553 /* VFP DP Registers. */
5287ad62
JB		 17554 REGSET(d,VFD), REGSET(D,VFD),
17555 /* Extra Neon DP registers. */
17556 REGSETH(d,VFD), REGSETH(D,VFD),
17557
17558 /* Neon QP registers. */
17559 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW		 17560
17561 /* VFP control registers. */
17562 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17563 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB		 17564 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
17565 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
17566 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
17567 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
c19d1205
ZW		 17568
17569 /* Maverick DSP coprocessor registers. */
17570 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
17571 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
17572
17573 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
17574 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
17575 REGDEF(dspsc,0,DSPSC),
17576
17577 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
17578 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
17579 REGDEF(DSPSC,0,DSPSC),
17580
17581 /* iWMMXt data registers - p0, c0-15. */
17582 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
17583
17584 /* iWMMXt control registers - p1, c0-3. */
17585 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
17586 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
17587 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
17588 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
17589
17590 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17591 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
17592 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
17593 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
17594 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
17595
17596 /* XScale accumulator registers. */
17597 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
17598};
17599#undef REGDEF
17600#undef REGNUM
17601#undef REGSET
7ed4c4c5 17602
c19d1205
ZW		 17603/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17604 within psr_required_here. */
17605static const struct asm_psr psrs[] =
17606{
17607 /* Backward compatibility notation. Note that "all" is no longer
17608 truly all possible PSR bits. */
17609 {"all", PSR_c | PSR_f},
17610 {"flg", PSR_f},
17611 {"ctl", PSR_c},
17612
17613 /* Individual flags. */
17614 {"f", PSR_f},
17615 {"c", PSR_c},
17616 {"x", PSR_x},
17617 {"s", PSR_s},
59b42a0d 17618
c19d1205
ZW		 17619 /* Combinations of flags. */
17620 {"fs", PSR_f | PSR_s},
17621 {"fx", PSR_f | PSR_x},
17622 {"fc", PSR_f | PSR_c},
17623 {"sf", PSR_s | PSR_f},
17624 {"sx", PSR_s | PSR_x},
17625 {"sc", PSR_s | PSR_c},
17626 {"xf", PSR_x | PSR_f},
17627 {"xs", PSR_x | PSR_s},
17628 {"xc", PSR_x | PSR_c},
17629 {"cf", PSR_c | PSR_f},
17630 {"cs", PSR_c | PSR_s},
17631 {"cx", PSR_c | PSR_x},
17632 {"fsx", PSR_f | PSR_s | PSR_x},
17633 {"fsc", PSR_f | PSR_s | PSR_c},
17634 {"fxs", PSR_f | PSR_x | PSR_s},
17635 {"fxc", PSR_f | PSR_x | PSR_c},
17636 {"fcs", PSR_f | PSR_c | PSR_s},
17637 {"fcx", PSR_f | PSR_c | PSR_x},
17638 {"sfx", PSR_s | PSR_f | PSR_x},
17639 {"sfc", PSR_s | PSR_f | PSR_c},
17640 {"sxf", PSR_s | PSR_x | PSR_f},
17641 {"sxc", PSR_s | PSR_x | PSR_c},
17642 {"scf", PSR_s | PSR_c | PSR_f},
17643 {"scx", PSR_s | PSR_c | PSR_x},
17644 {"xfs", PSR_x | PSR_f | PSR_s},
17645 {"xfc", PSR_x | PSR_f | PSR_c},
17646 {"xsf", PSR_x | PSR_s | PSR_f},
17647 {"xsc", PSR_x | PSR_s | PSR_c},
17648 {"xcf", PSR_x | PSR_c | PSR_f},
17649 {"xcs", PSR_x | PSR_c | PSR_s},
17650 {"cfs", PSR_c | PSR_f | PSR_s},
17651 {"cfx", PSR_c | PSR_f | PSR_x},
17652 {"csf", PSR_c | PSR_s | PSR_f},
17653 {"csx", PSR_c | PSR_s | PSR_x},
17654 {"cxf", PSR_c | PSR_x | PSR_f},
17655 {"cxs", PSR_c | PSR_x | PSR_s},
17656 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
17657 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
17658 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
17659 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
17660 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
17661 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
17662 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
17663 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
17664 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
17665 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
17666 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
17667 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
17668 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
17669 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
17670 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
17671 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
17672 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
17673 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
17674 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
17675 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
17676 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
17677 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
17678 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
17679 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
17680};
17681
62b3e311
PB		 17682/* Table of V7M psr names. */
17683static const struct asm_psr v7m_psrs[] =
17684{
2b744c99
PB		 17685 {"apsr", 0 }, {"APSR", 0 },
17686 {"iapsr", 1 }, {"IAPSR", 1 },
17687 {"eapsr", 2 }, {"EAPSR", 2 },
17688 {"psr", 3 }, {"PSR", 3 },
17689 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17690 {"ipsr", 5 }, {"IPSR", 5 },
17691 {"epsr", 6 }, {"EPSR", 6 },
17692 {"iepsr", 7 }, {"IEPSR", 7 },
17693 {"msp", 8 }, {"MSP", 8 },
17694 {"psp", 9 }, {"PSP", 9 },
17695 {"primask", 16}, {"PRIMASK", 16},
17696 {"basepri", 17}, {"BASEPRI", 17},
00bbc0bd
NC		 17697 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17698 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
2b744c99
PB		 17699 {"faultmask", 19}, {"FAULTMASK", 19},
17700 {"control", 20}, {"CONTROL", 20}
62b3e311
PB		 17701};
17702
c19d1205
ZW		 17703/* Table of all shift-in-operand names. */
17704static const struct asm_shift_name shift_names [] =
b99bd4ef 17705{
c19d1205
ZW		 17706 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
17707 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
17708 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
17709 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
17710 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
17711 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
17712};
b99bd4ef 17713
c19d1205
ZW		 17714/* Table of all explicit relocation names. */
17715#ifdef OBJ_ELF
17716static struct reloc_entry reloc_names[] =
17717{
17718 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
17719 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
17720 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
17721 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
17722 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
17723 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
17724 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
17725 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
17726 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
17727 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 17728 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS		 17729 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
17730 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 17731 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 17732 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 17733 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 17734 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
477330fc 17735 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
c19d1205
ZW		 17736};
17737#endif
b99bd4ef 17738
c19d1205
ZW		 17739/* Table of all conditional affixes. 0xF is not defined as a condition code. */
17740static const struct asm_cond conds[] =
17741{
17742 {"eq", 0x0},
17743 {"ne", 0x1},
17744 {"cs", 0x2}, {"hs", 0x2},
17745 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17746 {"mi", 0x4},
17747 {"pl", 0x5},
17748 {"vs", 0x6},
17749 {"vc", 0x7},
17750 {"hi", 0x8},
17751 {"ls", 0x9},
17752 {"ge", 0xa},
17753 {"lt", 0xb},
17754 {"gt", 0xc},
17755 {"le", 0xd},
17756 {"al", 0xe}
17757};
bfae80f2 17758
e797f7e0
MGD		 17759#define UL_BARRIER(L,U,CODE,FEAT) \
17760 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17761 { U, CODE, ARM_FEATURE (FEAT, 0) }
17762
62b3e311
PB		 17763static struct asm_barrier_opt barrier_opt_names[] =
17764{
e797f7e0
MGD		 17765 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
17766 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
17767 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
17768 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
17769 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
17770 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
17771 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
17772 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
17773 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
17774 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
17775 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
17776 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
17777 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
17778 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
17779 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
17780 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB		 17781};
17782
e797f7e0
MGD		 17783#undef UL_BARRIER
17784
c19d1205
ZW		 17785/* Table of ARM-format instructions. */
17786
17787/* Macros for gluing together operand strings. N.B. In all cases
17788 other than OPS0, the trailing OP_stop comes from default
17789 zero-initialization of the unspecified elements of the array. */
17790#define OPS0() { OP_stop, }
17791#define OPS1(a) { OP_##a, }
17792#define OPS2(a,b) { OP_##a,OP_##b, }
17793#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17794#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17795#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17796#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17797
5be8be5d
DG		 17798/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17799 This is useful when mixing operands for ARM and THUMB, i.e. using the
17800 MIX_ARM_THUMB_OPERANDS macro.
17801 In order to use these macros, prefix the number of operands with _
17802 e.g. _3. */
17803#define OPS_1(a) { a, }
17804#define OPS_2(a,b) { a,b, }
17805#define OPS_3(a,b,c) { a,b,c, }
17806#define OPS_4(a,b,c,d) { a,b,c,d, }
17807#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17808#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17809
c19d1205
ZW		 17810/* These macros abstract out the exact format of the mnemonic table and
17811 save some repeated characters. */
17812
17813/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
17814#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 17815 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
1887dd22 17816 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW		 17817
17818/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
17819 a T_MNEM_xyz enumerator. */
17820#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 17821 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 17822#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 17823 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW		 17824
17825/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
17826 infix after the third character. */
17827#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 17828 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
1887dd22 17829 THUMB_VARIANT, do_##ae, do_##te }
088fa78e 17830#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 17831 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
088fa78e 17832 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 17833#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 17834 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 17835#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 17836 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 17837#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 17838 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 17839#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 17840 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 17841
c19d1205 17842/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB		 17843 field is still 0xE. Many of the Thumb variants can be executed
17844 conditionally, so this is checked separately. */
c19d1205 17845#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 17846 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 17847 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 17848
dd5181d5
KT		 17849/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
17850 Used by mnemonics that have very minimal differences in the encoding for
17851 ARM and Thumb variants and can be handled in a common function. */
17852#define TUEc(mnem, op, top, nops, ops, en) \
17853 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
17854 THUMB_VARIANT, do_##en, do_##en }
17855
c19d1205
ZW		 17856/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
17857 condition code field. */
17858#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 17859 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 17860 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW		 17861
17862/* ARM-only variants of all the above. */
6a86118a 17863#define CE(mnem, op, nops, ops, ae) \
21d799b5 17864 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
6a86118a
NC		 17865
17866#define C3(mnem, op, nops, ops, ae) \
17867 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17868
e3cb604e
PB		 17869/* Legacy mnemonics that always have conditional infix after the third
17870 character. */
17871#define CL(mnem, op, nops, ops, ae) \
21d799b5 17872 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB		 17873 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17874
8f06b2d8
PB		 17875/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
17876#define cCE(mnem, op, nops, ops, ae) \
21d799b5 17877 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 17878
e3cb604e
PB		 17879/* Legacy coprocessor instructions where conditional infix and conditional
17880 suffix are ambiguous. For consistency this includes all FPA instructions,
17881 not just the potentially ambiguous ones. */
17882#define cCL(mnem, op, nops, ops, ae) \
21d799b5 17883 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB		 17884 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
17885
17886/* Coprocessor, takes either a suffix or a position-3 infix
17887 (for an FPA corner case). */
17888#define C3E(mnem, op, nops, ops, ae) \
21d799b5 17889 { mnem, OPS##nops ops, OT_csuf_or_in3, \
e3cb604e 17890 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 17891
6a86118a 17892#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC		 17893 { m1 #m2 m3, OPS##nops ops, \
17894 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
6a86118a
NC		 17895 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17896
17897#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC		 17898 xCM_ (m1, , m2, op, nops, ops, ae), \
17899 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17900 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17901 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17902 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17903 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17904 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17905 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17906 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17907 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17908 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17909 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17910 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17911 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17912 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17913 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17914 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17915 xCM_ (m1, le, m2, op, nops, ops, ae), \
17916 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC		 17917
17918#define UE(mnem, op, nops, ops, ae) \
17919 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17920
17921#define UF(mnem, op, nops, ops, ae) \
17922 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17923
5287ad62
JB		 17924/* Neon data-processing. ARM versions are unconditional with cond=0xf.
17925 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17926 use the same encoding function for each. */
17927#define NUF(mnem, op, nops, ops, enc) \
17928 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17929 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17930
17931/* Neon data processing, version which indirects through neon_enc_tab for
17932 the various overloaded versions of opcodes. */
17933#define nUF(mnem, op, nops, ops, enc) \
21d799b5 17934 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5287ad62
JB		 17935 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17936
17937/* Neon insn with conditional suffix for the ARM version, non-overloaded
17938 version. */
037e8744
JB		 17939#define NCE_tag(mnem, op, nops, ops, enc, tag) \
17940 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5287ad62
JB		 17941 THUMB_VARIANT, do_##enc, do_##enc }
17942
037e8744 17943#define NCE(mnem, op, nops, ops, enc) \
e07e6e58 17944 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB		 17945
17946#define NCEF(mnem, op, nops, ops, enc) \
e07e6e58 17947 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 17948
5287ad62 17949/* Neon insn with conditional suffix for the ARM version, overloaded types. */
037e8744 17950#define nCE_tag(mnem, op, nops, ops, enc, tag) \
21d799b5 17951 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5287ad62
JB		 17952 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17953
037e8744 17954#define nCE(mnem, op, nops, ops, enc) \
e07e6e58 17955 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB		 17956
17957#define nCEF(mnem, op, nops, ops, enc) \
e07e6e58 17958 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 17959
c19d1205
ZW		 17960#define do_0 0
17961
c19d1205 17962static const struct asm_opcode insns[] =
bfae80f2 17963{
e74cfd16
PB		 17964#define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17965#define THUMB_VARIANT &arm_ext_v4t
21d799b5
NC		 17966 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
17967 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
17968 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
17969 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
17970 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
17971 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
17972 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
17973 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
17974 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
17975 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
17976 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
17977 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
17978 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
17979 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
17980 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
17981 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW		 17982
17983 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17984 for setting PSR flag bits. They are obsolete in V6 and do not
17985 have Thumb equivalents. */
21d799b5
NC		 17986 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17987 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
17988 CL("tstp", 110f000, 2, (RR, SH), cmp),
17989 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17990 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
17991 CL("cmpp", 150f000, 2, (RR, SH), cmp),
17992 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17993 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
17994 CL("cmnp", 170f000, 2, (RR, SH), cmp),
17995
17996 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
17997 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
17998 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
17999 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18000
18001 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG		 18002 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18003 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18004 OP_RRnpc),
18005 OP_ADDRGLDR),ldst, t_ldst),
18006 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC		 18007
18008 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18009 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18010 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18011 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18012 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18013 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18014
18015 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18016 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18017 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18018 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 18019
c19d1205 18020 /* Pseudo ops. */
21d799b5 18021 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 18022 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 18023 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
c19d1205
ZW		 18024
18025 /* Thumb-compatibility pseudo ops. */
21d799b5
NC		 18026 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18027 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18028 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18029 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18030 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18031 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18032 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18033 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18034 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18035 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18036 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18037 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 18038
16a4cf17 18039 /* These may simplify to neg. */
21d799b5
NC		 18040 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18041 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 18042
c921be7d
NC		 18043#undef THUMB_VARIANT
18044#define THUMB_VARIANT & arm_ext_v6
18045
21d799b5 18046 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW		 18047
18048 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC		 18049#undef THUMB_VARIANT
18050#define THUMB_VARIANT & arm_ext_v6t2
18051
21d799b5
NC		 18052 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18053 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18054 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 18055
5be8be5d
DG		 18056 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18057 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18058 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18059 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 18060
21d799b5
NC		 18061 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18062 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 18063
21d799b5
NC		 18064 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18065 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW		 18066
18067 /* V1 instructions with no Thumb analogue at all. */
21d799b5 18068 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW		 18069 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18070
18071 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18072 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18073 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18074 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18075 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18076 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18077 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18078 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18079
c921be7d
NC		 18080#undef ARM_VARIANT
18081#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18082#undef THUMB_VARIANT
18083#define THUMB_VARIANT & arm_ext_v4t
18084
21d799b5
NC		 18085 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18086 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 18087
c921be7d
NC		 18088#undef THUMB_VARIANT
18089#define THUMB_VARIANT & arm_ext_v6t2
18090
21d799b5 18091 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW		 18092 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18093
18094 /* Generic coprocessor instructions. */
21d799b5
NC		 18095 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18096 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18097 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18098 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18099 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18100 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 18101 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 18102
c921be7d
NC		 18103#undef ARM_VARIANT
18104#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18105
21d799b5 18106 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW		 18107 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18108
c921be7d
NC		 18109#undef ARM_VARIANT
18110#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18111#undef THUMB_VARIANT
18112#define THUMB_VARIANT & arm_ext_msr
18113
d2cd1205
JB		 18114 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18115 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 18116
c921be7d
NC		 18117#undef ARM_VARIANT
18118#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18119#undef THUMB_VARIANT
18120#define THUMB_VARIANT & arm_ext_v6t2
18121
21d799b5
NC		 18122 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18123 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18124 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18125 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18126 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18127 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18128 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18129 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 18130
c921be7d
NC		 18131#undef ARM_VARIANT
18132#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18133#undef THUMB_VARIANT
18134#define THUMB_VARIANT & arm_ext_v4t
18135
5be8be5d
DG		 18136 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18137 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18138 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18139 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE		 18140 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18141 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 18142
c921be7d
NC		 18143#undef ARM_VARIANT
18144#define ARM_VARIANT & arm_ext_v4t_5
18145
c19d1205
ZW		 18146 /* ARM Architecture 4T. */
18147 /* Note: bx (and blx) are required on V5, even if the processor does
18148 not support Thumb. */
21d799b5 18149 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 18150
c921be7d
NC		 18151#undef ARM_VARIANT
18152#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18153#undef THUMB_VARIANT
18154#define THUMB_VARIANT & arm_ext_v5t
18155
c19d1205
ZW		 18156 /* Note: blx has 2 variants; the .value coded here is for
18157 BLX(2). Only this variant has conditional execution. */
21d799b5
NC		 18158 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18159 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 18160
c921be7d
NC		 18161#undef THUMB_VARIANT
18162#define THUMB_VARIANT & arm_ext_v6t2
18163
21d799b5
NC		 18164 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18165 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18166 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18167 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18168 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18169 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18170 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18171 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 18172
c921be7d
NC		 18173#undef ARM_VARIANT
18174#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
9e3c6df6
PB		 18175#undef THUMB_VARIANT
18176#define THUMB_VARIANT &arm_ext_v5exp
c921be7d 18177
21d799b5
NC		 18178 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18179 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18180 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18181 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 18182
21d799b5
NC		 18183 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18184 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 18185
21d799b5
NC		 18186 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18187 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18188 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18189 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 18190
21d799b5
NC		 18191 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18192 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18193 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18194 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 18195
21d799b5
NC		 18196 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18197 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 18198
03ee1b7f
NC		 18199 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18200 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18201 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18202 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 18203
c921be7d
NC		 18204#undef ARM_VARIANT
18205#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
9e3c6df6
PB		 18206#undef THUMB_VARIANT
18207#define THUMB_VARIANT &arm_ext_v6t2
c921be7d 18208
21d799b5 18209 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG		 18210 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18211 ldrd, t_ldstd),
18212 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18213 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 18214
21d799b5
NC		 18215 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18216 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 18217
c921be7d
NC		 18218#undef ARM_VARIANT
18219#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18220
21d799b5 18221 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 18222
c921be7d
NC		 18223#undef ARM_VARIANT
18224#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18225#undef THUMB_VARIANT
18226#define THUMB_VARIANT & arm_ext_v6
18227
21d799b5
NC		 18228 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18229 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18230 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18231 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18232 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18233 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18234 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18235 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18236 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18237 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 18238
c921be7d
NC		 18239#undef THUMB_VARIANT
18240#define THUMB_VARIANT & arm_ext_v6t2
18241
5be8be5d
DG		 18242 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18243 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18244 strex, t_strex),
21d799b5
NC		 18245 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18246 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 18247
21d799b5
NC		 18248 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18249 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 18250
9e3c6df6 18251/* ARM V6 not included in V7M. */
c921be7d
NC		 18252#undef THUMB_VARIANT
18253#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 18254 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 18255 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB		 18256 UF(rfeib, 9900a00, 1, (RRw), rfe),
18257 UF(rfeda, 8100a00, 1, (RRw), rfe),
18258 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18259 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE		 18260 UF(rfefa, 8100a00, 1, (RRw), rfe),
18261 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18262 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 18263 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE		 18264 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18265 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 18266 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 18267 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 18268 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 18269 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 18270 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 18271 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
c921be7d 18272
9e3c6df6
PB		 18273/* ARM V6 not included in V7M (eg. integer SIMD). */
18274#undef THUMB_VARIANT
18275#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC		 18276 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18277 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18278 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18279 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18280 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18281 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18282 /* Old name for QASX. */
21d799b5
NC		 18283 TCE("qaddsubx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18284 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18285 /* Old name for QSAX. */
21d799b5
NC		 18286 TCE("qsubaddx", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18287 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18288 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18289 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18290 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18291 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18292 /* Old name for SASX. */
21d799b5
NC		 18293 TCE("saddsubx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18294 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18295 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18296 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18297 /* Old name for SHASX. */
21d799b5
NC		 18298 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18299 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18300 /* Old name for SHSAX. */
21d799b5
NC		 18301 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18302 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18303 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18304 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18305 /* Old name for SSAX. */
21d799b5
NC		 18306 TCE("ssubaddx", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18307 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18308 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18309 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18310 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18311 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18312 /* Old name for UASX. */
21d799b5
NC		 18313 TCE("uaddsubx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18314 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18315 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18316 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18317 /* Old name for UHASX. */
21d799b5
NC		 18318 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18319 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18320 /* Old name for UHSAX. */
21d799b5
NC		 18321 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18322 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18323 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18324 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18325 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18326 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18327 /* Old name for UQASX. */
21d799b5
NC		 18328 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18329 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18330 /* Old name for UQSAX. */
21d799b5
NC		 18331 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18332 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18333 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18334 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18335 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18336 /* Old name for USAX. */
21d799b5
NC		 18337 TCE("usubaddx", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18338 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18339 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18340 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18341 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18342 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18343 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18344 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18345 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18346 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18347 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18348 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18349 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18350 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18351 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18352 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18353 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18354 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18355 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18356 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18357 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18358 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18359 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18360 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18361 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18362 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18363 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18364 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18365 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC		 18366 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18367 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18368 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18369 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18370 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 18371
c921be7d
NC		 18372#undef ARM_VARIANT
18373#define ARM_VARIANT & arm_ext_v6k
18374#undef THUMB_VARIANT
18375#define THUMB_VARIANT & arm_ext_v6k
18376
21d799b5
NC		 18377 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18378 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18379 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18380 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 18381
c921be7d
NC		 18382#undef THUMB_VARIANT
18383#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG		 18384 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18385 ldrexd, t_ldrexd),
18386 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18387 RRnpcb), strexd, t_strexd),
ebdca51a 18388
c921be7d
NC		 18389#undef THUMB_VARIANT
18390#define THUMB_VARIANT & arm_ext_v6t2
5be8be5d
DG		 18391 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18392 rd_rn, rd_rn),
18393 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18394 rd_rn, rd_rn),
18395 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 18396 strex, t_strexbh),
5be8be5d 18397 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 18398 strex, t_strexbh),
21d799b5 18399 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 18400
c921be7d 18401#undef ARM_VARIANT
f4c65163
MGD		 18402#define ARM_VARIANT & arm_ext_sec
18403#undef THUMB_VARIANT
18404#define THUMB_VARIANT & arm_ext_sec
c921be7d 18405
21d799b5 18406 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 18407
90ec0d68
MGD		 18408#undef ARM_VARIANT
18409#define ARM_VARIANT & arm_ext_virt
18410#undef THUMB_VARIANT
18411#define THUMB_VARIANT & arm_ext_virt
18412
18413 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18414 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18415
c921be7d
NC		 18416#undef ARM_VARIANT
18417#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD		 18418#undef THUMB_VARIANT
18419#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 18420
21d799b5
NC		 18421 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18422 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18423 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18424 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 18425
21d799b5
NC		 18426 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18427 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18428 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18429 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 18430
5be8be5d
DG		 18431 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18432 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18433 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18434 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 18435
bf3eeda7
NS		 18436 /* Thumb-only instructions. */
18437#undef ARM_VARIANT
18438#define ARM_VARIANT NULL
18439 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18440 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC		 18441
18442 /* ARM does not really have an IT instruction, so always allow it.
18443 The opcode is copied from Thumb in order to allow warnings in
18444 -mimplicit-it=[never | arm] modes. */
18445#undef ARM_VARIANT
18446#define ARM_VARIANT & arm_ext_v1
18447
21d799b5
NC		 18448 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18449 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18450 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18451 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18452 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18453 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18454 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18455 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18456 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18457 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18458 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18459 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18460 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18461 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18462 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 18463 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC		 18464 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18465 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 18466
92e90b6e 18467 /* Thumb2 only instructions. */
c921be7d
NC		 18468#undef ARM_VARIANT
18469#define ARM_VARIANT NULL
92e90b6e 18470
21d799b5
NC		 18471 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18472 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18473 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18474 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18475 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18476 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 18477
eea54501
MGD		 18478 /* Hardware division instructions. */
18479#undef ARM_VARIANT
18480#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC		 18481#undef THUMB_VARIANT
18482#define THUMB_VARIANT & arm_ext_div
18483
eea54501
MGD		 18484 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18485 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 18486
7e806470 18487 /* ARM V6M/V7 instructions. */
c921be7d
NC		 18488#undef ARM_VARIANT
18489#define ARM_VARIANT & arm_ext_barrier
18490#undef THUMB_VARIANT
18491#define THUMB_VARIANT & arm_ext_barrier
18492
ccb84d65
JB		 18493 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18494 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18495 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 18496
62b3e311 18497 /* ARM V7 instructions. */
c921be7d
NC		 18498#undef ARM_VARIANT
18499#define ARM_VARIANT & arm_ext_v7
18500#undef THUMB_VARIANT
18501#define THUMB_VARIANT & arm_ext_v7
18502
21d799b5
NC		 18503 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18504 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 18505
60e5ef9f
MGD		 18506#undef ARM_VARIANT
18507#define ARM_VARIANT & arm_ext_mp
18508#undef THUMB_VARIANT
18509#define THUMB_VARIANT & arm_ext_mp
18510
18511 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18512
53c4b28b
MGD		 18513 /* AArchv8 instructions. */
18514#undef ARM_VARIANT
18515#define ARM_VARIANT & arm_ext_v8
18516#undef THUMB_VARIANT
18517#define THUMB_VARIANT & arm_ext_v8
18518
18519 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
8884b720 18520 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
4b8c8c02
RE		 18521 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18522 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
9eb6c0f1 18523 ldrexd, t_ldrexd),
4b8c8c02
RE		 18524 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18525 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18526 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18527 stlex, t_stlex),
18528 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
9eb6c0f1 18529 strexd, t_strexd),
4b8c8c02
RE		 18530 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18531 stlex, t_stlex),
18532 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18533 stlex, t_stlex),
18534 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18535 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18536 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18537 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18538 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18539 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
53c4b28b 18540
8884b720 18541 /* ARMv8 T32 only. */
b79f7053
MGD		 18542#undef ARM_VARIANT
18543#define ARM_VARIANT NULL
18544 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18545 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18546 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18547
33399f07
MGD		 18548 /* FP for ARMv8. */
18549#undef ARM_VARIANT
18550#define ARM_VARIANT & fpu_vfp_ext_armv8
18551#undef THUMB_VARIANT
18552#define THUMB_VARIANT & fpu_vfp_ext_armv8
18553
18554 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18555 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18556 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18557 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
73924fbc
MGD		 18558 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18559 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
7e8e6784
MGD		 18560 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18561 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18562 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
18563 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
30bdf752
MGD		 18564 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
18565 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
18566 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
18567 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
18568 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
18569 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
18570 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
33399f07 18571
91ff7894
MGD		 18572 /* Crypto v1 extensions. */
18573#undef ARM_VARIANT
18574#define ARM_VARIANT & fpu_crypto_ext_armv8
18575#undef THUMB_VARIANT
18576#define THUMB_VARIANT & fpu_crypto_ext_armv8
18577
18578 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
18579 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
18580 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
18581 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD		 18582 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
18583 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
18584 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
18585 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
18586 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
18587 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
18588 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD		 18589 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
18590 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
18591 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 18592
dd5181d5
KT		 18593#undef ARM_VARIANT
18594#define ARM_VARIANT & crc_ext_armv8
18595#undef THUMB_VARIANT
18596#define THUMB_VARIANT & crc_ext_armv8
18597 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
18598 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
18599 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
18600 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
18601 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
18602 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
18603
c921be7d
NC		 18604#undef ARM_VARIANT
18605#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD		 18606#undef THUMB_VARIANT
18607#define THUMB_VARIANT NULL
c921be7d 18608
21d799b5
NC		 18609 cCE("wfs", e200110, 1, (RR), rd),
18610 cCE("rfs", e300110, 1, (RR), rd),
18611 cCE("wfc", e400110, 1, (RR), rd),
18612 cCE("rfc", e500110, 1, (RR), rd),
18613
18614 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
18615 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
18616 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
18617 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
18618
18619 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
18620 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
18621 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
18622 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
18623
18624 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
18625 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
18626 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
18627 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
18628 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
18629 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
18630 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
18631 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
18632 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
18633 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
18634 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
18635 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
18636
18637 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
18638 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
18639 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
18640 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
18641 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
18642 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
18643 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
18644 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
18645 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
18646 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
18647 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
18648 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
18649
18650 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
18651 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
18652 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
18653 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
18654 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
18655 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
18656 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
18657 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
18658 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
18659 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
18660 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
18661 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
18662
18663 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
18664 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
18665 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
18666 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
18667 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
18668 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
18669 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
18670 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
18671 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
18672 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
18673 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
18674 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
18675
18676 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
18677 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
18678 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
18679 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
18680 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
18681 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
18682 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
18683 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
18684 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
18685 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
18686 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
18687 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
18688
18689 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
18690 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
18691 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
18692 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
18693 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
18694 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
18695 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
18696 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
18697 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
18698 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
18699 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
18700 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
18701
18702 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
18703 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
18704 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
18705 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
18706 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
18707 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
18708 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
18709 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
18710 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
18711 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
18712 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
18713 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
18714
18715 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
18716 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
18717 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
18718 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
18719 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
18720 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
18721 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
18722 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
18723 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
18724 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
18725 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
18726 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
18727
18728 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
18729 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
18730 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
18731 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
18732 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
18733 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
18734 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
18735 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
18736 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
18737 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
18738 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
18739 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
18740
18741 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
18742 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
18743 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
18744 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
18745 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
18746 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
18747 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
18748 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
18749 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
18750 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
18751 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
18752 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
18753
18754 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
18755 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
18756 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
18757 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
18758 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
18759 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
18760 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
18761 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
18762 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
18763 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
18764 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
18765 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
18766
18767 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
18768 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
18769 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
18770 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
18771 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
18772 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
18773 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
18774 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
18775 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
18776 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
18777 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
18778 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
18779
18780 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
18781 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
18782 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
18783 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
18784 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
18785 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
18786 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
18787 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
18788 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
18789 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
18790 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
18791 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
18792
18793 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
18794 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
18795 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
18796 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
18797 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
18798 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
18799 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
18800 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
18801 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
18802 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
18803 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
18804 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
18805
18806 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
18807 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
18808 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
18809 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
18810 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
18811 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
18812 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
18813 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
18814 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
18815 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
18816 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
18817 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
18818
18819 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
18820 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
18821 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
18822 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
18823 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
18824 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
18825 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
18826 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
18827 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
18828 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
18829 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
18830 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
18831
18832 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
18833 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
18834 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
18835 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
18836 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
18837 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18838 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18839 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18840 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
18841 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
18842 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
18843 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
18844
18845 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
18846 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
18847 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
18848 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
18849 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
18850 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18851 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18852 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18853 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
18854 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
18855 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
18856 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
18857
18858 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
18859 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
18860 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
18861 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
18862 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
18863 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18864 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18865 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18866 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
18867 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
18868 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
18869 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
18870
18871 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
18872 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
18873 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
18874 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
18875 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
18876 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18877 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18878 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18879 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
18880 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
18881 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
18882 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
18883
18884 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
18885 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
18886 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
18887 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
18888 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
18889 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18890 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18891 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18892 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
18893 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
18894 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
18895 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
18896
18897 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
18898 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
18899 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
18900 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
18901 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
18902 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18903 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18904 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18905 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
18906 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
18907 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
18908 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
18909
18910 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
18911 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
18912 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
18913 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
18914 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
18915 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18916 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18917 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18918 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
18919 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
18920 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
18921 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
18922
18923 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
18924 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
18925 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
18926 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
18927 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
18928 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18929 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18930 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18931 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
18932 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
18933 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
18934 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
18935
18936 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
18937 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
18938 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
18939 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
18940 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
18941 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18942 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18943 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18944 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
18945 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
18946 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
18947 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
18948
18949 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
18950 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
18951 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
18952 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
18953 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
18954 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18955 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18956 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18957 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
18958 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
18959 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
18960 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
18961
18962 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18963 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18964 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18965 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18966 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18967 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18968 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18969 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18970 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18971 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18972 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18973 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18974
18975 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18976 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18977 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18978 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18979 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18980 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18981 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18982 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18983 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18984 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18985 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18986 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
18987
18988 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
18989 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
18990 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
18991 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
18992 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
18993 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
18994 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
18995 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
18996 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
18997 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
18998 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
18999 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19000
19001 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19002 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19003 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19004 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19005
19006 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19007 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19008 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19009 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19010 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19011 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19012 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19013 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19014 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19015 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19016 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19017 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 19018
c19d1205
ZW		 19019 /* The implementation of the FIX instruction is broken on some
19020 assemblers, in that it accepts a precision specifier as well as a
19021 rounding specifier, despite the fact that this is meaningless.
19022 To be more compatible, we accept it as well, though of course it
19023 does not set any bits. */
21d799b5
NC		 19024 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19025 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19026 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19027 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19028 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19029 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19030 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19031 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19032 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19033 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19034 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19035 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19036 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 19037
c19d1205 19038 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC		 19039#undef ARM_VARIANT
19040#define ARM_VARIANT & fpu_fpa_ext_v2
19041
21d799b5
NC		 19042 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19043 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19044 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19045 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19046 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19047 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 19048
c921be7d
NC		 19049#undef ARM_VARIANT
19050#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19051
c19d1205 19052 /* Moves and type conversions. */
21d799b5
NC		 19053 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19054 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19055 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19056 cCE("fmstat", ef1fa10, 0, (), noargs),
7465e07a
NC		 19057 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19058 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
21d799b5
NC		 19059 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19060 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19061 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19062 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19063 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19064 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19065 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19066 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW		 19067
19068 /* Memory operations. */
21d799b5
NC		 19069 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19070 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD		 19071 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19072 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19073 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19074 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19075 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19076 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19077 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19078 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19079 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19080 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19081 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19082 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19083 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19084 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19085 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19086 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 19087
c19d1205 19088 /* Monadic operations. */
21d799b5
NC		 19089 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19090 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19091 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW		 19092
19093 /* Dyadic operations. */
21d799b5
NC		 19094 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19095 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19096 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19097 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19098 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19099 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19100 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19101 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19102 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 19103
c19d1205 19104 /* Comparisons. */
21d799b5
NC		 19105 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19106 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19107 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19108 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 19109
62f3b8c8
PB		 19110 /* Double precision load/store are still present on single precision
19111 implementations. */
19112 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19113 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD		 19114 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19115 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19116 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19117 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19118 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19119 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19120 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19121 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 19122
c921be7d
NC		 19123#undef ARM_VARIANT
19124#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19125
c19d1205 19126 /* Moves and type conversions. */
21d799b5
NC		 19127 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19128 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19129 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19130 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19131 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19132 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19133 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19134 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19135 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19136 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19137 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19138 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19139 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 19140
c19d1205 19141 /* Monadic operations. */
21d799b5
NC		 19142 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19143 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19144 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW		 19145
19146 /* Dyadic operations. */
21d799b5
NC		 19147 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19148 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19149 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19150 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19151 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19152 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19153 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19154 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19155 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 19156
c19d1205 19157 /* Comparisons. */
21d799b5
NC		 19158 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19159 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19160 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19161 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 19162
c921be7d
NC		 19163#undef ARM_VARIANT
19164#define ARM_VARIANT & fpu_vfp_ext_v2
19165
21d799b5
NC		 19166 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19167 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19168 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19169 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
5287ad62 19170
037e8744
JB		 19171/* Instructions which may belong to either the Neon or VFP instruction sets.
19172 Individual encoder functions perform additional architecture checks. */
c921be7d
NC		 19173#undef ARM_VARIANT
19174#define ARM_VARIANT & fpu_vfp_ext_v1xd
19175#undef THUMB_VARIANT
19176#define THUMB_VARIANT & fpu_vfp_ext_v1xd
19177
037e8744
JB		 19178 /* These mnemonics are unique to VFP. */
19179 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19180 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC		 19181 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19182 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19183 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19184 nCE(vcmp, _vcmp, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
19185 nCE(vcmpe, _vcmpe, 2, (RVSD, RVSD_I0), vfp_nsyn_cmp),
037e8744
JB		 19186 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19187 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19188 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19189
19190 /* Mnemonics shared by Neon and VFP. */
21d799b5
NC		 19191 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19192 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19193 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 19194
21d799b5
NC		 19195 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19196 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
037e8744
JB		 19197
19198 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19199 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19200
55881a11
MGD		 19201 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19202 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19203 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19204 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19205 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19206 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
4962c51a
MS		 19207 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19208 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
037e8744 19209
5f1af56b 19210 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
e3e535bc 19211 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
c70a8987
MGD		 19212 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19213 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
f31fef98 19214
037e8744
JB		 19215
19216 /* NOTE: All VMOV encoding is special-cased! */
19217 NCE(vmov, 0, 1, (VMOV), neon_mov),
19218 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19219
c921be7d
NC		 19220#undef THUMB_VARIANT
19221#define THUMB_VARIANT & fpu_neon_ext_v1
19222#undef ARM_VARIANT
19223#define ARM_VARIANT & fpu_neon_ext_v1
19224
5287ad62
JB		 19225 /* Data processing with three registers of the same length. */
19226 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19227 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19228 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19229 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19230 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19231 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19232 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19233 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19234 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19235 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19236 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19237 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19238 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19239 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7
JB		 19240 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19241 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19242 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19243 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62
JB		 19244 /* If not immediate, fall back to neon_dyadic_i64_su.
19245 shl_imm should accept I8 I16 I32 I64,
19246 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21d799b5
NC		 19247 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19248 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19249 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19250 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
5287ad62 19251 /* Logic ops, types optional & ignored. */
4316f0d2
DG		 19252 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19253 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19254 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19255 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19256 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19257 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19258 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19259 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19260 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19261 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB		 19262 /* Bitfield ops, untyped. */
19263 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19264 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19265 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19266 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19267 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19268 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19269 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
21d799b5
NC		 19270 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19271 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19272 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19273 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19274 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19275 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB		 19276 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19277 back to neon_dyadic_if_su. */
21d799b5
NC		 19278 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19279 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19280 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19281 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19282 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19283 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19284 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19285 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 19286 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC		 19287 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19288 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 19289 /* As above, D registers only. */
21d799b5
NC		 19290 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19291 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 19292 /* Int and float variants, signedness unimportant. */
21d799b5
NC		 19293 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19294 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19295 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 19296 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC		 19297 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19298 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB		 19299 /* vtst takes sizes 8, 16, 32. */
19300 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19301 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19302 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 19303 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 19304 /* VQD{R}MULH takes S16 S32. */
21d799b5
NC		 19305 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19306 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19307 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19308 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB		 19309 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19310 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19311 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19312 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB		 19313 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19314 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19315 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19316 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB		 19317 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19318 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19319 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19320 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19321
19322 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 19323 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB		 19324 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19325
19326 /* Data processing with two registers and a shift amount. */
19327 /* Right shifts, and variants with rounding.
19328 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19329 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19330 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19331 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19332 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19333 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19334 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19335 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19336 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19337 /* Shift and insert. Sizes accepted 8 16 32 64. */
19338 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19339 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19340 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19341 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19342 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19343 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19344 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19345 /* Right shift immediate, saturating & narrowing, with rounding variants.
19346 Types accepted S16 S32 S64 U16 U32 U64. */
19347 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19348 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19349 /* As above, unsigned. Types accepted S16 S32 S64. */
19350 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19351 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19352 /* Right shift narrowing. Types accepted I16 I32 I64. */
19353 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19354 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19355 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 19356 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 19357 /* CVT with optional immediate for fixed-point variant. */
21d799b5 19358 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 19359
4316f0d2
DG		 19360 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19361 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB		 19362
19363 /* Data processing, three registers of different lengths. */
19364 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19365 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19366 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19367 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19368 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19369 /* If not scalar, fall back to neon_dyadic_long.
19370 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC		 19371 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19372 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB		 19373 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19374 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19375 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19376 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19377 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19378 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19379 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19380 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19381 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC		 19382 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19383 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19384 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB		 19385 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19386 S16 S32 U16 U32. */
21d799b5 19387 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB		 19388
19389 /* Extract. Size 8. */
3b8d421e
PB		 19390 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19391 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB		 19392
19393 /* Two registers, miscellaneous. */
19394 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19395 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19396 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19397 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19398 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19399 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19400 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19401 /* Vector replicate. Sizes 8 16 32. */
21d799b5
NC		 19402 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19403 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB		 19404 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19405 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19406 /* VMOVN. Types I16 I32 I64. */
21d799b5 19407 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 19408 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 19409 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 19410 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 19411 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB		 19412 /* VZIP / VUZP. Sizes 8 16 32. */
19413 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19414 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19415 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19416 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19417 /* VQABS / VQNEG. Types S8 S16 S32. */
19418 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19419 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19420 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19421 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19422 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19423 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19424 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19425 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19426 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19427 /* Reciprocal estimates. Types U32 F32. */
19428 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19429 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19430 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19431 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19432 /* VCLS. Types S8 S16 S32. */
19433 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19434 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19435 /* VCLZ. Types I8 I16 I32. */
19436 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19437 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19438 /* VCNT. Size 8. */
19439 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19440 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19441 /* Two address, untyped. */
19442 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19443 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19444 /* VTRN. Sizes 8 16 32. */
21d799b5
NC		 19445 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19446 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB		 19447
19448 /* Table lookup. Size 8. */
19449 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19450 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19451
c921be7d
NC		 19452#undef THUMB_VARIANT
19453#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19454#undef ARM_VARIANT
19455#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19456
5287ad62 19457 /* Neon element/structure load/store. */
21d799b5
NC		 19458 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19459 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19460 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19461 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19462 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19463 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19464 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19465 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 19466
c921be7d 19467#undef THUMB_VARIANT
62f3b8c8
PB		 19468#define THUMB_VARIANT &fpu_vfp_ext_v3xd
19469#undef ARM_VARIANT
19470#define ARM_VARIANT &fpu_vfp_ext_v3xd
19471 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19472 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19473 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19474 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19475 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19476 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19477 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19478 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19479 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19480
19481#undef THUMB_VARIANT
c921be7d
NC		 19482#define THUMB_VARIANT & fpu_vfp_ext_v3
19483#undef ARM_VARIANT
19484#define ARM_VARIANT & fpu_vfp_ext_v3
19485
21d799b5 19486 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 19487 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19488 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19489 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19490 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19491 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19492 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19493 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19494 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 19495
62f3b8c8
PB		 19496#undef ARM_VARIANT
19497#define ARM_VARIANT &fpu_vfp_ext_fma
19498#undef THUMB_VARIANT
19499#define THUMB_VARIANT &fpu_vfp_ext_fma
19500 /* Mnemonics shared by Neon and VFP. These are included in the
19501 VFP FMA variant; NEON and VFP FMA always includes the NEON
19502 FMA instructions. */
19503 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19504 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19505 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19506 the v form should always be used. */
19507 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19508 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19509 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19510 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19511 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19512 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19513
5287ad62 19514#undef THUMB_VARIANT
c921be7d
NC		 19515#undef ARM_VARIANT
19516#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19517
21d799b5
NC		 19518 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19519 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19520 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19521 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19522 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19523 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19524 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19525 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 19526
c921be7d
NC		 19527#undef ARM_VARIANT
19528#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19529
21d799b5
NC		 19530 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19531 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19532 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19533 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19534 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19535 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19536 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19537 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19538 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
19539 cCE("textrmub", e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19540 cCE("textrmuh", e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19541 cCE("textrmuw", e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19542 cCE("textrmsb", e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19543 cCE("textrmsh", e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19544 cCE("textrmsw", e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19545 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19546 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19547 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19548 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19549 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19550 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19551 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19552 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19553 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19554 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19555 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19556 cCE("tmovmskb", e100030, 2, (RR, RIWR), rd_rn),
19557 cCE("tmovmskh", e500030, 2, (RR, RIWR), rd_rn),
19558 cCE("tmovmskw", e900030, 2, (RR, RIWR), rd_rn),
19559 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19560 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19561 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19562 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
19563 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
19564 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
19565 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
19566 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
19567 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19568 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19569 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19570 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19571 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19572 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19573 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19574 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19575 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19576 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
19577 cCE("walignr0", e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19578 cCE("walignr1", e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19579 cCE("walignr2", ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19580 cCE("walignr3", eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19581 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19582 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19583 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19584 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19585 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19586 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19587 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19588 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19589 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19590 cCE("wcmpgtub", e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19591 cCE("wcmpgtuh", e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19592 cCE("wcmpgtuw", e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19593 cCE("wcmpgtsb", e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19594 cCE("wcmpgtsh", e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19595 cCE("wcmpgtsw", eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19596 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19597 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19598 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19599 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19600 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19601 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19602 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19603 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19604 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19605 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19606 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19607 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19608 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19609 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19610 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19611 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19612 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19613 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19614 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19615 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19616 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19617 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19618 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
19619 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19620 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19621 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19622 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19623 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19624 cCE("wpackhss", e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19625 cCE("wpackhus", e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19626 cCE("wpackwss", eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19627 cCE("wpackwus", e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19628 cCE("wpackdss", ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19629 cCE("wpackdus", ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19630 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19631 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19632 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19633 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19634 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19635 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19636 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19637 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19638 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19639 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19640 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
19641 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19642 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19643 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19644 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19645 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19646 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19647 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19648 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19649 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19650 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19651 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19652 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19653 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19654 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19655 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19656 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19657 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
19658 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
19659 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19660 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
19661 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
19662 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
19663 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19664 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19665 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19666 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19667 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19668 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19669 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19670 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19671 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19672 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
19673 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
19674 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
19675 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
19676 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
19677 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
19678 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19679 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19680 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19681 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
19682 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
19683 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
19684 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
19685 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
19686 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
19687 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19688 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19689 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19690 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19691 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 19692
c921be7d
NC		 19693#undef ARM_VARIANT
19694#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19695
21d799b5
NC		 19696 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
19697 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
19698 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
19699 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
19700 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
19701 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
19702 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19703 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19704 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19705 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19706 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19707 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19708 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19709 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19710 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19711 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19712 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19713 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19714 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19715 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19716 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
19717 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19718 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19719 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19720 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19721 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19722 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19723 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19724 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19725 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19726 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19727 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19728 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19729 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19730 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19731 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19732 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19733 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19734 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19735 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19736 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19737 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19738 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19739 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19740 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19741 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19742 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19743 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19744 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19745 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19746 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19747 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19748 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19749 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19750 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19751 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
19752 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 19753
c921be7d
NC		 19754#undef ARM_VARIANT
19755#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19756
21d799b5
NC		 19757 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19758 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19759 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19760 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19761 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
19762 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
19763 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
19764 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
19765 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
19766 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
19767 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
19768 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
19769 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
19770 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
19771 cCE("cfmv64lr", e000510, 2, (RMDX, RR), rn_rd),
19772 cCE("cfmvr64l", e100510, 2, (RR, RMDX), rd_rn),
19773 cCE("cfmv64hr", e000530, 2, (RMDX, RR), rn_rd),
19774 cCE("cfmvr64h", e100530, 2, (RR, RMDX), rd_rn),
19775 cCE("cfmval32", e200440, 2, (RMAX, RMFX), rd_rn),
19776 cCE("cfmv32al", e100440, 2, (RMFX, RMAX), rd_rn),
19777 cCE("cfmvam32", e200460, 2, (RMAX, RMFX), rd_rn),
19778 cCE("cfmv32am", e100460, 2, (RMFX, RMAX), rd_rn),
19779 cCE("cfmvah32", e200480, 2, (RMAX, RMFX), rd_rn),
19780 cCE("cfmv32ah", e100480, 2, (RMFX, RMAX), rd_rn),
19781 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
19782 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
19783 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
19784 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
19785 cCE("cfmvsc32", e2004e0, 2, (RMDS, RMDX), mav_dspsc),
19786 cCE("cfmv32sc", e1004e0, 2, (RMDX, RMDS), rd),
19787 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
19788 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
19789 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
19790 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
19791 cCE("cfcvt32s", e000480, 2, (RMF, RMFX), rd_rn),
19792 cCE("cfcvt32d", e0004a0, 2, (RMD, RMFX), rd_rn),
19793 cCE("cfcvt64s", e0004c0, 2, (RMF, RMDX), rd_rn),
19794 cCE("cfcvt64d", e0004e0, 2, (RMD, RMDX), rd_rn),
19795 cCE("cfcvts32", e100580, 2, (RMFX, RMF), rd_rn),
19796 cCE("cfcvtd32", e1005a0, 2, (RMFX, RMD), rd_rn),
19797 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
19798 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
19799 cCE("cfrshl32", e000550, 3, (RMFX, RMFX, RR), mav_triple),
19800 cCE("cfrshl64", e000570, 3, (RMDX, RMDX, RR), mav_triple),
19801 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
19802 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
19803 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
19804 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
19805 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
19806 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
19807 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
19808 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
19809 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
19810 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
19811 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
19812 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
19813 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
19814 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
19815 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
19816 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
19817 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
19818 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
19819 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
19820 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
19821 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19822 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19823 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19824 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19825 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19826 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
19827 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19828 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
19829 cCE("cfmadd32", e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19830 cCE("cfmsub32", e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
19831 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
19832 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
c19d1205
ZW		 19833};
19834#undef ARM_VARIANT
19835#undef THUMB_VARIANT
19836#undef TCE
c19d1205
ZW		 19837#undef TUE
19838#undef TUF
19839#undef TCC
8f06b2d8 19840#undef cCE
e3cb604e
PB		 19841#undef cCL
19842#undef C3E
c19d1205
ZW		 19843#undef CE
19844#undef CM
19845#undef UE
19846#undef UF
19847#undef UT
5287ad62
JB		 19848#undef NUF
19849#undef nUF
19850#undef NCE
19851#undef nCE
c19d1205
ZW		 19852#undef OPS0
19853#undef OPS1
19854#undef OPS2
19855#undef OPS3
19856#undef OPS4
19857#undef OPS5
19858#undef OPS6
19859#undef do_0
19860\f
19861/* MD interface: bits in the object file. */
bfae80f2 19862
c19d1205
ZW		 19863/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
19864 for use in the a.out file, and stores them in the array pointed to by buf.
19865 This knows about the endian-ness of the target machine and does
19866 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
19867 2 (short) and 4 (long) Floating numbers are put out as a series of
19868 LITTLENUMS (shorts, here at least). */
b99bd4ef 19869
c19d1205
ZW		 19870void
19871md_number_to_chars (char * buf, valueT val, int n)
19872{
19873 if (target_big_endian)
19874 number_to_chars_bigendian (buf, val, n);
19875 else
19876 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE		 19877}
19878
c19d1205
ZW		 19879static valueT
19880md_chars_to_number (char * buf, int n)
bfae80f2 19881{
c19d1205
ZW		 19882 valueT result = 0;
19883 unsigned char * where = (unsigned char *) buf;
bfae80f2 19884
c19d1205 19885 if (target_big_endian)
b99bd4ef 19886 {
c19d1205
ZW		 19887 while (n--)
19888 {
19889 result <<= 8;
19890 result |= (*where++ & 255);
19891 }
b99bd4ef 19892 }
c19d1205 19893 else
b99bd4ef 19894 {
c19d1205
ZW		 19895 while (n--)
19896 {
19897 result <<= 8;
19898 result |= (where[n] & 255);
19899 }
bfae80f2 19900 }
b99bd4ef 19901
c19d1205 19902 return result;
bfae80f2 19903}
b99bd4ef 19904
c19d1205 19905/* MD interface: Sections. */
b99bd4ef 19906
fa94de6b
RM		 19907/* Calculate the maximum variable size (i.e., excluding fr_fix)
19908 that an rs_machine_dependent frag may reach. */
19909
19910unsigned int
19911arm_frag_max_var (fragS *fragp)
19912{
19913 /* We only use rs_machine_dependent for variable-size Thumb instructions,
19914 which are either THUMB_SIZE (2) or INSN_SIZE (4).
19915
19916 Note that we generate relaxable instructions even for cases that don't
19917 really need it, like an immediate that's a trivial constant. So we're
19918 overestimating the instruction size for some of those cases. Rather
19919 than putting more intelligence here, it would probably be better to
19920 avoid generating a relaxation frag in the first place when it can be
19921 determined up front that a short instruction will suffice. */
19922
19923 gas_assert (fragp->fr_type == rs_machine_dependent);
19924 return INSN_SIZE;
19925}
19926
0110f2b8
PB		 19927/* Estimate the size of a frag before relaxing. Assume everything fits in
19928 2 bytes. */
19929
c19d1205 19930int
0110f2b8 19931md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW		 19932 segT segtype ATTRIBUTE_UNUSED)
19933{
0110f2b8
PB		 19934 fragp->fr_var = 2;
19935 return 2;
19936}
19937
19938/* Convert a machine dependent frag. */
19939
19940void
19941md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
19942{
19943 unsigned long insn;
19944 unsigned long old_op;
19945 char *buf;
19946 expressionS exp;
19947 fixS *fixp;
19948 int reloc_type;
19949 int pc_rel;
19950 int opcode;
19951
19952 buf = fragp->fr_literal + fragp->fr_fix;
19953
19954 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC		 19955 if (fragp->fr_symbol)
19956 {
0110f2b8
PB		 19957 exp.X_op = O_symbol;
19958 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC		 19959 }
19960 else
19961 {
0110f2b8 19962 exp.X_op = O_constant;
5f4273c7 19963 }
0110f2b8
PB		 19964 exp.X_add_number = fragp->fr_offset;
19965 opcode = fragp->fr_subtype;
19966 switch (opcode)
19967 {
19968 case T_MNEM_ldr_pc:
19969 case T_MNEM_ldr_pc2:
19970 case T_MNEM_ldr_sp:
19971 case T_MNEM_str_sp:
19972 case T_MNEM_ldr:
19973 case T_MNEM_ldrb:
19974 case T_MNEM_ldrh:
19975 case T_MNEM_str:
19976 case T_MNEM_strb:
19977 case T_MNEM_strh:
19978 if (fragp->fr_var == 4)
19979 {
5f4273c7 19980 insn = THUMB_OP32 (opcode);
0110f2b8
PB		 19981 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
19982 {
19983 insn |= (old_op & 0x700) << 4;
19984 }
19985 else
19986 {
19987 insn |= (old_op & 7) << 12;
19988 insn |= (old_op & 0x38) << 13;
19989 }
19990 insn |= 0x00000c00;
19991 put_thumb32_insn (buf, insn);
19992 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
19993 }
19994 else
19995 {
19996 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
19997 }
19998 pc_rel = (opcode == T_MNEM_ldr_pc2);
19999 break;
20000 case T_MNEM_adr:
20001 if (fragp->fr_var == 4)
20002 {
20003 insn = THUMB_OP32 (opcode);
20004 insn |= (old_op & 0xf0) << 4;
20005 put_thumb32_insn (buf, insn);
20006 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20007 }
20008 else
20009 {
20010 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20011 exp.X_add_number -= 4;
20012 }
20013 pc_rel = 1;
20014 break;
20015 case T_MNEM_mov:
20016 case T_MNEM_movs:
20017 case T_MNEM_cmp:
20018 case T_MNEM_cmn:
20019 if (fragp->fr_var == 4)
20020 {
20021 int r0off = (opcode == T_MNEM_mov
20022 || opcode == T_MNEM_movs) ? 0 : 8;
20023 insn = THUMB_OP32 (opcode);
20024 insn = (insn & 0xe1ffffff) | 0x10000000;
20025 insn |= (old_op & 0x700) << r0off;
20026 put_thumb32_insn (buf, insn);
20027 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20028 }
20029 else
20030 {
20031 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20032 }
20033 pc_rel = 0;
20034 break;
20035 case T_MNEM_b:
20036 if (fragp->fr_var == 4)
20037 {
20038 insn = THUMB_OP32(opcode);
20039 put_thumb32_insn (buf, insn);
20040 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20041 }
20042 else
20043 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20044 pc_rel = 1;
20045 break;
20046 case T_MNEM_bcond:
20047 if (fragp->fr_var == 4)
20048 {
20049 insn = THUMB_OP32(opcode);
20050 insn |= (old_op & 0xf00) << 14;
20051 put_thumb32_insn (buf, insn);
20052 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20053 }
20054 else
20055 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20056 pc_rel = 1;
20057 break;
20058 case T_MNEM_add_sp:
20059 case T_MNEM_add_pc:
20060 case T_MNEM_inc_sp:
20061 case T_MNEM_dec_sp:
20062 if (fragp->fr_var == 4)
20063 {
20064 /* ??? Choose between add and addw. */
20065 insn = THUMB_OP32 (opcode);
20066 insn |= (old_op & 0xf0) << 4;
20067 put_thumb32_insn (buf, insn);
16805f35
PB		 20068 if (opcode == T_MNEM_add_pc)
20069 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20070 else
20071 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB		 20072 }
20073 else
20074 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20075 pc_rel = 0;
20076 break;
20077
20078 case T_MNEM_addi:
20079 case T_MNEM_addis:
20080 case T_MNEM_subi:
20081 case T_MNEM_subis:
20082 if (fragp->fr_var == 4)
20083 {
20084 insn = THUMB_OP32 (opcode);
20085 insn |= (old_op & 0xf0) << 4;
20086 insn |= (old_op & 0xf) << 16;
20087 put_thumb32_insn (buf, insn);
16805f35
PB		 20088 if (insn & (1 << 20))
20089 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20090 else
20091 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB		 20092 }
20093 else
20094 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20095 pc_rel = 0;
20096 break;
20097 default:
5f4273c7 20098 abort ();
0110f2b8
PB		 20099 }
20100 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 20101 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB		 20102 fixp->fx_file = fragp->fr_file;
20103 fixp->fx_line = fragp->fr_line;
20104 fragp->fr_fix += fragp->fr_var;
20105}
20106
20107/* Return the size of a relaxable immediate operand instruction.
20108 SHIFT and SIZE specify the form of the allowable immediate. */
20109static int
20110relax_immediate (fragS *fragp, int size, int shift)
20111{
20112 offsetT offset;
20113 offsetT mask;
20114 offsetT low;
20115
20116 /* ??? Should be able to do better than this. */
20117 if (fragp->fr_symbol)
20118 return 4;
20119
20120 low = (1 << shift) - 1;
20121 mask = (1 << (shift + size)) - (1 << shift);
20122 offset = fragp->fr_offset;
20123 /* Force misaligned offsets to 32-bit variant. */
20124 if (offset & low)
5e77afaa 20125 return 4;
0110f2b8
PB		 20126 if (offset & ~mask)
20127 return 4;
20128 return 2;
20129}
20130
5e77afaa
PB		 20131/* Get the address of a symbol during relaxation. */
20132static addressT
5f4273c7 20133relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB		 20134{
20135 fragS *sym_frag;
20136 addressT addr;
20137 symbolS *sym;
20138
20139 sym = fragp->fr_symbol;
20140 sym_frag = symbol_get_frag (sym);
20141 know (S_GET_SEGMENT (sym) != absolute_section
20142 || sym_frag == &zero_address_frag);
20143 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20144
20145 /* If frag has yet to be reached on this pass, assume it will
20146 move by STRETCH just as we did. If this is not so, it will
20147 be because some frag between grows, and that will force
20148 another pass. */
20149
20150 if (stretch != 0
20151 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB		 20152 {
20153 fragS *f;
20154
20155 /* Adjust stretch for any alignment frag. Note that if have
20156 been expanding the earlier code, the symbol may be
20157 defined in what appears to be an earlier frag. FIXME:
20158 This doesn't handle the fr_subtype field, which specifies
20159 a maximum number of bytes to skip when doing an
20160 alignment. */
20161 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20162 {
20163 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20164 {
20165 if (stretch < 0)
20166 stretch = - ((- stretch)
20167 & ~ ((1 << (int) f->fr_offset) - 1));
20168 else
20169 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20170 if (stretch == 0)
20171 break;
20172 }
20173 }
20174 if (f != NULL)
20175 addr += stretch;
20176 }
5e77afaa
PB		 20177
20178 return addr;
20179}
20180
0110f2b8
PB		 20181/* Return the size of a relaxable adr pseudo-instruction or PC-relative
20182 load. */
20183static int
5e77afaa 20184relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB		 20185{
20186 addressT addr;
20187 offsetT val;
20188
20189 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC		 20190 if (fragp->fr_symbol == NULL
20191 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 20192 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20193 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 20194 return 4;
20195
5f4273c7 20196 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 20197 addr = fragp->fr_address + fragp->fr_fix;
20198 addr = (addr + 4) & ~3;
5e77afaa 20199 /* Force misaligned targets to 32-bit variant. */
0110f2b8 20200 if (val & 3)
5e77afaa 20201 return 4;
0110f2b8
PB		 20202 val -= addr;
20203 if (val < 0 || val > 1020)
20204 return 4;
20205 return 2;
20206}
20207
20208/* Return the size of a relaxable add/sub immediate instruction. */
20209static int
20210relax_addsub (fragS *fragp, asection *sec)
20211{
20212 char *buf;
20213 int op;
20214
20215 buf = fragp->fr_literal + fragp->fr_fix;
20216 op = bfd_get_16(sec->owner, buf);
20217 if ((op & 0xf) == ((op >> 4) & 0xf))
20218 return relax_immediate (fragp, 8, 0);
20219 else
20220 return relax_immediate (fragp, 3, 0);
20221}
20222
e83a675f
RE		 20223/* Return TRUE iff the definition of symbol S could be pre-empted
20224 (overridden) at link or load time. */
20225static bfd_boolean
20226symbol_preemptible (symbolS *s)
20227{
20228 /* Weak symbols can always be pre-empted. */
20229 if (S_IS_WEAK (s))
20230 return TRUE;
20231
20232 /* Non-global symbols cannot be pre-empted. */
20233 if (! S_IS_EXTERNAL (s))
20234 return FALSE;
20235
20236#ifdef OBJ_ELF
20237 /* In ELF, a global symbol can be marked protected, or private. In that
20238 case it can't be pre-empted (other definitions in the same link unit
20239 would violate the ODR). */
20240 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20241 return FALSE;
20242#endif
20243
20244 /* Other global symbols might be pre-empted. */
20245 return TRUE;
20246}
0110f2b8
PB		 20247
20248/* Return the size of a relaxable branch instruction. BITS is the
20249 size of the offset field in the narrow instruction. */
20250
20251static int
5e77afaa 20252relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB		 20253{
20254 addressT addr;
20255 offsetT val;
20256 offsetT limit;
20257
20258 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 20259 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 20260 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20261 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 20262 return 4;
20263
267bf995 20264#ifdef OBJ_ELF
e83a675f 20265 /* A branch to a function in ARM state will require interworking. */
267bf995
RR		 20266 if (S_IS_DEFINED (fragp->fr_symbol)
20267 && ARM_IS_FUNC (fragp->fr_symbol))
20268 return 4;
e83a675f 20269#endif
0d9b4b55 20270
e83a675f 20271 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 20272 return 4;
267bf995 20273
5f4273c7 20274 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 20275 addr = fragp->fr_address + fragp->fr_fix + 4;
20276 val -= addr;
20277
20278 /* Offset is a signed value *2 */
20279 limit = 1 << bits;
20280 if (val >= limit || val < -limit)
20281 return 4;
20282 return 2;
20283}
20284
20285
20286/* Relax a machine dependent frag. This returns the amount by which
20287 the current size of the frag should change. */
20288
20289int
5e77afaa 20290arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB		 20291{
20292 int oldsize;
20293 int newsize;
20294
20295 oldsize = fragp->fr_var;
20296 switch (fragp->fr_subtype)
20297 {
20298 case T_MNEM_ldr_pc2:
5f4273c7 20299 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 20300 break;
20301 case T_MNEM_ldr_pc:
20302 case T_MNEM_ldr_sp:
20303 case T_MNEM_str_sp:
5f4273c7 20304 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB		 20305 break;
20306 case T_MNEM_ldr:
20307 case T_MNEM_str:
5f4273c7 20308 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB		 20309 break;
20310 case T_MNEM_ldrh:
20311 case T_MNEM_strh:
5f4273c7 20312 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB		 20313 break;
20314 case T_MNEM_ldrb:
20315 case T_MNEM_strb:
5f4273c7 20316 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB		 20317 break;
20318 case T_MNEM_adr:
5f4273c7 20319 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 20320 break;
20321 case T_MNEM_mov:
20322 case T_MNEM_movs:
20323 case T_MNEM_cmp:
20324 case T_MNEM_cmn:
5f4273c7 20325 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB		 20326 break;
20327 case T_MNEM_b:
5f4273c7 20328 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB		 20329 break;
20330 case T_MNEM_bcond:
5f4273c7 20331 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB		 20332 break;
20333 case T_MNEM_add_sp:
20334 case T_MNEM_add_pc:
20335 newsize = relax_immediate (fragp, 8, 2);
20336 break;
20337 case T_MNEM_inc_sp:
20338 case T_MNEM_dec_sp:
20339 newsize = relax_immediate (fragp, 7, 2);
20340 break;
20341 case T_MNEM_addi:
20342 case T_MNEM_addis:
20343 case T_MNEM_subi:
20344 case T_MNEM_subis:
20345 newsize = relax_addsub (fragp, sec);
20346 break;
20347 default:
5f4273c7 20348 abort ();
0110f2b8 20349 }
5e77afaa
PB		 20350
20351 fragp->fr_var = newsize;
20352 /* Freeze wide instructions that are at or before the same location as
20353 in the previous pass. This avoids infinite loops.
5f4273c7
NC		 20354 Don't freeze them unconditionally because targets may be artificially
20355 misaligned by the expansion of preceding frags. */
5e77afaa 20356 if (stretch <= 0 && newsize > 2)
0110f2b8 20357 {
0110f2b8 20358 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 20359 frag_wane (fragp);
0110f2b8 20360 }
5e77afaa 20361
0110f2b8 20362 return newsize - oldsize;
c19d1205 20363}
b99bd4ef 20364
c19d1205 20365/* Round up a section size to the appropriate boundary. */
b99bd4ef 20366
c19d1205
ZW		 20367valueT
20368md_section_align (segT segment ATTRIBUTE_UNUSED,
20369 valueT size)
20370{
f0927246
NC		 20371#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20372 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20373 {
20374 /* For a.out, force the section size to be aligned. If we don't do
20375 this, BFD will align it for us, but it will not write out the
20376 final bytes of the section. This may be a bug in BFD, but it is
20377 easier to fix it here since that is how the other a.out targets
20378 work. */
20379 int align;
20380
20381 align = bfd_get_section_alignment (stdoutput, segment);
20382 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20383 }
c19d1205 20384#endif
f0927246
NC		 20385
20386 return size;
bfae80f2 20387}
b99bd4ef 20388
c19d1205
ZW		 20389/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20390 of an rs_align_code fragment. */
20391
20392void
20393arm_handle_align (fragS * fragP)
bfae80f2 20394{
e7495e45
NS		 20395 static char const arm_noop[2][2][4] =
20396 {
20397 { /* ARMv1 */
20398 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20399 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20400 },
20401 { /* ARMv6k */
20402 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20403 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20404 },
20405 };
20406 static char const thumb_noop[2][2][2] =
20407 {
20408 { /* Thumb-1 */
20409 {0xc0, 0x46}, /* LE */
20410 {0x46, 0xc0}, /* BE */
20411 },
20412 { /* Thumb-2 */
20413 {0x00, 0xbf}, /* LE */
20414 {0xbf, 0x00} /* BE */
20415 }
20416 };
20417 static char const wide_thumb_noop[2][4] =
20418 { /* Wide Thumb-2 */
20419 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20420 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20421 };
c921be7d 20422
e7495e45 20423 unsigned bytes, fix, noop_size;
c19d1205
ZW		 20424 char * p;
20425 const char * noop;
e7495e45 20426 const char *narrow_noop = NULL;
cd000bff
DJ		 20427#ifdef OBJ_ELF
20428 enum mstate state;
20429#endif
bfae80f2 20430
c19d1205 20431 if (fragP->fr_type != rs_align_code)
bfae80f2
RE		 20432 return;
20433
c19d1205
ZW		 20434 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20435 p = fragP->fr_literal + fragP->fr_fix;
20436 fix = 0;
bfae80f2 20437
c19d1205
ZW		 20438 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20439 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 20440
cd000bff 20441 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 20442
cd000bff 20443 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 20444 {
e7495e45
NS		 20445 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
20446 {
20447 narrow_noop = thumb_noop[1][target_big_endian];
20448 noop = wide_thumb_noop[target_big_endian];
20449 }
c19d1205 20450 else
e7495e45
NS		 20451 noop = thumb_noop[0][target_big_endian];
20452 noop_size = 2;
cd000bff
DJ		 20453#ifdef OBJ_ELF
20454 state = MAP_THUMB;
20455#endif
7ed4c4c5
NC		 20456 }
20457 else
20458 {
e7495e45
NS		 20459 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k) != 0]
20460 [target_big_endian];
20461 noop_size = 4;
cd000bff
DJ		 20462#ifdef OBJ_ELF
20463 state = MAP_ARM;
20464#endif
7ed4c4c5 20465 }
c921be7d 20466
e7495e45 20467 fragP->fr_var = noop_size;
c921be7d 20468
c19d1205 20469 if (bytes & (noop_size - 1))
7ed4c4c5 20470 {
c19d1205 20471 fix = bytes & (noop_size - 1);
cd000bff
DJ		 20472#ifdef OBJ_ELF
20473 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20474#endif
c19d1205
ZW		 20475 memset (p, 0, fix);
20476 p += fix;
20477 bytes -= fix;
a737bd4d 20478 }
a737bd4d 20479
e7495e45
NS		 20480 if (narrow_noop)
20481 {
20482 if (bytes & noop_size)
20483 {
20484 /* Insert a narrow noop. */
20485 memcpy (p, narrow_noop, noop_size);
20486 p += noop_size;
20487 bytes -= noop_size;
20488 fix += noop_size;
20489 }
20490
20491 /* Use wide noops for the remainder */
20492 noop_size = 4;
20493 }
20494
c19d1205 20495 while (bytes >= noop_size)
a737bd4d 20496 {
c19d1205
ZW		 20497 memcpy (p, noop, noop_size);
20498 p += noop_size;
20499 bytes -= noop_size;
20500 fix += noop_size;
a737bd4d
NC		 20501 }
20502
c19d1205 20503 fragP->fr_fix += fix;
a737bd4d
NC		 20504}
20505
c19d1205
ZW		 20506/* Called from md_do_align. Used to create an alignment
20507 frag in a code section. */
20508
20509void
20510arm_frag_align_code (int n, int max)
bfae80f2 20511{
c19d1205 20512 char * p;
7ed4c4c5 20513
c19d1205 20514 /* We assume that there will never be a requirement
6ec8e702 20515 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 20516 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC		 20517 {
20518 char err_msg[128];
20519
fa94de6b 20520 sprintf (err_msg,
477330fc
RM		 20521 _("alignments greater than %d bytes not supported in .text sections."),
20522 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 20523 as_fatal ("%s", err_msg);
6ec8e702 20524 }
bfae80f2 20525
c19d1205
ZW		 20526 p = frag_var (rs_align_code,
20527 MAX_MEM_FOR_RS_ALIGN_CODE,
20528 1,
20529 (relax_substateT) max,
20530 (symbolS *) NULL,
20531 (offsetT) n,
20532 (char *) NULL);
20533 *p = 0;
20534}
bfae80f2 20535
8dc2430f
NC		 20536/* Perform target specific initialisation of a frag.
20537 Note - despite the name this initialisation is not done when the frag
20538 is created, but only when its type is assigned. A frag can be created
20539 and used a long time before its type is set, so beware of assuming that
20540 this initialisationis performed first. */
bfae80f2 20541
cd000bff
DJ		 20542#ifndef OBJ_ELF
20543void
20544arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20545{
20546 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 20547 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ		 20548}
20549
20550#else /* OBJ_ELF is defined. */
c19d1205 20551void
cd000bff 20552arm_init_frag (fragS * fragP, int max_chars)
c19d1205 20553{
8dc2430f
NC		 20554 /* If the current ARM vs THUMB mode has not already
20555 been recorded into this frag then do so now. */
cd000bff
DJ		 20556 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
20557 {
20558 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
20559
20560 /* Record a mapping symbol for alignment frags. We will delete this
20561 later if the alignment ends up empty. */
20562 switch (fragP->fr_type)
20563 {
20564 case rs_align:
20565 case rs_align_test:
20566 case rs_fill:
20567 mapping_state_2 (MAP_DATA, max_chars);
20568 break;
20569 case rs_align_code:
20570 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
20571 break;
20572 default:
20573 break;
20574 }
20575 }
bfae80f2
RE		 20576}
20577
c19d1205
ZW		 20578/* When we change sections we need to issue a new mapping symbol. */
20579
20580void
20581arm_elf_change_section (void)
bfae80f2 20582{
c19d1205
ZW		 20583 /* Link an unlinked unwind index table section to the .text section. */
20584 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
20585 && elf_linked_to_section (now_seg) == NULL)
20586 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE		 20587}
20588
c19d1205
ZW		 20589int
20590arm_elf_section_type (const char * str, size_t len)
e45d0630 20591{
c19d1205
ZW		 20592 if (len == 5 && strncmp (str, "exidx", 5) == 0)
20593 return SHT_ARM_EXIDX;
e45d0630 20594
c19d1205
ZW		 20595 return -1;
20596}
20597\f
20598/* Code to deal with unwinding tables. */
e45d0630 20599
c19d1205 20600static void add_unwind_adjustsp (offsetT);
e45d0630 20601
5f4273c7 20602/* Generate any deferred unwind frame offset. */
e45d0630 20603
bfae80f2 20604static void
c19d1205 20605flush_pending_unwind (void)
bfae80f2 20606{
c19d1205 20607 offsetT offset;
bfae80f2 20608
c19d1205
ZW		 20609 offset = unwind.pending_offset;
20610 unwind.pending_offset = 0;
20611 if (offset != 0)
20612 add_unwind_adjustsp (offset);
bfae80f2
RE		 20613}
20614
c19d1205
ZW		 20615/* Add an opcode to this list for this function. Two-byte opcodes should
20616 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20617 order. */
20618
bfae80f2 20619static void
c19d1205 20620add_unwind_opcode (valueT op, int length)
bfae80f2 20621{
c19d1205
ZW		 20622 /* Add any deferred stack adjustment. */
20623 if (unwind.pending_offset)
20624 flush_pending_unwind ();
bfae80f2 20625
c19d1205 20626 unwind.sp_restored = 0;
bfae80f2 20627
c19d1205 20628 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 20629 {
c19d1205
ZW		 20630 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
20631 if (unwind.opcodes)
21d799b5 20632 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
477330fc 20633 unwind.opcode_alloc);
c19d1205 20634 else
21d799b5 20635 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
bfae80f2 20636 }
c19d1205 20637 while (length > 0)
bfae80f2 20638 {
c19d1205
ZW		 20639 length--;
20640 unwind.opcodes[unwind.opcode_count] = op & 0xff;
20641 op >>= 8;
20642 unwind.opcode_count++;
bfae80f2 20643 }
bfae80f2
RE		 20644}
20645
c19d1205
ZW		 20646/* Add unwind opcodes to adjust the stack pointer. */
20647
bfae80f2 20648static void
c19d1205 20649add_unwind_adjustsp (offsetT offset)
bfae80f2 20650{
c19d1205 20651 valueT op;
bfae80f2 20652
c19d1205 20653 if (offset > 0x200)
bfae80f2 20654 {
c19d1205
ZW		 20655 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20656 char bytes[5];
20657 int n;
20658 valueT o;
bfae80f2 20659
c19d1205
ZW		 20660 /* Long form: 0xb2, uleb128. */
20661 /* This might not fit in a word so add the individual bytes,
20662 remembering the list is built in reverse order. */
20663 o = (valueT) ((offset - 0x204) >> 2);
20664 if (o == 0)
20665 add_unwind_opcode (0, 1);
bfae80f2 20666
c19d1205
ZW		 20667 /* Calculate the uleb128 encoding of the offset. */
20668 n = 0;
20669 while (o)
20670 {
20671 bytes[n] = o & 0x7f;
20672 o >>= 7;
20673 if (o)
20674 bytes[n] |= 0x80;
20675 n++;
20676 }
20677 /* Add the insn. */
20678 for (; n; n--)
20679 add_unwind_opcode (bytes[n - 1], 1);
20680 add_unwind_opcode (0xb2, 1);
20681 }
20682 else if (offset > 0x100)
bfae80f2 20683 {
c19d1205
ZW		 20684 /* Two short opcodes. */
20685 add_unwind_opcode (0x3f, 1);
20686 op = (offset - 0x104) >> 2;
20687 add_unwind_opcode (op, 1);
bfae80f2 20688 }
c19d1205
ZW		 20689 else if (offset > 0)
20690 {
20691 /* Short opcode. */
20692 op = (offset - 4) >> 2;
20693 add_unwind_opcode (op, 1);
20694 }
20695 else if (offset < 0)
bfae80f2 20696 {
c19d1205
ZW		 20697 offset = -offset;
20698 while (offset > 0x100)
bfae80f2 20699 {
c19d1205
ZW		 20700 add_unwind_opcode (0x7f, 1);
20701 offset -= 0x100;
bfae80f2 20702 }
c19d1205
ZW		 20703 op = ((offset - 4) >> 2) | 0x40;
20704 add_unwind_opcode (op, 1);
bfae80f2 20705 }
bfae80f2
RE		 20706}
20707
c19d1205
ZW		 20708/* Finish the list of unwind opcodes for this function. */
20709static void
20710finish_unwind_opcodes (void)
bfae80f2 20711{
c19d1205 20712 valueT op;
bfae80f2 20713
c19d1205 20714 if (unwind.fp_used)
bfae80f2 20715 {
708587a4 20716 /* Adjust sp as necessary. */
c19d1205
ZW		 20717 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
20718 flush_pending_unwind ();
bfae80f2 20719
c19d1205
ZW		 20720 /* After restoring sp from the frame pointer. */
20721 op = 0x90 | unwind.fp_reg;
20722 add_unwind_opcode (op, 1);
20723 }
20724 else
20725 flush_pending_unwind ();
bfae80f2
RE		 20726}
20727
bfae80f2 20728
c19d1205
ZW		 20729/* Start an exception table entry. If idx is nonzero this is an index table
20730 entry. */
bfae80f2
RE		 20731
20732static void
c19d1205 20733start_unwind_section (const segT text_seg, int idx)
bfae80f2 20734{
c19d1205
ZW		 20735 const char * text_name;
20736 const char * prefix;
20737 const char * prefix_once;
20738 const char * group_name;
20739 size_t prefix_len;
20740 size_t text_len;
20741 char * sec_name;
20742 size_t sec_name_len;
20743 int type;
20744 int flags;
20745 int linkonce;
bfae80f2 20746
c19d1205 20747 if (idx)
bfae80f2 20748 {
c19d1205
ZW		 20749 prefix = ELF_STRING_ARM_unwind;
20750 prefix_once = ELF_STRING_ARM_unwind_once;
20751 type = SHT_ARM_EXIDX;
bfae80f2 20752 }
c19d1205 20753 else
bfae80f2 20754 {
c19d1205
ZW		 20755 prefix = ELF_STRING_ARM_unwind_info;
20756 prefix_once = ELF_STRING_ARM_unwind_info_once;
20757 type = SHT_PROGBITS;
bfae80f2
RE		 20758 }
20759
c19d1205
ZW		 20760 text_name = segment_name (text_seg);
20761 if (streq (text_name, ".text"))
20762 text_name = "";
20763
20764 if (strncmp (text_name, ".gnu.linkonce.t.",
20765 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 20766 {
c19d1205
ZW		 20767 prefix = prefix_once;
20768 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE		 20769 }
20770
c19d1205
ZW		 20771 prefix_len = strlen (prefix);
20772 text_len = strlen (text_name);
20773 sec_name_len = prefix_len + text_len;
21d799b5 20774 sec_name = (char *) xmalloc (sec_name_len + 1);
c19d1205
ZW		 20775 memcpy (sec_name, prefix, prefix_len);
20776 memcpy (sec_name + prefix_len, text_name, text_len);
20777 sec_name[prefix_len + text_len] = '\0';
bfae80f2 20778
c19d1205
ZW		 20779 flags = SHF_ALLOC;
20780 linkonce = 0;
20781 group_name = 0;
bfae80f2 20782
c19d1205
ZW		 20783 /* Handle COMDAT group. */
20784 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 20785 {
c19d1205
ZW		 20786 group_name = elf_group_name (text_seg);
20787 if (group_name == NULL)
20788 {
bd3ba5d1 20789 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW		 20790 segment_name (text_seg));
20791 ignore_rest_of_line ();
20792 return;
20793 }
20794 flags |= SHF_GROUP;
20795 linkonce = 1;
bfae80f2
RE		 20796 }
20797
c19d1205 20798 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
bfae80f2 20799
5f4273c7 20800 /* Set the section link for index tables. */
c19d1205
ZW		 20801 if (idx)
20802 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE		 20803}
20804
bfae80f2 20805
c19d1205
ZW		 20806/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20807 personality routine data. Returns zero, or the index table value for
20808 and inline entry. */
20809
20810static valueT
20811create_unwind_entry (int have_data)
bfae80f2 20812{
c19d1205
ZW		 20813 int size;
20814 addressT where;
20815 char *ptr;
20816 /* The current word of data. */
20817 valueT data;
20818 /* The number of bytes left in this word. */
20819 int n;
bfae80f2 20820
c19d1205 20821 finish_unwind_opcodes ();
bfae80f2 20822
c19d1205
ZW		 20823 /* Remember the current text section. */
20824 unwind.saved_seg = now_seg;
20825 unwind.saved_subseg = now_subseg;
bfae80f2 20826
c19d1205 20827 start_unwind_section (now_seg, 0);
bfae80f2 20828
c19d1205 20829 if (unwind.personality_routine == NULL)
bfae80f2 20830 {
c19d1205
ZW		 20831 if (unwind.personality_index == -2)
20832 {
20833 if (have_data)
5f4273c7 20834 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW		 20835 return 1; /* EXIDX_CANTUNWIND. */
20836 }
bfae80f2 20837
c19d1205
ZW		 20838 /* Use a default personality routine if none is specified. */
20839 if (unwind.personality_index == -1)
20840 {
20841 if (unwind.opcode_count > 3)
20842 unwind.personality_index = 1;
20843 else
20844 unwind.personality_index = 0;
20845 }
bfae80f2 20846
c19d1205
ZW		 20847 /* Space for the personality routine entry. */
20848 if (unwind.personality_index == 0)
20849 {
20850 if (unwind.opcode_count > 3)
20851 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 20852
c19d1205
ZW		 20853 if (!have_data)
20854 {
20855 /* All the data is inline in the index table. */
20856 data = 0x80;
20857 n = 3;
20858 while (unwind.opcode_count > 0)
20859 {
20860 unwind.opcode_count--;
20861 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20862 n--;
20863 }
bfae80f2 20864
c19d1205
ZW		 20865 /* Pad with "finish" opcodes. */
20866 while (n--)
20867 data = (data << 8) | 0xb0;
bfae80f2 20868
c19d1205
ZW		 20869 return data;
20870 }
20871 size = 0;
20872 }
20873 else
20874 /* We get two opcodes "free" in the first word. */
20875 size = unwind.opcode_count - 2;
20876 }
20877 else
5011093d
NC		 20878 {
20879 gas_assert (unwind.personality_index == -1);
20880
20881 /* An extra byte is required for the opcode count. */
20882 size = unwind.opcode_count + 1;
20883 }
bfae80f2 20884
c19d1205
ZW		 20885 size = (size + 3) >> 2;
20886 if (size > 0xff)
20887 as_bad (_("too many unwind opcodes"));
bfae80f2 20888
c19d1205
ZW		 20889 frag_align (2, 0, 0);
20890 record_alignment (now_seg, 2);
20891 unwind.table_entry = expr_build_dot ();
20892
20893 /* Allocate the table entry. */
20894 ptr = frag_more ((size << 2) + 4);
74929e7b
NC		 20895 /* PR 13449: Zero the table entries in case some of them are not used. */
20896 memset (ptr, 0, (size << 2) + 4);
c19d1205 20897 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 20898
c19d1205 20899 switch (unwind.personality_index)
bfae80f2 20900 {
c19d1205
ZW		 20901 case -1:
20902 /* ??? Should this be a PLT generating relocation? */
20903 /* Custom personality routine. */
20904 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
20905 BFD_RELOC_ARM_PREL31);
bfae80f2 20906
c19d1205
ZW		 20907 where += 4;
20908 ptr += 4;
bfae80f2 20909
c19d1205 20910 /* Set the first byte to the number of additional words. */
5011093d 20911 data = size > 0 ? size - 1 : 0;
c19d1205
ZW		 20912 n = 3;
20913 break;
bfae80f2 20914
c19d1205
ZW		 20915 /* ABI defined personality routines. */
20916 case 0:
20917 /* Three opcodes bytes are packed into the first word. */
20918 data = 0x80;
20919 n = 3;
20920 break;
bfae80f2 20921
c19d1205
ZW		 20922 case 1:
20923 case 2:
20924 /* The size and first two opcode bytes go in the first word. */
20925 data = ((0x80 + unwind.personality_index) << 8) | size;
20926 n = 2;
20927 break;
bfae80f2 20928
c19d1205
ZW		 20929 default:
20930 /* Should never happen. */
20931 abort ();
20932 }
bfae80f2 20933
c19d1205
ZW		 20934 /* Pack the opcodes into words (MSB first), reversing the list at the same
20935 time. */
20936 while (unwind.opcode_count > 0)
20937 {
20938 if (n == 0)
20939 {
20940 md_number_to_chars (ptr, data, 4);
20941 ptr += 4;
20942 n = 4;
20943 data = 0;
20944 }
20945 unwind.opcode_count--;
20946 n--;
20947 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
20948 }
20949
20950 /* Finish off the last word. */
20951 if (n < 4)
20952 {
20953 /* Pad with "finish" opcodes. */
20954 while (n--)
20955 data = (data << 8) | 0xb0;
20956
20957 md_number_to_chars (ptr, data, 4);
20958 }
20959
20960 if (!have_data)
20961 {
20962 /* Add an empty descriptor if there is no user-specified data. */
20963 ptr = frag_more (4);
20964 md_number_to_chars (ptr, 0, 4);
20965 }
20966
20967 return 0;
bfae80f2
RE		 20968}
20969
f0927246
NC		 20970
20971/* Initialize the DWARF-2 unwind information for this procedure. */
20972
20973void
20974tc_arm_frame_initial_instructions (void)
20975{
20976 cfi_add_CFA_def_cfa (REG_SP, 0);
20977}
20978#endif /* OBJ_ELF */
20979
c19d1205
ZW		 20980/* Convert REGNAME to a DWARF-2 register number. */
20981
20982int
1df69f4f 20983tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 20984{
1df69f4f 20985 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
c19d1205
ZW		 20986
20987 if (reg == FAIL)
20988 return -1;
20989
20990 return reg;
bfae80f2
RE		 20991}
20992
f0927246 20993#ifdef TE_PE
c19d1205 20994void
f0927246 20995tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 20996{
91d6fa6a 20997 expressionS exp;
bfae80f2 20998
91d6fa6a
NC		 20999 exp.X_op = O_secrel;
21000 exp.X_add_symbol = symbol;
21001 exp.X_add_number = 0;
21002 emit_expr (&exp, size);
f0927246
NC		 21003}
21004#endif
bfae80f2 21005
c19d1205 21006/* MD interface: Symbol and relocation handling. */
bfae80f2 21007
2fc8bdac
ZW		 21008/* Return the address within the segment that a PC-relative fixup is
21009 relative to. For ARM, PC-relative fixups applied to instructions
21010 are generally relative to the location of the fixup plus 8 bytes.
21011 Thumb branches are offset by 4, and Thumb loads relative to PC
21012 require special handling. */
bfae80f2 21013
c19d1205 21014long
2fc8bdac 21015md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 21016{
2fc8bdac
ZW		 21017 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21018
21019 /* If this is pc-relative and we are going to emit a relocation
21020 then we just want to put out any pipeline compensation that the linker
53baae48
NC		 21021 will need. Otherwise we want to use the calculated base.
21022 For WinCE we skip the bias for externals as well, since this
21023 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 21024 if (fixP->fx_pcrel
2fc8bdac 21025 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC		 21026 || (arm_force_relocation (fixP)
21027#ifdef TE_WINCE
21028 && !S_IS_EXTERNAL (fixP->fx_addsy)
21029#endif
21030 )))
2fc8bdac 21031 base = 0;
bfae80f2 21032
267bf995 21033
c19d1205 21034 switch (fixP->fx_r_type)
bfae80f2 21035 {
2fc8bdac
ZW		 21036 /* PC relative addressing on the Thumb is slightly odd as the
21037 bottom two bits of the PC are forced to zero for the
21038 calculation. This happens *after* application of the
21039 pipeline offset. However, Thumb adrl already adjusts for
21040 this, so we need not do it again. */
c19d1205 21041 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 21042 return base & ~3;
c19d1205
ZW		 21043
21044 case BFD_RELOC_ARM_THUMB_OFFSET:
21045 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 21046 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 21047 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 21048 return (base + 4) & ~3;
c19d1205 21049
2fc8bdac
ZW		 21050 /* Thumb branches are simply offset by +4. */
21051 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21052 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21053 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21054 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 21055 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac 21056 return base + 4;
bfae80f2 21057
267bf995 21058 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL		 21059 if (fixP->fx_addsy
21060 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21061 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 21062 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM		 21063 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21064 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR		 21065 return base + 4;
21066
00adf2d4
JB		 21067 /* BLX is like branches above, but forces the low two bits of PC to
21068 zero. */
486499d0
CL		 21069 case BFD_RELOC_THUMB_PCREL_BLX:
21070 if (fixP->fx_addsy
21071 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21072 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21073 && THUMB_IS_FUNC (fixP->fx_addsy)
21074 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21075 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB		 21076 return (base + 4) & ~3;
21077
2fc8bdac
ZW		 21078 /* ARM mode branches are offset by +8. However, the Windows CE
21079 loader expects the relocation not to take this into account. */
267bf995 21080 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL		 21081 if (fixP->fx_addsy
21082 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21083 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21084 && ARM_IS_FUNC (fixP->fx_addsy)
21085 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21086 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 21087 return base + 8;
267bf995 21088
486499d0
CL		 21089 case BFD_RELOC_ARM_PCREL_CALL:
21090 if (fixP->fx_addsy
21091 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21092 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21093 && THUMB_IS_FUNC (fixP->fx_addsy)
21094 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21095 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 21096 return base + 8;
267bf995 21097
2fc8bdac 21098 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 21099 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 21100 case BFD_RELOC_ARM_PLT32:
c19d1205 21101#ifdef TE_WINCE
5f4273c7 21102 /* When handling fixups immediately, because we have already
477330fc 21103 discovered the value of a symbol, or the address of the frag involved
53baae48 21104 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM		 21105 see fixup_segment() in write.c
21106 The S_IS_EXTERNAL test handles the case of global symbols.
21107 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC		 21108 if (fixP->fx_pcrel
21109 && fixP->fx_addsy != NULL
21110 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21111 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21112 return base + 8;
2fc8bdac 21113 return base;
c19d1205 21114#else
2fc8bdac 21115 return base + 8;
c19d1205 21116#endif
2fc8bdac 21117
267bf995 21118
2fc8bdac
ZW		 21119 /* ARM mode loads relative to PC are also offset by +8. Unlike
21120 branches, the Windows CE loader *does* expect the relocation
21121 to take this into account. */
21122 case BFD_RELOC_ARM_OFFSET_IMM:
21123 case BFD_RELOC_ARM_OFFSET_IMM8:
21124 case BFD_RELOC_ARM_HWLITERAL:
21125 case BFD_RELOC_ARM_LITERAL:
21126 case BFD_RELOC_ARM_CP_OFF_IMM:
21127 return base + 8;
21128
21129
21130 /* Other PC-relative relocations are un-offset. */
21131 default:
21132 return base;
21133 }
bfae80f2
RE		 21134}
21135
c19d1205
ZW		 21136/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21137 Otherwise we have no need to default values of symbols. */
21138
21139symbolS *
21140md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
bfae80f2 21141{
c19d1205
ZW		 21142#ifdef OBJ_ELF
21143 if (name[0] == '_' && name[1] == 'G'
21144 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21145 {
21146 if (!GOT_symbol)
21147 {
21148 if (symbol_find (name))
bd3ba5d1 21149 as_bad (_("GOT already in the symbol table"));
bfae80f2 21150
c19d1205
ZW		 21151 GOT_symbol = symbol_new (name, undefined_section,
21152 (valueT) 0, & zero_address_frag);
21153 }
bfae80f2 21154
c19d1205 21155 return GOT_symbol;
bfae80f2 21156 }
c19d1205 21157#endif
bfae80f2 21158
c921be7d 21159 return NULL;
bfae80f2
RE		 21160}
21161
55cf6793 21162/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW		 21163 computed as two separate immediate values, added together. We
21164 already know that this value cannot be computed by just one ARM
21165 instruction. */
21166
21167static unsigned int
21168validate_immediate_twopart (unsigned int val,
21169 unsigned int * highpart)
bfae80f2 21170{
c19d1205
ZW		 21171 unsigned int a;
21172 unsigned int i;
bfae80f2 21173
c19d1205
ZW		 21174 for (i = 0; i < 32; i += 2)
21175 if (((a = rotate_left (val, i)) & 0xff) != 0)
21176 {
21177 if (a & 0xff00)
21178 {
21179 if (a & ~ 0xffff)
21180 continue;
21181 * highpart = (a >> 8) | ((i + 24) << 7);
21182 }
21183 else if (a & 0xff0000)
21184 {
21185 if (a & 0xff000000)
21186 continue;
21187 * highpart = (a >> 16) | ((i + 16) << 7);
21188 }
21189 else
21190 {
9c2799c2 21191 gas_assert (a & 0xff000000);
c19d1205
ZW		 21192 * highpart = (a >> 24) | ((i + 8) << 7);
21193 }
bfae80f2 21194
c19d1205
ZW		 21195 return (a & 0xff) | (i << 7);
21196 }
bfae80f2 21197
c19d1205 21198 return FAIL;
bfae80f2
RE		 21199}
21200
c19d1205
ZW		 21201static int
21202validate_offset_imm (unsigned int val, int hwse)
21203{
21204 if ((hwse && val > 255) || val > 4095)
21205 return FAIL;
21206 return val;
21207}
bfae80f2 21208
55cf6793 21209/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW		 21210 negative immediate constant by altering the instruction. A bit of
21211 a hack really.
21212 MOV <-> MVN
21213 AND <-> BIC
21214 ADC <-> SBC
21215 by inverting the second operand, and
21216 ADD <-> SUB
21217 CMP <-> CMN
21218 by negating the second operand. */
bfae80f2 21219
c19d1205
ZW		 21220static int
21221negate_data_op (unsigned long * instruction,
21222 unsigned long value)
bfae80f2 21223{
c19d1205
ZW		 21224 int op, new_inst;
21225 unsigned long negated, inverted;
bfae80f2 21226
c19d1205
ZW		 21227 negated = encode_arm_immediate (-value);
21228 inverted = encode_arm_immediate (~value);
bfae80f2 21229
c19d1205
ZW		 21230 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21231 switch (op)
bfae80f2 21232 {
c19d1205
ZW		 21233 /* First negates. */
21234 case OPCODE_SUB: /* ADD <-> SUB */
21235 new_inst = OPCODE_ADD;
21236 value = negated;
21237 break;
bfae80f2 21238
c19d1205
ZW		 21239 case OPCODE_ADD:
21240 new_inst = OPCODE_SUB;
21241 value = negated;
21242 break;
bfae80f2 21243
c19d1205
ZW		 21244 case OPCODE_CMP: /* CMP <-> CMN */
21245 new_inst = OPCODE_CMN;
21246 value = negated;
21247 break;
bfae80f2 21248
c19d1205
ZW		 21249 case OPCODE_CMN:
21250 new_inst = OPCODE_CMP;
21251 value = negated;
21252 break;
bfae80f2 21253
c19d1205
ZW		 21254 /* Now Inverted ops. */
21255 case OPCODE_MOV: /* MOV <-> MVN */
21256 new_inst = OPCODE_MVN;
21257 value = inverted;
21258 break;
bfae80f2 21259
c19d1205
ZW		 21260 case OPCODE_MVN:
21261 new_inst = OPCODE_MOV;
21262 value = inverted;
21263 break;
bfae80f2 21264
c19d1205
ZW		 21265 case OPCODE_AND: /* AND <-> BIC */
21266 new_inst = OPCODE_BIC;
21267 value = inverted;
21268 break;
bfae80f2 21269
c19d1205
ZW		 21270 case OPCODE_BIC:
21271 new_inst = OPCODE_AND;
21272 value = inverted;
21273 break;
bfae80f2 21274
c19d1205
ZW		 21275 case OPCODE_ADC: /* ADC <-> SBC */
21276 new_inst = OPCODE_SBC;
21277 value = inverted;
21278 break;
bfae80f2 21279
c19d1205
ZW		 21280 case OPCODE_SBC:
21281 new_inst = OPCODE_ADC;
21282 value = inverted;
21283 break;
bfae80f2 21284
c19d1205
ZW		 21285 /* We cannot do anything. */
21286 default:
21287 return FAIL;
b99bd4ef
NC		 21288 }
21289
c19d1205
ZW		 21290 if (value == (unsigned) FAIL)
21291 return FAIL;
21292
21293 *instruction &= OPCODE_MASK;
21294 *instruction |= new_inst << DATA_OP_SHIFT;
21295 return value;
b99bd4ef
NC		 21296}
21297
ef8d22e6
PB		 21298/* Like negate_data_op, but for Thumb-2. */
21299
21300static unsigned int
16dd5e42 21301thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB		 21302{
21303 int op, new_inst;
21304 int rd;
16dd5e42 21305 unsigned int negated, inverted;
ef8d22e6
PB		 21306
21307 negated = encode_thumb32_immediate (-value);
21308 inverted = encode_thumb32_immediate (~value);
21309
21310 rd = (*instruction >> 8) & 0xf;
21311 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21312 switch (op)
21313 {
21314 /* ADD <-> SUB. Includes CMP <-> CMN. */
21315 case T2_OPCODE_SUB:
21316 new_inst = T2_OPCODE_ADD;
21317 value = negated;
21318 break;
21319
21320 case T2_OPCODE_ADD:
21321 new_inst = T2_OPCODE_SUB;
21322 value = negated;
21323 break;
21324
21325 /* ORR <-> ORN. Includes MOV <-> MVN. */
21326 case T2_OPCODE_ORR:
21327 new_inst = T2_OPCODE_ORN;
21328 value = inverted;
21329 break;
21330
21331 case T2_OPCODE_ORN:
21332 new_inst = T2_OPCODE_ORR;
21333 value = inverted;
21334 break;
21335
21336 /* AND <-> BIC. TST has no inverted equivalent. */
21337 case T2_OPCODE_AND:
21338 new_inst = T2_OPCODE_BIC;
21339 if (rd == 15)
21340 value = FAIL;
21341 else
21342 value = inverted;
21343 break;
21344
21345 case T2_OPCODE_BIC:
21346 new_inst = T2_OPCODE_AND;
21347 value = inverted;
21348 break;
21349
21350 /* ADC <-> SBC */
21351 case T2_OPCODE_ADC:
21352 new_inst = T2_OPCODE_SBC;
21353 value = inverted;
21354 break;
21355
21356 case T2_OPCODE_SBC:
21357 new_inst = T2_OPCODE_ADC;
21358 value = inverted;
21359 break;
21360
21361 /* We cannot do anything. */
21362 default:
21363 return FAIL;
21364 }
21365
16dd5e42 21366 if (value == (unsigned int)FAIL)
ef8d22e6
PB		 21367 return FAIL;
21368
21369 *instruction &= T2_OPCODE_MASK;
21370 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21371 return value;
21372}
21373
8f06b2d8
PB		 21374/* Read a 32-bit thumb instruction from buf. */
21375static unsigned long
21376get_thumb32_insn (char * buf)
21377{
21378 unsigned long insn;
21379 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21380 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21381
21382 return insn;
21383}
21384
a8bc6c78
PB		 21385
21386/* We usually want to set the low bit on the address of thumb function
21387 symbols. In particular .word foo - . should have the low bit set.
21388 Generic code tries to fold the difference of two symbols to
21389 a constant. Prevent this and force a relocation when the first symbols
21390 is a thumb function. */
c921be7d
NC		 21391
21392bfd_boolean
a8bc6c78
PB		 21393arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21394{
21395 if (op == O_subtract
21396 && l->X_op == O_symbol
21397 && r->X_op == O_symbol
21398 && THUMB_IS_FUNC (l->X_add_symbol))
21399 {
21400 l->X_op = O_subtract;
21401 l->X_op_symbol = r->X_add_symbol;
21402 l->X_add_number -= r->X_add_number;
c921be7d 21403 return TRUE;
a8bc6c78 21404 }
c921be7d 21405
a8bc6c78 21406 /* Process as normal. */
c921be7d 21407 return FALSE;
a8bc6c78
PB		 21408}
21409
4a42ebbc
RR		 21410/* Encode Thumb2 unconditional branches and calls. The encoding
21411 for the 2 are identical for the immediate values. */
21412
21413static void
21414encode_thumb2_b_bl_offset (char * buf, offsetT value)
21415{
21416#define T2I1I2MASK ((1 << 13) | (1 << 11))
21417 offsetT newval;
21418 offsetT newval2;
21419 addressT S, I1, I2, lo, hi;
21420
21421 S = (value >> 24) & 0x01;
21422 I1 = (value >> 23) & 0x01;
21423 I2 = (value >> 22) & 0x01;
21424 hi = (value >> 12) & 0x3ff;
fa94de6b 21425 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR		 21426 newval = md_chars_to_number (buf, THUMB_SIZE);
21427 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21428 newval |= (S << 10) | hi;
21429 newval2 &= ~T2I1I2MASK;
21430 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21431 md_number_to_chars (buf, newval, THUMB_SIZE);
21432 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21433}
21434
c19d1205 21435void
55cf6793 21436md_apply_fix (fixS * fixP,
c19d1205
ZW		 21437 valueT * valP,
21438 segT seg)
21439{
21440 offsetT value = * valP;
21441 offsetT newval;
21442 unsigned int newimm;
21443 unsigned long temp;
21444 int sign;
21445 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 21446
9c2799c2 21447 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 21448
c19d1205 21449 /* Note whether this will delete the relocation. */
4962c51a 21450
c19d1205
ZW		 21451 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21452 fixP->fx_done = 1;
b99bd4ef 21453
adbaf948 21454 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 21455 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW		 21456 for emit_reloc. */
21457 value &= 0xffffffff;
21458 value ^= 0x80000000;
5f4273c7 21459 value -= 0x80000000;
adbaf948
ZW		 21460
21461 *valP = value;
c19d1205 21462 fixP->fx_addnumber = value;
b99bd4ef 21463
adbaf948
ZW		 21464 /* Same treatment for fixP->fx_offset. */
21465 fixP->fx_offset &= 0xffffffff;
21466 fixP->fx_offset ^= 0x80000000;
21467 fixP->fx_offset -= 0x80000000;
21468
c19d1205 21469 switch (fixP->fx_r_type)
b99bd4ef 21470 {
c19d1205
ZW		 21471 case BFD_RELOC_NONE:
21472 /* This will need to go in the object file. */
21473 fixP->fx_done = 0;
21474 break;
b99bd4ef 21475
c19d1205
ZW		 21476 case BFD_RELOC_ARM_IMMEDIATE:
21477 /* We claim that this fixup has been processed here,
21478 even if in fact we generate an error because we do
21479 not have a reloc for it, so tc_gen_reloc will reject it. */
21480 fixP->fx_done = 1;
b99bd4ef 21481
77db8e2e 21482 if (fixP->fx_addsy)
b99bd4ef 21483 {
77db8e2e 21484 const char *msg = 0;
b99bd4ef 21485
77db8e2e
NC		 21486 if (! S_IS_DEFINED (fixP->fx_addsy))
21487 msg = _("undefined symbol %s used as an immediate value");
21488 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21489 msg = _("symbol %s is in a different section");
21490 else if (S_IS_WEAK (fixP->fx_addsy))
21491 msg = _("symbol %s is weak and may be overridden later");
21492
21493 if (msg)
21494 {
21495 as_bad_where (fixP->fx_file, fixP->fx_line,
21496 msg, S_GET_NAME (fixP->fx_addsy));
21497 break;
21498 }
42e5fcbf
AS		 21499 }
21500
c19d1205
ZW		 21501 temp = md_chars_to_number (buf, INSN_SIZE);
21502
5e73442d
SL		 21503 /* If the offset is negative, we should use encoding A2 for ADR. */
21504 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21505 newimm = negate_data_op (&temp, value);
21506 else
21507 {
21508 newimm = encode_arm_immediate (value);
21509
21510 /* If the instruction will fail, see if we can fix things up by
21511 changing the opcode. */
21512 if (newimm == (unsigned int) FAIL)
21513 newimm = negate_data_op (&temp, value);
21514 }
21515
21516 if (newimm == (unsigned int) FAIL)
b99bd4ef 21517 {
c19d1205
ZW		 21518 as_bad_where (fixP->fx_file, fixP->fx_line,
21519 _("invalid constant (%lx) after fixup"),
21520 (unsigned long) value);
21521 break;
b99bd4ef 21522 }
b99bd4ef 21523
c19d1205
ZW		 21524 newimm |= (temp & 0xfffff000);
21525 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21526 break;
b99bd4ef 21527
c19d1205
ZW		 21528 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21529 {
21530 unsigned int highpart = 0;
21531 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 21532
77db8e2e 21533 if (fixP->fx_addsy)
42e5fcbf 21534 {
77db8e2e 21535 const char *msg = 0;
42e5fcbf 21536
77db8e2e
NC		 21537 if (! S_IS_DEFINED (fixP->fx_addsy))
21538 msg = _("undefined symbol %s used as an immediate value");
21539 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21540 msg = _("symbol %s is in a different section");
21541 else if (S_IS_WEAK (fixP->fx_addsy))
21542 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 21543
77db8e2e
NC		 21544 if (msg)
21545 {
21546 as_bad_where (fixP->fx_file, fixP->fx_line,
21547 msg, S_GET_NAME (fixP->fx_addsy));
21548 break;
21549 }
21550 }
fa94de6b 21551
c19d1205
ZW		 21552 newimm = encode_arm_immediate (value);
21553 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 21554
c19d1205
ZW		 21555 /* If the instruction will fail, see if we can fix things up by
21556 changing the opcode. */
21557 if (newimm == (unsigned int) FAIL
21558 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
21559 {
21560 /* No ? OK - try using two ADD instructions to generate
21561 the value. */
21562 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 21563
c19d1205
ZW		 21564 /* Yes - then make sure that the second instruction is
21565 also an add. */
21566 if (newimm != (unsigned int) FAIL)
21567 newinsn = temp;
21568 /* Still No ? Try using a negated value. */
21569 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
21570 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
21571 /* Otherwise - give up. */
21572 else
21573 {
21574 as_bad_where (fixP->fx_file, fixP->fx_line,
21575 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21576 (long) value);
21577 break;
21578 }
b99bd4ef 21579
c19d1205
ZW		 21580 /* Replace the first operand in the 2nd instruction (which
21581 is the PC) with the destination register. We have
21582 already added in the PC in the first instruction and we
21583 do not want to do it again. */
21584 newinsn &= ~ 0xf0000;
21585 newinsn |= ((newinsn & 0x0f000) << 4);
21586 }
b99bd4ef 21587
c19d1205
ZW		 21588 newimm |= (temp & 0xfffff000);
21589 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 21590
c19d1205
ZW		 21591 highpart |= (newinsn & 0xfffff000);
21592 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
21593 }
21594 break;
b99bd4ef 21595
c19d1205 21596 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 21597 if (!fixP->fx_done && seg->use_rela_p)
21598 value = 0;
21599
c19d1205 21600 case BFD_RELOC_ARM_LITERAL:
26d97720 21601 sign = value > 0;
b99bd4ef 21602
c19d1205
ZW		 21603 if (value < 0)
21604 value = - value;
b99bd4ef 21605
c19d1205 21606 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 21607 {
c19d1205
ZW		 21608 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
21609 as_bad_where (fixP->fx_file, fixP->fx_line,
21610 _("invalid literal constant: pool needs to be closer"));
21611 else
21612 as_bad_where (fixP->fx_file, fixP->fx_line,
21613 _("bad immediate value for offset (%ld)"),
21614 (long) value);
21615 break;
f03698e6
RE		 21616 }
21617
c19d1205 21618 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 21619 if (value == 0)
21620 newval &= 0xfffff000;
21621 else
21622 {
21623 newval &= 0xff7ff000;
21624 newval |= value | (sign ? INDEX_UP : 0);
21625 }
c19d1205
ZW		 21626 md_number_to_chars (buf, newval, INSN_SIZE);
21627 break;
b99bd4ef 21628
c19d1205
ZW		 21629 case BFD_RELOC_ARM_OFFSET_IMM8:
21630 case BFD_RELOC_ARM_HWLITERAL:
26d97720 21631 sign = value > 0;
b99bd4ef 21632
c19d1205
ZW		 21633 if (value < 0)
21634 value = - value;
b99bd4ef 21635
c19d1205 21636 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 21637 {
c19d1205
ZW		 21638 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
21639 as_bad_where (fixP->fx_file, fixP->fx_line,
21640 _("invalid literal constant: pool needs to be closer"));
21641 else
427d0db6
RM		 21642 as_bad_where (fixP->fx_file, fixP->fx_line,
21643 _("bad immediate value for 8-bit offset (%ld)"),
21644 (long) value);
c19d1205 21645 break;
b99bd4ef
NC		 21646 }
21647
c19d1205 21648 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 21649 if (value == 0)
21650 newval &= 0xfffff0f0;
21651 else
21652 {
21653 newval &= 0xff7ff0f0;
21654 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
21655 }
c19d1205
ZW		 21656 md_number_to_chars (buf, newval, INSN_SIZE);
21657 break;
b99bd4ef 21658
c19d1205
ZW		 21659 case BFD_RELOC_ARM_T32_OFFSET_U8:
21660 if (value < 0 || value > 1020 || value % 4 != 0)
21661 as_bad_where (fixP->fx_file, fixP->fx_line,
21662 _("bad immediate value for offset (%ld)"), (long) value);
21663 value /= 4;
b99bd4ef 21664
c19d1205 21665 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW		 21666 newval |= value;
21667 md_number_to_chars (buf+2, newval, THUMB_SIZE);
21668 break;
b99bd4ef 21669
c19d1205
ZW		 21670 case BFD_RELOC_ARM_T32_OFFSET_IMM:
21671 /* This is a complicated relocation used for all varieties of Thumb32
21672 load/store instruction with immediate offset:
21673
21674 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 21675 *4, optional writeback(W)
c19d1205
ZW		 21676 (doubleword load/store)
21677
21678 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21679 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21680 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21681 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21682 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21683
21684 Uppercase letters indicate bits that are already encoded at
21685 this point. Lowercase letters are our problem. For the
21686 second block of instructions, the secondary opcode nybble
21687 (bits 8..11) is present, and bit 23 is zero, even if this is
21688 a PC-relative operation. */
21689 newval = md_chars_to_number (buf, THUMB_SIZE);
21690 newval <<= 16;
21691 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 21692
c19d1205 21693 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 21694 {
c19d1205
ZW		 21695 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21696 if (value >= 0)
21697 newval |= (1 << 23);
21698 else
21699 value = -value;
21700 if (value % 4 != 0)
21701 {
21702 as_bad_where (fixP->fx_file, fixP->fx_line,
21703 _("offset not a multiple of 4"));
21704 break;
21705 }
21706 value /= 4;
216d22bc 21707 if (value > 0xff)
c19d1205
ZW		 21708 {
21709 as_bad_where (fixP->fx_file, fixP->fx_line,
21710 _("offset out of range"));
21711 break;
21712 }
21713 newval &= ~0xff;
b99bd4ef 21714 }
c19d1205 21715 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 21716 {
c19d1205
ZW		 21717 /* PC-relative, 12-bit offset. */
21718 if (value >= 0)
21719 newval |= (1 << 23);
21720 else
21721 value = -value;
216d22bc 21722 if (value > 0xfff)
c19d1205
ZW		 21723 {
21724 as_bad_where (fixP->fx_file, fixP->fx_line,
21725 _("offset out of range"));
21726 break;
21727 }
21728 newval &= ~0xfff;
b99bd4ef 21729 }
c19d1205 21730 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 21731 {
c19d1205
ZW		 21732 /* Writeback: 8-bit, +/- offset. */
21733 if (value >= 0)
21734 newval |= (1 << 9);
21735 else
21736 value = -value;
216d22bc 21737 if (value > 0xff)
c19d1205
ZW		 21738 {
21739 as_bad_where (fixP->fx_file, fixP->fx_line,
21740 _("offset out of range"));
21741 break;
21742 }
21743 newval &= ~0xff;
b99bd4ef 21744 }
c19d1205 21745 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 21746 {
c19d1205 21747 /* T-instruction: positive 8-bit offset. */
216d22bc 21748 if (value < 0 || value > 0xff)
b99bd4ef 21749 {
c19d1205
ZW		 21750 as_bad_where (fixP->fx_file, fixP->fx_line,
21751 _("offset out of range"));
21752 break;
b99bd4ef 21753 }
c19d1205
ZW		 21754 newval &= ~0xff;
21755 newval |= value;
b99bd4ef
NC		 21756 }
21757 else
b99bd4ef 21758 {
c19d1205
ZW		 21759 /* Positive 12-bit or negative 8-bit offset. */
21760 int limit;
21761 if (value >= 0)
b99bd4ef 21762 {
c19d1205
ZW		 21763 newval |= (1 << 23);
21764 limit = 0xfff;
21765 }
21766 else
21767 {
21768 value = -value;
21769 limit = 0xff;
21770 }
21771 if (value > limit)
21772 {
21773 as_bad_where (fixP->fx_file, fixP->fx_line,
21774 _("offset out of range"));
21775 break;
b99bd4ef 21776 }
c19d1205 21777 newval &= ~limit;
b99bd4ef 21778 }
b99bd4ef 21779
c19d1205
ZW		 21780 newval |= value;
21781 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
21782 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
21783 break;
404ff6b5 21784
c19d1205
ZW		 21785 case BFD_RELOC_ARM_SHIFT_IMM:
21786 newval = md_chars_to_number (buf, INSN_SIZE);
21787 if (((unsigned long) value) > 32
21788 || (value == 32
21789 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
21790 {
21791 as_bad_where (fixP->fx_file, fixP->fx_line,
21792 _("shift expression is too large"));
21793 break;
21794 }
404ff6b5 21795
c19d1205
ZW		 21796 if (value == 0)
21797 /* Shifts of zero must be done as lsl. */
21798 newval &= ~0x60;
21799 else if (value == 32)
21800 value = 0;
21801 newval &= 0xfffff07f;
21802 newval |= (value & 0x1f) << 7;
21803 md_number_to_chars (buf, newval, INSN_SIZE);
21804 break;
404ff6b5 21805
c19d1205 21806 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 21807 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 21808 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 21809 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW		 21810 /* We claim that this fixup has been processed here,
21811 even if in fact we generate an error because we do
21812 not have a reloc for it, so tc_gen_reloc will reject it. */
21813 fixP->fx_done = 1;
404ff6b5 21814
c19d1205
ZW		 21815 if (fixP->fx_addsy
21816 && ! S_IS_DEFINED (fixP->fx_addsy))
21817 {
21818 as_bad_where (fixP->fx_file, fixP->fx_line,
21819 _("undefined symbol %s used as an immediate value"),
21820 S_GET_NAME (fixP->fx_addsy));
21821 break;
21822 }
404ff6b5 21823
c19d1205
ZW		 21824 newval = md_chars_to_number (buf, THUMB_SIZE);
21825 newval <<= 16;
21826 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 21827
16805f35
PB		 21828 newimm = FAIL;
21829 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
21830 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB		 21831 {
21832 newimm = encode_thumb32_immediate (value);
21833 if (newimm == (unsigned int) FAIL)
21834 newimm = thumb32_negate_data_op (&newval, value);
21835 }
16805f35
PB		 21836 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
21837 && newimm == (unsigned int) FAIL)
92e90b6e 21838 {
16805f35
PB		 21839 /* Turn add/sum into addw/subw. */
21840 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
21841 newval = (newval & 0xfeffffff) | 0x02000000;
40f246e3
NC		 21842 /* No flat 12-bit imm encoding for addsw/subsw. */
21843 if ((newval & 0x00100000) == 0)
e9f89963 21844 {
40f246e3
NC		 21845 /* 12 bit immediate for addw/subw. */
21846 if (value < 0)
21847 {
21848 value = -value;
21849 newval ^= 0x00a00000;
21850 }
21851 if (value > 0xfff)
21852 newimm = (unsigned int) FAIL;
21853 else
21854 newimm = value;
e9f89963 21855 }
92e90b6e 21856 }
cc8a6dd0 21857
c19d1205 21858 if (newimm == (unsigned int)FAIL)
3631a3c8 21859 {
c19d1205
ZW		 21860 as_bad_where (fixP->fx_file, fixP->fx_line,
21861 _("invalid constant (%lx) after fixup"),
21862 (unsigned long) value);
21863 break;
3631a3c8
NC		 21864 }
21865
c19d1205
ZW		 21866 newval |= (newimm & 0x800) << 15;
21867 newval |= (newimm & 0x700) << 4;
21868 newval |= (newimm & 0x0ff);
cc8a6dd0 21869
c19d1205
ZW		 21870 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
21871 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
21872 break;
a737bd4d 21873
3eb17e6b 21874 case BFD_RELOC_ARM_SMC:
c19d1205
ZW		 21875 if (((unsigned long) value) > 0xffff)
21876 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 21877 _("invalid smc expression"));
2fc8bdac 21878 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 21879 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21880 md_number_to_chars (buf, newval, INSN_SIZE);
21881 break;
a737bd4d 21882
90ec0d68
MGD		 21883 case BFD_RELOC_ARM_HVC:
21884 if (((unsigned long) value) > 0xffff)
21885 as_bad_where (fixP->fx_file, fixP->fx_line,
21886 _("invalid hvc expression"));
21887 newval = md_chars_to_number (buf, INSN_SIZE);
21888 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
21889 md_number_to_chars (buf, newval, INSN_SIZE);
21890 break;
21891
c19d1205 21892 case BFD_RELOC_ARM_SWI:
adbaf948 21893 if (fixP->tc_fix_data != 0)
c19d1205
ZW		 21894 {
21895 if (((unsigned long) value) > 0xff)
21896 as_bad_where (fixP->fx_file, fixP->fx_line,
21897 _("invalid swi expression"));
2fc8bdac 21898 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW		 21899 newval |= value;
21900 md_number_to_chars (buf, newval, THUMB_SIZE);
21901 }
21902 else
21903 {
21904 if (((unsigned long) value) > 0x00ffffff)
21905 as_bad_where (fixP->fx_file, fixP->fx_line,
21906 _("invalid swi expression"));
2fc8bdac 21907 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 21908 newval |= value;
21909 md_number_to_chars (buf, newval, INSN_SIZE);
21910 }
21911 break;
a737bd4d 21912
c19d1205
ZW		 21913 case BFD_RELOC_ARM_MULTI:
21914 if (((unsigned long) value) > 0xffff)
21915 as_bad_where (fixP->fx_file, fixP->fx_line,
21916 _("invalid expression in load/store multiple"));
21917 newval = value | md_chars_to_number (buf, INSN_SIZE);
21918 md_number_to_chars (buf, newval, INSN_SIZE);
21919 break;
a737bd4d 21920
c19d1205 21921#ifdef OBJ_ELF
39b41c9c 21922 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR		 21923
21924 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21925 && fixP->fx_addsy
34e77a92 21926 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 21927 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21928 && THUMB_IS_FUNC (fixP->fx_addsy))
21929 /* Flip the bl to blx. This is a simple flip
21930 bit here because we generate PCREL_CALL for
21931 unconditional bls. */
21932 {
21933 newval = md_chars_to_number (buf, INSN_SIZE);
21934 newval = newval | 0x10000000;
21935 md_number_to_chars (buf, newval, INSN_SIZE);
21936 temp = 1;
21937 fixP->fx_done = 1;
21938 }
39b41c9c
PB		 21939 else
21940 temp = 3;
21941 goto arm_branch_common;
21942
21943 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR		 21944 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21945 && fixP->fx_addsy
34e77a92 21946 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 21947 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21948 && THUMB_IS_FUNC (fixP->fx_addsy))
21949 {
21950 /* This would map to a bl<cond>, b<cond>,
21951 b<always> to a Thumb function. We
21952 need to force a relocation for this particular
21953 case. */
21954 newval = md_chars_to_number (buf, INSN_SIZE);
21955 fixP->fx_done = 0;
21956 }
21957
2fc8bdac 21958 case BFD_RELOC_ARM_PLT32:
c19d1205 21959#endif
39b41c9c
PB		 21960 case BFD_RELOC_ARM_PCREL_BRANCH:
21961 temp = 3;
21962 goto arm_branch_common;
a737bd4d 21963
39b41c9c 21964 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 21965
39b41c9c 21966 temp = 1;
267bf995
RR		 21967 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
21968 && fixP->fx_addsy
34e77a92 21969 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 21970 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21971 && ARM_IS_FUNC (fixP->fx_addsy))
21972 {
21973 /* Flip the blx to a bl and warn. */
21974 const char *name = S_GET_NAME (fixP->fx_addsy);
21975 newval = 0xeb000000;
21976 as_warn_where (fixP->fx_file, fixP->fx_line,
21977 _("blx to '%s' an ARM ISA state function changed to bl"),
21978 name);
21979 md_number_to_chars (buf, newval, INSN_SIZE);
21980 temp = 3;
21981 fixP->fx_done = 1;
21982 }
21983
21984#ifdef OBJ_ELF
21985 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 21986 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR		 21987#endif
21988
39b41c9c 21989 arm_branch_common:
c19d1205 21990 /* We are going to store value (shifted right by two) in the
39b41c9c
PB		 21991 instruction, in a 24 bit, signed field. Bits 26 through 32 either
21992 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
21993 also be be clear. */
21994 if (value & temp)
c19d1205 21995 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW		 21996 _("misaligned branch destination"));
21997 if ((value & (offsetT)0xfe000000) != (offsetT)0
21998 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 21999 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22000
2fc8bdac 22001 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 22002 {
2fc8bdac
ZW		 22003 newval = md_chars_to_number (buf, INSN_SIZE);
22004 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB		 22005 /* Set the H bit on BLX instructions. */
22006 if (temp == 1)
22007 {
22008 if (value & 2)
22009 newval |= 0x01000000;
22010 else
22011 newval &= ~0x01000000;
22012 }
2fc8bdac 22013 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 22014 }
c19d1205 22015 break;
a737bd4d 22016
25fe350b
MS		 22017 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22018 /* CBZ can only branch forward. */
a737bd4d 22019
738755b0 22020 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM		 22021 (which, strictly speaking, are prohibited) will be turned into
22022 no-ops.
738755b0
MS		 22023
22024 FIXME: It may be better to remove the instruction completely and
22025 perform relaxation. */
22026 if (value == -2)
2fc8bdac
ZW		 22027 {
22028 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 22029 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW		 22030 md_number_to_chars (buf, newval, THUMB_SIZE);
22031 }
738755b0
MS		 22032 else
22033 {
22034 if (value & ~0x7e)
08f10d51 22035 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 22036
477330fc 22037 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS		 22038 {
22039 newval = md_chars_to_number (buf, THUMB_SIZE);
22040 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22041 md_number_to_chars (buf, newval, THUMB_SIZE);
22042 }
22043 }
c19d1205 22044 break;
a737bd4d 22045
c19d1205 22046 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac 22047 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
08f10d51 22048 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22049
2fc8bdac
ZW		 22050 if (fixP->fx_done || !seg->use_rela_p)
22051 {
22052 newval = md_chars_to_number (buf, THUMB_SIZE);
22053 newval |= (value & 0x1ff) >> 1;
22054 md_number_to_chars (buf, newval, THUMB_SIZE);
22055 }
c19d1205 22056 break;
a737bd4d 22057
c19d1205 22058 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac 22059 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
08f10d51 22060 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22061
2fc8bdac
ZW		 22062 if (fixP->fx_done || !seg->use_rela_p)
22063 {
22064 newval = md_chars_to_number (buf, THUMB_SIZE);
22065 newval |= (value & 0xfff) >> 1;
22066 md_number_to_chars (buf, newval, THUMB_SIZE);
22067 }
c19d1205 22068 break;
a737bd4d 22069
c19d1205 22070 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR		 22071 if (fixP->fx_addsy
22072 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 22073 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22074 && ARM_IS_FUNC (fixP->fx_addsy)
22075 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22076 {
22077 /* Force a relocation for a branch 20 bits wide. */
22078 fixP->fx_done = 0;
22079 }
08f10d51 22080 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
2fc8bdac
ZW		 22081 as_bad_where (fixP->fx_file, fixP->fx_line,
22082 _("conditional branch out of range"));
404ff6b5 22083
2fc8bdac
ZW		 22084 if (fixP->fx_done || !seg->use_rela_p)
22085 {
22086 offsetT newval2;
22087 addressT S, J1, J2, lo, hi;
404ff6b5 22088
2fc8bdac
ZW		 22089 S = (value & 0x00100000) >> 20;
22090 J2 = (value & 0x00080000) >> 19;
22091 J1 = (value & 0x00040000) >> 18;
22092 hi = (value & 0x0003f000) >> 12;
22093 lo = (value & 0x00000ffe) >> 1;
6c43fab6 22094
2fc8bdac
ZW		 22095 newval = md_chars_to_number (buf, THUMB_SIZE);
22096 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22097 newval |= (S << 10) | hi;
22098 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22099 md_number_to_chars (buf, newval, THUMB_SIZE);
22100 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22101 }
c19d1205 22102 break;
6c43fab6 22103
c19d1205 22104 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR		 22105 /* If there is a blx from a thumb state function to
22106 another thumb function flip this to a bl and warn
22107 about it. */
22108
22109 if (fixP->fx_addsy
34e77a92 22110 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22111 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22112 && THUMB_IS_FUNC (fixP->fx_addsy))
22113 {
22114 const char *name = S_GET_NAME (fixP->fx_addsy);
22115 as_warn_where (fixP->fx_file, fixP->fx_line,
22116 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22117 name);
22118 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22119 newval = newval | 0x1000;
22120 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22121 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22122 fixP->fx_done = 1;
22123 }
22124
22125
22126 goto thumb_bl_common;
22127
c19d1205 22128 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR		 22129 /* A bl from Thumb state ISA to an internal ARM state function
22130 is converted to a blx. */
22131 if (fixP->fx_addsy
22132 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 22133 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22134 && ARM_IS_FUNC (fixP->fx_addsy)
22135 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22136 {
22137 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22138 newval = newval & ~0x1000;
22139 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22140 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22141 fixP->fx_done = 1;
22142 }
22143
22144 thumb_bl_common:
22145
2fc8bdac
ZW		 22146 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22147 /* For a BLX instruction, make sure that the relocation is rounded up
22148 to a word boundary. This follows the semantics of the instruction
22149 which specifies that bit 1 of the target address will come from bit
22150 1 of the base address. */
d406f3e4
JB		 22151 value = (value + 3) & ~ 3;
22152
22153#ifdef OBJ_ELF
22154 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22155 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22156 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22157#endif
404ff6b5 22158
2b2f5df9
NC		 22159 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22160 {
22161 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22162 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22163 else if ((value & ~0x1ffffff)
22164 && ((value & ~0x1ffffff) != ~0x1ffffff))
22165 as_bad_where (fixP->fx_file, fixP->fx_line,
22166 _("Thumb2 branch out of range"));
22167 }
4a42ebbc
RR		 22168
22169 if (fixP->fx_done || !seg->use_rela_p)
22170 encode_thumb2_b_bl_offset (buf, value);
22171
c19d1205 22172 break;
404ff6b5 22173
c19d1205 22174 case BFD_RELOC_THUMB_PCREL_BRANCH25:
08f10d51
NC		 22175 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22176 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 22177
2fc8bdac 22178 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 22179 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 22180
2fc8bdac 22181 break;
a737bd4d 22182
2fc8bdac
ZW		 22183 case BFD_RELOC_8:
22184 if (fixP->fx_done || !seg->use_rela_p)
22185 md_number_to_chars (buf, value, 1);
c19d1205 22186 break;
a737bd4d 22187
c19d1205 22188 case BFD_RELOC_16:
2fc8bdac 22189 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 22190 md_number_to_chars (buf, value, 2);
c19d1205 22191 break;
a737bd4d 22192
c19d1205 22193#ifdef OBJ_ELF
0855e32b
NS		 22194 case BFD_RELOC_ARM_TLS_CALL:
22195 case BFD_RELOC_ARM_THM_TLS_CALL:
22196 case BFD_RELOC_ARM_TLS_DESCSEQ:
22197 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
22198 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22199 break;
22200
22201 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 22202 case BFD_RELOC_ARM_TLS_GD32:
22203 case BFD_RELOC_ARM_TLS_LE32:
22204 case BFD_RELOC_ARM_TLS_IE32:
22205 case BFD_RELOC_ARM_TLS_LDM32:
22206 case BFD_RELOC_ARM_TLS_LDO32:
22207 S_SET_THREAD_LOCAL (fixP->fx_addsy);
22208 /* fall through */
6c43fab6 22209
c19d1205
ZW		 22210 case BFD_RELOC_ARM_GOT32:
22211 case BFD_RELOC_ARM_GOTOFF:
2fc8bdac
ZW		 22212 if (fixP->fx_done || !seg->use_rela_p)
22213 md_number_to_chars (buf, 0, 4);
c19d1205 22214 break;
b43420e6
NC		 22215
22216 case BFD_RELOC_ARM_GOT_PREL:
22217 if (fixP->fx_done || !seg->use_rela_p)
477330fc 22218 md_number_to_chars (buf, value, 4);
b43420e6
NC		 22219 break;
22220
9a6f4e97
NS		 22221 case BFD_RELOC_ARM_TARGET2:
22222 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM		 22223 addend here for REL targets, because it won't be written out
22224 during reloc processing later. */
9a6f4e97
NS		 22225 if (fixP->fx_done || !seg->use_rela_p)
22226 md_number_to_chars (buf, fixP->fx_offset, 4);
22227 break;
c19d1205 22228#endif
6c43fab6 22229
c19d1205
ZW		 22230 case BFD_RELOC_RVA:
22231 case BFD_RELOC_32:
22232 case BFD_RELOC_ARM_TARGET1:
22233 case BFD_RELOC_ARM_ROSEGREL32:
22234 case BFD_RELOC_ARM_SBREL32:
22235 case BFD_RELOC_32_PCREL:
f0927246
NC		 22236#ifdef TE_PE
22237 case BFD_RELOC_32_SECREL:
22238#endif
2fc8bdac 22239 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC		 22240#ifdef TE_WINCE
22241 /* For WinCE we only do this for pcrel fixups. */
22242 if (fixP->fx_done || fixP->fx_pcrel)
22243#endif
22244 md_number_to_chars (buf, value, 4);
c19d1205 22245 break;
6c43fab6 22246
c19d1205
ZW		 22247#ifdef OBJ_ELF
22248 case BFD_RELOC_ARM_PREL31:
2fc8bdac 22249 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW		 22250 {
22251 newval = md_chars_to_number (buf, 4) & 0x80000000;
22252 if ((value ^ (value >> 1)) & 0x40000000)
22253 {
22254 as_bad_where (fixP->fx_file, fixP->fx_line,
22255 _("rel31 relocation overflow"));
22256 }
22257 newval |= value & 0x7fffffff;
22258 md_number_to_chars (buf, newval, 4);
22259 }
22260 break;
c19d1205 22261#endif
a737bd4d 22262
c19d1205 22263 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 22264 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
c19d1205
ZW		 22265 if (value < -1023 || value > 1023 || (value & 3))
22266 as_bad_where (fixP->fx_file, fixP->fx_line,
22267 _("co-processor offset out of range"));
22268 cp_off_common:
26d97720 22269 sign = value > 0;
c19d1205
ZW		 22270 if (value < 0)
22271 value = -value;
8f06b2d8
PB		 22272 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22273 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22274 newval = md_chars_to_number (buf, INSN_SIZE);
22275 else
22276 newval = get_thumb32_insn (buf);
26d97720
NS		 22277 if (value == 0)
22278 newval &= 0xffffff00;
22279 else
22280 {
22281 newval &= 0xff7fff00;
22282 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22283 }
8f06b2d8
PB		 22284 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22285 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22286 md_number_to_chars (buf, newval, INSN_SIZE);
22287 else
22288 put_thumb32_insn (buf, newval);
c19d1205 22289 break;
a737bd4d 22290
c19d1205 22291 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 22292 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW		 22293 if (value < -255 || value > 255)
22294 as_bad_where (fixP->fx_file, fixP->fx_line,
22295 _("co-processor offset out of range"));
df7849c5 22296 value *= 4;
c19d1205 22297 goto cp_off_common;
6c43fab6 22298
c19d1205
ZW		 22299 case BFD_RELOC_ARM_THUMB_OFFSET:
22300 newval = md_chars_to_number (buf, THUMB_SIZE);
22301 /* Exactly what ranges, and where the offset is inserted depends
22302 on the type of instruction, we can establish this from the
22303 top 4 bits. */
22304 switch (newval >> 12)
22305 {
22306 case 4: /* PC load. */
22307 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22308 forced to zero for these loads; md_pcrel_from has already
22309 compensated for this. */
22310 if (value & 3)
22311 as_bad_where (fixP->fx_file, fixP->fx_line,
22312 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC		 22313 (((unsigned long) fixP->fx_frag->fr_address
22314 + (unsigned long) fixP->fx_where) & ~3)
22315 + (unsigned long) value);
a737bd4d 22316
c19d1205
ZW		 22317 if (value & ~0x3fc)
22318 as_bad_where (fixP->fx_file, fixP->fx_line,
22319 _("invalid offset, value too big (0x%08lX)"),
22320 (long) value);
a737bd4d 22321
c19d1205
ZW		 22322 newval |= value >> 2;
22323 break;
a737bd4d 22324
c19d1205
ZW		 22325 case 9: /* SP load/store. */
22326 if (value & ~0x3fc)
22327 as_bad_where (fixP->fx_file, fixP->fx_line,
22328 _("invalid offset, value too big (0x%08lX)"),
22329 (long) value);
22330 newval |= value >> 2;
22331 break;
6c43fab6 22332
c19d1205
ZW		 22333 case 6: /* Word load/store. */
22334 if (value & ~0x7c)
22335 as_bad_where (fixP->fx_file, fixP->fx_line,
22336 _("invalid offset, value too big (0x%08lX)"),
22337 (long) value);
22338 newval |= value << 4; /* 6 - 2. */
22339 break;
a737bd4d 22340
c19d1205
ZW		 22341 case 7: /* Byte load/store. */
22342 if (value & ~0x1f)
22343 as_bad_where (fixP->fx_file, fixP->fx_line,
22344 _("invalid offset, value too big (0x%08lX)"),
22345 (long) value);
22346 newval |= value << 6;
22347 break;
a737bd4d 22348
c19d1205
ZW		 22349 case 8: /* Halfword load/store. */
22350 if (value & ~0x3e)
22351 as_bad_where (fixP->fx_file, fixP->fx_line,
22352 _("invalid offset, value too big (0x%08lX)"),
22353 (long) value);
22354 newval |= value << 5; /* 6 - 1. */
22355 break;
a737bd4d 22356
c19d1205
ZW		 22357 default:
22358 as_bad_where (fixP->fx_file, fixP->fx_line,
22359 "Unable to process relocation for thumb opcode: %lx",
22360 (unsigned long) newval);
22361 break;
22362 }
22363 md_number_to_chars (buf, newval, THUMB_SIZE);
22364 break;
a737bd4d 22365
c19d1205
ZW		 22366 case BFD_RELOC_ARM_THUMB_ADD:
22367 /* This is a complicated relocation, since we use it for all of
22368 the following immediate relocations:
a737bd4d 22369
c19d1205
ZW		 22370 3bit ADD/SUB
22371 8bit ADD/SUB
22372 9bit ADD/SUB SP word-aligned
22373 10bit ADD PC/SP word-aligned
a737bd4d 22374
c19d1205
ZW		 22375 The type of instruction being processed is encoded in the
22376 instruction field:
a737bd4d 22377
c19d1205
ZW		 22378 0x8000 SUB
22379 0x00F0 Rd
22380 0x000F Rs
22381 */
22382 newval = md_chars_to_number (buf, THUMB_SIZE);
22383 {
22384 int rd = (newval >> 4) & 0xf;
22385 int rs = newval & 0xf;
22386 int subtract = !!(newval & 0x8000);
a737bd4d 22387
c19d1205
ZW		 22388 /* Check for HI regs, only very restricted cases allowed:
22389 Adjusting SP, and using PC or SP to get an address. */
22390 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22391 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22392 as_bad_where (fixP->fx_file, fixP->fx_line,
22393 _("invalid Hi register with immediate"));
a737bd4d 22394
c19d1205
ZW		 22395 /* If value is negative, choose the opposite instruction. */
22396 if (value < 0)
22397 {
22398 value = -value;
22399 subtract = !subtract;
22400 if (value < 0)
22401 as_bad_where (fixP->fx_file, fixP->fx_line,
22402 _("immediate value out of range"));
22403 }
a737bd4d 22404
c19d1205
ZW		 22405 if (rd == REG_SP)
22406 {
22407 if (value & ~0x1fc)
22408 as_bad_where (fixP->fx_file, fixP->fx_line,
22409 _("invalid immediate for stack address calculation"));
22410 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22411 newval |= value >> 2;
22412 }
22413 else if (rs == REG_PC || rs == REG_SP)
22414 {
22415 if (subtract || value & ~0x3fc)
22416 as_bad_where (fixP->fx_file, fixP->fx_line,
22417 _("invalid immediate for address calculation (value = 0x%08lX)"),
22418 (unsigned long) value);
22419 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22420 newval |= rd << 8;
22421 newval |= value >> 2;
22422 }
22423 else if (rs == rd)
22424 {
22425 if (value & ~0xff)
22426 as_bad_where (fixP->fx_file, fixP->fx_line,
22427 _("immediate value out of range"));
22428 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22429 newval |= (rd << 8) | value;
22430 }
22431 else
22432 {
22433 if (value & ~0x7)
22434 as_bad_where (fixP->fx_file, fixP->fx_line,
22435 _("immediate value out of range"));
22436 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22437 newval |= rd | (rs << 3) | (value << 6);
22438 }
22439 }
22440 md_number_to_chars (buf, newval, THUMB_SIZE);
22441 break;
a737bd4d 22442
c19d1205
ZW		 22443 case BFD_RELOC_ARM_THUMB_IMM:
22444 newval = md_chars_to_number (buf, THUMB_SIZE);
22445 if (value < 0 || value > 255)
22446 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 22447 _("invalid immediate: %ld is out of range"),
c19d1205
ZW		 22448 (long) value);
22449 newval |= value;
22450 md_number_to_chars (buf, newval, THUMB_SIZE);
22451 break;
a737bd4d 22452
c19d1205
ZW		 22453 case BFD_RELOC_ARM_THUMB_SHIFT:
22454 /* 5bit shift value (0..32). LSL cannot take 32. */
22455 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22456 temp = newval & 0xf800;
22457 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22458 as_bad_where (fixP->fx_file, fixP->fx_line,
22459 _("invalid shift value: %ld"), (long) value);
22460 /* Shifts of zero must be encoded as LSL. */
22461 if (value == 0)
22462 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22463 /* Shifts of 32 are encoded as zero. */
22464 else if (value == 32)
22465 value = 0;
22466 newval |= value << 6;
22467 md_number_to_chars (buf, newval, THUMB_SIZE);
22468 break;
a737bd4d 22469
c19d1205
ZW		 22470 case BFD_RELOC_VTABLE_INHERIT:
22471 case BFD_RELOC_VTABLE_ENTRY:
22472 fixP->fx_done = 0;
22473 return;
6c43fab6 22474
b6895b4f
PB		 22475 case BFD_RELOC_ARM_MOVW:
22476 case BFD_RELOC_ARM_MOVT:
22477 case BFD_RELOC_ARM_THUMB_MOVW:
22478 case BFD_RELOC_ARM_THUMB_MOVT:
22479 if (fixP->fx_done || !seg->use_rela_p)
22480 {
22481 /* REL format relocations are limited to a 16-bit addend. */
22482 if (!fixP->fx_done)
22483 {
39623e12 22484 if (value < -0x8000 || value > 0x7fff)
b6895b4f 22485 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 22486 _("offset out of range"));
b6895b4f
PB		 22487 }
22488 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22489 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22490 {
22491 value >>= 16;
22492 }
22493
22494 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22495 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22496 {
22497 newval = get_thumb32_insn (buf);
22498 newval &= 0xfbf08f00;
22499 newval |= (value & 0xf000) << 4;
22500 newval |= (value & 0x0800) << 15;
22501 newval |= (value & 0x0700) << 4;
22502 newval |= (value & 0x00ff);
22503 put_thumb32_insn (buf, newval);
22504 }
22505 else
22506 {
22507 newval = md_chars_to_number (buf, 4);
22508 newval &= 0xfff0f000;
22509 newval |= value & 0x0fff;
22510 newval |= (value & 0xf000) << 4;
22511 md_number_to_chars (buf, newval, 4);
22512 }
22513 }
22514 return;
22515
4962c51a
MS		 22516 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22517 case BFD_RELOC_ARM_ALU_PC_G0:
22518 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22519 case BFD_RELOC_ARM_ALU_PC_G1:
22520 case BFD_RELOC_ARM_ALU_PC_G2:
22521 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22522 case BFD_RELOC_ARM_ALU_SB_G0:
22523 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22524 case BFD_RELOC_ARM_ALU_SB_G1:
22525 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 22526 gas_assert (!fixP->fx_done);
4962c51a
MS		 22527 if (!seg->use_rela_p)
22528 {
477330fc
RM		 22529 bfd_vma insn;
22530 bfd_vma encoded_addend;
22531 bfd_vma addend_abs = abs (value);
22532
22533 /* Check that the absolute value of the addend can be
22534 expressed as an 8-bit constant plus a rotation. */
22535 encoded_addend = encode_arm_immediate (addend_abs);
22536 if (encoded_addend == (unsigned int) FAIL)
4962c51a 22537 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 22538 _("the offset 0x%08lX is not representable"),
22539 (unsigned long) addend_abs);
22540
22541 /* Extract the instruction. */
22542 insn = md_chars_to_number (buf, INSN_SIZE);
22543
22544 /* If the addend is positive, use an ADD instruction.
22545 Otherwise use a SUB. Take care not to destroy the S bit. */
22546 insn &= 0xff1fffff;
22547 if (value < 0)
22548 insn |= 1 << 22;
22549 else
22550 insn |= 1 << 23;
22551
22552 /* Place the encoded addend into the first 12 bits of the
22553 instruction. */
22554 insn &= 0xfffff000;
22555 insn |= encoded_addend;
22556
22557 /* Update the instruction. */
22558 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS		 22559 }
22560 break;
22561
22562 case BFD_RELOC_ARM_LDR_PC_G0:
22563 case BFD_RELOC_ARM_LDR_PC_G1:
22564 case BFD_RELOC_ARM_LDR_PC_G2:
22565 case BFD_RELOC_ARM_LDR_SB_G0:
22566 case BFD_RELOC_ARM_LDR_SB_G1:
22567 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 22568 gas_assert (!fixP->fx_done);
4962c51a 22569 if (!seg->use_rela_p)
477330fc
RM		 22570 {
22571 bfd_vma insn;
22572 bfd_vma addend_abs = abs (value);
4962c51a 22573
477330fc
RM		 22574 /* Check that the absolute value of the addend can be
22575 encoded in 12 bits. */
22576 if (addend_abs >= 0x1000)
4962c51a 22577 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 22578 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22579 (unsigned long) addend_abs);
22580
22581 /* Extract the instruction. */
22582 insn = md_chars_to_number (buf, INSN_SIZE);
22583
22584 /* If the addend is negative, clear bit 23 of the instruction.
22585 Otherwise set it. */
22586 if (value < 0)
22587 insn &= ~(1 << 23);
22588 else
22589 insn |= 1 << 23;
22590
22591 /* Place the absolute value of the addend into the first 12 bits
22592 of the instruction. */
22593 insn &= 0xfffff000;
22594 insn |= addend_abs;
22595
22596 /* Update the instruction. */
22597 md_number_to_chars (buf, insn, INSN_SIZE);
22598 }
4962c51a
MS		 22599 break;
22600
22601 case BFD_RELOC_ARM_LDRS_PC_G0:
22602 case BFD_RELOC_ARM_LDRS_PC_G1:
22603 case BFD_RELOC_ARM_LDRS_PC_G2:
22604 case BFD_RELOC_ARM_LDRS_SB_G0:
22605 case BFD_RELOC_ARM_LDRS_SB_G1:
22606 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 22607 gas_assert (!fixP->fx_done);
4962c51a 22608 if (!seg->use_rela_p)
477330fc
RM		 22609 {
22610 bfd_vma insn;
22611 bfd_vma addend_abs = abs (value);
4962c51a 22612
477330fc
RM		 22613 /* Check that the absolute value of the addend can be
22614 encoded in 8 bits. */
22615 if (addend_abs >= 0x100)
4962c51a 22616 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 22617 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22618 (unsigned long) addend_abs);
22619
22620 /* Extract the instruction. */
22621 insn = md_chars_to_number (buf, INSN_SIZE);
22622
22623 /* If the addend is negative, clear bit 23 of the instruction.
22624 Otherwise set it. */
22625 if (value < 0)
22626 insn &= ~(1 << 23);
22627 else
22628 insn |= 1 << 23;
22629
22630 /* Place the first four bits of the absolute value of the addend
22631 into the first 4 bits of the instruction, and the remaining
22632 four into bits 8 .. 11. */
22633 insn &= 0xfffff0f0;
22634 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
22635
22636 /* Update the instruction. */
22637 md_number_to_chars (buf, insn, INSN_SIZE);
22638 }
4962c51a
MS		 22639 break;
22640
22641 case BFD_RELOC_ARM_LDC_PC_G0:
22642 case BFD_RELOC_ARM_LDC_PC_G1:
22643 case BFD_RELOC_ARM_LDC_PC_G2:
22644 case BFD_RELOC_ARM_LDC_SB_G0:
22645 case BFD_RELOC_ARM_LDC_SB_G1:
22646 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 22647 gas_assert (!fixP->fx_done);
4962c51a 22648 if (!seg->use_rela_p)
477330fc
RM		 22649 {
22650 bfd_vma insn;
22651 bfd_vma addend_abs = abs (value);
4962c51a 22652
477330fc
RM		 22653 /* Check that the absolute value of the addend is a multiple of
22654 four and, when divided by four, fits in 8 bits. */
22655 if (addend_abs & 0x3)
4962c51a 22656 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 22657 _("bad offset 0x%08lX (must be word-aligned)"),
22658 (unsigned long) addend_abs);
4962c51a 22659
477330fc 22660 if ((addend_abs >> 2) > 0xff)
4962c51a 22661 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 22662 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22663 (unsigned long) addend_abs);
22664
22665 /* Extract the instruction. */
22666 insn = md_chars_to_number (buf, INSN_SIZE);
22667
22668 /* If the addend is negative, clear bit 23 of the instruction.
22669 Otherwise set it. */
22670 if (value < 0)
22671 insn &= ~(1 << 23);
22672 else
22673 insn |= 1 << 23;
22674
22675 /* Place the addend (divided by four) into the first eight
22676 bits of the instruction. */
22677 insn &= 0xfffffff0;
22678 insn |= addend_abs >> 2;
22679
22680 /* Update the instruction. */
22681 md_number_to_chars (buf, insn, INSN_SIZE);
22682 }
4962c51a
MS		 22683 break;
22684
845b51d6
PB		 22685 case BFD_RELOC_ARM_V4BX:
22686 /* This will need to go in the object file. */
22687 fixP->fx_done = 0;
22688 break;
22689
c19d1205
ZW		 22690 case BFD_RELOC_UNUSED:
22691 default:
22692 as_bad_where (fixP->fx_file, fixP->fx_line,
22693 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
22694 }
6c43fab6
RE		 22695}
22696
c19d1205
ZW		 22697/* Translate internal representation of relocation info to BFD target
22698 format. */
a737bd4d 22699
c19d1205 22700arelent *
00a97672 22701tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 22702{
c19d1205
ZW		 22703 arelent * reloc;
22704 bfd_reloc_code_real_type code;
a737bd4d 22705
21d799b5 22706 reloc = (arelent *) xmalloc (sizeof (arelent));
a737bd4d 22707
21d799b5 22708 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
c19d1205
ZW		 22709 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
22710 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 22711
2fc8bdac 22712 if (fixp->fx_pcrel)
00a97672
RS		 22713 {
22714 if (section->use_rela_p)
22715 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
22716 else
22717 fixp->fx_offset = reloc->address;
22718 }
c19d1205 22719 reloc->addend = fixp->fx_offset;
a737bd4d 22720
c19d1205 22721 switch (fixp->fx_r_type)
a737bd4d 22722 {
c19d1205
ZW		 22723 case BFD_RELOC_8:
22724 if (fixp->fx_pcrel)
22725 {
22726 code = BFD_RELOC_8_PCREL;
22727 break;
22728 }
a737bd4d 22729
c19d1205
ZW		 22730 case BFD_RELOC_16:
22731 if (fixp->fx_pcrel)
22732 {
22733 code = BFD_RELOC_16_PCREL;
22734 break;
22735 }
6c43fab6 22736
c19d1205
ZW		 22737 case BFD_RELOC_32:
22738 if (fixp->fx_pcrel)
22739 {
22740 code = BFD_RELOC_32_PCREL;
22741 break;
22742 }
a737bd4d 22743
b6895b4f
PB		 22744 case BFD_RELOC_ARM_MOVW:
22745 if (fixp->fx_pcrel)
22746 {
22747 code = BFD_RELOC_ARM_MOVW_PCREL;
22748 break;
22749 }
22750
22751 case BFD_RELOC_ARM_MOVT:
22752 if (fixp->fx_pcrel)
22753 {
22754 code = BFD_RELOC_ARM_MOVT_PCREL;
22755 break;
22756 }
22757
22758 case BFD_RELOC_ARM_THUMB_MOVW:
22759 if (fixp->fx_pcrel)
22760 {
22761 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
22762 break;
22763 }
22764
22765 case BFD_RELOC_ARM_THUMB_MOVT:
22766 if (fixp->fx_pcrel)
22767 {
22768 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
22769 break;
22770 }
22771
c19d1205
ZW		 22772 case BFD_RELOC_NONE:
22773 case BFD_RELOC_ARM_PCREL_BRANCH:
22774 case BFD_RELOC_ARM_PCREL_BLX:
22775 case BFD_RELOC_RVA:
22776 case BFD_RELOC_THUMB_PCREL_BRANCH7:
22777 case BFD_RELOC_THUMB_PCREL_BRANCH9:
22778 case BFD_RELOC_THUMB_PCREL_BRANCH12:
22779 case BFD_RELOC_THUMB_PCREL_BRANCH20:
22780 case BFD_RELOC_THUMB_PCREL_BRANCH23:
22781 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW		 22782 case BFD_RELOC_VTABLE_ENTRY:
22783 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC		 22784#ifdef TE_PE
22785 case BFD_RELOC_32_SECREL:
22786#endif
c19d1205
ZW		 22787 code = fixp->fx_r_type;
22788 break;
a737bd4d 22789
00adf2d4
JB		 22790 case BFD_RELOC_THUMB_PCREL_BLX:
22791#ifdef OBJ_ELF
22792 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
22793 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
22794 else
22795#endif
22796 code = BFD_RELOC_THUMB_PCREL_BLX;
22797 break;
22798
c19d1205
ZW		 22799 case BFD_RELOC_ARM_LITERAL:
22800 case BFD_RELOC_ARM_HWLITERAL:
22801 /* If this is called then the a literal has
22802 been referenced across a section boundary. */
22803 as_bad_where (fixp->fx_file, fixp->fx_line,
22804 _("literal referenced across section boundary"));
22805 return NULL;
a737bd4d 22806
c19d1205 22807#ifdef OBJ_ELF
0855e32b
NS		 22808 case BFD_RELOC_ARM_TLS_CALL:
22809 case BFD_RELOC_ARM_THM_TLS_CALL:
22810 case BFD_RELOC_ARM_TLS_DESCSEQ:
22811 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW		 22812 case BFD_RELOC_ARM_GOT32:
22813 case BFD_RELOC_ARM_GOTOFF:
b43420e6 22814 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW		 22815 case BFD_RELOC_ARM_PLT32:
22816 case BFD_RELOC_ARM_TARGET1:
22817 case BFD_RELOC_ARM_ROSEGREL32:
22818 case BFD_RELOC_ARM_SBREL32:
22819 case BFD_RELOC_ARM_PREL31:
22820 case BFD_RELOC_ARM_TARGET2:
22821 case BFD_RELOC_ARM_TLS_LE32:
22822 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB		 22823 case BFD_RELOC_ARM_PCREL_CALL:
22824 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS		 22825 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22826 case BFD_RELOC_ARM_ALU_PC_G0:
22827 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22828 case BFD_RELOC_ARM_ALU_PC_G1:
22829 case BFD_RELOC_ARM_ALU_PC_G2:
22830 case BFD_RELOC_ARM_LDR_PC_G0:
22831 case BFD_RELOC_ARM_LDR_PC_G1:
22832 case BFD_RELOC_ARM_LDR_PC_G2:
22833 case BFD_RELOC_ARM_LDRS_PC_G0:
22834 case BFD_RELOC_ARM_LDRS_PC_G1:
22835 case BFD_RELOC_ARM_LDRS_PC_G2:
22836 case BFD_RELOC_ARM_LDC_PC_G0:
22837 case BFD_RELOC_ARM_LDC_PC_G1:
22838 case BFD_RELOC_ARM_LDC_PC_G2:
22839 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22840 case BFD_RELOC_ARM_ALU_SB_G0:
22841 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22842 case BFD_RELOC_ARM_ALU_SB_G1:
22843 case BFD_RELOC_ARM_ALU_SB_G2:
22844 case BFD_RELOC_ARM_LDR_SB_G0:
22845 case BFD_RELOC_ARM_LDR_SB_G1:
22846 case BFD_RELOC_ARM_LDR_SB_G2:
22847 case BFD_RELOC_ARM_LDRS_SB_G0:
22848 case BFD_RELOC_ARM_LDRS_SB_G1:
22849 case BFD_RELOC_ARM_LDRS_SB_G2:
22850 case BFD_RELOC_ARM_LDC_SB_G0:
22851 case BFD_RELOC_ARM_LDC_SB_G1:
22852 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 22853 case BFD_RELOC_ARM_V4BX:
c19d1205
ZW		 22854 code = fixp->fx_r_type;
22855 break;
a737bd4d 22856
0855e32b 22857 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 22858 case BFD_RELOC_ARM_TLS_GD32:
22859 case BFD_RELOC_ARM_TLS_IE32:
22860 case BFD_RELOC_ARM_TLS_LDM32:
22861 /* BFD will include the symbol's address in the addend.
22862 But we don't want that, so subtract it out again here. */
22863 if (!S_IS_COMMON (fixp->fx_addsy))
22864 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
22865 code = fixp->fx_r_type;
22866 break;
22867#endif
a737bd4d 22868
c19d1205
ZW		 22869 case BFD_RELOC_ARM_IMMEDIATE:
22870 as_bad_where (fixp->fx_file, fixp->fx_line,
22871 _("internal relocation (type: IMMEDIATE) not fixed up"));
22872 return NULL;
a737bd4d 22873
c19d1205
ZW		 22874 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22875 as_bad_where (fixp->fx_file, fixp->fx_line,
22876 _("ADRL used for a symbol not defined in the same file"));
22877 return NULL;
a737bd4d 22878
c19d1205 22879 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 22880 if (section->use_rela_p)
22881 {
22882 code = fixp->fx_r_type;
22883 break;
22884 }
22885
c19d1205
ZW		 22886 if (fixp->fx_addsy != NULL
22887 && !S_IS_DEFINED (fixp->fx_addsy)
22888 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 22889 {
c19d1205
ZW		 22890 as_bad_where (fixp->fx_file, fixp->fx_line,
22891 _("undefined local label `%s'"),
22892 S_GET_NAME (fixp->fx_addsy));
22893 return NULL;
a737bd4d
NC		 22894 }
22895
c19d1205
ZW		 22896 as_bad_where (fixp->fx_file, fixp->fx_line,
22897 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
22898 return NULL;
a737bd4d 22899
c19d1205
ZW		 22900 default:
22901 {
22902 char * type;
6c43fab6 22903
c19d1205
ZW		 22904 switch (fixp->fx_r_type)
22905 {
22906 case BFD_RELOC_NONE: type = "NONE"; break;
22907 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
22908 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 22909 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW		 22910 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
22911 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
22912 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 22913 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 22914 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW		 22915 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
22916 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
22917 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
22918 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
22919 default: type = _("<unknown>"); break;
22920 }
22921 as_bad_where (fixp->fx_file, fixp->fx_line,
22922 _("cannot represent %s relocation in this object file format"),
22923 type);
22924 return NULL;
22925 }
a737bd4d 22926 }
6c43fab6 22927
c19d1205
ZW		 22928#ifdef OBJ_ELF
22929 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
22930 && GOT_symbol
22931 && fixp->fx_addsy == GOT_symbol)
22932 {
22933 code = BFD_RELOC_ARM_GOTPC;
22934 reloc->addend = fixp->fx_offset = reloc->address;
22935 }
22936#endif
6c43fab6 22937
c19d1205 22938 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 22939
c19d1205
ZW		 22940 if (reloc->howto == NULL)
22941 {
22942 as_bad_where (fixp->fx_file, fixp->fx_line,
22943 _("cannot represent %s relocation in this object file format"),
22944 bfd_get_reloc_code_name (code));
22945 return NULL;
22946 }
6c43fab6 22947
c19d1205
ZW		 22948 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
22949 vtable entry to be used in the relocation's section offset. */
22950 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
22951 reloc->address = fixp->fx_offset;
6c43fab6 22952
c19d1205 22953 return reloc;
6c43fab6
RE		 22954}
22955
c19d1205 22956/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 22957
c19d1205
ZW		 22958void
22959cons_fix_new_arm (fragS * frag,
22960 int where,
22961 int size,
22962 expressionS * exp)
6c43fab6 22963{
c19d1205
ZW		 22964 bfd_reloc_code_real_type type;
22965 int pcrel = 0;
6c43fab6 22966
c19d1205
ZW		 22967 /* Pick a reloc.
22968 FIXME: @@ Should look at CPU word size. */
22969 switch (size)
22970 {
22971 case 1:
22972 type = BFD_RELOC_8;
22973 break;
22974 case 2:
22975 type = BFD_RELOC_16;
22976 break;
22977 case 4:
22978 default:
22979 type = BFD_RELOC_32;
22980 break;
22981 case 8:
22982 type = BFD_RELOC_64;
22983 break;
22984 }
6c43fab6 22985
f0927246
NC		 22986#ifdef TE_PE
22987 if (exp->X_op == O_secrel)
22988 {
22989 exp->X_op = O_symbol;
22990 type = BFD_RELOC_32_SECREL;
22991 }
22992#endif
22993
c19d1205
ZW		 22994 fix_new_exp (frag, where, (int) size, exp, pcrel, type);
22995}
6c43fab6 22996
4343666d 22997#if defined (OBJ_COFF)
c19d1205
ZW		 22998void
22999arm_validate_fix (fixS * fixP)
6c43fab6 23000{
c19d1205
ZW		 23001 /* If the destination of the branch is a defined symbol which does not have
23002 the THUMB_FUNC attribute, then we must be calling a function which has
23003 the (interfacearm) attribute. We look for the Thumb entry point to that
23004 function and change the branch to refer to that function instead. */
23005 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23006 && fixP->fx_addsy != NULL
23007 && S_IS_DEFINED (fixP->fx_addsy)
23008 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 23009 {
c19d1205 23010 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 23011 }
c19d1205
ZW		 23012}
23013#endif
6c43fab6 23014
267bf995 23015
c19d1205
ZW		 23016int
23017arm_force_relocation (struct fix * fixp)
23018{
23019#if defined (OBJ_COFF) && defined (TE_PE)
23020 if (fixp->fx_r_type == BFD_RELOC_RVA)
23021 return 1;
23022#endif
6c43fab6 23023
267bf995
RR		 23024 /* In case we have a call or a branch to a function in ARM ISA mode from
23025 a thumb function or vice-versa force the relocation. These relocations
23026 are cleared off for some cores that might have blx and simple transformations
23027 are possible. */
23028
23029#ifdef OBJ_ELF
23030 switch (fixp->fx_r_type)
23031 {
23032 case BFD_RELOC_ARM_PCREL_JUMP:
23033 case BFD_RELOC_ARM_PCREL_CALL:
23034 case BFD_RELOC_THUMB_PCREL_BLX:
23035 if (THUMB_IS_FUNC (fixp->fx_addsy))
23036 return 1;
23037 break;
23038
23039 case BFD_RELOC_ARM_PCREL_BLX:
23040 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23041 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23042 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23043 if (ARM_IS_FUNC (fixp->fx_addsy))
23044 return 1;
23045 break;
23046
23047 default:
23048 break;
23049 }
23050#endif
23051
b5884301
PB		 23052 /* Resolve these relocations even if the symbol is extern or weak.
23053 Technically this is probably wrong due to symbol preemption.
23054 In practice these relocations do not have enough range to be useful
23055 at dynamic link time, and some code (e.g. in the Linux kernel)
23056 expects these references to be resolved. */
c19d1205
ZW		 23057 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23058 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 23059 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 23060 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB		 23061 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23062 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23063 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 23064 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB		 23065 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23066 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB		 23067 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23068 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23069 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23070 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 23071 return 0;
a737bd4d 23072
4962c51a
MS		 23073 /* Always leave these relocations for the linker. */
23074 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23075 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23076 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23077 return 1;
23078
f0291e4c
PB		 23079 /* Always generate relocations against function symbols. */
23080 if (fixp->fx_r_type == BFD_RELOC_32
23081 && fixp->fx_addsy
23082 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23083 return 1;
23084
c19d1205 23085 return generic_force_reloc (fixp);
404ff6b5
AH		 23086}
23087
0ffdc86c 23088#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB		 23089/* Relocations against function names must be left unadjusted,
23090 so that the linker can use this information to generate interworking
23091 stubs. The MIPS version of this function
c19d1205
ZW		 23092 also prevents relocations that are mips-16 specific, but I do not
23093 know why it does this.
404ff6b5 23094
c19d1205
ZW		 23095 FIXME:
23096 There is one other problem that ought to be addressed here, but
23097 which currently is not: Taking the address of a label (rather
23098 than a function) and then later jumping to that address. Such
23099 addresses also ought to have their bottom bit set (assuming that
23100 they reside in Thumb code), but at the moment they will not. */
404ff6b5 23101
c19d1205
ZW		 23102bfd_boolean
23103arm_fix_adjustable (fixS * fixP)
404ff6b5 23104{
c19d1205
ZW		 23105 if (fixP->fx_addsy == NULL)
23106 return 1;
404ff6b5 23107
e28387c3
PB		 23108 /* Preserve relocations against symbols with function type. */
23109 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 23110 return FALSE;
e28387c3 23111
c19d1205
ZW		 23112 if (THUMB_IS_FUNC (fixP->fx_addsy)
23113 && fixP->fx_subsy == NULL)
c921be7d 23114 return FALSE;
a737bd4d 23115
c19d1205
ZW		 23116 /* We need the symbol name for the VTABLE entries. */
23117 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23118 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 23119 return FALSE;
404ff6b5 23120
c19d1205
ZW		 23121 /* Don't allow symbols to be discarded on GOT related relocs. */
23122 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23123 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23124 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23125 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23126 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23127 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23128 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23129 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS		 23130 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23131 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23132 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23133 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23134 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 23135 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 23136 return FALSE;
a737bd4d 23137
4962c51a
MS		 23138 /* Similarly for group relocations. */
23139 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23140 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23141 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 23142 return FALSE;
4962c51a 23143
79947c54
CD		 23144 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23145 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23146 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23147 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23148 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23149 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23150 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23151 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23152 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 23153 return FALSE;
79947c54 23154
c921be7d 23155 return TRUE;
a737bd4d 23156}
0ffdc86c
NC		 23157#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23158
23159#ifdef OBJ_ELF
404ff6b5 23160
c19d1205
ZW		 23161const char *
23162elf32_arm_target_format (void)
404ff6b5 23163{
c19d1205
ZW		 23164#ifdef TE_SYMBIAN
23165 return (target_big_endian
23166 ? "elf32-bigarm-symbian"
23167 : "elf32-littlearm-symbian");
23168#elif defined (TE_VXWORKS)
23169 return (target_big_endian
23170 ? "elf32-bigarm-vxworks"
23171 : "elf32-littlearm-vxworks");
b38cadfb
NC		 23172#elif defined (TE_NACL)
23173 return (target_big_endian
23174 ? "elf32-bigarm-nacl"
23175 : "elf32-littlearm-nacl");
c19d1205
ZW		 23176#else
23177 if (target_big_endian)
23178 return "elf32-bigarm";
23179 else
23180 return "elf32-littlearm";
23181#endif
404ff6b5
AH		 23182}
23183
c19d1205
ZW		 23184void
23185armelf_frob_symbol (symbolS * symp,
23186 int * puntp)
404ff6b5 23187{
c19d1205
ZW		 23188 elf_frob_symbol (symp, puntp);
23189}
23190#endif
404ff6b5 23191
c19d1205 23192/* MD interface: Finalization. */
a737bd4d 23193
c19d1205
ZW		 23194void
23195arm_cleanup (void)
23196{
23197 literal_pool * pool;
a737bd4d 23198
e07e6e58
NC		 23199 /* Ensure that all the IT blocks are properly closed. */
23200 check_it_blocks_finished ();
23201
c19d1205
ZW		 23202 for (pool = list_of_pools; pool; pool = pool->next)
23203 {
5f4273c7 23204 /* Put it at the end of the relevant section. */
c19d1205
ZW		 23205 subseg_set (pool->section, pool->sub_section);
23206#ifdef OBJ_ELF
23207 arm_elf_change_section ();
23208#endif
23209 s_ltorg (0);
23210 }
404ff6b5
AH		 23211}
23212
cd000bff
DJ		 23213#ifdef OBJ_ELF
23214/* Remove any excess mapping symbols generated for alignment frags in
23215 SEC. We may have created a mapping symbol before a zero byte
23216 alignment; remove it if there's a mapping symbol after the
23217 alignment. */
23218static void
23219check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23220 void *dummy ATTRIBUTE_UNUSED)
23221{
23222 segment_info_type *seginfo = seg_info (sec);
23223 fragS *fragp;
23224
23225 if (seginfo == NULL || seginfo->frchainP == NULL)
23226 return;
23227
23228 for (fragp = seginfo->frchainP->frch_root;
23229 fragp != NULL;
23230 fragp = fragp->fr_next)
23231 {
23232 symbolS *sym = fragp->tc_frag_data.last_map;
23233 fragS *next = fragp->fr_next;
23234
23235 /* Variable-sized frags have been converted to fixed size by
23236 this point. But if this was variable-sized to start with,
23237 there will be a fixed-size frag after it. So don't handle
23238 next == NULL. */
23239 if (sym == NULL || next == NULL)
23240 continue;
23241
23242 if (S_GET_VALUE (sym) < next->fr_address)
23243 /* Not at the end of this frag. */
23244 continue;
23245 know (S_GET_VALUE (sym) == next->fr_address);
23246
23247 do
23248 {
23249 if (next->tc_frag_data.first_map != NULL)
23250 {
23251 /* Next frag starts with a mapping symbol. Discard this
23252 one. */
23253 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23254 break;
23255 }
23256
23257 if (next->fr_next == NULL)
23258 {
23259 /* This mapping symbol is at the end of the section. Discard
23260 it. */
23261 know (next->fr_fix == 0 && next->fr_var == 0);
23262 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23263 break;
23264 }
23265
23266 /* As long as we have empty frags without any mapping symbols,
23267 keep looking. */
23268 /* If the next frag is non-empty and does not start with a
23269 mapping symbol, then this mapping symbol is required. */
23270 if (next->fr_address != next->fr_next->fr_address)
23271 break;
23272
23273 next = next->fr_next;
23274 }
23275 while (next != NULL);
23276 }
23277}
23278#endif
23279
c19d1205
ZW		 23280/* Adjust the symbol table. This marks Thumb symbols as distinct from
23281 ARM ones. */
404ff6b5 23282
c19d1205
ZW		 23283void
23284arm_adjust_symtab (void)
404ff6b5 23285{
c19d1205
ZW		 23286#ifdef OBJ_COFF
23287 symbolS * sym;
404ff6b5 23288
c19d1205
ZW		 23289 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23290 {
23291 if (ARM_IS_THUMB (sym))
23292 {
23293 if (THUMB_IS_FUNC (sym))
23294 {
23295 /* Mark the symbol as a Thumb function. */
23296 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23297 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23298 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 23299
c19d1205
ZW		 23300 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23301 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23302 else
23303 as_bad (_("%s: unexpected function type: %d"),
23304 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23305 }
23306 else switch (S_GET_STORAGE_CLASS (sym))
23307 {
23308 case C_EXT:
23309 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23310 break;
23311 case C_STAT:
23312 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23313 break;
23314 case C_LABEL:
23315 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23316 break;
23317 default:
23318 /* Do nothing. */
23319 break;
23320 }
23321 }
a737bd4d 23322
c19d1205
ZW		 23323 if (ARM_IS_INTERWORK (sym))
23324 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 23325 }
c19d1205
ZW		 23326#endif
23327#ifdef OBJ_ELF
23328 symbolS * sym;
23329 char bind;
404ff6b5 23330
c19d1205 23331 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 23332 {
c19d1205
ZW		 23333 if (ARM_IS_THUMB (sym))
23334 {
23335 elf_symbol_type * elf_sym;
404ff6b5 23336
c19d1205
ZW		 23337 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23338 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 23339
b0796911
PB		 23340 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23341 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW		 23342 {
23343 /* If it's a .thumb_func, declare it as so,
23344 otherwise tag label as .code 16. */
23345 if (THUMB_IS_FUNC (sym))
35fc36a8
RS		 23346 elf_sym->internal_elf_sym.st_target_internal
23347 = ST_BRANCH_TO_THUMB;
3ba67470 23348 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW		 23349 elf_sym->internal_elf_sym.st_info =
23350 ELF_ST_INFO (bind, STT_ARM_16BIT);
23351 }
23352 }
23353 }
cd000bff
DJ		 23354
23355 /* Remove any overlapping mapping symbols generated by alignment frags. */
23356 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM		 23357 /* Now do generic ELF adjustments. */
23358 elf_adjust_symtab ();
c19d1205 23359#endif
404ff6b5
AH		 23360}
23361
c19d1205 23362/* MD interface: Initialization. */
404ff6b5 23363
a737bd4d 23364static void
c19d1205 23365set_constant_flonums (void)
a737bd4d 23366{
c19d1205 23367 int i;
404ff6b5 23368
c19d1205
ZW		 23369 for (i = 0; i < NUM_FLOAT_VALS; i++)
23370 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23371 abort ();
a737bd4d 23372}
404ff6b5 23373
3e9e4fcf
JB		 23374/* Auto-select Thumb mode if it's the only available instruction set for the
23375 given architecture. */
23376
23377static void
23378autoselect_thumb_from_cpu_variant (void)
23379{
23380 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23381 opcode_select (16);
23382}
23383
c19d1205
ZW		 23384void
23385md_begin (void)
a737bd4d 23386{
c19d1205
ZW		 23387 unsigned mach;
23388 unsigned int i;
404ff6b5 23389
c19d1205
ZW		 23390 if ( (arm_ops_hsh = hash_new ()) == NULL
23391 || (arm_cond_hsh = hash_new ()) == NULL
23392 || (arm_shift_hsh = hash_new ()) == NULL
23393 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 23394 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 23395 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB		 23396 || (arm_reloc_hsh = hash_new ()) == NULL
23397 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW		 23398 as_fatal (_("virtual memory exhausted"));
23399
23400 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 23401 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 23402 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 23403 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
c19d1205 23404 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 23405 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 23406 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 23407 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 23408 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 23409 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 23410 (void *) (v7m_psrs + i));
c19d1205 23411 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 23412 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB		 23413 for (i = 0;
23414 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23415 i++)
d3ce72d0 23416 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 23417 (void *) (barrier_opt_names + i));
c19d1205 23418#ifdef OBJ_ELF
3da1d841
NC		 23419 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23420 {
23421 struct reloc_entry * entry = reloc_names + i;
23422
23423 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23424 /* This makes encode_branch() use the EABI versions of this relocation. */
23425 entry->reloc = BFD_RELOC_UNUSED;
23426
23427 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23428 }
c19d1205
ZW		 23429#endif
23430
23431 set_constant_flonums ();
404ff6b5 23432
c19d1205
ZW		 23433 /* Set the cpu variant based on the command-line options. We prefer
23434 -mcpu= over -march= if both are set (as for GCC); and we prefer
23435 -mfpu= over any other way of setting the floating point unit.
23436 Use of legacy options with new options are faulted. */
e74cfd16 23437 if (legacy_cpu)
404ff6b5 23438 {
e74cfd16 23439 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW		 23440 as_bad (_("use of old and new-style options to set CPU type"));
23441
23442 mcpu_cpu_opt = legacy_cpu;
404ff6b5 23443 }
e74cfd16 23444 else if (!mcpu_cpu_opt)
c19d1205 23445 mcpu_cpu_opt = march_cpu_opt;
404ff6b5 23446
e74cfd16 23447 if (legacy_fpu)
c19d1205 23448 {
e74cfd16 23449 if (mfpu_opt)
c19d1205 23450 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f
RE		 23451
23452 mfpu_opt = legacy_fpu;
23453 }
e74cfd16 23454 else if (!mfpu_opt)
03b1477f 23455 {
45eb4c1b
NS		 23456#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23457 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE		 23458 /* Some environments specify a default FPU. If they don't, infer it
23459 from the processor. */
e74cfd16 23460 if (mcpu_fpu_opt)
03b1477f
RE		 23461 mfpu_opt = mcpu_fpu_opt;
23462 else
23463 mfpu_opt = march_fpu_opt;
39c2da32 23464#else
e74cfd16 23465 mfpu_opt = &fpu_default;
39c2da32 23466#endif
03b1477f
RE		 23467 }
23468
e74cfd16 23469 if (!mfpu_opt)
03b1477f 23470 {
493cb6ef 23471 if (mcpu_cpu_opt != NULL)
e74cfd16 23472 mfpu_opt = &fpu_default;
493cb6ef 23473 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
e74cfd16 23474 mfpu_opt = &fpu_arch_vfp_v2;
03b1477f 23475 else
e74cfd16 23476 mfpu_opt = &fpu_arch_fpa;
03b1477f
RE		 23477 }
23478
ee065d83 23479#ifdef CPU_DEFAULT
e74cfd16 23480 if (!mcpu_cpu_opt)
ee065d83 23481 {
e74cfd16
PB		 23482 mcpu_cpu_opt = &cpu_default;
23483 selected_cpu = cpu_default;
ee065d83 23484 }
e74cfd16
PB		 23485#else
23486 if (mcpu_cpu_opt)
23487 selected_cpu = *mcpu_cpu_opt;
ee065d83 23488 else
e74cfd16 23489 mcpu_cpu_opt = &arm_arch_any;
ee065d83 23490#endif
03b1477f 23491
e74cfd16 23492 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
03b1477f 23493
3e9e4fcf
JB		 23494 autoselect_thumb_from_cpu_variant ();
23495
e74cfd16 23496 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 23497
f17c130b 23498#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 23499 {
7cc69913
NC		 23500 unsigned int flags = 0;
23501
23502#if defined OBJ_ELF
23503 flags = meabi_flags;
d507cf36
PB		 23504
23505 switch (meabi_flags)
33a392fb 23506 {
d507cf36 23507 case EF_ARM_EABI_UNKNOWN:
7cc69913 23508#endif
d507cf36
PB		 23509 /* Set the flags in the private structure. */
23510 if (uses_apcs_26) flags |= F_APCS26;
23511 if (support_interwork) flags |= F_INTERWORK;
23512 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 23513 if (pic_code) flags |= F_PIC;
e74cfd16 23514 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC		 23515 flags |= F_SOFT_FLOAT;
23516
d507cf36
PB		 23517 switch (mfloat_abi_opt)
23518 {
23519 case ARM_FLOAT_ABI_SOFT:
23520 case ARM_FLOAT_ABI_SOFTFP:
23521 flags |= F_SOFT_FLOAT;
23522 break;
33a392fb 23523
d507cf36
PB		 23524 case ARM_FLOAT_ABI_HARD:
23525 if (flags & F_SOFT_FLOAT)
23526 as_bad (_("hard-float conflicts with specified fpu"));
23527 break;
23528 }
03b1477f 23529
e74cfd16
PB		 23530 /* Using pure-endian doubles (even if soft-float). */
23531 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 23532 flags |= F_VFP_FLOAT;
f17c130b 23533
fde78edd 23534#if defined OBJ_ELF
e74cfd16 23535 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 23536 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB		 23537 break;
23538
8cb51566 23539 case EF_ARM_EABI_VER4:
3a4a14e9 23540 case EF_ARM_EABI_VER5:
c19d1205 23541 /* No additional flags to set. */
d507cf36
PB		 23542 break;
23543
23544 default:
23545 abort ();
23546 }
7cc69913 23547#endif
b99bd4ef
NC		 23548 bfd_set_private_flags (stdoutput, flags);
23549
23550 /* We have run out flags in the COFF header to encode the
23551 status of ATPCS support, so instead we create a dummy,
c19d1205 23552 empty, debug section called .arm.atpcs. */
b99bd4ef
NC		 23553 if (atpcs)
23554 {
23555 asection * sec;
23556
23557 sec = bfd_make_section (stdoutput, ".arm.atpcs");
23558
23559 if (sec != NULL)
23560 {
23561 bfd_set_section_flags
23562 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
23563 bfd_set_section_size (stdoutput, sec, 0);
23564 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
23565 }
23566 }
7cc69913 23567 }
f17c130b 23568#endif
b99bd4ef
NC		 23569
23570 /* Record the CPU type as well. */
2d447fca
JM		 23571 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
23572 mach = bfd_mach_arm_iWMMXt2;
23573 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 23574 mach = bfd_mach_arm_iWMMXt;
e74cfd16 23575 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 23576 mach = bfd_mach_arm_XScale;
e74cfd16 23577 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 23578 mach = bfd_mach_arm_ep9312;
e74cfd16 23579 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 23580 mach = bfd_mach_arm_5TE;
e74cfd16 23581 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 23582 {
e74cfd16 23583 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 23584 mach = bfd_mach_arm_5T;
23585 else
23586 mach = bfd_mach_arm_5;
23587 }
e74cfd16 23588 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 23589 {
e74cfd16 23590 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 23591 mach = bfd_mach_arm_4T;
23592 else
23593 mach = bfd_mach_arm_4;
23594 }
e74cfd16 23595 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 23596 mach = bfd_mach_arm_3M;
e74cfd16
PB		 23597 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
23598 mach = bfd_mach_arm_3;
23599 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
23600 mach = bfd_mach_arm_2a;
23601 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
23602 mach = bfd_mach_arm_2;
23603 else
23604 mach = bfd_mach_arm_unknown;
b99bd4ef
NC		 23605
23606 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
23607}
23608
c19d1205 23609/* Command line processing. */
b99bd4ef 23610
c19d1205
ZW		 23611/* md_parse_option
23612 Invocation line includes a switch not recognized by the base assembler.
23613 See if it's a processor-specific option.
b99bd4ef 23614
c19d1205
ZW		 23615 This routine is somewhat complicated by the need for backwards
23616 compatibility (since older releases of gcc can't be changed).
23617 The new options try to make the interface as compatible as
23618 possible with GCC.
b99bd4ef 23619
c19d1205 23620 New options (supported) are:
b99bd4ef 23621
c19d1205
ZW		 23622 -mcpu=<cpu name> Assemble for selected processor
23623 -march=<architecture name> Assemble for selected architecture
23624 -mfpu=<fpu architecture> Assemble for selected FPU.
23625 -EB/-mbig-endian Big-endian
23626 -EL/-mlittle-endian Little-endian
23627 -k Generate PIC code
23628 -mthumb Start in Thumb mode
23629 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 23630
278df34e 23631 -m[no-]warn-deprecated Warn about deprecated features
267bf995 23632
c19d1205 23633 For now we will also provide support for:
b99bd4ef 23634
c19d1205
ZW		 23635 -mapcs-32 32-bit Program counter
23636 -mapcs-26 26-bit Program counter
23637 -macps-float Floats passed in FP registers
23638 -mapcs-reentrant Reentrant code
23639 -matpcs
23640 (sometime these will probably be replaced with -mapcs=<list of options>
23641 and -matpcs=<list of options>)
b99bd4ef 23642
c19d1205
ZW		 23643 The remaining options are only supported for back-wards compatibility.
23644 Cpu variants, the arm part is optional:
23645 -m[arm]1 Currently not supported.
23646 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23647 -m[arm]3 Arm 3 processor
23648 -m[arm]6[xx], Arm 6 processors
23649 -m[arm]7[xx][t][[d]m] Arm 7 processors
23650 -m[arm]8[10] Arm 8 processors
23651 -m[arm]9[20][tdmi] Arm 9 processors
23652 -mstrongarm[110[0]] StrongARM processors
23653 -mxscale XScale processors
23654 -m[arm]v[2345[t[e]]] Arm architectures
23655 -mall All (except the ARM1)
23656 FP variants:
23657 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23658 -mfpe-old (No float load/store multiples)
23659 -mvfpxd VFP Single precision
23660 -mvfp All VFP
23661 -mno-fpu Disable all floating point instructions
b99bd4ef 23662
c19d1205
ZW		 23663 The following CPU names are recognized:
23664 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23665 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23666 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23667 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23668 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23669 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23670 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 23671
c19d1205 23672 */
b99bd4ef 23673
c19d1205 23674const char * md_shortopts = "m:k";
b99bd4ef 23675
c19d1205
ZW		 23676#ifdef ARM_BI_ENDIAN
23677#define OPTION_EB (OPTION_MD_BASE + 0)
23678#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 23679#else
c19d1205
ZW		 23680#if TARGET_BYTES_BIG_ENDIAN
23681#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 23682#else
c19d1205
ZW		 23683#define OPTION_EL (OPTION_MD_BASE + 1)
23684#endif
b99bd4ef 23685#endif
845b51d6 23686#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
b99bd4ef 23687
c19d1205 23688struct option md_longopts[] =
b99bd4ef 23689{
c19d1205
ZW		 23690#ifdef OPTION_EB
23691 {"EB", no_argument, NULL, OPTION_EB},
23692#endif
23693#ifdef OPTION_EL
23694 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 23695#endif
845b51d6 23696 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
c19d1205
ZW		 23697 {NULL, no_argument, NULL, 0}
23698};
b99bd4ef 23699
c19d1205 23700size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 23701
c19d1205 23702struct arm_option_table
b99bd4ef 23703{
c19d1205
ZW		 23704 char *option; /* Option name to match. */
23705 char *help; /* Help information. */
23706 int *var; /* Variable to change. */
23707 int value; /* What to change it to. */
23708 char *deprecated; /* If non-null, print this message. */
23709};
b99bd4ef 23710
c19d1205
ZW		 23711struct arm_option_table arm_opts[] =
23712{
23713 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
23714 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
23715 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23716 &support_interwork, 1, NULL},
23717 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
23718 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
23719 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
23720 1, NULL},
23721 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
23722 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
23723 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
23724 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
23725 NULL},
b99bd4ef 23726
c19d1205
ZW		 23727 /* These are recognized by the assembler, but have no affect on code. */
23728 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
23729 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS		 23730
23731 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
23732 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23733 &warn_on_deprecated, 0, NULL},
e74cfd16
PB		 23734 {NULL, NULL, NULL, 0, NULL}
23735};
23736
23737struct arm_legacy_option_table
23738{
23739 char *option; /* Option name to match. */
23740 const arm_feature_set **var; /* Variable to change. */
23741 const arm_feature_set value; /* What to change it to. */
23742 char *deprecated; /* If non-null, print this message. */
23743};
b99bd4ef 23744
e74cfd16
PB		 23745const struct arm_legacy_option_table arm_legacy_opts[] =
23746{
c19d1205
ZW		 23747 /* DON'T add any new processors to this list -- we want the whole list
23748 to go away... Add them to the processors table instead. */
e74cfd16
PB		 23749 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23750 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
23751 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23752 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
23753 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23754 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
23755 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23756 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
23757 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23758 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
23759 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23760 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
23761 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23762 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
23763 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23764 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
23765 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23766 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
23767 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23768 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
23769 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23770 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
23771 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23772 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
23773 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23774 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
23775 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23776 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
23777 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23778 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
23779 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23780 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
23781 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23782 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
23783 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23784 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
23785 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23786 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
23787 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23788 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
23789 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23790 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
23791 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23792 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
23793 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23794 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
23795 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23796 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23797 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23798 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
23799 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23800 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
23801 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23802 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
23803 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23804 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
23805 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23806 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
23807 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23808 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
23809 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23810 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
23811 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23812 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
23813 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23814 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
23815 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23816 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
23817 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
23818 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 23819 N_("use -mcpu=strongarm110")},
e74cfd16 23820 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 23821 N_("use -mcpu=strongarm1100")},
e74cfd16 23822 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 23823 N_("use -mcpu=strongarm1110")},
e74cfd16
PB		 23824 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
23825 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
23826 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 23827
c19d1205 23828 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB		 23829 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23830 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
23831 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23832 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
23833 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23834 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
23835 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23836 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
23837 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23838 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
23839 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23840 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
23841 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23842 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
23843 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23844 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
23845 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
23846 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 23847
c19d1205 23848 /* Floating point variants -- don't add any more to this list either. */
e74cfd16
PB		 23849 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
23850 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
23851 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
23852 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 23853 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 23854
e74cfd16 23855 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 23856};
7ed4c4c5 23857
c19d1205 23858struct arm_cpu_option_table
7ed4c4c5 23859{
c19d1205 23860 char *name;
f3bad469 23861 size_t name_len;
e74cfd16 23862 const arm_feature_set value;
c19d1205
ZW		 23863 /* For some CPUs we assume an FPU unless the user explicitly sets
23864 -mfpu=... */
e74cfd16 23865 const arm_feature_set default_fpu;
ee065d83
PB		 23866 /* The canonical name of the CPU, or NULL to use NAME converted to upper
23867 case. */
23868 const char *canonical_name;
c19d1205 23869};
7ed4c4c5 23870
c19d1205
ZW		 23871/* This list should, at a minimum, contain all the cpu names
23872 recognized by GCC. */
f3bad469 23873#define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
e74cfd16 23874static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 23875{
f3bad469
MGD		 23876 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
23877 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
23878 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
23879 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23880 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
23881 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23882 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23883 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23884 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23885 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23886 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23887 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23888 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23889 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23890 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23891 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
23892 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23893 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23894 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23895 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23896 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23897 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23898 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23899 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23900 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23901 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23902 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23903 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
23904 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23905 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23906 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23907 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23908 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23909 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23910 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23911 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23912 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23913 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23914 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23915 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
23916 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23917 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23918 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23919 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
23920 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
23921 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
c19d1205
ZW		 23922 /* For V5 or later processors we default to using VFP; but the user
23923 should really set the FPU type explicitly. */
f3bad469
MGD		 23924 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23925 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23926 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23927 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
23928 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23929 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23930 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
23931 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23932 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
23933 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
23934 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23935 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23936 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23937 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23938 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23939 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
23940 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
23941 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23942 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23943 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
23944 "ARM1026EJ-S"),
23945 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
23946 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23947 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23948 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23949 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23950 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
23951 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
23952 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
23953 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
23954 "ARM1136JF-S"),
23955 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
23956 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
23957 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
23958 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
23959 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
23960 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
23961 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
23962 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
23963 FPU_NONE, "Cortex-A5"),
23964 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23965 FPU_ARCH_NEON_VFP_V4,
23966 "Cortex-A7"),
23967 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
23968 ARM_FEATURE (0, FPU_VFP_V3
477330fc 23969 | FPU_NEON_EXT_V1),
f3bad469
MGD		 23970 "Cortex-A8"),
23971 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
23972 ARM_FEATURE (0, FPU_VFP_V3
477330fc 23973 | FPU_NEON_EXT_V1),
f3bad469 23974 "Cortex-A9"),
63a4bc21
KT		 23975 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23976 FPU_ARCH_NEON_VFP_V4,
23977 "Cortex-A12"),
f3bad469
MGD		 23978 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT,
23979 FPU_ARCH_NEON_VFP_V4,
23980 "Cortex-A15"),
92eb40d9 23981 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
477330fc 23982 "Cortex-A53"),
92eb40d9 23983 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
477330fc 23984 "Cortex-A57"),
f3bad469
MGD		 23985 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
23986 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
23987 "Cortex-R4F"),
23988 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
23989 FPU_NONE, "Cortex-R5"),
70a8bc5b 23990 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
23991 FPU_ARCH_VFP_V3D16,
23992 "Cortex-R7"),
f3bad469
MGD		 23993 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
23994 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
23995 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
23996 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
ce32bd10 23997 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
c19d1205 23998 /* ??? XSCALE is really an architecture. */
f3bad469 23999 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
c19d1205 24000 /* ??? iwmmxt is not a processor. */
f3bad469
MGD		 24001 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24002 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24003 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
c19d1205 24004 /* Maverick */
f3bad469 24005 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
da4339ed
NC		 24006 FPU_ARCH_MAVERICK, "ARM920T"),
24007 /* Marvell processors. */
4a81b02a 24008 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
477330fc 24009 FPU_ARCH_VFP_V3D16, NULL),
da4339ed 24010
f3bad469 24011 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 24012};
f3bad469 24013#undef ARM_CPU_OPT
7ed4c4c5 24014
c19d1205 24015struct arm_arch_option_table
7ed4c4c5 24016{
c19d1205 24017 char *name;
f3bad469 24018 size_t name_len;
e74cfd16
PB		 24019 const arm_feature_set value;
24020 const arm_feature_set default_fpu;
c19d1205 24021};
7ed4c4c5 24022
c19d1205
ZW		 24023/* This list should, at a minimum, contain all the architecture names
24024 recognized by GCC. */
f3bad469 24025#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
e74cfd16 24026static const struct arm_arch_option_table arm_archs[] =
c19d1205 24027{
f3bad469
MGD		 24028 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24029 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24030 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24031 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24032 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24033 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24034 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24035 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24036 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24037 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24038 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24039 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24040 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24041 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24042 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24043 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24044 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24045 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24046 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24047 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24048 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24049 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24050 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24051 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24052 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24053 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24054 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24055 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24056 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
c450d570
PB		 24057 /* The official spelling of the ARMv7 profile variants is the dashed form.
24058 Accept the non-dashed form for compatibility with old toolchains. */
f3bad469
MGD		 24059 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24060 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24061 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24062 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24063 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24064 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24065 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
bca38921 24066 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
f3bad469
MGD		 24067 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24068 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24069 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24070 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 24071};
f3bad469 24072#undef ARM_ARCH_OPT
7ed4c4c5 24073
69133863
MGD		 24074/* ISA extensions in the co-processor and main instruction set space. */
24075struct arm_option_extension_value_table
c19d1205
ZW		 24076{
24077 char *name;
f3bad469 24078 size_t name_len;
e74cfd16 24079 const arm_feature_set value;
69133863 24080 const arm_feature_set allowed_archs;
c19d1205 24081};
7ed4c4c5 24082
69133863
MGD		 24083/* The following table must be in alphabetical order with a NULL last entry.
24084 */
f3bad469 24085#define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
69133863 24086static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 24087{
dd5181d5 24088 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (ARM_EXT_V8, 0)),
bca38921
MGD		 24089 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24090 ARM_FEATURE (ARM_EXT_V8, 0)),
24091 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8,
24092 ARM_FEATURE (ARM_EXT_V8, 0)),
f3bad469
MGD		 24093 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
24094 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
24095 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24096 ARM_EXT_OPT ("iwmmxt2",
24097 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24098 ARM_EXT_OPT ("maverick",
477330fc 24099 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
f3bad469
MGD		 24100 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
24101 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
bca38921
MGD		 24102 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
24103 ARM_FEATURE (ARM_EXT_V8, 0)),
f3bad469
MGD		 24104 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
24105 ARM_FEATURE (ARM_EXT_V6M, 0)),
24106 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
24107 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24108 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24109 | ARM_EXT_DIV, 0),
24110 ARM_FEATURE (ARM_EXT_V7A, 0)),
24111 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24112 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
69133863 24113};
f3bad469 24114#undef ARM_EXT_OPT
69133863
MGD		 24115
24116/* ISA floating-point and Advanced SIMD extensions. */
24117struct arm_option_fpu_value_table
24118{
24119 char *name;
24120 const arm_feature_set value;
c19d1205 24121};
7ed4c4c5 24122
c19d1205
ZW		 24123/* This list should, at a minimum, contain all the fpu names
24124 recognized by GCC. */
69133863 24125static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW		 24126{
24127 {"softfpa", FPU_NONE},
24128 {"fpe", FPU_ARCH_FPE},
24129 {"fpe2", FPU_ARCH_FPE},
24130 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24131 {"fpa", FPU_ARCH_FPA},
24132 {"fpa10", FPU_ARCH_FPA},
24133 {"fpa11", FPU_ARCH_FPA},
24134 {"arm7500fe", FPU_ARCH_FPA},
24135 {"softvfp", FPU_ARCH_VFP},
24136 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24137 {"vfp", FPU_ARCH_VFP_V2},
24138 {"vfp9", FPU_ARCH_VFP_V2},
b1cc4aeb 24139 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
c19d1205
ZW		 24140 {"vfp10", FPU_ARCH_VFP_V2},
24141 {"vfp10-r0", FPU_ARCH_VFP_V1},
24142 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB		 24143 {"vfpv2", FPU_ARCH_VFP_V2},
24144 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 24145 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 24146 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB		 24147 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24148 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24149 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW		 24150 {"arm1020t", FPU_ARCH_VFP_V1},
24151 {"arm1020e", FPU_ARCH_VFP_V2},
24152 {"arm1136jfs", FPU_ARCH_VFP_V2},
24153 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24154 {"maverick", FPU_ARCH_MAVERICK},
5287ad62 24155 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 24156 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB		 24157 {"vfpv4", FPU_ARCH_VFP_V4},
24158 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 24159 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
62f3b8c8 24160 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD		 24161 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24162 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24163 {"crypto-neon-fp-armv8",
24164 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
e74cfd16
PB		 24165 {NULL, ARM_ARCH_NONE}
24166};
24167
24168struct arm_option_value_table
24169{
24170 char *name;
24171 long value;
c19d1205 24172};
7ed4c4c5 24173
e74cfd16 24174static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW		 24175{
24176 {"hard", ARM_FLOAT_ABI_HARD},
24177 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24178 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 24179 {NULL, 0}
c19d1205 24180};
7ed4c4c5 24181
c19d1205 24182#ifdef OBJ_ELF
3a4a14e9 24183/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 24184static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW		 24185{
24186 {"gnu", EF_ARM_EABI_UNKNOWN},
24187 {"4", EF_ARM_EABI_VER4},
3a4a14e9 24188 {"5", EF_ARM_EABI_VER5},
e74cfd16 24189 {NULL, 0}
c19d1205
ZW		 24190};
24191#endif
7ed4c4c5 24192
c19d1205
ZW		 24193struct arm_long_option_table
24194{
24195 char * option; /* Substring to match. */
24196 char * help; /* Help information. */
24197 int (* func) (char * subopt); /* Function to decode sub-option. */
24198 char * deprecated; /* If non-null, print this message. */
24199};
7ed4c4c5 24200
c921be7d 24201static bfd_boolean
f3bad469 24202arm_parse_extension (char *str, const arm_feature_set **opt_p)
7ed4c4c5 24203{
21d799b5
NC		 24204 arm_feature_set *ext_set = (arm_feature_set *)
24205 xmalloc (sizeof (arm_feature_set));
e74cfd16 24206
69133863 24207 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM		 24208 extensions being added before being removed. We achieve this by having
24209 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 24210 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 24211 or removing it (0) and only allowing it to change in the order
69133863
MGD		 24212 -1 -> 1 -> 0. */
24213 const struct arm_option_extension_value_table * opt = NULL;
24214 int adding_value = -1;
24215
e74cfd16
PB		 24216 /* Copy the feature set, so that we can modify it. */
24217 *ext_set = **opt_p;
24218 *opt_p = ext_set;
24219
c19d1205 24220 while (str != NULL && *str != 0)
7ed4c4c5 24221 {
f3bad469
MGD		 24222 char *ext;
24223 size_t len;
7ed4c4c5 24224
c19d1205
ZW		 24225 if (*str != '+')
24226 {
24227 as_bad (_("invalid architectural extension"));
c921be7d 24228 return FALSE;
c19d1205 24229 }
7ed4c4c5 24230
c19d1205
ZW		 24231 str++;
24232 ext = strchr (str, '+');
7ed4c4c5 24233
c19d1205 24234 if (ext != NULL)
f3bad469 24235 len = ext - str;
c19d1205 24236 else
f3bad469 24237 len = strlen (str);
7ed4c4c5 24238
f3bad469 24239 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD		 24240 {
24241 if (adding_value != 0)
24242 {
24243 adding_value = 0;
24244 opt = arm_extensions;
24245 }
24246
f3bad469 24247 len -= 2;
69133863
MGD		 24248 str += 2;
24249 }
f3bad469 24250 else if (len > 0)
69133863
MGD		 24251 {
24252 if (adding_value == -1)
24253 {
24254 adding_value = 1;
24255 opt = arm_extensions;
24256 }
24257 else if (adding_value != 1)
24258 {
24259 as_bad (_("must specify extensions to add before specifying "
24260 "those to remove"));
24261 return FALSE;
24262 }
24263 }
24264
f3bad469 24265 if (len == 0)
c19d1205
ZW		 24266 {
24267 as_bad (_("missing architectural extension"));
c921be7d 24268 return FALSE;
c19d1205 24269 }
7ed4c4c5 24270
69133863
MGD		 24271 gas_assert (adding_value != -1);
24272 gas_assert (opt != NULL);
24273
24274 /* Scan over the options table trying to find an exact match. */
24275 for (; opt->name != NULL; opt++)
f3bad469 24276 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24277 {
69133863
MGD		 24278 /* Check we can apply the extension to this architecture. */
24279 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24280 {
24281 as_bad (_("extension does not apply to the base architecture"));
24282 return FALSE;
24283 }
24284
24285 /* Add or remove the extension. */
24286 if (adding_value)
24287 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->value);
24288 else
24289 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->value);
24290
c19d1205
ZW		 24291 break;
24292 }
7ed4c4c5 24293
c19d1205
ZW		 24294 if (opt->name == NULL)
24295 {
69133863
MGD		 24296 /* Did we fail to find an extension because it wasn't specified in
24297 alphabetical order, or because it does not exist? */
24298
24299 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 24300 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD		 24301 break;
24302
24303 if (opt->name == NULL)
24304 as_bad (_("unknown architectural extension `%s'"), str);
24305 else
24306 as_bad (_("architectural extensions must be specified in "
24307 "alphabetical order"));
24308
c921be7d 24309 return FALSE;
c19d1205 24310 }
69133863
MGD		 24311 else
24312 {
24313 /* We should skip the extension we've just matched the next time
24314 round. */
24315 opt++;
24316 }
7ed4c4c5 24317
c19d1205
ZW		 24318 str = ext;
24319 };
7ed4c4c5 24320
c921be7d 24321 return TRUE;
c19d1205 24322}
7ed4c4c5 24323
c921be7d 24324static bfd_boolean
f3bad469 24325arm_parse_cpu (char *str)
7ed4c4c5 24326{
f3bad469
MGD		 24327 const struct arm_cpu_option_table *opt;
24328 char *ext = strchr (str, '+');
24329 size_t len;
7ed4c4c5 24330
c19d1205 24331 if (ext != NULL)
f3bad469 24332 len = ext - str;
7ed4c4c5 24333 else
f3bad469 24334 len = strlen (str);
7ed4c4c5 24335
f3bad469 24336 if (len == 0)
7ed4c4c5 24337 {
c19d1205 24338 as_bad (_("missing cpu name `%s'"), str);
c921be7d 24339 return FALSE;
7ed4c4c5
NC		 24340 }
24341
c19d1205 24342 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 24343 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24344 {
e74cfd16
PB		 24345 mcpu_cpu_opt = &opt->value;
24346 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 24347 if (opt->canonical_name)
5f4273c7 24348 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 24349 else
24350 {
f3bad469 24351 size_t i;
c921be7d 24352
f3bad469 24353 for (i = 0; i < len; i++)
ee065d83
PB		 24354 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24355 selected_cpu_name[i] = 0;
24356 }
7ed4c4c5 24357
c19d1205
ZW		 24358 if (ext != NULL)
24359 return arm_parse_extension (ext, &mcpu_cpu_opt);
7ed4c4c5 24360
c921be7d 24361 return TRUE;
c19d1205 24362 }
7ed4c4c5 24363
c19d1205 24364 as_bad (_("unknown cpu `%s'"), str);
c921be7d 24365 return FALSE;
7ed4c4c5
NC		 24366}
24367
c921be7d 24368static bfd_boolean
f3bad469 24369arm_parse_arch (char *str)
7ed4c4c5 24370{
e74cfd16 24371 const struct arm_arch_option_table *opt;
c19d1205 24372 char *ext = strchr (str, '+');
f3bad469 24373 size_t len;
7ed4c4c5 24374
c19d1205 24375 if (ext != NULL)
f3bad469 24376 len = ext - str;
7ed4c4c5 24377 else
f3bad469 24378 len = strlen (str);
7ed4c4c5 24379
f3bad469 24380 if (len == 0)
7ed4c4c5 24381 {
c19d1205 24382 as_bad (_("missing architecture name `%s'"), str);
c921be7d 24383 return FALSE;
7ed4c4c5
NC		 24384 }
24385
c19d1205 24386 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 24387 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24388 {
e74cfd16
PB		 24389 march_cpu_opt = &opt->value;
24390 march_fpu_opt = &opt->default_fpu;
5f4273c7 24391 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 24392
c19d1205
ZW		 24393 if (ext != NULL)
24394 return arm_parse_extension (ext, &march_cpu_opt);
7ed4c4c5 24395
c921be7d 24396 return TRUE;
c19d1205
ZW		 24397 }
24398
24399 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 24400 return FALSE;
7ed4c4c5 24401}
eb043451 24402
c921be7d 24403static bfd_boolean
c19d1205
ZW		 24404arm_parse_fpu (char * str)
24405{
69133863 24406 const struct arm_option_fpu_value_table * opt;
b99bd4ef 24407
c19d1205
ZW		 24408 for (opt = arm_fpus; opt->name != NULL; opt++)
24409 if (streq (opt->name, str))
24410 {
e74cfd16 24411 mfpu_opt = &opt->value;
c921be7d 24412 return TRUE;
c19d1205 24413 }
b99bd4ef 24414
c19d1205 24415 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 24416 return FALSE;
c19d1205
ZW		 24417}
24418
c921be7d 24419static bfd_boolean
c19d1205 24420arm_parse_float_abi (char * str)
b99bd4ef 24421{
e74cfd16 24422 const struct arm_option_value_table * opt;
b99bd4ef 24423
c19d1205
ZW		 24424 for (opt = arm_float_abis; opt->name != NULL; opt++)
24425 if (streq (opt->name, str))
24426 {
24427 mfloat_abi_opt = opt->value;
c921be7d 24428 return TRUE;
c19d1205 24429 }
cc8a6dd0 24430
c19d1205 24431 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 24432 return FALSE;
c19d1205 24433}
b99bd4ef 24434
c19d1205 24435#ifdef OBJ_ELF
c921be7d 24436static bfd_boolean
c19d1205
ZW		 24437arm_parse_eabi (char * str)
24438{
e74cfd16 24439 const struct arm_option_value_table *opt;
cc8a6dd0 24440
c19d1205
ZW		 24441 for (opt = arm_eabis; opt->name != NULL; opt++)
24442 if (streq (opt->name, str))
24443 {
24444 meabi_flags = opt->value;
c921be7d 24445 return TRUE;
c19d1205
ZW		 24446 }
24447 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 24448 return FALSE;
c19d1205
ZW		 24449}
24450#endif
cc8a6dd0 24451
c921be7d 24452static bfd_boolean
e07e6e58
NC		 24453arm_parse_it_mode (char * str)
24454{
c921be7d 24455 bfd_boolean ret = TRUE;
e07e6e58
NC		 24456
24457 if (streq ("arm", str))
24458 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24459 else if (streq ("thumb", str))
24460 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24461 else if (streq ("always", str))
24462 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24463 else if (streq ("never", str))
24464 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24465 else
24466 {
24467 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 24468 "arm, thumb, always, or never."), str);
c921be7d 24469 ret = FALSE;
e07e6e58
NC		 24470 }
24471
24472 return ret;
24473}
24474
c19d1205
ZW		 24475struct arm_long_option_table arm_long_opts[] =
24476{
24477 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24478 arm_parse_cpu, NULL},
24479 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24480 arm_parse_arch, NULL},
24481 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24482 arm_parse_fpu, NULL},
24483 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24484 arm_parse_float_abi, NULL},
24485#ifdef OBJ_ELF
7fac0536 24486 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW		 24487 arm_parse_eabi, NULL},
24488#endif
e07e6e58
NC		 24489 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24490 arm_parse_it_mode, NULL},
c19d1205
ZW		 24491 {NULL, NULL, 0, NULL}
24492};
cc8a6dd0 24493
c19d1205
ZW		 24494int
24495md_parse_option (int c, char * arg)
24496{
24497 struct arm_option_table *opt;
e74cfd16 24498 const struct arm_legacy_option_table *fopt;
c19d1205 24499 struct arm_long_option_table *lopt;
b99bd4ef 24500
c19d1205 24501 switch (c)
b99bd4ef 24502 {
c19d1205
ZW		 24503#ifdef OPTION_EB
24504 case OPTION_EB:
24505 target_big_endian = 1;
24506 break;
24507#endif
cc8a6dd0 24508
c19d1205
ZW		 24509#ifdef OPTION_EL
24510 case OPTION_EL:
24511 target_big_endian = 0;
24512 break;
24513#endif
b99bd4ef 24514
845b51d6
PB		 24515 case OPTION_FIX_V4BX:
24516 fix_v4bx = TRUE;
24517 break;
24518
c19d1205
ZW		 24519 case 'a':
24520 /* Listing option. Just ignore these, we don't support additional
24521 ones. */
24522 return 0;
b99bd4ef 24523
c19d1205
ZW		 24524 default:
24525 for (opt = arm_opts; opt->option != NULL; opt++)
24526 {
24527 if (c == opt->option[0]
24528 && ((arg == NULL && opt->option[1] == 0)
24529 || streq (arg, opt->option + 1)))
24530 {
c19d1205 24531 /* If the option is deprecated, tell the user. */
278df34e 24532 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW		 24533 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24534 arg ? arg : "", _(opt->deprecated));
b99bd4ef 24535
c19d1205
ZW		 24536 if (opt->var != NULL)
24537 *opt->var = opt->value;
cc8a6dd0 24538
c19d1205
ZW		 24539 return 1;
24540 }
24541 }
b99bd4ef 24542
e74cfd16
PB		 24543 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
24544 {
24545 if (c == fopt->option[0]
24546 && ((arg == NULL && fopt->option[1] == 0)
24547 || streq (arg, fopt->option + 1)))
24548 {
e74cfd16 24549 /* If the option is deprecated, tell the user. */
278df34e 24550 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB		 24551 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
24552 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB		 24553
24554 if (fopt->var != NULL)
24555 *fopt->var = &fopt->value;
24556
24557 return 1;
24558 }
24559 }
24560
c19d1205
ZW		 24561 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24562 {
24563 /* These options are expected to have an argument. */
24564 if (c == lopt->option[0]
24565 && arg != NULL
24566 && strncmp (arg, lopt->option + 1,
24567 strlen (lopt->option + 1)) == 0)
24568 {
c19d1205 24569 /* If the option is deprecated, tell the user. */
278df34e 24570 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW		 24571 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
24572 _(lopt->deprecated));
b99bd4ef 24573
c19d1205
ZW		 24574 /* Call the sup-option parser. */
24575 return lopt->func (arg + strlen (lopt->option) - 1);
24576 }
24577 }
a737bd4d 24578
c19d1205
ZW		 24579 return 0;
24580 }
a394c00f 24581
c19d1205
ZW		 24582 return 1;
24583}
a394c00f 24584
c19d1205
ZW		 24585void
24586md_show_usage (FILE * fp)
a394c00f 24587{
c19d1205
ZW		 24588 struct arm_option_table *opt;
24589 struct arm_long_option_table *lopt;
a394c00f 24590
c19d1205 24591 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 24592
c19d1205
ZW		 24593 for (opt = arm_opts; opt->option != NULL; opt++)
24594 if (opt->help != NULL)
24595 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 24596
c19d1205
ZW		 24597 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
24598 if (lopt->help != NULL)
24599 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 24600
c19d1205
ZW		 24601#ifdef OPTION_EB
24602 fprintf (fp, _("\
24603 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC		 24604#endif
24605
c19d1205
ZW		 24606#ifdef OPTION_EL
24607 fprintf (fp, _("\
24608 -EL assemble code for a little-endian cpu\n"));
a737bd4d 24609#endif
845b51d6
PB		 24610
24611 fprintf (fp, _("\
24612 --fix-v4bx Allow BX in ARMv4 code\n"));
c19d1205 24613}
ee065d83
PB		 24614
24615
24616#ifdef OBJ_ELF
62b3e311
PB		 24617typedef struct
24618{
24619 int val;
24620 arm_feature_set flags;
24621} cpu_arch_ver_table;
24622
24623/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24624 least features first. */
24625static const cpu_arch_ver_table cpu_arch_ver[] =
24626{
24627 {1, ARM_ARCH_V4},
24628 {2, ARM_ARCH_V4T},
24629 {3, ARM_ARCH_V5},
ee3c0378 24630 {3, ARM_ARCH_V5T},
62b3e311
PB		 24631 {4, ARM_ARCH_V5TE},
24632 {5, ARM_ARCH_V5TEJ},
24633 {6, ARM_ARCH_V6},
7e806470 24634 {9, ARM_ARCH_V6K},
f4c65163 24635 {7, ARM_ARCH_V6Z},
91e22acd 24636 {11, ARM_ARCH_V6M},
b2a5fbdc 24637 {12, ARM_ARCH_V6SM},
7e806470 24638 {8, ARM_ARCH_V6T2},
bca38921 24639 {10, ARM_ARCH_V7A_IDIV_MP_SEC_VIRT},
62b3e311
PB		 24640 {10, ARM_ARCH_V7R},
24641 {10, ARM_ARCH_V7M},
bca38921 24642 {14, ARM_ARCH_V8A},
62b3e311
PB		 24643 {0, ARM_ARCH_NONE}
24644};
24645
ee3c0378
AS		 24646/* Set an attribute if it has not already been set by the user. */
24647static void
24648aeabi_set_attribute_int (int tag, int value)
24649{
24650 if (tag < 1
24651 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24652 || !attributes_set_explicitly[tag])
24653 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
24654}
24655
24656static void
24657aeabi_set_attribute_string (int tag, const char *value)
24658{
24659 if (tag < 1
24660 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
24661 || !attributes_set_explicitly[tag])
24662 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
24663}
24664
ee065d83
PB		 24665/* Set the public EABI object attributes. */
24666static void
24667aeabi_set_public_attributes (void)
24668{
24669 int arch;
69239280 24670 char profile;
90ec0d68 24671 int virt_sec = 0;
bca38921 24672 int fp16_optional = 0;
e74cfd16 24673 arm_feature_set flags;
62b3e311
PB		 24674 arm_feature_set tmp;
24675 const cpu_arch_ver_table *p;
ee065d83
PB		 24676
24677 /* Choose the architecture based on the capabilities of the requested cpu
24678 (if any) and/or the instructions actually used. */
e74cfd16
PB		 24679 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
24680 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
24681 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
ddd7f988
RE		 24682
24683 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
24684 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
24685
24686 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
24687 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
24688
24689 /* Allow the user to override the reported architecture. */
7a1d4c38
PB		 24690 if (object_arch)
24691 {
24692 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
24693 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
24694 }
24695
251665fc
MGD		 24696 /* We need to make sure that the attributes do not identify us as v6S-M
24697 when the only v6S-M feature in use is the Operating System Extensions. */
24698 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
24699 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
477330fc 24700 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
251665fc 24701
62b3e311
PB		 24702 tmp = flags;
24703 arch = 0;
24704 for (p = cpu_arch_ver; p->val; p++)
24705 {
24706 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
24707 {
24708 arch = p->val;
24709 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
24710 }
24711 }
ee065d83 24712
9e3c6df6
PB		 24713 /* The table lookup above finds the last architecture to contribute
24714 a new feature. Unfortunately, Tag13 is a subset of the union of
24715 v6T2 and v7-M, so it is never seen as contributing a new feature.
24716 We can not search for the last entry which is entirely used,
24717 because if no CPU is specified we build up only those flags
24718 actually used. Perhaps we should separate out the specified
24719 and implicit cases. Avoid taking this path for -march=all by
24720 checking for contradictory v7-A / v7-M features. */
24721 if (arch == 10
24722 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
24723 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
24724 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
24725 arch = 13;
24726
ee065d83
PB		 24727 /* Tag_CPU_name. */
24728 if (selected_cpu_name[0])
24729 {
91d6fa6a 24730 char *q;
ee065d83 24731
91d6fa6a
NC		 24732 q = selected_cpu_name;
24733 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB		 24734 {
24735 int i;
5f4273c7 24736
91d6fa6a
NC		 24737 q += 4;
24738 for (i = 0; q[i]; i++)
24739 q[i] = TOUPPER (q[i]);
ee065d83 24740 }
91d6fa6a 24741 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 24742 }
62f3b8c8 24743
ee065d83 24744 /* Tag_CPU_arch. */
ee3c0378 24745 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 24746
62b3e311
PB		 24747 /* Tag_CPU_arch_profile. */
24748 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
69239280 24749 profile = 'A';
62b3e311 24750 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
69239280 24751 profile = 'R';
7e806470 24752 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
69239280
MGD		 24753 profile = 'M';
24754 else
24755 profile = '\0';
24756
24757 if (profile != '\0')
24758 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 24759
ee065d83 24760 /* Tag_ARM_ISA_use. */
ee3c0378
AS		 24761 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
24762 || arch == 0)
24763 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 24764
ee065d83 24765 /* Tag_THUMB_ISA_use. */
ee3c0378
AS		 24766 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
24767 || arch == 0)
24768 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
24769 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
62f3b8c8 24770
ee065d83 24771 /* Tag_VFP_arch. */
bca38921
MGD		 24772 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8))
24773 aeabi_set_attribute_int (Tag_VFP_arch, 7);
24774 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB		 24775 aeabi_set_attribute_int (Tag_VFP_arch,
24776 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
24777 ? 5 : 6);
24778 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD		 24779 {
24780 fp16_optional = 1;
24781 aeabi_set_attribute_int (Tag_VFP_arch, 3);
24782 }
ada65aa3 24783 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD		 24784 {
24785 aeabi_set_attribute_int (Tag_VFP_arch, 4);
24786 fp16_optional = 1;
24787 }
ee3c0378
AS		 24788 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
24789 aeabi_set_attribute_int (Tag_VFP_arch, 2);
24790 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 24791 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 24792 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 24793
4547cb56
NC		 24794 /* Tag_ABI_HardFP_use. */
24795 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
24796 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
24797 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
24798
ee065d83 24799 /* Tag_WMMX_arch. */
ee3c0378
AS		 24800 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
24801 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
24802 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
24803 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 24804
ee3c0378 24805 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
bca38921
MGD		 24806 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
24807 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
24808 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
24809 {
24810 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
24811 {
24812 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
24813 }
24814 else
24815 {
24816 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
24817 fp16_optional = 1;
24818 }
24819 }
fa94de6b 24820
ee3c0378 24821 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 24822 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 24823 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 24824
69239280
MGD		 24825 /* Tag_DIV_use.
24826
24827 We set Tag_DIV_use to two when integer divide instructions have been used
24828 in ARM state, or when Thumb integer divide instructions have been used,
24829 but we have no architecture profile set, nor have we any ARM instructions.
24830
bca38921
MGD		 24831 For ARMv8 we set the tag to 0 as integer divide is implied by the base
24832 architecture.
24833
69239280 24834 For new architectures we will have to check these tests. */
bca38921
MGD		 24835 gas_assert (arch <= TAG_CPU_ARCH_V8);
24836 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
24837 aeabi_set_attribute_int (Tag_DIV_use, 0);
24838 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
24839 || (profile == '\0'
24840 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
24841 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 24842 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD		 24843
24844 /* Tag_MP_extension_use. */
24845 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
24846 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD		 24847
24848 /* Tag Virtualization_use. */
24849 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD		 24850 virt_sec |= 1;
24851 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
24852 virt_sec |= 2;
24853 if (virt_sec != 0)
24854 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
ee065d83
PB		 24855}
24856
104d59d1 24857/* Add the default contents for the .ARM.attributes section. */
ee065d83
PB		 24858void
24859arm_md_end (void)
24860{
ee065d83
PB		 24861 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
24862 return;
24863
24864 aeabi_set_public_attributes ();
ee065d83 24865}
8463be01 24866#endif /* OBJ_ELF */
ee065d83
PB		 24867
24868
24869/* Parse a .cpu directive. */
24870
24871static void
24872s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
24873{
e74cfd16 24874 const struct arm_cpu_option_table *opt;
ee065d83
PB		 24875 char *name;
24876 char saved_char;
24877
24878 name = input_line_pointer;
5f4273c7 24879 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 24880 input_line_pointer++;
24881 saved_char = *input_line_pointer;
24882 *input_line_pointer = 0;
24883
24884 /* Skip the first "all" entry. */
24885 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
24886 if (streq (opt->name, name))
24887 {
e74cfd16
PB		 24888 mcpu_cpu_opt = &opt->value;
24889 selected_cpu = opt->value;
ee065d83 24890 if (opt->canonical_name)
5f4273c7 24891 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 24892 else
24893 {
24894 int i;
24895 for (i = 0; opt->name[i]; i++)
24896 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 24897
ee065d83
PB		 24898 selected_cpu_name[i] = 0;
24899 }
e74cfd16 24900 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 24901 *input_line_pointer = saved_char;
24902 demand_empty_rest_of_line ();
24903 return;
24904 }
24905 as_bad (_("unknown cpu `%s'"), name);
24906 *input_line_pointer = saved_char;
24907 ignore_rest_of_line ();
24908}
24909
24910
24911/* Parse a .arch directive. */
24912
24913static void
24914s_arm_arch (int ignored ATTRIBUTE_UNUSED)
24915{
e74cfd16 24916 const struct arm_arch_option_table *opt;
ee065d83
PB		 24917 char saved_char;
24918 char *name;
24919
24920 name = input_line_pointer;
5f4273c7 24921 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 24922 input_line_pointer++;
24923 saved_char = *input_line_pointer;
24924 *input_line_pointer = 0;
24925
24926 /* Skip the first "all" entry. */
24927 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24928 if (streq (opt->name, name))
24929 {
e74cfd16
PB		 24930 mcpu_cpu_opt = &opt->value;
24931 selected_cpu = opt->value;
5f4273c7 24932 strcpy (selected_cpu_name, opt->name);
e74cfd16 24933 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 24934 *input_line_pointer = saved_char;
24935 demand_empty_rest_of_line ();
24936 return;
24937 }
24938
24939 as_bad (_("unknown architecture `%s'\n"), name);
24940 *input_line_pointer = saved_char;
24941 ignore_rest_of_line ();
24942}
24943
24944
7a1d4c38
PB		 24945/* Parse a .object_arch directive. */
24946
24947static void
24948s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
24949{
24950 const struct arm_arch_option_table *opt;
24951 char saved_char;
24952 char *name;
24953
24954 name = input_line_pointer;
5f4273c7 24955 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB		 24956 input_line_pointer++;
24957 saved_char = *input_line_pointer;
24958 *input_line_pointer = 0;
24959
24960 /* Skip the first "all" entry. */
24961 for (opt = arm_archs + 1; opt->name != NULL; opt++)
24962 if (streq (opt->name, name))
24963 {
24964 object_arch = &opt->value;
24965 *input_line_pointer = saved_char;
24966 demand_empty_rest_of_line ();
24967 return;
24968 }
24969
24970 as_bad (_("unknown architecture `%s'\n"), name);
24971 *input_line_pointer = saved_char;
24972 ignore_rest_of_line ();
24973}
24974
69133863
MGD		 24975/* Parse a .arch_extension directive. */
24976
24977static void
24978s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
24979{
24980 const struct arm_option_extension_value_table *opt;
24981 char saved_char;
24982 char *name;
24983 int adding_value = 1;
24984
24985 name = input_line_pointer;
24986 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
24987 input_line_pointer++;
24988 saved_char = *input_line_pointer;
24989 *input_line_pointer = 0;
24990
24991 if (strlen (name) >= 2
24992 && strncmp (name, "no", 2) == 0)
24993 {
24994 adding_value = 0;
24995 name += 2;
24996 }
24997
24998 for (opt = arm_extensions; opt->name != NULL; opt++)
24999 if (streq (opt->name, name))
25000 {
25001 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25002 {
25003 as_bad (_("architectural extension `%s' is not allowed for the "
25004 "current base architecture"), name);
25005 break;
25006 }
25007
25008 if (adding_value)
25009 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu, opt->value);
25010 else
25011 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->value);
25012
25013 mcpu_cpu_opt = &selected_cpu;
25014 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25015 *input_line_pointer = saved_char;
25016 demand_empty_rest_of_line ();
25017 return;
25018 }
25019
25020 if (opt->name == NULL)
25021 as_bad (_("unknown architecture `%s'\n"), name);
25022
25023 *input_line_pointer = saved_char;
25024 ignore_rest_of_line ();
25025}
25026
ee065d83
PB		 25027/* Parse a .fpu directive. */
25028
25029static void
25030s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25031{
69133863 25032 const struct arm_option_fpu_value_table *opt;
ee065d83
PB		 25033 char saved_char;
25034 char *name;
25035
25036 name = input_line_pointer;
5f4273c7 25037 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25038 input_line_pointer++;
25039 saved_char = *input_line_pointer;
25040 *input_line_pointer = 0;
5f4273c7 25041
ee065d83
PB		 25042 for (opt = arm_fpus; opt->name != NULL; opt++)
25043 if (streq (opt->name, name))
25044 {
e74cfd16
PB		 25045 mfpu_opt = &opt->value;
25046 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25047 *input_line_pointer = saved_char;
25048 demand_empty_rest_of_line ();
25049 return;
25050 }
25051
25052 as_bad (_("unknown floating point format `%s'\n"), name);
25053 *input_line_pointer = saved_char;
25054 ignore_rest_of_line ();
25055}
ee065d83 25056
794ba86a 25057/* Copy symbol information. */
f31fef98 25058
794ba86a
DJ		 25059void
25060arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25061{
25062 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25063}
e04befd0 25064
f31fef98 25065#ifdef OBJ_ELF
e04befd0
AS		 25066/* Given a symbolic attribute NAME, return the proper integer value.
25067 Returns -1 if the attribute is not known. */
f31fef98 25068
e04befd0
AS		 25069int
25070arm_convert_symbolic_attribute (const char *name)
25071{
f31fef98
NC		 25072 static const struct
25073 {
25074 const char * name;
25075 const int tag;
25076 }
25077 attribute_table[] =
25078 {
25079 /* When you modify this table you should
25080 also modify the list in doc/c-arm.texi. */
e04befd0 25081#define T(tag) {#tag, tag}
f31fef98
NC		 25082 T (Tag_CPU_raw_name),
25083 T (Tag_CPU_name),
25084 T (Tag_CPU_arch),
25085 T (Tag_CPU_arch_profile),
25086 T (Tag_ARM_ISA_use),
25087 T (Tag_THUMB_ISA_use),
75375b3e 25088 T (Tag_FP_arch),
f31fef98
NC		 25089 T (Tag_VFP_arch),
25090 T (Tag_WMMX_arch),
25091 T (Tag_Advanced_SIMD_arch),
25092 T (Tag_PCS_config),
25093 T (Tag_ABI_PCS_R9_use),
25094 T (Tag_ABI_PCS_RW_data),
25095 T (Tag_ABI_PCS_RO_data),
25096 T (Tag_ABI_PCS_GOT_use),
25097 T (Tag_ABI_PCS_wchar_t),
25098 T (Tag_ABI_FP_rounding),
25099 T (Tag_ABI_FP_denormal),
25100 T (Tag_ABI_FP_exceptions),
25101 T (Tag_ABI_FP_user_exceptions),
25102 T (Tag_ABI_FP_number_model),
75375b3e 25103 T (Tag_ABI_align_needed),
f31fef98 25104 T (Tag_ABI_align8_needed),
75375b3e 25105 T (Tag_ABI_align_preserved),
f31fef98
NC		 25106 T (Tag_ABI_align8_preserved),
25107 T (Tag_ABI_enum_size),
25108 T (Tag_ABI_HardFP_use),
25109 T (Tag_ABI_VFP_args),
25110 T (Tag_ABI_WMMX_args),
25111 T (Tag_ABI_optimization_goals),
25112 T (Tag_ABI_FP_optimization_goals),
25113 T (Tag_compatibility),
25114 T (Tag_CPU_unaligned_access),
75375b3e 25115 T (Tag_FP_HP_extension),
f31fef98
NC		 25116 T (Tag_VFP_HP_extension),
25117 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD		 25118 T (Tag_MPextension_use),
25119 T (Tag_DIV_use),
f31fef98
NC		 25120 T (Tag_nodefaults),
25121 T (Tag_also_compatible_with),
25122 T (Tag_conformance),
25123 T (Tag_T2EE_use),
25124 T (Tag_Virtualization_use),
cd21e546 25125 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 25126#undef T
f31fef98 25127 };
e04befd0
AS		 25128 unsigned int i;
25129
25130 if (name == NULL)
25131 return -1;
25132
f31fef98 25133 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 25134 if (streq (name, attribute_table[i].name))
e04befd0
AS		 25135 return attribute_table[i].tag;
25136
25137 return -1;
25138}
267bf995
RR		 25139
25140
25141/* Apply sym value for relocations only in the case that
25142 they are for local symbols and you have the respective
25143 architectural feature for blx and simple switches. */
25144int
25145arm_apply_sym_value (struct fix * fixP)
25146{
25147 if (fixP->fx_addsy
25148 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
34e77a92 25149 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR		 25150 {
25151 switch (fixP->fx_r_type)
25152 {
25153 case BFD_RELOC_ARM_PCREL_BLX:
25154 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25155 if (ARM_IS_FUNC (fixP->fx_addsy))
25156 return 1;
25157 break;
25158
25159 case BFD_RELOC_ARM_PCREL_CALL:
25160 case BFD_RELOC_THUMB_PCREL_BLX:
25161 if (THUMB_IS_FUNC (fixP->fx_addsy))
25162 return 1;
25163 break;
25164
25165 default:
25166 break;
25167 }
25168
25169 }
25170 return 0;
25171}
f31fef98 25172#endif /* OBJ_ELF */
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