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x86: don't disassemble MOVBE with two suffixes
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9ab00b61
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (MOVBE_Fixup): Delete.
4 (Mv): Define.
5 (prefix_table): Use Mv for movbe entries.
6
2875b28a
JB		 72020-07-14 Jan Beulich <jbeulich@suse.com>
8
9 * i386-dis.c (CRC32_Fixup): Delete.
10 (prefix_table): Use Eb/Ev for crc32 entries.
11
e184e611
JB		 122020-07-14 Jan Beulich <jbeulich@suse.com>
13
14 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
15 Conditionalize invocations of "USED_REX (0)".
16
e8b5d5f9
JB		 172020-07-14 Jan Beulich <jbeulich@suse.com>
18
19 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
20 CH, DH, BH, AX, DX): Delete.
21 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
22 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
23 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
24
260cd341
LC		 252020-07-10 Lili Cui <lili.cui@intel.com>
26
27 * i386-dis.c (TMM): New.
28 (EXtmm): Likewise.
29 (VexTmm): Likewise.
30 (MVexSIBMEM): Likewise.
31 (tmm_mode): Likewise.
32 (vex_sibmem_mode): Likewise.
33 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
34 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
35 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
36 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
37 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
38 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
39 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
40 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
41 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
42 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
43 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
44 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
45 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
46 (PREFIX_VEX_0F3849_X86_64): Likewise.
47 (PREFIX_VEX_0F384B_X86_64): Likewise.
48 (PREFIX_VEX_0F385C_X86_64): Likewise.
49 (PREFIX_VEX_0F385E_X86_64): Likewise.
50 (X86_64_VEX_0F3849): Likewise.
51 (X86_64_VEX_0F384B): Likewise.
52 (X86_64_VEX_0F385C): Likewise.
53 (X86_64_VEX_0F385E): Likewise.
54 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
55 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
56 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
57 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
58 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
59 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
60 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
61 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
62 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
63 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
64 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
65 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
66 (VEX_W_0F3849_X86_64_P_0): Likewise.
67 (VEX_W_0F3849_X86_64_P_2): Likewise.
68 (VEX_W_0F3849_X86_64_P_3): Likewise.
69 (VEX_W_0F384B_X86_64_P_1): Likewise.
70 (VEX_W_0F384B_X86_64_P_2): Likewise.
71 (VEX_W_0F384B_X86_64_P_3): Likewise.
72 (VEX_W_0F385C_X86_64_P_1): Likewise.
73 (VEX_W_0F385E_X86_64_P_0): Likewise.
74 (VEX_W_0F385E_X86_64_P_1): Likewise.
75 (VEX_W_0F385E_X86_64_P_2): Likewise.
76 (VEX_W_0F385E_X86_64_P_3): Likewise.
77 (names_tmm): Likewise.
78 (att_names_tmm): Likewise.
79 (intel_operand_size): Handle void_mode.
80 (OP_XMM): Handle tmm_mode.
81 (OP_EX): Likewise.
82 (OP_VEX): Likewise.
83 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
84 CpuAMX_BF16 and CpuAMX_TILE.
85 (operand_type_shorthands): Add RegTMM.
86 (operand_type_init): Likewise.
87 (operand_types): Add Tmmword.
88 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
89 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
90 * i386-opc.h (CpuAMX_INT8): New.
91 (CpuAMX_BF16): Likewise.
92 (CpuAMX_TILE): Likewise.
93 (SIBMEM): Likewise.
94 (Tmmword): Likewise.
95 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
96 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
97 (i386_operand_type): Add tmmword.
98 * i386-opc.tbl: Add AMX instructions.
99 * i386-reg.tbl: Add AMX registers.
100 * i386-init.h: Regenerated.
101 * i386-tbl.h: Likewise.
102
467bbef0
JB		 1032020-07-08 Jan Beulich <jbeulich@suse.com>
104
105 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
106 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
107 Rename to ...
108 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
109 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
110 respectively.
111 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
112 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
113 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
114 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
115 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
116 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
117 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
118 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
119 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
120 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
121 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
122 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
123 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
124 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
125 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
126 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
127 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
128 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
129 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
130 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
131 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
132 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
133 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
134 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
135 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
136 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
137 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
138 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
139 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
140 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
141 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
142 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
143 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
144 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
145 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
146 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
147 (reg_table): Re-order XOP entries. Adjust their operands.
148 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
149 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
150 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
151 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
152 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
153 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
154 entries by references ...
155 (vex_len_table): ... to resepctive new entries here. For several
156 new and existing entries reference ...
157 (vex_w_table): ... new entries here.
158 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
159
6384fd9e
JB		 1602020-07-08 Jan Beulich <jbeulich@suse.com>
161
162 * i386-dis.c (XMVexScalarI4): Define.
163 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
164 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
165 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
166 (vex_len_table): Move scalar FMA4 entries ...
167 (prefix_table): ... here.
168 (OP_REG_VexI4): Handle scalar_mode.
169 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
170 * i386-tbl.h: Re-generate.
171
e6123d0c
JB		 1722020-07-08 Jan Beulich <jbeulich@suse.com>
173
174 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
175 Vex_2src_2): Delete.
176 (OP_VexW, VexW): New.
177 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
178 for shifts and rotates by register.
179
93abb146
JB		 1802020-07-08 Jan Beulich <jbeulich@suse.com>
181
182 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
183 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
184 OP_EX_VexReg): Delete.
185 (OP_VexI4, VexI4): New.
186 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
187 (prefix_table): ... here.
188 (print_insn): Drop setting of vex_w_done.
189
b13b1bc0
JB		 1902020-07-08 Jan Beulich <jbeulich@suse.com>
191
192 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
193 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
194 (xop_table): Replace operands of 4-operand insns.
195 (OP_REG_VexI4): Move VEX.W based operand swaping here.
196
f337259f
CZ		 1972020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
198
199 * arc-opc.c (insert_rbd): New function.
200 (RBD): Define.
201 (RBDdup): Likewise.
202 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
203 instructions.
204
931452b6
JB		 2052020-07-07 Jan Beulich <jbeulich@suse.com>
206
207 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
208 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
209 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
210 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
211 Delete.
212 (putop): Handle "BW".
213 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
214 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
215 and 0F3A3F ...
216 * i386-dis-evex-prefix.h: ... here.
217
b5b098c2
JB		 2182020-07-06 Jan Beulich <jbeulich@suse.com>
219
220 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
221 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
222 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
223 VEX_W_0FXOP_09_83): New enumerators.
224 (xop_table): Reference the above.
225 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
226 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
227 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
228 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
229
21a3faeb
JB		 2302020-07-06 Jan Beulich <jbeulich@suse.com>
231
232 * i386-dis.c (EVEX_W_0F3838_P_1,
233 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
234 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
235 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
236 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
237 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
238 (putop): Centralize management of last[]. Delete SAVE_LAST.
239 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
240 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
241 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
242 * i386-dis-evex-prefix.h: here.
243
bc152a17
JB		 2442020-07-06 Jan Beulich <jbeulich@suse.com>
245
246 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
247 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
248 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
249 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
250 enumerators.
251 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
252 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
253 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
254 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
255 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
256 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
257 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
258 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
259 these, respectively.
260 * i386-dis-evex-len.h: Adjust comments.
261 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
262 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
263 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
264 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
265 MOD_EVEX_0F385B_P_2_W_1 table entries.
266 * i386-dis-evex-w.h: Reference mod_table[] for
267 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
268 EVEX_W_0F385B_P_2.
269
c82a99a0
JB		 2702020-07-06 Jan Beulich <jbeulich@suse.com>
271
272 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
273 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
274 EXymm.
275 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
276 Likewise. Mark 256-bit entries invalid.
277
fedfb81e
JB		 2782020-07-06 Jan Beulich <jbeulich@suse.com>
279
280 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
281 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
282 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
283 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
284 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
285 PREFIX_EVEX_0F382B): Delete.
286 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
287 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
288 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
289 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
290 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
291 to ...
292 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
293 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
294 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
295 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
296 respectively.
297 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
298 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
299 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
300 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
301 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
302 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
303 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
304 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
305 PREFIX_EVEX_0F382B): Remove table entries.
306 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
307 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
308 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
309
3a57774c
JB		 3102020-07-06 Jan Beulich <jbeulich@suse.com>
311
312 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
313 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
314 enumerators.
315 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
316 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
317 EVEX_LEN_0F3A01_P_2_W_1 table entries.
318 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
319 entries.
320
e74d9fa9
JB		 3212020-07-06 Jan Beulich <jbeulich@suse.com>
322
323 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
324 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
325 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
326 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
327 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
328 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
329 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
330 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
331 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
332 entries.
333
6431c801
JB		 3342020-07-06 Jan Beulich <jbeulich@suse.com>
335
336 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
337 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
338 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
339 respectively.
340 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
341 entries.
342 * i386-dis-evex.h (evex_table): Reference VEX table entry for
343 opcode 0F3A1D.
344 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
345 entry.
346 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
347
6df22cf6
JB		 3482020-07-06 Jan Beulich <jbeulich@suse.com>
349
350 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
351 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
352 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
353 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
354 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
355 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
356 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
357 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
358 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
359 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
360 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
361 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
362 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
363 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
364 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
365 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
366 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
367 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
368 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
369 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
370 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
371 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
372 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
373 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
374 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
375 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
376 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
377 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
378 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
379 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
380 (prefix_table): Add EXxEVexR to FMA table entries.
381 (OP_Rounding): Move abort() invocation.
382 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
383 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
384 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
385 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
386 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
387 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
388 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
389 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
390 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
391 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
392 0F3ACE, 0F3ACF.
393 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
394 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
395 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
396 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
397 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
398 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
399 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
400 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
401 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
402 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
403 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
404 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
405 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
406 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
407 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
408 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
409 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
410 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
411 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
412 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
413 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
414 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
415 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
416 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
417 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
418 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
419 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
420 Delete table entries.
421 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
422 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
423 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
424 Likewise.
425
39e0f456
JB		 4262020-07-06 Jan Beulich <jbeulich@suse.com>
427
428 * i386-dis.c (EXqScalarS): Delete.
429 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
430 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
431
5b872f7d
JB		 4322020-07-06 Jan Beulich <jbeulich@suse.com>
433
434 * i386-dis.c (safe-ctype.h): Include.
435 (EXdScalar, EXqScalar): Delete.
436 (d_scalar_mode, q_scalar_mode): Delete.
437 (prefix_table, vex_len_table): Use EXxmm_md in place of
438 EXdScalar and EXxmm_mq in place of EXqScalar.
439 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
440 d_scalar_mode and q_scalar_mode.
441 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
442 (vmovsd): Use EXxmm_mq.
443
ddc73fa9
NC		 4442020-07-06 Yuri Chornoivan <yurchor@ukr.net>
445
446 PR 26204
447 * arc-dis.c: Fix spelling mistake.
448 * po/opcodes.pot: Regenerate.
449
17550be7
NC		 4502020-07-06 Nick Clifton <nickc@redhat.com>
451
452 * po/pt_BR.po: Updated Brazilian Portugugese translation.
453 * po/uk.po: Updated Ukranian translation.
454
b19d852d
NC		 4552020-07-04 Nick Clifton <nickc@redhat.com>
456
457 * configure: Regenerate.
458 * po/opcodes.pot: Regenerate.
459
b115b9fd
NC		 4602020-07-04 Nick Clifton <nickc@redhat.com>
461
462 Binutils 2.35 branch created.
463
c2ecccb3
L		 4642020-07-02 H.J. Lu <hongjiu.lu@intel.com>
465
466 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
467 * i386-opc.h (VexSwapSources): New.
468 (i386_opcode_modifier): Add vexswapsources.
469 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
470 with two source operands swapped.
471 * i386-tbl.h: Regenerated.
472
08ccfccf
NC		 4732020-06-30 Nelson Chu <nelson.chu@sifive.com>
474
475 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
476 unprivileged CSR can also be initialized.
477
279edac5
AM		 4782020-06-29 Alan Modra <amodra@gmail.com>
479
480 * arm-dis.c: Use C style comments.
481 * cr16-opc.c: Likewise.
482 * ft32-dis.c: Likewise.
483 * moxie-opc.c: Likewise.
484 * tic54x-dis.c: Likewise.
485 * s12z-opc.c: Remove useless comment.
486 * xgate-dis.c: Likewise.
487
e978ad62
L		 4882020-06-26 H.J. Lu <hongjiu.lu@intel.com>
489
490 * i386-opc.tbl: Add a blank line.
491
63112cd6
L		 4922020-06-26 H.J. Lu <hongjiu.lu@intel.com>
493
494 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
495 (VecSIB128): Renamed to ...
496 (VECSIB128): This.
497 (VecSIB256): Renamed to ...
498 (VECSIB256): This.
499 (VecSIB512): Renamed to ...
500 (VECSIB512): This.
501 (VecSIB): Renamed to ...
502 (SIB): This.
503 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 504 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 505 (VecSIB256): Likewise.
506 (VecSIB512): Likewise.
79b32e73 507 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 508 and VecSIB512, respectively.
509
d1c36125
JB		 5102020-06-26 Jan Beulich <jbeulich@suse.com>
511
512 * i386-dis.c: Adjust description of I macro.
513 (x86_64_table): Drop use of I.
514 (float_mem): Replace use of I.
515 (putop): Remove handling of I. Adjust setting/clearing of "alt".
516
2a1bb84c
JB		 5172020-06-26 Jan Beulich <jbeulich@suse.com>
518
519 * i386-dis.c: (print_insn): Avoid straight assignment to
520 priv.orig_sizeflag when processing -M sub-options.
521
8f570d62
JB		 5222020-06-25 Jan Beulich <jbeulich@suse.com>
523
524 * i386-dis.c: Adjust description of J macro.
525 (dis386, x86_64_table, mod_table): Replace J.
526 (putop): Remove handling of J.
527
464dc4af
JB		 5282020-06-25 Jan Beulich <jbeulich@suse.com>
529
530 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
531
589958d6
JB		 5322020-06-25 Jan Beulich <jbeulich@suse.com>
533
534 * i386-dis.c: Adjust description of "LQ" macro.
535 (dis386_twobyte): Use LQ for sysret.
536 (putop): Adjust handling of LQ.
537
39ff0b81
NC		 5382020-06-22 Nelson Chu <nelson.chu@sifive.com>
539
540 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
541 * riscv-dis.c: Include elfxx-riscv.h.
542
d27c357a
JB		 5432020-06-18 H.J. Lu <hongjiu.lu@intel.com>
544
545 * i386-dis.c (prefix_table): Revert the last vmgexit change.
546
6fde587f
CL		 5472020-06-17 Lili Cui <lili.cui@intel.com>
548
549 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
550
efe30057
L		 5512020-06-14 H.J. Lu <hongjiu.lu@intel.com>
552
553 PR gas/26115
554 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
555 * i386-opc.tbl: Likewise.
556 * i386-tbl.h: Regenerated.
557
d8af286f
NC		 5582020-06-12 Nelson Chu <nelson.chu@sifive.com>
559
560 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
561
14962256
AC		 5622020-06-11 Alex Coplan <alex.coplan@arm.com>
563
564 * aarch64-opc.c (SYSREG): New macro for describing system registers.
565 (SR_CORE): Likewise.
566 (SR_FEAT): Likewise.
567 (SR_RNG): Likewise.
568 (SR_V8_1): Likewise.
569 (SR_V8_2): Likewise.
570 (SR_V8_3): Likewise.
571 (SR_V8_4): Likewise.
572 (SR_PAN): Likewise.
573 (SR_RAS): Likewise.
574 (SR_SSBS): Likewise.
575 (SR_SVE): Likewise.
576 (SR_ID_PFR2): Likewise.
577 (SR_PROFILE): Likewise.
578 (SR_MEMTAG): Likewise.
579 (SR_SCXTNUM): Likewise.
580 (aarch64_sys_regs): Refactor to store feature information in the table.
581 (aarch64_sys_reg_supported_p): Collapse logic for system registers
582 that now describe their own features.
583 (aarch64_pstatefield_supported_p): Likewise.
584
f9630fa6
L		 5852020-06-09 H.J. Lu <hongjiu.lu@intel.com>
586
587 * i386-dis.c (prefix_table): Fix a typo in comments.
588
73239888
JB		 5892020-06-09 Jan Beulich <jbeulich@suse.com>
590
591 * i386-dis.c (rex_ignored): Delete.
592 (ckprefix): Drop rex_ignored initialization.
593 (get_valid_dis386): Drop setting of rex_ignored.
594 (print_insn): Drop checking of rex_ignored. Don't record data
595 size prefix as used with VEX-and-alike encodings.
596
18897deb
JB		 5972020-06-09 Jan Beulich <jbeulich@suse.com>
598
599 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
600 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
601 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
602 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
603 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
604 VEX_0F12, and VEX_0F16.
605 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
606 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
607 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
608 from movlps and movhlps. New MOD_0F12_PREFIX_2,
609 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
610 MOD_VEX_0F16_PREFIX_2 entries.
611
97e6786a
JB		 6122020-06-09 Jan Beulich <jbeulich@suse.com>
613
614 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
615 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
616 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
617 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
618 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
619 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
620 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
621 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
622 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
623 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
624 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
625 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
626 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
627 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
628 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
629 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
630 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
631 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
632 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
633 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
634 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
635 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
636 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
637 EVEX_W_0FC6_P_2): Delete.
638 (print_insn): Add EVEX.W vs embedded prefix consistency check
639 to prefix validation.
640 * i386-dis-evex.h (evex_table): Don't further descend for
641 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
642 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
643 and 0F2B.
644 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
645 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
646 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
647 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
648 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
649 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
650 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
651 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
652 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
653 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
654 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
655 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
656 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
657 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
658 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
659 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
660 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
661 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
662 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
663 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
664 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
665 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
666 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
667 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
668 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
669 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
670 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
671
bf926894
JB		 6722020-06-09 Jan Beulich <jbeulich@suse.com>
673
674 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
675 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
676 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
677 vmovmskpX.
678 (print_insn): Drop pointless check against bad_opcode. Split
679 prefix validation into legacy and VEX-and-alike parts.
680 (putop): Re-work 'X' macro handling.
681
a5aaedb9
JB		 6822020-06-09 Jan Beulich <jbeulich@suse.com>
683
684 * i386-dis.c (MOD_0F51): Rename to ...
685 (MOD_0F50): ... this.
686
26417f19
AC		 6872020-06-08 Alex Coplan <alex.coplan@arm.com>
688
689 * arm-dis.c (arm_opcodes): Add dfb.
690 (thumb32_opcodes): Add dfb.
691
8a6fb3f9
JB		 6922020-06-08 Jan Beulich <jbeulich@suse.com>
693
694 * i386-opc.h (reg_entry): Const-qualify reg_name field.
695
1424c35d
AM		 6962020-06-06 Alan Modra <amodra@gmail.com>
697
698 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
699
d3d1cc7b
AM		 7002020-06-05 Alan Modra <amodra@gmail.com>
701
702 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
703 size is large enough.
704
d8740be1
JM		 7052020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
706
707 * disassemble.c (disassemble_init_for_target): Set endian_code for
708 bpf targets.
709 * bpf-desc.c: Regenerate.
710 * bpf-opc.c: Likewise.
711 * bpf-dis.c: Likewise.
712
e9bffec9
JM		 7132020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
714
715 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
716 (cgen_put_insn_value): Likewise.
717 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
718 * cgen-dis.in (print_insn): Likewise.
719 * cgen-ibld.in (insert_1): Likewise.
720 (insert_1): Likewise.
721 (insert_insn_normal): Likewise.
722 (extract_1): Likewise.
723 * bpf-dis.c: Regenerate.
724 * bpf-ibld.c: Likewise.
725 * bpf-ibld.c: Likewise.
726 * cgen-dis.in: Likewise.
727 * cgen-ibld.in: Likewise.
728 * cgen-opc.c: Likewise.
729 * epiphany-dis.c: Likewise.
730 * epiphany-ibld.c: Likewise.
731 * fr30-dis.c: Likewise.
732 * fr30-ibld.c: Likewise.
733 * frv-dis.c: Likewise.
734 * frv-ibld.c: Likewise.
735 * ip2k-dis.c: Likewise.
736 * ip2k-ibld.c: Likewise.
737 * iq2000-dis.c: Likewise.
738 * iq2000-ibld.c: Likewise.
739 * lm32-dis.c: Likewise.
740 * lm32-ibld.c: Likewise.
741 * m32c-dis.c: Likewise.
742 * m32c-ibld.c: Likewise.
743 * m32r-dis.c: Likewise.
744 * m32r-ibld.c: Likewise.
745 * mep-dis.c: Likewise.
746 * mep-ibld.c: Likewise.
747 * mt-dis.c: Likewise.
748 * mt-ibld.c: Likewise.
749 * or1k-dis.c: Likewise.
750 * or1k-ibld.c: Likewise.
751 * xc16x-dis.c: Likewise.
752 * xc16x-ibld.c: Likewise.
753 * xstormy16-dis.c: Likewise.
754 * xstormy16-ibld.c: Likewise.
755
b3db6d07
JM		 7562020-06-04 Jose E. Marchesi <jemarch@gnu.org>
757
758 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
759 (print_insn_): Handle instruction endian.
760 * bpf-dis.c: Regenerate.
761 * bpf-desc.c: Regenerate.
762 * epiphany-dis.c: Likewise.
763 * epiphany-desc.c: Likewise.
764 * fr30-dis.c: Likewise.
765 * fr30-desc.c: Likewise.
766 * frv-dis.c: Likewise.
767 * frv-desc.c: Likewise.
768 * ip2k-dis.c: Likewise.
769 * ip2k-desc.c: Likewise.
770 * iq2000-dis.c: Likewise.
771 * iq2000-desc.c: Likewise.
772 * lm32-dis.c: Likewise.
773 * lm32-desc.c: Likewise.
774 * m32c-dis.c: Likewise.
775 * m32c-desc.c: Likewise.
776 * m32r-dis.c: Likewise.
777 * m32r-desc.c: Likewise.
778 * mep-dis.c: Likewise.
779 * mep-desc.c: Likewise.
780 * mt-dis.c: Likewise.
781 * mt-desc.c: Likewise.
782 * or1k-dis.c: Likewise.
783 * or1k-desc.c: Likewise.
784 * xc16x-dis.c: Likewise.
785 * xc16x-desc.c: Likewise.
786 * xstormy16-dis.c: Likewise.
787 * xstormy16-desc.c: Likewise.
788
4ee4189f
NC		 7892020-06-03 Nick Clifton <nickc@redhat.com>
790
791 * po/sr.po: Updated Serbian translation.
792
44730156
NC		 7932020-06-03 Nelson Chu <nelson.chu@sifive.com>
794
795 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
796 (riscv_get_priv_spec_class): Likewise.
797
3c3d0376
AM		 7982020-06-01 Alan Modra <amodra@gmail.com>
799
800 * bpf-desc.c: Regenerate.
801
78c1c354
JM		 8022020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
803 David Faust <david.faust@oracle.com>
804
805 * bpf-desc.c: Regenerate.
806 * bpf-opc.h: Likewise.
807 * bpf-opc.c: Likewise.
808 * bpf-dis.c: Likewise.
809
efcf5fb5
AM		 8102020-05-28 Alan Modra <amodra@gmail.com>
811
812 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
813 values.
814
ab382d64
AM		 8152020-05-28 Alan Modra <amodra@gmail.com>
816
817 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
818 immediates.
819 (print_insn_ns32k): Revert last change.
820
151f5de4
NC		 8212020-05-28 Nick Clifton <nickc@redhat.com>
822
823 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
824 static.
825
25e1eca8
SL		 8262020-05-26 Sandra Loosemore <sandra@codesourcery.com>
827
828 Fix extraction of signed constants in nios2 disassembler (again).
829
830 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
831 extractions of signed fields.
832
57b17940
SSF		 8332020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
834
835 * s390-opc.txt: Relocate vector load/store instructions with
836 additional alignment parameter and change architecture level
837 constraint from z14 to z13.
838
d96bf37b
AM		 8392020-05-21 Alan Modra <amodra@gmail.com>
840
841 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
842 * sparc-dis.c: Likewise.
843 * tic4x-dis.c: Likewise.
844 * xtensa-dis.c: Likewise.
845 * bpf-desc.c: Regenerate.
846 * epiphany-desc.c: Regenerate.
847 * fr30-desc.c: Regenerate.
848 * frv-desc.c: Regenerate.
849 * ip2k-desc.c: Regenerate.
850 * iq2000-desc.c: Regenerate.
851 * lm32-desc.c: Regenerate.
852 * m32c-desc.c: Regenerate.
853 * m32r-desc.c: Regenerate.
854 * mep-asm.c: Regenerate.
855 * mep-desc.c: Regenerate.
856 * mt-desc.c: Regenerate.
857 * or1k-desc.c: Regenerate.
858 * xc16x-desc.c: Regenerate.
859 * xstormy16-desc.c: Regenerate.
860
8f595e9b
NC		 8612020-05-20 Nelson Chu <nelson.chu@sifive.com>
862
863 * riscv-opc.c (riscv_ext_version_table): The table used to store
864 all information about the supported spec and the corresponding ISA
865 versions. Currently, only Zicsr is supported to verify the
866 correctness of Z sub extension settings. Others will be supported
867 in the future patches.
868 (struct isa_spec_t, isa_specs): List for all supported ISA spec
869 classes and the corresponding strings.
870 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
871 spec class by giving a ISA spec string.
872 * riscv-opc.c (struct priv_spec_t): New structure.
873 (struct priv_spec_t priv_specs): List for all supported privilege spec
874 classes and the corresponding strings.
875 (riscv_get_priv_spec_class): New function. Get the corresponding
876 privilege spec class by giving a spec string.
877 (riscv_get_priv_spec_name): New function. Get the corresponding
878 privilege spec string by giving a CSR version class.
879 * riscv-dis.c: Updated since DECLARE_CSR is changed.
880 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
881 according to the chosen version. Build a hash table riscv_csr_hash to
882 store the valid CSR for the chosen pirv verison. Dump the direct
883 CSR address rather than it's name if it is invalid.
884 (parse_riscv_dis_option_without_args): New function. Parse the options
885 without arguments.
886 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
887 parse the options without arguments first, and then handle the options
888 with arguments. Add the new option -Mpriv-spec, which has argument.
889 * riscv-dis.c (print_riscv_disassembler_options): Add description
890 about the new OBJDUMP option.
891
3d205eb4
PB		 8922020-05-19 Peter Bergner <bergner@linux.ibm.com>
893
894 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
895 WC values on POWER10 sync, dcbf and wait instructions.
896 (insert_pl, extract_pl): New functions.
897 (L2OPT, LS, WC): Use insert_ls and extract_ls.
898 (LS3): New , 3-bit L for sync.
899 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
900 (SC2, PL): New, 2-bit SC and PL for sync and wait.
901 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
902 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
903 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
904 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
905 <wait>: Enable PL operand on POWER10.
906 <dcbf>: Enable L3OPT operand on POWER10.
907 <sync>: Enable SC2 operand on POWER10.
908
a501eb44
SH		 9092020-05-19 Stafford Horne <shorne@gmail.com>
910
911 PR 25184
912 * or1k-asm.c: Regenerate.
913 * or1k-desc.c: Regenerate.
914 * or1k-desc.h: Regenerate.
915 * or1k-dis.c: Regenerate.
916 * or1k-ibld.c: Regenerate.
917 * or1k-opc.c: Regenerate.
918 * or1k-opc.h: Regenerate.
919 * or1k-opinst.c: Regenerate.
920
3b646889
AM		 9212020-05-11 Alan Modra <amodra@gmail.com>
922
923 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
924 xsmaxcqp, xsmincqp.
925
9cc4ce88
AM		 9262020-05-11 Alan Modra <amodra@gmail.com>
927
928 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
929 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
930
5d57bc3f
AM		 9312020-05-11 Alan Modra <amodra@gmail.com>
932
933 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
934
66ef5847
AM		 9352020-05-11 Alan Modra <amodra@gmail.com>
936
937 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
938 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
939
4f3e9537
PB		 9402020-05-11 Peter Bergner <bergner@linux.ibm.com>
941
942 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
943 mnemonics.
944
ec40e91c
AM		 9452020-05-11 Alan Modra <amodra@gmail.com>
946
947 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
948 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
949 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
950 (prefix_opcodes): Add xxeval.
951
d7e97a76
AM		 9522020-05-11 Alan Modra <amodra@gmail.com>
953
954 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
955 xxgenpcvwm, xxgenpcvdm.
956
fdefed7c
AM		 9572020-05-11 Alan Modra <amodra@gmail.com>
958
959 * ppc-opc.c (MP, VXVAM_MASK): Define.
960 (VXVAPS_MASK): Use VXVA_MASK.
961 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
962 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
963 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
964 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
965
aa3c112f
AM		 9662020-05-11 Alan Modra <amodra@gmail.com>
967 Peter Bergner <bergner@linux.ibm.com>
968
969 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
970 New functions.
971 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
972 YMSK2, XA6a, XA6ap, XB6a entries.
973 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
974 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
975 (PPCVSX4): Define.
976 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
977 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
978 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
979 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
980 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
981 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
982 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
983 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
984 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
985 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
986 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
987 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
988 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
989 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
990
6edbfd3b
AM		 9912020-05-11 Alan Modra <amodra@gmail.com>
992
993 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
994 (insert_xts, extract_xts): New functions.
995 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
996 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
997 (VXRC_MASK, VXSH_MASK): Define.
998 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
999 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1000 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1001 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1002 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1003 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1004 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1005
c7d7aea2
AM		 10062020-05-11 Alan Modra <amodra@gmail.com>
1007
1008 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1009 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1010 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1011 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1012 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1013
94ba9882
AM		 10142020-05-11 Alan Modra <amodra@gmail.com>
1015
1016 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1017 (XTP, DQXP, DQXP_MASK): Define.
1018 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1019 (prefix_opcodes): Add plxvp and pstxvp.
1020
f4791f1a
AM		 10212020-05-11 Alan Modra <amodra@gmail.com>
1022
1023 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1024 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1025 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1026
3ff0a5ba
PB		 10272020-05-11 Peter Bergner <bergner@linux.ibm.com>
1028
1029 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1030
afef4fe9
PB		 10312020-05-11 Peter Bergner <bergner@linux.ibm.com>
1032
1033 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1034 (L1OPT): Define.
1035 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1036
1224c05d
PB		 10372020-05-11 Peter Bergner <bergner@linux.ibm.com>
1038
1039 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1040
6bbb0c05
AM		 10412020-05-11 Alan Modra <amodra@gmail.com>
1042
1043 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1044
7c1f4227
AM		 10452020-05-11 Alan Modra <amodra@gmail.com>
1046
1047 * ppc-dis.c (ppc_opts): Add "power10" entry.
1048 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1049 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1050
73199c2b
NC		 10512020-05-11 Nick Clifton <nickc@redhat.com>
1052
1053 * po/fr.po: Updated French translation.
1054
09c1e68a
AC		 10552020-04-30 Alex Coplan <alex.coplan@arm.com>
1056
1057 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1058 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1059 (operand_general_constraint_met_p): validate
1060 AARCH64_OPND_UNDEFINED.
1061 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1062 for FLD_imm16_2.
1063 * aarch64-asm-2.c: Regenerated.
1064 * aarch64-dis-2.c: Regenerated.
1065 * aarch64-opc-2.c: Regenerated.
1066
9654d51a
NC		 10672020-04-29 Nick Clifton <nickc@redhat.com>
1068
1069 PR 22699
1070 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1071 and SETRC insns.
1072
c2e71e57
NC		 10732020-04-29 Nick Clifton <nickc@redhat.com>
1074
1075 * po/sv.po: Updated Swedish translation.
1076
5c936ef5
NC		 10772020-04-29 Nick Clifton <nickc@redhat.com>
1078
1079 PR 22699
1080 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1081 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1082 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1083 IMM0_8U case.
1084
bb2a1453
AS		 10852020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1086
1087 PR 25848
1088 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1089 cmpi only on m68020up and cpu32.
1090
c2e5c986
SD		 10912020-04-20 Sudakshina Das <sudi.das@arm.com>
1092
1093 * aarch64-asm.c (aarch64_ins_none): New.
1094 * aarch64-asm.h (ins_none): New declaration.
1095 * aarch64-dis.c (aarch64_ext_none): New.
1096 * aarch64-dis.h (ext_none): New declaration.
1097 * aarch64-opc.c (aarch64_print_operand): Update case for
1098 AARCH64_OPND_BARRIER_PSB.
1099 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1100 (AARCH64_OPERANDS): Update inserter/extracter for
1101 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1102 * aarch64-asm-2.c: Regenerated.
1103 * aarch64-dis-2.c: Regenerated.
1104 * aarch64-opc-2.c: Regenerated.
1105
8a6e1d1d
SD		 11062020-04-20 Sudakshina Das <sudi.das@arm.com>
1107
1108 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1109 (aarch64_feature_ras, RAS): Likewise.
1110 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1111 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1112 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1113 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1114 * aarch64-asm-2.c: Regenerated.
1115 * aarch64-dis-2.c: Regenerated.
1116 * aarch64-opc-2.c: Regenerated.
1117
e409955d
FS		 11182020-04-17 Fredrik Strupe <fredrik@strupe.net>
1119
1120 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1121 (print_insn_neon): Support disassembly of conditional
1122 instructions.
1123
c54a9b56
DF		 11242020-02-16 David Faust <david.faust@oracle.com>
1125
1126 * bpf-desc.c: Regenerate.
1127 * bpf-desc.h: Likewise.
1128 * bpf-opc.c: Regenerate.
1129 * bpf-opc.h: Likewise.
1130
bb651e8b
CL		 11312020-04-07 Lili Cui <lili.cui@intel.com>
1132
1133 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1134 (prefix_table): New instructions (see prefixes above).
1135 (rm_table): Likewise
1136 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1137 CPU_ANY_TSXLDTRK_FLAGS.
1138 (cpu_flags): Add CpuTSXLDTRK.
1139 * i386-opc.h (enum): Add CpuTSXLDTRK.
1140 (i386_cpu_flags): Add cputsxldtrk.
1141 * i386-opc.tbl: Add XSUSPLDTRK insns.
1142 * i386-init.h: Regenerate.
1143 * i386-tbl.h: Likewise.
1144
4b27d27c
L		 11452020-04-02 Lili Cui <lili.cui@intel.com>
1146
1147 * i386-dis.c (prefix_table): New instructions serialize.
1148 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1149 CPU_ANY_SERIALIZE_FLAGS.
1150 (cpu_flags): Add CpuSERIALIZE.
1151 * i386-opc.h (enum): Add CpuSERIALIZE.
1152 (i386_cpu_flags): Add cpuserialize.
1153 * i386-opc.tbl: Add SERIALIZE insns.
1154 * i386-init.h: Regenerate.
1155 * i386-tbl.h: Likewise.
1156
832a5807
AM		 11572020-03-26 Alan Modra <amodra@gmail.com>
1158
1159 * disassemble.h (opcodes_assert): Declare.
1160 (OPCODES_ASSERT): Define.
1161 * disassemble.c: Don't include assert.h. Include opintl.h.
1162 (opcodes_assert): New function.
1163 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1164 (bfd_h8_disassemble): Reduce size of data array. Correctly
1165 calculate maxlen. Omit insn decoding when insn length exceeds
1166 maxlen. Exit from nibble loop when looking for E, before
1167 accessing next data byte. Move processing of E outside loop.
1168 Replace tests of maxlen in loop with assertions.
1169
4c4addbe
AM		 11702020-03-26 Alan Modra <amodra@gmail.com>
1171
1172 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1173
a18cd0ca
AM		 11742020-03-25 Alan Modra <amodra@gmail.com>
1175
1176 * z80-dis.c (suffix): Init mybuf.
1177
57cb32b3
AM		 11782020-03-22 Alan Modra <amodra@gmail.com>
1179
1180 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1181 successflly read from section.
1182
beea5cc1
AM		 11832020-03-22 Alan Modra <amodra@gmail.com>
1184
1185 * arc-dis.c (find_format): Use ISO C string concatenation rather
1186 than line continuation within a string. Don't access needs_limm
1187 before testing opcode != NULL.
1188
03704c77
AM		 11892020-03-22 Alan Modra <amodra@gmail.com>
1190
1191 * ns32k-dis.c (print_insn_arg): Update comment.
1192 (print_insn_ns32k): Reduce size of index_offset array, and
1193 initialize, passing -1 to print_insn_arg for args that are not
1194 an index. Don't exit arg loop early. Abort on bad arg number.
1195
d1023b5d
AM		 11962020-03-22 Alan Modra <amodra@gmail.com>
1197
1198 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1199 * s12z-opc.c: Formatting.
1200 (operands_f): Return an int.
1201 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1202 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1203 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1204 (exg_sex_discrim): Likewise.
1205 (create_immediate_operand, create_bitfield_operand),
1206 (create_register_operand_with_size, create_register_all_operand),
1207 (create_register_all16_operand, create_simple_memory_operand),
1208 (create_memory_operand, create_memory_auto_operand): Don't
1209 segfault on malloc failure.
1210 (z_ext24_decode): Return an int status, negative on fail, zero
1211 on success.
1212 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1213 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1214 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1215 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1216 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1217 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1218 (loop_primitive_decode, shift_decode, psh_pul_decode),
1219 (bit_field_decode): Similarly.
1220 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1221 to return value, update callers.
1222 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1223 Don't segfault on NULL operand.
1224 (decode_operation): Return OP_INVALID on first fail.
1225 (decode_s12z): Check all reads, returning -1 on fail.
1226
340f3ac8
AM		 12272020-03-20 Alan Modra <amodra@gmail.com>
1228
1229 * metag-dis.c (print_insn_metag): Don't ignore status from
1230 read_memory_func.
1231
fe90ae8a
AM		 12322020-03-20 Alan Modra <amodra@gmail.com>
1233
1234 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1235 Initialize parts of buffer not written when handling a possible
1236 2-byte insn at end of section. Don't attempt decoding of such
1237 an insn by the 4-byte machinery.
1238
833d919c
AM		 12392020-03-20 Alan Modra <amodra@gmail.com>
1240
1241 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1242 partially filled buffer. Prevent lookup of 4-byte insns when
1243 only VLE 2-byte insns are possible due to section size. Print
1244 ".word" rather than ".long" for 2-byte leftovers.
1245
327ef784
NC		 12462020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1247
1248 PR 25641
1249 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1250
1673df32
JB		 12512020-03-13 Jan Beulich <jbeulich@suse.com>
1252
1253 * i386-dis.c (X86_64_0D): Rename to ...
1254 (X86_64_0E): ... this.
1255
384f3689
L		 12562020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1257
1258 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1259 * Makefile.in: Regenerated.
1260
865e2027
JB		 12612020-03-09 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1264 3-operand pseudos.
1265 * i386-tbl.h: Re-generate.
1266
2f13234b
JB		 12672020-03-09 Jan Beulich <jbeulich@suse.com>
1268
1269 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1270 vprot*, vpsha*, and vpshl*.
1271 * i386-tbl.h: Re-generate.
1272
3fabc179
JB		 12732020-03-09 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1276 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1277 * i386-tbl.h: Re-generate.
1278
3677e4c1
JB		 12792020-03-09 Jan Beulich <jbeulich@suse.com>
1280
1281 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1282 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1283 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1284 * i386-tbl.h: Re-generate.
1285
4c4898e8
JB		 12862020-03-09 Jan Beulich <jbeulich@suse.com>
1287
1288 * i386-gen.c (struct template_arg, struct template_instance,
1289 struct template_param, struct template, templates,
1290 parse_template, expand_templates): New.
1291 (process_i386_opcodes): Various local variables moved to
1292 expand_templates. Call parse_template and expand_templates.
1293 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1294 * i386-tbl.h: Re-generate.
1295
bc49bfd8
JB		 12962020-03-06 Jan Beulich <jbeulich@suse.com>
1297
1298 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1299 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1300 register and memory source templates. Replace VexW= by VexW*
1301 where applicable.
1302 * i386-tbl.h: Re-generate.
1303
4873e243
JB		 13042020-03-06 Jan Beulich <jbeulich@suse.com>
1305
1306 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1307 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1308 * i386-tbl.h: Re-generate.
1309
672a349b
JB		 13102020-03-06 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1313 * i386-tbl.h: Re-generate.
1314
4ed21b58
JB		 13152020-03-06 Jan Beulich <jbeulich@suse.com>
1316
1317 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1318 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1319 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1320 VexW0 on SSE2AVX variants.
1321 (vmovq): Drop NoRex64 from XMM/XMM variants.
1322 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1323 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1324 applicable use VexW0.
1325 * i386-tbl.h: Re-generate.
1326
643bb870
JB		 13272020-03-06 Jan Beulich <jbeulich@suse.com>
1328
1329 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1330 * i386-opc.h (Rex64): Delete.
1331 (struct i386_opcode_modifier): Remove rex64 field.
1332 * i386-opc.tbl (crc32): Drop Rex64.
1333 Replace Rex64 with Size64 everywhere else.
1334 * i386-tbl.h: Re-generate.
1335
a23b33b3
JB		 13362020-03-06 Jan Beulich <jbeulich@suse.com>
1337
1338 * i386-dis.c (OP_E_memory): Exclude recording of used address
1339 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1340 addressed memory operands for MPX insns.
1341
a0497384
JB		 13422020-03-06 Jan Beulich <jbeulich@suse.com>
1343
1344 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1345 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1346 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1347 (ptwrite): Split into non-64-bit and 64-bit forms.
1348 * i386-tbl.h: Re-generate.
1349
b630c145
JB		 13502020-03-06 Jan Beulich <jbeulich@suse.com>
1351
1352 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1353 template.
1354 * i386-tbl.h: Re-generate.
1355
a847e322
JB		 13562020-03-04 Jan Beulich <jbeulich@suse.com>
1357
1358 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1359 (prefix_table): Move vmmcall here. Add vmgexit.
1360 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1361 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1362 (cpu_flags): Add CpuSEV_ES entry.
1363 * i386-opc.h (CpuSEV_ES): New.
1364 (union i386_cpu_flags): Add cpusev_es field.
1365 * i386-opc.tbl (vmgexit): New.
1366 * i386-init.h, i386-tbl.h: Re-generate.
1367
3cd7f3e3
L		 13682020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1369
1370 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1371 with MnemonicSize.
1372 * i386-opc.h (IGNORESIZE): New.
1373 (DEFAULTSIZE): Likewise.
1374 (IgnoreSize): Removed.
1375 (DefaultSize): Likewise.
1376 (MnemonicSize): New.
1377 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1378 mnemonicsize.
1379 * i386-opc.tbl (IgnoreSize): New.
1380 (DefaultSize): Likewise.
1381 * i386-tbl.h: Regenerated.
1382
b8ba1385
SB		 13832020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1384
1385 PR 25627
1386 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1387 instructions.
1388
10d97a0f
L		 13892020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1390
1391 PR gas/25622
1392 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1393 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1394 * i386-tbl.h: Regenerated.
1395
dc1e8a47
AM		 13962020-02-26 Alan Modra <amodra@gmail.com>
1397
1398 * aarch64-asm.c: Indent labels correctly.
1399 * aarch64-dis.c: Likewise.
1400 * aarch64-gen.c: Likewise.
1401 * aarch64-opc.c: Likewise.
1402 * alpha-dis.c: Likewise.
1403 * i386-dis.c: Likewise.
1404 * nds32-asm.c: Likewise.
1405 * nfp-dis.c: Likewise.
1406 * visium-dis.c: Likewise.
1407
265b4673
CZ		 14082020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1409
1410 * arc-regs.h (int_vector_base): Make it available for all ARC
1411 CPUs.
1412
bd0cf5a6
NC		 14132020-02-20 Nelson Chu <nelson.chu@sifive.com>
1414
1415 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1416 changed.
1417
fa164239
JW		 14182020-02-19 Nelson Chu <nelson.chu@sifive.com>
1419
1420 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1421 c.mv/c.li if rs1 is zero.
1422
272a84b1
L		 14232020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1424
1425 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1426 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1427 CPU_POPCNT_FLAGS.
1428 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1429 * i386-opc.h (CpuABM): Removed.
1430 (CpuPOPCNT): New.
1431 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1432 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1433 popcnt. Remove CpuABM from lzcnt.
1434 * i386-init.h: Regenerated.
1435 * i386-tbl.h: Likewise.
1436
1f730c46
JB		 14372020-02-17 Jan Beulich <jbeulich@suse.com>
1438
1439 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1440 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1441 VexW1 instead of open-coding them.
1442 * i386-tbl.h: Re-generate.
1443
c8f8eebc
JB		 14442020-02-17 Jan Beulich <jbeulich@suse.com>
1445
1446 * i386-opc.tbl (AddrPrefixOpReg): Define.
1447 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1448 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1449 templates. Drop NoRex64.
1450 * i386-tbl.h: Re-generate.
1451
b9915cbc
JB		 14522020-02-17 Jan Beulich <jbeulich@suse.com>
1453
1454 PR gas/6518
1455 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1456 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1457 into Intel syntax instance (with Unpsecified) and AT&T one
1458 (without).
1459 (vcvtneps2bf16): Likewise, along with folding the two so far
1460 separate ones.
1461 * i386-tbl.h: Re-generate.
1462
ce504911
L		 14632020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1464
1465 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1466 CPU_ANY_SSE4A_FLAGS.
1467
dabec65d
AM		 14682020-02-17 Alan Modra <amodra@gmail.com>
1469
1470 * i386-gen.c (cpu_flag_init): Correct last change.
1471
af5c13b0
L		 14722020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1473
1474 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1475 CPU_ANY_SSE4_FLAGS.
1476
6867aac0
L		 14772020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1478
1479 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1480 (movzx): Likewise.
1481
65fca059
JB		 14822020-02-14 Jan Beulich <jbeulich@suse.com>
1483
1484 PR gas/25438
1485 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1486 destination for Cpu64-only variant.
1487 (movzx): Fold patterns.
1488 * i386-tbl.h: Re-generate.
1489
7deea9aa
JB		 14902020-02-13 Jan Beulich <jbeulich@suse.com>
1491
1492 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1493 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1494 CPU_ANY_SSE4_FLAGS entry.
1495 * i386-init.h: Re-generate.
1496
6c0946d0
JB		 14972020-02-12 Jan Beulich <jbeulich@suse.com>
1498
1499 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1500 with Unspecified, making the present one AT&T syntax only.
1501 * i386-tbl.h: Re-generate.
1502
ddb56fe6
JB		 15032020-02-12 Jan Beulich <jbeulich@suse.com>
1504
1505 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1506 * i386-tbl.h: Re-generate.
1507
5990e377
JB		 15082020-02-12 Jan Beulich <jbeulich@suse.com>
1509
1510 PR gas/24546
1511 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1512 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1513 Amd64 and Intel64 templates.
1514 (call, jmp): Likewise for far indirect variants. Dro
1515 Unspecified.
1516 * i386-tbl.h: Re-generate.
1517
50128d0c
JB		 15182020-02-11 Jan Beulich <jbeulich@suse.com>
1519
1520 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1521 * i386-opc.h (ShortForm): Delete.
1522 (struct i386_opcode_modifier): Remove shortform field.
1523 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1524 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1525 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1526 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1527 Drop ShortForm.
1528 * i386-tbl.h: Re-generate.
1529
1e05b5c4
JB		 15302020-02-11 Jan Beulich <jbeulich@suse.com>
1531
1532 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1533 fucompi): Drop ShortForm from operand-less templates.
1534 * i386-tbl.h: Re-generate.
1535
2f5dd314
AM		 15362020-02-11 Alan Modra <amodra@gmail.com>
1537
1538 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1539 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1540 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1541 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1542 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1543
5aae9ae9
MM		 15442020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1545
1546 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1547 (cde_opcodes): Add VCX* instructions.
1548
4934a27c
MM		 15492020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1550 Matthew Malcomson <matthew.malcomson@arm.com>
1551
1552 * arm-dis.c (struct cdeopcode32): New.
1553 (CDE_OPCODE): New macro.
1554 (cde_opcodes): New disassembly table.
1555 (regnames): New option to table.
1556 (cde_coprocs): New global variable.
1557 (print_insn_cde): New
1558 (print_insn_thumb32): Use print_insn_cde.
1559 (parse_arm_disassembler_options): Parse coprocN args.
1560
4b5aaf5f
L		 15612020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1562
1563 PR gas/25516
1564 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1565 with ISA64.
1566 * i386-opc.h (AMD64): Removed.
1567 (Intel64): Likewose.
1568 (AMD64): New.
1569 (INTEL64): Likewise.
1570 (INTEL64ONLY): Likewise.
1571 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1572 * i386-opc.tbl (Amd64): New.
1573 (Intel64): Likewise.
1574 (Intel64Only): Likewise.
1575 Replace AMD64 with Amd64. Update sysenter/sysenter with
1576 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1577 * i386-tbl.h: Regenerated.
1578
9fc0b501
SB		 15792020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1580
1581 PR 25469
1582 * z80-dis.c: Add support for GBZ80 opcodes.
1583
c5d7be0c
AM		 15842020-02-04 Alan Modra <amodra@gmail.com>
1585
1586 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1587
44e4546f
AM		 15882020-02-03 Alan Modra <amodra@gmail.com>
1589
1590 * m32c-ibld.c: Regenerate.
1591
b2b1453a
AM		 15922020-02-01 Alan Modra <amodra@gmail.com>
1593
1594 * frv-ibld.c: Regenerate.
1595
4102be5c
JB		 15962020-01-31 Jan Beulich <jbeulich@suse.com>
1597
1598 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1599 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1600 (OP_E_memory): Replace xmm_mdq_mode case label by
1601 vex_scalar_w_dq_mode one.
1602 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1603
825bd36c
JB		 16042020-01-31 Jan Beulich <jbeulich@suse.com>
1605
1606 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1607 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1608 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1609 (intel_operand_size): Drop vex_w_dq_mode case label.
1610
c3036ed0
RS		 16112020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1612
1613 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1614 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1615
0c115f84
AM		 16162020-01-30 Alan Modra <amodra@gmail.com>
1617
1618 * m32c-ibld.c: Regenerate.
1619
bd434cc4
JM		 16202020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1621
1622 * bpf-opc.c: Regenerate.
1623
aeab2b26
JB		 16242020-01-30 Jan Beulich <jbeulich@suse.com>
1625
1626 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1627 (dis386): Use them to replace C2/C3 table entries.
1628 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1629 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1630 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1631 * i386-tbl.h: Re-generate.
1632
62b3f548
JB		 16332020-01-30 Jan Beulich <jbeulich@suse.com>
1634
1635 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1636 forms.
1637 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1638 DefaultSize.
1639 * i386-tbl.h: Re-generate.
1640
1bd8ae10
AM		 16412020-01-30 Alan Modra <amodra@gmail.com>
1642
1643 * tic4x-dis.c (tic4x_dp): Make unsigned.
1644
bc31405e
L		 16452020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1646 Jan Beulich <jbeulich@suse.com>
1647
1648 PR binutils/25445
1649 * i386-dis.c (MOVSXD_Fixup): New function.
1650 (movsxd_mode): New enum.
1651 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1652 (intel_operand_size): Handle movsxd_mode.
1653 (OP_E_register): Likewise.
1654 (OP_G): Likewise.
1655 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1656 register on movsxd. Add movsxd with 16-bit destination register
1657 for AMD64 and Intel64 ISAs.
1658 * i386-tbl.h: Regenerated.
1659
7568c93b
TC		 16602020-01-27 Tamar Christina <tamar.christina@arm.com>
1661
1662 PR 25403
1663 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1664 * aarch64-asm-2.c: Regenerate
1665 * aarch64-dis-2.c: Likewise.
1666 * aarch64-opc-2.c: Likewise.
1667
c006a730
JB		 16682020-01-21 Jan Beulich <jbeulich@suse.com>
1669
1670 * i386-opc.tbl (sysret): Drop DefaultSize.
1671 * i386-tbl.h: Re-generate.
1672
c906a69a
JB		 16732020-01-21 Jan Beulich <jbeulich@suse.com>
1674
1675 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1676 Dword.
1677 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1678 * i386-tbl.h: Re-generate.
1679
26916852
NC		 16802020-01-20 Nick Clifton <nickc@redhat.com>
1681
1682 * po/de.po: Updated German translation.
1683 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1684 * po/uk.po: Updated Ukranian translation.
1685
4d6cbb64
AM		 16862020-01-20 Alan Modra <amodra@gmail.com>
1687
1688 * hppa-dis.c (fput_const): Remove useless cast.
1689
2bddb71a
AM		 16902020-01-20 Alan Modra <amodra@gmail.com>
1691
1692 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1693
1b1bb2c6
NC		 16942020-01-18 Nick Clifton <nickc@redhat.com>
1695
1696 * configure: Regenerate.
1697 * po/opcodes.pot: Regenerate.
1698
ae774686
NC		 16992020-01-18 Nick Clifton <nickc@redhat.com>
1700
1701 Binutils 2.34 branch created.
1702
07f1f3aa
CB		 17032020-01-17 Christian Biesinger <cbiesinger@google.com>
1704
1705 * opintl.h: Fix spelling error (seperate).
1706
42e04b36
L		 17072020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1708
1709 * i386-opc.tbl: Add {vex} pseudo prefix.
1710 * i386-tbl.h: Regenerated.
1711
2da2eaf4
AV		 17122020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1713
1714 PR 25376
1715 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1716 (neon_opcodes): Likewise.
1717 (select_arm_features): Make sure we enable MVE bits when selecting
1718 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1719 any architecture.
1720
d0849eed
JB		 17212020-01-16 Jan Beulich <jbeulich@suse.com>
1722
1723 * i386-opc.tbl: Drop stale comment from XOP section.
1724
9cf70a44
JB		 17252020-01-16 Jan Beulich <jbeulich@suse.com>
1726
1727 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1728 (extractps): Add VexWIG to SSE2AVX forms.
1729 * i386-tbl.h: Re-generate.
1730
4814632e
JB		 17312020-01-16 Jan Beulich <jbeulich@suse.com>
1732
1733 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1734 Size64 from and use VexW1 on SSE2AVX forms.
1735 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1736 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1737 * i386-tbl.h: Re-generate.
1738
aad09917
AM		 17392020-01-15 Alan Modra <amodra@gmail.com>
1740
1741 * tic4x-dis.c (tic4x_version): Make unsigned long.
1742 (optab, optab_special, registernames): New file scope vars.
1743 (tic4x_print_register): Set up registernames rather than
1744 malloc'd registertable.
1745 (tic4x_disassemble): Delete optable and optable_special. Use
1746 optab and optab_special instead. Throw away old optab,
1747 optab_special and registernames when info->mach changes.
1748
7a6bf3be
SB		 17492020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1750
1751 PR 25377
1752 * z80-dis.c (suffix): Use .db instruction to generate double
1753 prefix.
1754
ca1eaac0
AM		 17552020-01-14 Alan Modra <amodra@gmail.com>
1756
1757 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1758 values to unsigned before shifting.
1759
1d67fe3b
TT		 17602020-01-13 Thomas Troeger <tstroege@gmx.de>
1761
1762 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1763 flow instructions.
1764 (print_insn_thumb16, print_insn_thumb32): Likewise.
1765 (print_insn): Initialize the insn info.
1766 * i386-dis.c (print_insn): Initialize the insn info fields, and
1767 detect jumps.
1768
5e4f7e05
CZ		 17692012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1770
1771 * arc-opc.c (C_NE): Make it required.
1772
b9fe6b8a
CZ		 17732012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1774
1775 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1776 reserved register name.
1777
90dee485
AM		 17782020-01-13 Alan Modra <amodra@gmail.com>
1779
1780 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1781 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1782
febda64f
AM		 17832020-01-13 Alan Modra <amodra@gmail.com>
1784
1785 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1786 result of wasm_read_leb128 in a uint64_t and check that bits
1787 are not lost when copying to other locals. Use uint32_t for
1788 most locals. Use PRId64 when printing int64_t.
1789
df08b588
AM		 17902020-01-13 Alan Modra <amodra@gmail.com>
1791
1792 * score-dis.c: Formatting.
1793 * score7-dis.c: Formatting.
1794
b2c759ce
AM		 17952020-01-13 Alan Modra <amodra@gmail.com>
1796
1797 * score-dis.c (print_insn_score48): Use unsigned variables for
1798 unsigned values. Don't left shift negative values.
1799 (print_insn_score32): Likewise.
1800 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1801
5496abe1
AM		 18022020-01-13 Alan Modra <amodra@gmail.com>
1803
1804 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1805
202e762b
AM		 18062020-01-13 Alan Modra <amodra@gmail.com>
1807
1808 * fr30-ibld.c: Regenerate.
1809
7ef412cf
AM		 18102020-01-13 Alan Modra <amodra@gmail.com>
1811
1812 * xgate-dis.c (print_insn): Don't left shift signed value.
1813 (ripBits): Formatting, use 1u.
1814
7f578b95
AM		 18152020-01-10 Alan Modra <amodra@gmail.com>
1816
1817 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1818 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1819
441af85b
AM		 18202020-01-10 Alan Modra <amodra@gmail.com>
1821
1822 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1823 and XRREG value earlier to avoid a shift with negative exponent.
1824 * m10200-dis.c (disassemble): Similarly.
1825
bce58db4
NC		 18262020-01-09 Nick Clifton <nickc@redhat.com>
1827
1828 PR 25224
1829 * z80-dis.c (ld_ii_ii): Use correct cast.
1830
40c75bc8
SB		 18312020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1832
1833 PR 25224
1834 * z80-dis.c (ld_ii_ii): Use character constant when checking
1835 opcode byte value.
1836
d835a58b
JB		 18372020-01-09 Jan Beulich <jbeulich@suse.com>
1838
1839 * i386-dis.c (SEP_Fixup): New.
1840 (SEP): Define.
1841 (dis386_twobyte): Use it for sysenter/sysexit.
1842 (enum x86_64_isa): Change amd64 enumerator to value 1.
1843 (OP_J): Compare isa64 against intel64 instead of amd64.
1844 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1845 forms.
1846 * i386-tbl.h: Re-generate.
1847
030a2e78
AM		 18482020-01-08 Alan Modra <amodra@gmail.com>
1849
1850 * z8k-dis.c: Include libiberty.h
1851 (instr_data_s): Make max_fetched unsigned.
1852 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1853 Don't exceed byte_info bounds.
1854 (output_instr): Make num_bytes unsigned.
1855 (unpack_instr): Likewise for nibl_count and loop.
1856 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1857 idx unsigned.
1858 * z8k-opc.h: Regenerate.
1859
bb82aefe
SV		 18602020-01-07 Shahab Vahedi <shahab@synopsys.com>
1861
1862 * arc-tbl.h (llock): Use 'LLOCK' as class.
1863 (llockd): Likewise.
1864 (scond): Use 'SCOND' as class.
1865 (scondd): Likewise.
1866 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1867 (scondd): Likewise.
1868
cc6aa1a6
AM		 18692020-01-06 Alan Modra <amodra@gmail.com>
1870
1871 * m32c-ibld.c: Regenerate.
1872
660e62b1
AM		 18732020-01-06 Alan Modra <amodra@gmail.com>
1874
1875 PR 25344
1876 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1877 Peek at next byte to prevent recursion on repeated prefix bytes.
1878 Ensure uninitialised "mybuf" is not accessed.
1879 (print_insn_z80): Don't zero n_fetch and n_used here,..
1880 (print_insn_z80_buf): ..do it here instead.
1881
c9ae58fe
AM		 18822020-01-04 Alan Modra <amodra@gmail.com>
1883
1884 * m32r-ibld.c: Regenerate.
1885
5f57d4ec
AM		 18862020-01-04 Alan Modra <amodra@gmail.com>
1887
1888 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1889
2c5c1196
AM		 18902020-01-04 Alan Modra <amodra@gmail.com>
1891
1892 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1893
2e98c6c5
AM		 18942020-01-04 Alan Modra <amodra@gmail.com>
1895
1896 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1897
567dfba2
JB		 18982020-01-03 Jan Beulich <jbeulich@suse.com>
1899
5437a02a
JB		 1900 * aarch64-tbl.h (aarch64_opcode_table): Use
1901 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1902
19032020-01-03 Jan Beulich <jbeulich@suse.com>
1904
1905 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1906 forms of SUDOT and USDOT.
1907
8c45011a
JB		 19082020-01-03 Jan Beulich <jbeulich@suse.com>
1909
5437a02a 1910 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1911 uzip{1,2}.
1912 * opcodes/aarch64-dis-2.c: Re-generate.
1913
f4950f76
JB		 19142020-01-03 Jan Beulich <jbeulich@suse.com>
1915
5437a02a 1916 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1917 FMMLA encoding.
1918 * opcodes/aarch64-dis-2.c: Re-generate.
1919
6655dba2
SB		 19202020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1921
1922 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1923
b14ce8bf
AM		 19242020-01-01 Alan Modra <amodra@gmail.com>
1925
1926 Update year range in copyright notice of all files.
1927
0b114740 1928For older changes see ChangeLog-2019
3499769a 1929\f
0b114740 1930Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1931
1932Copying and distribution of this file, with or without modification,
1933are permitted in any medium without royalty provided the copyright
1934notice and this notice are preserved.
1935
1936Local Variables:
1937mode: change-log
1938left-margin: 8
1939fill-column: 74
1940version-control: never
1941End:
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