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2002-06-04 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
d3eb724f
CD		 12002-06-04 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c: Add an FSF Copyright notice to this file.
4
ba46ddd0
CD		 52002-06-04 Chris Demetriou <cgd@broadcom.com>
6 Ed Satterthwaite <ehs@broadcom.com>
7
8 * cp1.c (Infinity): Remove.
9 * sim-main.h (Infinity): Likewise.
10
11 * cp1.c (fp_unary, fp_binary): New functions.
12 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
13 (fp_sqrt): New functions, implemented in terms of the above.
14 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
15 (Recip, SquareRoot): Remove (replaced by functions above).
16 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
17 (fp_recip, fp_sqrt): New prototypes.
18 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
19 (Recip, SquareRoot): Replace prototypes with #defines which
20 invoke the functions above.
21
18d8a52d
CD		 222002-06-03 Chris Demetriou <cgd@broadcom.com>
23
24 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
25 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
26 file, remove PARAMS from prototypes.
27 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
28 simulator state arguments.
29 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
30 pass simulator state arguments.
31 * cp1.c (SD): Redefine as CPU_STATE(cpu).
32 (store_fpr, convert): Remove 'sd' argument.
33 (value_fpr): Likewise. Convert to use 'SD' instead.
34
0f154cbd
CD		 352002-06-03 Chris Demetriou <cgd@broadcom.com>
36
37 * cp1.c (Min, Max): Remove #if 0'd functions.
38 * sim-main.h (Min, Max): Remove.
39
e80fc152
CD		 402002-06-03 Chris Demetriou <cgd@broadcom.com>
41
42 * cp1.c: fix formatting of switch case and default labels.
43 * interp.c: Likewise.
44 * sim-main.c: Likewise.
45
bad673a9
CD		 462002-06-03 Chris Demetriou <cgd@broadcom.com>
47
48 * cp1.c: Clean up comments which describe FP formats.
49 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
50
7cbea089
CD		 512002-06-03 Chris Demetriou <cgd@broadcom.com>
52 Ed Satterthwaite <ehs@broadcom.com>
53
54 * configure.in (mipsisa64sb1*-*-*): New target for supporting
55 Broadcom SiByte SB-1 processor configurations.
56 * configure: Regenerate.
57 * sb1.igen: New file.
58 * mips.igen: Include sb1.igen.
59 (sb1): New model.
60 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
61 * mdmx.igen: Add "sb1" model to all appropriate functions and
62 instructions.
63 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
64 (ob_func, ob_acc): Reference the above.
65 (qh_acc): Adjust to keep the same size as ob_acc.
66 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
67 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
68
909daa82
CD		 692002-06-03 Chris Demetriou <cgd@broadcom.com>
70
71 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
72
f4f1b9f1
CD		 732002-06-02 Chris Demetriou <cgd@broadcom.com>
74 Ed Satterthwaite <ehs@broadcom.com>
75
76 * mips.igen (mdmx): New (pseudo-)model.
77 * mdmx.c, mdmx.igen: New files.
78 * Makefile.in (SIM_OBJS): Add mdmx.o.
79 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
80 New typedefs.
81 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
82 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
83 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
84 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
85 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
86 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
87 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
88 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
89 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
90 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
91 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
92 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
93 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
94 (qh_fmtsel): New macros.
95 (_sim_cpu): New member "acc".
96 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
97 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
98
5accf1ff
CD		 992002-05-01 Chris Demetriou <cgd@broadcom.com>
100
101 * interp.c: Use 'deprecated' rather than 'depreciated.'
102 * sim-main.h: Likewise.
103
402586aa
CD		 1042002-05-01 Chris Demetriou <cgd@broadcom.com>
105
106 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
107 which wouldn't compile anyway.
108 * sim-main.h (unpredictable_action): New function prototype.
109 (Unpredictable): Define to call igen function unpredictable().
110 (NotWordValue): New macro to call igen function not_word_value().
111 (UndefinedResult): Remove.
112 * interp.c (undefined_result): Remove.
113 (unpredictable_action): New function.
114 * mips.igen (not_word_value, unpredictable): New functions.
115 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
116 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
117 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
118 NotWordValue() to check for unpredictable inputs, then
119 Unpredictable() to handle them.
120
c9b9995a
CD		 1212002-02-24 Chris Demetriou <cgd@broadcom.com>
122
123 * mips.igen: Fix formatting of calls to Unpredictable().
124
e1015982
AC		 1252002-04-20 Andrew Cagney <ac131313@redhat.com>
126
127 * interp.c (sim_open): Revert previous change.
128
b882a66b
AO		 1292002-04-18 Alexandre Oliva <aoliva@redhat.com>
130
131 * interp.c (sim_open): Disable chunk of code that wrote code in
132 vector table entries.
133
c429b7dd
CD		 1342002-03-19 Chris Demetriou <cgd@broadcom.com>
135
136 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
137 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
138 unused definitions.
139
37d146fa
CD		 1402002-03-19 Chris Demetriou <cgd@broadcom.com>
141
142 * cp1.c: Fix many formatting issues.
143
07892c0b
CD		 1442002-03-19 Chris G. Demetriou <cgd@broadcom.com>
145
146 * cp1.c (fpu_format_name): New function to replace...
147 (DOFMT): This. Delete, and update all callers.
148 (fpu_rounding_mode_name): New function to replace...
149 (RMMODE): This. Delete, and update all callers.
150
487f79b7
CD		 1512002-03-19 Chris G. Demetriou <cgd@broadcom.com>
152
153 * interp.c: Move FPU support routines from here to...
154 * cp1.c: Here. New file.
155 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
156 (cp1.o): New target.
157
1e799e28
CD		 1582002-03-12 Chris Demetriou <cgd@broadcom.com>
159
160 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
161 * mips.igen (mips32, mips64): New models, add to all instructions
162 and functions as appropriate.
163 (loadstore_ea, check_u64): New variant for model mips64.
164 (check_fmt_p): New variant for models mipsV and mips64, remove
165 mipsV model marking fro other variant.
166 (SLL) Rename to...
167 (SLLa) this.
168 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
169 for mips32 and mips64.
170 (DCLO, DCLZ): New instructions for mips64.
171
82f728db
CD		 1722002-03-07 Chris Demetriou <cgd@broadcom.com>
173
174 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
175 immediate or code as a hex value with the "%#lx" format.
176 (ANDI): Likewise, and fix printed instruction name.
177
b96e7ef1
CD		 1782002-03-05 Chris Demetriou <cgd@broadcom.com>
179
180 * sim-main.h (UndefinedResult, Unpredictable): New macros
181 which currently do nothing.
182
d35d4f70
CD		 1832002-03-05 Chris Demetriou <cgd@broadcom.com>
184
185 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
186 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
187 (status_CU3): New definitions.
188
189 * sim-main.h (ExceptionCause): Add new values for MIPS32
190 and MIPS64: MDMX, MCheck, CacheErr. Update comments
191 for DebugBreakPoint and NMIReset to note their status in
192 MIPS32 and MIPS64.
193 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
194 (SignalExceptionCacheErr): New exception macros.
195
3ad6f714
CD		 1962002-03-05 Chris Demetriou <cgd@broadcom.com>
197
198 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
199 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
200 is always enabled.
201 (SignalExceptionCoProcessorUnusable): Take as argument the
202 unusable coprocessor number.
203
86b77b47
CD		 2042002-03-05 Chris Demetriou <cgd@broadcom.com>
205
206 * mips.igen: Fix formatting of all SignalException calls.
207
97a88e93 2082002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 209
210 * sim-main.h (SIGNEXTEND): Remove.
211
97a88e93 2122002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 213
214 * mips.igen: Remove gencode comment from top of file, fix
215 spelling in another comment.
216
97a88e93 2172002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 218
219 * mips.igen (check_fmt, check_fmt_p): New functions to check
220 whether specific floating point formats are usable.
221 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
222 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
223 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
224 Use the new functions.
225 (do_c_cond_fmt): Remove format checks...
226 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
227
97a88e93 2282002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 229
230 * mips.igen: Fix formatting of check_fpu calls.
231
41774c9d
CD		 2322002-03-03 Chris Demetriou <cgd@broadcom.com>
233
234 * mips.igen (FLOOR.L.fmt): Store correct destination register.
235
4a0bd876
CD		 2362002-03-03 Chris Demetriou <cgd@broadcom.com>
237
238 * mips.igen: Remove whitespace at end of lines.
239
09297648
CD		 2402002-03-02 Chris Demetriou <cgd@broadcom.com>
241
242 * mips.igen (loadstore_ea): New function to do effective
243 address calculations.
244 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
245 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
246 CACHE): Use loadstore_ea to do effective address computations.
247
043b7057
CD		 2482002-03-02 Chris Demetriou <cgd@broadcom.com>
249
250 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
251 * mips.igen (LL, CxC1, MxC1): Likewise.
252
c1e8ada4
CD		 2532002-03-02 Chris Demetriou <cgd@broadcom.com>
254
255 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
256 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
257 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
258 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
259 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
260 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
261 Don't split opcode fields by hand, use the opcode field values
262 provided by igen.
263
3e1dca16
CD		 2642002-03-01 Chris Demetriou <cgd@broadcom.com>
265
266 * mips.igen (do_divu): Fix spacing.
267
268 * mips.igen (do_dsllv): Move to be right before DSLLV,
269 to match the rest of the do_<shift> functions.
270
fff8d27d
CD		 2712002-03-01 Chris Demetriou <cgd@broadcom.com>
272
273 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
274 DSRL32, do_dsrlv): Trace inputs and results.
275
0d3e762b
CD		 2762002-03-01 Chris Demetriou <cgd@broadcom.com>
277
278 * mips.igen (CACHE): Provide instruction-printing string.
279
280 * interp.c (signal_exception): Comment tokens after #endif.
281
eb5fcf93
CD		 2822002-02-28 Chris Demetriou <cgd@broadcom.com>
283
284 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
285 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
286 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
287 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
288 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
289 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
290 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
291 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
292
bb22bd7d
CD		 2932002-02-28 Chris Demetriou <cgd@broadcom.com>
294
295 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
296 instruction-printing string.
297 (LWU): Use '64' as the filter flag.
298
91a177cf
CD		 2992002-02-28 Chris Demetriou <cgd@broadcom.com>
300
301 * mips.igen (SDXC1): Fix instruction-printing string.
302
387f484a
CD		 3032002-02-28 Chris Demetriou <cgd@broadcom.com>
304
305 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
306 filter flags "32,f".
307
3d81f391
CD		 3082002-02-27 Chris Demetriou <cgd@broadcom.com>
309
310 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
311 as the filter flag.
312
af5107af
CD		 3132002-02-27 Chris Demetriou <cgd@broadcom.com>
314
315 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
316 add a comma) so that it more closely match the MIPS ISA
317 documentation opcode partitioning.
318 (PREF): Put useful names on opcode fields, and include
319 instruction-printing string.
320
ca971540
CD		 3212002-02-27 Chris Demetriou <cgd@broadcom.com>
322
323 * mips.igen (check_u64): New function which in the future will
324 check whether 64-bit instructions are usable and signal an
325 exception if not. Currently a no-op.
326 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
327 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
328 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
329 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
330
331 * mips.igen (check_fpu): New function which in the future will
332 check whether FPU instructions are usable and signal an exception
333 if not. Currently a no-op.
334 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
335 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
336 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
337 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
338 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
339 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
340 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
341 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
342
1c47a468
CD		 3432002-02-27 Chris Demetriou <cgd@broadcom.com>
344
345 * mips.igen (do_load_left, do_load_right): Move to be immediately
346 following do_load.
347 (do_store_left, do_store_right): Move to be immediately following
348 do_store.
349
603a98e7
CD		 3502002-02-27 Chris Demetriou <cgd@broadcom.com>
351
352 * mips.igen (mipsV): New model name. Also, add it to
353 all instructions and functions where it is appropriate.
354
c5d00cc7
CD		 3552002-02-18 Chris Demetriou <cgd@broadcom.com>
356
357 * mips.igen: For all functions and instructions, list model
358 names that support that instruction one per line.
359
074e9cb8
CD		 3602002-02-11 Chris Demetriou <cgd@broadcom.com>
361
362 * mips.igen: Add some additional comments about supported
363 models, and about which instructions go where.
364 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
365 order as is used in the rest of the file.
366
9805e229
CD		 3672002-02-11 Chris Demetriou <cgd@broadcom.com>
368
369 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
370 indicating that ALU32_END or ALU64_END are there to check
371 for overflow.
372 (DADD): Likewise, but also remove previous comment about
373 overflow checking.
374
f701dad2
CD		 3752002-02-10 Chris Demetriou <cgd@broadcom.com>
376
377 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
378 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
379 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
380 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
381 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
382 fields (i.e., add and move commas) so that they more closely
383 match the MIPS ISA documentation opcode partitioning.
384
3852002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 386
387 * mips.igen (ADDI): Print immediate value.
388 (BREAK): Print code.
389 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
390 (SLL): Print "nop" specially, and don't run the code
391 that does the shift for the "nop" case.
392
9e52972e
FF		 3932001-11-17 Fred Fish <fnf@redhat.com>
394
395 * sim-main.h (float_operation): Move enum declaration outside
396 of _sim_cpu struct declaration.
397
c0efbca4
JB		 3982001-04-12 Jim Blandy <jimb@redhat.com>
399
400 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
401 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
402 set of the FCSR.
403 * sim-main.h (COCIDX): Remove definition; this isn't supported by
404 PENDING_FILL, and you can get the intended effect gracefully by
405 calling PENDING_SCHED directly.
406
fb891446
BE		 4072001-02-23 Ben Elliston <bje@redhat.com>
408
409 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
410 already defined elsewhere.
411
8030f857
BE		 4122001-02-19 Ben Elliston <bje@redhat.com>
413
414 * sim-main.h (sim_monitor): Return an int.
415 * interp.c (sim_monitor): Add return values.
416 (signal_exception): Handle error conditions from sim_monitor.
417
56b48a7a
CD		 4182001-02-08 Ben Elliston <bje@redhat.com>
419
420 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
421 (store_memory): Likewise, pass cia to sim_core_write*.
422
d3ee60d9
FCE		 4232000-10-19 Frank Ch. Eigler <fche@redhat.com>
424
425 On advice from Chris G. Demetriou <cgd@sibyte.com>:
426 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
427
071da002
AC		 428Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
429
430 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
431 * Makefile.in: Don't delete *.igen when cleaning directory.
432
a28c02cd
AC		 433Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
434
435 * m16.igen (break): Call SignalException not sim_engine_halt.
436
80ee11fa
AC		 437Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
438
439 From Jason Eckhardt:
440 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
441
673388c0
AC		 442Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
443
444 * mips.igen (MxC1, DMxC1): Fix printf formatting.
445
4c0deff4
NC		 4462000-05-24 Michael Hayes <mhayes@cygnus.com>
447
448 * mips.igen (do_dmultx): Fix typo.
449
eb2d80b4
AC		 450Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
451
452 * configure: Regenerated to track ../common/aclocal.m4 changes.
453
dd37a34b
AC		 454Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
455
456 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
457
4c0deff4
NC		 4582000-04-12 Frank Ch. Eigler <fche@redhat.com>
459
460 * sim-main.h (GPR_CLEAR): Define macro.
461
e30db738
AC		 462Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
463
464 * interp.c (decode_coproc): Output long using %lx and not %s.
465
cb7450ea
FCE		 4662000-03-21 Frank Ch. Eigler <fche@redhat.com>
467
468 * interp.c (sim_open): Sort & extend dummy memory regions for
469 --board=jmr3904 for eCos.
470
a3027dd7
FCE		 4712000-03-02 Frank Ch. Eigler <fche@redhat.com>
472
473 * configure: Regenerated.
474
475Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
476
477 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
478 calls, conditional on the simulator being in verbose mode.
479
dfcd3bfb
JM		 480Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
481
482 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
483 cache don't get ReservedInstruction traps.
484
c2d11a7d
JM		 4851999-11-29 Mark Salter <msalter@cygnus.com>
486
487 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
488 to clear status bits in sdisr register. This is how the hardware works.
489
490 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
491 being used by cygmon.
492
4ce44c66
JM		 4931999-11-11 Andrew Haley <aph@cygnus.com>
494
495 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
496 instructions.
497
cff3e48b
JM		 498Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
499
500 * mips.igen (MULT): Correct previous mis-applied patch.
501
d4f3574e
SS		 502Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
503
504 * mips.igen (delayslot32): Handle sequence like
505 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
506 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
507 (MULT): Actually pass the third register...
508
5091999-09-03 Mark Salter <msalter@cygnus.com>
510
511 * interp.c (sim_open): Added more memory aliases for additional
512 hardware being touched by cygmon on jmr3904 board.
513
514Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
515
516 * configure: Regenerated to track ../common/aclocal.m4 changes.
517
a0b3c4fd
JM		 518Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
519
520 * interp.c (sim_store_register): Handle case where client - GDB -
521 specifies that a 4 byte register is 8 bytes in size.
522 (sim_fetch_register): Ditto.
523
adf40b2e
JM		 5241999-07-14 Frank Ch. Eigler <fche@cygnus.com>
525
526 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
527 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
528 (idt_monitor_base): Base address for IDT monitor traps.
529 (pmon_monitor_base): Ditto for PMON.
530 (lsipmon_monitor_base): Ditto for LSI PMON.
531 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
532 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
533 (sim_firmware_command): New function.
534 (mips_option_handler): Call it for OPTION_FIRMWARE.
535 (sim_open): Allocate memory for idt_monitor region. If "--board"
536 option was given, add no monitor by default. Add BREAK hooks only if
537 monitors are also there.
538
43e526b9
JM		 539Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
540
541 * interp.c (sim_monitor): Flush output before reading input.
542
543Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
544
545 * tconfig.in (SIM_HANDLES_LMA): Always define.
546
547Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
548
549 From Mark Salter <msalter@cygnus.com>:
550 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
551 (sim_open): Add setup for BSP board.
552
9846de1b
JM		 553Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
554
555 * mips.igen (MULT, MULTU): Add syntax for two operand version.
556 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
557 them as unimplemented.
558
cd0fc7c3
SS		 5591999-05-08 Felix Lee <flee@cygnus.com>
560
561 * configure: Regenerated to track ../common/aclocal.m4 changes.
562
7a292a7a
SS		 5631999-04-21 Frank Ch. Eigler <fche@cygnus.com>
564
565 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
566
567Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
568
569 * configure.in: Any mips64vr5*-*-* target should have
570 -DTARGET_ENABLE_FR=1.
571 (default_endian): Any mips64vr*el-*-* target should default to
572 LITTLE_ENDIAN.
573 * configure: Re-generate.
574
5751999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
576
577 * mips.igen (ldl): Extend from _16_, not 32.
578
579Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
580
581 * interp.c (sim_store_register): Force registers written to by GDB
582 into an un-interpreted state.
583
c906108c
SS		 5841999-02-05 Frank Ch. Eigler <fche@cygnus.com>
585
586 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
587 CPU, start periodic background I/O polls.
588 (tx3904sio_poll): New function: periodic I/O poller.
589
5901998-12-30 Frank Ch. Eigler <fche@cygnus.com>
591
592 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
593
594Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
595
596 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
597 case statement.
598
5991998-12-29 Frank Ch. Eigler <fche@cygnus.com>
600
601 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
602 (load_word): Call SIM_CORE_SIGNAL hook on error.
603 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
604 starting. For exception dispatching, pass PC instead of NULL_CIA.
605 (decode_coproc): Use COP0_BADVADDR to store faulting address.
606 * sim-main.h (COP0_BADVADDR): Define.
607 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
608 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
609 (_sim_cpu): Add exc_* fields to store register value snapshots.
610 * mips.igen (*): Replace memory-related SignalException* calls
611 with references to SIM_CORE_SIGNAL hook.
612
613 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
614 fix.
615 * sim-main.c (*): Minor warning cleanups.
616
6171998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
618
619 * m16.igen (DADDIU5): Correct type-o.
620
621Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
622
623 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
624 variables.
625
626Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
627
628 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
629 to include path.
630 (interp.o): Add dependency on itable.h
631 (oengine.c, gencode): Delete remaining references.
632 (BUILT_SRC_FROM_GEN): Clean up.
633
6341998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
635
636 * vr4run.c: New.
637 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
638 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
639 tmp-run-hack) : New.
640 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
641 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
642 Drop the "64" qualifier to get the HACK generator working.
643 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
644 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
645 qualifier to get the hack generator working.
646 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
647 (DSLL): Use do_dsll.
648 (DSLLV): Use do_dsllv.
649 (DSRA): Use do_dsra.
650 (DSRL): Use do_dsrl.
651 (DSRLV): Use do_dsrlv.
652 (BC1): Move *vr4100 to get the HACK generator working.
653 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
654 get the HACK generator working.
655 (MACC) Rename to get the HACK generator working.
656 (DMACC,MACCS,DMACCS): Add the 64.
657
6581998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
659
660 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
661 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
662
6631998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
664
665 * mips/interp.c (DEBUG): Cleanups.
666
6671998-12-10 Frank Ch. Eigler <fche@cygnus.com>
668
669 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
670 (tx3904sio_tickle): fflush after a stdout character output.
671
6721998-12-03 Frank Ch. Eigler <fche@cygnus.com>
673
674 * interp.c (sim_close): Uninstall modules.
675
676Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
677
678 * sim-main.h, interp.c (sim_monitor): Change to global
679 function.
680
681Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
682
683 * configure.in (vr4100): Only include vr4100 instructions in
684 simulator.
685 * configure: Re-generate.
686 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
687
688Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
689
690 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
691 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
692 true alternative.
693
694 * configure.in (sim_default_gen, sim_use_gen): Replace with
695 sim_gen.
696 (--enable-sim-igen): Delete config option. Always using IGEN.
697 * configure: Re-generate.
698
699 * Makefile.in (gencode): Kill, kill, kill.
700 * gencode.c: Ditto.
701
702Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
703
704 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
705 bit mips16 igen simulator.
706 * configure: Re-generate.
707
708 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
709 as part of vr4100 ISA.
710 * vr.igen: Mark all instructions as 64 bit only.
711
712Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
713
714 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
715 Pacify GCC.
716
717Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
718
719 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
720 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
721 * configure: Re-generate.
722
723 * m16.igen (BREAK): Define breakpoint instruction.
724 (JALX32): Mark instruction as mips16 and not r3900.
725 * mips.igen (C.cond.fmt): Fix typo in instruction format.
726
727 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
728
729Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
730
731 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
732 insn as a debug breakpoint.
733
734 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
735 pending.slot_size.
736 (PENDING_SCHED): Clean up trace statement.
737 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
738 (PENDING_FILL): Delay write by only one cycle.
739 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
740
741 * sim-main.c (pending_tick): Clean up trace statements. Add trace
742 of pending writes.
743 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
744 32 & 64.
745 (pending_tick): Move incrementing of index to FOR statement.
746 (pending_tick): Only update PENDING_OUT after a write has occured.
747
748 * configure.in: Add explicit mips-lsi-* target. Use gencode to
749 build simulator.
750 * configure: Re-generate.
751
752 * interp.c (sim_engine_run OLD): Delete explicit call to
753 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
754
755Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
756
757 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
758 interrupt level number to match changed SignalExceptionInterrupt
759 macro.
760
761Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
762
763 * interp.c: #include "itable.h" if WITH_IGEN.
764 (get_insn_name): New function.
765 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
766 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
767
768Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
769
770 * configure: Rebuilt to inhale new common/aclocal.m4.
771
772Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
773
774 * dv-tx3904sio.c: Include sim-assert.h.
775
776Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
777
778 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
779 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
780 Reorganize target-specific sim-hardware checks.
781 * configure: rebuilt.
782 * interp.c (sim_open): For tx39 target boards, set
783 OPERATING_ENVIRONMENT, add tx3904sio devices.
784 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
785 ROM executables. Install dv-sockser into sim-modules list.
786
787 * dv-tx3904irc.c: Compiler warning clean-up.
788 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
789 frequent hw-trace messages.
790
791Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
792
793 * vr.igen (MulAcc): Identify as a vr4100 specific function.
794
795Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
796
797 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
798
799 * vr.igen: New file.
800 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
801 * mips.igen: Define vr4100 model. Include vr.igen.
802Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
803
804 * mips.igen (check_mf_hilo): Correct check.
805
806Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
807
808 * sim-main.h (interrupt_event): Add prototype.
809
810 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
811 register_ptr, register_value.
812 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
813
814 * sim-main.h (tracefh): Make extern.
815
816Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
817
818 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
819 Reduce unnecessarily high timer event frequency.
820 * dv-tx3904cpu.c: Ditto for interrupt event.
821
822Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
823
824 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
825 to allay warnings.
826 (interrupt_event): Made non-static.
827
828 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
829 interchange of configuration values for external vs. internal
830 clock dividers.
831
832Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
833
834 * mips.igen (BREAK): Moved code to here for
835 simulator-reserved break instructions.
836 * gencode.c (build_instruction): Ditto.
837 * interp.c (signal_exception): Code moved from here. Non-
838 reserved instructions now use exception vector, rather
839 than halting sim.
840 * sim-main.h: Moved magic constants to here.
841
842Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
843
844 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
845 register upon non-zero interrupt event level, clear upon zero
846 event value.
847 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
848 by passing zero event value.
849 (*_io_{read,write}_buffer): Endianness fixes.
850 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
851 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
852
853 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
854 serial I/O and timer module at base address 0xFFFF0000.
855
856Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
857
858 * mips.igen (SWC1) : Correct the handling of ReverseEndian
859 and BigEndianCPU.
860
861Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
862
863 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
864 parts.
865 * configure: Update.
866
867Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
868
869 * dv-tx3904tmr.c: New file - implements tx3904 timer.
870 * dv-tx3904{irc,cpu}.c: Mild reformatting.
871 * configure.in: Include tx3904tmr in hw_device list.
872 * configure: Rebuilt.
873 * interp.c (sim_open): Instantiate three timer instances.
874 Fix address typo of tx3904irc instance.
875
876Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
877
878 * interp.c (signal_exception): SystemCall exception now uses
879 the exception vector.
880
881Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
882
883 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
884 to allay warnings.
885
886Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
887
888 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
889
890Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
891
892 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
893
894 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
895 sim-main.h. Declare a struct hw_descriptor instead of struct
896 hw_device_descriptor.
897
898Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
899
900 * mips.igen (do_store_left, do_load_left): Compute nr of left and
901 right bits and then re-align left hand bytes to correct byte
902 lanes. Fix incorrect computation in do_store_left when loading
903 bytes from second word.
904
905Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
906
907 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
908 * interp.c (sim_open): Only create a device tree when HW is
909 enabled.
910
911 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
912 * interp.c (signal_exception): Ditto.
913
914Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
915
916 * gencode.c: Mark BEGEZALL as LIKELY.
917
918Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
919
920 * sim-main.h (ALU32_END): Sign extend 32 bit results.
921 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
922
923Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
924
925 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
926 modules. Recognize TX39 target with "mips*tx39" pattern.
927 * configure: Rebuilt.
928 * sim-main.h (*): Added many macros defining bits in
929 TX39 control registers.
930 (SignalInterrupt): Send actual PC instead of NULL.
931 (SignalNMIReset): New exception type.
932 * interp.c (board): New variable for future use to identify
933 a particular board being simulated.
934 (mips_option_handler,mips_options): Added "--board" option.
935 (interrupt_event): Send actual PC.
936 (sim_open): Make memory layout conditional on board setting.
937 (signal_exception): Initial implementation of hardware interrupt
938 handling. Accept another break instruction variant for simulator
939 exit.
940 (decode_coproc): Implement RFE instruction for TX39.
941 (mips.igen): Decode RFE instruction as such.
942 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
943 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
944 bbegin to implement memory map.
945 * dv-tx3904cpu.c: New file.
946 * dv-tx3904irc.c: New file.
947
948Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
949
950 * mips.igen (check_mt_hilo): Create a separate r3900 version.
951
952Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
953
954 * tx.igen (madd,maddu): Replace calls to check_op_hilo
955 with calls to check_div_hilo.
956
957Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
958
959 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
960 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
961 Add special r3900 version of do_mult_hilo.
962 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
963 with calls to check_mult_hilo.
964 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
965 with calls to check_div_hilo.
966
967Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
968
969 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
970 Document a replacement.
971
972Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
973
974 * interp.c (sim_monitor): Make mon_printf work.
975
976Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
977
978 * sim-main.h (INSN_NAME): New arg `cpu'.
979
980Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
981
982 * configure: Regenerated to track ../common/aclocal.m4 changes.
983
984Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
985
986 * configure: Regenerated to track ../common/aclocal.m4 changes.
987 * config.in: Ditto.
988
989Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
990
991 * acconfig.h: New file.
992 * configure.in: Reverted change of Apr 24; use sinclude again.
993
994Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
995
996 * configure: Regenerated to track ../common/aclocal.m4 changes.
997 * config.in: Ditto.
998
999Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1000
1001 * configure.in: Don't call sinclude.
1002
1003Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1004
1005 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1006
1007Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008
1009 * mips.igen (ERET): Implement.
1010
1011 * interp.c (decode_coproc): Return sign-extended EPC.
1012
1013 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1014
1015 * interp.c (signal_exception): Do not ignore Trap.
1016 (signal_exception): On TRAP, restart at exception address.
1017 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1018 (signal_exception): Update.
1019 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1020 so that TRAP instructions are caught.
1021
1022Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1023
1024 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1025 contains HI/LO access history.
1026 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1027 (HIACCESS, LOACCESS): Delete, replace with
1028 (HIHISTORY, LOHISTORY): New macros.
1029 (CHECKHILO): Delete all, moved to mips.igen
1030
1031 * gencode.c (build_instruction): Do not generate checks for
1032 correct HI/LO register usage.
1033
1034 * interp.c (old_engine_run): Delete checks for correct HI/LO
1035 register usage.
1036
1037 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1038 check_mf_cycles): New functions.
1039 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1040 do_divu, domultx, do_mult, do_multu): Use.
1041
1042 * tx.igen ("madd", "maddu"): Use.
1043
1044Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045
1046 * mips.igen (DSRAV): Use function do_dsrav.
1047 (SRAV): Use new function do_srav.
1048
1049 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1050 (B): Sign extend 11 bit immediate.
1051 (EXT-B*): Shift 16 bit immediate left by 1.
1052 (ADDIU*): Don't sign extend immediate value.
1053
1054Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055
1056 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1057
1058 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1059 functions.
1060
1061 * mips.igen (delayslot32, nullify_next_insn): New functions.
1062 (m16.igen): Always include.
1063 (do_*): Add more tracing.
1064
1065 * m16.igen (delayslot16): Add NIA argument, could be called by a
1066 32 bit MIPS16 instruction.
1067
1068 * interp.c (ifetch16): Move function from here.
1069 * sim-main.c (ifetch16): To here.
1070
1071 * sim-main.c (ifetch16, ifetch32): Update to match current
1072 implementations of LH, LW.
1073 (signal_exception): Don't print out incorrect hex value of illegal
1074 instruction.
1075
1076Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1077
1078 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1079 instruction.
1080
1081 * m16.igen: Implement MIPS16 instructions.
1082
1083 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1084 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1085 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1086 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1087 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1088 bodies of corresponding code from 32 bit insn to these. Also used
1089 by MIPS16 versions of functions.
1090
1091 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1092 (IMEM16): Drop NR argument from macro.
1093
1094Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1095
1096 * Makefile.in (SIM_OBJS): Add sim-main.o.
1097
1098 * sim-main.h (address_translation, load_memory, store_memory,
1099 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1100 as INLINE_SIM_MAIN.
1101 (pr_addr, pr_uword64): Declare.
1102 (sim-main.c): Include when H_REVEALS_MODULE_P.
1103
1104 * interp.c (address_translation, load_memory, store_memory,
1105 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1106 from here.
1107 * sim-main.c: To here. Fix compilation problems.
1108
1109 * configure.in: Enable inlining.
1110 * configure: Re-config.
1111
1112Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * configure: Regenerated to track ../common/aclocal.m4 changes.
1115
1116Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1117
1118 * mips.igen: Include tx.igen.
1119 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1120 * tx.igen: New file, contains MADD and MADDU.
1121
1122 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1123 the hardwired constant `7'.
1124 (store_memory): Ditto.
1125 (LOADDRMASK): Move definition to sim-main.h.
1126
1127 mips.igen (MTC0): Enable for r3900.
1128 (ADDU): Add trace.
1129
1130 mips.igen (do_load_byte): Delete.
1131 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1132 do_store_right): New functions.
1133 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1134
1135 configure.in: Let the tx39 use igen again.
1136 configure: Update.
1137
1138Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1139
1140 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1141 not an address sized quantity. Return zero for cache sizes.
1142
1143Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1144
1145 * mips.igen (r3900): r3900 does not support 64 bit integer
1146 operations.
1147
1148Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1149
1150 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1151 than igen one.
1152 * configure : Rebuild.
1153
1154Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155
1156 * configure: Regenerated to track ../common/aclocal.m4 changes.
1157
1158Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1159
1160 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1161
1162Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1163
1164 * configure: Regenerated to track ../common/aclocal.m4 changes.
1165 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1166
1167Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1168
1169 * configure: Regenerated to track ../common/aclocal.m4 changes.
1170
1171Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * interp.c (Max, Min): Comment out functions. Not yet used.
1174
1175Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * configure: Regenerated to track ../common/aclocal.m4 changes.
1178
1179Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1180
1181 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1182 configurable settings for stand-alone simulator.
1183
1184 * configure.in: Added X11 search, just in case.
1185
1186 * configure: Regenerated.
1187
1188Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1189
1190 * interp.c (sim_write, sim_read, load_memory, store_memory):
1191 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1192
1193Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * sim-main.h (GETFCC): Return an unsigned value.
1196
1197Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1198
1199 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1200 (DADD): Result destination is RD not RT.
1201
1202Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1203
1204 * sim-main.h (HIACCESS, LOACCESS): Always define.
1205
1206 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1207
1208 * interp.c (sim_info): Delete.
1209
1210Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1211
1212 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1213 (mips_option_handler): New argument `cpu'.
1214 (sim_open): Update call to sim_add_option_table.
1215
1216Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * mips.igen (CxC1): Add tracing.
1219
1220Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1221
1222 * sim-main.h (Max, Min): Declare.
1223
1224 * interp.c (Max, Min): New functions.
1225
1226 * mips.igen (BC1): Add tracing.
1227
1228Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1229
1230 * interp.c Added memory map for stack in vr4100
1231
1232Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1233
1234 * interp.c (load_memory): Add missing "break"'s.
1235
1236Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1237
1238 * interp.c (sim_store_register, sim_fetch_register): Pass in
1239 length parameter. Return -1.
1240
1241Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1242
1243 * interp.c: Added hardware init hook, fixed warnings.
1244
1245Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1246
1247 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1248
1249Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1250
1251 * interp.c (ifetch16): New function.
1252
1253 * sim-main.h (IMEM32): Rename IMEM.
1254 (IMEM16_IMMED): Define.
1255 (IMEM16): Define.
1256 (DELAY_SLOT): Update.
1257
1258 * m16run.c (sim_engine_run): New file.
1259
1260 * m16.igen: All instructions except LB.
1261 (LB): Call do_load_byte.
1262 * mips.igen (do_load_byte): New function.
1263 (LB): Call do_load_byte.
1264
1265 * mips.igen: Move spec for insn bit size and high bit from here.
1266 * Makefile.in (tmp-igen, tmp-m16): To here.
1267
1268 * m16.dc: New file, decode mips16 instructions.
1269
1270 * Makefile.in (SIM_NO_ALL): Define.
1271 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1272
1273Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1274
1275 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1276 point unit to 32 bit registers.
1277 * configure: Re-generate.
1278
1279Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1280
1281 * configure.in (sim_use_gen): Make IGEN the default simulator
1282 generator for generic 32 and 64 bit mips targets.
1283 * configure: Re-generate.
1284
1285Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1288 bitsize.
1289
1290 * interp.c (sim_fetch_register, sim_store_register): Read/write
1291 FGR from correct location.
1292 (sim_open): Set size of FGR's according to
1293 WITH_TARGET_FLOATING_POINT_BITSIZE.
1294
1295 * sim-main.h (FGR): Store floating point registers in a separate
1296 array.
1297
1298Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 * configure: Regenerated to track ../common/aclocal.m4 changes.
1301
1302Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1303
1304 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1305
1306 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1307
1308 * interp.c (pending_tick): New function. Deliver pending writes.
1309
1310 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1311 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1312 it can handle mixed sized quantites and single bits.
1313
1314Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * interp.c (oengine.h): Do not include when building with IGEN.
1317 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1318 (sim_info): Ditto for PROCESSOR_64BIT.
1319 (sim_monitor): Replace ut_reg with unsigned_word.
1320 (*): Ditto for t_reg.
1321 (LOADDRMASK): Define.
1322 (sim_open): Remove defunct check that host FP is IEEE compliant,
1323 using software to emulate floating point.
1324 (value_fpr, ...): Always compile, was conditional on HASFPU.
1325
1326Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1329 size.
1330
1331 * interp.c (SD, CPU): Define.
1332 (mips_option_handler): Set flags in each CPU.
1333 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1334 (sim_close): Do not clear STATE, deleted anyway.
1335 (sim_write, sim_read): Assume CPU zero's vm should be used for
1336 data transfers.
1337 (sim_create_inferior): Set the PC for all processors.
1338 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1339 argument.
1340 (mips16_entry): Pass correct nr of args to store_word, load_word.
1341 (ColdReset): Cold reset all cpu's.
1342 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1343 (sim_monitor, load_memory, store_memory, signal_exception): Use
1344 `CPU' instead of STATE_CPU.
1345
1346
1347 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1348 SD or CPU_.
1349
1350 * sim-main.h (signal_exception): Add sim_cpu arg.
1351 (SignalException*): Pass both SD and CPU to signal_exception.
1352 * interp.c (signal_exception): Update.
1353
1354 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1355 Ditto
1356 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1357 address_translation): Ditto
1358 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1359
1360Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * configure: Regenerated to track ../common/aclocal.m4 changes.
1363
1364Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1367
1368 * mips.igen (model): Map processor names onto BFD name.
1369
1370 * sim-main.h (CPU_CIA): Delete.
1371 (SET_CIA, GET_CIA): Define
1372
1373Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1376 regiser.
1377
1378 * configure.in (default_endian): Configure a big-endian simulator
1379 by default.
1380 * configure: Re-generate.
1381
1382Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1383
1384 * configure: Regenerated to track ../common/aclocal.m4 changes.
1385
1386Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1387
1388 * interp.c (sim_monitor): Handle Densan monitor outbyte
1389 and inbyte functions.
1390
13911997-12-29 Felix Lee <flee@cygnus.com>
1392
1393 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1394
1395Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1396
1397 * Makefile.in (tmp-igen): Arrange for $zero to always be
1398 reset to zero after every instruction.
1399
1400Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1401
1402 * configure: Regenerated to track ../common/aclocal.m4 changes.
1403 * config.in: Ditto.
1404
1405Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1406
1407 * mips.igen (MSUB): Fix to work like MADD.
1408 * gencode.c (MSUB): Similarly.
1409
1410Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1411
1412 * configure: Regenerated to track ../common/aclocal.m4 changes.
1413
1414Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1417
1418Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1419
1420 * sim-main.h (sim-fpu.h): Include.
1421
1422 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1423 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1424 using host independant sim_fpu module.
1425
1426Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * interp.c (signal_exception): Report internal errors with SIGABRT
1429 not SIGQUIT.
1430
1431 * sim-main.h (C0_CONFIG): New register.
1432 (signal.h): No longer include.
1433
1434 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1435
1436Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1437
1438 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1439
1440Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1441
1442 * mips.igen: Tag vr5000 instructions.
1443 (ANDI): Was missing mipsIV model, fix assembler syntax.
1444 (do_c_cond_fmt): New function.
1445 (C.cond.fmt): Handle mips I-III which do not support CC field
1446 separatly.
1447 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1448 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1449 in IV3.2 spec.
1450 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1451 vr5000 which saves LO in a GPR separatly.
1452
1453 * configure.in (enable-sim-igen): For vr5000, select vr5000
1454 specific instructions.
1455 * configure: Re-generate.
1456
1457Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1460
1461 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1462 fmt_uninterpreted_64 bit cases to switch. Convert to
1463 fmt_formatted,
1464
1465 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1466
1467 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1468 as specified in IV3.2 spec.
1469 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1470
1471Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1474 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1475 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1476 PENDING_FILL versions of instructions. Simplify.
1477 (X): New function.
1478 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1479 instructions.
1480 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1481 a signed value.
1482 (MTHI, MFHI): Disable code checking HI-LO.
1483
1484 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1485 global.
1486 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1487
1488Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1489
1490 * gencode.c (build_mips16_operands): Replace IPC with cia.
1491
1492 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1493 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1494 IPC to `cia'.
1495 (UndefinedResult): Replace function with macro/function
1496 combination.
1497 (sim_engine_run): Don't save PC in IPC.
1498
1499 * sim-main.h (IPC): Delete.
1500
1501
1502 * interp.c (signal_exception, store_word, load_word,
1503 address_translation, load_memory, store_memory, cache_op,
1504 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1505 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1506 current instruction address - cia - argument.
1507 (sim_read, sim_write): Call address_translation directly.
1508 (sim_engine_run): Rename variable vaddr to cia.
1509 (signal_exception): Pass cia to sim_monitor
1510
1511 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1512 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1513 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1514
1515 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1516 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1517 SIM_ASSERT.
1518
1519 * interp.c (signal_exception): Pass restart address to
1520 sim_engine_restart.
1521
1522 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1523 idecode.o): Add dependency.
1524
1525 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1526 Delete definitions
1527 (DELAY_SLOT): Update NIA not PC with branch address.
1528 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1529
1530 * mips.igen: Use CIA not PC in branch calculations.
1531 (illegal): Call SignalException.
1532 (BEQ, ADDIU): Fix assembler.
1533
1534Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1535
1536 * m16.igen (JALX): Was missing.
1537
1538 * configure.in (enable-sim-igen): New configuration option.
1539 * configure: Re-generate.
1540
1541 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1542
1543 * interp.c (load_memory, store_memory): Delete parameter RAW.
1544 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1545 bypassing {load,store}_memory.
1546
1547 * sim-main.h (ByteSwapMem): Delete definition.
1548
1549 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1550
1551 * interp.c (sim_do_command, sim_commands): Delete mips specific
1552 commands. Handled by module sim-options.
1553
1554 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1555 (WITH_MODULO_MEMORY): Define.
1556
1557 * interp.c (sim_info): Delete code printing memory size.
1558
1559 * interp.c (mips_size): Nee sim_size, delete function.
1560 (power2): Delete.
1561 (monitor, monitor_base, monitor_size): Delete global variables.
1562 (sim_open, sim_close): Delete code creating monitor and other
1563 memory regions. Use sim-memopts module, via sim_do_commandf, to
1564 manage memory regions.
1565 (load_memory, store_memory): Use sim-core for memory model.
1566
1567 * interp.c (address_translation): Delete all memory map code
1568 except line forcing 32 bit addresses.
1569
1570Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1573 trace options.
1574
1575 * interp.c (logfh, logfile): Delete globals.
1576 (sim_open, sim_close): Delete code opening & closing log file.
1577 (mips_option_handler): Delete -l and -n options.
1578 (OPTION mips_options): Ditto.
1579
1580 * interp.c (OPTION mips_options): Rename option trace to dinero.
1581 (mips_option_handler): Update.
1582
1583Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * interp.c (fetch_str): New function.
1586 (sim_monitor): Rewrite using sim_read & sim_write.
1587 (sim_open): Check magic number.
1588 (sim_open): Write monitor vectors into memory using sim_write.
1589 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1590 (sim_read, sim_write): Simplify - transfer data one byte at a
1591 time.
1592 (load_memory, store_memory): Clarify meaning of parameter RAW.
1593
1594 * sim-main.h (isHOST): Defete definition.
1595 (isTARGET): Mark as depreciated.
1596 (address_translation): Delete parameter HOST.
1597
1598 * interp.c (address_translation): Delete parameter HOST.
1599
1600Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1601
1602 * mips.igen:
1603
1604 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1605 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1606
1607Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * mips.igen: Add model filter field to records.
1610
1611Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1612
1613 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1614
1615 interp.c (sim_engine_run): Do not compile function sim_engine_run
1616 when WITH_IGEN == 1.
1617
1618 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1619 target architecture.
1620
1621 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1622 igen. Replace with configuration variables sim_igen_flags /
1623 sim_m16_flags.
1624
1625 * m16.igen: New file. Copy mips16 insns here.
1626 * mips.igen: From here.
1627
1628Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1631 to top.
1632 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1633
1634Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1635
1636 * gencode.c (build_instruction): Follow sim_write's lead in using
1637 BigEndianMem instead of !ByteSwapMem.
1638
1639Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * configure.in (sim_gen): Dependent on target, select type of
1642 generator. Always select old style generator.
1643
1644 configure: Re-generate.
1645
1646 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1647 targets.
1648 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1649 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1650 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1651 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1652 SIM_@sim_gen@_*, set by autoconf.
1653
1654Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1655
1656 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1657
1658 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1659 CURRENT_FLOATING_POINT instead.
1660
1661 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1662 (address_translation): Raise exception InstructionFetch when
1663 translation fails and isINSTRUCTION.
1664
1665 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1666 sim_engine_run): Change type of of vaddr and paddr to
1667 address_word.
1668 (address_translation, prefetch, load_memory, store_memory,
1669 cache_op): Change type of vAddr and pAddr to address_word.
1670
1671 * gencode.c (build_instruction): Change type of vaddr and paddr to
1672 address_word.
1673
1674Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1677 macro to obtain result of ALU op.
1678
1679Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1680
1681 * interp.c (sim_info): Call profile_print.
1682
1683Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1684
1685 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1686
1687 * sim-main.h (WITH_PROFILE): Do not define, defined in
1688 common/sim-config.h. Use sim-profile module.
1689 (simPROFILE): Delete defintion.
1690
1691 * interp.c (PROFILE): Delete definition.
1692 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1693 (sim_close): Delete code writing profile histogram.
1694 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1695 Delete.
1696 (sim_engine_run): Delete code profiling the PC.
1697
1698Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1699
1700 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1701
1702 * interp.c (sim_monitor): Make register pointers of type
1703 unsigned_word*.
1704
1705 * sim-main.h: Make registers of type unsigned_word not
1706 signed_word.
1707
1708Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1709
1710 * interp.c (sync_operation): Rename from SyncOperation, make
1711 global, add SD argument.
1712 (prefetch): Rename from Prefetch, make global, add SD argument.
1713 (decode_coproc): Make global.
1714
1715 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1716
1717 * gencode.c (build_instruction): Generate DecodeCoproc not
1718 decode_coproc calls.
1719
1720 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1721 (SizeFGR): Move to sim-main.h
1722 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1723 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1724 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1725 sim-main.h.
1726 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1727 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1728 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1729 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1730 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1731 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1732
1733 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1734 exception.
1735 (sim-alu.h): Include.
1736 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1737 (sim_cia): Typedef to instruction_address.
1738
1739Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * Makefile.in (interp.o): Rename generated file engine.c to
1742 oengine.c.
1743
1744 * interp.c: Update.
1745
1746Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1747
1748 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1749
1750Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1751
1752 * gencode.c (build_instruction): For "FPSQRT", output correct
1753 number of arguments to Recip.
1754
1755Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * Makefile.in (interp.o): Depends on sim-main.h
1758
1759 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1760
1761 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1762 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1763 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1764 STATE, DSSTATE): Define
1765 (GPR, FGRIDX, ..): Define.
1766
1767 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1768 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1769 (GPR, FGRIDX, ...): Delete macros.
1770
1771 * interp.c: Update names to match defines from sim-main.h
1772
1773Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1774
1775 * interp.c (sim_monitor): Add SD argument.
1776 (sim_warning): Delete. Replace calls with calls to
1777 sim_io_eprintf.
1778 (sim_error): Delete. Replace calls with sim_io_error.
1779 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1780 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1781 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1782 argument.
1783 (mips_size): Rename from sim_size. Add SD argument.
1784
1785 * interp.c (simulator): Delete global variable.
1786 (callback): Delete global variable.
1787 (mips_option_handler, sim_open, sim_write, sim_read,
1788 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1789 sim_size,sim_monitor): Use sim_io_* not callback->*.
1790 (sim_open): ZALLOC simulator struct.
1791 (PROFILE): Do not define.
1792
1793Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794
1795 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1796 support.h with corresponding code.
1797
1798 * sim-main.h (word64, uword64), support.h: Move definition to
1799 sim-main.h.
1800 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1801
1802 * support.h: Delete
1803 * Makefile.in: Update dependencies
1804 * interp.c: Do not include.
1805
1806Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1807
1808 * interp.c (address_translation, load_memory, store_memory,
1809 cache_op): Rename to from AddressTranslation et.al., make global,
1810 add SD argument
1811
1812 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1813 CacheOp): Define.
1814
1815 * interp.c (SignalException): Rename to signal_exception, make
1816 global.
1817
1818 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1819
1820 * sim-main.h (SignalException, SignalExceptionInterrupt,
1821 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1822 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1823 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1824 Define.
1825
1826 * interp.c, support.h: Use.
1827
1828Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1831 to value_fpr / store_fpr. Add SD argument.
1832 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1833 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1834
1835 * sim-main.h (ValueFPR, StoreFPR): Define.
1836
1837Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1838
1839 * interp.c (sim_engine_run): Check consistency between configure
1840 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1841 and HASFPU.
1842
1843 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1844 (mips_fpu): Configure WITH_FLOATING_POINT.
1845 (mips_endian): Configure WITH_TARGET_ENDIAN.
1846 * configure: Update.
1847
1848Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * configure: Regenerated to track ../common/aclocal.m4 changes.
1851
1852Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1853
1854 * configure: Regenerated.
1855
1856Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1857
1858 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1859
1860Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1861
1862 * gencode.c (print_igen_insn_models): Assume certain architectures
1863 include all mips* instructions.
1864 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1865 instruction.
1866
1867 * Makefile.in (tmp.igen): Add target. Generate igen input from
1868 gencode file.
1869
1870 * gencode.c (FEATURE_IGEN): Define.
1871 (main): Add --igen option. Generate output in igen format.
1872 (process_instructions): Format output according to igen option.
1873 (print_igen_insn_format): New function.
1874 (print_igen_insn_models): New function.
1875 (process_instructions): Only issue warnings and ignore
1876 instructions when no FEATURE_IGEN.
1877
1878Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1881 MIPS targets.
1882
1883Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * configure: Regenerated to track ../common/aclocal.m4 changes.
1886
1887Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1888
1889 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1890 SIM_RESERVED_BITS): Delete, moved to common.
1891 (SIM_EXTRA_CFLAGS): Update.
1892
1893Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * configure.in: Configure non-strict memory alignment.
1896 * configure: Regenerated to track ../common/aclocal.m4 changes.
1897
1898Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1899
1900 * configure: Regenerated to track ../common/aclocal.m4 changes.
1901
1902Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1903
1904 * gencode.c (SDBBP,DERET): Added (3900) insns.
1905 (RFE): Turn on for 3900.
1906 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1907 (dsstate): Made global.
1908 (SUBTARGET_R3900): Added.
1909 (CANCELDELAYSLOT): New.
1910 (SignalException): Ignore SystemCall rather than ignore and
1911 terminate. Add DebugBreakPoint handling.
1912 (decode_coproc): New insns RFE, DERET; and new registers Debug
1913 and DEPC protected by SUBTARGET_R3900.
1914 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1915 bits explicitly.
1916 * Makefile.in,configure.in: Add mips subtarget option.
1917 * configure: Update.
1918
1919Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1920
1921 * gencode.c: Add r3900 (tx39).
1922
1923
1924Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1925
1926 * gencode.c (build_instruction): Don't need to subtract 4 for
1927 JALR, just 2.
1928
1929Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1930
1931 * interp.c: Correct some HASFPU problems.
1932
1933Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1934
1935 * configure: Regenerated to track ../common/aclocal.m4 changes.
1936
1937Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 * interp.c (mips_options): Fix samples option short form, should
1940 be `x'.
1941
1942Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1943
1944 * interp.c (sim_info): Enable info code. Was just returning.
1945
1946Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1947
1948 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1949 MFC0.
1950
1951Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1954 constants.
1955 (build_instruction): Ditto for LL.
1956
1957Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1958
1959 * configure: Regenerated to track ../common/aclocal.m4 changes.
1960
1961Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1962
1963 * configure: Regenerated to track ../common/aclocal.m4 changes.
1964 * config.in: Ditto.
1965
1966Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * interp.c (sim_open): Add call to sim_analyze_program, update
1969 call to sim_config.
1970
1971Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1972
1973 * interp.c (sim_kill): Delete.
1974 (sim_create_inferior): Add ABFD argument. Set PC from same.
1975 (sim_load): Move code initializing trap handlers from here.
1976 (sim_open): To here.
1977 (sim_load): Delete, use sim-hload.c.
1978
1979 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1980
1981Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * configure: Regenerated to track ../common/aclocal.m4 changes.
1984 * config.in: Ditto.
1985
1986Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * interp.c (sim_open): Add ABFD argument.
1989 (sim_load): Move call to sim_config from here.
1990 (sim_open): To here. Check return status.
1991
1992Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1993
1994 * gencode.c (build_instruction): Two arg MADD should
1995 not assign result to $0.
1996
1997Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1998
1999 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2000 * sim/mips/configure.in: Regenerate.
2001
2002Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2003
2004 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2005 signed8, unsigned8 et.al. types.
2006
2007 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2008 hosts when selecting subreg.
2009
2010Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2011
2012 * interp.c (sim_engine_run): Reset the ZERO register to zero
2013 regardless of FEATURE_WARN_ZERO.
2014 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2015
2016Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2017
2018 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2019 (SignalException): For BreakPoints ignore any mode bits and just
2020 save the PC.
2021 (SignalException): Always set the CAUSE register.
2022
2023Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2024
2025 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2026 exception has been taken.
2027
2028 * interp.c: Implement the ERET and mt/f sr instructions.
2029
2030Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2031
2032 * interp.c (SignalException): Don't bother restarting an
2033 interrupt.
2034
2035Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2036
2037 * interp.c (SignalException): Really take an interrupt.
2038 (interrupt_event): Only deliver interrupts when enabled.
2039
2040Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041
2042 * interp.c (sim_info): Only print info when verbose.
2043 (sim_info) Use sim_io_printf for output.
2044
2045Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046
2047 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2048 mips architectures.
2049
2050Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * interp.c (sim_do_command): Check for common commands if a
2053 simulator specific command fails.
2054
2055Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2056
2057 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2058 and simBE when DEBUG is defined.
2059
2060Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * interp.c (interrupt_event): New function. Pass exception event
2063 onto exception handler.
2064
2065 * configure.in: Check for stdlib.h.
2066 * configure: Regenerate.
2067
2068 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2069 variable declaration.
2070 (build_instruction): Initialize memval1.
2071 (build_instruction): Add UNUSED attribute to byte, bigend,
2072 reverse.
2073 (build_operands): Ditto.
2074
2075 * interp.c: Fix GCC warnings.
2076 (sim_get_quit_code): Delete.
2077
2078 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2079 * Makefile.in: Ditto.
2080 * configure: Re-generate.
2081
2082 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2083
2084Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2085
2086 * interp.c (mips_option_handler): New function parse argumes using
2087 sim-options.
2088 (myname): Replace with STATE_MY_NAME.
2089 (sim_open): Delete check for host endianness - performed by
2090 sim_config.
2091 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2092 (sim_open): Move much of the initialization from here.
2093 (sim_load): To here. After the image has been loaded and
2094 endianness set.
2095 (sim_open): Move ColdReset from here.
2096 (sim_create_inferior): To here.
2097 (sim_open): Make FP check less dependant on host endianness.
2098
2099 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2100 run.
2101 * interp.c (sim_set_callbacks): Delete.
2102
2103 * interp.c (membank, membank_base, membank_size): Replace with
2104 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2105 (sim_open): Remove call to callback->init. gdb/run do this.
2106
2107 * interp.c: Update
2108
2109 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2110
2111 * interp.c (big_endian_p): Delete, replaced by
2112 current_target_byte_order.
2113
2114Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2115
2116 * interp.c (host_read_long, host_read_word, host_swap_word,
2117 host_swap_long): Delete. Using common sim-endian.
2118 (sim_fetch_register, sim_store_register): Use H2T.
2119 (pipeline_ticks): Delete. Handled by sim-events.
2120 (sim_info): Update.
2121 (sim_engine_run): Update.
2122
2123Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2124
2125 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2126 reason from here.
2127 (SignalException): To here. Signal using sim_engine_halt.
2128 (sim_stop_reason): Delete, moved to common.
2129
2130Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2131
2132 * interp.c (sim_open): Add callback argument.
2133 (sim_set_callbacks): Delete SIM_DESC argument.
2134 (sim_size): Ditto.
2135
2136Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2137
2138 * Makefile.in (SIM_OBJS): Add common modules.
2139
2140 * interp.c (sim_set_callbacks): Also set SD callback.
2141 (set_endianness, xfer_*, swap_*): Delete.
2142 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2143 Change to functions using sim-endian macros.
2144 (control_c, sim_stop): Delete, use common version.
2145 (simulate): Convert into.
2146 (sim_engine_run): This function.
2147 (sim_resume): Delete.
2148
2149 * interp.c (simulation): New variable - the simulator object.
2150 (sim_kind): Delete global - merged into simulation.
2151 (sim_load): Cleanup. Move PC assignment from here.
2152 (sim_create_inferior): To here.
2153
2154 * sim-main.h: New file.
2155 * interp.c (sim-main.h): Include.
2156
2157Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2158
2159 * configure: Regenerated to track ../common/aclocal.m4 changes.
2160
2161Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2162
2163 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2164
2165Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2166
2167 * gencode.c (build_instruction): DIV instructions: check
2168 for division by zero and integer overflow before using
2169 host's division operation.
2170
2171Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2172
2173 * Makefile.in (SIM_OBJS): Add sim-load.o.
2174 * interp.c: #include bfd.h.
2175 (target_byte_order): Delete.
2176 (sim_kind, myname, big_endian_p): New static locals.
2177 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2178 after argument parsing. Recognize -E arg, set endianness accordingly.
2179 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2180 load file into simulator. Set PC from bfd.
2181 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2182 (set_endianness): Use big_endian_p instead of target_byte_order.
2183
2184Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185
2186 * interp.c (sim_size): Delete prototype - conflicts with
2187 definition in remote-sim.h. Correct definition.
2188
2189Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2190
2191 * configure: Regenerated to track ../common/aclocal.m4 changes.
2192 * config.in: Ditto.
2193
2194Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2195
2196 * interp.c (sim_open): New arg `kind'.
2197
2198 * configure: Regenerated to track ../common/aclocal.m4 changes.
2199
2200Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2201
2202 * configure: Regenerated to track ../common/aclocal.m4 changes.
2203
2204Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2205
2206 * interp.c (sim_open): Set optind to 0 before calling getopt.
2207
2208Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2209
2210 * configure: Regenerated to track ../common/aclocal.m4 changes.
2211
2212Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2213
2214 * interp.c : Replace uses of pr_addr with pr_uword64
2215 where the bit length is always 64 independent of SIM_ADDR.
2216 (pr_uword64) : added.
2217
2218Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2219
2220 * configure: Re-generate.
2221
2222Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2223
2224 * configure: Regenerate to track ../common/aclocal.m4 changes.
2225
2226Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2227
2228 * interp.c (sim_open): New SIM_DESC result. Argument is now
2229 in argv form.
2230 (other sim_*): New SIM_DESC argument.
2231
2232Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2233
2234 * interp.c: Fix printing of addresses for non-64-bit targets.
2235 (pr_addr): Add function to print address based on size.
2236
2237Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2238
2239 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2240
2241Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2242
2243 * gencode.c (build_mips16_operands): Correct computation of base
2244 address for extended PC relative instruction.
2245
2246Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2247
2248 * interp.c (mips16_entry): Add support for floating point cases.
2249 (SignalException): Pass floating point cases to mips16_entry.
2250 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2251 registers.
2252 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2253 or fmt_word.
2254 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2255 and then set the state to fmt_uninterpreted.
2256 (COP_SW): Temporarily set the state to fmt_word while calling
2257 ValueFPR.
2258
2259Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2260
2261 * gencode.c (build_instruction): The high order may be set in the
2262 comparison flags at any ISA level, not just ISA 4.
2263
2264Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2265
2266 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2267 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2268 * configure.in: sinclude ../common/aclocal.m4.
2269 * configure: Regenerated.
2270
2271Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2272
2273 * configure: Rebuild after change to aclocal.m4.
2274
2275Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2276
2277 * configure configure.in Makefile.in: Update to new configure
2278 scheme which is more compatible with WinGDB builds.
2279 * configure.in: Improve comment on how to run autoconf.
2280 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2281 * Makefile.in: Use autoconf substitution to install common
2282 makefile fragment.
2283
2284Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2285
2286 * gencode.c (build_instruction): Use BigEndianCPU instead of
2287 ByteSwapMem.
2288
2289Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2290
2291 * interp.c (sim_monitor): Make output to stdout visible in
2292 wingdb's I/O log window.
2293
2294Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2295
2296 * support.h: Undo previous change to SIGTRAP
2297 and SIGQUIT values.
2298
2299Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2300
2301 * interp.c (store_word, load_word): New static functions.
2302 (mips16_entry): New static function.
2303 (SignalException): Look for mips16 entry and exit instructions.
2304 (simulate): Use the correct index when setting fpr_state after
2305 doing a pending move.
2306
2307Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2308
2309 * interp.c: Fix byte-swapping code throughout to work on
2310 both little- and big-endian hosts.
2311
2312Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2313
2314 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2315 with gdb/config/i386/xm-windows.h.
2316
2317Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2318
2319 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2320 that messes up arithmetic shifts.
2321
2322Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2323
2324 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2325 SIGTRAP and SIGQUIT for _WIN32.
2326
2327Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2328
2329 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2330 force a 64 bit multiplication.
2331 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2332 destination register is 0, since that is the default mips16 nop
2333 instruction.
2334
2335Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2336
2337 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2338 (build_endian_shift): Don't check proc64.
2339 (build_instruction): Always set memval to uword64. Cast op2 to
2340 uword64 when shifting it left in memory instructions. Always use
2341 the same code for stores--don't special case proc64.
2342
2343 * gencode.c (build_mips16_operands): Fix base PC value for PC
2344 relative operands.
2345 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2346 jal instruction.
2347 * interp.c (simJALDELAYSLOT): Define.
2348 (JALDELAYSLOT): Define.
2349 (INDELAYSLOT, INJALDELAYSLOT): Define.
2350 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2351
2352Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2353
2354 * interp.c (sim_open): add flush_cache as a PMON routine
2355 (sim_monitor): handle flush_cache by ignoring it
2356
2357Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2358
2359 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2360 BigEndianMem.
2361 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2362 (BigEndianMem): Rename to ByteSwapMem and change sense.
2363 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2364 BigEndianMem references to !ByteSwapMem.
2365 (set_endianness): New function, with prototype.
2366 (sim_open): Call set_endianness.
2367 (sim_info): Use simBE instead of BigEndianMem.
2368 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2369 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2370 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2371 ifdefs, keeping the prototype declaration.
2372 (swap_word): Rewrite correctly.
2373 (ColdReset): Delete references to CONFIG. Delete endianness related
2374 code; moved to set_endianness.
2375
2376Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2377
2378 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2379 * interp.c (CHECKHILO): Define away.
2380 (simSIGINT): New macro.
2381 (membank_size): Increase from 1MB to 2MB.
2382 (control_c): New function.
2383 (sim_resume): Rename parameter signal to signal_number. Add local
2384 variable prev. Call signal before and after simulate.
2385 (sim_stop_reason): Add simSIGINT support.
2386 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2387 functions always.
2388 (sim_warning): Delete call to SignalException. Do call printf_filtered
2389 if logfh is NULL.
2390 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2391 a call to sim_warning.
2392
2393Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2394
2395 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2396 16 bit instructions.
2397
2398Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2399
2400 Add support for mips16 (16 bit MIPS implementation):
2401 * gencode.c (inst_type): Add mips16 instruction encoding types.
2402 (GETDATASIZEINSN): Define.
2403 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2404 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2405 mtlo.
2406 (MIPS16_DECODE): New table, for mips16 instructions.
2407 (bitmap_val): New static function.
2408 (struct mips16_op): Define.
2409 (mips16_op_table): New table, for mips16 operands.
2410 (build_mips16_operands): New static function.
2411 (process_instructions): If PC is odd, decode a mips16
2412 instruction. Break out instruction handling into new
2413 build_instruction function.
2414 (build_instruction): New static function, broken out of
2415 process_instructions. Check modifiers rather than flags for SHIFT
2416 bit count and m[ft]{hi,lo} direction.
2417 (usage): Pass program name to fprintf.
2418 (main): Remove unused variable this_option_optind. Change
2419 ``*loptarg++'' to ``loptarg++''.
2420 (my_strtoul): Parenthesize && within ||.
2421 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2422 (simulate): If PC is odd, fetch a 16 bit instruction, and
2423 increment PC by 2 rather than 4.
2424 * configure.in: Add case for mips16*-*-*.
2425 * configure: Rebuild.
2426
2427Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2428
2429 * interp.c: Allow -t to enable tracing in standalone simulator.
2430 Fix garbage output in trace file and error messages.
2431
2432Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2433
2434 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2435 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2436 * configure.in: Simplify using macros in ../common/aclocal.m4.
2437 * configure: Regenerated.
2438 * tconfig.in: New file.
2439
2440Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2441
2442 * interp.c: Fix bugs in 64-bit port.
2443 Use ansi function declarations for msvc compiler.
2444 Initialize and test file pointer in trace code.
2445 Prevent duplicate definition of LAST_EMED_REGNUM.
2446
2447Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2448
2449 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2450
2451Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2452
2453 * interp.c (SignalException): Check for explicit terminating
2454 breakpoint value.
2455 * gencode.c: Pass instruction value through SignalException()
2456 calls for Trap, Breakpoint and Syscall.
2457
2458Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2459
2460 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2461 only used on those hosts that provide it.
2462 * configure.in: Add sqrt() to list of functions to be checked for.
2463 * config.in: Re-generated.
2464 * configure: Re-generated.
2465
2466Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2467
2468 * gencode.c (process_instructions): Call build_endian_shift when
2469 expanding STORE RIGHT, to fix swr.
2470 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2471 clear the high bits.
2472 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2473 Fix float to int conversions to produce signed values.
2474
2475Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2476
2477 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2478 (process_instructions): Correct handling of nor instruction.
2479 Correct shift count for 32 bit shift instructions. Correct sign
2480 extension for arithmetic shifts to not shift the number of bits in
2481 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2482 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2483 Fix madd.
2484 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2485 It's OK to have a mult follow a mult. What's not OK is to have a
2486 mult follow an mfhi.
2487 (Convert): Comment out incorrect rounding code.
2488
2489Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2490
2491 * interp.c (sim_monitor): Improved monitor printf
2492 simulation. Tidied up simulator warnings, and added "--log" option
2493 for directing warning message output.
2494 * gencode.c: Use sim_warning() rather than WARNING macro.
2495
2496Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2497
2498 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2499 getopt1.o, rather than on gencode.c. Link objects together.
2500 Don't link against -liberty.
2501 (gencode.o, getopt.o, getopt1.o): New targets.
2502 * gencode.c: Include <ctype.h> and "ansidecl.h".
2503 (AND): Undefine after including "ansidecl.h".
2504 (ULONG_MAX): Define if not defined.
2505 (OP_*): Don't define macros; now defined in opcode/mips.h.
2506 (main): Call my_strtoul rather than strtoul.
2507 (my_strtoul): New static function.
2508
2509Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2510
2511 * gencode.c (process_instructions): Generate word64 and uword64
2512 instead of `long long' and `unsigned long long' data types.
2513 * interp.c: #include sysdep.h to get signals, and define default
2514 for SIGBUS.
2515 * (Convert): Work around for Visual-C++ compiler bug with type
2516 conversion.
2517 * support.h: Make things compile under Visual-C++ by using
2518 __int64 instead of `long long'. Change many refs to long long
2519 into word64/uword64 typedefs.
2520
2521Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2522
2523 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2524 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2525 (docdir): Removed.
2526 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2527 (AC_PROG_INSTALL): Added.
2528 (AC_PROG_CC): Moved to before configure.host call.
2529 * configure: Rebuilt.
2530
2531Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2532
2533 * configure.in: Define @SIMCONF@ depending on mips target.
2534 * configure: Rebuild.
2535 * Makefile.in (run): Add @SIMCONF@ to control simulator
2536 construction.
2537 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2538 * interp.c: Remove some debugging, provide more detailed error
2539 messages, update memory accesses to use LOADDRMASK.
2540
2541Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2542
2543 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2544 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2545 stamp-h.
2546 * configure: Rebuild.
2547 * config.in: New file, generated by autoheader.
2548 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2549 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2550 HAVE_ANINT and HAVE_AINT, as appropriate.
2551 * Makefile.in (run): Use @LIBS@ rather than -lm.
2552 (interp.o): Depend upon config.h.
2553 (Makefile): Just rebuild Makefile.
2554 (clean): Remove stamp-h.
2555 (mostlyclean): Make the same as clean, not as distclean.
2556 (config.h, stamp-h): New targets.
2557
2558Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2559
2560 * interp.c (ColdReset): Fix boolean test. Make all simulator
2561 globals static.
2562
2563Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2564
2565 * interp.c (xfer_direct_word, xfer_direct_long,
2566 swap_direct_word, swap_direct_long, xfer_big_word,
2567 xfer_big_long, xfer_little_word, xfer_little_long,
2568 swap_word,swap_long): Added.
2569 * interp.c (ColdReset): Provide function indirection to
2570 host<->simulated_target transfer routines.
2571 * interp.c (sim_store_register, sim_fetch_register): Updated to
2572 make use of indirected transfer routines.
2573
2574Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2575
2576 * gencode.c (process_instructions): Ensure FP ABS instruction
2577 recognised.
2578 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2579 system call support.
2580
2581Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2582
2583 * interp.c (sim_do_command): Complain if callback structure not
2584 initialised.
2585
2586Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2587
2588 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2589 support for Sun hosts.
2590 * Makefile.in (gencode): Ensure the host compiler and libraries
2591 used for cross-hosted build.
2592
2593Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2594
2595 * interp.c, gencode.c: Some more (TODO) tidying.
2596
2597Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2598
2599 * gencode.c, interp.c: Replaced explicit long long references with
2600 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2601 * support.h (SET64LO, SET64HI): Macros added.
2602
2603Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2604
2605 * configure: Regenerate with autoconf 2.7.
2606
2607Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2608
2609 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2610 * support.h: Remove superfluous "1" from #if.
2611 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2612
2613Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2614
2615 * interp.c (StoreFPR): Control UndefinedResult() call on
2616 WARN_RESULT manifest.
2617
2618Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2619
2620 * gencode.c: Tidied instruction decoding, and added FP instruction
2621 support.
2622
2623 * interp.c: Added dineroIII, and BSD profiling support. Also
2624 run-time FP handling.
2625
2626Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2627
2628 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2629 gencode.c, interp.c, support.h: created.
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