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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
cf92e05c | 13 | #include <memalign.h> |
0b23fb36 | 14 | #include <net.h> |
84f64c8b | 15 | #include <netdev.h> |
0b23fb36 IY |
16 | #include <miiphy.h> |
17 | #include "fec_mxc.h" | |
18 | ||
19 | #include <asm/arch/clock.h> | |
20 | #include <asm/arch/imx-regs.h> | |
fbecbaa1 | 21 | #include <asm/imx-common/sys_proto.h> |
0b23fb36 IY |
22 | #include <asm/io.h> |
23 | #include <asm/errno.h> | |
e2a66e60 | 24 | #include <linux/compiler.h> |
0b23fb36 IY |
25 | |
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
bc1ce150 MV |
28 | /* |
29 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
30 | * the code in the tightloops this timeout is used in adds some overhead. | |
31 | */ | |
32 | #define FEC_XFER_TIMEOUT 5000 | |
33 | ||
db5b7f56 FE |
34 | /* |
35 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
36 | * 64-byte alignment in the DMA RX FEC buffer. | |
37 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
38 | * satisfies the alignment on other SoCs (32-bytes) | |
39 | */ | |
40 | #define FEC_DMA_RX_MINALIGN 64 | |
41 | ||
0b23fb36 IY |
42 | #ifndef CONFIG_MII |
43 | #error "CONFIG_MII has to be defined!" | |
44 | #endif | |
45 | ||
5c1ad3e6 EN |
46 | #ifndef CONFIG_FEC_XCV_TYPE |
47 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
48 | #endif |
49 | ||
be7e87e2 MV |
50 | /* |
51 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
52 | * sending and after receiving. | |
53 | */ | |
5c1ad3e6 EN |
54 | #ifdef CONFIG_MX28 |
55 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
56 | #endif | |
57 | ||
58 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
59 | ||
60 | /* Check various alignment issues at compile time */ | |
61 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
62 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
63 | #endif | |
64 | ||
65 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
66 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
67 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
68 | #endif |
69 | ||
0b23fb36 IY |
70 | #undef DEBUG |
71 | ||
5c1ad3e6 | 72 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
73 | static void swap_packet(uint32_t *packet, int length) |
74 | { | |
75 | int i; | |
76 | ||
77 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
78 | packet[i] = __swab32(packet[i]); | |
79 | } | |
80 | #endif | |
81 | ||
0b23fb36 IY |
82 | /* |
83 | * MII-interface related functions | |
84 | */ | |
13947f43 TK |
85 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
86 | uint8_t regAddr) | |
0b23fb36 | 87 | { |
0b23fb36 IY |
88 | uint32_t reg; /* convenient holder for the PHY register */ |
89 | uint32_t phy; /* convenient holder for the PHY */ | |
90 | uint32_t start; | |
13947f43 | 91 | int val; |
0b23fb36 IY |
92 | |
93 | /* | |
94 | * reading from any PHY's register is done by properly | |
95 | * programming the FEC's MII data register. | |
96 | */ | |
d133b881 | 97 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
98 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
99 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
100 | ||
101 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 102 | phy | reg, ð->mii_data); |
0b23fb36 IY |
103 | |
104 | /* | |
105 | * wait for the related interrupt | |
106 | */ | |
a60d1e5b | 107 | start = get_timer(0); |
d133b881 | 108 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
109 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
110 | printf("Read MDIO failed...\n"); | |
111 | return -1; | |
112 | } | |
113 | } | |
114 | ||
115 | /* | |
116 | * clear mii interrupt bit | |
117 | */ | |
d133b881 | 118 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
119 | |
120 | /* | |
121 | * it's now safe to read the PHY's register | |
122 | */ | |
13947f43 TK |
123 | val = (unsigned short)readl(ð->mii_data); |
124 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
125 | regAddr, val); | |
126 | return val; | |
0b23fb36 IY |
127 | } |
128 | ||
575c5cc0 | 129 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
130 | { |
131 | /* | |
132 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
133 | * and do not drop the Preamble. | |
134 | */ | |
6ba45cc0 MN |
135 | register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 5000000); |
136 | #ifdef FEC_QUIRK_ENET_MAC | |
137 | speed--; | |
138 | #endif | |
139 | speed <<= 1; | |
140 | writel(speed, ð->mii_speed); | |
575c5cc0 | 141 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 142 | } |
0b23fb36 | 143 | |
13947f43 TK |
144 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
145 | uint8_t regAddr, uint16_t data) | |
146 | { | |
0b23fb36 IY |
147 | uint32_t reg; /* convenient holder for the PHY register */ |
148 | uint32_t phy; /* convenient holder for the PHY */ | |
149 | uint32_t start; | |
150 | ||
151 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
152 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
153 | ||
154 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 155 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
156 | |
157 | /* | |
158 | * wait for the MII interrupt | |
159 | */ | |
a60d1e5b | 160 | start = get_timer(0); |
d133b881 | 161 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
162 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
163 | printf("Write MDIO failed...\n"); | |
164 | return -1; | |
165 | } | |
166 | } | |
167 | ||
168 | /* | |
169 | * clear MII interrupt bit | |
170 | */ | |
d133b881 | 171 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 172 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
173 | regAddr, data); |
174 | ||
175 | return 0; | |
176 | } | |
177 | ||
84f64c8b JH |
178 | static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, |
179 | int regAddr) | |
13947f43 TK |
180 | { |
181 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
182 | } | |
183 | ||
84f64c8b JH |
184 | static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, |
185 | int regAddr, u16 data) | |
13947f43 TK |
186 | { |
187 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
188 | } | |
189 | ||
190 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
191 | static int miiphy_restart_aneg(struct eth_device *dev) |
192 | { | |
b774fe9d SB |
193 | int ret = 0; |
194 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 195 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 196 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 197 | |
0b23fb36 IY |
198 | /* |
199 | * Wake up from sleep if necessary | |
200 | * Reset PHY, then delay 300ns | |
201 | */ | |
cb17b92d | 202 | #ifdef CONFIG_MX27 |
13947f43 | 203 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 204 | #endif |
13947f43 | 205 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
206 | udelay(1000); |
207 | ||
208 | /* | |
209 | * Set the auto-negotiation advertisement register bits | |
210 | */ | |
13947f43 | 211 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
212 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
213 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 214 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 215 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
216 | |
217 | if (fec->mii_postcall) | |
218 | ret = fec->mii_postcall(fec->phy_id); | |
219 | ||
b774fe9d | 220 | #endif |
2e5f4421 | 221 | return ret; |
0b23fb36 IY |
222 | } |
223 | ||
224 | static int miiphy_wait_aneg(struct eth_device *dev) | |
225 | { | |
226 | uint32_t start; | |
13947f43 | 227 | int status; |
9e27e9dc | 228 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 229 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
230 | |
231 | /* | |
232 | * Wait for AN completion | |
233 | */ | |
a60d1e5b | 234 | start = get_timer(0); |
0b23fb36 IY |
235 | do { |
236 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
237 | printf("%s: Autonegotiation timeout\n", dev->name); | |
238 | return -1; | |
239 | } | |
240 | ||
13947f43 TK |
241 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
242 | if (status < 0) { | |
243 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
244 | dev->name, status); |
245 | return -1; | |
246 | } | |
8ef583a0 | 247 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
248 | |
249 | return 0; | |
250 | } | |
13947f43 TK |
251 | #endif |
252 | ||
0b23fb36 IY |
253 | static int fec_rx_task_enable(struct fec_priv *fec) |
254 | { | |
c0b5a3bb | 255 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
256 | return 0; |
257 | } | |
258 | ||
259 | static int fec_rx_task_disable(struct fec_priv *fec) | |
260 | { | |
261 | return 0; | |
262 | } | |
263 | ||
264 | static int fec_tx_task_enable(struct fec_priv *fec) | |
265 | { | |
c0b5a3bb | 266 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
267 | return 0; |
268 | } | |
269 | ||
270 | static int fec_tx_task_disable(struct fec_priv *fec) | |
271 | { | |
272 | return 0; | |
273 | } | |
274 | ||
275 | /** | |
276 | * Initialize receive task's buffer descriptors | |
277 | * @param[in] fec all we know about the device yet | |
278 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 279 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
280 | * @return 0 on success |
281 | * | |
79e5f27b | 282 | * Init all RX descriptors to default values. |
0b23fb36 | 283 | */ |
79e5f27b | 284 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 285 | { |
5c1ad3e6 | 286 | uint32_t size; |
79e5f27b | 287 | uint8_t *data; |
5c1ad3e6 EN |
288 | int i; |
289 | ||
0b23fb36 | 290 | /* |
79e5f27b MV |
291 | * Reload the RX descriptors with default values and wipe |
292 | * the RX buffers. | |
0b23fb36 | 293 | */ |
5c1ad3e6 EN |
294 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
295 | for (i = 0; i < count; i++) { | |
79e5f27b MV |
296 | data = (uint8_t *)fec->rbd_base[i].data_pointer; |
297 | memset(data, 0, dsize); | |
298 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
299 | ||
300 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
301 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
302 | } |
303 | ||
304 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 305 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
306 | fec->rbd_index = 0; |
307 | ||
79e5f27b MV |
308 | flush_dcache_range((unsigned)fec->rbd_base, |
309 | (unsigned)fec->rbd_base + size); | |
0b23fb36 IY |
310 | } |
311 | ||
312 | /** | |
313 | * Initialize transmit task's buffer descriptors | |
314 | * @param[in] fec all we know about the device yet | |
315 | * | |
316 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
317 | * Note: There is a race condition in the hardware. When only one BD is in | |
318 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
319 | * This bit in combination with the READY bit results into double transmit | |
320 | * of each data buffer. It seems the state machine checks READY earlier then | |
321 | * resetting it after the first transfer. | |
322 | * Using two BDs solves this issue. | |
323 | */ | |
324 | static void fec_tbd_init(struct fec_priv *fec) | |
325 | { | |
5c1ad3e6 EN |
326 | unsigned addr = (unsigned)fec->tbd_base; |
327 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
328 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
329 | |
330 | memset(fec->tbd_base, 0, size); | |
331 | fec->tbd_base[0].status = 0; | |
332 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 333 | fec->tbd_index = 0; |
79e5f27b | 334 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
335 | } |
336 | ||
337 | /** | |
338 | * Mark the given read buffer descriptor as free | |
339 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
340 | * @param[in] pRbd buffer descriptor to mark free again | |
341 | */ | |
342 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
343 | { | |
5c1ad3e6 | 344 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 345 | if (last) |
5c1ad3e6 EN |
346 | flags |= FEC_RBD_WRAP; |
347 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
348 | writew(0, &pRbd->data_length); |
349 | } | |
350 | ||
be252b65 FE |
351 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
352 | unsigned char *mac) | |
0b23fb36 | 353 | { |
be252b65 | 354 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 355 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
356 | } |
357 | ||
4294b248 | 358 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 359 | { |
4294b248 | 360 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
361 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
362 | ||
363 | writel(0, &fec->eth->iaddr1); | |
364 | writel(0, &fec->eth->iaddr2); | |
365 | writel(0, &fec->eth->gaddr1); | |
366 | writel(0, &fec->eth->gaddr2); | |
367 | ||
368 | /* | |
369 | * Set physical address | |
370 | */ | |
371 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
372 | &fec->eth->paddr1); | |
373 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
a5990b26 MV |
378 | /* |
379 | * Do initial configuration of the FEC registers | |
380 | */ | |
381 | static void fec_reg_setup(struct fec_priv *fec) | |
382 | { | |
383 | uint32_t rcntrl; | |
384 | ||
385 | /* | |
386 | * Set interrupt mask register | |
387 | */ | |
388 | writel(0x00000000, &fec->eth->imask); | |
389 | ||
390 | /* | |
391 | * Clear FEC-Lite interrupt event register(IEVENT) | |
392 | */ | |
393 | writel(0xffffffff, &fec->eth->ievent); | |
394 | ||
395 | ||
396 | /* | |
397 | * Set FEC-Lite receive control register(R_CNTRL): | |
398 | */ | |
399 | ||
400 | /* Start with frame length = 1518, common for all modes. */ | |
401 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 402 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
403 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
404 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
405 | rcntrl |= FEC_RCNTRL_RGMII; |
406 | else if (fec->xcv_type == RMII) | |
407 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
408 | |
409 | writel(rcntrl, &fec->eth->r_cntrl); | |
410 | } | |
411 | ||
0b23fb36 IY |
412 | /** |
413 | * Start the FEC engine | |
414 | * @param[in] dev Our device to handle | |
415 | */ | |
416 | static int fec_open(struct eth_device *edev) | |
417 | { | |
418 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 419 | int speed; |
5c1ad3e6 EN |
420 | uint32_t addr, size; |
421 | int i; | |
0b23fb36 IY |
422 | |
423 | debug("fec_open: fec_open(dev)\n"); | |
424 | /* full-duplex, heartbeat disabled */ | |
425 | writel(1 << 2, &fec->eth->x_cntrl); | |
426 | fec->rbd_index = 0; | |
427 | ||
5c1ad3e6 EN |
428 | /* Invalidate all descriptors */ |
429 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
430 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
431 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
432 | ||
433 | /* Flush the descriptors into RAM */ | |
434 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
435 | ARCH_DMA_MINALIGN); | |
436 | addr = (uint32_t)fec->rbd_base; | |
437 | flush_dcache_range(addr, addr + size); | |
438 | ||
28774cba | 439 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
440 | /* Enable ENET HW endian SWAP */ |
441 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
442 | &fec->eth->ecntrl); | |
443 | /* Enable ENET store and forward mode */ | |
444 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
445 | &fec->eth->x_wmrk); | |
446 | #endif | |
0b23fb36 IY |
447 | /* |
448 | * Enable FEC-Lite controller | |
449 | */ | |
cb17b92d JR |
450 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
451 | &fec->eth->ecntrl); | |
7df51fd8 | 452 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 JR |
453 | udelay(100); |
454 | /* | |
455 | * setup the MII gasket for RMII mode | |
456 | */ | |
457 | ||
458 | /* disable the gasket */ | |
459 | writew(0, &fec->eth->miigsk_enr); | |
460 | ||
461 | /* wait for the gasket to be disabled */ | |
462 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
463 | udelay(2); | |
464 | ||
465 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
466 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
467 | ||
468 | /* re-enable the gasket */ | |
469 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
470 | ||
471 | /* wait until MII gasket is ready */ | |
472 | int max_loops = 10; | |
473 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
474 | if (--max_loops <= 0) { | |
475 | printf("WAIT for MII Gasket ready timed out\n"); | |
476 | break; | |
477 | } | |
478 | } | |
479 | #endif | |
0b23fb36 | 480 | |
13947f43 | 481 | #ifdef CONFIG_PHYLIB |
4dc27eed | 482 | { |
13947f43 | 483 | /* Start up the PHY */ |
11af8d65 TT |
484 | int ret = phy_startup(fec->phydev); |
485 | ||
486 | if (ret) { | |
487 | printf("Could not initialize PHY %s\n", | |
488 | fec->phydev->dev->name); | |
489 | return ret; | |
490 | } | |
13947f43 | 491 | speed = fec->phydev->speed; |
13947f43 TK |
492 | } |
493 | #else | |
0b23fb36 | 494 | miiphy_wait_aneg(edev); |
28774cba | 495 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 496 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 497 | #endif |
0b23fb36 | 498 | |
28774cba TK |
499 | #ifdef FEC_QUIRK_ENET_MAC |
500 | { | |
501 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 502 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
503 | if (speed == _1000BASET) |
504 | ecr |= FEC_ECNTRL_SPEED; | |
505 | else if (speed != _100BASET) | |
506 | rcr |= FEC_RCNTRL_RMII_10T; | |
507 | writel(ecr, &fec->eth->ecntrl); | |
508 | writel(rcr, &fec->eth->r_cntrl); | |
509 | } | |
510 | #endif | |
511 | debug("%s:Speed=%i\n", __func__, speed); | |
512 | ||
0b23fb36 IY |
513 | /* |
514 | * Enable SmartDMA receive task | |
515 | */ | |
516 | fec_rx_task_enable(fec); | |
517 | ||
518 | udelay(100000); | |
519 | return 0; | |
520 | } | |
521 | ||
522 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
523 | { | |
0b23fb36 | 524 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 525 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
79e5f27b | 526 | int i; |
0b23fb36 | 527 | |
e9319f11 JR |
528 | /* Initialize MAC address */ |
529 | fec_set_hwaddr(dev); | |
530 | ||
0b23fb36 | 531 | /* |
79e5f27b | 532 | * Setup transmit descriptors, there are two in total. |
0b23fb36 | 533 | */ |
79e5f27b | 534 | fec_tbd_init(fec); |
0b23fb36 | 535 | |
79e5f27b MV |
536 | /* Setup receive descriptors. */ |
537 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 538 | |
a5990b26 | 539 | fec_reg_setup(fec); |
9eb3770b | 540 | |
f41471e6 | 541 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 542 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 543 | |
0b23fb36 IY |
544 | /* |
545 | * Set Opcode/Pause Duration Register | |
546 | */ | |
547 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
548 | writel(0x2, &fec->eth->x_wmrk); | |
549 | /* | |
550 | * Set multicast address filter | |
551 | */ | |
552 | writel(0x00000000, &fec->eth->gaddr1); | |
553 | writel(0x00000000, &fec->eth->gaddr2); | |
554 | ||
555 | ||
fbecbaa1 PF |
556 | /* Do not access reserved register for i.MX6UL */ |
557 | if (!is_cpu_type(MXC_CPU_MX6UL)) { | |
558 | /* clear MIB RAM */ | |
559 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
560 | writel(0, i); | |
0b23fb36 | 561 | |
fbecbaa1 PF |
562 | /* FIFO receive start register */ |
563 | writel(0x520, &fec->eth->r_fstart); | |
564 | } | |
0b23fb36 IY |
565 | |
566 | /* size and address of each buffer */ | |
567 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
568 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
569 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
570 | ||
13947f43 | 571 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
572 | if (fec->xcv_type != SEVENWIRE) |
573 | miiphy_restart_aneg(dev); | |
13947f43 | 574 | #endif |
0b23fb36 IY |
575 | fec_open(dev); |
576 | return 0; | |
577 | } | |
578 | ||
579 | /** | |
580 | * Halt the FEC engine | |
581 | * @param[in] dev Our device to handle | |
582 | */ | |
583 | static void fec_halt(struct eth_device *dev) | |
584 | { | |
9e27e9dc | 585 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
586 | int counter = 0xffff; |
587 | ||
588 | /* | |
589 | * issue graceful stop command to the FEC transmitter if necessary | |
590 | */ | |
cb17b92d | 591 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
592 | &fec->eth->x_cntrl); |
593 | ||
594 | debug("eth_halt: wait for stop regs\n"); | |
595 | /* | |
596 | * wait for graceful stop to register | |
597 | */ | |
598 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 599 | udelay(1); |
0b23fb36 IY |
600 | |
601 | /* | |
602 | * Disable SmartDMA tasks | |
603 | */ | |
604 | fec_tx_task_disable(fec); | |
605 | fec_rx_task_disable(fec); | |
606 | ||
607 | /* | |
608 | * Disable the Ethernet Controller | |
609 | * Note: this will also reset the BD index counter! | |
610 | */ | |
740d6ae5 JR |
611 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
612 | &fec->eth->ecntrl); | |
0b23fb36 IY |
613 | fec->rbd_index = 0; |
614 | fec->tbd_index = 0; | |
0b23fb36 IY |
615 | debug("eth_halt: done\n"); |
616 | } | |
617 | ||
618 | /** | |
619 | * Transmit one frame | |
620 | * @param[in] dev Our ethernet device to handle | |
621 | * @param[in] packet Pointer to the data to be transmitted | |
622 | * @param[in] length Data count in bytes | |
623 | * @return 0 on success | |
624 | */ | |
442dac4c | 625 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
626 | { |
627 | unsigned int status; | |
efe24d2e | 628 | uint32_t size, end; |
5c1ad3e6 | 629 | uint32_t addr; |
bc1ce150 MV |
630 | int timeout = FEC_XFER_TIMEOUT; |
631 | int ret = 0; | |
0b23fb36 IY |
632 | |
633 | /* | |
634 | * This routine transmits one frame. This routine only accepts | |
635 | * 6-byte Ethernet addresses. | |
636 | */ | |
637 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
638 | ||
639 | /* | |
640 | * Check for valid length of data. | |
641 | */ | |
642 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 643 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
644 | return -1; |
645 | } | |
646 | ||
647 | /* | |
5c1ad3e6 EN |
648 | * Setup the transmit buffer. We are always using the first buffer for |
649 | * transmission, the second will be empty and only used to stop the DMA | |
650 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 651 | */ |
5c1ad3e6 | 652 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
653 | swap_packet((uint32_t *)packet, length); |
654 | #endif | |
5c1ad3e6 EN |
655 | |
656 | addr = (uint32_t)packet; | |
efe24d2e MV |
657 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
658 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
659 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 660 | |
0b23fb36 | 661 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
662 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
663 | ||
0b23fb36 IY |
664 | /* |
665 | * update BD's status now | |
666 | * This block: | |
667 | * - is always the last in a chain (means no chain) | |
668 | * - should transmitt the CRC | |
669 | * - might be the last BD in the list, so the address counter should | |
670 | * wrap (-> keep the WRAP flag) | |
671 | */ | |
672 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
673 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
674 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
675 | ||
5c1ad3e6 EN |
676 | /* |
677 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
678 | * After this code, the descriptors will be safely in RAM and we | |
679 | * can start DMA. | |
680 | */ | |
681 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
682 | addr = (uint32_t)fec->tbd_base; | |
683 | flush_dcache_range(addr, addr + size); | |
684 | ||
ab94cd49 MV |
685 | /* |
686 | * Below we read the DMA descriptor's last four bytes back from the | |
687 | * DRAM. This is important in order to make sure that all WRITE | |
688 | * operations on the bus that were triggered by previous cache FLUSH | |
689 | * have completed. | |
690 | * | |
691 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
692 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
693 | * for the bus structure of MX28. The scenario is as follows: | |
694 | * | |
695 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
696 | * to DRAM due to flush_dcache_range() | |
697 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
698 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
699 | * | |
700 | * Note that 2) does sometimes finish before 1) due to reordering of | |
701 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
702 | * DMA descriptor is fully written into DRAM. This results in occasional | |
703 | * corruption of the DMA descriptor. | |
704 | */ | |
705 | readl(addr + size - 4); | |
706 | ||
0b23fb36 IY |
707 | /* |
708 | * Enable SmartDMA transmit task | |
709 | */ | |
710 | fec_tx_task_enable(fec); | |
711 | ||
712 | /* | |
5c1ad3e6 EN |
713 | * Wait until frame is sent. On each turn of the wait cycle, we must |
714 | * invalidate data cache to see what's really in RAM. Also, we need | |
715 | * barrier here. | |
0b23fb36 | 716 | */ |
67449098 | 717 | while (--timeout) { |
c0b5a3bb | 718 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 719 | break; |
0b23fb36 | 720 | } |
5c1ad3e6 | 721 | |
f599288d | 722 | if (!timeout) { |
67449098 | 723 | ret = -EINVAL; |
f599288d FE |
724 | goto out; |
725 | } | |
726 | ||
727 | /* | |
728 | * The TDAR bit is cleared when the descriptors are all out from TX | |
729 | * but on mx6solox we noticed that the READY bit is still not cleared | |
730 | * right after TDAR. | |
731 | * These are two distinct signals, and in IC simulation, we found that | |
732 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
733 | * cleared. | |
734 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
735 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
736 | * version. | |
737 | * | |
738 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
739 | * which covers the mx6solox case and does not harm the other SoCs. | |
740 | */ | |
741 | timeout = FEC_XFER_TIMEOUT; | |
742 | while (--timeout) { | |
743 | invalidate_dcache_range(addr, addr + size); | |
744 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
745 | FEC_TBD_READY)) | |
746 | break; | |
747 | } | |
67449098 | 748 | |
f599288d | 749 | if (!timeout) |
67449098 MV |
750 | ret = -EINVAL; |
751 | ||
f599288d | 752 | out: |
67449098 | 753 | debug("fec_send: status 0x%x index %d ret %i\n", |
0b23fb36 | 754 | readw(&fec->tbd_base[fec->tbd_index].status), |
67449098 | 755 | fec->tbd_index, ret); |
0b23fb36 IY |
756 | /* for next transmission use the other buffer */ |
757 | if (fec->tbd_index) | |
758 | fec->tbd_index = 0; | |
759 | else | |
760 | fec->tbd_index = 1; | |
761 | ||
bc1ce150 | 762 | return ret; |
0b23fb36 IY |
763 | } |
764 | ||
765 | /** | |
766 | * Pull one frame from the card | |
767 | * @param[in] dev Our ethernet device to handle | |
768 | * @return Length of packet read | |
769 | */ | |
770 | static int fec_recv(struct eth_device *dev) | |
771 | { | |
772 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
773 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
774 | unsigned long ievent; | |
775 | int frame_length, len = 0; | |
0b23fb36 | 776 | uint16_t bd_status; |
efe24d2e | 777 | uint32_t addr, size, end; |
5c1ad3e6 | 778 | int i; |
fd37f195 | 779 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
0b23fb36 IY |
780 | |
781 | /* | |
782 | * Check if any critical events have happened | |
783 | */ | |
784 | ievent = readl(&fec->eth->ievent); | |
785 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 786 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
787 | if (ievent & FEC_IEVENT_BABR) { |
788 | fec_halt(dev); | |
789 | fec_init(dev, fec->bd); | |
790 | printf("some error: 0x%08lx\n", ievent); | |
791 | return 0; | |
792 | } | |
793 | if (ievent & FEC_IEVENT_HBERR) { | |
794 | /* Heartbeat error */ | |
795 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
796 | &fec->eth->x_cntrl); | |
797 | } | |
798 | if (ievent & FEC_IEVENT_GRA) { | |
799 | /* Graceful stop complete */ | |
800 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
801 | fec_halt(dev); | |
802 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
803 | &fec->eth->x_cntrl); | |
804 | fec_init(dev, fec->bd); | |
805 | } | |
806 | } | |
807 | ||
808 | /* | |
5c1ad3e6 EN |
809 | * Read the buffer status. Before the status can be read, the data cache |
810 | * must be invalidated, because the data in RAM might have been changed | |
811 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
812 | * no need to worry they'd overlap. | |
813 | * | |
814 | * WARNING: By invalidating the descriptor here, we also invalidate | |
815 | * the descriptors surrounding this one. Therefore we can NOT change the | |
816 | * contents of this descriptor nor the surrounding ones. The problem is | |
817 | * that in order to mark the descriptor as processed, we need to change | |
818 | * the descriptor. The solution is to mark the whole cache line when all | |
819 | * descriptors in the cache line are processed. | |
0b23fb36 | 820 | */ |
5c1ad3e6 EN |
821 | addr = (uint32_t)rbd; |
822 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
823 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
824 | invalidate_dcache_range(addr, addr + size); | |
825 | ||
0b23fb36 IY |
826 | bd_status = readw(&rbd->status); |
827 | debug("fec_recv: status 0x%x\n", bd_status); | |
828 | ||
829 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
830 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
831 | ((readw(&rbd->data_length) - 4) > 14)) { | |
832 | /* | |
833 | * Get buffer address and size | |
834 | */ | |
b189584b | 835 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 836 | frame_length = readw(&rbd->data_length) - 4; |
5c1ad3e6 EN |
837 | /* |
838 | * Invalidate data cache over the buffer | |
839 | */ | |
efe24d2e MV |
840 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
841 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
842 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 843 | |
0b23fb36 IY |
844 | /* |
845 | * Fill the buffer and pass it to upper layers | |
846 | */ | |
5c1ad3e6 | 847 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
b189584b | 848 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 849 | #endif |
b189584b | 850 | memcpy(buff, (char *)addr, frame_length); |
1fd92db8 | 851 | net_process_received_packet(buff, frame_length); |
0b23fb36 IY |
852 | len = frame_length; |
853 | } else { | |
854 | if (bd_status & FEC_RBD_ERR) | |
b189584b AA |
855 | printf("error frame: 0x%08x 0x%08x\n", |
856 | addr, bd_status); | |
0b23fb36 | 857 | } |
5c1ad3e6 | 858 | |
0b23fb36 | 859 | /* |
5c1ad3e6 EN |
860 | * Free the current buffer, restart the engine and move forward |
861 | * to the next buffer. Here we check if the whole cacheline of | |
862 | * descriptors was already processed and if so, we mark it free | |
863 | * as whole. | |
0b23fb36 | 864 | */ |
5c1ad3e6 EN |
865 | size = RXDESC_PER_CACHELINE - 1; |
866 | if ((fec->rbd_index & size) == size) { | |
867 | i = fec->rbd_index - size; | |
868 | addr = (uint32_t)&fec->rbd_base[i]; | |
869 | for (; i <= fec->rbd_index ; i++) { | |
870 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
871 | &fec->rbd_base[i]); | |
872 | } | |
873 | flush_dcache_range(addr, | |
874 | addr + ARCH_DMA_MINALIGN); | |
875 | } | |
876 | ||
0b23fb36 IY |
877 | fec_rx_task_enable(fec); |
878 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
879 | } | |
880 | debug("fec_recv: stop\n"); | |
881 | ||
882 | return len; | |
883 | } | |
884 | ||
ef8e3a3b TK |
885 | static void fec_set_dev_name(char *dest, int dev_id) |
886 | { | |
887 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
888 | } | |
889 | ||
79e5f27b MV |
890 | static int fec_alloc_descs(struct fec_priv *fec) |
891 | { | |
892 | unsigned int size; | |
893 | int i; | |
894 | uint8_t *data; | |
895 | ||
896 | /* Allocate TX descriptors. */ | |
897 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
898 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
899 | if (!fec->tbd_base) | |
900 | goto err_tx; | |
901 | ||
902 | /* Allocate RX descriptors. */ | |
903 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
904 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
905 | if (!fec->rbd_base) | |
906 | goto err_rx; | |
907 | ||
908 | memset(fec->rbd_base, 0, size); | |
909 | ||
910 | /* Allocate RX buffers. */ | |
911 | ||
912 | /* Maximum RX buffer size. */ | |
db5b7f56 | 913 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 914 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 915 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
916 | if (!data) { |
917 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
918 | goto err_ring; | |
919 | } | |
920 | ||
921 | memset(data, 0, size); | |
922 | ||
923 | fec->rbd_base[i].data_pointer = (uint32_t)data; | |
924 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
925 | fec->rbd_base[i].data_length = 0; | |
926 | /* Flush the buffer to memory. */ | |
927 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
928 | } | |
929 | ||
930 | /* Mark the last RBD to close the ring. */ | |
931 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
932 | ||
933 | fec->rbd_index = 0; | |
934 | fec->tbd_index = 0; | |
935 | ||
936 | return 0; | |
937 | ||
938 | err_ring: | |
939 | for (; i >= 0; i--) | |
940 | free((void *)fec->rbd_base[i].data_pointer); | |
941 | free(fec->rbd_base); | |
942 | err_rx: | |
943 | free(fec->tbd_base); | |
944 | err_tx: | |
945 | return -ENOMEM; | |
946 | } | |
947 | ||
948 | static void fec_free_descs(struct fec_priv *fec) | |
949 | { | |
950 | int i; | |
951 | ||
952 | for (i = 0; i < FEC_RBD_NUM; i++) | |
953 | free((void *)fec->rbd_base[i].data_pointer); | |
954 | free(fec->rbd_base); | |
955 | free(fec->tbd_base); | |
956 | } | |
957 | ||
fe428b90 TK |
958 | #ifdef CONFIG_PHYLIB |
959 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
960 | struct mii_dev *bus, struct phy_device *phydev) | |
961 | #else | |
962 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
963 | struct mii_dev *bus, int phy_id) | |
964 | #endif | |
0b23fb36 | 965 | { |
0b23fb36 | 966 | struct eth_device *edev; |
9e27e9dc | 967 | struct fec_priv *fec; |
0b23fb36 | 968 | unsigned char ethaddr[6]; |
e382fb48 MV |
969 | uint32_t start; |
970 | int ret = 0; | |
0b23fb36 IY |
971 | |
972 | /* create and fill edev struct */ | |
973 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
974 | if (!edev) { | |
9e27e9dc | 975 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
976 | ret = -ENOMEM; |
977 | goto err1; | |
9e27e9dc MV |
978 | } |
979 | ||
980 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
981 | if (!fec) { | |
982 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
983 | ret = -ENOMEM; |
984 | goto err2; | |
0b23fb36 | 985 | } |
9e27e9dc | 986 | |
de0b9576 | 987 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
988 | memset(fec, 0, sizeof(*fec)); |
989 | ||
79e5f27b MV |
990 | ret = fec_alloc_descs(fec); |
991 | if (ret) | |
992 | goto err3; | |
993 | ||
0b23fb36 IY |
994 | edev->priv = fec; |
995 | edev->init = fec_init; | |
996 | edev->send = fec_send; | |
997 | edev->recv = fec_recv; | |
998 | edev->halt = fec_halt; | |
fb57ec97 | 999 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 1000 | |
9e27e9dc | 1001 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
1002 | fec->bd = bd; |
1003 | ||
392b8502 | 1004 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
1005 | |
1006 | /* Reset chip. */ | |
cb17b92d | 1007 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
1008 | start = get_timer(0); |
1009 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1010 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
1011 | printf("FEC MXC: Timeout reseting chip\n"); | |
79e5f27b | 1012 | goto err4; |
e382fb48 | 1013 | } |
0b23fb36 | 1014 | udelay(10); |
e382fb48 | 1015 | } |
0b23fb36 | 1016 | |
a5990b26 | 1017 | fec_reg_setup(fec); |
ef8e3a3b TK |
1018 | fec_set_dev_name(edev->name, dev_id); |
1019 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
1020 | fec->bus = bus; |
1021 | fec_mii_setspeed(bus->priv); | |
1022 | #ifdef CONFIG_PHYLIB | |
1023 | fec->phydev = phydev; | |
1024 | phy_connect_dev(phydev, edev); | |
1025 | /* Configure phy */ | |
1026 | phy_config(phydev); | |
1027 | #else | |
9e27e9dc | 1028 | fec->phy_id = phy_id; |
fe428b90 TK |
1029 | #endif |
1030 | eth_register(edev); | |
1031 | ||
1032 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { | |
1033 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
1034 | memcpy(edev->enetaddr, ethaddr, 6); | |
ddb636bd EN |
1035 | if (!getenv("ethaddr")) |
1036 | eth_setenv_enetaddr("ethaddr", ethaddr); | |
fe428b90 TK |
1037 | } |
1038 | return ret; | |
79e5f27b MV |
1039 | err4: |
1040 | fec_free_descs(fec); | |
fe428b90 TK |
1041 | err3: |
1042 | free(fec); | |
1043 | err2: | |
1044 | free(edev); | |
1045 | err1: | |
1046 | return ret; | |
1047 | } | |
1048 | ||
1049 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) | |
1050 | { | |
1051 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; | |
1052 | struct mii_dev *bus; | |
1053 | int ret; | |
0b23fb36 | 1054 | |
13947f43 TK |
1055 | bus = mdio_alloc(); |
1056 | if (!bus) { | |
1057 | printf("mdio_alloc failed\n"); | |
fe428b90 | 1058 | return NULL; |
13947f43 TK |
1059 | } |
1060 | bus->read = fec_phy_read; | |
1061 | bus->write = fec_phy_write; | |
fe428b90 | 1062 | bus->priv = eth; |
ef8e3a3b | 1063 | fec_set_dev_name(bus->name, dev_id); |
fe428b90 TK |
1064 | |
1065 | ret = mdio_register(bus); | |
1066 | if (ret) { | |
1067 | printf("mdio_register failed\n"); | |
1068 | free(bus); | |
1069 | return NULL; | |
1070 | } | |
1071 | fec_mii_setspeed(eth); | |
1072 | return bus; | |
1073 | } | |
1074 | ||
1075 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
1076 | { | |
1077 | uint32_t base_mii; | |
1078 | struct mii_dev *bus = NULL; | |
1079 | #ifdef CONFIG_PHYLIB | |
1080 | struct phy_device *phydev = NULL; | |
1081 | #endif | |
1082 | int ret; | |
1083 | ||
5c1ad3e6 | 1084 | #ifdef CONFIG_MX28 |
13947f43 TK |
1085 | /* |
1086 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1087 | * Only the first one can access the MDIO bus. | |
1088 | */ | |
fe428b90 | 1089 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1090 | #else |
fe428b90 | 1091 | base_mii = addr; |
13947f43 | 1092 | #endif |
fe428b90 TK |
1093 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1094 | bus = fec_get_miibus(base_mii, dev_id); | |
1095 | if (!bus) | |
1096 | return -ENOMEM; | |
4dc27eed | 1097 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1098 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed TK |
1099 | if (!phydev) { |
1100 | free(bus); | |
fe428b90 | 1101 | return -ENOMEM; |
4dc27eed | 1102 | } |
fe428b90 TK |
1103 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1104 | #else | |
1105 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1106 | #endif |
fe428b90 TK |
1107 | if (ret) { |
1108 | #ifdef CONFIG_PHYLIB | |
1109 | free(phydev); | |
1110 | #endif | |
1111 | free(bus); | |
1112 | } | |
e382fb48 | 1113 | return ret; |
eef24480 | 1114 | } |
0b23fb36 | 1115 | |
eef24480 TK |
1116 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1117 | int fecmxc_initialize(bd_t *bd) | |
1118 | { | |
1119 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1120 | IMX_FEC_BASE); | |
0b23fb36 | 1121 | } |
eef24480 | 1122 | #endif |
2e5f4421 | 1123 | |
13947f43 | 1124 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1125 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1126 | { | |
1127 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1128 | fec->mii_postcall = cb; | |
1129 | return 0; | |
1130 | } | |
13947f43 | 1131 | #endif |