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2002-06-07 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
196496ed
CD		 12002-06-07 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c: Clean up formatting of a few comments.
4 (value_fpr): Reformat switch statement.
5
cfe9ea23
CD		 62002-06-06 Chris Demetriou <cgd@broadcom.com>
7 Ed Satterthwaite <ehs@broadcom.com>
8
9 * cp1.h: New file.
10 * sim-main.h: Include cp1.h.
11 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
12 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
13 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
14 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
15 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
16 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
17 * cp1.c: Don't include sim-fpu.h; already included by
18 sim-main.h. Clean up formatting of some comments.
19 (NaN, Equal, Less): Remove.
20 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
21 (fp_cmp): New functions.
22 * mips.igen (do_c_cond_fmt): Remove.
23 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
24 Compare. Add result tracing.
25 (CxC1): Remove, replace with...
26 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
27 (DMxC1): Remove, replace with...
28 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
29 (MxC1): Remove, replace with...
30 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
31
ee7254b0
CD		 322002-06-04 Chris Demetriou <cgd@broadcom.com>
33
34 * sim-main.h (FGRIDX): Remove, replace all uses with...
35 (FGR_BASE): New macro.
36 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
37 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
38 (NR_FGR, FGR): Likewise.
39 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
40 * mips.igen: Likewise.
41
d3eb724f
CD		 422002-06-04 Chris Demetriou <cgd@broadcom.com>
43
44 * cp1.c: Add an FSF Copyright notice to this file.
45
ba46ddd0
CD		 462002-06-04 Chris Demetriou <cgd@broadcom.com>
47 Ed Satterthwaite <ehs@broadcom.com>
48
49 * cp1.c (Infinity): Remove.
50 * sim-main.h (Infinity): Likewise.
51
52 * cp1.c (fp_unary, fp_binary): New functions.
53 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
54 (fp_sqrt): New functions, implemented in terms of the above.
55 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
56 (Recip, SquareRoot): Remove (replaced by functions above).
57 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
58 (fp_recip, fp_sqrt): New prototypes.
59 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
60 (Recip, SquareRoot): Replace prototypes with #defines which
61 invoke the functions above.
62
18d8a52d
CD		 632002-06-03 Chris Demetriou <cgd@broadcom.com>
64
65 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
66 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
67 file, remove PARAMS from prototypes.
68 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
69 simulator state arguments.
70 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
71 pass simulator state arguments.
72 * cp1.c (SD): Redefine as CPU_STATE(cpu).
73 (store_fpr, convert): Remove 'sd' argument.
74 (value_fpr): Likewise. Convert to use 'SD' instead.
75
0f154cbd
CD		 762002-06-03 Chris Demetriou <cgd@broadcom.com>
77
78 * cp1.c (Min, Max): Remove #if 0'd functions.
79 * sim-main.h (Min, Max): Remove.
80
e80fc152
CD		 812002-06-03 Chris Demetriou <cgd@broadcom.com>
82
83 * cp1.c: fix formatting of switch case and default labels.
84 * interp.c: Likewise.
85 * sim-main.c: Likewise.
86
bad673a9
CD		 872002-06-03 Chris Demetriou <cgd@broadcom.com>
88
89 * cp1.c: Clean up comments which describe FP formats.
90 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
91
7cbea089
CD		 922002-06-03 Chris Demetriou <cgd@broadcom.com>
93 Ed Satterthwaite <ehs@broadcom.com>
94
95 * configure.in (mipsisa64sb1*-*-*): New target for supporting
96 Broadcom SiByte SB-1 processor configurations.
97 * configure: Regenerate.
98 * sb1.igen: New file.
99 * mips.igen: Include sb1.igen.
100 (sb1): New model.
101 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
102 * mdmx.igen: Add "sb1" model to all appropriate functions and
103 instructions.
104 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
105 (ob_func, ob_acc): Reference the above.
106 (qh_acc): Adjust to keep the same size as ob_acc.
107 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
108 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
109
909daa82
CD		 1102002-06-03 Chris Demetriou <cgd@broadcom.com>
111
112 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
113
f4f1b9f1
CD		 1142002-06-02 Chris Demetriou <cgd@broadcom.com>
115 Ed Satterthwaite <ehs@broadcom.com>
116
117 * mips.igen (mdmx): New (pseudo-)model.
118 * mdmx.c, mdmx.igen: New files.
119 * Makefile.in (SIM_OBJS): Add mdmx.o.
120 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
121 New typedefs.
122 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
123 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
124 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
125 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
126 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
127 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
128 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
129 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
130 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
131 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
132 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
133 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
134 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
135 (qh_fmtsel): New macros.
136 (_sim_cpu): New member "acc".
137 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
138 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
139
5accf1ff
CD		 1402002-05-01 Chris Demetriou <cgd@broadcom.com>
141
142 * interp.c: Use 'deprecated' rather than 'depreciated.'
143 * sim-main.h: Likewise.
144
402586aa
CD		 1452002-05-01 Chris Demetriou <cgd@broadcom.com>
146
147 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
148 which wouldn't compile anyway.
149 * sim-main.h (unpredictable_action): New function prototype.
150 (Unpredictable): Define to call igen function unpredictable().
151 (NotWordValue): New macro to call igen function not_word_value().
152 (UndefinedResult): Remove.
153 * interp.c (undefined_result): Remove.
154 (unpredictable_action): New function.
155 * mips.igen (not_word_value, unpredictable): New functions.
156 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
157 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
158 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
159 NotWordValue() to check for unpredictable inputs, then
160 Unpredictable() to handle them.
161
c9b9995a
CD		 1622002-02-24 Chris Demetriou <cgd@broadcom.com>
163
164 * mips.igen: Fix formatting of calls to Unpredictable().
165
e1015982
AC		 1662002-04-20 Andrew Cagney <ac131313@redhat.com>
167
168 * interp.c (sim_open): Revert previous change.
169
b882a66b
AO		 1702002-04-18 Alexandre Oliva <aoliva@redhat.com>
171
172 * interp.c (sim_open): Disable chunk of code that wrote code in
173 vector table entries.
174
c429b7dd
CD		 1752002-03-19 Chris Demetriou <cgd@broadcom.com>
176
177 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
178 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
179 unused definitions.
180
37d146fa
CD		 1812002-03-19 Chris Demetriou <cgd@broadcom.com>
182
183 * cp1.c: Fix many formatting issues.
184
07892c0b
CD		 1852002-03-19 Chris G. Demetriou <cgd@broadcom.com>
186
187 * cp1.c (fpu_format_name): New function to replace...
188 (DOFMT): This. Delete, and update all callers.
189 (fpu_rounding_mode_name): New function to replace...
190 (RMMODE): This. Delete, and update all callers.
191
487f79b7
CD		 1922002-03-19 Chris G. Demetriou <cgd@broadcom.com>
193
194 * interp.c: Move FPU support routines from here to...
195 * cp1.c: Here. New file.
196 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
197 (cp1.o): New target.
198
1e799e28
CD		 1992002-03-12 Chris Demetriou <cgd@broadcom.com>
200
201 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
202 * mips.igen (mips32, mips64): New models, add to all instructions
203 and functions as appropriate.
204 (loadstore_ea, check_u64): New variant for model mips64.
205 (check_fmt_p): New variant for models mipsV and mips64, remove
206 mipsV model marking fro other variant.
207 (SLL) Rename to...
208 (SLLa) this.
209 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
210 for mips32 and mips64.
211 (DCLO, DCLZ): New instructions for mips64.
212
82f728db
CD		 2132002-03-07 Chris Demetriou <cgd@broadcom.com>
214
215 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
216 immediate or code as a hex value with the "%#lx" format.
217 (ANDI): Likewise, and fix printed instruction name.
218
b96e7ef1
CD		 2192002-03-05 Chris Demetriou <cgd@broadcom.com>
220
221 * sim-main.h (UndefinedResult, Unpredictable): New macros
222 which currently do nothing.
223
d35d4f70
CD		 2242002-03-05 Chris Demetriou <cgd@broadcom.com>
225
226 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
227 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
228 (status_CU3): New definitions.
229
230 * sim-main.h (ExceptionCause): Add new values for MIPS32
231 and MIPS64: MDMX, MCheck, CacheErr. Update comments
232 for DebugBreakPoint and NMIReset to note their status in
233 MIPS32 and MIPS64.
234 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
235 (SignalExceptionCacheErr): New exception macros.
236
3ad6f714
CD		 2372002-03-05 Chris Demetriou <cgd@broadcom.com>
238
239 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
240 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
241 is always enabled.
242 (SignalExceptionCoProcessorUnusable): Take as argument the
243 unusable coprocessor number.
244
86b77b47
CD		 2452002-03-05 Chris Demetriou <cgd@broadcom.com>
246
247 * mips.igen: Fix formatting of all SignalException calls.
248
97a88e93 2492002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 250
251 * sim-main.h (SIGNEXTEND): Remove.
252
97a88e93 2532002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 254
255 * mips.igen: Remove gencode comment from top of file, fix
256 spelling in another comment.
257
97a88e93 2582002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 259
260 * mips.igen (check_fmt, check_fmt_p): New functions to check
261 whether specific floating point formats are usable.
262 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
263 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
264 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
265 Use the new functions.
266 (do_c_cond_fmt): Remove format checks...
267 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
268
97a88e93 2692002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 270
271 * mips.igen: Fix formatting of check_fpu calls.
272
41774c9d
CD		 2732002-03-03 Chris Demetriou <cgd@broadcom.com>
274
275 * mips.igen (FLOOR.L.fmt): Store correct destination register.
276
4a0bd876
CD		 2772002-03-03 Chris Demetriou <cgd@broadcom.com>
278
279 * mips.igen: Remove whitespace at end of lines.
280
09297648
CD		 2812002-03-02 Chris Demetriou <cgd@broadcom.com>
282
283 * mips.igen (loadstore_ea): New function to do effective
284 address calculations.
285 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
286 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
287 CACHE): Use loadstore_ea to do effective address computations.
288
043b7057
CD		 2892002-03-02 Chris Demetriou <cgd@broadcom.com>
290
291 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
292 * mips.igen (LL, CxC1, MxC1): Likewise.
293
c1e8ada4
CD		 2942002-03-02 Chris Demetriou <cgd@broadcom.com>
295
296 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
297 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
298 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
299 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
300 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
301 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
302 Don't split opcode fields by hand, use the opcode field values
303 provided by igen.
304
3e1dca16
CD		 3052002-03-01 Chris Demetriou <cgd@broadcom.com>
306
307 * mips.igen (do_divu): Fix spacing.
308
309 * mips.igen (do_dsllv): Move to be right before DSLLV,
310 to match the rest of the do_<shift> functions.
311
fff8d27d
CD		 3122002-03-01 Chris Demetriou <cgd@broadcom.com>
313
314 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
315 DSRL32, do_dsrlv): Trace inputs and results.
316
0d3e762b
CD		 3172002-03-01 Chris Demetriou <cgd@broadcom.com>
318
319 * mips.igen (CACHE): Provide instruction-printing string.
320
321 * interp.c (signal_exception): Comment tokens after #endif.
322
eb5fcf93
CD		 3232002-02-28 Chris Demetriou <cgd@broadcom.com>
324
325 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
326 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
327 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
328 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
329 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
330 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
331 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
332 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
333
bb22bd7d
CD		 3342002-02-28 Chris Demetriou <cgd@broadcom.com>
335
336 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
337 instruction-printing string.
338 (LWU): Use '64' as the filter flag.
339
91a177cf
CD		 3402002-02-28 Chris Demetriou <cgd@broadcom.com>
341
342 * mips.igen (SDXC1): Fix instruction-printing string.
343
387f484a
CD		 3442002-02-28 Chris Demetriou <cgd@broadcom.com>
345
346 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
347 filter flags "32,f".
348
3d81f391
CD		 3492002-02-27 Chris Demetriou <cgd@broadcom.com>
350
351 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
352 as the filter flag.
353
af5107af
CD		 3542002-02-27 Chris Demetriou <cgd@broadcom.com>
355
356 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
357 add a comma) so that it more closely match the MIPS ISA
358 documentation opcode partitioning.
359 (PREF): Put useful names on opcode fields, and include
360 instruction-printing string.
361
ca971540
CD		 3622002-02-27 Chris Demetriou <cgd@broadcom.com>
363
364 * mips.igen (check_u64): New function which in the future will
365 check whether 64-bit instructions are usable and signal an
366 exception if not. Currently a no-op.
367 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
368 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
369 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
370 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
371
372 * mips.igen (check_fpu): New function which in the future will
373 check whether FPU instructions are usable and signal an exception
374 if not. Currently a no-op.
375 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
376 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
377 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
378 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
379 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
380 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
381 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
382 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
383
1c47a468
CD		 3842002-02-27 Chris Demetriou <cgd@broadcom.com>
385
386 * mips.igen (do_load_left, do_load_right): Move to be immediately
387 following do_load.
388 (do_store_left, do_store_right): Move to be immediately following
389 do_store.
390
603a98e7
CD		 3912002-02-27 Chris Demetriou <cgd@broadcom.com>
392
393 * mips.igen (mipsV): New model name. Also, add it to
394 all instructions and functions where it is appropriate.
395
c5d00cc7
CD		 3962002-02-18 Chris Demetriou <cgd@broadcom.com>
397
398 * mips.igen: For all functions and instructions, list model
399 names that support that instruction one per line.
400
074e9cb8
CD		 4012002-02-11 Chris Demetriou <cgd@broadcom.com>
402
403 * mips.igen: Add some additional comments about supported
404 models, and about which instructions go where.
405 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
406 order as is used in the rest of the file.
407
9805e229
CD		 4082002-02-11 Chris Demetriou <cgd@broadcom.com>
409
410 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
411 indicating that ALU32_END or ALU64_END are there to check
412 for overflow.
413 (DADD): Likewise, but also remove previous comment about
414 overflow checking.
415
f701dad2
CD		 4162002-02-10 Chris Demetriou <cgd@broadcom.com>
417
418 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
419 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
420 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
421 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
422 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
423 fields (i.e., add and move commas) so that they more closely
424 match the MIPS ISA documentation opcode partitioning.
425
4262002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 427
428 * mips.igen (ADDI): Print immediate value.
429 (BREAK): Print code.
430 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
431 (SLL): Print "nop" specially, and don't run the code
432 that does the shift for the "nop" case.
433
9e52972e
FF		 4342001-11-17 Fred Fish <fnf@redhat.com>
435
436 * sim-main.h (float_operation): Move enum declaration outside
437 of _sim_cpu struct declaration.
438
c0efbca4
JB		 4392001-04-12 Jim Blandy <jimb@redhat.com>
440
441 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
442 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
443 set of the FCSR.
444 * sim-main.h (COCIDX): Remove definition; this isn't supported by
445 PENDING_FILL, and you can get the intended effect gracefully by
446 calling PENDING_SCHED directly.
447
fb891446
BE		 4482001-02-23 Ben Elliston <bje@redhat.com>
449
450 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
451 already defined elsewhere.
452
8030f857
BE		 4532001-02-19 Ben Elliston <bje@redhat.com>
454
455 * sim-main.h (sim_monitor): Return an int.
456 * interp.c (sim_monitor): Add return values.
457 (signal_exception): Handle error conditions from sim_monitor.
458
56b48a7a
CD		 4592001-02-08 Ben Elliston <bje@redhat.com>
460
461 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
462 (store_memory): Likewise, pass cia to sim_core_write*.
463
d3ee60d9
FCE		 4642000-10-19 Frank Ch. Eigler <fche@redhat.com>
465
466 On advice from Chris G. Demetriou <cgd@sibyte.com>:
467 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
468
071da002
AC		 469Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
470
471 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
472 * Makefile.in: Don't delete *.igen when cleaning directory.
473
a28c02cd
AC		 474Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
475
476 * m16.igen (break): Call SignalException not sim_engine_halt.
477
80ee11fa
AC		 478Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
479
480 From Jason Eckhardt:
481 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
482
673388c0
AC		 483Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
484
485 * mips.igen (MxC1, DMxC1): Fix printf formatting.
486
4c0deff4
NC		 4872000-05-24 Michael Hayes <mhayes@cygnus.com>
488
489 * mips.igen (do_dmultx): Fix typo.
490
eb2d80b4
AC		 491Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
492
493 * configure: Regenerated to track ../common/aclocal.m4 changes.
494
dd37a34b
AC		 495Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
496
497 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
498
4c0deff4
NC		 4992000-04-12 Frank Ch. Eigler <fche@redhat.com>
500
501 * sim-main.h (GPR_CLEAR): Define macro.
502
e30db738
AC		 503Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
504
505 * interp.c (decode_coproc): Output long using %lx and not %s.
506
cb7450ea
FCE		 5072000-03-21 Frank Ch. Eigler <fche@redhat.com>
508
509 * interp.c (sim_open): Sort & extend dummy memory regions for
510 --board=jmr3904 for eCos.
511
a3027dd7
FCE		 5122000-03-02 Frank Ch. Eigler <fche@redhat.com>
513
514 * configure: Regenerated.
515
516Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
517
518 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
519 calls, conditional on the simulator being in verbose mode.
520
dfcd3bfb
JM		 521Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
522
523 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
524 cache don't get ReservedInstruction traps.
525
c2d11a7d
JM		 5261999-11-29 Mark Salter <msalter@cygnus.com>
527
528 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
529 to clear status bits in sdisr register. This is how the hardware works.
530
531 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
532 being used by cygmon.
533
4ce44c66
JM		 5341999-11-11 Andrew Haley <aph@cygnus.com>
535
536 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
537 instructions.
538
cff3e48b
JM		 539Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
540
541 * mips.igen (MULT): Correct previous mis-applied patch.
542
d4f3574e
SS		 543Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
544
545 * mips.igen (delayslot32): Handle sequence like
546 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
547 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
548 (MULT): Actually pass the third register...
549
5501999-09-03 Mark Salter <msalter@cygnus.com>
551
552 * interp.c (sim_open): Added more memory aliases for additional
553 hardware being touched by cygmon on jmr3904 board.
554
555Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
556
557 * configure: Regenerated to track ../common/aclocal.m4 changes.
558
a0b3c4fd
JM		 559Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
560
561 * interp.c (sim_store_register): Handle case where client - GDB -
562 specifies that a 4 byte register is 8 bytes in size.
563 (sim_fetch_register): Ditto.
564
adf40b2e
JM		 5651999-07-14 Frank Ch. Eigler <fche@cygnus.com>
566
567 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
568 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
569 (idt_monitor_base): Base address for IDT monitor traps.
570 (pmon_monitor_base): Ditto for PMON.
571 (lsipmon_monitor_base): Ditto for LSI PMON.
572 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
573 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
574 (sim_firmware_command): New function.
575 (mips_option_handler): Call it for OPTION_FIRMWARE.
576 (sim_open): Allocate memory for idt_monitor region. If "--board"
577 option was given, add no monitor by default. Add BREAK hooks only if
578 monitors are also there.
579
43e526b9
JM		 580Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
581
582 * interp.c (sim_monitor): Flush output before reading input.
583
584Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
585
586 * tconfig.in (SIM_HANDLES_LMA): Always define.
587
588Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
589
590 From Mark Salter <msalter@cygnus.com>:
591 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
592 (sim_open): Add setup for BSP board.
593
9846de1b
JM		 594Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
595
596 * mips.igen (MULT, MULTU): Add syntax for two operand version.
597 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
598 them as unimplemented.
599
cd0fc7c3
SS		 6001999-05-08 Felix Lee <flee@cygnus.com>
601
602 * configure: Regenerated to track ../common/aclocal.m4 changes.
603
7a292a7a
SS		 6041999-04-21 Frank Ch. Eigler <fche@cygnus.com>
605
606 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
607
608Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
609
610 * configure.in: Any mips64vr5*-*-* target should have
611 -DTARGET_ENABLE_FR=1.
612 (default_endian): Any mips64vr*el-*-* target should default to
613 LITTLE_ENDIAN.
614 * configure: Re-generate.
615
6161999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
617
618 * mips.igen (ldl): Extend from _16_, not 32.
619
620Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
621
622 * interp.c (sim_store_register): Force registers written to by GDB
623 into an un-interpreted state.
624
c906108c
SS		 6251999-02-05 Frank Ch. Eigler <fche@cygnus.com>
626
627 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
628 CPU, start periodic background I/O polls.
629 (tx3904sio_poll): New function: periodic I/O poller.
630
6311998-12-30 Frank Ch. Eigler <fche@cygnus.com>
632
633 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
634
635Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
636
637 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
638 case statement.
639
6401998-12-29 Frank Ch. Eigler <fche@cygnus.com>
641
642 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
643 (load_word): Call SIM_CORE_SIGNAL hook on error.
644 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
645 starting. For exception dispatching, pass PC instead of NULL_CIA.
646 (decode_coproc): Use COP0_BADVADDR to store faulting address.
647 * sim-main.h (COP0_BADVADDR): Define.
648 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
649 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
650 (_sim_cpu): Add exc_* fields to store register value snapshots.
651 * mips.igen (*): Replace memory-related SignalException* calls
652 with references to SIM_CORE_SIGNAL hook.
653
654 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
655 fix.
656 * sim-main.c (*): Minor warning cleanups.
657
6581998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
659
660 * m16.igen (DADDIU5): Correct type-o.
661
662Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
663
664 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
665 variables.
666
667Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
668
669 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
670 to include path.
671 (interp.o): Add dependency on itable.h
672 (oengine.c, gencode): Delete remaining references.
673 (BUILT_SRC_FROM_GEN): Clean up.
674
6751998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
676
677 * vr4run.c: New.
678 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
679 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
680 tmp-run-hack) : New.
681 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
682 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
683 Drop the "64" qualifier to get the HACK generator working.
684 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
685 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
686 qualifier to get the hack generator working.
687 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
688 (DSLL): Use do_dsll.
689 (DSLLV): Use do_dsllv.
690 (DSRA): Use do_dsra.
691 (DSRL): Use do_dsrl.
692 (DSRLV): Use do_dsrlv.
693 (BC1): Move *vr4100 to get the HACK generator working.
694 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
695 get the HACK generator working.
696 (MACC) Rename to get the HACK generator working.
697 (DMACC,MACCS,DMACCS): Add the 64.
698
6991998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
700
701 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
702 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
703
7041998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
705
706 * mips/interp.c (DEBUG): Cleanups.
707
7081998-12-10 Frank Ch. Eigler <fche@cygnus.com>
709
710 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
711 (tx3904sio_tickle): fflush after a stdout character output.
712
7131998-12-03 Frank Ch. Eigler <fche@cygnus.com>
714
715 * interp.c (sim_close): Uninstall modules.
716
717Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
718
719 * sim-main.h, interp.c (sim_monitor): Change to global
720 function.
721
722Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
723
724 * configure.in (vr4100): Only include vr4100 instructions in
725 simulator.
726 * configure: Re-generate.
727 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
728
729Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
730
731 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
732 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
733 true alternative.
734
735 * configure.in (sim_default_gen, sim_use_gen): Replace with
736 sim_gen.
737 (--enable-sim-igen): Delete config option. Always using IGEN.
738 * configure: Re-generate.
739
740 * Makefile.in (gencode): Kill, kill, kill.
741 * gencode.c: Ditto.
742
743Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
744
745 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
746 bit mips16 igen simulator.
747 * configure: Re-generate.
748
749 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
750 as part of vr4100 ISA.
751 * vr.igen: Mark all instructions as 64 bit only.
752
753Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
754
755 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
756 Pacify GCC.
757
758Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
759
760 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
761 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
762 * configure: Re-generate.
763
764 * m16.igen (BREAK): Define breakpoint instruction.
765 (JALX32): Mark instruction as mips16 and not r3900.
766 * mips.igen (C.cond.fmt): Fix typo in instruction format.
767
768 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
769
770Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
771
772 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
773 insn as a debug breakpoint.
774
775 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
776 pending.slot_size.
777 (PENDING_SCHED): Clean up trace statement.
778 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
779 (PENDING_FILL): Delay write by only one cycle.
780 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
781
782 * sim-main.c (pending_tick): Clean up trace statements. Add trace
783 of pending writes.
784 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
785 32 & 64.
786 (pending_tick): Move incrementing of index to FOR statement.
787 (pending_tick): Only update PENDING_OUT after a write has occured.
788
789 * configure.in: Add explicit mips-lsi-* target. Use gencode to
790 build simulator.
791 * configure: Re-generate.
792
793 * interp.c (sim_engine_run OLD): Delete explicit call to
794 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
795
796Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
797
798 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
799 interrupt level number to match changed SignalExceptionInterrupt
800 macro.
801
802Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
803
804 * interp.c: #include "itable.h" if WITH_IGEN.
805 (get_insn_name): New function.
806 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
807 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
808
809Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
810
811 * configure: Rebuilt to inhale new common/aclocal.m4.
812
813Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
814
815 * dv-tx3904sio.c: Include sim-assert.h.
816
817Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
818
819 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
820 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
821 Reorganize target-specific sim-hardware checks.
822 * configure: rebuilt.
823 * interp.c (sim_open): For tx39 target boards, set
824 OPERATING_ENVIRONMENT, add tx3904sio devices.
825 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
826 ROM executables. Install dv-sockser into sim-modules list.
827
828 * dv-tx3904irc.c: Compiler warning clean-up.
829 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
830 frequent hw-trace messages.
831
832Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
833
834 * vr.igen (MulAcc): Identify as a vr4100 specific function.
835
836Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
837
838 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
839
840 * vr.igen: New file.
841 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
842 * mips.igen: Define vr4100 model. Include vr.igen.
843Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
844
845 * mips.igen (check_mf_hilo): Correct check.
846
847Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
848
849 * sim-main.h (interrupt_event): Add prototype.
850
851 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
852 register_ptr, register_value.
853 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
854
855 * sim-main.h (tracefh): Make extern.
856
857Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
858
859 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
860 Reduce unnecessarily high timer event frequency.
861 * dv-tx3904cpu.c: Ditto for interrupt event.
862
863Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
864
865 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
866 to allay warnings.
867 (interrupt_event): Made non-static.
868
869 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
870 interchange of configuration values for external vs. internal
871 clock dividers.
872
873Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
874
875 * mips.igen (BREAK): Moved code to here for
876 simulator-reserved break instructions.
877 * gencode.c (build_instruction): Ditto.
878 * interp.c (signal_exception): Code moved from here. Non-
879 reserved instructions now use exception vector, rather
880 than halting sim.
881 * sim-main.h: Moved magic constants to here.
882
883Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
884
885 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
886 register upon non-zero interrupt event level, clear upon zero
887 event value.
888 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
889 by passing zero event value.
890 (*_io_{read,write}_buffer): Endianness fixes.
891 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
892 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
893
894 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
895 serial I/O and timer module at base address 0xFFFF0000.
896
897Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
898
899 * mips.igen (SWC1) : Correct the handling of ReverseEndian
900 and BigEndianCPU.
901
902Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
903
904 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
905 parts.
906 * configure: Update.
907
908Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
909
910 * dv-tx3904tmr.c: New file - implements tx3904 timer.
911 * dv-tx3904{irc,cpu}.c: Mild reformatting.
912 * configure.in: Include tx3904tmr in hw_device list.
913 * configure: Rebuilt.
914 * interp.c (sim_open): Instantiate three timer instances.
915 Fix address typo of tx3904irc instance.
916
917Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
918
919 * interp.c (signal_exception): SystemCall exception now uses
920 the exception vector.
921
922Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
923
924 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
925 to allay warnings.
926
927Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
928
929 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
930
931Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
932
933 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
934
935 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
936 sim-main.h. Declare a struct hw_descriptor instead of struct
937 hw_device_descriptor.
938
939Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
940
941 * mips.igen (do_store_left, do_load_left): Compute nr of left and
942 right bits and then re-align left hand bytes to correct byte
943 lanes. Fix incorrect computation in do_store_left when loading
944 bytes from second word.
945
946Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
947
948 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
949 * interp.c (sim_open): Only create a device tree when HW is
950 enabled.
951
952 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
953 * interp.c (signal_exception): Ditto.
954
955Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
956
957 * gencode.c: Mark BEGEZALL as LIKELY.
958
959Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
960
961 * sim-main.h (ALU32_END): Sign extend 32 bit results.
962 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
963
964Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
965
966 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
967 modules. Recognize TX39 target with "mips*tx39" pattern.
968 * configure: Rebuilt.
969 * sim-main.h (*): Added many macros defining bits in
970 TX39 control registers.
971 (SignalInterrupt): Send actual PC instead of NULL.
972 (SignalNMIReset): New exception type.
973 * interp.c (board): New variable for future use to identify
974 a particular board being simulated.
975 (mips_option_handler,mips_options): Added "--board" option.
976 (interrupt_event): Send actual PC.
977 (sim_open): Make memory layout conditional on board setting.
978 (signal_exception): Initial implementation of hardware interrupt
979 handling. Accept another break instruction variant for simulator
980 exit.
981 (decode_coproc): Implement RFE instruction for TX39.
982 (mips.igen): Decode RFE instruction as such.
983 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
984 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
985 bbegin to implement memory map.
986 * dv-tx3904cpu.c: New file.
987 * dv-tx3904irc.c: New file.
988
989Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
990
991 * mips.igen (check_mt_hilo): Create a separate r3900 version.
992
993Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
994
995 * tx.igen (madd,maddu): Replace calls to check_op_hilo
996 with calls to check_div_hilo.
997
998Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
999
1000 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1001 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1002 Add special r3900 version of do_mult_hilo.
1003 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1004 with calls to check_mult_hilo.
1005 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1006 with calls to check_div_hilo.
1007
1008Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1009
1010 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1011 Document a replacement.
1012
1013Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1014
1015 * interp.c (sim_monitor): Make mon_printf work.
1016
1017Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1018
1019 * sim-main.h (INSN_NAME): New arg `cpu'.
1020
1021Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1022
1023 * configure: Regenerated to track ../common/aclocal.m4 changes.
1024
1025Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1026
1027 * configure: Regenerated to track ../common/aclocal.m4 changes.
1028 * config.in: Ditto.
1029
1030Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1031
1032 * acconfig.h: New file.
1033 * configure.in: Reverted change of Apr 24; use sinclude again.
1034
1035Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1036
1037 * configure: Regenerated to track ../common/aclocal.m4 changes.
1038 * config.in: Ditto.
1039
1040Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1041
1042 * configure.in: Don't call sinclude.
1043
1044Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1045
1046 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1047
1048Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049
1050 * mips.igen (ERET): Implement.
1051
1052 * interp.c (decode_coproc): Return sign-extended EPC.
1053
1054 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1055
1056 * interp.c (signal_exception): Do not ignore Trap.
1057 (signal_exception): On TRAP, restart at exception address.
1058 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1059 (signal_exception): Update.
1060 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1061 so that TRAP instructions are caught.
1062
1063Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1064
1065 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1066 contains HI/LO access history.
1067 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1068 (HIACCESS, LOACCESS): Delete, replace with
1069 (HIHISTORY, LOHISTORY): New macros.
1070 (CHECKHILO): Delete all, moved to mips.igen
1071
1072 * gencode.c (build_instruction): Do not generate checks for
1073 correct HI/LO register usage.
1074
1075 * interp.c (old_engine_run): Delete checks for correct HI/LO
1076 register usage.
1077
1078 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1079 check_mf_cycles): New functions.
1080 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1081 do_divu, domultx, do_mult, do_multu): Use.
1082
1083 * tx.igen ("madd", "maddu"): Use.
1084
1085Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1086
1087 * mips.igen (DSRAV): Use function do_dsrav.
1088 (SRAV): Use new function do_srav.
1089
1090 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1091 (B): Sign extend 11 bit immediate.
1092 (EXT-B*): Shift 16 bit immediate left by 1.
1093 (ADDIU*): Don't sign extend immediate value.
1094
1095Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1096
1097 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1098
1099 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1100 functions.
1101
1102 * mips.igen (delayslot32, nullify_next_insn): New functions.
1103 (m16.igen): Always include.
1104 (do_*): Add more tracing.
1105
1106 * m16.igen (delayslot16): Add NIA argument, could be called by a
1107 32 bit MIPS16 instruction.
1108
1109 * interp.c (ifetch16): Move function from here.
1110 * sim-main.c (ifetch16): To here.
1111
1112 * sim-main.c (ifetch16, ifetch32): Update to match current
1113 implementations of LH, LW.
1114 (signal_exception): Don't print out incorrect hex value of illegal
1115 instruction.
1116
1117Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1118
1119 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1120 instruction.
1121
1122 * m16.igen: Implement MIPS16 instructions.
1123
1124 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1125 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1126 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1127 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1128 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1129 bodies of corresponding code from 32 bit insn to these. Also used
1130 by MIPS16 versions of functions.
1131
1132 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1133 (IMEM16): Drop NR argument from macro.
1134
1135Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136
1137 * Makefile.in (SIM_OBJS): Add sim-main.o.
1138
1139 * sim-main.h (address_translation, load_memory, store_memory,
1140 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1141 as INLINE_SIM_MAIN.
1142 (pr_addr, pr_uword64): Declare.
1143 (sim-main.c): Include when H_REVEALS_MODULE_P.
1144
1145 * interp.c (address_translation, load_memory, store_memory,
1146 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1147 from here.
1148 * sim-main.c: To here. Fix compilation problems.
1149
1150 * configure.in: Enable inlining.
1151 * configure: Re-config.
1152
1153Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1154
1155 * configure: Regenerated to track ../common/aclocal.m4 changes.
1156
1157Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1158
1159 * mips.igen: Include tx.igen.
1160 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1161 * tx.igen: New file, contains MADD and MADDU.
1162
1163 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1164 the hardwired constant `7'.
1165 (store_memory): Ditto.
1166 (LOADDRMASK): Move definition to sim-main.h.
1167
1168 mips.igen (MTC0): Enable for r3900.
1169 (ADDU): Add trace.
1170
1171 mips.igen (do_load_byte): Delete.
1172 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1173 do_store_right): New functions.
1174 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1175
1176 configure.in: Let the tx39 use igen again.
1177 configure: Update.
1178
1179Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1180
1181 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1182 not an address sized quantity. Return zero for cache sizes.
1183
1184Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * mips.igen (r3900): r3900 does not support 64 bit integer
1187 operations.
1188
1189Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1190
1191 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1192 than igen one.
1193 * configure : Rebuild.
1194
1195Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1196
1197 * configure: Regenerated to track ../common/aclocal.m4 changes.
1198
1199Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1200
1201 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1202
1203Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1204
1205 * configure: Regenerated to track ../common/aclocal.m4 changes.
1206 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1207
1208Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1209
1210 * configure: Regenerated to track ../common/aclocal.m4 changes.
1211
1212Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 * interp.c (Max, Min): Comment out functions. Not yet used.
1215
1216Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * configure: Regenerated to track ../common/aclocal.m4 changes.
1219
1220Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1221
1222 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1223 configurable settings for stand-alone simulator.
1224
1225 * configure.in: Added X11 search, just in case.
1226
1227 * configure: Regenerated.
1228
1229Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1230
1231 * interp.c (sim_write, sim_read, load_memory, store_memory):
1232 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1233
1234Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1235
1236 * sim-main.h (GETFCC): Return an unsigned value.
1237
1238Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1241 (DADD): Result destination is RD not RT.
1242
1243Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1244
1245 * sim-main.h (HIACCESS, LOACCESS): Always define.
1246
1247 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1248
1249 * interp.c (sim_info): Delete.
1250
1251Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1252
1253 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1254 (mips_option_handler): New argument `cpu'.
1255 (sim_open): Update call to sim_add_option_table.
1256
1257Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * mips.igen (CxC1): Add tracing.
1260
1261Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1262
1263 * sim-main.h (Max, Min): Declare.
1264
1265 * interp.c (Max, Min): New functions.
1266
1267 * mips.igen (BC1): Add tracing.
1268
1269Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1270
1271 * interp.c Added memory map for stack in vr4100
1272
1273Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1274
1275 * interp.c (load_memory): Add missing "break"'s.
1276
1277Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1278
1279 * interp.c (sim_store_register, sim_fetch_register): Pass in
1280 length parameter. Return -1.
1281
1282Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1283
1284 * interp.c: Added hardware init hook, fixed warnings.
1285
1286Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1287
1288 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1289
1290Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1291
1292 * interp.c (ifetch16): New function.
1293
1294 * sim-main.h (IMEM32): Rename IMEM.
1295 (IMEM16_IMMED): Define.
1296 (IMEM16): Define.
1297 (DELAY_SLOT): Update.
1298
1299 * m16run.c (sim_engine_run): New file.
1300
1301 * m16.igen: All instructions except LB.
1302 (LB): Call do_load_byte.
1303 * mips.igen (do_load_byte): New function.
1304 (LB): Call do_load_byte.
1305
1306 * mips.igen: Move spec for insn bit size and high bit from here.
1307 * Makefile.in (tmp-igen, tmp-m16): To here.
1308
1309 * m16.dc: New file, decode mips16 instructions.
1310
1311 * Makefile.in (SIM_NO_ALL): Define.
1312 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1313
1314Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1315
1316 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1317 point unit to 32 bit registers.
1318 * configure: Re-generate.
1319
1320Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1321
1322 * configure.in (sim_use_gen): Make IGEN the default simulator
1323 generator for generic 32 and 64 bit mips targets.
1324 * configure: Re-generate.
1325
1326Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1329 bitsize.
1330
1331 * interp.c (sim_fetch_register, sim_store_register): Read/write
1332 FGR from correct location.
1333 (sim_open): Set size of FGR's according to
1334 WITH_TARGET_FLOATING_POINT_BITSIZE.
1335
1336 * sim-main.h (FGR): Store floating point registers in a separate
1337 array.
1338
1339Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1340
1341 * configure: Regenerated to track ../common/aclocal.m4 changes.
1342
1343Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344
1345 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1346
1347 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1348
1349 * interp.c (pending_tick): New function. Deliver pending writes.
1350
1351 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1352 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1353 it can handle mixed sized quantites and single bits.
1354
1355Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * interp.c (oengine.h): Do not include when building with IGEN.
1358 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1359 (sim_info): Ditto for PROCESSOR_64BIT.
1360 (sim_monitor): Replace ut_reg with unsigned_word.
1361 (*): Ditto for t_reg.
1362 (LOADDRMASK): Define.
1363 (sim_open): Remove defunct check that host FP is IEEE compliant,
1364 using software to emulate floating point.
1365 (value_fpr, ...): Always compile, was conditional on HASFPU.
1366
1367Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1368
1369 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1370 size.
1371
1372 * interp.c (SD, CPU): Define.
1373 (mips_option_handler): Set flags in each CPU.
1374 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1375 (sim_close): Do not clear STATE, deleted anyway.
1376 (sim_write, sim_read): Assume CPU zero's vm should be used for
1377 data transfers.
1378 (sim_create_inferior): Set the PC for all processors.
1379 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1380 argument.
1381 (mips16_entry): Pass correct nr of args to store_word, load_word.
1382 (ColdReset): Cold reset all cpu's.
1383 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1384 (sim_monitor, load_memory, store_memory, signal_exception): Use
1385 `CPU' instead of STATE_CPU.
1386
1387
1388 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1389 SD or CPU_.
1390
1391 * sim-main.h (signal_exception): Add sim_cpu arg.
1392 (SignalException*): Pass both SD and CPU to signal_exception.
1393 * interp.c (signal_exception): Update.
1394
1395 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1396 Ditto
1397 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1398 address_translation): Ditto
1399 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1400
1401Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * configure: Regenerated to track ../common/aclocal.m4 changes.
1404
1405Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406
1407 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1408
1409 * mips.igen (model): Map processor names onto BFD name.
1410
1411 * sim-main.h (CPU_CIA): Delete.
1412 (SET_CIA, GET_CIA): Define
1413
1414Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1417 regiser.
1418
1419 * configure.in (default_endian): Configure a big-endian simulator
1420 by default.
1421 * configure: Re-generate.
1422
1423Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1424
1425 * configure: Regenerated to track ../common/aclocal.m4 changes.
1426
1427Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1428
1429 * interp.c (sim_monitor): Handle Densan monitor outbyte
1430 and inbyte functions.
1431
14321997-12-29 Felix Lee <flee@cygnus.com>
1433
1434 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1435
1436Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1437
1438 * Makefile.in (tmp-igen): Arrange for $zero to always be
1439 reset to zero after every instruction.
1440
1441Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1442
1443 * configure: Regenerated to track ../common/aclocal.m4 changes.
1444 * config.in: Ditto.
1445
1446Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1447
1448 * mips.igen (MSUB): Fix to work like MADD.
1449 * gencode.c (MSUB): Similarly.
1450
1451Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1452
1453 * configure: Regenerated to track ../common/aclocal.m4 changes.
1454
1455Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1456
1457 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1458
1459Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 * sim-main.h (sim-fpu.h): Include.
1462
1463 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1464 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1465 using host independant sim_fpu module.
1466
1467Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1468
1469 * interp.c (signal_exception): Report internal errors with SIGABRT
1470 not SIGQUIT.
1471
1472 * sim-main.h (C0_CONFIG): New register.
1473 (signal.h): No longer include.
1474
1475 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1476
1477Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1478
1479 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1480
1481Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1482
1483 * mips.igen: Tag vr5000 instructions.
1484 (ANDI): Was missing mipsIV model, fix assembler syntax.
1485 (do_c_cond_fmt): New function.
1486 (C.cond.fmt): Handle mips I-III which do not support CC field
1487 separatly.
1488 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1489 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1490 in IV3.2 spec.
1491 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1492 vr5000 which saves LO in a GPR separatly.
1493
1494 * configure.in (enable-sim-igen): For vr5000, select vr5000
1495 specific instructions.
1496 * configure: Re-generate.
1497
1498Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1501
1502 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1503 fmt_uninterpreted_64 bit cases to switch. Convert to
1504 fmt_formatted,
1505
1506 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1507
1508 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1509 as specified in IV3.2 spec.
1510 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1511
1512Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1513
1514 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1515 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1516 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1517 PENDING_FILL versions of instructions. Simplify.
1518 (X): New function.
1519 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1520 instructions.
1521 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1522 a signed value.
1523 (MTHI, MFHI): Disable code checking HI-LO.
1524
1525 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1526 global.
1527 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1528
1529Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * gencode.c (build_mips16_operands): Replace IPC with cia.
1532
1533 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1534 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1535 IPC to `cia'.
1536 (UndefinedResult): Replace function with macro/function
1537 combination.
1538 (sim_engine_run): Don't save PC in IPC.
1539
1540 * sim-main.h (IPC): Delete.
1541
1542
1543 * interp.c (signal_exception, store_word, load_word,
1544 address_translation, load_memory, store_memory, cache_op,
1545 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1546 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1547 current instruction address - cia - argument.
1548 (sim_read, sim_write): Call address_translation directly.
1549 (sim_engine_run): Rename variable vaddr to cia.
1550 (signal_exception): Pass cia to sim_monitor
1551
1552 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1553 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1554 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1555
1556 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1557 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1558 SIM_ASSERT.
1559
1560 * interp.c (signal_exception): Pass restart address to
1561 sim_engine_restart.
1562
1563 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1564 idecode.o): Add dependency.
1565
1566 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1567 Delete definitions
1568 (DELAY_SLOT): Update NIA not PC with branch address.
1569 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1570
1571 * mips.igen: Use CIA not PC in branch calculations.
1572 (illegal): Call SignalException.
1573 (BEQ, ADDIU): Fix assembler.
1574
1575Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * m16.igen (JALX): Was missing.
1578
1579 * configure.in (enable-sim-igen): New configuration option.
1580 * configure: Re-generate.
1581
1582 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1583
1584 * interp.c (load_memory, store_memory): Delete parameter RAW.
1585 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1586 bypassing {load,store}_memory.
1587
1588 * sim-main.h (ByteSwapMem): Delete definition.
1589
1590 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1591
1592 * interp.c (sim_do_command, sim_commands): Delete mips specific
1593 commands. Handled by module sim-options.
1594
1595 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1596 (WITH_MODULO_MEMORY): Define.
1597
1598 * interp.c (sim_info): Delete code printing memory size.
1599
1600 * interp.c (mips_size): Nee sim_size, delete function.
1601 (power2): Delete.
1602 (monitor, monitor_base, monitor_size): Delete global variables.
1603 (sim_open, sim_close): Delete code creating monitor and other
1604 memory regions. Use sim-memopts module, via sim_do_commandf, to
1605 manage memory regions.
1606 (load_memory, store_memory): Use sim-core for memory model.
1607
1608 * interp.c (address_translation): Delete all memory map code
1609 except line forcing 32 bit addresses.
1610
1611Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1612
1613 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1614 trace options.
1615
1616 * interp.c (logfh, logfile): Delete globals.
1617 (sim_open, sim_close): Delete code opening & closing log file.
1618 (mips_option_handler): Delete -l and -n options.
1619 (OPTION mips_options): Ditto.
1620
1621 * interp.c (OPTION mips_options): Rename option trace to dinero.
1622 (mips_option_handler): Update.
1623
1624Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1625
1626 * interp.c (fetch_str): New function.
1627 (sim_monitor): Rewrite using sim_read & sim_write.
1628 (sim_open): Check magic number.
1629 (sim_open): Write monitor vectors into memory using sim_write.
1630 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1631 (sim_read, sim_write): Simplify - transfer data one byte at a
1632 time.
1633 (load_memory, store_memory): Clarify meaning of parameter RAW.
1634
1635 * sim-main.h (isHOST): Defete definition.
1636 (isTARGET): Mark as depreciated.
1637 (address_translation): Delete parameter HOST.
1638
1639 * interp.c (address_translation): Delete parameter HOST.
1640
1641Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1642
1643 * mips.igen:
1644
1645 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1646 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1647
1648Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1649
1650 * mips.igen: Add model filter field to records.
1651
1652Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1653
1654 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1655
1656 interp.c (sim_engine_run): Do not compile function sim_engine_run
1657 when WITH_IGEN == 1.
1658
1659 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1660 target architecture.
1661
1662 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1663 igen. Replace with configuration variables sim_igen_flags /
1664 sim_m16_flags.
1665
1666 * m16.igen: New file. Copy mips16 insns here.
1667 * mips.igen: From here.
1668
1669Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1670
1671 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1672 to top.
1673 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1674
1675Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1676
1677 * gencode.c (build_instruction): Follow sim_write's lead in using
1678 BigEndianMem instead of !ByteSwapMem.
1679
1680Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1681
1682 * configure.in (sim_gen): Dependent on target, select type of
1683 generator. Always select old style generator.
1684
1685 configure: Re-generate.
1686
1687 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1688 targets.
1689 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1690 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1691 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1692 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1693 SIM_@sim_gen@_*, set by autoconf.
1694
1695Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1696
1697 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1698
1699 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1700 CURRENT_FLOATING_POINT instead.
1701
1702 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1703 (address_translation): Raise exception InstructionFetch when
1704 translation fails and isINSTRUCTION.
1705
1706 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1707 sim_engine_run): Change type of of vaddr and paddr to
1708 address_word.
1709 (address_translation, prefetch, load_memory, store_memory,
1710 cache_op): Change type of vAddr and pAddr to address_word.
1711
1712 * gencode.c (build_instruction): Change type of vaddr and paddr to
1713 address_word.
1714
1715Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1716
1717 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1718 macro to obtain result of ALU op.
1719
1720Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1721
1722 * interp.c (sim_info): Call profile_print.
1723
1724Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1725
1726 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1727
1728 * sim-main.h (WITH_PROFILE): Do not define, defined in
1729 common/sim-config.h. Use sim-profile module.
1730 (simPROFILE): Delete defintion.
1731
1732 * interp.c (PROFILE): Delete definition.
1733 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1734 (sim_close): Delete code writing profile histogram.
1735 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1736 Delete.
1737 (sim_engine_run): Delete code profiling the PC.
1738
1739Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1740
1741 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1742
1743 * interp.c (sim_monitor): Make register pointers of type
1744 unsigned_word*.
1745
1746 * sim-main.h: Make registers of type unsigned_word not
1747 signed_word.
1748
1749Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1750
1751 * interp.c (sync_operation): Rename from SyncOperation, make
1752 global, add SD argument.
1753 (prefetch): Rename from Prefetch, make global, add SD argument.
1754 (decode_coproc): Make global.
1755
1756 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1757
1758 * gencode.c (build_instruction): Generate DecodeCoproc not
1759 decode_coproc calls.
1760
1761 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1762 (SizeFGR): Move to sim-main.h
1763 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1764 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1765 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1766 sim-main.h.
1767 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1768 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1769 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1770 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1771 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1772 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1773
1774 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1775 exception.
1776 (sim-alu.h): Include.
1777 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1778 (sim_cia): Typedef to instruction_address.
1779
1780Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * Makefile.in (interp.o): Rename generated file engine.c to
1783 oengine.c.
1784
1785 * interp.c: Update.
1786
1787Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1788
1789 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1790
1791Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1792
1793 * gencode.c (build_instruction): For "FPSQRT", output correct
1794 number of arguments to Recip.
1795
1796Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797
1798 * Makefile.in (interp.o): Depends on sim-main.h
1799
1800 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1801
1802 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1803 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1804 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1805 STATE, DSSTATE): Define
1806 (GPR, FGRIDX, ..): Define.
1807
1808 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1809 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1810 (GPR, FGRIDX, ...): Delete macros.
1811
1812 * interp.c: Update names to match defines from sim-main.h
1813
1814Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1815
1816 * interp.c (sim_monitor): Add SD argument.
1817 (sim_warning): Delete. Replace calls with calls to
1818 sim_io_eprintf.
1819 (sim_error): Delete. Replace calls with sim_io_error.
1820 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1821 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1822 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1823 argument.
1824 (mips_size): Rename from sim_size. Add SD argument.
1825
1826 * interp.c (simulator): Delete global variable.
1827 (callback): Delete global variable.
1828 (mips_option_handler, sim_open, sim_write, sim_read,
1829 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1830 sim_size,sim_monitor): Use sim_io_* not callback->*.
1831 (sim_open): ZALLOC simulator struct.
1832 (PROFILE): Do not define.
1833
1834Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1835
1836 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1837 support.h with corresponding code.
1838
1839 * sim-main.h (word64, uword64), support.h: Move definition to
1840 sim-main.h.
1841 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1842
1843 * support.h: Delete
1844 * Makefile.in: Update dependencies
1845 * interp.c: Do not include.
1846
1847Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * interp.c (address_translation, load_memory, store_memory,
1850 cache_op): Rename to from AddressTranslation et.al., make global,
1851 add SD argument
1852
1853 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1854 CacheOp): Define.
1855
1856 * interp.c (SignalException): Rename to signal_exception, make
1857 global.
1858
1859 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1860
1861 * sim-main.h (SignalException, SignalExceptionInterrupt,
1862 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1863 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1864 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1865 Define.
1866
1867 * interp.c, support.h: Use.
1868
1869Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1872 to value_fpr / store_fpr. Add SD argument.
1873 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1874 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1875
1876 * sim-main.h (ValueFPR, StoreFPR): Define.
1877
1878Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * interp.c (sim_engine_run): Check consistency between configure
1881 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1882 and HASFPU.
1883
1884 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1885 (mips_fpu): Configure WITH_FLOATING_POINT.
1886 (mips_endian): Configure WITH_TARGET_ENDIAN.
1887 * configure: Update.
1888
1889Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * configure: Regenerated to track ../common/aclocal.m4 changes.
1892
1893Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1894
1895 * configure: Regenerated.
1896
1897Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1898
1899 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1900
1901Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1902
1903 * gencode.c (print_igen_insn_models): Assume certain architectures
1904 include all mips* instructions.
1905 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1906 instruction.
1907
1908 * Makefile.in (tmp.igen): Add target. Generate igen input from
1909 gencode file.
1910
1911 * gencode.c (FEATURE_IGEN): Define.
1912 (main): Add --igen option. Generate output in igen format.
1913 (process_instructions): Format output according to igen option.
1914 (print_igen_insn_format): New function.
1915 (print_igen_insn_models): New function.
1916 (process_instructions): Only issue warnings and ignore
1917 instructions when no FEATURE_IGEN.
1918
1919Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1920
1921 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1922 MIPS targets.
1923
1924Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1925
1926 * configure: Regenerated to track ../common/aclocal.m4 changes.
1927
1928Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1929
1930 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1931 SIM_RESERVED_BITS): Delete, moved to common.
1932 (SIM_EXTRA_CFLAGS): Update.
1933
1934Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * configure.in: Configure non-strict memory alignment.
1937 * configure: Regenerated to track ../common/aclocal.m4 changes.
1938
1939Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1940
1941 * configure: Regenerated to track ../common/aclocal.m4 changes.
1942
1943Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1944
1945 * gencode.c (SDBBP,DERET): Added (3900) insns.
1946 (RFE): Turn on for 3900.
1947 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1948 (dsstate): Made global.
1949 (SUBTARGET_R3900): Added.
1950 (CANCELDELAYSLOT): New.
1951 (SignalException): Ignore SystemCall rather than ignore and
1952 terminate. Add DebugBreakPoint handling.
1953 (decode_coproc): New insns RFE, DERET; and new registers Debug
1954 and DEPC protected by SUBTARGET_R3900.
1955 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1956 bits explicitly.
1957 * Makefile.in,configure.in: Add mips subtarget option.
1958 * configure: Update.
1959
1960Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1961
1962 * gencode.c: Add r3900 (tx39).
1963
1964
1965Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1966
1967 * gencode.c (build_instruction): Don't need to subtract 4 for
1968 JALR, just 2.
1969
1970Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1971
1972 * interp.c: Correct some HASFPU problems.
1973
1974Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1975
1976 * configure: Regenerated to track ../common/aclocal.m4 changes.
1977
1978Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * interp.c (mips_options): Fix samples option short form, should
1981 be `x'.
1982
1983Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984
1985 * interp.c (sim_info): Enable info code. Was just returning.
1986
1987Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1990 MFC0.
1991
1992Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1993
1994 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1995 constants.
1996 (build_instruction): Ditto for LL.
1997
1998Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1999
2000 * configure: Regenerated to track ../common/aclocal.m4 changes.
2001
2002Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * configure: Regenerated to track ../common/aclocal.m4 changes.
2005 * config.in: Ditto.
2006
2007Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2008
2009 * interp.c (sim_open): Add call to sim_analyze_program, update
2010 call to sim_config.
2011
2012Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * interp.c (sim_kill): Delete.
2015 (sim_create_inferior): Add ABFD argument. Set PC from same.
2016 (sim_load): Move code initializing trap handlers from here.
2017 (sim_open): To here.
2018 (sim_load): Delete, use sim-hload.c.
2019
2020 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2021
2022Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * configure: Regenerated to track ../common/aclocal.m4 changes.
2025 * config.in: Ditto.
2026
2027Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * interp.c (sim_open): Add ABFD argument.
2030 (sim_load): Move call to sim_config from here.
2031 (sim_open): To here. Check return status.
2032
2033Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2034
2035 * gencode.c (build_instruction): Two arg MADD should
2036 not assign result to $0.
2037
2038Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2039
2040 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2041 * sim/mips/configure.in: Regenerate.
2042
2043Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2044
2045 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2046 signed8, unsigned8 et.al. types.
2047
2048 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2049 hosts when selecting subreg.
2050
2051Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2052
2053 * interp.c (sim_engine_run): Reset the ZERO register to zero
2054 regardless of FEATURE_WARN_ZERO.
2055 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2056
2057Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2058
2059 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2060 (SignalException): For BreakPoints ignore any mode bits and just
2061 save the PC.
2062 (SignalException): Always set the CAUSE register.
2063
2064Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2067 exception has been taken.
2068
2069 * interp.c: Implement the ERET and mt/f sr instructions.
2070
2071Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * interp.c (SignalException): Don't bother restarting an
2074 interrupt.
2075
2076Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * interp.c (SignalException): Really take an interrupt.
2079 (interrupt_event): Only deliver interrupts when enabled.
2080
2081Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * interp.c (sim_info): Only print info when verbose.
2084 (sim_info) Use sim_io_printf for output.
2085
2086Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2089 mips architectures.
2090
2091Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * interp.c (sim_do_command): Check for common commands if a
2094 simulator specific command fails.
2095
2096Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2097
2098 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2099 and simBE when DEBUG is defined.
2100
2101Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2102
2103 * interp.c (interrupt_event): New function. Pass exception event
2104 onto exception handler.
2105
2106 * configure.in: Check for stdlib.h.
2107 * configure: Regenerate.
2108
2109 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2110 variable declaration.
2111 (build_instruction): Initialize memval1.
2112 (build_instruction): Add UNUSED attribute to byte, bigend,
2113 reverse.
2114 (build_operands): Ditto.
2115
2116 * interp.c: Fix GCC warnings.
2117 (sim_get_quit_code): Delete.
2118
2119 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2120 * Makefile.in: Ditto.
2121 * configure: Re-generate.
2122
2123 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2124
2125Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2126
2127 * interp.c (mips_option_handler): New function parse argumes using
2128 sim-options.
2129 (myname): Replace with STATE_MY_NAME.
2130 (sim_open): Delete check for host endianness - performed by
2131 sim_config.
2132 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2133 (sim_open): Move much of the initialization from here.
2134 (sim_load): To here. After the image has been loaded and
2135 endianness set.
2136 (sim_open): Move ColdReset from here.
2137 (sim_create_inferior): To here.
2138 (sim_open): Make FP check less dependant on host endianness.
2139
2140 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2141 run.
2142 * interp.c (sim_set_callbacks): Delete.
2143
2144 * interp.c (membank, membank_base, membank_size): Replace with
2145 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2146 (sim_open): Remove call to callback->init. gdb/run do this.
2147
2148 * interp.c: Update
2149
2150 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2151
2152 * interp.c (big_endian_p): Delete, replaced by
2153 current_target_byte_order.
2154
2155Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2156
2157 * interp.c (host_read_long, host_read_word, host_swap_word,
2158 host_swap_long): Delete. Using common sim-endian.
2159 (sim_fetch_register, sim_store_register): Use H2T.
2160 (pipeline_ticks): Delete. Handled by sim-events.
2161 (sim_info): Update.
2162 (sim_engine_run): Update.
2163
2164Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165
2166 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2167 reason from here.
2168 (SignalException): To here. Signal using sim_engine_halt.
2169 (sim_stop_reason): Delete, moved to common.
2170
2171Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2172
2173 * interp.c (sim_open): Add callback argument.
2174 (sim_set_callbacks): Delete SIM_DESC argument.
2175 (sim_size): Ditto.
2176
2177Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * Makefile.in (SIM_OBJS): Add common modules.
2180
2181 * interp.c (sim_set_callbacks): Also set SD callback.
2182 (set_endianness, xfer_*, swap_*): Delete.
2183 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2184 Change to functions using sim-endian macros.
2185 (control_c, sim_stop): Delete, use common version.
2186 (simulate): Convert into.
2187 (sim_engine_run): This function.
2188 (sim_resume): Delete.
2189
2190 * interp.c (simulation): New variable - the simulator object.
2191 (sim_kind): Delete global - merged into simulation.
2192 (sim_load): Cleanup. Move PC assignment from here.
2193 (sim_create_inferior): To here.
2194
2195 * sim-main.h: New file.
2196 * interp.c (sim-main.h): Include.
2197
2198Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2199
2200 * configure: Regenerated to track ../common/aclocal.m4 changes.
2201
2202Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2203
2204 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2205
2206Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2207
2208 * gencode.c (build_instruction): DIV instructions: check
2209 for division by zero and integer overflow before using
2210 host's division operation.
2211
2212Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2213
2214 * Makefile.in (SIM_OBJS): Add sim-load.o.
2215 * interp.c: #include bfd.h.
2216 (target_byte_order): Delete.
2217 (sim_kind, myname, big_endian_p): New static locals.
2218 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2219 after argument parsing. Recognize -E arg, set endianness accordingly.
2220 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2221 load file into simulator. Set PC from bfd.
2222 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2223 (set_endianness): Use big_endian_p instead of target_byte_order.
2224
2225Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2226
2227 * interp.c (sim_size): Delete prototype - conflicts with
2228 definition in remote-sim.h. Correct definition.
2229
2230Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2231
2232 * configure: Regenerated to track ../common/aclocal.m4 changes.
2233 * config.in: Ditto.
2234
2235Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2236
2237 * interp.c (sim_open): New arg `kind'.
2238
2239 * configure: Regenerated to track ../common/aclocal.m4 changes.
2240
2241Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2242
2243 * configure: Regenerated to track ../common/aclocal.m4 changes.
2244
2245Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2246
2247 * interp.c (sim_open): Set optind to 0 before calling getopt.
2248
2249Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2250
2251 * configure: Regenerated to track ../common/aclocal.m4 changes.
2252
2253Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2254
2255 * interp.c : Replace uses of pr_addr with pr_uword64
2256 where the bit length is always 64 independent of SIM_ADDR.
2257 (pr_uword64) : added.
2258
2259Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2260
2261 * configure: Re-generate.
2262
2263Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2264
2265 * configure: Regenerate to track ../common/aclocal.m4 changes.
2266
2267Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2268
2269 * interp.c (sim_open): New SIM_DESC result. Argument is now
2270 in argv form.
2271 (other sim_*): New SIM_DESC argument.
2272
2273Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2274
2275 * interp.c: Fix printing of addresses for non-64-bit targets.
2276 (pr_addr): Add function to print address based on size.
2277
2278Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2279
2280 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2281
2282Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2283
2284 * gencode.c (build_mips16_operands): Correct computation of base
2285 address for extended PC relative instruction.
2286
2287Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2288
2289 * interp.c (mips16_entry): Add support for floating point cases.
2290 (SignalException): Pass floating point cases to mips16_entry.
2291 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2292 registers.
2293 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2294 or fmt_word.
2295 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2296 and then set the state to fmt_uninterpreted.
2297 (COP_SW): Temporarily set the state to fmt_word while calling
2298 ValueFPR.
2299
2300Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2301
2302 * gencode.c (build_instruction): The high order may be set in the
2303 comparison flags at any ISA level, not just ISA 4.
2304
2305Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2306
2307 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2308 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2309 * configure.in: sinclude ../common/aclocal.m4.
2310 * configure: Regenerated.
2311
2312Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2313
2314 * configure: Rebuild after change to aclocal.m4.
2315
2316Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2317
2318 * configure configure.in Makefile.in: Update to new configure
2319 scheme which is more compatible with WinGDB builds.
2320 * configure.in: Improve comment on how to run autoconf.
2321 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2322 * Makefile.in: Use autoconf substitution to install common
2323 makefile fragment.
2324
2325Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2326
2327 * gencode.c (build_instruction): Use BigEndianCPU instead of
2328 ByteSwapMem.
2329
2330Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2331
2332 * interp.c (sim_monitor): Make output to stdout visible in
2333 wingdb's I/O log window.
2334
2335Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2336
2337 * support.h: Undo previous change to SIGTRAP
2338 and SIGQUIT values.
2339
2340Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2341
2342 * interp.c (store_word, load_word): New static functions.
2343 (mips16_entry): New static function.
2344 (SignalException): Look for mips16 entry and exit instructions.
2345 (simulate): Use the correct index when setting fpr_state after
2346 doing a pending move.
2347
2348Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2349
2350 * interp.c: Fix byte-swapping code throughout to work on
2351 both little- and big-endian hosts.
2352
2353Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2354
2355 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2356 with gdb/config/i386/xm-windows.h.
2357
2358Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2359
2360 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2361 that messes up arithmetic shifts.
2362
2363Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2364
2365 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2366 SIGTRAP and SIGQUIT for _WIN32.
2367
2368Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2369
2370 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2371 force a 64 bit multiplication.
2372 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2373 destination register is 0, since that is the default mips16 nop
2374 instruction.
2375
2376Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2377
2378 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2379 (build_endian_shift): Don't check proc64.
2380 (build_instruction): Always set memval to uword64. Cast op2 to
2381 uword64 when shifting it left in memory instructions. Always use
2382 the same code for stores--don't special case proc64.
2383
2384 * gencode.c (build_mips16_operands): Fix base PC value for PC
2385 relative operands.
2386 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2387 jal instruction.
2388 * interp.c (simJALDELAYSLOT): Define.
2389 (JALDELAYSLOT): Define.
2390 (INDELAYSLOT, INJALDELAYSLOT): Define.
2391 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2392
2393Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2394
2395 * interp.c (sim_open): add flush_cache as a PMON routine
2396 (sim_monitor): handle flush_cache by ignoring it
2397
2398Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2399
2400 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2401 BigEndianMem.
2402 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2403 (BigEndianMem): Rename to ByteSwapMem and change sense.
2404 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2405 BigEndianMem references to !ByteSwapMem.
2406 (set_endianness): New function, with prototype.
2407 (sim_open): Call set_endianness.
2408 (sim_info): Use simBE instead of BigEndianMem.
2409 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2410 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2411 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2412 ifdefs, keeping the prototype declaration.
2413 (swap_word): Rewrite correctly.
2414 (ColdReset): Delete references to CONFIG. Delete endianness related
2415 code; moved to set_endianness.
2416
2417Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2418
2419 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2420 * interp.c (CHECKHILO): Define away.
2421 (simSIGINT): New macro.
2422 (membank_size): Increase from 1MB to 2MB.
2423 (control_c): New function.
2424 (sim_resume): Rename parameter signal to signal_number. Add local
2425 variable prev. Call signal before and after simulate.
2426 (sim_stop_reason): Add simSIGINT support.
2427 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2428 functions always.
2429 (sim_warning): Delete call to SignalException. Do call printf_filtered
2430 if logfh is NULL.
2431 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2432 a call to sim_warning.
2433
2434Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2435
2436 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2437 16 bit instructions.
2438
2439Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2440
2441 Add support for mips16 (16 bit MIPS implementation):
2442 * gencode.c (inst_type): Add mips16 instruction encoding types.
2443 (GETDATASIZEINSN): Define.
2444 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2445 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2446 mtlo.
2447 (MIPS16_DECODE): New table, for mips16 instructions.
2448 (bitmap_val): New static function.
2449 (struct mips16_op): Define.
2450 (mips16_op_table): New table, for mips16 operands.
2451 (build_mips16_operands): New static function.
2452 (process_instructions): If PC is odd, decode a mips16
2453 instruction. Break out instruction handling into new
2454 build_instruction function.
2455 (build_instruction): New static function, broken out of
2456 process_instructions. Check modifiers rather than flags for SHIFT
2457 bit count and m[ft]{hi,lo} direction.
2458 (usage): Pass program name to fprintf.
2459 (main): Remove unused variable this_option_optind. Change
2460 ``*loptarg++'' to ``loptarg++''.
2461 (my_strtoul): Parenthesize && within ||.
2462 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2463 (simulate): If PC is odd, fetch a 16 bit instruction, and
2464 increment PC by 2 rather than 4.
2465 * configure.in: Add case for mips16*-*-*.
2466 * configure: Rebuild.
2467
2468Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2469
2470 * interp.c: Allow -t to enable tracing in standalone simulator.
2471 Fix garbage output in trace file and error messages.
2472
2473Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2474
2475 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2476 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2477 * configure.in: Simplify using macros in ../common/aclocal.m4.
2478 * configure: Regenerated.
2479 * tconfig.in: New file.
2480
2481Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2482
2483 * interp.c: Fix bugs in 64-bit port.
2484 Use ansi function declarations for msvc compiler.
2485 Initialize and test file pointer in trace code.
2486 Prevent duplicate definition of LAST_EMED_REGNUM.
2487
2488Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2489
2490 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2491
2492Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2493
2494 * interp.c (SignalException): Check for explicit terminating
2495 breakpoint value.
2496 * gencode.c: Pass instruction value through SignalException()
2497 calls for Trap, Breakpoint and Syscall.
2498
2499Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2500
2501 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2502 only used on those hosts that provide it.
2503 * configure.in: Add sqrt() to list of functions to be checked for.
2504 * config.in: Re-generated.
2505 * configure: Re-generated.
2506
2507Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2508
2509 * gencode.c (process_instructions): Call build_endian_shift when
2510 expanding STORE RIGHT, to fix swr.
2511 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2512 clear the high bits.
2513 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2514 Fix float to int conversions to produce signed values.
2515
2516Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2517
2518 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2519 (process_instructions): Correct handling of nor instruction.
2520 Correct shift count for 32 bit shift instructions. Correct sign
2521 extension for arithmetic shifts to not shift the number of bits in
2522 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2523 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2524 Fix madd.
2525 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2526 It's OK to have a mult follow a mult. What's not OK is to have a
2527 mult follow an mfhi.
2528 (Convert): Comment out incorrect rounding code.
2529
2530Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2531
2532 * interp.c (sim_monitor): Improved monitor printf
2533 simulation. Tidied up simulator warnings, and added "--log" option
2534 for directing warning message output.
2535 * gencode.c: Use sim_warning() rather than WARNING macro.
2536
2537Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2538
2539 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2540 getopt1.o, rather than on gencode.c. Link objects together.
2541 Don't link against -liberty.
2542 (gencode.o, getopt.o, getopt1.o): New targets.
2543 * gencode.c: Include <ctype.h> and "ansidecl.h".
2544 (AND): Undefine after including "ansidecl.h".
2545 (ULONG_MAX): Define if not defined.
2546 (OP_*): Don't define macros; now defined in opcode/mips.h.
2547 (main): Call my_strtoul rather than strtoul.
2548 (my_strtoul): New static function.
2549
2550Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2551
2552 * gencode.c (process_instructions): Generate word64 and uword64
2553 instead of `long long' and `unsigned long long' data types.
2554 * interp.c: #include sysdep.h to get signals, and define default
2555 for SIGBUS.
2556 * (Convert): Work around for Visual-C++ compiler bug with type
2557 conversion.
2558 * support.h: Make things compile under Visual-C++ by using
2559 __int64 instead of `long long'. Change many refs to long long
2560 into word64/uword64 typedefs.
2561
2562Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2563
2564 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2565 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2566 (docdir): Removed.
2567 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2568 (AC_PROG_INSTALL): Added.
2569 (AC_PROG_CC): Moved to before configure.host call.
2570 * configure: Rebuilt.
2571
2572Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2573
2574 * configure.in: Define @SIMCONF@ depending on mips target.
2575 * configure: Rebuild.
2576 * Makefile.in (run): Add @SIMCONF@ to control simulator
2577 construction.
2578 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2579 * interp.c: Remove some debugging, provide more detailed error
2580 messages, update memory accesses to use LOADDRMASK.
2581
2582Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2583
2584 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2585 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2586 stamp-h.
2587 * configure: Rebuild.
2588 * config.in: New file, generated by autoheader.
2589 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2590 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2591 HAVE_ANINT and HAVE_AINT, as appropriate.
2592 * Makefile.in (run): Use @LIBS@ rather than -lm.
2593 (interp.o): Depend upon config.h.
2594 (Makefile): Just rebuild Makefile.
2595 (clean): Remove stamp-h.
2596 (mostlyclean): Make the same as clean, not as distclean.
2597 (config.h, stamp-h): New targets.
2598
2599Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2600
2601 * interp.c (ColdReset): Fix boolean test. Make all simulator
2602 globals static.
2603
2604Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2605
2606 * interp.c (xfer_direct_word, xfer_direct_long,
2607 swap_direct_word, swap_direct_long, xfer_big_word,
2608 xfer_big_long, xfer_little_word, xfer_little_long,
2609 swap_word,swap_long): Added.
2610 * interp.c (ColdReset): Provide function indirection to
2611 host<->simulated_target transfer routines.
2612 * interp.c (sim_store_register, sim_fetch_register): Updated to
2613 make use of indirected transfer routines.
2614
2615Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2616
2617 * gencode.c (process_instructions): Ensure FP ABS instruction
2618 recognised.
2619 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2620 system call support.
2621
2622Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2623
2624 * interp.c (sim_do_command): Complain if callback structure not
2625 initialised.
2626
2627Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2628
2629 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2630 support for Sun hosts.
2631 * Makefile.in (gencode): Ensure the host compiler and libraries
2632 used for cross-hosted build.
2633
2634Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2635
2636 * interp.c, gencode.c: Some more (TODO) tidying.
2637
2638Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2639
2640 * gencode.c, interp.c: Replaced explicit long long references with
2641 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2642 * support.h (SET64LO, SET64HI): Macros added.
2643
2644Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2645
2646 * configure: Regenerate with autoconf 2.7.
2647
2648Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2649
2650 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2651 * support.h: Remove superfluous "1" from #if.
2652 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2653
2654Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2655
2656 * interp.c (StoreFPR): Control UndefinedResult() call on
2657 WARN_RESULT manifest.
2658
2659Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2660
2661 * gencode.c: Tidied instruction decoding, and added FP instruction
2662 support.
2663
2664 * interp.c: Added dineroIII, and BSD profiling support. Also
2665 run-time FP handling.
2666
2667Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2668
2669 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2670 gencode.c, interp.c, support.h: created.
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