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2002-06-07 H.J. Lu <hjl@gnu.org>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
cfe9ea23
CD		 12002-06-06 Chris Demetriou <cgd@broadcom.com>
2 Ed Satterthwaite <ehs@broadcom.com>
3
4 * cp1.h: New file.
5 * sim-main.h: Include cp1.h.
6 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
7 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
8 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
9 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
10 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
11 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
12 * cp1.c: Don't include sim-fpu.h; already included by
13 sim-main.h. Clean up formatting of some comments.
14 (NaN, Equal, Less): Remove.
15 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
16 (fp_cmp): New functions.
17 * mips.igen (do_c_cond_fmt): Remove.
18 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
19 Compare. Add result tracing.
20 (CxC1): Remove, replace with...
21 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
22 (DMxC1): Remove, replace with...
23 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
24 (MxC1): Remove, replace with...
25 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
26
ee7254b0
CD		 272002-06-04 Chris Demetriou <cgd@broadcom.com>
28
29 * sim-main.h (FGRIDX): Remove, replace all uses with...
30 (FGR_BASE): New macro.
31 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
32 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
33 (NR_FGR, FGR): Likewise.
34 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
35 * mips.igen: Likewise.
36
d3eb724f
CD		 372002-06-04 Chris Demetriou <cgd@broadcom.com>
38
39 * cp1.c: Add an FSF Copyright notice to this file.
40
ba46ddd0
CD		 412002-06-04 Chris Demetriou <cgd@broadcom.com>
42 Ed Satterthwaite <ehs@broadcom.com>
43
44 * cp1.c (Infinity): Remove.
45 * sim-main.h (Infinity): Likewise.
46
47 * cp1.c (fp_unary, fp_binary): New functions.
48 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
49 (fp_sqrt): New functions, implemented in terms of the above.
50 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
51 (Recip, SquareRoot): Remove (replaced by functions above).
52 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
53 (fp_recip, fp_sqrt): New prototypes.
54 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
55 (Recip, SquareRoot): Replace prototypes with #defines which
56 invoke the functions above.
57
18d8a52d
CD		 582002-06-03 Chris Demetriou <cgd@broadcom.com>
59
60 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
61 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
62 file, remove PARAMS from prototypes.
63 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
64 simulator state arguments.
65 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
66 pass simulator state arguments.
67 * cp1.c (SD): Redefine as CPU_STATE(cpu).
68 (store_fpr, convert): Remove 'sd' argument.
69 (value_fpr): Likewise. Convert to use 'SD' instead.
70
0f154cbd
CD		 712002-06-03 Chris Demetriou <cgd@broadcom.com>
72
73 * cp1.c (Min, Max): Remove #if 0'd functions.
74 * sim-main.h (Min, Max): Remove.
75
e80fc152
CD		 762002-06-03 Chris Demetriou <cgd@broadcom.com>
77
78 * cp1.c: fix formatting of switch case and default labels.
79 * interp.c: Likewise.
80 * sim-main.c: Likewise.
81
bad673a9
CD		 822002-06-03 Chris Demetriou <cgd@broadcom.com>
83
84 * cp1.c: Clean up comments which describe FP formats.
85 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
86
7cbea089
CD		 872002-06-03 Chris Demetriou <cgd@broadcom.com>
88 Ed Satterthwaite <ehs@broadcom.com>
89
90 * configure.in (mipsisa64sb1*-*-*): New target for supporting
91 Broadcom SiByte SB-1 processor configurations.
92 * configure: Regenerate.
93 * sb1.igen: New file.
94 * mips.igen: Include sb1.igen.
95 (sb1): New model.
96 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
97 * mdmx.igen: Add "sb1" model to all appropriate functions and
98 instructions.
99 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
100 (ob_func, ob_acc): Reference the above.
101 (qh_acc): Adjust to keep the same size as ob_acc.
102 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
103 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
104
909daa82
CD		 1052002-06-03 Chris Demetriou <cgd@broadcom.com>
106
107 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
108
f4f1b9f1
CD		 1092002-06-02 Chris Demetriou <cgd@broadcom.com>
110 Ed Satterthwaite <ehs@broadcom.com>
111
112 * mips.igen (mdmx): New (pseudo-)model.
113 * mdmx.c, mdmx.igen: New files.
114 * Makefile.in (SIM_OBJS): Add mdmx.o.
115 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
116 New typedefs.
117 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
118 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
119 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
120 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
121 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
122 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
123 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
124 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
125 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
126 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
127 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
128 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
129 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
130 (qh_fmtsel): New macros.
131 (_sim_cpu): New member "acc".
132 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
133 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
134
5accf1ff
CD		 1352002-05-01 Chris Demetriou <cgd@broadcom.com>
136
137 * interp.c: Use 'deprecated' rather than 'depreciated.'
138 * sim-main.h: Likewise.
139
402586aa
CD		 1402002-05-01 Chris Demetriou <cgd@broadcom.com>
141
142 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
143 which wouldn't compile anyway.
144 * sim-main.h (unpredictable_action): New function prototype.
145 (Unpredictable): Define to call igen function unpredictable().
146 (NotWordValue): New macro to call igen function not_word_value().
147 (UndefinedResult): Remove.
148 * interp.c (undefined_result): Remove.
149 (unpredictable_action): New function.
150 * mips.igen (not_word_value, unpredictable): New functions.
151 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
152 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
153 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
154 NotWordValue() to check for unpredictable inputs, then
155 Unpredictable() to handle them.
156
c9b9995a
CD		 1572002-02-24 Chris Demetriou <cgd@broadcom.com>
158
159 * mips.igen: Fix formatting of calls to Unpredictable().
160
e1015982
AC		 1612002-04-20 Andrew Cagney <ac131313@redhat.com>
162
163 * interp.c (sim_open): Revert previous change.
164
b882a66b
AO		 1652002-04-18 Alexandre Oliva <aoliva@redhat.com>
166
167 * interp.c (sim_open): Disable chunk of code that wrote code in
168 vector table entries.
169
c429b7dd
CD		 1702002-03-19 Chris Demetriou <cgd@broadcom.com>
171
172 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
173 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
174 unused definitions.
175
37d146fa
CD		 1762002-03-19 Chris Demetriou <cgd@broadcom.com>
177
178 * cp1.c: Fix many formatting issues.
179
07892c0b
CD		 1802002-03-19 Chris G. Demetriou <cgd@broadcom.com>
181
182 * cp1.c (fpu_format_name): New function to replace...
183 (DOFMT): This. Delete, and update all callers.
184 (fpu_rounding_mode_name): New function to replace...
185 (RMMODE): This. Delete, and update all callers.
186
487f79b7
CD		 1872002-03-19 Chris G. Demetriou <cgd@broadcom.com>
188
189 * interp.c: Move FPU support routines from here to...
190 * cp1.c: Here. New file.
191 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
192 (cp1.o): New target.
193
1e799e28
CD		 1942002-03-12 Chris Demetriou <cgd@broadcom.com>
195
196 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
197 * mips.igen (mips32, mips64): New models, add to all instructions
198 and functions as appropriate.
199 (loadstore_ea, check_u64): New variant for model mips64.
200 (check_fmt_p): New variant for models mipsV and mips64, remove
201 mipsV model marking fro other variant.
202 (SLL) Rename to...
203 (SLLa) this.
204 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
205 for mips32 and mips64.
206 (DCLO, DCLZ): New instructions for mips64.
207
82f728db
CD		 2082002-03-07 Chris Demetriou <cgd@broadcom.com>
209
210 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
211 immediate or code as a hex value with the "%#lx" format.
212 (ANDI): Likewise, and fix printed instruction name.
213
b96e7ef1
CD		 2142002-03-05 Chris Demetriou <cgd@broadcom.com>
215
216 * sim-main.h (UndefinedResult, Unpredictable): New macros
217 which currently do nothing.
218
d35d4f70
CD		 2192002-03-05 Chris Demetriou <cgd@broadcom.com>
220
221 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
222 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
223 (status_CU3): New definitions.
224
225 * sim-main.h (ExceptionCause): Add new values for MIPS32
226 and MIPS64: MDMX, MCheck, CacheErr. Update comments
227 for DebugBreakPoint and NMIReset to note their status in
228 MIPS32 and MIPS64.
229 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
230 (SignalExceptionCacheErr): New exception macros.
231
3ad6f714
CD		 2322002-03-05 Chris Demetriou <cgd@broadcom.com>
233
234 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
235 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
236 is always enabled.
237 (SignalExceptionCoProcessorUnusable): Take as argument the
238 unusable coprocessor number.
239
86b77b47
CD		 2402002-03-05 Chris Demetriou <cgd@broadcom.com>
241
242 * mips.igen: Fix formatting of all SignalException calls.
243
97a88e93 2442002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 245
246 * sim-main.h (SIGNEXTEND): Remove.
247
97a88e93 2482002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 249
250 * mips.igen: Remove gencode comment from top of file, fix
251 spelling in another comment.
252
97a88e93 2532002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 254
255 * mips.igen (check_fmt, check_fmt_p): New functions to check
256 whether specific floating point formats are usable.
257 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
258 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
259 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
260 Use the new functions.
261 (do_c_cond_fmt): Remove format checks...
262 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
263
97a88e93 2642002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 265
266 * mips.igen: Fix formatting of check_fpu calls.
267
41774c9d
CD		 2682002-03-03 Chris Demetriou <cgd@broadcom.com>
269
270 * mips.igen (FLOOR.L.fmt): Store correct destination register.
271
4a0bd876
CD		 2722002-03-03 Chris Demetriou <cgd@broadcom.com>
273
274 * mips.igen: Remove whitespace at end of lines.
275
09297648
CD		 2762002-03-02 Chris Demetriou <cgd@broadcom.com>
277
278 * mips.igen (loadstore_ea): New function to do effective
279 address calculations.
280 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
281 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
282 CACHE): Use loadstore_ea to do effective address computations.
283
043b7057
CD		 2842002-03-02 Chris Demetriou <cgd@broadcom.com>
285
286 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
287 * mips.igen (LL, CxC1, MxC1): Likewise.
288
c1e8ada4
CD		 2892002-03-02 Chris Demetriou <cgd@broadcom.com>
290
291 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
292 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
293 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
294 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
295 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
296 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
297 Don't split opcode fields by hand, use the opcode field values
298 provided by igen.
299
3e1dca16
CD		 3002002-03-01 Chris Demetriou <cgd@broadcom.com>
301
302 * mips.igen (do_divu): Fix spacing.
303
304 * mips.igen (do_dsllv): Move to be right before DSLLV,
305 to match the rest of the do_<shift> functions.
306
fff8d27d
CD		 3072002-03-01 Chris Demetriou <cgd@broadcom.com>
308
309 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
310 DSRL32, do_dsrlv): Trace inputs and results.
311
0d3e762b
CD		 3122002-03-01 Chris Demetriou <cgd@broadcom.com>
313
314 * mips.igen (CACHE): Provide instruction-printing string.
315
316 * interp.c (signal_exception): Comment tokens after #endif.
317
eb5fcf93
CD		 3182002-02-28 Chris Demetriou <cgd@broadcom.com>
319
320 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
321 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
322 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
323 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
324 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
325 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
326 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
327 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
328
bb22bd7d
CD		 3292002-02-28 Chris Demetriou <cgd@broadcom.com>
330
331 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
332 instruction-printing string.
333 (LWU): Use '64' as the filter flag.
334
91a177cf
CD		 3352002-02-28 Chris Demetriou <cgd@broadcom.com>
336
337 * mips.igen (SDXC1): Fix instruction-printing string.
338
387f484a
CD		 3392002-02-28 Chris Demetriou <cgd@broadcom.com>
340
341 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
342 filter flags "32,f".
343
3d81f391
CD		 3442002-02-27 Chris Demetriou <cgd@broadcom.com>
345
346 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
347 as the filter flag.
348
af5107af
CD		 3492002-02-27 Chris Demetriou <cgd@broadcom.com>
350
351 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
352 add a comma) so that it more closely match the MIPS ISA
353 documentation opcode partitioning.
354 (PREF): Put useful names on opcode fields, and include
355 instruction-printing string.
356
ca971540
CD		 3572002-02-27 Chris Demetriou <cgd@broadcom.com>
358
359 * mips.igen (check_u64): New function which in the future will
360 check whether 64-bit instructions are usable and signal an
361 exception if not. Currently a no-op.
362 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
363 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
364 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
365 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
366
367 * mips.igen (check_fpu): New function which in the future will
368 check whether FPU instructions are usable and signal an exception
369 if not. Currently a no-op.
370 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
371 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
372 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
373 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
374 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
375 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
376 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
377 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
378
1c47a468
CD		 3792002-02-27 Chris Demetriou <cgd@broadcom.com>
380
381 * mips.igen (do_load_left, do_load_right): Move to be immediately
382 following do_load.
383 (do_store_left, do_store_right): Move to be immediately following
384 do_store.
385
603a98e7
CD		 3862002-02-27 Chris Demetriou <cgd@broadcom.com>
387
388 * mips.igen (mipsV): New model name. Also, add it to
389 all instructions and functions where it is appropriate.
390
c5d00cc7
CD		 3912002-02-18 Chris Demetriou <cgd@broadcom.com>
392
393 * mips.igen: For all functions and instructions, list model
394 names that support that instruction one per line.
395
074e9cb8
CD		 3962002-02-11 Chris Demetriou <cgd@broadcom.com>
397
398 * mips.igen: Add some additional comments about supported
399 models, and about which instructions go where.
400 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
401 order as is used in the rest of the file.
402
9805e229
CD		 4032002-02-11 Chris Demetriou <cgd@broadcom.com>
404
405 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
406 indicating that ALU32_END or ALU64_END are there to check
407 for overflow.
408 (DADD): Likewise, but also remove previous comment about
409 overflow checking.
410
f701dad2
CD		 4112002-02-10 Chris Demetriou <cgd@broadcom.com>
412
413 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
414 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
415 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
416 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
417 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
418 fields (i.e., add and move commas) so that they more closely
419 match the MIPS ISA documentation opcode partitioning.
420
4212002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 422
423 * mips.igen (ADDI): Print immediate value.
424 (BREAK): Print code.
425 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
426 (SLL): Print "nop" specially, and don't run the code
427 that does the shift for the "nop" case.
428
9e52972e
FF		 4292001-11-17 Fred Fish <fnf@redhat.com>
430
431 * sim-main.h (float_operation): Move enum declaration outside
432 of _sim_cpu struct declaration.
433
c0efbca4
JB		 4342001-04-12 Jim Blandy <jimb@redhat.com>
435
436 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
437 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
438 set of the FCSR.
439 * sim-main.h (COCIDX): Remove definition; this isn't supported by
440 PENDING_FILL, and you can get the intended effect gracefully by
441 calling PENDING_SCHED directly.
442
fb891446
BE		 4432001-02-23 Ben Elliston <bje@redhat.com>
444
445 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
446 already defined elsewhere.
447
8030f857
BE		 4482001-02-19 Ben Elliston <bje@redhat.com>
449
450 * sim-main.h (sim_monitor): Return an int.
451 * interp.c (sim_monitor): Add return values.
452 (signal_exception): Handle error conditions from sim_monitor.
453
56b48a7a
CD		 4542001-02-08 Ben Elliston <bje@redhat.com>
455
456 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
457 (store_memory): Likewise, pass cia to sim_core_write*.
458
d3ee60d9
FCE		 4592000-10-19 Frank Ch. Eigler <fche@redhat.com>
460
461 On advice from Chris G. Demetriou <cgd@sibyte.com>:
462 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
463
071da002
AC		 464Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
465
466 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
467 * Makefile.in: Don't delete *.igen when cleaning directory.
468
a28c02cd
AC		 469Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
470
471 * m16.igen (break): Call SignalException not sim_engine_halt.
472
80ee11fa
AC		 473Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
474
475 From Jason Eckhardt:
476 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
477
673388c0
AC		 478Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
479
480 * mips.igen (MxC1, DMxC1): Fix printf formatting.
481
4c0deff4
NC		 4822000-05-24 Michael Hayes <mhayes@cygnus.com>
483
484 * mips.igen (do_dmultx): Fix typo.
485
eb2d80b4
AC		 486Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
487
488 * configure: Regenerated to track ../common/aclocal.m4 changes.
489
dd37a34b
AC		 490Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
491
492 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
493
4c0deff4
NC		 4942000-04-12 Frank Ch. Eigler <fche@redhat.com>
495
496 * sim-main.h (GPR_CLEAR): Define macro.
497
e30db738
AC		 498Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
499
500 * interp.c (decode_coproc): Output long using %lx and not %s.
501
cb7450ea
FCE		 5022000-03-21 Frank Ch. Eigler <fche@redhat.com>
503
504 * interp.c (sim_open): Sort & extend dummy memory regions for
505 --board=jmr3904 for eCos.
506
a3027dd7
FCE		 5072000-03-02 Frank Ch. Eigler <fche@redhat.com>
508
509 * configure: Regenerated.
510
511Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
512
513 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
514 calls, conditional on the simulator being in verbose mode.
515
dfcd3bfb
JM		 516Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
517
518 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
519 cache don't get ReservedInstruction traps.
520
c2d11a7d
JM		 5211999-11-29 Mark Salter <msalter@cygnus.com>
522
523 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
524 to clear status bits in sdisr register. This is how the hardware works.
525
526 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
527 being used by cygmon.
528
4ce44c66
JM		 5291999-11-11 Andrew Haley <aph@cygnus.com>
530
531 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
532 instructions.
533
cff3e48b
JM		 534Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
535
536 * mips.igen (MULT): Correct previous mis-applied patch.
537
d4f3574e
SS		 538Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
539
540 * mips.igen (delayslot32): Handle sequence like
541 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
542 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
543 (MULT): Actually pass the third register...
544
5451999-09-03 Mark Salter <msalter@cygnus.com>
546
547 * interp.c (sim_open): Added more memory aliases for additional
548 hardware being touched by cygmon on jmr3904 board.
549
550Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
551
552 * configure: Regenerated to track ../common/aclocal.m4 changes.
553
a0b3c4fd
JM		 554Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
555
556 * interp.c (sim_store_register): Handle case where client - GDB -
557 specifies that a 4 byte register is 8 bytes in size.
558 (sim_fetch_register): Ditto.
559
adf40b2e
JM		 5601999-07-14 Frank Ch. Eigler <fche@cygnus.com>
561
562 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
563 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
564 (idt_monitor_base): Base address for IDT monitor traps.
565 (pmon_monitor_base): Ditto for PMON.
566 (lsipmon_monitor_base): Ditto for LSI PMON.
567 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
568 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
569 (sim_firmware_command): New function.
570 (mips_option_handler): Call it for OPTION_FIRMWARE.
571 (sim_open): Allocate memory for idt_monitor region. If "--board"
572 option was given, add no monitor by default. Add BREAK hooks only if
573 monitors are also there.
574
43e526b9
JM		 575Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
576
577 * interp.c (sim_monitor): Flush output before reading input.
578
579Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
580
581 * tconfig.in (SIM_HANDLES_LMA): Always define.
582
583Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
584
585 From Mark Salter <msalter@cygnus.com>:
586 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
587 (sim_open): Add setup for BSP board.
588
9846de1b
JM		 589Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
590
591 * mips.igen (MULT, MULTU): Add syntax for two operand version.
592 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
593 them as unimplemented.
594
cd0fc7c3
SS		 5951999-05-08 Felix Lee <flee@cygnus.com>
596
597 * configure: Regenerated to track ../common/aclocal.m4 changes.
598
7a292a7a
SS		 5991999-04-21 Frank Ch. Eigler <fche@cygnus.com>
600
601 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
602
603Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
604
605 * configure.in: Any mips64vr5*-*-* target should have
606 -DTARGET_ENABLE_FR=1.
607 (default_endian): Any mips64vr*el-*-* target should default to
608 LITTLE_ENDIAN.
609 * configure: Re-generate.
610
6111999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
612
613 * mips.igen (ldl): Extend from _16_, not 32.
614
615Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
616
617 * interp.c (sim_store_register): Force registers written to by GDB
618 into an un-interpreted state.
619
c906108c
SS		 6201999-02-05 Frank Ch. Eigler <fche@cygnus.com>
621
622 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
623 CPU, start periodic background I/O polls.
624 (tx3904sio_poll): New function: periodic I/O poller.
625
6261998-12-30 Frank Ch. Eigler <fche@cygnus.com>
627
628 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
629
630Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
631
632 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
633 case statement.
634
6351998-12-29 Frank Ch. Eigler <fche@cygnus.com>
636
637 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
638 (load_word): Call SIM_CORE_SIGNAL hook on error.
639 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
640 starting. For exception dispatching, pass PC instead of NULL_CIA.
641 (decode_coproc): Use COP0_BADVADDR to store faulting address.
642 * sim-main.h (COP0_BADVADDR): Define.
643 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
644 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
645 (_sim_cpu): Add exc_* fields to store register value snapshots.
646 * mips.igen (*): Replace memory-related SignalException* calls
647 with references to SIM_CORE_SIGNAL hook.
648
649 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
650 fix.
651 * sim-main.c (*): Minor warning cleanups.
652
6531998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
654
655 * m16.igen (DADDIU5): Correct type-o.
656
657Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
658
659 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
660 variables.
661
662Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
663
664 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
665 to include path.
666 (interp.o): Add dependency on itable.h
667 (oengine.c, gencode): Delete remaining references.
668 (BUILT_SRC_FROM_GEN): Clean up.
669
6701998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
671
672 * vr4run.c: New.
673 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
674 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
675 tmp-run-hack) : New.
676 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
677 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
678 Drop the "64" qualifier to get the HACK generator working.
679 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
680 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
681 qualifier to get the hack generator working.
682 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
683 (DSLL): Use do_dsll.
684 (DSLLV): Use do_dsllv.
685 (DSRA): Use do_dsra.
686 (DSRL): Use do_dsrl.
687 (DSRLV): Use do_dsrlv.
688 (BC1): Move *vr4100 to get the HACK generator working.
689 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
690 get the HACK generator working.
691 (MACC) Rename to get the HACK generator working.
692 (DMACC,MACCS,DMACCS): Add the 64.
693
6941998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
695
696 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
697 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
698
6991998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
700
701 * mips/interp.c (DEBUG): Cleanups.
702
7031998-12-10 Frank Ch. Eigler <fche@cygnus.com>
704
705 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
706 (tx3904sio_tickle): fflush after a stdout character output.
707
7081998-12-03 Frank Ch. Eigler <fche@cygnus.com>
709
710 * interp.c (sim_close): Uninstall modules.
711
712Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
713
714 * sim-main.h, interp.c (sim_monitor): Change to global
715 function.
716
717Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
718
719 * configure.in (vr4100): Only include vr4100 instructions in
720 simulator.
721 * configure: Re-generate.
722 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
723
724Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
725
726 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
727 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
728 true alternative.
729
730 * configure.in (sim_default_gen, sim_use_gen): Replace with
731 sim_gen.
732 (--enable-sim-igen): Delete config option. Always using IGEN.
733 * configure: Re-generate.
734
735 * Makefile.in (gencode): Kill, kill, kill.
736 * gencode.c: Ditto.
737
738Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
739
740 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
741 bit mips16 igen simulator.
742 * configure: Re-generate.
743
744 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
745 as part of vr4100 ISA.
746 * vr.igen: Mark all instructions as 64 bit only.
747
748Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
749
750 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
751 Pacify GCC.
752
753Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
754
755 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
756 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
757 * configure: Re-generate.
758
759 * m16.igen (BREAK): Define breakpoint instruction.
760 (JALX32): Mark instruction as mips16 and not r3900.
761 * mips.igen (C.cond.fmt): Fix typo in instruction format.
762
763 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
764
765Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
766
767 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
768 insn as a debug breakpoint.
769
770 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
771 pending.slot_size.
772 (PENDING_SCHED): Clean up trace statement.
773 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
774 (PENDING_FILL): Delay write by only one cycle.
775 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
776
777 * sim-main.c (pending_tick): Clean up trace statements. Add trace
778 of pending writes.
779 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
780 32 & 64.
781 (pending_tick): Move incrementing of index to FOR statement.
782 (pending_tick): Only update PENDING_OUT after a write has occured.
783
784 * configure.in: Add explicit mips-lsi-* target. Use gencode to
785 build simulator.
786 * configure: Re-generate.
787
788 * interp.c (sim_engine_run OLD): Delete explicit call to
789 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
790
791Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
792
793 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
794 interrupt level number to match changed SignalExceptionInterrupt
795 macro.
796
797Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
798
799 * interp.c: #include "itable.h" if WITH_IGEN.
800 (get_insn_name): New function.
801 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
802 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
803
804Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
805
806 * configure: Rebuilt to inhale new common/aclocal.m4.
807
808Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
809
810 * dv-tx3904sio.c: Include sim-assert.h.
811
812Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
813
814 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
815 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
816 Reorganize target-specific sim-hardware checks.
817 * configure: rebuilt.
818 * interp.c (sim_open): For tx39 target boards, set
819 OPERATING_ENVIRONMENT, add tx3904sio devices.
820 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
821 ROM executables. Install dv-sockser into sim-modules list.
822
823 * dv-tx3904irc.c: Compiler warning clean-up.
824 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
825 frequent hw-trace messages.
826
827Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
828
829 * vr.igen (MulAcc): Identify as a vr4100 specific function.
830
831Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
832
833 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
834
835 * vr.igen: New file.
836 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
837 * mips.igen: Define vr4100 model. Include vr.igen.
838Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
839
840 * mips.igen (check_mf_hilo): Correct check.
841
842Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
843
844 * sim-main.h (interrupt_event): Add prototype.
845
846 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
847 register_ptr, register_value.
848 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
849
850 * sim-main.h (tracefh): Make extern.
851
852Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
853
854 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
855 Reduce unnecessarily high timer event frequency.
856 * dv-tx3904cpu.c: Ditto for interrupt event.
857
858Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
859
860 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
861 to allay warnings.
862 (interrupt_event): Made non-static.
863
864 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
865 interchange of configuration values for external vs. internal
866 clock dividers.
867
868Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
869
870 * mips.igen (BREAK): Moved code to here for
871 simulator-reserved break instructions.
872 * gencode.c (build_instruction): Ditto.
873 * interp.c (signal_exception): Code moved from here. Non-
874 reserved instructions now use exception vector, rather
875 than halting sim.
876 * sim-main.h: Moved magic constants to here.
877
878Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
879
880 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
881 register upon non-zero interrupt event level, clear upon zero
882 event value.
883 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
884 by passing zero event value.
885 (*_io_{read,write}_buffer): Endianness fixes.
886 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
887 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
888
889 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
890 serial I/O and timer module at base address 0xFFFF0000.
891
892Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
893
894 * mips.igen (SWC1) : Correct the handling of ReverseEndian
895 and BigEndianCPU.
896
897Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
898
899 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
900 parts.
901 * configure: Update.
902
903Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
904
905 * dv-tx3904tmr.c: New file - implements tx3904 timer.
906 * dv-tx3904{irc,cpu}.c: Mild reformatting.
907 * configure.in: Include tx3904tmr in hw_device list.
908 * configure: Rebuilt.
909 * interp.c (sim_open): Instantiate three timer instances.
910 Fix address typo of tx3904irc instance.
911
912Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
913
914 * interp.c (signal_exception): SystemCall exception now uses
915 the exception vector.
916
917Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
918
919 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
920 to allay warnings.
921
922Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
923
924 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
925
926Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
927
928 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
929
930 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
931 sim-main.h. Declare a struct hw_descriptor instead of struct
932 hw_device_descriptor.
933
934Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
935
936 * mips.igen (do_store_left, do_load_left): Compute nr of left and
937 right bits and then re-align left hand bytes to correct byte
938 lanes. Fix incorrect computation in do_store_left when loading
939 bytes from second word.
940
941Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
942
943 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
944 * interp.c (sim_open): Only create a device tree when HW is
945 enabled.
946
947 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
948 * interp.c (signal_exception): Ditto.
949
950Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
951
952 * gencode.c: Mark BEGEZALL as LIKELY.
953
954Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
955
956 * sim-main.h (ALU32_END): Sign extend 32 bit results.
957 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
958
959Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
960
961 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
962 modules. Recognize TX39 target with "mips*tx39" pattern.
963 * configure: Rebuilt.
964 * sim-main.h (*): Added many macros defining bits in
965 TX39 control registers.
966 (SignalInterrupt): Send actual PC instead of NULL.
967 (SignalNMIReset): New exception type.
968 * interp.c (board): New variable for future use to identify
969 a particular board being simulated.
970 (mips_option_handler,mips_options): Added "--board" option.
971 (interrupt_event): Send actual PC.
972 (sim_open): Make memory layout conditional on board setting.
973 (signal_exception): Initial implementation of hardware interrupt
974 handling. Accept another break instruction variant for simulator
975 exit.
976 (decode_coproc): Implement RFE instruction for TX39.
977 (mips.igen): Decode RFE instruction as such.
978 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
979 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
980 bbegin to implement memory map.
981 * dv-tx3904cpu.c: New file.
982 * dv-tx3904irc.c: New file.
983
984Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
985
986 * mips.igen (check_mt_hilo): Create a separate r3900 version.
987
988Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
989
990 * tx.igen (madd,maddu): Replace calls to check_op_hilo
991 with calls to check_div_hilo.
992
993Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
994
995 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
996 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
997 Add special r3900 version of do_mult_hilo.
998 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
999 with calls to check_mult_hilo.
1000 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1001 with calls to check_div_hilo.
1002
1003Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1004
1005 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1006 Document a replacement.
1007
1008Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1009
1010 * interp.c (sim_monitor): Make mon_printf work.
1011
1012Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1013
1014 * sim-main.h (INSN_NAME): New arg `cpu'.
1015
1016Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1017
1018 * configure: Regenerated to track ../common/aclocal.m4 changes.
1019
1020Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1021
1022 * configure: Regenerated to track ../common/aclocal.m4 changes.
1023 * config.in: Ditto.
1024
1025Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1026
1027 * acconfig.h: New file.
1028 * configure.in: Reverted change of Apr 24; use sinclude again.
1029
1030Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1031
1032 * configure: Regenerated to track ../common/aclocal.m4 changes.
1033 * config.in: Ditto.
1034
1035Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1036
1037 * configure.in: Don't call sinclude.
1038
1039Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1040
1041 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1042
1043Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1044
1045 * mips.igen (ERET): Implement.
1046
1047 * interp.c (decode_coproc): Return sign-extended EPC.
1048
1049 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1050
1051 * interp.c (signal_exception): Do not ignore Trap.
1052 (signal_exception): On TRAP, restart at exception address.
1053 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1054 (signal_exception): Update.
1055 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1056 so that TRAP instructions are caught.
1057
1058Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1059
1060 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1061 contains HI/LO access history.
1062 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1063 (HIACCESS, LOACCESS): Delete, replace with
1064 (HIHISTORY, LOHISTORY): New macros.
1065 (CHECKHILO): Delete all, moved to mips.igen
1066
1067 * gencode.c (build_instruction): Do not generate checks for
1068 correct HI/LO register usage.
1069
1070 * interp.c (old_engine_run): Delete checks for correct HI/LO
1071 register usage.
1072
1073 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1074 check_mf_cycles): New functions.
1075 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1076 do_divu, domultx, do_mult, do_multu): Use.
1077
1078 * tx.igen ("madd", "maddu"): Use.
1079
1080Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1081
1082 * mips.igen (DSRAV): Use function do_dsrav.
1083 (SRAV): Use new function do_srav.
1084
1085 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1086 (B): Sign extend 11 bit immediate.
1087 (EXT-B*): Shift 16 bit immediate left by 1.
1088 (ADDIU*): Don't sign extend immediate value.
1089
1090Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1091
1092 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1093
1094 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1095 functions.
1096
1097 * mips.igen (delayslot32, nullify_next_insn): New functions.
1098 (m16.igen): Always include.
1099 (do_*): Add more tracing.
1100
1101 * m16.igen (delayslot16): Add NIA argument, could be called by a
1102 32 bit MIPS16 instruction.
1103
1104 * interp.c (ifetch16): Move function from here.
1105 * sim-main.c (ifetch16): To here.
1106
1107 * sim-main.c (ifetch16, ifetch32): Update to match current
1108 implementations of LH, LW.
1109 (signal_exception): Don't print out incorrect hex value of illegal
1110 instruction.
1111
1112Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1113
1114 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1115 instruction.
1116
1117 * m16.igen: Implement MIPS16 instructions.
1118
1119 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1120 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1121 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1122 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1123 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1124 bodies of corresponding code from 32 bit insn to these. Also used
1125 by MIPS16 versions of functions.
1126
1127 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1128 (IMEM16): Drop NR argument from macro.
1129
1130Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1131
1132 * Makefile.in (SIM_OBJS): Add sim-main.o.
1133
1134 * sim-main.h (address_translation, load_memory, store_memory,
1135 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1136 as INLINE_SIM_MAIN.
1137 (pr_addr, pr_uword64): Declare.
1138 (sim-main.c): Include when H_REVEALS_MODULE_P.
1139
1140 * interp.c (address_translation, load_memory, store_memory,
1141 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1142 from here.
1143 * sim-main.c: To here. Fix compilation problems.
1144
1145 * configure.in: Enable inlining.
1146 * configure: Re-config.
1147
1148Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1149
1150 * configure: Regenerated to track ../common/aclocal.m4 changes.
1151
1152Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1153
1154 * mips.igen: Include tx.igen.
1155 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1156 * tx.igen: New file, contains MADD and MADDU.
1157
1158 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1159 the hardwired constant `7'.
1160 (store_memory): Ditto.
1161 (LOADDRMASK): Move definition to sim-main.h.
1162
1163 mips.igen (MTC0): Enable for r3900.
1164 (ADDU): Add trace.
1165
1166 mips.igen (do_load_byte): Delete.
1167 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1168 do_store_right): New functions.
1169 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1170
1171 configure.in: Let the tx39 use igen again.
1172 configure: Update.
1173
1174Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1175
1176 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1177 not an address sized quantity. Return zero for cache sizes.
1178
1179Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1180
1181 * mips.igen (r3900): r3900 does not support 64 bit integer
1182 operations.
1183
1184Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1185
1186 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1187 than igen one.
1188 * configure : Rebuild.
1189
1190Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * configure: Regenerated to track ../common/aclocal.m4 changes.
1193
1194Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1195
1196 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1197
1198Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1199
1200 * configure: Regenerated to track ../common/aclocal.m4 changes.
1201 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1202
1203Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1204
1205 * configure: Regenerated to track ../common/aclocal.m4 changes.
1206
1207Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1208
1209 * interp.c (Max, Min): Comment out functions. Not yet used.
1210
1211Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1212
1213 * configure: Regenerated to track ../common/aclocal.m4 changes.
1214
1215Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1216
1217 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1218 configurable settings for stand-alone simulator.
1219
1220 * configure.in: Added X11 search, just in case.
1221
1222 * configure: Regenerated.
1223
1224Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1225
1226 * interp.c (sim_write, sim_read, load_memory, store_memory):
1227 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1228
1229Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1230
1231 * sim-main.h (GETFCC): Return an unsigned value.
1232
1233Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1234
1235 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1236 (DADD): Result destination is RD not RT.
1237
1238Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * sim-main.h (HIACCESS, LOACCESS): Always define.
1241
1242 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1243
1244 * interp.c (sim_info): Delete.
1245
1246Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1247
1248 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1249 (mips_option_handler): New argument `cpu'.
1250 (sim_open): Update call to sim_add_option_table.
1251
1252Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1253
1254 * mips.igen (CxC1): Add tracing.
1255
1256Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1257
1258 * sim-main.h (Max, Min): Declare.
1259
1260 * interp.c (Max, Min): New functions.
1261
1262 * mips.igen (BC1): Add tracing.
1263
1264Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1265
1266 * interp.c Added memory map for stack in vr4100
1267
1268Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1269
1270 * interp.c (load_memory): Add missing "break"'s.
1271
1272Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1273
1274 * interp.c (sim_store_register, sim_fetch_register): Pass in
1275 length parameter. Return -1.
1276
1277Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1278
1279 * interp.c: Added hardware init hook, fixed warnings.
1280
1281Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1284
1285Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * interp.c (ifetch16): New function.
1288
1289 * sim-main.h (IMEM32): Rename IMEM.
1290 (IMEM16_IMMED): Define.
1291 (IMEM16): Define.
1292 (DELAY_SLOT): Update.
1293
1294 * m16run.c (sim_engine_run): New file.
1295
1296 * m16.igen: All instructions except LB.
1297 (LB): Call do_load_byte.
1298 * mips.igen (do_load_byte): New function.
1299 (LB): Call do_load_byte.
1300
1301 * mips.igen: Move spec for insn bit size and high bit from here.
1302 * Makefile.in (tmp-igen, tmp-m16): To here.
1303
1304 * m16.dc: New file, decode mips16 instructions.
1305
1306 * Makefile.in (SIM_NO_ALL): Define.
1307 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1308
1309Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1310
1311 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1312 point unit to 32 bit registers.
1313 * configure: Re-generate.
1314
1315Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1316
1317 * configure.in (sim_use_gen): Make IGEN the default simulator
1318 generator for generic 32 and 64 bit mips targets.
1319 * configure: Re-generate.
1320
1321Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1322
1323 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1324 bitsize.
1325
1326 * interp.c (sim_fetch_register, sim_store_register): Read/write
1327 FGR from correct location.
1328 (sim_open): Set size of FGR's according to
1329 WITH_TARGET_FLOATING_POINT_BITSIZE.
1330
1331 * sim-main.h (FGR): Store floating point registers in a separate
1332 array.
1333
1334Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1335
1336 * configure: Regenerated to track ../common/aclocal.m4 changes.
1337
1338Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1339
1340 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1341
1342 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1343
1344 * interp.c (pending_tick): New function. Deliver pending writes.
1345
1346 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1347 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1348 it can handle mixed sized quantites and single bits.
1349
1350Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1351
1352 * interp.c (oengine.h): Do not include when building with IGEN.
1353 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1354 (sim_info): Ditto for PROCESSOR_64BIT.
1355 (sim_monitor): Replace ut_reg with unsigned_word.
1356 (*): Ditto for t_reg.
1357 (LOADDRMASK): Define.
1358 (sim_open): Remove defunct check that host FP is IEEE compliant,
1359 using software to emulate floating point.
1360 (value_fpr, ...): Always compile, was conditional on HASFPU.
1361
1362Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1363
1364 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1365 size.
1366
1367 * interp.c (SD, CPU): Define.
1368 (mips_option_handler): Set flags in each CPU.
1369 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1370 (sim_close): Do not clear STATE, deleted anyway.
1371 (sim_write, sim_read): Assume CPU zero's vm should be used for
1372 data transfers.
1373 (sim_create_inferior): Set the PC for all processors.
1374 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1375 argument.
1376 (mips16_entry): Pass correct nr of args to store_word, load_word.
1377 (ColdReset): Cold reset all cpu's.
1378 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1379 (sim_monitor, load_memory, store_memory, signal_exception): Use
1380 `CPU' instead of STATE_CPU.
1381
1382
1383 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1384 SD or CPU_.
1385
1386 * sim-main.h (signal_exception): Add sim_cpu arg.
1387 (SignalException*): Pass both SD and CPU to signal_exception.
1388 * interp.c (signal_exception): Update.
1389
1390 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1391 Ditto
1392 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1393 address_translation): Ditto
1394 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1395
1396Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1397
1398 * configure: Regenerated to track ../common/aclocal.m4 changes.
1399
1400Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1401
1402 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1403
1404 * mips.igen (model): Map processor names onto BFD name.
1405
1406 * sim-main.h (CPU_CIA): Delete.
1407 (SET_CIA, GET_CIA): Define
1408
1409Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1410
1411 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1412 regiser.
1413
1414 * configure.in (default_endian): Configure a big-endian simulator
1415 by default.
1416 * configure: Re-generate.
1417
1418Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1419
1420 * configure: Regenerated to track ../common/aclocal.m4 changes.
1421
1422Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1423
1424 * interp.c (sim_monitor): Handle Densan monitor outbyte
1425 and inbyte functions.
1426
14271997-12-29 Felix Lee <flee@cygnus.com>
1428
1429 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1430
1431Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1432
1433 * Makefile.in (tmp-igen): Arrange for $zero to always be
1434 reset to zero after every instruction.
1435
1436Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * configure: Regenerated to track ../common/aclocal.m4 changes.
1439 * config.in: Ditto.
1440
1441Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1442
1443 * mips.igen (MSUB): Fix to work like MADD.
1444 * gencode.c (MSUB): Similarly.
1445
1446Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1447
1448 * configure: Regenerated to track ../common/aclocal.m4 changes.
1449
1450Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1451
1452 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1453
1454Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * sim-main.h (sim-fpu.h): Include.
1457
1458 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1459 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1460 using host independant sim_fpu module.
1461
1462Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * interp.c (signal_exception): Report internal errors with SIGABRT
1465 not SIGQUIT.
1466
1467 * sim-main.h (C0_CONFIG): New register.
1468 (signal.h): No longer include.
1469
1470 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1471
1472Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1473
1474 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1475
1476Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1477
1478 * mips.igen: Tag vr5000 instructions.
1479 (ANDI): Was missing mipsIV model, fix assembler syntax.
1480 (do_c_cond_fmt): New function.
1481 (C.cond.fmt): Handle mips I-III which do not support CC field
1482 separatly.
1483 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1484 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1485 in IV3.2 spec.
1486 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1487 vr5000 which saves LO in a GPR separatly.
1488
1489 * configure.in (enable-sim-igen): For vr5000, select vr5000
1490 specific instructions.
1491 * configure: Re-generate.
1492
1493Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1494
1495 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1496
1497 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1498 fmt_uninterpreted_64 bit cases to switch. Convert to
1499 fmt_formatted,
1500
1501 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1502
1503 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1504 as specified in IV3.2 spec.
1505 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1506
1507Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1510 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1511 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1512 PENDING_FILL versions of instructions. Simplify.
1513 (X): New function.
1514 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1515 instructions.
1516 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1517 a signed value.
1518 (MTHI, MFHI): Disable code checking HI-LO.
1519
1520 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1521 global.
1522 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1523
1524Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * gencode.c (build_mips16_operands): Replace IPC with cia.
1527
1528 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1529 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1530 IPC to `cia'.
1531 (UndefinedResult): Replace function with macro/function
1532 combination.
1533 (sim_engine_run): Don't save PC in IPC.
1534
1535 * sim-main.h (IPC): Delete.
1536
1537
1538 * interp.c (signal_exception, store_word, load_word,
1539 address_translation, load_memory, store_memory, cache_op,
1540 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1541 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1542 current instruction address - cia - argument.
1543 (sim_read, sim_write): Call address_translation directly.
1544 (sim_engine_run): Rename variable vaddr to cia.
1545 (signal_exception): Pass cia to sim_monitor
1546
1547 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1548 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1549 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1550
1551 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1552 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1553 SIM_ASSERT.
1554
1555 * interp.c (signal_exception): Pass restart address to
1556 sim_engine_restart.
1557
1558 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1559 idecode.o): Add dependency.
1560
1561 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1562 Delete definitions
1563 (DELAY_SLOT): Update NIA not PC with branch address.
1564 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1565
1566 * mips.igen: Use CIA not PC in branch calculations.
1567 (illegal): Call SignalException.
1568 (BEQ, ADDIU): Fix assembler.
1569
1570Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * m16.igen (JALX): Was missing.
1573
1574 * configure.in (enable-sim-igen): New configuration option.
1575 * configure: Re-generate.
1576
1577 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1578
1579 * interp.c (load_memory, store_memory): Delete parameter RAW.
1580 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1581 bypassing {load,store}_memory.
1582
1583 * sim-main.h (ByteSwapMem): Delete definition.
1584
1585 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1586
1587 * interp.c (sim_do_command, sim_commands): Delete mips specific
1588 commands. Handled by module sim-options.
1589
1590 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1591 (WITH_MODULO_MEMORY): Define.
1592
1593 * interp.c (sim_info): Delete code printing memory size.
1594
1595 * interp.c (mips_size): Nee sim_size, delete function.
1596 (power2): Delete.
1597 (monitor, monitor_base, monitor_size): Delete global variables.
1598 (sim_open, sim_close): Delete code creating monitor and other
1599 memory regions. Use sim-memopts module, via sim_do_commandf, to
1600 manage memory regions.
1601 (load_memory, store_memory): Use sim-core for memory model.
1602
1603 * interp.c (address_translation): Delete all memory map code
1604 except line forcing 32 bit addresses.
1605
1606Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1607
1608 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1609 trace options.
1610
1611 * interp.c (logfh, logfile): Delete globals.
1612 (sim_open, sim_close): Delete code opening & closing log file.
1613 (mips_option_handler): Delete -l and -n options.
1614 (OPTION mips_options): Ditto.
1615
1616 * interp.c (OPTION mips_options): Rename option trace to dinero.
1617 (mips_option_handler): Update.
1618
1619Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1620
1621 * interp.c (fetch_str): New function.
1622 (sim_monitor): Rewrite using sim_read & sim_write.
1623 (sim_open): Check magic number.
1624 (sim_open): Write monitor vectors into memory using sim_write.
1625 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1626 (sim_read, sim_write): Simplify - transfer data one byte at a
1627 time.
1628 (load_memory, store_memory): Clarify meaning of parameter RAW.
1629
1630 * sim-main.h (isHOST): Defete definition.
1631 (isTARGET): Mark as depreciated.
1632 (address_translation): Delete parameter HOST.
1633
1634 * interp.c (address_translation): Delete parameter HOST.
1635
1636Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1637
1638 * mips.igen:
1639
1640 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1641 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1642
1643Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 * mips.igen: Add model filter field to records.
1646
1647Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1648
1649 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1650
1651 interp.c (sim_engine_run): Do not compile function sim_engine_run
1652 when WITH_IGEN == 1.
1653
1654 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1655 target architecture.
1656
1657 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1658 igen. Replace with configuration variables sim_igen_flags /
1659 sim_m16_flags.
1660
1661 * m16.igen: New file. Copy mips16 insns here.
1662 * mips.igen: From here.
1663
1664Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1665
1666 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1667 to top.
1668 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1669
1670Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1671
1672 * gencode.c (build_instruction): Follow sim_write's lead in using
1673 BigEndianMem instead of !ByteSwapMem.
1674
1675Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * configure.in (sim_gen): Dependent on target, select type of
1678 generator. Always select old style generator.
1679
1680 configure: Re-generate.
1681
1682 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1683 targets.
1684 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1685 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1686 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1687 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1688 SIM_@sim_gen@_*, set by autoconf.
1689
1690Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1691
1692 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1693
1694 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1695 CURRENT_FLOATING_POINT instead.
1696
1697 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1698 (address_translation): Raise exception InstructionFetch when
1699 translation fails and isINSTRUCTION.
1700
1701 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1702 sim_engine_run): Change type of of vaddr and paddr to
1703 address_word.
1704 (address_translation, prefetch, load_memory, store_memory,
1705 cache_op): Change type of vAddr and pAddr to address_word.
1706
1707 * gencode.c (build_instruction): Change type of vaddr and paddr to
1708 address_word.
1709
1710Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1711
1712 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1713 macro to obtain result of ALU op.
1714
1715Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1716
1717 * interp.c (sim_info): Call profile_print.
1718
1719Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1722
1723 * sim-main.h (WITH_PROFILE): Do not define, defined in
1724 common/sim-config.h. Use sim-profile module.
1725 (simPROFILE): Delete defintion.
1726
1727 * interp.c (PROFILE): Delete definition.
1728 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1729 (sim_close): Delete code writing profile histogram.
1730 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1731 Delete.
1732 (sim_engine_run): Delete code profiling the PC.
1733
1734Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1735
1736 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1737
1738 * interp.c (sim_monitor): Make register pointers of type
1739 unsigned_word*.
1740
1741 * sim-main.h: Make registers of type unsigned_word not
1742 signed_word.
1743
1744Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745
1746 * interp.c (sync_operation): Rename from SyncOperation, make
1747 global, add SD argument.
1748 (prefetch): Rename from Prefetch, make global, add SD argument.
1749 (decode_coproc): Make global.
1750
1751 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1752
1753 * gencode.c (build_instruction): Generate DecodeCoproc not
1754 decode_coproc calls.
1755
1756 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1757 (SizeFGR): Move to sim-main.h
1758 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1759 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1760 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1761 sim-main.h.
1762 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1763 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1764 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1765 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1766 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1767 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1768
1769 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1770 exception.
1771 (sim-alu.h): Include.
1772 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1773 (sim_cia): Typedef to instruction_address.
1774
1775Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1776
1777 * Makefile.in (interp.o): Rename generated file engine.c to
1778 oengine.c.
1779
1780 * interp.c: Update.
1781
1782Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1783
1784 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1785
1786Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1787
1788 * gencode.c (build_instruction): For "FPSQRT", output correct
1789 number of arguments to Recip.
1790
1791Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1792
1793 * Makefile.in (interp.o): Depends on sim-main.h
1794
1795 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1796
1797 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1798 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1799 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1800 STATE, DSSTATE): Define
1801 (GPR, FGRIDX, ..): Define.
1802
1803 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1804 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1805 (GPR, FGRIDX, ...): Delete macros.
1806
1807 * interp.c: Update names to match defines from sim-main.h
1808
1809Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * interp.c (sim_monitor): Add SD argument.
1812 (sim_warning): Delete. Replace calls with calls to
1813 sim_io_eprintf.
1814 (sim_error): Delete. Replace calls with sim_io_error.
1815 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1816 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1817 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1818 argument.
1819 (mips_size): Rename from sim_size. Add SD argument.
1820
1821 * interp.c (simulator): Delete global variable.
1822 (callback): Delete global variable.
1823 (mips_option_handler, sim_open, sim_write, sim_read,
1824 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1825 sim_size,sim_monitor): Use sim_io_* not callback->*.
1826 (sim_open): ZALLOC simulator struct.
1827 (PROFILE): Do not define.
1828
1829Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1830
1831 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1832 support.h with corresponding code.
1833
1834 * sim-main.h (word64, uword64), support.h: Move definition to
1835 sim-main.h.
1836 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1837
1838 * support.h: Delete
1839 * Makefile.in: Update dependencies
1840 * interp.c: Do not include.
1841
1842Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * interp.c (address_translation, load_memory, store_memory,
1845 cache_op): Rename to from AddressTranslation et.al., make global,
1846 add SD argument
1847
1848 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1849 CacheOp): Define.
1850
1851 * interp.c (SignalException): Rename to signal_exception, make
1852 global.
1853
1854 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1855
1856 * sim-main.h (SignalException, SignalExceptionInterrupt,
1857 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1858 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1859 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1860 Define.
1861
1862 * interp.c, support.h: Use.
1863
1864Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1865
1866 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1867 to value_fpr / store_fpr. Add SD argument.
1868 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1869 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1870
1871 * sim-main.h (ValueFPR, StoreFPR): Define.
1872
1873Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1874
1875 * interp.c (sim_engine_run): Check consistency between configure
1876 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1877 and HASFPU.
1878
1879 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1880 (mips_fpu): Configure WITH_FLOATING_POINT.
1881 (mips_endian): Configure WITH_TARGET_ENDIAN.
1882 * configure: Update.
1883
1884Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * configure: Regenerated to track ../common/aclocal.m4 changes.
1887
1888Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1889
1890 * configure: Regenerated.
1891
1892Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1893
1894 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1895
1896Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * gencode.c (print_igen_insn_models): Assume certain architectures
1899 include all mips* instructions.
1900 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1901 instruction.
1902
1903 * Makefile.in (tmp.igen): Add target. Generate igen input from
1904 gencode file.
1905
1906 * gencode.c (FEATURE_IGEN): Define.
1907 (main): Add --igen option. Generate output in igen format.
1908 (process_instructions): Format output according to igen option.
1909 (print_igen_insn_format): New function.
1910 (print_igen_insn_models): New function.
1911 (process_instructions): Only issue warnings and ignore
1912 instructions when no FEATURE_IGEN.
1913
1914Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1917 MIPS targets.
1918
1919Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1920
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1922
1923Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1926 SIM_RESERVED_BITS): Delete, moved to common.
1927 (SIM_EXTRA_CFLAGS): Update.
1928
1929Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1930
1931 * configure.in: Configure non-strict memory alignment.
1932 * configure: Regenerated to track ../common/aclocal.m4 changes.
1933
1934Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * configure: Regenerated to track ../common/aclocal.m4 changes.
1937
1938Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1939
1940 * gencode.c (SDBBP,DERET): Added (3900) insns.
1941 (RFE): Turn on for 3900.
1942 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1943 (dsstate): Made global.
1944 (SUBTARGET_R3900): Added.
1945 (CANCELDELAYSLOT): New.
1946 (SignalException): Ignore SystemCall rather than ignore and
1947 terminate. Add DebugBreakPoint handling.
1948 (decode_coproc): New insns RFE, DERET; and new registers Debug
1949 and DEPC protected by SUBTARGET_R3900.
1950 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1951 bits explicitly.
1952 * Makefile.in,configure.in: Add mips subtarget option.
1953 * configure: Update.
1954
1955Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1956
1957 * gencode.c: Add r3900 (tx39).
1958
1959
1960Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1961
1962 * gencode.c (build_instruction): Don't need to subtract 4 for
1963 JALR, just 2.
1964
1965Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1966
1967 * interp.c: Correct some HASFPU problems.
1968
1969Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1970
1971 * configure: Regenerated to track ../common/aclocal.m4 changes.
1972
1973Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * interp.c (mips_options): Fix samples option short form, should
1976 be `x'.
1977
1978Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * interp.c (sim_info): Enable info code. Was just returning.
1981
1982Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1985 MFC0.
1986
1987Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1990 constants.
1991 (build_instruction): Ditto for LL.
1992
1993Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1994
1995 * configure: Regenerated to track ../common/aclocal.m4 changes.
1996
1997Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * configure: Regenerated to track ../common/aclocal.m4 changes.
2000 * config.in: Ditto.
2001
2002Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * interp.c (sim_open): Add call to sim_analyze_program, update
2005 call to sim_config.
2006
2007Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2008
2009 * interp.c (sim_kill): Delete.
2010 (sim_create_inferior): Add ABFD argument. Set PC from same.
2011 (sim_load): Move code initializing trap handlers from here.
2012 (sim_open): To here.
2013 (sim_load): Delete, use sim-hload.c.
2014
2015 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2016
2017Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * configure: Regenerated to track ../common/aclocal.m4 changes.
2020 * config.in: Ditto.
2021
2022Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * interp.c (sim_open): Add ABFD argument.
2025 (sim_load): Move call to sim_config from here.
2026 (sim_open): To here. Check return status.
2027
2028Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2029
2030 * gencode.c (build_instruction): Two arg MADD should
2031 not assign result to $0.
2032
2033Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2034
2035 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2036 * sim/mips/configure.in: Regenerate.
2037
2038Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2039
2040 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2041 signed8, unsigned8 et.al. types.
2042
2043 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2044 hosts when selecting subreg.
2045
2046Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2047
2048 * interp.c (sim_engine_run): Reset the ZERO register to zero
2049 regardless of FEATURE_WARN_ZERO.
2050 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2051
2052Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2053
2054 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2055 (SignalException): For BreakPoints ignore any mode bits and just
2056 save the PC.
2057 (SignalException): Always set the CAUSE register.
2058
2059Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2060
2061 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2062 exception has been taken.
2063
2064 * interp.c: Implement the ERET and mt/f sr instructions.
2065
2066Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2067
2068 * interp.c (SignalException): Don't bother restarting an
2069 interrupt.
2070
2071Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * interp.c (SignalException): Really take an interrupt.
2074 (interrupt_event): Only deliver interrupts when enabled.
2075
2076Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2077
2078 * interp.c (sim_info): Only print info when verbose.
2079 (sim_info) Use sim_io_printf for output.
2080
2081Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2084 mips architectures.
2085
2086Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * interp.c (sim_do_command): Check for common commands if a
2089 simulator specific command fails.
2090
2091Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2092
2093 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2094 and simBE when DEBUG is defined.
2095
2096Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2097
2098 * interp.c (interrupt_event): New function. Pass exception event
2099 onto exception handler.
2100
2101 * configure.in: Check for stdlib.h.
2102 * configure: Regenerate.
2103
2104 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2105 variable declaration.
2106 (build_instruction): Initialize memval1.
2107 (build_instruction): Add UNUSED attribute to byte, bigend,
2108 reverse.
2109 (build_operands): Ditto.
2110
2111 * interp.c: Fix GCC warnings.
2112 (sim_get_quit_code): Delete.
2113
2114 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2115 * Makefile.in: Ditto.
2116 * configure: Re-generate.
2117
2118 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2119
2120Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2121
2122 * interp.c (mips_option_handler): New function parse argumes using
2123 sim-options.
2124 (myname): Replace with STATE_MY_NAME.
2125 (sim_open): Delete check for host endianness - performed by
2126 sim_config.
2127 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2128 (sim_open): Move much of the initialization from here.
2129 (sim_load): To here. After the image has been loaded and
2130 endianness set.
2131 (sim_open): Move ColdReset from here.
2132 (sim_create_inferior): To here.
2133 (sim_open): Make FP check less dependant on host endianness.
2134
2135 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2136 run.
2137 * interp.c (sim_set_callbacks): Delete.
2138
2139 * interp.c (membank, membank_base, membank_size): Replace with
2140 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2141 (sim_open): Remove call to callback->init. gdb/run do this.
2142
2143 * interp.c: Update
2144
2145 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2146
2147 * interp.c (big_endian_p): Delete, replaced by
2148 current_target_byte_order.
2149
2150Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * interp.c (host_read_long, host_read_word, host_swap_word,
2153 host_swap_long): Delete. Using common sim-endian.
2154 (sim_fetch_register, sim_store_register): Use H2T.
2155 (pipeline_ticks): Delete. Handled by sim-events.
2156 (sim_info): Update.
2157 (sim_engine_run): Update.
2158
2159Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160
2161 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2162 reason from here.
2163 (SignalException): To here. Signal using sim_engine_halt.
2164 (sim_stop_reason): Delete, moved to common.
2165
2166Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2167
2168 * interp.c (sim_open): Add callback argument.
2169 (sim_set_callbacks): Delete SIM_DESC argument.
2170 (sim_size): Ditto.
2171
2172Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * Makefile.in (SIM_OBJS): Add common modules.
2175
2176 * interp.c (sim_set_callbacks): Also set SD callback.
2177 (set_endianness, xfer_*, swap_*): Delete.
2178 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2179 Change to functions using sim-endian macros.
2180 (control_c, sim_stop): Delete, use common version.
2181 (simulate): Convert into.
2182 (sim_engine_run): This function.
2183 (sim_resume): Delete.
2184
2185 * interp.c (simulation): New variable - the simulator object.
2186 (sim_kind): Delete global - merged into simulation.
2187 (sim_load): Cleanup. Move PC assignment from here.
2188 (sim_create_inferior): To here.
2189
2190 * sim-main.h: New file.
2191 * interp.c (sim-main.h): Include.
2192
2193Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2194
2195 * configure: Regenerated to track ../common/aclocal.m4 changes.
2196
2197Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2198
2199 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2200
2201Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2202
2203 * gencode.c (build_instruction): DIV instructions: check
2204 for division by zero and integer overflow before using
2205 host's division operation.
2206
2207Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2208
2209 * Makefile.in (SIM_OBJS): Add sim-load.o.
2210 * interp.c: #include bfd.h.
2211 (target_byte_order): Delete.
2212 (sim_kind, myname, big_endian_p): New static locals.
2213 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2214 after argument parsing. Recognize -E arg, set endianness accordingly.
2215 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2216 load file into simulator. Set PC from bfd.
2217 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2218 (set_endianness): Use big_endian_p instead of target_byte_order.
2219
2220Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * interp.c (sim_size): Delete prototype - conflicts with
2223 definition in remote-sim.h. Correct definition.
2224
2225Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2226
2227 * configure: Regenerated to track ../common/aclocal.m4 changes.
2228 * config.in: Ditto.
2229
2230Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2231
2232 * interp.c (sim_open): New arg `kind'.
2233
2234 * configure: Regenerated to track ../common/aclocal.m4 changes.
2235
2236Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2237
2238 * configure: Regenerated to track ../common/aclocal.m4 changes.
2239
2240Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2241
2242 * interp.c (sim_open): Set optind to 0 before calling getopt.
2243
2244Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2245
2246 * configure: Regenerated to track ../common/aclocal.m4 changes.
2247
2248Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2249
2250 * interp.c : Replace uses of pr_addr with pr_uword64
2251 where the bit length is always 64 independent of SIM_ADDR.
2252 (pr_uword64) : added.
2253
2254Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2255
2256 * configure: Re-generate.
2257
2258Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2259
2260 * configure: Regenerate to track ../common/aclocal.m4 changes.
2261
2262Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2263
2264 * interp.c (sim_open): New SIM_DESC result. Argument is now
2265 in argv form.
2266 (other sim_*): New SIM_DESC argument.
2267
2268Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2269
2270 * interp.c: Fix printing of addresses for non-64-bit targets.
2271 (pr_addr): Add function to print address based on size.
2272
2273Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2274
2275 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2276
2277Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2278
2279 * gencode.c (build_mips16_operands): Correct computation of base
2280 address for extended PC relative instruction.
2281
2282Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2283
2284 * interp.c (mips16_entry): Add support for floating point cases.
2285 (SignalException): Pass floating point cases to mips16_entry.
2286 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2287 registers.
2288 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2289 or fmt_word.
2290 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2291 and then set the state to fmt_uninterpreted.
2292 (COP_SW): Temporarily set the state to fmt_word while calling
2293 ValueFPR.
2294
2295Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2296
2297 * gencode.c (build_instruction): The high order may be set in the
2298 comparison flags at any ISA level, not just ISA 4.
2299
2300Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2301
2302 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2303 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2304 * configure.in: sinclude ../common/aclocal.m4.
2305 * configure: Regenerated.
2306
2307Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2308
2309 * configure: Rebuild after change to aclocal.m4.
2310
2311Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2312
2313 * configure configure.in Makefile.in: Update to new configure
2314 scheme which is more compatible with WinGDB builds.
2315 * configure.in: Improve comment on how to run autoconf.
2316 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2317 * Makefile.in: Use autoconf substitution to install common
2318 makefile fragment.
2319
2320Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2321
2322 * gencode.c (build_instruction): Use BigEndianCPU instead of
2323 ByteSwapMem.
2324
2325Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2326
2327 * interp.c (sim_monitor): Make output to stdout visible in
2328 wingdb's I/O log window.
2329
2330Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2331
2332 * support.h: Undo previous change to SIGTRAP
2333 and SIGQUIT values.
2334
2335Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2336
2337 * interp.c (store_word, load_word): New static functions.
2338 (mips16_entry): New static function.
2339 (SignalException): Look for mips16 entry and exit instructions.
2340 (simulate): Use the correct index when setting fpr_state after
2341 doing a pending move.
2342
2343Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2344
2345 * interp.c: Fix byte-swapping code throughout to work on
2346 both little- and big-endian hosts.
2347
2348Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2349
2350 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2351 with gdb/config/i386/xm-windows.h.
2352
2353Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2354
2355 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2356 that messes up arithmetic shifts.
2357
2358Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2359
2360 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2361 SIGTRAP and SIGQUIT for _WIN32.
2362
2363Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2364
2365 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2366 force a 64 bit multiplication.
2367 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2368 destination register is 0, since that is the default mips16 nop
2369 instruction.
2370
2371Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2372
2373 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2374 (build_endian_shift): Don't check proc64.
2375 (build_instruction): Always set memval to uword64. Cast op2 to
2376 uword64 when shifting it left in memory instructions. Always use
2377 the same code for stores--don't special case proc64.
2378
2379 * gencode.c (build_mips16_operands): Fix base PC value for PC
2380 relative operands.
2381 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2382 jal instruction.
2383 * interp.c (simJALDELAYSLOT): Define.
2384 (JALDELAYSLOT): Define.
2385 (INDELAYSLOT, INJALDELAYSLOT): Define.
2386 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2387
2388Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2389
2390 * interp.c (sim_open): add flush_cache as a PMON routine
2391 (sim_monitor): handle flush_cache by ignoring it
2392
2393Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2394
2395 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2396 BigEndianMem.
2397 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2398 (BigEndianMem): Rename to ByteSwapMem and change sense.
2399 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2400 BigEndianMem references to !ByteSwapMem.
2401 (set_endianness): New function, with prototype.
2402 (sim_open): Call set_endianness.
2403 (sim_info): Use simBE instead of BigEndianMem.
2404 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2405 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2406 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2407 ifdefs, keeping the prototype declaration.
2408 (swap_word): Rewrite correctly.
2409 (ColdReset): Delete references to CONFIG. Delete endianness related
2410 code; moved to set_endianness.
2411
2412Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2413
2414 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2415 * interp.c (CHECKHILO): Define away.
2416 (simSIGINT): New macro.
2417 (membank_size): Increase from 1MB to 2MB.
2418 (control_c): New function.
2419 (sim_resume): Rename parameter signal to signal_number. Add local
2420 variable prev. Call signal before and after simulate.
2421 (sim_stop_reason): Add simSIGINT support.
2422 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2423 functions always.
2424 (sim_warning): Delete call to SignalException. Do call printf_filtered
2425 if logfh is NULL.
2426 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2427 a call to sim_warning.
2428
2429Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2430
2431 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2432 16 bit instructions.
2433
2434Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2435
2436 Add support for mips16 (16 bit MIPS implementation):
2437 * gencode.c (inst_type): Add mips16 instruction encoding types.
2438 (GETDATASIZEINSN): Define.
2439 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2440 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2441 mtlo.
2442 (MIPS16_DECODE): New table, for mips16 instructions.
2443 (bitmap_val): New static function.
2444 (struct mips16_op): Define.
2445 (mips16_op_table): New table, for mips16 operands.
2446 (build_mips16_operands): New static function.
2447 (process_instructions): If PC is odd, decode a mips16
2448 instruction. Break out instruction handling into new
2449 build_instruction function.
2450 (build_instruction): New static function, broken out of
2451 process_instructions. Check modifiers rather than flags for SHIFT
2452 bit count and m[ft]{hi,lo} direction.
2453 (usage): Pass program name to fprintf.
2454 (main): Remove unused variable this_option_optind. Change
2455 ``*loptarg++'' to ``loptarg++''.
2456 (my_strtoul): Parenthesize && within ||.
2457 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2458 (simulate): If PC is odd, fetch a 16 bit instruction, and
2459 increment PC by 2 rather than 4.
2460 * configure.in: Add case for mips16*-*-*.
2461 * configure: Rebuild.
2462
2463Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2464
2465 * interp.c: Allow -t to enable tracing in standalone simulator.
2466 Fix garbage output in trace file and error messages.
2467
2468Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2469
2470 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2471 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2472 * configure.in: Simplify using macros in ../common/aclocal.m4.
2473 * configure: Regenerated.
2474 * tconfig.in: New file.
2475
2476Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2477
2478 * interp.c: Fix bugs in 64-bit port.
2479 Use ansi function declarations for msvc compiler.
2480 Initialize and test file pointer in trace code.
2481 Prevent duplicate definition of LAST_EMED_REGNUM.
2482
2483Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2484
2485 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2486
2487Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2488
2489 * interp.c (SignalException): Check for explicit terminating
2490 breakpoint value.
2491 * gencode.c: Pass instruction value through SignalException()
2492 calls for Trap, Breakpoint and Syscall.
2493
2494Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2495
2496 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2497 only used on those hosts that provide it.
2498 * configure.in: Add sqrt() to list of functions to be checked for.
2499 * config.in: Re-generated.
2500 * configure: Re-generated.
2501
2502Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2503
2504 * gencode.c (process_instructions): Call build_endian_shift when
2505 expanding STORE RIGHT, to fix swr.
2506 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2507 clear the high bits.
2508 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2509 Fix float to int conversions to produce signed values.
2510
2511Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2512
2513 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2514 (process_instructions): Correct handling of nor instruction.
2515 Correct shift count for 32 bit shift instructions. Correct sign
2516 extension for arithmetic shifts to not shift the number of bits in
2517 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2518 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2519 Fix madd.
2520 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2521 It's OK to have a mult follow a mult. What's not OK is to have a
2522 mult follow an mfhi.
2523 (Convert): Comment out incorrect rounding code.
2524
2525Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2526
2527 * interp.c (sim_monitor): Improved monitor printf
2528 simulation. Tidied up simulator warnings, and added "--log" option
2529 for directing warning message output.
2530 * gencode.c: Use sim_warning() rather than WARNING macro.
2531
2532Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2533
2534 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2535 getopt1.o, rather than on gencode.c. Link objects together.
2536 Don't link against -liberty.
2537 (gencode.o, getopt.o, getopt1.o): New targets.
2538 * gencode.c: Include <ctype.h> and "ansidecl.h".
2539 (AND): Undefine after including "ansidecl.h".
2540 (ULONG_MAX): Define if not defined.
2541 (OP_*): Don't define macros; now defined in opcode/mips.h.
2542 (main): Call my_strtoul rather than strtoul.
2543 (my_strtoul): New static function.
2544
2545Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2546
2547 * gencode.c (process_instructions): Generate word64 and uword64
2548 instead of `long long' and `unsigned long long' data types.
2549 * interp.c: #include sysdep.h to get signals, and define default
2550 for SIGBUS.
2551 * (Convert): Work around for Visual-C++ compiler bug with type
2552 conversion.
2553 * support.h: Make things compile under Visual-C++ by using
2554 __int64 instead of `long long'. Change many refs to long long
2555 into word64/uword64 typedefs.
2556
2557Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2558
2559 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2560 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2561 (docdir): Removed.
2562 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2563 (AC_PROG_INSTALL): Added.
2564 (AC_PROG_CC): Moved to before configure.host call.
2565 * configure: Rebuilt.
2566
2567Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2568
2569 * configure.in: Define @SIMCONF@ depending on mips target.
2570 * configure: Rebuild.
2571 * Makefile.in (run): Add @SIMCONF@ to control simulator
2572 construction.
2573 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2574 * interp.c: Remove some debugging, provide more detailed error
2575 messages, update memory accesses to use LOADDRMASK.
2576
2577Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2578
2579 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2580 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2581 stamp-h.
2582 * configure: Rebuild.
2583 * config.in: New file, generated by autoheader.
2584 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2585 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2586 HAVE_ANINT and HAVE_AINT, as appropriate.
2587 * Makefile.in (run): Use @LIBS@ rather than -lm.
2588 (interp.o): Depend upon config.h.
2589 (Makefile): Just rebuild Makefile.
2590 (clean): Remove stamp-h.
2591 (mostlyclean): Make the same as clean, not as distclean.
2592 (config.h, stamp-h): New targets.
2593
2594Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2595
2596 * interp.c (ColdReset): Fix boolean test. Make all simulator
2597 globals static.
2598
2599Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2600
2601 * interp.c (xfer_direct_word, xfer_direct_long,
2602 swap_direct_word, swap_direct_long, xfer_big_word,
2603 xfer_big_long, xfer_little_word, xfer_little_long,
2604 swap_word,swap_long): Added.
2605 * interp.c (ColdReset): Provide function indirection to
2606 host<->simulated_target transfer routines.
2607 * interp.c (sim_store_register, sim_fetch_register): Updated to
2608 make use of indirected transfer routines.
2609
2610Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2611
2612 * gencode.c (process_instructions): Ensure FP ABS instruction
2613 recognised.
2614 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2615 system call support.
2616
2617Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2618
2619 * interp.c (sim_do_command): Complain if callback structure not
2620 initialised.
2621
2622Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2623
2624 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2625 support for Sun hosts.
2626 * Makefile.in (gencode): Ensure the host compiler and libraries
2627 used for cross-hosted build.
2628
2629Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2630
2631 * interp.c, gencode.c: Some more (TODO) tidying.
2632
2633Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2634
2635 * gencode.c, interp.c: Replaced explicit long long references with
2636 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2637 * support.h (SET64LO, SET64HI): Macros added.
2638
2639Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2640
2641 * configure: Regenerate with autoconf 2.7.
2642
2643Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2644
2645 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2646 * support.h: Remove superfluous "1" from #if.
2647 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2648
2649Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2650
2651 * interp.c (StoreFPR): Control UndefinedResult() call on
2652 WARN_RESULT manifest.
2653
2654Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2655
2656 * gencode.c: Tidied instruction decoding, and added FP instruction
2657 support.
2658
2659 * interp.c: Added dineroIII, and BSD profiling support. Also
2660 run-time FP handling.
2661
2662Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2663
2664 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2665 gencode.c, interp.c, support.h: created.
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