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Assorted compiler warning fixes
[thirdparty/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
b99bd4ef
NC		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC		 6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC		 8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC		 14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC		 19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC		 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC		 31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b
RE		 34#include "opcode/arm.h"
35
b99bd4ef
NC		 36#ifdef OBJ_ELF
37#include "elf/arm.h"
a394c00f 38#include "dw2gencfi.h"
b99bd4ef
NC		 39#endif
40
f0927246
NC		 41#include "dwarf2dbg.h"
42
7ed4c4c5
NC		 43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
c19d1205
ZW		 51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
7ed4c4c5 55 /* The segment containing the function. */
c19d1205
ZW		 56 segT saved_seg;
57 subsegT saved_subseg;
7ed4c4c5
NC		 58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
c19d1205
ZW		 60 int opcode_count;
61 int opcode_alloc;
7ed4c4c5 62 /* The number of bytes pushed to the stack. */
c19d1205 63 offsetT frame_size;
7ed4c4c5
NC		 64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
c19d1205 67 offsetT pending_offset;
7ed4c4c5 68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW		 69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
7ed4c4c5 72 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 73 unsigned fp_used:1;
7ed4c4c5 74 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 75 unsigned sp_restored:1;
7ed4c4c5
NC		 76} unwind;
77
8b1ad454
NC		 78#endif /* OBJ_ELF */
79
4962c51a
MS		 80/* Results from operand parsing worker functions. */
81
82typedef enum
83{
84 PARSE_OPERAND_SUCCESS,
85 PARSE_OPERAND_FAIL,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87} parse_operand_result;
88
33a392fb
PB		 89enum arm_float_abi
90{
91 ARM_FLOAT_ABI_HARD,
92 ARM_FLOAT_ABI_SOFTFP,
93 ARM_FLOAT_ABI_SOFT
94};
95
c19d1205 96/* Types of processor to assemble for. */
b99bd4ef 97#ifndef CPU_DEFAULT
8a59fff3 98/* The code that was here used to select a default CPU depending on compiler
fa94de6b 99 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD		 100 changing gas' default behaviour depending upon the build host.
101
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
b99bd4ef
NC		 104#endif
105
106#ifndef FPU_DEFAULT
c820d418
MM		 107# ifdef TE_LINUX
108# define FPU_DEFAULT FPU_ARCH_FPA
109# elif defined (TE_NetBSD)
110# ifdef OBJ_ELF
111# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
112# else
113 /* Legacy a.out format. */
114# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
115# endif
4e7fd91e
PB		 116# elif defined (TE_VXWORKS)
117# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM		 118# else
119 /* For backwards compatibility, default to FPA. */
120# define FPU_DEFAULT FPU_ARCH_FPA
121# endif
122#endif /* ifndef FPU_DEFAULT */
b99bd4ef 123
c19d1205 124#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 125
e74cfd16
PB		 126static arm_feature_set cpu_variant;
127static arm_feature_set arm_arch_used;
128static arm_feature_set thumb_arch_used;
b99bd4ef 129
b99bd4ef 130/* Flags stored in private area of BFD structure. */
c19d1205
ZW		 131static int uses_apcs_26 = FALSE;
132static int atpcs = FALSE;
b34976b6
AM		 133static int support_interwork = FALSE;
134static int uses_apcs_float = FALSE;
c19d1205 135static int pic_code = FALSE;
845b51d6 136static int fix_v4bx = FALSE;
278df34e
NS		 137/* Warn on using deprecated features. */
138static int warn_on_deprecated = TRUE;
139
2e6976a8
DG		 140/* Understand CodeComposer Studio assembly syntax. */
141bfd_boolean codecomposer_syntax = FALSE;
03b1477f
RE		 142
143/* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
145 assembly flags. */
e74cfd16
PB		 146static const arm_feature_set *legacy_cpu = NULL;
147static const arm_feature_set *legacy_fpu = NULL;
148
149static const arm_feature_set *mcpu_cpu_opt = NULL;
150static const arm_feature_set *mcpu_fpu_opt = NULL;
151static const arm_feature_set *march_cpu_opt = NULL;
152static const arm_feature_set *march_fpu_opt = NULL;
153static const arm_feature_set *mfpu_opt = NULL;
7a1d4c38 154static const arm_feature_set *object_arch = NULL;
e74cfd16
PB		 155
156/* Constants for known architecture features. */
157static const arm_feature_set fpu_default = FPU_DEFAULT;
158static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
5287ad62
JB		 160static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
e74cfd16
PB		 162static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166
167#ifdef CPU_DEFAULT
168static const arm_feature_set cpu_default = CPU_DEFAULT;
169#endif
170
171static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
e74cfd16 187static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
b2a5fbdc 188static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
62b3e311 189static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
9e3c6df6 190static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
7e806470
PB		 191static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
62b3e311
PB		 193static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
9e3c6df6 197static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
bca38921 198static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
7e806470 199static const arm_feature_set arm_ext_m =
b2a5fbdc 200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
60e5ef9f 201static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
f4c65163 202static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
b2a5fbdc 203static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
eea54501 204static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
90ec0d68 205static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
e74cfd16
PB		 206
207static const arm_feature_set arm_arch_any = ARM_ANY;
208static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
251665fc 211static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
e74cfd16 212
2d447fca
JM		 213static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
e74cfd16
PB		 215static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
62f3b8c8 227static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
5287ad62 228static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
b1cc4aeb
PB		 229static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
5287ad62
JB		 231static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
62f3b8c8
PB		 234static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
bca38921
MGD		 237static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
a715796b
TG		 239static const arm_feature_set fpu_vfp_ext_armv8xd =
240 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8xD);
bca38921
MGD		 241static const arm_feature_set fpu_neon_ext_armv8 =
242 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
243static const arm_feature_set fpu_crypto_ext_armv8 =
244 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
dd5181d5
KT		 245static const arm_feature_set crc_ext_armv8 =
246 ARM_FEATURE (0, CRC_EXT_ARMV8);
e74cfd16 247
33a392fb 248static int mfloat_abi_opt = -1;
e74cfd16
PB		 249/* Record user cpu selection for object attributes. */
250static arm_feature_set selected_cpu = ARM_ARCH_NONE;
ee065d83
PB		 251/* Must be long enough to hold any of the names in arm_cpus. */
252static char selected_cpu_name[16];
8d67f500 253
aacf0b33
KT		 254extern FLONUM_TYPE generic_floating_point_number;
255
8d67f500
NC		 256/* Return if no cpu was selected on command-line. */
257static bfd_boolean
258no_cpu_selected (void)
259{
260 return selected_cpu.core == arm_arch_none.core
261 && selected_cpu.coproc == arm_arch_none.coproc;
262}
263
7cc69913 264#ifdef OBJ_ELF
deeaaff8
DJ		 265# ifdef EABI_DEFAULT
266static int meabi_flags = EABI_DEFAULT;
267# else
d507cf36 268static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 269# endif
e1da3f5b 270
ee3c0378
AS		 271static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
272
e1da3f5b 273bfd_boolean
5f4273c7 274arm_is_eabi (void)
e1da3f5b
PB		 275{
276 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
277}
7cc69913 278#endif
b99bd4ef 279
b99bd4ef 280#ifdef OBJ_ELF
c19d1205 281/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC		 282symbolS * GOT_symbol;
283#endif
284
b99bd4ef
NC		 285/* 0: assemble for ARM,
286 1: assemble for Thumb,
287 2: assemble for Thumb even though target CPU does not support thumb
288 instructions. */
289static int thumb_mode = 0;
8dc2430f
NC		 290/* A value distinct from the possible values for thumb_mode that we
291 can use to record whether thumb_mode has been copied into the
292 tc_frag_data field of a frag. */
293#define MODE_RECORDED (1 << 4)
b99bd4ef 294
e07e6e58
NC		 295/* Specifies the intrinsic IT insn behavior mode. */
296enum implicit_it_mode
297{
298 IMPLICIT_IT_MODE_NEVER = 0x00,
299 IMPLICIT_IT_MODE_ARM = 0x01,
300 IMPLICIT_IT_MODE_THUMB = 0x02,
301 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
302};
303static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
304
c19d1205
ZW		 305/* If unified_syntax is true, we are processing the new unified
306 ARM/Thumb syntax. Important differences from the old ARM mode:
307
308 - Immediate operands do not require a # prefix.
309 - Conditional affixes always appear at the end of the
310 instruction. (For backward compatibility, those instructions
311 that formerly had them in the middle, continue to accept them
312 there.)
313 - The IT instruction may appear, and if it does is validated
314 against subsequent conditional affixes. It does not generate
315 machine code.
316
317 Important differences from the old Thumb mode:
318
319 - Immediate operands do not require a # prefix.
320 - Most of the V6T2 instructions are only available in unified mode.
321 - The .N and .W suffixes are recognized and honored (it is an error
322 if they cannot be honored).
323 - All instructions set the flags if and only if they have an 's' affix.
324 - Conditional affixes may be used. They are validated against
325 preceding IT instructions. Unlike ARM mode, you cannot use a
326 conditional affix except in the scope of an IT instruction. */
327
328static bfd_boolean unified_syntax = FALSE;
b99bd4ef 329
bacebabc
RM		 330/* An immediate operand can start with #, and ld*, st*, pld operands
331 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM		 332 before a [, which can appear as the first operand for pld.
333 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
334const char arm_symbol_chars[] = "#[]{}";
bacebabc 335
5287ad62
JB		 336enum neon_el_type
337{
dcbf9037 338 NT_invtype,
5287ad62
JB		 339 NT_untyped,
340 NT_integer,
341 NT_float,
342 NT_poly,
343 NT_signed,
dcbf9037 344 NT_unsigned
5287ad62
JB		 345};
346
347struct neon_type_el
348{
349 enum neon_el_type type;
350 unsigned size;
351};
352
353#define NEON_MAX_TYPE_ELS 4
354
355struct neon_type
356{
357 struct neon_type_el el[NEON_MAX_TYPE_ELS];
358 unsigned elems;
359};
360
e07e6e58
NC		 361enum it_instruction_type
362{
363 OUTSIDE_IT_INSN,
364 INSIDE_IT_INSN,
365 INSIDE_IT_LAST_INSN,
366 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 367 if inside, should be the last one. */
e07e6e58 368 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 369 i.e. BKPT and NOP. */
e07e6e58
NC		 370 IT_INSN /* The IT insn has been parsed. */
371};
372
ad6cec43
MGD		 373/* The maximum number of operands we need. */
374#define ARM_IT_MAX_OPERANDS 6
375
b99bd4ef
NC		 376struct arm_it
377{
c19d1205 378 const char * error;
b99bd4ef 379 unsigned long instruction;
c19d1205
ZW		 380 int size;
381 int size_req;
382 int cond;
037e8744
JB		 383 /* "uncond_value" is set to the value in place of the conditional field in
384 unconditional versions of the instruction, or -1 if nothing is
385 appropriate. */
386 int uncond_value;
5287ad62 387 struct neon_type vectype;
88714cb8
DG		 388 /* This does not indicate an actual NEON instruction, only that
389 the mnemonic accepts neon-style type suffixes. */
390 int is_neon;
0110f2b8
PB		 391 /* Set to the opcode if the instruction needs relaxation.
392 Zero if the instruction is not relaxed. */
393 unsigned long relax;
b99bd4ef
NC		 394 struct
395 {
396 bfd_reloc_code_real_type type;
c19d1205
ZW		 397 expressionS exp;
398 int pc_rel;
b99bd4ef 399 } reloc;
b99bd4ef 400
e07e6e58
NC		 401 enum it_instruction_type it_insn_type;
402
c19d1205
ZW		 403 struct
404 {
405 unsigned reg;
ca3f61f7 406 signed int imm;
dcbf9037 407 struct neon_type_el vectype;
ca3f61f7
NC		 408 unsigned present : 1; /* Operand present. */
409 unsigned isreg : 1; /* Operand was a register. */
410 unsigned immisreg : 1; /* .imm field is a second register. */
5287ad62
JB		 411 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
412 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 413 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB		 414 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
415 instructions. This allows us to disambiguate ARM <-> vector insns. */
416 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 417 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5287ad62 418 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
037e8744 419 unsigned issingle : 1; /* Operand is VFP single-precision register. */
ca3f61f7
NC		 420 unsigned hasreloc : 1; /* Operand has relocation suffix. */
421 unsigned writeback : 1; /* Operand has trailing ! */
422 unsigned preind : 1; /* Preindexed address. */
423 unsigned postind : 1; /* Postindexed address. */
424 unsigned negative : 1; /* Index register was negated. */
425 unsigned shifted : 1; /* Shift applied to operation. */
426 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 427 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC		 428};
429
c19d1205 430static struct arm_it inst;
b99bd4ef
NC		 431
432#define NUM_FLOAT_VALS 8
433
05d2d07e 434const char * fp_const[] =
b99bd4ef
NC		 435{
436 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
437};
438
c19d1205 439/* Number of littlenums required to hold an extended precision number. */
b99bd4ef
NC		 440#define MAX_LITTLENUMS 6
441
442LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
443
444#define FAIL (-1)
445#define SUCCESS (0)
446
447#define SUFF_S 1
448#define SUFF_D 2
449#define SUFF_E 3
450#define SUFF_P 4
451
c19d1205
ZW		 452#define CP_T_X 0x00008000
453#define CP_T_Y 0x00400000
b99bd4ef 454
c19d1205
ZW		 455#define CONDS_BIT 0x00100000
456#define LOAD_BIT 0x00100000
b99bd4ef
NC		 457
458#define DOUBLE_LOAD_FLAG 0x00000001
459
460struct asm_cond
461{
d3ce72d0 462 const char * template_name;
c921be7d 463 unsigned long value;
b99bd4ef
NC		 464};
465
c19d1205 466#define COND_ALWAYS 0xE
b99bd4ef 467
b99bd4ef
NC		 468struct asm_psr
469{
d3ce72d0 470 const char * template_name;
c921be7d 471 unsigned long field;
b99bd4ef
NC		 472};
473
62b3e311
PB		 474struct asm_barrier_opt
475{
e797f7e0
MGD		 476 const char * template_name;
477 unsigned long value;
478 const arm_feature_set arch;
62b3e311
PB		 479};
480
2d2255b5 481/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC		 482#define SPSR_BIT (1 << 22)
483
c19d1205
ZW		 484/* The individual PSR flag bits. */
485#define PSR_c (1 << 16)
486#define PSR_x (1 << 17)
487#define PSR_s (1 << 18)
488#define PSR_f (1 << 19)
b99bd4ef 489
c19d1205 490struct reloc_entry
bfae80f2 491{
c921be7d
NC		 492 char * name;
493 bfd_reloc_code_real_type reloc;
bfae80f2
RE		 494};
495
5287ad62 496enum vfp_reg_pos
bfae80f2 497{
5287ad62
JB		 498 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
499 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE		 500};
501
502enum vfp_ldstm_type
503{
504 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
505};
506
dcbf9037
JB		 507/* Bits for DEFINED field in neon_typed_alias. */
508#define NTA_HASTYPE 1
509#define NTA_HASINDEX 2
510
511struct neon_typed_alias
512{
c921be7d
NC		 513 unsigned char defined;
514 unsigned char index;
515 struct neon_type_el eltype;
dcbf9037
JB		 516};
517
c19d1205
ZW		 518/* ARM register categories. This includes coprocessor numbers and various
519 architecture extensions' registers. */
520enum arm_reg_type
bfae80f2 521{
c19d1205
ZW		 522 REG_TYPE_RN,
523 REG_TYPE_CP,
524 REG_TYPE_CN,
525 REG_TYPE_FN,
526 REG_TYPE_VFS,
527 REG_TYPE_VFD,
5287ad62 528 REG_TYPE_NQ,
037e8744 529 REG_TYPE_VFSD,
5287ad62 530 REG_TYPE_NDQ,
037e8744 531 REG_TYPE_NSDQ,
c19d1205
ZW		 532 REG_TYPE_VFC,
533 REG_TYPE_MVF,
534 REG_TYPE_MVD,
535 REG_TYPE_MVFX,
536 REG_TYPE_MVDX,
537 REG_TYPE_MVAX,
538 REG_TYPE_DSPSC,
539 REG_TYPE_MMXWR,
540 REG_TYPE_MMXWC,
541 REG_TYPE_MMXWCG,
542 REG_TYPE_XSCALE,
90ec0d68 543 REG_TYPE_RNB
bfae80f2
RE		 544};
545
dcbf9037
JB		 546/* Structure for a hash table entry for a register.
547 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
548 information which states whether a vector type or index is specified (for a
549 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE		 550struct reg_entry
551{
c921be7d 552 const char * name;
90ec0d68 553 unsigned int number;
c921be7d
NC		 554 unsigned char type;
555 unsigned char builtin;
556 struct neon_typed_alias * neon;
6c43fab6
RE		 557};
558
c19d1205 559/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 560const char * const reg_expected_msgs[] =
c19d1205
ZW		 561{
562 N_("ARM register expected"),
563 N_("bad or missing co-processor number"),
564 N_("co-processor register expected"),
565 N_("FPA register expected"),
566 N_("VFP single precision register expected"),
5287ad62
JB		 567 N_("VFP/Neon double precision register expected"),
568 N_("Neon quad precision register expected"),
037e8744 569 N_("VFP single or double precision register expected"),
5287ad62 570 N_("Neon double or quad precision register expected"),
037e8744 571 N_("VFP single, double or Neon quad precision register expected"),
c19d1205
ZW		 572 N_("VFP system register expected"),
573 N_("Maverick MVF register expected"),
574 N_("Maverick MVD register expected"),
575 N_("Maverick MVFX register expected"),
576 N_("Maverick MVDX register expected"),
577 N_("Maverick MVAX register expected"),
578 N_("Maverick DSPSC register expected"),
579 N_("iWMMXt data register expected"),
580 N_("iWMMXt control register expected"),
581 N_("iWMMXt scalar register expected"),
582 N_("XScale accumulator register expected"),
6c43fab6
RE		 583};
584
c19d1205 585/* Some well known registers that we refer to directly elsewhere. */
bd340a04 586#define REG_R12 12
c19d1205
ZW		 587#define REG_SP 13
588#define REG_LR 14
589#define REG_PC 15
404ff6b5 590
b99bd4ef
NC		 591/* ARM instructions take 4bytes in the object file, Thumb instructions
592 take 2: */
c19d1205 593#define INSN_SIZE 4
b99bd4ef
NC		 594
595struct asm_opcode
596{
597 /* Basic string to match. */
d3ce72d0 598 const char * template_name;
c19d1205
ZW		 599
600 /* Parameters to instruction. */
5be8be5d 601 unsigned int operands[8];
c19d1205
ZW		 602
603 /* Conditional tag - see opcode_lookup. */
604 unsigned int tag : 4;
b99bd4ef
NC		 605
606 /* Basic instruction code. */
c19d1205 607 unsigned int avalue : 28;
b99bd4ef 608
c19d1205
ZW		 609 /* Thumb-format instruction code. */
610 unsigned int tvalue;
b99bd4ef 611
90e4755a 612 /* Which architecture variant provides this instruction. */
c921be7d
NC		 613 const arm_feature_set * avariant;
614 const arm_feature_set * tvariant;
c19d1205
ZW		 615
616 /* Function to call to encode instruction in ARM format. */
617 void (* aencode) (void);
b99bd4ef 618
c19d1205
ZW		 619 /* Function to call to encode instruction in Thumb format. */
620 void (* tencode) (void);
b99bd4ef
NC		 621};
622
a737bd4d
NC		 623/* Defines for various bits that we will want to toggle. */
624#define INST_IMMEDIATE 0x02000000
625#define OFFSET_REG 0x02000000
c19d1205 626#define HWOFFSET_IMM 0x00400000
a737bd4d
NC		 627#define SHIFT_BY_REG 0x00000010
628#define PRE_INDEX 0x01000000
629#define INDEX_UP 0x00800000
630#define WRITE_BACK 0x00200000
631#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 632#define CPSI_MMOD 0x00020000
90e4755a 633
a737bd4d
NC		 634#define LITERAL_MASK 0xf000f000
635#define OPCODE_MASK 0xfe1fffff
636#define V4_STR_BIT 0x00000020
8335d6aa 637#define VLDR_VMOV_SAME 0x0040f000
90e4755a 638
efd81785
PB		 639#define T2_SUBS_PC_LR 0xf3de8f00
640
a737bd4d 641#define DATA_OP_SHIFT 21
90e4755a 642
ef8d22e6
PB		 643#define T2_OPCODE_MASK 0xfe1fffff
644#define T2_DATA_OP_SHIFT 21
645
6530b175
NC		 646#define A_COND_MASK 0xf0000000
647#define A_PUSH_POP_OP_MASK 0x0fff0000
648
649/* Opcodes for pushing/poping registers to/from the stack. */
650#define A1_OPCODE_PUSH 0x092d0000
651#define A2_OPCODE_PUSH 0x052d0004
652#define A2_OPCODE_POP 0x049d0004
653
a737bd4d
NC		 654/* Codes to distinguish the arithmetic instructions. */
655#define OPCODE_AND 0
656#define OPCODE_EOR 1
657#define OPCODE_SUB 2
658#define OPCODE_RSB 3
659#define OPCODE_ADD 4
660#define OPCODE_ADC 5
661#define OPCODE_SBC 6
662#define OPCODE_RSC 7
663#define OPCODE_TST 8
664#define OPCODE_TEQ 9
665#define OPCODE_CMP 10
666#define OPCODE_CMN 11
667#define OPCODE_ORR 12
668#define OPCODE_MOV 13
669#define OPCODE_BIC 14
670#define OPCODE_MVN 15
90e4755a 671
ef8d22e6
PB		 672#define T2_OPCODE_AND 0
673#define T2_OPCODE_BIC 1
674#define T2_OPCODE_ORR 2
675#define T2_OPCODE_ORN 3
676#define T2_OPCODE_EOR 4
677#define T2_OPCODE_ADD 8
678#define T2_OPCODE_ADC 10
679#define T2_OPCODE_SBC 11
680#define T2_OPCODE_SUB 13
681#define T2_OPCODE_RSB 14
682
a737bd4d
NC		 683#define T_OPCODE_MUL 0x4340
684#define T_OPCODE_TST 0x4200
685#define T_OPCODE_CMN 0x42c0
686#define T_OPCODE_NEG 0x4240
687#define T_OPCODE_MVN 0x43c0
90e4755a 688
a737bd4d
NC		 689#define T_OPCODE_ADD_R3 0x1800
690#define T_OPCODE_SUB_R3 0x1a00
691#define T_OPCODE_ADD_HI 0x4400
692#define T_OPCODE_ADD_ST 0xb000
693#define T_OPCODE_SUB_ST 0xb080
694#define T_OPCODE_ADD_SP 0xa800
695#define T_OPCODE_ADD_PC 0xa000
696#define T_OPCODE_ADD_I8 0x3000
697#define T_OPCODE_SUB_I8 0x3800
698#define T_OPCODE_ADD_I3 0x1c00
699#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 700
a737bd4d
NC		 701#define T_OPCODE_ASR_R 0x4100
702#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW		 703#define T_OPCODE_LSR_R 0x40c0
704#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC		 705#define T_OPCODE_ASR_I 0x1000
706#define T_OPCODE_LSL_I 0x0000
707#define T_OPCODE_LSR_I 0x0800
b99bd4ef 708
a737bd4d
NC		 709#define T_OPCODE_MOV_I8 0x2000
710#define T_OPCODE_CMP_I8 0x2800
711#define T_OPCODE_CMP_LR 0x4280
712#define T_OPCODE_MOV_HR 0x4600
713#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 714
a737bd4d
NC		 715#define T_OPCODE_LDR_PC 0x4800
716#define T_OPCODE_LDR_SP 0x9800
717#define T_OPCODE_STR_SP 0x9000
718#define T_OPCODE_LDR_IW 0x6800
719#define T_OPCODE_STR_IW 0x6000
720#define T_OPCODE_LDR_IH 0x8800
721#define T_OPCODE_STR_IH 0x8000
722#define T_OPCODE_LDR_IB 0x7800
723#define T_OPCODE_STR_IB 0x7000
724#define T_OPCODE_LDR_RW 0x5800
725#define T_OPCODE_STR_RW 0x5000
726#define T_OPCODE_LDR_RH 0x5a00
727#define T_OPCODE_STR_RH 0x5200
728#define T_OPCODE_LDR_RB 0x5c00
729#define T_OPCODE_STR_RB 0x5400
c9b604bd 730
a737bd4d
NC		 731#define T_OPCODE_PUSH 0xb400
732#define T_OPCODE_POP 0xbc00
b99bd4ef 733
2fc8bdac 734#define T_OPCODE_BRANCH 0xe000
b99bd4ef 735
a737bd4d 736#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 737#define THUMB_PP_PC_LR 0x0100
c19d1205 738#define THUMB_LOAD_BIT 0x0800
53365c0d 739#define THUMB2_LOAD_BIT 0x00100000
c19d1205
ZW		 740
741#define BAD_ARGS _("bad arguments to instruction")
fdfde340 742#define BAD_SP _("r13 not allowed here")
c19d1205
ZW		 743#define BAD_PC _("r15 not allowed here")
744#define BAD_COND _("instruction cannot be conditional")
745#define BAD_OVERLAP _("registers may not be the same")
746#define BAD_HIREG _("lo register required")
747#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
01cfc07f 748#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
dfa9f0d5
PB		 749#define BAD_BRANCH _("branch must be last instruction in IT block")
750#define BAD_NOT_IT _("instruction not allowed in IT block")
037e8744 751#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58
NC		 752#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
753#define BAD_IT_COND _("incorrect condition in IT block")
754#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 755#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG		 756#define BAD_PC_ADDRESSING \
757 _("cannot use register index with PC-relative addressing")
758#define BAD_PC_WRITEBACK \
759 _("cannot use writeback with PC-relative addressing")
08f10d51 760#define BAD_RANGE _("branch out of range")
dd5181d5 761#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
c19d1205 762
c921be7d
NC		 763static struct hash_control * arm_ops_hsh;
764static struct hash_control * arm_cond_hsh;
765static struct hash_control * arm_shift_hsh;
766static struct hash_control * arm_psr_hsh;
767static struct hash_control * arm_v7m_psr_hsh;
768static struct hash_control * arm_reg_hsh;
769static struct hash_control * arm_reloc_hsh;
770static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 771
b99bd4ef
NC		 772/* Stuff needed to resolve the label ambiguity
773 As:
774 ...
775 label: <insn>
776 may differ from:
777 ...
778 label:
5f4273c7 779 <insn> */
b99bd4ef
NC		 780
781symbolS * last_label_seen;
b34976b6 782static int label_is_thumb_function_name = FALSE;
e07e6e58 783
3d0c9500
NC		 784/* Literal pool structure. Held on a per-section
785 and per-sub-section basis. */
a737bd4d 786
c19d1205 787#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 788typedef struct literal_pool
b99bd4ef 789{
c921be7d
NC		 790 expressionS literals [MAX_LITERAL_POOL_SIZE];
791 unsigned int next_free_entry;
792 unsigned int id;
793 symbolS * symbol;
794 segT section;
795 subsegT sub_section;
a8040cf2
NC		 796#ifdef OBJ_ELF
797 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
798#endif
c921be7d 799 struct literal_pool * next;
8335d6aa 800 unsigned int alignment;
3d0c9500 801} literal_pool;
b99bd4ef 802
3d0c9500
NC		 803/* Pointer to a linked list of literal pools. */
804literal_pool * list_of_pools = NULL;
e27ec89e 805
2e6976a8
DG		 806typedef enum asmfunc_states
807{
808 OUTSIDE_ASMFUNC,
809 WAITING_ASMFUNC_NAME,
810 WAITING_ENDASMFUNC
811} asmfunc_states;
812
813static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
814
e07e6e58
NC		 815#ifdef OBJ_ELF
816# define now_it seg_info (now_seg)->tc_segment_info_data.current_it
817#else
818static struct current_it now_it;
819#endif
820
821static inline int
822now_it_compatible (int cond)
823{
824 return (cond & ~1) == (now_it.cc & ~1);
825}
826
827static inline int
828conditional_insn (void)
829{
830 return inst.cond != COND_ALWAYS;
831}
832
833static int in_it_block (void);
834
835static int handle_it_state (void);
836
837static void force_automatic_it_block_close (void);
838
c921be7d
NC		 839static void it_fsm_post_encode (void);
840
e07e6e58
NC		 841#define set_it_insn_type(type) \
842 do \
843 { \
844 inst.it_insn_type = type; \
845 if (handle_it_state () == FAIL) \
477330fc 846 return; \
e07e6e58
NC		 847 } \
848 while (0)
849
c921be7d
NC		 850#define set_it_insn_type_nonvoid(type, failret) \
851 do \
852 { \
853 inst.it_insn_type = type; \
854 if (handle_it_state () == FAIL) \
477330fc 855 return failret; \
c921be7d
NC		 856 } \
857 while(0)
858
e07e6e58
NC		 859#define set_it_insn_type_last() \
860 do \
861 { \
862 if (inst.cond == COND_ALWAYS) \
477330fc 863 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 864 else \
477330fc 865 set_it_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC		 866 } \
867 while (0)
868
c19d1205 869/* Pure syntax. */
b99bd4ef 870
c19d1205
ZW		 871/* This array holds the chars that always start a comment. If the
872 pre-processor is disabled, these aren't very useful. */
2e6976a8 873char arm_comment_chars[] = "@";
3d0c9500 874
c19d1205
ZW		 875/* This array holds the chars that only start a comment at the beginning of
876 a line. If the line seems to have the form '# 123 filename'
877 .line and .file directives will appear in the pre-processed output. */
878/* Note that input_file.c hand checks for '#' at the beginning of the
879 first line of the input file. This is because the compiler outputs
880 #NO_APP at the beginning of its output. */
881/* Also note that comments like this one will always work. */
882const char line_comment_chars[] = "#";
3d0c9500 883
2e6976a8 884char arm_line_separator_chars[] = ";";
b99bd4ef 885
c19d1205
ZW		 886/* Chars that can be used to separate mant
887 from exp in floating point numbers. */
888const char EXP_CHARS[] = "eE";
3d0c9500 889
c19d1205
ZW		 890/* Chars that mean this number is a floating point constant. */
891/* As in 0f12.456 */
892/* or 0d1.2345e12 */
b99bd4ef 893
c19d1205 894const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 895
c19d1205
ZW		 896/* Prefix characters that indicate the start of an immediate
897 value. */
898#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 899
c19d1205
ZW		 900/* Separator character handling. */
901
902#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
903
904static inline int
905skip_past_char (char ** str, char c)
906{
8ab8155f
NC		 907 /* PR gas/14987: Allow for whitespace before the expected character. */
908 skip_whitespace (*str);
427d0db6 909
c19d1205
ZW		 910 if (**str == c)
911 {
912 (*str)++;
913 return SUCCESS;
3d0c9500 914 }
c19d1205
ZW		 915 else
916 return FAIL;
917}
c921be7d 918
c19d1205 919#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 920
c19d1205
ZW		 921/* Arithmetic expressions (possibly involving symbols). */
922
923/* Return TRUE if anything in the expression is a bignum. */
924
925static int
926walk_no_bignums (symbolS * sp)
927{
928 if (symbol_get_value_expression (sp)->X_op == O_big)
929 return 1;
930
931 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 932 {
c19d1205
ZW		 933 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
934 || (symbol_get_value_expression (sp)->X_op_symbol
935 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC		 936 }
937
c19d1205 938 return 0;
3d0c9500
NC		 939}
940
c19d1205
ZW		 941static int in_my_get_expression = 0;
942
943/* Third argument to my_get_expression. */
944#define GE_NO_PREFIX 0
945#define GE_IMM_PREFIX 1
946#define GE_OPT_PREFIX 2
5287ad62
JB		 947/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
948 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
949#define GE_OPT_PREFIX_BIG 3
a737bd4d 950
b99bd4ef 951static int
c19d1205 952my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 953{
c19d1205
ZW		 954 char * save_in;
955 segT seg;
b99bd4ef 956
c19d1205
ZW		 957 /* In unified syntax, all prefixes are optional. */
958 if (unified_syntax)
5287ad62 959 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 960 : GE_OPT_PREFIX;
b99bd4ef 961
c19d1205 962 switch (prefix_mode)
b99bd4ef 963 {
c19d1205
ZW		 964 case GE_NO_PREFIX: break;
965 case GE_IMM_PREFIX:
966 if (!is_immediate_prefix (**str))
967 {
968 inst.error = _("immediate expression requires a # prefix");
969 return FAIL;
970 }
971 (*str)++;
972 break;
973 case GE_OPT_PREFIX:
5287ad62 974 case GE_OPT_PREFIX_BIG:
c19d1205
ZW		 975 if (is_immediate_prefix (**str))
976 (*str)++;
977 break;
978 default: abort ();
979 }
b99bd4ef 980
c19d1205 981 memset (ep, 0, sizeof (expressionS));
b99bd4ef 982
c19d1205
ZW		 983 save_in = input_line_pointer;
984 input_line_pointer = *str;
985 in_my_get_expression = 1;
986 seg = expression (ep);
987 in_my_get_expression = 0;
988
f86adc07 989 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 990 {
f86adc07 991 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW		 992 *str = input_line_pointer;
993 input_line_pointer = save_in;
994 if (inst.error == NULL)
f86adc07
NS		 995 inst.error = (ep->X_op == O_absent
996 ? _("missing expression") :_("bad expression"));
c19d1205
ZW		 997 return 1;
998 }
b99bd4ef 999
c19d1205
ZW		 1000#ifdef OBJ_AOUT
1001 if (seg != absolute_section
1002 && seg != text_section
1003 && seg != data_section
1004 && seg != bss_section
1005 && seg != undefined_section)
1006 {
1007 inst.error = _("bad segment");
1008 *str = input_line_pointer;
1009 input_line_pointer = save_in;
1010 return 1;
b99bd4ef 1011 }
87975d2a
AM		 1012#else
1013 (void) seg;
c19d1205 1014#endif
b99bd4ef 1015
c19d1205
ZW		 1016 /* Get rid of any bignums now, so that we don't generate an error for which
1017 we can't establish a line number later on. Big numbers are never valid
1018 in instructions, which is where this routine is always called. */
5287ad62
JB		 1019 if (prefix_mode != GE_OPT_PREFIX_BIG
1020 && (ep->X_op == O_big
477330fc 1021 || (ep->X_add_symbol
5287ad62 1022 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1023 || (ep->X_op_symbol
5287ad62 1024 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW		 1025 {
1026 inst.error = _("invalid constant");
1027 *str = input_line_pointer;
1028 input_line_pointer = save_in;
1029 return 1;
1030 }
b99bd4ef 1031
c19d1205
ZW		 1032 *str = input_line_pointer;
1033 input_line_pointer = save_in;
1034 return 0;
b99bd4ef
NC		 1035}
1036
c19d1205
ZW		 1037/* Turn a string in input_line_pointer into a floating point constant
1038 of type TYPE, and store the appropriate bytes in *LITP. The number
1039 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1040 returned, or NULL on OK.
b99bd4ef 1041
c19d1205
ZW		 1042 Note that fp constants aren't represent in the normal way on the ARM.
1043 In big endian mode, things are as expected. However, in little endian
1044 mode fp constants are big-endian word-wise, and little-endian byte-wise
1045 within the words. For example, (double) 1.1 in big endian mode is
1046 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1047 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1048
c19d1205 1049 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1050
c19d1205
ZW		 1051char *
1052md_atof (int type, char * litP, int * sizeP)
1053{
1054 int prec;
1055 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1056 char *t;
1057 int i;
b99bd4ef 1058
c19d1205
ZW		 1059 switch (type)
1060 {
1061 case 'f':
1062 case 'F':
1063 case 's':
1064 case 'S':
1065 prec = 2;
1066 break;
b99bd4ef 1067
c19d1205
ZW		 1068 case 'd':
1069 case 'D':
1070 case 'r':
1071 case 'R':
1072 prec = 4;
1073 break;
b99bd4ef 1074
c19d1205
ZW		 1075 case 'x':
1076 case 'X':
499ac353 1077 prec = 5;
c19d1205 1078 break;
b99bd4ef 1079
c19d1205
ZW		 1080 case 'p':
1081 case 'P':
499ac353 1082 prec = 5;
c19d1205 1083 break;
a737bd4d 1084
c19d1205
ZW		 1085 default:
1086 *sizeP = 0;
499ac353 1087 return _("Unrecognized or unsupported floating point constant");
c19d1205 1088 }
b99bd4ef 1089
c19d1205
ZW		 1090 t = atof_ieee (input_line_pointer, type, words);
1091 if (t)
1092 input_line_pointer = t;
499ac353 1093 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1094
c19d1205
ZW		 1095 if (target_big_endian)
1096 {
1097 for (i = 0; i < prec; i++)
1098 {
499ac353
NC		 1099 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1100 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1101 }
1102 }
1103 else
1104 {
e74cfd16 1105 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
c19d1205
ZW		 1106 for (i = prec - 1; i >= 0; i--)
1107 {
499ac353
NC		 1108 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1109 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1110 }
1111 else
1112 /* For a 4 byte float the order of elements in `words' is 1 0.
1113 For an 8 byte float the order is 1 0 3 2. */
1114 for (i = 0; i < prec; i += 2)
1115 {
499ac353
NC		 1116 md_number_to_chars (litP, (valueT) words[i + 1],
1117 sizeof (LITTLENUM_TYPE));
1118 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1119 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1120 litP += 2 * sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1121 }
1122 }
b99bd4ef 1123
499ac353 1124 return NULL;
c19d1205 1125}
b99bd4ef 1126
c19d1205
ZW		 1127/* We handle all bad expressions here, so that we can report the faulty
1128 instruction in the error message. */
1129void
91d6fa6a 1130md_operand (expressionS * exp)
c19d1205
ZW		 1131{
1132 if (in_my_get_expression)
91d6fa6a 1133 exp->X_op = O_illegal;
b99bd4ef
NC		 1134}
1135
c19d1205 1136/* Immediate values. */
b99bd4ef 1137
c19d1205
ZW		 1138/* Generic immediate-value read function for use in directives.
1139 Accepts anything that 'expression' can fold to a constant.
1140 *val receives the number. */
1141#ifdef OBJ_ELF
1142static int
1143immediate_for_directive (int *val)
b99bd4ef 1144{
c19d1205
ZW		 1145 expressionS exp;
1146 exp.X_op = O_illegal;
b99bd4ef 1147
c19d1205
ZW		 1148 if (is_immediate_prefix (*input_line_pointer))
1149 {
1150 input_line_pointer++;
1151 expression (&exp);
1152 }
b99bd4ef 1153
c19d1205
ZW		 1154 if (exp.X_op != O_constant)
1155 {
1156 as_bad (_("expected #constant"));
1157 ignore_rest_of_line ();
1158 return FAIL;
1159 }
1160 *val = exp.X_add_number;
1161 return SUCCESS;
b99bd4ef 1162}
c19d1205 1163#endif
b99bd4ef 1164
c19d1205 1165/* Register parsing. */
b99bd4ef 1166
c19d1205
ZW		 1167/* Generic register parser. CCP points to what should be the
1168 beginning of a register name. If it is indeed a valid register
1169 name, advance CCP over it and return the reg_entry structure;
1170 otherwise return NULL. Does not issue diagnostics. */
1171
1172static struct reg_entry *
1173arm_reg_parse_multi (char **ccp)
b99bd4ef 1174{
c19d1205
ZW		 1175 char *start = *ccp;
1176 char *p;
1177 struct reg_entry *reg;
b99bd4ef 1178
477330fc
RM		 1179 skip_whitespace (start);
1180
c19d1205
ZW		 1181#ifdef REGISTER_PREFIX
1182 if (*start != REGISTER_PREFIX)
01cfc07f 1183 return NULL;
c19d1205
ZW		 1184 start++;
1185#endif
1186#ifdef OPTIONAL_REGISTER_PREFIX
1187 if (*start == OPTIONAL_REGISTER_PREFIX)
1188 start++;
1189#endif
b99bd4ef 1190
c19d1205
ZW		 1191 p = start;
1192 if (!ISALPHA (*p) || !is_name_beginner (*p))
1193 return NULL;
b99bd4ef 1194
c19d1205
ZW		 1195 do
1196 p++;
1197 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1198
1199 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1200
1201 if (!reg)
1202 return NULL;
1203
1204 *ccp = p;
1205 return reg;
b99bd4ef
NC		 1206}
1207
1208static int
dcbf9037 1209arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1210 enum arm_reg_type type)
b99bd4ef 1211{
c19d1205
ZW		 1212 /* Alternative syntaxes are accepted for a few register classes. */
1213 switch (type)
1214 {
1215 case REG_TYPE_MVF:
1216 case REG_TYPE_MVD:
1217 case REG_TYPE_MVFX:
1218 case REG_TYPE_MVDX:
1219 /* Generic coprocessor register names are allowed for these. */
79134647 1220 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW		 1221 return reg->number;
1222 break;
69b97547 1223
c19d1205
ZW		 1224 case REG_TYPE_CP:
1225 /* For backward compatibility, a bare number is valid here. */
1226 {
1227 unsigned long processor = strtoul (start, ccp, 10);
1228 if (*ccp != start && processor <= 15)
1229 return processor;
1230 }
6057a28f 1231
c19d1205
ZW		 1232 case REG_TYPE_MMXWC:
1233 /* WC includes WCG. ??? I'm not sure this is true for all
1234 instructions that take WC registers. */
79134647 1235 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1236 return reg->number;
6057a28f 1237 break;
c19d1205 1238
6057a28f 1239 default:
c19d1205 1240 break;
6057a28f
NC		 1241 }
1242
dcbf9037
JB		 1243 return FAIL;
1244}
1245
1246/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1247 return value is the register number or FAIL. */
1248
1249static int
1250arm_reg_parse (char **ccp, enum arm_reg_type type)
1251{
1252 char *start = *ccp;
1253 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1254 int ret;
1255
1256 /* Do not allow a scalar (reg+index) to parse as a register. */
1257 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1258 return FAIL;
1259
1260 if (reg && reg->type == type)
1261 return reg->number;
1262
1263 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1264 return ret;
1265
c19d1205
ZW		 1266 *ccp = start;
1267 return FAIL;
1268}
69b97547 1269
dcbf9037
JB		 1270/* Parse a Neon type specifier. *STR should point at the leading '.'
1271 character. Does no verification at this stage that the type fits the opcode
1272 properly. E.g.,
1273
1274 .i32.i32.s16
1275 .s32.f32
1276 .u16
1277
1278 Can all be legally parsed by this function.
1279
1280 Fills in neon_type struct pointer with parsed information, and updates STR
1281 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1282 type, FAIL if not. */
1283
1284static int
1285parse_neon_type (struct neon_type *type, char **str)
1286{
1287 char *ptr = *str;
1288
1289 if (type)
1290 type->elems = 0;
1291
1292 while (type->elems < NEON_MAX_TYPE_ELS)
1293 {
1294 enum neon_el_type thistype = NT_untyped;
1295 unsigned thissize = -1u;
1296
1297 if (*ptr != '.')
1298 break;
1299
1300 ptr++;
1301
1302 /* Just a size without an explicit type. */
1303 if (ISDIGIT (*ptr))
1304 goto parsesize;
1305
1306 switch (TOLOWER (*ptr))
1307 {
1308 case 'i': thistype = NT_integer; break;
1309 case 'f': thistype = NT_float; break;
1310 case 'p': thistype = NT_poly; break;
1311 case 's': thistype = NT_signed; break;
1312 case 'u': thistype = NT_unsigned; break;
477330fc
RM		 1313 case 'd':
1314 thistype = NT_float;
1315 thissize = 64;
1316 ptr++;
1317 goto done;
dcbf9037
JB		 1318 default:
1319 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1320 return FAIL;
1321 }
1322
1323 ptr++;
1324
1325 /* .f is an abbreviation for .f32. */
1326 if (thistype == NT_float && !ISDIGIT (*ptr))
1327 thissize = 32;
1328 else
1329 {
1330 parsesize:
1331 thissize = strtoul (ptr, &ptr, 10);
1332
1333 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM		 1334 && thissize != 64)
1335 {
1336 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB		 1337 return FAIL;
1338 }
1339 }
1340
037e8744 1341 done:
dcbf9037 1342 if (type)
477330fc
RM		 1343 {
1344 type->el[type->elems].type = thistype;
dcbf9037
JB		 1345 type->el[type->elems].size = thissize;
1346 type->elems++;
1347 }
1348 }
1349
1350 /* Empty/missing type is not a successful parse. */
1351 if (type->elems == 0)
1352 return FAIL;
1353
1354 *str = ptr;
1355
1356 return SUCCESS;
1357}
1358
1359/* Errors may be set multiple times during parsing or bit encoding
1360 (particularly in the Neon bits), but usually the earliest error which is set
1361 will be the most meaningful. Avoid overwriting it with later (cascading)
1362 errors by calling this function. */
1363
1364static void
1365first_error (const char *err)
1366{
1367 if (!inst.error)
1368 inst.error = err;
1369}
1370
1371/* Parse a single type, e.g. ".s32", leading period included. */
1372static int
1373parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1374{
1375 char *str = *ccp;
1376 struct neon_type optype;
1377
1378 if (*str == '.')
1379 {
1380 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM		 1381 {
1382 if (optype.elems == 1)
1383 *vectype = optype.el[0];
1384 else
1385 {
1386 first_error (_("only one type should be specified for operand"));
1387 return FAIL;
1388 }
1389 }
dcbf9037 1390 else
477330fc
RM		 1391 {
1392 first_error (_("vector type expected"));
1393 return FAIL;
1394 }
dcbf9037
JB		 1395 }
1396 else
1397 return FAIL;
5f4273c7 1398
dcbf9037 1399 *ccp = str;
5f4273c7 1400
dcbf9037
JB		 1401 return SUCCESS;
1402}
1403
1404/* Special meanings for indices (which have a range of 0-7), which will fit into
1405 a 4-bit integer. */
1406
1407#define NEON_ALL_LANES 15
1408#define NEON_INTERLEAVE_LANES 14
1409
1410/* Parse either a register or a scalar, with an optional type. Return the
1411 register number, and optionally fill in the actual type of the register
1412 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1413 type/index information in *TYPEINFO. */
1414
1415static int
1416parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM		 1417 enum arm_reg_type *rtype,
1418 struct neon_typed_alias *typeinfo)
dcbf9037
JB		 1419{
1420 char *str = *ccp;
1421 struct reg_entry *reg = arm_reg_parse_multi (&str);
1422 struct neon_typed_alias atype;
1423 struct neon_type_el parsetype;
1424
1425 atype.defined = 0;
1426 atype.index = -1;
1427 atype.eltype.type = NT_invtype;
1428 atype.eltype.size = -1;
1429
1430 /* Try alternate syntax for some types of register. Note these are mutually
1431 exclusive with the Neon syntax extensions. */
1432 if (reg == NULL)
1433 {
1434 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1435 if (altreg != FAIL)
477330fc 1436 *ccp = str;
dcbf9037 1437 if (typeinfo)
477330fc 1438 *typeinfo = atype;
dcbf9037
JB		 1439 return altreg;
1440 }
1441
037e8744
JB		 1442 /* Undo polymorphism when a set of register types may be accepted. */
1443 if ((type == REG_TYPE_NDQ
1444 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1445 || (type == REG_TYPE_VFSD
477330fc 1446 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1447 || (type == REG_TYPE_NSDQ
477330fc
RM		 1448 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1449 || reg->type == REG_TYPE_NQ))
f512f76f
NC		 1450 || (type == REG_TYPE_MMXWC
1451 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1452 type = (enum arm_reg_type) reg->type;
dcbf9037
JB		 1453
1454 if (type != reg->type)
1455 return FAIL;
1456
1457 if (reg->neon)
1458 atype = *reg->neon;
5f4273c7 1459
dcbf9037
JB		 1460 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1461 {
1462 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM		 1463 {
1464 first_error (_("can't redefine type for operand"));
1465 return FAIL;
1466 }
dcbf9037
JB		 1467 atype.defined |= NTA_HASTYPE;
1468 atype.eltype = parsetype;
1469 }
5f4273c7 1470
dcbf9037
JB		 1471 if (skip_past_char (&str, '[') == SUCCESS)
1472 {
1473 if (type != REG_TYPE_VFD)
477330fc
RM		 1474 {
1475 first_error (_("only D registers may be indexed"));
1476 return FAIL;
1477 }
5f4273c7 1478
dcbf9037 1479 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 1480 {
1481 first_error (_("can't change index for operand"));
1482 return FAIL;
1483 }
dcbf9037
JB		 1484
1485 atype.defined |= NTA_HASINDEX;
1486
1487 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1488 atype.index = NEON_ALL_LANES;
dcbf9037 1489 else
477330fc
RM		 1490 {
1491 expressionS exp;
dcbf9037 1492
477330fc 1493 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1494
477330fc
RM		 1495 if (exp.X_op != O_constant)
1496 {
1497 first_error (_("constant expression required"));
1498 return FAIL;
1499 }
dcbf9037 1500
477330fc
RM		 1501 if (skip_past_char (&str, ']') == FAIL)
1502 return FAIL;
dcbf9037 1503
477330fc
RM		 1504 atype.index = exp.X_add_number;
1505 }
dcbf9037 1506 }
5f4273c7 1507
dcbf9037
JB		 1508 if (typeinfo)
1509 *typeinfo = atype;
5f4273c7 1510
dcbf9037
JB		 1511 if (rtype)
1512 *rtype = type;
5f4273c7 1513
dcbf9037 1514 *ccp = str;
5f4273c7 1515
dcbf9037
JB		 1516 return reg->number;
1517}
1518
1519/* Like arm_reg_parse, but allow allow the following extra features:
1520 - If RTYPE is non-zero, return the (possibly restricted) type of the
1521 register (e.g. Neon double or quad reg when either has been requested).
1522 - If this is a Neon vector type with additional type information, fill
1523 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1524 This function will fault on encountering a scalar. */
dcbf9037
JB		 1525
1526static int
1527arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1528 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB		 1529{
1530 struct neon_typed_alias atype;
1531 char *str = *ccp;
1532 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1533
1534 if (reg == FAIL)
1535 return FAIL;
1536
0855e32b
NS		 1537 /* Do not allow regname(... to parse as a register. */
1538 if (*str == '(')
1539 return FAIL;
1540
dcbf9037
JB		 1541 /* Do not allow a scalar (reg+index) to parse as a register. */
1542 if ((atype.defined & NTA_HASINDEX) != 0)
1543 {
1544 first_error (_("register operand expected, but got scalar"));
1545 return FAIL;
1546 }
1547
1548 if (vectype)
1549 *vectype = atype.eltype;
1550
1551 *ccp = str;
1552
1553 return reg;
1554}
1555
1556#define NEON_SCALAR_REG(X) ((X) >> 4)
1557#define NEON_SCALAR_INDEX(X) ((X) & 15)
1558
5287ad62
JB		 1559/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1560 have enough information to be able to do a good job bounds-checking. So, we
1561 just do easy checks here, and do further checks later. */
1562
1563static int
dcbf9037 1564parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
5287ad62 1565{
dcbf9037 1566 int reg;
5287ad62 1567 char *str = *ccp;
dcbf9037 1568 struct neon_typed_alias atype;
5f4273c7 1569
dcbf9037 1570 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
5f4273c7 1571
dcbf9037 1572 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1573 return FAIL;
5f4273c7 1574
dcbf9037 1575 if (atype.index == NEON_ALL_LANES)
5287ad62 1576 {
dcbf9037 1577 first_error (_("scalar must have an index"));
5287ad62
JB		 1578 return FAIL;
1579 }
dcbf9037 1580 else if (atype.index >= 64 / elsize)
5287ad62 1581 {
dcbf9037 1582 first_error (_("scalar index out of range"));
5287ad62
JB		 1583 return FAIL;
1584 }
5f4273c7 1585
dcbf9037
JB		 1586 if (type)
1587 *type = atype.eltype;
5f4273c7 1588
5287ad62 1589 *ccp = str;
5f4273c7 1590
dcbf9037 1591 return reg * 16 + atype.index;
5287ad62
JB		 1592}
1593
c19d1205 1594/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1595
c19d1205
ZW		 1596static long
1597parse_reg_list (char ** strp)
1598{
1599 char * str = * strp;
1600 long range = 0;
1601 int another_range;
a737bd4d 1602
c19d1205
ZW		 1603 /* We come back here if we get ranges concatenated by '+' or '|'. */
1604 do
6057a28f 1605 {
477330fc
RM		 1606 skip_whitespace (str);
1607
c19d1205 1608 another_range = 0;
a737bd4d 1609
c19d1205
ZW		 1610 if (*str == '{')
1611 {
1612 int in_range = 0;
1613 int cur_reg = -1;
a737bd4d 1614
c19d1205
ZW		 1615 str++;
1616 do
1617 {
1618 int reg;
6057a28f 1619
dcbf9037 1620 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
c19d1205 1621 {
dcbf9037 1622 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
c19d1205
ZW		 1623 return FAIL;
1624 }
a737bd4d 1625
c19d1205
ZW		 1626 if (in_range)
1627 {
1628 int i;
a737bd4d 1629
c19d1205
ZW		 1630 if (reg <= cur_reg)
1631 {
dcbf9037 1632 first_error (_("bad range in register list"));
c19d1205
ZW		 1633 return FAIL;
1634 }
40a18ebd 1635
c19d1205
ZW		 1636 for (i = cur_reg + 1; i < reg; i++)
1637 {
1638 if (range & (1 << i))
1639 as_tsktsk
1640 (_("Warning: duplicated register (r%d) in register list"),
1641 i);
1642 else
1643 range |= 1 << i;
1644 }
1645 in_range = 0;
1646 }
a737bd4d 1647
c19d1205
ZW		 1648 if (range & (1 << reg))
1649 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1650 reg);
1651 else if (reg <= cur_reg)
1652 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1653
c19d1205
ZW		 1654 range |= 1 << reg;
1655 cur_reg = reg;
1656 }
1657 while (skip_past_comma (&str) != FAIL
1658 || (in_range = 1, *str++ == '-'));
1659 str--;
a737bd4d 1660
d996d970 1661 if (skip_past_char (&str, '}') == FAIL)
c19d1205 1662 {
dcbf9037 1663 first_error (_("missing `}'"));
c19d1205
ZW		 1664 return FAIL;
1665 }
1666 }
1667 else
1668 {
91d6fa6a 1669 expressionS exp;
40a18ebd 1670
91d6fa6a 1671 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1672 return FAIL;
40a18ebd 1673
91d6fa6a 1674 if (exp.X_op == O_constant)
c19d1205 1675 {
91d6fa6a
NC		 1676 if (exp.X_add_number
1677 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW		 1678 {
1679 inst.error = _("invalid register mask");
1680 return FAIL;
1681 }
a737bd4d 1682
91d6fa6a 1683 if ((range & exp.X_add_number) != 0)
c19d1205 1684 {
91d6fa6a 1685 int regno = range & exp.X_add_number;
a737bd4d 1686
c19d1205
ZW		 1687 regno &= -regno;
1688 regno = (1 << regno) - 1;
1689 as_tsktsk
1690 (_("Warning: duplicated register (r%d) in register list"),
1691 regno);
1692 }
a737bd4d 1693
91d6fa6a 1694 range |= exp.X_add_number;
c19d1205
ZW		 1695 }
1696 else
1697 {
1698 if (inst.reloc.type != 0)
1699 {
1700 inst.error = _("expression too complex");
1701 return FAIL;
1702 }
a737bd4d 1703
91d6fa6a 1704 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
c19d1205
ZW		 1705 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1706 inst.reloc.pc_rel = 0;
1707 }
1708 }
a737bd4d 1709
c19d1205
ZW		 1710 if (*str == '|' || *str == '+')
1711 {
1712 str++;
1713 another_range = 1;
1714 }
a737bd4d 1715 }
c19d1205 1716 while (another_range);
a737bd4d 1717
c19d1205
ZW		 1718 *strp = str;
1719 return range;
a737bd4d
NC		 1720}
1721
5287ad62
JB		 1722/* Types of registers in a list. */
1723
1724enum reg_list_els
1725{
1726 REGLIST_VFP_S,
1727 REGLIST_VFP_D,
1728 REGLIST_NEON_D
1729};
1730
c19d1205
ZW		 1731/* Parse a VFP register list. If the string is invalid return FAIL.
1732 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB		 1733 register. Parses registers of type ETYPE.
1734 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1735 - Q registers can be used to specify pairs of D registers
1736 - { } can be omitted from around a singleton register list
477330fc
RM		 1737 FIXME: This is not implemented, as it would require backtracking in
1738 some cases, e.g.:
1739 vtbl.8 d3,d4,d5
1740 This could be done (the meaning isn't really ambiguous), but doesn't
1741 fit in well with the current parsing framework.
dcbf9037
JB		 1742 - 32 D registers may be used (also true for VFPv3).
1743 FIXME: Types are ignored in these register lists, which is probably a
1744 bug. */
6057a28f 1745
c19d1205 1746static int
037e8744 1747parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
6057a28f 1748{
037e8744 1749 char *str = *ccp;
c19d1205
ZW		 1750 int base_reg;
1751 int new_base;
21d799b5 1752 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 1753 int max_regs = 0;
c19d1205
ZW		 1754 int count = 0;
1755 int warned = 0;
1756 unsigned long mask = 0;
a737bd4d 1757 int i;
6057a28f 1758
477330fc 1759 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB		 1760 {
1761 inst.error = _("expecting {");
1762 return FAIL;
1763 }
6057a28f 1764
5287ad62 1765 switch (etype)
c19d1205 1766 {
5287ad62 1767 case REGLIST_VFP_S:
c19d1205
ZW		 1768 regtype = REG_TYPE_VFS;
1769 max_regs = 32;
5287ad62 1770 break;
5f4273c7 1771
5287ad62
JB		 1772 case REGLIST_VFP_D:
1773 regtype = REG_TYPE_VFD;
b7fc2769 1774 break;
5f4273c7 1775
b7fc2769
JB		 1776 case REGLIST_NEON_D:
1777 regtype = REG_TYPE_NDQ;
1778 break;
1779 }
1780
1781 if (etype != REGLIST_VFP_S)
1782 {
b1cc4aeb
PB		 1783 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1784 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 1785 {
1786 max_regs = 32;
1787 if (thumb_mode)
1788 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1789 fpu_vfp_ext_d32);
1790 else
1791 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1792 fpu_vfp_ext_d32);
1793 }
5287ad62 1794 else
477330fc 1795 max_regs = 16;
c19d1205 1796 }
6057a28f 1797
c19d1205 1798 base_reg = max_regs;
a737bd4d 1799
c19d1205
ZW		 1800 do
1801 {
5287ad62 1802 int setmask = 1, addregs = 1;
dcbf9037 1803
037e8744 1804 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 1805
c19d1205 1806 if (new_base == FAIL)
a737bd4d 1807 {
dcbf9037 1808 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW		 1809 return FAIL;
1810 }
5f4273c7 1811
b7fc2769 1812 if (new_base >= max_regs)
477330fc
RM		 1813 {
1814 first_error (_("register out of range in list"));
1815 return FAIL;
1816 }
5f4273c7 1817
5287ad62
JB		 1818 /* Note: a value of 2 * n is returned for the register Q<n>. */
1819 if (regtype == REG_TYPE_NQ)
477330fc
RM		 1820 {
1821 setmask = 3;
1822 addregs = 2;
1823 }
5287ad62 1824
c19d1205
ZW		 1825 if (new_base < base_reg)
1826 base_reg = new_base;
a737bd4d 1827
5287ad62 1828 if (mask & (setmask << new_base))
c19d1205 1829 {
dcbf9037 1830 first_error (_("invalid register list"));
c19d1205 1831 return FAIL;
a737bd4d 1832 }
a737bd4d 1833
c19d1205
ZW		 1834 if ((mask >> new_base) != 0 && ! warned)
1835 {
1836 as_tsktsk (_("register list not in ascending order"));
1837 warned = 1;
1838 }
0bbf2aa4 1839
5287ad62
JB		 1840 mask |= setmask << new_base;
1841 count += addregs;
0bbf2aa4 1842
037e8744 1843 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW		 1844 {
1845 int high_range;
0bbf2aa4 1846
037e8744 1847 str++;
0bbf2aa4 1848
037e8744 1849 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 1850 == FAIL)
c19d1205
ZW		 1851 {
1852 inst.error = gettext (reg_expected_msgs[regtype]);
1853 return FAIL;
1854 }
0bbf2aa4 1855
477330fc
RM		 1856 if (high_range >= max_regs)
1857 {
1858 first_error (_("register out of range in list"));
1859 return FAIL;
1860 }
b7fc2769 1861
477330fc
RM		 1862 if (regtype == REG_TYPE_NQ)
1863 high_range = high_range + 1;
5287ad62 1864
c19d1205
ZW		 1865 if (high_range <= new_base)
1866 {
1867 inst.error = _("register range not in ascending order");
1868 return FAIL;
1869 }
0bbf2aa4 1870
5287ad62 1871 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 1872 {
5287ad62 1873 if (mask & (setmask << new_base))
0bbf2aa4 1874 {
c19d1205
ZW		 1875 inst.error = _("invalid register list");
1876 return FAIL;
0bbf2aa4 1877 }
c19d1205 1878
5287ad62
JB		 1879 mask |= setmask << new_base;
1880 count += addregs;
0bbf2aa4 1881 }
0bbf2aa4 1882 }
0bbf2aa4 1883 }
037e8744 1884 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 1885
037e8744 1886 str++;
0bbf2aa4 1887
c19d1205
ZW		 1888 /* Sanity check -- should have raised a parse error above. */
1889 if (count == 0 || count > max_regs)
1890 abort ();
1891
1892 *pbase = base_reg;
1893
1894 /* Final test -- the registers must be consecutive. */
1895 mask >>= base_reg;
1896 for (i = 0; i < count; i++)
1897 {
1898 if ((mask & (1u << i)) == 0)
1899 {
1900 inst.error = _("non-contiguous register range");
1901 return FAIL;
1902 }
1903 }
1904
037e8744
JB		 1905 *ccp = str;
1906
c19d1205 1907 return count;
b99bd4ef
NC		 1908}
1909
dcbf9037
JB		 1910/* True if two alias types are the same. */
1911
c921be7d 1912static bfd_boolean
dcbf9037
JB		 1913neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1914{
1915 if (!a && !b)
c921be7d 1916 return TRUE;
5f4273c7 1917
dcbf9037 1918 if (!a || !b)
c921be7d 1919 return FALSE;
dcbf9037
JB		 1920
1921 if (a->defined != b->defined)
c921be7d 1922 return FALSE;
5f4273c7 1923
dcbf9037
JB		 1924 if ((a->defined & NTA_HASTYPE) != 0
1925 && (a->eltype.type != b->eltype.type
477330fc 1926 || a->eltype.size != b->eltype.size))
c921be7d 1927 return FALSE;
dcbf9037
JB		 1928
1929 if ((a->defined & NTA_HASINDEX) != 0
1930 && (a->index != b->index))
c921be7d 1931 return FALSE;
5f4273c7 1932
c921be7d 1933 return TRUE;
dcbf9037
JB		 1934}
1935
5287ad62
JB		 1936/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1937 The base register is put in *PBASE.
dcbf9037 1938 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB		 1939 the return value.
1940 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB		 1941 Bits [6:5] encode the list length (minus one).
1942 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 1943
5287ad62 1944#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 1945#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB		 1946#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1947
1948static int
dcbf9037 1949parse_neon_el_struct_list (char **str, unsigned *pbase,
477330fc 1950 struct neon_type_el *eltype)
5287ad62
JB		 1951{
1952 char *ptr = *str;
1953 int base_reg = -1;
1954 int reg_incr = -1;
1955 int count = 0;
1956 int lane = -1;
1957 int leading_brace = 0;
1958 enum arm_reg_type rtype = REG_TYPE_NDQ;
20203fb9
NC		 1959 const char *const incr_error = _("register stride must be 1 or 2");
1960 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 1961 struct neon_typed_alias firsttype;
5f4273c7 1962
5287ad62
JB		 1963 if (skip_past_char (&ptr, '{') == SUCCESS)
1964 leading_brace = 1;
5f4273c7 1965
5287ad62
JB		 1966 do
1967 {
dcbf9037
JB		 1968 struct neon_typed_alias atype;
1969 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1970
5287ad62 1971 if (getreg == FAIL)
477330fc
RM		 1972 {
1973 first_error (_(reg_expected_msgs[rtype]));
1974 return FAIL;
1975 }
5f4273c7 1976
5287ad62 1977 if (base_reg == -1)
477330fc
RM		 1978 {
1979 base_reg = getreg;
1980 if (rtype == REG_TYPE_NQ)
1981 {
1982 reg_incr = 1;
1983 }
1984 firsttype = atype;
1985 }
5287ad62 1986 else if (reg_incr == -1)
477330fc
RM		 1987 {
1988 reg_incr = getreg - base_reg;
1989 if (reg_incr < 1 || reg_incr > 2)
1990 {
1991 first_error (_(incr_error));
1992 return FAIL;
1993 }
1994 }
5287ad62 1995 else if (getreg != base_reg + reg_incr * count)
477330fc
RM		 1996 {
1997 first_error (_(incr_error));
1998 return FAIL;
1999 }
dcbf9037 2000
c921be7d 2001 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM		 2002 {
2003 first_error (_(type_error));
2004 return FAIL;
2005 }
5f4273c7 2006
5287ad62 2007 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 2008 modes. */
5287ad62 2009 if (ptr[0] == '-')
477330fc
RM		 2010 {
2011 struct neon_typed_alias htype;
2012 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2013 if (lane == -1)
2014 lane = NEON_INTERLEAVE_LANES;
2015 else if (lane != NEON_INTERLEAVE_LANES)
2016 {
2017 first_error (_(type_error));
2018 return FAIL;
2019 }
2020 if (reg_incr == -1)
2021 reg_incr = 1;
2022 else if (reg_incr != 1)
2023 {
2024 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2025 return FAIL;
2026 }
2027 ptr++;
2028 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2029 if (hireg == FAIL)
2030 {
2031 first_error (_(reg_expected_msgs[rtype]));
2032 return FAIL;
2033 }
2034 if (! neon_alias_types_same (&htype, &firsttype))
2035 {
2036 first_error (_(type_error));
2037 return FAIL;
2038 }
2039 count += hireg + dregs - getreg;
2040 continue;
2041 }
5f4273c7 2042
5287ad62
JB		 2043 /* If we're using Q registers, we can't use [] or [n] syntax. */
2044 if (rtype == REG_TYPE_NQ)
477330fc
RM		 2045 {
2046 count += 2;
2047 continue;
2048 }
5f4273c7 2049
dcbf9037 2050 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 2051 {
2052 if (lane == -1)
2053 lane = atype.index;
2054 else if (lane != atype.index)
2055 {
2056 first_error (_(type_error));
2057 return FAIL;
2058 }
2059 }
5287ad62 2060 else if (lane == -1)
477330fc 2061 lane = NEON_INTERLEAVE_LANES;
5287ad62 2062 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM		 2063 {
2064 first_error (_(type_error));
2065 return FAIL;
2066 }
5287ad62
JB		 2067 count++;
2068 }
2069 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2070
5287ad62
JB		 2071 /* No lane set by [x]. We must be interleaving structures. */
2072 if (lane == -1)
2073 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2074
5287ad62
JB		 2075 /* Sanity check. */
2076 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2077 || (count > 1 && reg_incr == -1))
2078 {
dcbf9037 2079 first_error (_("error parsing element/structure list"));
5287ad62
JB		 2080 return FAIL;
2081 }
2082
2083 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2084 {
dcbf9037 2085 first_error (_("expected }"));
5287ad62
JB		 2086 return FAIL;
2087 }
5f4273c7 2088
5287ad62
JB		 2089 if (reg_incr == -1)
2090 reg_incr = 1;
2091
dcbf9037
JB		 2092 if (eltype)
2093 *eltype = firsttype.eltype;
2094
5287ad62
JB		 2095 *pbase = base_reg;
2096 *str = ptr;
5f4273c7 2097
5287ad62
JB		 2098 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2099}
2100
c19d1205
ZW		 2101/* Parse an explicit relocation suffix on an expression. This is
2102 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2103 arm_reloc_hsh contains no entries, so this function can only
2104 succeed if there is no () after the word. Returns -1 on error,
2105 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2106
c19d1205
ZW		 2107static int
2108parse_reloc (char **str)
b99bd4ef 2109{
c19d1205
ZW		 2110 struct reloc_entry *r;
2111 char *p, *q;
b99bd4ef 2112
c19d1205
ZW		 2113 if (**str != '(')
2114 return BFD_RELOC_UNUSED;
b99bd4ef 2115
c19d1205
ZW		 2116 p = *str + 1;
2117 q = p;
2118
2119 while (*q && *q != ')' && *q != ',')
2120 q++;
2121 if (*q != ')')
2122 return -1;
2123
21d799b5
NC		 2124 if ((r = (struct reloc_entry *)
2125 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW		 2126 return -1;
2127
2128 *str = q + 1;
2129 return r->reloc;
b99bd4ef
NC		 2130}
2131
c19d1205
ZW		 2132/* Directives: register aliases. */
2133
dcbf9037 2134static struct reg_entry *
90ec0d68 2135insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2136{
d3ce72d0 2137 struct reg_entry *new_reg;
c19d1205 2138 const char *name;
b99bd4ef 2139
d3ce72d0 2140 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2141 {
d3ce72d0 2142 if (new_reg->builtin)
c19d1205 2143 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2144
c19d1205
ZW		 2145 /* Only warn about a redefinition if it's not defined as the
2146 same register. */
d3ce72d0 2147 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2148 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2149
d929913e 2150 return NULL;
c19d1205 2151 }
b99bd4ef 2152
c19d1205 2153 name = xstrdup (str);
d3ce72d0 2154 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
b99bd4ef 2155
d3ce72d0
NC		 2156 new_reg->name = name;
2157 new_reg->number = number;
2158 new_reg->type = type;
2159 new_reg->builtin = FALSE;
2160 new_reg->neon = NULL;
b99bd4ef 2161
d3ce72d0 2162 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2163 abort ();
5f4273c7 2164
d3ce72d0 2165 return new_reg;
dcbf9037
JB		 2166}
2167
2168static void
2169insert_neon_reg_alias (char *str, int number, int type,
477330fc 2170 struct neon_typed_alias *atype)
dcbf9037
JB		 2171{
2172 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2173
dcbf9037
JB		 2174 if (!reg)
2175 {
2176 first_error (_("attempt to redefine typed alias"));
2177 return;
2178 }
5f4273c7 2179
dcbf9037
JB		 2180 if (atype)
2181 {
21d799b5 2182 reg->neon = (struct neon_typed_alias *)
477330fc 2183 xmalloc (sizeof (struct neon_typed_alias));
dcbf9037
JB		 2184 *reg->neon = *atype;
2185 }
c19d1205 2186}
b99bd4ef 2187
c19d1205 2188/* Look for the .req directive. This is of the form:
b99bd4ef 2189
c19d1205 2190 new_register_name .req existing_register_name
b99bd4ef 2191
c19d1205 2192 If we find one, or if it looks sufficiently like one that we want to
d929913e 2193 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2194
d929913e 2195static bfd_boolean
c19d1205
ZW		 2196create_register_alias (char * newname, char *p)
2197{
2198 struct reg_entry *old;
2199 char *oldname, *nbuf;
2200 size_t nlen;
b99bd4ef 2201
c19d1205
ZW		 2202 /* The input scrubber ensures that whitespace after the mnemonic is
2203 collapsed to single spaces. */
2204 oldname = p;
2205 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2206 return FALSE;
b99bd4ef 2207
c19d1205
ZW		 2208 oldname += 6;
2209 if (*oldname == '\0')
d929913e 2210 return FALSE;
b99bd4ef 2211
21d799b5 2212 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2213 if (!old)
b99bd4ef 2214 {
c19d1205 2215 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2216 return TRUE;
b99bd4ef
NC		 2217 }
2218
c19d1205
ZW		 2219 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2220 the desired alias name, and p points to its end. If not, then
2221 the desired alias name is in the global original_case_string. */
2222#ifdef TC_CASE_SENSITIVE
2223 nlen = p - newname;
2224#else
2225 newname = original_case_string;
2226 nlen = strlen (newname);
2227#endif
b99bd4ef 2228
21d799b5 2229 nbuf = (char *) alloca (nlen + 1);
c19d1205
ZW		 2230 memcpy (nbuf, newname, nlen);
2231 nbuf[nlen] = '\0';
b99bd4ef 2232
c19d1205
ZW		 2233 /* Create aliases under the new name as stated; an all-lowercase
2234 version of the new name; and an all-uppercase version of the new
2235 name. */
d929913e
NC		 2236 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2237 {
2238 for (p = nbuf; *p; p++)
2239 *p = TOUPPER (*p);
c19d1205 2240
d929913e
NC		 2241 if (strncmp (nbuf, newname, nlen))
2242 {
2243 /* If this attempt to create an additional alias fails, do not bother
2244 trying to create the all-lower case alias. We will fail and issue
2245 a second, duplicate error message. This situation arises when the
2246 programmer does something like:
2247 foo .req r0
2248 Foo .req r1
2249 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2250 the artificial FOO alias because it has already been created by the
d929913e
NC		 2251 first .req. */
2252 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2253 return TRUE;
2254 }
c19d1205 2255
d929913e
NC		 2256 for (p = nbuf; *p; p++)
2257 *p = TOLOWER (*p);
c19d1205 2258
d929913e
NC		 2259 if (strncmp (nbuf, newname, nlen))
2260 insert_reg_alias (nbuf, old->number, old->type);
2261 }
c19d1205 2262
d929913e 2263 return TRUE;
b99bd4ef
NC		 2264}
2265
dcbf9037
JB		 2266/* Create a Neon typed/indexed register alias using directives, e.g.:
2267 X .dn d5.s32[1]
2268 Y .qn 6.s16
2269 Z .dn d7
2270 T .dn Z[0]
2271 These typed registers can be used instead of the types specified after the
2272 Neon mnemonic, so long as all operands given have types. Types can also be
2273 specified directly, e.g.:
5f4273c7 2274 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2275
c921be7d 2276static bfd_boolean
dcbf9037
JB		 2277create_neon_reg_alias (char *newname, char *p)
2278{
2279 enum arm_reg_type basetype;
2280 struct reg_entry *basereg;
2281 struct reg_entry mybasereg;
2282 struct neon_type ntype;
2283 struct neon_typed_alias typeinfo;
12d6b0b7 2284 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2285 int namelen;
5f4273c7 2286
dcbf9037
JB		 2287 typeinfo.defined = 0;
2288 typeinfo.eltype.type = NT_invtype;
2289 typeinfo.eltype.size = -1;
2290 typeinfo.index = -1;
5f4273c7 2291
dcbf9037 2292 nameend = p;
5f4273c7 2293
dcbf9037
JB		 2294 if (strncmp (p, " .dn ", 5) == 0)
2295 basetype = REG_TYPE_VFD;
2296 else if (strncmp (p, " .qn ", 5) == 0)
2297 basetype = REG_TYPE_NQ;
2298 else
c921be7d 2299 return FALSE;
5f4273c7 2300
dcbf9037 2301 p += 5;
5f4273c7 2302
dcbf9037 2303 if (*p == '\0')
c921be7d 2304 return FALSE;
5f4273c7 2305
dcbf9037
JB		 2306 basereg = arm_reg_parse_multi (&p);
2307
2308 if (basereg && basereg->type != basetype)
2309 {
2310 as_bad (_("bad type for register"));
c921be7d 2311 return FALSE;
dcbf9037
JB		 2312 }
2313
2314 if (basereg == NULL)
2315 {
2316 expressionS exp;
2317 /* Try parsing as an integer. */
2318 my_get_expression (&exp, &p, GE_NO_PREFIX);
2319 if (exp.X_op != O_constant)
477330fc
RM		 2320 {
2321 as_bad (_("expression must be constant"));
2322 return FALSE;
2323 }
dcbf9037
JB		 2324 basereg = &mybasereg;
2325 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2326 : exp.X_add_number;
dcbf9037
JB		 2327 basereg->neon = 0;
2328 }
2329
2330 if (basereg->neon)
2331 typeinfo = *basereg->neon;
2332
2333 if (parse_neon_type (&ntype, &p) == SUCCESS)
2334 {
2335 /* We got a type. */
2336 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM		 2337 {
2338 as_bad (_("can't redefine the type of a register alias"));
2339 return FALSE;
2340 }
5f4273c7 2341
dcbf9037
JB		 2342 typeinfo.defined |= NTA_HASTYPE;
2343 if (ntype.elems != 1)
477330fc
RM		 2344 {
2345 as_bad (_("you must specify a single type only"));
2346 return FALSE;
2347 }
dcbf9037
JB		 2348 typeinfo.eltype = ntype.el[0];
2349 }
5f4273c7 2350
dcbf9037
JB		 2351 if (skip_past_char (&p, '[') == SUCCESS)
2352 {
2353 expressionS exp;
2354 /* We got a scalar index. */
5f4273c7 2355
dcbf9037 2356 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM		 2357 {
2358 as_bad (_("can't redefine the index of a scalar alias"));
2359 return FALSE;
2360 }
5f4273c7 2361
dcbf9037 2362 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2363
dcbf9037 2364 if (exp.X_op != O_constant)
477330fc
RM		 2365 {
2366 as_bad (_("scalar index must be constant"));
2367 return FALSE;
2368 }
5f4273c7 2369
dcbf9037
JB		 2370 typeinfo.defined |= NTA_HASINDEX;
2371 typeinfo.index = exp.X_add_number;
5f4273c7 2372
dcbf9037 2373 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM		 2374 {
2375 as_bad (_("expecting ]"));
2376 return FALSE;
2377 }
dcbf9037
JB		 2378 }
2379
15735687
NS		 2380 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2381 the desired alias name, and p points to its end. If not, then
2382 the desired alias name is in the global original_case_string. */
2383#ifdef TC_CASE_SENSITIVE
dcbf9037 2384 namelen = nameend - newname;
15735687
NS		 2385#else
2386 newname = original_case_string;
2387 namelen = strlen (newname);
2388#endif
2389
21d799b5 2390 namebuf = (char *) alloca (namelen + 1);
dcbf9037
JB		 2391 strncpy (namebuf, newname, namelen);
2392 namebuf[namelen] = '\0';
5f4273c7 2393
dcbf9037 2394 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2395 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2396
dcbf9037
JB		 2397 /* Insert name in all uppercase. */
2398 for (p = namebuf; *p; p++)
2399 *p = TOUPPER (*p);
5f4273c7 2400
dcbf9037
JB		 2401 if (strncmp (namebuf, newname, namelen))
2402 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2403 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2404
dcbf9037
JB		 2405 /* Insert name in all lowercase. */
2406 for (p = namebuf; *p; p++)
2407 *p = TOLOWER (*p);
5f4273c7 2408
dcbf9037
JB		 2409 if (strncmp (namebuf, newname, namelen))
2410 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2411 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2412
c921be7d 2413 return TRUE;
dcbf9037
JB		 2414}
2415
c19d1205
ZW		 2416/* Should never be called, as .req goes between the alias and the
2417 register name, not at the beginning of the line. */
c921be7d 2418
b99bd4ef 2419static void
c19d1205 2420s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2421{
c19d1205
ZW		 2422 as_bad (_("invalid syntax for .req directive"));
2423}
b99bd4ef 2424
dcbf9037
JB		 2425static void
2426s_dn (int a ATTRIBUTE_UNUSED)
2427{
2428 as_bad (_("invalid syntax for .dn directive"));
2429}
2430
2431static void
2432s_qn (int a ATTRIBUTE_UNUSED)
2433{
2434 as_bad (_("invalid syntax for .qn directive"));
2435}
2436
c19d1205
ZW		 2437/* The .unreq directive deletes an alias which was previously defined
2438 by .req. For example:
b99bd4ef 2439
c19d1205
ZW		 2440 my_alias .req r11
2441 .unreq my_alias */
b99bd4ef
NC		 2442
2443static void
c19d1205 2444s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2445{
c19d1205
ZW		 2446 char * name;
2447 char saved_char;
b99bd4ef 2448
c19d1205
ZW		 2449 name = input_line_pointer;
2450
2451 while (*input_line_pointer != 0
2452 && *input_line_pointer != ' '
2453 && *input_line_pointer != '\n')
2454 ++input_line_pointer;
2455
2456 saved_char = *input_line_pointer;
2457 *input_line_pointer = 0;
2458
2459 if (!*name)
2460 as_bad (_("invalid syntax for .unreq directive"));
2461 else
2462 {
21d799b5 2463 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2464 name);
c19d1205
ZW		 2465
2466 if (!reg)
2467 as_bad (_("unknown register alias '%s'"), name);
2468 else if (reg->builtin)
a1727c1a 2469 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW		 2470 name);
2471 else
2472 {
d929913e
NC		 2473 char * p;
2474 char * nbuf;
2475
db0bc284 2476 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2477 free ((char *) reg->name);
477330fc
RM		 2478 if (reg->neon)
2479 free (reg->neon);
c19d1205 2480 free (reg);
d929913e
NC		 2481
2482 /* Also locate the all upper case and all lower case versions.
2483 Do not complain if we cannot find one or the other as it
2484 was probably deleted above. */
5f4273c7 2485
d929913e
NC		 2486 nbuf = strdup (name);
2487 for (p = nbuf; *p; p++)
2488 *p = TOUPPER (*p);
21d799b5 2489 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2490 if (reg)
2491 {
db0bc284 2492 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2493 free ((char *) reg->name);
2494 if (reg->neon)
2495 free (reg->neon);
2496 free (reg);
2497 }
2498
2499 for (p = nbuf; *p; p++)
2500 *p = TOLOWER (*p);
21d799b5 2501 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2502 if (reg)
2503 {
db0bc284 2504 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2505 free ((char *) reg->name);
2506 if (reg->neon)
2507 free (reg->neon);
2508 free (reg);
2509 }
2510
2511 free (nbuf);
c19d1205
ZW		 2512 }
2513 }
b99bd4ef 2514
c19d1205 2515 *input_line_pointer = saved_char;
b99bd4ef
NC		 2516 demand_empty_rest_of_line ();
2517}
2518
c19d1205
ZW		 2519/* Directives: Instruction set selection. */
2520
2521#ifdef OBJ_ELF
2522/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2523 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2524 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2525 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2526
cd000bff
DJ		 2527/* Create a new mapping symbol for the transition to STATE. */
2528
2529static void
2530make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2531{
a737bd4d 2532 symbolS * symbolP;
c19d1205
ZW		 2533 const char * symname;
2534 int type;
b99bd4ef 2535
c19d1205 2536 switch (state)
b99bd4ef 2537 {
c19d1205
ZW		 2538 case MAP_DATA:
2539 symname = "$d";
2540 type = BSF_NO_FLAGS;
2541 break;
2542 case MAP_ARM:
2543 symname = "$a";
2544 type = BSF_NO_FLAGS;
2545 break;
2546 case MAP_THUMB:
2547 symname = "$t";
2548 type = BSF_NO_FLAGS;
2549 break;
c19d1205
ZW		 2550 default:
2551 abort ();
2552 }
2553
cd000bff 2554 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW		 2555 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2556
2557 switch (state)
2558 {
2559 case MAP_ARM:
2560 THUMB_SET_FUNC (symbolP, 0);
2561 ARM_SET_THUMB (symbolP, 0);
2562 ARM_SET_INTERWORK (symbolP, support_interwork);
2563 break;
2564
2565 case MAP_THUMB:
2566 THUMB_SET_FUNC (symbolP, 1);
2567 ARM_SET_THUMB (symbolP, 1);
2568 ARM_SET_INTERWORK (symbolP, support_interwork);
2569 break;
2570
2571 case MAP_DATA:
2572 default:
cd000bff
DJ		 2573 break;
2574 }
2575
2576 /* Save the mapping symbols for future reference. Also check that
2577 we do not place two mapping symbols at the same offset within a
2578 frag. We'll handle overlap between frags in
2de7820f
JZ		 2579 check_mapping_symbols.
2580
2581 If .fill or other data filling directive generates zero sized data,
2582 the mapping symbol for the following code will have the same value
2583 as the one generated for the data filling directive. In this case,
2584 we replace the old symbol with the new one at the same address. */
cd000bff
DJ		 2585 if (value == 0)
2586 {
2de7820f
JZ		 2587 if (frag->tc_frag_data.first_map != NULL)
2588 {
2589 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2590 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2591 }
cd000bff
DJ		 2592 frag->tc_frag_data.first_map = symbolP;
2593 }
2594 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ		 2595 {
2596 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ		 2597 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2598 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2599 }
cd000bff
DJ		 2600 frag->tc_frag_data.last_map = symbolP;
2601}
2602
2603/* We must sometimes convert a region marked as code to data during
2604 code alignment, if an odd number of bytes have to be padded. The
2605 code mapping symbol is pushed to an aligned address. */
2606
2607static void
2608insert_data_mapping_symbol (enum mstate state,
2609 valueT value, fragS *frag, offsetT bytes)
2610{
2611 /* If there was already a mapping symbol, remove it. */
2612 if (frag->tc_frag_data.last_map != NULL
2613 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2614 {
2615 symbolS *symp = frag->tc_frag_data.last_map;
2616
2617 if (value == 0)
2618 {
2619 know (frag->tc_frag_data.first_map == symp);
2620 frag->tc_frag_data.first_map = NULL;
2621 }
2622 frag->tc_frag_data.last_map = NULL;
2623 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2624 }
cd000bff
DJ		 2625
2626 make_mapping_symbol (MAP_DATA, value, frag);
2627 make_mapping_symbol (state, value + bytes, frag);
2628}
2629
2630static void mapping_state_2 (enum mstate state, int max_chars);
2631
2632/* Set the mapping state to STATE. Only call this when about to
2633 emit some STATE bytes to the file. */
2634
2635void
2636mapping_state (enum mstate state)
2637{
940b5ce0
DJ		 2638 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2639
cd000bff
DJ		 2640#define TRANSITION(from, to) (mapstate == (from) && state == (to))
2641
2642 if (mapstate == state)
2643 /* The mapping symbol has already been emitted.
2644 There is nothing else to do. */
2645 return;
49c62a33
NC		 2646
2647 if (state == MAP_ARM || state == MAP_THUMB)
2648 /* PR gas/12931
2649 All ARM instructions require 4-byte alignment.
2650 (Almost) all Thumb instructions require 2-byte alignment.
2651
2652 When emitting instructions into any section, mark the section
2653 appropriately.
2654
2655 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2656 but themselves require 2-byte alignment; this applies to some
2657 PC- relative forms. However, these cases will invovle implicit
2658 literal pool generation or an explicit .align >=2, both of
2659 which will cause the section to me marked with sufficient
2660 alignment. Thus, we don't handle those cases here. */
2661 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2662
2663 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
cd000bff
DJ		 2664 /* This case will be evaluated later in the next else. */
2665 return;
2666 else if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
477330fc 2667 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
cd000bff
DJ		 2668 {
2669 /* Only add the symbol if the offset is > 0:
477330fc
RM		 2670 if we're at the first frag, check it's size > 0;
2671 if we're not at the first frag, then for sure
2672 the offset is > 0. */
cd000bff
DJ		 2673 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2674 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2675
2676 if (add_symbol)
477330fc 2677 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
cd000bff
DJ		 2678 }
2679
2680 mapping_state_2 (state, 0);
2681#undef TRANSITION
2682}
2683
2684/* Same as mapping_state, but MAX_CHARS bytes have already been
2685 allocated. Put the mapping symbol that far back. */
2686
2687static void
2688mapping_state_2 (enum mstate state, int max_chars)
2689{
940b5ce0
DJ		 2690 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2691
2692 if (!SEG_NORMAL (now_seg))
2693 return;
2694
cd000bff
DJ		 2695 if (mapstate == state)
2696 /* The mapping symbol has already been emitted.
2697 There is nothing else to do. */
2698 return;
2699
cd000bff
DJ		 2700 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2701 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205
ZW		 2702}
2703#else
d3106081
NS		 2704#define mapping_state(x) ((void)0)
2705#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW		 2706#endif
2707
2708/* Find the real, Thumb encoded start of a Thumb function. */
2709
4343666d 2710#ifdef OBJ_COFF
c19d1205
ZW		 2711static symbolS *
2712find_real_start (symbolS * symbolP)
2713{
2714 char * real_start;
2715 const char * name = S_GET_NAME (symbolP);
2716 symbolS * new_target;
2717
2718 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2719#define STUB_NAME ".real_start_of"
2720
2721 if (name == NULL)
2722 abort ();
2723
37f6032b
ZW		 2724 /* The compiler may generate BL instructions to local labels because
2725 it needs to perform a branch to a far away location. These labels
2726 do not have a corresponding ".real_start_of" label. We check
2727 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2728 the ".real_start_of" convention for nonlocal branches. */
2729 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW		 2730 return symbolP;
2731
37f6032b 2732 real_start = ACONCAT ((STUB_NAME, name, NULL));
c19d1205
ZW		 2733 new_target = symbol_find (real_start);
2734
2735 if (new_target == NULL)
2736 {
bd3ba5d1 2737 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW		 2738 new_target = symbolP;
2739 }
2740
c19d1205
ZW		 2741 return new_target;
2742}
4343666d 2743#endif
c19d1205
ZW		 2744
2745static void
2746opcode_select (int width)
2747{
2748 switch (width)
2749 {
2750 case 16:
2751 if (! thumb_mode)
2752 {
e74cfd16 2753 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW		 2754 as_bad (_("selected processor does not support THUMB opcodes"));
2755
2756 thumb_mode = 1;
2757 /* No need to force the alignment, since we will have been
2758 coming from ARM mode, which is word-aligned. */
2759 record_alignment (now_seg, 1);
2760 }
c19d1205
ZW		 2761 break;
2762
2763 case 32:
2764 if (thumb_mode)
2765 {
e74cfd16 2766 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW		 2767 as_bad (_("selected processor does not support ARM opcodes"));
2768
2769 thumb_mode = 0;
2770
2771 if (!need_pass_2)
2772 frag_align (2, 0, 0);
2773
2774 record_alignment (now_seg, 1);
2775 }
c19d1205
ZW		 2776 break;
2777
2778 default:
2779 as_bad (_("invalid instruction size selected (%d)"), width);
2780 }
2781}
2782
2783static void
2784s_arm (int ignore ATTRIBUTE_UNUSED)
2785{
2786 opcode_select (32);
2787 demand_empty_rest_of_line ();
2788}
2789
2790static void
2791s_thumb (int ignore ATTRIBUTE_UNUSED)
2792{
2793 opcode_select (16);
2794 demand_empty_rest_of_line ();
2795}
2796
2797static void
2798s_code (int unused ATTRIBUTE_UNUSED)
2799{
2800 int temp;
2801
2802 temp = get_absolute_expression ();
2803 switch (temp)
2804 {
2805 case 16:
2806 case 32:
2807 opcode_select (temp);
2808 break;
2809
2810 default:
2811 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2812 }
2813}
2814
2815static void
2816s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2817{
2818 /* If we are not already in thumb mode go into it, EVEN if
2819 the target processor does not support thumb instructions.
2820 This is used by gcc/config/arm/lib1funcs.asm for example
2821 to compile interworking support functions even if the
2822 target processor should not support interworking. */
2823 if (! thumb_mode)
2824 {
2825 thumb_mode = 2;
2826 record_alignment (now_seg, 1);
2827 }
2828
2829 demand_empty_rest_of_line ();
2830}
2831
2832static void
2833s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2834{
2835 s_thumb (0);
2836
2837 /* The following label is the name/address of the start of a Thumb function.
2838 We need to know this for the interworking support. */
2839 label_is_thumb_function_name = TRUE;
2840}
2841
2842/* Perform a .set directive, but also mark the alias as
2843 being a thumb function. */
2844
2845static void
2846s_thumb_set (int equiv)
2847{
2848 /* XXX the following is a duplicate of the code for s_set() in read.c
2849 We cannot just call that code as we need to get at the symbol that
2850 is created. */
2851 char * name;
2852 char delim;
2853 char * end_name;
2854 symbolS * symbolP;
2855
2856 /* Especial apologies for the random logic:
2857 This just grew, and could be parsed much more simply!
2858 Dean - in haste. */
2859 name = input_line_pointer;
2860 delim = get_symbol_end ();
2861 end_name = input_line_pointer;
2862 *end_name = delim;
2863
2864 if (*input_line_pointer != ',')
2865 {
2866 *end_name = 0;
2867 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC		 2868 *end_name = delim;
2869 ignore_rest_of_line ();
2870 return;
2871 }
2872
2873 input_line_pointer++;
2874 *end_name = 0;
2875
2876 if (name[0] == '.' && name[1] == '\0')
2877 {
2878 /* XXX - this should not happen to .thumb_set. */
2879 abort ();
2880 }
2881
2882 if ((symbolP = symbol_find (name)) == NULL
2883 && (symbolP = md_undefined_symbol (name)) == NULL)
2884 {
2885#ifndef NO_LISTING
2886 /* When doing symbol listings, play games with dummy fragments living
2887 outside the normal fragment chain to record the file and line info
c19d1205 2888 for this symbol. */
b99bd4ef
NC		 2889 if (listing & LISTING_SYMBOLS)
2890 {
2891 extern struct list_info_struct * listing_tail;
21d799b5 2892 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC		 2893
2894 memset (dummy_frag, 0, sizeof (fragS));
2895 dummy_frag->fr_type = rs_fill;
2896 dummy_frag->line = listing_tail;
2897 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2898 dummy_frag->fr_symbol = symbolP;
2899 }
2900 else
2901#endif
2902 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2903
2904#ifdef OBJ_COFF
2905 /* "set" symbols are local unless otherwise specified. */
2906 SF_SET_LOCAL (symbolP);
2907#endif /* OBJ_COFF */
2908 } /* Make a new symbol. */
2909
2910 symbol_table_insert (symbolP);
2911
2912 * end_name = delim;
2913
2914 if (equiv
2915 && S_IS_DEFINED (symbolP)
2916 && S_GET_SEGMENT (symbolP) != reg_section)
2917 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2918
2919 pseudo_set (symbolP);
2920
2921 demand_empty_rest_of_line ();
2922
c19d1205 2923 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC		 2924
2925 THUMB_SET_FUNC (symbolP, 1);
2926 ARM_SET_THUMB (symbolP, 1);
2927#if defined OBJ_ELF || defined OBJ_COFF
2928 ARM_SET_INTERWORK (symbolP, support_interwork);
2929#endif
2930}
2931
c19d1205 2932/* Directives: Mode selection. */
b99bd4ef 2933
c19d1205
ZW		 2934/* .syntax [unified|divided] - choose the new unified syntax
2935 (same for Arm and Thumb encoding, modulo slight differences in what
2936 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 2937static void
c19d1205 2938s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2939{
c19d1205
ZW		 2940 char *name, delim;
2941
2942 name = input_line_pointer;
2943 delim = get_symbol_end ();
2944
2945 if (!strcasecmp (name, "unified"))
2946 unified_syntax = TRUE;
2947 else if (!strcasecmp (name, "divided"))
2948 unified_syntax = FALSE;
2949 else
2950 {
2951 as_bad (_("unrecognized syntax mode \"%s\""), name);
2952 return;
2953 }
2954 *input_line_pointer = delim;
b99bd4ef
NC		 2955 demand_empty_rest_of_line ();
2956}
2957
c19d1205
ZW		 2958/* Directives: sectioning and alignment. */
2959
2960/* Same as s_align_ptwo but align 0 => align 2. */
2961
b99bd4ef 2962static void
c19d1205 2963s_align (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2964{
a737bd4d 2965 int temp;
dce323d1 2966 bfd_boolean fill_p;
c19d1205
ZW		 2967 long temp_fill;
2968 long max_alignment = 15;
b99bd4ef
NC		 2969
2970 temp = get_absolute_expression ();
c19d1205
ZW		 2971 if (temp > max_alignment)
2972 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2973 else if (temp < 0)
b99bd4ef 2974 {
c19d1205
ZW		 2975 as_bad (_("alignment negative. 0 assumed."));
2976 temp = 0;
2977 }
b99bd4ef 2978
c19d1205
ZW		 2979 if (*input_line_pointer == ',')
2980 {
2981 input_line_pointer++;
2982 temp_fill = get_absolute_expression ();
dce323d1 2983 fill_p = TRUE;
b99bd4ef 2984 }
c19d1205 2985 else
dce323d1
PB		 2986 {
2987 fill_p = FALSE;
2988 temp_fill = 0;
2989 }
b99bd4ef 2990
c19d1205
ZW		 2991 if (!temp)
2992 temp = 2;
b99bd4ef 2993
c19d1205
ZW		 2994 /* Only make a frag if we HAVE to. */
2995 if (temp && !need_pass_2)
dce323d1
PB		 2996 {
2997 if (!fill_p && subseg_text_p (now_seg))
2998 frag_align_code (temp, 0);
2999 else
3000 frag_align (temp, (int) temp_fill, 0);
3001 }
c19d1205
ZW		 3002 demand_empty_rest_of_line ();
3003
3004 record_alignment (now_seg, temp);
b99bd4ef
NC		 3005}
3006
c19d1205
ZW		 3007static void
3008s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 3009{
c19d1205
ZW		 3010 /* We don't support putting frags in the BSS segment, we fake it by
3011 marking in_bss, then looking at s_skip for clues. */
3012 subseg_set (bss_section, 0);
3013 demand_empty_rest_of_line ();
cd000bff
DJ		 3014
3015#ifdef md_elf_section_change_hook
3016 md_elf_section_change_hook ();
3017#endif
c19d1205 3018}
b99bd4ef 3019
c19d1205
ZW		 3020static void
3021s_even (int ignore ATTRIBUTE_UNUSED)
3022{
3023 /* Never make frag if expect extra pass. */
3024 if (!need_pass_2)
3025 frag_align (1, 0, 0);
b99bd4ef 3026
c19d1205 3027 record_alignment (now_seg, 1);
b99bd4ef 3028
c19d1205 3029 demand_empty_rest_of_line ();
b99bd4ef
NC		 3030}
3031
2e6976a8
DG		 3032/* Directives: CodeComposer Studio. */
3033
3034/* .ref (for CodeComposer Studio syntax only). */
3035static void
3036s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3037{
3038 if (codecomposer_syntax)
3039 ignore_rest_of_line ();
3040 else
3041 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3042}
3043
3044/* If name is not NULL, then it is used for marking the beginning of a
3045 function, wherease if it is NULL then it means the function end. */
3046static void
3047asmfunc_debug (const char * name)
3048{
3049 static const char * last_name = NULL;
3050
3051 if (name != NULL)
3052 {
3053 gas_assert (last_name == NULL);
3054 last_name = name;
3055
3056 if (debug_type == DEBUG_STABS)
3057 stabs_generate_asm_func (name, name);
3058 }
3059 else
3060 {
3061 gas_assert (last_name != NULL);
3062
3063 if (debug_type == DEBUG_STABS)
3064 stabs_generate_asm_endfunc (last_name, last_name);
3065
3066 last_name = NULL;
3067 }
3068}
3069
3070static void
3071s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3072{
3073 if (codecomposer_syntax)
3074 {
3075 switch (asmfunc_state)
3076 {
3077 case OUTSIDE_ASMFUNC:
3078 asmfunc_state = WAITING_ASMFUNC_NAME;
3079 break;
3080
3081 case WAITING_ASMFUNC_NAME:
3082 as_bad (_(".asmfunc repeated."));
3083 break;
3084
3085 case WAITING_ENDASMFUNC:
3086 as_bad (_(".asmfunc without function."));
3087 break;
3088 }
3089 demand_empty_rest_of_line ();
3090 }
3091 else
3092 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3093}
3094
3095static void
3096s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3097{
3098 if (codecomposer_syntax)
3099 {
3100 switch (asmfunc_state)
3101 {
3102 case OUTSIDE_ASMFUNC:
3103 as_bad (_(".endasmfunc without a .asmfunc."));
3104 break;
3105
3106 case WAITING_ASMFUNC_NAME:
3107 as_bad (_(".endasmfunc without function."));
3108 break;
3109
3110 case WAITING_ENDASMFUNC:
3111 asmfunc_state = OUTSIDE_ASMFUNC;
3112 asmfunc_debug (NULL);
3113 break;
3114 }
3115 demand_empty_rest_of_line ();
3116 }
3117 else
3118 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3119}
3120
3121static void
3122s_ccs_def (int name)
3123{
3124 if (codecomposer_syntax)
3125 s_globl (name);
3126 else
3127 as_bad (_(".def pseudo-op only available with -mccs flag."));
3128}
3129
c19d1205 3130/* Directives: Literal pools. */
a737bd4d 3131
c19d1205
ZW		 3132static literal_pool *
3133find_literal_pool (void)
a737bd4d 3134{
c19d1205 3135 literal_pool * pool;
a737bd4d 3136
c19d1205 3137 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3138 {
c19d1205
ZW		 3139 if (pool->section == now_seg
3140 && pool->sub_section == now_subseg)
3141 break;
a737bd4d
NC		 3142 }
3143
c19d1205 3144 return pool;
a737bd4d
NC		 3145}
3146
c19d1205
ZW		 3147static literal_pool *
3148find_or_make_literal_pool (void)
a737bd4d 3149{
c19d1205
ZW		 3150 /* Next literal pool ID number. */
3151 static unsigned int latest_pool_num = 1;
3152 literal_pool * pool;
a737bd4d 3153
c19d1205 3154 pool = find_literal_pool ();
a737bd4d 3155
c19d1205 3156 if (pool == NULL)
a737bd4d 3157 {
c19d1205 3158 /* Create a new pool. */
21d799b5 3159 pool = (literal_pool *) xmalloc (sizeof (* pool));
c19d1205
ZW		 3160 if (! pool)
3161 return NULL;
a737bd4d 3162
c19d1205
ZW		 3163 pool->next_free_entry = 0;
3164 pool->section = now_seg;
3165 pool->sub_section = now_subseg;
3166 pool->next = list_of_pools;
3167 pool->symbol = NULL;
8335d6aa 3168 pool->alignment = 2;
c19d1205
ZW		 3169
3170 /* Add it to the list. */
3171 list_of_pools = pool;
a737bd4d 3172 }
a737bd4d 3173
c19d1205
ZW		 3174 /* New pools, and emptied pools, will have a NULL symbol. */
3175 if (pool->symbol == NULL)
a737bd4d 3176 {
c19d1205
ZW		 3177 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3178 (valueT) 0, &zero_address_frag);
3179 pool->id = latest_pool_num ++;
a737bd4d
NC		 3180 }
3181
c19d1205
ZW		 3182 /* Done. */
3183 return pool;
a737bd4d
NC		 3184}
3185
c19d1205 3186/* Add the literal in the global 'inst'
5f4273c7 3187 structure to the relevant literal pool. */
b99bd4ef
NC		 3188
3189static int
8335d6aa 3190add_to_lit_pool (unsigned int nbytes)
b99bd4ef 3191{
8335d6aa
JW		 3192#define PADDING_SLOT 0x1
3193#define LIT_ENTRY_SIZE_MASK 0xFF
c19d1205 3194 literal_pool * pool;
8335d6aa
JW		 3195 unsigned int entry, pool_size = 0;
3196 bfd_boolean padding_slot_p = FALSE;
e56c722b 3197 unsigned imm1 = 0;
8335d6aa
JW		 3198 unsigned imm2 = 0;
3199
3200 if (nbytes == 8)
3201 {
3202 imm1 = inst.operands[1].imm;
3203 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3204 : inst.reloc.exp.X_unsigned ? 0
2569ceb0 3205 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
8335d6aa
JW		 3206 if (target_big_endian)
3207 {
3208 imm1 = imm2;
3209 imm2 = inst.operands[1].imm;
3210 }
3211 }
b99bd4ef 3212
c19d1205
ZW		 3213 pool = find_or_make_literal_pool ();
3214
3215 /* Check if this literal value is already in the pool. */
3216 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3217 {
8335d6aa
JW		 3218 if (nbytes == 4)
3219 {
3220 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3221 && (inst.reloc.exp.X_op == O_constant)
3222 && (pool->literals[entry].X_add_number
3223 == inst.reloc.exp.X_add_number)
3224 && (pool->literals[entry].X_md == nbytes)
3225 && (pool->literals[entry].X_unsigned
3226 == inst.reloc.exp.X_unsigned))
3227 break;
3228
3229 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3230 && (inst.reloc.exp.X_op == O_symbol)
3231 && (pool->literals[entry].X_add_number
3232 == inst.reloc.exp.X_add_number)
3233 && (pool->literals[entry].X_add_symbol
3234 == inst.reloc.exp.X_add_symbol)
3235 && (pool->literals[entry].X_op_symbol
3236 == inst.reloc.exp.X_op_symbol)
3237 && (pool->literals[entry].X_md == nbytes))
3238 break;
3239 }
3240 else if ((nbytes == 8)
3241 && !(pool_size & 0x7)
3242 && ((entry + 1) != pool->next_free_entry)
3243 && (pool->literals[entry].X_op == O_constant)
19f2f6a9 3244 && (pool->literals[entry].X_add_number == (offsetT) imm1)
8335d6aa
JW		 3245 && (pool->literals[entry].X_unsigned
3246 == inst.reloc.exp.X_unsigned)
3247 && (pool->literals[entry + 1].X_op == O_constant)
19f2f6a9 3248 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
8335d6aa
JW		 3249 && (pool->literals[entry + 1].X_unsigned
3250 == inst.reloc.exp.X_unsigned))
c19d1205
ZW		 3251 break;
3252
8335d6aa
JW		 3253 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3254 if (padding_slot_p && (nbytes == 4))
c19d1205 3255 break;
8335d6aa
JW		 3256
3257 pool_size += 4;
b99bd4ef
NC		 3258 }
3259
c19d1205
ZW		 3260 /* Do we need to create a new entry? */
3261 if (entry == pool->next_free_entry)
3262 {
3263 if (entry >= MAX_LITERAL_POOL_SIZE)
3264 {
3265 inst.error = _("literal pool overflow");
3266 return FAIL;
3267 }
3268
8335d6aa
JW		 3269 if (nbytes == 8)
3270 {
3271 /* For 8-byte entries, we align to an 8-byte boundary,
3272 and split it into two 4-byte entries, because on 32-bit
3273 host, 8-byte constants are treated as big num, thus
3274 saved in "generic_bignum" which will be overwritten
3275 by later assignments.
3276
3277 We also need to make sure there is enough space for
3278 the split.
3279
3280 We also check to make sure the literal operand is a
3281 constant number. */
19f2f6a9
JW		 3282 if (!(inst.reloc.exp.X_op == O_constant
3283 || inst.reloc.exp.X_op == O_big))
8335d6aa
JW		 3284 {
3285 inst.error = _("invalid type for literal pool");
3286 return FAIL;
3287 }
3288 else if (pool_size & 0x7)
3289 {
3290 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3291 {
3292 inst.error = _("literal pool overflow");
3293 return FAIL;
3294 }
3295
3296 pool->literals[entry] = inst.reloc.exp;
3297 pool->literals[entry].X_add_number = 0;
3298 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3299 pool->next_free_entry += 1;
3300 pool_size += 4;
3301 }
3302 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3303 {
3304 inst.error = _("literal pool overflow");
3305 return FAIL;
3306 }
3307
3308 pool->literals[entry] = inst.reloc.exp;
3309 pool->literals[entry].X_op = O_constant;
3310 pool->literals[entry].X_add_number = imm1;
3311 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3312 pool->literals[entry++].X_md = 4;
3313 pool->literals[entry] = inst.reloc.exp;
3314 pool->literals[entry].X_op = O_constant;
3315 pool->literals[entry].X_add_number = imm2;
3316 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3317 pool->literals[entry].X_md = 4;
3318 pool->alignment = 3;
3319 pool->next_free_entry += 1;
3320 }
3321 else
3322 {
3323 pool->literals[entry] = inst.reloc.exp;
3324 pool->literals[entry].X_md = 4;
3325 }
3326
a8040cf2
NC		 3327#ifdef OBJ_ELF
3328 /* PR ld/12974: Record the location of the first source line to reference
3329 this entry in the literal pool. If it turns out during linking that the
3330 symbol does not exist we will be able to give an accurate line number for
3331 the (first use of the) missing reference. */
3332 if (debug_type == DEBUG_DWARF2)
3333 dwarf2_where (pool->locs + entry);
3334#endif
c19d1205
ZW		 3335 pool->next_free_entry += 1;
3336 }
8335d6aa
JW		 3337 else if (padding_slot_p)
3338 {
3339 pool->literals[entry] = inst.reloc.exp;
3340 pool->literals[entry].X_md = nbytes;
3341 }
b99bd4ef 3342
c19d1205 3343 inst.reloc.exp.X_op = O_symbol;
8335d6aa 3344 inst.reloc.exp.X_add_number = pool_size;
c19d1205 3345 inst.reloc.exp.X_add_symbol = pool->symbol;
b99bd4ef 3346
c19d1205 3347 return SUCCESS;
b99bd4ef
NC		 3348}
3349
2e6976a8
DG		 3350bfd_boolean
3351tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest)
3352{
3353 bfd_boolean ret = TRUE;
3354
3355 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3356 {
3357 const char *label = rest;
3358
3359 while (!is_end_of_line[(int) label[-1]])
3360 --label;
3361
3362 if (*label == '.')
3363 {
3364 as_bad (_("Invalid label '%s'"), label);
3365 ret = FALSE;
3366 }
3367
3368 asmfunc_debug (label);
3369
3370 asmfunc_state = WAITING_ENDASMFUNC;
3371 }
3372
3373 return ret;
3374}
3375
c19d1205
ZW		 3376/* Can't use symbol_new here, so have to create a symbol and then at
3377 a later date assign it a value. Thats what these functions do. */
e16bb312 3378
c19d1205
ZW		 3379static void
3380symbol_locate (symbolS * symbolP,
3381 const char * name, /* It is copied, the caller can modify. */
3382 segT segment, /* Segment identifier (SEG_<something>). */
3383 valueT valu, /* Symbol value. */
3384 fragS * frag) /* Associated fragment. */
3385{
e57e6ddc 3386 size_t name_length;
c19d1205 3387 char * preserved_copy_of_name;
e16bb312 3388
c19d1205
ZW		 3389 name_length = strlen (name) + 1; /* +1 for \0. */
3390 obstack_grow (&notes, name, name_length);
21d799b5 3391 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3392
c19d1205
ZW		 3393#ifdef tc_canonicalize_symbol_name
3394 preserved_copy_of_name =
3395 tc_canonicalize_symbol_name (preserved_copy_of_name);
3396#endif
b99bd4ef 3397
c19d1205 3398 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3399
c19d1205
ZW		 3400 S_SET_SEGMENT (symbolP, segment);
3401 S_SET_VALUE (symbolP, valu);
3402 symbol_clear_list_pointers (symbolP);
b99bd4ef 3403
c19d1205 3404 symbol_set_frag (symbolP, frag);
b99bd4ef 3405
c19d1205
ZW		 3406 /* Link to end of symbol chain. */
3407 {
3408 extern int symbol_table_frozen;
b99bd4ef 3409
c19d1205
ZW		 3410 if (symbol_table_frozen)
3411 abort ();
3412 }
b99bd4ef 3413
c19d1205 3414 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3415
c19d1205 3416 obj_symbol_new_hook (symbolP);
b99bd4ef 3417
c19d1205
ZW		 3418#ifdef tc_symbol_new_hook
3419 tc_symbol_new_hook (symbolP);
3420#endif
3421
3422#ifdef DEBUG_SYMS
3423 verify_symbol_chain (symbol_rootP, symbol_lastP);
3424#endif /* DEBUG_SYMS */
b99bd4ef
NC		 3425}
3426
c19d1205
ZW		 3427static void
3428s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3429{
c19d1205
ZW		 3430 unsigned int entry;
3431 literal_pool * pool;
3432 char sym_name[20];
b99bd4ef 3433
c19d1205
ZW		 3434 pool = find_literal_pool ();
3435 if (pool == NULL
3436 || pool->symbol == NULL
3437 || pool->next_free_entry == 0)
3438 return;
b99bd4ef 3439
c19d1205
ZW		 3440 /* Align pool as you have word accesses.
3441 Only make a frag if we have to. */
3442 if (!need_pass_2)
8335d6aa 3443 frag_align (pool->alignment, 0, 0);
b99bd4ef 3444
c19d1205 3445 record_alignment (now_seg, 2);
b99bd4ef 3446
aaca88ef 3447#ifdef OBJ_ELF
47fc6e36
WN		 3448 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3449 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
aaca88ef 3450#endif
c19d1205 3451 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3452
c19d1205
ZW		 3453 symbol_locate (pool->symbol, sym_name, now_seg,
3454 (valueT) frag_now_fix (), frag_now);
3455 symbol_table_insert (pool->symbol);
b99bd4ef 3456
c19d1205 3457 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3458
c19d1205
ZW		 3459#if defined OBJ_COFF || defined OBJ_ELF
3460 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3461#endif
6c43fab6 3462
c19d1205 3463 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC		 3464 {
3465#ifdef OBJ_ELF
3466 if (debug_type == DEBUG_DWARF2)
3467 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3468#endif
3469 /* First output the expression in the instruction to the pool. */
8335d6aa
JW		 3470 emit_expr (&(pool->literals[entry]),
3471 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
a8040cf2 3472 }
b99bd4ef 3473
c19d1205
ZW		 3474 /* Mark the pool as empty. */
3475 pool->next_free_entry = 0;
3476 pool->symbol = NULL;
b99bd4ef
NC		 3477}
3478
c19d1205
ZW		 3479#ifdef OBJ_ELF
3480/* Forward declarations for functions below, in the MD interface
3481 section. */
3482static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3483static valueT create_unwind_entry (int);
3484static void start_unwind_section (const segT, int);
3485static void add_unwind_opcode (valueT, int);
3486static void flush_pending_unwind (void);
b99bd4ef 3487
c19d1205 3488/* Directives: Data. */
b99bd4ef 3489
c19d1205
ZW		 3490static void
3491s_arm_elf_cons (int nbytes)
3492{
3493 expressionS exp;
b99bd4ef 3494
c19d1205
ZW		 3495#ifdef md_flush_pending_output
3496 md_flush_pending_output ();
3497#endif
b99bd4ef 3498
c19d1205 3499 if (is_it_end_of_statement ())
b99bd4ef 3500 {
c19d1205
ZW		 3501 demand_empty_rest_of_line ();
3502 return;
b99bd4ef
NC		 3503 }
3504
c19d1205
ZW		 3505#ifdef md_cons_align
3506 md_cons_align (nbytes);
3507#endif
b99bd4ef 3508
c19d1205
ZW		 3509 mapping_state (MAP_DATA);
3510 do
b99bd4ef 3511 {
c19d1205
ZW		 3512 int reloc;
3513 char *base = input_line_pointer;
b99bd4ef 3514
c19d1205 3515 expression (& exp);
b99bd4ef 3516
c19d1205
ZW		 3517 if (exp.X_op != O_symbol)
3518 emit_expr (&exp, (unsigned int) nbytes);
3519 else
3520 {
3521 char *before_reloc = input_line_pointer;
3522 reloc = parse_reloc (&input_line_pointer);
3523 if (reloc == -1)
3524 {
3525 as_bad (_("unrecognized relocation suffix"));
3526 ignore_rest_of_line ();
3527 return;
3528 }
3529 else if (reloc == BFD_RELOC_UNUSED)
3530 emit_expr (&exp, (unsigned int) nbytes);
3531 else
3532 {
21d799b5 3533 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM		 3534 bfd_reloc_type_lookup (stdoutput,
3535 (bfd_reloc_code_real_type) reloc);
c19d1205 3536 int size = bfd_get_reloc_size (howto);
b99bd4ef 3537
2fc8bdac
ZW		 3538 if (reloc == BFD_RELOC_ARM_PLT32)
3539 {
3540 as_bad (_("(plt) is only valid on branch targets"));
3541 reloc = BFD_RELOC_UNUSED;
3542 size = 0;
3543 }
3544
c19d1205 3545 if (size > nbytes)
2fc8bdac 3546 as_bad (_("%s relocations do not fit in %d bytes"),
c19d1205
ZW		 3547 howto->name, nbytes);
3548 else
3549 {
3550 /* We've parsed an expression stopping at O_symbol.
3551 But there may be more expression left now that we
3552 have parsed the relocation marker. Parse it again.
3553 XXX Surely there is a cleaner way to do this. */
3554 char *p = input_line_pointer;
3555 int offset;
21d799b5 3556 char *save_buf = (char *) alloca (input_line_pointer - base);
c19d1205
ZW		 3557 memcpy (save_buf, base, input_line_pointer - base);
3558 memmove (base + (input_line_pointer - before_reloc),
3559 base, before_reloc - base);
3560
3561 input_line_pointer = base + (input_line_pointer-before_reloc);
3562 expression (&exp);
3563 memcpy (base, save_buf, p - base);
3564
3565 offset = nbytes - size;
4b1a927e
AM		 3566 p = frag_more (nbytes);
3567 memset (p, 0, nbytes);
c19d1205 3568 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3569 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
c19d1205
ZW		 3570 }
3571 }
3572 }
b99bd4ef 3573 }
c19d1205 3574 while (*input_line_pointer++ == ',');
b99bd4ef 3575
c19d1205
ZW		 3576 /* Put terminator back into stream. */
3577 input_line_pointer --;
3578 demand_empty_rest_of_line ();
b99bd4ef
NC		 3579}
3580
c921be7d
NC		 3581/* Emit an expression containing a 32-bit thumb instruction.
3582 Implementation based on put_thumb32_insn. */
3583
3584static void
3585emit_thumb32_expr (expressionS * exp)
3586{
3587 expressionS exp_high = *exp;
3588
3589 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3590 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3591 exp->X_add_number &= 0xffff;
3592 emit_expr (exp, (unsigned int) THUMB_SIZE);
3593}
3594
3595/* Guess the instruction size based on the opcode. */
3596
3597static int
3598thumb_insn_size (int opcode)
3599{
3600 if ((unsigned int) opcode < 0xe800u)
3601 return 2;
3602 else if ((unsigned int) opcode >= 0xe8000000u)
3603 return 4;
3604 else
3605 return 0;
3606}
3607
3608static bfd_boolean
3609emit_insn (expressionS *exp, int nbytes)
3610{
3611 int size = 0;
3612
3613 if (exp->X_op == O_constant)
3614 {
3615 size = nbytes;
3616
3617 if (size == 0)
3618 size = thumb_insn_size (exp->X_add_number);
3619
3620 if (size != 0)
3621 {
3622 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3623 {
3624 as_bad (_(".inst.n operand too big. "\
3625 "Use .inst.w instead"));
3626 size = 0;
3627 }
3628 else
3629 {
3630 if (now_it.state == AUTOMATIC_IT_BLOCK)
3631 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3632 else
3633 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3634
3635 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3636 emit_thumb32_expr (exp);
3637 else
3638 emit_expr (exp, (unsigned int) size);
3639
3640 it_fsm_post_encode ();
3641 }
3642 }
3643 else
3644 as_bad (_("cannot determine Thumb instruction size. " \
3645 "Use .inst.n/.inst.w instead"));
3646 }
3647 else
3648 as_bad (_("constant expression required"));
3649
3650 return (size != 0);
3651}
3652
3653/* Like s_arm_elf_cons but do not use md_cons_align and
3654 set the mapping state to MAP_ARM/MAP_THUMB. */
3655
3656static void
3657s_arm_elf_inst (int nbytes)
3658{
3659 if (is_it_end_of_statement ())
3660 {
3661 demand_empty_rest_of_line ();
3662 return;
3663 }
3664
3665 /* Calling mapping_state () here will not change ARM/THUMB,
3666 but will ensure not to be in DATA state. */
3667
3668 if (thumb_mode)
3669 mapping_state (MAP_THUMB);
3670 else
3671 {
3672 if (nbytes != 0)
3673 {
3674 as_bad (_("width suffixes are invalid in ARM mode"));
3675 ignore_rest_of_line ();
3676 return;
3677 }
3678
3679 nbytes = 4;
3680
3681 mapping_state (MAP_ARM);
3682 }
3683
3684 do
3685 {
3686 expressionS exp;
3687
3688 expression (& exp);
3689
3690 if (! emit_insn (& exp, nbytes))
3691 {
3692 ignore_rest_of_line ();
3693 return;
3694 }
3695 }
3696 while (*input_line_pointer++ == ',');
3697
3698 /* Put terminator back into stream. */
3699 input_line_pointer --;
3700 demand_empty_rest_of_line ();
3701}
b99bd4ef 3702
c19d1205 3703/* Parse a .rel31 directive. */
b99bd4ef 3704
c19d1205
ZW		 3705static void
3706s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3707{
3708 expressionS exp;
3709 char *p;
3710 valueT highbit;
b99bd4ef 3711
c19d1205
ZW		 3712 highbit = 0;
3713 if (*input_line_pointer == '1')
3714 highbit = 0x80000000;
3715 else if (*input_line_pointer != '0')
3716 as_bad (_("expected 0 or 1"));
b99bd4ef 3717
c19d1205
ZW		 3718 input_line_pointer++;
3719 if (*input_line_pointer != ',')
3720 as_bad (_("missing comma"));
3721 input_line_pointer++;
b99bd4ef 3722
c19d1205
ZW		 3723#ifdef md_flush_pending_output
3724 md_flush_pending_output ();
3725#endif
b99bd4ef 3726
c19d1205
ZW		 3727#ifdef md_cons_align
3728 md_cons_align (4);
3729#endif
b99bd4ef 3730
c19d1205 3731 mapping_state (MAP_DATA);
b99bd4ef 3732
c19d1205 3733 expression (&exp);
b99bd4ef 3734
c19d1205
ZW		 3735 p = frag_more (4);
3736 md_number_to_chars (p, highbit, 4);
3737 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3738 BFD_RELOC_ARM_PREL31);
b99bd4ef 3739
c19d1205 3740 demand_empty_rest_of_line ();
b99bd4ef
NC		 3741}
3742
c19d1205 3743/* Directives: AEABI stack-unwind tables. */
b99bd4ef 3744
c19d1205 3745/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 3746
c19d1205
ZW		 3747static void
3748s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3749{
3750 demand_empty_rest_of_line ();
921e5f0a
PB		 3751 if (unwind.proc_start)
3752 {
c921be7d 3753 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB		 3754 return;
3755 }
3756
c19d1205
ZW		 3757 /* Mark the start of the function. */
3758 unwind.proc_start = expr_build_dot ();
b99bd4ef 3759
c19d1205
ZW		 3760 /* Reset the rest of the unwind info. */
3761 unwind.opcode_count = 0;
3762 unwind.table_entry = NULL;
3763 unwind.personality_routine = NULL;
3764 unwind.personality_index = -1;
3765 unwind.frame_size = 0;
3766 unwind.fp_offset = 0;
fdfde340 3767 unwind.fp_reg = REG_SP;
c19d1205
ZW		 3768 unwind.fp_used = 0;
3769 unwind.sp_restored = 0;
3770}
b99bd4ef 3771
b99bd4ef 3772
c19d1205
ZW		 3773/* Parse a handlerdata directive. Creates the exception handling table entry
3774 for the function. */
b99bd4ef 3775
c19d1205
ZW		 3776static void
3777s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3778{
3779 demand_empty_rest_of_line ();
921e5f0a 3780 if (!unwind.proc_start)
c921be7d 3781 as_bad (MISSING_FNSTART);
921e5f0a 3782
c19d1205 3783 if (unwind.table_entry)
6decc662 3784 as_bad (_("duplicate .handlerdata directive"));
f02232aa 3785
c19d1205
ZW		 3786 create_unwind_entry (1);
3787}
a737bd4d 3788
c19d1205 3789/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 3790
c19d1205
ZW		 3791static void
3792s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3793{
3794 long where;
3795 char *ptr;
3796 valueT val;
940b5ce0 3797 unsigned int marked_pr_dependency;
f02232aa 3798
c19d1205 3799 demand_empty_rest_of_line ();
f02232aa 3800
921e5f0a
PB		 3801 if (!unwind.proc_start)
3802 {
c921be7d 3803 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB		 3804 return;
3805 }
3806
c19d1205
ZW		 3807 /* Add eh table entry. */
3808 if (unwind.table_entry == NULL)
3809 val = create_unwind_entry (0);
3810 else
3811 val = 0;
f02232aa 3812
c19d1205
ZW		 3813 /* Add index table entry. This is two words. */
3814 start_unwind_section (unwind.saved_seg, 1);
3815 frag_align (2, 0, 0);
3816 record_alignment (now_seg, 2);
b99bd4ef 3817
c19d1205 3818 ptr = frag_more (8);
5011093d 3819 memset (ptr, 0, 8);
c19d1205 3820 where = frag_now_fix () - 8;
f02232aa 3821
c19d1205
ZW		 3822 /* Self relative offset of the function start. */
3823 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3824 BFD_RELOC_ARM_PREL31);
f02232aa 3825
c19d1205
ZW		 3826 /* Indicate dependency on EHABI-defined personality routines to the
3827 linker, if it hasn't been done already. */
940b5ce0
DJ		 3828 marked_pr_dependency
3829 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW		 3830 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3831 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3832 {
5f4273c7
NC		 3833 static const char *const name[] =
3834 {
3835 "__aeabi_unwind_cpp_pr0",
3836 "__aeabi_unwind_cpp_pr1",
3837 "__aeabi_unwind_cpp_pr2"
3838 };
c19d1205
ZW		 3839 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3840 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 3841 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 3842 |= 1 << unwind.personality_index;
c19d1205 3843 }
f02232aa 3844
c19d1205
ZW		 3845 if (val)
3846 /* Inline exception table entry. */
3847 md_number_to_chars (ptr + 4, val, 4);
3848 else
3849 /* Self relative offset of the table entry. */
3850 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3851 BFD_RELOC_ARM_PREL31);
f02232aa 3852
c19d1205
ZW		 3853 /* Restore the original section. */
3854 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB		 3855
3856 unwind.proc_start = NULL;
c19d1205 3857}
f02232aa 3858
f02232aa 3859
c19d1205 3860/* Parse an unwind_cantunwind directive. */
b99bd4ef 3861
c19d1205
ZW		 3862static void
3863s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3864{
3865 demand_empty_rest_of_line ();
921e5f0a 3866 if (!unwind.proc_start)
c921be7d 3867 as_bad (MISSING_FNSTART);
921e5f0a 3868
c19d1205
ZW		 3869 if (unwind.personality_routine || unwind.personality_index != -1)
3870 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 3871
c19d1205
ZW		 3872 unwind.personality_index = -2;
3873}
b99bd4ef 3874
b99bd4ef 3875
c19d1205 3876/* Parse a personalityindex directive. */
b99bd4ef 3877
c19d1205
ZW		 3878static void
3879s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3880{
3881 expressionS exp;
b99bd4ef 3882
921e5f0a 3883 if (!unwind.proc_start)
c921be7d 3884 as_bad (MISSING_FNSTART);
921e5f0a 3885
c19d1205
ZW		 3886 if (unwind.personality_routine || unwind.personality_index != -1)
3887 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 3888
c19d1205 3889 expression (&exp);
b99bd4ef 3890
c19d1205
ZW		 3891 if (exp.X_op != O_constant
3892 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 3893 {
c19d1205
ZW		 3894 as_bad (_("bad personality routine number"));
3895 ignore_rest_of_line ();
3896 return;
b99bd4ef
NC		 3897 }
3898
c19d1205 3899 unwind.personality_index = exp.X_add_number;
b99bd4ef 3900
c19d1205
ZW		 3901 demand_empty_rest_of_line ();
3902}
e16bb312 3903
e16bb312 3904
c19d1205 3905/* Parse a personality directive. */
e16bb312 3906
c19d1205
ZW		 3907static void
3908s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3909{
3910 char *name, *p, c;
a737bd4d 3911
921e5f0a 3912 if (!unwind.proc_start)
c921be7d 3913 as_bad (MISSING_FNSTART);
921e5f0a 3914
c19d1205
ZW		 3915 if (unwind.personality_routine || unwind.personality_index != -1)
3916 as_bad (_("duplicate .personality directive"));
a737bd4d 3917
c19d1205
ZW		 3918 name = input_line_pointer;
3919 c = get_symbol_end ();
3920 p = input_line_pointer;
3921 unwind.personality_routine = symbol_find_or_make (name);
3922 *p = c;
3923 demand_empty_rest_of_line ();
3924}
e16bb312 3925
e16bb312 3926
c19d1205 3927/* Parse a directive saving core registers. */
e16bb312 3928
c19d1205
ZW		 3929static void
3930s_arm_unwind_save_core (void)
e16bb312 3931{
c19d1205
ZW		 3932 valueT op;
3933 long range;
3934 int n;
e16bb312 3935
c19d1205
ZW		 3936 range = parse_reg_list (&input_line_pointer);
3937 if (range == FAIL)
e16bb312 3938 {
c19d1205
ZW		 3939 as_bad (_("expected register list"));
3940 ignore_rest_of_line ();
3941 return;
3942 }
e16bb312 3943
c19d1205 3944 demand_empty_rest_of_line ();
e16bb312 3945
c19d1205
ZW		 3946 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3947 into .unwind_save {..., sp...}. We aren't bothered about the value of
3948 ip because it is clobbered by calls. */
3949 if (unwind.sp_restored && unwind.fp_reg == 12
3950 && (range & 0x3000) == 0x1000)
3951 {
3952 unwind.opcode_count--;
3953 unwind.sp_restored = 0;
3954 range = (range | 0x2000) & ~0x1000;
3955 unwind.pending_offset = 0;
3956 }
e16bb312 3957
01ae4198
DJ		 3958 /* Pop r4-r15. */
3959 if (range & 0xfff0)
c19d1205 3960 {
01ae4198
DJ		 3961 /* See if we can use the short opcodes. These pop a block of up to 8
3962 registers starting with r4, plus maybe r14. */
3963 for (n = 0; n < 8; n++)
3964 {
3965 /* Break at the first non-saved register. */
3966 if ((range & (1 << (n + 4))) == 0)
3967 break;
3968 }
3969 /* See if there are any other bits set. */
3970 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3971 {
3972 /* Use the long form. */
3973 op = 0x8000 | ((range >> 4) & 0xfff);
3974 add_unwind_opcode (op, 2);
3975 }
0dd132b6 3976 else
01ae4198
DJ		 3977 {
3978 /* Use the short form. */
3979 if (range & 0x4000)
3980 op = 0xa8; /* Pop r14. */
3981 else
3982 op = 0xa0; /* Do not pop r14. */
3983 op |= (n - 1);
3984 add_unwind_opcode (op, 1);
3985 }
c19d1205 3986 }
0dd132b6 3987
c19d1205
ZW		 3988 /* Pop r0-r3. */
3989 if (range & 0xf)
3990 {
3991 op = 0xb100 | (range & 0xf);
3992 add_unwind_opcode (op, 2);
0dd132b6
NC		 3993 }
3994
c19d1205
ZW		 3995 /* Record the number of bytes pushed. */
3996 for (n = 0; n < 16; n++)
3997 {
3998 if (range & (1 << n))
3999 unwind.frame_size += 4;
4000 }
0dd132b6
NC		 4001}
4002
c19d1205
ZW		 4003
4004/* Parse a directive saving FPA registers. */
b99bd4ef
NC		 4005
4006static void
c19d1205 4007s_arm_unwind_save_fpa (int reg)
b99bd4ef 4008{
c19d1205
ZW		 4009 expressionS exp;
4010 int num_regs;
4011 valueT op;
b99bd4ef 4012
c19d1205
ZW		 4013 /* Get Number of registers to transfer. */
4014 if (skip_past_comma (&input_line_pointer) != FAIL)
4015 expression (&exp);
4016 else
4017 exp.X_op = O_illegal;
b99bd4ef 4018
c19d1205 4019 if (exp.X_op != O_constant)
b99bd4ef 4020 {
c19d1205
ZW		 4021 as_bad (_("expected , <constant>"));
4022 ignore_rest_of_line ();
b99bd4ef
NC		 4023 return;
4024 }
4025
c19d1205
ZW		 4026 num_regs = exp.X_add_number;
4027
4028 if (num_regs < 1 || num_regs > 4)
b99bd4ef 4029 {
c19d1205
ZW		 4030 as_bad (_("number of registers must be in the range [1:4]"));
4031 ignore_rest_of_line ();
b99bd4ef
NC		 4032 return;
4033 }
4034
c19d1205 4035 demand_empty_rest_of_line ();
b99bd4ef 4036
c19d1205
ZW		 4037 if (reg == 4)
4038 {
4039 /* Short form. */
4040 op = 0xb4 | (num_regs - 1);
4041 add_unwind_opcode (op, 1);
4042 }
b99bd4ef
NC		 4043 else
4044 {
c19d1205
ZW		 4045 /* Long form. */
4046 op = 0xc800 | (reg << 4) | (num_regs - 1);
4047 add_unwind_opcode (op, 2);
b99bd4ef 4048 }
c19d1205 4049 unwind.frame_size += num_regs * 12;
b99bd4ef
NC		 4050}
4051
c19d1205 4052
fa073d69
MS		 4053/* Parse a directive saving VFP registers for ARMv6 and above. */
4054
4055static void
4056s_arm_unwind_save_vfp_armv6 (void)
4057{
4058 int count;
4059 unsigned int start;
4060 valueT op;
4061 int num_vfpv3_regs = 0;
4062 int num_regs_below_16;
4063
4064 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
4065 if (count == FAIL)
4066 {
4067 as_bad (_("expected register list"));
4068 ignore_rest_of_line ();
4069 return;
4070 }
4071
4072 demand_empty_rest_of_line ();
4073
4074 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4075 than FSTMX/FLDMX-style ones). */
4076
4077 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4078 if (start >= 16)
4079 num_vfpv3_regs = count;
4080 else if (start + count > 16)
4081 num_vfpv3_regs = start + count - 16;
4082
4083 if (num_vfpv3_regs > 0)
4084 {
4085 int start_offset = start > 16 ? start - 16 : 0;
4086 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4087 add_unwind_opcode (op, 2);
4088 }
4089
4090 /* Generate opcode for registers numbered in the range 0 .. 15. */
4091 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 4092 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS		 4093 if (num_regs_below_16 > 0)
4094 {
4095 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4096 add_unwind_opcode (op, 2);
4097 }
4098
4099 unwind.frame_size += count * 8;
4100}
4101
4102
4103/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC		 4104
4105static void
c19d1205 4106s_arm_unwind_save_vfp (void)
b99bd4ef 4107{
c19d1205 4108 int count;
ca3f61f7 4109 unsigned int reg;
c19d1205 4110 valueT op;
b99bd4ef 4111
5287ad62 4112 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
c19d1205 4113 if (count == FAIL)
b99bd4ef 4114 {
c19d1205
ZW		 4115 as_bad (_("expected register list"));
4116 ignore_rest_of_line ();
b99bd4ef
NC		 4117 return;
4118 }
4119
c19d1205 4120 demand_empty_rest_of_line ();
b99bd4ef 4121
c19d1205 4122 if (reg == 8)
b99bd4ef 4123 {
c19d1205
ZW		 4124 /* Short form. */
4125 op = 0xb8 | (count - 1);
4126 add_unwind_opcode (op, 1);
b99bd4ef 4127 }
c19d1205 4128 else
b99bd4ef 4129 {
c19d1205
ZW		 4130 /* Long form. */
4131 op = 0xb300 | (reg << 4) | (count - 1);
4132 add_unwind_opcode (op, 2);
b99bd4ef 4133 }
c19d1205
ZW		 4134 unwind.frame_size += count * 8 + 4;
4135}
b99bd4ef 4136
b99bd4ef 4137
c19d1205
ZW		 4138/* Parse a directive saving iWMMXt data registers. */
4139
4140static void
4141s_arm_unwind_save_mmxwr (void)
4142{
4143 int reg;
4144 int hi_reg;
4145 int i;
4146 unsigned mask = 0;
4147 valueT op;
b99bd4ef 4148
c19d1205
ZW		 4149 if (*input_line_pointer == '{')
4150 input_line_pointer++;
b99bd4ef 4151
c19d1205 4152 do
b99bd4ef 4153 {
dcbf9037 4154 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 4155
c19d1205 4156 if (reg == FAIL)
b99bd4ef 4157 {
9b7132d3 4158 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 4159 goto error;
b99bd4ef
NC		 4160 }
4161
c19d1205
ZW		 4162 if (mask >> reg)
4163 as_tsktsk (_("register list not in ascending order"));
4164 mask |= 1 << reg;
b99bd4ef 4165
c19d1205
ZW		 4166 if (*input_line_pointer == '-')
4167 {
4168 input_line_pointer++;
dcbf9037 4169 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW		 4170 if (hi_reg == FAIL)
4171 {
9b7132d3 4172 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW		 4173 goto error;
4174 }
4175 else if (reg >= hi_reg)
4176 {
4177 as_bad (_("bad register range"));
4178 goto error;
4179 }
4180 for (; reg < hi_reg; reg++)
4181 mask |= 1 << reg;
4182 }
4183 }
4184 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4185
d996d970 4186 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4187
c19d1205 4188 demand_empty_rest_of_line ();
b99bd4ef 4189
708587a4 4190 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4191 the list. */
4192 flush_pending_unwind ();
b99bd4ef 4193
c19d1205 4194 for (i = 0; i < 16; i++)
b99bd4ef 4195 {
c19d1205
ZW		 4196 if (mask & (1 << i))
4197 unwind.frame_size += 8;
b99bd4ef
NC		 4198 }
4199
c19d1205
ZW		 4200 /* Attempt to combine with a previous opcode. We do this because gcc
4201 likes to output separate unwind directives for a single block of
4202 registers. */
4203 if (unwind.opcode_count > 0)
b99bd4ef 4204 {
c19d1205
ZW		 4205 i = unwind.opcodes[unwind.opcode_count - 1];
4206 if ((i & 0xf8) == 0xc0)
4207 {
4208 i &= 7;
4209 /* Only merge if the blocks are contiguous. */
4210 if (i < 6)
4211 {
4212 if ((mask & 0xfe00) == (1 << 9))
4213 {
4214 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4215 unwind.opcode_count--;
4216 }
4217 }
4218 else if (i == 6 && unwind.opcode_count >= 2)
4219 {
4220 i = unwind.opcodes[unwind.opcode_count - 2];
4221 reg = i >> 4;
4222 i &= 0xf;
b99bd4ef 4223
c19d1205
ZW		 4224 op = 0xffff << (reg - 1);
4225 if (reg > 0
87a1fd79 4226 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW		 4227 {
4228 op = (1 << (reg + i + 1)) - 1;
4229 op &= ~((1 << reg) - 1);
4230 mask |= op;
4231 unwind.opcode_count -= 2;
4232 }
4233 }
4234 }
b99bd4ef
NC		 4235 }
4236
c19d1205
ZW		 4237 hi_reg = 15;
4238 /* We want to generate opcodes in the order the registers have been
4239 saved, ie. descending order. */
4240 for (reg = 15; reg >= -1; reg--)
b99bd4ef 4241 {
c19d1205
ZW		 4242 /* Save registers in blocks. */
4243 if (reg < 0
4244 || !(mask & (1 << reg)))
4245 {
4246 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 4247 preceding block. */
c19d1205
ZW		 4248 if (reg != hi_reg)
4249 {
4250 if (reg == 9)
4251 {
4252 /* Short form. */
4253 op = 0xc0 | (hi_reg - 10);
4254 add_unwind_opcode (op, 1);
4255 }
4256 else
4257 {
4258 /* Long form. */
4259 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4260 add_unwind_opcode (op, 2);
4261 }
4262 }
4263 hi_reg = reg - 1;
4264 }
b99bd4ef
NC		 4265 }
4266
c19d1205
ZW		 4267 return;
4268error:
4269 ignore_rest_of_line ();
b99bd4ef
NC		 4270}
4271
4272static void
c19d1205 4273s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4274{
c19d1205
ZW		 4275 int reg;
4276 int hi_reg;
4277 unsigned mask = 0;
4278 valueT op;
b99bd4ef 4279
c19d1205
ZW		 4280 if (*input_line_pointer == '{')
4281 input_line_pointer++;
b99bd4ef 4282
477330fc
RM		 4283 skip_whitespace (input_line_pointer);
4284
c19d1205 4285 do
b99bd4ef 4286 {
dcbf9037 4287 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4288
c19d1205
ZW		 4289 if (reg == FAIL)
4290 {
9b7132d3 4291 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4292 goto error;
4293 }
b99bd4ef 4294
c19d1205
ZW		 4295 reg -= 8;
4296 if (mask >> reg)
4297 as_tsktsk (_("register list not in ascending order"));
4298 mask |= 1 << reg;
b99bd4ef 4299
c19d1205
ZW		 4300 if (*input_line_pointer == '-')
4301 {
4302 input_line_pointer++;
dcbf9037 4303 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW		 4304 if (hi_reg == FAIL)
4305 {
9b7132d3 4306 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4307 goto error;
4308 }
4309 else if (reg >= hi_reg)
4310 {
4311 as_bad (_("bad register range"));
4312 goto error;
4313 }
4314 for (; reg < hi_reg; reg++)
4315 mask |= 1 << reg;
4316 }
b99bd4ef 4317 }
c19d1205 4318 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4319
d996d970 4320 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4321
c19d1205
ZW		 4322 demand_empty_rest_of_line ();
4323
708587a4 4324 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4325 the list. */
4326 flush_pending_unwind ();
b99bd4ef 4327
c19d1205 4328 for (reg = 0; reg < 16; reg++)
b99bd4ef 4329 {
c19d1205
ZW		 4330 if (mask & (1 << reg))
4331 unwind.frame_size += 4;
b99bd4ef 4332 }
c19d1205
ZW		 4333 op = 0xc700 | mask;
4334 add_unwind_opcode (op, 2);
4335 return;
4336error:
4337 ignore_rest_of_line ();
b99bd4ef
NC		 4338}
4339
c19d1205 4340
fa073d69
MS		 4341/* Parse an unwind_save directive.
4342 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4343
b99bd4ef 4344static void
fa073d69 4345s_arm_unwind_save (int arch_v6)
b99bd4ef 4346{
c19d1205
ZW		 4347 char *peek;
4348 struct reg_entry *reg;
4349 bfd_boolean had_brace = FALSE;
b99bd4ef 4350
921e5f0a 4351 if (!unwind.proc_start)
c921be7d 4352 as_bad (MISSING_FNSTART);
921e5f0a 4353
c19d1205
ZW		 4354 /* Figure out what sort of save we have. */
4355 peek = input_line_pointer;
b99bd4ef 4356
c19d1205 4357 if (*peek == '{')
b99bd4ef 4358 {
c19d1205
ZW		 4359 had_brace = TRUE;
4360 peek++;
b99bd4ef
NC		 4361 }
4362
c19d1205 4363 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4364
c19d1205 4365 if (!reg)
b99bd4ef 4366 {
c19d1205
ZW		 4367 as_bad (_("register expected"));
4368 ignore_rest_of_line ();
b99bd4ef
NC		 4369 return;
4370 }
4371
c19d1205 4372 switch (reg->type)
b99bd4ef 4373 {
c19d1205
ZW		 4374 case REG_TYPE_FN:
4375 if (had_brace)
4376 {
4377 as_bad (_("FPA .unwind_save does not take a register list"));
4378 ignore_rest_of_line ();
4379 return;
4380 }
93ac2687 4381 input_line_pointer = peek;
c19d1205 4382 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4383 return;
c19d1205 4384
1f5afe1c
NC		 4385 case REG_TYPE_RN:
4386 s_arm_unwind_save_core ();
4387 return;
4388
fa073d69
MS		 4389 case REG_TYPE_VFD:
4390 if (arch_v6)
477330fc 4391 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4392 else
477330fc 4393 s_arm_unwind_save_vfp ();
fa073d69 4394 return;
1f5afe1c
NC		 4395
4396 case REG_TYPE_MMXWR:
4397 s_arm_unwind_save_mmxwr ();
4398 return;
4399
4400 case REG_TYPE_MMXWCG:
4401 s_arm_unwind_save_mmxwcg ();
4402 return;
c19d1205
ZW		 4403
4404 default:
4405 as_bad (_(".unwind_save does not support this kind of register"));
4406 ignore_rest_of_line ();
b99bd4ef 4407 }
c19d1205 4408}
b99bd4ef 4409
b99bd4ef 4410
c19d1205
ZW		 4411/* Parse an unwind_movsp directive. */
4412
4413static void
4414s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4415{
4416 int reg;
4417 valueT op;
4fa3602b 4418 int offset;
c19d1205 4419
921e5f0a 4420 if (!unwind.proc_start)
c921be7d 4421 as_bad (MISSING_FNSTART);
921e5f0a 4422
dcbf9037 4423 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4424 if (reg == FAIL)
b99bd4ef 4425 {
9b7132d3 4426 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4427 ignore_rest_of_line ();
b99bd4ef
NC		 4428 return;
4429 }
4fa3602b
PB		 4430
4431 /* Optional constant. */
4432 if (skip_past_comma (&input_line_pointer) != FAIL)
4433 {
4434 if (immediate_for_directive (&offset) == FAIL)
4435 return;
4436 }
4437 else
4438 offset = 0;
4439
c19d1205 4440 demand_empty_rest_of_line ();
b99bd4ef 4441
c19d1205 4442 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4443 {
c19d1205 4444 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC		 4445 return;
4446 }
4447
c19d1205
ZW		 4448 if (unwind.fp_reg != REG_SP)
4449 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4450
c19d1205
ZW		 4451 /* Generate opcode to restore the value. */
4452 op = 0x90 | reg;
4453 add_unwind_opcode (op, 1);
4454
4455 /* Record the information for later. */
4456 unwind.fp_reg = reg;
4fa3602b 4457 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4458 unwind.sp_restored = 1;
b05fe5cf
ZW		 4459}
4460
c19d1205
ZW		 4461/* Parse an unwind_pad directive. */
4462
b05fe5cf 4463static void
c19d1205 4464s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4465{
c19d1205 4466 int offset;
b05fe5cf 4467
921e5f0a 4468 if (!unwind.proc_start)
c921be7d 4469 as_bad (MISSING_FNSTART);
921e5f0a 4470
c19d1205
ZW		 4471 if (immediate_for_directive (&offset) == FAIL)
4472 return;
b99bd4ef 4473
c19d1205
ZW		 4474 if (offset & 3)
4475 {
4476 as_bad (_("stack increment must be multiple of 4"));
4477 ignore_rest_of_line ();
4478 return;
4479 }
b99bd4ef 4480
c19d1205
ZW		 4481 /* Don't generate any opcodes, just record the details for later. */
4482 unwind.frame_size += offset;
4483 unwind.pending_offset += offset;
4484
4485 demand_empty_rest_of_line ();
4486}
4487
4488/* Parse an unwind_setfp directive. */
4489
4490static void
4491s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4492{
c19d1205
ZW		 4493 int sp_reg;
4494 int fp_reg;
4495 int offset;
4496
921e5f0a 4497 if (!unwind.proc_start)
c921be7d 4498 as_bad (MISSING_FNSTART);
921e5f0a 4499
dcbf9037 4500 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW		 4501 if (skip_past_comma (&input_line_pointer) == FAIL)
4502 sp_reg = FAIL;
4503 else
dcbf9037 4504 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4505
c19d1205
ZW		 4506 if (fp_reg == FAIL || sp_reg == FAIL)
4507 {
4508 as_bad (_("expected <reg>, <reg>"));
4509 ignore_rest_of_line ();
4510 return;
4511 }
b99bd4ef 4512
c19d1205
ZW		 4513 /* Optional constant. */
4514 if (skip_past_comma (&input_line_pointer) != FAIL)
4515 {
4516 if (immediate_for_directive (&offset) == FAIL)
4517 return;
4518 }
4519 else
4520 offset = 0;
a737bd4d 4521
c19d1205 4522 demand_empty_rest_of_line ();
a737bd4d 4523
fdfde340 4524 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4525 {
c19d1205
ZW		 4526 as_bad (_("register must be either sp or set by a previous"
4527 "unwind_movsp directive"));
4528 return;
a737bd4d
NC		 4529 }
4530
c19d1205
ZW		 4531 /* Don't generate any opcodes, just record the information for later. */
4532 unwind.fp_reg = fp_reg;
4533 unwind.fp_used = 1;
fdfde340 4534 if (sp_reg == REG_SP)
c19d1205
ZW		 4535 unwind.fp_offset = unwind.frame_size - offset;
4536 else
4537 unwind.fp_offset -= offset;
a737bd4d
NC		 4538}
4539
c19d1205
ZW		 4540/* Parse an unwind_raw directive. */
4541
4542static void
4543s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4544{
c19d1205 4545 expressionS exp;
708587a4 4546 /* This is an arbitrary limit. */
c19d1205
ZW		 4547 unsigned char op[16];
4548 int count;
a737bd4d 4549
921e5f0a 4550 if (!unwind.proc_start)
c921be7d 4551 as_bad (MISSING_FNSTART);
921e5f0a 4552
c19d1205
ZW		 4553 expression (&exp);
4554 if (exp.X_op == O_constant
4555 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4556 {
c19d1205
ZW		 4557 unwind.frame_size += exp.X_add_number;
4558 expression (&exp);
4559 }
4560 else
4561 exp.X_op = O_illegal;
a737bd4d 4562
c19d1205
ZW		 4563 if (exp.X_op != O_constant)
4564 {
4565 as_bad (_("expected <offset>, <opcode>"));
4566 ignore_rest_of_line ();
4567 return;
4568 }
a737bd4d 4569
c19d1205 4570 count = 0;
a737bd4d 4571
c19d1205
ZW		 4572 /* Parse the opcode. */
4573 for (;;)
4574 {
4575 if (count >= 16)
4576 {
4577 as_bad (_("unwind opcode too long"));
4578 ignore_rest_of_line ();
a737bd4d 4579 }
c19d1205 4580 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4581 {
c19d1205
ZW		 4582 as_bad (_("invalid unwind opcode"));
4583 ignore_rest_of_line ();
4584 return;
a737bd4d 4585 }
c19d1205 4586 op[count++] = exp.X_add_number;
a737bd4d 4587
c19d1205
ZW		 4588 /* Parse the next byte. */
4589 if (skip_past_comma (&input_line_pointer) == FAIL)
4590 break;
a737bd4d 4591
c19d1205
ZW		 4592 expression (&exp);
4593 }
b99bd4ef 4594
c19d1205
ZW		 4595 /* Add the opcode bytes in reverse order. */
4596 while (count--)
4597 add_unwind_opcode (op[count], 1);
b99bd4ef 4598
c19d1205 4599 demand_empty_rest_of_line ();
b99bd4ef 4600}
ee065d83
PB		 4601
4602
4603/* Parse a .eabi_attribute directive. */
4604
4605static void
4606s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4607{
0420f52b 4608 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378
AS		 4609
4610 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4611 attributes_set_explicitly[tag] = 1;
ee065d83
PB		 4612}
4613
0855e32b
NS		 4614/* Emit a tls fix for the symbol. */
4615
4616static void
4617s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4618{
4619 char *p;
4620 expressionS exp;
4621#ifdef md_flush_pending_output
4622 md_flush_pending_output ();
4623#endif
4624
4625#ifdef md_cons_align
4626 md_cons_align (4);
4627#endif
4628
4629 /* Since we're just labelling the code, there's no need to define a
4630 mapping symbol. */
4631 expression (&exp);
4632 p = obstack_next_free (&frchain_now->frch_obstack);
4633 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4634 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4635 : BFD_RELOC_ARM_TLS_DESCSEQ);
4636}
cdf9ccec 4637#endif /* OBJ_ELF */
0855e32b 4638
ee065d83 4639static void s_arm_arch (int);
7a1d4c38 4640static void s_arm_object_arch (int);
ee065d83
PB		 4641static void s_arm_cpu (int);
4642static void s_arm_fpu (int);
69133863 4643static void s_arm_arch_extension (int);
b99bd4ef 4644
f0927246
NC		 4645#ifdef TE_PE
4646
4647static void
5f4273c7 4648pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC		 4649{
4650 expressionS exp;
4651
4652 do
4653 {
4654 expression (&exp);
4655 if (exp.X_op == O_symbol)
4656 exp.X_op = O_secrel;
4657
4658 emit_expr (&exp, 4);
4659 }
4660 while (*input_line_pointer++ == ',');
4661
4662 input_line_pointer--;
4663 demand_empty_rest_of_line ();
4664}
4665#endif /* TE_PE */
4666
c19d1205
ZW		 4667/* This table describes all the machine specific pseudo-ops the assembler
4668 has to support. The fields are:
4669 pseudo-op name without dot
4670 function to call to execute this pseudo-op
4671 Integer arg to pass to the function. */
b99bd4ef 4672
c19d1205 4673const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4674{
c19d1205
ZW		 4675 /* Never called because '.req' does not start a line. */
4676 { "req", s_req, 0 },
dcbf9037
JB		 4677 /* Following two are likewise never called. */
4678 { "dn", s_dn, 0 },
4679 { "qn", s_qn, 0 },
c19d1205
ZW		 4680 { "unreq", s_unreq, 0 },
4681 { "bss", s_bss, 0 },
4682 { "align", s_align, 0 },
4683 { "arm", s_arm, 0 },
4684 { "thumb", s_thumb, 0 },
4685 { "code", s_code, 0 },
4686 { "force_thumb", s_force_thumb, 0 },
4687 { "thumb_func", s_thumb_func, 0 },
4688 { "thumb_set", s_thumb_set, 0 },
4689 { "even", s_even, 0 },
4690 { "ltorg", s_ltorg, 0 },
4691 { "pool", s_ltorg, 0 },
4692 { "syntax", s_syntax, 0 },
8463be01
PB		 4693 { "cpu", s_arm_cpu, 0 },
4694 { "arch", s_arm_arch, 0 },
7a1d4c38 4695 { "object_arch", s_arm_object_arch, 0 },
8463be01 4696 { "fpu", s_arm_fpu, 0 },
69133863 4697 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 4698#ifdef OBJ_ELF
c921be7d
NC		 4699 { "word", s_arm_elf_cons, 4 },
4700 { "long", s_arm_elf_cons, 4 },
4701 { "inst.n", s_arm_elf_inst, 2 },
4702 { "inst.w", s_arm_elf_inst, 4 },
4703 { "inst", s_arm_elf_inst, 0 },
4704 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW		 4705 { "fnstart", s_arm_unwind_fnstart, 0 },
4706 { "fnend", s_arm_unwind_fnend, 0 },
4707 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4708 { "personality", s_arm_unwind_personality, 0 },
4709 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4710 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4711 { "save", s_arm_unwind_save, 0 },
fa073d69 4712 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW		 4713 { "movsp", s_arm_unwind_movsp, 0 },
4714 { "pad", s_arm_unwind_pad, 0 },
4715 { "setfp", s_arm_unwind_setfp, 0 },
4716 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 4717 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 4718 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW		 4719#else
4720 { "word", cons, 4},
f0927246
NC		 4721
4722 /* These are used for dwarf. */
4723 {"2byte", cons, 2},
4724 {"4byte", cons, 4},
4725 {"8byte", cons, 8},
4726 /* These are used for dwarf2. */
4727 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4728 { "loc", dwarf2_directive_loc, 0 },
4729 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW		 4730#endif
4731 { "extend", float_cons, 'x' },
4732 { "ldouble", float_cons, 'x' },
4733 { "packed", float_cons, 'p' },
f0927246
NC		 4734#ifdef TE_PE
4735 {"secrel32", pe_directive_secrel, 0},
4736#endif
2e6976a8
DG		 4737
4738 /* These are for compatibility with CodeComposer Studio. */
4739 {"ref", s_ccs_ref, 0},
4740 {"def", s_ccs_def, 0},
4741 {"asmfunc", s_ccs_asmfunc, 0},
4742 {"endasmfunc", s_ccs_endasmfunc, 0},
4743
c19d1205
ZW		 4744 { 0, 0, 0 }
4745};
4746\f
4747/* Parser functions used exclusively in instruction operands. */
b99bd4ef 4748
c19d1205
ZW		 4749/* Generic immediate-value read function for use in insn parsing.
4750 STR points to the beginning of the immediate (the leading #);
4751 VAL receives the value; if the value is outside [MIN, MAX]
4752 issue an error. PREFIX_OPT is true if the immediate prefix is
4753 optional. */
b99bd4ef 4754
c19d1205
ZW		 4755static int
4756parse_immediate (char **str, int *val, int min, int max,
4757 bfd_boolean prefix_opt)
4758{
4759 expressionS exp;
4760 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4761 if (exp.X_op != O_constant)
b99bd4ef 4762 {
c19d1205
ZW		 4763 inst.error = _("constant expression required");
4764 return FAIL;
4765 }
b99bd4ef 4766
c19d1205
ZW		 4767 if (exp.X_add_number < min || exp.X_add_number > max)
4768 {
4769 inst.error = _("immediate value out of range");
4770 return FAIL;
4771 }
b99bd4ef 4772
c19d1205
ZW		 4773 *val = exp.X_add_number;
4774 return SUCCESS;
4775}
b99bd4ef 4776
5287ad62 4777/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 4778 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB		 4779 instructions. Puts the result directly in inst.operands[i]. */
4780
4781static int
8335d6aa
JW		 4782parse_big_immediate (char **str, int i, expressionS *in_exp,
4783 bfd_boolean allow_symbol_p)
5287ad62
JB		 4784{
4785 expressionS exp;
8335d6aa 4786 expressionS *exp_p = in_exp ? in_exp : &exp;
5287ad62
JB		 4787 char *ptr = *str;
4788
8335d6aa 4789 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5287ad62 4790
8335d6aa 4791 if (exp_p->X_op == O_constant)
036dc3f7 4792 {
8335d6aa 4793 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
036dc3f7
PB		 4794 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4795 O_constant. We have to be careful not to break compilation for
4796 32-bit X_add_number, though. */
8335d6aa 4797 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 4798 {
8335d6aa
JW		 4799 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4800 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
4801 & 0xffffffff);
036dc3f7
PB		 4802 inst.operands[i].regisimm = 1;
4803 }
4804 }
8335d6aa
JW		 4805 else if (exp_p->X_op == O_big
4806 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5287ad62
JB		 4807 {
4808 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 4809
5287ad62 4810 /* Bignums have their least significant bits in
477330fc
RM		 4811 generic_bignum[0]. Make sure we put 32 bits in imm and
4812 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 4813 gas_assert (parts != 0);
95b75c01
NC		 4814
4815 /* Make sure that the number is not too big.
4816 PR 11972: Bignums can now be sign-extended to the
4817 size of a .octa so check that the out of range bits
4818 are all zero or all one. */
8335d6aa 4819 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
95b75c01
NC		 4820 {
4821 LITTLENUM_TYPE m = -1;
4822
4823 if (generic_bignum[parts * 2] != 0
4824 && generic_bignum[parts * 2] != m)
4825 return FAIL;
4826
8335d6aa 4827 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
95b75c01
NC		 4828 if (generic_bignum[j] != generic_bignum[j-1])
4829 return FAIL;
4830 }
4831
5287ad62
JB		 4832 inst.operands[i].imm = 0;
4833 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 4834 inst.operands[i].imm |= generic_bignum[idx]
4835 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 4836 inst.operands[i].reg = 0;
4837 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 4838 inst.operands[i].reg |= generic_bignum[idx]
4839 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 4840 inst.operands[i].regisimm = 1;
4841 }
8335d6aa 4842 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5287ad62 4843 return FAIL;
5f4273c7 4844
5287ad62
JB		 4845 *str = ptr;
4846
4847 return SUCCESS;
4848}
4849
c19d1205
ZW		 4850/* Returns the pseudo-register number of an FPA immediate constant,
4851 or FAIL if there isn't a valid constant here. */
b99bd4ef 4852
c19d1205
ZW		 4853static int
4854parse_fpa_immediate (char ** str)
4855{
4856 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4857 char * save_in;
4858 expressionS exp;
4859 int i;
4860 int j;
b99bd4ef 4861
c19d1205
ZW		 4862 /* First try and match exact strings, this is to guarantee
4863 that some formats will work even for cross assembly. */
b99bd4ef 4864
c19d1205
ZW		 4865 for (i = 0; fp_const[i]; i++)
4866 {
4867 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 4868 {
c19d1205 4869 char *start = *str;
b99bd4ef 4870
c19d1205
ZW		 4871 *str += strlen (fp_const[i]);
4872 if (is_end_of_line[(unsigned char) **str])
4873 return i + 8;
4874 *str = start;
4875 }
4876 }
b99bd4ef 4877
c19d1205
ZW		 4878 /* Just because we didn't get a match doesn't mean that the constant
4879 isn't valid, just that it is in a format that we don't
4880 automatically recognize. Try parsing it with the standard
4881 expression routines. */
b99bd4ef 4882
c19d1205 4883 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 4884
c19d1205
ZW		 4885 /* Look for a raw floating point number. */
4886 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4887 && is_end_of_line[(unsigned char) *save_in])
4888 {
4889 for (i = 0; i < NUM_FLOAT_VALS; i++)
4890 {
4891 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 4892 {
c19d1205
ZW		 4893 if (words[j] != fp_values[i][j])
4894 break;
b99bd4ef
NC		 4895 }
4896
c19d1205 4897 if (j == MAX_LITTLENUMS)
b99bd4ef 4898 {
c19d1205
ZW		 4899 *str = save_in;
4900 return i + 8;
b99bd4ef
NC		 4901 }
4902 }
4903 }
b99bd4ef 4904
c19d1205
ZW		 4905 /* Try and parse a more complex expression, this will probably fail
4906 unless the code uses a floating point prefix (eg "0f"). */
4907 save_in = input_line_pointer;
4908 input_line_pointer = *str;
4909 if (expression (&exp) == absolute_section
4910 && exp.X_op == O_big
4911 && exp.X_add_number < 0)
4912 {
4913 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4914 Ditto for 15. */
4915 if (gen_to_words (words, 5, (long) 15) == 0)
4916 {
4917 for (i = 0; i < NUM_FLOAT_VALS; i++)
4918 {
4919 for (j = 0; j < MAX_LITTLENUMS; j++)
4920 {
4921 if (words[j] != fp_values[i][j])
4922 break;
4923 }
b99bd4ef 4924
c19d1205
ZW		 4925 if (j == MAX_LITTLENUMS)
4926 {
4927 *str = input_line_pointer;
4928 input_line_pointer = save_in;
4929 return i + 8;
4930 }
4931 }
4932 }
b99bd4ef
NC		 4933 }
4934
c19d1205
ZW		 4935 *str = input_line_pointer;
4936 input_line_pointer = save_in;
4937 inst.error = _("invalid FPA immediate expression");
4938 return FAIL;
b99bd4ef
NC		 4939}
4940
136da414
JB		 4941/* Returns 1 if a number has "quarter-precision" float format
4942 0baBbbbbbc defgh000 00000000 00000000. */
4943
4944static int
4945is_quarter_float (unsigned imm)
4946{
4947 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4948 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4949}
4950
aacf0b33
KT		 4951
4952/* Detect the presence of a floating point or integer zero constant,
4953 i.e. #0.0 or #0. */
4954
4955static bfd_boolean
4956parse_ifimm_zero (char **in)
4957{
4958 int error_code;
4959
4960 if (!is_immediate_prefix (**in))
4961 return FALSE;
4962
4963 ++*in;
4964 error_code = atof_generic (in, ".", EXP_CHARS,
4965 &generic_floating_point_number);
4966
4967 if (!error_code
4968 && generic_floating_point_number.sign == '+'
4969 && (generic_floating_point_number.low
4970 > generic_floating_point_number.leader))
4971 return TRUE;
4972
4973 return FALSE;
4974}
4975
136da414
JB		 4976/* Parse an 8-bit "quarter-precision" floating point number of the form:
4977 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB		 4978 The zero and minus-zero cases need special handling, since they can't be
4979 encoded in the "quarter-precision" float format, but can nonetheless be
4980 loaded as integer constants. */
136da414
JB		 4981
4982static unsigned
4983parse_qfloat_immediate (char **ccp, int *immed)
4984{
4985 char *str = *ccp;
c96612cc 4986 char *fpnum;
136da414 4987 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 4988 int found_fpchar = 0;
5f4273c7 4989
136da414 4990 skip_past_char (&str, '#');
5f4273c7 4991
c96612cc
JB		 4992 /* We must not accidentally parse an integer as a floating-point number. Make
4993 sure that the value we parse is not an integer by checking for special
4994 characters '.' or 'e'.
4995 FIXME: This is a horrible hack, but doing better is tricky because type
4996 information isn't in a very usable state at parse time. */
4997 fpnum = str;
4998 skip_whitespace (fpnum);
4999
5000 if (strncmp (fpnum, "0x", 2) == 0)
5001 return FAIL;
5002 else
5003 {
5004 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM		 5005 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5006 {
5007 found_fpchar = 1;
5008 break;
5009 }
c96612cc
JB		 5010
5011 if (!found_fpchar)
477330fc 5012 return FAIL;
c96612cc 5013 }
5f4273c7 5014
136da414
JB		 5015 if ((str = atof_ieee (str, 's', words)) != NULL)
5016 {
5017 unsigned fpword = 0;
5018 int i;
5f4273c7 5019
136da414
JB		 5020 /* Our FP word must be 32 bits (single-precision FP). */
5021 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM		 5022 {
5023 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5024 fpword |= words[i];
5025 }
5f4273c7 5026
c96612cc 5027 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 5028 *immed = fpword;
136da414 5029 else
477330fc 5030 return FAIL;
136da414
JB		 5031
5032 *ccp = str;
5f4273c7 5033
136da414
JB		 5034 return SUCCESS;
5035 }
5f4273c7 5036
136da414
JB		 5037 return FAIL;
5038}
5039
c19d1205
ZW		 5040/* Shift operands. */
5041enum shift_kind
b99bd4ef 5042{
c19d1205
ZW		 5043 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
5044};
b99bd4ef 5045
c19d1205
ZW		 5046struct asm_shift_name
5047{
5048 const char *name;
5049 enum shift_kind kind;
5050};
b99bd4ef 5051
c19d1205
ZW		 5052/* Third argument to parse_shift. */
5053enum parse_shift_mode
5054{
5055 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5056 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5057 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5058 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5059 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5060};
b99bd4ef 5061
c19d1205
ZW		 5062/* Parse a <shift> specifier on an ARM data processing instruction.
5063 This has three forms:
b99bd4ef 5064
c19d1205
ZW		 5065 (LSL|LSR|ASL|ASR|ROR) Rs
5066 (LSL|LSR|ASL|ASR|ROR) #imm
5067 RRX
b99bd4ef 5068
c19d1205
ZW		 5069 Note that ASL is assimilated to LSL in the instruction encoding, and
5070 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 5071
c19d1205
ZW		 5072static int
5073parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 5074{
c19d1205
ZW		 5075 const struct asm_shift_name *shift_name;
5076 enum shift_kind shift;
5077 char *s = *str;
5078 char *p = s;
5079 int reg;
b99bd4ef 5080
c19d1205
ZW		 5081 for (p = *str; ISALPHA (*p); p++)
5082 ;
b99bd4ef 5083
c19d1205 5084 if (p == *str)
b99bd4ef 5085 {
c19d1205
ZW		 5086 inst.error = _("shift expression expected");
5087 return FAIL;
b99bd4ef
NC		 5088 }
5089
21d799b5 5090 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 5091 p - *str);
c19d1205
ZW		 5092
5093 if (shift_name == NULL)
b99bd4ef 5094 {
c19d1205
ZW		 5095 inst.error = _("shift expression expected");
5096 return FAIL;
b99bd4ef
NC		 5097 }
5098
c19d1205 5099 shift = shift_name->kind;
b99bd4ef 5100
c19d1205
ZW		 5101 switch (mode)
5102 {
5103 case NO_SHIFT_RESTRICT:
5104 case SHIFT_IMMEDIATE: break;
b99bd4ef 5105
c19d1205
ZW		 5106 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5107 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5108 {
5109 inst.error = _("'LSL' or 'ASR' required");
5110 return FAIL;
5111 }
5112 break;
b99bd4ef 5113
c19d1205
ZW		 5114 case SHIFT_LSL_IMMEDIATE:
5115 if (shift != SHIFT_LSL)
5116 {
5117 inst.error = _("'LSL' required");
5118 return FAIL;
5119 }
5120 break;
b99bd4ef 5121
c19d1205
ZW		 5122 case SHIFT_ASR_IMMEDIATE:
5123 if (shift != SHIFT_ASR)
5124 {
5125 inst.error = _("'ASR' required");
5126 return FAIL;
5127 }
5128 break;
b99bd4ef 5129
c19d1205
ZW		 5130 default: abort ();
5131 }
b99bd4ef 5132
c19d1205
ZW		 5133 if (shift != SHIFT_RRX)
5134 {
5135 /* Whitespace can appear here if the next thing is a bare digit. */
5136 skip_whitespace (p);
b99bd4ef 5137
c19d1205 5138 if (mode == NO_SHIFT_RESTRICT
dcbf9037 5139 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5140 {
5141 inst.operands[i].imm = reg;
5142 inst.operands[i].immisreg = 1;
5143 }
5144 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5145 return FAIL;
5146 }
5147 inst.operands[i].shift_kind = shift;
5148 inst.operands[i].shifted = 1;
5149 *str = p;
5150 return SUCCESS;
b99bd4ef
NC		 5151}
5152
c19d1205 5153/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 5154
c19d1205
ZW		 5155 #<immediate>
5156 #<immediate>, <rotate>
5157 <Rm>
5158 <Rm>, <shift>
b99bd4ef 5159
c19d1205
ZW		 5160 where <shift> is defined by parse_shift above, and <rotate> is a
5161 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 5162 is deferred to md_apply_fix. */
b99bd4ef 5163
c19d1205
ZW		 5164static int
5165parse_shifter_operand (char **str, int i)
5166{
5167 int value;
91d6fa6a 5168 expressionS exp;
b99bd4ef 5169
dcbf9037 5170 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5171 {
5172 inst.operands[i].reg = value;
5173 inst.operands[i].isreg = 1;
b99bd4ef 5174
c19d1205
ZW		 5175 /* parse_shift will override this if appropriate */
5176 inst.reloc.exp.X_op = O_constant;
5177 inst.reloc.exp.X_add_number = 0;
b99bd4ef 5178
c19d1205
ZW		 5179 if (skip_past_comma (str) == FAIL)
5180 return SUCCESS;
b99bd4ef 5181
c19d1205
ZW		 5182 /* Shift operation on register. */
5183 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC		 5184 }
5185
c19d1205
ZW		 5186 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
5187 return FAIL;
b99bd4ef 5188
c19d1205 5189 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 5190 {
c19d1205 5191 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 5192 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 5193 return FAIL;
b99bd4ef 5194
91d6fa6a 5195 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
c19d1205
ZW		 5196 {
5197 inst.error = _("constant expression expected");
5198 return FAIL;
5199 }
b99bd4ef 5200
91d6fa6a 5201 value = exp.X_add_number;
c19d1205
ZW		 5202 if (value < 0 || value > 30 || value % 2 != 0)
5203 {
5204 inst.error = _("invalid rotation");
5205 return FAIL;
5206 }
5207 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
5208 {
5209 inst.error = _("invalid constant");
5210 return FAIL;
5211 }
09d92015 5212
a415b1cd
JB		 5213 /* Encode as specified. */
5214 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
5215 return SUCCESS;
09d92015
MM		 5216 }
5217
c19d1205
ZW		 5218 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5219 inst.reloc.pc_rel = 0;
5220 return SUCCESS;
09d92015
MM		 5221}
5222
4962c51a
MS		 5223/* Group relocation information. Each entry in the table contains the
5224 textual name of the relocation as may appear in assembler source
5225 and must end with a colon.
5226 Along with this textual name are the relocation codes to be used if
5227 the corresponding instruction is an ALU instruction (ADD or SUB only),
5228 an LDR, an LDRS, or an LDC. */
5229
5230struct group_reloc_table_entry
5231{
5232 const char *name;
5233 int alu_code;
5234 int ldr_code;
5235 int ldrs_code;
5236 int ldc_code;
5237};
5238
5239typedef enum
5240{
5241 /* Varieties of non-ALU group relocation. */
5242
5243 GROUP_LDR,
5244 GROUP_LDRS,
5245 GROUP_LDC
5246} group_reloc_type;
5247
5248static struct group_reloc_table_entry group_reloc_table[] =
5249 { /* Program counter relative: */
5250 { "pc_g0_nc",
5251 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5252 0, /* LDR */
5253 0, /* LDRS */
5254 0 }, /* LDC */
5255 { "pc_g0",
5256 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5257 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5258 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5259 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5260 { "pc_g1_nc",
5261 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5262 0, /* LDR */
5263 0, /* LDRS */
5264 0 }, /* LDC */
5265 { "pc_g1",
5266 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5267 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5268 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5269 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5270 { "pc_g2",
5271 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5272 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5273 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5274 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5275 /* Section base relative */
5276 { "sb_g0_nc",
5277 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5278 0, /* LDR */
5279 0, /* LDRS */
5280 0 }, /* LDC */
5281 { "sb_g0",
5282 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5283 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5284 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5285 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5286 { "sb_g1_nc",
5287 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5288 0, /* LDR */
5289 0, /* LDRS */
5290 0 }, /* LDC */
5291 { "sb_g1",
5292 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5293 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5294 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5295 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5296 { "sb_g2",
5297 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5298 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5299 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5300 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5301
5302/* Given the address of a pointer pointing to the textual name of a group
5303 relocation as may appear in assembler source, attempt to find its details
5304 in group_reloc_table. The pointer will be updated to the character after
5305 the trailing colon. On failure, FAIL will be returned; SUCCESS
5306 otherwise. On success, *entry will be updated to point at the relevant
5307 group_reloc_table entry. */
5308
5309static int
5310find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5311{
5312 unsigned int i;
5313 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5314 {
5315 int length = strlen (group_reloc_table[i].name);
5316
5f4273c7
NC		 5317 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5318 && (*str)[length] == ':')
477330fc
RM		 5319 {
5320 *out = &group_reloc_table[i];
5321 *str += (length + 1);
5322 return SUCCESS;
5323 }
4962c51a
MS		 5324 }
5325
5326 return FAIL;
5327}
5328
5329/* Parse a <shifter_operand> for an ARM data processing instruction
5330 (as for parse_shifter_operand) where group relocations are allowed:
5331
5332 #<immediate>
5333 #<immediate>, <rotate>
5334 #:<group_reloc>:<expression>
5335 <Rm>
5336 <Rm>, <shift>
5337
5338 where <group_reloc> is one of the strings defined in group_reloc_table.
5339 The hashes are optional.
5340
5341 Everything else is as for parse_shifter_operand. */
5342
5343static parse_operand_result
5344parse_shifter_operand_group_reloc (char **str, int i)
5345{
5346 /* Determine if we have the sequence of characters #: or just :
5347 coming next. If we do, then we check for a group relocation.
5348 If we don't, punt the whole lot to parse_shifter_operand. */
5349
5350 if (((*str)[0] == '#' && (*str)[1] == ':')
5351 || (*str)[0] == ':')
5352 {
5353 struct group_reloc_table_entry *entry;
5354
5355 if ((*str)[0] == '#')
477330fc 5356 (*str) += 2;
4962c51a 5357 else
477330fc 5358 (*str)++;
4962c51a
MS		 5359
5360 /* Try to parse a group relocation. Anything else is an error. */
5361 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM		 5362 {
5363 inst.error = _("unknown group relocation");
5364 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5365 }
4962c51a
MS		 5366
5367 /* We now have the group relocation table entry corresponding to
477330fc 5368 the name in the assembler source. Next, we parse the expression. */
4962c51a 5369 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
477330fc 5370 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS		 5371
5372 /* Record the relocation type (always the ALU variant here). */
21d799b5 5373 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
9c2799c2 5374 gas_assert (inst.reloc.type != 0);
4962c51a
MS		 5375
5376 return PARSE_OPERAND_SUCCESS;
5377 }
5378 else
5379 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5380 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS		 5381
5382 /* Never reached. */
5383}
5384
8e560766
MGD		 5385/* Parse a Neon alignment expression. Information is written to
5386 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5387
8e560766
MGD		 5388 align .imm = align << 8, .immisalign=1, .preind=0 */
5389static parse_operand_result
5390parse_neon_alignment (char **str, int i)
5391{
5392 char *p = *str;
5393 expressionS exp;
5394
5395 my_get_expression (&exp, &p, GE_NO_PREFIX);
5396
5397 if (exp.X_op != O_constant)
5398 {
5399 inst.error = _("alignment must be constant");
5400 return PARSE_OPERAND_FAIL;
5401 }
5402
5403 inst.operands[i].imm = exp.X_add_number << 8;
5404 inst.operands[i].immisalign = 1;
5405 /* Alignments are not pre-indexes. */
5406 inst.operands[i].preind = 0;
5407
5408 *str = p;
5409 return PARSE_OPERAND_SUCCESS;
5410}
5411
c19d1205
ZW		 5412/* Parse all forms of an ARM address expression. Information is written
5413 to inst.operands[i] and/or inst.reloc.
09d92015 5414
c19d1205 5415 Preindexed addressing (.preind=1):
09d92015 5416
c19d1205
ZW		 5417 [Rn, #offset] .reg=Rn .reloc.exp=offset
5418 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5419 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5420 .shift_kind=shift .reloc.exp=shift_imm
09d92015 5421
c19d1205 5422 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5423
c19d1205 5424 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5425
c19d1205
ZW		 5426 [Rn], #offset .reg=Rn .reloc.exp=offset
5427 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5428 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5429 .shift_kind=shift .reloc.exp=shift_imm
09d92015 5430
c19d1205 5431 Unindexed addressing (.preind=0, .postind=0):
09d92015 5432
c19d1205 5433 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5434
c19d1205 5435 Other:
09d92015 5436
c19d1205
ZW		 5437 [Rn]{!} shorthand for [Rn,#0]{!}
5438 =immediate .isreg=0 .reloc.exp=immediate
5439 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
09d92015 5440
c19d1205
ZW		 5441 It is the caller's responsibility to check for addressing modes not
5442 supported by the instruction, and to set inst.reloc.type. */
5443
4962c51a
MS		 5444static parse_operand_result
5445parse_address_main (char **str, int i, int group_relocations,
477330fc 5446 group_reloc_type group_type)
09d92015 5447{
c19d1205
ZW		 5448 char *p = *str;
5449 int reg;
09d92015 5450
c19d1205 5451 if (skip_past_char (&p, '[') == FAIL)
09d92015 5452 {
c19d1205
ZW		 5453 if (skip_past_char (&p, '=') == FAIL)
5454 {
974da60d 5455 /* Bare address - translate to PC-relative offset. */
c19d1205
ZW		 5456 inst.reloc.pc_rel = 1;
5457 inst.operands[i].reg = REG_PC;
5458 inst.operands[i].isreg = 1;
5459 inst.operands[i].preind = 1;
09d92015 5460
8335d6aa
JW		 5461 if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
5462 return PARSE_OPERAND_FAIL;
5463 }
5464 else if (parse_big_immediate (&p, i, &inst.reloc.exp,
5465 /*allow_symbol_p=*/TRUE))
4962c51a 5466 return PARSE_OPERAND_FAIL;
09d92015 5467
c19d1205 5468 *str = p;
4962c51a 5469 return PARSE_OPERAND_SUCCESS;
09d92015
MM		 5470 }
5471
8ab8155f
NC		 5472 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5473 skip_whitespace (p);
5474
dcbf9037 5475 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5476 {
c19d1205 5477 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5478 return PARSE_OPERAND_FAIL;
09d92015 5479 }
c19d1205
ZW		 5480 inst.operands[i].reg = reg;
5481 inst.operands[i].isreg = 1;
09d92015 5482
c19d1205 5483 if (skip_past_comma (&p) == SUCCESS)
09d92015 5484 {
c19d1205 5485 inst.operands[i].preind = 1;
09d92015 5486
c19d1205
ZW		 5487 if (*p == '+') p++;
5488 else if (*p == '-') p++, inst.operands[i].negative = 1;
5489
dcbf9037 5490 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5491 {
c19d1205
ZW		 5492 inst.operands[i].imm = reg;
5493 inst.operands[i].immisreg = 1;
5494
5495 if (skip_past_comma (&p) == SUCCESS)
5496 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5497 return PARSE_OPERAND_FAIL;
c19d1205 5498 }
5287ad62 5499 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD		 5500 {
5501 /* FIXME: '@' should be used here, but it's filtered out by generic
5502 code before we get to see it here. This may be subject to
5503 change. */
5504 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5505
8e560766
MGD		 5506 if (result != PARSE_OPERAND_SUCCESS)
5507 return result;
5508 }
c19d1205
ZW		 5509 else
5510 {
5511 if (inst.operands[i].negative)
5512 {
5513 inst.operands[i].negative = 0;
5514 p--;
5515 }
4962c51a 5516
5f4273c7
NC		 5517 if (group_relocations
5518 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS		 5519 {
5520 struct group_reloc_table_entry *entry;
5521
477330fc
RM		 5522 /* Skip over the #: or : sequence. */
5523 if (*p == '#')
5524 p += 2;
5525 else
5526 p++;
4962c51a
MS		 5527
5528 /* Try to parse a group relocation. Anything else is an
477330fc 5529 error. */
4962c51a
MS		 5530 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5531 {
5532 inst.error = _("unknown group relocation");
5533 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5534 }
5535
5536 /* We now have the group relocation table entry corresponding to
5537 the name in the assembler source. Next, we parse the
477330fc 5538 expression. */
4962c51a
MS		 5539 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5540 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5541
5542 /* Record the relocation type. */
477330fc
RM		 5543 switch (group_type)
5544 {
5545 case GROUP_LDR:
5546 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5547 break;
4962c51a 5548
477330fc
RM		 5549 case GROUP_LDRS:
5550 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5551 break;
4962c51a 5552
477330fc
RM		 5553 case GROUP_LDC:
5554 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5555 break;
4962c51a 5556
477330fc
RM		 5557 default:
5558 gas_assert (0);
5559 }
4962c51a 5560
477330fc 5561 if (inst.reloc.type == 0)
4962c51a
MS		 5562 {
5563 inst.error = _("this group relocation is not allowed on this instruction");
5564 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5565 }
477330fc
RM		 5566 }
5567 else
26d97720
NS		 5568 {
5569 char *q = p;
5570 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5571 return PARSE_OPERAND_FAIL;
5572 /* If the offset is 0, find out if it's a +0 or -0. */
5573 if (inst.reloc.exp.X_op == O_constant
5574 && inst.reloc.exp.X_add_number == 0)
5575 {
5576 skip_whitespace (q);
5577 if (*q == '#')
5578 {
5579 q++;
5580 skip_whitespace (q);
5581 }
5582 if (*q == '-')
5583 inst.operands[i].negative = 1;
5584 }
5585 }
09d92015
MM		 5586 }
5587 }
8e560766
MGD		 5588 else if (skip_past_char (&p, ':') == SUCCESS)
5589 {
5590 /* FIXME: '@' should be used here, but it's filtered out by generic code
5591 before we get to see it here. This may be subject to change. */
5592 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5593
8e560766
MGD		 5594 if (result != PARSE_OPERAND_SUCCESS)
5595 return result;
5596 }
09d92015 5597
c19d1205 5598 if (skip_past_char (&p, ']') == FAIL)
09d92015 5599 {
c19d1205 5600 inst.error = _("']' expected");
4962c51a 5601 return PARSE_OPERAND_FAIL;
09d92015
MM		 5602 }
5603
c19d1205
ZW		 5604 if (skip_past_char (&p, '!') == SUCCESS)
5605 inst.operands[i].writeback = 1;
09d92015 5606
c19d1205 5607 else if (skip_past_comma (&p) == SUCCESS)
09d92015 5608 {
c19d1205
ZW		 5609 if (skip_past_char (&p, '{') == SUCCESS)
5610 {
5611 /* [Rn], {expr} - unindexed, with option */
5612 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 5613 0, 255, TRUE) == FAIL)
4962c51a 5614 return PARSE_OPERAND_FAIL;
09d92015 5615
c19d1205
ZW		 5616 if (skip_past_char (&p, '}') == FAIL)
5617 {
5618 inst.error = _("'}' expected at end of 'option' field");
4962c51a 5619 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5620 }
5621 if (inst.operands[i].preind)
5622 {
5623 inst.error = _("cannot combine index with option");
4962c51a 5624 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5625 }
5626 *str = p;
4962c51a 5627 return PARSE_OPERAND_SUCCESS;
09d92015 5628 }
c19d1205
ZW		 5629 else
5630 {
5631 inst.operands[i].postind = 1;
5632 inst.operands[i].writeback = 1;
09d92015 5633
c19d1205
ZW		 5634 if (inst.operands[i].preind)
5635 {
5636 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 5637 return PARSE_OPERAND_FAIL;
c19d1205 5638 }
09d92015 5639
c19d1205
ZW		 5640 if (*p == '+') p++;
5641 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 5642
dcbf9037 5643 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 5644 {
477330fc
RM		 5645 /* We might be using the immediate for alignment already. If we
5646 are, OR the register number into the low-order bits. */
5647 if (inst.operands[i].immisalign)
5648 inst.operands[i].imm |= reg;
5649 else
5650 inst.operands[i].imm = reg;
c19d1205 5651 inst.operands[i].immisreg = 1;
a737bd4d 5652
c19d1205
ZW		 5653 if (skip_past_comma (&p) == SUCCESS)
5654 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5655 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5656 }
5657 else
5658 {
26d97720 5659 char *q = p;
c19d1205
ZW		 5660 if (inst.operands[i].negative)
5661 {
5662 inst.operands[i].negative = 0;
5663 p--;
5664 }
5665 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4962c51a 5666 return PARSE_OPERAND_FAIL;
26d97720
NS		 5667 /* If the offset is 0, find out if it's a +0 or -0. */
5668 if (inst.reloc.exp.X_op == O_constant
5669 && inst.reloc.exp.X_add_number == 0)
5670 {
5671 skip_whitespace (q);
5672 if (*q == '#')
5673 {
5674 q++;
5675 skip_whitespace (q);
5676 }
5677 if (*q == '-')
5678 inst.operands[i].negative = 1;
5679 }
c19d1205
ZW		 5680 }
5681 }
a737bd4d
NC		 5682 }
5683
c19d1205
ZW		 5684 /* If at this point neither .preind nor .postind is set, we have a
5685 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5686 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5687 {
5688 inst.operands[i].preind = 1;
5689 inst.reloc.exp.X_op = O_constant;
5690 inst.reloc.exp.X_add_number = 0;
5691 }
5692 *str = p;
4962c51a
MS		 5693 return PARSE_OPERAND_SUCCESS;
5694}
5695
5696static int
5697parse_address (char **str, int i)
5698{
21d799b5 5699 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 5700 ? SUCCESS : FAIL;
4962c51a
MS		 5701}
5702
5703static parse_operand_result
5704parse_address_group_reloc (char **str, int i, group_reloc_type type)
5705{
5706 return parse_address_main (str, i, 1, type);
a737bd4d
NC		 5707}
5708
b6895b4f
PB		 5709/* Parse an operand for a MOVW or MOVT instruction. */
5710static int
5711parse_half (char **str)
5712{
5713 char * p;
5f4273c7 5714
b6895b4f
PB		 5715 p = *str;
5716 skip_past_char (&p, '#');
5f4273c7 5717 if (strncasecmp (p, ":lower16:", 9) == 0)
b6895b4f
PB		 5718 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5719 else if (strncasecmp (p, ":upper16:", 9) == 0)
5720 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5721
5722 if (inst.reloc.type != BFD_RELOC_UNUSED)
5723 {
5724 p += 9;
5f4273c7 5725 skip_whitespace (p);
b6895b4f
PB		 5726 }
5727
5728 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5729 return FAIL;
5730
5731 if (inst.reloc.type == BFD_RELOC_UNUSED)
5732 {
5733 if (inst.reloc.exp.X_op != O_constant)
5734 {
5735 inst.error = _("constant expression expected");
5736 return FAIL;
5737 }
5738 if (inst.reloc.exp.X_add_number < 0
5739 || inst.reloc.exp.X_add_number > 0xffff)
5740 {
5741 inst.error = _("immediate value out of range");
5742 return FAIL;
5743 }
5744 }
5745 *str = p;
5746 return SUCCESS;
5747}
5748
c19d1205 5749/* Miscellaneous. */
a737bd4d 5750
c19d1205
ZW		 5751/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5752 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5753static int
d2cd1205 5754parse_psr (char **str, bfd_boolean lhs)
09d92015 5755{
c19d1205
ZW		 5756 char *p;
5757 unsigned long psr_field;
62b3e311
PB		 5758 const struct asm_psr *psr;
5759 char *start;
d2cd1205 5760 bfd_boolean is_apsr = FALSE;
ac7f631b 5761 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 5762
a4482bb6
NC		 5763 /* PR gas/12698: If the user has specified -march=all then m_profile will
5764 be TRUE, but we want to ignore it in this case as we are building for any
5765 CPU type, including non-m variants. */
5766 if (selected_cpu.core == arm_arch_any.core)
5767 m_profile = FALSE;
5768
c19d1205
ZW		 5769 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5770 feature for ease of use and backwards compatibility. */
5771 p = *str;
62b3e311 5772 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB		 5773 {
5774 if (m_profile)
5775 goto unsupported_psr;
fa94de6b 5776
d2cd1205
JB		 5777 psr_field = SPSR_BIT;
5778 }
5779 else if (strncasecmp (p, "CPSR", 4) == 0)
5780 {
5781 if (m_profile)
5782 goto unsupported_psr;
5783
5784 psr_field = 0;
5785 }
5786 else if (strncasecmp (p, "APSR", 4) == 0)
5787 {
5788 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5789 and ARMv7-R architecture CPUs. */
5790 is_apsr = TRUE;
5791 psr_field = 0;
5792 }
5793 else if (m_profile)
62b3e311
PB		 5794 {
5795 start = p;
5796 do
5797 p++;
5798 while (ISALNUM (*p) || *p == '_');
5799
d2cd1205
JB		 5800 if (strncasecmp (start, "iapsr", 5) == 0
5801 || strncasecmp (start, "eapsr", 5) == 0
5802 || strncasecmp (start, "xpsr", 4) == 0
5803 || strncasecmp (start, "psr", 3) == 0)
5804 p = start + strcspn (start, "rR") + 1;
5805
21d799b5 5806 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 5807 p - start);
d2cd1205 5808
62b3e311
PB		 5809 if (!psr)
5810 return FAIL;
09d92015 5811
d2cd1205
JB		 5812 /* If APSR is being written, a bitfield may be specified. Note that
5813 APSR itself is handled above. */
5814 if (psr->field <= 3)
5815 {
5816 psr_field = psr->field;
5817 is_apsr = TRUE;
5818 goto check_suffix;
5819 }
5820
62b3e311 5821 *str = p;
d2cd1205
JB		 5822 /* M-profile MSR instructions have the mask field set to "10", except
5823 *PSR variants which modify APSR, which may use a different mask (and
5824 have been handled already). Do that by setting the PSR_f field
5825 here. */
5826 return psr->field | (lhs ? PSR_f : 0);
62b3e311 5827 }
d2cd1205
JB		 5828 else
5829 goto unsupported_psr;
09d92015 5830
62b3e311 5831 p += 4;
d2cd1205 5832check_suffix:
c19d1205
ZW		 5833 if (*p == '_')
5834 {
5835 /* A suffix follows. */
c19d1205
ZW		 5836 p++;
5837 start = p;
a737bd4d 5838
c19d1205
ZW		 5839 do
5840 p++;
5841 while (ISALNUM (*p) || *p == '_');
a737bd4d 5842
d2cd1205
JB		 5843 if (is_apsr)
5844 {
5845 /* APSR uses a notation for bits, rather than fields. */
5846 unsigned int nzcvq_bits = 0;
5847 unsigned int g_bit = 0;
5848 char *bit;
fa94de6b 5849
d2cd1205
JB		 5850 for (bit = start; bit != p; bit++)
5851 {
5852 switch (TOLOWER (*bit))
477330fc 5853 {
d2cd1205
JB		 5854 case 'n':
5855 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5856 break;
5857
5858 case 'z':
5859 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5860 break;
5861
5862 case 'c':
5863 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5864 break;
5865
5866 case 'v':
5867 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5868 break;
fa94de6b 5869
d2cd1205
JB		 5870 case 'q':
5871 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5872 break;
fa94de6b 5873
d2cd1205
JB		 5874 case 'g':
5875 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5876 break;
fa94de6b 5877
d2cd1205
JB		 5878 default:
5879 inst.error = _("unexpected bit specified after APSR");
5880 return FAIL;
5881 }
5882 }
fa94de6b 5883
d2cd1205
JB		 5884 if (nzcvq_bits == 0x1f)
5885 psr_field |= PSR_f;
fa94de6b 5886
d2cd1205
JB		 5887 if (g_bit == 0x1)
5888 {
5889 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 5890 {
d2cd1205
JB		 5891 inst.error = _("selected processor does not "
5892 "support DSP extension");
5893 return FAIL;
5894 }
5895
5896 psr_field |= PSR_s;
5897 }
fa94de6b 5898
d2cd1205
JB		 5899 if ((nzcvq_bits & 0x20) != 0
5900 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5901 || (g_bit & 0x2) != 0)
5902 {
5903 inst.error = _("bad bitmask specified after APSR");
5904 return FAIL;
5905 }
5906 }
5907 else
477330fc 5908 {
d2cd1205 5909 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 5910 p - start);
d2cd1205 5911 if (!psr)
477330fc 5912 goto error;
a737bd4d 5913
d2cd1205
JB		 5914 psr_field |= psr->field;
5915 }
a737bd4d 5916 }
c19d1205 5917 else
a737bd4d 5918 {
c19d1205
ZW		 5919 if (ISALNUM (*p))
5920 goto error; /* Garbage after "[CS]PSR". */
5921
d2cd1205 5922 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 5923 is deprecated, but allow it anyway. */
d2cd1205
JB		 5924 if (is_apsr && lhs)
5925 {
5926 psr_field |= PSR_f;
5927 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5928 "deprecated"));
5929 }
5930 else if (!m_profile)
5931 /* These bits are never right for M-profile devices: don't set them
5932 (only code paths which read/write APSR reach here). */
5933 psr_field |= (PSR_c | PSR_f);
a737bd4d 5934 }
c19d1205
ZW		 5935 *str = p;
5936 return psr_field;
a737bd4d 5937
d2cd1205
JB		 5938 unsupported_psr:
5939 inst.error = _("selected processor does not support requested special "
5940 "purpose register");
5941 return FAIL;
5942
c19d1205
ZW		 5943 error:
5944 inst.error = _("flag for {c}psr instruction expected");
5945 return FAIL;
a737bd4d
NC		 5946}
5947
c19d1205
ZW		 5948/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5949 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 5950
c19d1205
ZW		 5951static int
5952parse_cps_flags (char **str)
a737bd4d 5953{
c19d1205
ZW		 5954 int val = 0;
5955 int saw_a_flag = 0;
5956 char *s = *str;
a737bd4d 5957
c19d1205
ZW		 5958 for (;;)
5959 switch (*s++)
5960 {
5961 case '\0': case ',':
5962 goto done;
a737bd4d 5963
c19d1205
ZW		 5964 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5965 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5966 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 5967
c19d1205
ZW		 5968 default:
5969 inst.error = _("unrecognized CPS flag");
5970 return FAIL;
5971 }
a737bd4d 5972
c19d1205
ZW		 5973 done:
5974 if (saw_a_flag == 0)
a737bd4d 5975 {
c19d1205
ZW		 5976 inst.error = _("missing CPS flags");
5977 return FAIL;
a737bd4d 5978 }
a737bd4d 5979
c19d1205
ZW		 5980 *str = s - 1;
5981 return val;
a737bd4d
NC		 5982}
5983
c19d1205
ZW		 5984/* Parse an endian specifier ("BE" or "LE", case insensitive);
5985 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC		 5986
5987static int
c19d1205 5988parse_endian_specifier (char **str)
a737bd4d 5989{
c19d1205
ZW		 5990 int little_endian;
5991 char *s = *str;
a737bd4d 5992
c19d1205
ZW		 5993 if (strncasecmp (s, "BE", 2))
5994 little_endian = 0;
5995 else if (strncasecmp (s, "LE", 2))
5996 little_endian = 1;
5997 else
a737bd4d 5998 {
c19d1205 5999 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6000 return FAIL;
6001 }
6002
c19d1205 6003 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 6004 {
c19d1205 6005 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6006 return FAIL;
6007 }
6008
c19d1205
ZW		 6009 *str = s + 2;
6010 return little_endian;
6011}
a737bd4d 6012
c19d1205
ZW		 6013/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6014 value suitable for poking into the rotate field of an sxt or sxta
6015 instruction, or FAIL on error. */
6016
6017static int
6018parse_ror (char **str)
6019{
6020 int rot;
6021 char *s = *str;
6022
6023 if (strncasecmp (s, "ROR", 3) == 0)
6024 s += 3;
6025 else
a737bd4d 6026 {
c19d1205 6027 inst.error = _("missing rotation field after comma");
a737bd4d
NC		 6028 return FAIL;
6029 }
c19d1205
ZW		 6030
6031 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6032 return FAIL;
6033
6034 switch (rot)
a737bd4d 6035 {
c19d1205
ZW		 6036 case 0: *str = s; return 0x0;
6037 case 8: *str = s; return 0x1;
6038 case 16: *str = s; return 0x2;
6039 case 24: *str = s; return 0x3;
6040
6041 default:
6042 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC		 6043 return FAIL;
6044 }
c19d1205 6045}
a737bd4d 6046
c19d1205
ZW		 6047/* Parse a conditional code (from conds[] below). The value returned is in the
6048 range 0 .. 14, or FAIL. */
6049static int
6050parse_cond (char **str)
6051{
c462b453 6052 char *q;
c19d1205 6053 const struct asm_cond *c;
c462b453
PB		 6054 int n;
6055 /* Condition codes are always 2 characters, so matching up to
6056 3 characters is sufficient. */
6057 char cond[3];
a737bd4d 6058
c462b453
PB		 6059 q = *str;
6060 n = 0;
6061 while (ISALPHA (*q) && n < 3)
6062 {
e07e6e58 6063 cond[n] = TOLOWER (*q);
c462b453
PB		 6064 q++;
6065 n++;
6066 }
a737bd4d 6067
21d799b5 6068 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 6069 if (!c)
a737bd4d 6070 {
c19d1205 6071 inst.error = _("condition required");
a737bd4d
NC		 6072 return FAIL;
6073 }
6074
c19d1205
ZW		 6075 *str = q;
6076 return c->value;
6077}
6078
e797f7e0
MGD		 6079/* If the given feature available in the selected CPU, mark it as used.
6080 Returns TRUE iff feature is available. */
6081static bfd_boolean
6082mark_feature_used (const arm_feature_set *feature)
6083{
6084 /* Ensure the option is valid on the current architecture. */
6085 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
6086 return FALSE;
6087
6088 /* Add the appropriate architecture feature for the barrier option used.
6089 */
6090 if (thumb_mode)
6091 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
6092 else
6093 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
6094
6095 return TRUE;
6096}
6097
62b3e311
PB		 6098/* Parse an option for a barrier instruction. Returns the encoding for the
6099 option, or FAIL. */
6100static int
6101parse_barrier (char **str)
6102{
6103 char *p, *q;
6104 const struct asm_barrier_opt *o;
6105
6106 p = q = *str;
6107 while (ISALPHA (*q))
6108 q++;
6109
21d799b5 6110 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 6111 q - p);
62b3e311
PB		 6112 if (!o)
6113 return FAIL;
6114
e797f7e0
MGD		 6115 if (!mark_feature_used (&o->arch))
6116 return FAIL;
6117
62b3e311
PB		 6118 *str = q;
6119 return o->value;
6120}
6121
92e90b6e
PB		 6122/* Parse the operands of a table branch instruction. Similar to a memory
6123 operand. */
6124static int
6125parse_tb (char **str)
6126{
6127 char * p = *str;
6128 int reg;
6129
6130 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB		 6131 {
6132 inst.error = _("'[' expected");
6133 return FAIL;
6134 }
92e90b6e 6135
dcbf9037 6136 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6137 {
6138 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6139 return FAIL;
6140 }
6141 inst.operands[0].reg = reg;
6142
6143 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB		 6144 {
6145 inst.error = _("',' expected");
6146 return FAIL;
6147 }
5f4273c7 6148
dcbf9037 6149 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6150 {
6151 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6152 return FAIL;
6153 }
6154 inst.operands[0].imm = reg;
6155
6156 if (skip_past_comma (&p) == SUCCESS)
6157 {
6158 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6159 return FAIL;
6160 if (inst.reloc.exp.X_add_number != 1)
6161 {
6162 inst.error = _("invalid shift");
6163 return FAIL;
6164 }
6165 inst.operands[0].shifted = 1;
6166 }
6167
6168 if (skip_past_char (&p, ']') == FAIL)
6169 {
6170 inst.error = _("']' expected");
6171 return FAIL;
6172 }
6173 *str = p;
6174 return SUCCESS;
6175}
6176
5287ad62
JB		 6177/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6178 information on the types the operands can take and how they are encoded.
037e8744
JB		 6179 Up to four operands may be read; this function handles setting the
6180 ".present" field for each read operand itself.
5287ad62
JB		 6181 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6182 else returns FAIL. */
6183
6184static int
6185parse_neon_mov (char **str, int *which_operand)
6186{
6187 int i = *which_operand, val;
6188 enum arm_reg_type rtype;
6189 char *ptr = *str;
dcbf9037 6190 struct neon_type_el optype;
5f4273c7 6191
dcbf9037 6192 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB		 6193 {
6194 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6195 inst.operands[i].reg = val;
6196 inst.operands[i].isscalar = 1;
dcbf9037 6197 inst.operands[i].vectype = optype;
5287ad62
JB		 6198 inst.operands[i++].present = 1;
6199
6200 if (skip_past_comma (&ptr) == FAIL)
477330fc 6201 goto wanted_comma;
5f4273c7 6202
dcbf9037 6203 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 6204 goto wanted_arm;
5f4273c7 6205
5287ad62
JB		 6206 inst.operands[i].reg = val;
6207 inst.operands[i].isreg = 1;
6208 inst.operands[i].present = 1;
6209 }
037e8744 6210 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
477330fc 6211 != FAIL)
5287ad62
JB		 6212 {
6213 /* Cases 0, 1, 2, 3, 5 (D only). */
6214 if (skip_past_comma (&ptr) == FAIL)
477330fc 6215 goto wanted_comma;
5f4273c7 6216
5287ad62
JB		 6217 inst.operands[i].reg = val;
6218 inst.operands[i].isreg = 1;
6219 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB		 6220 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6221 inst.operands[i].isvec = 1;
dcbf9037 6222 inst.operands[i].vectype = optype;
5287ad62
JB		 6223 inst.operands[i++].present = 1;
6224
dcbf9037 6225 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6226 {
6227 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6228 Case 13: VMOV <Sd>, <Rm> */
6229 inst.operands[i].reg = val;
6230 inst.operands[i].isreg = 1;
6231 inst.operands[i].present = 1;
6232
6233 if (rtype == REG_TYPE_NQ)
6234 {
6235 first_error (_("can't use Neon quad register here"));
6236 return FAIL;
6237 }
6238 else if (rtype != REG_TYPE_VFS)
6239 {
6240 i++;
6241 if (skip_past_comma (&ptr) == FAIL)
6242 goto wanted_comma;
6243 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6244 goto wanted_arm;
6245 inst.operands[i].reg = val;
6246 inst.operands[i].isreg = 1;
6247 inst.operands[i].present = 1;
6248 }
6249 }
037e8744 6250 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
477330fc
RM		 6251 &optype)) != FAIL)
6252 {
6253 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6254 Case 1: VMOV<c><q> <Dd>, <Dm>
6255 Case 8: VMOV.F32 <Sd>, <Sm>
6256 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6257
6258 inst.operands[i].reg = val;
6259 inst.operands[i].isreg = 1;
6260 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6261 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6262 inst.operands[i].isvec = 1;
6263 inst.operands[i].vectype = optype;
6264 inst.operands[i].present = 1;
6265
6266 if (skip_past_comma (&ptr) == SUCCESS)
6267 {
6268 /* Case 15. */
6269 i++;
6270
6271 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6272 goto wanted_arm;
6273
6274 inst.operands[i].reg = val;
6275 inst.operands[i].isreg = 1;
6276 inst.operands[i++].present = 1;
6277
6278 if (skip_past_comma (&ptr) == FAIL)
6279 goto wanted_comma;
6280
6281 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6282 goto wanted_arm;
6283
6284 inst.operands[i].reg = val;
6285 inst.operands[i].isreg = 1;
6286 inst.operands[i].present = 1;
6287 }
6288 }
4641781c 6289 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM		 6290 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6291 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6292 Case 10: VMOV.F32 <Sd>, #<imm>
6293 Case 11: VMOV.F64 <Dd>, #<imm> */
6294 inst.operands[i].immisfloat = 1;
8335d6aa
JW		 6295 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6296 == SUCCESS)
477330fc
RM		 6297 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6298 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6299 ;
5287ad62 6300 else
477330fc
RM		 6301 {
6302 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6303 return FAIL;
6304 }
5287ad62 6305 }
dcbf9037 6306 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB		 6307 {
6308 /* Cases 6, 7. */
6309 inst.operands[i].reg = val;
6310 inst.operands[i].isreg = 1;
6311 inst.operands[i++].present = 1;
5f4273c7 6312
5287ad62 6313 if (skip_past_comma (&ptr) == FAIL)
477330fc 6314 goto wanted_comma;
5f4273c7 6315
dcbf9037 6316 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
477330fc
RM		 6317 {
6318 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6319 inst.operands[i].reg = val;
6320 inst.operands[i].isscalar = 1;
6321 inst.operands[i].present = 1;
6322 inst.operands[i].vectype = optype;
6323 }
dcbf9037 6324 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6325 {
6326 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6327 inst.operands[i].reg = val;
6328 inst.operands[i].isreg = 1;
6329 inst.operands[i++].present = 1;
6330
6331 if (skip_past_comma (&ptr) == FAIL)
6332 goto wanted_comma;
6333
6334 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6335 == FAIL)
6336 {
6337 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6338 return FAIL;
6339 }
6340
6341 inst.operands[i].reg = val;
6342 inst.operands[i].isreg = 1;
6343 inst.operands[i].isvec = 1;
6344 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6345 inst.operands[i].vectype = optype;
6346 inst.operands[i].present = 1;
6347
6348 if (rtype == REG_TYPE_VFS)
6349 {
6350 /* Case 14. */
6351 i++;
6352 if (skip_past_comma (&ptr) == FAIL)
6353 goto wanted_comma;
6354 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6355 &optype)) == FAIL)
6356 {
6357 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6358 return FAIL;
6359 }
6360 inst.operands[i].reg = val;
6361 inst.operands[i].isreg = 1;
6362 inst.operands[i].isvec = 1;
6363 inst.operands[i].issingle = 1;
6364 inst.operands[i].vectype = optype;
6365 inst.operands[i].present = 1;
6366 }
6367 }
037e8744 6368 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM		 6369 != FAIL)
6370 {
6371 /* Case 13. */
6372 inst.operands[i].reg = val;
6373 inst.operands[i].isreg = 1;
6374 inst.operands[i].isvec = 1;
6375 inst.operands[i].issingle = 1;
6376 inst.operands[i].vectype = optype;
6377 inst.operands[i].present = 1;
6378 }
5287ad62
JB		 6379 }
6380 else
6381 {
dcbf9037 6382 first_error (_("parse error"));
5287ad62
JB		 6383 return FAIL;
6384 }
6385
6386 /* Successfully parsed the operands. Update args. */
6387 *which_operand = i;
6388 *str = ptr;
6389 return SUCCESS;
6390
5f4273c7 6391 wanted_comma:
dcbf9037 6392 first_error (_("expected comma"));
5287ad62 6393 return FAIL;
5f4273c7
NC		 6394
6395 wanted_arm:
dcbf9037 6396 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 6397 return FAIL;
5287ad62
JB		 6398}
6399
5be8be5d
DG		 6400/* Use this macro when the operand constraints are different
6401 for ARM and THUMB (e.g. ldrd). */
6402#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6403 ((arm_operand) | ((thumb_operand) << 16))
6404
c19d1205
ZW		 6405/* Matcher codes for parse_operands. */
6406enum operand_parse_code
6407{
6408 OP_stop, /* end of line */
6409
6410 OP_RR, /* ARM register */
6411 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 6412 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 6413 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 6414 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 6415 optional trailing ! */
c19d1205
ZW		 6416 OP_RRw, /* ARM register, not r15, optional trailing ! */
6417 OP_RCP, /* Coprocessor number */
6418 OP_RCN, /* Coprocessor register */
6419 OP_RF, /* FPA register */
6420 OP_RVS, /* VFP single precision register */
5287ad62
JB		 6421 OP_RVD, /* VFP double precision register (0..15) */
6422 OP_RND, /* Neon double precision register (0..31) */
6423 OP_RNQ, /* Neon quad precision register */
037e8744 6424 OP_RVSD, /* VFP single or double precision register */
5287ad62 6425 OP_RNDQ, /* Neon double or quad precision register */
037e8744 6426 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 6427 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW		 6428 OP_RVC, /* VFP control register */
6429 OP_RMF, /* Maverick F register */
6430 OP_RMD, /* Maverick D register */
6431 OP_RMFX, /* Maverick FX register */
6432 OP_RMDX, /* Maverick DX register */
6433 OP_RMAX, /* Maverick AX register */
6434 OP_RMDS, /* Maverick DSPSC register */
6435 OP_RIWR, /* iWMMXt wR register */
6436 OP_RIWC, /* iWMMXt wC register */
6437 OP_RIWG, /* iWMMXt wCG register */
6438 OP_RXA, /* XScale accumulator register */
6439
6440 OP_REGLST, /* ARM register list */
6441 OP_VRSLST, /* VFP single-precision register list */
6442 OP_VRDLST, /* VFP double-precision register list */
037e8744 6443 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB		 6444 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6445 OP_NSTRLST, /* Neon element/structure list */
6446
5287ad62 6447 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 6448 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
aacf0b33 6449 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
5287ad62 6450 OP_RR_RNSC, /* ARM reg or Neon scalar. */
037e8744 6451 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5287ad62
JB		 6452 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6453 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6454 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 6455 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5287ad62 6456 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
2d447fca 6457 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5287ad62
JB		 6458
6459 OP_I0, /* immediate zero */
c19d1205
ZW		 6460 OP_I7, /* immediate value 0 .. 7 */
6461 OP_I15, /* 0 .. 15 */
6462 OP_I16, /* 1 .. 16 */
5287ad62 6463 OP_I16z, /* 0 .. 16 */
c19d1205
ZW		 6464 OP_I31, /* 0 .. 31 */
6465 OP_I31w, /* 0 .. 31, optional trailing ! */
6466 OP_I32, /* 1 .. 32 */
5287ad62
JB		 6467 OP_I32z, /* 0 .. 32 */
6468 OP_I63, /* 0 .. 63 */
c19d1205 6469 OP_I63s, /* -64 .. 63 */
5287ad62
JB		 6470 OP_I64, /* 1 .. 64 */
6471 OP_I64z, /* 0 .. 64 */
c19d1205 6472 OP_I255, /* 0 .. 255 */
c19d1205
ZW		 6473
6474 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6475 OP_I7b, /* 0 .. 7 */
6476 OP_I15b, /* 0 .. 15 */
6477 OP_I31b, /* 0 .. 31 */
6478
6479 OP_SH, /* shifter operand */
4962c51a 6480 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 6481 OP_ADDR, /* Memory address expression (any mode) */
4962c51a
MS		 6482 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6483 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6484 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW		 6485 OP_EXP, /* arbitrary expression */
6486 OP_EXPi, /* same, with optional immediate prefix */
6487 OP_EXPr, /* same, with optional relocation suffix */
b6895b4f 6488 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c19d1205
ZW		 6489
6490 OP_CPSF, /* CPS flags */
6491 OP_ENDI, /* Endianness specifier */
d2cd1205
JB		 6492 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6493 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 6494 OP_COND, /* conditional code */
92e90b6e 6495 OP_TB, /* Table branch. */
c19d1205 6496
037e8744
JB		 6497 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6498
c19d1205
ZW		 6499 OP_RRnpc_I0, /* ARM register or literal 0 */
6500 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6501 OP_RR_EXi, /* ARM register or expression with imm prefix */
6502 OP_RF_IF, /* FPA register or immediate */
6503 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 6504 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW		 6505
6506 /* Optional operands. */
6507 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6508 OP_oI31b, /* 0 .. 31 */
5287ad62 6509 OP_oI32b, /* 1 .. 32 */
5f1af56b 6510 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW		 6511 OP_oIffffb, /* 0 .. 65535 */
6512 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6513
6514 OP_oRR, /* ARM register */
6515 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 6516 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 6517 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB		 6518 OP_oRND, /* Optional Neon double precision register */
6519 OP_oRNQ, /* Optional Neon quad precision register */
6520 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 6521 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
c19d1205
ZW		 6522 OP_oSHll, /* LSL immediate */
6523 OP_oSHar, /* ASR immediate */
6524 OP_oSHllar, /* LSL or ASR immediate */
6525 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 6526 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 6527
5be8be5d
DG		 6528 /* Some pre-defined mixed (ARM/THUMB) operands. */
6529 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6530 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6531 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6532
c19d1205
ZW		 6533 OP_FIRST_OPTIONAL = OP_oI7b
6534};
a737bd4d 6535
c19d1205
ZW		 6536/* Generic instruction operand parser. This does no encoding and no
6537 semantic validation; it merely squirrels values away in the inst
6538 structure. Returns SUCCESS or FAIL depending on whether the
6539 specified grammar matched. */
6540static int
5be8be5d 6541parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 6542{
5be8be5d 6543 unsigned const int *upat = pattern;
c19d1205
ZW		 6544 char *backtrack_pos = 0;
6545 const char *backtrack_error = 0;
99aad254 6546 int i, val = 0, backtrack_index = 0;
5287ad62 6547 enum arm_reg_type rtype;
4962c51a 6548 parse_operand_result result;
5be8be5d 6549 unsigned int op_parse_code;
c19d1205 6550
e07e6e58
NC		 6551#define po_char_or_fail(chr) \
6552 do \
6553 { \
6554 if (skip_past_char (&str, chr) == FAIL) \
477330fc 6555 goto bad_args; \
e07e6e58
NC		 6556 } \
6557 while (0)
c19d1205 6558
e07e6e58
NC		 6559#define po_reg_or_fail(regtype) \
6560 do \
dcbf9037 6561 { \
e07e6e58 6562 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 6563 & inst.operands[i].vectype); \
e07e6e58 6564 if (val == FAIL) \
477330fc
RM		 6565 { \
6566 first_error (_(reg_expected_msgs[regtype])); \
6567 goto failure; \
6568 } \
e07e6e58
NC		 6569 inst.operands[i].reg = val; \
6570 inst.operands[i].isreg = 1; \
6571 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6572 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6573 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM		 6574 || rtype == REG_TYPE_VFD \
6575 || rtype == REG_TYPE_NQ); \
dcbf9037 6576 } \
e07e6e58
NC		 6577 while (0)
6578
6579#define po_reg_or_goto(regtype, label) \
6580 do \
6581 { \
6582 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6583 & inst.operands[i].vectype); \
6584 if (val == FAIL) \
6585 goto label; \
dcbf9037 6586 \
e07e6e58
NC		 6587 inst.operands[i].reg = val; \
6588 inst.operands[i].isreg = 1; \
6589 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6590 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6591 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 6592 || rtype == REG_TYPE_VFD \
e07e6e58
NC		 6593 || rtype == REG_TYPE_NQ); \
6594 } \
6595 while (0)
6596
6597#define po_imm_or_fail(min, max, popt) \
6598 do \
6599 { \
6600 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6601 goto failure; \
6602 inst.operands[i].imm = val; \
6603 } \
6604 while (0)
6605
6606#define po_scalar_or_goto(elsz, label) \
6607 do \
6608 { \
6609 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6610 if (val == FAIL) \
6611 goto label; \
6612 inst.operands[i].reg = val; \
6613 inst.operands[i].isscalar = 1; \
6614 } \
6615 while (0)
6616
6617#define po_misc_or_fail(expr) \
6618 do \
6619 { \
6620 if (expr) \
6621 goto failure; \
6622 } \
6623 while (0)
6624
6625#define po_misc_or_fail_no_backtrack(expr) \
6626 do \
6627 { \
6628 result = expr; \
6629 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6630 backtrack_pos = 0; \
6631 if (result != PARSE_OPERAND_SUCCESS) \
6632 goto failure; \
6633 } \
6634 while (0)
4962c51a 6635
52e7f43d
RE		 6636#define po_barrier_or_imm(str) \
6637 do \
6638 { \
6639 val = parse_barrier (&str); \
ccb84d65
JB		 6640 if (val == FAIL && ! ISALPHA (*str)) \
6641 goto immediate; \
6642 if (val == FAIL \
6643 /* ISB can only take SY as an option. */ \
6644 || ((inst.instruction & 0xf0) == 0x60 \
6645 && val != 0xf)) \
52e7f43d 6646 { \
ccb84d65
JB		 6647 inst.error = _("invalid barrier type"); \
6648 backtrack_pos = 0; \
6649 goto failure; \
52e7f43d
RE		 6650 } \
6651 } \
6652 while (0)
6653
c19d1205
ZW		 6654 skip_whitespace (str);
6655
6656 for (i = 0; upat[i] != OP_stop; i++)
6657 {
5be8be5d
DG		 6658 op_parse_code = upat[i];
6659 if (op_parse_code >= 1<<16)
6660 op_parse_code = thumb ? (op_parse_code >> 16)
6661 : (op_parse_code & ((1<<16)-1));
6662
6663 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW		 6664 {
6665 /* Remember where we are in case we need to backtrack. */
9c2799c2 6666 gas_assert (!backtrack_pos);
c19d1205
ZW		 6667 backtrack_pos = str;
6668 backtrack_error = inst.error;
6669 backtrack_index = i;
6670 }
6671
b6702015 6672 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW		 6673 po_char_or_fail (',');
6674
5be8be5d 6675 switch (op_parse_code)
c19d1205
ZW		 6676 {
6677 /* Registers */
6678 case OP_oRRnpc:
5be8be5d 6679 case OP_oRRnpcsp:
c19d1205 6680 case OP_RRnpc:
5be8be5d 6681 case OP_RRnpcsp:
c19d1205
ZW		 6682 case OP_oRR:
6683 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6684 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6685 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6686 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6687 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6688 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 6689 case OP_oRND:
5287ad62 6690 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB		 6691 case OP_RVC:
6692 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6693 break;
6694 /* Also accept generic coprocessor regs for unknown registers. */
6695 coproc_reg:
6696 po_reg_or_fail (REG_TYPE_CN);
6697 break;
c19d1205
ZW		 6698 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6699 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6700 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6701 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6702 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6703 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6704 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6705 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6706 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6707 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 6708 case OP_oRNQ:
5287ad62 6709 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
477330fc 6710 case OP_oRNDQ:
5287ad62 6711 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
477330fc
RM		 6712 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6713 case OP_oRNSDQ:
6714 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6715
6716 /* Neon scalar. Using an element size of 8 means that some invalid
6717 scalars are accepted here, so deal with those in later code. */
6718 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6719
6720 case OP_RNDQ_I0:
6721 {
6722 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6723 break;
6724 try_imm0:
6725 po_imm_or_fail (0, 0, TRUE);
6726 }
6727 break;
6728
6729 case OP_RVSD_I0:
6730 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6731 break;
6732
aacf0b33
KT		 6733 case OP_RSVD_FI0:
6734 {
6735 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
6736 break;
6737 try_ifimm0:
6738 if (parse_ifimm_zero (&str))
6739 inst.operands[i].imm = 0;
6740 else
6741 {
6742 inst.error
6743 = _("only floating point zero is allowed as immediate value");
6744 goto failure;
6745 }
6746 }
6747 break;
6748
477330fc
RM		 6749 case OP_RR_RNSC:
6750 {
6751 po_scalar_or_goto (8, try_rr);
6752 break;
6753 try_rr:
6754 po_reg_or_fail (REG_TYPE_RN);
6755 }
6756 break;
6757
6758 case OP_RNSDQ_RNSC:
6759 {
6760 po_scalar_or_goto (8, try_nsdq);
6761 break;
6762 try_nsdq:
6763 po_reg_or_fail (REG_TYPE_NSDQ);
6764 }
6765 break;
6766
6767 case OP_RNDQ_RNSC:
6768 {
6769 po_scalar_or_goto (8, try_ndq);
6770 break;
6771 try_ndq:
6772 po_reg_or_fail (REG_TYPE_NDQ);
6773 }
6774 break;
6775
6776 case OP_RND_RNSC:
6777 {
6778 po_scalar_or_goto (8, try_vfd);
6779 break;
6780 try_vfd:
6781 po_reg_or_fail (REG_TYPE_VFD);
6782 }
6783 break;
6784
6785 case OP_VMOV:
6786 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6787 not careful then bad things might happen. */
6788 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6789 break;
6790
6791 case OP_RNDQ_Ibig:
6792 {
6793 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6794 break;
6795 try_immbig:
6796 /* There's a possibility of getting a 64-bit immediate here, so
6797 we need special handling. */
8335d6aa
JW		 6798 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
6799 == FAIL)
477330fc
RM		 6800 {
6801 inst.error = _("immediate value is out of range");
6802 goto failure;
6803 }
6804 }
6805 break;
6806
6807 case OP_RNDQ_I63b:
6808 {
6809 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6810 break;
6811 try_shimm:
6812 po_imm_or_fail (0, 63, TRUE);
6813 }
6814 break;
c19d1205
ZW		 6815
6816 case OP_RRnpcb:
6817 po_char_or_fail ('[');
6818 po_reg_or_fail (REG_TYPE_RN);
6819 po_char_or_fail (']');
6820 break;
a737bd4d 6821
55881a11 6822 case OP_RRnpctw:
c19d1205 6823 case OP_RRw:
b6702015 6824 case OP_oRRw:
c19d1205
ZW		 6825 po_reg_or_fail (REG_TYPE_RN);
6826 if (skip_past_char (&str, '!') == SUCCESS)
6827 inst.operands[i].writeback = 1;
6828 break;
6829
6830 /* Immediates */
6831 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6832 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6833 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 6834 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW		 6835 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6836 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 6837 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
c19d1205 6838 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM		 6839 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6840 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6841 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 6842 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW		 6843
6844 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6845 case OP_oI7b:
6846 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6847 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6848 case OP_oI31b:
6849 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM		 6850 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6851 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW		 6852 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6853
6854 /* Immediate variants */
6855 case OP_oI255c:
6856 po_char_or_fail ('{');
6857 po_imm_or_fail (0, 255, TRUE);
6858 po_char_or_fail ('}');
6859 break;
6860
6861 case OP_I31w:
6862 /* The expression parser chokes on a trailing !, so we have
6863 to find it first and zap it. */
6864 {
6865 char *s = str;
6866 while (*s && *s != ',')
6867 s++;
6868 if (s[-1] == '!')
6869 {
6870 s[-1] = '\0';
6871 inst.operands[i].writeback = 1;
6872 }
6873 po_imm_or_fail (0, 31, TRUE);
6874 if (str == s - 1)
6875 str = s;
6876 }
6877 break;
6878
6879 /* Expressions */
6880 case OP_EXPi: EXPi:
6881 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6882 GE_OPT_PREFIX));
6883 break;
6884
6885 case OP_EXP:
6886 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6887 GE_NO_PREFIX));
6888 break;
6889
6890 case OP_EXPr: EXPr:
6891 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6892 GE_NO_PREFIX));
6893 if (inst.reloc.exp.X_op == O_symbol)
a737bd4d 6894 {
c19d1205
ZW		 6895 val = parse_reloc (&str);
6896 if (val == -1)
6897 {
6898 inst.error = _("unrecognized relocation suffix");
6899 goto failure;
6900 }
6901 else if (val != BFD_RELOC_UNUSED)
6902 {
6903 inst.operands[i].imm = val;
6904 inst.operands[i].hasreloc = 1;
6905 }
a737bd4d 6906 }
c19d1205 6907 break;
a737bd4d 6908
b6895b4f
PB		 6909 /* Operand for MOVW or MOVT. */
6910 case OP_HALF:
6911 po_misc_or_fail (parse_half (&str));
6912 break;
6913
e07e6e58 6914 /* Register or expression. */
c19d1205
ZW		 6915 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6916 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 6917
e07e6e58 6918 /* Register or immediate. */
c19d1205
ZW		 6919 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6920 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 6921
c19d1205
ZW		 6922 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6923 IF:
6924 if (!is_immediate_prefix (*str))
6925 goto bad_args;
6926 str++;
6927 val = parse_fpa_immediate (&str);
6928 if (val == FAIL)
6929 goto failure;
6930 /* FPA immediates are encoded as registers 8-15.
6931 parse_fpa_immediate has already applied the offset. */
6932 inst.operands[i].reg = val;
6933 inst.operands[i].isreg = 1;
6934 break;
09d92015 6935
2d447fca
JM		 6936 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6937 I32z: po_imm_or_fail (0, 32, FALSE); break;
6938
e07e6e58 6939 /* Two kinds of register. */
c19d1205
ZW		 6940 case OP_RIWR_RIWC:
6941 {
6942 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM		 6943 if (!rege
6944 || (rege->type != REG_TYPE_MMXWR
6945 && rege->type != REG_TYPE_MMXWC
6946 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW		 6947 {
6948 inst.error = _("iWMMXt data or control register expected");
6949 goto failure;
6950 }
6951 inst.operands[i].reg = rege->number;
6952 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6953 }
6954 break;
09d92015 6955
41adaa5c
JM		 6956 case OP_RIWC_RIWG:
6957 {
6958 struct reg_entry *rege = arm_reg_parse_multi (&str);
6959 if (!rege
6960 || (rege->type != REG_TYPE_MMXWC
6961 && rege->type != REG_TYPE_MMXWCG))
6962 {
6963 inst.error = _("iWMMXt control register expected");
6964 goto failure;
6965 }
6966 inst.operands[i].reg = rege->number;
6967 inst.operands[i].isreg = 1;
6968 }
6969 break;
6970
c19d1205
ZW		 6971 /* Misc */
6972 case OP_CPSF: val = parse_cps_flags (&str); break;
6973 case OP_ENDI: val = parse_endian_specifier (&str); break;
6974 case OP_oROR: val = parse_ror (&str); break;
c19d1205 6975 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE		 6976 case OP_oBARRIER_I15:
6977 po_barrier_or_imm (str); break;
6978 immediate:
6979 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 6980 goto failure;
52e7f43d 6981 break;
c19d1205 6982
fa94de6b 6983 case OP_wPSR:
d2cd1205 6984 case OP_rPSR:
90ec0d68
MGD		 6985 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6986 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6987 {
6988 inst.error = _("Banked registers are not available with this "
6989 "architecture.");
6990 goto failure;
6991 }
6992 break;
d2cd1205
JB		 6993 try_psr:
6994 val = parse_psr (&str, op_parse_code == OP_wPSR);
6995 break;
037e8744 6996
477330fc
RM		 6997 case OP_APSR_RR:
6998 po_reg_or_goto (REG_TYPE_RN, try_apsr);
6999 break;
7000 try_apsr:
7001 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7002 instruction). */
7003 if (strncasecmp (str, "APSR_", 5) == 0)
7004 {
7005 unsigned found = 0;
7006 str += 5;
7007 while (found < 15)
7008 switch (*str++)
7009 {
7010 case 'c': found = (found & 1) ? 16 : found | 1; break;
7011 case 'n': found = (found & 2) ? 16 : found | 2; break;
7012 case 'z': found = (found & 4) ? 16 : found | 4; break;
7013 case 'v': found = (found & 8) ? 16 : found | 8; break;
7014 default: found = 16;
7015 }
7016 if (found != 15)
7017 goto failure;
7018 inst.operands[i].isvec = 1;
f7c21dc7
NC		 7019 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7020 inst.operands[i].reg = REG_PC;
477330fc
RM		 7021 }
7022 else
7023 goto failure;
7024 break;
037e8744 7025
92e90b6e
PB		 7026 case OP_TB:
7027 po_misc_or_fail (parse_tb (&str));
7028 break;
7029
e07e6e58 7030 /* Register lists. */
c19d1205
ZW		 7031 case OP_REGLST:
7032 val = parse_reg_list (&str);
7033 if (*str == '^')
7034 {
7035 inst.operands[1].writeback = 1;
7036 str++;
7037 }
7038 break;
09d92015 7039
c19d1205 7040 case OP_VRSLST:
5287ad62 7041 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
c19d1205 7042 break;
09d92015 7043
c19d1205 7044 case OP_VRDLST:
5287ad62 7045 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
c19d1205 7046 break;
a737bd4d 7047
477330fc
RM		 7048 case OP_VRSDLST:
7049 /* Allow Q registers too. */
7050 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7051 REGLIST_NEON_D);
7052 if (val == FAIL)
7053 {
7054 inst.error = NULL;
7055 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7056 REGLIST_VFP_S);
7057 inst.operands[i].issingle = 1;
7058 }
7059 break;
7060
7061 case OP_NRDLST:
7062 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7063 REGLIST_NEON_D);
7064 break;
5287ad62
JB		 7065
7066 case OP_NSTRLST:
477330fc
RM		 7067 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7068 &inst.operands[i].vectype);
7069 break;
5287ad62 7070
c19d1205
ZW		 7071 /* Addressing modes */
7072 case OP_ADDR:
7073 po_misc_or_fail (parse_address (&str, i));
7074 break;
09d92015 7075
4962c51a
MS		 7076 case OP_ADDRGLDR:
7077 po_misc_or_fail_no_backtrack (
477330fc 7078 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS		 7079 break;
7080
7081 case OP_ADDRGLDRS:
7082 po_misc_or_fail_no_backtrack (
477330fc 7083 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS		 7084 break;
7085
7086 case OP_ADDRGLDC:
7087 po_misc_or_fail_no_backtrack (
477330fc 7088 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS		 7089 break;
7090
c19d1205
ZW		 7091 case OP_SH:
7092 po_misc_or_fail (parse_shifter_operand (&str, i));
7093 break;
09d92015 7094
4962c51a
MS		 7095 case OP_SHG:
7096 po_misc_or_fail_no_backtrack (
477330fc 7097 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS		 7098 break;
7099
c19d1205
ZW		 7100 case OP_oSHll:
7101 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7102 break;
09d92015 7103
c19d1205
ZW		 7104 case OP_oSHar:
7105 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7106 break;
09d92015 7107
c19d1205
ZW		 7108 case OP_oSHllar:
7109 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7110 break;
09d92015 7111
c19d1205 7112 default:
5be8be5d 7113 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 7114 }
09d92015 7115
c19d1205
ZW		 7116 /* Various value-based sanity checks and shared operations. We
7117 do not signal immediate failures for the register constraints;
7118 this allows a syntax error to take precedence. */
5be8be5d 7119 switch (op_parse_code)
c19d1205
ZW		 7120 {
7121 case OP_oRRnpc:
7122 case OP_RRnpc:
7123 case OP_RRnpcb:
7124 case OP_RRw:
b6702015 7125 case OP_oRRw:
c19d1205
ZW		 7126 case OP_RRnpc_I0:
7127 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7128 inst.error = BAD_PC;
7129 break;
09d92015 7130
5be8be5d
DG		 7131 case OP_oRRnpcsp:
7132 case OP_RRnpcsp:
7133 if (inst.operands[i].isreg)
7134 {
7135 if (inst.operands[i].reg == REG_PC)
7136 inst.error = BAD_PC;
7137 else if (inst.operands[i].reg == REG_SP)
7138 inst.error = BAD_SP;
7139 }
7140 break;
7141
55881a11 7142 case OP_RRnpctw:
fa94de6b
RM		 7143 if (inst.operands[i].isreg
7144 && inst.operands[i].reg == REG_PC
55881a11
MGD		 7145 && (inst.operands[i].writeback || thumb))
7146 inst.error = BAD_PC;
7147 break;
7148
c19d1205
ZW		 7149 case OP_CPSF:
7150 case OP_ENDI:
7151 case OP_oROR:
d2cd1205
JB		 7152 case OP_wPSR:
7153 case OP_rPSR:
c19d1205 7154 case OP_COND:
52e7f43d 7155 case OP_oBARRIER_I15:
c19d1205
ZW		 7156 case OP_REGLST:
7157 case OP_VRSLST:
7158 case OP_VRDLST:
477330fc
RM		 7159 case OP_VRSDLST:
7160 case OP_NRDLST:
7161 case OP_NSTRLST:
c19d1205
ZW		 7162 if (val == FAIL)
7163 goto failure;
7164 inst.operands[i].imm = val;
7165 break;
a737bd4d 7166
c19d1205
ZW		 7167 default:
7168 break;
7169 }
09d92015 7170
c19d1205
ZW		 7171 /* If we get here, this operand was successfully parsed. */
7172 inst.operands[i].present = 1;
7173 continue;
09d92015 7174
c19d1205 7175 bad_args:
09d92015 7176 inst.error = BAD_ARGS;
c19d1205
ZW		 7177
7178 failure:
7179 if (!backtrack_pos)
d252fdde
PB		 7180 {
7181 /* The parse routine should already have set inst.error, but set a
5f4273c7 7182 default here just in case. */
d252fdde
PB		 7183 if (!inst.error)
7184 inst.error = _("syntax error");
7185 return FAIL;
7186 }
c19d1205
ZW		 7187
7188 /* Do not backtrack over a trailing optional argument that
7189 absorbed some text. We will only fail again, with the
7190 'garbage following instruction' error message, which is
7191 probably less helpful than the current one. */
7192 if (backtrack_index == i && backtrack_pos != str
7193 && upat[i+1] == OP_stop)
d252fdde
PB		 7194 {
7195 if (!inst.error)
7196 inst.error = _("syntax error");
7197 return FAIL;
7198 }
c19d1205
ZW		 7199
7200 /* Try again, skipping the optional argument at backtrack_pos. */
7201 str = backtrack_pos;
7202 inst.error = backtrack_error;
7203 inst.operands[backtrack_index].present = 0;
7204 i = backtrack_index;
7205 backtrack_pos = 0;
09d92015 7206 }
09d92015 7207
c19d1205
ZW		 7208 /* Check that we have parsed all the arguments. */
7209 if (*str != '\0' && !inst.error)
7210 inst.error = _("garbage following instruction");
09d92015 7211
c19d1205 7212 return inst.error ? FAIL : SUCCESS;
09d92015
MM		 7213}
7214
c19d1205
ZW		 7215#undef po_char_or_fail
7216#undef po_reg_or_fail
7217#undef po_reg_or_goto
7218#undef po_imm_or_fail
5287ad62 7219#undef po_scalar_or_fail
52e7f43d 7220#undef po_barrier_or_imm
e07e6e58 7221
c19d1205 7222/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC		 7223#define constraint(expr, err) \
7224 do \
c19d1205 7225 { \
e07e6e58
NC		 7226 if (expr) \
7227 { \
7228 inst.error = err; \
7229 return; \
7230 } \
c19d1205 7231 } \
e07e6e58 7232 while (0)
c19d1205 7233
fdfde340
JM		 7234/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7235 instructions are unpredictable if these registers are used. This
7236 is the BadReg predicate in ARM's Thumb-2 documentation. */
7237#define reject_bad_reg(reg) \
7238 do \
7239 if (reg == REG_SP || reg == REG_PC) \
7240 { \
7241 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7242 return; \
7243 } \
7244 while (0)
7245
94206790
MM		 7246/* If REG is R13 (the stack pointer), warn that its use is
7247 deprecated. */
7248#define warn_deprecated_sp(reg) \
7249 do \
7250 if (warn_on_deprecated && reg == REG_SP) \
7251 as_warn (_("use of r13 is deprecated")); \
7252 while (0)
7253
c19d1205
ZW		 7254/* Functions for operand encoding. ARM, then Thumb. */
7255
d840c081 7256#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
c19d1205
ZW		 7257
7258/* If VAL can be encoded in the immediate field of an ARM instruction,
7259 return the encoded form. Otherwise, return FAIL. */
7260
7261static unsigned int
7262encode_arm_immediate (unsigned int val)
09d92015 7263{
c19d1205
ZW		 7264 unsigned int a, i;
7265
7266 for (i = 0; i < 32; i += 2)
7267 if ((a = rotate_left (val, i)) <= 0xff)
7268 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7269
7270 return FAIL;
09d92015
MM		 7271}
7272
c19d1205
ZW		 7273/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7274 return the encoded form. Otherwise, return FAIL. */
7275static unsigned int
7276encode_thumb32_immediate (unsigned int val)
09d92015 7277{
c19d1205 7278 unsigned int a, i;
09d92015 7279
9c3c69f2 7280 if (val <= 0xff)
c19d1205 7281 return val;
a737bd4d 7282
9c3c69f2 7283 for (i = 1; i <= 24; i++)
09d92015 7284 {
9c3c69f2
PB		 7285 a = val >> i;
7286 if ((val & ~(0xff << i)) == 0)
7287 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 7288 }
a737bd4d 7289
c19d1205
ZW		 7290 a = val & 0xff;
7291 if (val == ((a << 16) | a))
7292 return 0x100 | a;
7293 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
7294 return 0x300 | a;
09d92015 7295
c19d1205
ZW		 7296 a = val & 0xff00;
7297 if (val == ((a << 16) | a))
7298 return 0x200 | (a >> 8);
a737bd4d 7299
c19d1205 7300 return FAIL;
09d92015 7301}
5287ad62 7302/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM		 7303
7304static void
5287ad62
JB		 7305encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7306{
7307 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7308 && reg > 15)
7309 {
b1cc4aeb 7310 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 7311 {
7312 if (thumb_mode)
7313 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7314 fpu_vfp_ext_d32);
7315 else
7316 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7317 fpu_vfp_ext_d32);
7318 }
5287ad62 7319 else
477330fc
RM		 7320 {
7321 first_error (_("D register out of range for selected VFP version"));
7322 return;
7323 }
5287ad62
JB		 7324 }
7325
c19d1205 7326 switch (pos)
09d92015 7327 {
c19d1205
ZW		 7328 case VFP_REG_Sd:
7329 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7330 break;
7331
7332 case VFP_REG_Sn:
7333 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7334 break;
7335
7336 case VFP_REG_Sm:
7337 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7338 break;
7339
5287ad62
JB		 7340 case VFP_REG_Dd:
7341 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7342 break;
5f4273c7 7343
5287ad62
JB		 7344 case VFP_REG_Dn:
7345 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7346 break;
5f4273c7 7347
5287ad62
JB		 7348 case VFP_REG_Dm:
7349 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7350 break;
7351
c19d1205
ZW		 7352 default:
7353 abort ();
09d92015 7354 }
09d92015
MM		 7355}
7356
c19d1205 7357/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 7358 if any, is handled by md_apply_fix. */
09d92015 7359static void
c19d1205 7360encode_arm_shift (int i)
09d92015 7361{
c19d1205
ZW		 7362 if (inst.operands[i].shift_kind == SHIFT_RRX)
7363 inst.instruction |= SHIFT_ROR << 5;
7364 else
09d92015 7365 {
c19d1205
ZW		 7366 inst.instruction |= inst.operands[i].shift_kind << 5;
7367 if (inst.operands[i].immisreg)
7368 {
7369 inst.instruction |= SHIFT_BY_REG;
7370 inst.instruction |= inst.operands[i].imm << 8;
7371 }
7372 else
7373 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 7374 }
c19d1205 7375}
09d92015 7376
c19d1205
ZW		 7377static void
7378encode_arm_shifter_operand (int i)
7379{
7380 if (inst.operands[i].isreg)
09d92015 7381 {
c19d1205
ZW		 7382 inst.instruction |= inst.operands[i].reg;
7383 encode_arm_shift (i);
09d92015 7384 }
c19d1205 7385 else
a415b1cd
JB		 7386 {
7387 inst.instruction |= INST_IMMEDIATE;
7388 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7389 inst.instruction |= inst.operands[i].imm;
7390 }
09d92015
MM		 7391}
7392
c19d1205 7393/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 7394static void
c19d1205 7395encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 7396{
2b2f5df9
NC		 7397 /* PR 14260:
7398 Generate an error if the operand is not a register. */
7399 constraint (!inst.operands[i].isreg,
7400 _("Instruction does not support =N addresses"));
7401
c19d1205 7402 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 7403
c19d1205 7404 if (inst.operands[i].preind)
09d92015 7405 {
c19d1205
ZW		 7406 if (is_t)
7407 {
7408 inst.error = _("instruction does not accept preindexed addressing");
7409 return;
7410 }
7411 inst.instruction |= PRE_INDEX;
7412 if (inst.operands[i].writeback)
7413 inst.instruction |= WRITE_BACK;
09d92015 7414
c19d1205
ZW		 7415 }
7416 else if (inst.operands[i].postind)
7417 {
9c2799c2 7418 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 7419 if (is_t)
7420 inst.instruction |= WRITE_BACK;
7421 }
7422 else /* unindexed - only for coprocessor */
09d92015 7423 {
c19d1205 7424 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM		 7425 return;
7426 }
7427
c19d1205
ZW		 7428 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7429 && (((inst.instruction & 0x000f0000) >> 16)
7430 == ((inst.instruction & 0x0000f000) >> 12)))
7431 as_warn ((inst.instruction & LOAD_BIT)
7432 ? _("destination register same as write-back base")
7433 : _("source register same as write-back base"));
09d92015
MM		 7434}
7435
c19d1205
ZW		 7436/* inst.operands[i] was set up by parse_address. Encode it into an
7437 ARM-format mode 2 load or store instruction. If is_t is true,
7438 reject forms that cannot be used with a T instruction (i.e. not
7439 post-indexed). */
a737bd4d 7440static void
c19d1205 7441encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 7442{
5be8be5d
DG		 7443 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7444
c19d1205 7445 encode_arm_addr_mode_common (i, is_t);
a737bd4d 7446
c19d1205 7447 if (inst.operands[i].immisreg)
09d92015 7448 {
5be8be5d
DG		 7449 constraint ((inst.operands[i].imm == REG_PC
7450 || (is_pc && inst.operands[i].writeback)),
7451 BAD_PC_ADDRESSING);
c19d1205
ZW		 7452 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7453 inst.instruction |= inst.operands[i].imm;
7454 if (!inst.operands[i].negative)
7455 inst.instruction |= INDEX_UP;
7456 if (inst.operands[i].shifted)
7457 {
7458 if (inst.operands[i].shift_kind == SHIFT_RRX)
7459 inst.instruction |= SHIFT_ROR << 5;
7460 else
7461 {
7462 inst.instruction |= inst.operands[i].shift_kind << 5;
7463 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7464 }
7465 }
09d92015 7466 }
c19d1205 7467 else /* immediate offset in inst.reloc */
09d92015 7468 {
5be8be5d
DG		 7469 if (is_pc && !inst.reloc.pc_rel)
7470 {
7471 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ		 7472
7473 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7474 cannot use PC in addressing.
7475 PC cannot be used in writeback addressing, either. */
7476 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 7477 BAD_PC_ADDRESSING);
23a10334 7478
dc5ec521 7479 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ		 7480 if (warn_on_deprecated
7481 && !is_load
7482 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
7483 as_warn (_("use of PC in this instruction is deprecated"));
5be8be5d
DG		 7484 }
7485
c19d1205 7486 if (inst.reloc.type == BFD_RELOC_UNUSED)
26d97720
NS		 7487 {
7488 /* Prefer + for zero encoded value. */
7489 if (!inst.operands[i].negative)
7490 inst.instruction |= INDEX_UP;
7491 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7492 }
09d92015 7493 }
09d92015
MM		 7494}
7495
c19d1205
ZW		 7496/* inst.operands[i] was set up by parse_address. Encode it into an
7497 ARM-format mode 3 load or store instruction. Reject forms that
7498 cannot be used with such instructions. If is_t is true, reject
7499 forms that cannot be used with a T instruction (i.e. not
7500 post-indexed). */
7501static void
7502encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 7503{
c19d1205 7504 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 7505 {
c19d1205
ZW		 7506 inst.error = _("instruction does not accept scaled register index");
7507 return;
09d92015 7508 }
a737bd4d 7509
c19d1205 7510 encode_arm_addr_mode_common (i, is_t);
a737bd4d 7511
c19d1205
ZW		 7512 if (inst.operands[i].immisreg)
7513 {
5be8be5d 7514 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 7515 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 7516 BAD_PC_ADDRESSING);
eb9f3f00
JB		 7517 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7518 BAD_PC_WRITEBACK);
c19d1205
ZW		 7519 inst.instruction |= inst.operands[i].imm;
7520 if (!inst.operands[i].negative)
7521 inst.instruction |= INDEX_UP;
7522 }
7523 else /* immediate offset in inst.reloc */
7524 {
5be8be5d
DG		 7525 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7526 && inst.operands[i].writeback),
7527 BAD_PC_WRITEBACK);
c19d1205
ZW		 7528 inst.instruction |= HWOFFSET_IMM;
7529 if (inst.reloc.type == BFD_RELOC_UNUSED)
26d97720
NS		 7530 {
7531 /* Prefer + for zero encoded value. */
7532 if (!inst.operands[i].negative)
7533 inst.instruction |= INDEX_UP;
7534
7535 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7536 }
c19d1205 7537 }
a737bd4d
NC		 7538}
7539
8335d6aa
JW		 7540/* Write immediate bits [7:0] to the following locations:
7541
7542 |28/24|23 19|18 16|15 4|3 0|
7543 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7544
7545 This function is used by VMOV/VMVN/VORR/VBIC. */
7546
7547static void
7548neon_write_immbits (unsigned immbits)
7549{
7550 inst.instruction |= immbits & 0xf;
7551 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
7552 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
7553}
7554
7555/* Invert low-order SIZE bits of XHI:XLO. */
7556
7557static void
7558neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
7559{
7560 unsigned immlo = xlo ? *xlo : 0;
7561 unsigned immhi = xhi ? *xhi : 0;
7562
7563 switch (size)
7564 {
7565 case 8:
7566 immlo = (~immlo) & 0xff;
7567 break;
7568
7569 case 16:
7570 immlo = (~immlo) & 0xffff;
7571 break;
7572
7573 case 64:
7574 immhi = (~immhi) & 0xffffffff;
7575 /* fall through. */
7576
7577 case 32:
7578 immlo = (~immlo) & 0xffffffff;
7579 break;
7580
7581 default:
7582 abort ();
7583 }
7584
7585 if (xlo)
7586 *xlo = immlo;
7587
7588 if (xhi)
7589 *xhi = immhi;
7590}
7591
7592/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7593 A, B, C, D. */
09d92015 7594
c19d1205 7595static int
8335d6aa 7596neon_bits_same_in_bytes (unsigned imm)
09d92015 7597{
8335d6aa
JW		 7598 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
7599 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
7600 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
7601 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
7602}
a737bd4d 7603
8335d6aa 7604/* For immediate of above form, return 0bABCD. */
09d92015 7605
8335d6aa
JW		 7606static unsigned
7607neon_squash_bits (unsigned imm)
7608{
7609 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
7610 | ((imm & 0x01000000) >> 21);
7611}
7612
7613/* Compress quarter-float representation to 0b...000 abcdefgh. */
7614
7615static unsigned
7616neon_qfloat_bits (unsigned imm)
7617{
7618 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
7619}
7620
7621/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7622 the instruction. *OP is passed as the initial value of the op field, and
7623 may be set to a different value depending on the constant (i.e.
7624 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7625 MVN). If the immediate looks like a repeated pattern then also
7626 try smaller element sizes. */
7627
7628static int
7629neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
7630 unsigned *immbits, int *op, int size,
7631 enum neon_el_type type)
7632{
7633 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7634 float. */
7635 if (type == NT_float && !float_p)
7636 return FAIL;
7637
7638 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
09d92015 7639 {
8335d6aa
JW		 7640 if (size != 32 || *op == 1)
7641 return FAIL;
7642 *immbits = neon_qfloat_bits (immlo);
7643 return 0xf;
7644 }
7645
7646 if (size == 64)
7647 {
7648 if (neon_bits_same_in_bytes (immhi)
7649 && neon_bits_same_in_bytes (immlo))
c19d1205 7650 {
8335d6aa
JW		 7651 if (*op == 1)
7652 return FAIL;
7653 *immbits = (neon_squash_bits (immhi) << 4)
7654 | neon_squash_bits (immlo);
7655 *op = 1;
7656 return 0xe;
c19d1205 7657 }
a737bd4d 7658
8335d6aa
JW		 7659 if (immhi != immlo)
7660 return FAIL;
7661 }
a737bd4d 7662
8335d6aa 7663 if (size >= 32)
09d92015 7664 {
8335d6aa 7665 if (immlo == (immlo & 0x000000ff))
c19d1205 7666 {
8335d6aa
JW		 7667 *immbits = immlo;
7668 return 0x0;
c19d1205 7669 }
8335d6aa 7670 else if (immlo == (immlo & 0x0000ff00))
c19d1205 7671 {
8335d6aa
JW		 7672 *immbits = immlo >> 8;
7673 return 0x2;
c19d1205 7674 }
8335d6aa
JW		 7675 else if (immlo == (immlo & 0x00ff0000))
7676 {
7677 *immbits = immlo >> 16;
7678 return 0x4;
7679 }
7680 else if (immlo == (immlo & 0xff000000))
7681 {
7682 *immbits = immlo >> 24;
7683 return 0x6;
7684 }
7685 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
7686 {
7687 *immbits = (immlo >> 8) & 0xff;
7688 return 0xc;
7689 }
7690 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
7691 {
7692 *immbits = (immlo >> 16) & 0xff;
7693 return 0xd;
7694 }
7695
7696 if ((immlo & 0xffff) != (immlo >> 16))
7697 return FAIL;
7698 immlo &= 0xffff;
09d92015 7699 }
a737bd4d 7700
8335d6aa 7701 if (size >= 16)
4962c51a 7702 {
8335d6aa
JW		 7703 if (immlo == (immlo & 0x000000ff))
7704 {
7705 *immbits = immlo;
7706 return 0x8;
7707 }
7708 else if (immlo == (immlo & 0x0000ff00))
7709 {
7710 *immbits = immlo >> 8;
7711 return 0xa;
7712 }
7713
7714 if ((immlo & 0xff) != (immlo >> 8))
7715 return FAIL;
7716 immlo &= 0xff;
4962c51a
MS		 7717 }
7718
8335d6aa
JW		 7719 if (immlo == (immlo & 0x000000ff))
7720 {
7721 /* Don't allow MVN with 8-bit immediate. */
7722 if (*op == 1)
7723 return FAIL;
7724 *immbits = immlo;
7725 return 0xe;
7726 }
26d97720 7727
8335d6aa 7728 return FAIL;
c19d1205 7729}
a737bd4d 7730
8335d6aa
JW		 7731enum lit_type
7732{
7733 CONST_THUMB,
7734 CONST_ARM,
7735 CONST_VEC
7736};
7737
c19d1205
ZW		 7738/* inst.reloc.exp describes an "=expr" load pseudo-operation.
7739 Determine whether it can be performed with a move instruction; if
7740 it can, convert inst.instruction to that move instruction and
c921be7d
NC		 7741 return TRUE; if it can't, convert inst.instruction to a literal-pool
7742 load and return FALSE. If this is not a valid thing to do in the
7743 current context, set inst.error and return TRUE.
a737bd4d 7744
c19d1205
ZW		 7745 inst.operands[i] describes the destination register. */
7746
c921be7d 7747static bfd_boolean
8335d6aa 7748move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
c19d1205 7749{
53365c0d 7750 unsigned long tbit;
8335d6aa
JW		 7751 bfd_boolean thumb_p = (t == CONST_THUMB);
7752 bfd_boolean arm_p = (t == CONST_ARM);
7753 bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;
53365c0d
PB		 7754
7755 if (thumb_p)
7756 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7757 else
7758 tbit = LOAD_BIT;
7759
7760 if ((inst.instruction & tbit) == 0)
09d92015 7761 {
c19d1205 7762 inst.error = _("invalid pseudo operation");
c921be7d 7763 return TRUE;
09d92015 7764 }
8335d6aa
JW		 7765 if (inst.reloc.exp.X_op != O_constant
7766 && inst.reloc.exp.X_op != O_symbol
7767 && inst.reloc.exp.X_op != O_big)
09d92015
MM		 7768 {
7769 inst.error = _("constant expression expected");
c921be7d 7770 return TRUE;
09d92015 7771 }
8335d6aa
JW		 7772 if ((inst.reloc.exp.X_op == O_constant
7773 || inst.reloc.exp.X_op == O_big)
7774 && !inst.operands[i].issingle)
7775 {
7776 if (thumb_p && inst.reloc.exp.X_op == O_constant)
7777 {
7778 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7779 {
7780 /* This can be done with a mov(1) instruction. */
7781 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7782 inst.instruction |= inst.reloc.exp.X_add_number;
7783 return TRUE;
7784 }
7785 }
7786 else if (arm_p && inst.reloc.exp.X_op == O_constant)
7787 {
7788 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7789 if (value != FAIL)
7790 {
7791 /* This can be done with a mov instruction. */
7792 inst.instruction &= LITERAL_MASK;
7793 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7794 inst.instruction |= value & 0xfff;
7795 return TRUE;
7796 }
7797
7798 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7799 if (value != FAIL)
7800 {
7801 /* This can be done with a mvn instruction. */
7802 inst.instruction &= LITERAL_MASK;
7803 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7804 inst.instruction |= value & 0xfff;
7805 return TRUE;
7806 }
7807 }
7808 else if (vec64_p)
7809 {
7810 int op = 0;
7811 unsigned immbits = 0;
7812 unsigned immlo = inst.operands[1].imm;
7813 unsigned immhi = inst.operands[1].regisimm
7814 ? inst.operands[1].reg
7815 : inst.reloc.exp.X_unsigned
7816 ? 0
2569ceb0 7817 : ((bfd_int64_t)((int) immlo)) >> 32;
8335d6aa
JW		 7818 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
7819 &op, 64, NT_invtype);
7820
7821 if (cmode == FAIL)
7822 {
7823 neon_invert_size (&immlo, &immhi, 64);
7824 op = !op;
7825 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
7826 &op, 64, NT_invtype);
7827 }
7828 if (cmode != FAIL)
7829 {
7830 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
7831 | (1 << 23)
7832 | (cmode << 8)
7833 | (op << 5)
7834 | (1 << 4);
7835 /* Fill other bits in vmov encoding for both thumb and arm. */
7836 if (thumb_mode)
7837 inst.instruction |= (0x7 << 29) | (0xF << 24);
7838 else
7839 inst.instruction |= (0xF << 28) | (0x1 << 25);
7840 neon_write_immbits (immbits);
7841 return TRUE;
7842 }
7843 }
7844 }
7845
7846 if (add_to_lit_pool ((!inst.operands[i].isvec
7847 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
7848 return TRUE;
7849
7850 inst.operands[1].reg = REG_PC;
7851 inst.operands[1].isreg = 1;
7852 inst.operands[1].preind = 1;
7853 inst.reloc.pc_rel = 1;
7854 inst.reloc.type = (thumb_p
7855 ? BFD_RELOC_ARM_THUMB_OFFSET
7856 : (mode_3
7857 ? BFD_RELOC_ARM_HWLITERAL
7858 : BFD_RELOC_ARM_LITERAL));
7859 return FALSE;
7860}
7861
7862/* inst.operands[i] was set up by parse_address. Encode it into an
7863 ARM-format instruction. Reject all forms which cannot be encoded
7864 into a coprocessor load/store instruction. If wb_ok is false,
7865 reject use of writeback; if unind_ok is false, reject use of
7866 unindexed addressing. If reloc_override is not 0, use it instead
7867 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7868 (in which case it is preserved). */
7869
7870static int
7871encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7872{
7873 if (!inst.operands[i].isreg)
7874 {
7875 gas_assert (inst.operands[0].isvec);
7876 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
7877 return SUCCESS;
7878 }
7879
7880 inst.instruction |= inst.operands[i].reg << 16;
7881
7882 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7883
7884 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7885 {
7886 gas_assert (!inst.operands[i].writeback);
7887 if (!unind_ok)
7888 {
7889 inst.error = _("instruction does not support unindexed addressing");
7890 return FAIL;
7891 }
7892 inst.instruction |= inst.operands[i].imm;
7893 inst.instruction |= INDEX_UP;
7894 return SUCCESS;
7895 }
7896
7897 if (inst.operands[i].preind)
7898 inst.instruction |= PRE_INDEX;
7899
7900 if (inst.operands[i].writeback)
09d92015 7901 {
8335d6aa 7902 if (inst.operands[i].reg == REG_PC)
c19d1205 7903 {
8335d6aa
JW		 7904 inst.error = _("pc may not be used with write-back");
7905 return FAIL;
c19d1205 7906 }
8335d6aa 7907 if (!wb_ok)
c19d1205 7908 {
8335d6aa
JW		 7909 inst.error = _("instruction does not support writeback");
7910 return FAIL;
c19d1205 7911 }
8335d6aa 7912 inst.instruction |= WRITE_BACK;
09d92015
MM		 7913 }
7914
8335d6aa
JW		 7915 if (reloc_override)
7916 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7917 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7918 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7919 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
c19d1205 7920 {
8335d6aa
JW		 7921 if (thumb_mode)
7922 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7923 else
7924 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205 7925 }
8335d6aa
JW		 7926
7927 /* Prefer + for zero encoded value. */
7928 if (!inst.operands[i].negative)
7929 inst.instruction |= INDEX_UP;
7930
7931 return SUCCESS;
09d92015
MM		 7932}
7933
5f4273c7 7934/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW		 7935 First some generics; their names are taken from the conventional
7936 bit positions for register arguments in ARM format instructions. */
09d92015 7937
a737bd4d 7938static void
c19d1205 7939do_noargs (void)
09d92015 7940{
c19d1205 7941}
a737bd4d 7942
c19d1205
ZW		 7943static void
7944do_rd (void)
7945{
7946 inst.instruction |= inst.operands[0].reg << 12;
7947}
a737bd4d 7948
c19d1205
ZW		 7949static void
7950do_rd_rm (void)
7951{
7952 inst.instruction |= inst.operands[0].reg << 12;
7953 inst.instruction |= inst.operands[1].reg;
7954}
09d92015 7955
9eb6c0f1
MGD		 7956static void
7957do_rm_rn (void)
7958{
7959 inst.instruction |= inst.operands[0].reg;
7960 inst.instruction |= inst.operands[1].reg << 16;
7961}
7962
c19d1205
ZW		 7963static void
7964do_rd_rn (void)
7965{
7966 inst.instruction |= inst.operands[0].reg << 12;
7967 inst.instruction |= inst.operands[1].reg << 16;
7968}
a737bd4d 7969
c19d1205
ZW		 7970static void
7971do_rn_rd (void)
7972{
7973 inst.instruction |= inst.operands[0].reg << 16;
7974 inst.instruction |= inst.operands[1].reg << 12;
7975}
09d92015 7976
59d09be6
MGD		 7977static bfd_boolean
7978check_obsolete (const arm_feature_set *feature, const char *msg)
7979{
7980 if (ARM_CPU_IS_ANY (cpu_variant))
7981 {
7982 as_warn ("%s", msg);
7983 return TRUE;
7984 }
7985 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7986 {
7987 as_bad ("%s", msg);
7988 return TRUE;
7989 }
7990
7991 return FALSE;
7992}
7993
c19d1205
ZW		 7994static void
7995do_rd_rm_rn (void)
7996{
9a64e435 7997 unsigned Rn = inst.operands[2].reg;
708587a4 7998 /* Enforce restrictions on SWP instruction. */
9a64e435 7999 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG		 8000 {
8001 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8002 _("Rn must not overlap other operands"));
8003
59d09be6
MGD		 8004 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8005 */
8006 if (!check_obsolete (&arm_ext_v8,
8007 _("swp{b} use is obsoleted for ARMv8 and later"))
8008 && warn_on_deprecated
8009 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
8010 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 8011 }
59d09be6 8012
c19d1205
ZW		 8013 inst.instruction |= inst.operands[0].reg << 12;
8014 inst.instruction |= inst.operands[1].reg;
9a64e435 8015 inst.instruction |= Rn << 16;
c19d1205 8016}
09d92015 8017
c19d1205
ZW		 8018static void
8019do_rd_rn_rm (void)
8020{
8021 inst.instruction |= inst.operands[0].reg << 12;
8022 inst.instruction |= inst.operands[1].reg << 16;
8023 inst.instruction |= inst.operands[2].reg;
8024}
a737bd4d 8025
c19d1205
ZW		 8026static void
8027do_rm_rd_rn (void)
8028{
5be8be5d
DG		 8029 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8030 constraint (((inst.reloc.exp.X_op != O_constant
8031 && inst.reloc.exp.X_op != O_illegal)
8032 || inst.reloc.exp.X_add_number != 0),
8033 BAD_ADDR_MODE);
c19d1205
ZW		 8034 inst.instruction |= inst.operands[0].reg;
8035 inst.instruction |= inst.operands[1].reg << 12;
8036 inst.instruction |= inst.operands[2].reg << 16;
8037}
09d92015 8038
c19d1205
ZW		 8039static void
8040do_imm0 (void)
8041{
8042 inst.instruction |= inst.operands[0].imm;
8043}
09d92015 8044
c19d1205
ZW		 8045static void
8046do_rd_cpaddr (void)
8047{
8048 inst.instruction |= inst.operands[0].reg << 12;
8049 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 8050}
a737bd4d 8051
c19d1205
ZW		 8052/* ARM instructions, in alphabetical order by function name (except
8053 that wrapper functions appear immediately after the function they
8054 wrap). */
09d92015 8055
c19d1205
ZW		 8056/* This is a pseudo-op of the form "adr rd, label" to be converted
8057 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM		 8058
8059static void
c19d1205 8060do_adr (void)
09d92015 8061{
c19d1205 8062 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 8063
c19d1205
ZW		 8064 /* Frag hacking will turn this into a sub instruction if the offset turns
8065 out to be negative. */
8066 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
c19d1205 8067 inst.reloc.pc_rel = 1;
2fc8bdac 8068 inst.reloc.exp.X_add_number -= 8;
c19d1205 8069}
b99bd4ef 8070
c19d1205
ZW		 8071/* This is a pseudo-op of the form "adrl rd, label" to be converted
8072 into a relative address of the form:
8073 add rd, pc, #low(label-.-8)"
8074 add rd, rd, #high(label-.-8)" */
b99bd4ef 8075
c19d1205
ZW		 8076static void
8077do_adrl (void)
8078{
8079 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 8080
c19d1205
ZW		 8081 /* Frag hacking will turn this into a sub instruction if the offset turns
8082 out to be negative. */
8083 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
c19d1205
ZW		 8084 inst.reloc.pc_rel = 1;
8085 inst.size = INSN_SIZE * 2;
2fc8bdac 8086 inst.reloc.exp.X_add_number -= 8;
b99bd4ef
NC		 8087}
8088
b99bd4ef 8089static void
c19d1205 8090do_arit (void)
b99bd4ef 8091{
c19d1205
ZW		 8092 if (!inst.operands[1].present)
8093 inst.operands[1].reg = inst.operands[0].reg;
8094 inst.instruction |= inst.operands[0].reg << 12;
8095 inst.instruction |= inst.operands[1].reg << 16;
8096 encode_arm_shifter_operand (2);
8097}
b99bd4ef 8098
62b3e311
PB		 8099static void
8100do_barrier (void)
8101{
8102 if (inst.operands[0].present)
ccb84d65 8103 inst.instruction |= inst.operands[0].imm;
62b3e311
PB		 8104 else
8105 inst.instruction |= 0xf;
8106}
8107
c19d1205
ZW		 8108static void
8109do_bfc (void)
8110{
8111 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8112 constraint (msb > 32, _("bit-field extends past end of register"));
8113 /* The instruction encoding stores the LSB and MSB,
8114 not the LSB and width. */
8115 inst.instruction |= inst.operands[0].reg << 12;
8116 inst.instruction |= inst.operands[1].imm << 7;
8117 inst.instruction |= (msb - 1) << 16;
8118}
b99bd4ef 8119
c19d1205
ZW		 8120static void
8121do_bfi (void)
8122{
8123 unsigned int msb;
b99bd4ef 8124
c19d1205
ZW		 8125 /* #0 in second position is alternative syntax for bfc, which is
8126 the same instruction but with REG_PC in the Rm field. */
8127 if (!inst.operands[1].isreg)
8128 inst.operands[1].reg = REG_PC;
b99bd4ef 8129
c19d1205
ZW		 8130 msb = inst.operands[2].imm + inst.operands[3].imm;
8131 constraint (msb > 32, _("bit-field extends past end of register"));
8132 /* The instruction encoding stores the LSB and MSB,
8133 not the LSB and width. */
8134 inst.instruction |= inst.operands[0].reg << 12;
8135 inst.instruction |= inst.operands[1].reg;
8136 inst.instruction |= inst.operands[2].imm << 7;
8137 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC		 8138}
8139
b99bd4ef 8140static void
c19d1205 8141do_bfx (void)
b99bd4ef 8142{
c19d1205
ZW		 8143 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8144 _("bit-field extends past end of register"));
8145 inst.instruction |= inst.operands[0].reg << 12;
8146 inst.instruction |= inst.operands[1].reg;
8147 inst.instruction |= inst.operands[2].imm << 7;
8148 inst.instruction |= (inst.operands[3].imm - 1) << 16;
8149}
09d92015 8150
c19d1205
ZW		 8151/* ARM V5 breakpoint instruction (argument parse)
8152 BKPT <16 bit unsigned immediate>
8153 Instruction is not conditional.
8154 The bit pattern given in insns[] has the COND_ALWAYS condition,
8155 and it is an error if the caller tried to override that. */
b99bd4ef 8156
c19d1205
ZW		 8157static void
8158do_bkpt (void)
8159{
8160 /* Top 12 of 16 bits to bits 19:8. */
8161 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 8162
c19d1205
ZW		 8163 /* Bottom 4 of 16 bits to bits 3:0. */
8164 inst.instruction |= inst.operands[0].imm & 0xf;
8165}
09d92015 8166
c19d1205
ZW		 8167static void
8168encode_branch (int default_reloc)
8169{
8170 if (inst.operands[0].hasreloc)
8171 {
0855e32b
NS		 8172 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8173 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
8174 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8175 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
8176 ? BFD_RELOC_ARM_PLT32
8177 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 8178 }
b99bd4ef 8179 else
9ae92b05 8180 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
2fc8bdac 8181 inst.reloc.pc_rel = 1;
b99bd4ef
NC		 8182}
8183
b99bd4ef 8184static void
c19d1205 8185do_branch (void)
b99bd4ef 8186{
39b41c9c
PB		 8187#ifdef OBJ_ELF
8188 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8189 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8190 else
8191#endif
8192 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8193}
8194
8195static void
8196do_bl (void)
8197{
8198#ifdef OBJ_ELF
8199 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8200 {
8201 if (inst.cond == COND_ALWAYS)
8202 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
8203 else
8204 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8205 }
8206 else
8207#endif
8208 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 8209}
b99bd4ef 8210
c19d1205
ZW		 8211/* ARM V5 branch-link-exchange instruction (argument parse)
8212 BLX <target_addr> ie BLX(1)
8213 BLX{<condition>} <Rm> ie BLX(2)
8214 Unfortunately, there are two different opcodes for this mnemonic.
8215 So, the insns[].value is not used, and the code here zaps values
8216 into inst.instruction.
8217 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 8218
c19d1205
ZW		 8219static void
8220do_blx (void)
8221{
8222 if (inst.operands[0].isreg)
b99bd4ef 8223 {
c19d1205
ZW		 8224 /* Arg is a register; the opcode provided by insns[] is correct.
8225 It is not illegal to do "blx pc", just useless. */
8226 if (inst.operands[0].reg == REG_PC)
8227 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 8228
c19d1205
ZW		 8229 inst.instruction |= inst.operands[0].reg;
8230 }
8231 else
b99bd4ef 8232 {
c19d1205 8233 /* Arg is an address; this instruction cannot be executed
267bf995
RR		 8234 conditionally, and the opcode must be adjusted.
8235 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8236 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 8237 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 8238 inst.instruction = 0xfa000000;
267bf995 8239 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 8240 }
c19d1205
ZW		 8241}
8242
8243static void
8244do_bx (void)
8245{
845b51d6
PB		 8246 bfd_boolean want_reloc;
8247
c19d1205
ZW		 8248 if (inst.operands[0].reg == REG_PC)
8249 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 8250
c19d1205 8251 inst.instruction |= inst.operands[0].reg;
845b51d6
PB		 8252 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8253 it is for ARMv4t or earlier. */
8254 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
8255 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
8256 want_reloc = TRUE;
8257
5ad34203 8258#ifdef OBJ_ELF
845b51d6 8259 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 8260#endif
584206db 8261 want_reloc = FALSE;
845b51d6
PB		 8262
8263 if (want_reloc)
8264 inst.reloc.type = BFD_RELOC_ARM_V4BX;
09d92015
MM		 8265}
8266
c19d1205
ZW		 8267
8268/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC		 8269
8270static void
c19d1205 8271do_bxj (void)
a737bd4d 8272{
c19d1205
ZW		 8273 if (inst.operands[0].reg == REG_PC)
8274 as_tsktsk (_("use of r15 in bxj is not really useful"));
8275
8276 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC		 8277}
8278
c19d1205
ZW		 8279/* Co-processor data operation:
8280 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8281 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8282static void
8283do_cdp (void)
8284{
8285 inst.instruction |= inst.operands[0].reg << 8;
8286 inst.instruction |= inst.operands[1].imm << 20;
8287 inst.instruction |= inst.operands[2].reg << 12;
8288 inst.instruction |= inst.operands[3].reg << 16;
8289 inst.instruction |= inst.operands[4].reg;
8290 inst.instruction |= inst.operands[5].imm << 5;
8291}
a737bd4d
NC		 8292
8293static void
c19d1205 8294do_cmp (void)
a737bd4d 8295{
c19d1205
ZW		 8296 inst.instruction |= inst.operands[0].reg << 16;
8297 encode_arm_shifter_operand (1);
a737bd4d
NC		 8298}
8299
c19d1205
ZW		 8300/* Transfer between coprocessor and ARM registers.
8301 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8302 MRC2
8303 MCR{cond}
8304 MCR2
8305
8306 No special properties. */
09d92015 8307
dcbd0d71
MGD		 8308struct deprecated_coproc_regs_s
8309{
8310 unsigned cp;
8311 int opc1;
8312 unsigned crn;
8313 unsigned crm;
8314 int opc2;
8315 arm_feature_set deprecated;
8316 arm_feature_set obsoleted;
8317 const char *dep_msg;
8318 const char *obs_msg;
8319};
8320
8321#define DEPR_ACCESS_V8 \
8322 N_("This coprocessor register access is deprecated in ARMv8")
8323
8324/* Table of all deprecated coprocessor registers. */
8325static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
8326{
8327 {15, 0, 7, 10, 5, /* CP15DMB. */
8328 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8329 DEPR_ACCESS_V8, NULL},
8330 {15, 0, 7, 10, 4, /* CP15DSB. */
8331 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8332 DEPR_ACCESS_V8, NULL},
8333 {15, 0, 7, 5, 4, /* CP15ISB. */
8334 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8335 DEPR_ACCESS_V8, NULL},
8336 {14, 6, 1, 0, 0, /* TEEHBR. */
8337 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8338 DEPR_ACCESS_V8, NULL},
8339 {14, 6, 0, 0, 0, /* TEECR. */
8340 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8341 DEPR_ACCESS_V8, NULL},
8342};
8343
8344#undef DEPR_ACCESS_V8
8345
8346static const size_t deprecated_coproc_reg_count =
8347 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
8348
09d92015 8349static void
c19d1205 8350do_co_reg (void)
09d92015 8351{
fdfde340 8352 unsigned Rd;
dcbd0d71 8353 size_t i;
fdfde340
JM		 8354
8355 Rd = inst.operands[2].reg;
8356 if (thumb_mode)
8357 {
8358 if (inst.instruction == 0xee000010
8359 || inst.instruction == 0xfe000010)
8360 /* MCR, MCR2 */
8361 reject_bad_reg (Rd);
8362 else
8363 /* MRC, MRC2 */
8364 constraint (Rd == REG_SP, BAD_SP);
8365 }
8366 else
8367 {
8368 /* MCR */
8369 if (inst.instruction == 0xe000010)
8370 constraint (Rd == REG_PC, BAD_PC);
8371 }
8372
dcbd0d71
MGD		 8373 for (i = 0; i < deprecated_coproc_reg_count; ++i)
8374 {
8375 const struct deprecated_coproc_regs_s *r =
8376 deprecated_coproc_regs + i;
8377
8378 if (inst.operands[0].reg == r->cp
8379 && inst.operands[1].imm == r->opc1
8380 && inst.operands[3].reg == r->crn
8381 && inst.operands[4].reg == r->crm
8382 && inst.operands[5].imm == r->opc2)
8383 {
b10bf8c5 8384 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 8385 && warn_on_deprecated
dcbd0d71
MGD		 8386 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
8387 as_warn ("%s", r->dep_msg);
8388 }
8389 }
fdfde340 8390
c19d1205
ZW		 8391 inst.instruction |= inst.operands[0].reg << 8;
8392 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 8393 inst.instruction |= Rd << 12;
c19d1205
ZW		 8394 inst.instruction |= inst.operands[3].reg << 16;
8395 inst.instruction |= inst.operands[4].reg;
8396 inst.instruction |= inst.operands[5].imm << 5;
8397}
09d92015 8398
c19d1205
ZW		 8399/* Transfer between coprocessor register and pair of ARM registers.
8400 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8401 MCRR2
8402 MRRC{cond}
8403 MRRC2
b99bd4ef 8404
c19d1205 8405 Two XScale instructions are special cases of these:
09d92015 8406
c19d1205
ZW		 8407 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8408 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 8409
5f4273c7 8410 Result unpredictable if Rd or Rn is R15. */
a737bd4d 8411
c19d1205
ZW		 8412static void
8413do_co_reg2c (void)
8414{
fdfde340
JM		 8415 unsigned Rd, Rn;
8416
8417 Rd = inst.operands[2].reg;
8418 Rn = inst.operands[3].reg;
8419
8420 if (thumb_mode)
8421 {
8422 reject_bad_reg (Rd);
8423 reject_bad_reg (Rn);
8424 }
8425 else
8426 {
8427 constraint (Rd == REG_PC, BAD_PC);
8428 constraint (Rn == REG_PC, BAD_PC);
8429 }
8430
c19d1205
ZW		 8431 inst.instruction |= inst.operands[0].reg << 8;
8432 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM		 8433 inst.instruction |= Rd << 12;
8434 inst.instruction |= Rn << 16;
c19d1205 8435 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC		 8436}
8437
c19d1205
ZW		 8438static void
8439do_cpsi (void)
8440{
8441 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB		 8442 if (inst.operands[1].present)
8443 {
8444 inst.instruction |= CPSI_MMOD;
8445 inst.instruction |= inst.operands[1].imm;
8446 }
c19d1205 8447}
b99bd4ef 8448
62b3e311
PB		 8449static void
8450do_dbg (void)
8451{
8452 inst.instruction |= inst.operands[0].imm;
8453}
8454
eea54501
MGD		 8455static void
8456do_div (void)
8457{
8458 unsigned Rd, Rn, Rm;
8459
8460 Rd = inst.operands[0].reg;
8461 Rn = (inst.operands[1].present
8462 ? inst.operands[1].reg : Rd);
8463 Rm = inst.operands[2].reg;
8464
8465 constraint ((Rd == REG_PC), BAD_PC);
8466 constraint ((Rn == REG_PC), BAD_PC);
8467 constraint ((Rm == REG_PC), BAD_PC);
8468
8469 inst.instruction |= Rd << 16;
8470 inst.instruction |= Rn << 0;
8471 inst.instruction |= Rm << 8;
8472}
8473
b99bd4ef 8474static void
c19d1205 8475do_it (void)
b99bd4ef 8476{
c19d1205 8477 /* There is no IT instruction in ARM mode. We
e07e6e58
NC		 8478 process it to do the validation as if in
8479 thumb mode, just in case the code gets
8480 assembled for thumb using the unified syntax. */
8481
c19d1205 8482 inst.size = 0;
e07e6e58
NC		 8483 if (unified_syntax)
8484 {
8485 set_it_insn_type (IT_INSN);
8486 now_it.mask = (inst.instruction & 0xf) | 0x10;
8487 now_it.cc = inst.operands[0].imm;
8488 }
09d92015 8489}
b99bd4ef 8490
6530b175
NC		 8491/* If there is only one register in the register list,
8492 then return its register number. Otherwise return -1. */
8493static int
8494only_one_reg_in_list (int range)
8495{
8496 int i = ffs (range) - 1;
8497 return (i > 15 || range != (1 << i)) ? -1 : i;
8498}
8499
09d92015 8500static void
6530b175 8501encode_ldmstm(int from_push_pop_mnem)
ea6ef066 8502{
c19d1205
ZW		 8503 int base_reg = inst.operands[0].reg;
8504 int range = inst.operands[1].imm;
6530b175 8505 int one_reg;
ea6ef066 8506
c19d1205
ZW		 8507 inst.instruction |= base_reg << 16;
8508 inst.instruction |= range;
ea6ef066 8509
c19d1205
ZW		 8510 if (inst.operands[1].writeback)
8511 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 8512
c19d1205 8513 if (inst.operands[0].writeback)
ea6ef066 8514 {
c19d1205
ZW		 8515 inst.instruction |= WRITE_BACK;
8516 /* Check for unpredictable uses of writeback. */
8517 if (inst.instruction & LOAD_BIT)
09d92015 8518 {
c19d1205
ZW		 8519 /* Not allowed in LDM type 2. */
8520 if ((inst.instruction & LDM_TYPE_2_OR_3)
8521 && ((range & (1 << REG_PC)) == 0))
8522 as_warn (_("writeback of base register is UNPREDICTABLE"));
8523 /* Only allowed if base reg not in list for other types. */
8524 else if (range & (1 << base_reg))
8525 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8526 }
8527 else /* STM. */
8528 {
8529 /* Not allowed for type 2. */
8530 if (inst.instruction & LDM_TYPE_2_OR_3)
8531 as_warn (_("writeback of base register is UNPREDICTABLE"));
8532 /* Only allowed if base reg not in list, or first in list. */
8533 else if ((range & (1 << base_reg))
8534 && (range & ((1 << base_reg) - 1)))
8535 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 8536 }
ea6ef066 8537 }
6530b175
NC		 8538
8539 /* If PUSH/POP has only one register, then use the A2 encoding. */
8540 one_reg = only_one_reg_in_list (range);
8541 if (from_push_pop_mnem && one_reg >= 0)
8542 {
8543 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
8544
8545 inst.instruction &= A_COND_MASK;
8546 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
8547 inst.instruction |= one_reg << 12;
8548 }
8549}
8550
8551static void
8552do_ldmstm (void)
8553{
8554 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC		 8555}
8556
c19d1205
ZW		 8557/* ARMv5TE load-consecutive (argument parse)
8558 Mode is like LDRH.
8559
8560 LDRccD R, mode
8561 STRccD R, mode. */
8562
a737bd4d 8563static void
c19d1205 8564do_ldrd (void)
a737bd4d 8565{
c19d1205 8566 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 8567 _("first transfer register must be even"));
c19d1205
ZW		 8568 constraint (inst.operands[1].present
8569 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 8570 _("can only transfer two consecutive registers"));
c19d1205
ZW		 8571 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8572 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 8573
c19d1205
ZW		 8574 if (!inst.operands[1].present)
8575 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 8576
c56791bb
RE		 8577 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8578 register and the first register written; we have to diagnose
8579 overlap between the base and the second register written here. */
ea6ef066 8580
c56791bb
RE		 8581 if (inst.operands[2].reg == inst.operands[1].reg
8582 && (inst.operands[2].writeback || inst.operands[2].postind))
8583 as_warn (_("base register written back, and overlaps "
8584 "second transfer register"));
b05fe5cf 8585
c56791bb
RE		 8586 if (!(inst.instruction & V4_STR_BIT))
8587 {
c19d1205 8588 /* For an index-register load, the index register must not overlap the
c56791bb
RE		 8589 destination (even if not write-back). */
8590 if (inst.operands[2].immisreg
8591 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8592 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8593 as_warn (_("index register overlaps transfer register"));
b05fe5cf 8594 }
c19d1205
ZW		 8595 inst.instruction |= inst.operands[0].reg << 12;
8596 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW		 8597}
8598
8599static void
c19d1205 8600do_ldrex (void)
b05fe5cf 8601{
c19d1205
ZW		 8602 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8603 || inst.operands[1].postind || inst.operands[1].writeback
8604 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC		 8605 || inst.operands[1].negative
8606 /* This can arise if the programmer has written
8607 strex rN, rM, foo
8608 or if they have mistakenly used a register name as the last
8609 operand, eg:
8610 strex rN, rM, rX
8611 It is very difficult to distinguish between these two cases
8612 because "rX" might actually be a label. ie the register
8613 name has been occluded by a symbol of the same name. So we
8614 just generate a general 'bad addressing mode' type error
8615 message and leave it up to the programmer to discover the
8616 true cause and fix their mistake. */
8617 || (inst.operands[1].reg == REG_PC),
8618 BAD_ADDR_MODE);
b05fe5cf 8619
c19d1205
ZW		 8620 constraint (inst.reloc.exp.X_op != O_constant
8621 || inst.reloc.exp.X_add_number != 0,
8622 _("offset must be zero in ARM encoding"));
b05fe5cf 8623
5be8be5d
DG		 8624 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8625
c19d1205
ZW		 8626 inst.instruction |= inst.operands[0].reg << 12;
8627 inst.instruction |= inst.operands[1].reg << 16;
8628 inst.reloc.type = BFD_RELOC_UNUSED;
b05fe5cf
ZW		 8629}
8630
8631static void
c19d1205 8632do_ldrexd (void)
b05fe5cf 8633{
c19d1205
ZW		 8634 constraint (inst.operands[0].reg % 2 != 0,
8635 _("even register required"));
8636 constraint (inst.operands[1].present
8637 && inst.operands[1].reg != inst.operands[0].reg + 1,
8638 _("can only load two consecutive registers"));
8639 /* If op 1 were present and equal to PC, this function wouldn't
8640 have been called in the first place. */
8641 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 8642
c19d1205
ZW		 8643 inst.instruction |= inst.operands[0].reg << 12;
8644 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW		 8645}
8646
1be5fd2e
NC		 8647/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8648 which is not a multiple of four is UNPREDICTABLE. */
8649static void
8650check_ldr_r15_aligned (void)
8651{
8652 constraint (!(inst.operands[1].immisreg)
8653 && (inst.operands[0].reg == REG_PC
8654 && inst.operands[1].reg == REG_PC
8655 && (inst.reloc.exp.X_add_number & 0x3)),
8656 _("ldr to register 15 must be 4-byte alligned"));
8657}
8658
b05fe5cf 8659static void
c19d1205 8660do_ldst (void)
b05fe5cf 8661{
c19d1205
ZW		 8662 inst.instruction |= inst.operands[0].reg << 12;
8663 if (!inst.operands[1].isreg)
8335d6aa 8664 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
b05fe5cf 8665 return;
c19d1205 8666 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 8667 check_ldr_r15_aligned ();
b05fe5cf
ZW		 8668}
8669
8670static void
c19d1205 8671do_ldstt (void)
b05fe5cf 8672{
c19d1205
ZW		 8673 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8674 reject [Rn,...]. */
8675 if (inst.operands[1].preind)
b05fe5cf 8676 {
bd3ba5d1
NC		 8677 constraint (inst.reloc.exp.X_op != O_constant
8678 || inst.reloc.exp.X_add_number != 0,
c19d1205 8679 _("this instruction requires a post-indexed address"));
b05fe5cf 8680
c19d1205
ZW		 8681 inst.operands[1].preind = 0;
8682 inst.operands[1].postind = 1;
8683 inst.operands[1].writeback = 1;
b05fe5cf 8684 }
c19d1205
ZW		 8685 inst.instruction |= inst.operands[0].reg << 12;
8686 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8687}
b05fe5cf 8688
c19d1205 8689/* Halfword and signed-byte load/store operations. */
b05fe5cf 8690
c19d1205
ZW		 8691static void
8692do_ldstv4 (void)
8693{
ff4a8d2b 8694 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW		 8695 inst.instruction |= inst.operands[0].reg << 12;
8696 if (!inst.operands[1].isreg)
8335d6aa 8697 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
b05fe5cf 8698 return;
c19d1205 8699 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW		 8700}
8701
8702static void
c19d1205 8703do_ldsttv4 (void)
b05fe5cf 8704{
c19d1205
ZW		 8705 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8706 reject [Rn,...]. */
8707 if (inst.operands[1].preind)
b05fe5cf 8708 {
bd3ba5d1
NC		 8709 constraint (inst.reloc.exp.X_op != O_constant
8710 || inst.reloc.exp.X_add_number != 0,
c19d1205 8711 _("this instruction requires a post-indexed address"));
b05fe5cf 8712
c19d1205
ZW		 8713 inst.operands[1].preind = 0;
8714 inst.operands[1].postind = 1;
8715 inst.operands[1].writeback = 1;
b05fe5cf 8716 }
c19d1205
ZW		 8717 inst.instruction |= inst.operands[0].reg << 12;
8718 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8719}
b05fe5cf 8720
c19d1205
ZW		 8721/* Co-processor register load/store.
8722 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8723static void
8724do_lstc (void)
8725{
8726 inst.instruction |= inst.operands[0].reg << 8;
8727 inst.instruction |= inst.operands[1].reg << 12;
8728 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW		 8729}
8730
b05fe5cf 8731static void
c19d1205 8732do_mlas (void)
b05fe5cf 8733{
8fb9d7b9 8734 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 8735 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 8736 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 8737 && !(inst.instruction & 0x00400000))
8fb9d7b9 8738 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 8739
c19d1205
ZW		 8740 inst.instruction |= inst.operands[0].reg << 16;
8741 inst.instruction |= inst.operands[1].reg;
8742 inst.instruction |= inst.operands[2].reg << 8;
8743 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 8744}
b05fe5cf 8745
c19d1205
ZW		 8746static void
8747do_mov (void)
8748{
8749 inst.instruction |= inst.operands[0].reg << 12;
8750 encode_arm_shifter_operand (1);
8751}
b05fe5cf 8752
c19d1205
ZW		 8753/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8754static void
8755do_mov16 (void)
8756{
b6895b4f
PB		 8757 bfd_vma imm;
8758 bfd_boolean top;
8759
8760 top = (inst.instruction & 0x00400000) != 0;
8761 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8762 _(":lower16: not allowed this instruction"));
8763 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8764 _(":upper16: not allowed instruction"));
c19d1205 8765 inst.instruction |= inst.operands[0].reg << 12;
b6895b4f
PB		 8766 if (inst.reloc.type == BFD_RELOC_UNUSED)
8767 {
8768 imm = inst.reloc.exp.X_add_number;
8769 /* The value is in two pieces: 0:11, 16:19. */
8770 inst.instruction |= (imm & 0x00000fff);
8771 inst.instruction |= (imm & 0x0000f000) << 4;
8772 }
b05fe5cf 8773}
b99bd4ef 8774
037e8744
JB		 8775static void do_vfp_nsyn_opcode (const char *);
8776
8777static int
8778do_vfp_nsyn_mrs (void)
8779{
8780 if (inst.operands[0].isvec)
8781 {
8782 if (inst.operands[1].reg != 1)
477330fc 8783 first_error (_("operand 1 must be FPSCR"));
037e8744
JB		 8784 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8785 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8786 do_vfp_nsyn_opcode ("fmstat");
8787 }
8788 else if (inst.operands[1].isvec)
8789 do_vfp_nsyn_opcode ("fmrx");
8790 else
8791 return FAIL;
5f4273c7 8792
037e8744
JB		 8793 return SUCCESS;
8794}
8795
8796static int
8797do_vfp_nsyn_msr (void)
8798{
8799 if (inst.operands[0].isvec)
8800 do_vfp_nsyn_opcode ("fmxr");
8801 else
8802 return FAIL;
8803
8804 return SUCCESS;
8805}
8806
f7c21dc7
NC		 8807static void
8808do_vmrs (void)
8809{
8810 unsigned Rt = inst.operands[0].reg;
fa94de6b 8811
16d02dc9 8812 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC		 8813 {
8814 inst.error = BAD_SP;
8815 return;
8816 }
8817
8818 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 8819 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC		 8820 {
8821 inst.error = BAD_PC;
8822 return;
8823 }
8824
16d02dc9
JB		 8825 /* If we get through parsing the register name, we just insert the number
8826 generated into the instruction without further validation. */
8827 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC		 8828 inst.instruction |= (Rt << 12);
8829}
8830
8831static void
8832do_vmsr (void)
8833{
8834 unsigned Rt = inst.operands[1].reg;
fa94de6b 8835
f7c21dc7
NC		 8836 if (thumb_mode)
8837 reject_bad_reg (Rt);
8838 else if (Rt == REG_PC)
8839 {
8840 inst.error = BAD_PC;
8841 return;
8842 }
8843
16d02dc9
JB		 8844 /* If we get through parsing the register name, we just insert the number
8845 generated into the instruction without further validation. */
8846 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC		 8847 inst.instruction |= (Rt << 12);
8848}
8849
b99bd4ef 8850static void
c19d1205 8851do_mrs (void)
b99bd4ef 8852{
90ec0d68
MGD		 8853 unsigned br;
8854
037e8744
JB		 8855 if (do_vfp_nsyn_mrs () == SUCCESS)
8856 return;
8857
ff4a8d2b 8858 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 8859 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD		 8860
8861 if (inst.operands[1].isreg)
8862 {
8863 br = inst.operands[1].reg;
8864 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8865 as_bad (_("bad register for mrs"));
8866 }
8867 else
8868 {
8869 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8870 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8871 != (PSR_c|PSR_f),
d2cd1205 8872 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD		 8873 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8874 }
8875
8876 inst.instruction |= br;
c19d1205 8877}
b99bd4ef 8878
c19d1205
ZW		 8879/* Two possible forms:
8880 "{C|S}PSR_<field>, Rm",
8881 "{C|S}PSR_f, #expression". */
b99bd4ef 8882
c19d1205
ZW		 8883static void
8884do_msr (void)
8885{
037e8744
JB		 8886 if (do_vfp_nsyn_msr () == SUCCESS)
8887 return;
8888
c19d1205
ZW		 8889 inst.instruction |= inst.operands[0].imm;
8890 if (inst.operands[1].isreg)
8891 inst.instruction |= inst.operands[1].reg;
8892 else
b99bd4ef 8893 {
c19d1205
ZW		 8894 inst.instruction |= INST_IMMEDIATE;
8895 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8896 inst.reloc.pc_rel = 0;
b99bd4ef 8897 }
b99bd4ef
NC		 8898}
8899
c19d1205
ZW		 8900static void
8901do_mul (void)
a737bd4d 8902{
ff4a8d2b
NC		 8903 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8904
c19d1205
ZW		 8905 if (!inst.operands[2].present)
8906 inst.operands[2].reg = inst.operands[0].reg;
8907 inst.instruction |= inst.operands[0].reg << 16;
8908 inst.instruction |= inst.operands[1].reg;
8909 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 8910
8fb9d7b9
MS		 8911 if (inst.operands[0].reg == inst.operands[1].reg
8912 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8913 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC		 8914}
8915
c19d1205
ZW		 8916/* Long Multiply Parser
8917 UMULL RdLo, RdHi, Rm, Rs
8918 SMULL RdLo, RdHi, Rm, Rs
8919 UMLAL RdLo, RdHi, Rm, Rs
8920 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC		 8921
8922static void
c19d1205 8923do_mull (void)
b99bd4ef 8924{
c19d1205
ZW		 8925 inst.instruction |= inst.operands[0].reg << 12;
8926 inst.instruction |= inst.operands[1].reg << 16;
8927 inst.instruction |= inst.operands[2].reg;
8928 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 8929
682b27ad
PB		 8930 /* rdhi and rdlo must be different. */
8931 if (inst.operands[0].reg == inst.operands[1].reg)
8932 as_tsktsk (_("rdhi and rdlo must be different"));
8933
8934 /* rdhi, rdlo and rm must all be different before armv6. */
8935 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 8936 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 8937 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW		 8938 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8939}
b99bd4ef 8940
c19d1205
ZW		 8941static void
8942do_nop (void)
8943{
e7495e45
NS		 8944 if (inst.operands[0].present
8945 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW		 8946 {
8947 /* Architectural NOP hints are CPSR sets with no bits selected. */
8948 inst.instruction &= 0xf0000000;
e7495e45
NS		 8949 inst.instruction |= 0x0320f000;
8950 if (inst.operands[0].present)
8951 inst.instruction |= inst.operands[0].imm;
c19d1205 8952 }
b99bd4ef
NC		 8953}
8954
c19d1205
ZW		 8955/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8956 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8957 Condition defaults to COND_ALWAYS.
8958 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC		 8959
8960static void
c19d1205 8961do_pkhbt (void)
b99bd4ef 8962{
c19d1205
ZW		 8963 inst.instruction |= inst.operands[0].reg << 12;
8964 inst.instruction |= inst.operands[1].reg << 16;
8965 inst.instruction |= inst.operands[2].reg;
8966 if (inst.operands[3].present)
8967 encode_arm_shift (3);
8968}
b99bd4ef 8969
c19d1205 8970/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 8971
c19d1205
ZW		 8972static void
8973do_pkhtb (void)
8974{
8975 if (!inst.operands[3].present)
b99bd4ef 8976 {
c19d1205
ZW		 8977 /* If the shift specifier is omitted, turn the instruction
8978 into pkhbt rd, rm, rn. */
8979 inst.instruction &= 0xfff00010;
8980 inst.instruction |= inst.operands[0].reg << 12;
8981 inst.instruction |= inst.operands[1].reg;
8982 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 8983 }
8984 else
8985 {
c19d1205
ZW		 8986 inst.instruction |= inst.operands[0].reg << 12;
8987 inst.instruction |= inst.operands[1].reg << 16;
8988 inst.instruction |= inst.operands[2].reg;
8989 encode_arm_shift (3);
b99bd4ef
NC		 8990 }
8991}
8992
c19d1205 8993/* ARMv5TE: Preload-Cache
60e5ef9f 8994 MP Extensions: Preload for write
c19d1205 8995
60e5ef9f 8996 PLD(W) <addr_mode>
c19d1205
ZW		 8997
8998 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC		 8999
9000static void
c19d1205 9001do_pld (void)
b99bd4ef 9002{
c19d1205
ZW		 9003 constraint (!inst.operands[0].isreg,
9004 _("'[' expected after PLD mnemonic"));
9005 constraint (inst.operands[0].postind,
9006 _("post-indexed expression used in preload instruction"));
9007 constraint (inst.operands[0].writeback,
9008 _("writeback used in preload instruction"));
9009 constraint (!inst.operands[0].preind,
9010 _("unindexed addressing used in preload instruction"));
c19d1205
ZW		 9011 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9012}
b99bd4ef 9013
62b3e311
PB		 9014/* ARMv7: PLI <addr_mode> */
9015static void
9016do_pli (void)
9017{
9018 constraint (!inst.operands[0].isreg,
9019 _("'[' expected after PLI mnemonic"));
9020 constraint (inst.operands[0].postind,
9021 _("post-indexed expression used in preload instruction"));
9022 constraint (inst.operands[0].writeback,
9023 _("writeback used in preload instruction"));
9024 constraint (!inst.operands[0].preind,
9025 _("unindexed addressing used in preload instruction"));
9026 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9027 inst.instruction &= ~PRE_INDEX;
9028}
9029
c19d1205
ZW		 9030static void
9031do_push_pop (void)
9032{
9033 inst.operands[1] = inst.operands[0];
9034 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
9035 inst.operands[0].isreg = 1;
9036 inst.operands[0].writeback = 1;
9037 inst.operands[0].reg = REG_SP;
6530b175 9038 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 9039}
b99bd4ef 9040
c19d1205
ZW		 9041/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9042 word at the specified address and the following word
9043 respectively.
9044 Unconditionally executed.
9045 Error if Rn is R15. */
b99bd4ef 9046
c19d1205
ZW		 9047static void
9048do_rfe (void)
9049{
9050 inst.instruction |= inst.operands[0].reg << 16;
9051 if (inst.operands[0].writeback)
9052 inst.instruction |= WRITE_BACK;
9053}
b99bd4ef 9054
c19d1205 9055/* ARM V6 ssat (argument parse). */
b99bd4ef 9056
c19d1205
ZW		 9057static void
9058do_ssat (void)
9059{
9060 inst.instruction |= inst.operands[0].reg << 12;
9061 inst.instruction |= (inst.operands[1].imm - 1) << 16;
9062 inst.instruction |= inst.operands[2].reg;
b99bd4ef 9063
c19d1205
ZW		 9064 if (inst.operands[3].present)
9065 encode_arm_shift (3);
b99bd4ef
NC		 9066}
9067
c19d1205 9068/* ARM V6 usat (argument parse). */
b99bd4ef
NC		 9069
9070static void
c19d1205 9071do_usat (void)
b99bd4ef 9072{
c19d1205
ZW		 9073 inst.instruction |= inst.operands[0].reg << 12;
9074 inst.instruction |= inst.operands[1].imm << 16;
9075 inst.instruction |= inst.operands[2].reg;
b99bd4ef 9076
c19d1205
ZW		 9077 if (inst.operands[3].present)
9078 encode_arm_shift (3);
b99bd4ef
NC		 9079}
9080
c19d1205 9081/* ARM V6 ssat16 (argument parse). */
09d92015
MM		 9082
9083static void
c19d1205 9084do_ssat16 (void)
09d92015 9085{
c19d1205
ZW		 9086 inst.instruction |= inst.operands[0].reg << 12;
9087 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
9088 inst.instruction |= inst.operands[2].reg;
09d92015
MM		 9089}
9090
c19d1205
ZW		 9091static void
9092do_usat16 (void)
a737bd4d 9093{
c19d1205
ZW		 9094 inst.instruction |= inst.operands[0].reg << 12;
9095 inst.instruction |= inst.operands[1].imm << 16;
9096 inst.instruction |= inst.operands[2].reg;
9097}
a737bd4d 9098
c19d1205
ZW		 9099/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9100 preserving the other bits.
a737bd4d 9101
c19d1205
ZW		 9102 setend <endian_specifier>, where <endian_specifier> is either
9103 BE or LE. */
a737bd4d 9104
c19d1205
ZW		 9105static void
9106do_setend (void)
9107{
12e37cbc
MGD		 9108 if (warn_on_deprecated
9109 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
9110 as_warn (_("setend use is deprecated for ARMv8"));
9111
c19d1205
ZW		 9112 if (inst.operands[0].imm)
9113 inst.instruction |= 0x200;
a737bd4d
NC		 9114}
9115
9116static void
c19d1205 9117do_shift (void)
a737bd4d 9118{
c19d1205
ZW		 9119 unsigned int Rm = (inst.operands[1].present
9120 ? inst.operands[1].reg
9121 : inst.operands[0].reg);
a737bd4d 9122
c19d1205
ZW		 9123 inst.instruction |= inst.operands[0].reg << 12;
9124 inst.instruction |= Rm;
9125 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 9126 {
c19d1205
ZW		 9127 inst.instruction |= inst.operands[2].reg << 8;
9128 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC		 9129 /* PR 12854: Error on extraneous shifts. */
9130 constraint (inst.operands[2].shifted,
9131 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC		 9132 }
9133 else
c19d1205 9134 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC		 9135}
9136
09d92015 9137static void
3eb17e6b 9138do_smc (void)
09d92015 9139{
3eb17e6b 9140 inst.reloc.type = BFD_RELOC_ARM_SMC;
c19d1205 9141 inst.reloc.pc_rel = 0;
09d92015
MM		 9142}
9143
90ec0d68
MGD		 9144static void
9145do_hvc (void)
9146{
9147 inst.reloc.type = BFD_RELOC_ARM_HVC;
9148 inst.reloc.pc_rel = 0;
9149}
9150
09d92015 9151static void
c19d1205 9152do_swi (void)
09d92015 9153{
c19d1205
ZW		 9154 inst.reloc.type = BFD_RELOC_ARM_SWI;
9155 inst.reloc.pc_rel = 0;
09d92015
MM		 9156}
9157
c19d1205
ZW		 9158/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9159 SMLAxy{cond} Rd,Rm,Rs,Rn
9160 SMLAWy{cond} Rd,Rm,Rs,Rn
9161 Error if any register is R15. */
e16bb312 9162
c19d1205
ZW		 9163static void
9164do_smla (void)
e16bb312 9165{
c19d1205
ZW		 9166 inst.instruction |= inst.operands[0].reg << 16;
9167 inst.instruction |= inst.operands[1].reg;
9168 inst.instruction |= inst.operands[2].reg << 8;
9169 inst.instruction |= inst.operands[3].reg << 12;
9170}
a737bd4d 9171
c19d1205
ZW		 9172/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9173 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9174 Error if any register is R15.
9175 Warning if Rdlo == Rdhi. */
a737bd4d 9176
c19d1205
ZW		 9177static void
9178do_smlal (void)
9179{
9180 inst.instruction |= inst.operands[0].reg << 12;
9181 inst.instruction |= inst.operands[1].reg << 16;
9182 inst.instruction |= inst.operands[2].reg;
9183 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 9184
c19d1205
ZW		 9185 if (inst.operands[0].reg == inst.operands[1].reg)
9186 as_tsktsk (_("rdhi and rdlo must be different"));
9187}
a737bd4d 9188
c19d1205
ZW		 9189/* ARM V5E (El Segundo) signed-multiply (argument parse)
9190 SMULxy{cond} Rd,Rm,Rs
9191 Error if any register is R15. */
a737bd4d 9192
c19d1205
ZW		 9193static void
9194do_smul (void)
9195{
9196 inst.instruction |= inst.operands[0].reg << 16;
9197 inst.instruction |= inst.operands[1].reg;
9198 inst.instruction |= inst.operands[2].reg << 8;
9199}
a737bd4d 9200
b6702015
PB		 9201/* ARM V6 srs (argument parse). The variable fields in the encoding are
9202 the same for both ARM and Thumb-2. */
a737bd4d 9203
c19d1205
ZW		 9204static void
9205do_srs (void)
9206{
b6702015
PB		 9207 int reg;
9208
9209 if (inst.operands[0].present)
9210 {
9211 reg = inst.operands[0].reg;
fdfde340 9212 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB		 9213 }
9214 else
fdfde340 9215 reg = REG_SP;
b6702015
PB		 9216
9217 inst.instruction |= reg << 16;
9218 inst.instruction |= inst.operands[1].imm;
9219 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW		 9220 inst.instruction |= WRITE_BACK;
9221}
a737bd4d 9222
c19d1205 9223/* ARM V6 strex (argument parse). */
a737bd4d 9224
c19d1205
ZW		 9225static void
9226do_strex (void)
9227{
9228 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9229 || inst.operands[2].postind || inst.operands[2].writeback
9230 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC		 9231 || inst.operands[2].negative
9232 /* See comment in do_ldrex(). */
9233 || (inst.operands[2].reg == REG_PC),
9234 BAD_ADDR_MODE);
a737bd4d 9235
c19d1205
ZW		 9236 constraint (inst.operands[0].reg == inst.operands[1].reg
9237 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 9238
c19d1205
ZW		 9239 constraint (inst.reloc.exp.X_op != O_constant
9240 || inst.reloc.exp.X_add_number != 0,
9241 _("offset must be zero in ARM encoding"));
a737bd4d 9242
c19d1205
ZW		 9243 inst.instruction |= inst.operands[0].reg << 12;
9244 inst.instruction |= inst.operands[1].reg;
9245 inst.instruction |= inst.operands[2].reg << 16;
9246 inst.reloc.type = BFD_RELOC_UNUSED;
e16bb312
NC		 9247}
9248
877807f8
NC		 9249static void
9250do_t_strexbh (void)
9251{
9252 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9253 || inst.operands[2].postind || inst.operands[2].writeback
9254 || inst.operands[2].immisreg || inst.operands[2].shifted
9255 || inst.operands[2].negative,
9256 BAD_ADDR_MODE);
9257
9258 constraint (inst.operands[0].reg == inst.operands[1].reg
9259 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9260
9261 do_rm_rd_rn ();
9262}
9263
e16bb312 9264static void
c19d1205 9265do_strexd (void)
e16bb312 9266{
c19d1205
ZW		 9267 constraint (inst.operands[1].reg % 2 != 0,
9268 _("even register required"));
9269 constraint (inst.operands[2].present
9270 && inst.operands[2].reg != inst.operands[1].reg + 1,
9271 _("can only store two consecutive registers"));
9272 /* If op 2 were present and equal to PC, this function wouldn't
9273 have been called in the first place. */
9274 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 9275
c19d1205
ZW		 9276 constraint (inst.operands[0].reg == inst.operands[1].reg
9277 || inst.operands[0].reg == inst.operands[1].reg + 1
9278 || inst.operands[0].reg == inst.operands[3].reg,
9279 BAD_OVERLAP);
e16bb312 9280
c19d1205
ZW		 9281 inst.instruction |= inst.operands[0].reg << 12;
9282 inst.instruction |= inst.operands[1].reg;
9283 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC		 9284}
9285
9eb6c0f1
MGD		 9286/* ARM V8 STRL. */
9287static void
4b8c8c02 9288do_stlex (void)
9eb6c0f1
MGD		 9289{
9290 constraint (inst.operands[0].reg == inst.operands[1].reg
9291 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9292
9293 do_rd_rm_rn ();
9294}
9295
9296static void
4b8c8c02 9297do_t_stlex (void)
9eb6c0f1
MGD		 9298{
9299 constraint (inst.operands[0].reg == inst.operands[1].reg
9300 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9301
9302 do_rm_rd_rn ();
9303}
9304
c19d1205
ZW		 9305/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9306 extends it to 32-bits, and adds the result to a value in another
9307 register. You can specify a rotation by 0, 8, 16, or 24 bits
9308 before extracting the 16-bit value.
9309 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9310 Condition defaults to COND_ALWAYS.
9311 Error if any register uses R15. */
9312
e16bb312 9313static void
c19d1205 9314do_sxtah (void)
e16bb312 9315{
c19d1205
ZW		 9316 inst.instruction |= inst.operands[0].reg << 12;
9317 inst.instruction |= inst.operands[1].reg << 16;
9318 inst.instruction |= inst.operands[2].reg;
9319 inst.instruction |= inst.operands[3].imm << 10;
9320}
e16bb312 9321
c19d1205 9322/* ARM V6 SXTH.
e16bb312 9323
c19d1205
ZW		 9324 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9325 Condition defaults to COND_ALWAYS.
9326 Error if any register uses R15. */
e16bb312
NC		 9327
9328static void
c19d1205 9329do_sxth (void)
e16bb312 9330{
c19d1205
ZW		 9331 inst.instruction |= inst.operands[0].reg << 12;
9332 inst.instruction |= inst.operands[1].reg;
9333 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 9334}
c19d1205
ZW		 9335\f
9336/* VFP instructions. In a logical order: SP variant first, monad
9337 before dyad, arithmetic then move then load/store. */
e16bb312
NC		 9338
9339static void
c19d1205 9340do_vfp_sp_monadic (void)
e16bb312 9341{
5287ad62
JB		 9342 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9343 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 9344}
9345
9346static void
c19d1205 9347do_vfp_sp_dyadic (void)
e16bb312 9348{
5287ad62
JB		 9349 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9350 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9351 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 9352}
9353
9354static void
c19d1205 9355do_vfp_sp_compare_z (void)
e16bb312 9356{
5287ad62 9357 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC		 9358}
9359
9360static void
c19d1205 9361do_vfp_dp_sp_cvt (void)
e16bb312 9362{
5287ad62
JB		 9363 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9364 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 9365}
9366
9367static void
c19d1205 9368do_vfp_sp_dp_cvt (void)
e16bb312 9369{
5287ad62
JB		 9370 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9371 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC		 9372}
9373
9374static void
c19d1205 9375do_vfp_reg_from_sp (void)
e16bb312 9376{
c19d1205 9377 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 9378 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC		 9379}
9380
9381static void
c19d1205 9382do_vfp_reg2_from_sp2 (void)
e16bb312 9383{
c19d1205
ZW		 9384 constraint (inst.operands[2].imm != 2,
9385 _("only two consecutive VFP SP registers allowed here"));
9386 inst.instruction |= inst.operands[0].reg << 12;
9387 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 9388 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 9389}
9390
9391static void
c19d1205 9392do_vfp_sp_from_reg (void)
e16bb312 9393{
5287ad62 9394 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 9395 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC		 9396}
9397
9398static void
c19d1205 9399do_vfp_sp2_from_reg2 (void)
e16bb312 9400{
c19d1205
ZW		 9401 constraint (inst.operands[0].imm != 2,
9402 _("only two consecutive VFP SP registers allowed here"));
5287ad62 9403 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW		 9404 inst.instruction |= inst.operands[1].reg << 12;
9405 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC		 9406}
9407
9408static void
c19d1205 9409do_vfp_sp_ldst (void)
e16bb312 9410{
5287ad62 9411 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 9412 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 9413}
9414
9415static void
c19d1205 9416do_vfp_dp_ldst (void)
e16bb312 9417{
5287ad62 9418 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 9419 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 9420}
9421
c19d1205 9422
e16bb312 9423static void
c19d1205 9424vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 9425{
c19d1205
ZW		 9426 if (inst.operands[0].writeback)
9427 inst.instruction |= WRITE_BACK;
9428 else
9429 constraint (ldstm_type != VFP_LDSTMIA,
9430 _("this addressing mode requires base-register writeback"));
9431 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 9432 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 9433 inst.instruction |= inst.operands[1].imm;
e16bb312
NC		 9434}
9435
9436static void
c19d1205 9437vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 9438{
c19d1205 9439 int count;
e16bb312 9440
c19d1205
ZW		 9441 if (inst.operands[0].writeback)
9442 inst.instruction |= WRITE_BACK;
9443 else
9444 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9445 _("this addressing mode requires base-register writeback"));
e16bb312 9446
c19d1205 9447 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 9448 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 9449
c19d1205
ZW		 9450 count = inst.operands[1].imm << 1;
9451 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
9452 count += 1;
e16bb312 9453
c19d1205 9454 inst.instruction |= count;
e16bb312
NC		 9455}
9456
9457static void
c19d1205 9458do_vfp_sp_ldstmia (void)
e16bb312 9459{
c19d1205 9460 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 9461}
9462
9463static void
c19d1205 9464do_vfp_sp_ldstmdb (void)
e16bb312 9465{
c19d1205 9466 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 9467}
9468
9469static void
c19d1205 9470do_vfp_dp_ldstmia (void)
e16bb312 9471{
c19d1205 9472 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 9473}
9474
9475static void
c19d1205 9476do_vfp_dp_ldstmdb (void)
e16bb312 9477{
c19d1205 9478 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 9479}
9480
9481static void
c19d1205 9482do_vfp_xp_ldstmia (void)
e16bb312 9483{
c19d1205
ZW		 9484 vfp_dp_ldstm (VFP_LDSTMIAX);
9485}
e16bb312 9486
c19d1205
ZW		 9487static void
9488do_vfp_xp_ldstmdb (void)
9489{
9490 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 9491}
5287ad62
JB		 9492
9493static void
9494do_vfp_dp_rd_rm (void)
9495{
9496 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9497 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9498}
9499
9500static void
9501do_vfp_dp_rn_rd (void)
9502{
9503 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
9504 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9505}
9506
9507static void
9508do_vfp_dp_rd_rn (void)
9509{
9510 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9511 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9512}
9513
9514static void
9515do_vfp_dp_rd_rn_rm (void)
9516{
9517 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9518 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9519 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
9520}
9521
9522static void
9523do_vfp_dp_rd (void)
9524{
9525 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9526}
9527
9528static void
9529do_vfp_dp_rm_rd_rn (void)
9530{
9531 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
9532 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9533 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9534}
9535
9536/* VFPv3 instructions. */
9537static void
9538do_vfp_sp_const (void)
9539{
9540 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB		 9541 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9542 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 9543}
9544
9545static void
9546do_vfp_dp_const (void)
9547{
9548 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB		 9549 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9550 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 9551}
9552
9553static void
9554vfp_conv (int srcsize)
9555{
5f1af56b
MGD		 9556 int immbits = srcsize - inst.operands[1].imm;
9557
fa94de6b
RM		 9558 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9559 {
5f1af56b 9560 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 9561 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD		 9562 inst.error = _("immediate value out of range, expected range [0, 16]");
9563 return;
9564 }
fa94de6b 9565 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD		 9566 {
9567 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 9568 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD		 9569 inst.error = _("immediate value out of range, expected range [1, 32]");
9570 return;
9571 }
9572
5287ad62
JB		 9573 inst.instruction |= (immbits & 1) << 5;
9574 inst.instruction |= (immbits >> 1);
9575}
9576
9577static void
9578do_vfp_sp_conv_16 (void)
9579{
9580 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9581 vfp_conv (16);
9582}
9583
9584static void
9585do_vfp_dp_conv_16 (void)
9586{
9587 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9588 vfp_conv (16);
9589}
9590
9591static void
9592do_vfp_sp_conv_32 (void)
9593{
9594 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9595 vfp_conv (32);
9596}
9597
9598static void
9599do_vfp_dp_conv_32 (void)
9600{
9601 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9602 vfp_conv (32);
9603}
c19d1205
ZW		 9604\f
9605/* FPA instructions. Also in a logical order. */
e16bb312 9606
c19d1205
ZW		 9607static void
9608do_fpa_cmp (void)
9609{
9610 inst.instruction |= inst.operands[0].reg << 16;
9611 inst.instruction |= inst.operands[1].reg;
9612}
b99bd4ef
NC		 9613
9614static void
c19d1205 9615do_fpa_ldmstm (void)
b99bd4ef 9616{
c19d1205
ZW		 9617 inst.instruction |= inst.operands[0].reg << 12;
9618 switch (inst.operands[1].imm)
9619 {
9620 case 1: inst.instruction |= CP_T_X; break;
9621 case 2: inst.instruction |= CP_T_Y; break;
9622 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9623 case 4: break;
9624 default: abort ();
9625 }
b99bd4ef 9626
c19d1205
ZW		 9627 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9628 {
9629 /* The instruction specified "ea" or "fd", so we can only accept
9630 [Rn]{!}. The instruction does not really support stacking or
9631 unstacking, so we have to emulate these by setting appropriate
9632 bits and offsets. */
9633 constraint (inst.reloc.exp.X_op != O_constant
9634 || inst.reloc.exp.X_add_number != 0,
9635 _("this instruction does not support indexing"));
b99bd4ef 9636
c19d1205
ZW		 9637 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9638 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 9639
c19d1205
ZW		 9640 if (!(inst.instruction & INDEX_UP))
9641 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
b99bd4ef 9642
c19d1205
ZW		 9643 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9644 {
9645 inst.operands[2].preind = 0;
9646 inst.operands[2].postind = 1;
9647 }
9648 }
b99bd4ef 9649
c19d1205 9650 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 9651}
c19d1205
ZW		 9652\f
9653/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 9654
c19d1205
ZW		 9655static void
9656do_iwmmxt_tandorc (void)
9657{
9658 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9659}
b99bd4ef 9660
c19d1205
ZW		 9661static void
9662do_iwmmxt_textrc (void)
9663{
9664 inst.instruction |= inst.operands[0].reg << 12;
9665 inst.instruction |= inst.operands[1].imm;
9666}
b99bd4ef
NC		 9667
9668static void
c19d1205 9669do_iwmmxt_textrm (void)
b99bd4ef 9670{
c19d1205
ZW		 9671 inst.instruction |= inst.operands[0].reg << 12;
9672 inst.instruction |= inst.operands[1].reg << 16;
9673 inst.instruction |= inst.operands[2].imm;
9674}
b99bd4ef 9675
c19d1205
ZW		 9676static void
9677do_iwmmxt_tinsr (void)
9678{
9679 inst.instruction |= inst.operands[0].reg << 16;
9680 inst.instruction |= inst.operands[1].reg << 12;
9681 inst.instruction |= inst.operands[2].imm;
9682}
b99bd4ef 9683
c19d1205
ZW		 9684static void
9685do_iwmmxt_tmia (void)
9686{
9687 inst.instruction |= inst.operands[0].reg << 5;
9688 inst.instruction |= inst.operands[1].reg;
9689 inst.instruction |= inst.operands[2].reg << 12;
9690}
b99bd4ef 9691
c19d1205
ZW		 9692static void
9693do_iwmmxt_waligni (void)
9694{
9695 inst.instruction |= inst.operands[0].reg << 12;
9696 inst.instruction |= inst.operands[1].reg << 16;
9697 inst.instruction |= inst.operands[2].reg;
9698 inst.instruction |= inst.operands[3].imm << 20;
9699}
b99bd4ef 9700
2d447fca
JM		 9701static void
9702do_iwmmxt_wmerge (void)
9703{
9704 inst.instruction |= inst.operands[0].reg << 12;
9705 inst.instruction |= inst.operands[1].reg << 16;
9706 inst.instruction |= inst.operands[2].reg;
9707 inst.instruction |= inst.operands[3].imm << 21;
9708}
9709
c19d1205
ZW		 9710static void
9711do_iwmmxt_wmov (void)
9712{
9713 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9714 inst.instruction |= inst.operands[0].reg << 12;
9715 inst.instruction |= inst.operands[1].reg << 16;
9716 inst.instruction |= inst.operands[1].reg;
9717}
b99bd4ef 9718
c19d1205
ZW		 9719static void
9720do_iwmmxt_wldstbh (void)
9721{
8f06b2d8 9722 int reloc;
c19d1205 9723 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB		 9724 if (thumb_mode)
9725 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9726 else
9727 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9728 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC		 9729}
9730
c19d1205
ZW		 9731static void
9732do_iwmmxt_wldstw (void)
9733{
9734 /* RIWR_RIWC clears .isreg for a control register. */
9735 if (!inst.operands[0].isreg)
9736 {
9737 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9738 inst.instruction |= 0xf0000000;
9739 }
b99bd4ef 9740
c19d1205
ZW		 9741 inst.instruction |= inst.operands[0].reg << 12;
9742 encode_arm_cp_address (1, TRUE, TRUE, 0);
9743}
b99bd4ef
NC		 9744
9745static void
c19d1205 9746do_iwmmxt_wldstd (void)
b99bd4ef 9747{
c19d1205 9748 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM		 9749 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9750 && inst.operands[1].immisreg)
9751 {
9752 inst.instruction &= ~0x1a000ff;
9753 inst.instruction |= (0xf << 28);
9754 if (inst.operands[1].preind)
9755 inst.instruction |= PRE_INDEX;
9756 if (!inst.operands[1].negative)
9757 inst.instruction |= INDEX_UP;
9758 if (inst.operands[1].writeback)
9759 inst.instruction |= WRITE_BACK;
9760 inst.instruction |= inst.operands[1].reg << 16;
9761 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9762 inst.instruction |= inst.operands[1].imm;
9763 }
9764 else
9765 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 9766}
b99bd4ef 9767
c19d1205
ZW		 9768static void
9769do_iwmmxt_wshufh (void)
9770{
9771 inst.instruction |= inst.operands[0].reg << 12;
9772 inst.instruction |= inst.operands[1].reg << 16;
9773 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9774 inst.instruction |= (inst.operands[2].imm & 0x0f);
9775}
b99bd4ef 9776
c19d1205
ZW		 9777static void
9778do_iwmmxt_wzero (void)
9779{
9780 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9781 inst.instruction |= inst.operands[0].reg;
9782 inst.instruction |= inst.operands[0].reg << 12;
9783 inst.instruction |= inst.operands[0].reg << 16;
9784}
2d447fca
JM		 9785
9786static void
9787do_iwmmxt_wrwrwr_or_imm5 (void)
9788{
9789 if (inst.operands[2].isreg)
9790 do_rd_rn_rm ();
9791 else {
9792 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9793 _("immediate operand requires iWMMXt2"));
9794 do_rd_rn ();
9795 if (inst.operands[2].imm == 0)
9796 {
9797 switch ((inst.instruction >> 20) & 0xf)
9798 {
9799 case 4:
9800 case 5:
9801 case 6:
5f4273c7 9802 case 7:
2d447fca
JM		 9803 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9804 inst.operands[2].imm = 16;
9805 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9806 break;
9807 case 8:
9808 case 9:
9809 case 10:
9810 case 11:
9811 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9812 inst.operands[2].imm = 32;
9813 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9814 break;
9815 case 12:
9816 case 13:
9817 case 14:
9818 case 15:
9819 {
9820 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9821 unsigned long wrn;
9822 wrn = (inst.instruction >> 16) & 0xf;
9823 inst.instruction &= 0xff0fff0f;
9824 inst.instruction |= wrn;
9825 /* Bail out here; the instruction is now assembled. */
9826 return;
9827 }
9828 }
9829 }
9830 /* Map 32 -> 0, etc. */
9831 inst.operands[2].imm &= 0x1f;
9832 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9833 }
9834}
c19d1205
ZW		 9835\f
9836/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9837 operations first, then control, shift, and load/store. */
b99bd4ef 9838
c19d1205 9839/* Insns like "foo X,Y,Z". */
b99bd4ef 9840
c19d1205
ZW		 9841static void
9842do_mav_triple (void)
9843{
9844 inst.instruction |= inst.operands[0].reg << 16;
9845 inst.instruction |= inst.operands[1].reg;
9846 inst.instruction |= inst.operands[2].reg << 12;
9847}
b99bd4ef 9848
c19d1205
ZW		 9849/* Insns like "foo W,X,Y,Z".
9850 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 9851
c19d1205
ZW		 9852static void
9853do_mav_quad (void)
9854{
9855 inst.instruction |= inst.operands[0].reg << 5;
9856 inst.instruction |= inst.operands[1].reg << 12;
9857 inst.instruction |= inst.operands[2].reg << 16;
9858 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC		 9859}
9860
c19d1205
ZW		 9861/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9862static void
9863do_mav_dspsc (void)
a737bd4d 9864{
c19d1205
ZW		 9865 inst.instruction |= inst.operands[1].reg << 12;
9866}
a737bd4d 9867
c19d1205
ZW		 9868/* Maverick shift immediate instructions.
9869 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9870 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 9871
c19d1205
ZW		 9872static void
9873do_mav_shift (void)
9874{
9875 int imm = inst.operands[2].imm;
a737bd4d 9876
c19d1205
ZW		 9877 inst.instruction |= inst.operands[0].reg << 12;
9878 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 9879
c19d1205
ZW		 9880 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9881 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9882 Bit 4 should be 0. */
9883 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 9884
c19d1205
ZW		 9885 inst.instruction |= imm;
9886}
9887\f
9888/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 9889
c19d1205
ZW		 9890/* Xscale multiply-accumulate (argument parse)
9891 MIAcc acc0,Rm,Rs
9892 MIAPHcc acc0,Rm,Rs
9893 MIAxycc acc0,Rm,Rs. */
a737bd4d 9894
c19d1205
ZW		 9895static void
9896do_xsc_mia (void)
9897{
9898 inst.instruction |= inst.operands[1].reg;
9899 inst.instruction |= inst.operands[2].reg << 12;
9900}
a737bd4d 9901
c19d1205 9902/* Xscale move-accumulator-register (argument parse)
a737bd4d 9903
c19d1205 9904 MARcc acc0,RdLo,RdHi. */
b99bd4ef 9905
c19d1205
ZW		 9906static void
9907do_xsc_mar (void)
9908{
9909 inst.instruction |= inst.operands[1].reg << 12;
9910 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 9911}
9912
c19d1205 9913/* Xscale move-register-accumulator (argument parse)
b99bd4ef 9914
c19d1205 9915 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC		 9916
9917static void
c19d1205 9918do_xsc_mra (void)
b99bd4ef 9919{
c19d1205
ZW		 9920 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9921 inst.instruction |= inst.operands[0].reg << 12;
9922 inst.instruction |= inst.operands[1].reg << 16;
9923}
9924\f
9925/* Encoding functions relevant only to Thumb. */
b99bd4ef 9926
c19d1205
ZW		 9927/* inst.operands[i] is a shifted-register operand; encode
9928 it into inst.instruction in the format used by Thumb32. */
9929
9930static void
9931encode_thumb32_shifted_operand (int i)
9932{
9933 unsigned int value = inst.reloc.exp.X_add_number;
9934 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 9935
9c3c69f2
PB		 9936 constraint (inst.operands[i].immisreg,
9937 _("shift by register not allowed in thumb mode"));
c19d1205
ZW		 9938 inst.instruction |= inst.operands[i].reg;
9939 if (shift == SHIFT_RRX)
9940 inst.instruction |= SHIFT_ROR << 4;
9941 else
b99bd4ef 9942 {
c19d1205
ZW		 9943 constraint (inst.reloc.exp.X_op != O_constant,
9944 _("expression too complex"));
9945
9946 constraint (value > 32
9947 || (value == 32 && (shift == SHIFT_LSL
9948 || shift == SHIFT_ROR)),
9949 _("shift expression is too large"));
9950
9951 if (value == 0)
9952 shift = SHIFT_LSL;
9953 else if (value == 32)
9954 value = 0;
9955
9956 inst.instruction |= shift << 4;
9957 inst.instruction |= (value & 0x1c) << 10;
9958 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 9959 }
c19d1205 9960}
b99bd4ef 9961
b99bd4ef 9962
c19d1205
ZW		 9963/* inst.operands[i] was set up by parse_address. Encode it into a
9964 Thumb32 format load or store instruction. Reject forms that cannot
9965 be used with such instructions. If is_t is true, reject forms that
9966 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG		 9967 that cannot be used with a D instruction. If it is a store insn,
9968 reject PC in Rn. */
b99bd4ef 9969
c19d1205
ZW		 9970static void
9971encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9972{
5be8be5d 9973 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW		 9974
9975 constraint (!inst.operands[i].isreg,
53365c0d 9976 _("Instruction does not support =N addresses"));
b99bd4ef 9977
c19d1205
ZW		 9978 inst.instruction |= inst.operands[i].reg << 16;
9979 if (inst.operands[i].immisreg)
b99bd4ef 9980 {
5be8be5d 9981 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW		 9982 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9983 constraint (inst.operands[i].negative,
9984 _("Thumb does not support negative register indexing"));
9985 constraint (inst.operands[i].postind,
9986 _("Thumb does not support register post-indexing"));
9987 constraint (inst.operands[i].writeback,
9988 _("Thumb does not support register indexing with writeback"));
9989 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9990 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 9991
f40d1643 9992 inst.instruction |= inst.operands[i].imm;
c19d1205 9993 if (inst.operands[i].shifted)
b99bd4ef 9994 {
c19d1205
ZW		 9995 constraint (inst.reloc.exp.X_op != O_constant,
9996 _("expression too complex"));
9c3c69f2
PB		 9997 constraint (inst.reloc.exp.X_add_number < 0
9998 || inst.reloc.exp.X_add_number > 3,
c19d1205 9999 _("shift out of range"));
9c3c69f2 10000 inst.instruction |= inst.reloc.exp.X_add_number << 4;
c19d1205
ZW		 10001 }
10002 inst.reloc.type = BFD_RELOC_UNUSED;
10003 }
10004 else if (inst.operands[i].preind)
10005 {
5be8be5d 10006 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 10007 constraint (is_t && inst.operands[i].writeback,
c19d1205 10008 _("cannot use writeback with this instruction"));
4755303e
WN		 10009 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10010 BAD_PC_ADDRESSING);
c19d1205
ZW		 10011
10012 if (is_d)
10013 {
10014 inst.instruction |= 0x01000000;
10015 if (inst.operands[i].writeback)
10016 inst.instruction |= 0x00200000;
b99bd4ef 10017 }
c19d1205 10018 else
b99bd4ef 10019 {
c19d1205
ZW		 10020 inst.instruction |= 0x00000c00;
10021 if (inst.operands[i].writeback)
10022 inst.instruction |= 0x00000100;
b99bd4ef 10023 }
c19d1205 10024 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 10025 }
c19d1205 10026 else if (inst.operands[i].postind)
b99bd4ef 10027 {
9c2799c2 10028 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 10029 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10030 constraint (is_t, _("cannot use post-indexing with this instruction"));
10031
10032 if (is_d)
10033 inst.instruction |= 0x00200000;
10034 else
10035 inst.instruction |= 0x00000900;
10036 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10037 }
10038 else /* unindexed - only for coprocessor */
10039 inst.error = _("instruction does not accept unindexed addressing");
10040}
10041
10042/* Table of Thumb instructions which exist in both 16- and 32-bit
10043 encodings (the latter only in post-V6T2 cores). The index is the
10044 value used in the insns table below. When there is more than one
10045 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB		 10046 holds variant (1).
10047 Also contains several pseudo-instructions used during relaxation. */
c19d1205 10048#define T16_32_TAB \
21d799b5
NC		 10049 X(_adc, 4140, eb400000), \
10050 X(_adcs, 4140, eb500000), \
10051 X(_add, 1c00, eb000000), \
10052 X(_adds, 1c00, eb100000), \
10053 X(_addi, 0000, f1000000), \
10054 X(_addis, 0000, f1100000), \
10055 X(_add_pc,000f, f20f0000), \
10056 X(_add_sp,000d, f10d0000), \
10057 X(_adr, 000f, f20f0000), \
10058 X(_and, 4000, ea000000), \
10059 X(_ands, 4000, ea100000), \
10060 X(_asr, 1000, fa40f000), \
10061 X(_asrs, 1000, fa50f000), \
10062 X(_b, e000, f000b000), \
10063 X(_bcond, d000, f0008000), \
10064 X(_bic, 4380, ea200000), \
10065 X(_bics, 4380, ea300000), \
10066 X(_cmn, 42c0, eb100f00), \
10067 X(_cmp, 2800, ebb00f00), \
10068 X(_cpsie, b660, f3af8400), \
10069 X(_cpsid, b670, f3af8600), \
10070 X(_cpy, 4600, ea4f0000), \
10071 X(_dec_sp,80dd, f1ad0d00), \
10072 X(_eor, 4040, ea800000), \
10073 X(_eors, 4040, ea900000), \
10074 X(_inc_sp,00dd, f10d0d00), \
10075 X(_ldmia, c800, e8900000), \
10076 X(_ldr, 6800, f8500000), \
10077 X(_ldrb, 7800, f8100000), \
10078 X(_ldrh, 8800, f8300000), \
10079 X(_ldrsb, 5600, f9100000), \
10080 X(_ldrsh, 5e00, f9300000), \
10081 X(_ldr_pc,4800, f85f0000), \
10082 X(_ldr_pc2,4800, f85f0000), \
10083 X(_ldr_sp,9800, f85d0000), \
10084 X(_lsl, 0000, fa00f000), \
10085 X(_lsls, 0000, fa10f000), \
10086 X(_lsr, 0800, fa20f000), \
10087 X(_lsrs, 0800, fa30f000), \
10088 X(_mov, 2000, ea4f0000), \
10089 X(_movs, 2000, ea5f0000), \
10090 X(_mul, 4340, fb00f000), \
10091 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10092 X(_mvn, 43c0, ea6f0000), \
10093 X(_mvns, 43c0, ea7f0000), \
10094 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10095 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10096 X(_orr, 4300, ea400000), \
10097 X(_orrs, 4300, ea500000), \
10098 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10099 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10100 X(_rev, ba00, fa90f080), \
10101 X(_rev16, ba40, fa90f090), \
10102 X(_revsh, bac0, fa90f0b0), \
10103 X(_ror, 41c0, fa60f000), \
10104 X(_rors, 41c0, fa70f000), \
10105 X(_sbc, 4180, eb600000), \
10106 X(_sbcs, 4180, eb700000), \
10107 X(_stmia, c000, e8800000), \
10108 X(_str, 6000, f8400000), \
10109 X(_strb, 7000, f8000000), \
10110 X(_strh, 8000, f8200000), \
10111 X(_str_sp,9000, f84d0000), \
10112 X(_sub, 1e00, eba00000), \
10113 X(_subs, 1e00, ebb00000), \
10114 X(_subi, 8000, f1a00000), \
10115 X(_subis, 8000, f1b00000), \
10116 X(_sxtb, b240, fa4ff080), \
10117 X(_sxth, b200, fa0ff080), \
10118 X(_tst, 4200, ea100f00), \
10119 X(_uxtb, b2c0, fa5ff080), \
10120 X(_uxth, b280, fa1ff080), \
10121 X(_nop, bf00, f3af8000), \
10122 X(_yield, bf10, f3af8001), \
10123 X(_wfe, bf20, f3af8002), \
10124 X(_wfi, bf30, f3af8003), \
53c4b28b 10125 X(_sev, bf40, f3af8004), \
74db7efb
NC		 10126 X(_sevl, bf50, f3af8005), \
10127 X(_udf, de00, f7f0a000)
c19d1205
ZW		 10128
10129/* To catch errors in encoding functions, the codes are all offset by
10130 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10131 as 16-bit instructions. */
21d799b5 10132#define X(a,b,c) T_MNEM##a
c19d1205
ZW		 10133enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
10134#undef X
10135
10136#define X(a,b,c) 0x##b
10137static const unsigned short thumb_op16[] = { T16_32_TAB };
10138#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10139#undef X
10140
10141#define X(a,b,c) 0x##c
10142static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC		 10143#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10144#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW		 10145#undef X
10146#undef T16_32_TAB
10147
10148/* Thumb instruction encoders, in alphabetical order. */
10149
92e90b6e 10150/* ADDW or SUBW. */
c921be7d 10151
92e90b6e
PB		 10152static void
10153do_t_add_sub_w (void)
10154{
10155 int Rd, Rn;
10156
10157 Rd = inst.operands[0].reg;
10158 Rn = inst.operands[1].reg;
10159
539d4391
NC		 10160 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10161 is the SP-{plus,minus}-immediate form of the instruction. */
10162 if (Rn == REG_SP)
10163 constraint (Rd == REG_PC, BAD_PC);
10164 else
10165 reject_bad_reg (Rd);
fdfde340 10166
92e90b6e
PB		 10167 inst.instruction |= (Rn << 16) | (Rd << 8);
10168 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10169}
10170
c19d1205
ZW		 10171/* Parse an add or subtract instruction. We get here with inst.instruction
10172 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10173
10174static void
10175do_t_add_sub (void)
10176{
10177 int Rd, Rs, Rn;
10178
10179 Rd = inst.operands[0].reg;
10180 Rs = (inst.operands[1].present
10181 ? inst.operands[1].reg /* Rd, Rs, foo */
10182 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10183
e07e6e58
NC		 10184 if (Rd == REG_PC)
10185 set_it_insn_type_last ();
10186
c19d1205
ZW		 10187 if (unified_syntax)
10188 {
0110f2b8
PB		 10189 bfd_boolean flags;
10190 bfd_boolean narrow;
10191 int opcode;
10192
10193 flags = (inst.instruction == T_MNEM_adds
10194 || inst.instruction == T_MNEM_subs);
10195 if (flags)
e07e6e58 10196 narrow = !in_it_block ();
0110f2b8 10197 else
e07e6e58 10198 narrow = in_it_block ();
c19d1205 10199 if (!inst.operands[2].isreg)
b99bd4ef 10200 {
16805f35
PB		 10201 int add;
10202
fdfde340
JM		 10203 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10204
16805f35
PB		 10205 add = (inst.instruction == T_MNEM_add
10206 || inst.instruction == T_MNEM_adds);
0110f2b8
PB		 10207 opcode = 0;
10208 if (inst.size_req != 4)
10209 {
0110f2b8 10210 /* Attempt to use a narrow opcode, with relaxation if
477330fc 10211 appropriate. */
0110f2b8
PB		 10212 if (Rd == REG_SP && Rs == REG_SP && !flags)
10213 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
10214 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
10215 opcode = T_MNEM_add_sp;
10216 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
10217 opcode = T_MNEM_add_pc;
10218 else if (Rd <= 7 && Rs <= 7 && narrow)
10219 {
10220 if (flags)
10221 opcode = add ? T_MNEM_addis : T_MNEM_subis;
10222 else
10223 opcode = add ? T_MNEM_addi : T_MNEM_subi;
10224 }
10225 if (opcode)
10226 {
10227 inst.instruction = THUMB_OP16(opcode);
10228 inst.instruction |= (Rd << 4) | Rs;
10229 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10230 if (inst.size_req != 2)
10231 inst.relax = opcode;
10232 }
10233 else
10234 constraint (inst.size_req == 2, BAD_HIREG);
10235 }
10236 if (inst.size_req == 4
10237 || (inst.size_req != 2 && !opcode))
10238 {
efd81785
PB		 10239 if (Rd == REG_PC)
10240 {
fdfde340 10241 constraint (add, BAD_PC);
efd81785
PB		 10242 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10243 _("only SUBS PC, LR, #const allowed"));
10244 constraint (inst.reloc.exp.X_op != O_constant,
10245 _("expression too complex"));
10246 constraint (inst.reloc.exp.X_add_number < 0
10247 || inst.reloc.exp.X_add_number > 0xff,
10248 _("immediate value out of range"));
10249 inst.instruction = T2_SUBS_PC_LR
10250 | inst.reloc.exp.X_add_number;
10251 inst.reloc.type = BFD_RELOC_UNUSED;
10252 return;
10253 }
10254 else if (Rs == REG_PC)
16805f35
PB		 10255 {
10256 /* Always use addw/subw. */
10257 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
10258 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10259 }
10260 else
10261 {
10262 inst.instruction = THUMB_OP32 (inst.instruction);
10263 inst.instruction = (inst.instruction & 0xe1ffffff)
10264 | 0x10000000;
10265 if (flags)
10266 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10267 else
10268 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
10269 }
dc4503c6
PB		 10270 inst.instruction |= Rd << 8;
10271 inst.instruction |= Rs << 16;
0110f2b8 10272 }
b99bd4ef 10273 }
c19d1205
ZW		 10274 else
10275 {
5f4cb198
NC		 10276 unsigned int value = inst.reloc.exp.X_add_number;
10277 unsigned int shift = inst.operands[2].shift_kind;
10278
c19d1205
ZW		 10279 Rn = inst.operands[2].reg;
10280 /* See if we can do this with a 16-bit instruction. */
10281 if (!inst.operands[2].shifted && inst.size_req != 4)
10282 {
e27ec89e
PB		 10283 if (Rd > 7 || Rs > 7 || Rn > 7)
10284 narrow = FALSE;
10285
10286 if (narrow)
c19d1205 10287 {
e27ec89e
PB		 10288 inst.instruction = ((inst.instruction == T_MNEM_adds
10289 || inst.instruction == T_MNEM_add)
c19d1205
ZW		 10290 ? T_OPCODE_ADD_R3
10291 : T_OPCODE_SUB_R3);
10292 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10293 return;
10294 }
b99bd4ef 10295
7e806470 10296 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 10297 {
7e806470
PB		 10298 /* Thumb-1 cores (except v6-M) require at least one high
10299 register in a narrow non flag setting add. */
10300 if (Rd > 7 || Rn > 7
10301 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
10302 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 10303 {
7e806470
PB		 10304 if (Rd == Rn)
10305 {
10306 Rn = Rs;
10307 Rs = Rd;
10308 }
c19d1205
ZW		 10309 inst.instruction = T_OPCODE_ADD_HI;
10310 inst.instruction |= (Rd & 8) << 4;
10311 inst.instruction |= (Rd & 7);
10312 inst.instruction |= Rn << 3;
10313 return;
10314 }
c19d1205
ZW		 10315 }
10316 }
c921be7d 10317
fdfde340
JM		 10318 constraint (Rd == REG_PC, BAD_PC);
10319 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10320 constraint (Rs == REG_PC, BAD_PC);
10321 reject_bad_reg (Rn);
10322
c19d1205
ZW		 10323 /* If we get here, it can't be done in 16 bits. */
10324 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10325 _("shift must be constant"));
10326 inst.instruction = THUMB_OP32 (inst.instruction);
10327 inst.instruction |= Rd << 8;
10328 inst.instruction |= Rs << 16;
5f4cb198
NC		 10329 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10330 _("shift value over 3 not allowed in thumb mode"));
10331 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10332 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW		 10333 encode_thumb32_shifted_operand (2);
10334 }
10335 }
10336 else
10337 {
10338 constraint (inst.instruction == T_MNEM_adds
10339 || inst.instruction == T_MNEM_subs,
10340 BAD_THUMB32);
b99bd4ef 10341
c19d1205 10342 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 10343 {
c19d1205
ZW		 10344 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10345 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
10346 BAD_HIREG);
10347
10348 inst.instruction = (inst.instruction == T_MNEM_add
10349 ? 0x0000 : 0x8000);
10350 inst.instruction |= (Rd << 4) | Rs;
10351 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC		 10352 return;
10353 }
10354
c19d1205
ZW		 10355 Rn = inst.operands[2].reg;
10356 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 10357
c19d1205
ZW		 10358 /* We now have Rd, Rs, and Rn set to registers. */
10359 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 10360 {
c19d1205
ZW		 10361 /* Can't do this for SUB. */
10362 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10363 inst.instruction = T_OPCODE_ADD_HI;
10364 inst.instruction |= (Rd & 8) << 4;
10365 inst.instruction |= (Rd & 7);
10366 if (Rs == Rd)
10367 inst.instruction |= Rn << 3;
10368 else if (Rn == Rd)
10369 inst.instruction |= Rs << 3;
10370 else
10371 constraint (1, _("dest must overlap one source register"));
10372 }
10373 else
10374 {
10375 inst.instruction = (inst.instruction == T_MNEM_add
10376 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
10377 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 10378 }
b99bd4ef 10379 }
b99bd4ef
NC		 10380}
10381
c19d1205
ZW		 10382static void
10383do_t_adr (void)
10384{
fdfde340
JM		 10385 unsigned Rd;
10386
10387 Rd = inst.operands[0].reg;
10388 reject_bad_reg (Rd);
10389
10390 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB		 10391 {
10392 /* Defer to section relaxation. */
10393 inst.relax = inst.instruction;
10394 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 10395 inst.instruction |= Rd << 4;
0110f2b8
PB		 10396 }
10397 else if (unified_syntax && inst.size_req != 2)
e9f89963 10398 {
0110f2b8 10399 /* Generate a 32-bit opcode. */
e9f89963 10400 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 10401 inst.instruction |= Rd << 8;
e9f89963
PB		 10402 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
10403 inst.reloc.pc_rel = 1;
10404 }
10405 else
10406 {
0110f2b8 10407 /* Generate a 16-bit opcode. */
e9f89963
PB		 10408 inst.instruction = THUMB_OP16 (inst.instruction);
10409 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10410 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
10411 inst.reloc.pc_rel = 1;
b99bd4ef 10412
fdfde340 10413 inst.instruction |= Rd << 4;
e9f89963 10414 }
c19d1205 10415}
b99bd4ef 10416
c19d1205
ZW		 10417/* Arithmetic instructions for which there is just one 16-bit
10418 instruction encoding, and it allows only two low registers.
10419 For maximal compatibility with ARM syntax, we allow three register
10420 operands even when Thumb-32 instructions are not available, as long
10421 as the first two are identical. For instance, both "sbc r0,r1" and
10422 "sbc r0,r0,r1" are allowed. */
b99bd4ef 10423static void
c19d1205 10424do_t_arit3 (void)
b99bd4ef 10425{
c19d1205 10426 int Rd, Rs, Rn;
b99bd4ef 10427
c19d1205
ZW		 10428 Rd = inst.operands[0].reg;
10429 Rs = (inst.operands[1].present
10430 ? inst.operands[1].reg /* Rd, Rs, foo */
10431 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10432 Rn = inst.operands[2].reg;
b99bd4ef 10433
fdfde340
JM		 10434 reject_bad_reg (Rd);
10435 reject_bad_reg (Rs);
10436 if (inst.operands[2].isreg)
10437 reject_bad_reg (Rn);
10438
c19d1205 10439 if (unified_syntax)
b99bd4ef 10440 {
c19d1205
ZW		 10441 if (!inst.operands[2].isreg)
10442 {
10443 /* For an immediate, we always generate a 32-bit opcode;
10444 section relaxation will shrink it later if possible. */
10445 inst.instruction = THUMB_OP32 (inst.instruction);
10446 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10447 inst.instruction |= Rd << 8;
10448 inst.instruction |= Rs << 16;
10449 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10450 }
10451 else
10452 {
e27ec89e
PB		 10453 bfd_boolean narrow;
10454
c19d1205 10455 /* See if we can do this with a 16-bit instruction. */
e27ec89e 10456 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 10457 narrow = !in_it_block ();
e27ec89e 10458 else
e07e6e58 10459 narrow = in_it_block ();
e27ec89e
PB		 10460
10461 if (Rd > 7 || Rn > 7 || Rs > 7)
10462 narrow = FALSE;
10463 if (inst.operands[2].shifted)
10464 narrow = FALSE;
10465 if (inst.size_req == 4)
10466 narrow = FALSE;
10467
10468 if (narrow
c19d1205
ZW		 10469 && Rd == Rs)
10470 {
10471 inst.instruction = THUMB_OP16 (inst.instruction);
10472 inst.instruction |= Rd;
10473 inst.instruction |= Rn << 3;
10474 return;
10475 }
b99bd4ef 10476
c19d1205
ZW		 10477 /* If we get here, it can't be done in 16 bits. */
10478 constraint (inst.operands[2].shifted
10479 && inst.operands[2].immisreg,
10480 _("shift must be constant"));
10481 inst.instruction = THUMB_OP32 (inst.instruction);
10482 inst.instruction |= Rd << 8;
10483 inst.instruction |= Rs << 16;
10484 encode_thumb32_shifted_operand (2);
10485 }
a737bd4d 10486 }
c19d1205 10487 else
b99bd4ef 10488 {
c19d1205
ZW		 10489 /* On its face this is a lie - the instruction does set the
10490 flags. However, the only supported mnemonic in this mode
10491 says it doesn't. */
10492 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 10493
c19d1205
ZW		 10494 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10495 _("unshifted register required"));
10496 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10497 constraint (Rd != Rs,
10498 _("dest and source1 must be the same register"));
a737bd4d 10499
c19d1205
ZW		 10500 inst.instruction = THUMB_OP16 (inst.instruction);
10501 inst.instruction |= Rd;
10502 inst.instruction |= Rn << 3;
b99bd4ef 10503 }
a737bd4d 10504}
b99bd4ef 10505
c19d1205
ZW		 10506/* Similarly, but for instructions where the arithmetic operation is
10507 commutative, so we can allow either of them to be different from
10508 the destination operand in a 16-bit instruction. For instance, all
10509 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10510 accepted. */
10511static void
10512do_t_arit3c (void)
a737bd4d 10513{
c19d1205 10514 int Rd, Rs, Rn;
b99bd4ef 10515
c19d1205
ZW		 10516 Rd = inst.operands[0].reg;
10517 Rs = (inst.operands[1].present
10518 ? inst.operands[1].reg /* Rd, Rs, foo */
10519 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10520 Rn = inst.operands[2].reg;
c921be7d 10521
fdfde340
JM		 10522 reject_bad_reg (Rd);
10523 reject_bad_reg (Rs);
10524 if (inst.operands[2].isreg)
10525 reject_bad_reg (Rn);
a737bd4d 10526
c19d1205 10527 if (unified_syntax)
a737bd4d 10528 {
c19d1205 10529 if (!inst.operands[2].isreg)
b99bd4ef 10530 {
c19d1205
ZW		 10531 /* For an immediate, we always generate a 32-bit opcode;
10532 section relaxation will shrink it later if possible. */
10533 inst.instruction = THUMB_OP32 (inst.instruction);
10534 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10535 inst.instruction |= Rd << 8;
10536 inst.instruction |= Rs << 16;
10537 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 10538 }
c19d1205 10539 else
a737bd4d 10540 {
e27ec89e
PB		 10541 bfd_boolean narrow;
10542
c19d1205 10543 /* See if we can do this with a 16-bit instruction. */
e27ec89e 10544 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 10545 narrow = !in_it_block ();
e27ec89e 10546 else
e07e6e58 10547 narrow = in_it_block ();
e27ec89e
PB		 10548
10549 if (Rd > 7 || Rn > 7 || Rs > 7)
10550 narrow = FALSE;
10551 if (inst.operands[2].shifted)
10552 narrow = FALSE;
10553 if (inst.size_req == 4)
10554 narrow = FALSE;
10555
10556 if (narrow)
a737bd4d 10557 {
c19d1205 10558 if (Rd == Rs)
a737bd4d 10559 {
c19d1205
ZW		 10560 inst.instruction = THUMB_OP16 (inst.instruction);
10561 inst.instruction |= Rd;
10562 inst.instruction |= Rn << 3;
10563 return;
a737bd4d 10564 }
c19d1205 10565 if (Rd == Rn)
a737bd4d 10566 {
c19d1205
ZW		 10567 inst.instruction = THUMB_OP16 (inst.instruction);
10568 inst.instruction |= Rd;
10569 inst.instruction |= Rs << 3;
10570 return;
a737bd4d
NC		 10571 }
10572 }
c19d1205
ZW		 10573
10574 /* If we get here, it can't be done in 16 bits. */
10575 constraint (inst.operands[2].shifted
10576 && inst.operands[2].immisreg,
10577 _("shift must be constant"));
10578 inst.instruction = THUMB_OP32 (inst.instruction);
10579 inst.instruction |= Rd << 8;
10580 inst.instruction |= Rs << 16;
10581 encode_thumb32_shifted_operand (2);
a737bd4d 10582 }
b99bd4ef 10583 }
c19d1205
ZW		 10584 else
10585 {
10586 /* On its face this is a lie - the instruction does set the
10587 flags. However, the only supported mnemonic in this mode
10588 says it doesn't. */
10589 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 10590
c19d1205
ZW		 10591 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10592 _("unshifted register required"));
10593 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10594
10595 inst.instruction = THUMB_OP16 (inst.instruction);
10596 inst.instruction |= Rd;
10597
10598 if (Rd == Rs)
10599 inst.instruction |= Rn << 3;
10600 else if (Rd == Rn)
10601 inst.instruction |= Rs << 3;
10602 else
10603 constraint (1, _("dest must overlap one source register"));
10604 }
a737bd4d
NC		 10605}
10606
c19d1205
ZW		 10607static void
10608do_t_bfc (void)
a737bd4d 10609{
fdfde340 10610 unsigned Rd;
c19d1205
ZW		 10611 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10612 constraint (msb > 32, _("bit-field extends past end of register"));
10613 /* The instruction encoding stores the LSB and MSB,
10614 not the LSB and width. */
fdfde340
JM		 10615 Rd = inst.operands[0].reg;
10616 reject_bad_reg (Rd);
10617 inst.instruction |= Rd << 8;
c19d1205
ZW		 10618 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10619 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10620 inst.instruction |= msb - 1;
b99bd4ef
NC		 10621}
10622
c19d1205
ZW		 10623static void
10624do_t_bfi (void)
b99bd4ef 10625{
fdfde340 10626 int Rd, Rn;
c19d1205 10627 unsigned int msb;
b99bd4ef 10628
fdfde340
JM		 10629 Rd = inst.operands[0].reg;
10630 reject_bad_reg (Rd);
10631
c19d1205
ZW		 10632 /* #0 in second position is alternative syntax for bfc, which is
10633 the same instruction but with REG_PC in the Rm field. */
10634 if (!inst.operands[1].isreg)
fdfde340
JM		 10635 Rn = REG_PC;
10636 else
10637 {
10638 Rn = inst.operands[1].reg;
10639 reject_bad_reg (Rn);
10640 }
b99bd4ef 10641
c19d1205
ZW		 10642 msb = inst.operands[2].imm + inst.operands[3].imm;
10643 constraint (msb > 32, _("bit-field extends past end of register"));
10644 /* The instruction encoding stores the LSB and MSB,
10645 not the LSB and width. */
fdfde340
JM		 10646 inst.instruction |= Rd << 8;
10647 inst.instruction |= Rn << 16;
c19d1205
ZW		 10648 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10649 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10650 inst.instruction |= msb - 1;
b99bd4ef
NC		 10651}
10652
c19d1205
ZW		 10653static void
10654do_t_bfx (void)
b99bd4ef 10655{
fdfde340
JM		 10656 unsigned Rd, Rn;
10657
10658 Rd = inst.operands[0].reg;
10659 Rn = inst.operands[1].reg;
10660
10661 reject_bad_reg (Rd);
10662 reject_bad_reg (Rn);
10663
c19d1205
ZW		 10664 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10665 _("bit-field extends past end of register"));
fdfde340
JM		 10666 inst.instruction |= Rd << 8;
10667 inst.instruction |= Rn << 16;
c19d1205
ZW		 10668 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10669 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10670 inst.instruction |= inst.operands[3].imm - 1;
10671}
b99bd4ef 10672
c19d1205
ZW		 10673/* ARM V5 Thumb BLX (argument parse)
10674 BLX <target_addr> which is BLX(1)
10675 BLX <Rm> which is BLX(2)
10676 Unfortunately, there are two different opcodes for this mnemonic.
10677 So, the insns[].value is not used, and the code here zaps values
10678 into inst.instruction.
b99bd4ef 10679
c19d1205
ZW		 10680 ??? How to take advantage of the additional two bits of displacement
10681 available in Thumb32 mode? Need new relocation? */
b99bd4ef 10682
c19d1205
ZW		 10683static void
10684do_t_blx (void)
10685{
e07e6e58
NC		 10686 set_it_insn_type_last ();
10687
c19d1205 10688 if (inst.operands[0].isreg)
fdfde340
JM		 10689 {
10690 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10691 /* We have a register, so this is BLX(2). */
10692 inst.instruction |= inst.operands[0].reg << 3;
10693 }
b99bd4ef
NC		 10694 else
10695 {
c19d1205 10696 /* No register. This must be BLX(1). */
2fc8bdac 10697 inst.instruction = 0xf000e800;
0855e32b 10698 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC		 10699 }
10700}
10701
c19d1205
ZW		 10702static void
10703do_t_branch (void)
b99bd4ef 10704{
0110f2b8 10705 int opcode;
dfa9f0d5 10706 int cond;
9ae92b05 10707 int reloc;
dfa9f0d5 10708
e07e6e58
NC		 10709 cond = inst.cond;
10710 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10711
10712 if (in_it_block ())
dfa9f0d5
PB		 10713 {
10714 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 10715 branches. */
dfa9f0d5 10716 cond = COND_ALWAYS;
dfa9f0d5
PB		 10717 }
10718 else
10719 cond = inst.cond;
10720
10721 if (cond != COND_ALWAYS)
0110f2b8
PB		 10722 opcode = T_MNEM_bcond;
10723 else
10724 opcode = inst.instruction;
10725
12d6b0b7
RS		 10726 if (unified_syntax
10727 && (inst.size_req == 4
10960bfb
PB		 10728 || (inst.size_req != 2
10729 && (inst.operands[0].hasreloc
10730 || inst.reloc.exp.X_op == O_constant))))
c19d1205 10731 {
0110f2b8 10732 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 10733 if (cond == COND_ALWAYS)
9ae92b05 10734 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW		 10735 else
10736 {
9c2799c2 10737 gas_assert (cond != 0xF);
dfa9f0d5 10738 inst.instruction |= cond << 22;
9ae92b05 10739 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW		 10740 }
10741 }
b99bd4ef
NC		 10742 else
10743 {
0110f2b8 10744 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 10745 if (cond == COND_ALWAYS)
9ae92b05 10746 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 10747 else
b99bd4ef 10748 {
dfa9f0d5 10749 inst.instruction |= cond << 8;
9ae92b05 10750 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 10751 }
0110f2b8
PB		 10752 /* Allow section relaxation. */
10753 if (unified_syntax && inst.size_req != 2)
10754 inst.relax = opcode;
b99bd4ef 10755 }
9ae92b05 10756 inst.reloc.type = reloc;
c19d1205 10757 inst.reloc.pc_rel = 1;
b99bd4ef
NC		 10758}
10759
8884b720 10760/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 10761 between the two is the maximum immediate allowed - which is passed in
8884b720 10762 RANGE. */
b99bd4ef 10763static void
8884b720 10764do_t_bkpt_hlt1 (int range)
b99bd4ef 10765{
dfa9f0d5
PB		 10766 constraint (inst.cond != COND_ALWAYS,
10767 _("instruction is always unconditional"));
c19d1205 10768 if (inst.operands[0].present)
b99bd4ef 10769 {
8884b720 10770 constraint (inst.operands[0].imm > range,
c19d1205
ZW		 10771 _("immediate value out of range"));
10772 inst.instruction |= inst.operands[0].imm;
b99bd4ef 10773 }
8884b720
MGD		 10774
10775 set_it_insn_type (NEUTRAL_IT_INSN);
10776}
10777
10778static void
10779do_t_hlt (void)
10780{
10781 do_t_bkpt_hlt1 (63);
10782}
10783
10784static void
10785do_t_bkpt (void)
10786{
10787 do_t_bkpt_hlt1 (255);
b99bd4ef
NC		 10788}
10789
10790static void
c19d1205 10791do_t_branch23 (void)
b99bd4ef 10792{
e07e6e58 10793 set_it_insn_type_last ();
0855e32b 10794 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 10795
0855e32b
NS		 10796 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10797 this file. We used to simply ignore the PLT reloc type here --
10798 the branch encoding is now needed to deal with TLSCALL relocs.
10799 So if we see a PLT reloc now, put it back to how it used to be to
10800 keep the preexisting behaviour. */
10801 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10802 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 10803
4343666d 10804#if defined(OBJ_COFF)
c19d1205
ZW		 10805 /* If the destination of the branch is a defined symbol which does not have
10806 the THUMB_FUNC attribute, then we must be calling a function which has
10807 the (interfacearm) attribute. We look for the Thumb entry point to that
10808 function and change the branch to refer to that function instead. */
10809 if ( inst.reloc.exp.X_op == O_symbol
10810 && inst.reloc.exp.X_add_symbol != NULL
10811 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10812 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10813 inst.reloc.exp.X_add_symbol =
10814 find_real_start (inst.reloc.exp.X_add_symbol);
4343666d 10815#endif
90e4755a
RE		 10816}
10817
10818static void
c19d1205 10819do_t_bx (void)
90e4755a 10820{
e07e6e58 10821 set_it_insn_type_last ();
c19d1205
ZW		 10822 inst.instruction |= inst.operands[0].reg << 3;
10823 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10824 should cause the alignment to be checked once it is known. This is
10825 because BX PC only works if the instruction is word aligned. */
10826}
90e4755a 10827
c19d1205
ZW		 10828static void
10829do_t_bxj (void)
10830{
fdfde340 10831 int Rm;
90e4755a 10832
e07e6e58 10833 set_it_insn_type_last ();
fdfde340
JM		 10834 Rm = inst.operands[0].reg;
10835 reject_bad_reg (Rm);
10836 inst.instruction |= Rm << 16;
90e4755a
RE		 10837}
10838
10839static void
c19d1205 10840do_t_clz (void)
90e4755a 10841{
fdfde340
JM		 10842 unsigned Rd;
10843 unsigned Rm;
10844
10845 Rd = inst.operands[0].reg;
10846 Rm = inst.operands[1].reg;
10847
10848 reject_bad_reg (Rd);
10849 reject_bad_reg (Rm);
10850
10851 inst.instruction |= Rd << 8;
10852 inst.instruction |= Rm << 16;
10853 inst.instruction |= Rm;
c19d1205 10854}
90e4755a 10855
dfa9f0d5
PB		 10856static void
10857do_t_cps (void)
10858{
e07e6e58 10859 set_it_insn_type (OUTSIDE_IT_INSN);
dfa9f0d5
PB		 10860 inst.instruction |= inst.operands[0].imm;
10861}
10862
c19d1205
ZW		 10863static void
10864do_t_cpsi (void)
10865{
e07e6e58 10866 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205 10867 if (unified_syntax
62b3e311
PB		 10868 && (inst.operands[1].present || inst.size_req == 4)
10869 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 10870 {
c19d1205
ZW		 10871 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10872 inst.instruction = 0xf3af8000;
10873 inst.instruction |= imod << 9;
10874 inst.instruction |= inst.operands[0].imm << 5;
10875 if (inst.operands[1].present)
10876 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 10877 }
c19d1205 10878 else
90e4755a 10879 {
62b3e311
PB		 10880 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10881 && (inst.operands[0].imm & 4),
10882 _("selected processor does not support 'A' form "
10883 "of this instruction"));
10884 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW		 10885 _("Thumb does not support the 2-argument "
10886 "form of this instruction"));
10887 inst.instruction |= inst.operands[0].imm;
90e4755a 10888 }
90e4755a
RE		 10889}
10890
c19d1205
ZW		 10891/* THUMB CPY instruction (argument parse). */
10892
90e4755a 10893static void
c19d1205 10894do_t_cpy (void)
90e4755a 10895{
c19d1205 10896 if (inst.size_req == 4)
90e4755a 10897 {
c19d1205
ZW		 10898 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10899 inst.instruction |= inst.operands[0].reg << 8;
10900 inst.instruction |= inst.operands[1].reg;
90e4755a 10901 }
c19d1205 10902 else
90e4755a 10903 {
c19d1205
ZW		 10904 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10905 inst.instruction |= (inst.operands[0].reg & 0x7);
10906 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 10907 }
90e4755a
RE		 10908}
10909
90e4755a 10910static void
25fe350b 10911do_t_cbz (void)
90e4755a 10912{
e07e6e58 10913 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW		 10914 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10915 inst.instruction |= inst.operands[0].reg;
10916 inst.reloc.pc_rel = 1;
10917 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10918}
90e4755a 10919
62b3e311
PB		 10920static void
10921do_t_dbg (void)
10922{
10923 inst.instruction |= inst.operands[0].imm;
10924}
10925
10926static void
10927do_t_div (void)
10928{
fdfde340
JM		 10929 unsigned Rd, Rn, Rm;
10930
10931 Rd = inst.operands[0].reg;
10932 Rn = (inst.operands[1].present
10933 ? inst.operands[1].reg : Rd);
10934 Rm = inst.operands[2].reg;
10935
10936 reject_bad_reg (Rd);
10937 reject_bad_reg (Rn);
10938 reject_bad_reg (Rm);
10939
10940 inst.instruction |= Rd << 8;
10941 inst.instruction |= Rn << 16;
10942 inst.instruction |= Rm;
62b3e311
PB		 10943}
10944
c19d1205
ZW		 10945static void
10946do_t_hint (void)
10947{
10948 if (unified_syntax && inst.size_req == 4)
10949 inst.instruction = THUMB_OP32 (inst.instruction);
10950 else
10951 inst.instruction = THUMB_OP16 (inst.instruction);
10952}
90e4755a 10953
c19d1205
ZW		 10954static void
10955do_t_it (void)
10956{
10957 unsigned int cond = inst.operands[0].imm;
e27ec89e 10958
e07e6e58
NC		 10959 set_it_insn_type (IT_INSN);
10960 now_it.mask = (inst.instruction & 0xf) | 0x10;
10961 now_it.cc = cond;
5a01bb1d 10962 now_it.warn_deprecated = FALSE;
e27ec89e
PB		 10963
10964 /* If the condition is a negative condition, invert the mask. */
c19d1205 10965 if ((cond & 0x1) == 0x0)
90e4755a 10966 {
c19d1205 10967 unsigned int mask = inst.instruction & 0x000f;
90e4755a 10968
c19d1205 10969 if ((mask & 0x7) == 0)
5a01bb1d
MGD		 10970 {
10971 /* No conversion needed. */
10972 now_it.block_length = 1;
10973 }
c19d1205 10974 else if ((mask & 0x3) == 0)
5a01bb1d
MGD		 10975 {
10976 mask ^= 0x8;
10977 now_it.block_length = 2;
10978 }
e27ec89e 10979 else if ((mask & 0x1) == 0)
5a01bb1d
MGD		 10980 {
10981 mask ^= 0xC;
10982 now_it.block_length = 3;
10983 }
c19d1205 10984 else
5a01bb1d
MGD		 10985 {
10986 mask ^= 0xE;
10987 now_it.block_length = 4;
10988 }
90e4755a 10989
e27ec89e
PB		 10990 inst.instruction &= 0xfff0;
10991 inst.instruction |= mask;
c19d1205 10992 }
90e4755a 10993
c19d1205
ZW		 10994 inst.instruction |= cond << 4;
10995}
90e4755a 10996
3c707909
PB		 10997/* Helper function used for both push/pop and ldm/stm. */
10998static void
10999encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
11000{
11001 bfd_boolean load;
11002
11003 load = (inst.instruction & (1 << 20)) != 0;
11004
11005 if (mask & (1 << 13))
11006 inst.error = _("SP not allowed in register list");
1e5b0379
NC		 11007
11008 if ((mask & (1 << base)) != 0
11009 && writeback)
11010 inst.error = _("having the base register in the register list when "
11011 "using write back is UNPREDICTABLE");
11012
3c707909
PB		 11013 if (load)
11014 {
e07e6e58 11015 if (mask & (1 << 15))
477330fc
RM		 11016 {
11017 if (mask & (1 << 14))
11018 inst.error = _("LR and PC should not both be in register list");
11019 else
11020 set_it_insn_type_last ();
11021 }
3c707909
PB		 11022 }
11023 else
11024 {
11025 if (mask & (1 << 15))
11026 inst.error = _("PC not allowed in register list");
3c707909
PB		 11027 }
11028
11029 if ((mask & (mask - 1)) == 0)
11030 {
11031 /* Single register transfers implemented as str/ldr. */
11032 if (writeback)
11033 {
11034 if (inst.instruction & (1 << 23))
11035 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
11036 else
11037 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
11038 }
11039 else
11040 {
11041 if (inst.instruction & (1 << 23))
11042 inst.instruction = 0x00800000; /* ia -> [base] */
11043 else
11044 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
11045 }
11046
11047 inst.instruction |= 0xf8400000;
11048 if (load)
11049 inst.instruction |= 0x00100000;
11050
5f4273c7 11051 mask = ffs (mask) - 1;
3c707909
PB		 11052 mask <<= 12;
11053 }
11054 else if (writeback)
11055 inst.instruction |= WRITE_BACK;
11056
11057 inst.instruction |= mask;
11058 inst.instruction |= base << 16;
11059}
11060
c19d1205
ZW		 11061static void
11062do_t_ldmstm (void)
11063{
11064 /* This really doesn't seem worth it. */
11065 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11066 _("expression too complex"));
11067 constraint (inst.operands[1].writeback,
11068 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 11069
c19d1205
ZW		 11070 if (unified_syntax)
11071 {
3c707909
PB		 11072 bfd_boolean narrow;
11073 unsigned mask;
11074
11075 narrow = FALSE;
c19d1205
ZW		 11076 /* See if we can use a 16-bit instruction. */
11077 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
11078 && inst.size_req != 4
3c707909 11079 && !(inst.operands[1].imm & ~0xff))
90e4755a 11080 {
3c707909 11081 mask = 1 << inst.operands[0].reg;
90e4755a 11082
eab4f823 11083 if (inst.operands[0].reg <= 7)
90e4755a 11084 {
3c707909 11085 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD		 11086 ? inst.operands[0].writeback
11087 : (inst.operands[0].writeback
11088 == !(inst.operands[1].imm & mask)))
477330fc 11089 {
eab4f823
MGD		 11090 if (inst.instruction == T_MNEM_stmia
11091 && (inst.operands[1].imm & mask)
11092 && (inst.operands[1].imm & (mask - 1)))
11093 as_warn (_("value stored for r%d is UNKNOWN"),
11094 inst.operands[0].reg);
3c707909 11095
eab4f823
MGD		 11096 inst.instruction = THUMB_OP16 (inst.instruction);
11097 inst.instruction |= inst.operands[0].reg << 8;
11098 inst.instruction |= inst.operands[1].imm;
11099 narrow = TRUE;
11100 }
11101 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11102 {
11103 /* This means 1 register in reg list one of 3 situations:
11104 1. Instruction is stmia, but without writeback.
11105 2. lmdia without writeback, but with Rn not in
477330fc 11106 reglist.
eab4f823
MGD		 11107 3. ldmia with writeback, but with Rn in reglist.
11108 Case 3 is UNPREDICTABLE behaviour, so we handle
11109 case 1 and 2 which can be converted into a 16-bit
11110 str or ldr. The SP cases are handled below. */
11111 unsigned long opcode;
11112 /* First, record an error for Case 3. */
11113 if (inst.operands[1].imm & mask
11114 && inst.operands[0].writeback)
fa94de6b 11115 inst.error =
eab4f823
MGD		 11116 _("having the base register in the register list when "
11117 "using write back is UNPREDICTABLE");
fa94de6b
RM		 11118
11119 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD		 11120 : T_MNEM_ldr);
11121 inst.instruction = THUMB_OP16 (opcode);
11122 inst.instruction |= inst.operands[0].reg << 3;
11123 inst.instruction |= (ffs (inst.operands[1].imm)-1);
11124 narrow = TRUE;
11125 }
90e4755a 11126 }
eab4f823 11127 else if (inst.operands[0] .reg == REG_SP)
90e4755a 11128 {
eab4f823
MGD		 11129 if (inst.operands[0].writeback)
11130 {
fa94de6b 11131 inst.instruction =
eab4f823 11132 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 11133 ? T_MNEM_push : T_MNEM_pop);
eab4f823 11134 inst.instruction |= inst.operands[1].imm;
477330fc 11135 narrow = TRUE;
eab4f823
MGD		 11136 }
11137 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11138 {
fa94de6b 11139 inst.instruction =
eab4f823 11140 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 11141 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 11142 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 11143 narrow = TRUE;
eab4f823 11144 }
90e4755a 11145 }
3c707909
PB		 11146 }
11147
11148 if (!narrow)
11149 {
c19d1205
ZW		 11150 if (inst.instruction < 0xffff)
11151 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 11152
5f4273c7
NC		 11153 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
11154 inst.operands[0].writeback);
90e4755a
RE		 11155 }
11156 }
c19d1205 11157 else
90e4755a 11158 {
c19d1205
ZW		 11159 constraint (inst.operands[0].reg > 7
11160 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB		 11161 constraint (inst.instruction != T_MNEM_ldmia
11162 && inst.instruction != T_MNEM_stmia,
11163 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 11164 if (inst.instruction == T_MNEM_stmia)
f03698e6 11165 {
c19d1205
ZW		 11166 if (!inst.operands[0].writeback)
11167 as_warn (_("this instruction will write back the base register"));
11168 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
11169 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 11170 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 11171 inst.operands[0].reg);
f03698e6 11172 }
c19d1205 11173 else
90e4755a 11174 {
c19d1205
ZW		 11175 if (!inst.operands[0].writeback
11176 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
11177 as_warn (_("this instruction will write back the base register"));
11178 else if (inst.operands[0].writeback
11179 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
11180 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE		 11181 }
11182
c19d1205
ZW		 11183 inst.instruction = THUMB_OP16 (inst.instruction);
11184 inst.instruction |= inst.operands[0].reg << 8;
11185 inst.instruction |= inst.operands[1].imm;
11186 }
11187}
e28cd48c 11188
c19d1205
ZW		 11189static void
11190do_t_ldrex (void)
11191{
11192 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11193 || inst.operands[1].postind || inst.operands[1].writeback
11194 || inst.operands[1].immisreg || inst.operands[1].shifted
11195 || inst.operands[1].negative,
01cfc07f 11196 BAD_ADDR_MODE);
e28cd48c 11197
5be8be5d
DG		 11198 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11199
c19d1205
ZW		 11200 inst.instruction |= inst.operands[0].reg << 12;
11201 inst.instruction |= inst.operands[1].reg << 16;
11202 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11203}
e28cd48c 11204
c19d1205
ZW		 11205static void
11206do_t_ldrexd (void)
11207{
11208 if (!inst.operands[1].present)
1cac9012 11209 {
c19d1205
ZW		 11210 constraint (inst.operands[0].reg == REG_LR,
11211 _("r14 not allowed as first register "
11212 "when second register is omitted"));
11213 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 11214 }
c19d1205
ZW		 11215 constraint (inst.operands[0].reg == inst.operands[1].reg,
11216 BAD_OVERLAP);
b99bd4ef 11217
c19d1205
ZW		 11218 inst.instruction |= inst.operands[0].reg << 12;
11219 inst.instruction |= inst.operands[1].reg << 8;
11220 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 11221}
11222
11223static void
c19d1205 11224do_t_ldst (void)
b99bd4ef 11225{
0110f2b8
PB		 11226 unsigned long opcode;
11227 int Rn;
11228
e07e6e58
NC		 11229 if (inst.operands[0].isreg
11230 && !inst.operands[0].preind
11231 && inst.operands[0].reg == REG_PC)
11232 set_it_insn_type_last ();
11233
0110f2b8 11234 opcode = inst.instruction;
c19d1205 11235 if (unified_syntax)
b99bd4ef 11236 {
53365c0d
PB		 11237 if (!inst.operands[1].isreg)
11238 {
11239 if (opcode <= 0xffff)
11240 inst.instruction = THUMB_OP32 (opcode);
8335d6aa 11241 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
53365c0d
PB		 11242 return;
11243 }
0110f2b8
PB		 11244 if (inst.operands[1].isreg
11245 && !inst.operands[1].writeback
c19d1205
ZW		 11246 && !inst.operands[1].shifted && !inst.operands[1].postind
11247 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB		 11248 && opcode <= 0xffff
11249 && inst.size_req != 4)
c19d1205 11250 {
0110f2b8
PB		 11251 /* Insn may have a 16-bit form. */
11252 Rn = inst.operands[1].reg;
11253 if (inst.operands[1].immisreg)
11254 {
11255 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 11256 /* [Rn, Rik] */
0110f2b8
PB		 11257 if (Rn <= 7 && inst.operands[1].imm <= 7)
11258 goto op16;
5be8be5d
DG		 11259 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
11260 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB		 11261 }
11262 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
11263 && opcode != T_MNEM_ldrsb)
11264 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
11265 || (Rn == REG_SP && opcode == T_MNEM_str))
11266 {
11267 /* [Rn, #const] */
11268 if (Rn > 7)
11269 {
11270 if (Rn == REG_PC)
11271 {
11272 if (inst.reloc.pc_rel)
11273 opcode = T_MNEM_ldr_pc2;
11274 else
11275 opcode = T_MNEM_ldr_pc;
11276 }
11277 else
11278 {
11279 if (opcode == T_MNEM_ldr)
11280 opcode = T_MNEM_ldr_sp;
11281 else
11282 opcode = T_MNEM_str_sp;
11283 }
11284 inst.instruction = inst.operands[0].reg << 8;
11285 }
11286 else
11287 {
11288 inst.instruction = inst.operands[0].reg;
11289 inst.instruction |= inst.operands[1].reg << 3;
11290 }
11291 inst.instruction |= THUMB_OP16 (opcode);
11292 if (inst.size_req == 2)
11293 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11294 else
11295 inst.relax = opcode;
11296 return;
11297 }
c19d1205 11298 }
0110f2b8 11299 /* Definitely a 32-bit variant. */
5be8be5d 11300
8d67f500
NC		 11301 /* Warning for Erratum 752419. */
11302 if (opcode == T_MNEM_ldr
11303 && inst.operands[0].reg == REG_SP
11304 && inst.operands[1].writeback == 1
11305 && !inst.operands[1].immisreg)
11306 {
11307 if (no_cpu_selected ()
11308 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM		 11309 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
11310 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC		 11311 as_warn (_("This instruction may be unpredictable "
11312 "if executed on M-profile cores "
11313 "with interrupts enabled."));
11314 }
11315
5be8be5d 11316 /* Do some validations regarding addressing modes. */
1be5fd2e 11317 if (inst.operands[1].immisreg)
5be8be5d
DG		 11318 reject_bad_reg (inst.operands[1].imm);
11319
1be5fd2e
NC		 11320 constraint (inst.operands[1].writeback == 1
11321 && inst.operands[0].reg == inst.operands[1].reg,
11322 BAD_OVERLAP);
11323
0110f2b8 11324 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW		 11325 inst.instruction |= inst.operands[0].reg << 12;
11326 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 11327 check_ldr_r15_aligned ();
b99bd4ef
NC		 11328 return;
11329 }
11330
c19d1205
ZW		 11331 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11332
11333 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 11334 {
c19d1205
ZW		 11335 /* Only [Rn,Rm] is acceptable. */
11336 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11337 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11338 || inst.operands[1].postind || inst.operands[1].shifted
11339 || inst.operands[1].negative,
11340 _("Thumb does not support this addressing mode"));
11341 inst.instruction = THUMB_OP16 (inst.instruction);
11342 goto op16;
b99bd4ef 11343 }
5f4273c7 11344
c19d1205
ZW		 11345 inst.instruction = THUMB_OP16 (inst.instruction);
11346 if (!inst.operands[1].isreg)
8335d6aa 11347 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
c19d1205 11348 return;
b99bd4ef 11349
c19d1205
ZW		 11350 constraint (!inst.operands[1].preind
11351 || inst.operands[1].shifted
11352 || inst.operands[1].writeback,
11353 _("Thumb does not support this addressing mode"));
11354 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 11355 {
c19d1205
ZW		 11356 constraint (inst.instruction & 0x0600,
11357 _("byte or halfword not valid for base register"));
11358 constraint (inst.operands[1].reg == REG_PC
11359 && !(inst.instruction & THUMB_LOAD_BIT),
11360 _("r15 based store not allowed"));
11361 constraint (inst.operands[1].immisreg,
11362 _("invalid base register for register offset"));
b99bd4ef 11363
c19d1205
ZW		 11364 if (inst.operands[1].reg == REG_PC)
11365 inst.instruction = T_OPCODE_LDR_PC;
11366 else if (inst.instruction & THUMB_LOAD_BIT)
11367 inst.instruction = T_OPCODE_LDR_SP;
11368 else
11369 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 11370
c19d1205
ZW		 11371 inst.instruction |= inst.operands[0].reg << 8;
11372 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11373 return;
11374 }
90e4755a 11375
c19d1205
ZW		 11376 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11377 if (!inst.operands[1].immisreg)
11378 {
11379 /* Immediate offset. */
11380 inst.instruction |= inst.operands[0].reg;
11381 inst.instruction |= inst.operands[1].reg << 3;
11382 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11383 return;
11384 }
90e4755a 11385
c19d1205
ZW		 11386 /* Register offset. */
11387 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11388 constraint (inst.operands[1].negative,
11389 _("Thumb does not support this addressing mode"));
90e4755a 11390
c19d1205
ZW		 11391 op16:
11392 switch (inst.instruction)
11393 {
11394 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
11395 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
11396 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
11397 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
11398 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
11399 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
11400 case 0x5600 /* ldrsb */:
11401 case 0x5e00 /* ldrsh */: break;
11402 default: abort ();
11403 }
90e4755a 11404
c19d1205
ZW		 11405 inst.instruction |= inst.operands[0].reg;
11406 inst.instruction |= inst.operands[1].reg << 3;
11407 inst.instruction |= inst.operands[1].imm << 6;
11408}
90e4755a 11409
c19d1205
ZW		 11410static void
11411do_t_ldstd (void)
11412{
11413 if (!inst.operands[1].present)
b99bd4ef 11414 {
c19d1205
ZW		 11415 inst.operands[1].reg = inst.operands[0].reg + 1;
11416 constraint (inst.operands[0].reg == REG_LR,
11417 _("r14 not allowed here"));
bd340a04 11418 constraint (inst.operands[0].reg == REG_R12,
477330fc 11419 _("r12 not allowed here"));
b99bd4ef 11420 }
bd340a04
MGD		 11421
11422 if (inst.operands[2].writeback
11423 && (inst.operands[0].reg == inst.operands[2].reg
11424 || inst.operands[1].reg == inst.operands[2].reg))
11425 as_warn (_("base register written back, and overlaps "
477330fc 11426 "one of transfer registers"));
bd340a04 11427
c19d1205
ZW		 11428 inst.instruction |= inst.operands[0].reg << 12;
11429 inst.instruction |= inst.operands[1].reg << 8;
11430 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC		 11431}
11432
c19d1205
ZW		 11433static void
11434do_t_ldstt (void)
11435{
11436 inst.instruction |= inst.operands[0].reg << 12;
11437 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
11438}
a737bd4d 11439
b99bd4ef 11440static void
c19d1205 11441do_t_mla (void)
b99bd4ef 11442{
fdfde340 11443 unsigned Rd, Rn, Rm, Ra;
c921be7d 11444
fdfde340
JM		 11445 Rd = inst.operands[0].reg;
11446 Rn = inst.operands[1].reg;
11447 Rm = inst.operands[2].reg;
11448 Ra = inst.operands[3].reg;
11449
11450 reject_bad_reg (Rd);
11451 reject_bad_reg (Rn);
11452 reject_bad_reg (Rm);
11453 reject_bad_reg (Ra);
11454
11455 inst.instruction |= Rd << 8;
11456 inst.instruction |= Rn << 16;
11457 inst.instruction |= Rm;
11458 inst.instruction |= Ra << 12;
c19d1205 11459}
b99bd4ef 11460
c19d1205
ZW		 11461static void
11462do_t_mlal (void)
11463{
fdfde340
JM		 11464 unsigned RdLo, RdHi, Rn, Rm;
11465
11466 RdLo = inst.operands[0].reg;
11467 RdHi = inst.operands[1].reg;
11468 Rn = inst.operands[2].reg;
11469 Rm = inst.operands[3].reg;
11470
11471 reject_bad_reg (RdLo);
11472 reject_bad_reg (RdHi);
11473 reject_bad_reg (Rn);
11474 reject_bad_reg (Rm);
11475
11476 inst.instruction |= RdLo << 12;
11477 inst.instruction |= RdHi << 8;
11478 inst.instruction |= Rn << 16;
11479 inst.instruction |= Rm;
c19d1205 11480}
b99bd4ef 11481
c19d1205
ZW		 11482static void
11483do_t_mov_cmp (void)
11484{
fdfde340
JM		 11485 unsigned Rn, Rm;
11486
11487 Rn = inst.operands[0].reg;
11488 Rm = inst.operands[1].reg;
11489
e07e6e58
NC		 11490 if (Rn == REG_PC)
11491 set_it_insn_type_last ();
11492
c19d1205 11493 if (unified_syntax)
b99bd4ef 11494 {
c19d1205
ZW		 11495 int r0off = (inst.instruction == T_MNEM_mov
11496 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 11497 unsigned long opcode;
3d388997
PB		 11498 bfd_boolean narrow;
11499 bfd_boolean low_regs;
11500
fdfde340 11501 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 11502 opcode = inst.instruction;
e07e6e58 11503 if (in_it_block ())
0110f2b8 11504 narrow = opcode != T_MNEM_movs;
3d388997 11505 else
0110f2b8 11506 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB		 11507 if (inst.size_req == 4
11508 || inst.operands[1].shifted)
11509 narrow = FALSE;
11510
efd81785
PB		 11511 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11512 if (opcode == T_MNEM_movs && inst.operands[1].isreg
11513 && !inst.operands[1].shifted
fdfde340
JM		 11514 && Rn == REG_PC
11515 && Rm == REG_LR)
efd81785
PB		 11516 {
11517 inst.instruction = T2_SUBS_PC_LR;
11518 return;
11519 }
11520
fdfde340
JM		 11521 if (opcode == T_MNEM_cmp)
11522 {
11523 constraint (Rn == REG_PC, BAD_PC);
94206790
MM		 11524 if (narrow)
11525 {
11526 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11527 but valid. */
11528 warn_deprecated_sp (Rm);
11529 /* R15 was documented as a valid choice for Rm in ARMv6,
11530 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11531 tools reject R15, so we do too. */
11532 constraint (Rm == REG_PC, BAD_PC);
11533 }
11534 else
11535 reject_bad_reg (Rm);
fdfde340
JM		 11536 }
11537 else if (opcode == T_MNEM_mov
11538 || opcode == T_MNEM_movs)
11539 {
11540 if (inst.operands[1].isreg)
11541 {
11542 if (opcode == T_MNEM_movs)
11543 {
11544 reject_bad_reg (Rn);
11545 reject_bad_reg (Rm);
11546 }
76fa04a4
MGD		 11547 else if (narrow)
11548 {
11549 /* This is mov.n. */
11550 if ((Rn == REG_SP || Rn == REG_PC)
11551 && (Rm == REG_SP || Rm == REG_PC))
11552 {
11553 as_warn (_("Use of r%u as a source register is "
11554 "deprecated when r%u is the destination "
11555 "register."), Rm, Rn);
11556 }
11557 }
11558 else
11559 {
11560 /* This is mov.w. */
11561 constraint (Rn == REG_PC, BAD_PC);
11562 constraint (Rm == REG_PC, BAD_PC);
11563 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11564 }
fdfde340
JM		 11565 }
11566 else
11567 reject_bad_reg (Rn);
11568 }
11569
c19d1205
ZW		 11570 if (!inst.operands[1].isreg)
11571 {
0110f2b8 11572 /* Immediate operand. */
e07e6e58 11573 if (!in_it_block () && opcode == T_MNEM_mov)
0110f2b8
PB		 11574 narrow = 0;
11575 if (low_regs && narrow)
11576 {
11577 inst.instruction = THUMB_OP16 (opcode);
fdfde340 11578 inst.instruction |= Rn << 8;
0110f2b8
PB		 11579 if (inst.size_req == 2)
11580 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11581 else
11582 inst.relax = opcode;
11583 }
11584 else
11585 {
11586 inst.instruction = THUMB_OP32 (inst.instruction);
11587 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 11588 inst.instruction |= Rn << r0off;
0110f2b8
PB		 11589 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11590 }
c19d1205 11591 }
728ca7c9
PB		 11592 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11593 && (inst.instruction == T_MNEM_mov
11594 || inst.instruction == T_MNEM_movs))
11595 {
11596 /* Register shifts are encoded as separate shift instructions. */
11597 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11598
e07e6e58 11599 if (in_it_block ())
728ca7c9
PB		 11600 narrow = !flags;
11601 else
11602 narrow = flags;
11603
11604 if (inst.size_req == 4)
11605 narrow = FALSE;
11606
11607 if (!low_regs || inst.operands[1].imm > 7)
11608 narrow = FALSE;
11609
fdfde340 11610 if (Rn != Rm)
728ca7c9
PB		 11611 narrow = FALSE;
11612
11613 switch (inst.operands[1].shift_kind)
11614 {
11615 case SHIFT_LSL:
11616 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11617 break;
11618 case SHIFT_ASR:
11619 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11620 break;
11621 case SHIFT_LSR:
11622 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11623 break;
11624 case SHIFT_ROR:
11625 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11626 break;
11627 default:
5f4273c7 11628 abort ();
728ca7c9
PB		 11629 }
11630
11631 inst.instruction = opcode;
11632 if (narrow)
11633 {
fdfde340 11634 inst.instruction |= Rn;
728ca7c9
PB		 11635 inst.instruction |= inst.operands[1].imm << 3;
11636 }
11637 else
11638 {
11639 if (flags)
11640 inst.instruction |= CONDS_BIT;
11641
fdfde340
JM		 11642 inst.instruction |= Rn << 8;
11643 inst.instruction |= Rm << 16;
728ca7c9
PB		 11644 inst.instruction |= inst.operands[1].imm;
11645 }
11646 }
3d388997 11647 else if (!narrow)
c19d1205 11648 {
728ca7c9
PB		 11649 /* Some mov with immediate shift have narrow variants.
11650 Register shifts are handled above. */
11651 if (low_regs && inst.operands[1].shifted
11652 && (inst.instruction == T_MNEM_mov
11653 || inst.instruction == T_MNEM_movs))
11654 {
e07e6e58 11655 if (in_it_block ())
728ca7c9
PB		 11656 narrow = (inst.instruction == T_MNEM_mov);
11657 else
11658 narrow = (inst.instruction == T_MNEM_movs);
11659 }
11660
11661 if (narrow)
11662 {
11663 switch (inst.operands[1].shift_kind)
11664 {
11665 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11666 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11667 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11668 default: narrow = FALSE; break;
11669 }
11670 }
11671
11672 if (narrow)
11673 {
fdfde340
JM		 11674 inst.instruction |= Rn;
11675 inst.instruction |= Rm << 3;
728ca7c9
PB		 11676 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11677 }
11678 else
11679 {
11680 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11681 inst.instruction |= Rn << r0off;
728ca7c9
PB		 11682 encode_thumb32_shifted_operand (1);
11683 }
c19d1205
ZW		 11684 }
11685 else
11686 switch (inst.instruction)
11687 {
11688 case T_MNEM_mov:
837b3435 11689 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD		 11690 results. Don't allow this. */
11691 if (low_regs)
11692 {
11693 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11694 "MOV Rd, Rs with two low registers is not "
11695 "permitted on this architecture");
fa94de6b 11696 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD		 11697 arm_ext_v6);
11698 }
11699
c19d1205 11700 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM		 11701 inst.instruction |= (Rn & 0x8) << 4;
11702 inst.instruction |= (Rn & 0x7);
11703 inst.instruction |= Rm << 3;
c19d1205 11704 break;
b99bd4ef 11705
c19d1205
ZW		 11706 case T_MNEM_movs:
11707 /* We know we have low registers at this point.
941a8a52
MGD		 11708 Generate LSLS Rd, Rs, #0. */
11709 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM		 11710 inst.instruction |= Rn;
11711 inst.instruction |= Rm << 3;
c19d1205
ZW		 11712 break;
11713
11714 case T_MNEM_cmp:
3d388997 11715 if (low_regs)
c19d1205
ZW		 11716 {
11717 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM		 11718 inst.instruction |= Rn;
11719 inst.instruction |= Rm << 3;
c19d1205
ZW		 11720 }
11721 else
11722 {
11723 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM		 11724 inst.instruction |= (Rn & 0x8) << 4;
11725 inst.instruction |= (Rn & 0x7);
11726 inst.instruction |= Rm << 3;
c19d1205
ZW		 11727 }
11728 break;
11729 }
b99bd4ef
NC		 11730 return;
11731 }
11732
c19d1205 11733 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC		 11734
11735 /* PR 10443: Do not silently ignore shifted operands. */
11736 constraint (inst.operands[1].shifted,
11737 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11738
c19d1205 11739 if (inst.operands[1].isreg)
b99bd4ef 11740 {
fdfde340 11741 if (Rn < 8 && Rm < 8)
b99bd4ef 11742 {
c19d1205
ZW		 11743 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11744 since a MOV instruction produces unpredictable results. */
11745 if (inst.instruction == T_OPCODE_MOV_I8)
11746 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 11747 else
c19d1205 11748 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 11749
fdfde340
JM		 11750 inst.instruction |= Rn;
11751 inst.instruction |= Rm << 3;
b99bd4ef
NC		 11752 }
11753 else
11754 {
c19d1205
ZW		 11755 if (inst.instruction == T_OPCODE_MOV_I8)
11756 inst.instruction = T_OPCODE_MOV_HR;
11757 else
11758 inst.instruction = T_OPCODE_CMP_HR;
11759 do_t_cpy ();
b99bd4ef
NC		 11760 }
11761 }
c19d1205 11762 else
b99bd4ef 11763 {
fdfde340 11764 constraint (Rn > 7,
c19d1205 11765 _("only lo regs allowed with immediate"));
fdfde340 11766 inst.instruction |= Rn << 8;
c19d1205
ZW		 11767 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11768 }
11769}
b99bd4ef 11770
c19d1205
ZW		 11771static void
11772do_t_mov16 (void)
11773{
fdfde340 11774 unsigned Rd;
b6895b4f
PB		 11775 bfd_vma imm;
11776 bfd_boolean top;
11777
11778 top = (inst.instruction & 0x00800000) != 0;
11779 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11780 {
11781 constraint (top, _(":lower16: not allowed this instruction"));
11782 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11783 }
11784 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11785 {
11786 constraint (!top, _(":upper16: not allowed this instruction"));
11787 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11788 }
11789
fdfde340
JM		 11790 Rd = inst.operands[0].reg;
11791 reject_bad_reg (Rd);
11792
11793 inst.instruction |= Rd << 8;
b6895b4f
PB		 11794 if (inst.reloc.type == BFD_RELOC_UNUSED)
11795 {
11796 imm = inst.reloc.exp.X_add_number;
11797 inst.instruction |= (imm & 0xf000) << 4;
11798 inst.instruction |= (imm & 0x0800) << 15;
11799 inst.instruction |= (imm & 0x0700) << 4;
11800 inst.instruction |= (imm & 0x00ff);
11801 }
c19d1205 11802}
b99bd4ef 11803
c19d1205
ZW		 11804static void
11805do_t_mvn_tst (void)
11806{
fdfde340 11807 unsigned Rn, Rm;
c921be7d 11808
fdfde340
JM		 11809 Rn = inst.operands[0].reg;
11810 Rm = inst.operands[1].reg;
11811
11812 if (inst.instruction == T_MNEM_cmp
11813 || inst.instruction == T_MNEM_cmn)
11814 constraint (Rn == REG_PC, BAD_PC);
11815 else
11816 reject_bad_reg (Rn);
11817 reject_bad_reg (Rm);
11818
c19d1205
ZW		 11819 if (unified_syntax)
11820 {
11821 int r0off = (inst.instruction == T_MNEM_mvn
11822 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB		 11823 bfd_boolean narrow;
11824
11825 if (inst.size_req == 4
11826 || inst.instruction > 0xffff
11827 || inst.operands[1].shifted
fdfde340 11828 || Rn > 7 || Rm > 7)
3d388997 11829 narrow = FALSE;
fe8b4cc3
KT		 11830 else if (inst.instruction == T_MNEM_cmn
11831 || inst.instruction == T_MNEM_tst)
3d388997
PB		 11832 narrow = TRUE;
11833 else if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 11834 narrow = !in_it_block ();
3d388997 11835 else
e07e6e58 11836 narrow = in_it_block ();
3d388997 11837
c19d1205 11838 if (!inst.operands[1].isreg)
b99bd4ef 11839 {
c19d1205
ZW		 11840 /* For an immediate, we always generate a 32-bit opcode;
11841 section relaxation will shrink it later if possible. */
11842 if (inst.instruction < 0xffff)
11843 inst.instruction = THUMB_OP32 (inst.instruction);
11844 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 11845 inst.instruction |= Rn << r0off;
c19d1205 11846 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11847 }
c19d1205 11848 else
b99bd4ef 11849 {
c19d1205 11850 /* See if we can do this with a 16-bit instruction. */
3d388997 11851 if (narrow)
b99bd4ef 11852 {
c19d1205 11853 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11854 inst.instruction |= Rn;
11855 inst.instruction |= Rm << 3;
b99bd4ef 11856 }
c19d1205 11857 else
b99bd4ef 11858 {
c19d1205
ZW		 11859 constraint (inst.operands[1].shifted
11860 && inst.operands[1].immisreg,
11861 _("shift must be constant"));
11862 if (inst.instruction < 0xffff)
11863 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11864 inst.instruction |= Rn << r0off;
c19d1205 11865 encode_thumb32_shifted_operand (1);
b99bd4ef 11866 }
b99bd4ef
NC		 11867 }
11868 }
11869 else
11870 {
c19d1205
ZW		 11871 constraint (inst.instruction > 0xffff
11872 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11873 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11874 _("unshifted register required"));
fdfde340 11875 constraint (Rn > 7 || Rm > 7,
c19d1205 11876 BAD_HIREG);
b99bd4ef 11877
c19d1205 11878 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11879 inst.instruction |= Rn;
11880 inst.instruction |= Rm << 3;
b99bd4ef 11881 }
b99bd4ef
NC		 11882}
11883
b05fe5cf 11884static void
c19d1205 11885do_t_mrs (void)
b05fe5cf 11886{
fdfde340 11887 unsigned Rd;
037e8744
JB		 11888
11889 if (do_vfp_nsyn_mrs () == SUCCESS)
11890 return;
11891
90ec0d68
MGD		 11892 Rd = inst.operands[0].reg;
11893 reject_bad_reg (Rd);
11894 inst.instruction |= Rd << 8;
11895
11896 if (inst.operands[1].isreg)
62b3e311 11897 {
90ec0d68
MGD		 11898 unsigned br = inst.operands[1].reg;
11899 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11900 as_bad (_("bad register for mrs"));
11901
11902 inst.instruction |= br & (0xf << 16);
11903 inst.instruction |= (br & 0x300) >> 4;
11904 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB		 11905 }
11906 else
11907 {
90ec0d68 11908 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 11909
d2cd1205 11910 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC		 11911 {
11912 /* PR gas/12698: The constraint is only applied for m_profile.
11913 If the user has specified -march=all, we want to ignore it as
11914 we are building for any CPU type, including non-m variants. */
11915 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11916 constraint ((flags != 0) && m_profile, _("selected processor does "
11917 "not support requested special purpose register"));
11918 }
90ec0d68 11919 else
d2cd1205
JB		 11920 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11921 devices). */
11922 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11923 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 11924
90ec0d68
MGD		 11925 inst.instruction |= (flags & SPSR_BIT) >> 2;
11926 inst.instruction |= inst.operands[1].imm & 0xff;
11927 inst.instruction |= 0xf0000;
11928 }
c19d1205 11929}
b05fe5cf 11930
c19d1205
ZW		 11931static void
11932do_t_msr (void)
11933{
62b3e311 11934 int flags;
fdfde340 11935 unsigned Rn;
62b3e311 11936
037e8744
JB		 11937 if (do_vfp_nsyn_msr () == SUCCESS)
11938 return;
11939
c19d1205
ZW		 11940 constraint (!inst.operands[1].isreg,
11941 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD		 11942
11943 if (inst.operands[0].isreg)
11944 flags = (int)(inst.operands[0].reg);
11945 else
11946 flags = inst.operands[0].imm;
11947
d2cd1205 11948 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 11949 {
d2cd1205
JB		 11950 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11951
1a43faaf 11952 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM		 11953 If the user has specified -march=all, we want to ignore it as
11954 we are building for any CPU type, including non-m variants. */
1a43faaf
NC		 11955 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11956 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM		 11957 && (bits & ~(PSR_s | PSR_f)) != 0)
11958 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11959 && bits != PSR_f)) && m_profile,
11960 _("selected processor does not support requested special "
11961 "purpose register"));
62b3e311
PB		 11962 }
11963 else
d2cd1205
JB		 11964 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11965 "requested special purpose register"));
c921be7d 11966
fdfde340
JM		 11967 Rn = inst.operands[1].reg;
11968 reject_bad_reg (Rn);
11969
62b3e311 11970 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD		 11971 inst.instruction |= (flags & 0xf0000) >> 8;
11972 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 11973 inst.instruction |= (flags & 0xff);
fdfde340 11974 inst.instruction |= Rn << 16;
c19d1205 11975}
b05fe5cf 11976
c19d1205
ZW		 11977static void
11978do_t_mul (void)
11979{
17828f45 11980 bfd_boolean narrow;
fdfde340 11981 unsigned Rd, Rn, Rm;
17828f45 11982
c19d1205
ZW		 11983 if (!inst.operands[2].present)
11984 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 11985
fdfde340
JM		 11986 Rd = inst.operands[0].reg;
11987 Rn = inst.operands[1].reg;
11988 Rm = inst.operands[2].reg;
11989
17828f45 11990 if (unified_syntax)
b05fe5cf 11991 {
17828f45 11992 if (inst.size_req == 4
fdfde340
JM		 11993 || (Rd != Rn
11994 && Rd != Rm)
11995 || Rn > 7
11996 || Rm > 7)
17828f45
JM		 11997 narrow = FALSE;
11998 else if (inst.instruction == T_MNEM_muls)
e07e6e58 11999 narrow = !in_it_block ();
17828f45 12000 else
e07e6e58 12001 narrow = in_it_block ();
b05fe5cf 12002 }
c19d1205 12003 else
b05fe5cf 12004 {
17828f45 12005 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 12006 constraint (Rn > 7 || Rm > 7,
c19d1205 12007 BAD_HIREG);
17828f45
JM		 12008 narrow = TRUE;
12009 }
b05fe5cf 12010
17828f45
JM		 12011 if (narrow)
12012 {
12013 /* 16-bit MULS/Conditional MUL. */
c19d1205 12014 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 12015 inst.instruction |= Rd;
b05fe5cf 12016
fdfde340
JM		 12017 if (Rd == Rn)
12018 inst.instruction |= Rm << 3;
12019 else if (Rd == Rm)
12020 inst.instruction |= Rn << 3;
c19d1205
ZW		 12021 else
12022 constraint (1, _("dest must overlap one source register"));
12023 }
17828f45
JM		 12024 else
12025 {
e07e6e58
NC		 12026 constraint (inst.instruction != T_MNEM_mul,
12027 _("Thumb-2 MUL must not set flags"));
17828f45
JM		 12028 /* 32-bit MUL. */
12029 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12030 inst.instruction |= Rd << 8;
12031 inst.instruction |= Rn << 16;
12032 inst.instruction |= Rm << 0;
12033
12034 reject_bad_reg (Rd);
12035 reject_bad_reg (Rn);
12036 reject_bad_reg (Rm);
17828f45 12037 }
c19d1205 12038}
b05fe5cf 12039
c19d1205
ZW		 12040static void
12041do_t_mull (void)
12042{
fdfde340 12043 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 12044
fdfde340
JM		 12045 RdLo = inst.operands[0].reg;
12046 RdHi = inst.operands[1].reg;
12047 Rn = inst.operands[2].reg;
12048 Rm = inst.operands[3].reg;
12049
12050 reject_bad_reg (RdLo);
12051 reject_bad_reg (RdHi);
12052 reject_bad_reg (Rn);
12053 reject_bad_reg (Rm);
12054
12055 inst.instruction |= RdLo << 12;
12056 inst.instruction |= RdHi << 8;
12057 inst.instruction |= Rn << 16;
12058 inst.instruction |= Rm;
12059
12060 if (RdLo == RdHi)
c19d1205
ZW		 12061 as_tsktsk (_("rdhi and rdlo must be different"));
12062}
b05fe5cf 12063
c19d1205
ZW		 12064static void
12065do_t_nop (void)
12066{
e07e6e58
NC		 12067 set_it_insn_type (NEUTRAL_IT_INSN);
12068
c19d1205
ZW		 12069 if (unified_syntax)
12070 {
12071 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 12072 {
c19d1205
ZW		 12073 inst.instruction = THUMB_OP32 (inst.instruction);
12074 inst.instruction |= inst.operands[0].imm;
12075 }
12076 else
12077 {
bc2d1808
NC		 12078 /* PR9722: Check for Thumb2 availability before
12079 generating a thumb2 nop instruction. */
afa62d5e 12080 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC		 12081 {
12082 inst.instruction = THUMB_OP16 (inst.instruction);
12083 inst.instruction |= inst.operands[0].imm << 4;
12084 }
12085 else
12086 inst.instruction = 0x46c0;
c19d1205
ZW		 12087 }
12088 }
12089 else
12090 {
12091 constraint (inst.operands[0].present,
12092 _("Thumb does not support NOP with hints"));
12093 inst.instruction = 0x46c0;
12094 }
12095}
b05fe5cf 12096
c19d1205
ZW		 12097static void
12098do_t_neg (void)
12099{
12100 if (unified_syntax)
12101 {
3d388997
PB		 12102 bfd_boolean narrow;
12103
12104 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 12105 narrow = !in_it_block ();
3d388997 12106 else
e07e6e58 12107 narrow = in_it_block ();
3d388997
PB		 12108 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12109 narrow = FALSE;
12110 if (inst.size_req == 4)
12111 narrow = FALSE;
12112
12113 if (!narrow)
c19d1205
ZW		 12114 {
12115 inst.instruction = THUMB_OP32 (inst.instruction);
12116 inst.instruction |= inst.operands[0].reg << 8;
12117 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW		 12118 }
12119 else
12120 {
c19d1205
ZW		 12121 inst.instruction = THUMB_OP16 (inst.instruction);
12122 inst.instruction |= inst.operands[0].reg;
12123 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW		 12124 }
12125 }
12126 else
12127 {
c19d1205
ZW		 12128 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12129 BAD_HIREG);
12130 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12131
12132 inst.instruction = THUMB_OP16 (inst.instruction);
12133 inst.instruction |= inst.operands[0].reg;
12134 inst.instruction |= inst.operands[1].reg << 3;
12135 }
12136}
12137
1c444d06
JM		 12138static void
12139do_t_orn (void)
12140{
12141 unsigned Rd, Rn;
12142
12143 Rd = inst.operands[0].reg;
12144 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
12145
fdfde340
JM		 12146 reject_bad_reg (Rd);
12147 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12148 reject_bad_reg (Rn);
12149
1c444d06
JM		 12150 inst.instruction |= Rd << 8;
12151 inst.instruction |= Rn << 16;
12152
12153 if (!inst.operands[2].isreg)
12154 {
12155 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12156 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12157 }
12158 else
12159 {
12160 unsigned Rm;
12161
12162 Rm = inst.operands[2].reg;
fdfde340 12163 reject_bad_reg (Rm);
1c444d06
JM		 12164
12165 constraint (inst.operands[2].shifted
12166 && inst.operands[2].immisreg,
12167 _("shift must be constant"));
12168 encode_thumb32_shifted_operand (2);
12169 }
12170}
12171
c19d1205
ZW		 12172static void
12173do_t_pkhbt (void)
12174{
fdfde340
JM		 12175 unsigned Rd, Rn, Rm;
12176
12177 Rd = inst.operands[0].reg;
12178 Rn = inst.operands[1].reg;
12179 Rm = inst.operands[2].reg;
12180
12181 reject_bad_reg (Rd);
12182 reject_bad_reg (Rn);
12183 reject_bad_reg (Rm);
12184
12185 inst.instruction |= Rd << 8;
12186 inst.instruction |= Rn << 16;
12187 inst.instruction |= Rm;
c19d1205
ZW		 12188 if (inst.operands[3].present)
12189 {
12190 unsigned int val = inst.reloc.exp.X_add_number;
12191 constraint (inst.reloc.exp.X_op != O_constant,
12192 _("expression too complex"));
12193 inst.instruction |= (val & 0x1c) << 10;
12194 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 12195 }
c19d1205 12196}
b05fe5cf 12197
c19d1205
ZW		 12198static void
12199do_t_pkhtb (void)
12200{
12201 if (!inst.operands[3].present)
1ef52f49
NC		 12202 {
12203 unsigned Rtmp;
12204
12205 inst.instruction &= ~0x00000020;
12206
12207 /* PR 10168. Swap the Rm and Rn registers. */
12208 Rtmp = inst.operands[1].reg;
12209 inst.operands[1].reg = inst.operands[2].reg;
12210 inst.operands[2].reg = Rtmp;
12211 }
c19d1205 12212 do_t_pkhbt ();
b05fe5cf
ZW		 12213}
12214
c19d1205
ZW		 12215static void
12216do_t_pld (void)
12217{
fdfde340
JM		 12218 if (inst.operands[0].immisreg)
12219 reject_bad_reg (inst.operands[0].imm);
12220
c19d1205
ZW		 12221 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
12222}
b05fe5cf 12223
c19d1205
ZW		 12224static void
12225do_t_push_pop (void)
b99bd4ef 12226{
e9f89963 12227 unsigned mask;
5f4273c7 12228
c19d1205
ZW		 12229 constraint (inst.operands[0].writeback,
12230 _("push/pop do not support {reglist}^"));
12231 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12232 _("expression too complex"));
b99bd4ef 12233
e9f89963 12234 mask = inst.operands[0].imm;
d3bfe16e 12235 if (inst.size_req != 4 && (mask & ~0xff) == 0)
3c707909 12236 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
d3bfe16e
JB		 12237 else if (inst.size_req != 4
12238 && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push
12239 ? REG_LR : REG_PC)))
b99bd4ef 12240 {
c19d1205
ZW		 12241 inst.instruction = THUMB_OP16 (inst.instruction);
12242 inst.instruction |= THUMB_PP_PC_LR;
3c707909 12243 inst.instruction |= mask & 0xff;
c19d1205
ZW		 12244 }
12245 else if (unified_syntax)
12246 {
3c707909 12247 inst.instruction = THUMB_OP32 (inst.instruction);
5f4273c7 12248 encode_thumb2_ldmstm (13, mask, TRUE);
c19d1205
ZW		 12249 }
12250 else
12251 {
12252 inst.error = _("invalid register list to push/pop instruction");
12253 return;
12254 }
c19d1205 12255}
b99bd4ef 12256
c19d1205
ZW		 12257static void
12258do_t_rbit (void)
12259{
fdfde340
JM		 12260 unsigned Rd, Rm;
12261
12262 Rd = inst.operands[0].reg;
12263 Rm = inst.operands[1].reg;
12264
12265 reject_bad_reg (Rd);
12266 reject_bad_reg (Rm);
12267
12268 inst.instruction |= Rd << 8;
12269 inst.instruction |= Rm << 16;
12270 inst.instruction |= Rm;
c19d1205 12271}
b99bd4ef 12272
c19d1205
ZW		 12273static void
12274do_t_rev (void)
12275{
fdfde340
JM		 12276 unsigned Rd, Rm;
12277
12278 Rd = inst.operands[0].reg;
12279 Rm = inst.operands[1].reg;
12280
12281 reject_bad_reg (Rd);
12282 reject_bad_reg (Rm);
12283
12284 if (Rd <= 7 && Rm <= 7
c19d1205
ZW		 12285 && inst.size_req != 4)
12286 {
12287 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 12288 inst.instruction |= Rd;
12289 inst.instruction |= Rm << 3;
c19d1205
ZW		 12290 }
12291 else if (unified_syntax)
12292 {
12293 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12294 inst.instruction |= Rd << 8;
12295 inst.instruction |= Rm << 16;
12296 inst.instruction |= Rm;
c19d1205
ZW		 12297 }
12298 else
12299 inst.error = BAD_HIREG;
12300}
b99bd4ef 12301
1c444d06
JM		 12302static void
12303do_t_rrx (void)
12304{
12305 unsigned Rd, Rm;
12306
12307 Rd = inst.operands[0].reg;
12308 Rm = inst.operands[1].reg;
12309
fdfde340
JM		 12310 reject_bad_reg (Rd);
12311 reject_bad_reg (Rm);
c921be7d 12312
1c444d06
JM		 12313 inst.instruction |= Rd << 8;
12314 inst.instruction |= Rm;
12315}
12316
c19d1205
ZW		 12317static void
12318do_t_rsb (void)
12319{
fdfde340 12320 unsigned Rd, Rs;
b99bd4ef 12321
c19d1205
ZW		 12322 Rd = inst.operands[0].reg;
12323 Rs = (inst.operands[1].present
12324 ? inst.operands[1].reg /* Rd, Rs, foo */
12325 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 12326
fdfde340
JM		 12327 reject_bad_reg (Rd);
12328 reject_bad_reg (Rs);
12329 if (inst.operands[2].isreg)
12330 reject_bad_reg (inst.operands[2].reg);
12331
c19d1205
ZW		 12332 inst.instruction |= Rd << 8;
12333 inst.instruction |= Rs << 16;
12334 if (!inst.operands[2].isreg)
12335 {
026d3abb
PB		 12336 bfd_boolean narrow;
12337
12338 if ((inst.instruction & 0x00100000) != 0)
e07e6e58 12339 narrow = !in_it_block ();
026d3abb 12340 else
e07e6e58 12341 narrow = in_it_block ();
026d3abb
PB		 12342
12343 if (Rd > 7 || Rs > 7)
12344 narrow = FALSE;
12345
12346 if (inst.size_req == 4 || !unified_syntax)
12347 narrow = FALSE;
12348
12349 if (inst.reloc.exp.X_op != O_constant
12350 || inst.reloc.exp.X_add_number != 0)
12351 narrow = FALSE;
12352
12353 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 12354 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB		 12355 if (narrow)
12356 {
12357 inst.reloc.type = BFD_RELOC_UNUSED;
12358 inst.instruction = THUMB_OP16 (T_MNEM_negs);
12359 inst.instruction |= Rs << 3;
12360 inst.instruction |= Rd;
12361 }
12362 else
12363 {
12364 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12365 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12366 }
c19d1205
ZW		 12367 }
12368 else
12369 encode_thumb32_shifted_operand (2);
12370}
b99bd4ef 12371
c19d1205
ZW		 12372static void
12373do_t_setend (void)
12374{
12e37cbc
MGD		 12375 if (warn_on_deprecated
12376 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12377 as_warn (_("setend use is deprecated for ARMv8"));
12378
e07e6e58 12379 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW		 12380 if (inst.operands[0].imm)
12381 inst.instruction |= 0x8;
12382}
b99bd4ef 12383
c19d1205
ZW		 12384static void
12385do_t_shift (void)
12386{
12387 if (!inst.operands[1].present)
12388 inst.operands[1].reg = inst.operands[0].reg;
12389
12390 if (unified_syntax)
12391 {
3d388997
PB		 12392 bfd_boolean narrow;
12393 int shift_kind;
12394
12395 switch (inst.instruction)
12396 {
12397 case T_MNEM_asr:
12398 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
12399 case T_MNEM_lsl:
12400 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
12401 case T_MNEM_lsr:
12402 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
12403 case T_MNEM_ror:
12404 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
12405 default: abort ();
12406 }
12407
12408 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 12409 narrow = !in_it_block ();
3d388997 12410 else
e07e6e58 12411 narrow = in_it_block ();
3d388997
PB		 12412 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12413 narrow = FALSE;
12414 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
12415 narrow = FALSE;
12416 if (inst.operands[2].isreg
12417 && (inst.operands[1].reg != inst.operands[0].reg
12418 || inst.operands[2].reg > 7))
12419 narrow = FALSE;
12420 if (inst.size_req == 4)
12421 narrow = FALSE;
12422
fdfde340
JM		 12423 reject_bad_reg (inst.operands[0].reg);
12424 reject_bad_reg (inst.operands[1].reg);
c921be7d 12425
3d388997 12426 if (!narrow)
c19d1205
ZW		 12427 {
12428 if (inst.operands[2].isreg)
b99bd4ef 12429 {
fdfde340 12430 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW		 12431 inst.instruction = THUMB_OP32 (inst.instruction);
12432 inst.instruction |= inst.operands[0].reg << 8;
12433 inst.instruction |= inst.operands[1].reg << 16;
12434 inst.instruction |= inst.operands[2].reg;
94342ec3
NC		 12435
12436 /* PR 12854: Error on extraneous shifts. */
12437 constraint (inst.operands[2].shifted,
12438 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 12439 }
12440 else
12441 {
12442 inst.operands[1].shifted = 1;
3d388997 12443 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW		 12444 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
12445 ? T_MNEM_movs : T_MNEM_mov);
12446 inst.instruction |= inst.operands[0].reg << 8;
12447 encode_thumb32_shifted_operand (1);
12448 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12449 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef
NC		 12450 }
12451 }
12452 else
12453 {
c19d1205 12454 if (inst.operands[2].isreg)
b99bd4ef 12455 {
3d388997 12456 switch (shift_kind)
b99bd4ef 12457 {
3d388997
PB		 12458 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
12459 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
12460 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
12461 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 12462 default: abort ();
b99bd4ef 12463 }
5f4273c7 12464
c19d1205
ZW		 12465 inst.instruction |= inst.operands[0].reg;
12466 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 12467
12468 /* PR 12854: Error on extraneous shifts. */
12469 constraint (inst.operands[2].shifted,
12470 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC		 12471 }
12472 else
12473 {
3d388997 12474 switch (shift_kind)
b99bd4ef 12475 {
3d388997
PB		 12476 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12477 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12478 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 12479 default: abort ();
b99bd4ef 12480 }
c19d1205
ZW		 12481 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12482 inst.instruction |= inst.operands[0].reg;
12483 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 12484 }
12485 }
c19d1205
ZW		 12486 }
12487 else
12488 {
12489 constraint (inst.operands[0].reg > 7
12490 || inst.operands[1].reg > 7, BAD_HIREG);
12491 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 12492
c19d1205
ZW		 12493 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
12494 {
12495 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12496 constraint (inst.operands[0].reg != inst.operands[1].reg,
12497 _("source1 and dest must be same register"));
b99bd4ef 12498
c19d1205
ZW		 12499 switch (inst.instruction)
12500 {
12501 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
12502 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
12503 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
12504 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
12505 default: abort ();
12506 }
5f4273c7 12507
c19d1205
ZW		 12508 inst.instruction |= inst.operands[0].reg;
12509 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 12510
12511 /* PR 12854: Error on extraneous shifts. */
12512 constraint (inst.operands[2].shifted,
12513 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 12514 }
12515 else
b99bd4ef 12516 {
c19d1205
ZW		 12517 switch (inst.instruction)
12518 {
12519 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
12520 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12521 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12522 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12523 default: abort ();
12524 }
12525 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12526 inst.instruction |= inst.operands[0].reg;
12527 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 12528 }
12529 }
b99bd4ef
NC		 12530}
12531
12532static void
c19d1205 12533do_t_simd (void)
b99bd4ef 12534{
fdfde340
JM		 12535 unsigned Rd, Rn, Rm;
12536
12537 Rd = inst.operands[0].reg;
12538 Rn = inst.operands[1].reg;
12539 Rm = inst.operands[2].reg;
12540
12541 reject_bad_reg (Rd);
12542 reject_bad_reg (Rn);
12543 reject_bad_reg (Rm);
12544
12545 inst.instruction |= Rd << 8;
12546 inst.instruction |= Rn << 16;
12547 inst.instruction |= Rm;
c19d1205 12548}
b99bd4ef 12549
03ee1b7f
NC		 12550static void
12551do_t_simd2 (void)
12552{
12553 unsigned Rd, Rn, Rm;
12554
12555 Rd = inst.operands[0].reg;
12556 Rm = inst.operands[1].reg;
12557 Rn = inst.operands[2].reg;
12558
12559 reject_bad_reg (Rd);
12560 reject_bad_reg (Rn);
12561 reject_bad_reg (Rm);
12562
12563 inst.instruction |= Rd << 8;
12564 inst.instruction |= Rn << 16;
12565 inst.instruction |= Rm;
12566}
12567
c19d1205 12568static void
3eb17e6b 12569do_t_smc (void)
c19d1205
ZW		 12570{
12571 unsigned int value = inst.reloc.exp.X_add_number;
f4c65163
MGD		 12572 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12573 _("SMC is not permitted on this architecture"));
c19d1205
ZW		 12574 constraint (inst.reloc.exp.X_op != O_constant,
12575 _("expression too complex"));
12576 inst.reloc.type = BFD_RELOC_UNUSED;
12577 inst.instruction |= (value & 0xf000) >> 12;
12578 inst.instruction |= (value & 0x0ff0);
12579 inst.instruction |= (value & 0x000f) << 16;
24382199
NC		 12580 /* PR gas/15623: SMC instructions must be last in an IT block. */
12581 set_it_insn_type_last ();
c19d1205 12582}
b99bd4ef 12583
90ec0d68
MGD		 12584static void
12585do_t_hvc (void)
12586{
12587 unsigned int value = inst.reloc.exp.X_add_number;
12588
12589 inst.reloc.type = BFD_RELOC_UNUSED;
12590 inst.instruction |= (value & 0x0fff);
12591 inst.instruction |= (value & 0xf000) << 4;
12592}
12593
c19d1205 12594static void
3a21c15a 12595do_t_ssat_usat (int bias)
c19d1205 12596{
fdfde340
JM		 12597 unsigned Rd, Rn;
12598
12599 Rd = inst.operands[0].reg;
12600 Rn = inst.operands[2].reg;
12601
12602 reject_bad_reg (Rd);
12603 reject_bad_reg (Rn);
12604
12605 inst.instruction |= Rd << 8;
3a21c15a 12606 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 12607 inst.instruction |= Rn << 16;
b99bd4ef 12608
c19d1205 12609 if (inst.operands[3].present)
b99bd4ef 12610 {
3a21c15a
NC		 12611 offsetT shift_amount = inst.reloc.exp.X_add_number;
12612
12613 inst.reloc.type = BFD_RELOC_UNUSED;
12614
c19d1205
ZW		 12615 constraint (inst.reloc.exp.X_op != O_constant,
12616 _("expression too complex"));
b99bd4ef 12617
3a21c15a 12618 if (shift_amount != 0)
6189168b 12619 {
3a21c15a
NC		 12620 constraint (shift_amount > 31,
12621 _("shift expression is too large"));
12622
c19d1205 12623 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC		 12624 inst.instruction |= 0x00200000; /* sh bit. */
12625
12626 inst.instruction |= (shift_amount & 0x1c) << 10;
12627 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC		 12628 }
12629 }
b99bd4ef 12630}
c921be7d 12631
3a21c15a
NC		 12632static void
12633do_t_ssat (void)
12634{
12635 do_t_ssat_usat (1);
12636}
b99bd4ef 12637
0dd132b6 12638static void
c19d1205 12639do_t_ssat16 (void)
0dd132b6 12640{
fdfde340
JM		 12641 unsigned Rd, Rn;
12642
12643 Rd = inst.operands[0].reg;
12644 Rn = inst.operands[2].reg;
12645
12646 reject_bad_reg (Rd);
12647 reject_bad_reg (Rn);
12648
12649 inst.instruction |= Rd << 8;
c19d1205 12650 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 12651 inst.instruction |= Rn << 16;
c19d1205 12652}
0dd132b6 12653
c19d1205
ZW		 12654static void
12655do_t_strex (void)
12656{
12657 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12658 || inst.operands[2].postind || inst.operands[2].writeback
12659 || inst.operands[2].immisreg || inst.operands[2].shifted
12660 || inst.operands[2].negative,
01cfc07f 12661 BAD_ADDR_MODE);
0dd132b6 12662
5be8be5d
DG		 12663 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12664
c19d1205
ZW		 12665 inst.instruction |= inst.operands[0].reg << 8;
12666 inst.instruction |= inst.operands[1].reg << 12;
12667 inst.instruction |= inst.operands[2].reg << 16;
12668 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC		 12669}
12670
b99bd4ef 12671static void
c19d1205 12672do_t_strexd (void)
b99bd4ef 12673{
c19d1205
ZW		 12674 if (!inst.operands[2].present)
12675 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 12676
c19d1205
ZW		 12677 constraint (inst.operands[0].reg == inst.operands[1].reg
12678 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 12679 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 12680 BAD_OVERLAP);
b99bd4ef 12681
c19d1205
ZW		 12682 inst.instruction |= inst.operands[0].reg;
12683 inst.instruction |= inst.operands[1].reg << 12;
12684 inst.instruction |= inst.operands[2].reg << 8;
12685 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC		 12686}
12687
12688static void
c19d1205 12689do_t_sxtah (void)
b99bd4ef 12690{
fdfde340
JM		 12691 unsigned Rd, Rn, Rm;
12692
12693 Rd = inst.operands[0].reg;
12694 Rn = inst.operands[1].reg;
12695 Rm = inst.operands[2].reg;
12696
12697 reject_bad_reg (Rd);
12698 reject_bad_reg (Rn);
12699 reject_bad_reg (Rm);
12700
12701 inst.instruction |= Rd << 8;
12702 inst.instruction |= Rn << 16;
12703 inst.instruction |= Rm;
c19d1205
ZW		 12704 inst.instruction |= inst.operands[3].imm << 4;
12705}
b99bd4ef 12706
c19d1205
ZW		 12707static void
12708do_t_sxth (void)
12709{
fdfde340
JM		 12710 unsigned Rd, Rm;
12711
12712 Rd = inst.operands[0].reg;
12713 Rm = inst.operands[1].reg;
12714
12715 reject_bad_reg (Rd);
12716 reject_bad_reg (Rm);
c921be7d
NC		 12717
12718 if (inst.instruction <= 0xffff
12719 && inst.size_req != 4
fdfde340 12720 && Rd <= 7 && Rm <= 7
c19d1205 12721 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 12722 {
c19d1205 12723 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 12724 inst.instruction |= Rd;
12725 inst.instruction |= Rm << 3;
b99bd4ef 12726 }
c19d1205 12727 else if (unified_syntax)
b99bd4ef 12728 {
c19d1205
ZW		 12729 if (inst.instruction <= 0xffff)
12730 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12731 inst.instruction |= Rd << 8;
12732 inst.instruction |= Rm;
c19d1205 12733 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 12734 }
c19d1205 12735 else
b99bd4ef 12736 {
c19d1205
ZW		 12737 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12738 _("Thumb encoding does not support rotation"));
12739 constraint (1, BAD_HIREG);
b99bd4ef 12740 }
c19d1205 12741}
b99bd4ef 12742
c19d1205
ZW		 12743static void
12744do_t_swi (void)
12745{
b2a5fbdc
MGD		 12746 /* We have to do the following check manually as ARM_EXT_OS only applies
12747 to ARM_EXT_V6M. */
12748 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12749 {
ac7f631b
NC		 12750 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12751 /* This only applies to the v6m howver, not later architectures. */
12752 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
b2a5fbdc
MGD		 12753 as_bad (_("SVC is not permitted on this architecture"));
12754 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12755 }
12756
c19d1205
ZW		 12757 inst.reloc.type = BFD_RELOC_ARM_SWI;
12758}
b99bd4ef 12759
92e90b6e
PB		 12760static void
12761do_t_tb (void)
12762{
fdfde340 12763 unsigned Rn, Rm;
92e90b6e
PB		 12764 int half;
12765
12766 half = (inst.instruction & 0x10) != 0;
e07e6e58 12767 set_it_insn_type_last ();
dfa9f0d5
PB		 12768 constraint (inst.operands[0].immisreg,
12769 _("instruction requires register index"));
fdfde340
JM		 12770
12771 Rn = inst.operands[0].reg;
12772 Rm = inst.operands[0].imm;
c921be7d 12773
fdfde340
JM		 12774 constraint (Rn == REG_SP, BAD_SP);
12775 reject_bad_reg (Rm);
12776
92e90b6e
PB		 12777 constraint (!half && inst.operands[0].shifted,
12778 _("instruction does not allow shifted index"));
fdfde340 12779 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB		 12780}
12781
74db7efb
NC		 12782static void
12783do_t_udf (void)
12784{
12785 if (!inst.operands[0].present)
12786 inst.operands[0].imm = 0;
12787
12788 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
12789 {
12790 constraint (inst.size_req == 2,
12791 _("immediate value out of range"));
12792 inst.instruction = THUMB_OP32 (inst.instruction);
12793 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
12794 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
12795 }
12796 else
12797 {
12798 inst.instruction = THUMB_OP16 (inst.instruction);
12799 inst.instruction |= inst.operands[0].imm;
12800 }
12801
12802 set_it_insn_type (NEUTRAL_IT_INSN);
12803}
12804
12805
c19d1205
ZW		 12806static void
12807do_t_usat (void)
12808{
3a21c15a 12809 do_t_ssat_usat (0);
b99bd4ef
NC		 12810}
12811
12812static void
c19d1205 12813do_t_usat16 (void)
b99bd4ef 12814{
fdfde340
JM		 12815 unsigned Rd, Rn;
12816
12817 Rd = inst.operands[0].reg;
12818 Rn = inst.operands[2].reg;
12819
12820 reject_bad_reg (Rd);
12821 reject_bad_reg (Rn);
12822
12823 inst.instruction |= Rd << 8;
c19d1205 12824 inst.instruction |= inst.operands[1].imm;
fdfde340 12825 inst.instruction |= Rn << 16;
b99bd4ef 12826}
c19d1205 12827
5287ad62 12828/* Neon instruction encoder helpers. */
5f4273c7 12829
5287ad62 12830/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 12831
5287ad62
JB		 12832/* An "invalid" code for the following tables. */
12833#define N_INV -1u
12834
12835struct neon_tab_entry
b99bd4ef 12836{
5287ad62
JB		 12837 unsigned integer;
12838 unsigned float_or_poly;
12839 unsigned scalar_or_imm;
12840};
5f4273c7 12841
5287ad62
JB		 12842/* Map overloaded Neon opcodes to their respective encodings. */
12843#define NEON_ENC_TAB \
12844 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12845 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12846 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12847 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12848 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12849 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12850 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12851 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12852 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12853 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12854 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12855 /* Register variants of the following two instructions are encoded as
e07e6e58 12856 vcge / vcgt with the operands reversed. */ \
92559b5b
PB		 12857 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12858 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB		 12859 X(vfma, N_INV, 0x0000c10, N_INV), \
12860 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB		 12861 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12862 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12863 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12864 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12865 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12866 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12867 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12868 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12869 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12870 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12871 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12872 X(vshl, 0x0000400, N_INV, 0x0800510), \
12873 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12874 X(vand, 0x0000110, N_INV, 0x0800030), \
12875 X(vbic, 0x0100110, N_INV, 0x0800030), \
12876 X(veor, 0x1000110, N_INV, N_INV), \
12877 X(vorn, 0x0300110, N_INV, 0x0800010), \
12878 X(vorr, 0x0200110, N_INV, 0x0800010), \
12879 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12880 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12881 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12882 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12883 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12884 X(vst1, 0x0000000, 0x0800000, N_INV), \
12885 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12886 X(vst2, 0x0000100, 0x0800100, N_INV), \
12887 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12888 X(vst3, 0x0000200, 0x0800200, N_INV), \
12889 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12890 X(vst4, 0x0000300, 0x0800300, N_INV), \
12891 X(vmovn, 0x1b20200, N_INV, N_INV), \
12892 X(vtrn, 0x1b20080, N_INV, N_INV), \
12893 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB		 12894 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12895 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB		 12896 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12897 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB		 12898 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12899 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB		 12900 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12901 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12902 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD		 12903 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12904 X(vseleq, 0xe000a00, N_INV, N_INV), \
12905 X(vselvs, 0xe100a00, N_INV, N_INV), \
12906 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD		 12907 X(vselgt, 0xe300a00, N_INV, N_INV), \
12908 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 12909 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD		 12910 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12911 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 12912 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 12913 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD		 12914 X(sha3op, 0x2000c00, N_INV, N_INV), \
12915 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12916 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB		 12917
12918enum neon_opc
12919{
12920#define X(OPC,I,F,S) N_MNEM_##OPC
12921NEON_ENC_TAB
12922#undef X
12923};
b99bd4ef 12924
5287ad62
JB		 12925static const struct neon_tab_entry neon_enc_tab[] =
12926{
12927#define X(OPC,I,F,S) { (I), (F), (S) }
12928NEON_ENC_TAB
12929#undef X
12930};
b99bd4ef 12931
88714cb8
DG		 12932/* Do not use these macros; instead, use NEON_ENCODE defined below. */
12933#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12934#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12935#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12936#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12937#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12938#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12939#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12940#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12941#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12942#define NEON_ENC_SINGLE_(X) \
037e8744 12943 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 12944#define NEON_ENC_DOUBLE_(X) \
037e8744 12945 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD		 12946#define NEON_ENC_FPV8_(X) \
12947 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 12948
88714cb8
DG		 12949#define NEON_ENCODE(type, inst) \
12950 do \
12951 { \
12952 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12953 inst.is_neon = 1; \
12954 } \
12955 while (0)
12956
12957#define check_neon_suffixes \
12958 do \
12959 { \
12960 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12961 { \
12962 as_bad (_("invalid neon suffix for non neon instruction")); \
12963 return; \
12964 } \
12965 } \
12966 while (0)
12967
037e8744
JB		 12968/* Define shapes for instruction operands. The following mnemonic characters
12969 are used in this table:
5287ad62 12970
037e8744 12971 F - VFP S<n> register
5287ad62
JB		 12972 D - Neon D<n> register
12973 Q - Neon Q<n> register
12974 I - Immediate
12975 S - Scalar
12976 R - ARM register
12977 L - D<n> register list
5f4273c7 12978
037e8744
JB		 12979 This table is used to generate various data:
12980 - enumerations of the form NS_DDR to be used as arguments to
12981 neon_select_shape.
12982 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 12983 - a table used to drive neon_select_shape. */
b99bd4ef 12984
037e8744
JB		 12985#define NEON_SHAPE_DEF \
12986 X(3, (D, D, D), DOUBLE), \
12987 X(3, (Q, Q, Q), QUAD), \
12988 X(3, (D, D, I), DOUBLE), \
12989 X(3, (Q, Q, I), QUAD), \
12990 X(3, (D, D, S), DOUBLE), \
12991 X(3, (Q, Q, S), QUAD), \
12992 X(2, (D, D), DOUBLE), \
12993 X(2, (Q, Q), QUAD), \
12994 X(2, (D, S), DOUBLE), \
12995 X(2, (Q, S), QUAD), \
12996 X(2, (D, R), DOUBLE), \
12997 X(2, (Q, R), QUAD), \
12998 X(2, (D, I), DOUBLE), \
12999 X(2, (Q, I), QUAD), \
13000 X(3, (D, L, D), DOUBLE), \
13001 X(2, (D, Q), MIXED), \
13002 X(2, (Q, D), MIXED), \
13003 X(3, (D, Q, I), MIXED), \
13004 X(3, (Q, D, I), MIXED), \
13005 X(3, (Q, D, D), MIXED), \
13006 X(3, (D, Q, Q), MIXED), \
13007 X(3, (Q, Q, D), MIXED), \
13008 X(3, (Q, D, S), MIXED), \
13009 X(3, (D, Q, S), MIXED), \
13010 X(4, (D, D, D, I), DOUBLE), \
13011 X(4, (Q, Q, Q, I), QUAD), \
13012 X(2, (F, F), SINGLE), \
13013 X(3, (F, F, F), SINGLE), \
13014 X(2, (F, I), SINGLE), \
13015 X(2, (F, D), MIXED), \
13016 X(2, (D, F), MIXED), \
13017 X(3, (F, F, I), MIXED), \
13018 X(4, (R, R, F, F), SINGLE), \
13019 X(4, (F, F, R, R), SINGLE), \
13020 X(3, (D, R, R), DOUBLE), \
13021 X(3, (R, R, D), DOUBLE), \
13022 X(2, (S, R), SINGLE), \
13023 X(2, (R, S), SINGLE), \
13024 X(2, (F, R), SINGLE), \
13025 X(2, (R, F), SINGLE)
13026
13027#define S2(A,B) NS_##A##B
13028#define S3(A,B,C) NS_##A##B##C
13029#define S4(A,B,C,D) NS_##A##B##C##D
13030
13031#define X(N, L, C) S##N L
13032
5287ad62
JB		 13033enum neon_shape
13034{
037e8744
JB		 13035 NEON_SHAPE_DEF,
13036 NS_NULL
5287ad62 13037};
b99bd4ef 13038
037e8744
JB		 13039#undef X
13040#undef S2
13041#undef S3
13042#undef S4
13043
13044enum neon_shape_class
13045{
13046 SC_SINGLE,
13047 SC_DOUBLE,
13048 SC_QUAD,
13049 SC_MIXED
13050};
13051
13052#define X(N, L, C) SC_##C
13053
13054static enum neon_shape_class neon_shape_class[] =
13055{
13056 NEON_SHAPE_DEF
13057};
13058
13059#undef X
13060
13061enum neon_shape_el
13062{
13063 SE_F,
13064 SE_D,
13065 SE_Q,
13066 SE_I,
13067 SE_S,
13068 SE_R,
13069 SE_L
13070};
13071
13072/* Register widths of above. */
13073static unsigned neon_shape_el_size[] =
13074{
13075 32,
13076 64,
13077 128,
13078 0,
13079 32,
13080 32,
13081 0
13082};
13083
13084struct neon_shape_info
13085{
13086 unsigned els;
13087 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
13088};
13089
13090#define S2(A,B) { SE_##A, SE_##B }
13091#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13092#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13093
13094#define X(N, L, C) { N, S##N L }
13095
13096static struct neon_shape_info neon_shape_tab[] =
13097{
13098 NEON_SHAPE_DEF
13099};
13100
13101#undef X
13102#undef S2
13103#undef S3
13104#undef S4
13105
5287ad62
JB		 13106/* Bit masks used in type checking given instructions.
13107 'N_EQK' means the type must be the same as (or based on in some way) the key
13108 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13109 set, various other bits can be set as well in order to modify the meaning of
13110 the type constraint. */
13111
13112enum neon_type_mask
13113{
8e79c3df
CM		 13114 N_S8 = 0x0000001,
13115 N_S16 = 0x0000002,
13116 N_S32 = 0x0000004,
13117 N_S64 = 0x0000008,
13118 N_U8 = 0x0000010,
13119 N_U16 = 0x0000020,
13120 N_U32 = 0x0000040,
13121 N_U64 = 0x0000080,
13122 N_I8 = 0x0000100,
13123 N_I16 = 0x0000200,
13124 N_I32 = 0x0000400,
13125 N_I64 = 0x0000800,
13126 N_8 = 0x0001000,
13127 N_16 = 0x0002000,
13128 N_32 = 0x0004000,
13129 N_64 = 0x0008000,
13130 N_P8 = 0x0010000,
13131 N_P16 = 0x0020000,
13132 N_F16 = 0x0040000,
13133 N_F32 = 0x0080000,
13134 N_F64 = 0x0100000,
4f51b4bd 13135 N_P64 = 0x0200000,
c921be7d
NC		 13136 N_KEY = 0x1000000, /* Key element (main type specifier). */
13137 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 13138 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 13139 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC		 13140 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
13141 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
13142 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13143 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13144 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13145 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
13146 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 13147 N_UTYP = 0,
4f51b4bd 13148 N_MAX_NONSPECIAL = N_P64
5287ad62
JB		 13149};
13150
dcbf9037
JB		 13151#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13152
5287ad62
JB		 13153#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13154#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13155#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13156#define N_SUF_32 (N_SU_32 | N_F32)
13157#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13158#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13159
13160/* Pass this as the first type argument to neon_check_type to ignore types
13161 altogether. */
13162#define N_IGNORE_TYPE (N_KEY | N_EQK)
13163
037e8744
JB		 13164/* Select a "shape" for the current instruction (describing register types or
13165 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13166 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13167 function of operand parsing, so this function doesn't need to be called.
13168 Shapes should be listed in order of decreasing length. */
5287ad62
JB		 13169
13170static enum neon_shape
037e8744 13171neon_select_shape (enum neon_shape shape, ...)
5287ad62 13172{
037e8744
JB		 13173 va_list ap;
13174 enum neon_shape first_shape = shape;
5287ad62
JB		 13175
13176 /* Fix missing optional operands. FIXME: we don't know at this point how
13177 many arguments we should have, so this makes the assumption that we have
13178 > 1. This is true of all current Neon opcodes, I think, but may not be
13179 true in the future. */
13180 if (!inst.operands[1].present)
13181 inst.operands[1] = inst.operands[0];
13182
037e8744 13183 va_start (ap, shape);
5f4273c7 13184
21d799b5 13185 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB		 13186 {
13187 unsigned j;
13188 int matches = 1;
13189
13190 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM		 13191 {
13192 if (!inst.operands[j].present)
13193 {
13194 matches = 0;
13195 break;
13196 }
13197
13198 switch (neon_shape_tab[shape].el[j])
13199 {
13200 case SE_F:
13201 if (!(inst.operands[j].isreg
13202 && inst.operands[j].isvec
13203 && inst.operands[j].issingle
13204 && !inst.operands[j].isquad))
13205 matches = 0;
13206 break;
13207
13208 case SE_D:
13209 if (!(inst.operands[j].isreg
13210 && inst.operands[j].isvec
13211 && !inst.operands[j].isquad
13212 && !inst.operands[j].issingle))
13213 matches = 0;
13214 break;
13215
13216 case SE_R:
13217 if (!(inst.operands[j].isreg
13218 && !inst.operands[j].isvec))
13219 matches = 0;
13220 break;
13221
13222 case SE_Q:
13223 if (!(inst.operands[j].isreg
13224 && inst.operands[j].isvec
13225 && inst.operands[j].isquad
13226 && !inst.operands[j].issingle))
13227 matches = 0;
13228 break;
13229
13230 case SE_I:
13231 if (!(!inst.operands[j].isreg
13232 && !inst.operands[j].isscalar))
13233 matches = 0;
13234 break;
13235
13236 case SE_S:
13237 if (!(!inst.operands[j].isreg
13238 && inst.operands[j].isscalar))
13239 matches = 0;
13240 break;
13241
13242 case SE_L:
13243 break;
13244 }
3fde54a2
JZ		 13245 if (!matches)
13246 break;
477330fc 13247 }
ad6cec43
MGD		 13248 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
13249 /* We've matched all the entries in the shape table, and we don't
13250 have any left over operands which have not been matched. */
477330fc 13251 break;
037e8744 13252 }
5f4273c7 13253
037e8744 13254 va_end (ap);
5287ad62 13255
037e8744
JB		 13256 if (shape == NS_NULL && first_shape != NS_NULL)
13257 first_error (_("invalid instruction shape"));
5287ad62 13258
037e8744
JB		 13259 return shape;
13260}
5287ad62 13261
037e8744
JB		 13262/* True if SHAPE is predominantly a quadword operation (most of the time, this
13263 means the Q bit should be set). */
13264
13265static int
13266neon_quad (enum neon_shape shape)
13267{
13268 return neon_shape_class[shape] == SC_QUAD;
5287ad62 13269}
037e8744 13270
5287ad62
JB		 13271static void
13272neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 13273 unsigned *g_size)
5287ad62
JB		 13274{
13275 /* Allow modification to be made to types which are constrained to be
13276 based on the key element, based on bits set alongside N_EQK. */
13277 if ((typebits & N_EQK) != 0)
13278 {
13279 if ((typebits & N_HLF) != 0)
13280 *g_size /= 2;
13281 else if ((typebits & N_DBL) != 0)
13282 *g_size *= 2;
13283 if ((typebits & N_SGN) != 0)
13284 *g_type = NT_signed;
13285 else if ((typebits & N_UNS) != 0)
477330fc 13286 *g_type = NT_unsigned;
5287ad62 13287 else if ((typebits & N_INT) != 0)
477330fc 13288 *g_type = NT_integer;
5287ad62 13289 else if ((typebits & N_FLT) != 0)
477330fc 13290 *g_type = NT_float;
dcbf9037 13291 else if ((typebits & N_SIZ) != 0)
477330fc 13292 *g_type = NT_untyped;
5287ad62
JB		 13293 }
13294}
5f4273c7 13295
5287ad62
JB		 13296/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13297 operand type, i.e. the single type specified in a Neon instruction when it
13298 is the only one given. */
13299
13300static struct neon_type_el
13301neon_type_promote (struct neon_type_el *key, unsigned thisarg)
13302{
13303 struct neon_type_el dest = *key;
5f4273c7 13304
9c2799c2 13305 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 13306
5287ad62
JB		 13307 neon_modify_type_size (thisarg, &dest.type, &dest.size);
13308
13309 return dest;
13310}
13311
13312/* Convert Neon type and size into compact bitmask representation. */
13313
13314static enum neon_type_mask
13315type_chk_of_el_type (enum neon_el_type type, unsigned size)
13316{
13317 switch (type)
13318 {
13319 case NT_untyped:
13320 switch (size)
477330fc
RM		 13321 {
13322 case 8: return N_8;
13323 case 16: return N_16;
13324 case 32: return N_32;
13325 case 64: return N_64;
13326 default: ;
13327 }
5287ad62
JB		 13328 break;
13329
13330 case NT_integer:
13331 switch (size)
477330fc
RM		 13332 {
13333 case 8: return N_I8;
13334 case 16: return N_I16;
13335 case 32: return N_I32;
13336 case 64: return N_I64;
13337 default: ;
13338 }
5287ad62
JB		 13339 break;
13340
13341 case NT_float:
037e8744 13342 switch (size)
477330fc 13343 {
8e79c3df 13344 case 16: return N_F16;
477330fc
RM		 13345 case 32: return N_F32;
13346 case 64: return N_F64;
13347 default: ;
13348 }
5287ad62
JB		 13349 break;
13350
13351 case NT_poly:
13352 switch (size)
477330fc
RM		 13353 {
13354 case 8: return N_P8;
13355 case 16: return N_P16;
4f51b4bd 13356 case 64: return N_P64;
477330fc
RM		 13357 default: ;
13358 }
5287ad62
JB		 13359 break;
13360
13361 case NT_signed:
13362 switch (size)
477330fc
RM		 13363 {
13364 case 8: return N_S8;
13365 case 16: return N_S16;
13366 case 32: return N_S32;
13367 case 64: return N_S64;
13368 default: ;
13369 }
5287ad62
JB		 13370 break;
13371
13372 case NT_unsigned:
13373 switch (size)
477330fc
RM		 13374 {
13375 case 8: return N_U8;
13376 case 16: return N_U16;
13377 case 32: return N_U32;
13378 case 64: return N_U64;
13379 default: ;
13380 }
5287ad62
JB		 13381 break;
13382
13383 default: ;
13384 }
5f4273c7 13385
5287ad62
JB		 13386 return N_UTYP;
13387}
13388
13389/* Convert compact Neon bitmask type representation to a type and size. Only
13390 handles the case where a single bit is set in the mask. */
13391
dcbf9037 13392static int
5287ad62 13393el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 13394 enum neon_type_mask mask)
5287ad62 13395{
dcbf9037
JB		 13396 if ((mask & N_EQK) != 0)
13397 return FAIL;
13398
5287ad62
JB		 13399 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
13400 *size = 8;
c70a8987 13401 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
5287ad62 13402 *size = 16;
dcbf9037 13403 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 13404 *size = 32;
4f51b4bd 13405 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 13406 *size = 64;
dcbf9037
JB		 13407 else
13408 return FAIL;
13409
5287ad62
JB		 13410 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
13411 *type = NT_signed;
dcbf9037 13412 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 13413 *type = NT_unsigned;
dcbf9037 13414 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 13415 *type = NT_integer;
dcbf9037 13416 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 13417 *type = NT_untyped;
4f51b4bd 13418 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 13419 *type = NT_poly;
c70a8987 13420 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
5287ad62 13421 *type = NT_float;
dcbf9037
JB		 13422 else
13423 return FAIL;
5f4273c7 13424
dcbf9037 13425 return SUCCESS;
5287ad62
JB		 13426}
13427
13428/* Modify a bitmask of allowed types. This is only needed for type
13429 relaxation. */
13430
13431static unsigned
13432modify_types_allowed (unsigned allowed, unsigned mods)
13433{
13434 unsigned size;
13435 enum neon_el_type type;
13436 unsigned destmask;
13437 int i;
5f4273c7 13438
5287ad62 13439 destmask = 0;
5f4273c7 13440
5287ad62
JB		 13441 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
13442 {
21d799b5 13443 if (el_type_of_type_chk (&type, &size,
477330fc
RM		 13444 (enum neon_type_mask) (allowed & i)) == SUCCESS)
13445 {
13446 neon_modify_type_size (mods, &type, &size);
13447 destmask |= type_chk_of_el_type (type, size);
13448 }
5287ad62 13449 }
5f4273c7 13450
5287ad62
JB		 13451 return destmask;
13452}
13453
13454/* Check type and return type classification.
13455 The manual states (paraphrase): If one datatype is given, it indicates the
13456 type given in:
13457 - the second operand, if there is one
13458 - the operand, if there is no second operand
13459 - the result, if there are no operands.
13460 This isn't quite good enough though, so we use a concept of a "key" datatype
13461 which is set on a per-instruction basis, which is the one which matters when
13462 only one data type is written.
13463 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 13464 Neon instructions should call it before performing bit encoding. */
5287ad62
JB		 13465
13466static struct neon_type_el
13467neon_check_type (unsigned els, enum neon_shape ns, ...)
13468{
13469 va_list ap;
13470 unsigned i, pass, key_el = 0;
13471 unsigned types[NEON_MAX_TYPE_ELS];
13472 enum neon_el_type k_type = NT_invtype;
13473 unsigned k_size = -1u;
13474 struct neon_type_el badtype = {NT_invtype, -1};
13475 unsigned key_allowed = 0;
13476
13477 /* Optional registers in Neon instructions are always (not) in operand 1.
13478 Fill in the missing operand here, if it was omitted. */
13479 if (els > 1 && !inst.operands[1].present)
13480 inst.operands[1] = inst.operands[0];
13481
13482 /* Suck up all the varargs. */
13483 va_start (ap, ns);
13484 for (i = 0; i < els; i++)
13485 {
13486 unsigned thisarg = va_arg (ap, unsigned);
13487 if (thisarg == N_IGNORE_TYPE)
477330fc
RM		 13488 {
13489 va_end (ap);
13490 return badtype;
13491 }
5287ad62
JB		 13492 types[i] = thisarg;
13493 if ((thisarg & N_KEY) != 0)
477330fc 13494 key_el = i;
5287ad62
JB		 13495 }
13496 va_end (ap);
13497
dcbf9037
JB		 13498 if (inst.vectype.elems > 0)
13499 for (i = 0; i < els; i++)
13500 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM		 13501 {
13502 first_error (_("types specified in both the mnemonic and operands"));
13503 return badtype;
13504 }
dcbf9037 13505
5287ad62
JB		 13506 /* Duplicate inst.vectype elements here as necessary.
13507 FIXME: No idea if this is exactly the same as the ARM assembler,
13508 particularly when an insn takes one register and one non-register
13509 operand. */
13510 if (inst.vectype.elems == 1 && els > 1)
13511 {
13512 unsigned j;
13513 inst.vectype.elems = els;
13514 inst.vectype.el[key_el] = inst.vectype.el[0];
13515 for (j = 0; j < els; j++)
477330fc
RM		 13516 if (j != key_el)
13517 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13518 types[j]);
dcbf9037
JB		 13519 }
13520 else if (inst.vectype.elems == 0 && els > 0)
13521 {
13522 unsigned j;
13523 /* No types were given after the mnemonic, so look for types specified
477330fc
RM		 13524 after each operand. We allow some flexibility here; as long as the
13525 "key" operand has a type, we can infer the others. */
dcbf9037 13526 for (j = 0; j < els; j++)
477330fc
RM		 13527 if (inst.operands[j].vectype.type != NT_invtype)
13528 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB		 13529
13530 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM		 13531 {
13532 for (j = 0; j < els; j++)
13533 if (inst.operands[j].vectype.type == NT_invtype)
13534 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13535 types[j]);
13536 }
dcbf9037 13537 else
477330fc
RM		 13538 {
13539 first_error (_("operand types can't be inferred"));
13540 return badtype;
13541 }
5287ad62
JB		 13542 }
13543 else if (inst.vectype.elems != els)
13544 {
dcbf9037 13545 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB		 13546 return badtype;
13547 }
13548
13549 for (pass = 0; pass < 2; pass++)
13550 {
13551 for (i = 0; i < els; i++)
477330fc
RM		 13552 {
13553 unsigned thisarg = types[i];
13554 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13555 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13556 enum neon_el_type g_type = inst.vectype.el[i].type;
13557 unsigned g_size = inst.vectype.el[i].size;
13558
13559 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 13560 integer types if sign-specific variants are unavailable. */
477330fc 13561 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB		 13562 && (types_allowed & N_SU_ALL) == 0)
13563 g_type = NT_integer;
13564
477330fc 13565 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB		 13566 them. Some instructions only care about signs for some element
13567 sizes, so handle that properly. */
477330fc 13568 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD		 13569 && ((g_size == 8 && (types_allowed & N_8) != 0)
13570 || (g_size == 16 && (types_allowed & N_16) != 0)
13571 || (g_size == 32 && (types_allowed & N_32) != 0)
13572 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB		 13573 g_type = NT_untyped;
13574
477330fc
RM		 13575 if (pass == 0)
13576 {
13577 if ((thisarg & N_KEY) != 0)
13578 {
13579 k_type = g_type;
13580 k_size = g_size;
13581 key_allowed = thisarg & ~N_KEY;
13582 }
13583 }
13584 else
13585 {
13586 if ((thisarg & N_VFP) != 0)
13587 {
13588 enum neon_shape_el regshape;
13589 unsigned regwidth, match;
99b253c5
NC		 13590
13591 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13592 if (ns == NS_NULL)
13593 {
13594 first_error (_("invalid instruction shape"));
13595 return badtype;
13596 }
477330fc
RM		 13597 regshape = neon_shape_tab[ns].el[i];
13598 regwidth = neon_shape_el_size[regshape];
13599
13600 /* In VFP mode, operands must match register widths. If we
13601 have a key operand, use its width, else use the width of
13602 the current operand. */
13603 if (k_size != -1u)
13604 match = k_size;
13605 else
13606 match = g_size;
13607
13608 if (regwidth != match)
13609 {
13610 first_error (_("operand size must match register width"));
13611 return badtype;
13612 }
13613 }
13614
13615 if ((thisarg & N_EQK) == 0)
13616 {
13617 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13618
13619 if ((given_type & types_allowed) == 0)
13620 {
13621 first_error (_("bad type in Neon instruction"));
13622 return badtype;
13623 }
13624 }
13625 else
13626 {
13627 enum neon_el_type mod_k_type = k_type;
13628 unsigned mod_k_size = k_size;
13629 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13630 if (g_type != mod_k_type || g_size != mod_k_size)
13631 {
13632 first_error (_("inconsistent types in Neon instruction"));
13633 return badtype;
13634 }
13635 }
13636 }
13637 }
5287ad62
JB		 13638 }
13639
13640 return inst.vectype.el[key_el];
13641}
13642
037e8744 13643/* Neon-style VFP instruction forwarding. */
5287ad62 13644
037e8744
JB		 13645/* Thumb VFP instructions have 0xE in the condition field. */
13646
13647static void
13648do_vfp_cond_or_thumb (void)
5287ad62 13649{
88714cb8
DG		 13650 inst.is_neon = 1;
13651
5287ad62 13652 if (thumb_mode)
037e8744 13653 inst.instruction |= 0xe0000000;
5287ad62 13654 else
037e8744 13655 inst.instruction |= inst.cond << 28;
5287ad62
JB		 13656}
13657
037e8744
JB		 13658/* Look up and encode a simple mnemonic, for use as a helper function for the
13659 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13660 etc. It is assumed that operand parsing has already been done, and that the
13661 operands are in the form expected by the given opcode (this isn't necessarily
13662 the same as the form in which they were parsed, hence some massaging must
13663 take place before this function is called).
13664 Checks current arch version against that in the looked-up opcode. */
5287ad62 13665
037e8744
JB		 13666static void
13667do_vfp_nsyn_opcode (const char *opname)
5287ad62 13668{
037e8744 13669 const struct asm_opcode *opcode;
5f4273c7 13670
21d799b5 13671 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 13672
037e8744
JB		 13673 if (!opcode)
13674 abort ();
5287ad62 13675
037e8744 13676 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM		 13677 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13678 _(BAD_FPU));
5287ad62 13679
88714cb8
DG		 13680 inst.is_neon = 1;
13681
037e8744
JB		 13682 if (thumb_mode)
13683 {
13684 inst.instruction = opcode->tvalue;
13685 opcode->tencode ();
13686 }
13687 else
13688 {
13689 inst.instruction = (inst.cond << 28) | opcode->avalue;
13690 opcode->aencode ();
13691 }
13692}
5287ad62
JB		 13693
13694static void
037e8744 13695do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 13696{
037e8744
JB		 13697 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13698
13699 if (rs == NS_FFF)
13700 {
13701 if (is_add)
477330fc 13702 do_vfp_nsyn_opcode ("fadds");
037e8744 13703 else
477330fc 13704 do_vfp_nsyn_opcode ("fsubs");
037e8744
JB		 13705 }
13706 else
13707 {
13708 if (is_add)
477330fc 13709 do_vfp_nsyn_opcode ("faddd");
037e8744 13710 else
477330fc 13711 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB		 13712 }
13713}
13714
13715/* Check operand types to see if this is a VFP instruction, and if so call
13716 PFN (). */
13717
13718static int
13719try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13720{
13721 enum neon_shape rs;
13722 struct neon_type_el et;
13723
13724 switch (args)
13725 {
13726 case 2:
13727 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13728 et = neon_check_type (2, rs,
477330fc 13729 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
037e8744 13730 break;
5f4273c7 13731
037e8744
JB		 13732 case 3:
13733 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13734 et = neon_check_type (3, rs,
477330fc 13735 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
037e8744
JB		 13736 break;
13737
13738 default:
13739 abort ();
13740 }
13741
13742 if (et.type != NT_invtype)
13743 {
13744 pfn (rs);
13745 return SUCCESS;
13746 }
037e8744 13747
99b253c5 13748 inst.error = NULL;
037e8744
JB		 13749 return FAIL;
13750}
13751
13752static void
13753do_vfp_nsyn_mla_mls (enum neon_shape rs)
13754{
13755 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 13756
037e8744
JB		 13757 if (rs == NS_FFF)
13758 {
13759 if (is_mla)
477330fc 13760 do_vfp_nsyn_opcode ("fmacs");
037e8744 13761 else
477330fc 13762 do_vfp_nsyn_opcode ("fnmacs");
037e8744
JB		 13763 }
13764 else
13765 {
13766 if (is_mla)
477330fc 13767 do_vfp_nsyn_opcode ("fmacd");
037e8744 13768 else
477330fc 13769 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB		 13770 }
13771}
13772
62f3b8c8
PB		 13773static void
13774do_vfp_nsyn_fma_fms (enum neon_shape rs)
13775{
13776 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13777
13778 if (rs == NS_FFF)
13779 {
13780 if (is_fma)
477330fc 13781 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 13782 else
477330fc 13783 do_vfp_nsyn_opcode ("ffnmas");
62f3b8c8
PB		 13784 }
13785 else
13786 {
13787 if (is_fma)
477330fc 13788 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 13789 else
477330fc 13790 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB		 13791 }
13792}
13793
037e8744
JB		 13794static void
13795do_vfp_nsyn_mul (enum neon_shape rs)
13796{
13797 if (rs == NS_FFF)
13798 do_vfp_nsyn_opcode ("fmuls");
13799 else
13800 do_vfp_nsyn_opcode ("fmuld");
13801}
13802
13803static void
13804do_vfp_nsyn_abs_neg (enum neon_shape rs)
13805{
13806 int is_neg = (inst.instruction & 0x80) != 0;
13807 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13808
13809 if (rs == NS_FF)
13810 {
13811 if (is_neg)
477330fc 13812 do_vfp_nsyn_opcode ("fnegs");
037e8744 13813 else
477330fc 13814 do_vfp_nsyn_opcode ("fabss");
037e8744
JB		 13815 }
13816 else
13817 {
13818 if (is_neg)
477330fc 13819 do_vfp_nsyn_opcode ("fnegd");
037e8744 13820 else
477330fc 13821 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB		 13822 }
13823}
13824
13825/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13826 insns belong to Neon, and are handled elsewhere. */
13827
13828static void
13829do_vfp_nsyn_ldm_stm (int is_dbmode)
13830{
13831 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13832 if (is_ldm)
13833 {
13834 if (is_dbmode)
477330fc 13835 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 13836 else
477330fc 13837 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB		 13838 }
13839 else
13840 {
13841 if (is_dbmode)
477330fc 13842 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 13843 else
477330fc 13844 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB		 13845 }
13846}
13847
037e8744
JB		 13848static void
13849do_vfp_nsyn_sqrt (void)
13850{
13851 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13852 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13853
037e8744
JB		 13854 if (rs == NS_FF)
13855 do_vfp_nsyn_opcode ("fsqrts");
13856 else
13857 do_vfp_nsyn_opcode ("fsqrtd");
13858}
13859
13860static void
13861do_vfp_nsyn_div (void)
13862{
13863 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13864 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13865 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13866
037e8744
JB		 13867 if (rs == NS_FFF)
13868 do_vfp_nsyn_opcode ("fdivs");
13869 else
13870 do_vfp_nsyn_opcode ("fdivd");
13871}
13872
13873static void
13874do_vfp_nsyn_nmul (void)
13875{
13876 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13877 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13878 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13879
037e8744
JB		 13880 if (rs == NS_FFF)
13881 {
88714cb8 13882 NEON_ENCODE (SINGLE, inst);
037e8744
JB		 13883 do_vfp_sp_dyadic ();
13884 }
13885 else
13886 {
88714cb8 13887 NEON_ENCODE (DOUBLE, inst);
037e8744
JB		 13888 do_vfp_dp_rd_rn_rm ();
13889 }
13890 do_vfp_cond_or_thumb ();
13891}
13892
13893static void
13894do_vfp_nsyn_cmp (void)
13895{
13896 if (inst.operands[1].isreg)
13897 {
13898 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13899 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13900
037e8744 13901 if (rs == NS_FF)
477330fc
RM		 13902 {
13903 NEON_ENCODE (SINGLE, inst);
13904 do_vfp_sp_monadic ();
13905 }
037e8744 13906 else
477330fc
RM		 13907 {
13908 NEON_ENCODE (DOUBLE, inst);
13909 do_vfp_dp_rd_rm ();
13910 }
037e8744
JB		 13911 }
13912 else
13913 {
13914 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13915 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13916
13917 switch (inst.instruction & 0x0fffffff)
477330fc
RM		 13918 {
13919 case N_MNEM_vcmp:
13920 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13921 break;
13922 case N_MNEM_vcmpe:
13923 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13924 break;
13925 default:
13926 abort ();
13927 }
5f4273c7 13928
037e8744 13929 if (rs == NS_FI)
477330fc
RM		 13930 {
13931 NEON_ENCODE (SINGLE, inst);
13932 do_vfp_sp_compare_z ();
13933 }
037e8744 13934 else
477330fc
RM		 13935 {
13936 NEON_ENCODE (DOUBLE, inst);
13937 do_vfp_dp_rd ();
13938 }
037e8744
JB		 13939 }
13940 do_vfp_cond_or_thumb ();
13941}
13942
13943static void
13944nsyn_insert_sp (void)
13945{
13946 inst.operands[1] = inst.operands[0];
13947 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 13948 inst.operands[0].reg = REG_SP;
037e8744
JB		 13949 inst.operands[0].isreg = 1;
13950 inst.operands[0].writeback = 1;
13951 inst.operands[0].present = 1;
13952}
13953
13954static void
13955do_vfp_nsyn_push (void)
13956{
13957 nsyn_insert_sp ();
13958 if (inst.operands[1].issingle)
13959 do_vfp_nsyn_opcode ("fstmdbs");
13960 else
13961 do_vfp_nsyn_opcode ("fstmdbd");
13962}
13963
13964static void
13965do_vfp_nsyn_pop (void)
13966{
13967 nsyn_insert_sp ();
13968 if (inst.operands[1].issingle)
22b5b651 13969 do_vfp_nsyn_opcode ("fldmias");
037e8744 13970 else
22b5b651 13971 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB		 13972}
13973
13974/* Fix up Neon data-processing instructions, ORing in the correct bits for
13975 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13976
88714cb8
DG		 13977static void
13978neon_dp_fixup (struct arm_it* insn)
037e8744 13979{
88714cb8
DG		 13980 unsigned int i = insn->instruction;
13981 insn->is_neon = 1;
13982
037e8744
JB		 13983 if (thumb_mode)
13984 {
13985 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13986 if (i & (1 << 24))
477330fc 13987 i |= 1 << 28;
5f4273c7 13988
037e8744 13989 i &= ~(1 << 24);
5f4273c7 13990
037e8744
JB		 13991 i |= 0xef000000;
13992 }
13993 else
13994 i |= 0xf2000000;
5f4273c7 13995
88714cb8 13996 insn->instruction = i;
037e8744
JB		 13997}
13998
13999/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14000 (0, 1, 2, 3). */
14001
14002static unsigned
14003neon_logbits (unsigned x)
14004{
14005 return ffs (x) - 4;
14006}
14007
14008#define LOW4(R) ((R) & 0xf)
14009#define HI1(R) (((R) >> 4) & 1)
14010
14011/* Encode insns with bit pattern:
14012
14013 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14014 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 14015
037e8744
JB		 14016 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14017 different meaning for some instruction. */
14018
14019static void
14020neon_three_same (int isquad, int ubit, int size)
14021{
14022 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14023 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14024 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14025 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14026 inst.instruction |= LOW4 (inst.operands[2].reg);
14027 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14028 inst.instruction |= (isquad != 0) << 6;
14029 inst.instruction |= (ubit != 0) << 24;
14030 if (size != -1)
14031 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 14032
88714cb8 14033 neon_dp_fixup (&inst);
037e8744
JB		 14034}
14035
14036/* Encode instructions of the form:
14037
14038 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14039 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB		 14040
14041 Don't write size if SIZE == -1. */
14042
14043static void
14044neon_two_same (int qbit, int ubit, int size)
14045{
14046 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14047 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14048 inst.instruction |= LOW4 (inst.operands[1].reg);
14049 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14050 inst.instruction |= (qbit != 0) << 6;
14051 inst.instruction |= (ubit != 0) << 24;
14052
14053 if (size != -1)
14054 inst.instruction |= neon_logbits (size) << 18;
14055
88714cb8 14056 neon_dp_fixup (&inst);
5287ad62
JB		 14057}
14058
14059/* Neon instruction encoders, in approximate order of appearance. */
14060
14061static void
14062do_neon_dyadic_i_su (void)
14063{
037e8744 14064 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14065 struct neon_type_el et = neon_check_type (3, rs,
14066 N_EQK, N_EQK, N_SU_32 | N_KEY);
037e8744 14067 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14068}
14069
14070static void
14071do_neon_dyadic_i64_su (void)
14072{
037e8744 14073 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14074 struct neon_type_el et = neon_check_type (3, rs,
14075 N_EQK, N_EQK, N_SU_ALL | N_KEY);
037e8744 14076 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14077}
14078
14079static void
14080neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 14081 unsigned immbits)
5287ad62
JB		 14082{
14083 unsigned size = et.size >> 3;
14084 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14085 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14086 inst.instruction |= LOW4 (inst.operands[1].reg);
14087 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14088 inst.instruction |= (isquad != 0) << 6;
14089 inst.instruction |= immbits << 16;
14090 inst.instruction |= (size >> 3) << 7;
14091 inst.instruction |= (size & 0x7) << 19;
14092 if (write_ubit)
14093 inst.instruction |= (uval != 0) << 24;
14094
88714cb8 14095 neon_dp_fixup (&inst);
5287ad62
JB		 14096}
14097
14098static void
14099do_neon_shl_imm (void)
14100{
14101 if (!inst.operands[2].isreg)
14102 {
037e8744 14103 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 14104 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
88714cb8 14105 NEON_ENCODE (IMMED, inst);
037e8744 14106 neon_imm_shift (FALSE, 0, neon_quad (rs), et, inst.operands[2].imm);
5287ad62
JB		 14107 }
14108 else
14109 {
037e8744 14110 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14111 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14112 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB		 14113 unsigned int tmp;
14114
14115 /* VSHL/VQSHL 3-register variants have syntax such as:
477330fc
RM		 14116 vshl.xx Dd, Dm, Dn
14117 whereas other 3-register operations encoded by neon_three_same have
14118 syntax like:
14119 vadd.xx Dd, Dn, Dm
14120 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14121 here. */
627907b7
JB		 14122 tmp = inst.operands[2].reg;
14123 inst.operands[2].reg = inst.operands[1].reg;
14124 inst.operands[1].reg = tmp;
88714cb8 14125 NEON_ENCODE (INTEGER, inst);
037e8744 14126 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14127 }
14128}
14129
14130static void
14131do_neon_qshl_imm (void)
14132{
14133 if (!inst.operands[2].isreg)
14134 {
037e8744 14135 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 14136 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
627907b7 14137
88714cb8 14138 NEON_ENCODE (IMMED, inst);
037e8744 14139 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 14140 inst.operands[2].imm);
5287ad62
JB		 14141 }
14142 else
14143 {
037e8744 14144 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14145 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14146 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB		 14147 unsigned int tmp;
14148
14149 /* See note in do_neon_shl_imm. */
14150 tmp = inst.operands[2].reg;
14151 inst.operands[2].reg = inst.operands[1].reg;
14152 inst.operands[1].reg = tmp;
88714cb8 14153 NEON_ENCODE (INTEGER, inst);
037e8744 14154 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14155 }
14156}
14157
627907b7
JB		 14158static void
14159do_neon_rshl (void)
14160{
14161 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14162 struct neon_type_el et = neon_check_type (3, rs,
14163 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14164 unsigned int tmp;
14165
14166 tmp = inst.operands[2].reg;
14167 inst.operands[2].reg = inst.operands[1].reg;
14168 inst.operands[1].reg = tmp;
14169 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14170}
14171
5287ad62
JB		 14172static int
14173neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
14174{
036dc3f7
PB		 14175 /* Handle .I8 pseudo-instructions. */
14176 if (size == 8)
5287ad62 14177 {
5287ad62 14178 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM		 14179 FIXME is this the intended semantics? There doesn't seem much point in
14180 accepting .I8 if so. */
5287ad62
JB		 14181 immediate |= immediate << 8;
14182 size = 16;
036dc3f7
PB		 14183 }
14184
14185 if (size >= 32)
14186 {
14187 if (immediate == (immediate & 0x000000ff))
14188 {
14189 *immbits = immediate;
14190 return 0x1;
14191 }
14192 else if (immediate == (immediate & 0x0000ff00))
14193 {
14194 *immbits = immediate >> 8;
14195 return 0x3;
14196 }
14197 else if (immediate == (immediate & 0x00ff0000))
14198 {
14199 *immbits = immediate >> 16;
14200 return 0x5;
14201 }
14202 else if (immediate == (immediate & 0xff000000))
14203 {
14204 *immbits = immediate >> 24;
14205 return 0x7;
14206 }
14207 if ((immediate & 0xffff) != (immediate >> 16))
14208 goto bad_immediate;
14209 immediate &= 0xffff;
5287ad62
JB		 14210 }
14211
14212 if (immediate == (immediate & 0x000000ff))
14213 {
14214 *immbits = immediate;
036dc3f7 14215 return 0x9;
5287ad62
JB		 14216 }
14217 else if (immediate == (immediate & 0x0000ff00))
14218 {
14219 *immbits = immediate >> 8;
036dc3f7 14220 return 0xb;
5287ad62
JB		 14221 }
14222
14223 bad_immediate:
dcbf9037 14224 first_error (_("immediate value out of range"));
5287ad62
JB		 14225 return FAIL;
14226}
14227
5287ad62
JB		 14228static void
14229do_neon_logic (void)
14230{
14231 if (inst.operands[2].present && inst.operands[2].isreg)
14232 {
037e8744 14233 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14234 neon_check_type (3, rs, N_IGNORE_TYPE);
14235 /* U bit and size field were set as part of the bitmask. */
88714cb8 14236 NEON_ENCODE (INTEGER, inst);
037e8744 14237 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14238 }
14239 else
14240 {
4316f0d2
DG		 14241 const int three_ops_form = (inst.operands[2].present
14242 && !inst.operands[2].isreg);
14243 const int immoperand = (three_ops_form ? 2 : 1);
14244 enum neon_shape rs = (three_ops_form
14245 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
14246 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
037e8744 14247 struct neon_type_el et = neon_check_type (2, rs,
477330fc 14248 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
21d799b5 14249 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB		 14250 unsigned immbits;
14251 int cmode;
5f4273c7 14252
5287ad62 14253 if (et.type == NT_invtype)
477330fc 14254 return;
5f4273c7 14255
4316f0d2
DG		 14256 if (three_ops_form)
14257 constraint (inst.operands[0].reg != inst.operands[1].reg,
14258 _("first and second operands shall be the same register"));
14259
88714cb8 14260 NEON_ENCODE (IMMED, inst);
5287ad62 14261
4316f0d2 14262 immbits = inst.operands[immoperand].imm;
036dc3f7
PB		 14263 if (et.size == 64)
14264 {
14265 /* .i64 is a pseudo-op, so the immediate must be a repeating
14266 pattern. */
4316f0d2
DG		 14267 if (immbits != (inst.operands[immoperand].regisimm ?
14268 inst.operands[immoperand].reg : 0))
036dc3f7
PB		 14269 {
14270 /* Set immbits to an invalid constant. */
14271 immbits = 0xdeadbeef;
14272 }
14273 }
14274
5287ad62 14275 switch (opcode)
477330fc
RM		 14276 {
14277 case N_MNEM_vbic:
14278 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14279 break;
14280
14281 case N_MNEM_vorr:
14282 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14283 break;
14284
14285 case N_MNEM_vand:
14286 /* Pseudo-instruction for VBIC. */
14287 neon_invert_size (&immbits, 0, et.size);
14288 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14289 break;
14290
14291 case N_MNEM_vorn:
14292 /* Pseudo-instruction for VORR. */
14293 neon_invert_size (&immbits, 0, et.size);
14294 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14295 break;
14296
14297 default:
14298 abort ();
14299 }
5287ad62
JB		 14300
14301 if (cmode == FAIL)
477330fc 14302 return;
5287ad62 14303
037e8744 14304 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14305 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14306 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14307 inst.instruction |= cmode << 8;
14308 neon_write_immbits (immbits);
5f4273c7 14309
88714cb8 14310 neon_dp_fixup (&inst);
5287ad62
JB		 14311 }
14312}
14313
14314static void
14315do_neon_bitfield (void)
14316{
037e8744 14317 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 14318 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 14319 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14320}
14321
14322static void
dcbf9037 14323neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 14324 unsigned destbits)
5287ad62 14325{
037e8744 14326 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 14327 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 14328 types | N_KEY);
5287ad62
JB		 14329 if (et.type == NT_float)
14330 {
88714cb8 14331 NEON_ENCODE (FLOAT, inst);
037e8744 14332 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14333 }
14334 else
14335 {
88714cb8 14336 NEON_ENCODE (INTEGER, inst);
037e8744 14337 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB		 14338 }
14339}
14340
14341static void
14342do_neon_dyadic_if_su (void)
14343{
dcbf9037 14344 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 14345}
14346
14347static void
14348do_neon_dyadic_if_su_d (void)
14349{
14350 /* This version only allow D registers, but that constraint is enforced during
14351 operand parsing so we don't need to do anything extra here. */
dcbf9037 14352 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 14353}
14354
5287ad62
JB		 14355static void
14356do_neon_dyadic_if_i_d (void)
14357{
428e3f1f
PB		 14358 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14359 affected if we specify unsigned args. */
14360 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB		 14361}
14362
037e8744
JB		 14363enum vfp_or_neon_is_neon_bits
14364{
14365 NEON_CHECK_CC = 1,
73924fbc
MGD		 14366 NEON_CHECK_ARCH = 2,
14367 NEON_CHECK_ARCH8 = 4
037e8744
JB		 14368};
14369
14370/* Call this function if an instruction which may have belonged to the VFP or
14371 Neon instruction sets, but turned out to be a Neon instruction (due to the
14372 operand types involved, etc.). We have to check and/or fix-up a couple of
14373 things:
14374
14375 - Make sure the user hasn't attempted to make a Neon instruction
14376 conditional.
14377 - Alter the value in the condition code field if necessary.
14378 - Make sure that the arch supports Neon instructions.
14379
14380 Which of these operations take place depends on bits from enum
14381 vfp_or_neon_is_neon_bits.
14382
14383 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14384 current instruction's condition is COND_ALWAYS, the condition field is
14385 changed to inst.uncond_value. This is necessary because instructions shared
14386 between VFP and Neon may be conditional for the VFP variants only, and the
14387 unconditional Neon version must have, e.g., 0xF in the condition field. */
14388
14389static int
14390vfp_or_neon_is_neon (unsigned check)
14391{
14392 /* Conditions are always legal in Thumb mode (IT blocks). */
14393 if (!thumb_mode && (check & NEON_CHECK_CC))
14394 {
14395 if (inst.cond != COND_ALWAYS)
477330fc
RM		 14396 {
14397 first_error (_(BAD_COND));
14398 return FAIL;
14399 }
037e8744 14400 if (inst.uncond_value != -1)
477330fc 14401 inst.instruction |= inst.uncond_value << 28;
037e8744 14402 }
5f4273c7 14403
037e8744 14404 if ((check & NEON_CHECK_ARCH)
73924fbc
MGD		 14405 && !mark_feature_used (&fpu_neon_ext_v1))
14406 {
14407 first_error (_(BAD_FPU));
14408 return FAIL;
14409 }
14410
14411 if ((check & NEON_CHECK_ARCH8)
14412 && !mark_feature_used (&fpu_neon_ext_armv8))
037e8744
JB		 14413 {
14414 first_error (_(BAD_FPU));
14415 return FAIL;
14416 }
5f4273c7 14417
037e8744
JB		 14418 return SUCCESS;
14419}
14420
5287ad62
JB		 14421static void
14422do_neon_addsub_if_i (void)
14423{
037e8744
JB		 14424 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14425 return;
14426
14427 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14428 return;
14429
5287ad62
JB		 14430 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14431 affected if we specify unsigned args. */
dcbf9037 14432 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB		 14433}
14434
14435/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14436 result to be:
14437 V<op> A,B (A is operand 0, B is operand 2)
14438 to mean:
14439 V<op> A,B,A
14440 not:
14441 V<op> A,B,B
14442 so handle that case specially. */
14443
14444static void
14445neon_exchange_operands (void)
14446{
14447 void *scratch = alloca (sizeof (inst.operands[0]));
14448 if (inst.operands[1].present)
14449 {
14450 /* Swap operands[1] and operands[2]. */
14451 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14452 inst.operands[1] = inst.operands[2];
14453 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14454 }
14455 else
14456 {
14457 inst.operands[1] = inst.operands[2];
14458 inst.operands[2] = inst.operands[0];
14459 }
14460}
14461
14462static void
14463neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14464{
14465 if (inst.operands[2].isreg)
14466 {
14467 if (invert)
477330fc 14468 neon_exchange_operands ();
dcbf9037 14469 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB		 14470 }
14471 else
14472 {
037e8744 14473 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 14474 struct neon_type_el et = neon_check_type (2, rs,
477330fc 14475 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 14476
88714cb8 14477 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 14478 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14479 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14480 inst.instruction |= LOW4 (inst.operands[1].reg);
14481 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14482 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14483 inst.instruction |= (et.type == NT_float) << 10;
14484 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14485
88714cb8 14486 neon_dp_fixup (&inst);
5287ad62
JB		 14487 }
14488}
14489
14490static void
14491do_neon_cmp (void)
14492{
14493 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14494}
14495
14496static void
14497do_neon_cmp_inv (void)
14498{
14499 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14500}
14501
14502static void
14503do_neon_ceq (void)
14504{
14505 neon_compare (N_IF_32, N_IF_32, FALSE);
14506}
14507
14508/* For multiply instructions, we have the possibility of 16-bit or 32-bit
14509 scalars, which are encoded in 5 bits, M : Rm.
14510 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14511 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14512 index in M. */
14513
14514static unsigned
14515neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14516{
dcbf9037
JB		 14517 unsigned regno = NEON_SCALAR_REG (scalar);
14518 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB		 14519
14520 switch (elsize)
14521 {
14522 case 16:
14523 if (regno > 7 || elno > 3)
477330fc 14524 goto bad_scalar;
5287ad62 14525 return regno | (elno << 3);
5f4273c7 14526
5287ad62
JB		 14527 case 32:
14528 if (regno > 15 || elno > 1)
477330fc 14529 goto bad_scalar;
5287ad62
JB		 14530 return regno | (elno << 4);
14531
14532 default:
14533 bad_scalar:
dcbf9037 14534 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB		 14535 }
14536
14537 return 0;
14538}
14539
14540/* Encode multiply / multiply-accumulate scalar instructions. */
14541
14542static void
14543neon_mul_mac (struct neon_type_el et, int ubit)
14544{
dcbf9037
JB		 14545 unsigned scalar;
14546
14547 /* Give a more helpful error message if we have an invalid type. */
14548 if (et.type == NT_invtype)
14549 return;
5f4273c7 14550
dcbf9037 14551 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB		 14552 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14553 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14554 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14555 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14556 inst.instruction |= LOW4 (scalar);
14557 inst.instruction |= HI1 (scalar) << 5;
14558 inst.instruction |= (et.type == NT_float) << 8;
14559 inst.instruction |= neon_logbits (et.size) << 20;
14560 inst.instruction |= (ubit != 0) << 24;
14561
88714cb8 14562 neon_dp_fixup (&inst);
5287ad62
JB		 14563}
14564
14565static void
14566do_neon_mac_maybe_scalar (void)
14567{
037e8744
JB		 14568 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14569 return;
14570
14571 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14572 return;
14573
5287ad62
JB		 14574 if (inst.operands[2].isscalar)
14575 {
037e8744 14576 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 14577 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14578 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
88714cb8 14579 NEON_ENCODE (SCALAR, inst);
037e8744 14580 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 14581 }
14582 else
428e3f1f
PB		 14583 {
14584 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14585 affected if we specify unsigned args. */
14586 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14587 }
5287ad62
JB		 14588}
14589
62f3b8c8
PB		 14590static void
14591do_neon_fmac (void)
14592{
14593 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14594 return;
14595
14596 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14597 return;
14598
14599 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14600}
14601
5287ad62
JB		 14602static void
14603do_neon_tst (void)
14604{
037e8744 14605 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14606 struct neon_type_el et = neon_check_type (3, rs,
14607 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 14608 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 14609}
14610
14611/* VMUL with 3 registers allows the P8 type. The scalar version supports the
14612 same types as the MAC equivalents. The polynomial type for this instruction
14613 is encoded the same as the integer type. */
14614
14615static void
14616do_neon_mul (void)
14617{
037e8744
JB		 14618 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14619 return;
14620
14621 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14622 return;
14623
5287ad62
JB		 14624 if (inst.operands[2].isscalar)
14625 do_neon_mac_maybe_scalar ();
14626 else
dcbf9037 14627 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
5287ad62
JB		 14628}
14629
14630static void
14631do_neon_qdmulh (void)
14632{
14633 if (inst.operands[2].isscalar)
14634 {
037e8744 14635 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 14636 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14637 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 14638 NEON_ENCODE (SCALAR, inst);
037e8744 14639 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 14640 }
14641 else
14642 {
037e8744 14643 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14644 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14645 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 14646 NEON_ENCODE (INTEGER, inst);
5287ad62 14647 /* The U bit (rounding) comes from bit mask. */
037e8744 14648 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 14649 }
14650}
14651
14652static void
14653do_neon_fcmp_absolute (void)
14654{
037e8744 14655 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14656 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14657 /* Size field comes from bit mask. */
037e8744 14658 neon_three_same (neon_quad (rs), 1, -1);
5287ad62
JB		 14659}
14660
14661static void
14662do_neon_fcmp_absolute_inv (void)
14663{
14664 neon_exchange_operands ();
14665 do_neon_fcmp_absolute ();
14666}
14667
14668static void
14669do_neon_step (void)
14670{
037e8744 14671 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14672 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
037e8744 14673 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14674}
14675
14676static void
14677do_neon_abs_neg (void)
14678{
037e8744
JB		 14679 enum neon_shape rs;
14680 struct neon_type_el et;
5f4273c7 14681
037e8744
JB		 14682 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14683 return;
14684
14685 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14686 return;
14687
14688 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14689 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
5f4273c7 14690
5287ad62
JB		 14691 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14692 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14693 inst.instruction |= LOW4 (inst.operands[1].reg);
14694 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14695 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14696 inst.instruction |= (et.type == NT_float) << 10;
14697 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14698
88714cb8 14699 neon_dp_fixup (&inst);
5287ad62
JB		 14700}
14701
14702static void
14703do_neon_sli (void)
14704{
037e8744 14705 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14706 struct neon_type_el et = neon_check_type (2, rs,
14707 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14708 int imm = inst.operands[2].imm;
14709 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 14710 _("immediate out of range for insert"));
037e8744 14711 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14712}
14713
14714static void
14715do_neon_sri (void)
14716{
037e8744 14717 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14718 struct neon_type_el et = neon_check_type (2, rs,
14719 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14720 int imm = inst.operands[2].imm;
14721 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14722 _("immediate out of range for insert"));
037e8744 14723 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB		 14724}
14725
14726static void
14727do_neon_qshlu_imm (void)
14728{
037e8744 14729 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14730 struct neon_type_el et = neon_check_type (2, rs,
14731 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14732 int imm = inst.operands[2].imm;
14733 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 14734 _("immediate out of range for shift"));
5287ad62
JB		 14735 /* Only encodes the 'U present' variant of the instruction.
14736 In this case, signed types have OP (bit 8) set to 0.
14737 Unsigned types have OP set to 1. */
14738 inst.instruction |= (et.type == NT_unsigned) << 8;
14739 /* The rest of the bits are the same as other immediate shifts. */
037e8744 14740 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14741}
14742
14743static void
14744do_neon_qmovn (void)
14745{
14746 struct neon_type_el et = neon_check_type (2, NS_DQ,
14747 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14748 /* Saturating move where operands can be signed or unsigned, and the
14749 destination has the same signedness. */
88714cb8 14750 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14751 if (et.type == NT_unsigned)
14752 inst.instruction |= 0xc0;
14753 else
14754 inst.instruction |= 0x80;
14755 neon_two_same (0, 1, et.size / 2);
14756}
14757
14758static void
14759do_neon_qmovun (void)
14760{
14761 struct neon_type_el et = neon_check_type (2, NS_DQ,
14762 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14763 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 14764 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14765 neon_two_same (0, 1, et.size / 2);
14766}
14767
14768static void
14769do_neon_rshift_sat_narrow (void)
14770{
14771 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14772 or unsigned. If operands are unsigned, results must also be unsigned. */
14773 struct neon_type_el et = neon_check_type (2, NS_DQI,
14774 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14775 int imm = inst.operands[2].imm;
14776 /* This gets the bounds check, size encoding and immediate bits calculation
14777 right. */
14778 et.size /= 2;
5f4273c7 14779
5287ad62
JB		 14780 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14781 VQMOVN.I<size> <Dd>, <Qm>. */
14782 if (imm == 0)
14783 {
14784 inst.operands[2].present = 0;
14785 inst.instruction = N_MNEM_vqmovn;
14786 do_neon_qmovn ();
14787 return;
14788 }
5f4273c7 14789
5287ad62 14790 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14791 _("immediate out of range"));
5287ad62
JB		 14792 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14793}
14794
14795static void
14796do_neon_rshift_sat_narrow_u (void)
14797{
14798 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14799 or unsigned. If operands are unsigned, results must also be unsigned. */
14800 struct neon_type_el et = neon_check_type (2, NS_DQI,
14801 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14802 int imm = inst.operands[2].imm;
14803 /* This gets the bounds check, size encoding and immediate bits calculation
14804 right. */
14805 et.size /= 2;
14806
14807 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14808 VQMOVUN.I<size> <Dd>, <Qm>. */
14809 if (imm == 0)
14810 {
14811 inst.operands[2].present = 0;
14812 inst.instruction = N_MNEM_vqmovun;
14813 do_neon_qmovun ();
14814 return;
14815 }
14816
14817 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14818 _("immediate out of range"));
5287ad62
JB		 14819 /* FIXME: The manual is kind of unclear about what value U should have in
14820 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14821 must be 1. */
14822 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14823}
14824
14825static void
14826do_neon_movn (void)
14827{
14828 struct neon_type_el et = neon_check_type (2, NS_DQ,
14829 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 14830 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14831 neon_two_same (0, 1, et.size / 2);
14832}
14833
14834static void
14835do_neon_rshift_narrow (void)
14836{
14837 struct neon_type_el et = neon_check_type (2, NS_DQI,
14838 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14839 int imm = inst.operands[2].imm;
14840 /* This gets the bounds check, size encoding and immediate bits calculation
14841 right. */
14842 et.size /= 2;
5f4273c7 14843
5287ad62
JB		 14844 /* If immediate is zero then we are a pseudo-instruction for
14845 VMOVN.I<size> <Dd>, <Qm> */
14846 if (imm == 0)
14847 {
14848 inst.operands[2].present = 0;
14849 inst.instruction = N_MNEM_vmovn;
14850 do_neon_movn ();
14851 return;
14852 }
5f4273c7 14853
5287ad62 14854 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14855 _("immediate out of range for narrowing operation"));
5287ad62
JB		 14856 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14857}
14858
14859static void
14860do_neon_shll (void)
14861{
14862 /* FIXME: Type checking when lengthening. */
14863 struct neon_type_el et = neon_check_type (2, NS_QDI,
14864 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14865 unsigned imm = inst.operands[2].imm;
14866
14867 if (imm == et.size)
14868 {
14869 /* Maximum shift variant. */
88714cb8 14870 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14871 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14872 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14873 inst.instruction |= LOW4 (inst.operands[1].reg);
14874 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14875 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14876
88714cb8 14877 neon_dp_fixup (&inst);
5287ad62
JB		 14878 }
14879 else
14880 {
14881 /* A more-specific type check for non-max versions. */
14882 et = neon_check_type (2, NS_QDI,
477330fc 14883 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 14884 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 14885 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14886 }
14887}
14888
037e8744 14889/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB		 14890 the current instruction is. */
14891
6b9a8b67
MGD		 14892#define CVT_FLAVOUR_VAR \
14893 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14894 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14895 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14896 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14897 /* Half-precision conversions. */ \
14898 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14899 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14900 /* VFP instructions. */ \
14901 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14902 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14903 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14904 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14905 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14906 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14907 /* VFP instructions with bitshift. */ \
14908 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14909 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14910 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14911 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14912 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14913 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14914 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14915 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14916
14917#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14918 neon_cvt_flavour_##C,
14919
14920/* The different types of conversions we can do. */
14921enum neon_cvt_flavour
14922{
14923 CVT_FLAVOUR_VAR
14924 neon_cvt_flavour_invalid,
14925 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14926};
14927
14928#undef CVT_VAR
14929
14930static enum neon_cvt_flavour
14931get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 14932{
6b9a8b67
MGD		 14933#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14934 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14935 if (et.type != NT_invtype) \
14936 { \
14937 inst.error = NULL; \
14938 return (neon_cvt_flavour_##C); \
5287ad62 14939 }
6b9a8b67 14940
5287ad62 14941 struct neon_type_el et;
037e8744 14942 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 14943 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB		 14944 /* The instruction versions which take an immediate take one register
14945 argument, which is extended to the width of the full register. Thus the
14946 "source" and "destination" registers must have the same width. Hack that
14947 here by making the size equal to the key (wider, in this case) operand. */
14948 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 14949
6b9a8b67
MGD		 14950 CVT_FLAVOUR_VAR;
14951
14952 return neon_cvt_flavour_invalid;
5287ad62
JB		 14953#undef CVT_VAR
14954}
14955
7e8e6784
MGD		 14956enum neon_cvt_mode
14957{
14958 neon_cvt_mode_a,
14959 neon_cvt_mode_n,
14960 neon_cvt_mode_p,
14961 neon_cvt_mode_m,
14962 neon_cvt_mode_z,
30bdf752
MGD		 14963 neon_cvt_mode_x,
14964 neon_cvt_mode_r
7e8e6784
MGD		 14965};
14966
037e8744
JB		 14967/* Neon-syntax VFP conversions. */
14968
5287ad62 14969static void
6b9a8b67 14970do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 14971{
037e8744 14972 const char *opname = 0;
5f4273c7 14973
037e8744 14974 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
5287ad62 14975 {
037e8744
JB		 14976 /* Conversions with immediate bitshift. */
14977 const char *enc[] =
477330fc 14978 {
6b9a8b67
MGD		 14979#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14980 CVT_FLAVOUR_VAR
14981 NULL
14982#undef CVT_VAR
477330fc 14983 };
037e8744 14984
6b9a8b67 14985 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM		 14986 {
14987 opname = enc[flavour];
14988 constraint (inst.operands[0].reg != inst.operands[1].reg,
14989 _("operands 0 and 1 must be the same register"));
14990 inst.operands[1] = inst.operands[2];
14991 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
14992 }
5287ad62
JB		 14993 }
14994 else
14995 {
037e8744
JB		 14996 /* Conversions without bitshift. */
14997 const char *enc[] =
477330fc 14998 {
6b9a8b67
MGD		 14999#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15000 CVT_FLAVOUR_VAR
15001 NULL
15002#undef CVT_VAR
477330fc 15003 };
037e8744 15004
6b9a8b67 15005 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 15006 opname = enc[flavour];
037e8744
JB		 15007 }
15008
15009 if (opname)
15010 do_vfp_nsyn_opcode (opname);
15011}
15012
15013static void
15014do_vfp_nsyn_cvtz (void)
15015{
15016 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
6b9a8b67 15017 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB		 15018 const char *enc[] =
15019 {
6b9a8b67
MGD		 15020#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15021 CVT_FLAVOUR_VAR
15022 NULL
15023#undef CVT_VAR
037e8744
JB		 15024 };
15025
6b9a8b67 15026 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB		 15027 do_vfp_nsyn_opcode (enc[flavour]);
15028}
f31fef98 15029
037e8744 15030static void
bacebabc 15031do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD		 15032 enum neon_cvt_mode mode)
15033{
15034 int sz, op;
15035 int rm;
15036
a715796b
TG		 15037 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15038 D register operands. */
15039 if (flavour == neon_cvt_flavour_s32_f64
15040 || flavour == neon_cvt_flavour_u32_f64)
15041 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15042 _(BAD_FPU));
15043
7e8e6784
MGD		 15044 set_it_insn_type (OUTSIDE_IT_INSN);
15045
15046 switch (flavour)
15047 {
15048 case neon_cvt_flavour_s32_f64:
15049 sz = 1;
827f64ff 15050 op = 1;
7e8e6784
MGD		 15051 break;
15052 case neon_cvt_flavour_s32_f32:
15053 sz = 0;
15054 op = 1;
15055 break;
15056 case neon_cvt_flavour_u32_f64:
15057 sz = 1;
15058 op = 0;
15059 break;
15060 case neon_cvt_flavour_u32_f32:
15061 sz = 0;
15062 op = 0;
15063 break;
15064 default:
15065 first_error (_("invalid instruction shape"));
15066 return;
15067 }
15068
15069 switch (mode)
15070 {
15071 case neon_cvt_mode_a: rm = 0; break;
15072 case neon_cvt_mode_n: rm = 1; break;
15073 case neon_cvt_mode_p: rm = 2; break;
15074 case neon_cvt_mode_m: rm = 3; break;
15075 default: first_error (_("invalid rounding mode")); return;
15076 }
15077
15078 NEON_ENCODE (FPV8, inst);
15079 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
15080 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
15081 inst.instruction |= sz << 8;
15082 inst.instruction |= op << 7;
15083 inst.instruction |= rm << 16;
15084 inst.instruction |= 0xf0000000;
15085 inst.is_neon = TRUE;
15086}
15087
15088static void
15089do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB		 15090{
15091 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
8e79c3df 15092 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
6b9a8b67 15093 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 15094
e3e535bc 15095 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 15096 if (mode == neon_cvt_mode_z
e3e535bc 15097 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
bacebabc
RM		 15098 && (flavour == neon_cvt_flavour_s32_f32
15099 || flavour == neon_cvt_flavour_u32_f32
15100 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 15101 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC		 15102 && (rs == NS_FD || rs == NS_FF))
15103 {
15104 do_vfp_nsyn_cvtz ();
15105 return;
15106 }
15107
037e8744 15108 /* VFP rather than Neon conversions. */
6b9a8b67 15109 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 15110 {
7e8e6784
MGD		 15111 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15112 do_vfp_nsyn_cvt (rs, flavour);
15113 else
15114 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15115
037e8744
JB		 15116 return;
15117 }
15118
15119 switch (rs)
15120 {
15121 case NS_DDI:
15122 case NS_QQI:
15123 {
477330fc
RM		 15124 unsigned immbits;
15125 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
35997600 15126
477330fc
RM		 15127 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15128 return;
037e8744 15129
477330fc
RM		 15130 /* Fixed-point conversion with #0 immediate is encoded as an
15131 integer conversion. */
15132 if (inst.operands[2].present && inst.operands[2].imm == 0)
15133 goto int_encode;
35997600 15134 immbits = 32 - inst.operands[2].imm;
477330fc
RM		 15135 NEON_ENCODE (IMMED, inst);
15136 if (flavour != neon_cvt_flavour_invalid)
15137 inst.instruction |= enctab[flavour];
15138 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15139 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15140 inst.instruction |= LOW4 (inst.operands[1].reg);
15141 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15142 inst.instruction |= neon_quad (rs) << 6;
15143 inst.instruction |= 1 << 21;
15144 inst.instruction |= immbits << 16;
15145
15146 neon_dp_fixup (&inst);
037e8744
JB		 15147 }
15148 break;
15149
15150 case NS_DD:
15151 case NS_QQ:
7e8e6784
MGD		 15152 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
15153 {
15154 NEON_ENCODE (FLOAT, inst);
15155 set_it_insn_type (OUTSIDE_IT_INSN);
15156
15157 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15158 return;
15159
15160 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15161 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15162 inst.instruction |= LOW4 (inst.operands[1].reg);
15163 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15164 inst.instruction |= neon_quad (rs) << 6;
15165 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
15166 inst.instruction |= mode << 8;
15167 if (thumb_mode)
15168 inst.instruction |= 0xfc000000;
15169 else
15170 inst.instruction |= 0xf0000000;
15171 }
15172 else
15173 {
037e8744 15174 int_encode:
7e8e6784
MGD		 15175 {
15176 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
037e8744 15177
7e8e6784 15178 NEON_ENCODE (INTEGER, inst);
037e8744 15179
7e8e6784
MGD		 15180 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15181 return;
037e8744 15182
7e8e6784
MGD		 15183 if (flavour != neon_cvt_flavour_invalid)
15184 inst.instruction |= enctab[flavour];
037e8744 15185
7e8e6784
MGD		 15186 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15187 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15188 inst.instruction |= LOW4 (inst.operands[1].reg);
15189 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15190 inst.instruction |= neon_quad (rs) << 6;
15191 inst.instruction |= 2 << 18;
037e8744 15192
7e8e6784
MGD		 15193 neon_dp_fixup (&inst);
15194 }
15195 }
15196 break;
037e8744 15197
8e79c3df
CM		 15198 /* Half-precision conversions for Advanced SIMD -- neon. */
15199 case NS_QD:
15200 case NS_DQ:
15201
15202 if ((rs == NS_DQ)
15203 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
15204 {
15205 as_bad (_("operand size must match register width"));
15206 break;
15207 }
15208
15209 if ((rs == NS_QD)
15210 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
15211 {
15212 as_bad (_("operand size must match register width"));
15213 break;
15214 }
15215
15216 if (rs == NS_DQ)
477330fc 15217 inst.instruction = 0x3b60600;
8e79c3df
CM		 15218 else
15219 inst.instruction = 0x3b60700;
15220
15221 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15222 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15223 inst.instruction |= LOW4 (inst.operands[1].reg);
15224 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 15225 neon_dp_fixup (&inst);
8e79c3df
CM		 15226 break;
15227
037e8744
JB		 15228 default:
15229 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD		 15230 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15231 do_vfp_nsyn_cvt (rs, flavour);
15232 else
15233 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 15234 }
5287ad62
JB		 15235}
15236
e3e535bc
NC		 15237static void
15238do_neon_cvtr (void)
15239{
7e8e6784 15240 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC		 15241}
15242
15243static void
15244do_neon_cvt (void)
15245{
7e8e6784
MGD		 15246 do_neon_cvt_1 (neon_cvt_mode_z);
15247}
15248
15249static void
15250do_neon_cvta (void)
15251{
15252 do_neon_cvt_1 (neon_cvt_mode_a);
15253}
15254
15255static void
15256do_neon_cvtn (void)
15257{
15258 do_neon_cvt_1 (neon_cvt_mode_n);
15259}
15260
15261static void
15262do_neon_cvtp (void)
15263{
15264 do_neon_cvt_1 (neon_cvt_mode_p);
15265}
15266
15267static void
15268do_neon_cvtm (void)
15269{
15270 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC		 15271}
15272
8e79c3df 15273static void
c70a8987 15274do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 15275{
c70a8987
MGD		 15276 if (is_double)
15277 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 15278
c70a8987
MGD		 15279 encode_arm_vfp_reg (inst.operands[0].reg,
15280 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
15281 encode_arm_vfp_reg (inst.operands[1].reg,
15282 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
15283 inst.instruction |= to ? 0x10000 : 0;
15284 inst.instruction |= t ? 0x80 : 0;
15285 inst.instruction |= is_double ? 0x100 : 0;
15286 do_vfp_cond_or_thumb ();
15287}
8e79c3df 15288
c70a8987
MGD		 15289static void
15290do_neon_cvttb_1 (bfd_boolean t)
15291{
15292 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
8e79c3df 15293
c70a8987
MGD		 15294 if (rs == NS_NULL)
15295 return;
15296 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
15297 {
15298 inst.error = NULL;
15299 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
15300 }
15301 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
15302 {
15303 inst.error = NULL;
15304 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
15305 }
15306 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
15307 {
a715796b
TG		 15308 /* The VCVTB and VCVTT instructions with D-register operands
15309 don't work for SP only targets. */
15310 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15311 _(BAD_FPU));
15312
c70a8987
MGD		 15313 inst.error = NULL;
15314 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
15315 }
15316 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
15317 {
a715796b
TG		 15318 /* The VCVTB and VCVTT instructions with D-register operands
15319 don't work for SP only targets. */
15320 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15321 _(BAD_FPU));
15322
c70a8987
MGD		 15323 inst.error = NULL;
15324 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
15325 }
15326 else
15327 return;
15328}
15329
15330static void
15331do_neon_cvtb (void)
15332{
15333 do_neon_cvttb_1 (FALSE);
8e79c3df
CM		 15334}
15335
15336
15337static void
15338do_neon_cvtt (void)
15339{
c70a8987 15340 do_neon_cvttb_1 (TRUE);
8e79c3df
CM		 15341}
15342
5287ad62
JB		 15343static void
15344neon_move_immediate (void)
15345{
037e8744
JB		 15346 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
15347 struct neon_type_el et = neon_check_type (2, rs,
15348 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 15349 unsigned immlo, immhi = 0, immbits;
c96612cc 15350 int op, cmode, float_p;
5287ad62 15351
037e8744 15352 constraint (et.type == NT_invtype,
477330fc 15353 _("operand size must be specified for immediate VMOV"));
037e8744 15354
5287ad62
JB		 15355 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15356 op = (inst.instruction & (1 << 5)) != 0;
15357
15358 immlo = inst.operands[1].imm;
15359 if (inst.operands[1].regisimm)
15360 immhi = inst.operands[1].reg;
15361
15362 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 15363 _("immediate has bits set outside the operand size"));
5287ad62 15364
c96612cc
JB		 15365 float_p = inst.operands[1].immisfloat;
15366
15367 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 15368 et.size, et.type)) == FAIL)
5287ad62
JB		 15369 {
15370 /* Invert relevant bits only. */
15371 neon_invert_size (&immlo, &immhi, et.size);
15372 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM		 15373 with one or the other; those cases are caught by
15374 neon_cmode_for_move_imm. */
5287ad62 15375 op = !op;
c96612cc
JB		 15376 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15377 &op, et.size, et.type)) == FAIL)
477330fc
RM		 15378 {
15379 first_error (_("immediate out of range"));
15380 return;
15381 }
5287ad62
JB		 15382 }
15383
15384 inst.instruction &= ~(1 << 5);
15385 inst.instruction |= op << 5;
15386
15387 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15388 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 15389 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15390 inst.instruction |= cmode << 8;
15391
15392 neon_write_immbits (immbits);
15393}
15394
15395static void
15396do_neon_mvn (void)
15397{
15398 if (inst.operands[1].isreg)
15399 {
037e8744 15400 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 15401
88714cb8 15402 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 15403 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15404 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15405 inst.instruction |= LOW4 (inst.operands[1].reg);
15406 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 15407 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15408 }
15409 else
15410 {
88714cb8 15411 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 15412 neon_move_immediate ();
15413 }
15414
88714cb8 15415 neon_dp_fixup (&inst);
5287ad62
JB		 15416}
15417
15418/* Encode instructions of form:
15419
15420 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 15421 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB		 15422
15423static void
15424neon_mixed_length (struct neon_type_el et, unsigned size)
15425{
15426 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15427 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15428 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15429 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15430 inst.instruction |= LOW4 (inst.operands[2].reg);
15431 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15432 inst.instruction |= (et.type == NT_unsigned) << 24;
15433 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 15434
88714cb8 15435 neon_dp_fixup (&inst);
5287ad62
JB		 15436}
15437
15438static void
15439do_neon_dyadic_long (void)
15440{
15441 /* FIXME: Type checking for lengthening op. */
15442 struct neon_type_el et = neon_check_type (3, NS_QDD,
15443 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15444 neon_mixed_length (et, et.size);
15445}
15446
15447static void
15448do_neon_abal (void)
15449{
15450 struct neon_type_el et = neon_check_type (3, NS_QDD,
15451 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15452 neon_mixed_length (et, et.size);
15453}
15454
15455static void
15456neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15457{
15458 if (inst.operands[2].isscalar)
15459 {
dcbf9037 15460 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 15461 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 15462 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 15463 neon_mul_mac (et, et.type == NT_unsigned);
15464 }
15465 else
15466 {
15467 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 15468 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 15469 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 15470 neon_mixed_length (et, et.size);
15471 }
15472}
15473
15474static void
15475do_neon_mac_maybe_scalar_long (void)
15476{
15477 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15478}
15479
15480static void
15481do_neon_dyadic_wide (void)
15482{
15483 struct neon_type_el et = neon_check_type (3, NS_QQD,
15484 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15485 neon_mixed_length (et, et.size);
15486}
15487
15488static void
15489do_neon_dyadic_narrow (void)
15490{
15491 struct neon_type_el et = neon_check_type (3, NS_QDD,
15492 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB		 15493 /* Operand sign is unimportant, and the U bit is part of the opcode,
15494 so force the operand type to integer. */
15495 et.type = NT_integer;
5287ad62
JB		 15496 neon_mixed_length (et, et.size / 2);
15497}
15498
15499static void
15500do_neon_mul_sat_scalar_long (void)
15501{
15502 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15503}
15504
15505static void
15506do_neon_vmull (void)
15507{
15508 if (inst.operands[2].isscalar)
15509 do_neon_mac_maybe_scalar_long ();
15510 else
15511 {
15512 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 15513 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 15514
5287ad62 15515 if (et.type == NT_poly)
477330fc 15516 NEON_ENCODE (POLY, inst);
5287ad62 15517 else
477330fc 15518 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD		 15519
15520 /* For polynomial encoding the U bit must be zero, and the size must
15521 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15522 obviously, as 0b10). */
15523 if (et.size == 64)
15524 {
15525 /* Check we're on the correct architecture. */
15526 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15527 inst.error =
15528 _("Instruction form not available on this architecture.");
15529
15530 et.size = 32;
15531 }
15532
5287ad62
JB		 15533 neon_mixed_length (et, et.size);
15534 }
15535}
15536
15537static void
15538do_neon_ext (void)
15539{
037e8744 15540 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB		 15541 struct neon_type_el et = neon_check_type (3, rs,
15542 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15543 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC		 15544
15545 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15546 _("shift out of range"));
5287ad62
JB		 15547 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15548 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15549 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15550 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15551 inst.instruction |= LOW4 (inst.operands[2].reg);
15552 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 15553 inst.instruction |= neon_quad (rs) << 6;
5287ad62 15554 inst.instruction |= imm << 8;
5f4273c7 15555
88714cb8 15556 neon_dp_fixup (&inst);
5287ad62
JB		 15557}
15558
15559static void
15560do_neon_rev (void)
15561{
037e8744 15562 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15563 struct neon_type_el et = neon_check_type (2, rs,
15564 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15565 unsigned op = (inst.instruction >> 7) & 3;
15566 /* N (width of reversed regions) is encoded as part of the bitmask. We
15567 extract it here to check the elements to be reversed are smaller.
15568 Otherwise we'd get a reserved instruction. */
15569 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
9c2799c2 15570 gas_assert (elsize != 0);
5287ad62 15571 constraint (et.size >= elsize,
477330fc 15572 _("elements must be smaller than reversal region"));
037e8744 15573 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15574}
15575
15576static void
15577do_neon_dup (void)
15578{
15579 if (inst.operands[1].isscalar)
15580 {
037e8744 15581 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 15582 struct neon_type_el et = neon_check_type (2, rs,
477330fc 15583 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 15584 unsigned sizebits = et.size >> 3;
dcbf9037 15585 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 15586 int logsize = neon_logbits (et.size);
dcbf9037 15587 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB		 15588
15589 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 15590 return;
037e8744 15591
88714cb8 15592 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 15593 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15594 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15595 inst.instruction |= LOW4 (dm);
15596 inst.instruction |= HI1 (dm) << 5;
037e8744 15597 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15598 inst.instruction |= x << 17;
15599 inst.instruction |= sizebits << 16;
5f4273c7 15600
88714cb8 15601 neon_dp_fixup (&inst);
5287ad62
JB		 15602 }
15603 else
15604 {
037e8744
JB		 15605 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15606 struct neon_type_el et = neon_check_type (2, rs,
477330fc 15607 N_8 | N_16 | N_32 | N_KEY, N_EQK);
5287ad62 15608 /* Duplicate ARM register to lanes of vector. */
88714cb8 15609 NEON_ENCODE (ARMREG, inst);
5287ad62 15610 switch (et.size)
477330fc
RM		 15611 {
15612 case 8: inst.instruction |= 0x400000; break;
15613 case 16: inst.instruction |= 0x000020; break;
15614 case 32: inst.instruction |= 0x000000; break;
15615 default: break;
15616 }
5287ad62
JB		 15617 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15618 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15619 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 15620 inst.instruction |= neon_quad (rs) << 21;
5287ad62 15621 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 15622 variants, except for the condition field. */
037e8744 15623 do_vfp_cond_or_thumb ();
5287ad62
JB		 15624 }
15625}
15626
15627/* VMOV has particularly many variations. It can be one of:
15628 0. VMOV<c><q> <Qd>, <Qm>
15629 1. VMOV<c><q> <Dd>, <Dm>
15630 (Register operations, which are VORR with Rm = Rn.)
15631 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15632 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15633 (Immediate loads.)
15634 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15635 (ARM register to scalar.)
15636 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15637 (Two ARM registers to vector.)
15638 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15639 (Scalar to ARM register.)
15640 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15641 (Vector to two ARM registers.)
037e8744
JB		 15642 8. VMOV.F32 <Sd>, <Sm>
15643 9. VMOV.F64 <Dd>, <Dm>
15644 (VFP register moves.)
15645 10. VMOV.F32 <Sd>, #imm
15646 11. VMOV.F64 <Dd>, #imm
15647 (VFP float immediate load.)
15648 12. VMOV <Rd>, <Sm>
15649 (VFP single to ARM reg.)
15650 13. VMOV <Sd>, <Rm>
15651 (ARM reg to VFP single.)
15652 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15653 (Two ARM regs to two VFP singles.)
15654 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15655 (Two VFP singles to two ARM regs.)
5f4273c7 15656
037e8744
JB		 15657 These cases can be disambiguated using neon_select_shape, except cases 1/9
15658 and 3/11 which depend on the operand type too.
5f4273c7 15659
5287ad62 15660 All the encoded bits are hardcoded by this function.
5f4273c7 15661
b7fc2769
JB		 15662 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15663 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 15664
5287ad62 15665 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 15666 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB		 15667
15668static void
15669do_neon_mov (void)
15670{
037e8744
JB		 15671 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15672 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15673 NS_NULL);
15674 struct neon_type_el et;
15675 const char *ldconst = 0;
5287ad62 15676
037e8744 15677 switch (rs)
5287ad62 15678 {
037e8744
JB		 15679 case NS_DD: /* case 1/9. */
15680 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15681 /* It is not an error here if no type is given. */
15682 inst.error = NULL;
15683 if (et.type == NT_float && et.size == 64)
477330fc
RM		 15684 {
15685 do_vfp_nsyn_opcode ("fcpyd");
15686 break;
15687 }
037e8744 15688 /* fall through. */
5287ad62 15689
037e8744
JB		 15690 case NS_QQ: /* case 0/1. */
15691 {
477330fc
RM		 15692 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15693 return;
15694 /* The architecture manual I have doesn't explicitly state which
15695 value the U bit should have for register->register moves, but
15696 the equivalent VORR instruction has U = 0, so do that. */
15697 inst.instruction = 0x0200110;
15698 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15699 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15700 inst.instruction |= LOW4 (inst.operands[1].reg);
15701 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15702 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15703 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15704 inst.instruction |= neon_quad (rs) << 6;
15705
15706 neon_dp_fixup (&inst);
037e8744
JB		 15707 }
15708 break;
5f4273c7 15709
037e8744
JB		 15710 case NS_DI: /* case 3/11. */
15711 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15712 inst.error = NULL;
15713 if (et.type == NT_float && et.size == 64)
477330fc
RM		 15714 {
15715 /* case 11 (fconstd). */
15716 ldconst = "fconstd";
15717 goto encode_fconstd;
15718 }
037e8744
JB		 15719 /* fall through. */
15720
15721 case NS_QI: /* case 2/3. */
15722 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
477330fc 15723 return;
037e8744
JB		 15724 inst.instruction = 0x0800010;
15725 neon_move_immediate ();
88714cb8 15726 neon_dp_fixup (&inst);
5287ad62 15727 break;
5f4273c7 15728
037e8744
JB		 15729 case NS_SR: /* case 4. */
15730 {
477330fc
RM		 15731 unsigned bcdebits = 0;
15732 int logsize;
15733 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15734 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 15735
05ac0ffb
JB		 15736 /* .<size> is optional here, defaulting to .32. */
15737 if (inst.vectype.elems == 0
15738 && inst.operands[0].vectype.type == NT_invtype
15739 && inst.operands[1].vectype.type == NT_invtype)
15740 {
15741 inst.vectype.el[0].type = NT_untyped;
15742 inst.vectype.el[0].size = 32;
15743 inst.vectype.elems = 1;
15744 }
15745
477330fc
RM		 15746 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15747 logsize = neon_logbits (et.size);
15748
15749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15750 _(BAD_FPU));
15751 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15752 && et.size != 32, _(BAD_FPU));
15753 constraint (et.type == NT_invtype, _("bad type for scalar"));
15754 constraint (x >= 64 / et.size, _("scalar index out of range"));
15755
15756 switch (et.size)
15757 {
15758 case 8: bcdebits = 0x8; break;
15759 case 16: bcdebits = 0x1; break;
15760 case 32: bcdebits = 0x0; break;
15761 default: ;
15762 }
15763
15764 bcdebits |= x << logsize;
15765
15766 inst.instruction = 0xe000b10;
15767 do_vfp_cond_or_thumb ();
15768 inst.instruction |= LOW4 (dn) << 16;
15769 inst.instruction |= HI1 (dn) << 7;
15770 inst.instruction |= inst.operands[1].reg << 12;
15771 inst.instruction |= (bcdebits & 3) << 5;
15772 inst.instruction |= (bcdebits >> 2) << 21;
037e8744
JB		 15773 }
15774 break;
5f4273c7 15775
037e8744 15776 case NS_DRR: /* case 5 (fmdrr). */
b7fc2769 15777 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
477330fc 15778 _(BAD_FPU));
b7fc2769 15779
037e8744
JB		 15780 inst.instruction = 0xc400b10;
15781 do_vfp_cond_or_thumb ();
15782 inst.instruction |= LOW4 (inst.operands[0].reg);
15783 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15784 inst.instruction |= inst.operands[1].reg << 12;
15785 inst.instruction |= inst.operands[2].reg << 16;
15786 break;
5f4273c7 15787
037e8744
JB		 15788 case NS_RS: /* case 6. */
15789 {
477330fc
RM		 15790 unsigned logsize;
15791 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15792 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15793 unsigned abcdebits = 0;
037e8744 15794
05ac0ffb
JB		 15795 /* .<dt> is optional here, defaulting to .32. */
15796 if (inst.vectype.elems == 0
15797 && inst.operands[0].vectype.type == NT_invtype
15798 && inst.operands[1].vectype.type == NT_invtype)
15799 {
15800 inst.vectype.el[0].type = NT_untyped;
15801 inst.vectype.el[0].size = 32;
15802 inst.vectype.elems = 1;
15803 }
15804
91d6fa6a
NC		 15805 et = neon_check_type (2, NS_NULL,
15806 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM		 15807 logsize = neon_logbits (et.size);
15808
15809 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15810 _(BAD_FPU));
15811 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15812 && et.size != 32, _(BAD_FPU));
15813 constraint (et.type == NT_invtype, _("bad type for scalar"));
15814 constraint (x >= 64 / et.size, _("scalar index out of range"));
15815
15816 switch (et.size)
15817 {
15818 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15819 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15820 case 32: abcdebits = 0x00; break;
15821 default: ;
15822 }
15823
15824 abcdebits |= x << logsize;
15825 inst.instruction = 0xe100b10;
15826 do_vfp_cond_or_thumb ();
15827 inst.instruction |= LOW4 (dn) << 16;
15828 inst.instruction |= HI1 (dn) << 7;
15829 inst.instruction |= inst.operands[0].reg << 12;
15830 inst.instruction |= (abcdebits & 3) << 5;
15831 inst.instruction |= (abcdebits >> 2) << 21;
037e8744
JB		 15832 }
15833 break;
5f4273c7 15834
037e8744
JB		 15835 case NS_RRD: /* case 7 (fmrrd). */
15836 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
477330fc 15837 _(BAD_FPU));
037e8744
JB		 15838
15839 inst.instruction = 0xc500b10;
15840 do_vfp_cond_or_thumb ();
15841 inst.instruction |= inst.operands[0].reg << 12;
15842 inst.instruction |= inst.operands[1].reg << 16;
15843 inst.instruction |= LOW4 (inst.operands[2].reg);
15844 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15845 break;
5f4273c7 15846
037e8744
JB		 15847 case NS_FF: /* case 8 (fcpys). */
15848 do_vfp_nsyn_opcode ("fcpys");
15849 break;
5f4273c7 15850
037e8744
JB		 15851 case NS_FI: /* case 10 (fconsts). */
15852 ldconst = "fconsts";
15853 encode_fconstd:
15854 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM		 15855 {
15856 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15857 do_vfp_nsyn_opcode (ldconst);
15858 }
5287ad62 15859 else
477330fc 15860 first_error (_("immediate out of range"));
037e8744 15861 break;
5f4273c7 15862
037e8744
JB		 15863 case NS_RF: /* case 12 (fmrs). */
15864 do_vfp_nsyn_opcode ("fmrs");
15865 break;
5f4273c7 15866
037e8744
JB		 15867 case NS_FR: /* case 13 (fmsr). */
15868 do_vfp_nsyn_opcode ("fmsr");
15869 break;
5f4273c7 15870
037e8744
JB		 15871 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15872 (one of which is a list), but we have parsed four. Do some fiddling to
15873 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15874 expect. */
15875 case NS_RRFF: /* case 14 (fmrrs). */
15876 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 15877 _("VFP registers must be adjacent"));
037e8744
JB		 15878 inst.operands[2].imm = 2;
15879 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15880 do_vfp_nsyn_opcode ("fmrrs");
15881 break;
5f4273c7 15882
037e8744
JB		 15883 case NS_FFRR: /* case 15 (fmsrr). */
15884 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 15885 _("VFP registers must be adjacent"));
037e8744
JB		 15886 inst.operands[1] = inst.operands[2];
15887 inst.operands[2] = inst.operands[3];
15888 inst.operands[0].imm = 2;
15889 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15890 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 15891 break;
5f4273c7 15892
4c261dff
NC		 15893 case NS_NULL:
15894 /* neon_select_shape has determined that the instruction
15895 shape is wrong and has already set the error message. */
15896 break;
15897
5287ad62
JB		 15898 default:
15899 abort ();
15900 }
15901}
15902
15903static void
15904do_neon_rshift_round_imm (void)
15905{
037e8744 15906 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 15907 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15908 int imm = inst.operands[2].imm;
15909
15910 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15911 if (imm == 0)
15912 {
15913 inst.operands[2].present = 0;
15914 do_neon_mov ();
15915 return;
15916 }
15917
15918 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 15919 _("immediate out of range for shift"));
037e8744 15920 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 15921 et.size - imm);
5287ad62
JB		 15922}
15923
15924static void
15925do_neon_movl (void)
15926{
15927 struct neon_type_el et = neon_check_type (2, NS_QD,
15928 N_EQK | N_DBL, N_SU_32 | N_KEY);
15929 unsigned sizebits = et.size >> 3;
15930 inst.instruction |= sizebits << 19;
15931 neon_two_same (0, et.type == NT_unsigned, -1);
15932}
15933
15934static void
15935do_neon_trn (void)
15936{
037e8744 15937 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15938 struct neon_type_el et = neon_check_type (2, rs,
15939 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 15940 NEON_ENCODE (INTEGER, inst);
037e8744 15941 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15942}
15943
15944static void
15945do_neon_zip_uzp (void)
15946{
037e8744 15947 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15948 struct neon_type_el et = neon_check_type (2, rs,
15949 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15950 if (rs == NS_DD && et.size == 32)
15951 {
15952 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15953 inst.instruction = N_MNEM_vtrn;
15954 do_neon_trn ();
15955 return;
15956 }
037e8744 15957 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15958}
15959
15960static void
15961do_neon_sat_abs_neg (void)
15962{
037e8744 15963 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15964 struct neon_type_el et = neon_check_type (2, rs,
15965 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 15966 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15967}
15968
15969static void
15970do_neon_pair_long (void)
15971{
037e8744 15972 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15973 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15974 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15975 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 15976 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15977}
15978
15979static void
15980do_neon_recip_est (void)
15981{
037e8744 15982 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15983 struct neon_type_el et = neon_check_type (2, rs,
15984 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15985 inst.instruction |= (et.type == NT_float) << 8;
037e8744 15986 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15987}
15988
15989static void
15990do_neon_cls (void)
15991{
037e8744 15992 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15993 struct neon_type_el et = neon_check_type (2, rs,
15994 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 15995 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15996}
15997
15998static void
15999do_neon_clz (void)
16000{
037e8744 16001 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 16002 struct neon_type_el et = neon_check_type (2, rs,
16003 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 16004 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 16005}
16006
16007static void
16008do_neon_cnt (void)
16009{
037e8744 16010 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 16011 struct neon_type_el et = neon_check_type (2, rs,
16012 N_EQK | N_INT, N_8 | N_KEY);
037e8744 16013 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 16014}
16015
16016static void
16017do_neon_swp (void)
16018{
037e8744
JB		 16019 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16020 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB		 16021}
16022
16023static void
16024do_neon_tbl_tbx (void)
16025{
16026 unsigned listlenbits;
dcbf9037 16027 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 16028
5287ad62
JB		 16029 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
16030 {
dcbf9037 16031 first_error (_("bad list length for table lookup"));
5287ad62
JB		 16032 return;
16033 }
5f4273c7 16034
5287ad62
JB		 16035 listlenbits = inst.operands[1].imm - 1;
16036 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16037 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16038 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16039 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16040 inst.instruction |= LOW4 (inst.operands[2].reg);
16041 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16042 inst.instruction |= listlenbits << 8;
5f4273c7 16043
88714cb8 16044 neon_dp_fixup (&inst);
5287ad62
JB		 16045}
16046
16047static void
16048do_neon_ldm_stm (void)
16049{
16050 /* P, U and L bits are part of bitmask. */
16051 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
16052 unsigned offsetbits = inst.operands[1].imm * 2;
16053
037e8744
JB		 16054 if (inst.operands[1].issingle)
16055 {
16056 do_vfp_nsyn_ldm_stm (is_dbmode);
16057 return;
16058 }
16059
5287ad62 16060 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 16061 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB		 16062
16063 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM		 16064 _("register list must contain at least 1 and at most 16 "
16065 "registers"));
5287ad62
JB		 16066
16067 inst.instruction |= inst.operands[0].reg << 16;
16068 inst.instruction |= inst.operands[0].writeback << 21;
16069 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16070 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
16071
16072 inst.instruction |= offsetbits;
5f4273c7 16073
037e8744 16074 do_vfp_cond_or_thumb ();
5287ad62
JB		 16075}
16076
16077static void
16078do_neon_ldr_str (void)
16079{
5287ad62 16080 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 16081
6844b2c2
MGD		 16082 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16083 And is UNPREDICTABLE in thumb mode. */
fa94de6b 16084 if (!is_ldr
6844b2c2 16085 && inst.operands[1].reg == REG_PC
ba86b375 16086 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 16087 {
94dcf8bf 16088 if (thumb_mode)
6844b2c2 16089 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf
JB		 16090 else if (warn_on_deprecated)
16091 as_warn (_("Use of PC here is deprecated"));
6844b2c2
MGD		 16092 }
16093
037e8744
JB		 16094 if (inst.operands[0].issingle)
16095 {
cd2f129f 16096 if (is_ldr)
477330fc 16097 do_vfp_nsyn_opcode ("flds");
cd2f129f 16098 else
477330fc 16099 do_vfp_nsyn_opcode ("fsts");
5287ad62
JB		 16100 }
16101 else
5287ad62 16102 {
cd2f129f 16103 if (is_ldr)
477330fc 16104 do_vfp_nsyn_opcode ("fldd");
5287ad62 16105 else
477330fc 16106 do_vfp_nsyn_opcode ("fstd");
5287ad62 16107 }
5287ad62
JB		 16108}
16109
16110/* "interleave" version also handles non-interleaving register VLD1/VST1
16111 instructions. */
16112
16113static void
16114do_neon_ld_st_interleave (void)
16115{
037e8744 16116 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 16117 N_8 | N_16 | N_32 | N_64);
5287ad62
JB		 16118 unsigned alignbits = 0;
16119 unsigned idx;
16120 /* The bits in this table go:
16121 0: register stride of one (0) or two (1)
16122 1,2: register list length, minus one (1, 2, 3, 4).
16123 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16124 We use -1 for invalid entries. */
16125 const int typetable[] =
16126 {
16127 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16128 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16129 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16130 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16131 };
16132 int typebits;
16133
dcbf9037
JB		 16134 if (et.type == NT_invtype)
16135 return;
16136
5287ad62
JB		 16137 if (inst.operands[1].immisalign)
16138 switch (inst.operands[1].imm >> 8)
16139 {
16140 case 64: alignbits = 1; break;
16141 case 128:
477330fc 16142 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 16143 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM		 16144 goto bad_alignment;
16145 alignbits = 2;
16146 break;
5287ad62 16147 case 256:
477330fc
RM		 16148 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16149 goto bad_alignment;
16150 alignbits = 3;
16151 break;
5287ad62
JB		 16152 default:
16153 bad_alignment:
477330fc
RM		 16154 first_error (_("bad alignment"));
16155 return;
5287ad62
JB		 16156 }
16157
16158 inst.instruction |= alignbits << 4;
16159 inst.instruction |= neon_logbits (et.size) << 6;
16160
16161 /* Bits [4:6] of the immediate in a list specifier encode register stride
16162 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16163 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16164 up the right value for "type" in a table based on this value and the given
16165 list style, then stick it back. */
16166 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 16167 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB		 16168
16169 typebits = typetable[idx];
5f4273c7 16170
5287ad62 16171 constraint (typebits == -1, _("bad list type for instruction"));
1d50d57c
WN		 16172 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
16173 _("bad element type for instruction"));
5287ad62
JB		 16174
16175 inst.instruction &= ~0xf00;
16176 inst.instruction |= typebits << 8;
16177}
16178
16179/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16180 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16181 otherwise. The variable arguments are a list of pairs of legal (size, align)
16182 values, terminated with -1. */
16183
16184static int
16185neon_alignment_bit (int size, int align, int *do_align, ...)
16186{
16187 va_list ap;
16188 int result = FAIL, thissize, thisalign;
5f4273c7 16189
5287ad62
JB		 16190 if (!inst.operands[1].immisalign)
16191 {
16192 *do_align = 0;
16193 return SUCCESS;
16194 }
5f4273c7 16195
5287ad62
JB		 16196 va_start (ap, do_align);
16197
16198 do
16199 {
16200 thissize = va_arg (ap, int);
16201 if (thissize == -1)
477330fc 16202 break;
5287ad62
JB		 16203 thisalign = va_arg (ap, int);
16204
16205 if (size == thissize && align == thisalign)
477330fc 16206 result = SUCCESS;
5287ad62
JB		 16207 }
16208 while (result != SUCCESS);
16209
16210 va_end (ap);
16211
16212 if (result == SUCCESS)
16213 *do_align = 1;
16214 else
dcbf9037 16215 first_error (_("unsupported alignment for instruction"));
5f4273c7 16216
5287ad62
JB		 16217 return result;
16218}
16219
16220static void
16221do_neon_ld_st_lane (void)
16222{
037e8744 16223 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB		 16224 int align_good, do_align = 0;
16225 int logsize = neon_logbits (et.size);
16226 int align = inst.operands[1].imm >> 8;
16227 int n = (inst.instruction >> 8) & 3;
16228 int max_el = 64 / et.size;
5f4273c7 16229
dcbf9037
JB		 16230 if (et.type == NT_invtype)
16231 return;
5f4273c7 16232
5287ad62 16233 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 16234 _("bad list length"));
5287ad62 16235 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 16236 _("scalar index out of range"));
5287ad62 16237 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM		 16238 && et.size == 8,
16239 _("stride of 2 unavailable when element size is 8"));
5f4273c7 16240
5287ad62
JB		 16241 switch (n)
16242 {
16243 case 0: /* VLD1 / VST1. */
16244 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
477330fc 16245 32, 32, -1);
5287ad62 16246 if (align_good == FAIL)
477330fc 16247 return;
5287ad62 16248 if (do_align)
477330fc
RM		 16249 {
16250 unsigned alignbits = 0;
16251 switch (et.size)
16252 {
16253 case 16: alignbits = 0x1; break;
16254 case 32: alignbits = 0x3; break;
16255 default: ;
16256 }
16257 inst.instruction |= alignbits << 4;
16258 }
5287ad62
JB		 16259 break;
16260
16261 case 1: /* VLD2 / VST2. */
16262 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
477330fc 16263 32, 64, -1);
5287ad62 16264 if (align_good == FAIL)
477330fc 16265 return;
5287ad62 16266 if (do_align)
477330fc 16267 inst.instruction |= 1 << 4;
5287ad62
JB		 16268 break;
16269
16270 case 2: /* VLD3 / VST3. */
16271 constraint (inst.operands[1].immisalign,
477330fc 16272 _("can't use alignment with this instruction"));
5287ad62
JB		 16273 break;
16274
16275 case 3: /* VLD4 / VST4. */
16276 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
477330fc 16277 16, 64, 32, 64, 32, 128, -1);
5287ad62 16278 if (align_good == FAIL)
477330fc 16279 return;
5287ad62 16280 if (do_align)
477330fc
RM		 16281 {
16282 unsigned alignbits = 0;
16283 switch (et.size)
16284 {
16285 case 8: alignbits = 0x1; break;
16286 case 16: alignbits = 0x1; break;
16287 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
16288 default: ;
16289 }
16290 inst.instruction |= alignbits << 4;
16291 }
5287ad62
JB		 16292 break;
16293
16294 default: ;
16295 }
16296
16297 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16298 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16299 inst.instruction |= 1 << (4 + logsize);
5f4273c7 16300
5287ad62
JB		 16301 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
16302 inst.instruction |= logsize << 10;
16303}
16304
16305/* Encode single n-element structure to all lanes VLD<n> instructions. */
16306
16307static void
16308do_neon_ld_dup (void)
16309{
037e8744 16310 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB		 16311 int align_good, do_align = 0;
16312
dcbf9037
JB		 16313 if (et.type == NT_invtype)
16314 return;
16315
5287ad62
JB		 16316 switch ((inst.instruction >> 8) & 3)
16317 {
16318 case 0: /* VLD1. */
9c2799c2 16319 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 16320 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
477330fc 16321 &do_align, 16, 16, 32, 32, -1);
5287ad62 16322 if (align_good == FAIL)
477330fc 16323 return;
5287ad62 16324 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM		 16325 {
16326 case 1: break;
16327 case 2: inst.instruction |= 1 << 5; break;
16328 default: first_error (_("bad list length")); return;
16329 }
5287ad62
JB		 16330 inst.instruction |= neon_logbits (et.size) << 6;
16331 break;
16332
16333 case 1: /* VLD2. */
16334 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
477330fc 16335 &do_align, 8, 16, 16, 32, 32, 64, -1);
5287ad62 16336 if (align_good == FAIL)
477330fc 16337 return;
5287ad62 16338 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 16339 _("bad list length"));
5287ad62 16340 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 16341 inst.instruction |= 1 << 5;
5287ad62
JB		 16342 inst.instruction |= neon_logbits (et.size) << 6;
16343 break;
16344
16345 case 2: /* VLD3. */
16346 constraint (inst.operands[1].immisalign,
477330fc 16347 _("can't use alignment with this instruction"));
5287ad62 16348 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 16349 _("bad list length"));
5287ad62 16350 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 16351 inst.instruction |= 1 << 5;
5287ad62
JB		 16352 inst.instruction |= neon_logbits (et.size) << 6;
16353 break;
16354
16355 case 3: /* VLD4. */
16356 {
477330fc
RM		 16357 int align = inst.operands[1].imm >> 8;
16358 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
16359 16, 64, 32, 64, 32, 128, -1);
16360 if (align_good == FAIL)
16361 return;
16362 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
16363 _("bad list length"));
16364 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16365 inst.instruction |= 1 << 5;
16366 if (et.size == 32 && align == 128)
16367 inst.instruction |= 0x3 << 6;
16368 else
16369 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB		 16370 }
16371 break;
16372
16373 default: ;
16374 }
16375
16376 inst.instruction |= do_align << 4;
16377}
16378
16379/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16380 apart from bits [11:4]. */
16381
16382static void
16383do_neon_ldx_stx (void)
16384{
b1a769ed
DG		 16385 if (inst.operands[1].isreg)
16386 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16387
5287ad62
JB		 16388 switch (NEON_LANE (inst.operands[0].imm))
16389 {
16390 case NEON_INTERLEAVE_LANES:
88714cb8 16391 NEON_ENCODE (INTERLV, inst);
5287ad62
JB		 16392 do_neon_ld_st_interleave ();
16393 break;
5f4273c7 16394
5287ad62 16395 case NEON_ALL_LANES:
88714cb8 16396 NEON_ENCODE (DUP, inst);
2d51fb74
JB		 16397 if (inst.instruction == N_INV)
16398 {
16399 first_error ("only loads support such operands");
16400 break;
16401 }
5287ad62
JB		 16402 do_neon_ld_dup ();
16403 break;
5f4273c7 16404
5287ad62 16405 default:
88714cb8 16406 NEON_ENCODE (LANE, inst);
5287ad62
JB		 16407 do_neon_ld_st_lane ();
16408 }
16409
16410 /* L bit comes from bit mask. */
16411 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16412 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16413 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 16414
5287ad62
JB		 16415 if (inst.operands[1].postind)
16416 {
16417 int postreg = inst.operands[1].imm & 0xf;
16418 constraint (!inst.operands[1].immisreg,
477330fc 16419 _("post-index must be a register"));
5287ad62 16420 constraint (postreg == 0xd || postreg == 0xf,
477330fc 16421 _("bad register for post-index"));
5287ad62
JB		 16422 inst.instruction |= postreg;
16423 }
4f2374c7 16424 else
5287ad62 16425 {
4f2374c7
WN		 16426 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16427 constraint (inst.reloc.exp.X_op != O_constant
16428 || inst.reloc.exp.X_add_number != 0,
16429 BAD_ADDR_MODE);
16430
16431 if (inst.operands[1].writeback)
16432 {
16433 inst.instruction |= 0xd;
16434 }
16435 else
16436 inst.instruction |= 0xf;
5287ad62 16437 }
5f4273c7 16438
5287ad62
JB		 16439 if (thumb_mode)
16440 inst.instruction |= 0xf9000000;
16441 else
16442 inst.instruction |= 0xf4000000;
16443}
33399f07
MGD		 16444
16445/* FP v8. */
16446static void
16447do_vfp_nsyn_fpv8 (enum neon_shape rs)
16448{
a715796b
TG		 16449 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16450 D register operands. */
16451 if (neon_shape_class[rs] == SC_DOUBLE)
16452 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16453 _(BAD_FPU));
16454
33399f07
MGD		 16455 NEON_ENCODE (FPV8, inst);
16456
16457 if (rs == NS_FFF)
16458 do_vfp_sp_dyadic ();
16459 else
16460 do_vfp_dp_rd_rn_rm ();
16461
16462 if (rs == NS_DDD)
16463 inst.instruction |= 0x100;
16464
16465 inst.instruction |= 0xf0000000;
16466}
16467
16468static void
16469do_vsel (void)
16470{
16471 set_it_insn_type (OUTSIDE_IT_INSN);
16472
16473 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16474 first_error (_("invalid instruction shape"));
16475}
16476
73924fbc
MGD		 16477static void
16478do_vmaxnm (void)
16479{
16480 set_it_insn_type (OUTSIDE_IT_INSN);
16481
16482 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16483 return;
16484
16485 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16486 return;
16487
16488 neon_dyadic_misc (NT_untyped, N_F32, 0);
16489}
16490
30bdf752
MGD		 16491static void
16492do_vrint_1 (enum neon_cvt_mode mode)
16493{
16494 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16495 struct neon_type_el et;
16496
16497 if (rs == NS_NULL)
16498 return;
16499
a715796b
TG		 16500 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16501 D register operands. */
16502 if (neon_shape_class[rs] == SC_DOUBLE)
16503 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16504 _(BAD_FPU));
16505
30bdf752
MGD		 16506 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16507 if (et.type != NT_invtype)
16508 {
16509 /* VFP encodings. */
16510 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16511 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16512 set_it_insn_type (OUTSIDE_IT_INSN);
16513
16514 NEON_ENCODE (FPV8, inst);
16515 if (rs == NS_FF)
16516 do_vfp_sp_monadic ();
16517 else
16518 do_vfp_dp_rd_rm ();
16519
16520 switch (mode)
16521 {
16522 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16523 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16524 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16525 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16526 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16527 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16528 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16529 default: abort ();
16530 }
16531
16532 inst.instruction |= (rs == NS_DD) << 8;
16533 do_vfp_cond_or_thumb ();
16534 }
16535 else
16536 {
16537 /* Neon encodings (or something broken...). */
16538 inst.error = NULL;
16539 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16540
16541 if (et.type == NT_invtype)
16542 return;
16543
16544 set_it_insn_type (OUTSIDE_IT_INSN);
16545 NEON_ENCODE (FLOAT, inst);
16546
16547 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16548 return;
16549
16550 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16551 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16552 inst.instruction |= LOW4 (inst.operands[1].reg);
16553 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16554 inst.instruction |= neon_quad (rs) << 6;
16555 switch (mode)
16556 {
16557 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16558 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16559 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16560 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16561 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16562 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16563 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16564 default: abort ();
16565 }
16566
16567 if (thumb_mode)
16568 inst.instruction |= 0xfc000000;
16569 else
16570 inst.instruction |= 0xf0000000;
16571 }
16572}
16573
16574static void
16575do_vrintx (void)
16576{
16577 do_vrint_1 (neon_cvt_mode_x);
16578}
16579
16580static void
16581do_vrintz (void)
16582{
16583 do_vrint_1 (neon_cvt_mode_z);
16584}
16585
16586static void
16587do_vrintr (void)
16588{
16589 do_vrint_1 (neon_cvt_mode_r);
16590}
16591
16592static void
16593do_vrinta (void)
16594{
16595 do_vrint_1 (neon_cvt_mode_a);
16596}
16597
16598static void
16599do_vrintn (void)
16600{
16601 do_vrint_1 (neon_cvt_mode_n);
16602}
16603
16604static void
16605do_vrintp (void)
16606{
16607 do_vrint_1 (neon_cvt_mode_p);
16608}
16609
16610static void
16611do_vrintm (void)
16612{
16613 do_vrint_1 (neon_cvt_mode_m);
16614}
16615
91ff7894
MGD		 16616/* Crypto v1 instructions. */
16617static void
16618do_crypto_2op_1 (unsigned elttype, int op)
16619{
16620 set_it_insn_type (OUTSIDE_IT_INSN);
16621
16622 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16623 == NT_invtype)
16624 return;
16625
16626 inst.error = NULL;
16627
16628 NEON_ENCODE (INTEGER, inst);
16629 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16630 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16631 inst.instruction |= LOW4 (inst.operands[1].reg);
16632 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16633 if (op != -1)
16634 inst.instruction |= op << 6;
16635
16636 if (thumb_mode)
16637 inst.instruction |= 0xfc000000;
16638 else
16639 inst.instruction |= 0xf0000000;
16640}
16641
48adcd8e
MGD		 16642static void
16643do_crypto_3op_1 (int u, int op)
16644{
16645 set_it_insn_type (OUTSIDE_IT_INSN);
16646
16647 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16648 N_32 | N_UNT | N_KEY).type == NT_invtype)
16649 return;
16650
16651 inst.error = NULL;
16652
16653 NEON_ENCODE (INTEGER, inst);
16654 neon_three_same (1, u, 8 << op);
16655}
16656
91ff7894
MGD		 16657static void
16658do_aese (void)
16659{
16660 do_crypto_2op_1 (N_8, 0);
16661}
16662
16663static void
16664do_aesd (void)
16665{
16666 do_crypto_2op_1 (N_8, 1);
16667}
16668
16669static void
16670do_aesmc (void)
16671{
16672 do_crypto_2op_1 (N_8, 2);
16673}
16674
16675static void
16676do_aesimc (void)
16677{
16678 do_crypto_2op_1 (N_8, 3);
16679}
16680
48adcd8e
MGD		 16681static void
16682do_sha1c (void)
16683{
16684 do_crypto_3op_1 (0, 0);
16685}
16686
16687static void
16688do_sha1p (void)
16689{
16690 do_crypto_3op_1 (0, 1);
16691}
16692
16693static void
16694do_sha1m (void)
16695{
16696 do_crypto_3op_1 (0, 2);
16697}
16698
16699static void
16700do_sha1su0 (void)
16701{
16702 do_crypto_3op_1 (0, 3);
16703}
91ff7894 16704
48adcd8e
MGD		 16705static void
16706do_sha256h (void)
16707{
16708 do_crypto_3op_1 (1, 0);
16709}
16710
16711static void
16712do_sha256h2 (void)
16713{
16714 do_crypto_3op_1 (1, 1);
16715}
16716
16717static void
16718do_sha256su1 (void)
16719{
16720 do_crypto_3op_1 (1, 2);
16721}
3c9017d2
MGD		 16722
16723static void
16724do_sha1h (void)
16725{
16726 do_crypto_2op_1 (N_32, -1);
16727}
16728
16729static void
16730do_sha1su1 (void)
16731{
16732 do_crypto_2op_1 (N_32, 0);
16733}
16734
16735static void
16736do_sha256su0 (void)
16737{
16738 do_crypto_2op_1 (N_32, 1);
16739}
dd5181d5
KT		 16740
16741static void
16742do_crc32_1 (unsigned int poly, unsigned int sz)
16743{
16744 unsigned int Rd = inst.operands[0].reg;
16745 unsigned int Rn = inst.operands[1].reg;
16746 unsigned int Rm = inst.operands[2].reg;
16747
16748 set_it_insn_type (OUTSIDE_IT_INSN);
16749 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16750 inst.instruction |= LOW4 (Rn) << 16;
16751 inst.instruction |= LOW4 (Rm);
16752 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16753 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16754
16755 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16756 as_warn (UNPRED_REG ("r15"));
16757 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16758 as_warn (UNPRED_REG ("r13"));
16759}
16760
16761static void
16762do_crc32b (void)
16763{
16764 do_crc32_1 (0, 0);
16765}
16766
16767static void
16768do_crc32h (void)
16769{
16770 do_crc32_1 (0, 1);
16771}
16772
16773static void
16774do_crc32w (void)
16775{
16776 do_crc32_1 (0, 2);
16777}
16778
16779static void
16780do_crc32cb (void)
16781{
16782 do_crc32_1 (1, 0);
16783}
16784
16785static void
16786do_crc32ch (void)
16787{
16788 do_crc32_1 (1, 1);
16789}
16790
16791static void
16792do_crc32cw (void)
16793{
16794 do_crc32_1 (1, 2);
16795}
16796
5287ad62
JB		 16797\f
16798/* Overall per-instruction processing. */
16799
16800/* We need to be able to fix up arbitrary expressions in some statements.
16801 This is so that we can handle symbols that are an arbitrary distance from
16802 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16803 which returns part of an address in a form which will be valid for
16804 a data instruction. We do this by pushing the expression into a symbol
16805 in the expr_section, and creating a fix for that. */
16806
16807static void
16808fix_new_arm (fragS * frag,
16809 int where,
16810 short int size,
16811 expressionS * exp,
16812 int pc_rel,
16813 int reloc)
16814{
16815 fixS * new_fix;
16816
16817 switch (exp->X_op)
16818 {
16819 case O_constant:
6e7ce2cd
PB		 16820 if (pc_rel)
16821 {
16822 /* Create an absolute valued symbol, so we have something to
477330fc
RM		 16823 refer to in the object file. Unfortunately for us, gas's
16824 generic expression parsing will already have folded out
16825 any use of .set foo/.type foo %function that may have
16826 been used to set type information of the target location,
16827 that's being specified symbolically. We have to presume
16828 the user knows what they are doing. */
6e7ce2cd
PB		 16829 char name[16 + 8];
16830 symbolS *symbol;
16831
16832 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16833
16834 symbol = symbol_find_or_make (name);
16835 S_SET_SEGMENT (symbol, absolute_section);
16836 symbol_set_frag (symbol, &zero_address_frag);
16837 S_SET_VALUE (symbol, exp->X_add_number);
16838 exp->X_op = O_symbol;
16839 exp->X_add_symbol = symbol;
16840 exp->X_add_number = 0;
16841 }
16842 /* FALLTHROUGH */
5287ad62
JB		 16843 case O_symbol:
16844 case O_add:
16845 case O_subtract:
21d799b5 16846 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 16847 (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 16848 break;
16849
16850 default:
21d799b5 16851 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 16852 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 16853 break;
16854 }
16855
16856 /* Mark whether the fix is to a THUMB instruction, or an ARM
16857 instruction. */
16858 new_fix->tc_fix_data = thumb_mode;
16859}
16860
16861/* Create a frg for an instruction requiring relaxation. */
16862static void
16863output_relax_insn (void)
16864{
16865 char * to;
16866 symbolS *sym;
0110f2b8
PB		 16867 int offset;
16868
6e1cb1a6
PB		 16869 /* The size of the instruction is unknown, so tie the debug info to the
16870 start of the instruction. */
16871 dwarf2_emit_insn (0);
6e1cb1a6 16872
0110f2b8
PB		 16873 switch (inst.reloc.exp.X_op)
16874 {
16875 case O_symbol:
16876 sym = inst.reloc.exp.X_add_symbol;
16877 offset = inst.reloc.exp.X_add_number;
16878 break;
16879 case O_constant:
16880 sym = NULL;
16881 offset = inst.reloc.exp.X_add_number;
16882 break;
16883 default:
16884 sym = make_expr_symbol (&inst.reloc.exp);
16885 offset = 0;
16886 break;
16887 }
16888 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16889 inst.relax, sym, offset, NULL/*offset, opcode*/);
16890 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB		 16891}
16892
16893/* Write a 32-bit thumb instruction to buf. */
16894static void
16895put_thumb32_insn (char * buf, unsigned long insn)
16896{
16897 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16898 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16899}
16900
b99bd4ef 16901static void
c19d1205 16902output_inst (const char * str)
b99bd4ef 16903{
c19d1205 16904 char * to = NULL;
b99bd4ef 16905
c19d1205 16906 if (inst.error)
b99bd4ef 16907 {
c19d1205 16908 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC		 16909 return;
16910 }
5f4273c7
NC		 16911 if (inst.relax)
16912 {
16913 output_relax_insn ();
0110f2b8 16914 return;
5f4273c7 16915 }
c19d1205
ZW		 16916 if (inst.size == 0)
16917 return;
b99bd4ef 16918
c19d1205 16919 to = frag_more (inst.size);
8dc2430f
NC		 16920 /* PR 9814: Record the thumb mode into the current frag so that we know
16921 what type of NOP padding to use, if necessary. We override any previous
16922 setting so that if the mode has changed then the NOPS that we use will
16923 match the encoding of the last instruction in the frag. */
cd000bff 16924 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW		 16925
16926 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 16927 {
9c2799c2 16928 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 16929 put_thumb32_insn (to, inst.instruction);
b99bd4ef 16930 }
c19d1205 16931 else if (inst.size > INSN_SIZE)
b99bd4ef 16932 {
9c2799c2 16933 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW		 16934 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16935 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 16936 }
c19d1205
ZW		 16937 else
16938 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 16939
c19d1205
ZW		 16940 if (inst.reloc.type != BFD_RELOC_UNUSED)
16941 fix_new_arm (frag_now, to - frag_now->fr_literal,
16942 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16943 inst.reloc.type);
b99bd4ef 16944
c19d1205 16945 dwarf2_emit_insn (inst.size);
c19d1205 16946}
b99bd4ef 16947
e07e6e58
NC		 16948static char *
16949output_it_inst (int cond, int mask, char * to)
16950{
16951 unsigned long instruction = 0xbf00;
16952
16953 mask &= 0xf;
16954 instruction |= mask;
16955 instruction |= cond << 4;
16956
16957 if (to == NULL)
16958 {
16959 to = frag_more (2);
16960#ifdef OBJ_ELF
16961 dwarf2_emit_insn (2);
16962#endif
16963 }
16964
16965 md_number_to_chars (to, instruction, 2);
16966
16967 return to;
16968}
16969
c19d1205
ZW		 16970/* Tag values used in struct asm_opcode's tag field. */
16971enum opcode_tag
16972{
16973 OT_unconditional, /* Instruction cannot be conditionalized.
16974 The ARM condition field is still 0xE. */
16975 OT_unconditionalF, /* Instruction cannot be conditionalized
16976 and carries 0xF in its ARM condition field. */
16977 OT_csuffix, /* Instruction takes a conditional suffix. */
037e8744 16978 OT_csuffixF, /* Some forms of the instruction take a conditional
477330fc
RM		 16979 suffix, others place 0xF where the condition field
16980 would be. */
c19d1205
ZW		 16981 OT_cinfix3, /* Instruction takes a conditional infix,
16982 beginning at character index 3. (In
16983 unified mode, it becomes a suffix.) */
088fa78e
KH		 16984 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16985 tsts, cmps, cmns, and teqs. */
e3cb604e
PB		 16986 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
16987 character index 3, even in unified mode. Used for
16988 legacy instructions where suffix and infix forms
16989 may be ambiguous. */
c19d1205 16990 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 16991 suffix or an infix at character index 3. */
c19d1205
ZW		 16992 OT_odd_infix_unc, /* This is the unconditional variant of an
16993 instruction that takes a conditional infix
16994 at an unusual position. In unified mode,
16995 this variant will accept a suffix. */
16996 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
16997 are the conditional variants of instructions that
16998 take conditional infixes in unusual positions.
16999 The infix appears at character index
17000 (tag - OT_odd_infix_0). These are not accepted
17001 in unified mode. */
17002};
b99bd4ef 17003
c19d1205
ZW		 17004/* Subroutine of md_assemble, responsible for looking up the primary
17005 opcode from the mnemonic the user wrote. STR points to the
17006 beginning of the mnemonic.
17007
17008 This is not simply a hash table lookup, because of conditional
17009 variants. Most instructions have conditional variants, which are
17010 expressed with a _conditional affix_ to the mnemonic. If we were
17011 to encode each conditional variant as a literal string in the opcode
17012 table, it would have approximately 20,000 entries.
17013
17014 Most mnemonics take this affix as a suffix, and in unified syntax,
17015 'most' is upgraded to 'all'. However, in the divided syntax, some
17016 instructions take the affix as an infix, notably the s-variants of
17017 the arithmetic instructions. Of those instructions, all but six
17018 have the infix appear after the third character of the mnemonic.
17019
17020 Accordingly, the algorithm for looking up primary opcodes given
17021 an identifier is:
17022
17023 1. Look up the identifier in the opcode table.
17024 If we find a match, go to step U.
17025
17026 2. Look up the last two characters of the identifier in the
17027 conditions table. If we find a match, look up the first N-2
17028 characters of the identifier in the opcode table. If we
17029 find a match, go to step CE.
17030
17031 3. Look up the fourth and fifth characters of the identifier in
17032 the conditions table. If we find a match, extract those
17033 characters from the identifier, and look up the remaining
17034 characters in the opcode table. If we find a match, go
17035 to step CM.
17036
17037 4. Fail.
17038
17039 U. Examine the tag field of the opcode structure, in case this is
17040 one of the six instructions with its conditional infix in an
17041 unusual place. If it is, the tag tells us where to find the
17042 infix; look it up in the conditions table and set inst.cond
17043 accordingly. Otherwise, this is an unconditional instruction.
17044 Again set inst.cond accordingly. Return the opcode structure.
17045
17046 CE. Examine the tag field to make sure this is an instruction that
17047 should receive a conditional suffix. If it is not, fail.
17048 Otherwise, set inst.cond from the suffix we already looked up,
17049 and return the opcode structure.
17050
17051 CM. Examine the tag field to make sure this is an instruction that
17052 should receive a conditional infix after the third character.
17053 If it is not, fail. Otherwise, undo the edits to the current
17054 line of input and proceed as for case CE. */
17055
17056static const struct asm_opcode *
17057opcode_lookup (char **str)
17058{
17059 char *end, *base;
17060 char *affix;
17061 const struct asm_opcode *opcode;
17062 const struct asm_cond *cond;
e3cb604e 17063 char save[2];
c19d1205
ZW		 17064
17065 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 17066 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 17067 for (base = end = *str; *end != '\0'; end++)
721a8186 17068 if (*end == ' ' || *end == '.')
c19d1205 17069 break;
b99bd4ef 17070
c19d1205 17071 if (end == base)
c921be7d 17072 return NULL;
b99bd4ef 17073
5287ad62 17074 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 17075 if (end[0] == '.')
b99bd4ef 17076 {
5287ad62 17077 int offset = 2;
5f4273c7 17078
267d2029 17079 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 17080 use. */
267d2029 17081 if (unified_syntax && end[1] == 'w')
c19d1205 17082 inst.size_req = 4;
267d2029 17083 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW		 17084 inst.size_req = 2;
17085 else
477330fc 17086 offset = 0;
5287ad62
JB		 17087
17088 inst.vectype.elems = 0;
17089
17090 *str = end + offset;
b99bd4ef 17091
5f4273c7 17092 if (end[offset] == '.')
5287ad62 17093 {
267d2029 17094 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM		 17095 non-unified ARM syntax mode). */
17096 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 17097 return NULL;
477330fc 17098 }
5287ad62 17099 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 17100 return NULL;
b99bd4ef 17101 }
c19d1205
ZW		 17102 else
17103 *str = end;
b99bd4ef 17104
c19d1205 17105 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 17106 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 17107 end - base);
c19d1205 17108 if (opcode)
b99bd4ef 17109 {
c19d1205
ZW		 17110 /* step U */
17111 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 17112 {
c19d1205
ZW		 17113 inst.cond = COND_ALWAYS;
17114 return opcode;
b99bd4ef 17115 }
b99bd4ef 17116
278df34e 17117 if (warn_on_deprecated && unified_syntax)
c19d1205
ZW		 17118 as_warn (_("conditional infixes are deprecated in unified syntax"));
17119 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 17120 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 17121 gas_assert (cond);
b99bd4ef 17122
c19d1205
ZW		 17123 inst.cond = cond->value;
17124 return opcode;
17125 }
b99bd4ef 17126
c19d1205
ZW		 17127 /* Cannot have a conditional suffix on a mnemonic of less than two
17128 characters. */
17129 if (end - base < 3)
c921be7d 17130 return NULL;
b99bd4ef 17131
c19d1205
ZW		 17132 /* Look for suffixed mnemonic. */
17133 affix = end - 2;
21d799b5
NC		 17134 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17135 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 17136 affix - base);
c19d1205
ZW		 17137 if (opcode && cond)
17138 {
17139 /* step CE */
17140 switch (opcode->tag)
17141 {
e3cb604e
PB		 17142 case OT_cinfix3_legacy:
17143 /* Ignore conditional suffixes matched on infix only mnemonics. */
17144 break;
17145
c19d1205 17146 case OT_cinfix3:
088fa78e 17147 case OT_cinfix3_deprecated:
c19d1205
ZW		 17148 case OT_odd_infix_unc:
17149 if (!unified_syntax)
e3cb604e 17150 return 0;
c19d1205
ZW		 17151 /* else fall through */
17152
17153 case OT_csuffix:
477330fc 17154 case OT_csuffixF:
c19d1205
ZW		 17155 case OT_csuf_or_in3:
17156 inst.cond = cond->value;
17157 return opcode;
17158
17159 case OT_unconditional:
17160 case OT_unconditionalF:
dfa9f0d5 17161 if (thumb_mode)
c921be7d 17162 inst.cond = cond->value;
dfa9f0d5
PB		 17163 else
17164 {
c921be7d 17165 /* Delayed diagnostic. */
dfa9f0d5
PB		 17166 inst.error = BAD_COND;
17167 inst.cond = COND_ALWAYS;
17168 }
c19d1205 17169 return opcode;
b99bd4ef 17170
c19d1205 17171 default:
c921be7d 17172 return NULL;
c19d1205
ZW		 17173 }
17174 }
b99bd4ef 17175
c19d1205
ZW		 17176 /* Cannot have a usual-position infix on a mnemonic of less than
17177 six characters (five would be a suffix). */
17178 if (end - base < 6)
c921be7d 17179 return NULL;
b99bd4ef 17180
c19d1205
ZW		 17181 /* Look for infixed mnemonic in the usual position. */
17182 affix = base + 3;
21d799b5 17183 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 17184 if (!cond)
c921be7d 17185 return NULL;
e3cb604e
PB		 17186
17187 memcpy (save, affix, 2);
17188 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 17189 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 17190 (end - base) - 2);
e3cb604e
PB		 17191 memmove (affix + 2, affix, (end - affix) - 2);
17192 memcpy (affix, save, 2);
17193
088fa78e
KH		 17194 if (opcode
17195 && (opcode->tag == OT_cinfix3
17196 || opcode->tag == OT_cinfix3_deprecated
17197 || opcode->tag == OT_csuf_or_in3
17198 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 17199 {
c921be7d 17200 /* Step CM. */
278df34e 17201 if (warn_on_deprecated && unified_syntax
088fa78e
KH		 17202 && (opcode->tag == OT_cinfix3
17203 || opcode->tag == OT_cinfix3_deprecated))
c19d1205
ZW		 17204 as_warn (_("conditional infixes are deprecated in unified syntax"));
17205
17206 inst.cond = cond->value;
17207 return opcode;
b99bd4ef
NC		 17208 }
17209
c921be7d 17210 return NULL;
b99bd4ef
NC		 17211}
17212
e07e6e58
NC		 17213/* This function generates an initial IT instruction, leaving its block
17214 virtually open for the new instructions. Eventually,
17215 the mask will be updated by now_it_add_mask () each time
17216 a new instruction needs to be included in the IT block.
17217 Finally, the block is closed with close_automatic_it_block ().
17218 The block closure can be requested either from md_assemble (),
17219 a tencode (), or due to a label hook. */
17220
17221static void
17222new_automatic_it_block (int cond)
17223{
17224 now_it.state = AUTOMATIC_IT_BLOCK;
17225 now_it.mask = 0x18;
17226 now_it.cc = cond;
17227 now_it.block_length = 1;
cd000bff 17228 mapping_state (MAP_THUMB);
e07e6e58 17229 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
5a01bb1d
MGD		 17230 now_it.warn_deprecated = FALSE;
17231 now_it.insn_cond = TRUE;
e07e6e58
NC		 17232}
17233
17234/* Close an automatic IT block.
17235 See comments in new_automatic_it_block (). */
17236
17237static void
17238close_automatic_it_block (void)
17239{
17240 now_it.mask = 0x10;
17241 now_it.block_length = 0;
17242}
17243
17244/* Update the mask of the current automatically-generated IT
17245 instruction. See comments in new_automatic_it_block (). */
17246
17247static void
17248now_it_add_mask (int cond)
17249{
17250#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17251#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 17252 | ((bitvalue) << (nbit)))
e07e6e58 17253 const int resulting_bit = (cond & 1);
c921be7d 17254
e07e6e58
NC		 17255 now_it.mask &= 0xf;
17256 now_it.mask = SET_BIT_VALUE (now_it.mask,
477330fc
RM		 17257 resulting_bit,
17258 (5 - now_it.block_length));
e07e6e58 17259 now_it.mask = SET_BIT_VALUE (now_it.mask,
477330fc
RM		 17260 1,
17261 ((5 - now_it.block_length) - 1) );
e07e6e58
NC		 17262 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
17263
17264#undef CLEAR_BIT
17265#undef SET_BIT_VALUE
e07e6e58
NC		 17266}
17267
17268/* The IT blocks handling machinery is accessed through the these functions:
17269 it_fsm_pre_encode () from md_assemble ()
17270 set_it_insn_type () optional, from the tencode functions
17271 set_it_insn_type_last () ditto
17272 in_it_block () ditto
17273 it_fsm_post_encode () from md_assemble ()
17274 force_automatic_it_block_close () from label habdling functions
17275
17276 Rationale:
17277 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM		 17278 initializing the IT insn type with a generic initial value depending
17279 on the inst.condition.
e07e6e58 17280 2) During the tencode function, two things may happen:
477330fc
RM		 17281 a) The tencode function overrides the IT insn type by
17282 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17283 b) The tencode function queries the IT block state by
17284 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17285
17286 Both set_it_insn_type and in_it_block run the internal FSM state
17287 handling function (handle_it_state), because: a) setting the IT insn
17288 type may incur in an invalid state (exiting the function),
17289 and b) querying the state requires the FSM to be updated.
17290 Specifically we want to avoid creating an IT block for conditional
17291 branches, so it_fsm_pre_encode is actually a guess and we can't
17292 determine whether an IT block is required until the tencode () routine
17293 has decided what type of instruction this actually it.
17294 Because of this, if set_it_insn_type and in_it_block have to be used,
17295 set_it_insn_type has to be called first.
17296
17297 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17298 determines the insn IT type depending on the inst.cond code.
17299 When a tencode () routine encodes an instruction that can be
17300 either outside an IT block, or, in the case of being inside, has to be
17301 the last one, set_it_insn_type_last () will determine the proper
17302 IT instruction type based on the inst.cond code. Otherwise,
17303 set_it_insn_type can be called for overriding that logic or
17304 for covering other cases.
17305
17306 Calling handle_it_state () may not transition the IT block state to
17307 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17308 still queried. Instead, if the FSM determines that the state should
17309 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17310 after the tencode () function: that's what it_fsm_post_encode () does.
17311
17312 Since in_it_block () calls the state handling function to get an
17313 updated state, an error may occur (due to invalid insns combination).
17314 In that case, inst.error is set.
17315 Therefore, inst.error has to be checked after the execution of
17316 the tencode () routine.
e07e6e58
NC		 17317
17318 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc
RM		 17319 any pending state change (if any) that didn't take place in
17320 handle_it_state () as explained above. */
e07e6e58
NC		 17321
17322static void
17323it_fsm_pre_encode (void)
17324{
17325 if (inst.cond != COND_ALWAYS)
17326 inst.it_insn_type = INSIDE_IT_INSN;
17327 else
17328 inst.it_insn_type = OUTSIDE_IT_INSN;
17329
17330 now_it.state_handled = 0;
17331}
17332
17333/* IT state FSM handling function. */
17334
17335static int
17336handle_it_state (void)
17337{
17338 now_it.state_handled = 1;
5a01bb1d 17339 now_it.insn_cond = FALSE;
e07e6e58
NC		 17340
17341 switch (now_it.state)
17342 {
17343 case OUTSIDE_IT_BLOCK:
17344 switch (inst.it_insn_type)
17345 {
17346 case OUTSIDE_IT_INSN:
17347 break;
17348
17349 case INSIDE_IT_INSN:
17350 case INSIDE_IT_LAST_INSN:
17351 if (thumb_mode == 0)
17352 {
c921be7d 17353 if (unified_syntax
e07e6e58
NC		 17354 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
17355 as_tsktsk (_("Warning: conditional outside an IT block"\
17356 " for Thumb."));
17357 }
17358 else
17359 {
17360 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
17361 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
17362 {
17363 /* Automatically generate the IT instruction. */
17364 new_automatic_it_block (inst.cond);
17365 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
17366 close_automatic_it_block ();
17367 }
17368 else
17369 {
17370 inst.error = BAD_OUT_IT;
17371 return FAIL;
17372 }
17373 }
17374 break;
17375
17376 case IF_INSIDE_IT_LAST_INSN:
17377 case NEUTRAL_IT_INSN:
17378 break;
17379
17380 case IT_INSN:
17381 now_it.state = MANUAL_IT_BLOCK;
17382 now_it.block_length = 0;
17383 break;
17384 }
17385 break;
17386
17387 case AUTOMATIC_IT_BLOCK:
17388 /* Three things may happen now:
17389 a) We should increment current it block size;
17390 b) We should close current it block (closing insn or 4 insns);
17391 c) We should close current it block and start a new one (due
17392 to incompatible conditions or
17393 4 insns-length block reached). */
17394
17395 switch (inst.it_insn_type)
17396 {
17397 case OUTSIDE_IT_INSN:
17398 /* The closure of the block shall happen immediatelly,
17399 so any in_it_block () call reports the block as closed. */
17400 force_automatic_it_block_close ();
17401 break;
17402
17403 case INSIDE_IT_INSN:
17404 case INSIDE_IT_LAST_INSN:
17405 case IF_INSIDE_IT_LAST_INSN:
17406 now_it.block_length++;
17407
17408 if (now_it.block_length > 4
17409 || !now_it_compatible (inst.cond))
17410 {
17411 force_automatic_it_block_close ();
17412 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17413 new_automatic_it_block (inst.cond);
17414 }
17415 else
17416 {
5a01bb1d 17417 now_it.insn_cond = TRUE;
e07e6e58
NC		 17418 now_it_add_mask (inst.cond);
17419 }
17420
17421 if (now_it.state == AUTOMATIC_IT_BLOCK
17422 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17423 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17424 close_automatic_it_block ();
17425 break;
17426
17427 case NEUTRAL_IT_INSN:
17428 now_it.block_length++;
5a01bb1d 17429 now_it.insn_cond = TRUE;
e07e6e58
NC		 17430
17431 if (now_it.block_length > 4)
17432 force_automatic_it_block_close ();
17433 else
17434 now_it_add_mask (now_it.cc & 1);
17435 break;
17436
17437 case IT_INSN:
17438 close_automatic_it_block ();
17439 now_it.state = MANUAL_IT_BLOCK;
17440 break;
17441 }
17442 break;
17443
17444 case MANUAL_IT_BLOCK:
17445 {
17446 /* Check conditional suffixes. */
17447 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17448 int is_last;
17449 now_it.mask <<= 1;
17450 now_it.mask &= 0x1f;
17451 is_last = (now_it.mask == 0x10);
5a01bb1d 17452 now_it.insn_cond = TRUE;
e07e6e58
NC		 17453
17454 switch (inst.it_insn_type)
17455 {
17456 case OUTSIDE_IT_INSN:
17457 inst.error = BAD_NOT_IT;
17458 return FAIL;
17459
17460 case INSIDE_IT_INSN:
17461 if (cond != inst.cond)
17462 {
17463 inst.error = BAD_IT_COND;
17464 return FAIL;
17465 }
17466 break;
17467
17468 case INSIDE_IT_LAST_INSN:
17469 case IF_INSIDE_IT_LAST_INSN:
17470 if (cond != inst.cond)
17471 {
17472 inst.error = BAD_IT_COND;
17473 return FAIL;
17474 }
17475 if (!is_last)
17476 {
17477 inst.error = BAD_BRANCH;
17478 return FAIL;
17479 }
17480 break;
17481
17482 case NEUTRAL_IT_INSN:
17483 /* The BKPT instruction is unconditional even in an IT block. */
17484 break;
17485
17486 case IT_INSN:
17487 inst.error = BAD_IT_IT;
17488 return FAIL;
17489 }
17490 }
17491 break;
17492 }
17493
17494 return SUCCESS;
17495}
17496
5a01bb1d
MGD		 17497struct depr_insn_mask
17498{
17499 unsigned long pattern;
17500 unsigned long mask;
17501 const char* description;
17502};
17503
17504/* List of 16-bit instruction patterns deprecated in an IT block in
17505 ARMv8. */
17506static const struct depr_insn_mask depr_it_insns[] = {
17507 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17508 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17509 { 0xa000, 0xb800, N_("ADR") },
17510 { 0x4800, 0xf800, N_("Literal loads") },
17511 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17512 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
c8de034b
JW		 17513 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17514 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17515 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
5a01bb1d
MGD		 17516 { 0, 0, NULL }
17517};
17518
e07e6e58
NC		 17519static void
17520it_fsm_post_encode (void)
17521{
17522 int is_last;
17523
17524 if (!now_it.state_handled)
17525 handle_it_state ();
17526
5a01bb1d
MGD		 17527 if (now_it.insn_cond
17528 && !now_it.warn_deprecated
17529 && warn_on_deprecated
17530 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17531 {
17532 if (inst.instruction >= 0x10000)
17533 {
0a8897c7 17534 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
5a01bb1d
MGD		 17535 "deprecated in ARMv8"));
17536 now_it.warn_deprecated = TRUE;
17537 }
17538 else
17539 {
17540 const struct depr_insn_mask *p = depr_it_insns;
17541
17542 while (p->mask != 0)
17543 {
17544 if ((inst.instruction & p->mask) == p->pattern)
17545 {
0a8897c7 17546 as_warn (_("IT blocks containing 16-bit Thumb instructions "
5a01bb1d
MGD		 17547 "of the following class are deprecated in ARMv8: "
17548 "%s"), p->description);
17549 now_it.warn_deprecated = TRUE;
17550 break;
17551 }
17552
17553 ++p;
17554 }
17555 }
17556
17557 if (now_it.block_length > 1)
17558 {
0a8897c7
KT		 17559 as_warn (_("IT blocks containing more than one conditional "
17560 "instruction are deprecated in ARMv8"));
5a01bb1d
MGD		 17561 now_it.warn_deprecated = TRUE;
17562 }
17563 }
17564
e07e6e58
NC		 17565 is_last = (now_it.mask == 0x10);
17566 if (is_last)
17567 {
17568 now_it.state = OUTSIDE_IT_BLOCK;
17569 now_it.mask = 0;
17570 }
17571}
17572
17573static void
17574force_automatic_it_block_close (void)
17575{
17576 if (now_it.state == AUTOMATIC_IT_BLOCK)
17577 {
17578 close_automatic_it_block ();
17579 now_it.state = OUTSIDE_IT_BLOCK;
17580 now_it.mask = 0;
17581 }
17582}
17583
17584static int
17585in_it_block (void)
17586{
17587 if (!now_it.state_handled)
17588 handle_it_state ();
17589
17590 return now_it.state != OUTSIDE_IT_BLOCK;
17591}
17592
c19d1205
ZW		 17593void
17594md_assemble (char *str)
b99bd4ef 17595{
c19d1205
ZW		 17596 char *p = str;
17597 const struct asm_opcode * opcode;
b99bd4ef 17598
c19d1205
ZW		 17599 /* Align the previous label if needed. */
17600 if (last_label_seen != NULL)
b99bd4ef 17601 {
c19d1205
ZW		 17602 symbol_set_frag (last_label_seen, frag_now);
17603 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17604 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC		 17605 }
17606
c19d1205
ZW		 17607 memset (&inst, '\0', sizeof (inst));
17608 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 17609
c19d1205
ZW		 17610 opcode = opcode_lookup (&p);
17611 if (!opcode)
b99bd4ef 17612 {
c19d1205 17613 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 17614 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 17615 if (! create_register_alias (str, p)
477330fc 17616 && ! create_neon_reg_alias (str, p))
c19d1205 17617 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 17618
b99bd4ef
NC		 17619 return;
17620 }
17621
278df34e 17622 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
088fa78e
KH		 17623 as_warn (_("s suffix on comparison instruction is deprecated"));
17624
037e8744
JB		 17625 /* The value which unconditional instructions should have in place of the
17626 condition field. */
17627 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17628
c19d1205 17629 if (thumb_mode)
b99bd4ef 17630 {
e74cfd16 17631 arm_feature_set variant;
8f06b2d8
PB		 17632
17633 variant = cpu_variant;
17634 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB		 17635 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17636 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 17637 /* Check that this instruction is supported for this CPU. */
62b3e311
PB		 17638 if (!opcode->tvariant
17639 || (thumb_mode == 1
17640 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 17641 {
bf3eeda7 17642 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
b99bd4ef
NC		 17643 return;
17644 }
c19d1205
ZW		 17645 if (inst.cond != COND_ALWAYS && !unified_syntax
17646 && opcode->tencode != do_t_branch)
b99bd4ef 17647 {
c19d1205 17648 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC		 17649 return;
17650 }
17651
752d5da4 17652 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
076d447c 17653 {
7e806470 17654 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
752d5da4
NC		 17655 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17656 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17657 {
17658 /* Two things are addressed here.
17659 1) Implicit require narrow instructions on Thumb-1.
17660 This avoids relaxation accidentally introducing Thumb-2
17661 instructions.
17662 2) Reject wide instructions in non Thumb-2 cores. */
17663 if (inst.size_req == 0)
17664 inst.size_req = 2;
17665 else if (inst.size_req == 4)
17666 {
bf3eeda7 17667 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
752d5da4
NC		 17668 return;
17669 }
17670 }
076d447c
PB		 17671 }
17672
c19d1205
ZW		 17673 inst.instruction = opcode->tvalue;
17674
5be8be5d 17675 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc
RM		 17676 {
17677 /* Prepare the it_insn_type for those encodings that don't set
17678 it. */
17679 it_fsm_pre_encode ();
c19d1205 17680
477330fc 17681 opcode->tencode ();
e07e6e58 17682
477330fc
RM		 17683 it_fsm_post_encode ();
17684 }
e27ec89e 17685
0110f2b8 17686 if (!(inst.error || inst.relax))
b99bd4ef 17687 {
9c2799c2 17688 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW		 17689 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17690 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 17691 {
c19d1205 17692 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC		 17693 return;
17694 }
17695 }
076d447c
PB		 17696
17697 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 17698 instruction. */
9c2799c2 17699 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 17700
e74cfd16
PB		 17701 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17702 *opcode->tvariant);
ee065d83 17703 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
708587a4 17704 set those bits when Thumb-2 32-bit instructions are seen. ie.
7e806470 17705 anything other than bl/blx and v6-M instructions.
3cfdb781
TG		 17706 The impact of relaxable instructions will be considered later after we
17707 finish all relaxation. */
17708 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
e07e6e58
NC		 17709 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17710 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
e74cfd16
PB		 17711 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17712 arm_ext_v6t2);
cd000bff 17713
88714cb8
DG		 17714 check_neon_suffixes;
17715
cd000bff 17716 if (!inst.error)
c877a2f2
NC		 17717 {
17718 mapping_state (MAP_THUMB);
17719 }
c19d1205 17720 }
3e9e4fcf 17721 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 17722 {
845b51d6
PB		 17723 bfd_boolean is_bx;
17724
17725 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17726 is_bx = (opcode->aencode == do_bx);
17727
c19d1205 17728 /* Check that this instruction is supported for this CPU. */
845b51d6
PB		 17729 if (!(is_bx && fix_v4bx)
17730 && !(opcode->avariant &&
17731 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 17732 {
bf3eeda7 17733 as_bad (_("selected processor does not support ARM mode `%s'"), str);
c19d1205 17734 return;
b99bd4ef 17735 }
c19d1205 17736 if (inst.size_req)
b99bd4ef 17737 {
c19d1205
ZW		 17738 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17739 return;
b99bd4ef
NC		 17740 }
17741
c19d1205
ZW		 17742 inst.instruction = opcode->avalue;
17743 if (opcode->tag == OT_unconditionalF)
17744 inst.instruction |= 0xF << 28;
17745 else
17746 inst.instruction |= inst.cond << 28;
17747 inst.size = INSN_SIZE;
5be8be5d 17748 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM		 17749 {
17750 it_fsm_pre_encode ();
17751 opcode->aencode ();
17752 it_fsm_post_encode ();
17753 }
ee065d83 17754 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 17755 on a hypothetical non-thumb v5 core. */
845b51d6 17756 if (is_bx)
e74cfd16 17757 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 17758 else
e74cfd16
PB		 17759 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17760 *opcode->avariant);
88714cb8
DG		 17761
17762 check_neon_suffixes;
17763
cd000bff 17764 if (!inst.error)
c877a2f2
NC		 17765 {
17766 mapping_state (MAP_ARM);
17767 }
b99bd4ef 17768 }
3e9e4fcf
JB		 17769 else
17770 {
17771 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17772 "-- `%s'"), str);
17773 return;
17774 }
c19d1205
ZW		 17775 output_inst (str);
17776}
b99bd4ef 17777
e07e6e58
NC		 17778static void
17779check_it_blocks_finished (void)
17780{
17781#ifdef OBJ_ELF
17782 asection *sect;
17783
17784 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17785 if (seg_info (sect)->tc_segment_info_data.current_it.state
17786 == MANUAL_IT_BLOCK)
17787 {
17788 as_warn (_("section '%s' finished with an open IT block."),
17789 sect->name);
17790 }
17791#else
17792 if (now_it.state == MANUAL_IT_BLOCK)
17793 as_warn (_("file finished with an open IT block."));
17794#endif
17795}
17796
c19d1205
ZW		 17797/* Various frobbings of labels and their addresses. */
17798
17799void
17800arm_start_line_hook (void)
17801{
17802 last_label_seen = NULL;
b99bd4ef
NC		 17803}
17804
c19d1205
ZW		 17805void
17806arm_frob_label (symbolS * sym)
b99bd4ef 17807{
c19d1205 17808 last_label_seen = sym;
b99bd4ef 17809
c19d1205 17810 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 17811
c19d1205
ZW		 17812#if defined OBJ_COFF || defined OBJ_ELF
17813 ARM_SET_INTERWORK (sym, support_interwork);
17814#endif
b99bd4ef 17815
e07e6e58
NC		 17816 force_automatic_it_block_close ();
17817
5f4273c7 17818 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW		 17819 as Thumb functions. This is because these labels, whilst
17820 they exist inside Thumb code, are not the entry points for
17821 possible ARM->Thumb calls. Also, these labels can be used
17822 as part of a computed goto or switch statement. eg gcc
17823 can generate code that looks like this:
b99bd4ef 17824
c19d1205
ZW		 17825 ldr r2, [pc, .Laaa]
17826 lsl r3, r3, #2
17827 ldr r2, [r3, r2]
17828 mov pc, r2
b99bd4ef 17829
c19d1205
ZW		 17830 .Lbbb: .word .Lxxx
17831 .Lccc: .word .Lyyy
17832 ..etc...
17833 .Laaa: .word Lbbb
b99bd4ef 17834
c19d1205
ZW		 17835 The first instruction loads the address of the jump table.
17836 The second instruction converts a table index into a byte offset.
17837 The third instruction gets the jump address out of the table.
17838 The fourth instruction performs the jump.
b99bd4ef 17839
c19d1205
ZW		 17840 If the address stored at .Laaa is that of a symbol which has the
17841 Thumb_Func bit set, then the linker will arrange for this address
17842 to have the bottom bit set, which in turn would mean that the
17843 address computation performed by the third instruction would end
17844 up with the bottom bit set. Since the ARM is capable of unaligned
17845 word loads, the instruction would then load the incorrect address
17846 out of the jump table, and chaos would ensue. */
17847 if (label_is_thumb_function_name
17848 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17849 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 17850 {
c19d1205
ZW		 17851 /* When the address of a Thumb function is taken the bottom
17852 bit of that address should be set. This will allow
17853 interworking between Arm and Thumb functions to work
17854 correctly. */
b99bd4ef 17855
c19d1205 17856 THUMB_SET_FUNC (sym, 1);
b99bd4ef 17857
c19d1205 17858 label_is_thumb_function_name = FALSE;
b99bd4ef 17859 }
07a53e5c 17860
07a53e5c 17861 dwarf2_emit_label (sym);
b99bd4ef
NC		 17862}
17863
c921be7d 17864bfd_boolean
c19d1205 17865arm_data_in_code (void)
b99bd4ef 17866{
c19d1205 17867 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 17868 {
c19d1205
ZW		 17869 *input_line_pointer = '/';
17870 input_line_pointer += 5;
17871 *input_line_pointer = 0;
c921be7d 17872 return TRUE;
b99bd4ef
NC		 17873 }
17874
c921be7d 17875 return FALSE;
b99bd4ef
NC		 17876}
17877
c19d1205
ZW		 17878char *
17879arm_canonicalize_symbol_name (char * name)
b99bd4ef 17880{
c19d1205 17881 int len;
b99bd4ef 17882
c19d1205
ZW		 17883 if (thumb_mode && (len = strlen (name)) > 5
17884 && streq (name + len - 5, "/data"))
17885 *(name + len - 5) = 0;
b99bd4ef 17886
c19d1205 17887 return name;
b99bd4ef 17888}
c19d1205
ZW		 17889\f
17890/* Table of all register names defined by default. The user can
17891 define additional names with .req. Note that all register names
17892 should appear in both upper and lowercase variants. Some registers
17893 also have mixed-case names. */
b99bd4ef 17894
dcbf9037 17895#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 17896#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 17897#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW		 17898#define REGSET(p,t) \
17899 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17900 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17901 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17902 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB		 17903#define REGSETH(p,t) \
17904 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17905 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17906 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17907 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17908#define REGSET2(p,t) \
17909 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17910 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17911 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17912 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD		 17913#define SPLRBANK(base,bank,t) \
17914 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17915 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17916 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17917 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17918 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17919 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 17920
c19d1205 17921static const struct reg_entry reg_names[] =
7ed4c4c5 17922{
c19d1205
ZW		 17923 /* ARM integer registers. */
17924 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 17925
c19d1205
ZW		 17926 /* ATPCS synonyms. */
17927 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17928 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17929 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 17930
c19d1205
ZW		 17931 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17932 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17933 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 17934
c19d1205
ZW		 17935 /* Well-known aliases. */
17936 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17937 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17938
17939 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17940 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17941
17942 /* Coprocessor numbers. */
17943 REGSET(p, CP), REGSET(P, CP),
17944
17945 /* Coprocessor register numbers. The "cr" variants are for backward
17946 compatibility. */
17947 REGSET(c, CN), REGSET(C, CN),
17948 REGSET(cr, CN), REGSET(CR, CN),
17949
90ec0d68
MGD		 17950 /* ARM banked registers. */
17951 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17952 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17953 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17954 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17955 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17956 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17957 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17958
17959 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17960 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17961 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17962 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17963 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 17964 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD		 17965 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17966 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17967
17968 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17969 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17970 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17971 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17972 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17973 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17974 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 17975 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD		 17976 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17977
c19d1205
ZW		 17978 /* FPA registers. */
17979 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17980 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17981
17982 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17983 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17984
17985 /* VFP SP registers. */
5287ad62
JB		 17986 REGSET(s,VFS), REGSET(S,VFS),
17987 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW		 17988
17989 /* VFP DP Registers. */
5287ad62
JB		 17990 REGSET(d,VFD), REGSET(D,VFD),
17991 /* Extra Neon DP registers. */
17992 REGSETH(d,VFD), REGSETH(D,VFD),
17993
17994 /* Neon QP registers. */
17995 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW		 17996
17997 /* VFP control registers. */
17998 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
17999 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB		 18000 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
18001 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
18002 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
18003 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
c19d1205
ZW		 18004
18005 /* Maverick DSP coprocessor registers. */
18006 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
18007 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
18008
18009 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
18010 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
18011 REGDEF(dspsc,0,DSPSC),
18012
18013 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
18014 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
18015 REGDEF(DSPSC,0,DSPSC),
18016
18017 /* iWMMXt data registers - p0, c0-15. */
18018 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
18019
18020 /* iWMMXt control registers - p1, c0-3. */
18021 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
18022 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
18023 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
18024 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
18025
18026 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18027 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
18028 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
18029 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
18030 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
18031
18032 /* XScale accumulator registers. */
18033 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
18034};
18035#undef REGDEF
18036#undef REGNUM
18037#undef REGSET
7ed4c4c5 18038
c19d1205
ZW		 18039/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18040 within psr_required_here. */
18041static const struct asm_psr psrs[] =
18042{
18043 /* Backward compatibility notation. Note that "all" is no longer
18044 truly all possible PSR bits. */
18045 {"all", PSR_c | PSR_f},
18046 {"flg", PSR_f},
18047 {"ctl", PSR_c},
18048
18049 /* Individual flags. */
18050 {"f", PSR_f},
18051 {"c", PSR_c},
18052 {"x", PSR_x},
18053 {"s", PSR_s},
59b42a0d 18054
c19d1205
ZW		 18055 /* Combinations of flags. */
18056 {"fs", PSR_f | PSR_s},
18057 {"fx", PSR_f | PSR_x},
18058 {"fc", PSR_f | PSR_c},
18059 {"sf", PSR_s | PSR_f},
18060 {"sx", PSR_s | PSR_x},
18061 {"sc", PSR_s | PSR_c},
18062 {"xf", PSR_x | PSR_f},
18063 {"xs", PSR_x | PSR_s},
18064 {"xc", PSR_x | PSR_c},
18065 {"cf", PSR_c | PSR_f},
18066 {"cs", PSR_c | PSR_s},
18067 {"cx", PSR_c | PSR_x},
18068 {"fsx", PSR_f | PSR_s | PSR_x},
18069 {"fsc", PSR_f | PSR_s | PSR_c},
18070 {"fxs", PSR_f | PSR_x | PSR_s},
18071 {"fxc", PSR_f | PSR_x | PSR_c},
18072 {"fcs", PSR_f | PSR_c | PSR_s},
18073 {"fcx", PSR_f | PSR_c | PSR_x},
18074 {"sfx", PSR_s | PSR_f | PSR_x},
18075 {"sfc", PSR_s | PSR_f | PSR_c},
18076 {"sxf", PSR_s | PSR_x | PSR_f},
18077 {"sxc", PSR_s | PSR_x | PSR_c},
18078 {"scf", PSR_s | PSR_c | PSR_f},
18079 {"scx", PSR_s | PSR_c | PSR_x},
18080 {"xfs", PSR_x | PSR_f | PSR_s},
18081 {"xfc", PSR_x | PSR_f | PSR_c},
18082 {"xsf", PSR_x | PSR_s | PSR_f},
18083 {"xsc", PSR_x | PSR_s | PSR_c},
18084 {"xcf", PSR_x | PSR_c | PSR_f},
18085 {"xcs", PSR_x | PSR_c | PSR_s},
18086 {"cfs", PSR_c | PSR_f | PSR_s},
18087 {"cfx", PSR_c | PSR_f | PSR_x},
18088 {"csf", PSR_c | PSR_s | PSR_f},
18089 {"csx", PSR_c | PSR_s | PSR_x},
18090 {"cxf", PSR_c | PSR_x | PSR_f},
18091 {"cxs", PSR_c | PSR_x | PSR_s},
18092 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
18093 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
18094 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
18095 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
18096 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
18097 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
18098 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
18099 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
18100 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
18101 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
18102 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
18103 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
18104 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
18105 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
18106 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
18107 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
18108 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
18109 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
18110 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
18111 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
18112 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
18113 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
18114 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
18115 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
18116};
18117
62b3e311
PB		 18118/* Table of V7M psr names. */
18119static const struct asm_psr v7m_psrs[] =
18120{
2b744c99
PB		 18121 {"apsr", 0 }, {"APSR", 0 },
18122 {"iapsr", 1 }, {"IAPSR", 1 },
18123 {"eapsr", 2 }, {"EAPSR", 2 },
18124 {"psr", 3 }, {"PSR", 3 },
18125 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18126 {"ipsr", 5 }, {"IPSR", 5 },
18127 {"epsr", 6 }, {"EPSR", 6 },
18128 {"iepsr", 7 }, {"IEPSR", 7 },
18129 {"msp", 8 }, {"MSP", 8 },
18130 {"psp", 9 }, {"PSP", 9 },
18131 {"primask", 16}, {"PRIMASK", 16},
18132 {"basepri", 17}, {"BASEPRI", 17},
00bbc0bd
NC		 18133 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18134 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
2b744c99
PB		 18135 {"faultmask", 19}, {"FAULTMASK", 19},
18136 {"control", 20}, {"CONTROL", 20}
62b3e311
PB		 18137};
18138
c19d1205
ZW		 18139/* Table of all shift-in-operand names. */
18140static const struct asm_shift_name shift_names [] =
b99bd4ef 18141{
c19d1205
ZW		 18142 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
18143 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
18144 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
18145 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
18146 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
18147 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
18148};
b99bd4ef 18149
c19d1205
ZW		 18150/* Table of all explicit relocation names. */
18151#ifdef OBJ_ELF
18152static struct reloc_entry reloc_names[] =
18153{
18154 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
18155 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
18156 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
18157 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
18158 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
18159 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
18160 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
18161 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
18162 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
18163 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 18164 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS		 18165 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
18166 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 18167 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 18168 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 18169 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 18170 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
477330fc 18171 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
c19d1205
ZW		 18172};
18173#endif
b99bd4ef 18174
c19d1205
ZW		 18175/* Table of all conditional affixes. 0xF is not defined as a condition code. */
18176static const struct asm_cond conds[] =
18177{
18178 {"eq", 0x0},
18179 {"ne", 0x1},
18180 {"cs", 0x2}, {"hs", 0x2},
18181 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18182 {"mi", 0x4},
18183 {"pl", 0x5},
18184 {"vs", 0x6},
18185 {"vc", 0x7},
18186 {"hi", 0x8},
18187 {"ls", 0x9},
18188 {"ge", 0xa},
18189 {"lt", 0xb},
18190 {"gt", 0xc},
18191 {"le", 0xd},
18192 {"al", 0xe}
18193};
bfae80f2 18194
e797f7e0
MGD		 18195#define UL_BARRIER(L,U,CODE,FEAT) \
18196 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
18197 { U, CODE, ARM_FEATURE (FEAT, 0) }
18198
62b3e311
PB		 18199static struct asm_barrier_opt barrier_opt_names[] =
18200{
e797f7e0
MGD		 18201 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
18202 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
18203 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
18204 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
18205 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
18206 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
18207 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
18208 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
18209 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
18210 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
18211 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
18212 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
18213 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
18214 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
18215 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
18216 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB		 18217};
18218
e797f7e0
MGD		 18219#undef UL_BARRIER
18220
c19d1205
ZW		 18221/* Table of ARM-format instructions. */
18222
18223/* Macros for gluing together operand strings. N.B. In all cases
18224 other than OPS0, the trailing OP_stop comes from default
18225 zero-initialization of the unspecified elements of the array. */
18226#define OPS0() { OP_stop, }
18227#define OPS1(a) { OP_##a, }
18228#define OPS2(a,b) { OP_##a,OP_##b, }
18229#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18230#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18231#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18232#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18233
5be8be5d
DG		 18234/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18235 This is useful when mixing operands for ARM and THUMB, i.e. using the
18236 MIX_ARM_THUMB_OPERANDS macro.
18237 In order to use these macros, prefix the number of operands with _
18238 e.g. _3. */
18239#define OPS_1(a) { a, }
18240#define OPS_2(a,b) { a,b, }
18241#define OPS_3(a,b,c) { a,b,c, }
18242#define OPS_4(a,b,c,d) { a,b,c,d, }
18243#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18244#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18245
c19d1205
ZW		 18246/* These macros abstract out the exact format of the mnemonic table and
18247 save some repeated characters. */
18248
18249/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18250#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 18251 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
1887dd22 18252 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW		 18253
18254/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18255 a T_MNEM_xyz enumerator. */
18256#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 18257 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 18258#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 18259 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW		 18260
18261/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18262 infix after the third character. */
18263#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 18264 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
1887dd22 18265 THUMB_VARIANT, do_##ae, do_##te }
088fa78e 18266#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 18267 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
088fa78e 18268 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 18269#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 18270 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 18271#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 18272 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 18273#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 18274 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 18275#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 18276 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 18277
c19d1205 18278/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB		 18279 field is still 0xE. Many of the Thumb variants can be executed
18280 conditionally, so this is checked separately. */
c19d1205 18281#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 18282 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 18283 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 18284
dd5181d5
KT		 18285/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18286 Used by mnemonics that have very minimal differences in the encoding for
18287 ARM and Thumb variants and can be handled in a common function. */
18288#define TUEc(mnem, op, top, nops, ops, en) \
18289 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18290 THUMB_VARIANT, do_##en, do_##en }
18291
c19d1205
ZW		 18292/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18293 condition code field. */
18294#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 18295 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 18296 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW		 18297
18298/* ARM-only variants of all the above. */
6a86118a 18299#define CE(mnem, op, nops, ops, ae) \
21d799b5 18300 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
6a86118a
NC		 18301
18302#define C3(mnem, op, nops, ops, ae) \
18303 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18304
e3cb604e
PB		 18305/* Legacy mnemonics that always have conditional infix after the third
18306 character. */
18307#define CL(mnem, op, nops, ops, ae) \
21d799b5 18308 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB		 18309 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18310
8f06b2d8
PB		 18311/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18312#define cCE(mnem, op, nops, ops, ae) \
21d799b5 18313 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 18314
e3cb604e
PB		 18315/* Legacy coprocessor instructions where conditional infix and conditional
18316 suffix are ambiguous. For consistency this includes all FPA instructions,
18317 not just the potentially ambiguous ones. */
18318#define cCL(mnem, op, nops, ops, ae) \
21d799b5 18319 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB		 18320 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18321
18322/* Coprocessor, takes either a suffix or a position-3 infix
18323 (for an FPA corner case). */
18324#define C3E(mnem, op, nops, ops, ae) \
21d799b5 18325 { mnem, OPS##nops ops, OT_csuf_or_in3, \
e3cb604e 18326 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 18327
6a86118a 18328#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC		 18329 { m1 #m2 m3, OPS##nops ops, \
18330 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
6a86118a
NC		 18331 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18332
18333#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC		 18334 xCM_ (m1, , m2, op, nops, ops, ae), \
18335 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18336 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18337 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18338 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18339 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18340 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18341 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18342 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18343 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18344 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18345 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18346 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18347 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18348 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18349 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18350 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18351 xCM_ (m1, le, m2, op, nops, ops, ae), \
18352 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC		 18353
18354#define UE(mnem, op, nops, ops, ae) \
18355 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18356
18357#define UF(mnem, op, nops, ops, ae) \
18358 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18359
5287ad62
JB		 18360/* Neon data-processing. ARM versions are unconditional with cond=0xf.
18361 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18362 use the same encoding function for each. */
18363#define NUF(mnem, op, nops, ops, enc) \
18364 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18365 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18366
18367/* Neon data processing, version which indirects through neon_enc_tab for
18368 the various overloaded versions of opcodes. */
18369#define nUF(mnem, op, nops, ops, enc) \
21d799b5 18370 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5287ad62
JB		 18371 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18372
18373/* Neon insn with conditional suffix for the ARM version, non-overloaded
18374 version. */
037e8744
JB		 18375#define NCE_tag(mnem, op, nops, ops, enc, tag) \
18376 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5287ad62
JB		 18377 THUMB_VARIANT, do_##enc, do_##enc }
18378
037e8744 18379#define NCE(mnem, op, nops, ops, enc) \
e07e6e58 18380 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB		 18381
18382#define NCEF(mnem, op, nops, ops, enc) \
e07e6e58 18383 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 18384
5287ad62 18385/* Neon insn with conditional suffix for the ARM version, overloaded types. */
037e8744 18386#define nCE_tag(mnem, op, nops, ops, enc, tag) \
21d799b5 18387 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5287ad62
JB		 18388 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18389
037e8744 18390#define nCE(mnem, op, nops, ops, enc) \
e07e6e58 18391 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB		 18392
18393#define nCEF(mnem, op, nops, ops, enc) \
e07e6e58 18394 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 18395
c19d1205
ZW		 18396#define do_0 0
18397
c19d1205 18398static const struct asm_opcode insns[] =
bfae80f2 18399{
74db7efb
NC		 18400#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18401#define THUMB_VARIANT & arm_ext_v4t
21d799b5
NC		 18402 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
18403 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
18404 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
18405 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
18406 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
18407 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
18408 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
18409 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
18410 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
18411 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
18412 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
18413 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
18414 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
18415 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18416 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18417 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW		 18418
18419 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18420 for setting PSR flag bits. They are obsolete in V6 and do not
18421 have Thumb equivalents. */
21d799b5
NC		 18422 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18423 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18424 CL("tstp", 110f000, 2, (RR, SH), cmp),
18425 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18426 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18427 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18428 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18429 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18430 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18431
18432 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18433 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18434 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18435 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18436
18437 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG		 18438 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18439 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18440 OP_RRnpc),
18441 OP_ADDRGLDR),ldst, t_ldst),
18442 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC		 18443
18444 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18445 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18446 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18447 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18448 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18449 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18450
18451 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18452 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18453 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18454 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 18455
c19d1205 18456 /* Pseudo ops. */
21d799b5 18457 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 18458 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 18459 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
74db7efb 18460 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
c19d1205
ZW		 18461
18462 /* Thumb-compatibility pseudo ops. */
21d799b5
NC		 18463 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18464 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18465 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18466 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18467 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18468 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18469 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18470 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18471 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18472 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18473 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18474 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 18475
16a4cf17 18476 /* These may simplify to neg. */
21d799b5
NC		 18477 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18478 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 18479
c921be7d
NC		 18480#undef THUMB_VARIANT
18481#define THUMB_VARIANT & arm_ext_v6
18482
21d799b5 18483 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW		 18484
18485 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC		 18486#undef THUMB_VARIANT
18487#define THUMB_VARIANT & arm_ext_v6t2
18488
21d799b5
NC		 18489 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18490 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18491 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 18492
5be8be5d
DG		 18493 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18494 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18495 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18496 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 18497
21d799b5
NC		 18498 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18499 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 18500
21d799b5
NC		 18501 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18502 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW		 18503
18504 /* V1 instructions with no Thumb analogue at all. */
21d799b5 18505 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW		 18506 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18507
18508 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18509 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18510 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18511 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18512 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18513 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18514 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18515 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18516
c921be7d
NC		 18517#undef ARM_VARIANT
18518#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18519#undef THUMB_VARIANT
18520#define THUMB_VARIANT & arm_ext_v4t
18521
21d799b5
NC		 18522 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18523 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 18524
c921be7d
NC		 18525#undef THUMB_VARIANT
18526#define THUMB_VARIANT & arm_ext_v6t2
18527
21d799b5 18528 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW		 18529 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18530
18531 /* Generic coprocessor instructions. */
21d799b5
NC		 18532 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18533 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18534 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18535 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18536 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18537 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 18538 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 18539
c921be7d
NC		 18540#undef ARM_VARIANT
18541#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18542
21d799b5 18543 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW		 18544 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18545
c921be7d
NC		 18546#undef ARM_VARIANT
18547#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18548#undef THUMB_VARIANT
18549#define THUMB_VARIANT & arm_ext_msr
18550
d2cd1205
JB		 18551 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18552 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 18553
c921be7d
NC		 18554#undef ARM_VARIANT
18555#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18556#undef THUMB_VARIANT
18557#define THUMB_VARIANT & arm_ext_v6t2
18558
21d799b5
NC		 18559 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18560 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18561 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18562 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18563 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18564 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18565 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18566 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 18567
c921be7d
NC		 18568#undef ARM_VARIANT
18569#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18570#undef THUMB_VARIANT
18571#define THUMB_VARIANT & arm_ext_v4t
18572
5be8be5d
DG		 18573 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18574 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18575 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18576 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE		 18577 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18578 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 18579
c921be7d
NC		 18580#undef ARM_VARIANT
18581#define ARM_VARIANT & arm_ext_v4t_5
18582
c19d1205
ZW		 18583 /* ARM Architecture 4T. */
18584 /* Note: bx (and blx) are required on V5, even if the processor does
18585 not support Thumb. */
21d799b5 18586 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 18587
c921be7d
NC		 18588#undef ARM_VARIANT
18589#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18590#undef THUMB_VARIANT
18591#define THUMB_VARIANT & arm_ext_v5t
18592
c19d1205
ZW		 18593 /* Note: blx has 2 variants; the .value coded here is for
18594 BLX(2). Only this variant has conditional execution. */
21d799b5
NC		 18595 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18596 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 18597
c921be7d
NC		 18598#undef THUMB_VARIANT
18599#define THUMB_VARIANT & arm_ext_v6t2
18600
21d799b5
NC		 18601 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18602 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18603 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18604 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18605 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18606 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18607 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18608 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 18609
c921be7d 18610#undef ARM_VARIANT
74db7efb
NC		 18611#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18612#undef THUMB_VARIANT
18613#define THUMB_VARIANT & arm_ext_v5exp
c921be7d 18614
21d799b5
NC		 18615 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18616 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18617 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18618 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 18619
21d799b5
NC		 18620 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18621 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 18622
21d799b5
NC		 18623 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18624 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18625 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18626 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 18627
21d799b5
NC		 18628 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18629 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18630 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18631 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 18632
21d799b5
NC		 18633 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18634 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 18635
03ee1b7f
NC		 18636 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18637 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18638 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18639 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 18640
c921be7d 18641#undef ARM_VARIANT
74db7efb
NC		 18642#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18643#undef THUMB_VARIANT
18644#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 18645
21d799b5 18646 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG		 18647 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18648 ldrd, t_ldstd),
18649 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18650 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 18651
21d799b5
NC		 18652 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18653 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 18654
c921be7d
NC		 18655#undef ARM_VARIANT
18656#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18657
21d799b5 18658 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 18659
c921be7d
NC		 18660#undef ARM_VARIANT
18661#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18662#undef THUMB_VARIANT
18663#define THUMB_VARIANT & arm_ext_v6
18664
21d799b5
NC		 18665 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18666 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18667 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18668 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18669 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18670 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18671 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18672 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18673 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18674 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 18675
c921be7d
NC		 18676#undef THUMB_VARIANT
18677#define THUMB_VARIANT & arm_ext_v6t2
18678
5be8be5d
DG		 18679 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18680 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18681 strex, t_strex),
21d799b5
NC		 18682 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18683 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 18684
21d799b5
NC		 18685 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18686 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 18687
9e3c6df6 18688/* ARM V6 not included in V7M. */
c921be7d
NC		 18689#undef THUMB_VARIANT
18690#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 18691 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 18692 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB		 18693 UF(rfeib, 9900a00, 1, (RRw), rfe),
18694 UF(rfeda, 8100a00, 1, (RRw), rfe),
18695 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18696 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE		 18697 UF(rfefa, 8100a00, 1, (RRw), rfe),
18698 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18699 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 18700 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE		 18701 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18702 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 18703 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 18704 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 18705 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 18706 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 18707 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 18708 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
c921be7d 18709
9e3c6df6
PB		 18710/* ARM V6 not included in V7M (eg. integer SIMD). */
18711#undef THUMB_VARIANT
18712#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC		 18713 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18714 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18715 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18716 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18717 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18718 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18719 /* Old name for QASX. */
74db7efb 18720 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 18721 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18722 /* Old name for QSAX. */
74db7efb 18723 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18724 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18725 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18726 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18727 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18728 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18729 /* Old name for SASX. */
74db7efb 18730 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18731 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18732 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18733 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18734 /* Old name for SHASX. */
21d799b5 18735 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18736 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18737 /* Old name for SHSAX. */
21d799b5
NC		 18738 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18739 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18740 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18741 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18742 /* Old name for SSAX. */
74db7efb 18743 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18744 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18745 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18746 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18747 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18748 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18749 /* Old name for UASX. */
74db7efb 18750 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18751 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18752 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18753 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18754 /* Old name for UHASX. */
21d799b5
NC		 18755 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18756 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18757 /* Old name for UHSAX. */
21d799b5
NC		 18758 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18759 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18760 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18761 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18762 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18763 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18764 /* Old name for UQASX. */
21d799b5
NC		 18765 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18766 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18767 /* Old name for UQSAX. */
21d799b5
NC		 18768 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18769 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18770 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18771 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18772 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18773 /* Old name for USAX. */
74db7efb 18774 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 18775 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18776 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18777 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18778 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18779 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18780 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18781 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18782 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18783 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18784 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18785 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18786 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18787 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18788 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18789 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18790 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18791 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18792 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18793 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18794 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18795 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18796 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18797 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18798 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18799 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18800 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18801 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18802 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC		 18803 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18804 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18805 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18806 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18807 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 18808
c921be7d
NC		 18809#undef ARM_VARIANT
18810#define ARM_VARIANT & arm_ext_v6k
18811#undef THUMB_VARIANT
18812#define THUMB_VARIANT & arm_ext_v6k
18813
21d799b5
NC		 18814 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18815 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18816 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18817 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 18818
c921be7d
NC		 18819#undef THUMB_VARIANT
18820#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG		 18821 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18822 ldrexd, t_ldrexd),
18823 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18824 RRnpcb), strexd, t_strexd),
ebdca51a 18825
c921be7d
NC		 18826#undef THUMB_VARIANT
18827#define THUMB_VARIANT & arm_ext_v6t2
5be8be5d
DG		 18828 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18829 rd_rn, rd_rn),
18830 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18831 rd_rn, rd_rn),
18832 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 18833 strex, t_strexbh),
5be8be5d 18834 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 18835 strex, t_strexbh),
21d799b5 18836 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 18837
c921be7d 18838#undef ARM_VARIANT
f4c65163 18839#define ARM_VARIANT & arm_ext_sec
74db7efb 18840#undef THUMB_VARIANT
f4c65163 18841#define THUMB_VARIANT & arm_ext_sec
c921be7d 18842
21d799b5 18843 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 18844
90ec0d68
MGD		 18845#undef ARM_VARIANT
18846#define ARM_VARIANT & arm_ext_virt
18847#undef THUMB_VARIANT
18848#define THUMB_VARIANT & arm_ext_virt
18849
18850 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18851 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18852
c921be7d 18853#undef ARM_VARIANT
74db7efb 18854#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD		 18855#undef THUMB_VARIANT
18856#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 18857
21d799b5
NC		 18858 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18859 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18860 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18861 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 18862
21d799b5
NC		 18863 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18864 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18865 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18866 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 18867
5be8be5d
DG		 18868 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18869 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18870 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18871 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 18872
bf3eeda7 18873 /* Thumb-only instructions. */
74db7efb 18874#undef ARM_VARIANT
bf3eeda7
NS		 18875#define ARM_VARIANT NULL
18876 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18877 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC		 18878
18879 /* ARM does not really have an IT instruction, so always allow it.
18880 The opcode is copied from Thumb in order to allow warnings in
18881 -mimplicit-it=[never | arm] modes. */
18882#undef ARM_VARIANT
18883#define ARM_VARIANT & arm_ext_v1
18884
21d799b5
NC		 18885 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18886 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18887 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18888 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18889 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18890 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18891 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18892 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18893 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18894 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18895 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18896 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18897 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18898 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18899 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 18900 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC		 18901 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18902 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 18903
92e90b6e 18904 /* Thumb2 only instructions. */
c921be7d
NC		 18905#undef ARM_VARIANT
18906#define ARM_VARIANT NULL
92e90b6e 18907
21d799b5
NC		 18908 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18909 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18910 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18911 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18912 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18913 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 18914
eea54501
MGD		 18915 /* Hardware division instructions. */
18916#undef ARM_VARIANT
18917#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC		 18918#undef THUMB_VARIANT
18919#define THUMB_VARIANT & arm_ext_div
18920
eea54501
MGD		 18921 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18922 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 18923
7e806470 18924 /* ARM V6M/V7 instructions. */
c921be7d
NC		 18925#undef ARM_VARIANT
18926#define ARM_VARIANT & arm_ext_barrier
18927#undef THUMB_VARIANT
18928#define THUMB_VARIANT & arm_ext_barrier
18929
ccb84d65
JB		 18930 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18931 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18932 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 18933
62b3e311 18934 /* ARM V7 instructions. */
c921be7d
NC		 18935#undef ARM_VARIANT
18936#define ARM_VARIANT & arm_ext_v7
18937#undef THUMB_VARIANT
18938#define THUMB_VARIANT & arm_ext_v7
18939
21d799b5
NC		 18940 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18941 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 18942
74db7efb 18943#undef ARM_VARIANT
60e5ef9f 18944#define ARM_VARIANT & arm_ext_mp
74db7efb 18945#undef THUMB_VARIANT
60e5ef9f
MGD		 18946#define THUMB_VARIANT & arm_ext_mp
18947
18948 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18949
53c4b28b
MGD		 18950 /* AArchv8 instructions. */
18951#undef ARM_VARIANT
18952#define ARM_VARIANT & arm_ext_v8
18953#undef THUMB_VARIANT
18954#define THUMB_VARIANT & arm_ext_v8
18955
18956 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
8884b720 18957 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
4b8c8c02
RE		 18958 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18959 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
9eb6c0f1 18960 ldrexd, t_ldrexd),
4b8c8c02
RE		 18961 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18962 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18963 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18964 stlex, t_stlex),
18965 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
9eb6c0f1 18966 strexd, t_strexd),
4b8c8c02
RE		 18967 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18968 stlex, t_stlex),
18969 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18970 stlex, t_stlex),
18971 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18972 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18973 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18974 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18975 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18976 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
53c4b28b 18977
8884b720 18978 /* ARMv8 T32 only. */
74db7efb 18979#undef ARM_VARIANT
b79f7053
MGD		 18980#define ARM_VARIANT NULL
18981 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18982 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18983 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18984
33399f07
MGD		 18985 /* FP for ARMv8. */
18986#undef ARM_VARIANT
a715796b 18987#define ARM_VARIANT & fpu_vfp_ext_armv8xd
33399f07 18988#undef THUMB_VARIANT
a715796b 18989#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
33399f07
MGD		 18990
18991 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
18992 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
18993 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
18994 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
73924fbc
MGD		 18995 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
18996 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
7e8e6784
MGD		 18997 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
18998 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
18999 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
19000 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
30bdf752
MGD		 19001 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
19002 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
19003 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
19004 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
19005 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
19006 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
19007 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
33399f07 19008
91ff7894
MGD		 19009 /* Crypto v1 extensions. */
19010#undef ARM_VARIANT
19011#define ARM_VARIANT & fpu_crypto_ext_armv8
19012#undef THUMB_VARIANT
19013#define THUMB_VARIANT & fpu_crypto_ext_armv8
19014
19015 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
19016 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
19017 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
19018 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD		 19019 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
19020 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
19021 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
19022 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
19023 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
19024 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
19025 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD		 19026 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
19027 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
19028 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 19029
dd5181d5 19030#undef ARM_VARIANT
74db7efb 19031#define ARM_VARIANT & crc_ext_armv8
dd5181d5
KT		 19032#undef THUMB_VARIANT
19033#define THUMB_VARIANT & crc_ext_armv8
19034 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
19035 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
19036 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
19037 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
19038 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
19039 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
19040
c921be7d
NC		 19041#undef ARM_VARIANT
19042#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD		 19043#undef THUMB_VARIANT
19044#define THUMB_VARIANT NULL
c921be7d 19045
21d799b5
NC		 19046 cCE("wfs", e200110, 1, (RR), rd),
19047 cCE("rfs", e300110, 1, (RR), rd),
19048 cCE("wfc", e400110, 1, (RR), rd),
19049 cCE("rfc", e500110, 1, (RR), rd),
19050
19051 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
19052 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
19053 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
19054 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
19055
19056 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
19057 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
19058 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
19059 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
19060
19061 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
19062 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
19063 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
19064 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
19065 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
19066 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
19067 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
19068 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
19069 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
19070 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
19071 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
19072 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
19073
19074 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
19075 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
19076 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
19077 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
19078 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
19079 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
19080 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
19081 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
19082 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
19083 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
19084 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
19085 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
19086
19087 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
19088 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
19089 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
19090 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
19091 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
19092 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
19093 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
19094 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
19095 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
19096 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
19097 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
19098 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
19099
19100 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
19101 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
19102 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
19103 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
19104 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
19105 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
19106 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
19107 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
19108 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
19109 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
19110 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
19111 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
19112
19113 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
19114 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
19115 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
19116 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
19117 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
19118 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
19119 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
19120 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
19121 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
19122 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
19123 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
19124 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
19125
19126 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
19127 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
19128 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
19129 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
19130 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
19131 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
19132 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
19133 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
19134 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
19135 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
19136 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
19137 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
19138
19139 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
19140 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
19141 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
19142 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
19143 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
19144 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
19145 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
19146 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
19147 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
19148 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
19149 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
19150 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
19151
19152 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
19153 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
19154 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
19155 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
19156 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
19157 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
19158 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
19159 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
19160 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
19161 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
19162 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
19163 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
19164
19165 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
19166 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
19167 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
19168 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
19169 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
19170 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
19171 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
19172 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
19173 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
19174 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
19175 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
19176 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
19177
19178 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
19179 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
19180 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
19181 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
19182 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
19183 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
19184 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
19185 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
19186 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
19187 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
19188 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
19189 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
19190
19191 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
19192 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
19193 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
19194 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
19195 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
19196 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
19197 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
19198 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
19199 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
19200 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
19201 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
19202 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
19203
19204 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
19205 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
19206 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
19207 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
19208 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
19209 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
19210 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
19211 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
19212 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
19213 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
19214 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
19215 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
19216
19217 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
19218 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
19219 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
19220 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
19221 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
19222 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
19223 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
19224 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
19225 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
19226 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
19227 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
19228 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
19229
19230 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
19231 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
19232 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
19233 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
19234 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
19235 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
19236 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
19237 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
19238 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
19239 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
19240 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
19241 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
19242
19243 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
19244 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
19245 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
19246 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
19247 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
19248 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
19249 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
19250 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
19251 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
19252 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
19253 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
19254 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
19255
19256 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
19257 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
19258 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
19259 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
19260 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
19261 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
19262 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
19263 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
19264 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
19265 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
19266 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
19267 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
19268
19269 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
19270 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
19271 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
19272 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
19273 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
19274 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19275 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19276 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19277 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
19278 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
19279 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
19280 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
19281
19282 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
19283 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
19284 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
19285 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
19286 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
19287 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19288 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19289 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19290 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
19291 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
19292 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
19293 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
19294
19295 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
19296 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
19297 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
19298 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
19299 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
19300 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19301 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19302 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19303 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
19304 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
19305 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
19306 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
19307
19308 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
19309 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
19310 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
19311 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
19312 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
19313 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19314 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19315 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19316 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
19317 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
19318 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
19319 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
19320
19321 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
19322 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
19323 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
19324 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
19325 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
19326 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19327 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19328 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19329 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
19330 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
19331 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
19332 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
19333
19334 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
19335 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
19336 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
19337 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
19338 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
19339 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19340 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19341 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19342 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
19343 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
19344 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
19345 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
19346
19347 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
19348 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
19349 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
19350 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
19351 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
19352 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19353 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19354 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19355 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
19356 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
19357 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
19358 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
19359
19360 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
19361 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
19362 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
19363 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
19364 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
19365 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19366 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19367 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19368 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
19369 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
19370 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
19371 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
19372
19373 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
19374 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
19375 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
19376 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
19377 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
19378 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19379 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19380 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19381 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
19382 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
19383 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
19384 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
19385
19386 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
19387 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
19388 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
19389 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
19390 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
19391 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19392 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19393 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19394 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
19395 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
19396 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
19397 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
19398
19399 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19400 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19401 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19402 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19403 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19404 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19405 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19406 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19407 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19408 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19409 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19410 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19411
19412 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19413 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19414 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19415 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19416 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19417 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19418 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19419 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19420 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19421 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19422 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19423 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19424
19425 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19426 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19427 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19428 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19429 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19430 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19431 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19432 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19433 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19434 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19435 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19436 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19437
19438 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19439 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19440 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19441 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19442
19443 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19444 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19445 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19446 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19447 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19448 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19449 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19450 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19451 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19452 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19453 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19454 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 19455
c19d1205
ZW		 19456 /* The implementation of the FIX instruction is broken on some
19457 assemblers, in that it accepts a precision specifier as well as a
19458 rounding specifier, despite the fact that this is meaningless.
19459 To be more compatible, we accept it as well, though of course it
19460 does not set any bits. */
21d799b5
NC		 19461 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19462 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19463 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19464 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19465 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19466 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19467 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19468 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19469 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19470 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19471 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19472 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19473 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 19474
c19d1205 19475 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC		 19476#undef ARM_VARIANT
19477#define ARM_VARIANT & fpu_fpa_ext_v2
19478
21d799b5
NC		 19479 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19480 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19481 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19482 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19483 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19484 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 19485
c921be7d
NC		 19486#undef ARM_VARIANT
19487#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19488
c19d1205 19489 /* Moves and type conversions. */
21d799b5
NC		 19490 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19491 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19492 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19493 cCE("fmstat", ef1fa10, 0, (), noargs),
7465e07a
NC		 19494 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19495 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
21d799b5
NC		 19496 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19497 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19498 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19499 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19500 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19501 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19502 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19503 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW		 19504
19505 /* Memory operations. */
21d799b5
NC		 19506 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19507 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD		 19508 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19509 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19510 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19511 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19512 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19513 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19514 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19515 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19516 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19517 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19518 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19519 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19520 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19521 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19522 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19523 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 19524
c19d1205 19525 /* Monadic operations. */
21d799b5
NC		 19526 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19527 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19528 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW		 19529
19530 /* Dyadic operations. */
21d799b5
NC		 19531 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19532 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19533 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19534 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19535 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19536 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19537 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19538 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19539 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 19540
c19d1205 19541 /* Comparisons. */
21d799b5
NC		 19542 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19543 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19544 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19545 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 19546
62f3b8c8
PB		 19547 /* Double precision load/store are still present on single precision
19548 implementations. */
19549 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19550 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD		 19551 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19552 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19553 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19554 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19555 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19556 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19557 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19558 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 19559
c921be7d
NC		 19560#undef ARM_VARIANT
19561#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19562
c19d1205 19563 /* Moves and type conversions. */
21d799b5
NC		 19564 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19565 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19566 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19567 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19568 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19569 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19570 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19571 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19572 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19573 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19574 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19575 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19576 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 19577
c19d1205 19578 /* Monadic operations. */
21d799b5
NC		 19579 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19580 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19581 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW		 19582
19583 /* Dyadic operations. */
21d799b5
NC		 19584 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19585 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19586 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19587 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19588 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19589 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19590 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19591 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19592 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 19593
c19d1205 19594 /* Comparisons. */
21d799b5
NC		 19595 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19596 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19597 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19598 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 19599
c921be7d
NC		 19600#undef ARM_VARIANT
19601#define ARM_VARIANT & fpu_vfp_ext_v2
19602
21d799b5
NC		 19603 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19604 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19605 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19606 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
5287ad62 19607
037e8744
JB		 19608/* Instructions which may belong to either the Neon or VFP instruction sets.
19609 Individual encoder functions perform additional architecture checks. */
c921be7d
NC		 19610#undef ARM_VARIANT
19611#define ARM_VARIANT & fpu_vfp_ext_v1xd
19612#undef THUMB_VARIANT
19613#define THUMB_VARIANT & fpu_vfp_ext_v1xd
19614
037e8744
JB		 19615 /* These mnemonics are unique to VFP. */
19616 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19617 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC		 19618 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19619 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19620 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
aacf0b33
KT		 19621 nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
19622 nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
037e8744
JB		 19623 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19624 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19625 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19626
19627 /* Mnemonics shared by Neon and VFP. */
21d799b5
NC		 19628 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19629 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19630 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 19631
21d799b5
NC		 19632 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19633 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
037e8744
JB		 19634
19635 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19636 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19637
55881a11
MGD		 19638 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19639 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19640 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19641 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19642 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19643 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
4962c51a
MS		 19644 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19645 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
037e8744 19646
5f1af56b 19647 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
e3e535bc 19648 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
c70a8987
MGD		 19649 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19650 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
f31fef98 19651
037e8744
JB		 19652
19653 /* NOTE: All VMOV encoding is special-cased! */
19654 NCE(vmov, 0, 1, (VMOV), neon_mov),
19655 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19656
c921be7d
NC		 19657#undef THUMB_VARIANT
19658#define THUMB_VARIANT & fpu_neon_ext_v1
19659#undef ARM_VARIANT
19660#define ARM_VARIANT & fpu_neon_ext_v1
19661
5287ad62
JB		 19662 /* Data processing with three registers of the same length. */
19663 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19664 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19665 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19666 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19667 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19668 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19669 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19670 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19671 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19672 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19673 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19674 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19675 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19676 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7
JB		 19677 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19678 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19679 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19680 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62
JB		 19681 /* If not immediate, fall back to neon_dyadic_i64_su.
19682 shl_imm should accept I8 I16 I32 I64,
19683 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21d799b5
NC		 19684 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19685 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19686 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19687 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
5287ad62 19688 /* Logic ops, types optional & ignored. */
4316f0d2
DG		 19689 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19690 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19691 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19692 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19693 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19694 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19695 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19696 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19697 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19698 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB		 19699 /* Bitfield ops, untyped. */
19700 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19701 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19702 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19703 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19704 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19705 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19706 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
21d799b5
NC		 19707 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19708 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19709 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19710 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19711 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19712 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB		 19713 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19714 back to neon_dyadic_if_su. */
21d799b5
NC		 19715 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19716 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19717 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19718 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19719 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19720 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19721 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19722 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 19723 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC		 19724 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19725 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 19726 /* As above, D registers only. */
21d799b5
NC		 19727 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19728 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 19729 /* Int and float variants, signedness unimportant. */
21d799b5
NC		 19730 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19731 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19732 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 19733 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC		 19734 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19735 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB		 19736 /* vtst takes sizes 8, 16, 32. */
19737 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19738 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19739 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 19740 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 19741 /* VQD{R}MULH takes S16 S32. */
21d799b5
NC		 19742 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19743 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19744 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19745 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB		 19746 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19747 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19748 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19749 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB		 19750 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19751 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19752 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19753 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB		 19754 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19755 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19756 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19757 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19758
19759 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 19760 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB		 19761 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19762
19763 /* Data processing with two registers and a shift amount. */
19764 /* Right shifts, and variants with rounding.
19765 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19766 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19767 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19768 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19769 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19770 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19771 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19772 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19773 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19774 /* Shift and insert. Sizes accepted 8 16 32 64. */
19775 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19776 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19777 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19778 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19779 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19780 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19781 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19782 /* Right shift immediate, saturating & narrowing, with rounding variants.
19783 Types accepted S16 S32 S64 U16 U32 U64. */
19784 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19785 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19786 /* As above, unsigned. Types accepted S16 S32 S64. */
19787 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19788 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19789 /* Right shift narrowing. Types accepted I16 I32 I64. */
19790 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19791 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19792 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 19793 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 19794 /* CVT with optional immediate for fixed-point variant. */
21d799b5 19795 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 19796
4316f0d2
DG		 19797 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19798 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB		 19799
19800 /* Data processing, three registers of different lengths. */
19801 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19802 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19803 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19804 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19805 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19806 /* If not scalar, fall back to neon_dyadic_long.
19807 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC		 19808 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19809 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB		 19810 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19811 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19812 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19813 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19814 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19815 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19816 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19817 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19818 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC		 19819 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19820 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19821 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB		 19822 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19823 S16 S32 U16 U32. */
21d799b5 19824 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB		 19825
19826 /* Extract. Size 8. */
3b8d421e
PB		 19827 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19828 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB		 19829
19830 /* Two registers, miscellaneous. */
19831 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19832 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19833 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19834 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19835 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19836 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19837 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19838 /* Vector replicate. Sizes 8 16 32. */
21d799b5
NC		 19839 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19840 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB		 19841 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19842 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19843 /* VMOVN. Types I16 I32 I64. */
21d799b5 19844 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 19845 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 19846 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 19847 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 19848 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB		 19849 /* VZIP / VUZP. Sizes 8 16 32. */
19850 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19851 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19852 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19853 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19854 /* VQABS / VQNEG. Types S8 S16 S32. */
19855 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19856 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19857 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19858 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19859 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19860 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19861 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19862 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19863 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19864 /* Reciprocal estimates. Types U32 F32. */
19865 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19866 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19867 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19868 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19869 /* VCLS. Types S8 S16 S32. */
19870 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19871 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19872 /* VCLZ. Types I8 I16 I32. */
19873 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19874 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19875 /* VCNT. Size 8. */
19876 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19877 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19878 /* Two address, untyped. */
19879 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19880 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19881 /* VTRN. Sizes 8 16 32. */
21d799b5
NC		 19882 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19883 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB		 19884
19885 /* Table lookup. Size 8. */
19886 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19887 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19888
c921be7d
NC		 19889#undef THUMB_VARIANT
19890#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19891#undef ARM_VARIANT
19892#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19893
5287ad62 19894 /* Neon element/structure load/store. */
21d799b5
NC		 19895 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19896 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19897 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19898 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19899 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19900 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19901 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19902 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 19903
c921be7d 19904#undef THUMB_VARIANT
74db7efb
NC		 19905#define THUMB_VARIANT & fpu_vfp_ext_v3xd
19906#undef ARM_VARIANT
19907#define ARM_VARIANT & fpu_vfp_ext_v3xd
62f3b8c8
PB		 19908 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19909 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19910 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19911 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19912 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19913 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19914 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19915 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19916 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19917
74db7efb 19918#undef THUMB_VARIANT
c921be7d
NC		 19919#define THUMB_VARIANT & fpu_vfp_ext_v3
19920#undef ARM_VARIANT
19921#define ARM_VARIANT & fpu_vfp_ext_v3
19922
21d799b5 19923 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 19924 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19925 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19926 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19927 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19928 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19929 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19930 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19931 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 19932
74db7efb
NC		 19933#undef ARM_VARIANT
19934#define ARM_VARIANT & fpu_vfp_ext_fma
19935#undef THUMB_VARIANT
19936#define THUMB_VARIANT & fpu_vfp_ext_fma
62f3b8c8
PB		 19937 /* Mnemonics shared by Neon and VFP. These are included in the
19938 VFP FMA variant; NEON and VFP FMA always includes the NEON
19939 FMA instructions. */
19940 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19941 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19942 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19943 the v form should always be used. */
19944 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19945 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19946 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19947 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19948 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19949 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19950
5287ad62 19951#undef THUMB_VARIANT
c921be7d
NC		 19952#undef ARM_VARIANT
19953#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19954
21d799b5
NC		 19955 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19956 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19957 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19958 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19959 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19960 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19961 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19962 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 19963
c921be7d
NC		 19964#undef ARM_VARIANT
19965#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19966
21d799b5
NC		 19967 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19968 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19969 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19970 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19971 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19972 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19973 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19974 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19975 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
74db7efb
NC		 19976 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19977 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19978 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19979 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19980 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19981 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21d799b5
NC		 19982 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19983 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19984 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19985 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
19986 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
19987 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19988 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19989 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19990 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19991 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
19992 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
74db7efb
NC		 19993 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
19994 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
19995 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21d799b5
NC		 19996 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
19997 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
19998 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
19999 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
20000 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
20001 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
20002 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
20003 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
20004 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20005 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20006 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20007 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20008 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20009 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20010 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20011 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20012 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20013 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
74db7efb
NC		 20014 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20015 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20016 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20017 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 20018 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20019 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20020 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20021 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20022 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20023 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20024 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20025 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20026 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 20027 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20028 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20029 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20030 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20031 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20032 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 20033 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20034 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20035 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20036 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20037 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20038 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20039 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20040 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20041 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20042 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20043 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20044 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20045 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20046 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20047 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20048 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20049 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20050 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20051 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20052 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20053 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20054 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20055 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
20056 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20057 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20058 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20059 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20060 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 20061 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20062 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20063 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20064 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20065 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20066 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 20067 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20068 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20069 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20070 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20071 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20072 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20073 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20074 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20075 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20076 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20077 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
20078 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20079 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20080 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20081 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20082 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20083 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20084 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20085 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20086 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20087 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20088 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20089 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20090 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20091 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20092 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20093 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20094 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20095 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20096 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20097 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20098 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20099 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20100 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20101 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20102 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20103 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20104 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20105 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20106 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20107 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20108 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20109 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
20110 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
20111 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
20112 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
20113 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
20114 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
20115 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20116 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20117 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20118 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
20119 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
20120 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
20121 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
20122 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
20123 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
20124 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20125 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20126 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20127 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20128 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 20129
c921be7d
NC		 20130#undef ARM_VARIANT
20131#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20132
21d799b5
NC		 20133 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
20134 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
20135 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
20136 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
20137 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
20138 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
20139 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20140 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20141 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20142 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20143 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20144 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20145 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20146 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20147 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20148 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20149 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20150 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20151 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20152 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20153 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
20154 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20155 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20156 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20157 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20158 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20159 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20160 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20161 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20162 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20163 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20164 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20165 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20166 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20167 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20168 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20169 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20170 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20171 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20172 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20173 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20174 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20175 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20176 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20177 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20178 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20179 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20180 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20181 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20182 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20183 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20184 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20185 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20186 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20187 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20188 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20189 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 20190
c921be7d
NC		 20191#undef ARM_VARIANT
20192#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20193
21d799b5
NC		 20194 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20195 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20196 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20197 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20198 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20199 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20200 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20201 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20202 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
20203 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
20204 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
20205 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
20206 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
20207 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
74db7efb
NC		 20208 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
20209 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
20210 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
20211 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
20212 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
20213 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
20214 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
20215 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
20216 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
20217 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21d799b5
NC		 20218 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
20219 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
20220 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
20221 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
74db7efb
NC		 20222 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
20223 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21d799b5
NC		 20224 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
20225 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
20226 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
20227 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
74db7efb
NC		 20228 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
20229 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
20230 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
20231 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
20232 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
20233 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21d799b5
NC		 20234 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
20235 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
74db7efb
NC		 20236 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
20237 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21d799b5
NC		 20238 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
20239 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
20240 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
20241 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
20242 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
20243 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
20244 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
20245 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
20246 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
20247 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
20248 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
20249 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
20250 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
20251 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
20252 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
20253 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
20254 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
20255 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
20256 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
20257 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
20258 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20259 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20260 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20261 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20262 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20263 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20264 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20265 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
74db7efb
NC		 20266 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20267 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21d799b5
NC		 20268 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20269 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
c19d1205
ZW		 20270};
20271#undef ARM_VARIANT
20272#undef THUMB_VARIANT
20273#undef TCE
c19d1205
ZW		 20274#undef TUE
20275#undef TUF
20276#undef TCC
8f06b2d8 20277#undef cCE
e3cb604e
PB		 20278#undef cCL
20279#undef C3E
c19d1205
ZW		 20280#undef CE
20281#undef CM
20282#undef UE
20283#undef UF
20284#undef UT
5287ad62
JB		 20285#undef NUF
20286#undef nUF
20287#undef NCE
20288#undef nCE
c19d1205
ZW		 20289#undef OPS0
20290#undef OPS1
20291#undef OPS2
20292#undef OPS3
20293#undef OPS4
20294#undef OPS5
20295#undef OPS6
20296#undef do_0
20297\f
20298/* MD interface: bits in the object file. */
bfae80f2 20299
c19d1205
ZW		 20300/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20301 for use in the a.out file, and stores them in the array pointed to by buf.
20302 This knows about the endian-ness of the target machine and does
20303 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20304 2 (short) and 4 (long) Floating numbers are put out as a series of
20305 LITTLENUMS (shorts, here at least). */
b99bd4ef 20306
c19d1205
ZW		 20307void
20308md_number_to_chars (char * buf, valueT val, int n)
20309{
20310 if (target_big_endian)
20311 number_to_chars_bigendian (buf, val, n);
20312 else
20313 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE		 20314}
20315
c19d1205
ZW		 20316static valueT
20317md_chars_to_number (char * buf, int n)
bfae80f2 20318{
c19d1205
ZW		 20319 valueT result = 0;
20320 unsigned char * where = (unsigned char *) buf;
bfae80f2 20321
c19d1205 20322 if (target_big_endian)
b99bd4ef 20323 {
c19d1205
ZW		 20324 while (n--)
20325 {
20326 result <<= 8;
20327 result |= (*where++ & 255);
20328 }
b99bd4ef 20329 }
c19d1205 20330 else
b99bd4ef 20331 {
c19d1205
ZW		 20332 while (n--)
20333 {
20334 result <<= 8;
20335 result |= (where[n] & 255);
20336 }
bfae80f2 20337 }
b99bd4ef 20338
c19d1205 20339 return result;
bfae80f2 20340}
b99bd4ef 20341
c19d1205 20342/* MD interface: Sections. */
b99bd4ef 20343
fa94de6b
RM		 20344/* Calculate the maximum variable size (i.e., excluding fr_fix)
20345 that an rs_machine_dependent frag may reach. */
20346
20347unsigned int
20348arm_frag_max_var (fragS *fragp)
20349{
20350 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20351 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20352
20353 Note that we generate relaxable instructions even for cases that don't
20354 really need it, like an immediate that's a trivial constant. So we're
20355 overestimating the instruction size for some of those cases. Rather
20356 than putting more intelligence here, it would probably be better to
20357 avoid generating a relaxation frag in the first place when it can be
20358 determined up front that a short instruction will suffice. */
20359
20360 gas_assert (fragp->fr_type == rs_machine_dependent);
20361 return INSN_SIZE;
20362}
20363
0110f2b8
PB		 20364/* Estimate the size of a frag before relaxing. Assume everything fits in
20365 2 bytes. */
20366
c19d1205 20367int
0110f2b8 20368md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW		 20369 segT segtype ATTRIBUTE_UNUSED)
20370{
0110f2b8
PB		 20371 fragp->fr_var = 2;
20372 return 2;
20373}
20374
20375/* Convert a machine dependent frag. */
20376
20377void
20378md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
20379{
20380 unsigned long insn;
20381 unsigned long old_op;
20382 char *buf;
20383 expressionS exp;
20384 fixS *fixp;
20385 int reloc_type;
20386 int pc_rel;
20387 int opcode;
20388
20389 buf = fragp->fr_literal + fragp->fr_fix;
20390
20391 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC		 20392 if (fragp->fr_symbol)
20393 {
0110f2b8
PB		 20394 exp.X_op = O_symbol;
20395 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC		 20396 }
20397 else
20398 {
0110f2b8 20399 exp.X_op = O_constant;
5f4273c7 20400 }
0110f2b8
PB		 20401 exp.X_add_number = fragp->fr_offset;
20402 opcode = fragp->fr_subtype;
20403 switch (opcode)
20404 {
20405 case T_MNEM_ldr_pc:
20406 case T_MNEM_ldr_pc2:
20407 case T_MNEM_ldr_sp:
20408 case T_MNEM_str_sp:
20409 case T_MNEM_ldr:
20410 case T_MNEM_ldrb:
20411 case T_MNEM_ldrh:
20412 case T_MNEM_str:
20413 case T_MNEM_strb:
20414 case T_MNEM_strh:
20415 if (fragp->fr_var == 4)
20416 {
5f4273c7 20417 insn = THUMB_OP32 (opcode);
0110f2b8
PB		 20418 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20419 {
20420 insn |= (old_op & 0x700) << 4;
20421 }
20422 else
20423 {
20424 insn |= (old_op & 7) << 12;
20425 insn |= (old_op & 0x38) << 13;
20426 }
20427 insn |= 0x00000c00;
20428 put_thumb32_insn (buf, insn);
20429 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20430 }
20431 else
20432 {
20433 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20434 }
20435 pc_rel = (opcode == T_MNEM_ldr_pc2);
20436 break;
20437 case T_MNEM_adr:
20438 if (fragp->fr_var == 4)
20439 {
20440 insn = THUMB_OP32 (opcode);
20441 insn |= (old_op & 0xf0) << 4;
20442 put_thumb32_insn (buf, insn);
20443 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20444 }
20445 else
20446 {
20447 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20448 exp.X_add_number -= 4;
20449 }
20450 pc_rel = 1;
20451 break;
20452 case T_MNEM_mov:
20453 case T_MNEM_movs:
20454 case T_MNEM_cmp:
20455 case T_MNEM_cmn:
20456 if (fragp->fr_var == 4)
20457 {
20458 int r0off = (opcode == T_MNEM_mov
20459 || opcode == T_MNEM_movs) ? 0 : 8;
20460 insn = THUMB_OP32 (opcode);
20461 insn = (insn & 0xe1ffffff) | 0x10000000;
20462 insn |= (old_op & 0x700) << r0off;
20463 put_thumb32_insn (buf, insn);
20464 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20465 }
20466 else
20467 {
20468 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20469 }
20470 pc_rel = 0;
20471 break;
20472 case T_MNEM_b:
20473 if (fragp->fr_var == 4)
20474 {
20475 insn = THUMB_OP32(opcode);
20476 put_thumb32_insn (buf, insn);
20477 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20478 }
20479 else
20480 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20481 pc_rel = 1;
20482 break;
20483 case T_MNEM_bcond:
20484 if (fragp->fr_var == 4)
20485 {
20486 insn = THUMB_OP32(opcode);
20487 insn |= (old_op & 0xf00) << 14;
20488 put_thumb32_insn (buf, insn);
20489 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20490 }
20491 else
20492 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20493 pc_rel = 1;
20494 break;
20495 case T_MNEM_add_sp:
20496 case T_MNEM_add_pc:
20497 case T_MNEM_inc_sp:
20498 case T_MNEM_dec_sp:
20499 if (fragp->fr_var == 4)
20500 {
20501 /* ??? Choose between add and addw. */
20502 insn = THUMB_OP32 (opcode);
20503 insn |= (old_op & 0xf0) << 4;
20504 put_thumb32_insn (buf, insn);
16805f35
PB		 20505 if (opcode == T_MNEM_add_pc)
20506 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20507 else
20508 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB		 20509 }
20510 else
20511 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20512 pc_rel = 0;
20513 break;
20514
20515 case T_MNEM_addi:
20516 case T_MNEM_addis:
20517 case T_MNEM_subi:
20518 case T_MNEM_subis:
20519 if (fragp->fr_var == 4)
20520 {
20521 insn = THUMB_OP32 (opcode);
20522 insn |= (old_op & 0xf0) << 4;
20523 insn |= (old_op & 0xf) << 16;
20524 put_thumb32_insn (buf, insn);
16805f35
PB		 20525 if (insn & (1 << 20))
20526 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20527 else
20528 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB		 20529 }
20530 else
20531 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20532 pc_rel = 0;
20533 break;
20534 default:
5f4273c7 20535 abort ();
0110f2b8
PB		 20536 }
20537 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 20538 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB		 20539 fixp->fx_file = fragp->fr_file;
20540 fixp->fx_line = fragp->fr_line;
20541 fragp->fr_fix += fragp->fr_var;
3cfdb781
TG		 20542
20543 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20544 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
20545 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
20546 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
0110f2b8
PB		 20547}
20548
20549/* Return the size of a relaxable immediate operand instruction.
20550 SHIFT and SIZE specify the form of the allowable immediate. */
20551static int
20552relax_immediate (fragS *fragp, int size, int shift)
20553{
20554 offsetT offset;
20555 offsetT mask;
20556 offsetT low;
20557
20558 /* ??? Should be able to do better than this. */
20559 if (fragp->fr_symbol)
20560 return 4;
20561
20562 low = (1 << shift) - 1;
20563 mask = (1 << (shift + size)) - (1 << shift);
20564 offset = fragp->fr_offset;
20565 /* Force misaligned offsets to 32-bit variant. */
20566 if (offset & low)
5e77afaa 20567 return 4;
0110f2b8
PB		 20568 if (offset & ~mask)
20569 return 4;
20570 return 2;
20571}
20572
5e77afaa
PB		 20573/* Get the address of a symbol during relaxation. */
20574static addressT
5f4273c7 20575relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB		 20576{
20577 fragS *sym_frag;
20578 addressT addr;
20579 symbolS *sym;
20580
20581 sym = fragp->fr_symbol;
20582 sym_frag = symbol_get_frag (sym);
20583 know (S_GET_SEGMENT (sym) != absolute_section
20584 || sym_frag == &zero_address_frag);
20585 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20586
20587 /* If frag has yet to be reached on this pass, assume it will
20588 move by STRETCH just as we did. If this is not so, it will
20589 be because some frag between grows, and that will force
20590 another pass. */
20591
20592 if (stretch != 0
20593 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB		 20594 {
20595 fragS *f;
20596
20597 /* Adjust stretch for any alignment frag. Note that if have
20598 been expanding the earlier code, the symbol may be
20599 defined in what appears to be an earlier frag. FIXME:
20600 This doesn't handle the fr_subtype field, which specifies
20601 a maximum number of bytes to skip when doing an
20602 alignment. */
20603 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20604 {
20605 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20606 {
20607 if (stretch < 0)
20608 stretch = - ((- stretch)
20609 & ~ ((1 << (int) f->fr_offset) - 1));
20610 else
20611 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20612 if (stretch == 0)
20613 break;
20614 }
20615 }
20616 if (f != NULL)
20617 addr += stretch;
20618 }
5e77afaa
PB		 20619
20620 return addr;
20621}
20622
0110f2b8
PB		 20623/* Return the size of a relaxable adr pseudo-instruction or PC-relative
20624 load. */
20625static int
5e77afaa 20626relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB		 20627{
20628 addressT addr;
20629 offsetT val;
20630
20631 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC		 20632 if (fragp->fr_symbol == NULL
20633 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 20634 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20635 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 20636 return 4;
20637
5f4273c7 20638 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 20639 addr = fragp->fr_address + fragp->fr_fix;
20640 addr = (addr + 4) & ~3;
5e77afaa 20641 /* Force misaligned targets to 32-bit variant. */
0110f2b8 20642 if (val & 3)
5e77afaa 20643 return 4;
0110f2b8
PB		 20644 val -= addr;
20645 if (val < 0 || val > 1020)
20646 return 4;
20647 return 2;
20648}
20649
20650/* Return the size of a relaxable add/sub immediate instruction. */
20651static int
20652relax_addsub (fragS *fragp, asection *sec)
20653{
20654 char *buf;
20655 int op;
20656
20657 buf = fragp->fr_literal + fragp->fr_fix;
20658 op = bfd_get_16(sec->owner, buf);
20659 if ((op & 0xf) == ((op >> 4) & 0xf))
20660 return relax_immediate (fragp, 8, 0);
20661 else
20662 return relax_immediate (fragp, 3, 0);
20663}
20664
e83a675f
RE		 20665/* Return TRUE iff the definition of symbol S could be pre-empted
20666 (overridden) at link or load time. */
20667static bfd_boolean
20668symbol_preemptible (symbolS *s)
20669{
20670 /* Weak symbols can always be pre-empted. */
20671 if (S_IS_WEAK (s))
20672 return TRUE;
20673
20674 /* Non-global symbols cannot be pre-empted. */
20675 if (! S_IS_EXTERNAL (s))
20676 return FALSE;
20677
20678#ifdef OBJ_ELF
20679 /* In ELF, a global symbol can be marked protected, or private. In that
20680 case it can't be pre-empted (other definitions in the same link unit
20681 would violate the ODR). */
20682 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20683 return FALSE;
20684#endif
20685
20686 /* Other global symbols might be pre-empted. */
20687 return TRUE;
20688}
0110f2b8
PB		 20689
20690/* Return the size of a relaxable branch instruction. BITS is the
20691 size of the offset field in the narrow instruction. */
20692
20693static int
5e77afaa 20694relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB		 20695{
20696 addressT addr;
20697 offsetT val;
20698 offsetT limit;
20699
20700 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 20701 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 20702 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20703 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 20704 return 4;
20705
267bf995 20706#ifdef OBJ_ELF
e83a675f 20707 /* A branch to a function in ARM state will require interworking. */
267bf995
RR		 20708 if (S_IS_DEFINED (fragp->fr_symbol)
20709 && ARM_IS_FUNC (fragp->fr_symbol))
20710 return 4;
e83a675f 20711#endif
0d9b4b55 20712
e83a675f 20713 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 20714 return 4;
267bf995 20715
5f4273c7 20716 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 20717 addr = fragp->fr_address + fragp->fr_fix + 4;
20718 val -= addr;
20719
20720 /* Offset is a signed value *2 */
20721 limit = 1 << bits;
20722 if (val >= limit || val < -limit)
20723 return 4;
20724 return 2;
20725}
20726
20727
20728/* Relax a machine dependent frag. This returns the amount by which
20729 the current size of the frag should change. */
20730
20731int
5e77afaa 20732arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB		 20733{
20734 int oldsize;
20735 int newsize;
20736
20737 oldsize = fragp->fr_var;
20738 switch (fragp->fr_subtype)
20739 {
20740 case T_MNEM_ldr_pc2:
5f4273c7 20741 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 20742 break;
20743 case T_MNEM_ldr_pc:
20744 case T_MNEM_ldr_sp:
20745 case T_MNEM_str_sp:
5f4273c7 20746 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB		 20747 break;
20748 case T_MNEM_ldr:
20749 case T_MNEM_str:
5f4273c7 20750 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB		 20751 break;
20752 case T_MNEM_ldrh:
20753 case T_MNEM_strh:
5f4273c7 20754 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB		 20755 break;
20756 case T_MNEM_ldrb:
20757 case T_MNEM_strb:
5f4273c7 20758 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB		 20759 break;
20760 case T_MNEM_adr:
5f4273c7 20761 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 20762 break;
20763 case T_MNEM_mov:
20764 case T_MNEM_movs:
20765 case T_MNEM_cmp:
20766 case T_MNEM_cmn:
5f4273c7 20767 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB		 20768 break;
20769 case T_MNEM_b:
5f4273c7 20770 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB		 20771 break;
20772 case T_MNEM_bcond:
5f4273c7 20773 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB		 20774 break;
20775 case T_MNEM_add_sp:
20776 case T_MNEM_add_pc:
20777 newsize = relax_immediate (fragp, 8, 2);
20778 break;
20779 case T_MNEM_inc_sp:
20780 case T_MNEM_dec_sp:
20781 newsize = relax_immediate (fragp, 7, 2);
20782 break;
20783 case T_MNEM_addi:
20784 case T_MNEM_addis:
20785 case T_MNEM_subi:
20786 case T_MNEM_subis:
20787 newsize = relax_addsub (fragp, sec);
20788 break;
20789 default:
5f4273c7 20790 abort ();
0110f2b8 20791 }
5e77afaa
PB		 20792
20793 fragp->fr_var = newsize;
20794 /* Freeze wide instructions that are at or before the same location as
20795 in the previous pass. This avoids infinite loops.
5f4273c7
NC		 20796 Don't freeze them unconditionally because targets may be artificially
20797 misaligned by the expansion of preceding frags. */
5e77afaa 20798 if (stretch <= 0 && newsize > 2)
0110f2b8 20799 {
0110f2b8 20800 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 20801 frag_wane (fragp);
0110f2b8 20802 }
5e77afaa 20803
0110f2b8 20804 return newsize - oldsize;
c19d1205 20805}
b99bd4ef 20806
c19d1205 20807/* Round up a section size to the appropriate boundary. */
b99bd4ef 20808
c19d1205
ZW		 20809valueT
20810md_section_align (segT segment ATTRIBUTE_UNUSED,
20811 valueT size)
20812{
f0927246
NC		 20813#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20814 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20815 {
20816 /* For a.out, force the section size to be aligned. If we don't do
20817 this, BFD will align it for us, but it will not write out the
20818 final bytes of the section. This may be a bug in BFD, but it is
20819 easier to fix it here since that is how the other a.out targets
20820 work. */
20821 int align;
20822
20823 align = bfd_get_section_alignment (stdoutput, segment);
20824 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20825 }
c19d1205 20826#endif
f0927246
NC		 20827
20828 return size;
bfae80f2 20829}
b99bd4ef 20830
c19d1205
ZW		 20831/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20832 of an rs_align_code fragment. */
20833
20834void
20835arm_handle_align (fragS * fragP)
bfae80f2 20836{
e7495e45
NS		 20837 static char const arm_noop[2][2][4] =
20838 {
20839 { /* ARMv1 */
20840 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20841 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20842 },
20843 { /* ARMv6k */
20844 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20845 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20846 },
20847 };
20848 static char const thumb_noop[2][2][2] =
20849 {
20850 { /* Thumb-1 */
20851 {0xc0, 0x46}, /* LE */
20852 {0x46, 0xc0}, /* BE */
20853 },
20854 { /* Thumb-2 */
20855 {0x00, 0xbf}, /* LE */
20856 {0xbf, 0x00} /* BE */
20857 }
20858 };
20859 static char const wide_thumb_noop[2][4] =
20860 { /* Wide Thumb-2 */
20861 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20862 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20863 };
c921be7d 20864
e7495e45 20865 unsigned bytes, fix, noop_size;
c19d1205
ZW		 20866 char * p;
20867 const char * noop;
e7495e45 20868 const char *narrow_noop = NULL;
cd000bff
DJ		 20869#ifdef OBJ_ELF
20870 enum mstate state;
20871#endif
bfae80f2 20872
c19d1205 20873 if (fragP->fr_type != rs_align_code)
bfae80f2
RE		 20874 return;
20875
c19d1205
ZW		 20876 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20877 p = fragP->fr_literal + fragP->fr_fix;
20878 fix = 0;
bfae80f2 20879
c19d1205
ZW		 20880 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20881 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 20882
cd000bff 20883 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 20884
cd000bff 20885 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 20886 {
7f78eb34
JW		 20887 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
20888 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
e7495e45
NS		 20889 {
20890 narrow_noop = thumb_noop[1][target_big_endian];
20891 noop = wide_thumb_noop[target_big_endian];
20892 }
c19d1205 20893 else
e7495e45
NS		 20894 noop = thumb_noop[0][target_big_endian];
20895 noop_size = 2;
cd000bff
DJ		 20896#ifdef OBJ_ELF
20897 state = MAP_THUMB;
20898#endif
7ed4c4c5
NC		 20899 }
20900 else
20901 {
7f78eb34
JW		 20902 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
20903 ? selected_cpu : arm_arch_none,
20904 arm_ext_v6k) != 0]
e7495e45
NS		 20905 [target_big_endian];
20906 noop_size = 4;
cd000bff
DJ		 20907#ifdef OBJ_ELF
20908 state = MAP_ARM;
20909#endif
7ed4c4c5 20910 }
c921be7d 20911
e7495e45 20912 fragP->fr_var = noop_size;
c921be7d 20913
c19d1205 20914 if (bytes & (noop_size - 1))
7ed4c4c5 20915 {
c19d1205 20916 fix = bytes & (noop_size - 1);
cd000bff
DJ		 20917#ifdef OBJ_ELF
20918 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20919#endif
c19d1205
ZW		 20920 memset (p, 0, fix);
20921 p += fix;
20922 bytes -= fix;
a737bd4d 20923 }
a737bd4d 20924
e7495e45
NS		 20925 if (narrow_noop)
20926 {
20927 if (bytes & noop_size)
20928 {
20929 /* Insert a narrow noop. */
20930 memcpy (p, narrow_noop, noop_size);
20931 p += noop_size;
20932 bytes -= noop_size;
20933 fix += noop_size;
20934 }
20935
20936 /* Use wide noops for the remainder */
20937 noop_size = 4;
20938 }
20939
c19d1205 20940 while (bytes >= noop_size)
a737bd4d 20941 {
c19d1205
ZW		 20942 memcpy (p, noop, noop_size);
20943 p += noop_size;
20944 bytes -= noop_size;
20945 fix += noop_size;
a737bd4d
NC		 20946 }
20947
c19d1205 20948 fragP->fr_fix += fix;
a737bd4d
NC		 20949}
20950
c19d1205
ZW		 20951/* Called from md_do_align. Used to create an alignment
20952 frag in a code section. */
20953
20954void
20955arm_frag_align_code (int n, int max)
bfae80f2 20956{
c19d1205 20957 char * p;
7ed4c4c5 20958
c19d1205 20959 /* We assume that there will never be a requirement
6ec8e702 20960 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 20961 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC		 20962 {
20963 char err_msg[128];
20964
fa94de6b 20965 sprintf (err_msg,
477330fc
RM		 20966 _("alignments greater than %d bytes not supported in .text sections."),
20967 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 20968 as_fatal ("%s", err_msg);
6ec8e702 20969 }
bfae80f2 20970
c19d1205
ZW		 20971 p = frag_var (rs_align_code,
20972 MAX_MEM_FOR_RS_ALIGN_CODE,
20973 1,
20974 (relax_substateT) max,
20975 (symbolS *) NULL,
20976 (offsetT) n,
20977 (char *) NULL);
20978 *p = 0;
20979}
bfae80f2 20980
8dc2430f
NC		 20981/* Perform target specific initialisation of a frag.
20982 Note - despite the name this initialisation is not done when the frag
20983 is created, but only when its type is assigned. A frag can be created
20984 and used a long time before its type is set, so beware of assuming that
20985 this initialisationis performed first. */
bfae80f2 20986
cd000bff
DJ		 20987#ifndef OBJ_ELF
20988void
20989arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
20990{
20991 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 20992 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ		 20993}
20994
20995#else /* OBJ_ELF is defined. */
c19d1205 20996void
cd000bff 20997arm_init_frag (fragS * fragP, int max_chars)
c19d1205 20998{
8dc2430f
NC		 20999 /* If the current ARM vs THUMB mode has not already
21000 been recorded into this frag then do so now. */
cd000bff
DJ		 21001 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
21002 {
21003 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21004
21005 /* Record a mapping symbol for alignment frags. We will delete this
21006 later if the alignment ends up empty. */
21007 switch (fragP->fr_type)
21008 {
21009 case rs_align:
21010 case rs_align_test:
21011 case rs_fill:
21012 mapping_state_2 (MAP_DATA, max_chars);
21013 break;
21014 case rs_align_code:
21015 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
21016 break;
21017 default:
21018 break;
21019 }
21020 }
bfae80f2
RE		 21021}
21022
c19d1205
ZW		 21023/* When we change sections we need to issue a new mapping symbol. */
21024
21025void
21026arm_elf_change_section (void)
bfae80f2 21027{
c19d1205
ZW		 21028 /* Link an unlinked unwind index table section to the .text section. */
21029 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
21030 && elf_linked_to_section (now_seg) == NULL)
21031 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE		 21032}
21033
c19d1205
ZW		 21034int
21035arm_elf_section_type (const char * str, size_t len)
e45d0630 21036{
c19d1205
ZW		 21037 if (len == 5 && strncmp (str, "exidx", 5) == 0)
21038 return SHT_ARM_EXIDX;
e45d0630 21039
c19d1205
ZW		 21040 return -1;
21041}
21042\f
21043/* Code to deal with unwinding tables. */
e45d0630 21044
c19d1205 21045static void add_unwind_adjustsp (offsetT);
e45d0630 21046
5f4273c7 21047/* Generate any deferred unwind frame offset. */
e45d0630 21048
bfae80f2 21049static void
c19d1205 21050flush_pending_unwind (void)
bfae80f2 21051{
c19d1205 21052 offsetT offset;
bfae80f2 21053
c19d1205
ZW		 21054 offset = unwind.pending_offset;
21055 unwind.pending_offset = 0;
21056 if (offset != 0)
21057 add_unwind_adjustsp (offset);
bfae80f2
RE		 21058}
21059
c19d1205
ZW		 21060/* Add an opcode to this list for this function. Two-byte opcodes should
21061 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21062 order. */
21063
bfae80f2 21064static void
c19d1205 21065add_unwind_opcode (valueT op, int length)
bfae80f2 21066{
c19d1205
ZW		 21067 /* Add any deferred stack adjustment. */
21068 if (unwind.pending_offset)
21069 flush_pending_unwind ();
bfae80f2 21070
c19d1205 21071 unwind.sp_restored = 0;
bfae80f2 21072
c19d1205 21073 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 21074 {
c19d1205
ZW		 21075 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
21076 if (unwind.opcodes)
21d799b5 21077 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
477330fc 21078 unwind.opcode_alloc);
c19d1205 21079 else
21d799b5 21080 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
bfae80f2 21081 }
c19d1205 21082 while (length > 0)
bfae80f2 21083 {
c19d1205
ZW		 21084 length--;
21085 unwind.opcodes[unwind.opcode_count] = op & 0xff;
21086 op >>= 8;
21087 unwind.opcode_count++;
bfae80f2 21088 }
bfae80f2
RE		 21089}
21090
c19d1205
ZW		 21091/* Add unwind opcodes to adjust the stack pointer. */
21092
bfae80f2 21093static void
c19d1205 21094add_unwind_adjustsp (offsetT offset)
bfae80f2 21095{
c19d1205 21096 valueT op;
bfae80f2 21097
c19d1205 21098 if (offset > 0x200)
bfae80f2 21099 {
c19d1205
ZW		 21100 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21101 char bytes[5];
21102 int n;
21103 valueT o;
bfae80f2 21104
c19d1205
ZW		 21105 /* Long form: 0xb2, uleb128. */
21106 /* This might not fit in a word so add the individual bytes,
21107 remembering the list is built in reverse order. */
21108 o = (valueT) ((offset - 0x204) >> 2);
21109 if (o == 0)
21110 add_unwind_opcode (0, 1);
bfae80f2 21111
c19d1205
ZW		 21112 /* Calculate the uleb128 encoding of the offset. */
21113 n = 0;
21114 while (o)
21115 {
21116 bytes[n] = o & 0x7f;
21117 o >>= 7;
21118 if (o)
21119 bytes[n] |= 0x80;
21120 n++;
21121 }
21122 /* Add the insn. */
21123 for (; n; n--)
21124 add_unwind_opcode (bytes[n - 1], 1);
21125 add_unwind_opcode (0xb2, 1);
21126 }
21127 else if (offset > 0x100)
bfae80f2 21128 {
c19d1205
ZW		 21129 /* Two short opcodes. */
21130 add_unwind_opcode (0x3f, 1);
21131 op = (offset - 0x104) >> 2;
21132 add_unwind_opcode (op, 1);
bfae80f2 21133 }
c19d1205
ZW		 21134 else if (offset > 0)
21135 {
21136 /* Short opcode. */
21137 op = (offset - 4) >> 2;
21138 add_unwind_opcode (op, 1);
21139 }
21140 else if (offset < 0)
bfae80f2 21141 {
c19d1205
ZW		 21142 offset = -offset;
21143 while (offset > 0x100)
bfae80f2 21144 {
c19d1205
ZW		 21145 add_unwind_opcode (0x7f, 1);
21146 offset -= 0x100;
bfae80f2 21147 }
c19d1205
ZW		 21148 op = ((offset - 4) >> 2) | 0x40;
21149 add_unwind_opcode (op, 1);
bfae80f2 21150 }
bfae80f2
RE		 21151}
21152
c19d1205
ZW		 21153/* Finish the list of unwind opcodes for this function. */
21154static void
21155finish_unwind_opcodes (void)
bfae80f2 21156{
c19d1205 21157 valueT op;
bfae80f2 21158
c19d1205 21159 if (unwind.fp_used)
bfae80f2 21160 {
708587a4 21161 /* Adjust sp as necessary. */
c19d1205
ZW		 21162 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
21163 flush_pending_unwind ();
bfae80f2 21164
c19d1205
ZW		 21165 /* After restoring sp from the frame pointer. */
21166 op = 0x90 | unwind.fp_reg;
21167 add_unwind_opcode (op, 1);
21168 }
21169 else
21170 flush_pending_unwind ();
bfae80f2
RE		 21171}
21172
bfae80f2 21173
c19d1205
ZW		 21174/* Start an exception table entry. If idx is nonzero this is an index table
21175 entry. */
bfae80f2
RE		 21176
21177static void
c19d1205 21178start_unwind_section (const segT text_seg, int idx)
bfae80f2 21179{
c19d1205
ZW		 21180 const char * text_name;
21181 const char * prefix;
21182 const char * prefix_once;
21183 const char * group_name;
21184 size_t prefix_len;
21185 size_t text_len;
21186 char * sec_name;
21187 size_t sec_name_len;
21188 int type;
21189 int flags;
21190 int linkonce;
bfae80f2 21191
c19d1205 21192 if (idx)
bfae80f2 21193 {
c19d1205
ZW		 21194 prefix = ELF_STRING_ARM_unwind;
21195 prefix_once = ELF_STRING_ARM_unwind_once;
21196 type = SHT_ARM_EXIDX;
bfae80f2 21197 }
c19d1205 21198 else
bfae80f2 21199 {
c19d1205
ZW		 21200 prefix = ELF_STRING_ARM_unwind_info;
21201 prefix_once = ELF_STRING_ARM_unwind_info_once;
21202 type = SHT_PROGBITS;
bfae80f2
RE		 21203 }
21204
c19d1205
ZW		 21205 text_name = segment_name (text_seg);
21206 if (streq (text_name, ".text"))
21207 text_name = "";
21208
21209 if (strncmp (text_name, ".gnu.linkonce.t.",
21210 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 21211 {
c19d1205
ZW		 21212 prefix = prefix_once;
21213 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE		 21214 }
21215
c19d1205
ZW		 21216 prefix_len = strlen (prefix);
21217 text_len = strlen (text_name);
21218 sec_name_len = prefix_len + text_len;
21d799b5 21219 sec_name = (char *) xmalloc (sec_name_len + 1);
c19d1205
ZW		 21220 memcpy (sec_name, prefix, prefix_len);
21221 memcpy (sec_name + prefix_len, text_name, text_len);
21222 sec_name[prefix_len + text_len] = '\0';
bfae80f2 21223
c19d1205
ZW		 21224 flags = SHF_ALLOC;
21225 linkonce = 0;
21226 group_name = 0;
bfae80f2 21227
c19d1205
ZW		 21228 /* Handle COMDAT group. */
21229 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 21230 {
c19d1205
ZW		 21231 group_name = elf_group_name (text_seg);
21232 if (group_name == NULL)
21233 {
bd3ba5d1 21234 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW		 21235 segment_name (text_seg));
21236 ignore_rest_of_line ();
21237 return;
21238 }
21239 flags |= SHF_GROUP;
21240 linkonce = 1;
bfae80f2
RE		 21241 }
21242
c19d1205 21243 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
bfae80f2 21244
5f4273c7 21245 /* Set the section link for index tables. */
c19d1205
ZW		 21246 if (idx)
21247 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE		 21248}
21249
bfae80f2 21250
c19d1205
ZW		 21251/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21252 personality routine data. Returns zero, or the index table value for
cad0da33 21253 an inline entry. */
c19d1205
ZW		 21254
21255static valueT
21256create_unwind_entry (int have_data)
bfae80f2 21257{
c19d1205
ZW		 21258 int size;
21259 addressT where;
21260 char *ptr;
21261 /* The current word of data. */
21262 valueT data;
21263 /* The number of bytes left in this word. */
21264 int n;
bfae80f2 21265
c19d1205 21266 finish_unwind_opcodes ();
bfae80f2 21267
c19d1205
ZW		 21268 /* Remember the current text section. */
21269 unwind.saved_seg = now_seg;
21270 unwind.saved_subseg = now_subseg;
bfae80f2 21271
c19d1205 21272 start_unwind_section (now_seg, 0);
bfae80f2 21273
c19d1205 21274 if (unwind.personality_routine == NULL)
bfae80f2 21275 {
c19d1205
ZW		 21276 if (unwind.personality_index == -2)
21277 {
21278 if (have_data)
5f4273c7 21279 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW		 21280 return 1; /* EXIDX_CANTUNWIND. */
21281 }
bfae80f2 21282
c19d1205
ZW		 21283 /* Use a default personality routine if none is specified. */
21284 if (unwind.personality_index == -1)
21285 {
21286 if (unwind.opcode_count > 3)
21287 unwind.personality_index = 1;
21288 else
21289 unwind.personality_index = 0;
21290 }
bfae80f2 21291
c19d1205
ZW		 21292 /* Space for the personality routine entry. */
21293 if (unwind.personality_index == 0)
21294 {
21295 if (unwind.opcode_count > 3)
21296 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 21297
c19d1205
ZW		 21298 if (!have_data)
21299 {
21300 /* All the data is inline in the index table. */
21301 data = 0x80;
21302 n = 3;
21303 while (unwind.opcode_count > 0)
21304 {
21305 unwind.opcode_count--;
21306 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21307 n--;
21308 }
bfae80f2 21309
c19d1205
ZW		 21310 /* Pad with "finish" opcodes. */
21311 while (n--)
21312 data = (data << 8) | 0xb0;
bfae80f2 21313
c19d1205
ZW		 21314 return data;
21315 }
21316 size = 0;
21317 }
21318 else
21319 /* We get two opcodes "free" in the first word. */
21320 size = unwind.opcode_count - 2;
21321 }
21322 else
5011093d 21323 {
cad0da33
NC		 21324 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21325 if (unwind.personality_index != -1)
21326 {
21327 as_bad (_("attempt to recreate an unwind entry"));
21328 return 1;
21329 }
5011093d
NC		 21330
21331 /* An extra byte is required for the opcode count. */
21332 size = unwind.opcode_count + 1;
21333 }
bfae80f2 21334
c19d1205
ZW		 21335 size = (size + 3) >> 2;
21336 if (size > 0xff)
21337 as_bad (_("too many unwind opcodes"));
bfae80f2 21338
c19d1205
ZW		 21339 frag_align (2, 0, 0);
21340 record_alignment (now_seg, 2);
21341 unwind.table_entry = expr_build_dot ();
21342
21343 /* Allocate the table entry. */
21344 ptr = frag_more ((size << 2) + 4);
74929e7b
NC		 21345 /* PR 13449: Zero the table entries in case some of them are not used. */
21346 memset (ptr, 0, (size << 2) + 4);
c19d1205 21347 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 21348
c19d1205 21349 switch (unwind.personality_index)
bfae80f2 21350 {
c19d1205
ZW		 21351 case -1:
21352 /* ??? Should this be a PLT generating relocation? */
21353 /* Custom personality routine. */
21354 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
21355 BFD_RELOC_ARM_PREL31);
bfae80f2 21356
c19d1205
ZW		 21357 where += 4;
21358 ptr += 4;
bfae80f2 21359
c19d1205 21360 /* Set the first byte to the number of additional words. */
5011093d 21361 data = size > 0 ? size - 1 : 0;
c19d1205
ZW		 21362 n = 3;
21363 break;
bfae80f2 21364
c19d1205
ZW		 21365 /* ABI defined personality routines. */
21366 case 0:
21367 /* Three opcodes bytes are packed into the first word. */
21368 data = 0x80;
21369 n = 3;
21370 break;
bfae80f2 21371
c19d1205
ZW		 21372 case 1:
21373 case 2:
21374 /* The size and first two opcode bytes go in the first word. */
21375 data = ((0x80 + unwind.personality_index) << 8) | size;
21376 n = 2;
21377 break;
bfae80f2 21378
c19d1205
ZW		 21379 default:
21380 /* Should never happen. */
21381 abort ();
21382 }
bfae80f2 21383
c19d1205
ZW		 21384 /* Pack the opcodes into words (MSB first), reversing the list at the same
21385 time. */
21386 while (unwind.opcode_count > 0)
21387 {
21388 if (n == 0)
21389 {
21390 md_number_to_chars (ptr, data, 4);
21391 ptr += 4;
21392 n = 4;
21393 data = 0;
21394 }
21395 unwind.opcode_count--;
21396 n--;
21397 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21398 }
21399
21400 /* Finish off the last word. */
21401 if (n < 4)
21402 {
21403 /* Pad with "finish" opcodes. */
21404 while (n--)
21405 data = (data << 8) | 0xb0;
21406
21407 md_number_to_chars (ptr, data, 4);
21408 }
21409
21410 if (!have_data)
21411 {
21412 /* Add an empty descriptor if there is no user-specified data. */
21413 ptr = frag_more (4);
21414 md_number_to_chars (ptr, 0, 4);
21415 }
21416
21417 return 0;
bfae80f2
RE		 21418}
21419
f0927246
NC		 21420
21421/* Initialize the DWARF-2 unwind information for this procedure. */
21422
21423void
21424tc_arm_frame_initial_instructions (void)
21425{
21426 cfi_add_CFA_def_cfa (REG_SP, 0);
21427}
21428#endif /* OBJ_ELF */
21429
c19d1205
ZW		 21430/* Convert REGNAME to a DWARF-2 register number. */
21431
21432int
1df69f4f 21433tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 21434{
1df69f4f 21435 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
1f5afe1c
NC		 21436 if (reg != FAIL)
21437 return reg;
c19d1205 21438
1f5afe1c
NC		 21439 /* PR 16694: Allow VFP registers as well. */
21440 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
21441 if (reg != FAIL)
21442 return 64 + reg;
c19d1205 21443
1f5afe1c
NC		 21444 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
21445 if (reg != FAIL)
21446 return reg + 256;
21447
21448 return -1;
bfae80f2
RE		 21449}
21450
f0927246 21451#ifdef TE_PE
c19d1205 21452void
f0927246 21453tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 21454{
91d6fa6a 21455 expressionS exp;
bfae80f2 21456
91d6fa6a
NC		 21457 exp.X_op = O_secrel;
21458 exp.X_add_symbol = symbol;
21459 exp.X_add_number = 0;
21460 emit_expr (&exp, size);
f0927246
NC		 21461}
21462#endif
bfae80f2 21463
c19d1205 21464/* MD interface: Symbol and relocation handling. */
bfae80f2 21465
2fc8bdac
ZW		 21466/* Return the address within the segment that a PC-relative fixup is
21467 relative to. For ARM, PC-relative fixups applied to instructions
21468 are generally relative to the location of the fixup plus 8 bytes.
21469 Thumb branches are offset by 4, and Thumb loads relative to PC
21470 require special handling. */
bfae80f2 21471
c19d1205 21472long
2fc8bdac 21473md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 21474{
2fc8bdac
ZW		 21475 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21476
21477 /* If this is pc-relative and we are going to emit a relocation
21478 then we just want to put out any pipeline compensation that the linker
53baae48
NC		 21479 will need. Otherwise we want to use the calculated base.
21480 For WinCE we skip the bias for externals as well, since this
21481 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 21482 if (fixP->fx_pcrel
2fc8bdac 21483 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC		 21484 || (arm_force_relocation (fixP)
21485#ifdef TE_WINCE
21486 && !S_IS_EXTERNAL (fixP->fx_addsy)
21487#endif
21488 )))
2fc8bdac 21489 base = 0;
bfae80f2 21490
267bf995 21491
c19d1205 21492 switch (fixP->fx_r_type)
bfae80f2 21493 {
2fc8bdac
ZW		 21494 /* PC relative addressing on the Thumb is slightly odd as the
21495 bottom two bits of the PC are forced to zero for the
21496 calculation. This happens *after* application of the
21497 pipeline offset. However, Thumb adrl already adjusts for
21498 this, so we need not do it again. */
c19d1205 21499 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 21500 return base & ~3;
c19d1205
ZW		 21501
21502 case BFD_RELOC_ARM_THUMB_OFFSET:
21503 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 21504 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 21505 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 21506 return (base + 4) & ~3;
c19d1205 21507
2fc8bdac
ZW		 21508 /* Thumb branches are simply offset by +4. */
21509 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21510 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21511 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21512 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 21513 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac 21514 return base + 4;
bfae80f2 21515
267bf995 21516 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL		 21517 if (fixP->fx_addsy
21518 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21519 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 21520 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM		 21521 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21522 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR		 21523 return base + 4;
21524
00adf2d4
JB		 21525 /* BLX is like branches above, but forces the low two bits of PC to
21526 zero. */
486499d0
CL		 21527 case BFD_RELOC_THUMB_PCREL_BLX:
21528 if (fixP->fx_addsy
21529 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21530 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21531 && THUMB_IS_FUNC (fixP->fx_addsy)
21532 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21533 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB		 21534 return (base + 4) & ~3;
21535
2fc8bdac
ZW		 21536 /* ARM mode branches are offset by +8. However, the Windows CE
21537 loader expects the relocation not to take this into account. */
267bf995 21538 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL		 21539 if (fixP->fx_addsy
21540 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21541 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21542 && ARM_IS_FUNC (fixP->fx_addsy)
21543 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21544 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 21545 return base + 8;
267bf995 21546
486499d0
CL		 21547 case BFD_RELOC_ARM_PCREL_CALL:
21548 if (fixP->fx_addsy
21549 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21550 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21551 && THUMB_IS_FUNC (fixP->fx_addsy)
21552 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21553 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 21554 return base + 8;
267bf995 21555
2fc8bdac 21556 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 21557 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 21558 case BFD_RELOC_ARM_PLT32:
c19d1205 21559#ifdef TE_WINCE
5f4273c7 21560 /* When handling fixups immediately, because we have already
477330fc 21561 discovered the value of a symbol, or the address of the frag involved
53baae48 21562 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM		 21563 see fixup_segment() in write.c
21564 The S_IS_EXTERNAL test handles the case of global symbols.
21565 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC		 21566 if (fixP->fx_pcrel
21567 && fixP->fx_addsy != NULL
21568 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21569 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21570 return base + 8;
2fc8bdac 21571 return base;
c19d1205 21572#else
2fc8bdac 21573 return base + 8;
c19d1205 21574#endif
2fc8bdac 21575
267bf995 21576
2fc8bdac
ZW		 21577 /* ARM mode loads relative to PC are also offset by +8. Unlike
21578 branches, the Windows CE loader *does* expect the relocation
21579 to take this into account. */
21580 case BFD_RELOC_ARM_OFFSET_IMM:
21581 case BFD_RELOC_ARM_OFFSET_IMM8:
21582 case BFD_RELOC_ARM_HWLITERAL:
21583 case BFD_RELOC_ARM_LITERAL:
21584 case BFD_RELOC_ARM_CP_OFF_IMM:
21585 return base + 8;
21586
21587
21588 /* Other PC-relative relocations are un-offset. */
21589 default:
21590 return base;
21591 }
bfae80f2
RE		 21592}
21593
c19d1205
ZW		 21594/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21595 Otherwise we have no need to default values of symbols. */
21596
21597symbolS *
21598md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
bfae80f2 21599{
c19d1205
ZW		 21600#ifdef OBJ_ELF
21601 if (name[0] == '_' && name[1] == 'G'
21602 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21603 {
21604 if (!GOT_symbol)
21605 {
21606 if (symbol_find (name))
bd3ba5d1 21607 as_bad (_("GOT already in the symbol table"));
bfae80f2 21608
c19d1205
ZW		 21609 GOT_symbol = symbol_new (name, undefined_section,
21610 (valueT) 0, & zero_address_frag);
21611 }
bfae80f2 21612
c19d1205 21613 return GOT_symbol;
bfae80f2 21614 }
c19d1205 21615#endif
bfae80f2 21616
c921be7d 21617 return NULL;
bfae80f2
RE		 21618}
21619
55cf6793 21620/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW		 21621 computed as two separate immediate values, added together. We
21622 already know that this value cannot be computed by just one ARM
21623 instruction. */
21624
21625static unsigned int
21626validate_immediate_twopart (unsigned int val,
21627 unsigned int * highpart)
bfae80f2 21628{
c19d1205
ZW		 21629 unsigned int a;
21630 unsigned int i;
bfae80f2 21631
c19d1205
ZW		 21632 for (i = 0; i < 32; i += 2)
21633 if (((a = rotate_left (val, i)) & 0xff) != 0)
21634 {
21635 if (a & 0xff00)
21636 {
21637 if (a & ~ 0xffff)
21638 continue;
21639 * highpart = (a >> 8) | ((i + 24) << 7);
21640 }
21641 else if (a & 0xff0000)
21642 {
21643 if (a & 0xff000000)
21644 continue;
21645 * highpart = (a >> 16) | ((i + 16) << 7);
21646 }
21647 else
21648 {
9c2799c2 21649 gas_assert (a & 0xff000000);
c19d1205
ZW		 21650 * highpart = (a >> 24) | ((i + 8) << 7);
21651 }
bfae80f2 21652
c19d1205
ZW		 21653 return (a & 0xff) | (i << 7);
21654 }
bfae80f2 21655
c19d1205 21656 return FAIL;
bfae80f2
RE		 21657}
21658
c19d1205
ZW		 21659static int
21660validate_offset_imm (unsigned int val, int hwse)
21661{
21662 if ((hwse && val > 255) || val > 4095)
21663 return FAIL;
21664 return val;
21665}
bfae80f2 21666
55cf6793 21667/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW		 21668 negative immediate constant by altering the instruction. A bit of
21669 a hack really.
21670 MOV <-> MVN
21671 AND <-> BIC
21672 ADC <-> SBC
21673 by inverting the second operand, and
21674 ADD <-> SUB
21675 CMP <-> CMN
21676 by negating the second operand. */
bfae80f2 21677
c19d1205
ZW		 21678static int
21679negate_data_op (unsigned long * instruction,
21680 unsigned long value)
bfae80f2 21681{
c19d1205
ZW		 21682 int op, new_inst;
21683 unsigned long negated, inverted;
bfae80f2 21684
c19d1205
ZW		 21685 negated = encode_arm_immediate (-value);
21686 inverted = encode_arm_immediate (~value);
bfae80f2 21687
c19d1205
ZW		 21688 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21689 switch (op)
bfae80f2 21690 {
c19d1205
ZW		 21691 /* First negates. */
21692 case OPCODE_SUB: /* ADD <-> SUB */
21693 new_inst = OPCODE_ADD;
21694 value = negated;
21695 break;
bfae80f2 21696
c19d1205
ZW		 21697 case OPCODE_ADD:
21698 new_inst = OPCODE_SUB;
21699 value = negated;
21700 break;
bfae80f2 21701
c19d1205
ZW		 21702 case OPCODE_CMP: /* CMP <-> CMN */
21703 new_inst = OPCODE_CMN;
21704 value = negated;
21705 break;
bfae80f2 21706
c19d1205
ZW		 21707 case OPCODE_CMN:
21708 new_inst = OPCODE_CMP;
21709 value = negated;
21710 break;
bfae80f2 21711
c19d1205
ZW		 21712 /* Now Inverted ops. */
21713 case OPCODE_MOV: /* MOV <-> MVN */
21714 new_inst = OPCODE_MVN;
21715 value = inverted;
21716 break;
bfae80f2 21717
c19d1205
ZW		 21718 case OPCODE_MVN:
21719 new_inst = OPCODE_MOV;
21720 value = inverted;
21721 break;
bfae80f2 21722
c19d1205
ZW		 21723 case OPCODE_AND: /* AND <-> BIC */
21724 new_inst = OPCODE_BIC;
21725 value = inverted;
21726 break;
bfae80f2 21727
c19d1205
ZW		 21728 case OPCODE_BIC:
21729 new_inst = OPCODE_AND;
21730 value = inverted;
21731 break;
bfae80f2 21732
c19d1205
ZW		 21733 case OPCODE_ADC: /* ADC <-> SBC */
21734 new_inst = OPCODE_SBC;
21735 value = inverted;
21736 break;
bfae80f2 21737
c19d1205
ZW		 21738 case OPCODE_SBC:
21739 new_inst = OPCODE_ADC;
21740 value = inverted;
21741 break;
bfae80f2 21742
c19d1205
ZW		 21743 /* We cannot do anything. */
21744 default:
21745 return FAIL;
b99bd4ef
NC		 21746 }
21747
c19d1205
ZW		 21748 if (value == (unsigned) FAIL)
21749 return FAIL;
21750
21751 *instruction &= OPCODE_MASK;
21752 *instruction |= new_inst << DATA_OP_SHIFT;
21753 return value;
b99bd4ef
NC		 21754}
21755
ef8d22e6
PB		 21756/* Like negate_data_op, but for Thumb-2. */
21757
21758static unsigned int
16dd5e42 21759thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB		 21760{
21761 int op, new_inst;
21762 int rd;
16dd5e42 21763 unsigned int negated, inverted;
ef8d22e6
PB		 21764
21765 negated = encode_thumb32_immediate (-value);
21766 inverted = encode_thumb32_immediate (~value);
21767
21768 rd = (*instruction >> 8) & 0xf;
21769 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21770 switch (op)
21771 {
21772 /* ADD <-> SUB. Includes CMP <-> CMN. */
21773 case T2_OPCODE_SUB:
21774 new_inst = T2_OPCODE_ADD;
21775 value = negated;
21776 break;
21777
21778 case T2_OPCODE_ADD:
21779 new_inst = T2_OPCODE_SUB;
21780 value = negated;
21781 break;
21782
21783 /* ORR <-> ORN. Includes MOV <-> MVN. */
21784 case T2_OPCODE_ORR:
21785 new_inst = T2_OPCODE_ORN;
21786 value = inverted;
21787 break;
21788
21789 case T2_OPCODE_ORN:
21790 new_inst = T2_OPCODE_ORR;
21791 value = inverted;
21792 break;
21793
21794 /* AND <-> BIC. TST has no inverted equivalent. */
21795 case T2_OPCODE_AND:
21796 new_inst = T2_OPCODE_BIC;
21797 if (rd == 15)
21798 value = FAIL;
21799 else
21800 value = inverted;
21801 break;
21802
21803 case T2_OPCODE_BIC:
21804 new_inst = T2_OPCODE_AND;
21805 value = inverted;
21806 break;
21807
21808 /* ADC <-> SBC */
21809 case T2_OPCODE_ADC:
21810 new_inst = T2_OPCODE_SBC;
21811 value = inverted;
21812 break;
21813
21814 case T2_OPCODE_SBC:
21815 new_inst = T2_OPCODE_ADC;
21816 value = inverted;
21817 break;
21818
21819 /* We cannot do anything. */
21820 default:
21821 return FAIL;
21822 }
21823
16dd5e42 21824 if (value == (unsigned int)FAIL)
ef8d22e6
PB		 21825 return FAIL;
21826
21827 *instruction &= T2_OPCODE_MASK;
21828 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21829 return value;
21830}
21831
8f06b2d8
PB		 21832/* Read a 32-bit thumb instruction from buf. */
21833static unsigned long
21834get_thumb32_insn (char * buf)
21835{
21836 unsigned long insn;
21837 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21838 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21839
21840 return insn;
21841}
21842
a8bc6c78
PB		 21843
21844/* We usually want to set the low bit on the address of thumb function
21845 symbols. In particular .word foo - . should have the low bit set.
21846 Generic code tries to fold the difference of two symbols to
21847 a constant. Prevent this and force a relocation when the first symbols
21848 is a thumb function. */
c921be7d
NC		 21849
21850bfd_boolean
a8bc6c78
PB		 21851arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21852{
21853 if (op == O_subtract
21854 && l->X_op == O_symbol
21855 && r->X_op == O_symbol
21856 && THUMB_IS_FUNC (l->X_add_symbol))
21857 {
21858 l->X_op = O_subtract;
21859 l->X_op_symbol = r->X_add_symbol;
21860 l->X_add_number -= r->X_add_number;
c921be7d 21861 return TRUE;
a8bc6c78 21862 }
c921be7d 21863
a8bc6c78 21864 /* Process as normal. */
c921be7d 21865 return FALSE;
a8bc6c78
PB		 21866}
21867
4a42ebbc
RR		 21868/* Encode Thumb2 unconditional branches and calls. The encoding
21869 for the 2 are identical for the immediate values. */
21870
21871static void
21872encode_thumb2_b_bl_offset (char * buf, offsetT value)
21873{
21874#define T2I1I2MASK ((1 << 13) | (1 << 11))
21875 offsetT newval;
21876 offsetT newval2;
21877 addressT S, I1, I2, lo, hi;
21878
21879 S = (value >> 24) & 0x01;
21880 I1 = (value >> 23) & 0x01;
21881 I2 = (value >> 22) & 0x01;
21882 hi = (value >> 12) & 0x3ff;
fa94de6b 21883 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR		 21884 newval = md_chars_to_number (buf, THUMB_SIZE);
21885 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21886 newval |= (S << 10) | hi;
21887 newval2 &= ~T2I1I2MASK;
21888 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21889 md_number_to_chars (buf, newval, THUMB_SIZE);
21890 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21891}
21892
c19d1205 21893void
55cf6793 21894md_apply_fix (fixS * fixP,
c19d1205
ZW		 21895 valueT * valP,
21896 segT seg)
21897{
21898 offsetT value = * valP;
21899 offsetT newval;
21900 unsigned int newimm;
21901 unsigned long temp;
21902 int sign;
21903 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 21904
9c2799c2 21905 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 21906
c19d1205 21907 /* Note whether this will delete the relocation. */
4962c51a 21908
c19d1205
ZW		 21909 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21910 fixP->fx_done = 1;
b99bd4ef 21911
adbaf948 21912 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 21913 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW		 21914 for emit_reloc. */
21915 value &= 0xffffffff;
21916 value ^= 0x80000000;
5f4273c7 21917 value -= 0x80000000;
adbaf948
ZW		 21918
21919 *valP = value;
c19d1205 21920 fixP->fx_addnumber = value;
b99bd4ef 21921
adbaf948
ZW		 21922 /* Same treatment for fixP->fx_offset. */
21923 fixP->fx_offset &= 0xffffffff;
21924 fixP->fx_offset ^= 0x80000000;
21925 fixP->fx_offset -= 0x80000000;
21926
c19d1205 21927 switch (fixP->fx_r_type)
b99bd4ef 21928 {
c19d1205
ZW		 21929 case BFD_RELOC_NONE:
21930 /* This will need to go in the object file. */
21931 fixP->fx_done = 0;
21932 break;
b99bd4ef 21933
c19d1205
ZW		 21934 case BFD_RELOC_ARM_IMMEDIATE:
21935 /* We claim that this fixup has been processed here,
21936 even if in fact we generate an error because we do
21937 not have a reloc for it, so tc_gen_reloc will reject it. */
21938 fixP->fx_done = 1;
b99bd4ef 21939
77db8e2e 21940 if (fixP->fx_addsy)
b99bd4ef 21941 {
77db8e2e 21942 const char *msg = 0;
b99bd4ef 21943
77db8e2e
NC		 21944 if (! S_IS_DEFINED (fixP->fx_addsy))
21945 msg = _("undefined symbol %s used as an immediate value");
21946 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21947 msg = _("symbol %s is in a different section");
21948 else if (S_IS_WEAK (fixP->fx_addsy))
21949 msg = _("symbol %s is weak and may be overridden later");
21950
21951 if (msg)
21952 {
21953 as_bad_where (fixP->fx_file, fixP->fx_line,
21954 msg, S_GET_NAME (fixP->fx_addsy));
21955 break;
21956 }
42e5fcbf
AS		 21957 }
21958
c19d1205
ZW		 21959 temp = md_chars_to_number (buf, INSN_SIZE);
21960
5e73442d
SL		 21961 /* If the offset is negative, we should use encoding A2 for ADR. */
21962 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21963 newimm = negate_data_op (&temp, value);
21964 else
21965 {
21966 newimm = encode_arm_immediate (value);
21967
21968 /* If the instruction will fail, see if we can fix things up by
21969 changing the opcode. */
21970 if (newimm == (unsigned int) FAIL)
21971 newimm = negate_data_op (&temp, value);
21972 }
21973
21974 if (newimm == (unsigned int) FAIL)
b99bd4ef 21975 {
c19d1205
ZW		 21976 as_bad_where (fixP->fx_file, fixP->fx_line,
21977 _("invalid constant (%lx) after fixup"),
21978 (unsigned long) value);
21979 break;
b99bd4ef 21980 }
b99bd4ef 21981
c19d1205
ZW		 21982 newimm |= (temp & 0xfffff000);
21983 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21984 break;
b99bd4ef 21985
c19d1205
ZW		 21986 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
21987 {
21988 unsigned int highpart = 0;
21989 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 21990
77db8e2e 21991 if (fixP->fx_addsy)
42e5fcbf 21992 {
77db8e2e 21993 const char *msg = 0;
42e5fcbf 21994
77db8e2e
NC		 21995 if (! S_IS_DEFINED (fixP->fx_addsy))
21996 msg = _("undefined symbol %s used as an immediate value");
21997 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21998 msg = _("symbol %s is in a different section");
21999 else if (S_IS_WEAK (fixP->fx_addsy))
22000 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 22001
77db8e2e
NC		 22002 if (msg)
22003 {
22004 as_bad_where (fixP->fx_file, fixP->fx_line,
22005 msg, S_GET_NAME (fixP->fx_addsy));
22006 break;
22007 }
22008 }
fa94de6b 22009
c19d1205
ZW		 22010 newimm = encode_arm_immediate (value);
22011 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 22012
c19d1205
ZW		 22013 /* If the instruction will fail, see if we can fix things up by
22014 changing the opcode. */
22015 if (newimm == (unsigned int) FAIL
22016 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
22017 {
22018 /* No ? OK - try using two ADD instructions to generate
22019 the value. */
22020 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 22021
c19d1205
ZW		 22022 /* Yes - then make sure that the second instruction is
22023 also an add. */
22024 if (newimm != (unsigned int) FAIL)
22025 newinsn = temp;
22026 /* Still No ? Try using a negated value. */
22027 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
22028 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
22029 /* Otherwise - give up. */
22030 else
22031 {
22032 as_bad_where (fixP->fx_file, fixP->fx_line,
22033 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22034 (long) value);
22035 break;
22036 }
b99bd4ef 22037
c19d1205
ZW		 22038 /* Replace the first operand in the 2nd instruction (which
22039 is the PC) with the destination register. We have
22040 already added in the PC in the first instruction and we
22041 do not want to do it again. */
22042 newinsn &= ~ 0xf0000;
22043 newinsn |= ((newinsn & 0x0f000) << 4);
22044 }
b99bd4ef 22045
c19d1205
ZW		 22046 newimm |= (temp & 0xfffff000);
22047 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 22048
c19d1205
ZW		 22049 highpart |= (newinsn & 0xfffff000);
22050 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
22051 }
22052 break;
b99bd4ef 22053
c19d1205 22054 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 22055 if (!fixP->fx_done && seg->use_rela_p)
22056 value = 0;
22057
c19d1205 22058 case BFD_RELOC_ARM_LITERAL:
26d97720 22059 sign = value > 0;
b99bd4ef 22060
c19d1205
ZW		 22061 if (value < 0)
22062 value = - value;
b99bd4ef 22063
c19d1205 22064 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 22065 {
c19d1205
ZW		 22066 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
22067 as_bad_where (fixP->fx_file, fixP->fx_line,
22068 _("invalid literal constant: pool needs to be closer"));
22069 else
22070 as_bad_where (fixP->fx_file, fixP->fx_line,
22071 _("bad immediate value for offset (%ld)"),
22072 (long) value);
22073 break;
f03698e6
RE		 22074 }
22075
c19d1205 22076 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 22077 if (value == 0)
22078 newval &= 0xfffff000;
22079 else
22080 {
22081 newval &= 0xff7ff000;
22082 newval |= value | (sign ? INDEX_UP : 0);
22083 }
c19d1205
ZW		 22084 md_number_to_chars (buf, newval, INSN_SIZE);
22085 break;
b99bd4ef 22086
c19d1205
ZW		 22087 case BFD_RELOC_ARM_OFFSET_IMM8:
22088 case BFD_RELOC_ARM_HWLITERAL:
26d97720 22089 sign = value > 0;
b99bd4ef 22090
c19d1205
ZW		 22091 if (value < 0)
22092 value = - value;
b99bd4ef 22093
c19d1205 22094 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 22095 {
c19d1205
ZW		 22096 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
22097 as_bad_where (fixP->fx_file, fixP->fx_line,
22098 _("invalid literal constant: pool needs to be closer"));
22099 else
427d0db6
RM		 22100 as_bad_where (fixP->fx_file, fixP->fx_line,
22101 _("bad immediate value for 8-bit offset (%ld)"),
22102 (long) value);
c19d1205 22103 break;
b99bd4ef
NC		 22104 }
22105
c19d1205 22106 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 22107 if (value == 0)
22108 newval &= 0xfffff0f0;
22109 else
22110 {
22111 newval &= 0xff7ff0f0;
22112 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
22113 }
c19d1205
ZW		 22114 md_number_to_chars (buf, newval, INSN_SIZE);
22115 break;
b99bd4ef 22116
c19d1205
ZW		 22117 case BFD_RELOC_ARM_T32_OFFSET_U8:
22118 if (value < 0 || value > 1020 || value % 4 != 0)
22119 as_bad_where (fixP->fx_file, fixP->fx_line,
22120 _("bad immediate value for offset (%ld)"), (long) value);
22121 value /= 4;
b99bd4ef 22122
c19d1205 22123 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW		 22124 newval |= value;
22125 md_number_to_chars (buf+2, newval, THUMB_SIZE);
22126 break;
b99bd4ef 22127
c19d1205
ZW		 22128 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22129 /* This is a complicated relocation used for all varieties of Thumb32
22130 load/store instruction with immediate offset:
22131
22132 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 22133 *4, optional writeback(W)
c19d1205
ZW		 22134 (doubleword load/store)
22135
22136 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22137 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22138 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22139 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22140 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22141
22142 Uppercase letters indicate bits that are already encoded at
22143 this point. Lowercase letters are our problem. For the
22144 second block of instructions, the secondary opcode nybble
22145 (bits 8..11) is present, and bit 23 is zero, even if this is
22146 a PC-relative operation. */
22147 newval = md_chars_to_number (buf, THUMB_SIZE);
22148 newval <<= 16;
22149 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 22150
c19d1205 22151 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 22152 {
c19d1205
ZW		 22153 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22154 if (value >= 0)
22155 newval |= (1 << 23);
22156 else
22157 value = -value;
22158 if (value % 4 != 0)
22159 {
22160 as_bad_where (fixP->fx_file, fixP->fx_line,
22161 _("offset not a multiple of 4"));
22162 break;
22163 }
22164 value /= 4;
216d22bc 22165 if (value > 0xff)
c19d1205
ZW		 22166 {
22167 as_bad_where (fixP->fx_file, fixP->fx_line,
22168 _("offset out of range"));
22169 break;
22170 }
22171 newval &= ~0xff;
b99bd4ef 22172 }
c19d1205 22173 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 22174 {
c19d1205
ZW		 22175 /* PC-relative, 12-bit offset. */
22176 if (value >= 0)
22177 newval |= (1 << 23);
22178 else
22179 value = -value;
216d22bc 22180 if (value > 0xfff)
c19d1205
ZW		 22181 {
22182 as_bad_where (fixP->fx_file, fixP->fx_line,
22183 _("offset out of range"));
22184 break;
22185 }
22186 newval &= ~0xfff;
b99bd4ef 22187 }
c19d1205 22188 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 22189 {
c19d1205
ZW		 22190 /* Writeback: 8-bit, +/- offset. */
22191 if (value >= 0)
22192 newval |= (1 << 9);
22193 else
22194 value = -value;
216d22bc 22195 if (value > 0xff)
c19d1205
ZW		 22196 {
22197 as_bad_where (fixP->fx_file, fixP->fx_line,
22198 _("offset out of range"));
22199 break;
22200 }
22201 newval &= ~0xff;
b99bd4ef 22202 }
c19d1205 22203 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 22204 {
c19d1205 22205 /* T-instruction: positive 8-bit offset. */
216d22bc 22206 if (value < 0 || value > 0xff)
b99bd4ef 22207 {
c19d1205
ZW		 22208 as_bad_where (fixP->fx_file, fixP->fx_line,
22209 _("offset out of range"));
22210 break;
b99bd4ef 22211 }
c19d1205
ZW		 22212 newval &= ~0xff;
22213 newval |= value;
b99bd4ef
NC		 22214 }
22215 else
b99bd4ef 22216 {
c19d1205
ZW		 22217 /* Positive 12-bit or negative 8-bit offset. */
22218 int limit;
22219 if (value >= 0)
b99bd4ef 22220 {
c19d1205
ZW		 22221 newval |= (1 << 23);
22222 limit = 0xfff;
22223 }
22224 else
22225 {
22226 value = -value;
22227 limit = 0xff;
22228 }
22229 if (value > limit)
22230 {
22231 as_bad_where (fixP->fx_file, fixP->fx_line,
22232 _("offset out of range"));
22233 break;
b99bd4ef 22234 }
c19d1205 22235 newval &= ~limit;
b99bd4ef 22236 }
b99bd4ef 22237
c19d1205
ZW		 22238 newval |= value;
22239 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
22240 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
22241 break;
404ff6b5 22242
c19d1205
ZW		 22243 case BFD_RELOC_ARM_SHIFT_IMM:
22244 newval = md_chars_to_number (buf, INSN_SIZE);
22245 if (((unsigned long) value) > 32
22246 || (value == 32
22247 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
22248 {
22249 as_bad_where (fixP->fx_file, fixP->fx_line,
22250 _("shift expression is too large"));
22251 break;
22252 }
404ff6b5 22253
c19d1205
ZW		 22254 if (value == 0)
22255 /* Shifts of zero must be done as lsl. */
22256 newval &= ~0x60;
22257 else if (value == 32)
22258 value = 0;
22259 newval &= 0xfffff07f;
22260 newval |= (value & 0x1f) << 7;
22261 md_number_to_chars (buf, newval, INSN_SIZE);
22262 break;
404ff6b5 22263
c19d1205 22264 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 22265 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 22266 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 22267 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW		 22268 /* We claim that this fixup has been processed here,
22269 even if in fact we generate an error because we do
22270 not have a reloc for it, so tc_gen_reloc will reject it. */
22271 fixP->fx_done = 1;
404ff6b5 22272
c19d1205
ZW		 22273 if (fixP->fx_addsy
22274 && ! S_IS_DEFINED (fixP->fx_addsy))
22275 {
22276 as_bad_where (fixP->fx_file, fixP->fx_line,
22277 _("undefined symbol %s used as an immediate value"),
22278 S_GET_NAME (fixP->fx_addsy));
22279 break;
22280 }
404ff6b5 22281
c19d1205
ZW		 22282 newval = md_chars_to_number (buf, THUMB_SIZE);
22283 newval <<= 16;
22284 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 22285
16805f35
PB		 22286 newimm = FAIL;
22287 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22288 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB		 22289 {
22290 newimm = encode_thumb32_immediate (value);
22291 if (newimm == (unsigned int) FAIL)
22292 newimm = thumb32_negate_data_op (&newval, value);
22293 }
16805f35
PB		 22294 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
22295 && newimm == (unsigned int) FAIL)
92e90b6e 22296 {
16805f35
PB		 22297 /* Turn add/sum into addw/subw. */
22298 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
22299 newval = (newval & 0xfeffffff) | 0x02000000;
40f246e3
NC		 22300 /* No flat 12-bit imm encoding for addsw/subsw. */
22301 if ((newval & 0x00100000) == 0)
e9f89963 22302 {
40f246e3
NC		 22303 /* 12 bit immediate for addw/subw. */
22304 if (value < 0)
22305 {
22306 value = -value;
22307 newval ^= 0x00a00000;
22308 }
22309 if (value > 0xfff)
22310 newimm = (unsigned int) FAIL;
22311 else
22312 newimm = value;
e9f89963 22313 }
92e90b6e 22314 }
cc8a6dd0 22315
c19d1205 22316 if (newimm == (unsigned int)FAIL)
3631a3c8 22317 {
c19d1205
ZW		 22318 as_bad_where (fixP->fx_file, fixP->fx_line,
22319 _("invalid constant (%lx) after fixup"),
22320 (unsigned long) value);
22321 break;
3631a3c8
NC		 22322 }
22323
c19d1205
ZW		 22324 newval |= (newimm & 0x800) << 15;
22325 newval |= (newimm & 0x700) << 4;
22326 newval |= (newimm & 0x0ff);
cc8a6dd0 22327
c19d1205
ZW		 22328 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
22329 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
22330 break;
a737bd4d 22331
3eb17e6b 22332 case BFD_RELOC_ARM_SMC:
c19d1205
ZW		 22333 if (((unsigned long) value) > 0xffff)
22334 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 22335 _("invalid smc expression"));
2fc8bdac 22336 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 22337 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
22338 md_number_to_chars (buf, newval, INSN_SIZE);
22339 break;
a737bd4d 22340
90ec0d68
MGD		 22341 case BFD_RELOC_ARM_HVC:
22342 if (((unsigned long) value) > 0xffff)
22343 as_bad_where (fixP->fx_file, fixP->fx_line,
22344 _("invalid hvc expression"));
22345 newval = md_chars_to_number (buf, INSN_SIZE);
22346 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
22347 md_number_to_chars (buf, newval, INSN_SIZE);
22348 break;
22349
c19d1205 22350 case BFD_RELOC_ARM_SWI:
adbaf948 22351 if (fixP->tc_fix_data != 0)
c19d1205
ZW		 22352 {
22353 if (((unsigned long) value) > 0xff)
22354 as_bad_where (fixP->fx_file, fixP->fx_line,
22355 _("invalid swi expression"));
2fc8bdac 22356 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW		 22357 newval |= value;
22358 md_number_to_chars (buf, newval, THUMB_SIZE);
22359 }
22360 else
22361 {
22362 if (((unsigned long) value) > 0x00ffffff)
22363 as_bad_where (fixP->fx_file, fixP->fx_line,
22364 _("invalid swi expression"));
2fc8bdac 22365 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 22366 newval |= value;
22367 md_number_to_chars (buf, newval, INSN_SIZE);
22368 }
22369 break;
a737bd4d 22370
c19d1205
ZW		 22371 case BFD_RELOC_ARM_MULTI:
22372 if (((unsigned long) value) > 0xffff)
22373 as_bad_where (fixP->fx_file, fixP->fx_line,
22374 _("invalid expression in load/store multiple"));
22375 newval = value | md_chars_to_number (buf, INSN_SIZE);
22376 md_number_to_chars (buf, newval, INSN_SIZE);
22377 break;
a737bd4d 22378
c19d1205 22379#ifdef OBJ_ELF
39b41c9c 22380 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR		 22381
22382 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22383 && fixP->fx_addsy
34e77a92 22384 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22385 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22386 && THUMB_IS_FUNC (fixP->fx_addsy))
22387 /* Flip the bl to blx. This is a simple flip
22388 bit here because we generate PCREL_CALL for
22389 unconditional bls. */
22390 {
22391 newval = md_chars_to_number (buf, INSN_SIZE);
22392 newval = newval | 0x10000000;
22393 md_number_to_chars (buf, newval, INSN_SIZE);
22394 temp = 1;
22395 fixP->fx_done = 1;
22396 }
39b41c9c
PB		 22397 else
22398 temp = 3;
22399 goto arm_branch_common;
22400
22401 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR		 22402 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22403 && fixP->fx_addsy
34e77a92 22404 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22405 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22406 && THUMB_IS_FUNC (fixP->fx_addsy))
22407 {
22408 /* This would map to a bl<cond>, b<cond>,
22409 b<always> to a Thumb function. We
22410 need to force a relocation for this particular
22411 case. */
22412 newval = md_chars_to_number (buf, INSN_SIZE);
22413 fixP->fx_done = 0;
22414 }
22415
2fc8bdac 22416 case BFD_RELOC_ARM_PLT32:
c19d1205 22417#endif
39b41c9c
PB		 22418 case BFD_RELOC_ARM_PCREL_BRANCH:
22419 temp = 3;
22420 goto arm_branch_common;
a737bd4d 22421
39b41c9c 22422 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 22423
39b41c9c 22424 temp = 1;
267bf995
RR		 22425 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22426 && fixP->fx_addsy
34e77a92 22427 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22428 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22429 && ARM_IS_FUNC (fixP->fx_addsy))
22430 {
22431 /* Flip the blx to a bl and warn. */
22432 const char *name = S_GET_NAME (fixP->fx_addsy);
22433 newval = 0xeb000000;
22434 as_warn_where (fixP->fx_file, fixP->fx_line,
22435 _("blx to '%s' an ARM ISA state function changed to bl"),
22436 name);
22437 md_number_to_chars (buf, newval, INSN_SIZE);
22438 temp = 3;
22439 fixP->fx_done = 1;
22440 }
22441
22442#ifdef OBJ_ELF
22443 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 22444 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR		 22445#endif
22446
39b41c9c 22447 arm_branch_common:
c19d1205 22448 /* We are going to store value (shifted right by two) in the
39b41c9c
PB		 22449 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22450 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22451 also be be clear. */
22452 if (value & temp)
c19d1205 22453 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW		 22454 _("misaligned branch destination"));
22455 if ((value & (offsetT)0xfe000000) != (offsetT)0
22456 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 22457 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22458
2fc8bdac 22459 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 22460 {
2fc8bdac
ZW		 22461 newval = md_chars_to_number (buf, INSN_SIZE);
22462 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB		 22463 /* Set the H bit on BLX instructions. */
22464 if (temp == 1)
22465 {
22466 if (value & 2)
22467 newval |= 0x01000000;
22468 else
22469 newval &= ~0x01000000;
22470 }
2fc8bdac 22471 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 22472 }
c19d1205 22473 break;
a737bd4d 22474
25fe350b
MS		 22475 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22476 /* CBZ can only branch forward. */
a737bd4d 22477
738755b0 22478 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM		 22479 (which, strictly speaking, are prohibited) will be turned into
22480 no-ops.
738755b0
MS		 22481
22482 FIXME: It may be better to remove the instruction completely and
22483 perform relaxation. */
22484 if (value == -2)
2fc8bdac
ZW		 22485 {
22486 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 22487 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW		 22488 md_number_to_chars (buf, newval, THUMB_SIZE);
22489 }
738755b0
MS		 22490 else
22491 {
22492 if (value & ~0x7e)
08f10d51 22493 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 22494
477330fc 22495 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS		 22496 {
22497 newval = md_chars_to_number (buf, THUMB_SIZE);
22498 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22499 md_number_to_chars (buf, newval, THUMB_SIZE);
22500 }
22501 }
c19d1205 22502 break;
a737bd4d 22503
c19d1205 22504 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac 22505 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
08f10d51 22506 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22507
2fc8bdac
ZW		 22508 if (fixP->fx_done || !seg->use_rela_p)
22509 {
22510 newval = md_chars_to_number (buf, THUMB_SIZE);
22511 newval |= (value & 0x1ff) >> 1;
22512 md_number_to_chars (buf, newval, THUMB_SIZE);
22513 }
c19d1205 22514 break;
a737bd4d 22515
c19d1205 22516 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac 22517 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
08f10d51 22518 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22519
2fc8bdac
ZW		 22520 if (fixP->fx_done || !seg->use_rela_p)
22521 {
22522 newval = md_chars_to_number (buf, THUMB_SIZE);
22523 newval |= (value & 0xfff) >> 1;
22524 md_number_to_chars (buf, newval, THUMB_SIZE);
22525 }
c19d1205 22526 break;
a737bd4d 22527
c19d1205 22528 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR		 22529 if (fixP->fx_addsy
22530 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 22531 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22532 && ARM_IS_FUNC (fixP->fx_addsy)
22533 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22534 {
22535 /* Force a relocation for a branch 20 bits wide. */
22536 fixP->fx_done = 0;
22537 }
08f10d51 22538 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
2fc8bdac
ZW		 22539 as_bad_where (fixP->fx_file, fixP->fx_line,
22540 _("conditional branch out of range"));
404ff6b5 22541
2fc8bdac
ZW		 22542 if (fixP->fx_done || !seg->use_rela_p)
22543 {
22544 offsetT newval2;
22545 addressT S, J1, J2, lo, hi;
404ff6b5 22546
2fc8bdac
ZW		 22547 S = (value & 0x00100000) >> 20;
22548 J2 = (value & 0x00080000) >> 19;
22549 J1 = (value & 0x00040000) >> 18;
22550 hi = (value & 0x0003f000) >> 12;
22551 lo = (value & 0x00000ffe) >> 1;
6c43fab6 22552
2fc8bdac
ZW		 22553 newval = md_chars_to_number (buf, THUMB_SIZE);
22554 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22555 newval |= (S << 10) | hi;
22556 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22557 md_number_to_chars (buf, newval, THUMB_SIZE);
22558 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22559 }
c19d1205 22560 break;
6c43fab6 22561
c19d1205 22562 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR		 22563 /* If there is a blx from a thumb state function to
22564 another thumb function flip this to a bl and warn
22565 about it. */
22566
22567 if (fixP->fx_addsy
34e77a92 22568 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22569 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22570 && THUMB_IS_FUNC (fixP->fx_addsy))
22571 {
22572 const char *name = S_GET_NAME (fixP->fx_addsy);
22573 as_warn_where (fixP->fx_file, fixP->fx_line,
22574 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22575 name);
22576 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22577 newval = newval | 0x1000;
22578 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22579 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22580 fixP->fx_done = 1;
22581 }
22582
22583
22584 goto thumb_bl_common;
22585
c19d1205 22586 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR		 22587 /* A bl from Thumb state ISA to an internal ARM state function
22588 is converted to a blx. */
22589 if (fixP->fx_addsy
22590 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 22591 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22592 && ARM_IS_FUNC (fixP->fx_addsy)
22593 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22594 {
22595 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22596 newval = newval & ~0x1000;
22597 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22598 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22599 fixP->fx_done = 1;
22600 }
22601
22602 thumb_bl_common:
22603
2fc8bdac
ZW		 22604 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22605 /* For a BLX instruction, make sure that the relocation is rounded up
22606 to a word boundary. This follows the semantics of the instruction
22607 which specifies that bit 1 of the target address will come from bit
22608 1 of the base address. */
d406f3e4
JB		 22609 value = (value + 3) & ~ 3;
22610
22611#ifdef OBJ_ELF
22612 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22613 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22614 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22615#endif
404ff6b5 22616
2b2f5df9
NC		 22617 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22618 {
22619 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22620 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22621 else if ((value & ~0x1ffffff)
22622 && ((value & ~0x1ffffff) != ~0x1ffffff))
22623 as_bad_where (fixP->fx_file, fixP->fx_line,
22624 _("Thumb2 branch out of range"));
22625 }
4a42ebbc
RR		 22626
22627 if (fixP->fx_done || !seg->use_rela_p)
22628 encode_thumb2_b_bl_offset (buf, value);
22629
c19d1205 22630 break;
404ff6b5 22631
c19d1205 22632 case BFD_RELOC_THUMB_PCREL_BRANCH25:
08f10d51
NC		 22633 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22634 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 22635
2fc8bdac 22636 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 22637 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 22638
2fc8bdac 22639 break;
a737bd4d 22640
2fc8bdac
ZW		 22641 case BFD_RELOC_8:
22642 if (fixP->fx_done || !seg->use_rela_p)
4b1a927e 22643 *buf = value;
c19d1205 22644 break;
a737bd4d 22645
c19d1205 22646 case BFD_RELOC_16:
2fc8bdac 22647 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 22648 md_number_to_chars (buf, value, 2);
c19d1205 22649 break;
a737bd4d 22650
c19d1205 22651#ifdef OBJ_ELF
0855e32b
NS		 22652 case BFD_RELOC_ARM_TLS_CALL:
22653 case BFD_RELOC_ARM_THM_TLS_CALL:
22654 case BFD_RELOC_ARM_TLS_DESCSEQ:
22655 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
0855e32b 22656 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 22657 case BFD_RELOC_ARM_TLS_GD32:
22658 case BFD_RELOC_ARM_TLS_LE32:
22659 case BFD_RELOC_ARM_TLS_IE32:
22660 case BFD_RELOC_ARM_TLS_LDM32:
22661 case BFD_RELOC_ARM_TLS_LDO32:
22662 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4b1a927e 22663 break;
6c43fab6 22664
c19d1205
ZW		 22665 case BFD_RELOC_ARM_GOT32:
22666 case BFD_RELOC_ARM_GOTOFF:
c19d1205 22667 break;
b43420e6
NC		 22668
22669 case BFD_RELOC_ARM_GOT_PREL:
22670 if (fixP->fx_done || !seg->use_rela_p)
477330fc 22671 md_number_to_chars (buf, value, 4);
b43420e6
NC		 22672 break;
22673
9a6f4e97
NS		 22674 case BFD_RELOC_ARM_TARGET2:
22675 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM		 22676 addend here for REL targets, because it won't be written out
22677 during reloc processing later. */
9a6f4e97
NS		 22678 if (fixP->fx_done || !seg->use_rela_p)
22679 md_number_to_chars (buf, fixP->fx_offset, 4);
22680 break;
c19d1205 22681#endif
6c43fab6 22682
c19d1205
ZW		 22683 case BFD_RELOC_RVA:
22684 case BFD_RELOC_32:
22685 case BFD_RELOC_ARM_TARGET1:
22686 case BFD_RELOC_ARM_ROSEGREL32:
22687 case BFD_RELOC_ARM_SBREL32:
22688 case BFD_RELOC_32_PCREL:
f0927246
NC		 22689#ifdef TE_PE
22690 case BFD_RELOC_32_SECREL:
22691#endif
2fc8bdac 22692 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC		 22693#ifdef TE_WINCE
22694 /* For WinCE we only do this for pcrel fixups. */
22695 if (fixP->fx_done || fixP->fx_pcrel)
22696#endif
22697 md_number_to_chars (buf, value, 4);
c19d1205 22698 break;
6c43fab6 22699
c19d1205
ZW		 22700#ifdef OBJ_ELF
22701 case BFD_RELOC_ARM_PREL31:
2fc8bdac 22702 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW		 22703 {
22704 newval = md_chars_to_number (buf, 4) & 0x80000000;
22705 if ((value ^ (value >> 1)) & 0x40000000)
22706 {
22707 as_bad_where (fixP->fx_file, fixP->fx_line,
22708 _("rel31 relocation overflow"));
22709 }
22710 newval |= value & 0x7fffffff;
22711 md_number_to_chars (buf, newval, 4);
22712 }
22713 break;
c19d1205 22714#endif
a737bd4d 22715
c19d1205 22716 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 22717 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
c19d1205
ZW		 22718 if (value < -1023 || value > 1023 || (value & 3))
22719 as_bad_where (fixP->fx_file, fixP->fx_line,
22720 _("co-processor offset out of range"));
22721 cp_off_common:
26d97720 22722 sign = value > 0;
c19d1205
ZW		 22723 if (value < 0)
22724 value = -value;
8f06b2d8
PB		 22725 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22726 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22727 newval = md_chars_to_number (buf, INSN_SIZE);
22728 else
22729 newval = get_thumb32_insn (buf);
26d97720
NS		 22730 if (value == 0)
22731 newval &= 0xffffff00;
22732 else
22733 {
22734 newval &= 0xff7fff00;
22735 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22736 }
8f06b2d8
PB		 22737 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22738 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22739 md_number_to_chars (buf, newval, INSN_SIZE);
22740 else
22741 put_thumb32_insn (buf, newval);
c19d1205 22742 break;
a737bd4d 22743
c19d1205 22744 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 22745 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW		 22746 if (value < -255 || value > 255)
22747 as_bad_where (fixP->fx_file, fixP->fx_line,
22748 _("co-processor offset out of range"));
df7849c5 22749 value *= 4;
c19d1205 22750 goto cp_off_common;
6c43fab6 22751
c19d1205
ZW		 22752 case BFD_RELOC_ARM_THUMB_OFFSET:
22753 newval = md_chars_to_number (buf, THUMB_SIZE);
22754 /* Exactly what ranges, and where the offset is inserted depends
22755 on the type of instruction, we can establish this from the
22756 top 4 bits. */
22757 switch (newval >> 12)
22758 {
22759 case 4: /* PC load. */
22760 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22761 forced to zero for these loads; md_pcrel_from has already
22762 compensated for this. */
22763 if (value & 3)
22764 as_bad_where (fixP->fx_file, fixP->fx_line,
22765 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC		 22766 (((unsigned long) fixP->fx_frag->fr_address
22767 + (unsigned long) fixP->fx_where) & ~3)
22768 + (unsigned long) value);
a737bd4d 22769
c19d1205
ZW		 22770 if (value & ~0x3fc)
22771 as_bad_where (fixP->fx_file, fixP->fx_line,
22772 _("invalid offset, value too big (0x%08lX)"),
22773 (long) value);
a737bd4d 22774
c19d1205
ZW		 22775 newval |= value >> 2;
22776 break;
a737bd4d 22777
c19d1205
ZW		 22778 case 9: /* SP load/store. */
22779 if (value & ~0x3fc)
22780 as_bad_where (fixP->fx_file, fixP->fx_line,
22781 _("invalid offset, value too big (0x%08lX)"),
22782 (long) value);
22783 newval |= value >> 2;
22784 break;
6c43fab6 22785
c19d1205
ZW		 22786 case 6: /* Word load/store. */
22787 if (value & ~0x7c)
22788 as_bad_where (fixP->fx_file, fixP->fx_line,
22789 _("invalid offset, value too big (0x%08lX)"),
22790 (long) value);
22791 newval |= value << 4; /* 6 - 2. */
22792 break;
a737bd4d 22793
c19d1205
ZW		 22794 case 7: /* Byte load/store. */
22795 if (value & ~0x1f)
22796 as_bad_where (fixP->fx_file, fixP->fx_line,
22797 _("invalid offset, value too big (0x%08lX)"),
22798 (long) value);
22799 newval |= value << 6;
22800 break;
a737bd4d 22801
c19d1205
ZW		 22802 case 8: /* Halfword load/store. */
22803 if (value & ~0x3e)
22804 as_bad_where (fixP->fx_file, fixP->fx_line,
22805 _("invalid offset, value too big (0x%08lX)"),
22806 (long) value);
22807 newval |= value << 5; /* 6 - 1. */
22808 break;
a737bd4d 22809
c19d1205
ZW		 22810 default:
22811 as_bad_where (fixP->fx_file, fixP->fx_line,
22812 "Unable to process relocation for thumb opcode: %lx",
22813 (unsigned long) newval);
22814 break;
22815 }
22816 md_number_to_chars (buf, newval, THUMB_SIZE);
22817 break;
a737bd4d 22818
c19d1205
ZW		 22819 case BFD_RELOC_ARM_THUMB_ADD:
22820 /* This is a complicated relocation, since we use it for all of
22821 the following immediate relocations:
a737bd4d 22822
c19d1205
ZW		 22823 3bit ADD/SUB
22824 8bit ADD/SUB
22825 9bit ADD/SUB SP word-aligned
22826 10bit ADD PC/SP word-aligned
a737bd4d 22827
c19d1205
ZW		 22828 The type of instruction being processed is encoded in the
22829 instruction field:
a737bd4d 22830
c19d1205
ZW		 22831 0x8000 SUB
22832 0x00F0 Rd
22833 0x000F Rs
22834 */
22835 newval = md_chars_to_number (buf, THUMB_SIZE);
22836 {
22837 int rd = (newval >> 4) & 0xf;
22838 int rs = newval & 0xf;
22839 int subtract = !!(newval & 0x8000);
a737bd4d 22840
c19d1205
ZW		 22841 /* Check for HI regs, only very restricted cases allowed:
22842 Adjusting SP, and using PC or SP to get an address. */
22843 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22844 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22845 as_bad_where (fixP->fx_file, fixP->fx_line,
22846 _("invalid Hi register with immediate"));
a737bd4d 22847
c19d1205
ZW		 22848 /* If value is negative, choose the opposite instruction. */
22849 if (value < 0)
22850 {
22851 value = -value;
22852 subtract = !subtract;
22853 if (value < 0)
22854 as_bad_where (fixP->fx_file, fixP->fx_line,
22855 _("immediate value out of range"));
22856 }
a737bd4d 22857
c19d1205
ZW		 22858 if (rd == REG_SP)
22859 {
22860 if (value & ~0x1fc)
22861 as_bad_where (fixP->fx_file, fixP->fx_line,
22862 _("invalid immediate for stack address calculation"));
22863 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22864 newval |= value >> 2;
22865 }
22866 else if (rs == REG_PC || rs == REG_SP)
22867 {
22868 if (subtract || value & ~0x3fc)
22869 as_bad_where (fixP->fx_file, fixP->fx_line,
22870 _("invalid immediate for address calculation (value = 0x%08lX)"),
22871 (unsigned long) value);
22872 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22873 newval |= rd << 8;
22874 newval |= value >> 2;
22875 }
22876 else if (rs == rd)
22877 {
22878 if (value & ~0xff)
22879 as_bad_where (fixP->fx_file, fixP->fx_line,
22880 _("immediate value out of range"));
22881 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22882 newval |= (rd << 8) | value;
22883 }
22884 else
22885 {
22886 if (value & ~0x7)
22887 as_bad_where (fixP->fx_file, fixP->fx_line,
22888 _("immediate value out of range"));
22889 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22890 newval |= rd | (rs << 3) | (value << 6);
22891 }
22892 }
22893 md_number_to_chars (buf, newval, THUMB_SIZE);
22894 break;
a737bd4d 22895
c19d1205
ZW		 22896 case BFD_RELOC_ARM_THUMB_IMM:
22897 newval = md_chars_to_number (buf, THUMB_SIZE);
22898 if (value < 0 || value > 255)
22899 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 22900 _("invalid immediate: %ld is out of range"),
c19d1205
ZW		 22901 (long) value);
22902 newval |= value;
22903 md_number_to_chars (buf, newval, THUMB_SIZE);
22904 break;
a737bd4d 22905
c19d1205
ZW		 22906 case BFD_RELOC_ARM_THUMB_SHIFT:
22907 /* 5bit shift value (0..32). LSL cannot take 32. */
22908 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22909 temp = newval & 0xf800;
22910 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22911 as_bad_where (fixP->fx_file, fixP->fx_line,
22912 _("invalid shift value: %ld"), (long) value);
22913 /* Shifts of zero must be encoded as LSL. */
22914 if (value == 0)
22915 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22916 /* Shifts of 32 are encoded as zero. */
22917 else if (value == 32)
22918 value = 0;
22919 newval |= value << 6;
22920 md_number_to_chars (buf, newval, THUMB_SIZE);
22921 break;
a737bd4d 22922
c19d1205
ZW		 22923 case BFD_RELOC_VTABLE_INHERIT:
22924 case BFD_RELOC_VTABLE_ENTRY:
22925 fixP->fx_done = 0;
22926 return;
6c43fab6 22927
b6895b4f
PB		 22928 case BFD_RELOC_ARM_MOVW:
22929 case BFD_RELOC_ARM_MOVT:
22930 case BFD_RELOC_ARM_THUMB_MOVW:
22931 case BFD_RELOC_ARM_THUMB_MOVT:
22932 if (fixP->fx_done || !seg->use_rela_p)
22933 {
22934 /* REL format relocations are limited to a 16-bit addend. */
22935 if (!fixP->fx_done)
22936 {
39623e12 22937 if (value < -0x8000 || value > 0x7fff)
b6895b4f 22938 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 22939 _("offset out of range"));
b6895b4f
PB		 22940 }
22941 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22942 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22943 {
22944 value >>= 16;
22945 }
22946
22947 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22948 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22949 {
22950 newval = get_thumb32_insn (buf);
22951 newval &= 0xfbf08f00;
22952 newval |= (value & 0xf000) << 4;
22953 newval |= (value & 0x0800) << 15;
22954 newval |= (value & 0x0700) << 4;
22955 newval |= (value & 0x00ff);
22956 put_thumb32_insn (buf, newval);
22957 }
22958 else
22959 {
22960 newval = md_chars_to_number (buf, 4);
22961 newval &= 0xfff0f000;
22962 newval |= value & 0x0fff;
22963 newval |= (value & 0xf000) << 4;
22964 md_number_to_chars (buf, newval, 4);
22965 }
22966 }
22967 return;
22968
4962c51a
MS		 22969 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22970 case BFD_RELOC_ARM_ALU_PC_G0:
22971 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22972 case BFD_RELOC_ARM_ALU_PC_G1:
22973 case BFD_RELOC_ARM_ALU_PC_G2:
22974 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22975 case BFD_RELOC_ARM_ALU_SB_G0:
22976 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22977 case BFD_RELOC_ARM_ALU_SB_G1:
22978 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 22979 gas_assert (!fixP->fx_done);
4962c51a
MS		 22980 if (!seg->use_rela_p)
22981 {
477330fc
RM		 22982 bfd_vma insn;
22983 bfd_vma encoded_addend;
22984 bfd_vma addend_abs = abs (value);
22985
22986 /* Check that the absolute value of the addend can be
22987 expressed as an 8-bit constant plus a rotation. */
22988 encoded_addend = encode_arm_immediate (addend_abs);
22989 if (encoded_addend == (unsigned int) FAIL)
4962c51a 22990 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 22991 _("the offset 0x%08lX is not representable"),
22992 (unsigned long) addend_abs);
22993
22994 /* Extract the instruction. */
22995 insn = md_chars_to_number (buf, INSN_SIZE);
22996
22997 /* If the addend is positive, use an ADD instruction.
22998 Otherwise use a SUB. Take care not to destroy the S bit. */
22999 insn &= 0xff1fffff;
23000 if (value < 0)
23001 insn |= 1 << 22;
23002 else
23003 insn |= 1 << 23;
23004
23005 /* Place the encoded addend into the first 12 bits of the
23006 instruction. */
23007 insn &= 0xfffff000;
23008 insn |= encoded_addend;
23009
23010 /* Update the instruction. */
23011 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS		 23012 }
23013 break;
23014
23015 case BFD_RELOC_ARM_LDR_PC_G0:
23016 case BFD_RELOC_ARM_LDR_PC_G1:
23017 case BFD_RELOC_ARM_LDR_PC_G2:
23018 case BFD_RELOC_ARM_LDR_SB_G0:
23019 case BFD_RELOC_ARM_LDR_SB_G1:
23020 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 23021 gas_assert (!fixP->fx_done);
4962c51a 23022 if (!seg->use_rela_p)
477330fc
RM		 23023 {
23024 bfd_vma insn;
23025 bfd_vma addend_abs = abs (value);
4962c51a 23026
477330fc
RM		 23027 /* Check that the absolute value of the addend can be
23028 encoded in 12 bits. */
23029 if (addend_abs >= 0x1000)
4962c51a 23030 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23031 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23032 (unsigned long) addend_abs);
23033
23034 /* Extract the instruction. */
23035 insn = md_chars_to_number (buf, INSN_SIZE);
23036
23037 /* If the addend is negative, clear bit 23 of the instruction.
23038 Otherwise set it. */
23039 if (value < 0)
23040 insn &= ~(1 << 23);
23041 else
23042 insn |= 1 << 23;
23043
23044 /* Place the absolute value of the addend into the first 12 bits
23045 of the instruction. */
23046 insn &= 0xfffff000;
23047 insn |= addend_abs;
23048
23049 /* Update the instruction. */
23050 md_number_to_chars (buf, insn, INSN_SIZE);
23051 }
4962c51a
MS		 23052 break;
23053
23054 case BFD_RELOC_ARM_LDRS_PC_G0:
23055 case BFD_RELOC_ARM_LDRS_PC_G1:
23056 case BFD_RELOC_ARM_LDRS_PC_G2:
23057 case BFD_RELOC_ARM_LDRS_SB_G0:
23058 case BFD_RELOC_ARM_LDRS_SB_G1:
23059 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 23060 gas_assert (!fixP->fx_done);
4962c51a 23061 if (!seg->use_rela_p)
477330fc
RM		 23062 {
23063 bfd_vma insn;
23064 bfd_vma addend_abs = abs (value);
4962c51a 23065
477330fc
RM		 23066 /* Check that the absolute value of the addend can be
23067 encoded in 8 bits. */
23068 if (addend_abs >= 0x100)
4962c51a 23069 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23070 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23071 (unsigned long) addend_abs);
23072
23073 /* Extract the instruction. */
23074 insn = md_chars_to_number (buf, INSN_SIZE);
23075
23076 /* If the addend is negative, clear bit 23 of the instruction.
23077 Otherwise set it. */
23078 if (value < 0)
23079 insn &= ~(1 << 23);
23080 else
23081 insn |= 1 << 23;
23082
23083 /* Place the first four bits of the absolute value of the addend
23084 into the first 4 bits of the instruction, and the remaining
23085 four into bits 8 .. 11. */
23086 insn &= 0xfffff0f0;
23087 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
23088
23089 /* Update the instruction. */
23090 md_number_to_chars (buf, insn, INSN_SIZE);
23091 }
4962c51a
MS		 23092 break;
23093
23094 case BFD_RELOC_ARM_LDC_PC_G0:
23095 case BFD_RELOC_ARM_LDC_PC_G1:
23096 case BFD_RELOC_ARM_LDC_PC_G2:
23097 case BFD_RELOC_ARM_LDC_SB_G0:
23098 case BFD_RELOC_ARM_LDC_SB_G1:
23099 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 23100 gas_assert (!fixP->fx_done);
4962c51a 23101 if (!seg->use_rela_p)
477330fc
RM		 23102 {
23103 bfd_vma insn;
23104 bfd_vma addend_abs = abs (value);
4962c51a 23105
477330fc
RM		 23106 /* Check that the absolute value of the addend is a multiple of
23107 four and, when divided by four, fits in 8 bits. */
23108 if (addend_abs & 0x3)
4962c51a 23109 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23110 _("bad offset 0x%08lX (must be word-aligned)"),
23111 (unsigned long) addend_abs);
4962c51a 23112
477330fc 23113 if ((addend_abs >> 2) > 0xff)
4962c51a 23114 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23115 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23116 (unsigned long) addend_abs);
23117
23118 /* Extract the instruction. */
23119 insn = md_chars_to_number (buf, INSN_SIZE);
23120
23121 /* If the addend is negative, clear bit 23 of the instruction.
23122 Otherwise set it. */
23123 if (value < 0)
23124 insn &= ~(1 << 23);
23125 else
23126 insn |= 1 << 23;
23127
23128 /* Place the addend (divided by four) into the first eight
23129 bits of the instruction. */
23130 insn &= 0xfffffff0;
23131 insn |= addend_abs >> 2;
23132
23133 /* Update the instruction. */
23134 md_number_to_chars (buf, insn, INSN_SIZE);
23135 }
4962c51a
MS		 23136 break;
23137
845b51d6
PB		 23138 case BFD_RELOC_ARM_V4BX:
23139 /* This will need to go in the object file. */
23140 fixP->fx_done = 0;
23141 break;
23142
c19d1205
ZW		 23143 case BFD_RELOC_UNUSED:
23144 default:
23145 as_bad_where (fixP->fx_file, fixP->fx_line,
23146 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
23147 }
6c43fab6
RE		 23148}
23149
c19d1205
ZW		 23150/* Translate internal representation of relocation info to BFD target
23151 format. */
a737bd4d 23152
c19d1205 23153arelent *
00a97672 23154tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 23155{
c19d1205
ZW		 23156 arelent * reloc;
23157 bfd_reloc_code_real_type code;
a737bd4d 23158
21d799b5 23159 reloc = (arelent *) xmalloc (sizeof (arelent));
a737bd4d 23160
21d799b5 23161 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
c19d1205
ZW		 23162 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
23163 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 23164
2fc8bdac 23165 if (fixp->fx_pcrel)
00a97672
RS		 23166 {
23167 if (section->use_rela_p)
23168 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
23169 else
23170 fixp->fx_offset = reloc->address;
23171 }
c19d1205 23172 reloc->addend = fixp->fx_offset;
a737bd4d 23173
c19d1205 23174 switch (fixp->fx_r_type)
a737bd4d 23175 {
c19d1205
ZW		 23176 case BFD_RELOC_8:
23177 if (fixp->fx_pcrel)
23178 {
23179 code = BFD_RELOC_8_PCREL;
23180 break;
23181 }
a737bd4d 23182
c19d1205
ZW		 23183 case BFD_RELOC_16:
23184 if (fixp->fx_pcrel)
23185 {
23186 code = BFD_RELOC_16_PCREL;
23187 break;
23188 }
6c43fab6 23189
c19d1205
ZW		 23190 case BFD_RELOC_32:
23191 if (fixp->fx_pcrel)
23192 {
23193 code = BFD_RELOC_32_PCREL;
23194 break;
23195 }
a737bd4d 23196
b6895b4f
PB		 23197 case BFD_RELOC_ARM_MOVW:
23198 if (fixp->fx_pcrel)
23199 {
23200 code = BFD_RELOC_ARM_MOVW_PCREL;
23201 break;
23202 }
23203
23204 case BFD_RELOC_ARM_MOVT:
23205 if (fixp->fx_pcrel)
23206 {
23207 code = BFD_RELOC_ARM_MOVT_PCREL;
23208 break;
23209 }
23210
23211 case BFD_RELOC_ARM_THUMB_MOVW:
23212 if (fixp->fx_pcrel)
23213 {
23214 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
23215 break;
23216 }
23217
23218 case BFD_RELOC_ARM_THUMB_MOVT:
23219 if (fixp->fx_pcrel)
23220 {
23221 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
23222 break;
23223 }
23224
c19d1205
ZW		 23225 case BFD_RELOC_NONE:
23226 case BFD_RELOC_ARM_PCREL_BRANCH:
23227 case BFD_RELOC_ARM_PCREL_BLX:
23228 case BFD_RELOC_RVA:
23229 case BFD_RELOC_THUMB_PCREL_BRANCH7:
23230 case BFD_RELOC_THUMB_PCREL_BRANCH9:
23231 case BFD_RELOC_THUMB_PCREL_BRANCH12:
23232 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23233 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23234 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW		 23235 case BFD_RELOC_VTABLE_ENTRY:
23236 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC		 23237#ifdef TE_PE
23238 case BFD_RELOC_32_SECREL:
23239#endif
c19d1205
ZW		 23240 code = fixp->fx_r_type;
23241 break;
a737bd4d 23242
00adf2d4
JB		 23243 case BFD_RELOC_THUMB_PCREL_BLX:
23244#ifdef OBJ_ELF
23245 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
23246 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
23247 else
23248#endif
23249 code = BFD_RELOC_THUMB_PCREL_BLX;
23250 break;
23251
c19d1205
ZW		 23252 case BFD_RELOC_ARM_LITERAL:
23253 case BFD_RELOC_ARM_HWLITERAL:
23254 /* If this is called then the a literal has
23255 been referenced across a section boundary. */
23256 as_bad_where (fixp->fx_file, fixp->fx_line,
23257 _("literal referenced across section boundary"));
23258 return NULL;
a737bd4d 23259
c19d1205 23260#ifdef OBJ_ELF
0855e32b
NS		 23261 case BFD_RELOC_ARM_TLS_CALL:
23262 case BFD_RELOC_ARM_THM_TLS_CALL:
23263 case BFD_RELOC_ARM_TLS_DESCSEQ:
23264 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW		 23265 case BFD_RELOC_ARM_GOT32:
23266 case BFD_RELOC_ARM_GOTOFF:
b43420e6 23267 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW		 23268 case BFD_RELOC_ARM_PLT32:
23269 case BFD_RELOC_ARM_TARGET1:
23270 case BFD_RELOC_ARM_ROSEGREL32:
23271 case BFD_RELOC_ARM_SBREL32:
23272 case BFD_RELOC_ARM_PREL31:
23273 case BFD_RELOC_ARM_TARGET2:
23274 case BFD_RELOC_ARM_TLS_LE32:
23275 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB		 23276 case BFD_RELOC_ARM_PCREL_CALL:
23277 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS		 23278 case BFD_RELOC_ARM_ALU_PC_G0_NC:
23279 case BFD_RELOC_ARM_ALU_PC_G0:
23280 case BFD_RELOC_ARM_ALU_PC_G1_NC:
23281 case BFD_RELOC_ARM_ALU_PC_G1:
23282 case BFD_RELOC_ARM_ALU_PC_G2:
23283 case BFD_RELOC_ARM_LDR_PC_G0:
23284 case BFD_RELOC_ARM_LDR_PC_G1:
23285 case BFD_RELOC_ARM_LDR_PC_G2:
23286 case BFD_RELOC_ARM_LDRS_PC_G0:
23287 case BFD_RELOC_ARM_LDRS_PC_G1:
23288 case BFD_RELOC_ARM_LDRS_PC_G2:
23289 case BFD_RELOC_ARM_LDC_PC_G0:
23290 case BFD_RELOC_ARM_LDC_PC_G1:
23291 case BFD_RELOC_ARM_LDC_PC_G2:
23292 case BFD_RELOC_ARM_ALU_SB_G0_NC:
23293 case BFD_RELOC_ARM_ALU_SB_G0:
23294 case BFD_RELOC_ARM_ALU_SB_G1_NC:
23295 case BFD_RELOC_ARM_ALU_SB_G1:
23296 case BFD_RELOC_ARM_ALU_SB_G2:
23297 case BFD_RELOC_ARM_LDR_SB_G0:
23298 case BFD_RELOC_ARM_LDR_SB_G1:
23299 case BFD_RELOC_ARM_LDR_SB_G2:
23300 case BFD_RELOC_ARM_LDRS_SB_G0:
23301 case BFD_RELOC_ARM_LDRS_SB_G1:
23302 case BFD_RELOC_ARM_LDRS_SB_G2:
23303 case BFD_RELOC_ARM_LDC_SB_G0:
23304 case BFD_RELOC_ARM_LDC_SB_G1:
23305 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 23306 case BFD_RELOC_ARM_V4BX:
c19d1205
ZW		 23307 code = fixp->fx_r_type;
23308 break;
a737bd4d 23309
0855e32b 23310 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 23311 case BFD_RELOC_ARM_TLS_GD32:
23312 case BFD_RELOC_ARM_TLS_IE32:
23313 case BFD_RELOC_ARM_TLS_LDM32:
23314 /* BFD will include the symbol's address in the addend.
23315 But we don't want that, so subtract it out again here. */
23316 if (!S_IS_COMMON (fixp->fx_addsy))
23317 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
23318 code = fixp->fx_r_type;
23319 break;
23320#endif
a737bd4d 23321
c19d1205
ZW		 23322 case BFD_RELOC_ARM_IMMEDIATE:
23323 as_bad_where (fixp->fx_file, fixp->fx_line,
23324 _("internal relocation (type: IMMEDIATE) not fixed up"));
23325 return NULL;
a737bd4d 23326
c19d1205
ZW		 23327 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
23328 as_bad_where (fixp->fx_file, fixp->fx_line,
23329 _("ADRL used for a symbol not defined in the same file"));
23330 return NULL;
a737bd4d 23331
c19d1205 23332 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 23333 if (section->use_rela_p)
23334 {
23335 code = fixp->fx_r_type;
23336 break;
23337 }
23338
c19d1205
ZW		 23339 if (fixp->fx_addsy != NULL
23340 && !S_IS_DEFINED (fixp->fx_addsy)
23341 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 23342 {
c19d1205
ZW		 23343 as_bad_where (fixp->fx_file, fixp->fx_line,
23344 _("undefined local label `%s'"),
23345 S_GET_NAME (fixp->fx_addsy));
23346 return NULL;
a737bd4d
NC		 23347 }
23348
c19d1205
ZW		 23349 as_bad_where (fixp->fx_file, fixp->fx_line,
23350 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23351 return NULL;
a737bd4d 23352
c19d1205
ZW		 23353 default:
23354 {
23355 char * type;
6c43fab6 23356
c19d1205
ZW		 23357 switch (fixp->fx_r_type)
23358 {
23359 case BFD_RELOC_NONE: type = "NONE"; break;
23360 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
23361 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 23362 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW		 23363 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
23364 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
23365 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 23366 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 23367 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW		 23368 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
23369 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
23370 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
23371 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
23372 default: type = _("<unknown>"); break;
23373 }
23374 as_bad_where (fixp->fx_file, fixp->fx_line,
23375 _("cannot represent %s relocation in this object file format"),
23376 type);
23377 return NULL;
23378 }
a737bd4d 23379 }
6c43fab6 23380
c19d1205
ZW		 23381#ifdef OBJ_ELF
23382 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
23383 && GOT_symbol
23384 && fixp->fx_addsy == GOT_symbol)
23385 {
23386 code = BFD_RELOC_ARM_GOTPC;
23387 reloc->addend = fixp->fx_offset = reloc->address;
23388 }
23389#endif
6c43fab6 23390
c19d1205 23391 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 23392
c19d1205
ZW		 23393 if (reloc->howto == NULL)
23394 {
23395 as_bad_where (fixp->fx_file, fixp->fx_line,
23396 _("cannot represent %s relocation in this object file format"),
23397 bfd_get_reloc_code_name (code));
23398 return NULL;
23399 }
6c43fab6 23400
c19d1205
ZW		 23401 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23402 vtable entry to be used in the relocation's section offset. */
23403 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23404 reloc->address = fixp->fx_offset;
6c43fab6 23405
c19d1205 23406 return reloc;
6c43fab6
RE		 23407}
23408
c19d1205 23409/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 23410
c19d1205
ZW		 23411void
23412cons_fix_new_arm (fragS * frag,
23413 int where,
23414 int size,
62ebcb5c
AM		 23415 expressionS * exp,
23416 bfd_reloc_code_real_type reloc)
6c43fab6 23417{
c19d1205 23418 int pcrel = 0;
6c43fab6 23419
c19d1205
ZW		 23420 /* Pick a reloc.
23421 FIXME: @@ Should look at CPU word size. */
23422 switch (size)
23423 {
23424 case 1:
62ebcb5c 23425 reloc = BFD_RELOC_8;
c19d1205
ZW		 23426 break;
23427 case 2:
62ebcb5c 23428 reloc = BFD_RELOC_16;
c19d1205
ZW		 23429 break;
23430 case 4:
23431 default:
62ebcb5c 23432 reloc = BFD_RELOC_32;
c19d1205
ZW		 23433 break;
23434 case 8:
62ebcb5c 23435 reloc = BFD_RELOC_64;
c19d1205
ZW		 23436 break;
23437 }
6c43fab6 23438
f0927246
NC		 23439#ifdef TE_PE
23440 if (exp->X_op == O_secrel)
23441 {
23442 exp->X_op = O_symbol;
62ebcb5c 23443 reloc = BFD_RELOC_32_SECREL;
f0927246
NC		 23444 }
23445#endif
23446
62ebcb5c 23447 fix_new_exp (frag, where, size, exp, pcrel, reloc);
c19d1205 23448}
6c43fab6 23449
4343666d 23450#if defined (OBJ_COFF)
c19d1205
ZW		 23451void
23452arm_validate_fix (fixS * fixP)
6c43fab6 23453{
c19d1205
ZW		 23454 /* If the destination of the branch is a defined symbol which does not have
23455 the THUMB_FUNC attribute, then we must be calling a function which has
23456 the (interfacearm) attribute. We look for the Thumb entry point to that
23457 function and change the branch to refer to that function instead. */
23458 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23459 && fixP->fx_addsy != NULL
23460 && S_IS_DEFINED (fixP->fx_addsy)
23461 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 23462 {
c19d1205 23463 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 23464 }
c19d1205
ZW		 23465}
23466#endif
6c43fab6 23467
267bf995 23468
c19d1205
ZW		 23469int
23470arm_force_relocation (struct fix * fixp)
23471{
23472#if defined (OBJ_COFF) && defined (TE_PE)
23473 if (fixp->fx_r_type == BFD_RELOC_RVA)
23474 return 1;
23475#endif
6c43fab6 23476
267bf995
RR		 23477 /* In case we have a call or a branch to a function in ARM ISA mode from
23478 a thumb function or vice-versa force the relocation. These relocations
23479 are cleared off for some cores that might have blx and simple transformations
23480 are possible. */
23481
23482#ifdef OBJ_ELF
23483 switch (fixp->fx_r_type)
23484 {
23485 case BFD_RELOC_ARM_PCREL_JUMP:
23486 case BFD_RELOC_ARM_PCREL_CALL:
23487 case BFD_RELOC_THUMB_PCREL_BLX:
23488 if (THUMB_IS_FUNC (fixp->fx_addsy))
23489 return 1;
23490 break;
23491
23492 case BFD_RELOC_ARM_PCREL_BLX:
23493 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23494 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23495 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23496 if (ARM_IS_FUNC (fixp->fx_addsy))
23497 return 1;
23498 break;
23499
23500 default:
23501 break;
23502 }
23503#endif
23504
b5884301
PB		 23505 /* Resolve these relocations even if the symbol is extern or weak.
23506 Technically this is probably wrong due to symbol preemption.
23507 In practice these relocations do not have enough range to be useful
23508 at dynamic link time, and some code (e.g. in the Linux kernel)
23509 expects these references to be resolved. */
c19d1205
ZW		 23510 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23511 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 23512 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 23513 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB		 23514 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23515 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23516 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 23517 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB		 23518 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23519 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB		 23520 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23521 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23522 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23523 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 23524 return 0;
a737bd4d 23525
4962c51a
MS		 23526 /* Always leave these relocations for the linker. */
23527 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23528 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23529 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23530 return 1;
23531
f0291e4c
PB		 23532 /* Always generate relocations against function symbols. */
23533 if (fixp->fx_r_type == BFD_RELOC_32
23534 && fixp->fx_addsy
23535 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23536 return 1;
23537
c19d1205 23538 return generic_force_reloc (fixp);
404ff6b5
AH		 23539}
23540
0ffdc86c 23541#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB		 23542/* Relocations against function names must be left unadjusted,
23543 so that the linker can use this information to generate interworking
23544 stubs. The MIPS version of this function
c19d1205
ZW		 23545 also prevents relocations that are mips-16 specific, but I do not
23546 know why it does this.
404ff6b5 23547
c19d1205
ZW		 23548 FIXME:
23549 There is one other problem that ought to be addressed here, but
23550 which currently is not: Taking the address of a label (rather
23551 than a function) and then later jumping to that address. Such
23552 addresses also ought to have their bottom bit set (assuming that
23553 they reside in Thumb code), but at the moment they will not. */
404ff6b5 23554
c19d1205
ZW		 23555bfd_boolean
23556arm_fix_adjustable (fixS * fixP)
404ff6b5 23557{
c19d1205
ZW		 23558 if (fixP->fx_addsy == NULL)
23559 return 1;
404ff6b5 23560
e28387c3
PB		 23561 /* Preserve relocations against symbols with function type. */
23562 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 23563 return FALSE;
e28387c3 23564
c19d1205
ZW		 23565 if (THUMB_IS_FUNC (fixP->fx_addsy)
23566 && fixP->fx_subsy == NULL)
c921be7d 23567 return FALSE;
a737bd4d 23568
c19d1205
ZW		 23569 /* We need the symbol name for the VTABLE entries. */
23570 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23571 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 23572 return FALSE;
404ff6b5 23573
c19d1205
ZW		 23574 /* Don't allow symbols to be discarded on GOT related relocs. */
23575 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23576 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23577 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23578 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23579 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23580 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23581 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23582 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS		 23583 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23584 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23585 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23586 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23587 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 23588 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 23589 return FALSE;
a737bd4d 23590
4962c51a
MS		 23591 /* Similarly for group relocations. */
23592 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23593 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23594 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 23595 return FALSE;
4962c51a 23596
79947c54
CD		 23597 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23598 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23599 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23600 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23601 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23602 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23603 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23604 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23605 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 23606 return FALSE;
79947c54 23607
c921be7d 23608 return TRUE;
a737bd4d 23609}
0ffdc86c
NC		 23610#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23611
23612#ifdef OBJ_ELF
404ff6b5 23613
c19d1205
ZW		 23614const char *
23615elf32_arm_target_format (void)
404ff6b5 23616{
c19d1205
ZW		 23617#ifdef TE_SYMBIAN
23618 return (target_big_endian
23619 ? "elf32-bigarm-symbian"
23620 : "elf32-littlearm-symbian");
23621#elif defined (TE_VXWORKS)
23622 return (target_big_endian
23623 ? "elf32-bigarm-vxworks"
23624 : "elf32-littlearm-vxworks");
b38cadfb
NC		 23625#elif defined (TE_NACL)
23626 return (target_big_endian
23627 ? "elf32-bigarm-nacl"
23628 : "elf32-littlearm-nacl");
c19d1205
ZW		 23629#else
23630 if (target_big_endian)
23631 return "elf32-bigarm";
23632 else
23633 return "elf32-littlearm";
23634#endif
404ff6b5
AH		 23635}
23636
c19d1205
ZW		 23637void
23638armelf_frob_symbol (symbolS * symp,
23639 int * puntp)
404ff6b5 23640{
c19d1205
ZW		 23641 elf_frob_symbol (symp, puntp);
23642}
23643#endif
404ff6b5 23644
c19d1205 23645/* MD interface: Finalization. */
a737bd4d 23646
c19d1205
ZW		 23647void
23648arm_cleanup (void)
23649{
23650 literal_pool * pool;
a737bd4d 23651
e07e6e58
NC		 23652 /* Ensure that all the IT blocks are properly closed. */
23653 check_it_blocks_finished ();
23654
c19d1205
ZW		 23655 for (pool = list_of_pools; pool; pool = pool->next)
23656 {
5f4273c7 23657 /* Put it at the end of the relevant section. */
c19d1205
ZW		 23658 subseg_set (pool->section, pool->sub_section);
23659#ifdef OBJ_ELF
23660 arm_elf_change_section ();
23661#endif
23662 s_ltorg (0);
23663 }
404ff6b5
AH		 23664}
23665
cd000bff
DJ		 23666#ifdef OBJ_ELF
23667/* Remove any excess mapping symbols generated for alignment frags in
23668 SEC. We may have created a mapping symbol before a zero byte
23669 alignment; remove it if there's a mapping symbol after the
23670 alignment. */
23671static void
23672check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23673 void *dummy ATTRIBUTE_UNUSED)
23674{
23675 segment_info_type *seginfo = seg_info (sec);
23676 fragS *fragp;
23677
23678 if (seginfo == NULL || seginfo->frchainP == NULL)
23679 return;
23680
23681 for (fragp = seginfo->frchainP->frch_root;
23682 fragp != NULL;
23683 fragp = fragp->fr_next)
23684 {
23685 symbolS *sym = fragp->tc_frag_data.last_map;
23686 fragS *next = fragp->fr_next;
23687
23688 /* Variable-sized frags have been converted to fixed size by
23689 this point. But if this was variable-sized to start with,
23690 there will be a fixed-size frag after it. So don't handle
23691 next == NULL. */
23692 if (sym == NULL || next == NULL)
23693 continue;
23694
23695 if (S_GET_VALUE (sym) < next->fr_address)
23696 /* Not at the end of this frag. */
23697 continue;
23698 know (S_GET_VALUE (sym) == next->fr_address);
23699
23700 do
23701 {
23702 if (next->tc_frag_data.first_map != NULL)
23703 {
23704 /* Next frag starts with a mapping symbol. Discard this
23705 one. */
23706 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23707 break;
23708 }
23709
23710 if (next->fr_next == NULL)
23711 {
23712 /* This mapping symbol is at the end of the section. Discard
23713 it. */
23714 know (next->fr_fix == 0 && next->fr_var == 0);
23715 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23716 break;
23717 }
23718
23719 /* As long as we have empty frags without any mapping symbols,
23720 keep looking. */
23721 /* If the next frag is non-empty and does not start with a
23722 mapping symbol, then this mapping symbol is required. */
23723 if (next->fr_address != next->fr_next->fr_address)
23724 break;
23725
23726 next = next->fr_next;
23727 }
23728 while (next != NULL);
23729 }
23730}
23731#endif
23732
c19d1205
ZW		 23733/* Adjust the symbol table. This marks Thumb symbols as distinct from
23734 ARM ones. */
404ff6b5 23735
c19d1205
ZW		 23736void
23737arm_adjust_symtab (void)
404ff6b5 23738{
c19d1205
ZW		 23739#ifdef OBJ_COFF
23740 symbolS * sym;
404ff6b5 23741
c19d1205
ZW		 23742 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23743 {
23744 if (ARM_IS_THUMB (sym))
23745 {
23746 if (THUMB_IS_FUNC (sym))
23747 {
23748 /* Mark the symbol as a Thumb function. */
23749 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23750 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23751 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 23752
c19d1205
ZW		 23753 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23754 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23755 else
23756 as_bad (_("%s: unexpected function type: %d"),
23757 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23758 }
23759 else switch (S_GET_STORAGE_CLASS (sym))
23760 {
23761 case C_EXT:
23762 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23763 break;
23764 case C_STAT:
23765 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23766 break;
23767 case C_LABEL:
23768 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23769 break;
23770 default:
23771 /* Do nothing. */
23772 break;
23773 }
23774 }
a737bd4d 23775
c19d1205
ZW		 23776 if (ARM_IS_INTERWORK (sym))
23777 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 23778 }
c19d1205
ZW		 23779#endif
23780#ifdef OBJ_ELF
23781 symbolS * sym;
23782 char bind;
404ff6b5 23783
c19d1205 23784 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 23785 {
c19d1205
ZW		 23786 if (ARM_IS_THUMB (sym))
23787 {
23788 elf_symbol_type * elf_sym;
404ff6b5 23789
c19d1205
ZW		 23790 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23791 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 23792
b0796911
PB		 23793 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23794 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW		 23795 {
23796 /* If it's a .thumb_func, declare it as so,
23797 otherwise tag label as .code 16. */
23798 if (THUMB_IS_FUNC (sym))
35fc36a8
RS		 23799 elf_sym->internal_elf_sym.st_target_internal
23800 = ST_BRANCH_TO_THUMB;
3ba67470 23801 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW		 23802 elf_sym->internal_elf_sym.st_info =
23803 ELF_ST_INFO (bind, STT_ARM_16BIT);
23804 }
23805 }
23806 }
cd000bff
DJ		 23807
23808 /* Remove any overlapping mapping symbols generated by alignment frags. */
23809 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM		 23810 /* Now do generic ELF adjustments. */
23811 elf_adjust_symtab ();
c19d1205 23812#endif
404ff6b5
AH		 23813}
23814
c19d1205 23815/* MD interface: Initialization. */
404ff6b5 23816
a737bd4d 23817static void
c19d1205 23818set_constant_flonums (void)
a737bd4d 23819{
c19d1205 23820 int i;
404ff6b5 23821
c19d1205
ZW		 23822 for (i = 0; i < NUM_FLOAT_VALS; i++)
23823 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23824 abort ();
a737bd4d 23825}
404ff6b5 23826
3e9e4fcf
JB		 23827/* Auto-select Thumb mode if it's the only available instruction set for the
23828 given architecture. */
23829
23830static void
23831autoselect_thumb_from_cpu_variant (void)
23832{
23833 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23834 opcode_select (16);
23835}
23836
c19d1205
ZW		 23837void
23838md_begin (void)
a737bd4d 23839{
c19d1205
ZW		 23840 unsigned mach;
23841 unsigned int i;
404ff6b5 23842
c19d1205
ZW		 23843 if ( (arm_ops_hsh = hash_new ()) == NULL
23844 || (arm_cond_hsh = hash_new ()) == NULL
23845 || (arm_shift_hsh = hash_new ()) == NULL
23846 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 23847 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 23848 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB		 23849 || (arm_reloc_hsh = hash_new ()) == NULL
23850 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW		 23851 as_fatal (_("virtual memory exhausted"));
23852
23853 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 23854 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 23855 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 23856 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
c19d1205 23857 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 23858 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 23859 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 23860 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 23861 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 23862 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 23863 (void *) (v7m_psrs + i));
c19d1205 23864 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 23865 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB		 23866 for (i = 0;
23867 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23868 i++)
d3ce72d0 23869 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 23870 (void *) (barrier_opt_names + i));
c19d1205 23871#ifdef OBJ_ELF
3da1d841
NC		 23872 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23873 {
23874 struct reloc_entry * entry = reloc_names + i;
23875
23876 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23877 /* This makes encode_branch() use the EABI versions of this relocation. */
23878 entry->reloc = BFD_RELOC_UNUSED;
23879
23880 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23881 }
c19d1205
ZW		 23882#endif
23883
23884 set_constant_flonums ();
404ff6b5 23885
c19d1205
ZW		 23886 /* Set the cpu variant based on the command-line options. We prefer
23887 -mcpu= over -march= if both are set (as for GCC); and we prefer
23888 -mfpu= over any other way of setting the floating point unit.
23889 Use of legacy options with new options are faulted. */
e74cfd16 23890 if (legacy_cpu)
404ff6b5 23891 {
e74cfd16 23892 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW		 23893 as_bad (_("use of old and new-style options to set CPU type"));
23894
23895 mcpu_cpu_opt = legacy_cpu;
404ff6b5 23896 }
e74cfd16 23897 else if (!mcpu_cpu_opt)
c19d1205 23898 mcpu_cpu_opt = march_cpu_opt;
404ff6b5 23899
e74cfd16 23900 if (legacy_fpu)
c19d1205 23901 {
e74cfd16 23902 if (mfpu_opt)
c19d1205 23903 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f
RE		 23904
23905 mfpu_opt = legacy_fpu;
23906 }
e74cfd16 23907 else if (!mfpu_opt)
03b1477f 23908 {
45eb4c1b
NS		 23909#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23910 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE		 23911 /* Some environments specify a default FPU. If they don't, infer it
23912 from the processor. */
e74cfd16 23913 if (mcpu_fpu_opt)
03b1477f
RE		 23914 mfpu_opt = mcpu_fpu_opt;
23915 else
23916 mfpu_opt = march_fpu_opt;
39c2da32 23917#else
e74cfd16 23918 mfpu_opt = &fpu_default;
39c2da32 23919#endif
03b1477f
RE		 23920 }
23921
e74cfd16 23922 if (!mfpu_opt)
03b1477f 23923 {
493cb6ef 23924 if (mcpu_cpu_opt != NULL)
e74cfd16 23925 mfpu_opt = &fpu_default;
493cb6ef 23926 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
e74cfd16 23927 mfpu_opt = &fpu_arch_vfp_v2;
03b1477f 23928 else
e74cfd16 23929 mfpu_opt = &fpu_arch_fpa;
03b1477f
RE		 23930 }
23931
ee065d83 23932#ifdef CPU_DEFAULT
e74cfd16 23933 if (!mcpu_cpu_opt)
ee065d83 23934 {
e74cfd16
PB		 23935 mcpu_cpu_opt = &cpu_default;
23936 selected_cpu = cpu_default;
ee065d83 23937 }
e74cfd16
PB		 23938#else
23939 if (mcpu_cpu_opt)
23940 selected_cpu = *mcpu_cpu_opt;
ee065d83 23941 else
e74cfd16 23942 mcpu_cpu_opt = &arm_arch_any;
ee065d83 23943#endif
03b1477f 23944
e74cfd16 23945 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
03b1477f 23946
3e9e4fcf
JB		 23947 autoselect_thumb_from_cpu_variant ();
23948
e74cfd16 23949 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 23950
f17c130b 23951#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 23952 {
7cc69913
NC		 23953 unsigned int flags = 0;
23954
23955#if defined OBJ_ELF
23956 flags = meabi_flags;
d507cf36
PB		 23957
23958 switch (meabi_flags)
33a392fb 23959 {
d507cf36 23960 case EF_ARM_EABI_UNKNOWN:
7cc69913 23961#endif
d507cf36
PB		 23962 /* Set the flags in the private structure. */
23963 if (uses_apcs_26) flags |= F_APCS26;
23964 if (support_interwork) flags |= F_INTERWORK;
23965 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 23966 if (pic_code) flags |= F_PIC;
e74cfd16 23967 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC		 23968 flags |= F_SOFT_FLOAT;
23969
d507cf36
PB		 23970 switch (mfloat_abi_opt)
23971 {
23972 case ARM_FLOAT_ABI_SOFT:
23973 case ARM_FLOAT_ABI_SOFTFP:
23974 flags |= F_SOFT_FLOAT;
23975 break;
33a392fb 23976
d507cf36
PB		 23977 case ARM_FLOAT_ABI_HARD:
23978 if (flags & F_SOFT_FLOAT)
23979 as_bad (_("hard-float conflicts with specified fpu"));
23980 break;
23981 }
03b1477f 23982
e74cfd16
PB		 23983 /* Using pure-endian doubles (even if soft-float). */
23984 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 23985 flags |= F_VFP_FLOAT;
f17c130b 23986
fde78edd 23987#if defined OBJ_ELF
e74cfd16 23988 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 23989 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB		 23990 break;
23991
8cb51566 23992 case EF_ARM_EABI_VER4:
3a4a14e9 23993 case EF_ARM_EABI_VER5:
c19d1205 23994 /* No additional flags to set. */
d507cf36
PB		 23995 break;
23996
23997 default:
23998 abort ();
23999 }
7cc69913 24000#endif
b99bd4ef
NC		 24001 bfd_set_private_flags (stdoutput, flags);
24002
24003 /* We have run out flags in the COFF header to encode the
24004 status of ATPCS support, so instead we create a dummy,
c19d1205 24005 empty, debug section called .arm.atpcs. */
b99bd4ef
NC		 24006 if (atpcs)
24007 {
24008 asection * sec;
24009
24010 sec = bfd_make_section (stdoutput, ".arm.atpcs");
24011
24012 if (sec != NULL)
24013 {
24014 bfd_set_section_flags
24015 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
24016 bfd_set_section_size (stdoutput, sec, 0);
24017 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
24018 }
24019 }
7cc69913 24020 }
f17c130b 24021#endif
b99bd4ef
NC		 24022
24023 /* Record the CPU type as well. */
2d447fca
JM		 24024 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
24025 mach = bfd_mach_arm_iWMMXt2;
24026 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 24027 mach = bfd_mach_arm_iWMMXt;
e74cfd16 24028 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 24029 mach = bfd_mach_arm_XScale;
e74cfd16 24030 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 24031 mach = bfd_mach_arm_ep9312;
e74cfd16 24032 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 24033 mach = bfd_mach_arm_5TE;
e74cfd16 24034 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 24035 {
e74cfd16 24036 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 24037 mach = bfd_mach_arm_5T;
24038 else
24039 mach = bfd_mach_arm_5;
24040 }
e74cfd16 24041 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 24042 {
e74cfd16 24043 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 24044 mach = bfd_mach_arm_4T;
24045 else
24046 mach = bfd_mach_arm_4;
24047 }
e74cfd16 24048 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 24049 mach = bfd_mach_arm_3M;
e74cfd16
PB		 24050 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
24051 mach = bfd_mach_arm_3;
24052 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
24053 mach = bfd_mach_arm_2a;
24054 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
24055 mach = bfd_mach_arm_2;
24056 else
24057 mach = bfd_mach_arm_unknown;
b99bd4ef
NC		 24058
24059 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
24060}
24061
c19d1205 24062/* Command line processing. */
b99bd4ef 24063
c19d1205
ZW		 24064/* md_parse_option
24065 Invocation line includes a switch not recognized by the base assembler.
24066 See if it's a processor-specific option.
b99bd4ef 24067
c19d1205
ZW		 24068 This routine is somewhat complicated by the need for backwards
24069 compatibility (since older releases of gcc can't be changed).
24070 The new options try to make the interface as compatible as
24071 possible with GCC.
b99bd4ef 24072
c19d1205 24073 New options (supported) are:
b99bd4ef 24074
c19d1205
ZW		 24075 -mcpu=<cpu name> Assemble for selected processor
24076 -march=<architecture name> Assemble for selected architecture
24077 -mfpu=<fpu architecture> Assemble for selected FPU.
24078 -EB/-mbig-endian Big-endian
24079 -EL/-mlittle-endian Little-endian
24080 -k Generate PIC code
24081 -mthumb Start in Thumb mode
24082 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 24083
278df34e 24084 -m[no-]warn-deprecated Warn about deprecated features
267bf995 24085
c19d1205 24086 For now we will also provide support for:
b99bd4ef 24087
c19d1205
ZW		 24088 -mapcs-32 32-bit Program counter
24089 -mapcs-26 26-bit Program counter
24090 -macps-float Floats passed in FP registers
24091 -mapcs-reentrant Reentrant code
24092 -matpcs
24093 (sometime these will probably be replaced with -mapcs=<list of options>
24094 and -matpcs=<list of options>)
b99bd4ef 24095
c19d1205
ZW		 24096 The remaining options are only supported for back-wards compatibility.
24097 Cpu variants, the arm part is optional:
24098 -m[arm]1 Currently not supported.
24099 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24100 -m[arm]3 Arm 3 processor
24101 -m[arm]6[xx], Arm 6 processors
24102 -m[arm]7[xx][t][[d]m] Arm 7 processors
24103 -m[arm]8[10] Arm 8 processors
24104 -m[arm]9[20][tdmi] Arm 9 processors
24105 -mstrongarm[110[0]] StrongARM processors
24106 -mxscale XScale processors
24107 -m[arm]v[2345[t[e]]] Arm architectures
24108 -mall All (except the ARM1)
24109 FP variants:
24110 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24111 -mfpe-old (No float load/store multiples)
24112 -mvfpxd VFP Single precision
24113 -mvfp All VFP
24114 -mno-fpu Disable all floating point instructions
b99bd4ef 24115
c19d1205
ZW		 24116 The following CPU names are recognized:
24117 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24118 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24119 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24120 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24121 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24122 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24123 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 24124
c19d1205 24125 */
b99bd4ef 24126
c19d1205 24127const char * md_shortopts = "m:k";
b99bd4ef 24128
c19d1205
ZW		 24129#ifdef ARM_BI_ENDIAN
24130#define OPTION_EB (OPTION_MD_BASE + 0)
24131#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 24132#else
c19d1205
ZW		 24133#if TARGET_BYTES_BIG_ENDIAN
24134#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 24135#else
c19d1205
ZW		 24136#define OPTION_EL (OPTION_MD_BASE + 1)
24137#endif
b99bd4ef 24138#endif
845b51d6 24139#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
b99bd4ef 24140
c19d1205 24141struct option md_longopts[] =
b99bd4ef 24142{
c19d1205
ZW		 24143#ifdef OPTION_EB
24144 {"EB", no_argument, NULL, OPTION_EB},
24145#endif
24146#ifdef OPTION_EL
24147 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 24148#endif
845b51d6 24149 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
c19d1205
ZW		 24150 {NULL, no_argument, NULL, 0}
24151};
b99bd4ef 24152
c19d1205 24153size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 24154
c19d1205 24155struct arm_option_table
b99bd4ef 24156{
c19d1205
ZW		 24157 char *option; /* Option name to match. */
24158 char *help; /* Help information. */
24159 int *var; /* Variable to change. */
24160 int value; /* What to change it to. */
24161 char *deprecated; /* If non-null, print this message. */
24162};
b99bd4ef 24163
c19d1205
ZW		 24164struct arm_option_table arm_opts[] =
24165{
24166 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
24167 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
24168 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24169 &support_interwork, 1, NULL},
24170 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
24171 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
24172 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
24173 1, NULL},
24174 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
24175 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
24176 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
24177 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
24178 NULL},
b99bd4ef 24179
c19d1205
ZW		 24180 /* These are recognized by the assembler, but have no affect on code. */
24181 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
24182 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS		 24183
24184 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
24185 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24186 &warn_on_deprecated, 0, NULL},
e74cfd16
PB		 24187 {NULL, NULL, NULL, 0, NULL}
24188};
24189
24190struct arm_legacy_option_table
24191{
24192 char *option; /* Option name to match. */
24193 const arm_feature_set **var; /* Variable to change. */
24194 const arm_feature_set value; /* What to change it to. */
24195 char *deprecated; /* If non-null, print this message. */
24196};
b99bd4ef 24197
e74cfd16
PB		 24198const struct arm_legacy_option_table arm_legacy_opts[] =
24199{
c19d1205
ZW		 24200 /* DON'T add any new processors to this list -- we want the whole list
24201 to go away... Add them to the processors table instead. */
e74cfd16
PB		 24202 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
24203 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
24204 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
24205 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
24206 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
24207 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
24208 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
24209 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
24210 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
24211 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
24212 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
24213 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
24214 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
24215 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
24216 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
24217 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
24218 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
24219 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
24220 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
24221 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
24222 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
24223 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
24224 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
24225 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
24226 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
24227 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
24228 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
24229 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
24230 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
24231 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
24232 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
24233 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
24234 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
24235 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
24236 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
24237 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
24238 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
24239 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
24240 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
24241 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
24242 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
24243 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
24244 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
24245 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
24246 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
24247 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
24248 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24249 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24250 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24251 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24252 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
24253 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
24254 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
24255 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
24256 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
24257 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
24258 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
24259 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
24260 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
24261 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
24262 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
24263 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
24264 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
24265 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
24266 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
24267 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
24268 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
24269 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
24270 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
24271 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 24272 N_("use -mcpu=strongarm110")},
e74cfd16 24273 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 24274 N_("use -mcpu=strongarm1100")},
e74cfd16 24275 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 24276 N_("use -mcpu=strongarm1110")},
e74cfd16
PB		 24277 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
24278 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
24279 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 24280
c19d1205 24281 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB		 24282 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
24283 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
24284 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
24285 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
24286 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
24287 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
24288 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
24289 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
24290 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
24291 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
24292 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
24293 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
24294 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
24295 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
24296 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
24297 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
24298 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
24299 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 24300
c19d1205 24301 /* Floating point variants -- don't add any more to this list either. */
e74cfd16
PB		 24302 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
24303 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
24304 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
24305 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 24306 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 24307
e74cfd16 24308 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 24309};
7ed4c4c5 24310
c19d1205 24311struct arm_cpu_option_table
7ed4c4c5 24312{
c19d1205 24313 char *name;
f3bad469 24314 size_t name_len;
e74cfd16 24315 const arm_feature_set value;
c19d1205
ZW		 24316 /* For some CPUs we assume an FPU unless the user explicitly sets
24317 -mfpu=... */
e74cfd16 24318 const arm_feature_set default_fpu;
ee065d83
PB		 24319 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24320 case. */
24321 const char *canonical_name;
c19d1205 24322};
7ed4c4c5 24323
c19d1205
ZW		 24324/* This list should, at a minimum, contain all the cpu names
24325 recognized by GCC. */
f3bad469 24326#define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
e74cfd16 24327static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 24328{
f3bad469
MGD		 24329 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
24330 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
24331 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
24332 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
24333 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
24334 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24335 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24336 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24337 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24338 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24339 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24340 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24341 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24342 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24343 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24344 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24345 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24346 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24347 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24348 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24349 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24350 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24351 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24352 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24353 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24354 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24355 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24356 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24357 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24358 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24359 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24360 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24361 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24362 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24363 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24364 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24365 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24366 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24367 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24368 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
24369 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24370 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24371 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24372 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24373 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24374 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
c19d1205
ZW		 24375 /* For V5 or later processors we default to using VFP; but the user
24376 should really set the FPU type explicitly. */
f3bad469
MGD		 24377 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24378 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24379 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
24380 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
24381 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
24382 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24383 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
24384 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24385 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24386 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
24387 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24388 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24389 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24390 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24391 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24392 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
24393 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24394 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24395 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24396 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
24397 "ARM1026EJ-S"),
24398 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
24399 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24400 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24401 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24402 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24403 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24404 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
24405 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
24406 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
24407 "ARM1136JF-S"),
24408 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
24409 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
24410 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
24411 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
24412 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
24413 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
24414 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
24415 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
24416 FPU_NONE, "Cortex-A5"),
c9fb6e58 24417 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
f3bad469
MGD		 24418 "Cortex-A7"),
24419 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
24420 ARM_FEATURE (0, FPU_VFP_V3
477330fc 24421 | FPU_NEON_EXT_V1),
f3bad469
MGD		 24422 "Cortex-A8"),
24423 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
24424 ARM_FEATURE (0, FPU_VFP_V3
477330fc 24425 | FPU_NEON_EXT_V1),
f3bad469 24426 "Cortex-A9"),
c9fb6e58 24427 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
63a4bc21 24428 "Cortex-A12"),
c9fb6e58 24429 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
f3bad469 24430 "Cortex-A15"),
d7adf960
KT		 24431 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24432 "Cortex-A17"),
92eb40d9 24433 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
477330fc 24434 "Cortex-A53"),
92eb40d9 24435 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
477330fc 24436 "Cortex-A57"),
f3bad469
MGD		 24437 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
24438 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
24439 "Cortex-R4F"),
24440 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
24441 FPU_NONE, "Cortex-R5"),
70a8bc5b 24442 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
24443 FPU_ARCH_VFP_V3D16,
24444 "Cortex-R7"),
a715796b 24445 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"),
f3bad469
MGD		 24446 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24447 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24448 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24449 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
ce32bd10 24450 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
c19d1205 24451 /* ??? XSCALE is really an architecture. */
f3bad469 24452 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
c19d1205 24453 /* ??? iwmmxt is not a processor. */
f3bad469
MGD		 24454 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24455 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24456 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
c19d1205 24457 /* Maverick */
f3bad469 24458 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
da4339ed
NC		 24459 FPU_ARCH_MAVERICK, "ARM920T"),
24460 /* Marvell processors. */
4a81b02a 24461 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
477330fc 24462 FPU_ARCH_VFP_V3D16, NULL),
4347085a
NC		 24463 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP
24464 | ARM_EXT_SEC, 0),
24465 FPU_ARCH_NEON_VFP_V4, NULL),
ea0d6bb9
PT		 24466 /* APM X-Gene family. */
24467 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24468 "APM X-Gene 1"),
24469 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24470 "APM X-Gene 2"),
da4339ed 24471
f3bad469 24472 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 24473};
f3bad469 24474#undef ARM_CPU_OPT
7ed4c4c5 24475
c19d1205 24476struct arm_arch_option_table
7ed4c4c5 24477{
c19d1205 24478 char *name;
f3bad469 24479 size_t name_len;
e74cfd16
PB		 24480 const arm_feature_set value;
24481 const arm_feature_set default_fpu;
c19d1205 24482};
7ed4c4c5 24483
c19d1205
ZW		 24484/* This list should, at a minimum, contain all the architecture names
24485 recognized by GCC. */
f3bad469 24486#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
e74cfd16 24487static const struct arm_arch_option_table arm_archs[] =
c19d1205 24488{
f3bad469
MGD		 24489 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24490 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24491 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24492 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24493 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24494 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24495 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24496 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24497 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24498 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24499 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24500 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24501 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24502 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24503 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24504 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24505 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24506 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24507 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24508 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24509 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24510 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24511 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24512 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24513 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24514 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24515 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24516 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24517 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
c450d570
PB		 24518 /* The official spelling of the ARMv7 profile variants is the dashed form.
24519 Accept the non-dashed form for compatibility with old toolchains. */
f3bad469 24520 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
c9fb6e58 24521 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
f3bad469
MGD		 24522 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24523 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24524 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24525 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24526 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24527 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
bca38921 24528 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
f3bad469
MGD		 24529 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24530 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24531 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24532 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 24533};
f3bad469 24534#undef ARM_ARCH_OPT
7ed4c4c5 24535
69133863
MGD		 24536/* ISA extensions in the co-processor and main instruction set space. */
24537struct arm_option_extension_value_table
c19d1205
ZW		 24538{
24539 char *name;
f3bad469 24540 size_t name_len;
5a70a223
JB		 24541 const arm_feature_set merge_value;
24542 const arm_feature_set clear_value;
69133863 24543 const arm_feature_set allowed_archs;
c19d1205 24544};
7ed4c4c5 24545
69133863
MGD		 24546/* The following table must be in alphabetical order with a NULL last entry.
24547 */
5a70a223 24548#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
69133863 24549static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 24550{
5a70a223
JB		 24551 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (0, CRC_EXT_ARMV8),
24552 ARM_FEATURE (ARM_EXT_V8, 0)),
bca38921 24553 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
5a70a223 24554 ARM_FEATURE (0, FPU_CRYPTO_ARMV8),
bca38921 24555 ARM_FEATURE (ARM_EXT_V8, 0)),
5a70a223 24556 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE (0, FPU_VFP_ARMV8),
bca38921 24557 ARM_FEATURE (ARM_EXT_V8, 0)),
f3bad469 24558 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
5a70a223 24559 ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
f3bad469 24560 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
5a70a223
JB		 24561 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT),
24562 ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24563 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2),
24564 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24565 ARM_EXT_OPT ("maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK),
24566 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
f3bad469 24567 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
5a70a223 24568 ARM_FEATURE (ARM_EXT_MP, 0),
f3bad469 24569 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
bca38921 24570 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
5a70a223 24571 ARM_FEATURE(0, FPU_NEON_ARMV8),
bca38921 24572 ARM_FEATURE (ARM_EXT_V8, 0)),
f3bad469 24573 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
5a70a223 24574 ARM_FEATURE (ARM_EXT_OS, 0),
f3bad469
MGD		 24575 ARM_FEATURE (ARM_EXT_V6M, 0)),
24576 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
5a70a223 24577 ARM_FEATURE (ARM_EXT_SEC, 0),
f3bad469
MGD		 24578 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24579 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24580 | ARM_EXT_DIV, 0),
5a70a223 24581 ARM_FEATURE (ARM_EXT_VIRT, 0),
f3bad469 24582 ARM_FEATURE (ARM_EXT_V7A, 0)),
5a70a223
JB		 24583 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE),
24584 ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24585 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
69133863 24586};
f3bad469 24587#undef ARM_EXT_OPT
69133863
MGD		 24588
24589/* ISA floating-point and Advanced SIMD extensions. */
24590struct arm_option_fpu_value_table
24591{
24592 char *name;
24593 const arm_feature_set value;
c19d1205 24594};
7ed4c4c5 24595
c19d1205
ZW		 24596/* This list should, at a minimum, contain all the fpu names
24597 recognized by GCC. */
69133863 24598static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW		 24599{
24600 {"softfpa", FPU_NONE},
24601 {"fpe", FPU_ARCH_FPE},
24602 {"fpe2", FPU_ARCH_FPE},
24603 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24604 {"fpa", FPU_ARCH_FPA},
24605 {"fpa10", FPU_ARCH_FPA},
24606 {"fpa11", FPU_ARCH_FPA},
24607 {"arm7500fe", FPU_ARCH_FPA},
24608 {"softvfp", FPU_ARCH_VFP},
24609 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24610 {"vfp", FPU_ARCH_VFP_V2},
24611 {"vfp9", FPU_ARCH_VFP_V2},
b1cc4aeb 24612 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
c19d1205
ZW		 24613 {"vfp10", FPU_ARCH_VFP_V2},
24614 {"vfp10-r0", FPU_ARCH_VFP_V1},
24615 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB		 24616 {"vfpv2", FPU_ARCH_VFP_V2},
24617 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 24618 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 24619 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB		 24620 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24621 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24622 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW		 24623 {"arm1020t", FPU_ARCH_VFP_V1},
24624 {"arm1020e", FPU_ARCH_VFP_V2},
24625 {"arm1136jfs", FPU_ARCH_VFP_V2},
24626 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24627 {"maverick", FPU_ARCH_MAVERICK},
5287ad62 24628 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 24629 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB		 24630 {"vfpv4", FPU_ARCH_VFP_V4},
24631 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 24632 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
a715796b
TG		 24633 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
24634 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
62f3b8c8 24635 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD		 24636 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24637 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24638 {"crypto-neon-fp-armv8",
24639 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
e74cfd16
PB		 24640 {NULL, ARM_ARCH_NONE}
24641};
24642
24643struct arm_option_value_table
24644{
24645 char *name;
24646 long value;
c19d1205 24647};
7ed4c4c5 24648
e74cfd16 24649static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW		 24650{
24651 {"hard", ARM_FLOAT_ABI_HARD},
24652 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24653 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 24654 {NULL, 0}
c19d1205 24655};
7ed4c4c5 24656
c19d1205 24657#ifdef OBJ_ELF
3a4a14e9 24658/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 24659static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW		 24660{
24661 {"gnu", EF_ARM_EABI_UNKNOWN},
24662 {"4", EF_ARM_EABI_VER4},
3a4a14e9 24663 {"5", EF_ARM_EABI_VER5},
e74cfd16 24664 {NULL, 0}
c19d1205
ZW		 24665};
24666#endif
7ed4c4c5 24667
c19d1205
ZW		 24668struct arm_long_option_table
24669{
24670 char * option; /* Substring to match. */
24671 char * help; /* Help information. */
24672 int (* func) (char * subopt); /* Function to decode sub-option. */
24673 char * deprecated; /* If non-null, print this message. */
24674};
7ed4c4c5 24675
c921be7d 24676static bfd_boolean
f3bad469 24677arm_parse_extension (char *str, const arm_feature_set **opt_p)
7ed4c4c5 24678{
21d799b5
NC		 24679 arm_feature_set *ext_set = (arm_feature_set *)
24680 xmalloc (sizeof (arm_feature_set));
e74cfd16 24681
69133863 24682 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM		 24683 extensions being added before being removed. We achieve this by having
24684 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 24685 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 24686 or removing it (0) and only allowing it to change in the order
69133863
MGD		 24687 -1 -> 1 -> 0. */
24688 const struct arm_option_extension_value_table * opt = NULL;
24689 int adding_value = -1;
24690
e74cfd16
PB		 24691 /* Copy the feature set, so that we can modify it. */
24692 *ext_set = **opt_p;
24693 *opt_p = ext_set;
24694
c19d1205 24695 while (str != NULL && *str != 0)
7ed4c4c5 24696 {
f3bad469
MGD		 24697 char *ext;
24698 size_t len;
7ed4c4c5 24699
c19d1205
ZW		 24700 if (*str != '+')
24701 {
24702 as_bad (_("invalid architectural extension"));
c921be7d 24703 return FALSE;
c19d1205 24704 }
7ed4c4c5 24705
c19d1205
ZW		 24706 str++;
24707 ext = strchr (str, '+');
7ed4c4c5 24708
c19d1205 24709 if (ext != NULL)
f3bad469 24710 len = ext - str;
c19d1205 24711 else
f3bad469 24712 len = strlen (str);
7ed4c4c5 24713
f3bad469 24714 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD		 24715 {
24716 if (adding_value != 0)
24717 {
24718 adding_value = 0;
24719 opt = arm_extensions;
24720 }
24721
f3bad469 24722 len -= 2;
69133863
MGD		 24723 str += 2;
24724 }
f3bad469 24725 else if (len > 0)
69133863
MGD		 24726 {
24727 if (adding_value == -1)
24728 {
24729 adding_value = 1;
24730 opt = arm_extensions;
24731 }
24732 else if (adding_value != 1)
24733 {
24734 as_bad (_("must specify extensions to add before specifying "
24735 "those to remove"));
24736 return FALSE;
24737 }
24738 }
24739
f3bad469 24740 if (len == 0)
c19d1205
ZW		 24741 {
24742 as_bad (_("missing architectural extension"));
c921be7d 24743 return FALSE;
c19d1205 24744 }
7ed4c4c5 24745
69133863
MGD		 24746 gas_assert (adding_value != -1);
24747 gas_assert (opt != NULL);
24748
24749 /* Scan over the options table trying to find an exact match. */
24750 for (; opt->name != NULL; opt++)
f3bad469 24751 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24752 {
69133863
MGD		 24753 /* Check we can apply the extension to this architecture. */
24754 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24755 {
24756 as_bad (_("extension does not apply to the base architecture"));
24757 return FALSE;
24758 }
24759
24760 /* Add or remove the extension. */
24761 if (adding_value)
5a70a223 24762 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
69133863 24763 else
5a70a223 24764 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
69133863 24765
c19d1205
ZW		 24766 break;
24767 }
7ed4c4c5 24768
c19d1205
ZW		 24769 if (opt->name == NULL)
24770 {
69133863
MGD		 24771 /* Did we fail to find an extension because it wasn't specified in
24772 alphabetical order, or because it does not exist? */
24773
24774 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 24775 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD		 24776 break;
24777
24778 if (opt->name == NULL)
24779 as_bad (_("unknown architectural extension `%s'"), str);
24780 else
24781 as_bad (_("architectural extensions must be specified in "
24782 "alphabetical order"));
24783
c921be7d 24784 return FALSE;
c19d1205 24785 }
69133863
MGD		 24786 else
24787 {
24788 /* We should skip the extension we've just matched the next time
24789 round. */
24790 opt++;
24791 }
7ed4c4c5 24792
c19d1205
ZW		 24793 str = ext;
24794 };
7ed4c4c5 24795
c921be7d 24796 return TRUE;
c19d1205 24797}
7ed4c4c5 24798
c921be7d 24799static bfd_boolean
f3bad469 24800arm_parse_cpu (char *str)
7ed4c4c5 24801{
f3bad469
MGD		 24802 const struct arm_cpu_option_table *opt;
24803 char *ext = strchr (str, '+');
24804 size_t len;
7ed4c4c5 24805
c19d1205 24806 if (ext != NULL)
f3bad469 24807 len = ext - str;
7ed4c4c5 24808 else
f3bad469 24809 len = strlen (str);
7ed4c4c5 24810
f3bad469 24811 if (len == 0)
7ed4c4c5 24812 {
c19d1205 24813 as_bad (_("missing cpu name `%s'"), str);
c921be7d 24814 return FALSE;
7ed4c4c5
NC		 24815 }
24816
c19d1205 24817 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 24818 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24819 {
e74cfd16
PB		 24820 mcpu_cpu_opt = &opt->value;
24821 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 24822 if (opt->canonical_name)
5f4273c7 24823 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 24824 else
24825 {
f3bad469 24826 size_t i;
c921be7d 24827
f3bad469 24828 for (i = 0; i < len; i++)
ee065d83
PB		 24829 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24830 selected_cpu_name[i] = 0;
24831 }
7ed4c4c5 24832
c19d1205
ZW		 24833 if (ext != NULL)
24834 return arm_parse_extension (ext, &mcpu_cpu_opt);
7ed4c4c5 24835
c921be7d 24836 return TRUE;
c19d1205 24837 }
7ed4c4c5 24838
c19d1205 24839 as_bad (_("unknown cpu `%s'"), str);
c921be7d 24840 return FALSE;
7ed4c4c5
NC		 24841}
24842
c921be7d 24843static bfd_boolean
f3bad469 24844arm_parse_arch (char *str)
7ed4c4c5 24845{
e74cfd16 24846 const struct arm_arch_option_table *opt;
c19d1205 24847 char *ext = strchr (str, '+');
f3bad469 24848 size_t len;
7ed4c4c5 24849
c19d1205 24850 if (ext != NULL)
f3bad469 24851 len = ext - str;
7ed4c4c5 24852 else
f3bad469 24853 len = strlen (str);
7ed4c4c5 24854
f3bad469 24855 if (len == 0)
7ed4c4c5 24856 {
c19d1205 24857 as_bad (_("missing architecture name `%s'"), str);
c921be7d 24858 return FALSE;
7ed4c4c5
NC		 24859 }
24860
c19d1205 24861 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 24862 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24863 {
e74cfd16
PB		 24864 march_cpu_opt = &opt->value;
24865 march_fpu_opt = &opt->default_fpu;
5f4273c7 24866 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 24867
c19d1205
ZW		 24868 if (ext != NULL)
24869 return arm_parse_extension (ext, &march_cpu_opt);
7ed4c4c5 24870
c921be7d 24871 return TRUE;
c19d1205
ZW		 24872 }
24873
24874 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 24875 return FALSE;
7ed4c4c5 24876}
eb043451 24877
c921be7d 24878static bfd_boolean
c19d1205
ZW		 24879arm_parse_fpu (char * str)
24880{
69133863 24881 const struct arm_option_fpu_value_table * opt;
b99bd4ef 24882
c19d1205
ZW		 24883 for (opt = arm_fpus; opt->name != NULL; opt++)
24884 if (streq (opt->name, str))
24885 {
e74cfd16 24886 mfpu_opt = &opt->value;
c921be7d 24887 return TRUE;
c19d1205 24888 }
b99bd4ef 24889
c19d1205 24890 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 24891 return FALSE;
c19d1205
ZW		 24892}
24893
c921be7d 24894static bfd_boolean
c19d1205 24895arm_parse_float_abi (char * str)
b99bd4ef 24896{
e74cfd16 24897 const struct arm_option_value_table * opt;
b99bd4ef 24898
c19d1205
ZW		 24899 for (opt = arm_float_abis; opt->name != NULL; opt++)
24900 if (streq (opt->name, str))
24901 {
24902 mfloat_abi_opt = opt->value;
c921be7d 24903 return TRUE;
c19d1205 24904 }
cc8a6dd0 24905
c19d1205 24906 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 24907 return FALSE;
c19d1205 24908}
b99bd4ef 24909
c19d1205 24910#ifdef OBJ_ELF
c921be7d 24911static bfd_boolean
c19d1205
ZW		 24912arm_parse_eabi (char * str)
24913{
e74cfd16 24914 const struct arm_option_value_table *opt;
cc8a6dd0 24915
c19d1205
ZW		 24916 for (opt = arm_eabis; opt->name != NULL; opt++)
24917 if (streq (opt->name, str))
24918 {
24919 meabi_flags = opt->value;
c921be7d 24920 return TRUE;
c19d1205
ZW		 24921 }
24922 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 24923 return FALSE;
c19d1205
ZW		 24924}
24925#endif
cc8a6dd0 24926
c921be7d 24927static bfd_boolean
e07e6e58
NC		 24928arm_parse_it_mode (char * str)
24929{
c921be7d 24930 bfd_boolean ret = TRUE;
e07e6e58
NC		 24931
24932 if (streq ("arm", str))
24933 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24934 else if (streq ("thumb", str))
24935 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24936 else if (streq ("always", str))
24937 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24938 else if (streq ("never", str))
24939 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24940 else
24941 {
24942 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 24943 "arm, thumb, always, or never."), str);
c921be7d 24944 ret = FALSE;
e07e6e58
NC		 24945 }
24946
24947 return ret;
24948}
24949
2e6976a8
DG		 24950static bfd_boolean
24951arm_ccs_mode (char * unused ATTRIBUTE_UNUSED)
24952{
24953 codecomposer_syntax = TRUE;
24954 arm_comment_chars[0] = ';';
24955 arm_line_separator_chars[0] = 0;
24956 return TRUE;
24957}
24958
c19d1205
ZW		 24959struct arm_long_option_table arm_long_opts[] =
24960{
24961 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24962 arm_parse_cpu, NULL},
24963 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24964 arm_parse_arch, NULL},
24965 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24966 arm_parse_fpu, NULL},
24967 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24968 arm_parse_float_abi, NULL},
24969#ifdef OBJ_ELF
7fac0536 24970 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW		 24971 arm_parse_eabi, NULL},
24972#endif
e07e6e58
NC		 24973 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24974 arm_parse_it_mode, NULL},
2e6976a8
DG		 24975 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24976 arm_ccs_mode, NULL},
c19d1205
ZW		 24977 {NULL, NULL, 0, NULL}
24978};
cc8a6dd0 24979
c19d1205
ZW		 24980int
24981md_parse_option (int c, char * arg)
24982{
24983 struct arm_option_table *opt;
e74cfd16 24984 const struct arm_legacy_option_table *fopt;
c19d1205 24985 struct arm_long_option_table *lopt;
b99bd4ef 24986
c19d1205 24987 switch (c)
b99bd4ef 24988 {
c19d1205
ZW		 24989#ifdef OPTION_EB
24990 case OPTION_EB:
24991 target_big_endian = 1;
24992 break;
24993#endif
cc8a6dd0 24994
c19d1205
ZW		 24995#ifdef OPTION_EL
24996 case OPTION_EL:
24997 target_big_endian = 0;
24998 break;
24999#endif
b99bd4ef 25000
845b51d6
PB		 25001 case OPTION_FIX_V4BX:
25002 fix_v4bx = TRUE;
25003 break;
25004
c19d1205
ZW		 25005 case 'a':
25006 /* Listing option. Just ignore these, we don't support additional
25007 ones. */
25008 return 0;
b99bd4ef 25009
c19d1205
ZW		 25010 default:
25011 for (opt = arm_opts; opt->option != NULL; opt++)
25012 {
25013 if (c == opt->option[0]
25014 && ((arg == NULL && opt->option[1] == 0)
25015 || streq (arg, opt->option + 1)))
25016 {
c19d1205 25017 /* If the option is deprecated, tell the user. */
278df34e 25018 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW		 25019 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25020 arg ? arg : "", _(opt->deprecated));
b99bd4ef 25021
c19d1205
ZW		 25022 if (opt->var != NULL)
25023 *opt->var = opt->value;
cc8a6dd0 25024
c19d1205
ZW		 25025 return 1;
25026 }
25027 }
b99bd4ef 25028
e74cfd16
PB		 25029 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
25030 {
25031 if (c == fopt->option[0]
25032 && ((arg == NULL && fopt->option[1] == 0)
25033 || streq (arg, fopt->option + 1)))
25034 {
e74cfd16 25035 /* If the option is deprecated, tell the user. */
278df34e 25036 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB		 25037 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25038 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB		 25039
25040 if (fopt->var != NULL)
25041 *fopt->var = &fopt->value;
25042
25043 return 1;
25044 }
25045 }
25046
c19d1205
ZW		 25047 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25048 {
25049 /* These options are expected to have an argument. */
25050 if (c == lopt->option[0]
25051 && arg != NULL
25052 && strncmp (arg, lopt->option + 1,
25053 strlen (lopt->option + 1)) == 0)
25054 {
c19d1205 25055 /* If the option is deprecated, tell the user. */
278df34e 25056 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW		 25057 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
25058 _(lopt->deprecated));
b99bd4ef 25059
c19d1205
ZW		 25060 /* Call the sup-option parser. */
25061 return lopt->func (arg + strlen (lopt->option) - 1);
25062 }
25063 }
a737bd4d 25064
c19d1205
ZW		 25065 return 0;
25066 }
a394c00f 25067
c19d1205
ZW		 25068 return 1;
25069}
a394c00f 25070
c19d1205
ZW		 25071void
25072md_show_usage (FILE * fp)
a394c00f 25073{
c19d1205
ZW		 25074 struct arm_option_table *opt;
25075 struct arm_long_option_table *lopt;
a394c00f 25076
c19d1205 25077 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 25078
c19d1205
ZW		 25079 for (opt = arm_opts; opt->option != NULL; opt++)
25080 if (opt->help != NULL)
25081 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 25082
c19d1205
ZW		 25083 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25084 if (lopt->help != NULL)
25085 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 25086
c19d1205
ZW		 25087#ifdef OPTION_EB
25088 fprintf (fp, _("\
25089 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC		 25090#endif
25091
c19d1205
ZW		 25092#ifdef OPTION_EL
25093 fprintf (fp, _("\
25094 -EL assemble code for a little-endian cpu\n"));
a737bd4d 25095#endif
845b51d6
PB		 25096
25097 fprintf (fp, _("\
25098 --fix-v4bx Allow BX in ARMv4 code\n"));
c19d1205 25099}
ee065d83
PB		 25100
25101
25102#ifdef OBJ_ELF
62b3e311
PB		 25103typedef struct
25104{
25105 int val;
25106 arm_feature_set flags;
25107} cpu_arch_ver_table;
25108
25109/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25110 least features first. */
25111static const cpu_arch_ver_table cpu_arch_ver[] =
25112{
25113 {1, ARM_ARCH_V4},
25114 {2, ARM_ARCH_V4T},
25115 {3, ARM_ARCH_V5},
ee3c0378 25116 {3, ARM_ARCH_V5T},
62b3e311
PB		 25117 {4, ARM_ARCH_V5TE},
25118 {5, ARM_ARCH_V5TEJ},
25119 {6, ARM_ARCH_V6},
7e806470 25120 {9, ARM_ARCH_V6K},
f4c65163 25121 {7, ARM_ARCH_V6Z},
91e22acd 25122 {11, ARM_ARCH_V6M},
b2a5fbdc 25123 {12, ARM_ARCH_V6SM},
7e806470 25124 {8, ARM_ARCH_V6T2},
c9fb6e58 25125 {10, ARM_ARCH_V7VE},
62b3e311
PB		 25126 {10, ARM_ARCH_V7R},
25127 {10, ARM_ARCH_V7M},
bca38921 25128 {14, ARM_ARCH_V8A},
62b3e311
PB		 25129 {0, ARM_ARCH_NONE}
25130};
25131
ee3c0378
AS		 25132/* Set an attribute if it has not already been set by the user. */
25133static void
25134aeabi_set_attribute_int (int tag, int value)
25135{
25136 if (tag < 1
25137 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
25138 || !attributes_set_explicitly[tag])
25139 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
25140}
25141
25142static void
25143aeabi_set_attribute_string (int tag, const char *value)
25144{
25145 if (tag < 1
25146 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
25147 || !attributes_set_explicitly[tag])
25148 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
25149}
25150
ee065d83 25151/* Set the public EABI object attributes. */
3cfdb781 25152void
ee065d83
PB		 25153aeabi_set_public_attributes (void)
25154{
25155 int arch;
69239280 25156 char profile;
90ec0d68 25157 int virt_sec = 0;
bca38921 25158 int fp16_optional = 0;
e74cfd16 25159 arm_feature_set flags;
62b3e311
PB		 25160 arm_feature_set tmp;
25161 const cpu_arch_ver_table *p;
ee065d83
PB		 25162
25163 /* Choose the architecture based on the capabilities of the requested cpu
25164 (if any) and/or the instructions actually used. */
e74cfd16
PB		 25165 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
25166 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
25167 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
ddd7f988
RE		 25168
25169 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
25170 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
25171
25172 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
25173 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
25174
7f78eb34
JW		 25175 selected_cpu = flags;
25176
ddd7f988 25177 /* Allow the user to override the reported architecture. */
7a1d4c38
PB		 25178 if (object_arch)
25179 {
25180 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
25181 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
25182 }
25183
251665fc
MGD		 25184 /* We need to make sure that the attributes do not identify us as v6S-M
25185 when the only v6S-M feature in use is the Operating System Extensions. */
25186 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
25187 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
477330fc 25188 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
251665fc 25189
62b3e311
PB		 25190 tmp = flags;
25191 arch = 0;
25192 for (p = cpu_arch_ver; p->val; p++)
25193 {
25194 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
25195 {
25196 arch = p->val;
25197 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
25198 }
25199 }
ee065d83 25200
9e3c6df6
PB		 25201 /* The table lookup above finds the last architecture to contribute
25202 a new feature. Unfortunately, Tag13 is a subset of the union of
25203 v6T2 and v7-M, so it is never seen as contributing a new feature.
25204 We can not search for the last entry which is entirely used,
25205 because if no CPU is specified we build up only those flags
25206 actually used. Perhaps we should separate out the specified
25207 and implicit cases. Avoid taking this path for -march=all by
25208 checking for contradictory v7-A / v7-M features. */
25209 if (arch == 10
25210 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
25211 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
25212 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
25213 arch = 13;
25214
ee065d83
PB		 25215 /* Tag_CPU_name. */
25216 if (selected_cpu_name[0])
25217 {
91d6fa6a 25218 char *q;
ee065d83 25219
91d6fa6a
NC		 25220 q = selected_cpu_name;
25221 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB		 25222 {
25223 int i;
5f4273c7 25224
91d6fa6a
NC		 25225 q += 4;
25226 for (i = 0; q[i]; i++)
25227 q[i] = TOUPPER (q[i]);
ee065d83 25228 }
91d6fa6a 25229 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 25230 }
62f3b8c8 25231
ee065d83 25232 /* Tag_CPU_arch. */
ee3c0378 25233 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 25234
62b3e311
PB		 25235 /* Tag_CPU_arch_profile. */
25236 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
69239280 25237 profile = 'A';
62b3e311 25238 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
69239280 25239 profile = 'R';
7e806470 25240 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
69239280
MGD		 25241 profile = 'M';
25242 else
25243 profile = '\0';
25244
25245 if (profile != '\0')
25246 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 25247
ee065d83 25248 /* Tag_ARM_ISA_use. */
ee3c0378
AS		 25249 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
25250 || arch == 0)
25251 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 25252
ee065d83 25253 /* Tag_THUMB_ISA_use. */
ee3c0378
AS		 25254 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
25255 || arch == 0)
25256 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
25257 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
62f3b8c8 25258
ee065d83 25259 /* Tag_VFP_arch. */
a715796b
TG		 25260 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
25261 aeabi_set_attribute_int (Tag_VFP_arch,
25262 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
25263 ? 7 : 8);
bca38921 25264 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB		 25265 aeabi_set_attribute_int (Tag_VFP_arch,
25266 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
25267 ? 5 : 6);
25268 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD		 25269 {
25270 fp16_optional = 1;
25271 aeabi_set_attribute_int (Tag_VFP_arch, 3);
25272 }
ada65aa3 25273 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD		 25274 {
25275 aeabi_set_attribute_int (Tag_VFP_arch, 4);
25276 fp16_optional = 1;
25277 }
ee3c0378
AS		 25278 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
25279 aeabi_set_attribute_int (Tag_VFP_arch, 2);
25280 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 25281 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 25282 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 25283
4547cb56
NC		 25284 /* Tag_ABI_HardFP_use. */
25285 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
25286 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
25287 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
25288
ee065d83 25289 /* Tag_WMMX_arch. */
ee3c0378
AS		 25290 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
25291 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
25292 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
25293 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 25294
ee3c0378 25295 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
bca38921
MGD		 25296 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
25297 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
25298 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
25299 {
25300 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
25301 {
25302 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
25303 }
25304 else
25305 {
25306 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
25307 fp16_optional = 1;
25308 }
25309 }
fa94de6b 25310
ee3c0378 25311 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 25312 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 25313 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 25314
69239280
MGD		 25315 /* Tag_DIV_use.
25316
25317 We set Tag_DIV_use to two when integer divide instructions have been used
25318 in ARM state, or when Thumb integer divide instructions have been used,
25319 but we have no architecture profile set, nor have we any ARM instructions.
25320
bca38921
MGD		 25321 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25322 architecture.
25323
69239280 25324 For new architectures we will have to check these tests. */
bca38921
MGD		 25325 gas_assert (arch <= TAG_CPU_ARCH_V8);
25326 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
25327 aeabi_set_attribute_int (Tag_DIV_use, 0);
25328 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
25329 || (profile == '\0'
25330 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
25331 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 25332 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD		 25333
25334 /* Tag_MP_extension_use. */
25335 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
25336 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD		 25337
25338 /* Tag Virtualization_use. */
25339 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD		 25340 virt_sec |= 1;
25341 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
25342 virt_sec |= 2;
25343 if (virt_sec != 0)
25344 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
ee065d83
PB		 25345}
25346
104d59d1 25347/* Add the default contents for the .ARM.attributes section. */
ee065d83
PB		 25348void
25349arm_md_end (void)
25350{
ee065d83
PB		 25351 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
25352 return;
25353
25354 aeabi_set_public_attributes ();
ee065d83 25355}
8463be01 25356#endif /* OBJ_ELF */
ee065d83
PB		 25357
25358
25359/* Parse a .cpu directive. */
25360
25361static void
25362s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
25363{
e74cfd16 25364 const struct arm_cpu_option_table *opt;
ee065d83
PB		 25365 char *name;
25366 char saved_char;
25367
25368 name = input_line_pointer;
5f4273c7 25369 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25370 input_line_pointer++;
25371 saved_char = *input_line_pointer;
25372 *input_line_pointer = 0;
25373
25374 /* Skip the first "all" entry. */
25375 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
25376 if (streq (opt->name, name))
25377 {
e74cfd16
PB		 25378 mcpu_cpu_opt = &opt->value;
25379 selected_cpu = opt->value;
ee065d83 25380 if (opt->canonical_name)
5f4273c7 25381 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 25382 else
25383 {
25384 int i;
25385 for (i = 0; opt->name[i]; i++)
25386 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 25387
ee065d83
PB		 25388 selected_cpu_name[i] = 0;
25389 }
e74cfd16 25390 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25391 *input_line_pointer = saved_char;
25392 demand_empty_rest_of_line ();
25393 return;
25394 }
25395 as_bad (_("unknown cpu `%s'"), name);
25396 *input_line_pointer = saved_char;
25397 ignore_rest_of_line ();
25398}
25399
25400
25401/* Parse a .arch directive. */
25402
25403static void
25404s_arm_arch (int ignored ATTRIBUTE_UNUSED)
25405{
e74cfd16 25406 const struct arm_arch_option_table *opt;
ee065d83
PB		 25407 char saved_char;
25408 char *name;
25409
25410 name = input_line_pointer;
5f4273c7 25411 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25412 input_line_pointer++;
25413 saved_char = *input_line_pointer;
25414 *input_line_pointer = 0;
25415
25416 /* Skip the first "all" entry. */
25417 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25418 if (streq (opt->name, name))
25419 {
e74cfd16
PB		 25420 mcpu_cpu_opt = &opt->value;
25421 selected_cpu = opt->value;
5f4273c7 25422 strcpy (selected_cpu_name, opt->name);
e74cfd16 25423 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25424 *input_line_pointer = saved_char;
25425 demand_empty_rest_of_line ();
25426 return;
25427 }
25428
25429 as_bad (_("unknown architecture `%s'\n"), name);
25430 *input_line_pointer = saved_char;
25431 ignore_rest_of_line ();
25432}
25433
25434
7a1d4c38
PB		 25435/* Parse a .object_arch directive. */
25436
25437static void
25438s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
25439{
25440 const struct arm_arch_option_table *opt;
25441 char saved_char;
25442 char *name;
25443
25444 name = input_line_pointer;
5f4273c7 25445 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB		 25446 input_line_pointer++;
25447 saved_char = *input_line_pointer;
25448 *input_line_pointer = 0;
25449
25450 /* Skip the first "all" entry. */
25451 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25452 if (streq (opt->name, name))
25453 {
25454 object_arch = &opt->value;
25455 *input_line_pointer = saved_char;
25456 demand_empty_rest_of_line ();
25457 return;
25458 }
25459
25460 as_bad (_("unknown architecture `%s'\n"), name);
25461 *input_line_pointer = saved_char;
25462 ignore_rest_of_line ();
25463}
25464
69133863
MGD		 25465/* Parse a .arch_extension directive. */
25466
25467static void
25468s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
25469{
25470 const struct arm_option_extension_value_table *opt;
25471 char saved_char;
25472 char *name;
25473 int adding_value = 1;
25474
25475 name = input_line_pointer;
25476 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25477 input_line_pointer++;
25478 saved_char = *input_line_pointer;
25479 *input_line_pointer = 0;
25480
25481 if (strlen (name) >= 2
25482 && strncmp (name, "no", 2) == 0)
25483 {
25484 adding_value = 0;
25485 name += 2;
25486 }
25487
25488 for (opt = arm_extensions; opt->name != NULL; opt++)
25489 if (streq (opt->name, name))
25490 {
25491 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25492 {
25493 as_bad (_("architectural extension `%s' is not allowed for the "
25494 "current base architecture"), name);
25495 break;
25496 }
25497
25498 if (adding_value)
5a70a223
JB		 25499 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
25500 opt->merge_value);
69133863 25501 else
5a70a223 25502 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
69133863
MGD		 25503
25504 mcpu_cpu_opt = &selected_cpu;
25505 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25506 *input_line_pointer = saved_char;
25507 demand_empty_rest_of_line ();
25508 return;
25509 }
25510
25511 if (opt->name == NULL)
e673710a 25512 as_bad (_("unknown architecture extension `%s'\n"), name);
69133863
MGD		 25513
25514 *input_line_pointer = saved_char;
25515 ignore_rest_of_line ();
25516}
25517
ee065d83
PB		 25518/* Parse a .fpu directive. */
25519
25520static void
25521s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25522{
69133863 25523 const struct arm_option_fpu_value_table *opt;
ee065d83
PB		 25524 char saved_char;
25525 char *name;
25526
25527 name = input_line_pointer;
5f4273c7 25528 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25529 input_line_pointer++;
25530 saved_char = *input_line_pointer;
25531 *input_line_pointer = 0;
5f4273c7 25532
ee065d83
PB		 25533 for (opt = arm_fpus; opt->name != NULL; opt++)
25534 if (streq (opt->name, name))
25535 {
e74cfd16
PB		 25536 mfpu_opt = &opt->value;
25537 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25538 *input_line_pointer = saved_char;
25539 demand_empty_rest_of_line ();
25540 return;
25541 }
25542
25543 as_bad (_("unknown floating point format `%s'\n"), name);
25544 *input_line_pointer = saved_char;
25545 ignore_rest_of_line ();
25546}
ee065d83 25547
794ba86a 25548/* Copy symbol information. */
f31fef98 25549
794ba86a
DJ		 25550void
25551arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25552{
25553 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25554}
e04befd0 25555
f31fef98 25556#ifdef OBJ_ELF
e04befd0
AS		 25557/* Given a symbolic attribute NAME, return the proper integer value.
25558 Returns -1 if the attribute is not known. */
f31fef98 25559
e04befd0
AS		 25560int
25561arm_convert_symbolic_attribute (const char *name)
25562{
f31fef98
NC		 25563 static const struct
25564 {
25565 const char * name;
25566 const int tag;
25567 }
25568 attribute_table[] =
25569 {
25570 /* When you modify this table you should
25571 also modify the list in doc/c-arm.texi. */
e04befd0 25572#define T(tag) {#tag, tag}
f31fef98
NC		 25573 T (Tag_CPU_raw_name),
25574 T (Tag_CPU_name),
25575 T (Tag_CPU_arch),
25576 T (Tag_CPU_arch_profile),
25577 T (Tag_ARM_ISA_use),
25578 T (Tag_THUMB_ISA_use),
75375b3e 25579 T (Tag_FP_arch),
f31fef98
NC		 25580 T (Tag_VFP_arch),
25581 T (Tag_WMMX_arch),
25582 T (Tag_Advanced_SIMD_arch),
25583 T (Tag_PCS_config),
25584 T (Tag_ABI_PCS_R9_use),
25585 T (Tag_ABI_PCS_RW_data),
25586 T (Tag_ABI_PCS_RO_data),
25587 T (Tag_ABI_PCS_GOT_use),
25588 T (Tag_ABI_PCS_wchar_t),
25589 T (Tag_ABI_FP_rounding),
25590 T (Tag_ABI_FP_denormal),
25591 T (Tag_ABI_FP_exceptions),
25592 T (Tag_ABI_FP_user_exceptions),
25593 T (Tag_ABI_FP_number_model),
75375b3e 25594 T (Tag_ABI_align_needed),
f31fef98 25595 T (Tag_ABI_align8_needed),
75375b3e 25596 T (Tag_ABI_align_preserved),
f31fef98
NC		 25597 T (Tag_ABI_align8_preserved),
25598 T (Tag_ABI_enum_size),
25599 T (Tag_ABI_HardFP_use),
25600 T (Tag_ABI_VFP_args),
25601 T (Tag_ABI_WMMX_args),
25602 T (Tag_ABI_optimization_goals),
25603 T (Tag_ABI_FP_optimization_goals),
25604 T (Tag_compatibility),
25605 T (Tag_CPU_unaligned_access),
75375b3e 25606 T (Tag_FP_HP_extension),
f31fef98
NC		 25607 T (Tag_VFP_HP_extension),
25608 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD		 25609 T (Tag_MPextension_use),
25610 T (Tag_DIV_use),
f31fef98
NC		 25611 T (Tag_nodefaults),
25612 T (Tag_also_compatible_with),
25613 T (Tag_conformance),
25614 T (Tag_T2EE_use),
25615 T (Tag_Virtualization_use),
cd21e546 25616 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 25617#undef T
f31fef98 25618 };
e04befd0
AS		 25619 unsigned int i;
25620
25621 if (name == NULL)
25622 return -1;
25623
f31fef98 25624 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 25625 if (streq (name, attribute_table[i].name))
e04befd0
AS		 25626 return attribute_table[i].tag;
25627
25628 return -1;
25629}
267bf995
RR		 25630
25631
25632/* Apply sym value for relocations only in the case that
25633 they are for local symbols and you have the respective
25634 architectural feature for blx and simple switches. */
25635int
25636arm_apply_sym_value (struct fix * fixP)
25637{
25638 if (fixP->fx_addsy
25639 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
34e77a92 25640 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR		 25641 {
25642 switch (fixP->fx_r_type)
25643 {
25644 case BFD_RELOC_ARM_PCREL_BLX:
25645 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25646 if (ARM_IS_FUNC (fixP->fx_addsy))
25647 return 1;
25648 break;
25649
25650 case BFD_RELOC_ARM_PCREL_CALL:
25651 case BFD_RELOC_THUMB_PCREL_BLX:
25652 if (THUMB_IS_FUNC (fixP->fx_addsy))
25653 return 1;
25654 break;
25655
25656 default:
25657 break;
25658 }
25659
25660 }
25661 return 0;
25662}
f31fef98 25663#endif /* OBJ_ELF */
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