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x86: extend %BW use to VP{COMPRESS,EXPAND}{B,W}
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
4726e9a4
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
4 (EXbScalar, EXwScalar): Fold to ...
5 (EXbwUnit): ... this.
6 (b_scalar_mode, w_scalar_mode): Fold to ...
7 (bw_unit_mode): ... this.
8 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
9 w_scalar_mode handling by bw_unit_mode one.
10 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
11 ...
12 * i386-dis-evex-prefix.h: ... here.
13
b24d668c
JB		 142020-07-14 Jan Beulich <jbeulich@suse.com>
15
16 * i386-dis.c (PCMPESTR_Fixup): Delete.
17 (dis386): Adjust "LQ" description.
18 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
19 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
20 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
21 vpcmpestrm, and vpcmpestri.
22 (putop): Honor "cond" when handling LQ.
23 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
24 vcvtsi2ss and vcvtusi2ss.
25 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
26 vcvtsi2sd and vcvtusi2sd.
27
c4de7606
JB		 282020-07-14 Jan Beulich <jbeulich@suse.com>
29
30 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
31 (simd_cmp_op): Add const.
32 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
33 (CMP_Fixup): Handle VEX case.
34 (prefix_table): Replace VCMP by CMP.
35 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
36
9ab00b61
JB		 372020-07-14 Jan Beulich <jbeulich@suse.com>
38
39 * i386-dis.c (MOVBE_Fixup): Delete.
40 (Mv): Define.
41 (prefix_table): Use Mv for movbe entries.
42
2875b28a
JB		 432020-07-14 Jan Beulich <jbeulich@suse.com>
44
45 * i386-dis.c (CRC32_Fixup): Delete.
46 (prefix_table): Use Eb/Ev for crc32 entries.
47
e184e611
JB		 482020-07-14 Jan Beulich <jbeulich@suse.com>
49
50 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
51 Conditionalize invocations of "USED_REX (0)".
52
e8b5d5f9
JB		 532020-07-14 Jan Beulich <jbeulich@suse.com>
54
55 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
56 CH, DH, BH, AX, DX): Delete.
57 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
58 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
59 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
60
260cd341
LC		 612020-07-10 Lili Cui <lili.cui@intel.com>
62
63 * i386-dis.c (TMM): New.
64 (EXtmm): Likewise.
65 (VexTmm): Likewise.
66 (MVexSIBMEM): Likewise.
67 (tmm_mode): Likewise.
68 (vex_sibmem_mode): Likewise.
69 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
70 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
71 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
72 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
73 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
74 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
75 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
76 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
77 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
78 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
79 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
80 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
81 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
82 (PREFIX_VEX_0F3849_X86_64): Likewise.
83 (PREFIX_VEX_0F384B_X86_64): Likewise.
84 (PREFIX_VEX_0F385C_X86_64): Likewise.
85 (PREFIX_VEX_0F385E_X86_64): Likewise.
86 (X86_64_VEX_0F3849): Likewise.
87 (X86_64_VEX_0F384B): Likewise.
88 (X86_64_VEX_0F385C): Likewise.
89 (X86_64_VEX_0F385E): Likewise.
90 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
91 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
92 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
93 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
94 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
95 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
96 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
97 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
98 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
99 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
100 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
101 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
102 (VEX_W_0F3849_X86_64_P_0): Likewise.
103 (VEX_W_0F3849_X86_64_P_2): Likewise.
104 (VEX_W_0F3849_X86_64_P_3): Likewise.
105 (VEX_W_0F384B_X86_64_P_1): Likewise.
106 (VEX_W_0F384B_X86_64_P_2): Likewise.
107 (VEX_W_0F384B_X86_64_P_3): Likewise.
108 (VEX_W_0F385C_X86_64_P_1): Likewise.
109 (VEX_W_0F385E_X86_64_P_0): Likewise.
110 (VEX_W_0F385E_X86_64_P_1): Likewise.
111 (VEX_W_0F385E_X86_64_P_2): Likewise.
112 (VEX_W_0F385E_X86_64_P_3): Likewise.
113 (names_tmm): Likewise.
114 (att_names_tmm): Likewise.
115 (intel_operand_size): Handle void_mode.
116 (OP_XMM): Handle tmm_mode.
117 (OP_EX): Likewise.
118 (OP_VEX): Likewise.
119 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
120 CpuAMX_BF16 and CpuAMX_TILE.
121 (operand_type_shorthands): Add RegTMM.
122 (operand_type_init): Likewise.
123 (operand_types): Add Tmmword.
124 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
125 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
126 * i386-opc.h (CpuAMX_INT8): New.
127 (CpuAMX_BF16): Likewise.
128 (CpuAMX_TILE): Likewise.
129 (SIBMEM): Likewise.
130 (Tmmword): Likewise.
131 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
132 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
133 (i386_operand_type): Add tmmword.
134 * i386-opc.tbl: Add AMX instructions.
135 * i386-reg.tbl: Add AMX registers.
136 * i386-init.h: Regenerated.
137 * i386-tbl.h: Likewise.
138
467bbef0
JB		 1392020-07-08 Jan Beulich <jbeulich@suse.com>
140
141 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
142 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
143 Rename to ...
144 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
145 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
146 respectively.
147 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
148 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
149 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
150 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
151 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
152 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
153 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
154 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
155 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
156 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
157 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
158 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
159 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
160 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
161 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
162 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
163 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
164 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
165 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
166 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
167 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
168 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
169 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
170 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
171 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
172 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
173 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
174 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
175 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
176 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
177 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
178 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
179 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
180 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
181 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
182 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
183 (reg_table): Re-order XOP entries. Adjust their operands.
184 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
185 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
186 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
187 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
188 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
189 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
190 entries by references ...
191 (vex_len_table): ... to resepctive new entries here. For several
192 new and existing entries reference ...
193 (vex_w_table): ... new entries here.
194 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
195
6384fd9e
JB		 1962020-07-08 Jan Beulich <jbeulich@suse.com>
197
198 * i386-dis.c (XMVexScalarI4): Define.
199 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
200 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
201 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
202 (vex_len_table): Move scalar FMA4 entries ...
203 (prefix_table): ... here.
204 (OP_REG_VexI4): Handle scalar_mode.
205 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
206 * i386-tbl.h: Re-generate.
207
e6123d0c
JB		 2082020-07-08 Jan Beulich <jbeulich@suse.com>
209
210 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
211 Vex_2src_2): Delete.
212 (OP_VexW, VexW): New.
213 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
214 for shifts and rotates by register.
215
93abb146
JB		 2162020-07-08 Jan Beulich <jbeulich@suse.com>
217
218 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
219 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
220 OP_EX_VexReg): Delete.
221 (OP_VexI4, VexI4): New.
222 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
223 (prefix_table): ... here.
224 (print_insn): Drop setting of vex_w_done.
225
b13b1bc0
JB		 2262020-07-08 Jan Beulich <jbeulich@suse.com>
227
228 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
229 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
230 (xop_table): Replace operands of 4-operand insns.
231 (OP_REG_VexI4): Move VEX.W based operand swaping here.
232
f337259f
CZ		 2332020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
234
235 * arc-opc.c (insert_rbd): New function.
236 (RBD): Define.
237 (RBDdup): Likewise.
238 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
239 instructions.
240
931452b6
JB		 2412020-07-07 Jan Beulich <jbeulich@suse.com>
242
243 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
244 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
245 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
246 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
247 Delete.
248 (putop): Handle "BW".
249 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
250 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
251 and 0F3A3F ...
252 * i386-dis-evex-prefix.h: ... here.
253
b5b098c2
JB		 2542020-07-06 Jan Beulich <jbeulich@suse.com>
255
256 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
257 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
258 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
259 VEX_W_0FXOP_09_83): New enumerators.
260 (xop_table): Reference the above.
261 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
262 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
263 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
264 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
265
21a3faeb
JB		 2662020-07-06 Jan Beulich <jbeulich@suse.com>
267
268 * i386-dis.c (EVEX_W_0F3838_P_1,
269 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
270 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
271 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
272 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
273 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
274 (putop): Centralize management of last[]. Delete SAVE_LAST.
275 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
276 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
277 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
278 * i386-dis-evex-prefix.h: here.
279
bc152a17
JB		 2802020-07-06 Jan Beulich <jbeulich@suse.com>
281
282 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
283 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
284 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
285 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
286 enumerators.
287 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
288 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
289 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
290 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
291 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
292 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
293 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
294 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
295 these, respectively.
296 * i386-dis-evex-len.h: Adjust comments.
297 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
298 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
299 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
300 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
301 MOD_EVEX_0F385B_P_2_W_1 table entries.
302 * i386-dis-evex-w.h: Reference mod_table[] for
303 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
304 EVEX_W_0F385B_P_2.
305
c82a99a0
JB		 3062020-07-06 Jan Beulich <jbeulich@suse.com>
307
308 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
309 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
310 EXymm.
311 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
312 Likewise. Mark 256-bit entries invalid.
313
fedfb81e
JB		 3142020-07-06 Jan Beulich <jbeulich@suse.com>
315
316 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
317 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
318 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
319 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
320 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
321 PREFIX_EVEX_0F382B): Delete.
322 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
323 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
324 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
325 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
326 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
327 to ...
328 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
329 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
330 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
331 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
332 respectively.
333 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
334 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
335 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
336 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
337 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
338 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
339 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
340 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
341 PREFIX_EVEX_0F382B): Remove table entries.
342 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
343 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
344 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
345
3a57774c
JB		 3462020-07-06 Jan Beulich <jbeulich@suse.com>
347
348 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
349 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
350 enumerators.
351 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
352 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
353 EVEX_LEN_0F3A01_P_2_W_1 table entries.
354 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
355 entries.
356
e74d9fa9
JB		 3572020-07-06 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
360 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
361 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
362 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
363 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
364 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
365 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
366 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
367 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
368 entries.
369
6431c801
JB		 3702020-07-06 Jan Beulich <jbeulich@suse.com>
371
372 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
373 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
374 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
375 respectively.
376 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
377 entries.
378 * i386-dis-evex.h (evex_table): Reference VEX table entry for
379 opcode 0F3A1D.
380 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
381 entry.
382 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
383
6df22cf6
JB		 3842020-07-06 Jan Beulich <jbeulich@suse.com>
385
386 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
387 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
388 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
389 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
390 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
391 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
392 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
393 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
394 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
395 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
396 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
397 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
398 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
399 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
400 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
401 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
402 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
403 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
404 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
405 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
406 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
407 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
408 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
409 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
410 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
411 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
412 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
413 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
414 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
415 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
416 (prefix_table): Add EXxEVexR to FMA table entries.
417 (OP_Rounding): Move abort() invocation.
418 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
419 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
420 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
421 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
422 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
423 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
424 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
425 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
426 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
427 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
428 0F3ACE, 0F3ACF.
429 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
430 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
431 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
432 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
433 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
434 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
435 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
436 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
437 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
438 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
439 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
440 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
441 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
442 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
443 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
444 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
445 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
446 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
447 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
448 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
449 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
450 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
451 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
452 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
453 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
454 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
455 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
456 Delete table entries.
457 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
458 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
459 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
460 Likewise.
461
39e0f456
JB		 4622020-07-06 Jan Beulich <jbeulich@suse.com>
463
464 * i386-dis.c (EXqScalarS): Delete.
465 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
466 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
467
5b872f7d
JB		 4682020-07-06 Jan Beulich <jbeulich@suse.com>
469
470 * i386-dis.c (safe-ctype.h): Include.
471 (EXdScalar, EXqScalar): Delete.
472 (d_scalar_mode, q_scalar_mode): Delete.
473 (prefix_table, vex_len_table): Use EXxmm_md in place of
474 EXdScalar and EXxmm_mq in place of EXqScalar.
475 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
476 d_scalar_mode and q_scalar_mode.
477 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
478 (vmovsd): Use EXxmm_mq.
479
ddc73fa9
NC		 4802020-07-06 Yuri Chornoivan <yurchor@ukr.net>
481
482 PR 26204
483 * arc-dis.c: Fix spelling mistake.
484 * po/opcodes.pot: Regenerate.
485
17550be7
NC		 4862020-07-06 Nick Clifton <nickc@redhat.com>
487
488 * po/pt_BR.po: Updated Brazilian Portugugese translation.
489 * po/uk.po: Updated Ukranian translation.
490
b19d852d
NC		 4912020-07-04 Nick Clifton <nickc@redhat.com>
492
493 * configure: Regenerate.
494 * po/opcodes.pot: Regenerate.
495
b115b9fd
NC		 4962020-07-04 Nick Clifton <nickc@redhat.com>
497
498 Binutils 2.35 branch created.
499
c2ecccb3
L		 5002020-07-02 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
503 * i386-opc.h (VexSwapSources): New.
504 (i386_opcode_modifier): Add vexswapsources.
505 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
506 with two source operands swapped.
507 * i386-tbl.h: Regenerated.
508
08ccfccf
NC		 5092020-06-30 Nelson Chu <nelson.chu@sifive.com>
510
511 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
512 unprivileged CSR can also be initialized.
513
279edac5
AM		 5142020-06-29 Alan Modra <amodra@gmail.com>
515
516 * arm-dis.c: Use C style comments.
517 * cr16-opc.c: Likewise.
518 * ft32-dis.c: Likewise.
519 * moxie-opc.c: Likewise.
520 * tic54x-dis.c: Likewise.
521 * s12z-opc.c: Remove useless comment.
522 * xgate-dis.c: Likewise.
523
e978ad62
L		 5242020-06-26 H.J. Lu <hongjiu.lu@intel.com>
525
526 * i386-opc.tbl: Add a blank line.
527
63112cd6
L		 5282020-06-26 H.J. Lu <hongjiu.lu@intel.com>
529
530 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
531 (VecSIB128): Renamed to ...
532 (VECSIB128): This.
533 (VecSIB256): Renamed to ...
534 (VECSIB256): This.
535 (VecSIB512): Renamed to ...
536 (VECSIB512): This.
537 (VecSIB): Renamed to ...
538 (SIB): This.
539 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 540 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 541 (VecSIB256): Likewise.
542 (VecSIB512): Likewise.
79b32e73 543 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 544 and VecSIB512, respectively.
545
d1c36125
JB		 5462020-06-26 Jan Beulich <jbeulich@suse.com>
547
548 * i386-dis.c: Adjust description of I macro.
549 (x86_64_table): Drop use of I.
550 (float_mem): Replace use of I.
551 (putop): Remove handling of I. Adjust setting/clearing of "alt".
552
2a1bb84c
JB		 5532020-06-26 Jan Beulich <jbeulich@suse.com>
554
555 * i386-dis.c: (print_insn): Avoid straight assignment to
556 priv.orig_sizeflag when processing -M sub-options.
557
8f570d62
JB		 5582020-06-25 Jan Beulich <jbeulich@suse.com>
559
560 * i386-dis.c: Adjust description of J macro.
561 (dis386, x86_64_table, mod_table): Replace J.
562 (putop): Remove handling of J.
563
464dc4af
JB		 5642020-06-25 Jan Beulich <jbeulich@suse.com>
565
566 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
567
589958d6
JB		 5682020-06-25 Jan Beulich <jbeulich@suse.com>
569
570 * i386-dis.c: Adjust description of "LQ" macro.
571 (dis386_twobyte): Use LQ for sysret.
572 (putop): Adjust handling of LQ.
573
39ff0b81
NC		 5742020-06-22 Nelson Chu <nelson.chu@sifive.com>
575
576 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
577 * riscv-dis.c: Include elfxx-riscv.h.
578
d27c357a
JB		 5792020-06-18 H.J. Lu <hongjiu.lu@intel.com>
580
581 * i386-dis.c (prefix_table): Revert the last vmgexit change.
582
6fde587f
CL		 5832020-06-17 Lili Cui <lili.cui@intel.com>
584
585 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
586
efe30057
L		 5872020-06-14 H.J. Lu <hongjiu.lu@intel.com>
588
589 PR gas/26115
590 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
591 * i386-opc.tbl: Likewise.
592 * i386-tbl.h: Regenerated.
593
d8af286f
NC		 5942020-06-12 Nelson Chu <nelson.chu@sifive.com>
595
596 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
597
14962256
AC		 5982020-06-11 Alex Coplan <alex.coplan@arm.com>
599
600 * aarch64-opc.c (SYSREG): New macro for describing system registers.
601 (SR_CORE): Likewise.
602 (SR_FEAT): Likewise.
603 (SR_RNG): Likewise.
604 (SR_V8_1): Likewise.
605 (SR_V8_2): Likewise.
606 (SR_V8_3): Likewise.
607 (SR_V8_4): Likewise.
608 (SR_PAN): Likewise.
609 (SR_RAS): Likewise.
610 (SR_SSBS): Likewise.
611 (SR_SVE): Likewise.
612 (SR_ID_PFR2): Likewise.
613 (SR_PROFILE): Likewise.
614 (SR_MEMTAG): Likewise.
615 (SR_SCXTNUM): Likewise.
616 (aarch64_sys_regs): Refactor to store feature information in the table.
617 (aarch64_sys_reg_supported_p): Collapse logic for system registers
618 that now describe their own features.
619 (aarch64_pstatefield_supported_p): Likewise.
620
f9630fa6
L		 6212020-06-09 H.J. Lu <hongjiu.lu@intel.com>
622
623 * i386-dis.c (prefix_table): Fix a typo in comments.
624
73239888
JB		 6252020-06-09 Jan Beulich <jbeulich@suse.com>
626
627 * i386-dis.c (rex_ignored): Delete.
628 (ckprefix): Drop rex_ignored initialization.
629 (get_valid_dis386): Drop setting of rex_ignored.
630 (print_insn): Drop checking of rex_ignored. Don't record data
631 size prefix as used with VEX-and-alike encodings.
632
18897deb
JB		 6332020-06-09 Jan Beulich <jbeulich@suse.com>
634
635 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
636 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
637 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
638 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
639 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
640 VEX_0F12, and VEX_0F16.
641 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
642 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
643 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
644 from movlps and movhlps. New MOD_0F12_PREFIX_2,
645 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
646 MOD_VEX_0F16_PREFIX_2 entries.
647
97e6786a
JB		 6482020-06-09 Jan Beulich <jbeulich@suse.com>
649
650 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
651 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
652 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
653 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
654 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
655 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
656 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
657 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
658 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
659 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
660 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
661 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
662 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
663 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
664 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
665 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
666 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
667 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
668 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
669 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
670 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
671 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
672 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
673 EVEX_W_0FC6_P_2): Delete.
674 (print_insn): Add EVEX.W vs embedded prefix consistency check
675 to prefix validation.
676 * i386-dis-evex.h (evex_table): Don't further descend for
677 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
678 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
679 and 0F2B.
680 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
681 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
682 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
683 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
684 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
685 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
686 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
687 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
688 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
689 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
690 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
691 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
692 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
693 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
694 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
695 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
696 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
697 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
698 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
699 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
700 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
701 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
702 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
703 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
704 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
705 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
706 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
707
bf926894
JB		 7082020-06-09 Jan Beulich <jbeulich@suse.com>
709
710 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
711 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
712 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
713 vmovmskpX.
714 (print_insn): Drop pointless check against bad_opcode. Split
715 prefix validation into legacy and VEX-and-alike parts.
716 (putop): Re-work 'X' macro handling.
717
a5aaedb9
JB		 7182020-06-09 Jan Beulich <jbeulich@suse.com>
719
720 * i386-dis.c (MOD_0F51): Rename to ...
721 (MOD_0F50): ... this.
722
26417f19
AC		 7232020-06-08 Alex Coplan <alex.coplan@arm.com>
724
725 * arm-dis.c (arm_opcodes): Add dfb.
726 (thumb32_opcodes): Add dfb.
727
8a6fb3f9
JB		 7282020-06-08 Jan Beulich <jbeulich@suse.com>
729
730 * i386-opc.h (reg_entry): Const-qualify reg_name field.
731
1424c35d
AM		 7322020-06-06 Alan Modra <amodra@gmail.com>
733
734 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
735
d3d1cc7b
AM		 7362020-06-05 Alan Modra <amodra@gmail.com>
737
738 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
739 size is large enough.
740
d8740be1
JM		 7412020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
742
743 * disassemble.c (disassemble_init_for_target): Set endian_code for
744 bpf targets.
745 * bpf-desc.c: Regenerate.
746 * bpf-opc.c: Likewise.
747 * bpf-dis.c: Likewise.
748
e9bffec9
JM		 7492020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
750
751 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
752 (cgen_put_insn_value): Likewise.
753 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
754 * cgen-dis.in (print_insn): Likewise.
755 * cgen-ibld.in (insert_1): Likewise.
756 (insert_1): Likewise.
757 (insert_insn_normal): Likewise.
758 (extract_1): Likewise.
759 * bpf-dis.c: Regenerate.
760 * bpf-ibld.c: Likewise.
761 * bpf-ibld.c: Likewise.
762 * cgen-dis.in: Likewise.
763 * cgen-ibld.in: Likewise.
764 * cgen-opc.c: Likewise.
765 * epiphany-dis.c: Likewise.
766 * epiphany-ibld.c: Likewise.
767 * fr30-dis.c: Likewise.
768 * fr30-ibld.c: Likewise.
769 * frv-dis.c: Likewise.
770 * frv-ibld.c: Likewise.
771 * ip2k-dis.c: Likewise.
772 * ip2k-ibld.c: Likewise.
773 * iq2000-dis.c: Likewise.
774 * iq2000-ibld.c: Likewise.
775 * lm32-dis.c: Likewise.
776 * lm32-ibld.c: Likewise.
777 * m32c-dis.c: Likewise.
778 * m32c-ibld.c: Likewise.
779 * m32r-dis.c: Likewise.
780 * m32r-ibld.c: Likewise.
781 * mep-dis.c: Likewise.
782 * mep-ibld.c: Likewise.
783 * mt-dis.c: Likewise.
784 * mt-ibld.c: Likewise.
785 * or1k-dis.c: Likewise.
786 * or1k-ibld.c: Likewise.
787 * xc16x-dis.c: Likewise.
788 * xc16x-ibld.c: Likewise.
789 * xstormy16-dis.c: Likewise.
790 * xstormy16-ibld.c: Likewise.
791
b3db6d07
JM		 7922020-06-04 Jose E. Marchesi <jemarch@gnu.org>
793
794 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
795 (print_insn_): Handle instruction endian.
796 * bpf-dis.c: Regenerate.
797 * bpf-desc.c: Regenerate.
798 * epiphany-dis.c: Likewise.
799 * epiphany-desc.c: Likewise.
800 * fr30-dis.c: Likewise.
801 * fr30-desc.c: Likewise.
802 * frv-dis.c: Likewise.
803 * frv-desc.c: Likewise.
804 * ip2k-dis.c: Likewise.
805 * ip2k-desc.c: Likewise.
806 * iq2000-dis.c: Likewise.
807 * iq2000-desc.c: Likewise.
808 * lm32-dis.c: Likewise.
809 * lm32-desc.c: Likewise.
810 * m32c-dis.c: Likewise.
811 * m32c-desc.c: Likewise.
812 * m32r-dis.c: Likewise.
813 * m32r-desc.c: Likewise.
814 * mep-dis.c: Likewise.
815 * mep-desc.c: Likewise.
816 * mt-dis.c: Likewise.
817 * mt-desc.c: Likewise.
818 * or1k-dis.c: Likewise.
819 * or1k-desc.c: Likewise.
820 * xc16x-dis.c: Likewise.
821 * xc16x-desc.c: Likewise.
822 * xstormy16-dis.c: Likewise.
823 * xstormy16-desc.c: Likewise.
824
4ee4189f
NC		 8252020-06-03 Nick Clifton <nickc@redhat.com>
826
827 * po/sr.po: Updated Serbian translation.
828
44730156
NC		 8292020-06-03 Nelson Chu <nelson.chu@sifive.com>
830
831 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
832 (riscv_get_priv_spec_class): Likewise.
833
3c3d0376
AM		 8342020-06-01 Alan Modra <amodra@gmail.com>
835
836 * bpf-desc.c: Regenerate.
837
78c1c354
JM		 8382020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
839 David Faust <david.faust@oracle.com>
840
841 * bpf-desc.c: Regenerate.
842 * bpf-opc.h: Likewise.
843 * bpf-opc.c: Likewise.
844 * bpf-dis.c: Likewise.
845
efcf5fb5
AM		 8462020-05-28 Alan Modra <amodra@gmail.com>
847
848 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
849 values.
850
ab382d64
AM		 8512020-05-28 Alan Modra <amodra@gmail.com>
852
853 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
854 immediates.
855 (print_insn_ns32k): Revert last change.
856
151f5de4
NC		 8572020-05-28 Nick Clifton <nickc@redhat.com>
858
859 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
860 static.
861
25e1eca8
SL		 8622020-05-26 Sandra Loosemore <sandra@codesourcery.com>
863
864 Fix extraction of signed constants in nios2 disassembler (again).
865
866 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
867 extractions of signed fields.
868
57b17940
SSF		 8692020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
870
871 * s390-opc.txt: Relocate vector load/store instructions with
872 additional alignment parameter and change architecture level
873 constraint from z14 to z13.
874
d96bf37b
AM		 8752020-05-21 Alan Modra <amodra@gmail.com>
876
877 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
878 * sparc-dis.c: Likewise.
879 * tic4x-dis.c: Likewise.
880 * xtensa-dis.c: Likewise.
881 * bpf-desc.c: Regenerate.
882 * epiphany-desc.c: Regenerate.
883 * fr30-desc.c: Regenerate.
884 * frv-desc.c: Regenerate.
885 * ip2k-desc.c: Regenerate.
886 * iq2000-desc.c: Regenerate.
887 * lm32-desc.c: Regenerate.
888 * m32c-desc.c: Regenerate.
889 * m32r-desc.c: Regenerate.
890 * mep-asm.c: Regenerate.
891 * mep-desc.c: Regenerate.
892 * mt-desc.c: Regenerate.
893 * or1k-desc.c: Regenerate.
894 * xc16x-desc.c: Regenerate.
895 * xstormy16-desc.c: Regenerate.
896
8f595e9b
NC		 8972020-05-20 Nelson Chu <nelson.chu@sifive.com>
898
899 * riscv-opc.c (riscv_ext_version_table): The table used to store
900 all information about the supported spec and the corresponding ISA
901 versions. Currently, only Zicsr is supported to verify the
902 correctness of Z sub extension settings. Others will be supported
903 in the future patches.
904 (struct isa_spec_t, isa_specs): List for all supported ISA spec
905 classes and the corresponding strings.
906 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
907 spec class by giving a ISA spec string.
908 * riscv-opc.c (struct priv_spec_t): New structure.
909 (struct priv_spec_t priv_specs): List for all supported privilege spec
910 classes and the corresponding strings.
911 (riscv_get_priv_spec_class): New function. Get the corresponding
912 privilege spec class by giving a spec string.
913 (riscv_get_priv_spec_name): New function. Get the corresponding
914 privilege spec string by giving a CSR version class.
915 * riscv-dis.c: Updated since DECLARE_CSR is changed.
916 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
917 according to the chosen version. Build a hash table riscv_csr_hash to
918 store the valid CSR for the chosen pirv verison. Dump the direct
919 CSR address rather than it's name if it is invalid.
920 (parse_riscv_dis_option_without_args): New function. Parse the options
921 without arguments.
922 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
923 parse the options without arguments first, and then handle the options
924 with arguments. Add the new option -Mpriv-spec, which has argument.
925 * riscv-dis.c (print_riscv_disassembler_options): Add description
926 about the new OBJDUMP option.
927
3d205eb4
PB		 9282020-05-19 Peter Bergner <bergner@linux.ibm.com>
929
930 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
931 WC values on POWER10 sync, dcbf and wait instructions.
932 (insert_pl, extract_pl): New functions.
933 (L2OPT, LS, WC): Use insert_ls and extract_ls.
934 (LS3): New , 3-bit L for sync.
935 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
936 (SC2, PL): New, 2-bit SC and PL for sync and wait.
937 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
938 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
939 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
940 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
941 <wait>: Enable PL operand on POWER10.
942 <dcbf>: Enable L3OPT operand on POWER10.
943 <sync>: Enable SC2 operand on POWER10.
944
a501eb44
SH		 9452020-05-19 Stafford Horne <shorne@gmail.com>
946
947 PR 25184
948 * or1k-asm.c: Regenerate.
949 * or1k-desc.c: Regenerate.
950 * or1k-desc.h: Regenerate.
951 * or1k-dis.c: Regenerate.
952 * or1k-ibld.c: Regenerate.
953 * or1k-opc.c: Regenerate.
954 * or1k-opc.h: Regenerate.
955 * or1k-opinst.c: Regenerate.
956
3b646889
AM		 9572020-05-11 Alan Modra <amodra@gmail.com>
958
959 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
960 xsmaxcqp, xsmincqp.
961
9cc4ce88
AM		 9622020-05-11 Alan Modra <amodra@gmail.com>
963
964 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
965 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
966
5d57bc3f
AM		 9672020-05-11 Alan Modra <amodra@gmail.com>
968
969 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
970
66ef5847
AM		 9712020-05-11 Alan Modra <amodra@gmail.com>
972
973 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
974 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
975
4f3e9537
PB		 9762020-05-11 Peter Bergner <bergner@linux.ibm.com>
977
978 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
979 mnemonics.
980
ec40e91c
AM		 9812020-05-11 Alan Modra <amodra@gmail.com>
982
983 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
984 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
985 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
986 (prefix_opcodes): Add xxeval.
987
d7e97a76
AM		 9882020-05-11 Alan Modra <amodra@gmail.com>
989
990 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
991 xxgenpcvwm, xxgenpcvdm.
992
fdefed7c
AM		 9932020-05-11 Alan Modra <amodra@gmail.com>
994
995 * ppc-opc.c (MP, VXVAM_MASK): Define.
996 (VXVAPS_MASK): Use VXVA_MASK.
997 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
998 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
999 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1000 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1001
aa3c112f
AM		 10022020-05-11 Alan Modra <amodra@gmail.com>
1003 Peter Bergner <bergner@linux.ibm.com>
1004
1005 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1006 New functions.
1007 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1008 YMSK2, XA6a, XA6ap, XB6a entries.
1009 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1010 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1011 (PPCVSX4): Define.
1012 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1013 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1014 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1015 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1016 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1017 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1018 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1019 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1020 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1021 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1022 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1023 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1024 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1025 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1026
6edbfd3b
AM		 10272020-05-11 Alan Modra <amodra@gmail.com>
1028
1029 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1030 (insert_xts, extract_xts): New functions.
1031 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1032 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1033 (VXRC_MASK, VXSH_MASK): Define.
1034 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1035 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1036 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1037 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1038 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1039 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1040 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1041
c7d7aea2
AM		 10422020-05-11 Alan Modra <amodra@gmail.com>
1043
1044 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1045 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1046 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1047 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1048 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1049
94ba9882
AM		 10502020-05-11 Alan Modra <amodra@gmail.com>
1051
1052 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1053 (XTP, DQXP, DQXP_MASK): Define.
1054 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1055 (prefix_opcodes): Add plxvp and pstxvp.
1056
f4791f1a
AM		 10572020-05-11 Alan Modra <amodra@gmail.com>
1058
1059 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1060 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1061 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1062
3ff0a5ba
PB		 10632020-05-11 Peter Bergner <bergner@linux.ibm.com>
1064
1065 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1066
afef4fe9
PB		 10672020-05-11 Peter Bergner <bergner@linux.ibm.com>
1068
1069 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1070 (L1OPT): Define.
1071 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1072
1224c05d
PB		 10732020-05-11 Peter Bergner <bergner@linux.ibm.com>
1074
1075 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1076
6bbb0c05
AM		 10772020-05-11 Alan Modra <amodra@gmail.com>
1078
1079 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1080
7c1f4227
AM		 10812020-05-11 Alan Modra <amodra@gmail.com>
1082
1083 * ppc-dis.c (ppc_opts): Add "power10" entry.
1084 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1085 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1086
73199c2b
NC		 10872020-05-11 Nick Clifton <nickc@redhat.com>
1088
1089 * po/fr.po: Updated French translation.
1090
09c1e68a
AC		 10912020-04-30 Alex Coplan <alex.coplan@arm.com>
1092
1093 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1094 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1095 (operand_general_constraint_met_p): validate
1096 AARCH64_OPND_UNDEFINED.
1097 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1098 for FLD_imm16_2.
1099 * aarch64-asm-2.c: Regenerated.
1100 * aarch64-dis-2.c: Regenerated.
1101 * aarch64-opc-2.c: Regenerated.
1102
9654d51a
NC		 11032020-04-29 Nick Clifton <nickc@redhat.com>
1104
1105 PR 22699
1106 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1107 and SETRC insns.
1108
c2e71e57
NC		 11092020-04-29 Nick Clifton <nickc@redhat.com>
1110
1111 * po/sv.po: Updated Swedish translation.
1112
5c936ef5
NC		 11132020-04-29 Nick Clifton <nickc@redhat.com>
1114
1115 PR 22699
1116 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1117 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1118 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1119 IMM0_8U case.
1120
bb2a1453
AS		 11212020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1122
1123 PR 25848
1124 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1125 cmpi only on m68020up and cpu32.
1126
c2e5c986
SD		 11272020-04-20 Sudakshina Das <sudi.das@arm.com>
1128
1129 * aarch64-asm.c (aarch64_ins_none): New.
1130 * aarch64-asm.h (ins_none): New declaration.
1131 * aarch64-dis.c (aarch64_ext_none): New.
1132 * aarch64-dis.h (ext_none): New declaration.
1133 * aarch64-opc.c (aarch64_print_operand): Update case for
1134 AARCH64_OPND_BARRIER_PSB.
1135 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1136 (AARCH64_OPERANDS): Update inserter/extracter for
1137 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1138 * aarch64-asm-2.c: Regenerated.
1139 * aarch64-dis-2.c: Regenerated.
1140 * aarch64-opc-2.c: Regenerated.
1141
8a6e1d1d
SD		 11422020-04-20 Sudakshina Das <sudi.das@arm.com>
1143
1144 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1145 (aarch64_feature_ras, RAS): Likewise.
1146 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1147 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1148 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1149 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1150 * aarch64-asm-2.c: Regenerated.
1151 * aarch64-dis-2.c: Regenerated.
1152 * aarch64-opc-2.c: Regenerated.
1153
e409955d
FS		 11542020-04-17 Fredrik Strupe <fredrik@strupe.net>
1155
1156 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1157 (print_insn_neon): Support disassembly of conditional
1158 instructions.
1159
c54a9b56
DF		 11602020-02-16 David Faust <david.faust@oracle.com>
1161
1162 * bpf-desc.c: Regenerate.
1163 * bpf-desc.h: Likewise.
1164 * bpf-opc.c: Regenerate.
1165 * bpf-opc.h: Likewise.
1166
bb651e8b
CL		 11672020-04-07 Lili Cui <lili.cui@intel.com>
1168
1169 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1170 (prefix_table): New instructions (see prefixes above).
1171 (rm_table): Likewise
1172 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1173 CPU_ANY_TSXLDTRK_FLAGS.
1174 (cpu_flags): Add CpuTSXLDTRK.
1175 * i386-opc.h (enum): Add CpuTSXLDTRK.
1176 (i386_cpu_flags): Add cputsxldtrk.
1177 * i386-opc.tbl: Add XSUSPLDTRK insns.
1178 * i386-init.h: Regenerate.
1179 * i386-tbl.h: Likewise.
1180
4b27d27c
L		 11812020-04-02 Lili Cui <lili.cui@intel.com>
1182
1183 * i386-dis.c (prefix_table): New instructions serialize.
1184 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1185 CPU_ANY_SERIALIZE_FLAGS.
1186 (cpu_flags): Add CpuSERIALIZE.
1187 * i386-opc.h (enum): Add CpuSERIALIZE.
1188 (i386_cpu_flags): Add cpuserialize.
1189 * i386-opc.tbl: Add SERIALIZE insns.
1190 * i386-init.h: Regenerate.
1191 * i386-tbl.h: Likewise.
1192
832a5807
AM		 11932020-03-26 Alan Modra <amodra@gmail.com>
1194
1195 * disassemble.h (opcodes_assert): Declare.
1196 (OPCODES_ASSERT): Define.
1197 * disassemble.c: Don't include assert.h. Include opintl.h.
1198 (opcodes_assert): New function.
1199 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1200 (bfd_h8_disassemble): Reduce size of data array. Correctly
1201 calculate maxlen. Omit insn decoding when insn length exceeds
1202 maxlen. Exit from nibble loop when looking for E, before
1203 accessing next data byte. Move processing of E outside loop.
1204 Replace tests of maxlen in loop with assertions.
1205
4c4addbe
AM		 12062020-03-26 Alan Modra <amodra@gmail.com>
1207
1208 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1209
a18cd0ca
AM		 12102020-03-25 Alan Modra <amodra@gmail.com>
1211
1212 * z80-dis.c (suffix): Init mybuf.
1213
57cb32b3
AM		 12142020-03-22 Alan Modra <amodra@gmail.com>
1215
1216 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1217 successflly read from section.
1218
beea5cc1
AM		 12192020-03-22 Alan Modra <amodra@gmail.com>
1220
1221 * arc-dis.c (find_format): Use ISO C string concatenation rather
1222 than line continuation within a string. Don't access needs_limm
1223 before testing opcode != NULL.
1224
03704c77
AM		 12252020-03-22 Alan Modra <amodra@gmail.com>
1226
1227 * ns32k-dis.c (print_insn_arg): Update comment.
1228 (print_insn_ns32k): Reduce size of index_offset array, and
1229 initialize, passing -1 to print_insn_arg for args that are not
1230 an index. Don't exit arg loop early. Abort on bad arg number.
1231
d1023b5d
AM		 12322020-03-22 Alan Modra <amodra@gmail.com>
1233
1234 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1235 * s12z-opc.c: Formatting.
1236 (operands_f): Return an int.
1237 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1238 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1239 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1240 (exg_sex_discrim): Likewise.
1241 (create_immediate_operand, create_bitfield_operand),
1242 (create_register_operand_with_size, create_register_all_operand),
1243 (create_register_all16_operand, create_simple_memory_operand),
1244 (create_memory_operand, create_memory_auto_operand): Don't
1245 segfault on malloc failure.
1246 (z_ext24_decode): Return an int status, negative on fail, zero
1247 on success.
1248 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1249 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1250 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1251 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1252 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1253 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1254 (loop_primitive_decode, shift_decode, psh_pul_decode),
1255 (bit_field_decode): Similarly.
1256 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1257 to return value, update callers.
1258 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1259 Don't segfault on NULL operand.
1260 (decode_operation): Return OP_INVALID on first fail.
1261 (decode_s12z): Check all reads, returning -1 on fail.
1262
340f3ac8
AM		 12632020-03-20 Alan Modra <amodra@gmail.com>
1264
1265 * metag-dis.c (print_insn_metag): Don't ignore status from
1266 read_memory_func.
1267
fe90ae8a
AM		 12682020-03-20 Alan Modra <amodra@gmail.com>
1269
1270 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1271 Initialize parts of buffer not written when handling a possible
1272 2-byte insn at end of section. Don't attempt decoding of such
1273 an insn by the 4-byte machinery.
1274
833d919c
AM		 12752020-03-20 Alan Modra <amodra@gmail.com>
1276
1277 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1278 partially filled buffer. Prevent lookup of 4-byte insns when
1279 only VLE 2-byte insns are possible due to section size. Print
1280 ".word" rather than ".long" for 2-byte leftovers.
1281
327ef784
NC		 12822020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1283
1284 PR 25641
1285 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1286
1673df32
JB		 12872020-03-13 Jan Beulich <jbeulich@suse.com>
1288
1289 * i386-dis.c (X86_64_0D): Rename to ...
1290 (X86_64_0E): ... this.
1291
384f3689
L		 12922020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1293
1294 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1295 * Makefile.in: Regenerated.
1296
865e2027
JB		 12972020-03-09 Jan Beulich <jbeulich@suse.com>
1298
1299 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1300 3-operand pseudos.
1301 * i386-tbl.h: Re-generate.
1302
2f13234b
JB		 13032020-03-09 Jan Beulich <jbeulich@suse.com>
1304
1305 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1306 vprot*, vpsha*, and vpshl*.
1307 * i386-tbl.h: Re-generate.
1308
3fabc179
JB		 13092020-03-09 Jan Beulich <jbeulich@suse.com>
1310
1311 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1312 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1313 * i386-tbl.h: Re-generate.
1314
3677e4c1
JB		 13152020-03-09 Jan Beulich <jbeulich@suse.com>
1316
1317 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1318 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1319 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1320 * i386-tbl.h: Re-generate.
1321
4c4898e8
JB		 13222020-03-09 Jan Beulich <jbeulich@suse.com>
1323
1324 * i386-gen.c (struct template_arg, struct template_instance,
1325 struct template_param, struct template, templates,
1326 parse_template, expand_templates): New.
1327 (process_i386_opcodes): Various local variables moved to
1328 expand_templates. Call parse_template and expand_templates.
1329 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1330 * i386-tbl.h: Re-generate.
1331
bc49bfd8
JB		 13322020-03-06 Jan Beulich <jbeulich@suse.com>
1333
1334 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1335 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1336 register and memory source templates. Replace VexW= by VexW*
1337 where applicable.
1338 * i386-tbl.h: Re-generate.
1339
4873e243
JB		 13402020-03-06 Jan Beulich <jbeulich@suse.com>
1341
1342 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1343 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1344 * i386-tbl.h: Re-generate.
1345
672a349b
JB		 13462020-03-06 Jan Beulich <jbeulich@suse.com>
1347
1348 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1349 * i386-tbl.h: Re-generate.
1350
4ed21b58
JB		 13512020-03-06 Jan Beulich <jbeulich@suse.com>
1352
1353 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1354 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1355 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1356 VexW0 on SSE2AVX variants.
1357 (vmovq): Drop NoRex64 from XMM/XMM variants.
1358 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1359 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1360 applicable use VexW0.
1361 * i386-tbl.h: Re-generate.
1362
643bb870
JB		 13632020-03-06 Jan Beulich <jbeulich@suse.com>
1364
1365 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1366 * i386-opc.h (Rex64): Delete.
1367 (struct i386_opcode_modifier): Remove rex64 field.
1368 * i386-opc.tbl (crc32): Drop Rex64.
1369 Replace Rex64 with Size64 everywhere else.
1370 * i386-tbl.h: Re-generate.
1371
a23b33b3
JB		 13722020-03-06 Jan Beulich <jbeulich@suse.com>
1373
1374 * i386-dis.c (OP_E_memory): Exclude recording of used address
1375 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1376 addressed memory operands for MPX insns.
1377
a0497384
JB		 13782020-03-06 Jan Beulich <jbeulich@suse.com>
1379
1380 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1381 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1382 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1383 (ptwrite): Split into non-64-bit and 64-bit forms.
1384 * i386-tbl.h: Re-generate.
1385
b630c145
JB		 13862020-03-06 Jan Beulich <jbeulich@suse.com>
1387
1388 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1389 template.
1390 * i386-tbl.h: Re-generate.
1391
a847e322
JB		 13922020-03-04 Jan Beulich <jbeulich@suse.com>
1393
1394 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1395 (prefix_table): Move vmmcall here. Add vmgexit.
1396 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1397 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1398 (cpu_flags): Add CpuSEV_ES entry.
1399 * i386-opc.h (CpuSEV_ES): New.
1400 (union i386_cpu_flags): Add cpusev_es field.
1401 * i386-opc.tbl (vmgexit): New.
1402 * i386-init.h, i386-tbl.h: Re-generate.
1403
3cd7f3e3
L		 14042020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1405
1406 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1407 with MnemonicSize.
1408 * i386-opc.h (IGNORESIZE): New.
1409 (DEFAULTSIZE): Likewise.
1410 (IgnoreSize): Removed.
1411 (DefaultSize): Likewise.
1412 (MnemonicSize): New.
1413 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1414 mnemonicsize.
1415 * i386-opc.tbl (IgnoreSize): New.
1416 (DefaultSize): Likewise.
1417 * i386-tbl.h: Regenerated.
1418
b8ba1385
SB		 14192020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1420
1421 PR 25627
1422 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1423 instructions.
1424
10d97a0f
L		 14252020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1426
1427 PR gas/25622
1428 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1429 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1430 * i386-tbl.h: Regenerated.
1431
dc1e8a47
AM		 14322020-02-26 Alan Modra <amodra@gmail.com>
1433
1434 * aarch64-asm.c: Indent labels correctly.
1435 * aarch64-dis.c: Likewise.
1436 * aarch64-gen.c: Likewise.
1437 * aarch64-opc.c: Likewise.
1438 * alpha-dis.c: Likewise.
1439 * i386-dis.c: Likewise.
1440 * nds32-asm.c: Likewise.
1441 * nfp-dis.c: Likewise.
1442 * visium-dis.c: Likewise.
1443
265b4673
CZ		 14442020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1445
1446 * arc-regs.h (int_vector_base): Make it available for all ARC
1447 CPUs.
1448
bd0cf5a6
NC		 14492020-02-20 Nelson Chu <nelson.chu@sifive.com>
1450
1451 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1452 changed.
1453
fa164239
JW		 14542020-02-19 Nelson Chu <nelson.chu@sifive.com>
1455
1456 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1457 c.mv/c.li if rs1 is zero.
1458
272a84b1
L		 14592020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1460
1461 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1462 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1463 CPU_POPCNT_FLAGS.
1464 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1465 * i386-opc.h (CpuABM): Removed.
1466 (CpuPOPCNT): New.
1467 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1468 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1469 popcnt. Remove CpuABM from lzcnt.
1470 * i386-init.h: Regenerated.
1471 * i386-tbl.h: Likewise.
1472
1f730c46
JB		 14732020-02-17 Jan Beulich <jbeulich@suse.com>
1474
1475 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1476 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1477 VexW1 instead of open-coding them.
1478 * i386-tbl.h: Re-generate.
1479
c8f8eebc
JB		 14802020-02-17 Jan Beulich <jbeulich@suse.com>
1481
1482 * i386-opc.tbl (AddrPrefixOpReg): Define.
1483 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1484 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1485 templates. Drop NoRex64.
1486 * i386-tbl.h: Re-generate.
1487
b9915cbc
JB		 14882020-02-17 Jan Beulich <jbeulich@suse.com>
1489
1490 PR gas/6518
1491 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1492 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1493 into Intel syntax instance (with Unpsecified) and AT&T one
1494 (without).
1495 (vcvtneps2bf16): Likewise, along with folding the two so far
1496 separate ones.
1497 * i386-tbl.h: Re-generate.
1498
ce504911
L		 14992020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1500
1501 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1502 CPU_ANY_SSE4A_FLAGS.
1503
dabec65d
AM		 15042020-02-17 Alan Modra <amodra@gmail.com>
1505
1506 * i386-gen.c (cpu_flag_init): Correct last change.
1507
af5c13b0
L		 15082020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1509
1510 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1511 CPU_ANY_SSE4_FLAGS.
1512
6867aac0
L		 15132020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1514
1515 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1516 (movzx): Likewise.
1517
65fca059
JB		 15182020-02-14 Jan Beulich <jbeulich@suse.com>
1519
1520 PR gas/25438
1521 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1522 destination for Cpu64-only variant.
1523 (movzx): Fold patterns.
1524 * i386-tbl.h: Re-generate.
1525
7deea9aa
JB		 15262020-02-13 Jan Beulich <jbeulich@suse.com>
1527
1528 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1529 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1530 CPU_ANY_SSE4_FLAGS entry.
1531 * i386-init.h: Re-generate.
1532
6c0946d0
JB		 15332020-02-12 Jan Beulich <jbeulich@suse.com>
1534
1535 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1536 with Unspecified, making the present one AT&T syntax only.
1537 * i386-tbl.h: Re-generate.
1538
ddb56fe6
JB		 15392020-02-12 Jan Beulich <jbeulich@suse.com>
1540
1541 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1542 * i386-tbl.h: Re-generate.
1543
5990e377
JB		 15442020-02-12 Jan Beulich <jbeulich@suse.com>
1545
1546 PR gas/24546
1547 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1548 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1549 Amd64 and Intel64 templates.
1550 (call, jmp): Likewise for far indirect variants. Dro
1551 Unspecified.
1552 * i386-tbl.h: Re-generate.
1553
50128d0c
JB		 15542020-02-11 Jan Beulich <jbeulich@suse.com>
1555
1556 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1557 * i386-opc.h (ShortForm): Delete.
1558 (struct i386_opcode_modifier): Remove shortform field.
1559 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1560 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1561 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1562 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1563 Drop ShortForm.
1564 * i386-tbl.h: Re-generate.
1565
1e05b5c4
JB		 15662020-02-11 Jan Beulich <jbeulich@suse.com>
1567
1568 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1569 fucompi): Drop ShortForm from operand-less templates.
1570 * i386-tbl.h: Re-generate.
1571
2f5dd314
AM		 15722020-02-11 Alan Modra <amodra@gmail.com>
1573
1574 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1575 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1576 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1577 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1578 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1579
5aae9ae9
MM		 15802020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1581
1582 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1583 (cde_opcodes): Add VCX* instructions.
1584
4934a27c
MM		 15852020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1586 Matthew Malcomson <matthew.malcomson@arm.com>
1587
1588 * arm-dis.c (struct cdeopcode32): New.
1589 (CDE_OPCODE): New macro.
1590 (cde_opcodes): New disassembly table.
1591 (regnames): New option to table.
1592 (cde_coprocs): New global variable.
1593 (print_insn_cde): New
1594 (print_insn_thumb32): Use print_insn_cde.
1595 (parse_arm_disassembler_options): Parse coprocN args.
1596
4b5aaf5f
L		 15972020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1598
1599 PR gas/25516
1600 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1601 with ISA64.
1602 * i386-opc.h (AMD64): Removed.
1603 (Intel64): Likewose.
1604 (AMD64): New.
1605 (INTEL64): Likewise.
1606 (INTEL64ONLY): Likewise.
1607 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1608 * i386-opc.tbl (Amd64): New.
1609 (Intel64): Likewise.
1610 (Intel64Only): Likewise.
1611 Replace AMD64 with Amd64. Update sysenter/sysenter with
1612 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1613 * i386-tbl.h: Regenerated.
1614
9fc0b501
SB		 16152020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1616
1617 PR 25469
1618 * z80-dis.c: Add support for GBZ80 opcodes.
1619
c5d7be0c
AM		 16202020-02-04 Alan Modra <amodra@gmail.com>
1621
1622 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1623
44e4546f
AM		 16242020-02-03 Alan Modra <amodra@gmail.com>
1625
1626 * m32c-ibld.c: Regenerate.
1627
b2b1453a
AM		 16282020-02-01 Alan Modra <amodra@gmail.com>
1629
1630 * frv-ibld.c: Regenerate.
1631
4102be5c
JB		 16322020-01-31 Jan Beulich <jbeulich@suse.com>
1633
1634 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1635 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1636 (OP_E_memory): Replace xmm_mdq_mode case label by
1637 vex_scalar_w_dq_mode one.
1638 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1639
825bd36c
JB		 16402020-01-31 Jan Beulich <jbeulich@suse.com>
1641
1642 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1643 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1644 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1645 (intel_operand_size): Drop vex_w_dq_mode case label.
1646
c3036ed0
RS		 16472020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1648
1649 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1650 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1651
0c115f84
AM		 16522020-01-30 Alan Modra <amodra@gmail.com>
1653
1654 * m32c-ibld.c: Regenerate.
1655
bd434cc4
JM		 16562020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1657
1658 * bpf-opc.c: Regenerate.
1659
aeab2b26
JB		 16602020-01-30 Jan Beulich <jbeulich@suse.com>
1661
1662 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1663 (dis386): Use them to replace C2/C3 table entries.
1664 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1665 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1666 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1667 * i386-tbl.h: Re-generate.
1668
62b3f548
JB		 16692020-01-30 Jan Beulich <jbeulich@suse.com>
1670
1671 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1672 forms.
1673 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1674 DefaultSize.
1675 * i386-tbl.h: Re-generate.
1676
1bd8ae10
AM		 16772020-01-30 Alan Modra <amodra@gmail.com>
1678
1679 * tic4x-dis.c (tic4x_dp): Make unsigned.
1680
bc31405e
L		 16812020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1682 Jan Beulich <jbeulich@suse.com>
1683
1684 PR binutils/25445
1685 * i386-dis.c (MOVSXD_Fixup): New function.
1686 (movsxd_mode): New enum.
1687 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1688 (intel_operand_size): Handle movsxd_mode.
1689 (OP_E_register): Likewise.
1690 (OP_G): Likewise.
1691 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1692 register on movsxd. Add movsxd with 16-bit destination register
1693 for AMD64 and Intel64 ISAs.
1694 * i386-tbl.h: Regenerated.
1695
7568c93b
TC		 16962020-01-27 Tamar Christina <tamar.christina@arm.com>
1697
1698 PR 25403
1699 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1700 * aarch64-asm-2.c: Regenerate
1701 * aarch64-dis-2.c: Likewise.
1702 * aarch64-opc-2.c: Likewise.
1703
c006a730
JB		 17042020-01-21 Jan Beulich <jbeulich@suse.com>
1705
1706 * i386-opc.tbl (sysret): Drop DefaultSize.
1707 * i386-tbl.h: Re-generate.
1708
c906a69a
JB		 17092020-01-21 Jan Beulich <jbeulich@suse.com>
1710
1711 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1712 Dword.
1713 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1714 * i386-tbl.h: Re-generate.
1715
26916852
NC		 17162020-01-20 Nick Clifton <nickc@redhat.com>
1717
1718 * po/de.po: Updated German translation.
1719 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1720 * po/uk.po: Updated Ukranian translation.
1721
4d6cbb64
AM		 17222020-01-20 Alan Modra <amodra@gmail.com>
1723
1724 * hppa-dis.c (fput_const): Remove useless cast.
1725
2bddb71a
AM		 17262020-01-20 Alan Modra <amodra@gmail.com>
1727
1728 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1729
1b1bb2c6
NC		 17302020-01-18 Nick Clifton <nickc@redhat.com>
1731
1732 * configure: Regenerate.
1733 * po/opcodes.pot: Regenerate.
1734
ae774686
NC		 17352020-01-18 Nick Clifton <nickc@redhat.com>
1736
1737 Binutils 2.34 branch created.
1738
07f1f3aa
CB		 17392020-01-17 Christian Biesinger <cbiesinger@google.com>
1740
1741 * opintl.h: Fix spelling error (seperate).
1742
42e04b36
L		 17432020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1744
1745 * i386-opc.tbl: Add {vex} pseudo prefix.
1746 * i386-tbl.h: Regenerated.
1747
2da2eaf4
AV		 17482020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1749
1750 PR 25376
1751 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1752 (neon_opcodes): Likewise.
1753 (select_arm_features): Make sure we enable MVE bits when selecting
1754 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1755 any architecture.
1756
d0849eed
JB		 17572020-01-16 Jan Beulich <jbeulich@suse.com>
1758
1759 * i386-opc.tbl: Drop stale comment from XOP section.
1760
9cf70a44
JB		 17612020-01-16 Jan Beulich <jbeulich@suse.com>
1762
1763 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1764 (extractps): Add VexWIG to SSE2AVX forms.
1765 * i386-tbl.h: Re-generate.
1766
4814632e
JB		 17672020-01-16 Jan Beulich <jbeulich@suse.com>
1768
1769 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1770 Size64 from and use VexW1 on SSE2AVX forms.
1771 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1772 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1773 * i386-tbl.h: Re-generate.
1774
aad09917
AM		 17752020-01-15 Alan Modra <amodra@gmail.com>
1776
1777 * tic4x-dis.c (tic4x_version): Make unsigned long.
1778 (optab, optab_special, registernames): New file scope vars.
1779 (tic4x_print_register): Set up registernames rather than
1780 malloc'd registertable.
1781 (tic4x_disassemble): Delete optable and optable_special. Use
1782 optab and optab_special instead. Throw away old optab,
1783 optab_special and registernames when info->mach changes.
1784
7a6bf3be
SB		 17852020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1786
1787 PR 25377
1788 * z80-dis.c (suffix): Use .db instruction to generate double
1789 prefix.
1790
ca1eaac0
AM		 17912020-01-14 Alan Modra <amodra@gmail.com>
1792
1793 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1794 values to unsigned before shifting.
1795
1d67fe3b
TT		 17962020-01-13 Thomas Troeger <tstroege@gmx.de>
1797
1798 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1799 flow instructions.
1800 (print_insn_thumb16, print_insn_thumb32): Likewise.
1801 (print_insn): Initialize the insn info.
1802 * i386-dis.c (print_insn): Initialize the insn info fields, and
1803 detect jumps.
1804
5e4f7e05
CZ		 18052012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1806
1807 * arc-opc.c (C_NE): Make it required.
1808
b9fe6b8a
CZ		 18092012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1810
1811 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1812 reserved register name.
1813
90dee485
AM		 18142020-01-13 Alan Modra <amodra@gmail.com>
1815
1816 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1817 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1818
febda64f
AM		 18192020-01-13 Alan Modra <amodra@gmail.com>
1820
1821 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1822 result of wasm_read_leb128 in a uint64_t and check that bits
1823 are not lost when copying to other locals. Use uint32_t for
1824 most locals. Use PRId64 when printing int64_t.
1825
df08b588
AM		 18262020-01-13 Alan Modra <amodra@gmail.com>
1827
1828 * score-dis.c: Formatting.
1829 * score7-dis.c: Formatting.
1830
b2c759ce
AM		 18312020-01-13 Alan Modra <amodra@gmail.com>
1832
1833 * score-dis.c (print_insn_score48): Use unsigned variables for
1834 unsigned values. Don't left shift negative values.
1835 (print_insn_score32): Likewise.
1836 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1837
5496abe1
AM		 18382020-01-13 Alan Modra <amodra@gmail.com>
1839
1840 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1841
202e762b
AM		 18422020-01-13 Alan Modra <amodra@gmail.com>
1843
1844 * fr30-ibld.c: Regenerate.
1845
7ef412cf
AM		 18462020-01-13 Alan Modra <amodra@gmail.com>
1847
1848 * xgate-dis.c (print_insn): Don't left shift signed value.
1849 (ripBits): Formatting, use 1u.
1850
7f578b95
AM		 18512020-01-10 Alan Modra <amodra@gmail.com>
1852
1853 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1854 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1855
441af85b
AM		 18562020-01-10 Alan Modra <amodra@gmail.com>
1857
1858 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1859 and XRREG value earlier to avoid a shift with negative exponent.
1860 * m10200-dis.c (disassemble): Similarly.
1861
bce58db4
NC		 18622020-01-09 Nick Clifton <nickc@redhat.com>
1863
1864 PR 25224
1865 * z80-dis.c (ld_ii_ii): Use correct cast.
1866
40c75bc8
SB		 18672020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1868
1869 PR 25224
1870 * z80-dis.c (ld_ii_ii): Use character constant when checking
1871 opcode byte value.
1872
d835a58b
JB		 18732020-01-09 Jan Beulich <jbeulich@suse.com>
1874
1875 * i386-dis.c (SEP_Fixup): New.
1876 (SEP): Define.
1877 (dis386_twobyte): Use it for sysenter/sysexit.
1878 (enum x86_64_isa): Change amd64 enumerator to value 1.
1879 (OP_J): Compare isa64 against intel64 instead of amd64.
1880 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1881 forms.
1882 * i386-tbl.h: Re-generate.
1883
030a2e78
AM		 18842020-01-08 Alan Modra <amodra@gmail.com>
1885
1886 * z8k-dis.c: Include libiberty.h
1887 (instr_data_s): Make max_fetched unsigned.
1888 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1889 Don't exceed byte_info bounds.
1890 (output_instr): Make num_bytes unsigned.
1891 (unpack_instr): Likewise for nibl_count and loop.
1892 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1893 idx unsigned.
1894 * z8k-opc.h: Regenerate.
1895
bb82aefe
SV		 18962020-01-07 Shahab Vahedi <shahab@synopsys.com>
1897
1898 * arc-tbl.h (llock): Use 'LLOCK' as class.
1899 (llockd): Likewise.
1900 (scond): Use 'SCOND' as class.
1901 (scondd): Likewise.
1902 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1903 (scondd): Likewise.
1904
cc6aa1a6
AM		 19052020-01-06 Alan Modra <amodra@gmail.com>
1906
1907 * m32c-ibld.c: Regenerate.
1908
660e62b1
AM		 19092020-01-06 Alan Modra <amodra@gmail.com>
1910
1911 PR 25344
1912 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1913 Peek at next byte to prevent recursion on repeated prefix bytes.
1914 Ensure uninitialised "mybuf" is not accessed.
1915 (print_insn_z80): Don't zero n_fetch and n_used here,..
1916 (print_insn_z80_buf): ..do it here instead.
1917
c9ae58fe
AM		 19182020-01-04 Alan Modra <amodra@gmail.com>
1919
1920 * m32r-ibld.c: Regenerate.
1921
5f57d4ec
AM		 19222020-01-04 Alan Modra <amodra@gmail.com>
1923
1924 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1925
2c5c1196
AM		 19262020-01-04 Alan Modra <amodra@gmail.com>
1927
1928 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1929
2e98c6c5
AM		 19302020-01-04 Alan Modra <amodra@gmail.com>
1931
1932 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1933
567dfba2
JB		 19342020-01-03 Jan Beulich <jbeulich@suse.com>
1935
5437a02a
JB		 1936 * aarch64-tbl.h (aarch64_opcode_table): Use
1937 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1938
19392020-01-03 Jan Beulich <jbeulich@suse.com>
1940
1941 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1942 forms of SUDOT and USDOT.
1943
8c45011a
JB		 19442020-01-03 Jan Beulich <jbeulich@suse.com>
1945
5437a02a 1946 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1947 uzip{1,2}.
1948 * opcodes/aarch64-dis-2.c: Re-generate.
1949
f4950f76
JB		 19502020-01-03 Jan Beulich <jbeulich@suse.com>
1951
5437a02a 1952 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1953 FMMLA encoding.
1954 * opcodes/aarch64-dis-2.c: Re-generate.
1955
6655dba2
SB		 19562020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1957
1958 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1959
b14ce8bf
AM		 19602020-01-01 Alan Modra <amodra@gmail.com>
1961
1962 Update year range in copyright notice of all files.
1963
0b114740 1964For older changes see ChangeLog-2019
3499769a 1965\f
0b114740 1966Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1967
1968Copying and distribution of this file, with or without modification,
1969are permitted in any medium without royalty provided the copyright
1970notice and this notice are preserved.
1971
1972Local Variables:
1973mode: change-log
1974left-margin: 8
1975fill-column: 74
1976version-control: never
1977End:
A mirror of the official binutils-gdb repository