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* config/tc-mips.c: Add define for $zero register.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
577d8c4b
CD		 12002-06-07 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c (convert): Remove unusable debugging code, and move MIPS
4 rounding mode to sim FP rounding mode flag conversion code into...
5 (rounding_mode): New function.
6
196496ed
CD		 72002-06-07 Chris Demetriou <cgd@broadcom.com>
8
9 * cp1.c: Clean up formatting of a few comments.
10 (value_fpr): Reformat switch statement.
11
cfe9ea23
CD		 122002-06-06 Chris Demetriou <cgd@broadcom.com>
13 Ed Satterthwaite <ehs@broadcom.com>
14
15 * cp1.h: New file.
16 * sim-main.h: Include cp1.h.
17 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
18 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
19 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
20 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
21 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
22 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
23 * cp1.c: Don't include sim-fpu.h; already included by
24 sim-main.h. Clean up formatting of some comments.
25 (NaN, Equal, Less): Remove.
26 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
27 (fp_cmp): New functions.
28 * mips.igen (do_c_cond_fmt): Remove.
29 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
30 Compare. Add result tracing.
31 (CxC1): Remove, replace with...
32 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
33 (DMxC1): Remove, replace with...
34 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
35 (MxC1): Remove, replace with...
36 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
37
ee7254b0
CD		 382002-06-04 Chris Demetriou <cgd@broadcom.com>
39
40 * sim-main.h (FGRIDX): Remove, replace all uses with...
41 (FGR_BASE): New macro.
42 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
43 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
44 (NR_FGR, FGR): Likewise.
45 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
46 * mips.igen: Likewise.
47
d3eb724f
CD		 482002-06-04 Chris Demetriou <cgd@broadcom.com>
49
50 * cp1.c: Add an FSF Copyright notice to this file.
51
ba46ddd0
CD		 522002-06-04 Chris Demetriou <cgd@broadcom.com>
53 Ed Satterthwaite <ehs@broadcom.com>
54
55 * cp1.c (Infinity): Remove.
56 * sim-main.h (Infinity): Likewise.
57
58 * cp1.c (fp_unary, fp_binary): New functions.
59 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
60 (fp_sqrt): New functions, implemented in terms of the above.
61 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
62 (Recip, SquareRoot): Remove (replaced by functions above).
63 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
64 (fp_recip, fp_sqrt): New prototypes.
65 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
66 (Recip, SquareRoot): Replace prototypes with #defines which
67 invoke the functions above.
68
18d8a52d
CD		 692002-06-03 Chris Demetriou <cgd@broadcom.com>
70
71 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
72 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
73 file, remove PARAMS from prototypes.
74 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
75 simulator state arguments.
76 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
77 pass simulator state arguments.
78 * cp1.c (SD): Redefine as CPU_STATE(cpu).
79 (store_fpr, convert): Remove 'sd' argument.
80 (value_fpr): Likewise. Convert to use 'SD' instead.
81
0f154cbd
CD		 822002-06-03 Chris Demetriou <cgd@broadcom.com>
83
84 * cp1.c (Min, Max): Remove #if 0'd functions.
85 * sim-main.h (Min, Max): Remove.
86
e80fc152
CD		 872002-06-03 Chris Demetriou <cgd@broadcom.com>
88
89 * cp1.c: fix formatting of switch case and default labels.
90 * interp.c: Likewise.
91 * sim-main.c: Likewise.
92
bad673a9
CD		 932002-06-03 Chris Demetriou <cgd@broadcom.com>
94
95 * cp1.c: Clean up comments which describe FP formats.
96 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
97
7cbea089
CD		 982002-06-03 Chris Demetriou <cgd@broadcom.com>
99 Ed Satterthwaite <ehs@broadcom.com>
100
101 * configure.in (mipsisa64sb1*-*-*): New target for supporting
102 Broadcom SiByte SB-1 processor configurations.
103 * configure: Regenerate.
104 * sb1.igen: New file.
105 * mips.igen: Include sb1.igen.
106 (sb1): New model.
107 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
108 * mdmx.igen: Add "sb1" model to all appropriate functions and
109 instructions.
110 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
111 (ob_func, ob_acc): Reference the above.
112 (qh_acc): Adjust to keep the same size as ob_acc.
113 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
114 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
115
909daa82
CD		 1162002-06-03 Chris Demetriou <cgd@broadcom.com>
117
118 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
119
f4f1b9f1
CD		 1202002-06-02 Chris Demetriou <cgd@broadcom.com>
121 Ed Satterthwaite <ehs@broadcom.com>
122
123 * mips.igen (mdmx): New (pseudo-)model.
124 * mdmx.c, mdmx.igen: New files.
125 * Makefile.in (SIM_OBJS): Add mdmx.o.
126 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
127 New typedefs.
128 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
129 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
130 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
131 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
132 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
133 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
134 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
135 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
136 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
137 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
138 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
139 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
140 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
141 (qh_fmtsel): New macros.
142 (_sim_cpu): New member "acc".
143 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
144 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
145
5accf1ff
CD		 1462002-05-01 Chris Demetriou <cgd@broadcom.com>
147
148 * interp.c: Use 'deprecated' rather than 'depreciated.'
149 * sim-main.h: Likewise.
150
402586aa
CD		 1512002-05-01 Chris Demetriou <cgd@broadcom.com>
152
153 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
154 which wouldn't compile anyway.
155 * sim-main.h (unpredictable_action): New function prototype.
156 (Unpredictable): Define to call igen function unpredictable().
157 (NotWordValue): New macro to call igen function not_word_value().
158 (UndefinedResult): Remove.
159 * interp.c (undefined_result): Remove.
160 (unpredictable_action): New function.
161 * mips.igen (not_word_value, unpredictable): New functions.
162 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
163 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
164 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
165 NotWordValue() to check for unpredictable inputs, then
166 Unpredictable() to handle them.
167
c9b9995a
CD		 1682002-02-24 Chris Demetriou <cgd@broadcom.com>
169
170 * mips.igen: Fix formatting of calls to Unpredictable().
171
e1015982
AC		 1722002-04-20 Andrew Cagney <ac131313@redhat.com>
173
174 * interp.c (sim_open): Revert previous change.
175
b882a66b
AO		 1762002-04-18 Alexandre Oliva <aoliva@redhat.com>
177
178 * interp.c (sim_open): Disable chunk of code that wrote code in
179 vector table entries.
180
c429b7dd
CD		 1812002-03-19 Chris Demetriou <cgd@broadcom.com>
182
183 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
184 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
185 unused definitions.
186
37d146fa
CD		 1872002-03-19 Chris Demetriou <cgd@broadcom.com>
188
189 * cp1.c: Fix many formatting issues.
190
07892c0b
CD		 1912002-03-19 Chris G. Demetriou <cgd@broadcom.com>
192
193 * cp1.c (fpu_format_name): New function to replace...
194 (DOFMT): This. Delete, and update all callers.
195 (fpu_rounding_mode_name): New function to replace...
196 (RMMODE): This. Delete, and update all callers.
197
487f79b7
CD		 1982002-03-19 Chris G. Demetriou <cgd@broadcom.com>
199
200 * interp.c: Move FPU support routines from here to...
201 * cp1.c: Here. New file.
202 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
203 (cp1.o): New target.
204
1e799e28
CD		 2052002-03-12 Chris Demetriou <cgd@broadcom.com>
206
207 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
208 * mips.igen (mips32, mips64): New models, add to all instructions
209 and functions as appropriate.
210 (loadstore_ea, check_u64): New variant for model mips64.
211 (check_fmt_p): New variant for models mipsV and mips64, remove
212 mipsV model marking fro other variant.
213 (SLL) Rename to...
214 (SLLa) this.
215 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
216 for mips32 and mips64.
217 (DCLO, DCLZ): New instructions for mips64.
218
82f728db
CD		 2192002-03-07 Chris Demetriou <cgd@broadcom.com>
220
221 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
222 immediate or code as a hex value with the "%#lx" format.
223 (ANDI): Likewise, and fix printed instruction name.
224
b96e7ef1
CD		 2252002-03-05 Chris Demetriou <cgd@broadcom.com>
226
227 * sim-main.h (UndefinedResult, Unpredictable): New macros
228 which currently do nothing.
229
d35d4f70
CD		 2302002-03-05 Chris Demetriou <cgd@broadcom.com>
231
232 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
233 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
234 (status_CU3): New definitions.
235
236 * sim-main.h (ExceptionCause): Add new values for MIPS32
237 and MIPS64: MDMX, MCheck, CacheErr. Update comments
238 for DebugBreakPoint and NMIReset to note their status in
239 MIPS32 and MIPS64.
240 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
241 (SignalExceptionCacheErr): New exception macros.
242
3ad6f714
CD		 2432002-03-05 Chris Demetriou <cgd@broadcom.com>
244
245 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
246 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
247 is always enabled.
248 (SignalExceptionCoProcessorUnusable): Take as argument the
249 unusable coprocessor number.
250
86b77b47
CD		 2512002-03-05 Chris Demetriou <cgd@broadcom.com>
252
253 * mips.igen: Fix formatting of all SignalException calls.
254
97a88e93 2552002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 256
257 * sim-main.h (SIGNEXTEND): Remove.
258
97a88e93 2592002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 260
261 * mips.igen: Remove gencode comment from top of file, fix
262 spelling in another comment.
263
97a88e93 2642002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 265
266 * mips.igen (check_fmt, check_fmt_p): New functions to check
267 whether specific floating point formats are usable.
268 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
269 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
270 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
271 Use the new functions.
272 (do_c_cond_fmt): Remove format checks...
273 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
274
97a88e93 2752002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 276
277 * mips.igen: Fix formatting of check_fpu calls.
278
41774c9d
CD		 2792002-03-03 Chris Demetriou <cgd@broadcom.com>
280
281 * mips.igen (FLOOR.L.fmt): Store correct destination register.
282
4a0bd876
CD		 2832002-03-03 Chris Demetriou <cgd@broadcom.com>
284
285 * mips.igen: Remove whitespace at end of lines.
286
09297648
CD		 2872002-03-02 Chris Demetriou <cgd@broadcom.com>
288
289 * mips.igen (loadstore_ea): New function to do effective
290 address calculations.
291 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
292 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
293 CACHE): Use loadstore_ea to do effective address computations.
294
043b7057
CD		 2952002-03-02 Chris Demetriou <cgd@broadcom.com>
296
297 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
298 * mips.igen (LL, CxC1, MxC1): Likewise.
299
c1e8ada4
CD		 3002002-03-02 Chris Demetriou <cgd@broadcom.com>
301
302 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
303 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
304 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
305 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
306 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
307 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
308 Don't split opcode fields by hand, use the opcode field values
309 provided by igen.
310
3e1dca16
CD		 3112002-03-01 Chris Demetriou <cgd@broadcom.com>
312
313 * mips.igen (do_divu): Fix spacing.
314
315 * mips.igen (do_dsllv): Move to be right before DSLLV,
316 to match the rest of the do_<shift> functions.
317
fff8d27d
CD		 3182002-03-01 Chris Demetriou <cgd@broadcom.com>
319
320 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
321 DSRL32, do_dsrlv): Trace inputs and results.
322
0d3e762b
CD		 3232002-03-01 Chris Demetriou <cgd@broadcom.com>
324
325 * mips.igen (CACHE): Provide instruction-printing string.
326
327 * interp.c (signal_exception): Comment tokens after #endif.
328
eb5fcf93
CD		 3292002-02-28 Chris Demetriou <cgd@broadcom.com>
330
331 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
332 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
333 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
334 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
335 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
336 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
337 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
338 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
339
bb22bd7d
CD		 3402002-02-28 Chris Demetriou <cgd@broadcom.com>
341
342 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
343 instruction-printing string.
344 (LWU): Use '64' as the filter flag.
345
91a177cf
CD		 3462002-02-28 Chris Demetriou <cgd@broadcom.com>
347
348 * mips.igen (SDXC1): Fix instruction-printing string.
349
387f484a
CD		 3502002-02-28 Chris Demetriou <cgd@broadcom.com>
351
352 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
353 filter flags "32,f".
354
3d81f391
CD		 3552002-02-27 Chris Demetriou <cgd@broadcom.com>
356
357 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
358 as the filter flag.
359
af5107af
CD		 3602002-02-27 Chris Demetriou <cgd@broadcom.com>
361
362 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
363 add a comma) so that it more closely match the MIPS ISA
364 documentation opcode partitioning.
365 (PREF): Put useful names on opcode fields, and include
366 instruction-printing string.
367
ca971540
CD		 3682002-02-27 Chris Demetriou <cgd@broadcom.com>
369
370 * mips.igen (check_u64): New function which in the future will
371 check whether 64-bit instructions are usable and signal an
372 exception if not. Currently a no-op.
373 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
374 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
375 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
376 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
377
378 * mips.igen (check_fpu): New function which in the future will
379 check whether FPU instructions are usable and signal an exception
380 if not. Currently a no-op.
381 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
382 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
383 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
384 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
385 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
386 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
387 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
388 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
389
1c47a468
CD		 3902002-02-27 Chris Demetriou <cgd@broadcom.com>
391
392 * mips.igen (do_load_left, do_load_right): Move to be immediately
393 following do_load.
394 (do_store_left, do_store_right): Move to be immediately following
395 do_store.
396
603a98e7
CD		 3972002-02-27 Chris Demetriou <cgd@broadcom.com>
398
399 * mips.igen (mipsV): New model name. Also, add it to
400 all instructions and functions where it is appropriate.
401
c5d00cc7
CD		 4022002-02-18 Chris Demetriou <cgd@broadcom.com>
403
404 * mips.igen: For all functions and instructions, list model
405 names that support that instruction one per line.
406
074e9cb8
CD		 4072002-02-11 Chris Demetriou <cgd@broadcom.com>
408
409 * mips.igen: Add some additional comments about supported
410 models, and about which instructions go where.
411 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
412 order as is used in the rest of the file.
413
9805e229
CD		 4142002-02-11 Chris Demetriou <cgd@broadcom.com>
415
416 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
417 indicating that ALU32_END or ALU64_END are there to check
418 for overflow.
419 (DADD): Likewise, but also remove previous comment about
420 overflow checking.
421
f701dad2
CD		 4222002-02-10 Chris Demetriou <cgd@broadcom.com>
423
424 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
425 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
426 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
427 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
428 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
429 fields (i.e., add and move commas) so that they more closely
430 match the MIPS ISA documentation opcode partitioning.
431
4322002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 433
434 * mips.igen (ADDI): Print immediate value.
435 (BREAK): Print code.
436 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
437 (SLL): Print "nop" specially, and don't run the code
438 that does the shift for the "nop" case.
439
9e52972e
FF		 4402001-11-17 Fred Fish <fnf@redhat.com>
441
442 * sim-main.h (float_operation): Move enum declaration outside
443 of _sim_cpu struct declaration.
444
c0efbca4
JB		 4452001-04-12 Jim Blandy <jimb@redhat.com>
446
447 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
448 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
449 set of the FCSR.
450 * sim-main.h (COCIDX): Remove definition; this isn't supported by
451 PENDING_FILL, and you can get the intended effect gracefully by
452 calling PENDING_SCHED directly.
453
fb891446
BE		 4542001-02-23 Ben Elliston <bje@redhat.com>
455
456 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
457 already defined elsewhere.
458
8030f857
BE		 4592001-02-19 Ben Elliston <bje@redhat.com>
460
461 * sim-main.h (sim_monitor): Return an int.
462 * interp.c (sim_monitor): Add return values.
463 (signal_exception): Handle error conditions from sim_monitor.
464
56b48a7a
CD		 4652001-02-08 Ben Elliston <bje@redhat.com>
466
467 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
468 (store_memory): Likewise, pass cia to sim_core_write*.
469
d3ee60d9
FCE		 4702000-10-19 Frank Ch. Eigler <fche@redhat.com>
471
472 On advice from Chris G. Demetriou <cgd@sibyte.com>:
473 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
474
071da002
AC		 475Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
476
477 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
478 * Makefile.in: Don't delete *.igen when cleaning directory.
479
a28c02cd
AC		 480Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
481
482 * m16.igen (break): Call SignalException not sim_engine_halt.
483
80ee11fa
AC		 484Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
485
486 From Jason Eckhardt:
487 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
488
673388c0
AC		 489Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
490
491 * mips.igen (MxC1, DMxC1): Fix printf formatting.
492
4c0deff4
NC		 4932000-05-24 Michael Hayes <mhayes@cygnus.com>
494
495 * mips.igen (do_dmultx): Fix typo.
496
eb2d80b4
AC		 497Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
498
499 * configure: Regenerated to track ../common/aclocal.m4 changes.
500
dd37a34b
AC		 501Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
502
503 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
504
4c0deff4
NC		 5052000-04-12 Frank Ch. Eigler <fche@redhat.com>
506
507 * sim-main.h (GPR_CLEAR): Define macro.
508
e30db738
AC		 509Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
510
511 * interp.c (decode_coproc): Output long using %lx and not %s.
512
cb7450ea
FCE		 5132000-03-21 Frank Ch. Eigler <fche@redhat.com>
514
515 * interp.c (sim_open): Sort & extend dummy memory regions for
516 --board=jmr3904 for eCos.
517
a3027dd7
FCE		 5182000-03-02 Frank Ch. Eigler <fche@redhat.com>
519
520 * configure: Regenerated.
521
522Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
523
524 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
525 calls, conditional on the simulator being in verbose mode.
526
dfcd3bfb
JM		 527Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
528
529 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
530 cache don't get ReservedInstruction traps.
531
c2d11a7d
JM		 5321999-11-29 Mark Salter <msalter@cygnus.com>
533
534 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
535 to clear status bits in sdisr register. This is how the hardware works.
536
537 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
538 being used by cygmon.
539
4ce44c66
JM		 5401999-11-11 Andrew Haley <aph@cygnus.com>
541
542 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
543 instructions.
544
cff3e48b
JM		 545Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
546
547 * mips.igen (MULT): Correct previous mis-applied patch.
548
d4f3574e
SS		 549Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
550
551 * mips.igen (delayslot32): Handle sequence like
552 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
553 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
554 (MULT): Actually pass the third register...
555
5561999-09-03 Mark Salter <msalter@cygnus.com>
557
558 * interp.c (sim_open): Added more memory aliases for additional
559 hardware being touched by cygmon on jmr3904 board.
560
561Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
562
563 * configure: Regenerated to track ../common/aclocal.m4 changes.
564
a0b3c4fd
JM		 565Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
566
567 * interp.c (sim_store_register): Handle case where client - GDB -
568 specifies that a 4 byte register is 8 bytes in size.
569 (sim_fetch_register): Ditto.
570
adf40b2e
JM		 5711999-07-14 Frank Ch. Eigler <fche@cygnus.com>
572
573 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
574 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
575 (idt_monitor_base): Base address for IDT monitor traps.
576 (pmon_monitor_base): Ditto for PMON.
577 (lsipmon_monitor_base): Ditto for LSI PMON.
578 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
579 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
580 (sim_firmware_command): New function.
581 (mips_option_handler): Call it for OPTION_FIRMWARE.
582 (sim_open): Allocate memory for idt_monitor region. If "--board"
583 option was given, add no monitor by default. Add BREAK hooks only if
584 monitors are also there.
585
43e526b9
JM		 586Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
587
588 * interp.c (sim_monitor): Flush output before reading input.
589
590Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
591
592 * tconfig.in (SIM_HANDLES_LMA): Always define.
593
594Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
595
596 From Mark Salter <msalter@cygnus.com>:
597 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
598 (sim_open): Add setup for BSP board.
599
9846de1b
JM		 600Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
601
602 * mips.igen (MULT, MULTU): Add syntax for two operand version.
603 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
604 them as unimplemented.
605
cd0fc7c3
SS		 6061999-05-08 Felix Lee <flee@cygnus.com>
607
608 * configure: Regenerated to track ../common/aclocal.m4 changes.
609
7a292a7a
SS		 6101999-04-21 Frank Ch. Eigler <fche@cygnus.com>
611
612 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
613
614Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
615
616 * configure.in: Any mips64vr5*-*-* target should have
617 -DTARGET_ENABLE_FR=1.
618 (default_endian): Any mips64vr*el-*-* target should default to
619 LITTLE_ENDIAN.
620 * configure: Re-generate.
621
6221999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
623
624 * mips.igen (ldl): Extend from _16_, not 32.
625
626Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
627
628 * interp.c (sim_store_register): Force registers written to by GDB
629 into an un-interpreted state.
630
c906108c
SS		 6311999-02-05 Frank Ch. Eigler <fche@cygnus.com>
632
633 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
634 CPU, start periodic background I/O polls.
635 (tx3904sio_poll): New function: periodic I/O poller.
636
6371998-12-30 Frank Ch. Eigler <fche@cygnus.com>
638
639 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
640
641Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
642
643 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
644 case statement.
645
6461998-12-29 Frank Ch. Eigler <fche@cygnus.com>
647
648 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
649 (load_word): Call SIM_CORE_SIGNAL hook on error.
650 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
651 starting. For exception dispatching, pass PC instead of NULL_CIA.
652 (decode_coproc): Use COP0_BADVADDR to store faulting address.
653 * sim-main.h (COP0_BADVADDR): Define.
654 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
655 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
656 (_sim_cpu): Add exc_* fields to store register value snapshots.
657 * mips.igen (*): Replace memory-related SignalException* calls
658 with references to SIM_CORE_SIGNAL hook.
659
660 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
661 fix.
662 * sim-main.c (*): Minor warning cleanups.
663
6641998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
665
666 * m16.igen (DADDIU5): Correct type-o.
667
668Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
669
670 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
671 variables.
672
673Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
674
675 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
676 to include path.
677 (interp.o): Add dependency on itable.h
678 (oengine.c, gencode): Delete remaining references.
679 (BUILT_SRC_FROM_GEN): Clean up.
680
6811998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
682
683 * vr4run.c: New.
684 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
685 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
686 tmp-run-hack) : New.
687 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
688 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
689 Drop the "64" qualifier to get the HACK generator working.
690 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
691 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
692 qualifier to get the hack generator working.
693 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
694 (DSLL): Use do_dsll.
695 (DSLLV): Use do_dsllv.
696 (DSRA): Use do_dsra.
697 (DSRL): Use do_dsrl.
698 (DSRLV): Use do_dsrlv.
699 (BC1): Move *vr4100 to get the HACK generator working.
700 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
701 get the HACK generator working.
702 (MACC) Rename to get the HACK generator working.
703 (DMACC,MACCS,DMACCS): Add the 64.
704
7051998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
706
707 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
708 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
709
7101998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
711
712 * mips/interp.c (DEBUG): Cleanups.
713
7141998-12-10 Frank Ch. Eigler <fche@cygnus.com>
715
716 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
717 (tx3904sio_tickle): fflush after a stdout character output.
718
7191998-12-03 Frank Ch. Eigler <fche@cygnus.com>
720
721 * interp.c (sim_close): Uninstall modules.
722
723Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
724
725 * sim-main.h, interp.c (sim_monitor): Change to global
726 function.
727
728Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
729
730 * configure.in (vr4100): Only include vr4100 instructions in
731 simulator.
732 * configure: Re-generate.
733 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
734
735Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
736
737 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
738 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
739 true alternative.
740
741 * configure.in (sim_default_gen, sim_use_gen): Replace with
742 sim_gen.
743 (--enable-sim-igen): Delete config option. Always using IGEN.
744 * configure: Re-generate.
745
746 * Makefile.in (gencode): Kill, kill, kill.
747 * gencode.c: Ditto.
748
749Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
750
751 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
752 bit mips16 igen simulator.
753 * configure: Re-generate.
754
755 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
756 as part of vr4100 ISA.
757 * vr.igen: Mark all instructions as 64 bit only.
758
759Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
760
761 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
762 Pacify GCC.
763
764Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
765
766 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
767 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
768 * configure: Re-generate.
769
770 * m16.igen (BREAK): Define breakpoint instruction.
771 (JALX32): Mark instruction as mips16 and not r3900.
772 * mips.igen (C.cond.fmt): Fix typo in instruction format.
773
774 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
775
776Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
777
778 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
779 insn as a debug breakpoint.
780
781 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
782 pending.slot_size.
783 (PENDING_SCHED): Clean up trace statement.
784 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
785 (PENDING_FILL): Delay write by only one cycle.
786 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
787
788 * sim-main.c (pending_tick): Clean up trace statements. Add trace
789 of pending writes.
790 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
791 32 & 64.
792 (pending_tick): Move incrementing of index to FOR statement.
793 (pending_tick): Only update PENDING_OUT after a write has occured.
794
795 * configure.in: Add explicit mips-lsi-* target. Use gencode to
796 build simulator.
797 * configure: Re-generate.
798
799 * interp.c (sim_engine_run OLD): Delete explicit call to
800 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
801
802Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
803
804 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
805 interrupt level number to match changed SignalExceptionInterrupt
806 macro.
807
808Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
809
810 * interp.c: #include "itable.h" if WITH_IGEN.
811 (get_insn_name): New function.
812 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
813 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
814
815Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
816
817 * configure: Rebuilt to inhale new common/aclocal.m4.
818
819Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
820
821 * dv-tx3904sio.c: Include sim-assert.h.
822
823Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
824
825 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
826 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
827 Reorganize target-specific sim-hardware checks.
828 * configure: rebuilt.
829 * interp.c (sim_open): For tx39 target boards, set
830 OPERATING_ENVIRONMENT, add tx3904sio devices.
831 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
832 ROM executables. Install dv-sockser into sim-modules list.
833
834 * dv-tx3904irc.c: Compiler warning clean-up.
835 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
836 frequent hw-trace messages.
837
838Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
839
840 * vr.igen (MulAcc): Identify as a vr4100 specific function.
841
842Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
843
844 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
845
846 * vr.igen: New file.
847 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
848 * mips.igen: Define vr4100 model. Include vr.igen.
849Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
850
851 * mips.igen (check_mf_hilo): Correct check.
852
853Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
854
855 * sim-main.h (interrupt_event): Add prototype.
856
857 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
858 register_ptr, register_value.
859 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
860
861 * sim-main.h (tracefh): Make extern.
862
863Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
864
865 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
866 Reduce unnecessarily high timer event frequency.
867 * dv-tx3904cpu.c: Ditto for interrupt event.
868
869Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
870
871 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
872 to allay warnings.
873 (interrupt_event): Made non-static.
874
875 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
876 interchange of configuration values for external vs. internal
877 clock dividers.
878
879Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
880
881 * mips.igen (BREAK): Moved code to here for
882 simulator-reserved break instructions.
883 * gencode.c (build_instruction): Ditto.
884 * interp.c (signal_exception): Code moved from here. Non-
885 reserved instructions now use exception vector, rather
886 than halting sim.
887 * sim-main.h: Moved magic constants to here.
888
889Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
890
891 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
892 register upon non-zero interrupt event level, clear upon zero
893 event value.
894 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
895 by passing zero event value.
896 (*_io_{read,write}_buffer): Endianness fixes.
897 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
898 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
899
900 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
901 serial I/O and timer module at base address 0xFFFF0000.
902
903Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
904
905 * mips.igen (SWC1) : Correct the handling of ReverseEndian
906 and BigEndianCPU.
907
908Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
909
910 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
911 parts.
912 * configure: Update.
913
914Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
915
916 * dv-tx3904tmr.c: New file - implements tx3904 timer.
917 * dv-tx3904{irc,cpu}.c: Mild reformatting.
918 * configure.in: Include tx3904tmr in hw_device list.
919 * configure: Rebuilt.
920 * interp.c (sim_open): Instantiate three timer instances.
921 Fix address typo of tx3904irc instance.
922
923Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
924
925 * interp.c (signal_exception): SystemCall exception now uses
926 the exception vector.
927
928Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
929
930 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
931 to allay warnings.
932
933Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
934
935 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
936
937Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
938
939 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
940
941 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
942 sim-main.h. Declare a struct hw_descriptor instead of struct
943 hw_device_descriptor.
944
945Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
946
947 * mips.igen (do_store_left, do_load_left): Compute nr of left and
948 right bits and then re-align left hand bytes to correct byte
949 lanes. Fix incorrect computation in do_store_left when loading
950 bytes from second word.
951
952Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
953
954 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
955 * interp.c (sim_open): Only create a device tree when HW is
956 enabled.
957
958 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
959 * interp.c (signal_exception): Ditto.
960
961Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
962
963 * gencode.c: Mark BEGEZALL as LIKELY.
964
965Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
966
967 * sim-main.h (ALU32_END): Sign extend 32 bit results.
968 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
969
970Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
971
972 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
973 modules. Recognize TX39 target with "mips*tx39" pattern.
974 * configure: Rebuilt.
975 * sim-main.h (*): Added many macros defining bits in
976 TX39 control registers.
977 (SignalInterrupt): Send actual PC instead of NULL.
978 (SignalNMIReset): New exception type.
979 * interp.c (board): New variable for future use to identify
980 a particular board being simulated.
981 (mips_option_handler,mips_options): Added "--board" option.
982 (interrupt_event): Send actual PC.
983 (sim_open): Make memory layout conditional on board setting.
984 (signal_exception): Initial implementation of hardware interrupt
985 handling. Accept another break instruction variant for simulator
986 exit.
987 (decode_coproc): Implement RFE instruction for TX39.
988 (mips.igen): Decode RFE instruction as such.
989 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
990 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
991 bbegin to implement memory map.
992 * dv-tx3904cpu.c: New file.
993 * dv-tx3904irc.c: New file.
994
995Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
996
997 * mips.igen (check_mt_hilo): Create a separate r3900 version.
998
999Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1000
1001 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1002 with calls to check_div_hilo.
1003
1004Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1005
1006 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1007 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1008 Add special r3900 version of do_mult_hilo.
1009 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1010 with calls to check_mult_hilo.
1011 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1012 with calls to check_div_hilo.
1013
1014Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1015
1016 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1017 Document a replacement.
1018
1019Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1020
1021 * interp.c (sim_monitor): Make mon_printf work.
1022
1023Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1024
1025 * sim-main.h (INSN_NAME): New arg `cpu'.
1026
1027Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1028
1029 * configure: Regenerated to track ../common/aclocal.m4 changes.
1030
1031Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1032
1033 * configure: Regenerated to track ../common/aclocal.m4 changes.
1034 * config.in: Ditto.
1035
1036Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1037
1038 * acconfig.h: New file.
1039 * configure.in: Reverted change of Apr 24; use sinclude again.
1040
1041Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1042
1043 * configure: Regenerated to track ../common/aclocal.m4 changes.
1044 * config.in: Ditto.
1045
1046Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1047
1048 * configure.in: Don't call sinclude.
1049
1050Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1051
1052 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1053
1054Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1055
1056 * mips.igen (ERET): Implement.
1057
1058 * interp.c (decode_coproc): Return sign-extended EPC.
1059
1060 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1061
1062 * interp.c (signal_exception): Do not ignore Trap.
1063 (signal_exception): On TRAP, restart at exception address.
1064 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1065 (signal_exception): Update.
1066 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1067 so that TRAP instructions are caught.
1068
1069Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1070
1071 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1072 contains HI/LO access history.
1073 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1074 (HIACCESS, LOACCESS): Delete, replace with
1075 (HIHISTORY, LOHISTORY): New macros.
1076 (CHECKHILO): Delete all, moved to mips.igen
1077
1078 * gencode.c (build_instruction): Do not generate checks for
1079 correct HI/LO register usage.
1080
1081 * interp.c (old_engine_run): Delete checks for correct HI/LO
1082 register usage.
1083
1084 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1085 check_mf_cycles): New functions.
1086 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1087 do_divu, domultx, do_mult, do_multu): Use.
1088
1089 * tx.igen ("madd", "maddu"): Use.
1090
1091Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1092
1093 * mips.igen (DSRAV): Use function do_dsrav.
1094 (SRAV): Use new function do_srav.
1095
1096 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1097 (B): Sign extend 11 bit immediate.
1098 (EXT-B*): Shift 16 bit immediate left by 1.
1099 (ADDIU*): Don't sign extend immediate value.
1100
1101Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1102
1103 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1104
1105 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1106 functions.
1107
1108 * mips.igen (delayslot32, nullify_next_insn): New functions.
1109 (m16.igen): Always include.
1110 (do_*): Add more tracing.
1111
1112 * m16.igen (delayslot16): Add NIA argument, could be called by a
1113 32 bit MIPS16 instruction.
1114
1115 * interp.c (ifetch16): Move function from here.
1116 * sim-main.c (ifetch16): To here.
1117
1118 * sim-main.c (ifetch16, ifetch32): Update to match current
1119 implementations of LH, LW.
1120 (signal_exception): Don't print out incorrect hex value of illegal
1121 instruction.
1122
1123Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1124
1125 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1126 instruction.
1127
1128 * m16.igen: Implement MIPS16 instructions.
1129
1130 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1131 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1132 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1133 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1134 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1135 bodies of corresponding code from 32 bit insn to these. Also used
1136 by MIPS16 versions of functions.
1137
1138 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1139 (IMEM16): Drop NR argument from macro.
1140
1141Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * Makefile.in (SIM_OBJS): Add sim-main.o.
1144
1145 * sim-main.h (address_translation, load_memory, store_memory,
1146 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1147 as INLINE_SIM_MAIN.
1148 (pr_addr, pr_uword64): Declare.
1149 (sim-main.c): Include when H_REVEALS_MODULE_P.
1150
1151 * interp.c (address_translation, load_memory, store_memory,
1152 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1153 from here.
1154 * sim-main.c: To here. Fix compilation problems.
1155
1156 * configure.in: Enable inlining.
1157 * configure: Re-config.
1158
1159Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1160
1161 * configure: Regenerated to track ../common/aclocal.m4 changes.
1162
1163Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1164
1165 * mips.igen: Include tx.igen.
1166 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1167 * tx.igen: New file, contains MADD and MADDU.
1168
1169 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1170 the hardwired constant `7'.
1171 (store_memory): Ditto.
1172 (LOADDRMASK): Move definition to sim-main.h.
1173
1174 mips.igen (MTC0): Enable for r3900.
1175 (ADDU): Add trace.
1176
1177 mips.igen (do_load_byte): Delete.
1178 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1179 do_store_right): New functions.
1180 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1181
1182 configure.in: Let the tx39 use igen again.
1183 configure: Update.
1184
1185Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1186
1187 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1188 not an address sized quantity. Return zero for cache sizes.
1189
1190Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * mips.igen (r3900): r3900 does not support 64 bit integer
1193 operations.
1194
1195Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1196
1197 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1198 than igen one.
1199 * configure : Rebuild.
1200
1201Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1202
1203 * configure: Regenerated to track ../common/aclocal.m4 changes.
1204
1205Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1206
1207 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1208
1209Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1210
1211 * configure: Regenerated to track ../common/aclocal.m4 changes.
1212 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1213
1214Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1215
1216 * configure: Regenerated to track ../common/aclocal.m4 changes.
1217
1218Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1219
1220 * interp.c (Max, Min): Comment out functions. Not yet used.
1221
1222Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1223
1224 * configure: Regenerated to track ../common/aclocal.m4 changes.
1225
1226Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1227
1228 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1229 configurable settings for stand-alone simulator.
1230
1231 * configure.in: Added X11 search, just in case.
1232
1233 * configure: Regenerated.
1234
1235Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1236
1237 * interp.c (sim_write, sim_read, load_memory, store_memory):
1238 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1239
1240Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1241
1242 * sim-main.h (GETFCC): Return an unsigned value.
1243
1244Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1245
1246 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1247 (DADD): Result destination is RD not RT.
1248
1249Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1250
1251 * sim-main.h (HIACCESS, LOACCESS): Always define.
1252
1253 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1254
1255 * interp.c (sim_info): Delete.
1256
1257Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1258
1259 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1260 (mips_option_handler): New argument `cpu'.
1261 (sim_open): Update call to sim_add_option_table.
1262
1263Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1264
1265 * mips.igen (CxC1): Add tracing.
1266
1267Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1268
1269 * sim-main.h (Max, Min): Declare.
1270
1271 * interp.c (Max, Min): New functions.
1272
1273 * mips.igen (BC1): Add tracing.
1274
1275Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1276
1277 * interp.c Added memory map for stack in vr4100
1278
1279Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1280
1281 * interp.c (load_memory): Add missing "break"'s.
1282
1283Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1284
1285 * interp.c (sim_store_register, sim_fetch_register): Pass in
1286 length parameter. Return -1.
1287
1288Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1289
1290 * interp.c: Added hardware init hook, fixed warnings.
1291
1292Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1293
1294 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1295
1296Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1297
1298 * interp.c (ifetch16): New function.
1299
1300 * sim-main.h (IMEM32): Rename IMEM.
1301 (IMEM16_IMMED): Define.
1302 (IMEM16): Define.
1303 (DELAY_SLOT): Update.
1304
1305 * m16run.c (sim_engine_run): New file.
1306
1307 * m16.igen: All instructions except LB.
1308 (LB): Call do_load_byte.
1309 * mips.igen (do_load_byte): New function.
1310 (LB): Call do_load_byte.
1311
1312 * mips.igen: Move spec for insn bit size and high bit from here.
1313 * Makefile.in (tmp-igen, tmp-m16): To here.
1314
1315 * m16.dc: New file, decode mips16 instructions.
1316
1317 * Makefile.in (SIM_NO_ALL): Define.
1318 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1319
1320Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1321
1322 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1323 point unit to 32 bit registers.
1324 * configure: Re-generate.
1325
1326Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * configure.in (sim_use_gen): Make IGEN the default simulator
1329 generator for generic 32 and 64 bit mips targets.
1330 * configure: Re-generate.
1331
1332Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1333
1334 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1335 bitsize.
1336
1337 * interp.c (sim_fetch_register, sim_store_register): Read/write
1338 FGR from correct location.
1339 (sim_open): Set size of FGR's according to
1340 WITH_TARGET_FLOATING_POINT_BITSIZE.
1341
1342 * sim-main.h (FGR): Store floating point registers in a separate
1343 array.
1344
1345Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1346
1347 * configure: Regenerated to track ../common/aclocal.m4 changes.
1348
1349Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1350
1351 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1352
1353 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1354
1355 * interp.c (pending_tick): New function. Deliver pending writes.
1356
1357 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1358 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1359 it can handle mixed sized quantites and single bits.
1360
1361Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362
1363 * interp.c (oengine.h): Do not include when building with IGEN.
1364 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1365 (sim_info): Ditto for PROCESSOR_64BIT.
1366 (sim_monitor): Replace ut_reg with unsigned_word.
1367 (*): Ditto for t_reg.
1368 (LOADDRMASK): Define.
1369 (sim_open): Remove defunct check that host FP is IEEE compliant,
1370 using software to emulate floating point.
1371 (value_fpr, ...): Always compile, was conditional on HASFPU.
1372
1373Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1376 size.
1377
1378 * interp.c (SD, CPU): Define.
1379 (mips_option_handler): Set flags in each CPU.
1380 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1381 (sim_close): Do not clear STATE, deleted anyway.
1382 (sim_write, sim_read): Assume CPU zero's vm should be used for
1383 data transfers.
1384 (sim_create_inferior): Set the PC for all processors.
1385 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1386 argument.
1387 (mips16_entry): Pass correct nr of args to store_word, load_word.
1388 (ColdReset): Cold reset all cpu's.
1389 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1390 (sim_monitor, load_memory, store_memory, signal_exception): Use
1391 `CPU' instead of STATE_CPU.
1392
1393
1394 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1395 SD or CPU_.
1396
1397 * sim-main.h (signal_exception): Add sim_cpu arg.
1398 (SignalException*): Pass both SD and CPU to signal_exception.
1399 * interp.c (signal_exception): Update.
1400
1401 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1402 Ditto
1403 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1404 address_translation): Ditto
1405 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1406
1407Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1408
1409 * configure: Regenerated to track ../common/aclocal.m4 changes.
1410
1411Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1412
1413 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1414
1415 * mips.igen (model): Map processor names onto BFD name.
1416
1417 * sim-main.h (CPU_CIA): Delete.
1418 (SET_CIA, GET_CIA): Define
1419
1420Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1421
1422 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1423 regiser.
1424
1425 * configure.in (default_endian): Configure a big-endian simulator
1426 by default.
1427 * configure: Re-generate.
1428
1429Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1430
1431 * configure: Regenerated to track ../common/aclocal.m4 changes.
1432
1433Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1434
1435 * interp.c (sim_monitor): Handle Densan monitor outbyte
1436 and inbyte functions.
1437
14381997-12-29 Felix Lee <flee@cygnus.com>
1439
1440 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1441
1442Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1443
1444 * Makefile.in (tmp-igen): Arrange for $zero to always be
1445 reset to zero after every instruction.
1446
1447Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1448
1449 * configure: Regenerated to track ../common/aclocal.m4 changes.
1450 * config.in: Ditto.
1451
1452Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1453
1454 * mips.igen (MSUB): Fix to work like MADD.
1455 * gencode.c (MSUB): Similarly.
1456
1457Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1458
1459 * configure: Regenerated to track ../common/aclocal.m4 changes.
1460
1461Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1462
1463 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1464
1465Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1466
1467 * sim-main.h (sim-fpu.h): Include.
1468
1469 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1470 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1471 using host independant sim_fpu module.
1472
1473Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1474
1475 * interp.c (signal_exception): Report internal errors with SIGABRT
1476 not SIGQUIT.
1477
1478 * sim-main.h (C0_CONFIG): New register.
1479 (signal.h): No longer include.
1480
1481 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1482
1483Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1484
1485 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1486
1487Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * mips.igen: Tag vr5000 instructions.
1490 (ANDI): Was missing mipsIV model, fix assembler syntax.
1491 (do_c_cond_fmt): New function.
1492 (C.cond.fmt): Handle mips I-III which do not support CC field
1493 separatly.
1494 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1495 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1496 in IV3.2 spec.
1497 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1498 vr5000 which saves LO in a GPR separatly.
1499
1500 * configure.in (enable-sim-igen): For vr5000, select vr5000
1501 specific instructions.
1502 * configure: Re-generate.
1503
1504Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1505
1506 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1507
1508 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1509 fmt_uninterpreted_64 bit cases to switch. Convert to
1510 fmt_formatted,
1511
1512 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1513
1514 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1515 as specified in IV3.2 spec.
1516 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1517
1518Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1519
1520 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1521 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1522 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1523 PENDING_FILL versions of instructions. Simplify.
1524 (X): New function.
1525 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1526 instructions.
1527 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1528 a signed value.
1529 (MTHI, MFHI): Disable code checking HI-LO.
1530
1531 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1532 global.
1533 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1534
1535Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1536
1537 * gencode.c (build_mips16_operands): Replace IPC with cia.
1538
1539 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1540 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1541 IPC to `cia'.
1542 (UndefinedResult): Replace function with macro/function
1543 combination.
1544 (sim_engine_run): Don't save PC in IPC.
1545
1546 * sim-main.h (IPC): Delete.
1547
1548
1549 * interp.c (signal_exception, store_word, load_word,
1550 address_translation, load_memory, store_memory, cache_op,
1551 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1552 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1553 current instruction address - cia - argument.
1554 (sim_read, sim_write): Call address_translation directly.
1555 (sim_engine_run): Rename variable vaddr to cia.
1556 (signal_exception): Pass cia to sim_monitor
1557
1558 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1559 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1560 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1561
1562 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1563 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1564 SIM_ASSERT.
1565
1566 * interp.c (signal_exception): Pass restart address to
1567 sim_engine_restart.
1568
1569 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1570 idecode.o): Add dependency.
1571
1572 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1573 Delete definitions
1574 (DELAY_SLOT): Update NIA not PC with branch address.
1575 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1576
1577 * mips.igen: Use CIA not PC in branch calculations.
1578 (illegal): Call SignalException.
1579 (BEQ, ADDIU): Fix assembler.
1580
1581Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1582
1583 * m16.igen (JALX): Was missing.
1584
1585 * configure.in (enable-sim-igen): New configuration option.
1586 * configure: Re-generate.
1587
1588 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1589
1590 * interp.c (load_memory, store_memory): Delete parameter RAW.
1591 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1592 bypassing {load,store}_memory.
1593
1594 * sim-main.h (ByteSwapMem): Delete definition.
1595
1596 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1597
1598 * interp.c (sim_do_command, sim_commands): Delete mips specific
1599 commands. Handled by module sim-options.
1600
1601 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1602 (WITH_MODULO_MEMORY): Define.
1603
1604 * interp.c (sim_info): Delete code printing memory size.
1605
1606 * interp.c (mips_size): Nee sim_size, delete function.
1607 (power2): Delete.
1608 (monitor, monitor_base, monitor_size): Delete global variables.
1609 (sim_open, sim_close): Delete code creating monitor and other
1610 memory regions. Use sim-memopts module, via sim_do_commandf, to
1611 manage memory regions.
1612 (load_memory, store_memory): Use sim-core for memory model.
1613
1614 * interp.c (address_translation): Delete all memory map code
1615 except line forcing 32 bit addresses.
1616
1617Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1620 trace options.
1621
1622 * interp.c (logfh, logfile): Delete globals.
1623 (sim_open, sim_close): Delete code opening & closing log file.
1624 (mips_option_handler): Delete -l and -n options.
1625 (OPTION mips_options): Ditto.
1626
1627 * interp.c (OPTION mips_options): Rename option trace to dinero.
1628 (mips_option_handler): Update.
1629
1630Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1631
1632 * interp.c (fetch_str): New function.
1633 (sim_monitor): Rewrite using sim_read & sim_write.
1634 (sim_open): Check magic number.
1635 (sim_open): Write monitor vectors into memory using sim_write.
1636 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1637 (sim_read, sim_write): Simplify - transfer data one byte at a
1638 time.
1639 (load_memory, store_memory): Clarify meaning of parameter RAW.
1640
1641 * sim-main.h (isHOST): Defete definition.
1642 (isTARGET): Mark as depreciated.
1643 (address_translation): Delete parameter HOST.
1644
1645 * interp.c (address_translation): Delete parameter HOST.
1646
1647Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1648
1649 * mips.igen:
1650
1651 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1652 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1653
1654Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1655
1656 * mips.igen: Add model filter field to records.
1657
1658Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1659
1660 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1661
1662 interp.c (sim_engine_run): Do not compile function sim_engine_run
1663 when WITH_IGEN == 1.
1664
1665 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1666 target architecture.
1667
1668 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1669 igen. Replace with configuration variables sim_igen_flags /
1670 sim_m16_flags.
1671
1672 * m16.igen: New file. Copy mips16 insns here.
1673 * mips.igen: From here.
1674
1675Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1678 to top.
1679 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1680
1681Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1682
1683 * gencode.c (build_instruction): Follow sim_write's lead in using
1684 BigEndianMem instead of !ByteSwapMem.
1685
1686Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1687
1688 * configure.in (sim_gen): Dependent on target, select type of
1689 generator. Always select old style generator.
1690
1691 configure: Re-generate.
1692
1693 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1694 targets.
1695 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1696 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1697 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1698 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1699 SIM_@sim_gen@_*, set by autoconf.
1700
1701Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1704
1705 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1706 CURRENT_FLOATING_POINT instead.
1707
1708 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1709 (address_translation): Raise exception InstructionFetch when
1710 translation fails and isINSTRUCTION.
1711
1712 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1713 sim_engine_run): Change type of of vaddr and paddr to
1714 address_word.
1715 (address_translation, prefetch, load_memory, store_memory,
1716 cache_op): Change type of vAddr and pAddr to address_word.
1717
1718 * gencode.c (build_instruction): Change type of vaddr and paddr to
1719 address_word.
1720
1721Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1722
1723 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1724 macro to obtain result of ALU op.
1725
1726Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727
1728 * interp.c (sim_info): Call profile_print.
1729
1730Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1733
1734 * sim-main.h (WITH_PROFILE): Do not define, defined in
1735 common/sim-config.h. Use sim-profile module.
1736 (simPROFILE): Delete defintion.
1737
1738 * interp.c (PROFILE): Delete definition.
1739 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1740 (sim_close): Delete code writing profile histogram.
1741 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1742 Delete.
1743 (sim_engine_run): Delete code profiling the PC.
1744
1745Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1746
1747 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1748
1749 * interp.c (sim_monitor): Make register pointers of type
1750 unsigned_word*.
1751
1752 * sim-main.h: Make registers of type unsigned_word not
1753 signed_word.
1754
1755Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * interp.c (sync_operation): Rename from SyncOperation, make
1758 global, add SD argument.
1759 (prefetch): Rename from Prefetch, make global, add SD argument.
1760 (decode_coproc): Make global.
1761
1762 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1763
1764 * gencode.c (build_instruction): Generate DecodeCoproc not
1765 decode_coproc calls.
1766
1767 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1768 (SizeFGR): Move to sim-main.h
1769 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1770 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1771 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1772 sim-main.h.
1773 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1774 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1775 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1776 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1777 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1778 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1779
1780 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1781 exception.
1782 (sim-alu.h): Include.
1783 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1784 (sim_cia): Typedef to instruction_address.
1785
1786Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1787
1788 * Makefile.in (interp.o): Rename generated file engine.c to
1789 oengine.c.
1790
1791 * interp.c: Update.
1792
1793Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794
1795 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1796
1797Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1798
1799 * gencode.c (build_instruction): For "FPSQRT", output correct
1800 number of arguments to Recip.
1801
1802Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1803
1804 * Makefile.in (interp.o): Depends on sim-main.h
1805
1806 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1807
1808 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1809 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1810 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1811 STATE, DSSTATE): Define
1812 (GPR, FGRIDX, ..): Define.
1813
1814 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1815 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1816 (GPR, FGRIDX, ...): Delete macros.
1817
1818 * interp.c: Update names to match defines from sim-main.h
1819
1820Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1821
1822 * interp.c (sim_monitor): Add SD argument.
1823 (sim_warning): Delete. Replace calls with calls to
1824 sim_io_eprintf.
1825 (sim_error): Delete. Replace calls with sim_io_error.
1826 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1827 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1828 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1829 argument.
1830 (mips_size): Rename from sim_size. Add SD argument.
1831
1832 * interp.c (simulator): Delete global variable.
1833 (callback): Delete global variable.
1834 (mips_option_handler, sim_open, sim_write, sim_read,
1835 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1836 sim_size,sim_monitor): Use sim_io_* not callback->*.
1837 (sim_open): ZALLOC simulator struct.
1838 (PROFILE): Do not define.
1839
1840Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1841
1842 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1843 support.h with corresponding code.
1844
1845 * sim-main.h (word64, uword64), support.h: Move definition to
1846 sim-main.h.
1847 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1848
1849 * support.h: Delete
1850 * Makefile.in: Update dependencies
1851 * interp.c: Do not include.
1852
1853Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * interp.c (address_translation, load_memory, store_memory,
1856 cache_op): Rename to from AddressTranslation et.al., make global,
1857 add SD argument
1858
1859 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1860 CacheOp): Define.
1861
1862 * interp.c (SignalException): Rename to signal_exception, make
1863 global.
1864
1865 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1866
1867 * sim-main.h (SignalException, SignalExceptionInterrupt,
1868 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1869 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1870 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1871 Define.
1872
1873 * interp.c, support.h: Use.
1874
1875Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1876
1877 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1878 to value_fpr / store_fpr. Add SD argument.
1879 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1880 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1881
1882 * sim-main.h (ValueFPR, StoreFPR): Define.
1883
1884Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * interp.c (sim_engine_run): Check consistency between configure
1887 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1888 and HASFPU.
1889
1890 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1891 (mips_fpu): Configure WITH_FLOATING_POINT.
1892 (mips_endian): Configure WITH_TARGET_ENDIAN.
1893 * configure: Update.
1894
1895Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1896
1897 * configure: Regenerated to track ../common/aclocal.m4 changes.
1898
1899Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1900
1901 * configure: Regenerated.
1902
1903Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1904
1905 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1906
1907Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * gencode.c (print_igen_insn_models): Assume certain architectures
1910 include all mips* instructions.
1911 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1912 instruction.
1913
1914 * Makefile.in (tmp.igen): Add target. Generate igen input from
1915 gencode file.
1916
1917 * gencode.c (FEATURE_IGEN): Define.
1918 (main): Add --igen option. Generate output in igen format.
1919 (process_instructions): Format output according to igen option.
1920 (print_igen_insn_format): New function.
1921 (print_igen_insn_models): New function.
1922 (process_instructions): Only issue warnings and ignore
1923 instructions when no FEATURE_IGEN.
1924
1925Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1928 MIPS targets.
1929
1930Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1931
1932 * configure: Regenerated to track ../common/aclocal.m4 changes.
1933
1934Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1935
1936 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1937 SIM_RESERVED_BITS): Delete, moved to common.
1938 (SIM_EXTRA_CFLAGS): Update.
1939
1940Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1941
1942 * configure.in: Configure non-strict memory alignment.
1943 * configure: Regenerated to track ../common/aclocal.m4 changes.
1944
1945Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1946
1947 * configure: Regenerated to track ../common/aclocal.m4 changes.
1948
1949Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1950
1951 * gencode.c (SDBBP,DERET): Added (3900) insns.
1952 (RFE): Turn on for 3900.
1953 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1954 (dsstate): Made global.
1955 (SUBTARGET_R3900): Added.
1956 (CANCELDELAYSLOT): New.
1957 (SignalException): Ignore SystemCall rather than ignore and
1958 terminate. Add DebugBreakPoint handling.
1959 (decode_coproc): New insns RFE, DERET; and new registers Debug
1960 and DEPC protected by SUBTARGET_R3900.
1961 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1962 bits explicitly.
1963 * Makefile.in,configure.in: Add mips subtarget option.
1964 * configure: Update.
1965
1966Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1967
1968 * gencode.c: Add r3900 (tx39).
1969
1970
1971Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1972
1973 * gencode.c (build_instruction): Don't need to subtract 4 for
1974 JALR, just 2.
1975
1976Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1977
1978 * interp.c: Correct some HASFPU problems.
1979
1980Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1981
1982 * configure: Regenerated to track ../common/aclocal.m4 changes.
1983
1984Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1985
1986 * interp.c (mips_options): Fix samples option short form, should
1987 be `x'.
1988
1989Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1990
1991 * interp.c (sim_info): Enable info code. Was just returning.
1992
1993Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1996 MFC0.
1997
1998Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1999
2000 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2001 constants.
2002 (build_instruction): Ditto for LL.
2003
2004Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2005
2006 * configure: Regenerated to track ../common/aclocal.m4 changes.
2007
2008Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2009
2010 * configure: Regenerated to track ../common/aclocal.m4 changes.
2011 * config.in: Ditto.
2012
2013Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2014
2015 * interp.c (sim_open): Add call to sim_analyze_program, update
2016 call to sim_config.
2017
2018Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2019
2020 * interp.c (sim_kill): Delete.
2021 (sim_create_inferior): Add ABFD argument. Set PC from same.
2022 (sim_load): Move code initializing trap handlers from here.
2023 (sim_open): To here.
2024 (sim_load): Delete, use sim-hload.c.
2025
2026 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2027
2028Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2029
2030 * configure: Regenerated to track ../common/aclocal.m4 changes.
2031 * config.in: Ditto.
2032
2033Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2034
2035 * interp.c (sim_open): Add ABFD argument.
2036 (sim_load): Move call to sim_config from here.
2037 (sim_open): To here. Check return status.
2038
2039Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2040
2041 * gencode.c (build_instruction): Two arg MADD should
2042 not assign result to $0.
2043
2044Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2045
2046 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2047 * sim/mips/configure.in: Regenerate.
2048
2049Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2050
2051 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2052 signed8, unsigned8 et.al. types.
2053
2054 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2055 hosts when selecting subreg.
2056
2057Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2058
2059 * interp.c (sim_engine_run): Reset the ZERO register to zero
2060 regardless of FEATURE_WARN_ZERO.
2061 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2062
2063Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2064
2065 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2066 (SignalException): For BreakPoints ignore any mode bits and just
2067 save the PC.
2068 (SignalException): Always set the CAUSE register.
2069
2070Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071
2072 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2073 exception has been taken.
2074
2075 * interp.c: Implement the ERET and mt/f sr instructions.
2076
2077Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * interp.c (SignalException): Don't bother restarting an
2080 interrupt.
2081
2082Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2083
2084 * interp.c (SignalException): Really take an interrupt.
2085 (interrupt_event): Only deliver interrupts when enabled.
2086
2087Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2088
2089 * interp.c (sim_info): Only print info when verbose.
2090 (sim_info) Use sim_io_printf for output.
2091
2092Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093
2094 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2095 mips architectures.
2096
2097Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098
2099 * interp.c (sim_do_command): Check for common commands if a
2100 simulator specific command fails.
2101
2102Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2103
2104 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2105 and simBE when DEBUG is defined.
2106
2107Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * interp.c (interrupt_event): New function. Pass exception event
2110 onto exception handler.
2111
2112 * configure.in: Check for stdlib.h.
2113 * configure: Regenerate.
2114
2115 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2116 variable declaration.
2117 (build_instruction): Initialize memval1.
2118 (build_instruction): Add UNUSED attribute to byte, bigend,
2119 reverse.
2120 (build_operands): Ditto.
2121
2122 * interp.c: Fix GCC warnings.
2123 (sim_get_quit_code): Delete.
2124
2125 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2126 * Makefile.in: Ditto.
2127 * configure: Re-generate.
2128
2129 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2130
2131Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * interp.c (mips_option_handler): New function parse argumes using
2134 sim-options.
2135 (myname): Replace with STATE_MY_NAME.
2136 (sim_open): Delete check for host endianness - performed by
2137 sim_config.
2138 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2139 (sim_open): Move much of the initialization from here.
2140 (sim_load): To here. After the image has been loaded and
2141 endianness set.
2142 (sim_open): Move ColdReset from here.
2143 (sim_create_inferior): To here.
2144 (sim_open): Make FP check less dependant on host endianness.
2145
2146 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2147 run.
2148 * interp.c (sim_set_callbacks): Delete.
2149
2150 * interp.c (membank, membank_base, membank_size): Replace with
2151 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2152 (sim_open): Remove call to callback->init. gdb/run do this.
2153
2154 * interp.c: Update
2155
2156 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2157
2158 * interp.c (big_endian_p): Delete, replaced by
2159 current_target_byte_order.
2160
2161Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * interp.c (host_read_long, host_read_word, host_swap_word,
2164 host_swap_long): Delete. Using common sim-endian.
2165 (sim_fetch_register, sim_store_register): Use H2T.
2166 (pipeline_ticks): Delete. Handled by sim-events.
2167 (sim_info): Update.
2168 (sim_engine_run): Update.
2169
2170Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2171
2172 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2173 reason from here.
2174 (SignalException): To here. Signal using sim_engine_halt.
2175 (sim_stop_reason): Delete, moved to common.
2176
2177Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2178
2179 * interp.c (sim_open): Add callback argument.
2180 (sim_set_callbacks): Delete SIM_DESC argument.
2181 (sim_size): Ditto.
2182
2183Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * Makefile.in (SIM_OBJS): Add common modules.
2186
2187 * interp.c (sim_set_callbacks): Also set SD callback.
2188 (set_endianness, xfer_*, swap_*): Delete.
2189 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2190 Change to functions using sim-endian macros.
2191 (control_c, sim_stop): Delete, use common version.
2192 (simulate): Convert into.
2193 (sim_engine_run): This function.
2194 (sim_resume): Delete.
2195
2196 * interp.c (simulation): New variable - the simulator object.
2197 (sim_kind): Delete global - merged into simulation.
2198 (sim_load): Cleanup. Move PC assignment from here.
2199 (sim_create_inferior): To here.
2200
2201 * sim-main.h: New file.
2202 * interp.c (sim-main.h): Include.
2203
2204Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2205
2206 * configure: Regenerated to track ../common/aclocal.m4 changes.
2207
2208Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2209
2210 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2211
2212Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2213
2214 * gencode.c (build_instruction): DIV instructions: check
2215 for division by zero and integer overflow before using
2216 host's division operation.
2217
2218Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2219
2220 * Makefile.in (SIM_OBJS): Add sim-load.o.
2221 * interp.c: #include bfd.h.
2222 (target_byte_order): Delete.
2223 (sim_kind, myname, big_endian_p): New static locals.
2224 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2225 after argument parsing. Recognize -E arg, set endianness accordingly.
2226 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2227 load file into simulator. Set PC from bfd.
2228 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2229 (set_endianness): Use big_endian_p instead of target_byte_order.
2230
2231Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2232
2233 * interp.c (sim_size): Delete prototype - conflicts with
2234 definition in remote-sim.h. Correct definition.
2235
2236Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2237
2238 * configure: Regenerated to track ../common/aclocal.m4 changes.
2239 * config.in: Ditto.
2240
2241Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2242
2243 * interp.c (sim_open): New arg `kind'.
2244
2245 * configure: Regenerated to track ../common/aclocal.m4 changes.
2246
2247Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2248
2249 * configure: Regenerated to track ../common/aclocal.m4 changes.
2250
2251Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2252
2253 * interp.c (sim_open): Set optind to 0 before calling getopt.
2254
2255Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2256
2257 * configure: Regenerated to track ../common/aclocal.m4 changes.
2258
2259Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2260
2261 * interp.c : Replace uses of pr_addr with pr_uword64
2262 where the bit length is always 64 independent of SIM_ADDR.
2263 (pr_uword64) : added.
2264
2265Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2266
2267 * configure: Re-generate.
2268
2269Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2270
2271 * configure: Regenerate to track ../common/aclocal.m4 changes.
2272
2273Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2274
2275 * interp.c (sim_open): New SIM_DESC result. Argument is now
2276 in argv form.
2277 (other sim_*): New SIM_DESC argument.
2278
2279Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2280
2281 * interp.c: Fix printing of addresses for non-64-bit targets.
2282 (pr_addr): Add function to print address based on size.
2283
2284Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2285
2286 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2287
2288Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2289
2290 * gencode.c (build_mips16_operands): Correct computation of base
2291 address for extended PC relative instruction.
2292
2293Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2294
2295 * interp.c (mips16_entry): Add support for floating point cases.
2296 (SignalException): Pass floating point cases to mips16_entry.
2297 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2298 registers.
2299 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2300 or fmt_word.
2301 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2302 and then set the state to fmt_uninterpreted.
2303 (COP_SW): Temporarily set the state to fmt_word while calling
2304 ValueFPR.
2305
2306Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2307
2308 * gencode.c (build_instruction): The high order may be set in the
2309 comparison flags at any ISA level, not just ISA 4.
2310
2311Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2312
2313 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2314 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2315 * configure.in: sinclude ../common/aclocal.m4.
2316 * configure: Regenerated.
2317
2318Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2319
2320 * configure: Rebuild after change to aclocal.m4.
2321
2322Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2323
2324 * configure configure.in Makefile.in: Update to new configure
2325 scheme which is more compatible with WinGDB builds.
2326 * configure.in: Improve comment on how to run autoconf.
2327 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2328 * Makefile.in: Use autoconf substitution to install common
2329 makefile fragment.
2330
2331Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2332
2333 * gencode.c (build_instruction): Use BigEndianCPU instead of
2334 ByteSwapMem.
2335
2336Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2337
2338 * interp.c (sim_monitor): Make output to stdout visible in
2339 wingdb's I/O log window.
2340
2341Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2342
2343 * support.h: Undo previous change to SIGTRAP
2344 and SIGQUIT values.
2345
2346Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2347
2348 * interp.c (store_word, load_word): New static functions.
2349 (mips16_entry): New static function.
2350 (SignalException): Look for mips16 entry and exit instructions.
2351 (simulate): Use the correct index when setting fpr_state after
2352 doing a pending move.
2353
2354Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2355
2356 * interp.c: Fix byte-swapping code throughout to work on
2357 both little- and big-endian hosts.
2358
2359Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2360
2361 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2362 with gdb/config/i386/xm-windows.h.
2363
2364Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2365
2366 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2367 that messes up arithmetic shifts.
2368
2369Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2370
2371 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2372 SIGTRAP and SIGQUIT for _WIN32.
2373
2374Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2375
2376 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2377 force a 64 bit multiplication.
2378 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2379 destination register is 0, since that is the default mips16 nop
2380 instruction.
2381
2382Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2383
2384 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2385 (build_endian_shift): Don't check proc64.
2386 (build_instruction): Always set memval to uword64. Cast op2 to
2387 uword64 when shifting it left in memory instructions. Always use
2388 the same code for stores--don't special case proc64.
2389
2390 * gencode.c (build_mips16_operands): Fix base PC value for PC
2391 relative operands.
2392 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2393 jal instruction.
2394 * interp.c (simJALDELAYSLOT): Define.
2395 (JALDELAYSLOT): Define.
2396 (INDELAYSLOT, INJALDELAYSLOT): Define.
2397 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2398
2399Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2400
2401 * interp.c (sim_open): add flush_cache as a PMON routine
2402 (sim_monitor): handle flush_cache by ignoring it
2403
2404Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2405
2406 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2407 BigEndianMem.
2408 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2409 (BigEndianMem): Rename to ByteSwapMem and change sense.
2410 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2411 BigEndianMem references to !ByteSwapMem.
2412 (set_endianness): New function, with prototype.
2413 (sim_open): Call set_endianness.
2414 (sim_info): Use simBE instead of BigEndianMem.
2415 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2416 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2417 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2418 ifdefs, keeping the prototype declaration.
2419 (swap_word): Rewrite correctly.
2420 (ColdReset): Delete references to CONFIG. Delete endianness related
2421 code; moved to set_endianness.
2422
2423Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2424
2425 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2426 * interp.c (CHECKHILO): Define away.
2427 (simSIGINT): New macro.
2428 (membank_size): Increase from 1MB to 2MB.
2429 (control_c): New function.
2430 (sim_resume): Rename parameter signal to signal_number. Add local
2431 variable prev. Call signal before and after simulate.
2432 (sim_stop_reason): Add simSIGINT support.
2433 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2434 functions always.
2435 (sim_warning): Delete call to SignalException. Do call printf_filtered
2436 if logfh is NULL.
2437 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2438 a call to sim_warning.
2439
2440Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2441
2442 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2443 16 bit instructions.
2444
2445Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2446
2447 Add support for mips16 (16 bit MIPS implementation):
2448 * gencode.c (inst_type): Add mips16 instruction encoding types.
2449 (GETDATASIZEINSN): Define.
2450 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2451 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2452 mtlo.
2453 (MIPS16_DECODE): New table, for mips16 instructions.
2454 (bitmap_val): New static function.
2455 (struct mips16_op): Define.
2456 (mips16_op_table): New table, for mips16 operands.
2457 (build_mips16_operands): New static function.
2458 (process_instructions): If PC is odd, decode a mips16
2459 instruction. Break out instruction handling into new
2460 build_instruction function.
2461 (build_instruction): New static function, broken out of
2462 process_instructions. Check modifiers rather than flags for SHIFT
2463 bit count and m[ft]{hi,lo} direction.
2464 (usage): Pass program name to fprintf.
2465 (main): Remove unused variable this_option_optind. Change
2466 ``*loptarg++'' to ``loptarg++''.
2467 (my_strtoul): Parenthesize && within ||.
2468 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2469 (simulate): If PC is odd, fetch a 16 bit instruction, and
2470 increment PC by 2 rather than 4.
2471 * configure.in: Add case for mips16*-*-*.
2472 * configure: Rebuild.
2473
2474Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2475
2476 * interp.c: Allow -t to enable tracing in standalone simulator.
2477 Fix garbage output in trace file and error messages.
2478
2479Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2480
2481 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2482 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2483 * configure.in: Simplify using macros in ../common/aclocal.m4.
2484 * configure: Regenerated.
2485 * tconfig.in: New file.
2486
2487Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2488
2489 * interp.c: Fix bugs in 64-bit port.
2490 Use ansi function declarations for msvc compiler.
2491 Initialize and test file pointer in trace code.
2492 Prevent duplicate definition of LAST_EMED_REGNUM.
2493
2494Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2495
2496 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2497
2498Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2499
2500 * interp.c (SignalException): Check for explicit terminating
2501 breakpoint value.
2502 * gencode.c: Pass instruction value through SignalException()
2503 calls for Trap, Breakpoint and Syscall.
2504
2505Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2506
2507 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2508 only used on those hosts that provide it.
2509 * configure.in: Add sqrt() to list of functions to be checked for.
2510 * config.in: Re-generated.
2511 * configure: Re-generated.
2512
2513Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2514
2515 * gencode.c (process_instructions): Call build_endian_shift when
2516 expanding STORE RIGHT, to fix swr.
2517 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2518 clear the high bits.
2519 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2520 Fix float to int conversions to produce signed values.
2521
2522Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2523
2524 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2525 (process_instructions): Correct handling of nor instruction.
2526 Correct shift count for 32 bit shift instructions. Correct sign
2527 extension for arithmetic shifts to not shift the number of bits in
2528 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2529 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2530 Fix madd.
2531 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2532 It's OK to have a mult follow a mult. What's not OK is to have a
2533 mult follow an mfhi.
2534 (Convert): Comment out incorrect rounding code.
2535
2536Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2537
2538 * interp.c (sim_monitor): Improved monitor printf
2539 simulation. Tidied up simulator warnings, and added "--log" option
2540 for directing warning message output.
2541 * gencode.c: Use sim_warning() rather than WARNING macro.
2542
2543Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2544
2545 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2546 getopt1.o, rather than on gencode.c. Link objects together.
2547 Don't link against -liberty.
2548 (gencode.o, getopt.o, getopt1.o): New targets.
2549 * gencode.c: Include <ctype.h> and "ansidecl.h".
2550 (AND): Undefine after including "ansidecl.h".
2551 (ULONG_MAX): Define if not defined.
2552 (OP_*): Don't define macros; now defined in opcode/mips.h.
2553 (main): Call my_strtoul rather than strtoul.
2554 (my_strtoul): New static function.
2555
2556Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2557
2558 * gencode.c (process_instructions): Generate word64 and uword64
2559 instead of `long long' and `unsigned long long' data types.
2560 * interp.c: #include sysdep.h to get signals, and define default
2561 for SIGBUS.
2562 * (Convert): Work around for Visual-C++ compiler bug with type
2563 conversion.
2564 * support.h: Make things compile under Visual-C++ by using
2565 __int64 instead of `long long'. Change many refs to long long
2566 into word64/uword64 typedefs.
2567
2568Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2569
2570 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2571 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2572 (docdir): Removed.
2573 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2574 (AC_PROG_INSTALL): Added.
2575 (AC_PROG_CC): Moved to before configure.host call.
2576 * configure: Rebuilt.
2577
2578Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2579
2580 * configure.in: Define @SIMCONF@ depending on mips target.
2581 * configure: Rebuild.
2582 * Makefile.in (run): Add @SIMCONF@ to control simulator
2583 construction.
2584 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2585 * interp.c: Remove some debugging, provide more detailed error
2586 messages, update memory accesses to use LOADDRMASK.
2587
2588Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2589
2590 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2591 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2592 stamp-h.
2593 * configure: Rebuild.
2594 * config.in: New file, generated by autoheader.
2595 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2596 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2597 HAVE_ANINT and HAVE_AINT, as appropriate.
2598 * Makefile.in (run): Use @LIBS@ rather than -lm.
2599 (interp.o): Depend upon config.h.
2600 (Makefile): Just rebuild Makefile.
2601 (clean): Remove stamp-h.
2602 (mostlyclean): Make the same as clean, not as distclean.
2603 (config.h, stamp-h): New targets.
2604
2605Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2606
2607 * interp.c (ColdReset): Fix boolean test. Make all simulator
2608 globals static.
2609
2610Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2611
2612 * interp.c (xfer_direct_word, xfer_direct_long,
2613 swap_direct_word, swap_direct_long, xfer_big_word,
2614 xfer_big_long, xfer_little_word, xfer_little_long,
2615 swap_word,swap_long): Added.
2616 * interp.c (ColdReset): Provide function indirection to
2617 host<->simulated_target transfer routines.
2618 * interp.c (sim_store_register, sim_fetch_register): Updated to
2619 make use of indirected transfer routines.
2620
2621Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2622
2623 * gencode.c (process_instructions): Ensure FP ABS instruction
2624 recognised.
2625 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2626 system call support.
2627
2628Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2629
2630 * interp.c (sim_do_command): Complain if callback structure not
2631 initialised.
2632
2633Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2634
2635 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2636 support for Sun hosts.
2637 * Makefile.in (gencode): Ensure the host compiler and libraries
2638 used for cross-hosted build.
2639
2640Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2641
2642 * interp.c, gencode.c: Some more (TODO) tidying.
2643
2644Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2645
2646 * gencode.c, interp.c: Replaced explicit long long references with
2647 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2648 * support.h (SET64LO, SET64HI): Macros added.
2649
2650Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2651
2652 * configure: Regenerate with autoconf 2.7.
2653
2654Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2655
2656 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2657 * support.h: Remove superfluous "1" from #if.
2658 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2659
2660Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2661
2662 * interp.c (StoreFPR): Control UndefinedResult() call on
2663 WARN_RESULT manifest.
2664
2665Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2666
2667 * gencode.c: Tidied instruction decoding, and added FP instruction
2668 support.
2669
2670 * interp.c: Added dineroIII, and BSD profiling support. Also
2671 run-time FP handling.
2672
2673Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2674
2675 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2676 gencode.c, interp.c, support.h: created.
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