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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
9 | */ |
10 | ||
11 | #include <common.h> | |
12 | #include <malloc.h> | |
cf92e05c | 13 | #include <memalign.h> |
0b23fb36 | 14 | #include <net.h> |
84f64c8b | 15 | #include <netdev.h> |
0b23fb36 IY |
16 | #include <miiphy.h> |
17 | #include "fec_mxc.h" | |
18 | ||
19 | #include <asm/arch/clock.h> | |
20 | #include <asm/arch/imx-regs.h> | |
fbecbaa1 | 21 | #include <asm/imx-common/sys_proto.h> |
0b23fb36 | 22 | #include <asm/io.h> |
1221ce45 | 23 | #include <linux/errno.h> |
e2a66e60 | 24 | #include <linux/compiler.h> |
0b23fb36 IY |
25 | |
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
bc1ce150 MV |
28 | /* |
29 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
30 | * the code in the tightloops this timeout is used in adds some overhead. | |
31 | */ | |
32 | #define FEC_XFER_TIMEOUT 5000 | |
33 | ||
db5b7f56 FE |
34 | /* |
35 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
36 | * 64-byte alignment in the DMA RX FEC buffer. | |
37 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
38 | * satisfies the alignment on other SoCs (32-bytes) | |
39 | */ | |
40 | #define FEC_DMA_RX_MINALIGN 64 | |
41 | ||
0b23fb36 IY |
42 | #ifndef CONFIG_MII |
43 | #error "CONFIG_MII has to be defined!" | |
44 | #endif | |
45 | ||
5c1ad3e6 EN |
46 | #ifndef CONFIG_FEC_XCV_TYPE |
47 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
48 | #endif |
49 | ||
be7e87e2 MV |
50 | /* |
51 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
52 | * sending and after receiving. | |
53 | */ | |
5c1ad3e6 EN |
54 | #ifdef CONFIG_MX28 |
55 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
56 | #endif | |
57 | ||
58 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
59 | ||
60 | /* Check various alignment issues at compile time */ | |
61 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
62 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
63 | #endif | |
64 | ||
65 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
66 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
67 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
68 | #endif |
69 | ||
0b23fb36 IY |
70 | #undef DEBUG |
71 | ||
5c1ad3e6 | 72 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
73 | static void swap_packet(uint32_t *packet, int length) |
74 | { | |
75 | int i; | |
76 | ||
77 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
78 | packet[i] = __swab32(packet[i]); | |
79 | } | |
80 | #endif | |
81 | ||
0b23fb36 IY |
82 | /* |
83 | * MII-interface related functions | |
84 | */ | |
13947f43 TK |
85 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
86 | uint8_t regAddr) | |
0b23fb36 | 87 | { |
0b23fb36 IY |
88 | uint32_t reg; /* convenient holder for the PHY register */ |
89 | uint32_t phy; /* convenient holder for the PHY */ | |
90 | uint32_t start; | |
13947f43 | 91 | int val; |
0b23fb36 IY |
92 | |
93 | /* | |
94 | * reading from any PHY's register is done by properly | |
95 | * programming the FEC's MII data register. | |
96 | */ | |
d133b881 | 97 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
98 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
99 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
100 | ||
101 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 102 | phy | reg, ð->mii_data); |
0b23fb36 IY |
103 | |
104 | /* | |
105 | * wait for the related interrupt | |
106 | */ | |
a60d1e5b | 107 | start = get_timer(0); |
d133b881 | 108 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
109 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
110 | printf("Read MDIO failed...\n"); | |
111 | return -1; | |
112 | } | |
113 | } | |
114 | ||
115 | /* | |
116 | * clear mii interrupt bit | |
117 | */ | |
d133b881 | 118 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
119 | |
120 | /* | |
121 | * it's now safe to read the PHY's register | |
122 | */ | |
13947f43 TK |
123 | val = (unsigned short)readl(ð->mii_data); |
124 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
125 | regAddr, val); | |
126 | return val; | |
0b23fb36 IY |
127 | } |
128 | ||
575c5cc0 | 129 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
130 | { |
131 | /* | |
132 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
133 | * and do not drop the Preamble. | |
843a3e58 MR |
134 | * |
135 | * The i.MX28 and i.MX6 types have another field in the MSCR (aka | |
136 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
137 | * versions are RAZ there, so just ignore the difference and write the | |
138 | * register always. | |
139 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
140 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
141 | * output. | |
142 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
143 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
144 | * holdtime cannot result in a value greater than 3. | |
4294b248 | 145 | */ |
843a3e58 MR |
146 | u32 pclk = imx_get_fecclk(); |
147 | u32 speed = DIV_ROUND_UP(pclk, 5000000); | |
148 | u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; | |
6ba45cc0 MN |
149 | #ifdef FEC_QUIRK_ENET_MAC |
150 | speed--; | |
151 | #endif | |
843a3e58 | 152 | writel(speed << 1 | hold << 8, ð->mii_speed); |
575c5cc0 | 153 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 154 | } |
0b23fb36 | 155 | |
13947f43 TK |
156 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
157 | uint8_t regAddr, uint16_t data) | |
158 | { | |
0b23fb36 IY |
159 | uint32_t reg; /* convenient holder for the PHY register */ |
160 | uint32_t phy; /* convenient holder for the PHY */ | |
161 | uint32_t start; | |
162 | ||
163 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
164 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
165 | ||
166 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 167 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
168 | |
169 | /* | |
170 | * wait for the MII interrupt | |
171 | */ | |
a60d1e5b | 172 | start = get_timer(0); |
d133b881 | 173 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
174 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
175 | printf("Write MDIO failed...\n"); | |
176 | return -1; | |
177 | } | |
178 | } | |
179 | ||
180 | /* | |
181 | * clear MII interrupt bit | |
182 | */ | |
d133b881 | 183 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 184 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
185 | regAddr, data); |
186 | ||
187 | return 0; | |
188 | } | |
189 | ||
84f64c8b JH |
190 | static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, |
191 | int regAddr) | |
13947f43 TK |
192 | { |
193 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
194 | } | |
195 | ||
84f64c8b JH |
196 | static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, |
197 | int regAddr, u16 data) | |
13947f43 TK |
198 | { |
199 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
200 | } | |
201 | ||
202 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
203 | static int miiphy_restart_aneg(struct eth_device *dev) |
204 | { | |
b774fe9d SB |
205 | int ret = 0; |
206 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 207 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 208 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 209 | |
0b23fb36 IY |
210 | /* |
211 | * Wake up from sleep if necessary | |
212 | * Reset PHY, then delay 300ns | |
213 | */ | |
cb17b92d | 214 | #ifdef CONFIG_MX27 |
13947f43 | 215 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 216 | #endif |
13947f43 | 217 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
218 | udelay(1000); |
219 | ||
220 | /* | |
221 | * Set the auto-negotiation advertisement register bits | |
222 | */ | |
13947f43 | 223 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
224 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
225 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 226 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 227 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
228 | |
229 | if (fec->mii_postcall) | |
230 | ret = fec->mii_postcall(fec->phy_id); | |
231 | ||
b774fe9d | 232 | #endif |
2e5f4421 | 233 | return ret; |
0b23fb36 IY |
234 | } |
235 | ||
0750701a | 236 | #ifndef CONFIG_FEC_FIXED_SPEED |
0b23fb36 IY |
237 | static int miiphy_wait_aneg(struct eth_device *dev) |
238 | { | |
239 | uint32_t start; | |
13947f43 | 240 | int status; |
9e27e9dc | 241 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 242 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
243 | |
244 | /* | |
245 | * Wait for AN completion | |
246 | */ | |
a60d1e5b | 247 | start = get_timer(0); |
0b23fb36 IY |
248 | do { |
249 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
250 | printf("%s: Autonegotiation timeout\n", dev->name); | |
251 | return -1; | |
252 | } | |
253 | ||
13947f43 TK |
254 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
255 | if (status < 0) { | |
256 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
257 | dev->name, status); |
258 | return -1; | |
259 | } | |
8ef583a0 | 260 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
261 | |
262 | return 0; | |
263 | } | |
0750701a | 264 | #endif /* CONFIG_FEC_FIXED_SPEED */ |
13947f43 TK |
265 | #endif |
266 | ||
0b23fb36 IY |
267 | static int fec_rx_task_enable(struct fec_priv *fec) |
268 | { | |
c0b5a3bb | 269 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
270 | return 0; |
271 | } | |
272 | ||
273 | static int fec_rx_task_disable(struct fec_priv *fec) | |
274 | { | |
275 | return 0; | |
276 | } | |
277 | ||
278 | static int fec_tx_task_enable(struct fec_priv *fec) | |
279 | { | |
c0b5a3bb | 280 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
281 | return 0; |
282 | } | |
283 | ||
284 | static int fec_tx_task_disable(struct fec_priv *fec) | |
285 | { | |
286 | return 0; | |
287 | } | |
288 | ||
289 | /** | |
290 | * Initialize receive task's buffer descriptors | |
291 | * @param[in] fec all we know about the device yet | |
292 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 293 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
294 | * @return 0 on success |
295 | * | |
79e5f27b | 296 | * Init all RX descriptors to default values. |
0b23fb36 | 297 | */ |
79e5f27b | 298 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 299 | { |
5c1ad3e6 | 300 | uint32_t size; |
79e5f27b | 301 | uint8_t *data; |
5c1ad3e6 EN |
302 | int i; |
303 | ||
0b23fb36 | 304 | /* |
79e5f27b MV |
305 | * Reload the RX descriptors with default values and wipe |
306 | * the RX buffers. | |
0b23fb36 | 307 | */ |
5c1ad3e6 EN |
308 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
309 | for (i = 0; i < count; i++) { | |
79e5f27b MV |
310 | data = (uint8_t *)fec->rbd_base[i].data_pointer; |
311 | memset(data, 0, dsize); | |
312 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
313 | ||
314 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
315 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
316 | } |
317 | ||
318 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 319 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
320 | fec->rbd_index = 0; |
321 | ||
79e5f27b MV |
322 | flush_dcache_range((unsigned)fec->rbd_base, |
323 | (unsigned)fec->rbd_base + size); | |
0b23fb36 IY |
324 | } |
325 | ||
326 | /** | |
327 | * Initialize transmit task's buffer descriptors | |
328 | * @param[in] fec all we know about the device yet | |
329 | * | |
330 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
331 | * Note: There is a race condition in the hardware. When only one BD is in | |
332 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
333 | * This bit in combination with the READY bit results into double transmit | |
334 | * of each data buffer. It seems the state machine checks READY earlier then | |
335 | * resetting it after the first transfer. | |
336 | * Using two BDs solves this issue. | |
337 | */ | |
338 | static void fec_tbd_init(struct fec_priv *fec) | |
339 | { | |
5c1ad3e6 EN |
340 | unsigned addr = (unsigned)fec->tbd_base; |
341 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
342 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
343 | |
344 | memset(fec->tbd_base, 0, size); | |
345 | fec->tbd_base[0].status = 0; | |
346 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 347 | fec->tbd_index = 0; |
79e5f27b | 348 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
349 | } |
350 | ||
351 | /** | |
352 | * Mark the given read buffer descriptor as free | |
353 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
354 | * @param[in] pRbd buffer descriptor to mark free again | |
355 | */ | |
356 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
357 | { | |
5c1ad3e6 | 358 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 359 | if (last) |
5c1ad3e6 EN |
360 | flags |= FEC_RBD_WRAP; |
361 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
362 | writew(0, &pRbd->data_length); |
363 | } | |
364 | ||
be252b65 FE |
365 | static int fec_get_hwaddr(struct eth_device *dev, int dev_id, |
366 | unsigned char *mac) | |
0b23fb36 | 367 | { |
be252b65 | 368 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 369 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
370 | } |
371 | ||
4294b248 | 372 | static int fec_set_hwaddr(struct eth_device *dev) |
0b23fb36 | 373 | { |
4294b248 | 374 | uchar *mac = dev->enetaddr; |
0b23fb36 IY |
375 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
376 | ||
377 | writel(0, &fec->eth->iaddr1); | |
378 | writel(0, &fec->eth->iaddr2); | |
379 | writel(0, &fec->eth->gaddr1); | |
380 | writel(0, &fec->eth->gaddr2); | |
381 | ||
382 | /* | |
383 | * Set physical address | |
384 | */ | |
385 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
386 | &fec->eth->paddr1); | |
387 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
a5990b26 MV |
392 | /* |
393 | * Do initial configuration of the FEC registers | |
394 | */ | |
395 | static void fec_reg_setup(struct fec_priv *fec) | |
396 | { | |
397 | uint32_t rcntrl; | |
398 | ||
399 | /* | |
400 | * Set interrupt mask register | |
401 | */ | |
402 | writel(0x00000000, &fec->eth->imask); | |
403 | ||
404 | /* | |
405 | * Clear FEC-Lite interrupt event register(IEVENT) | |
406 | */ | |
407 | writel(0xffffffff, &fec->eth->ievent); | |
408 | ||
409 | ||
410 | /* | |
411 | * Set FEC-Lite receive control register(R_CNTRL): | |
412 | */ | |
413 | ||
414 | /* Start with frame length = 1518, common for all modes. */ | |
415 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 416 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
417 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
418 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
419 | rcntrl |= FEC_RCNTRL_RGMII; |
420 | else if (fec->xcv_type == RMII) | |
421 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
422 | |
423 | writel(rcntrl, &fec->eth->r_cntrl); | |
424 | } | |
425 | ||
0b23fb36 IY |
426 | /** |
427 | * Start the FEC engine | |
428 | * @param[in] dev Our device to handle | |
429 | */ | |
430 | static int fec_open(struct eth_device *edev) | |
431 | { | |
432 | struct fec_priv *fec = (struct fec_priv *)edev->priv; | |
28774cba | 433 | int speed; |
5c1ad3e6 EN |
434 | uint32_t addr, size; |
435 | int i; | |
0b23fb36 IY |
436 | |
437 | debug("fec_open: fec_open(dev)\n"); | |
438 | /* full-duplex, heartbeat disabled */ | |
439 | writel(1 << 2, &fec->eth->x_cntrl); | |
440 | fec->rbd_index = 0; | |
441 | ||
5c1ad3e6 EN |
442 | /* Invalidate all descriptors */ |
443 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
444 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
445 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
446 | ||
447 | /* Flush the descriptors into RAM */ | |
448 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
449 | ARCH_DMA_MINALIGN); | |
450 | addr = (uint32_t)fec->rbd_base; | |
451 | flush_dcache_range(addr, addr + size); | |
452 | ||
28774cba | 453 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
454 | /* Enable ENET HW endian SWAP */ |
455 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
456 | &fec->eth->ecntrl); | |
457 | /* Enable ENET store and forward mode */ | |
458 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
459 | &fec->eth->x_wmrk); | |
460 | #endif | |
0b23fb36 IY |
461 | /* |
462 | * Enable FEC-Lite controller | |
463 | */ | |
cb17b92d JR |
464 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
465 | &fec->eth->ecntrl); | |
7df51fd8 | 466 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 JR |
467 | udelay(100); |
468 | /* | |
469 | * setup the MII gasket for RMII mode | |
470 | */ | |
471 | ||
472 | /* disable the gasket */ | |
473 | writew(0, &fec->eth->miigsk_enr); | |
474 | ||
475 | /* wait for the gasket to be disabled */ | |
476 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
477 | udelay(2); | |
478 | ||
479 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
480 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
481 | ||
482 | /* re-enable the gasket */ | |
483 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
484 | ||
485 | /* wait until MII gasket is ready */ | |
486 | int max_loops = 10; | |
487 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
488 | if (--max_loops <= 0) { | |
489 | printf("WAIT for MII Gasket ready timed out\n"); | |
490 | break; | |
491 | } | |
492 | } | |
493 | #endif | |
0b23fb36 | 494 | |
13947f43 | 495 | #ifdef CONFIG_PHYLIB |
4dc27eed | 496 | { |
13947f43 | 497 | /* Start up the PHY */ |
11af8d65 TT |
498 | int ret = phy_startup(fec->phydev); |
499 | ||
500 | if (ret) { | |
501 | printf("Could not initialize PHY %s\n", | |
502 | fec->phydev->dev->name); | |
503 | return ret; | |
504 | } | |
13947f43 | 505 | speed = fec->phydev->speed; |
13947f43 | 506 | } |
0750701a HS |
507 | #elif CONFIG_FEC_FIXED_SPEED |
508 | speed = CONFIG_FEC_FIXED_SPEED; | |
13947f43 | 509 | #else |
0b23fb36 | 510 | miiphy_wait_aneg(edev); |
28774cba | 511 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 512 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 513 | #endif |
0b23fb36 | 514 | |
28774cba TK |
515 | #ifdef FEC_QUIRK_ENET_MAC |
516 | { | |
517 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 518 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
519 | if (speed == _1000BASET) |
520 | ecr |= FEC_ECNTRL_SPEED; | |
521 | else if (speed != _100BASET) | |
522 | rcr |= FEC_RCNTRL_RMII_10T; | |
523 | writel(ecr, &fec->eth->ecntrl); | |
524 | writel(rcr, &fec->eth->r_cntrl); | |
525 | } | |
526 | #endif | |
527 | debug("%s:Speed=%i\n", __func__, speed); | |
528 | ||
0b23fb36 IY |
529 | /* |
530 | * Enable SmartDMA receive task | |
531 | */ | |
532 | fec_rx_task_enable(fec); | |
533 | ||
534 | udelay(100000); | |
535 | return 0; | |
536 | } | |
537 | ||
538 | static int fec_init(struct eth_device *dev, bd_t* bd) | |
539 | { | |
0b23fb36 | 540 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
9e27e9dc | 541 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
79e5f27b | 542 | int i; |
0b23fb36 | 543 | |
e9319f11 JR |
544 | /* Initialize MAC address */ |
545 | fec_set_hwaddr(dev); | |
546 | ||
0b23fb36 | 547 | /* |
79e5f27b | 548 | * Setup transmit descriptors, there are two in total. |
0b23fb36 | 549 | */ |
79e5f27b | 550 | fec_tbd_init(fec); |
0b23fb36 | 551 | |
79e5f27b MV |
552 | /* Setup receive descriptors. */ |
553 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 554 | |
a5990b26 | 555 | fec_reg_setup(fec); |
9eb3770b | 556 | |
f41471e6 | 557 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 558 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 559 | |
0b23fb36 IY |
560 | /* |
561 | * Set Opcode/Pause Duration Register | |
562 | */ | |
563 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
564 | writel(0x2, &fec->eth->x_wmrk); | |
565 | /* | |
566 | * Set multicast address filter | |
567 | */ | |
568 | writel(0x00000000, &fec->eth->gaddr1); | |
569 | writel(0x00000000, &fec->eth->gaddr2); | |
570 | ||
571 | ||
fbecbaa1 | 572 | /* Do not access reserved register for i.MX6UL */ |
87f99895 | 573 | if (!is_mx6ul()) { |
fbecbaa1 PF |
574 | /* clear MIB RAM */ |
575 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
576 | writel(0, i); | |
0b23fb36 | 577 | |
fbecbaa1 PF |
578 | /* FIFO receive start register */ |
579 | writel(0x520, &fec->eth->r_fstart); | |
580 | } | |
0b23fb36 IY |
581 | |
582 | /* size and address of each buffer */ | |
583 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
584 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
585 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
586 | ||
13947f43 | 587 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
588 | if (fec->xcv_type != SEVENWIRE) |
589 | miiphy_restart_aneg(dev); | |
13947f43 | 590 | #endif |
0b23fb36 IY |
591 | fec_open(dev); |
592 | return 0; | |
593 | } | |
594 | ||
595 | /** | |
596 | * Halt the FEC engine | |
597 | * @param[in] dev Our device to handle | |
598 | */ | |
599 | static void fec_halt(struct eth_device *dev) | |
600 | { | |
9e27e9dc | 601 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
0b23fb36 IY |
602 | int counter = 0xffff; |
603 | ||
604 | /* | |
605 | * issue graceful stop command to the FEC transmitter if necessary | |
606 | */ | |
cb17b92d | 607 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
608 | &fec->eth->x_cntrl); |
609 | ||
610 | debug("eth_halt: wait for stop regs\n"); | |
611 | /* | |
612 | * wait for graceful stop to register | |
613 | */ | |
614 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 615 | udelay(1); |
0b23fb36 IY |
616 | |
617 | /* | |
618 | * Disable SmartDMA tasks | |
619 | */ | |
620 | fec_tx_task_disable(fec); | |
621 | fec_rx_task_disable(fec); | |
622 | ||
623 | /* | |
624 | * Disable the Ethernet Controller | |
625 | * Note: this will also reset the BD index counter! | |
626 | */ | |
740d6ae5 JR |
627 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
628 | &fec->eth->ecntrl); | |
0b23fb36 IY |
629 | fec->rbd_index = 0; |
630 | fec->tbd_index = 0; | |
0b23fb36 IY |
631 | debug("eth_halt: done\n"); |
632 | } | |
633 | ||
634 | /** | |
635 | * Transmit one frame | |
636 | * @param[in] dev Our ethernet device to handle | |
637 | * @param[in] packet Pointer to the data to be transmitted | |
638 | * @param[in] length Data count in bytes | |
639 | * @return 0 on success | |
640 | */ | |
442dac4c | 641 | static int fec_send(struct eth_device *dev, void *packet, int length) |
0b23fb36 IY |
642 | { |
643 | unsigned int status; | |
efe24d2e | 644 | uint32_t size, end; |
5c1ad3e6 | 645 | uint32_t addr; |
bc1ce150 MV |
646 | int timeout = FEC_XFER_TIMEOUT; |
647 | int ret = 0; | |
0b23fb36 IY |
648 | |
649 | /* | |
650 | * This routine transmits one frame. This routine only accepts | |
651 | * 6-byte Ethernet addresses. | |
652 | */ | |
653 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
654 | ||
655 | /* | |
656 | * Check for valid length of data. | |
657 | */ | |
658 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 659 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
660 | return -1; |
661 | } | |
662 | ||
663 | /* | |
5c1ad3e6 EN |
664 | * Setup the transmit buffer. We are always using the first buffer for |
665 | * transmission, the second will be empty and only used to stop the DMA | |
666 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 667 | */ |
5c1ad3e6 | 668 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
669 | swap_packet((uint32_t *)packet, length); |
670 | #endif | |
5c1ad3e6 EN |
671 | |
672 | addr = (uint32_t)packet; | |
efe24d2e MV |
673 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
674 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
675 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 676 | |
0b23fb36 | 677 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
678 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
679 | ||
0b23fb36 IY |
680 | /* |
681 | * update BD's status now | |
682 | * This block: | |
683 | * - is always the last in a chain (means no chain) | |
684 | * - should transmitt the CRC | |
685 | * - might be the last BD in the list, so the address counter should | |
686 | * wrap (-> keep the WRAP flag) | |
687 | */ | |
688 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
689 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
690 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
691 | ||
5c1ad3e6 EN |
692 | /* |
693 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
694 | * After this code, the descriptors will be safely in RAM and we | |
695 | * can start DMA. | |
696 | */ | |
697 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
698 | addr = (uint32_t)fec->tbd_base; | |
699 | flush_dcache_range(addr, addr + size); | |
700 | ||
ab94cd49 MV |
701 | /* |
702 | * Below we read the DMA descriptor's last four bytes back from the | |
703 | * DRAM. This is important in order to make sure that all WRITE | |
704 | * operations on the bus that were triggered by previous cache FLUSH | |
705 | * have completed. | |
706 | * | |
707 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
708 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
709 | * for the bus structure of MX28. The scenario is as follows: | |
710 | * | |
711 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
712 | * to DRAM due to flush_dcache_range() | |
713 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
714 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
715 | * | |
716 | * Note that 2) does sometimes finish before 1) due to reordering of | |
717 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
718 | * DMA descriptor is fully written into DRAM. This results in occasional | |
719 | * corruption of the DMA descriptor. | |
720 | */ | |
721 | readl(addr + size - 4); | |
722 | ||
0b23fb36 IY |
723 | /* |
724 | * Enable SmartDMA transmit task | |
725 | */ | |
726 | fec_tx_task_enable(fec); | |
727 | ||
728 | /* | |
5c1ad3e6 EN |
729 | * Wait until frame is sent. On each turn of the wait cycle, we must |
730 | * invalidate data cache to see what's really in RAM. Also, we need | |
731 | * barrier here. | |
0b23fb36 | 732 | */ |
67449098 | 733 | while (--timeout) { |
c0b5a3bb | 734 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 735 | break; |
0b23fb36 | 736 | } |
5c1ad3e6 | 737 | |
f599288d | 738 | if (!timeout) { |
67449098 | 739 | ret = -EINVAL; |
f599288d FE |
740 | goto out; |
741 | } | |
742 | ||
743 | /* | |
744 | * The TDAR bit is cleared when the descriptors are all out from TX | |
745 | * but on mx6solox we noticed that the READY bit is still not cleared | |
746 | * right after TDAR. | |
747 | * These are two distinct signals, and in IC simulation, we found that | |
748 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
749 | * cleared. | |
750 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
751 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
752 | * version. | |
753 | * | |
754 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
755 | * which covers the mx6solox case and does not harm the other SoCs. | |
756 | */ | |
757 | timeout = FEC_XFER_TIMEOUT; | |
758 | while (--timeout) { | |
759 | invalidate_dcache_range(addr, addr + size); | |
760 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
761 | FEC_TBD_READY)) | |
762 | break; | |
763 | } | |
67449098 | 764 | |
f599288d | 765 | if (!timeout) |
67449098 MV |
766 | ret = -EINVAL; |
767 | ||
f599288d | 768 | out: |
67449098 | 769 | debug("fec_send: status 0x%x index %d ret %i\n", |
0b23fb36 | 770 | readw(&fec->tbd_base[fec->tbd_index].status), |
67449098 | 771 | fec->tbd_index, ret); |
0b23fb36 IY |
772 | /* for next transmission use the other buffer */ |
773 | if (fec->tbd_index) | |
774 | fec->tbd_index = 0; | |
775 | else | |
776 | fec->tbd_index = 1; | |
777 | ||
bc1ce150 | 778 | return ret; |
0b23fb36 IY |
779 | } |
780 | ||
781 | /** | |
782 | * Pull one frame from the card | |
783 | * @param[in] dev Our ethernet device to handle | |
784 | * @return Length of packet read | |
785 | */ | |
786 | static int fec_recv(struct eth_device *dev) | |
787 | { | |
788 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
789 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; | |
790 | unsigned long ievent; | |
791 | int frame_length, len = 0; | |
0b23fb36 | 792 | uint16_t bd_status; |
efe24d2e | 793 | uint32_t addr, size, end; |
5c1ad3e6 | 794 | int i; |
fd37f195 | 795 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
0b23fb36 IY |
796 | |
797 | /* | |
798 | * Check if any critical events have happened | |
799 | */ | |
800 | ievent = readl(&fec->eth->ievent); | |
801 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 802 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 IY |
803 | if (ievent & FEC_IEVENT_BABR) { |
804 | fec_halt(dev); | |
805 | fec_init(dev, fec->bd); | |
806 | printf("some error: 0x%08lx\n", ievent); | |
807 | return 0; | |
808 | } | |
809 | if (ievent & FEC_IEVENT_HBERR) { | |
810 | /* Heartbeat error */ | |
811 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
812 | &fec->eth->x_cntrl); | |
813 | } | |
814 | if (ievent & FEC_IEVENT_GRA) { | |
815 | /* Graceful stop complete */ | |
816 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
817 | fec_halt(dev); | |
818 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), | |
819 | &fec->eth->x_cntrl); | |
820 | fec_init(dev, fec->bd); | |
821 | } | |
822 | } | |
823 | ||
824 | /* | |
5c1ad3e6 EN |
825 | * Read the buffer status. Before the status can be read, the data cache |
826 | * must be invalidated, because the data in RAM might have been changed | |
827 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
828 | * no need to worry they'd overlap. | |
829 | * | |
830 | * WARNING: By invalidating the descriptor here, we also invalidate | |
831 | * the descriptors surrounding this one. Therefore we can NOT change the | |
832 | * contents of this descriptor nor the surrounding ones. The problem is | |
833 | * that in order to mark the descriptor as processed, we need to change | |
834 | * the descriptor. The solution is to mark the whole cache line when all | |
835 | * descriptors in the cache line are processed. | |
0b23fb36 | 836 | */ |
5c1ad3e6 EN |
837 | addr = (uint32_t)rbd; |
838 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
839 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
840 | invalidate_dcache_range(addr, addr + size); | |
841 | ||
0b23fb36 IY |
842 | bd_status = readw(&rbd->status); |
843 | debug("fec_recv: status 0x%x\n", bd_status); | |
844 | ||
845 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
846 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
847 | ((readw(&rbd->data_length) - 4) > 14)) { | |
848 | /* | |
849 | * Get buffer address and size | |
850 | */ | |
b189584b | 851 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 852 | frame_length = readw(&rbd->data_length) - 4; |
5c1ad3e6 EN |
853 | /* |
854 | * Invalidate data cache over the buffer | |
855 | */ | |
efe24d2e MV |
856 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
857 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
858 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 859 | |
0b23fb36 IY |
860 | /* |
861 | * Fill the buffer and pass it to upper layers | |
862 | */ | |
5c1ad3e6 | 863 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
b189584b | 864 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 865 | #endif |
b189584b | 866 | memcpy(buff, (char *)addr, frame_length); |
1fd92db8 | 867 | net_process_received_packet(buff, frame_length); |
0b23fb36 IY |
868 | len = frame_length; |
869 | } else { | |
870 | if (bd_status & FEC_RBD_ERR) | |
b189584b AA |
871 | printf("error frame: 0x%08x 0x%08x\n", |
872 | addr, bd_status); | |
0b23fb36 | 873 | } |
5c1ad3e6 | 874 | |
0b23fb36 | 875 | /* |
5c1ad3e6 EN |
876 | * Free the current buffer, restart the engine and move forward |
877 | * to the next buffer. Here we check if the whole cacheline of | |
878 | * descriptors was already processed and if so, we mark it free | |
879 | * as whole. | |
0b23fb36 | 880 | */ |
5c1ad3e6 EN |
881 | size = RXDESC_PER_CACHELINE - 1; |
882 | if ((fec->rbd_index & size) == size) { | |
883 | i = fec->rbd_index - size; | |
884 | addr = (uint32_t)&fec->rbd_base[i]; | |
885 | for (; i <= fec->rbd_index ; i++) { | |
886 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
887 | &fec->rbd_base[i]); | |
888 | } | |
889 | flush_dcache_range(addr, | |
890 | addr + ARCH_DMA_MINALIGN); | |
891 | } | |
892 | ||
0b23fb36 IY |
893 | fec_rx_task_enable(fec); |
894 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
895 | } | |
896 | debug("fec_recv: stop\n"); | |
897 | ||
898 | return len; | |
899 | } | |
900 | ||
ef8e3a3b TK |
901 | static void fec_set_dev_name(char *dest, int dev_id) |
902 | { | |
903 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
904 | } | |
905 | ||
79e5f27b MV |
906 | static int fec_alloc_descs(struct fec_priv *fec) |
907 | { | |
908 | unsigned int size; | |
909 | int i; | |
910 | uint8_t *data; | |
911 | ||
912 | /* Allocate TX descriptors. */ | |
913 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
914 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
915 | if (!fec->tbd_base) | |
916 | goto err_tx; | |
917 | ||
918 | /* Allocate RX descriptors. */ | |
919 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
920 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
921 | if (!fec->rbd_base) | |
922 | goto err_rx; | |
923 | ||
924 | memset(fec->rbd_base, 0, size); | |
925 | ||
926 | /* Allocate RX buffers. */ | |
927 | ||
928 | /* Maximum RX buffer size. */ | |
db5b7f56 | 929 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 930 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 931 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
932 | if (!data) { |
933 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
934 | goto err_ring; | |
935 | } | |
936 | ||
937 | memset(data, 0, size); | |
938 | ||
939 | fec->rbd_base[i].data_pointer = (uint32_t)data; | |
940 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
941 | fec->rbd_base[i].data_length = 0; | |
942 | /* Flush the buffer to memory. */ | |
943 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
944 | } | |
945 | ||
946 | /* Mark the last RBD to close the ring. */ | |
947 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
948 | ||
949 | fec->rbd_index = 0; | |
950 | fec->tbd_index = 0; | |
951 | ||
952 | return 0; | |
953 | ||
954 | err_ring: | |
955 | for (; i >= 0; i--) | |
956 | free((void *)fec->rbd_base[i].data_pointer); | |
957 | free(fec->rbd_base); | |
958 | err_rx: | |
959 | free(fec->tbd_base); | |
960 | err_tx: | |
961 | return -ENOMEM; | |
962 | } | |
963 | ||
964 | static void fec_free_descs(struct fec_priv *fec) | |
965 | { | |
966 | int i; | |
967 | ||
968 | for (i = 0; i < FEC_RBD_NUM; i++) | |
969 | free((void *)fec->rbd_base[i].data_pointer); | |
970 | free(fec->rbd_base); | |
971 | free(fec->tbd_base); | |
972 | } | |
973 | ||
fe428b90 TK |
974 | #ifdef CONFIG_PHYLIB |
975 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
976 | struct mii_dev *bus, struct phy_device *phydev) | |
977 | #else | |
978 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
979 | struct mii_dev *bus, int phy_id) | |
980 | #endif | |
0b23fb36 | 981 | { |
0b23fb36 | 982 | struct eth_device *edev; |
9e27e9dc | 983 | struct fec_priv *fec; |
0b23fb36 | 984 | unsigned char ethaddr[6]; |
e382fb48 MV |
985 | uint32_t start; |
986 | int ret = 0; | |
0b23fb36 IY |
987 | |
988 | /* create and fill edev struct */ | |
989 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
990 | if (!edev) { | |
9e27e9dc | 991 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
992 | ret = -ENOMEM; |
993 | goto err1; | |
9e27e9dc MV |
994 | } |
995 | ||
996 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
997 | if (!fec) { | |
998 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
999 | ret = -ENOMEM; |
1000 | goto err2; | |
0b23fb36 | 1001 | } |
9e27e9dc | 1002 | |
de0b9576 | 1003 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
1004 | memset(fec, 0, sizeof(*fec)); |
1005 | ||
79e5f27b MV |
1006 | ret = fec_alloc_descs(fec); |
1007 | if (ret) | |
1008 | goto err3; | |
1009 | ||
0b23fb36 IY |
1010 | edev->priv = fec; |
1011 | edev->init = fec_init; | |
1012 | edev->send = fec_send; | |
1013 | edev->recv = fec_recv; | |
1014 | edev->halt = fec_halt; | |
fb57ec97 | 1015 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 1016 | |
9e27e9dc | 1017 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
1018 | fec->bd = bd; |
1019 | ||
392b8502 | 1020 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
1021 | |
1022 | /* Reset chip. */ | |
cb17b92d | 1023 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
1024 | start = get_timer(0); |
1025 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1026 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
3450a859 | 1027 | printf("FEC MXC: Timeout resetting chip\n"); |
79e5f27b | 1028 | goto err4; |
e382fb48 | 1029 | } |
0b23fb36 | 1030 | udelay(10); |
e382fb48 | 1031 | } |
0b23fb36 | 1032 | |
a5990b26 | 1033 | fec_reg_setup(fec); |
ef8e3a3b TK |
1034 | fec_set_dev_name(edev->name, dev_id); |
1035 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
1036 | fec->bus = bus; |
1037 | fec_mii_setspeed(bus->priv); | |
1038 | #ifdef CONFIG_PHYLIB | |
1039 | fec->phydev = phydev; | |
1040 | phy_connect_dev(phydev, edev); | |
1041 | /* Configure phy */ | |
1042 | phy_config(phydev); | |
1043 | #else | |
9e27e9dc | 1044 | fec->phy_id = phy_id; |
fe428b90 TK |
1045 | #endif |
1046 | eth_register(edev); | |
1047 | ||
1048 | if (fec_get_hwaddr(edev, dev_id, ethaddr) == 0) { | |
1049 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
1050 | memcpy(edev->enetaddr, ethaddr, 6); | |
ddb636bd EN |
1051 | if (!getenv("ethaddr")) |
1052 | eth_setenv_enetaddr("ethaddr", ethaddr); | |
fe428b90 TK |
1053 | } |
1054 | return ret; | |
79e5f27b MV |
1055 | err4: |
1056 | fec_free_descs(fec); | |
fe428b90 TK |
1057 | err3: |
1058 | free(fec); | |
1059 | err2: | |
1060 | free(edev); | |
1061 | err1: | |
1062 | return ret; | |
1063 | } | |
1064 | ||
1065 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) | |
1066 | { | |
1067 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; | |
1068 | struct mii_dev *bus; | |
1069 | int ret; | |
0b23fb36 | 1070 | |
13947f43 TK |
1071 | bus = mdio_alloc(); |
1072 | if (!bus) { | |
1073 | printf("mdio_alloc failed\n"); | |
fe428b90 | 1074 | return NULL; |
13947f43 TK |
1075 | } |
1076 | bus->read = fec_phy_read; | |
1077 | bus->write = fec_phy_write; | |
fe428b90 | 1078 | bus->priv = eth; |
ef8e3a3b | 1079 | fec_set_dev_name(bus->name, dev_id); |
fe428b90 TK |
1080 | |
1081 | ret = mdio_register(bus); | |
1082 | if (ret) { | |
1083 | printf("mdio_register failed\n"); | |
1084 | free(bus); | |
1085 | return NULL; | |
1086 | } | |
1087 | fec_mii_setspeed(eth); | |
1088 | return bus; | |
1089 | } | |
1090 | ||
1091 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) | |
1092 | { | |
1093 | uint32_t base_mii; | |
1094 | struct mii_dev *bus = NULL; | |
1095 | #ifdef CONFIG_PHYLIB | |
1096 | struct phy_device *phydev = NULL; | |
1097 | #endif | |
1098 | int ret; | |
1099 | ||
5c1ad3e6 | 1100 | #ifdef CONFIG_MX28 |
13947f43 TK |
1101 | /* |
1102 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1103 | * Only the first one can access the MDIO bus. | |
1104 | */ | |
fe428b90 | 1105 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1106 | #else |
fe428b90 | 1107 | base_mii = addr; |
13947f43 | 1108 | #endif |
fe428b90 TK |
1109 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1110 | bus = fec_get_miibus(base_mii, dev_id); | |
1111 | if (!bus) | |
1112 | return -ENOMEM; | |
4dc27eed | 1113 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1114 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed | 1115 | if (!phydev) { |
845a57b4 | 1116 | mdio_unregister(bus); |
4dc27eed | 1117 | free(bus); |
fe428b90 | 1118 | return -ENOMEM; |
4dc27eed | 1119 | } |
fe428b90 TK |
1120 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1121 | #else | |
1122 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1123 | #endif |
fe428b90 TK |
1124 | if (ret) { |
1125 | #ifdef CONFIG_PHYLIB | |
1126 | free(phydev); | |
1127 | #endif | |
845a57b4 | 1128 | mdio_unregister(bus); |
fe428b90 TK |
1129 | free(bus); |
1130 | } | |
e382fb48 | 1131 | return ret; |
eef24480 | 1132 | } |
0b23fb36 | 1133 | |
eef24480 TK |
1134 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1135 | int fecmxc_initialize(bd_t *bd) | |
1136 | { | |
1137 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1138 | IMX_FEC_BASE); | |
0b23fb36 | 1139 | } |
eef24480 | 1140 | #endif |
2e5f4421 | 1141 | |
13947f43 | 1142 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1143 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1144 | { | |
1145 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1146 | fec->mii_postcall = cb; | |
1147 | return 0; | |
1148 | } | |
13947f43 | 1149 | #endif |