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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
9 | */ |
10 | ||
11 | #include <common.h> | |
60752ca8 | 12 | #include <dm.h> |
0b23fb36 | 13 | #include <malloc.h> |
cf92e05c | 14 | #include <memalign.h> |
0b23fb36 | 15 | #include <net.h> |
84f64c8b | 16 | #include <netdev.h> |
0b23fb36 IY |
17 | #include <miiphy.h> |
18 | #include "fec_mxc.h" | |
19 | ||
20 | #include <asm/arch/clock.h> | |
21 | #include <asm/arch/imx-regs.h> | |
fbecbaa1 | 22 | #include <asm/imx-common/sys_proto.h> |
0b23fb36 | 23 | #include <asm/io.h> |
1221ce45 | 24 | #include <linux/errno.h> |
e2a66e60 | 25 | #include <linux/compiler.h> |
0b23fb36 IY |
26 | |
27 | DECLARE_GLOBAL_DATA_PTR; | |
28 | ||
bc1ce150 MV |
29 | /* |
30 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
31 | * the code in the tightloops this timeout is used in adds some overhead. | |
32 | */ | |
33 | #define FEC_XFER_TIMEOUT 5000 | |
34 | ||
db5b7f56 FE |
35 | /* |
36 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
37 | * 64-byte alignment in the DMA RX FEC buffer. | |
38 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
39 | * satisfies the alignment on other SoCs (32-bytes) | |
40 | */ | |
41 | #define FEC_DMA_RX_MINALIGN 64 | |
42 | ||
0b23fb36 IY |
43 | #ifndef CONFIG_MII |
44 | #error "CONFIG_MII has to be defined!" | |
45 | #endif | |
46 | ||
5c1ad3e6 EN |
47 | #ifndef CONFIG_FEC_XCV_TYPE |
48 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
49 | #endif |
50 | ||
be7e87e2 MV |
51 | /* |
52 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
53 | * sending and after receiving. | |
54 | */ | |
5c1ad3e6 EN |
55 | #ifdef CONFIG_MX28 |
56 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
57 | #endif | |
58 | ||
59 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
60 | ||
61 | /* Check various alignment issues at compile time */ | |
62 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
63 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
64 | #endif | |
65 | ||
66 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
67 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
68 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
69 | #endif |
70 | ||
0b23fb36 IY |
71 | #undef DEBUG |
72 | ||
5c1ad3e6 | 73 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
74 | static void swap_packet(uint32_t *packet, int length) |
75 | { | |
76 | int i; | |
77 | ||
78 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
79 | packet[i] = __swab32(packet[i]); | |
80 | } | |
81 | #endif | |
82 | ||
0b23fb36 IY |
83 | /* |
84 | * MII-interface related functions | |
85 | */ | |
13947f43 TK |
86 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyAddr, |
87 | uint8_t regAddr) | |
0b23fb36 | 88 | { |
0b23fb36 IY |
89 | uint32_t reg; /* convenient holder for the PHY register */ |
90 | uint32_t phy; /* convenient holder for the PHY */ | |
91 | uint32_t start; | |
13947f43 | 92 | int val; |
0b23fb36 IY |
93 | |
94 | /* | |
95 | * reading from any PHY's register is done by properly | |
96 | * programming the FEC's MII data register. | |
97 | */ | |
d133b881 | 98 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
99 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; |
100 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
101 | ||
102 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 103 | phy | reg, ð->mii_data); |
0b23fb36 IY |
104 | |
105 | /* | |
106 | * wait for the related interrupt | |
107 | */ | |
a60d1e5b | 108 | start = get_timer(0); |
d133b881 | 109 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
110 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
111 | printf("Read MDIO failed...\n"); | |
112 | return -1; | |
113 | } | |
114 | } | |
115 | ||
116 | /* | |
117 | * clear mii interrupt bit | |
118 | */ | |
d133b881 | 119 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 IY |
120 | |
121 | /* | |
122 | * it's now safe to read the PHY's register | |
123 | */ | |
13947f43 TK |
124 | val = (unsigned short)readl(ð->mii_data); |
125 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, | |
126 | regAddr, val); | |
127 | return val; | |
0b23fb36 IY |
128 | } |
129 | ||
575c5cc0 | 130 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
131 | { |
132 | /* | |
133 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
134 | * and do not drop the Preamble. | |
843a3e58 MR |
135 | * |
136 | * The i.MX28 and i.MX6 types have another field in the MSCR (aka | |
137 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
138 | * versions are RAZ there, so just ignore the difference and write the | |
139 | * register always. | |
140 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
141 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
142 | * output. | |
143 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
144 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
145 | * holdtime cannot result in a value greater than 3. | |
4294b248 | 146 | */ |
843a3e58 MR |
147 | u32 pclk = imx_get_fecclk(); |
148 | u32 speed = DIV_ROUND_UP(pclk, 5000000); | |
149 | u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; | |
6ba45cc0 MN |
150 | #ifdef FEC_QUIRK_ENET_MAC |
151 | speed--; | |
152 | #endif | |
843a3e58 | 153 | writel(speed << 1 | hold << 8, ð->mii_speed); |
575c5cc0 | 154 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 155 | } |
0b23fb36 | 156 | |
13947f43 TK |
157 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyAddr, |
158 | uint8_t regAddr, uint16_t data) | |
159 | { | |
0b23fb36 IY |
160 | uint32_t reg; /* convenient holder for the PHY register */ |
161 | uint32_t phy; /* convenient holder for the PHY */ | |
162 | uint32_t start; | |
163 | ||
164 | reg = regAddr << FEC_MII_DATA_RA_SHIFT; | |
165 | phy = phyAddr << FEC_MII_DATA_PA_SHIFT; | |
166 | ||
167 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 168 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 IY |
169 | |
170 | /* | |
171 | * wait for the MII interrupt | |
172 | */ | |
a60d1e5b | 173 | start = get_timer(0); |
d133b881 | 174 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
175 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
176 | printf("Write MDIO failed...\n"); | |
177 | return -1; | |
178 | } | |
179 | } | |
180 | ||
181 | /* | |
182 | * clear MII interrupt bit | |
183 | */ | |
d133b881 | 184 | writel(FEC_IEVENT_MII, ð->ievent); |
13947f43 | 185 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyAddr, |
0b23fb36 IY |
186 | regAddr, data); |
187 | ||
188 | return 0; | |
189 | } | |
190 | ||
84f64c8b JH |
191 | static int fec_phy_read(struct mii_dev *bus, int phyAddr, int dev_addr, |
192 | int regAddr) | |
13947f43 TK |
193 | { |
194 | return fec_mdio_read(bus->priv, phyAddr, regAddr); | |
195 | } | |
196 | ||
84f64c8b JH |
197 | static int fec_phy_write(struct mii_dev *bus, int phyAddr, int dev_addr, |
198 | int regAddr, u16 data) | |
13947f43 TK |
199 | { |
200 | return fec_mdio_write(bus->priv, phyAddr, regAddr, data); | |
201 | } | |
202 | ||
203 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
204 | static int miiphy_restart_aneg(struct eth_device *dev) |
205 | { | |
b774fe9d SB |
206 | int ret = 0; |
207 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 208 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 209 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 210 | |
0b23fb36 IY |
211 | /* |
212 | * Wake up from sleep if necessary | |
213 | * Reset PHY, then delay 300ns | |
214 | */ | |
cb17b92d | 215 | #ifdef CONFIG_MX27 |
13947f43 | 216 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 217 | #endif |
13947f43 | 218 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
219 | udelay(1000); |
220 | ||
221 | /* | |
222 | * Set the auto-negotiation advertisement register bits | |
223 | */ | |
13947f43 | 224 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
8ef583a0 MF |
225 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
226 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 227 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
8ef583a0 | 228 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
229 | |
230 | if (fec->mii_postcall) | |
231 | ret = fec->mii_postcall(fec->phy_id); | |
232 | ||
b774fe9d | 233 | #endif |
2e5f4421 | 234 | return ret; |
0b23fb36 IY |
235 | } |
236 | ||
0750701a | 237 | #ifndef CONFIG_FEC_FIXED_SPEED |
0b23fb36 IY |
238 | static int miiphy_wait_aneg(struct eth_device *dev) |
239 | { | |
240 | uint32_t start; | |
13947f43 | 241 | int status; |
9e27e9dc | 242 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 243 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 IY |
244 | |
245 | /* | |
246 | * Wait for AN completion | |
247 | */ | |
a60d1e5b | 248 | start = get_timer(0); |
0b23fb36 IY |
249 | do { |
250 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
251 | printf("%s: Autonegotiation timeout\n", dev->name); | |
252 | return -1; | |
253 | } | |
254 | ||
13947f43 TK |
255 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
256 | if (status < 0) { | |
257 | printf("%s: Autonegotiation failed. status: %d\n", | |
0b23fb36 IY |
258 | dev->name, status); |
259 | return -1; | |
260 | } | |
8ef583a0 | 261 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
262 | |
263 | return 0; | |
264 | } | |
0750701a | 265 | #endif /* CONFIG_FEC_FIXED_SPEED */ |
13947f43 TK |
266 | #endif |
267 | ||
0b23fb36 IY |
268 | static int fec_rx_task_enable(struct fec_priv *fec) |
269 | { | |
c0b5a3bb | 270 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
271 | return 0; |
272 | } | |
273 | ||
274 | static int fec_rx_task_disable(struct fec_priv *fec) | |
275 | { | |
276 | return 0; | |
277 | } | |
278 | ||
279 | static int fec_tx_task_enable(struct fec_priv *fec) | |
280 | { | |
c0b5a3bb | 281 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
282 | return 0; |
283 | } | |
284 | ||
285 | static int fec_tx_task_disable(struct fec_priv *fec) | |
286 | { | |
287 | return 0; | |
288 | } | |
289 | ||
290 | /** | |
291 | * Initialize receive task's buffer descriptors | |
292 | * @param[in] fec all we know about the device yet | |
293 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 294 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
295 | * @return 0 on success |
296 | * | |
79e5f27b | 297 | * Init all RX descriptors to default values. |
0b23fb36 | 298 | */ |
79e5f27b | 299 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 300 | { |
5c1ad3e6 | 301 | uint32_t size; |
79e5f27b | 302 | uint8_t *data; |
5c1ad3e6 EN |
303 | int i; |
304 | ||
0b23fb36 | 305 | /* |
79e5f27b MV |
306 | * Reload the RX descriptors with default values and wipe |
307 | * the RX buffers. | |
0b23fb36 | 308 | */ |
5c1ad3e6 EN |
309 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
310 | for (i = 0; i < count; i++) { | |
79e5f27b MV |
311 | data = (uint8_t *)fec->rbd_base[i].data_pointer; |
312 | memset(data, 0, dsize); | |
313 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
314 | ||
315 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
316 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
317 | } |
318 | ||
319 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 320 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
321 | fec->rbd_index = 0; |
322 | ||
79e5f27b MV |
323 | flush_dcache_range((unsigned)fec->rbd_base, |
324 | (unsigned)fec->rbd_base + size); | |
0b23fb36 IY |
325 | } |
326 | ||
327 | /** | |
328 | * Initialize transmit task's buffer descriptors | |
329 | * @param[in] fec all we know about the device yet | |
330 | * | |
331 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
332 | * Note: There is a race condition in the hardware. When only one BD is in | |
333 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
334 | * This bit in combination with the READY bit results into double transmit | |
335 | * of each data buffer. It seems the state machine checks READY earlier then | |
336 | * resetting it after the first transfer. | |
337 | * Using two BDs solves this issue. | |
338 | */ | |
339 | static void fec_tbd_init(struct fec_priv *fec) | |
340 | { | |
5c1ad3e6 EN |
341 | unsigned addr = (unsigned)fec->tbd_base; |
342 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
343 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
344 | |
345 | memset(fec->tbd_base, 0, size); | |
346 | fec->tbd_base[0].status = 0; | |
347 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 348 | fec->tbd_index = 0; |
79e5f27b | 349 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
350 | } |
351 | ||
352 | /** | |
353 | * Mark the given read buffer descriptor as free | |
354 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
355 | * @param[in] pRbd buffer descriptor to mark free again | |
356 | */ | |
357 | static void fec_rbd_clean(int last, struct fec_bd *pRbd) | |
358 | { | |
5c1ad3e6 | 359 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 360 | if (last) |
5c1ad3e6 EN |
361 | flags |= FEC_RBD_WRAP; |
362 | writew(flags, &pRbd->status); | |
0b23fb36 IY |
363 | writew(0, &pRbd->data_length); |
364 | } | |
365 | ||
f54183e6 | 366 | static int fec_get_hwaddr(int dev_id, unsigned char *mac) |
0b23fb36 | 367 | { |
be252b65 | 368 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 369 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
370 | } |
371 | ||
60752ca8 JT |
372 | #ifdef CONFIG_DM_ETH |
373 | static int fecmxc_set_hwaddr(struct udevice *dev) | |
374 | #else | |
4294b248 | 375 | static int fec_set_hwaddr(struct eth_device *dev) |
60752ca8 | 376 | #endif |
0b23fb36 | 377 | { |
60752ca8 JT |
378 | #ifdef CONFIG_DM_ETH |
379 | struct fec_priv *fec = dev_get_priv(dev); | |
380 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
381 | uchar *mac = pdata->enetaddr; | |
382 | #else | |
4294b248 | 383 | uchar *mac = dev->enetaddr; |
0b23fb36 | 384 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 385 | #endif |
0b23fb36 IY |
386 | |
387 | writel(0, &fec->eth->iaddr1); | |
388 | writel(0, &fec->eth->iaddr2); | |
389 | writel(0, &fec->eth->gaddr1); | |
390 | writel(0, &fec->eth->gaddr2); | |
391 | ||
392 | /* | |
393 | * Set physical address | |
394 | */ | |
395 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], | |
396 | &fec->eth->paddr1); | |
397 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); | |
398 | ||
399 | return 0; | |
400 | } | |
401 | ||
a5990b26 MV |
402 | /* |
403 | * Do initial configuration of the FEC registers | |
404 | */ | |
405 | static void fec_reg_setup(struct fec_priv *fec) | |
406 | { | |
407 | uint32_t rcntrl; | |
408 | ||
409 | /* | |
410 | * Set interrupt mask register | |
411 | */ | |
412 | writel(0x00000000, &fec->eth->imask); | |
413 | ||
414 | /* | |
415 | * Clear FEC-Lite interrupt event register(IEVENT) | |
416 | */ | |
417 | writel(0xffffffff, &fec->eth->ievent); | |
418 | ||
419 | ||
420 | /* | |
421 | * Set FEC-Lite receive control register(R_CNTRL): | |
422 | */ | |
423 | ||
424 | /* Start with frame length = 1518, common for all modes. */ | |
425 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 426 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
427 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
428 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
429 | rcntrl |= FEC_RCNTRL_RGMII; |
430 | else if (fec->xcv_type == RMII) | |
431 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
432 | |
433 | writel(rcntrl, &fec->eth->r_cntrl); | |
434 | } | |
435 | ||
0b23fb36 IY |
436 | /** |
437 | * Start the FEC engine | |
438 | * @param[in] dev Our device to handle | |
439 | */ | |
60752ca8 JT |
440 | #ifdef CONFIG_DM_ETH |
441 | static int fec_open(struct udevice *dev) | |
442 | #else | |
0b23fb36 | 443 | static int fec_open(struct eth_device *edev) |
60752ca8 | 444 | #endif |
0b23fb36 | 445 | { |
60752ca8 JT |
446 | #ifdef CONFIG_DM_ETH |
447 | struct fec_priv *fec = dev_get_priv(dev); | |
448 | #else | |
0b23fb36 | 449 | struct fec_priv *fec = (struct fec_priv *)edev->priv; |
60752ca8 | 450 | #endif |
28774cba | 451 | int speed; |
5c1ad3e6 EN |
452 | uint32_t addr, size; |
453 | int i; | |
0b23fb36 IY |
454 | |
455 | debug("fec_open: fec_open(dev)\n"); | |
456 | /* full-duplex, heartbeat disabled */ | |
457 | writel(1 << 2, &fec->eth->x_cntrl); | |
458 | fec->rbd_index = 0; | |
459 | ||
5c1ad3e6 EN |
460 | /* Invalidate all descriptors */ |
461 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
462 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
463 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
464 | ||
465 | /* Flush the descriptors into RAM */ | |
466 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
467 | ARCH_DMA_MINALIGN); | |
468 | addr = (uint32_t)fec->rbd_base; | |
469 | flush_dcache_range(addr, addr + size); | |
470 | ||
28774cba | 471 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
472 | /* Enable ENET HW endian SWAP */ |
473 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
474 | &fec->eth->ecntrl); | |
475 | /* Enable ENET store and forward mode */ | |
476 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
477 | &fec->eth->x_wmrk); | |
478 | #endif | |
0b23fb36 IY |
479 | /* |
480 | * Enable FEC-Lite controller | |
481 | */ | |
cb17b92d JR |
482 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
483 | &fec->eth->ecntrl); | |
7df51fd8 | 484 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 JR |
485 | udelay(100); |
486 | /* | |
487 | * setup the MII gasket for RMII mode | |
488 | */ | |
489 | ||
490 | /* disable the gasket */ | |
491 | writew(0, &fec->eth->miigsk_enr); | |
492 | ||
493 | /* wait for the gasket to be disabled */ | |
494 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
495 | udelay(2); | |
496 | ||
497 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
498 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
499 | ||
500 | /* re-enable the gasket */ | |
501 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
502 | ||
503 | /* wait until MII gasket is ready */ | |
504 | int max_loops = 10; | |
505 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
506 | if (--max_loops <= 0) { | |
507 | printf("WAIT for MII Gasket ready timed out\n"); | |
508 | break; | |
509 | } | |
510 | } | |
511 | #endif | |
0b23fb36 | 512 | |
13947f43 | 513 | #ifdef CONFIG_PHYLIB |
4dc27eed | 514 | { |
13947f43 | 515 | /* Start up the PHY */ |
11af8d65 TT |
516 | int ret = phy_startup(fec->phydev); |
517 | ||
518 | if (ret) { | |
519 | printf("Could not initialize PHY %s\n", | |
520 | fec->phydev->dev->name); | |
521 | return ret; | |
522 | } | |
13947f43 | 523 | speed = fec->phydev->speed; |
13947f43 | 524 | } |
0750701a HS |
525 | #elif CONFIG_FEC_FIXED_SPEED |
526 | speed = CONFIG_FEC_FIXED_SPEED; | |
13947f43 | 527 | #else |
0b23fb36 | 528 | miiphy_wait_aneg(edev); |
28774cba | 529 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 530 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 531 | #endif |
0b23fb36 | 532 | |
28774cba TK |
533 | #ifdef FEC_QUIRK_ENET_MAC |
534 | { | |
535 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 536 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
537 | if (speed == _1000BASET) |
538 | ecr |= FEC_ECNTRL_SPEED; | |
539 | else if (speed != _100BASET) | |
540 | rcr |= FEC_RCNTRL_RMII_10T; | |
541 | writel(ecr, &fec->eth->ecntrl); | |
542 | writel(rcr, &fec->eth->r_cntrl); | |
543 | } | |
544 | #endif | |
545 | debug("%s:Speed=%i\n", __func__, speed); | |
546 | ||
0b23fb36 IY |
547 | /* |
548 | * Enable SmartDMA receive task | |
549 | */ | |
550 | fec_rx_task_enable(fec); | |
551 | ||
552 | udelay(100000); | |
553 | return 0; | |
554 | } | |
555 | ||
60752ca8 JT |
556 | #ifdef CONFIG_DM_ETH |
557 | static int fecmxc_init(struct udevice *dev) | |
558 | #else | |
0b23fb36 | 559 | static int fec_init(struct eth_device *dev, bd_t* bd) |
60752ca8 | 560 | #endif |
0b23fb36 | 561 | { |
60752ca8 JT |
562 | #ifdef CONFIG_DM_ETH |
563 | struct fec_priv *fec = dev_get_priv(dev); | |
564 | #else | |
0b23fb36 | 565 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 566 | #endif |
9e27e9dc | 567 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
79e5f27b | 568 | int i; |
0b23fb36 | 569 | |
e9319f11 | 570 | /* Initialize MAC address */ |
60752ca8 JT |
571 | #ifdef CONFIG_DM_ETH |
572 | fecmxc_set_hwaddr(dev); | |
573 | #else | |
e9319f11 | 574 | fec_set_hwaddr(dev); |
60752ca8 | 575 | #endif |
e9319f11 | 576 | |
0b23fb36 | 577 | /* |
79e5f27b | 578 | * Setup transmit descriptors, there are two in total. |
0b23fb36 | 579 | */ |
79e5f27b | 580 | fec_tbd_init(fec); |
0b23fb36 | 581 | |
79e5f27b MV |
582 | /* Setup receive descriptors. */ |
583 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 584 | |
a5990b26 | 585 | fec_reg_setup(fec); |
9eb3770b | 586 | |
f41471e6 | 587 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 588 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 589 | |
0b23fb36 IY |
590 | /* |
591 | * Set Opcode/Pause Duration Register | |
592 | */ | |
593 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ | |
594 | writel(0x2, &fec->eth->x_wmrk); | |
595 | /* | |
596 | * Set multicast address filter | |
597 | */ | |
598 | writel(0x00000000, &fec->eth->gaddr1); | |
599 | writel(0x00000000, &fec->eth->gaddr2); | |
600 | ||
601 | ||
fbecbaa1 | 602 | /* Do not access reserved register for i.MX6UL */ |
87f99895 | 603 | if (!is_mx6ul()) { |
fbecbaa1 PF |
604 | /* clear MIB RAM */ |
605 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
606 | writel(0, i); | |
0b23fb36 | 607 | |
fbecbaa1 PF |
608 | /* FIFO receive start register */ |
609 | writel(0x520, &fec->eth->r_fstart); | |
610 | } | |
0b23fb36 IY |
611 | |
612 | /* size and address of each buffer */ | |
613 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
614 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
615 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
616 | ||
13947f43 | 617 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
618 | if (fec->xcv_type != SEVENWIRE) |
619 | miiphy_restart_aneg(dev); | |
13947f43 | 620 | #endif |
0b23fb36 IY |
621 | fec_open(dev); |
622 | return 0; | |
623 | } | |
624 | ||
625 | /** | |
626 | * Halt the FEC engine | |
627 | * @param[in] dev Our device to handle | |
628 | */ | |
60752ca8 JT |
629 | #ifdef CONFIG_DM_ETH |
630 | static void fecmxc_halt(struct udevice *dev) | |
631 | #else | |
0b23fb36 | 632 | static void fec_halt(struct eth_device *dev) |
60752ca8 | 633 | #endif |
0b23fb36 | 634 | { |
60752ca8 JT |
635 | #ifdef CONFIG_DM_ETH |
636 | struct fec_priv *fec = dev_get_priv(dev); | |
637 | #else | |
9e27e9dc | 638 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 639 | #endif |
0b23fb36 IY |
640 | int counter = 0xffff; |
641 | ||
642 | /* | |
643 | * issue graceful stop command to the FEC transmitter if necessary | |
644 | */ | |
cb17b92d | 645 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
0b23fb36 IY |
646 | &fec->eth->x_cntrl); |
647 | ||
648 | debug("eth_halt: wait for stop regs\n"); | |
649 | /* | |
650 | * wait for graceful stop to register | |
651 | */ | |
652 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) | |
cb17b92d | 653 | udelay(1); |
0b23fb36 IY |
654 | |
655 | /* | |
656 | * Disable SmartDMA tasks | |
657 | */ | |
658 | fec_tx_task_disable(fec); | |
659 | fec_rx_task_disable(fec); | |
660 | ||
661 | /* | |
662 | * Disable the Ethernet Controller | |
663 | * Note: this will also reset the BD index counter! | |
664 | */ | |
740d6ae5 JR |
665 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
666 | &fec->eth->ecntrl); | |
0b23fb36 IY |
667 | fec->rbd_index = 0; |
668 | fec->tbd_index = 0; | |
0b23fb36 IY |
669 | debug("eth_halt: done\n"); |
670 | } | |
671 | ||
672 | /** | |
673 | * Transmit one frame | |
674 | * @param[in] dev Our ethernet device to handle | |
675 | * @param[in] packet Pointer to the data to be transmitted | |
676 | * @param[in] length Data count in bytes | |
677 | * @return 0 on success | |
678 | */ | |
60752ca8 JT |
679 | #ifdef CONFIG_DM_ETH |
680 | static int fecmxc_send(struct udevice *dev, void *packet, int length) | |
681 | #else | |
442dac4c | 682 | static int fec_send(struct eth_device *dev, void *packet, int length) |
60752ca8 | 683 | #endif |
0b23fb36 IY |
684 | { |
685 | unsigned int status; | |
efe24d2e | 686 | uint32_t size, end; |
5c1ad3e6 | 687 | uint32_t addr; |
bc1ce150 MV |
688 | int timeout = FEC_XFER_TIMEOUT; |
689 | int ret = 0; | |
0b23fb36 IY |
690 | |
691 | /* | |
692 | * This routine transmits one frame. This routine only accepts | |
693 | * 6-byte Ethernet addresses. | |
694 | */ | |
60752ca8 JT |
695 | #ifdef CONFIG_DM_ETH |
696 | struct fec_priv *fec = dev_get_priv(dev); | |
697 | #else | |
0b23fb36 | 698 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 699 | #endif |
0b23fb36 IY |
700 | |
701 | /* | |
702 | * Check for valid length of data. | |
703 | */ | |
704 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 705 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
706 | return -1; |
707 | } | |
708 | ||
709 | /* | |
5c1ad3e6 EN |
710 | * Setup the transmit buffer. We are always using the first buffer for |
711 | * transmission, the second will be empty and only used to stop the DMA | |
712 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 713 | */ |
5c1ad3e6 | 714 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
715 | swap_packet((uint32_t *)packet, length); |
716 | #endif | |
5c1ad3e6 EN |
717 | |
718 | addr = (uint32_t)packet; | |
efe24d2e MV |
719 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
720 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
721 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 722 | |
0b23fb36 | 723 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
724 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
725 | ||
0b23fb36 IY |
726 | /* |
727 | * update BD's status now | |
728 | * This block: | |
729 | * - is always the last in a chain (means no chain) | |
730 | * - should transmitt the CRC | |
731 | * - might be the last BD in the list, so the address counter should | |
732 | * wrap (-> keep the WRAP flag) | |
733 | */ | |
734 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
735 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
736 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
737 | ||
5c1ad3e6 EN |
738 | /* |
739 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
740 | * After this code, the descriptors will be safely in RAM and we | |
741 | * can start DMA. | |
742 | */ | |
743 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
744 | addr = (uint32_t)fec->tbd_base; | |
745 | flush_dcache_range(addr, addr + size); | |
746 | ||
ab94cd49 MV |
747 | /* |
748 | * Below we read the DMA descriptor's last four bytes back from the | |
749 | * DRAM. This is important in order to make sure that all WRITE | |
750 | * operations on the bus that were triggered by previous cache FLUSH | |
751 | * have completed. | |
752 | * | |
753 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
754 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
755 | * for the bus structure of MX28. The scenario is as follows: | |
756 | * | |
757 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
758 | * to DRAM due to flush_dcache_range() | |
759 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
760 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
761 | * | |
762 | * Note that 2) does sometimes finish before 1) due to reordering of | |
763 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
764 | * DMA descriptor is fully written into DRAM. This results in occasional | |
765 | * corruption of the DMA descriptor. | |
766 | */ | |
767 | readl(addr + size - 4); | |
768 | ||
0b23fb36 IY |
769 | /* |
770 | * Enable SmartDMA transmit task | |
771 | */ | |
772 | fec_tx_task_enable(fec); | |
773 | ||
774 | /* | |
5c1ad3e6 EN |
775 | * Wait until frame is sent. On each turn of the wait cycle, we must |
776 | * invalidate data cache to see what's really in RAM. Also, we need | |
777 | * barrier here. | |
0b23fb36 | 778 | */ |
67449098 | 779 | while (--timeout) { |
c0b5a3bb | 780 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 781 | break; |
0b23fb36 | 782 | } |
5c1ad3e6 | 783 | |
f599288d | 784 | if (!timeout) { |
67449098 | 785 | ret = -EINVAL; |
f599288d FE |
786 | goto out; |
787 | } | |
788 | ||
789 | /* | |
790 | * The TDAR bit is cleared when the descriptors are all out from TX | |
791 | * but on mx6solox we noticed that the READY bit is still not cleared | |
792 | * right after TDAR. | |
793 | * These are two distinct signals, and in IC simulation, we found that | |
794 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
795 | * cleared. | |
796 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
797 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
798 | * version. | |
799 | * | |
800 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
801 | * which covers the mx6solox case and does not harm the other SoCs. | |
802 | */ | |
803 | timeout = FEC_XFER_TIMEOUT; | |
804 | while (--timeout) { | |
805 | invalidate_dcache_range(addr, addr + size); | |
806 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
807 | FEC_TBD_READY)) | |
808 | break; | |
809 | } | |
67449098 | 810 | |
f599288d | 811 | if (!timeout) |
67449098 MV |
812 | ret = -EINVAL; |
813 | ||
f599288d | 814 | out: |
67449098 | 815 | debug("fec_send: status 0x%x index %d ret %i\n", |
0b23fb36 | 816 | readw(&fec->tbd_base[fec->tbd_index].status), |
67449098 | 817 | fec->tbd_index, ret); |
0b23fb36 IY |
818 | /* for next transmission use the other buffer */ |
819 | if (fec->tbd_index) | |
820 | fec->tbd_index = 0; | |
821 | else | |
822 | fec->tbd_index = 1; | |
823 | ||
bc1ce150 | 824 | return ret; |
0b23fb36 IY |
825 | } |
826 | ||
827 | /** | |
828 | * Pull one frame from the card | |
829 | * @param[in] dev Our ethernet device to handle | |
830 | * @return Length of packet read | |
831 | */ | |
60752ca8 JT |
832 | #ifdef CONFIG_DM_ETH |
833 | static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) | |
834 | #else | |
0b23fb36 | 835 | static int fec_recv(struct eth_device *dev) |
60752ca8 | 836 | #endif |
0b23fb36 | 837 | { |
60752ca8 JT |
838 | #ifdef CONFIG_DM_ETH |
839 | struct fec_priv *fec = dev_get_priv(dev); | |
840 | #else | |
0b23fb36 | 841 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 842 | #endif |
0b23fb36 IY |
843 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; |
844 | unsigned long ievent; | |
845 | int frame_length, len = 0; | |
0b23fb36 | 846 | uint16_t bd_status; |
efe24d2e | 847 | uint32_t addr, size, end; |
5c1ad3e6 | 848 | int i; |
fd37f195 | 849 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
0b23fb36 IY |
850 | |
851 | /* | |
852 | * Check if any critical events have happened | |
853 | */ | |
854 | ievent = readl(&fec->eth->ievent); | |
855 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 856 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 | 857 | if (ievent & FEC_IEVENT_BABR) { |
60752ca8 JT |
858 | #ifdef CONFIG_DM_ETH |
859 | fecmxc_halt(dev); | |
860 | fecmxc_init(dev); | |
861 | #else | |
0b23fb36 IY |
862 | fec_halt(dev); |
863 | fec_init(dev, fec->bd); | |
60752ca8 | 864 | #endif |
0b23fb36 IY |
865 | printf("some error: 0x%08lx\n", ievent); |
866 | return 0; | |
867 | } | |
868 | if (ievent & FEC_IEVENT_HBERR) { | |
869 | /* Heartbeat error */ | |
870 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
871 | &fec->eth->x_cntrl); | |
872 | } | |
873 | if (ievent & FEC_IEVENT_GRA) { | |
874 | /* Graceful stop complete */ | |
875 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
60752ca8 JT |
876 | #ifdef CONFIG_DM_ETH |
877 | fecmxc_halt(dev); | |
878 | #else | |
0b23fb36 | 879 | fec_halt(dev); |
60752ca8 | 880 | #endif |
0b23fb36 IY |
881 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), |
882 | &fec->eth->x_cntrl); | |
60752ca8 JT |
883 | #ifdef CONFIG_DM_ETH |
884 | fecmxc_init(dev); | |
885 | #else | |
0b23fb36 | 886 | fec_init(dev, fec->bd); |
60752ca8 | 887 | #endif |
0b23fb36 IY |
888 | } |
889 | } | |
890 | ||
891 | /* | |
5c1ad3e6 EN |
892 | * Read the buffer status. Before the status can be read, the data cache |
893 | * must be invalidated, because the data in RAM might have been changed | |
894 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
895 | * no need to worry they'd overlap. | |
896 | * | |
897 | * WARNING: By invalidating the descriptor here, we also invalidate | |
898 | * the descriptors surrounding this one. Therefore we can NOT change the | |
899 | * contents of this descriptor nor the surrounding ones. The problem is | |
900 | * that in order to mark the descriptor as processed, we need to change | |
901 | * the descriptor. The solution is to mark the whole cache line when all | |
902 | * descriptors in the cache line are processed. | |
0b23fb36 | 903 | */ |
5c1ad3e6 EN |
904 | addr = (uint32_t)rbd; |
905 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
906 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
907 | invalidate_dcache_range(addr, addr + size); | |
908 | ||
0b23fb36 IY |
909 | bd_status = readw(&rbd->status); |
910 | debug("fec_recv: status 0x%x\n", bd_status); | |
911 | ||
912 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
913 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
914 | ((readw(&rbd->data_length) - 4) > 14)) { | |
915 | /* | |
916 | * Get buffer address and size | |
917 | */ | |
b189584b | 918 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 919 | frame_length = readw(&rbd->data_length) - 4; |
5c1ad3e6 EN |
920 | /* |
921 | * Invalidate data cache over the buffer | |
922 | */ | |
efe24d2e MV |
923 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
924 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
925 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 926 | |
0b23fb36 IY |
927 | /* |
928 | * Fill the buffer and pass it to upper layers | |
929 | */ | |
5c1ad3e6 | 930 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
b189584b | 931 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 932 | #endif |
b189584b | 933 | memcpy(buff, (char *)addr, frame_length); |
1fd92db8 | 934 | net_process_received_packet(buff, frame_length); |
0b23fb36 IY |
935 | len = frame_length; |
936 | } else { | |
937 | if (bd_status & FEC_RBD_ERR) | |
b189584b AA |
938 | printf("error frame: 0x%08x 0x%08x\n", |
939 | addr, bd_status); | |
0b23fb36 | 940 | } |
5c1ad3e6 | 941 | |
0b23fb36 | 942 | /* |
5c1ad3e6 EN |
943 | * Free the current buffer, restart the engine and move forward |
944 | * to the next buffer. Here we check if the whole cacheline of | |
945 | * descriptors was already processed and if so, we mark it free | |
946 | * as whole. | |
0b23fb36 | 947 | */ |
5c1ad3e6 EN |
948 | size = RXDESC_PER_CACHELINE - 1; |
949 | if ((fec->rbd_index & size) == size) { | |
950 | i = fec->rbd_index - size; | |
951 | addr = (uint32_t)&fec->rbd_base[i]; | |
952 | for (; i <= fec->rbd_index ; i++) { | |
953 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
954 | &fec->rbd_base[i]); | |
955 | } | |
956 | flush_dcache_range(addr, | |
957 | addr + ARCH_DMA_MINALIGN); | |
958 | } | |
959 | ||
0b23fb36 IY |
960 | fec_rx_task_enable(fec); |
961 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
962 | } | |
963 | debug("fec_recv: stop\n"); | |
964 | ||
965 | return len; | |
966 | } | |
967 | ||
ef8e3a3b TK |
968 | static void fec_set_dev_name(char *dest, int dev_id) |
969 | { | |
970 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
971 | } | |
972 | ||
79e5f27b MV |
973 | static int fec_alloc_descs(struct fec_priv *fec) |
974 | { | |
975 | unsigned int size; | |
976 | int i; | |
977 | uint8_t *data; | |
978 | ||
979 | /* Allocate TX descriptors. */ | |
980 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
981 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
982 | if (!fec->tbd_base) | |
983 | goto err_tx; | |
984 | ||
985 | /* Allocate RX descriptors. */ | |
986 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
987 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
988 | if (!fec->rbd_base) | |
989 | goto err_rx; | |
990 | ||
991 | memset(fec->rbd_base, 0, size); | |
992 | ||
993 | /* Allocate RX buffers. */ | |
994 | ||
995 | /* Maximum RX buffer size. */ | |
db5b7f56 | 996 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 997 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 998 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
999 | if (!data) { |
1000 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
1001 | goto err_ring; | |
1002 | } | |
1003 | ||
1004 | memset(data, 0, size); | |
1005 | ||
1006 | fec->rbd_base[i].data_pointer = (uint32_t)data; | |
1007 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
1008 | fec->rbd_base[i].data_length = 0; | |
1009 | /* Flush the buffer to memory. */ | |
1010 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
1011 | } | |
1012 | ||
1013 | /* Mark the last RBD to close the ring. */ | |
1014 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
1015 | ||
1016 | fec->rbd_index = 0; | |
1017 | fec->tbd_index = 0; | |
1018 | ||
1019 | return 0; | |
1020 | ||
1021 | err_ring: | |
1022 | for (; i >= 0; i--) | |
1023 | free((void *)fec->rbd_base[i].data_pointer); | |
1024 | free(fec->rbd_base); | |
1025 | err_rx: | |
1026 | free(fec->tbd_base); | |
1027 | err_tx: | |
1028 | return -ENOMEM; | |
1029 | } | |
1030 | ||
1031 | static void fec_free_descs(struct fec_priv *fec) | |
1032 | { | |
1033 | int i; | |
1034 | ||
1035 | for (i = 0; i < FEC_RBD_NUM; i++) | |
1036 | free((void *)fec->rbd_base[i].data_pointer); | |
1037 | free(fec->rbd_base); | |
1038 | free(fec->tbd_base); | |
1039 | } | |
1040 | ||
60752ca8 JT |
1041 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) |
1042 | { | |
1043 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; | |
1044 | struct mii_dev *bus; | |
1045 | int ret; | |
1046 | ||
1047 | bus = mdio_alloc(); | |
1048 | if (!bus) { | |
1049 | printf("mdio_alloc failed\n"); | |
1050 | return NULL; | |
1051 | } | |
1052 | bus->read = fec_phy_read; | |
1053 | bus->write = fec_phy_write; | |
1054 | bus->priv = eth; | |
1055 | fec_set_dev_name(bus->name, dev_id); | |
1056 | ||
1057 | ret = mdio_register(bus); | |
1058 | if (ret) { | |
1059 | printf("mdio_register failed\n"); | |
1060 | free(bus); | |
1061 | return NULL; | |
1062 | } | |
1063 | fec_mii_setspeed(eth); | |
1064 | return bus; | |
1065 | } | |
1066 | ||
1067 | #ifndef CONFIG_DM_ETH | |
fe428b90 TK |
1068 | #ifdef CONFIG_PHYLIB |
1069 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
1070 | struct mii_dev *bus, struct phy_device *phydev) | |
1071 | #else | |
1072 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
1073 | struct mii_dev *bus, int phy_id) | |
1074 | #endif | |
0b23fb36 | 1075 | { |
0b23fb36 | 1076 | struct eth_device *edev; |
9e27e9dc | 1077 | struct fec_priv *fec; |
0b23fb36 | 1078 | unsigned char ethaddr[6]; |
e382fb48 MV |
1079 | uint32_t start; |
1080 | int ret = 0; | |
0b23fb36 IY |
1081 | |
1082 | /* create and fill edev struct */ | |
1083 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
1084 | if (!edev) { | |
9e27e9dc | 1085 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
1086 | ret = -ENOMEM; |
1087 | goto err1; | |
9e27e9dc MV |
1088 | } |
1089 | ||
1090 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
1091 | if (!fec) { | |
1092 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
1093 | ret = -ENOMEM; |
1094 | goto err2; | |
0b23fb36 | 1095 | } |
9e27e9dc | 1096 | |
de0b9576 | 1097 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
1098 | memset(fec, 0, sizeof(*fec)); |
1099 | ||
79e5f27b MV |
1100 | ret = fec_alloc_descs(fec); |
1101 | if (ret) | |
1102 | goto err3; | |
1103 | ||
0b23fb36 IY |
1104 | edev->priv = fec; |
1105 | edev->init = fec_init; | |
1106 | edev->send = fec_send; | |
1107 | edev->recv = fec_recv; | |
1108 | edev->halt = fec_halt; | |
fb57ec97 | 1109 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 1110 | |
9e27e9dc | 1111 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
1112 | fec->bd = bd; |
1113 | ||
392b8502 | 1114 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
1115 | |
1116 | /* Reset chip. */ | |
cb17b92d | 1117 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
1118 | start = get_timer(0); |
1119 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1120 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
3450a859 | 1121 | printf("FEC MXC: Timeout resetting chip\n"); |
79e5f27b | 1122 | goto err4; |
e382fb48 | 1123 | } |
0b23fb36 | 1124 | udelay(10); |
e382fb48 | 1125 | } |
0b23fb36 | 1126 | |
a5990b26 | 1127 | fec_reg_setup(fec); |
ef8e3a3b TK |
1128 | fec_set_dev_name(edev->name, dev_id); |
1129 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
1130 | fec->bus = bus; |
1131 | fec_mii_setspeed(bus->priv); | |
1132 | #ifdef CONFIG_PHYLIB | |
1133 | fec->phydev = phydev; | |
1134 | phy_connect_dev(phydev, edev); | |
1135 | /* Configure phy */ | |
1136 | phy_config(phydev); | |
1137 | #else | |
9e27e9dc | 1138 | fec->phy_id = phy_id; |
fe428b90 TK |
1139 | #endif |
1140 | eth_register(edev); | |
1141 | ||
f54183e6 | 1142 | if (fec_get_hwaddr(dev_id, ethaddr) == 0) { |
fe428b90 TK |
1143 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); |
1144 | memcpy(edev->enetaddr, ethaddr, 6); | |
ddb636bd EN |
1145 | if (!getenv("ethaddr")) |
1146 | eth_setenv_enetaddr("ethaddr", ethaddr); | |
fe428b90 TK |
1147 | } |
1148 | return ret; | |
79e5f27b MV |
1149 | err4: |
1150 | fec_free_descs(fec); | |
fe428b90 TK |
1151 | err3: |
1152 | free(fec); | |
1153 | err2: | |
1154 | free(edev); | |
1155 | err1: | |
1156 | return ret; | |
1157 | } | |
1158 | ||
fe428b90 TK |
1159 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) |
1160 | { | |
1161 | uint32_t base_mii; | |
1162 | struct mii_dev *bus = NULL; | |
1163 | #ifdef CONFIG_PHYLIB | |
1164 | struct phy_device *phydev = NULL; | |
1165 | #endif | |
1166 | int ret; | |
1167 | ||
5c1ad3e6 | 1168 | #ifdef CONFIG_MX28 |
13947f43 TK |
1169 | /* |
1170 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1171 | * Only the first one can access the MDIO bus. | |
1172 | */ | |
fe428b90 | 1173 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1174 | #else |
fe428b90 | 1175 | base_mii = addr; |
13947f43 | 1176 | #endif |
fe428b90 TK |
1177 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1178 | bus = fec_get_miibus(base_mii, dev_id); | |
1179 | if (!bus) | |
1180 | return -ENOMEM; | |
4dc27eed | 1181 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1182 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed | 1183 | if (!phydev) { |
845a57b4 | 1184 | mdio_unregister(bus); |
4dc27eed | 1185 | free(bus); |
fe428b90 | 1186 | return -ENOMEM; |
4dc27eed | 1187 | } |
fe428b90 TK |
1188 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1189 | #else | |
1190 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1191 | #endif |
fe428b90 TK |
1192 | if (ret) { |
1193 | #ifdef CONFIG_PHYLIB | |
1194 | free(phydev); | |
1195 | #endif | |
845a57b4 | 1196 | mdio_unregister(bus); |
fe428b90 TK |
1197 | free(bus); |
1198 | } | |
e382fb48 | 1199 | return ret; |
eef24480 | 1200 | } |
0b23fb36 | 1201 | |
eef24480 TK |
1202 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1203 | int fecmxc_initialize(bd_t *bd) | |
1204 | { | |
1205 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1206 | IMX_FEC_BASE); | |
0b23fb36 | 1207 | } |
eef24480 | 1208 | #endif |
2e5f4421 | 1209 | |
13947f43 | 1210 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1211 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1212 | { | |
1213 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1214 | fec->mii_postcall = cb; | |
1215 | return 0; | |
1216 | } | |
13947f43 | 1217 | #endif |
60752ca8 JT |
1218 | |
1219 | #else | |
1220 | ||
1221 | static const struct eth_ops fecmxc_ops = { | |
1222 | .start = fecmxc_init, | |
1223 | .send = fecmxc_send, | |
1224 | .recv = fecmxc_recv, | |
1225 | .stop = fecmxc_halt, | |
1226 | .write_hwaddr = fecmxc_set_hwaddr, | |
1227 | }; | |
1228 | ||
1229 | static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) | |
1230 | { | |
1231 | struct phy_device *phydev; | |
1232 | int mask = 0xffffffff; | |
1233 | ||
1234 | #ifdef CONFIG_PHYLIB | |
1235 | mask = 1 << CONFIG_FEC_MXC_PHYADDR; | |
1236 | #endif | |
1237 | ||
1238 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); | |
1239 | if (!phydev) | |
1240 | return -ENODEV; | |
1241 | ||
1242 | phy_connect_dev(phydev, dev); | |
1243 | ||
1244 | priv->phydev = phydev; | |
1245 | phy_config(phydev); | |
1246 | ||
1247 | return 0; | |
1248 | } | |
1249 | ||
1250 | static int fecmxc_probe(struct udevice *dev) | |
1251 | { | |
1252 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1253 | struct fec_priv *priv = dev_get_priv(dev); | |
1254 | struct mii_dev *bus = NULL; | |
1255 | int dev_id = -1; | |
1256 | unsigned char ethaddr[6]; | |
1257 | uint32_t start; | |
1258 | int ret; | |
1259 | ||
1260 | ret = fec_alloc_descs(priv); | |
1261 | if (ret) | |
1262 | return ret; | |
1263 | ||
1264 | bus = fec_get_miibus((uint32_t)priv->eth, dev_id); | |
1265 | if (!bus) | |
1266 | goto err_mii; | |
1267 | ||
1268 | priv->bus = bus; | |
1269 | priv->xcv_type = CONFIG_FEC_XCV_TYPE; | |
1270 | priv->interface = pdata->phy_interface; | |
1271 | ret = fec_phy_init(priv, dev); | |
1272 | if (ret) | |
1273 | goto err_phy; | |
1274 | ||
1275 | /* Reset chip. */ | |
1276 | writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, &priv->eth->ecntrl); | |
1277 | start = get_timer(0); | |
1278 | while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1279 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
1280 | printf("FEC MXC: Timeout reseting chip\n"); | |
1281 | goto err_timeout; | |
1282 | } | |
1283 | udelay(10); | |
1284 | } | |
1285 | ||
1286 | fec_reg_setup(priv); | |
1287 | fec_set_dev_name((char *)dev->name, dev_id); | |
1288 | priv->dev_id = (dev_id == -1) ? 0 : dev_id; | |
1289 | ||
1290 | ret = fec_get_hwaddr(dev_id, ethaddr); | |
1291 | if (!ret) { | |
1292 | debug("got MAC%d address from fuse: %pM\n", dev_id, ethaddr); | |
1293 | memcpy(pdata->enetaddr, ethaddr, 6); | |
1294 | if (!getenv("ethaddr")) | |
1295 | eth_setenv_enetaddr("ethaddr", ethaddr); | |
1296 | } | |
1297 | ||
1298 | return 0; | |
1299 | ||
1300 | err_timeout: | |
1301 | free(priv->phydev); | |
1302 | err_phy: | |
1303 | mdio_unregister(bus); | |
1304 | free(bus); | |
1305 | err_mii: | |
1306 | fec_free_descs(priv); | |
1307 | return ret; | |
1308 | } | |
1309 | ||
1310 | static int fecmxc_remove(struct udevice *dev) | |
1311 | { | |
1312 | struct fec_priv *priv = dev_get_priv(dev); | |
1313 | ||
1314 | free(priv->phydev); | |
1315 | fec_free_descs(priv); | |
1316 | mdio_unregister(priv->bus); | |
1317 | mdio_free(priv->bus); | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
1322 | static int fecmxc_ofdata_to_platdata(struct udevice *dev) | |
1323 | { | |
1324 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1325 | struct fec_priv *priv = dev_get_priv(dev); | |
1326 | const char *phy_mode; | |
1327 | ||
1328 | pdata->iobase = (phys_addr_t)dev_get_addr(dev); | |
1329 | priv->eth = (struct ethernet_regs *)pdata->iobase; | |
1330 | ||
1331 | pdata->phy_interface = -1; | |
1332 | phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); | |
1333 | if (phy_mode) | |
1334 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
1335 | if (pdata->phy_interface == -1) { | |
1336 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
1337 | return -EINVAL; | |
1338 | } | |
1339 | ||
1340 | /* TODO | |
1341 | * Need to get the reset-gpio and related properties from DT | |
1342 | * and implemet the enet reset code on .probe call | |
1343 | */ | |
1344 | ||
1345 | return 0; | |
1346 | } | |
1347 | ||
1348 | static const struct udevice_id fecmxc_ids[] = { | |
1349 | { .compatible = "fsl,imx6q-fec" }, | |
1350 | { } | |
1351 | }; | |
1352 | ||
1353 | U_BOOT_DRIVER(fecmxc_gem) = { | |
1354 | .name = "fecmxc", | |
1355 | .id = UCLASS_ETH, | |
1356 | .of_match = fecmxc_ids, | |
1357 | .ofdata_to_platdata = fecmxc_ofdata_to_platdata, | |
1358 | .probe = fecmxc_probe, | |
1359 | .remove = fecmxc_remove, | |
1360 | .ops = &fecmxc_ops, | |
1361 | .priv_auto_alloc_size = sizeof(struct fec_priv), | |
1362 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1363 | }; | |
1364 | #endif |