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2002-06-13 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
3a2b820e
CD		 12002-06-13 Chris Demetriou <cgd@broadcom.com>
2
3 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
4 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
5 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
6 (convert): Note that this function is not used for paired-single
7 format conversions.
8 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
9 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
10 (check_fmt_p): Enable paired-single support.
11 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
12 (PUU.PS): New instructions.
13 (CVT.S.fmt): Don't use this instruction for paired-single format
14 destinations.
15 * sim-main.h (FP_formats): New value 'fmt_ps.'
16 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
17 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
18
d18ea9c2
CD		 192002-06-12 Chris Demetriou <cgd@broadcom.com>
20
21 * mips.igen: Fix formatting of function calls in
22 many FP operations.
23
95fd5cee
CD		 242002-06-12 Chris Demetriou <cgd@broadcom.com>
25
26 * mips.igen (MOVN, MOVZ): Trace result.
27 (TNEI): Print "tnei" as the opcode name in traces.
28 (CEIL.W): Add disassembly string for traces.
29 (RSQRT.fmt): Make location of disassembly string consistent
30 with other instructions.
31
4f0d55ae
CD		 322002-06-12 Chris Demetriou <cgd@broadcom.com>
33
34 * mips.igen (X): Delete unused function.
35
3c25f8c7
AC		 362002-06-08 Andrew Cagney <cagney@redhat.com>
37
38 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
39
f3c08b7e
CD		 402002-06-07 Chris Demetriou <cgd@broadcom.com>
41 Ed Satterthwaite <ehs@broadcom.com>
42
43 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
44 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
45 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
46 (fp_nmsub): New prototypes.
47 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
48 (NegMultiplySub): New defines.
49 * mips.igen (RSQRT.fmt): Use RSquareRoot().
50 (MADD.D, MADD.S): Replace with...
51 (MADD.fmt): New instruction.
52 (MSUB.D, MSUB.S): Replace with...
53 (MSUB.fmt): New instruction.
54 (NMADD.D, NMADD.S): Replace with...
55 (NMADD.fmt): New instruction.
56 (NMSUB.D, MSUB.S): Replace with...
57 (NMSUB.fmt): New instruction.
58
52714ff9
CD		 592002-06-07 Chris Demetriou <cgd@broadcom.com>
60 Ed Satterthwaite <ehs@broadcom.com>
61
62 * cp1.c: Fix more comment spelling and formatting.
63 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
64 (denorm_mode): New function.
65 (fpu_unary, fpu_binary): Round results after operation, collect
66 status from rounding operations, and update the FCSR.
67 (convert): Collect status from integer conversions and rounding
68 operations, and update the FCSR. Adjust NaN values that result
69 from conversions. Convert to use sim_io_eprintf rather than
70 fprintf, and remove some debugging code.
71 * cp1.h (fenr_FS): New define.
72
577d8c4b
CD		 732002-06-07 Chris Demetriou <cgd@broadcom.com>
74
75 * cp1.c (convert): Remove unusable debugging code, and move MIPS
76 rounding mode to sim FP rounding mode flag conversion code into...
77 (rounding_mode): New function.
78
196496ed
CD		 792002-06-07 Chris Demetriou <cgd@broadcom.com>
80
81 * cp1.c: Clean up formatting of a few comments.
82 (value_fpr): Reformat switch statement.
83
cfe9ea23
CD		 842002-06-06 Chris Demetriou <cgd@broadcom.com>
85 Ed Satterthwaite <ehs@broadcom.com>
86
87 * cp1.h: New file.
88 * sim-main.h: Include cp1.h.
89 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
90 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
91 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
92 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
93 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
94 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
95 * cp1.c: Don't include sim-fpu.h; already included by
96 sim-main.h. Clean up formatting of some comments.
97 (NaN, Equal, Less): Remove.
98 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
99 (fp_cmp): New functions.
100 * mips.igen (do_c_cond_fmt): Remove.
101 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
102 Compare. Add result tracing.
103 (CxC1): Remove, replace with...
104 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
105 (DMxC1): Remove, replace with...
106 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
107 (MxC1): Remove, replace with...
108 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
109
ee7254b0
CD		 1102002-06-04 Chris Demetriou <cgd@broadcom.com>
111
112 * sim-main.h (FGRIDX): Remove, replace all uses with...
113 (FGR_BASE): New macro.
114 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
115 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
116 (NR_FGR, FGR): Likewise.
117 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
118 * mips.igen: Likewise.
119
d3eb724f
CD		 1202002-06-04 Chris Demetriou <cgd@broadcom.com>
121
122 * cp1.c: Add an FSF Copyright notice to this file.
123
ba46ddd0
CD		 1242002-06-04 Chris Demetriou <cgd@broadcom.com>
125 Ed Satterthwaite <ehs@broadcom.com>
126
127 * cp1.c (Infinity): Remove.
128 * sim-main.h (Infinity): Likewise.
129
130 * cp1.c (fp_unary, fp_binary): New functions.
131 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
132 (fp_sqrt): New functions, implemented in terms of the above.
133 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
134 (Recip, SquareRoot): Remove (replaced by functions above).
135 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
136 (fp_recip, fp_sqrt): New prototypes.
137 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
138 (Recip, SquareRoot): Replace prototypes with #defines which
139 invoke the functions above.
140
18d8a52d
CD		 1412002-06-03 Chris Demetriou <cgd@broadcom.com>
142
143 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
144 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
145 file, remove PARAMS from prototypes.
146 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
147 simulator state arguments.
148 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
149 pass simulator state arguments.
150 * cp1.c (SD): Redefine as CPU_STATE(cpu).
151 (store_fpr, convert): Remove 'sd' argument.
152 (value_fpr): Likewise. Convert to use 'SD' instead.
153
0f154cbd
CD		 1542002-06-03 Chris Demetriou <cgd@broadcom.com>
155
156 * cp1.c (Min, Max): Remove #if 0'd functions.
157 * sim-main.h (Min, Max): Remove.
158
e80fc152
CD		 1592002-06-03 Chris Demetriou <cgd@broadcom.com>
160
161 * cp1.c: fix formatting of switch case and default labels.
162 * interp.c: Likewise.
163 * sim-main.c: Likewise.
164
bad673a9
CD		 1652002-06-03 Chris Demetriou <cgd@broadcom.com>
166
167 * cp1.c: Clean up comments which describe FP formats.
168 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
169
7cbea089
CD		 1702002-06-03 Chris Demetriou <cgd@broadcom.com>
171 Ed Satterthwaite <ehs@broadcom.com>
172
173 * configure.in (mipsisa64sb1*-*-*): New target for supporting
174 Broadcom SiByte SB-1 processor configurations.
175 * configure: Regenerate.
176 * sb1.igen: New file.
177 * mips.igen: Include sb1.igen.
178 (sb1): New model.
179 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
180 * mdmx.igen: Add "sb1" model to all appropriate functions and
181 instructions.
182 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
183 (ob_func, ob_acc): Reference the above.
184 (qh_acc): Adjust to keep the same size as ob_acc.
185 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
186 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
187
909daa82
CD		 1882002-06-03 Chris Demetriou <cgd@broadcom.com>
189
190 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
191
f4f1b9f1
CD		 1922002-06-02 Chris Demetriou <cgd@broadcom.com>
193 Ed Satterthwaite <ehs@broadcom.com>
194
195 * mips.igen (mdmx): New (pseudo-)model.
196 * mdmx.c, mdmx.igen: New files.
197 * Makefile.in (SIM_OBJS): Add mdmx.o.
198 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
199 New typedefs.
200 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
201 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
202 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
203 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
204 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
205 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
206 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
207 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
208 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
209 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
210 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
211 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
212 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
213 (qh_fmtsel): New macros.
214 (_sim_cpu): New member "acc".
215 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
216 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
217
5accf1ff
CD		 2182002-05-01 Chris Demetriou <cgd@broadcom.com>
219
220 * interp.c: Use 'deprecated' rather than 'depreciated.'
221 * sim-main.h: Likewise.
222
402586aa
CD		 2232002-05-01 Chris Demetriou <cgd@broadcom.com>
224
225 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
226 which wouldn't compile anyway.
227 * sim-main.h (unpredictable_action): New function prototype.
228 (Unpredictable): Define to call igen function unpredictable().
229 (NotWordValue): New macro to call igen function not_word_value().
230 (UndefinedResult): Remove.
231 * interp.c (undefined_result): Remove.
232 (unpredictable_action): New function.
233 * mips.igen (not_word_value, unpredictable): New functions.
234 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
235 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
236 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
237 NotWordValue() to check for unpredictable inputs, then
238 Unpredictable() to handle them.
239
c9b9995a
CD		 2402002-02-24 Chris Demetriou <cgd@broadcom.com>
241
242 * mips.igen: Fix formatting of calls to Unpredictable().
243
e1015982
AC		 2442002-04-20 Andrew Cagney <ac131313@redhat.com>
245
246 * interp.c (sim_open): Revert previous change.
247
b882a66b
AO		 2482002-04-18 Alexandre Oliva <aoliva@redhat.com>
249
250 * interp.c (sim_open): Disable chunk of code that wrote code in
251 vector table entries.
252
c429b7dd
CD		 2532002-03-19 Chris Demetriou <cgd@broadcom.com>
254
255 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
256 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
257 unused definitions.
258
37d146fa
CD		 2592002-03-19 Chris Demetriou <cgd@broadcom.com>
260
261 * cp1.c: Fix many formatting issues.
262
07892c0b
CD		 2632002-03-19 Chris G. Demetriou <cgd@broadcom.com>
264
265 * cp1.c (fpu_format_name): New function to replace...
266 (DOFMT): This. Delete, and update all callers.
267 (fpu_rounding_mode_name): New function to replace...
268 (RMMODE): This. Delete, and update all callers.
269
487f79b7
CD		 2702002-03-19 Chris G. Demetriou <cgd@broadcom.com>
271
272 * interp.c: Move FPU support routines from here to...
273 * cp1.c: Here. New file.
274 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
275 (cp1.o): New target.
276
1e799e28
CD		 2772002-03-12 Chris Demetriou <cgd@broadcom.com>
278
279 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
280 * mips.igen (mips32, mips64): New models, add to all instructions
281 and functions as appropriate.
282 (loadstore_ea, check_u64): New variant for model mips64.
283 (check_fmt_p): New variant for models mipsV and mips64, remove
284 mipsV model marking fro other variant.
285 (SLL) Rename to...
286 (SLLa) this.
287 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
288 for mips32 and mips64.
289 (DCLO, DCLZ): New instructions for mips64.
290
82f728db
CD		 2912002-03-07 Chris Demetriou <cgd@broadcom.com>
292
293 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
294 immediate or code as a hex value with the "%#lx" format.
295 (ANDI): Likewise, and fix printed instruction name.
296
b96e7ef1
CD		 2972002-03-05 Chris Demetriou <cgd@broadcom.com>
298
299 * sim-main.h (UndefinedResult, Unpredictable): New macros
300 which currently do nothing.
301
d35d4f70
CD		 3022002-03-05 Chris Demetriou <cgd@broadcom.com>
303
304 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
305 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
306 (status_CU3): New definitions.
307
308 * sim-main.h (ExceptionCause): Add new values for MIPS32
309 and MIPS64: MDMX, MCheck, CacheErr. Update comments
310 for DebugBreakPoint and NMIReset to note their status in
311 MIPS32 and MIPS64.
312 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
313 (SignalExceptionCacheErr): New exception macros.
314
3ad6f714
CD		 3152002-03-05 Chris Demetriou <cgd@broadcom.com>
316
317 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
318 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
319 is always enabled.
320 (SignalExceptionCoProcessorUnusable): Take as argument the
321 unusable coprocessor number.
322
86b77b47
CD		 3232002-03-05 Chris Demetriou <cgd@broadcom.com>
324
325 * mips.igen: Fix formatting of all SignalException calls.
326
97a88e93 3272002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 328
329 * sim-main.h (SIGNEXTEND): Remove.
330
97a88e93 3312002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 332
333 * mips.igen: Remove gencode comment from top of file, fix
334 spelling in another comment.
335
97a88e93 3362002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 337
338 * mips.igen (check_fmt, check_fmt_p): New functions to check
339 whether specific floating point formats are usable.
340 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
341 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
342 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
343 Use the new functions.
344 (do_c_cond_fmt): Remove format checks...
345 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
346
97a88e93 3472002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 348
349 * mips.igen: Fix formatting of check_fpu calls.
350
41774c9d
CD		 3512002-03-03 Chris Demetriou <cgd@broadcom.com>
352
353 * mips.igen (FLOOR.L.fmt): Store correct destination register.
354
4a0bd876
CD		 3552002-03-03 Chris Demetriou <cgd@broadcom.com>
356
357 * mips.igen: Remove whitespace at end of lines.
358
09297648
CD		 3592002-03-02 Chris Demetriou <cgd@broadcom.com>
360
361 * mips.igen (loadstore_ea): New function to do effective
362 address calculations.
363 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
364 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
365 CACHE): Use loadstore_ea to do effective address computations.
366
043b7057
CD		 3672002-03-02 Chris Demetriou <cgd@broadcom.com>
368
369 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
370 * mips.igen (LL, CxC1, MxC1): Likewise.
371
c1e8ada4
CD		 3722002-03-02 Chris Demetriou <cgd@broadcom.com>
373
374 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
375 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
376 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
377 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
378 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
379 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
380 Don't split opcode fields by hand, use the opcode field values
381 provided by igen.
382
3e1dca16
CD		 3832002-03-01 Chris Demetriou <cgd@broadcom.com>
384
385 * mips.igen (do_divu): Fix spacing.
386
387 * mips.igen (do_dsllv): Move to be right before DSLLV,
388 to match the rest of the do_<shift> functions.
389
fff8d27d
CD		 3902002-03-01 Chris Demetriou <cgd@broadcom.com>
391
392 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
393 DSRL32, do_dsrlv): Trace inputs and results.
394
0d3e762b
CD		 3952002-03-01 Chris Demetriou <cgd@broadcom.com>
396
397 * mips.igen (CACHE): Provide instruction-printing string.
398
399 * interp.c (signal_exception): Comment tokens after #endif.
400
eb5fcf93
CD		 4012002-02-28 Chris Demetriou <cgd@broadcom.com>
402
403 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
404 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
405 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
406 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
407 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
408 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
409 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
410 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
411
bb22bd7d
CD		 4122002-02-28 Chris Demetriou <cgd@broadcom.com>
413
414 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
415 instruction-printing string.
416 (LWU): Use '64' as the filter flag.
417
91a177cf
CD		 4182002-02-28 Chris Demetriou <cgd@broadcom.com>
419
420 * mips.igen (SDXC1): Fix instruction-printing string.
421
387f484a
CD		 4222002-02-28 Chris Demetriou <cgd@broadcom.com>
423
424 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
425 filter flags "32,f".
426
3d81f391
CD		 4272002-02-27 Chris Demetriou <cgd@broadcom.com>
428
429 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
430 as the filter flag.
431
af5107af
CD		 4322002-02-27 Chris Demetriou <cgd@broadcom.com>
433
434 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
435 add a comma) so that it more closely match the MIPS ISA
436 documentation opcode partitioning.
437 (PREF): Put useful names on opcode fields, and include
438 instruction-printing string.
439
ca971540
CD		 4402002-02-27 Chris Demetriou <cgd@broadcom.com>
441
442 * mips.igen (check_u64): New function which in the future will
443 check whether 64-bit instructions are usable and signal an
444 exception if not. Currently a no-op.
445 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
446 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
447 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
448 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
449
450 * mips.igen (check_fpu): New function which in the future will
451 check whether FPU instructions are usable and signal an exception
452 if not. Currently a no-op.
453 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
454 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
455 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
456 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
457 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
458 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
459 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
460 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
461
1c47a468
CD		 4622002-02-27 Chris Demetriou <cgd@broadcom.com>
463
464 * mips.igen (do_load_left, do_load_right): Move to be immediately
465 following do_load.
466 (do_store_left, do_store_right): Move to be immediately following
467 do_store.
468
603a98e7
CD		 4692002-02-27 Chris Demetriou <cgd@broadcom.com>
470
471 * mips.igen (mipsV): New model name. Also, add it to
472 all instructions and functions where it is appropriate.
473
c5d00cc7
CD		 4742002-02-18 Chris Demetriou <cgd@broadcom.com>
475
476 * mips.igen: For all functions and instructions, list model
477 names that support that instruction one per line.
478
074e9cb8
CD		 4792002-02-11 Chris Demetriou <cgd@broadcom.com>
480
481 * mips.igen: Add some additional comments about supported
482 models, and about which instructions go where.
483 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
484 order as is used in the rest of the file.
485
9805e229
CD		 4862002-02-11 Chris Demetriou <cgd@broadcom.com>
487
488 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
489 indicating that ALU32_END or ALU64_END are there to check
490 for overflow.
491 (DADD): Likewise, but also remove previous comment about
492 overflow checking.
493
f701dad2
CD		 4942002-02-10 Chris Demetriou <cgd@broadcom.com>
495
496 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
497 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
498 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
499 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
500 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
501 fields (i.e., add and move commas) so that they more closely
502 match the MIPS ISA documentation opcode partitioning.
503
5042002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 505
506 * mips.igen (ADDI): Print immediate value.
507 (BREAK): Print code.
508 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
509 (SLL): Print "nop" specially, and don't run the code
510 that does the shift for the "nop" case.
511
9e52972e
FF		 5122001-11-17 Fred Fish <fnf@redhat.com>
513
514 * sim-main.h (float_operation): Move enum declaration outside
515 of _sim_cpu struct declaration.
516
c0efbca4
JB		 5172001-04-12 Jim Blandy <jimb@redhat.com>
518
519 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
520 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
521 set of the FCSR.
522 * sim-main.h (COCIDX): Remove definition; this isn't supported by
523 PENDING_FILL, and you can get the intended effect gracefully by
524 calling PENDING_SCHED directly.
525
fb891446
BE		 5262001-02-23 Ben Elliston <bje@redhat.com>
527
528 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
529 already defined elsewhere.
530
8030f857
BE		 5312001-02-19 Ben Elliston <bje@redhat.com>
532
533 * sim-main.h (sim_monitor): Return an int.
534 * interp.c (sim_monitor): Add return values.
535 (signal_exception): Handle error conditions from sim_monitor.
536
56b48a7a
CD		 5372001-02-08 Ben Elliston <bje@redhat.com>
538
539 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
540 (store_memory): Likewise, pass cia to sim_core_write*.
541
d3ee60d9
FCE		 5422000-10-19 Frank Ch. Eigler <fche@redhat.com>
543
544 On advice from Chris G. Demetriou <cgd@sibyte.com>:
545 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
546
071da002
AC		 547Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
548
549 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
550 * Makefile.in: Don't delete *.igen when cleaning directory.
551
a28c02cd
AC		 552Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
553
554 * m16.igen (break): Call SignalException not sim_engine_halt.
555
80ee11fa
AC		 556Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
557
558 From Jason Eckhardt:
559 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
560
673388c0
AC		 561Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
562
563 * mips.igen (MxC1, DMxC1): Fix printf formatting.
564
4c0deff4
NC		 5652000-05-24 Michael Hayes <mhayes@cygnus.com>
566
567 * mips.igen (do_dmultx): Fix typo.
568
eb2d80b4
AC		 569Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
570
571 * configure: Regenerated to track ../common/aclocal.m4 changes.
572
dd37a34b
AC		 573Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
574
575 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
576
4c0deff4
NC		 5772000-04-12 Frank Ch. Eigler <fche@redhat.com>
578
579 * sim-main.h (GPR_CLEAR): Define macro.
580
e30db738
AC		 581Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
582
583 * interp.c (decode_coproc): Output long using %lx and not %s.
584
cb7450ea
FCE		 5852000-03-21 Frank Ch. Eigler <fche@redhat.com>
586
587 * interp.c (sim_open): Sort & extend dummy memory regions for
588 --board=jmr3904 for eCos.
589
a3027dd7
FCE		 5902000-03-02 Frank Ch. Eigler <fche@redhat.com>
591
592 * configure: Regenerated.
593
594Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
595
596 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
597 calls, conditional on the simulator being in verbose mode.
598
dfcd3bfb
JM		 599Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
600
601 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
602 cache don't get ReservedInstruction traps.
603
c2d11a7d
JM		 6041999-11-29 Mark Salter <msalter@cygnus.com>
605
606 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
607 to clear status bits in sdisr register. This is how the hardware works.
608
609 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
610 being used by cygmon.
611
4ce44c66
JM		 6121999-11-11 Andrew Haley <aph@cygnus.com>
613
614 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
615 instructions.
616
cff3e48b
JM		 617Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
618
619 * mips.igen (MULT): Correct previous mis-applied patch.
620
d4f3574e
SS		 621Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
622
623 * mips.igen (delayslot32): Handle sequence like
624 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
625 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
626 (MULT): Actually pass the third register...
627
6281999-09-03 Mark Salter <msalter@cygnus.com>
629
630 * interp.c (sim_open): Added more memory aliases for additional
631 hardware being touched by cygmon on jmr3904 board.
632
633Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
634
635 * configure: Regenerated to track ../common/aclocal.m4 changes.
636
a0b3c4fd
JM		 637Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
638
639 * interp.c (sim_store_register): Handle case where client - GDB -
640 specifies that a 4 byte register is 8 bytes in size.
641 (sim_fetch_register): Ditto.
642
adf40b2e
JM		 6431999-07-14 Frank Ch. Eigler <fche@cygnus.com>
644
645 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
646 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
647 (idt_monitor_base): Base address for IDT monitor traps.
648 (pmon_monitor_base): Ditto for PMON.
649 (lsipmon_monitor_base): Ditto for LSI PMON.
650 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
651 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
652 (sim_firmware_command): New function.
653 (mips_option_handler): Call it for OPTION_FIRMWARE.
654 (sim_open): Allocate memory for idt_monitor region. If "--board"
655 option was given, add no monitor by default. Add BREAK hooks only if
656 monitors are also there.
657
43e526b9
JM		 658Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
659
660 * interp.c (sim_monitor): Flush output before reading input.
661
662Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
663
664 * tconfig.in (SIM_HANDLES_LMA): Always define.
665
666Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
667
668 From Mark Salter <msalter@cygnus.com>:
669 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
670 (sim_open): Add setup for BSP board.
671
9846de1b
JM		 672Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
673
674 * mips.igen (MULT, MULTU): Add syntax for two operand version.
675 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
676 them as unimplemented.
677
cd0fc7c3
SS		 6781999-05-08 Felix Lee <flee@cygnus.com>
679
680 * configure: Regenerated to track ../common/aclocal.m4 changes.
681
7a292a7a
SS		 6821999-04-21 Frank Ch. Eigler <fche@cygnus.com>
683
684 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
685
686Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
687
688 * configure.in: Any mips64vr5*-*-* target should have
689 -DTARGET_ENABLE_FR=1.
690 (default_endian): Any mips64vr*el-*-* target should default to
691 LITTLE_ENDIAN.
692 * configure: Re-generate.
693
6941999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
695
696 * mips.igen (ldl): Extend from _16_, not 32.
697
698Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
699
700 * interp.c (sim_store_register): Force registers written to by GDB
701 into an un-interpreted state.
702
c906108c
SS		 7031999-02-05 Frank Ch. Eigler <fche@cygnus.com>
704
705 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
706 CPU, start periodic background I/O polls.
707 (tx3904sio_poll): New function: periodic I/O poller.
708
7091998-12-30 Frank Ch. Eigler <fche@cygnus.com>
710
711 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
712
713Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
714
715 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
716 case statement.
717
7181998-12-29 Frank Ch. Eigler <fche@cygnus.com>
719
720 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
721 (load_word): Call SIM_CORE_SIGNAL hook on error.
722 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
723 starting. For exception dispatching, pass PC instead of NULL_CIA.
724 (decode_coproc): Use COP0_BADVADDR to store faulting address.
725 * sim-main.h (COP0_BADVADDR): Define.
726 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
727 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
728 (_sim_cpu): Add exc_* fields to store register value snapshots.
729 * mips.igen (*): Replace memory-related SignalException* calls
730 with references to SIM_CORE_SIGNAL hook.
731
732 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
733 fix.
734 * sim-main.c (*): Minor warning cleanups.
735
7361998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
737
738 * m16.igen (DADDIU5): Correct type-o.
739
740Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
741
742 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
743 variables.
744
745Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
746
747 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
748 to include path.
749 (interp.o): Add dependency on itable.h
750 (oengine.c, gencode): Delete remaining references.
751 (BUILT_SRC_FROM_GEN): Clean up.
752
7531998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
754
755 * vr4run.c: New.
756 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
757 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
758 tmp-run-hack) : New.
759 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
760 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
761 Drop the "64" qualifier to get the HACK generator working.
762 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
763 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
764 qualifier to get the hack generator working.
765 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
766 (DSLL): Use do_dsll.
767 (DSLLV): Use do_dsllv.
768 (DSRA): Use do_dsra.
769 (DSRL): Use do_dsrl.
770 (DSRLV): Use do_dsrlv.
771 (BC1): Move *vr4100 to get the HACK generator working.
772 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
773 get the HACK generator working.
774 (MACC) Rename to get the HACK generator working.
775 (DMACC,MACCS,DMACCS): Add the 64.
776
7771998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
778
779 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
780 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
781
7821998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
783
784 * mips/interp.c (DEBUG): Cleanups.
785
7861998-12-10 Frank Ch. Eigler <fche@cygnus.com>
787
788 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
789 (tx3904sio_tickle): fflush after a stdout character output.
790
7911998-12-03 Frank Ch. Eigler <fche@cygnus.com>
792
793 * interp.c (sim_close): Uninstall modules.
794
795Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
796
797 * sim-main.h, interp.c (sim_monitor): Change to global
798 function.
799
800Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
801
802 * configure.in (vr4100): Only include vr4100 instructions in
803 simulator.
804 * configure: Re-generate.
805 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
806
807Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
808
809 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
810 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
811 true alternative.
812
813 * configure.in (sim_default_gen, sim_use_gen): Replace with
814 sim_gen.
815 (--enable-sim-igen): Delete config option. Always using IGEN.
816 * configure: Re-generate.
817
818 * Makefile.in (gencode): Kill, kill, kill.
819 * gencode.c: Ditto.
820
821Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
822
823 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
824 bit mips16 igen simulator.
825 * configure: Re-generate.
826
827 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
828 as part of vr4100 ISA.
829 * vr.igen: Mark all instructions as 64 bit only.
830
831Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
832
833 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
834 Pacify GCC.
835
836Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
837
838 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
839 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
840 * configure: Re-generate.
841
842 * m16.igen (BREAK): Define breakpoint instruction.
843 (JALX32): Mark instruction as mips16 and not r3900.
844 * mips.igen (C.cond.fmt): Fix typo in instruction format.
845
846 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
847
848Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
849
850 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
851 insn as a debug breakpoint.
852
853 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
854 pending.slot_size.
855 (PENDING_SCHED): Clean up trace statement.
856 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
857 (PENDING_FILL): Delay write by only one cycle.
858 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
859
860 * sim-main.c (pending_tick): Clean up trace statements. Add trace
861 of pending writes.
862 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
863 32 & 64.
864 (pending_tick): Move incrementing of index to FOR statement.
865 (pending_tick): Only update PENDING_OUT after a write has occured.
866
867 * configure.in: Add explicit mips-lsi-* target. Use gencode to
868 build simulator.
869 * configure: Re-generate.
870
871 * interp.c (sim_engine_run OLD): Delete explicit call to
872 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
873
874Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
875
876 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
877 interrupt level number to match changed SignalExceptionInterrupt
878 macro.
879
880Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
881
882 * interp.c: #include "itable.h" if WITH_IGEN.
883 (get_insn_name): New function.
884 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
885 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
886
887Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
888
889 * configure: Rebuilt to inhale new common/aclocal.m4.
890
891Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
892
893 * dv-tx3904sio.c: Include sim-assert.h.
894
895Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
896
897 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
898 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
899 Reorganize target-specific sim-hardware checks.
900 * configure: rebuilt.
901 * interp.c (sim_open): For tx39 target boards, set
902 OPERATING_ENVIRONMENT, add tx3904sio devices.
903 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
904 ROM executables. Install dv-sockser into sim-modules list.
905
906 * dv-tx3904irc.c: Compiler warning clean-up.
907 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
908 frequent hw-trace messages.
909
910Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
911
912 * vr.igen (MulAcc): Identify as a vr4100 specific function.
913
914Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
915
916 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
917
918 * vr.igen: New file.
919 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
920 * mips.igen: Define vr4100 model. Include vr.igen.
921Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
922
923 * mips.igen (check_mf_hilo): Correct check.
924
925Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
926
927 * sim-main.h (interrupt_event): Add prototype.
928
929 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
930 register_ptr, register_value.
931 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
932
933 * sim-main.h (tracefh): Make extern.
934
935Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
936
937 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
938 Reduce unnecessarily high timer event frequency.
939 * dv-tx3904cpu.c: Ditto for interrupt event.
940
941Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
942
943 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
944 to allay warnings.
945 (interrupt_event): Made non-static.
946
947 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
948 interchange of configuration values for external vs. internal
949 clock dividers.
950
951Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
952
953 * mips.igen (BREAK): Moved code to here for
954 simulator-reserved break instructions.
955 * gencode.c (build_instruction): Ditto.
956 * interp.c (signal_exception): Code moved from here. Non-
957 reserved instructions now use exception vector, rather
958 than halting sim.
959 * sim-main.h: Moved magic constants to here.
960
961Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
962
963 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
964 register upon non-zero interrupt event level, clear upon zero
965 event value.
966 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
967 by passing zero event value.
968 (*_io_{read,write}_buffer): Endianness fixes.
969 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
970 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
971
972 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
973 serial I/O and timer module at base address 0xFFFF0000.
974
975Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
976
977 * mips.igen (SWC1) : Correct the handling of ReverseEndian
978 and BigEndianCPU.
979
980Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
981
982 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
983 parts.
984 * configure: Update.
985
986Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
987
988 * dv-tx3904tmr.c: New file - implements tx3904 timer.
989 * dv-tx3904{irc,cpu}.c: Mild reformatting.
990 * configure.in: Include tx3904tmr in hw_device list.
991 * configure: Rebuilt.
992 * interp.c (sim_open): Instantiate three timer instances.
993 Fix address typo of tx3904irc instance.
994
995Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
996
997 * interp.c (signal_exception): SystemCall exception now uses
998 the exception vector.
999
1000Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1001
1002 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1003 to allay warnings.
1004
1005Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1006
1007 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1008
1009Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1010
1011 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1012
1013 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1014 sim-main.h. Declare a struct hw_descriptor instead of struct
1015 hw_device_descriptor.
1016
1017Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1018
1019 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1020 right bits and then re-align left hand bytes to correct byte
1021 lanes. Fix incorrect computation in do_store_left when loading
1022 bytes from second word.
1023
1024Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1025
1026 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1027 * interp.c (sim_open): Only create a device tree when HW is
1028 enabled.
1029
1030 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1031 * interp.c (signal_exception): Ditto.
1032
1033Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1034
1035 * gencode.c: Mark BEGEZALL as LIKELY.
1036
1037Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1038
1039 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1040 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1041
1042Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1043
1044 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1045 modules. Recognize TX39 target with "mips*tx39" pattern.
1046 * configure: Rebuilt.
1047 * sim-main.h (*): Added many macros defining bits in
1048 TX39 control registers.
1049 (SignalInterrupt): Send actual PC instead of NULL.
1050 (SignalNMIReset): New exception type.
1051 * interp.c (board): New variable for future use to identify
1052 a particular board being simulated.
1053 (mips_option_handler,mips_options): Added "--board" option.
1054 (interrupt_event): Send actual PC.
1055 (sim_open): Make memory layout conditional on board setting.
1056 (signal_exception): Initial implementation of hardware interrupt
1057 handling. Accept another break instruction variant for simulator
1058 exit.
1059 (decode_coproc): Implement RFE instruction for TX39.
1060 (mips.igen): Decode RFE instruction as such.
1061 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1062 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1063 bbegin to implement memory map.
1064 * dv-tx3904cpu.c: New file.
1065 * dv-tx3904irc.c: New file.
1066
1067Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1068
1069 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1070
1071Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1072
1073 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1074 with calls to check_div_hilo.
1075
1076Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1077
1078 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1079 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1080 Add special r3900 version of do_mult_hilo.
1081 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1082 with calls to check_mult_hilo.
1083 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1084 with calls to check_div_hilo.
1085
1086Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1087
1088 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1089 Document a replacement.
1090
1091Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1092
1093 * interp.c (sim_monitor): Make mon_printf work.
1094
1095Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1096
1097 * sim-main.h (INSN_NAME): New arg `cpu'.
1098
1099Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1100
1101 * configure: Regenerated to track ../common/aclocal.m4 changes.
1102
1103Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1104
1105 * configure: Regenerated to track ../common/aclocal.m4 changes.
1106 * config.in: Ditto.
1107
1108Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1109
1110 * acconfig.h: New file.
1111 * configure.in: Reverted change of Apr 24; use sinclude again.
1112
1113Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1114
1115 * configure: Regenerated to track ../common/aclocal.m4 changes.
1116 * config.in: Ditto.
1117
1118Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1119
1120 * configure.in: Don't call sinclude.
1121
1122Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1123
1124 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1125
1126Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1127
1128 * mips.igen (ERET): Implement.
1129
1130 * interp.c (decode_coproc): Return sign-extended EPC.
1131
1132 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1133
1134 * interp.c (signal_exception): Do not ignore Trap.
1135 (signal_exception): On TRAP, restart at exception address.
1136 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1137 (signal_exception): Update.
1138 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1139 so that TRAP instructions are caught.
1140
1141Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1144 contains HI/LO access history.
1145 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1146 (HIACCESS, LOACCESS): Delete, replace with
1147 (HIHISTORY, LOHISTORY): New macros.
1148 (CHECKHILO): Delete all, moved to mips.igen
1149
1150 * gencode.c (build_instruction): Do not generate checks for
1151 correct HI/LO register usage.
1152
1153 * interp.c (old_engine_run): Delete checks for correct HI/LO
1154 register usage.
1155
1156 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1157 check_mf_cycles): New functions.
1158 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1159 do_divu, domultx, do_mult, do_multu): Use.
1160
1161 * tx.igen ("madd", "maddu"): Use.
1162
1163Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1164
1165 * mips.igen (DSRAV): Use function do_dsrav.
1166 (SRAV): Use new function do_srav.
1167
1168 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1169 (B): Sign extend 11 bit immediate.
1170 (EXT-B*): Shift 16 bit immediate left by 1.
1171 (ADDIU*): Don't sign extend immediate value.
1172
1173Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1174
1175 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1176
1177 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1178 functions.
1179
1180 * mips.igen (delayslot32, nullify_next_insn): New functions.
1181 (m16.igen): Always include.
1182 (do_*): Add more tracing.
1183
1184 * m16.igen (delayslot16): Add NIA argument, could be called by a
1185 32 bit MIPS16 instruction.
1186
1187 * interp.c (ifetch16): Move function from here.
1188 * sim-main.c (ifetch16): To here.
1189
1190 * sim-main.c (ifetch16, ifetch32): Update to match current
1191 implementations of LH, LW.
1192 (signal_exception): Don't print out incorrect hex value of illegal
1193 instruction.
1194
1195Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1196
1197 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1198 instruction.
1199
1200 * m16.igen: Implement MIPS16 instructions.
1201
1202 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1203 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1204 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1205 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1206 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1207 bodies of corresponding code from 32 bit insn to these. Also used
1208 by MIPS16 versions of functions.
1209
1210 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1211 (IMEM16): Drop NR argument from macro.
1212
1213Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1214
1215 * Makefile.in (SIM_OBJS): Add sim-main.o.
1216
1217 * sim-main.h (address_translation, load_memory, store_memory,
1218 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1219 as INLINE_SIM_MAIN.
1220 (pr_addr, pr_uword64): Declare.
1221 (sim-main.c): Include when H_REVEALS_MODULE_P.
1222
1223 * interp.c (address_translation, load_memory, store_memory,
1224 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1225 from here.
1226 * sim-main.c: To here. Fix compilation problems.
1227
1228 * configure.in: Enable inlining.
1229 * configure: Re-config.
1230
1231Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1232
1233 * configure: Regenerated to track ../common/aclocal.m4 changes.
1234
1235Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1236
1237 * mips.igen: Include tx.igen.
1238 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1239 * tx.igen: New file, contains MADD and MADDU.
1240
1241 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1242 the hardwired constant `7'.
1243 (store_memory): Ditto.
1244 (LOADDRMASK): Move definition to sim-main.h.
1245
1246 mips.igen (MTC0): Enable for r3900.
1247 (ADDU): Add trace.
1248
1249 mips.igen (do_load_byte): Delete.
1250 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1251 do_store_right): New functions.
1252 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1253
1254 configure.in: Let the tx39 use igen again.
1255 configure: Update.
1256
1257Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1260 not an address sized quantity. Return zero for cache sizes.
1261
1262Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1263
1264 * mips.igen (r3900): r3900 does not support 64 bit integer
1265 operations.
1266
1267Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1268
1269 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1270 than igen one.
1271 * configure : Rebuild.
1272
1273Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1274
1275 * configure: Regenerated to track ../common/aclocal.m4 changes.
1276
1277Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1278
1279 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1280
1281Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1282
1283 * configure: Regenerated to track ../common/aclocal.m4 changes.
1284 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1285
1286Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1287
1288 * configure: Regenerated to track ../common/aclocal.m4 changes.
1289
1290Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1291
1292 * interp.c (Max, Min): Comment out functions. Not yet used.
1293
1294Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * configure: Regenerated to track ../common/aclocal.m4 changes.
1297
1298Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1299
1300 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1301 configurable settings for stand-alone simulator.
1302
1303 * configure.in: Added X11 search, just in case.
1304
1305 * configure: Regenerated.
1306
1307Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1308
1309 * interp.c (sim_write, sim_read, load_memory, store_memory):
1310 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1311
1312Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1313
1314 * sim-main.h (GETFCC): Return an unsigned value.
1315
1316Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1317
1318 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1319 (DADD): Result destination is RD not RT.
1320
1321Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1322
1323 * sim-main.h (HIACCESS, LOACCESS): Always define.
1324
1325 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1326
1327 * interp.c (sim_info): Delete.
1328
1329Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1330
1331 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1332 (mips_option_handler): New argument `cpu'.
1333 (sim_open): Update call to sim_add_option_table.
1334
1335Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1336
1337 * mips.igen (CxC1): Add tracing.
1338
1339Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1340
1341 * sim-main.h (Max, Min): Declare.
1342
1343 * interp.c (Max, Min): New functions.
1344
1345 * mips.igen (BC1): Add tracing.
1346
1347Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1348
1349 * interp.c Added memory map for stack in vr4100
1350
1351Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1352
1353 * interp.c (load_memory): Add missing "break"'s.
1354
1355Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * interp.c (sim_store_register, sim_fetch_register): Pass in
1358 length parameter. Return -1.
1359
1360Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1361
1362 * interp.c: Added hardware init hook, fixed warnings.
1363
1364Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1367
1368Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1369
1370 * interp.c (ifetch16): New function.
1371
1372 * sim-main.h (IMEM32): Rename IMEM.
1373 (IMEM16_IMMED): Define.
1374 (IMEM16): Define.
1375 (DELAY_SLOT): Update.
1376
1377 * m16run.c (sim_engine_run): New file.
1378
1379 * m16.igen: All instructions except LB.
1380 (LB): Call do_load_byte.
1381 * mips.igen (do_load_byte): New function.
1382 (LB): Call do_load_byte.
1383
1384 * mips.igen: Move spec for insn bit size and high bit from here.
1385 * Makefile.in (tmp-igen, tmp-m16): To here.
1386
1387 * m16.dc: New file, decode mips16 instructions.
1388
1389 * Makefile.in (SIM_NO_ALL): Define.
1390 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1391
1392Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1395 point unit to 32 bit registers.
1396 * configure: Re-generate.
1397
1398Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1399
1400 * configure.in (sim_use_gen): Make IGEN the default simulator
1401 generator for generic 32 and 64 bit mips targets.
1402 * configure: Re-generate.
1403
1404Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1405
1406 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1407 bitsize.
1408
1409 * interp.c (sim_fetch_register, sim_store_register): Read/write
1410 FGR from correct location.
1411 (sim_open): Set size of FGR's according to
1412 WITH_TARGET_FLOATING_POINT_BITSIZE.
1413
1414 * sim-main.h (FGR): Store floating point registers in a separate
1415 array.
1416
1417Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1418
1419 * configure: Regenerated to track ../common/aclocal.m4 changes.
1420
1421Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1422
1423 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1424
1425 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1426
1427 * interp.c (pending_tick): New function. Deliver pending writes.
1428
1429 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1430 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1431 it can handle mixed sized quantites and single bits.
1432
1433Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * interp.c (oengine.h): Do not include when building with IGEN.
1436 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1437 (sim_info): Ditto for PROCESSOR_64BIT.
1438 (sim_monitor): Replace ut_reg with unsigned_word.
1439 (*): Ditto for t_reg.
1440 (LOADDRMASK): Define.
1441 (sim_open): Remove defunct check that host FP is IEEE compliant,
1442 using software to emulate floating point.
1443 (value_fpr, ...): Always compile, was conditional on HASFPU.
1444
1445Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1448 size.
1449
1450 * interp.c (SD, CPU): Define.
1451 (mips_option_handler): Set flags in each CPU.
1452 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1453 (sim_close): Do not clear STATE, deleted anyway.
1454 (sim_write, sim_read): Assume CPU zero's vm should be used for
1455 data transfers.
1456 (sim_create_inferior): Set the PC for all processors.
1457 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1458 argument.
1459 (mips16_entry): Pass correct nr of args to store_word, load_word.
1460 (ColdReset): Cold reset all cpu's.
1461 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1462 (sim_monitor, load_memory, store_memory, signal_exception): Use
1463 `CPU' instead of STATE_CPU.
1464
1465
1466 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1467 SD or CPU_.
1468
1469 * sim-main.h (signal_exception): Add sim_cpu arg.
1470 (SignalException*): Pass both SD and CPU to signal_exception.
1471 * interp.c (signal_exception): Update.
1472
1473 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1474 Ditto
1475 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1476 address_translation): Ditto
1477 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1478
1479Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1480
1481 * configure: Regenerated to track ../common/aclocal.m4 changes.
1482
1483Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1484
1485 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1486
1487 * mips.igen (model): Map processor names onto BFD name.
1488
1489 * sim-main.h (CPU_CIA): Delete.
1490 (SET_CIA, GET_CIA): Define
1491
1492Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1495 regiser.
1496
1497 * configure.in (default_endian): Configure a big-endian simulator
1498 by default.
1499 * configure: Re-generate.
1500
1501Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1502
1503 * configure: Regenerated to track ../common/aclocal.m4 changes.
1504
1505Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1506
1507 * interp.c (sim_monitor): Handle Densan monitor outbyte
1508 and inbyte functions.
1509
15101997-12-29 Felix Lee <flee@cygnus.com>
1511
1512 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1513
1514Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1515
1516 * Makefile.in (tmp-igen): Arrange for $zero to always be
1517 reset to zero after every instruction.
1518
1519Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1520
1521 * configure: Regenerated to track ../common/aclocal.m4 changes.
1522 * config.in: Ditto.
1523
1524Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1525
1526 * mips.igen (MSUB): Fix to work like MADD.
1527 * gencode.c (MSUB): Similarly.
1528
1529Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1530
1531 * configure: Regenerated to track ../common/aclocal.m4 changes.
1532
1533Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1536
1537Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * sim-main.h (sim-fpu.h): Include.
1540
1541 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1542 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1543 using host independant sim_fpu module.
1544
1545Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1546
1547 * interp.c (signal_exception): Report internal errors with SIGABRT
1548 not SIGQUIT.
1549
1550 * sim-main.h (C0_CONFIG): New register.
1551 (signal.h): No longer include.
1552
1553 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1554
1555Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1556
1557 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1558
1559Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1560
1561 * mips.igen: Tag vr5000 instructions.
1562 (ANDI): Was missing mipsIV model, fix assembler syntax.
1563 (do_c_cond_fmt): New function.
1564 (C.cond.fmt): Handle mips I-III which do not support CC field
1565 separatly.
1566 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1567 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1568 in IV3.2 spec.
1569 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1570 vr5000 which saves LO in a GPR separatly.
1571
1572 * configure.in (enable-sim-igen): For vr5000, select vr5000
1573 specific instructions.
1574 * configure: Re-generate.
1575
1576Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1577
1578 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1579
1580 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1581 fmt_uninterpreted_64 bit cases to switch. Convert to
1582 fmt_formatted,
1583
1584 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1585
1586 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1587 as specified in IV3.2 spec.
1588 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1589
1590Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1591
1592 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1593 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1594 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1595 PENDING_FILL versions of instructions. Simplify.
1596 (X): New function.
1597 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1598 instructions.
1599 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1600 a signed value.
1601 (MTHI, MFHI): Disable code checking HI-LO.
1602
1603 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1604 global.
1605 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1606
1607Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1608
1609 * gencode.c (build_mips16_operands): Replace IPC with cia.
1610
1611 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1612 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1613 IPC to `cia'.
1614 (UndefinedResult): Replace function with macro/function
1615 combination.
1616 (sim_engine_run): Don't save PC in IPC.
1617
1618 * sim-main.h (IPC): Delete.
1619
1620
1621 * interp.c (signal_exception, store_word, load_word,
1622 address_translation, load_memory, store_memory, cache_op,
1623 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1624 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1625 current instruction address - cia - argument.
1626 (sim_read, sim_write): Call address_translation directly.
1627 (sim_engine_run): Rename variable vaddr to cia.
1628 (signal_exception): Pass cia to sim_monitor
1629
1630 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1631 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1632 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1633
1634 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1635 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1636 SIM_ASSERT.
1637
1638 * interp.c (signal_exception): Pass restart address to
1639 sim_engine_restart.
1640
1641 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1642 idecode.o): Add dependency.
1643
1644 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1645 Delete definitions
1646 (DELAY_SLOT): Update NIA not PC with branch address.
1647 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1648
1649 * mips.igen: Use CIA not PC in branch calculations.
1650 (illegal): Call SignalException.
1651 (BEQ, ADDIU): Fix assembler.
1652
1653Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * m16.igen (JALX): Was missing.
1656
1657 * configure.in (enable-sim-igen): New configuration option.
1658 * configure: Re-generate.
1659
1660 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1661
1662 * interp.c (load_memory, store_memory): Delete parameter RAW.
1663 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1664 bypassing {load,store}_memory.
1665
1666 * sim-main.h (ByteSwapMem): Delete definition.
1667
1668 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1669
1670 * interp.c (sim_do_command, sim_commands): Delete mips specific
1671 commands. Handled by module sim-options.
1672
1673 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1674 (WITH_MODULO_MEMORY): Define.
1675
1676 * interp.c (sim_info): Delete code printing memory size.
1677
1678 * interp.c (mips_size): Nee sim_size, delete function.
1679 (power2): Delete.
1680 (monitor, monitor_base, monitor_size): Delete global variables.
1681 (sim_open, sim_close): Delete code creating monitor and other
1682 memory regions. Use sim-memopts module, via sim_do_commandf, to
1683 manage memory regions.
1684 (load_memory, store_memory): Use sim-core for memory model.
1685
1686 * interp.c (address_translation): Delete all memory map code
1687 except line forcing 32 bit addresses.
1688
1689Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1690
1691 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1692 trace options.
1693
1694 * interp.c (logfh, logfile): Delete globals.
1695 (sim_open, sim_close): Delete code opening & closing log file.
1696 (mips_option_handler): Delete -l and -n options.
1697 (OPTION mips_options): Ditto.
1698
1699 * interp.c (OPTION mips_options): Rename option trace to dinero.
1700 (mips_option_handler): Update.
1701
1702Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1703
1704 * interp.c (fetch_str): New function.
1705 (sim_monitor): Rewrite using sim_read & sim_write.
1706 (sim_open): Check magic number.
1707 (sim_open): Write monitor vectors into memory using sim_write.
1708 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1709 (sim_read, sim_write): Simplify - transfer data one byte at a
1710 time.
1711 (load_memory, store_memory): Clarify meaning of parameter RAW.
1712
1713 * sim-main.h (isHOST): Defete definition.
1714 (isTARGET): Mark as depreciated.
1715 (address_translation): Delete parameter HOST.
1716
1717 * interp.c (address_translation): Delete parameter HOST.
1718
1719Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * mips.igen:
1722
1723 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1724 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1725
1726Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1727
1728 * mips.igen: Add model filter field to records.
1729
1730Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1731
1732 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1733
1734 interp.c (sim_engine_run): Do not compile function sim_engine_run
1735 when WITH_IGEN == 1.
1736
1737 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1738 target architecture.
1739
1740 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1741 igen. Replace with configuration variables sim_igen_flags /
1742 sim_m16_flags.
1743
1744 * m16.igen: New file. Copy mips16 insns here.
1745 * mips.igen: From here.
1746
1747Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1750 to top.
1751 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1752
1753Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1754
1755 * gencode.c (build_instruction): Follow sim_write's lead in using
1756 BigEndianMem instead of !ByteSwapMem.
1757
1758Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1759
1760 * configure.in (sim_gen): Dependent on target, select type of
1761 generator. Always select old style generator.
1762
1763 configure: Re-generate.
1764
1765 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1766 targets.
1767 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1768 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1769 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1770 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1771 SIM_@sim_gen@_*, set by autoconf.
1772
1773Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1774
1775 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1776
1777 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1778 CURRENT_FLOATING_POINT instead.
1779
1780 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1781 (address_translation): Raise exception InstructionFetch when
1782 translation fails and isINSTRUCTION.
1783
1784 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1785 sim_engine_run): Change type of of vaddr and paddr to
1786 address_word.
1787 (address_translation, prefetch, load_memory, store_memory,
1788 cache_op): Change type of vAddr and pAddr to address_word.
1789
1790 * gencode.c (build_instruction): Change type of vaddr and paddr to
1791 address_word.
1792
1793Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1794
1795 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1796 macro to obtain result of ALU op.
1797
1798Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1799
1800 * interp.c (sim_info): Call profile_print.
1801
1802Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1803
1804 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1805
1806 * sim-main.h (WITH_PROFILE): Do not define, defined in
1807 common/sim-config.h. Use sim-profile module.
1808 (simPROFILE): Delete defintion.
1809
1810 * interp.c (PROFILE): Delete definition.
1811 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1812 (sim_close): Delete code writing profile histogram.
1813 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1814 Delete.
1815 (sim_engine_run): Delete code profiling the PC.
1816
1817Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818
1819 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1820
1821 * interp.c (sim_monitor): Make register pointers of type
1822 unsigned_word*.
1823
1824 * sim-main.h: Make registers of type unsigned_word not
1825 signed_word.
1826
1827Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1828
1829 * interp.c (sync_operation): Rename from SyncOperation, make
1830 global, add SD argument.
1831 (prefetch): Rename from Prefetch, make global, add SD argument.
1832 (decode_coproc): Make global.
1833
1834 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1835
1836 * gencode.c (build_instruction): Generate DecodeCoproc not
1837 decode_coproc calls.
1838
1839 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1840 (SizeFGR): Move to sim-main.h
1841 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1842 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1843 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1844 sim-main.h.
1845 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1846 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1847 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1848 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1849 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1850 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1851
1852 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1853 exception.
1854 (sim-alu.h): Include.
1855 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1856 (sim_cia): Typedef to instruction_address.
1857
1858Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * Makefile.in (interp.o): Rename generated file engine.c to
1861 oengine.c.
1862
1863 * interp.c: Update.
1864
1865Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1868
1869Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1870
1871 * gencode.c (build_instruction): For "FPSQRT", output correct
1872 number of arguments to Recip.
1873
1874Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1875
1876 * Makefile.in (interp.o): Depends on sim-main.h
1877
1878 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1879
1880 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1881 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1882 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1883 STATE, DSSTATE): Define
1884 (GPR, FGRIDX, ..): Define.
1885
1886 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1887 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1888 (GPR, FGRIDX, ...): Delete macros.
1889
1890 * interp.c: Update names to match defines from sim-main.h
1891
1892Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1893
1894 * interp.c (sim_monitor): Add SD argument.
1895 (sim_warning): Delete. Replace calls with calls to
1896 sim_io_eprintf.
1897 (sim_error): Delete. Replace calls with sim_io_error.
1898 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1899 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1900 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1901 argument.
1902 (mips_size): Rename from sim_size. Add SD argument.
1903
1904 * interp.c (simulator): Delete global variable.
1905 (callback): Delete global variable.
1906 (mips_option_handler, sim_open, sim_write, sim_read,
1907 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1908 sim_size,sim_monitor): Use sim_io_* not callback->*.
1909 (sim_open): ZALLOC simulator struct.
1910 (PROFILE): Do not define.
1911
1912Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1913
1914 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1915 support.h with corresponding code.
1916
1917 * sim-main.h (word64, uword64), support.h: Move definition to
1918 sim-main.h.
1919 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1920
1921 * support.h: Delete
1922 * Makefile.in: Update dependencies
1923 * interp.c: Do not include.
1924
1925Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * interp.c (address_translation, load_memory, store_memory,
1928 cache_op): Rename to from AddressTranslation et.al., make global,
1929 add SD argument
1930
1931 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1932 CacheOp): Define.
1933
1934 * interp.c (SignalException): Rename to signal_exception, make
1935 global.
1936
1937 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1938
1939 * sim-main.h (SignalException, SignalExceptionInterrupt,
1940 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1941 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1942 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1943 Define.
1944
1945 * interp.c, support.h: Use.
1946
1947Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1950 to value_fpr / store_fpr. Add SD argument.
1951 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1952 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1953
1954 * sim-main.h (ValueFPR, StoreFPR): Define.
1955
1956Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1957
1958 * interp.c (sim_engine_run): Check consistency between configure
1959 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1960 and HASFPU.
1961
1962 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1963 (mips_fpu): Configure WITH_FLOATING_POINT.
1964 (mips_endian): Configure WITH_TARGET_ENDIAN.
1965 * configure: Update.
1966
1967Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1968
1969 * configure: Regenerated to track ../common/aclocal.m4 changes.
1970
1971Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1972
1973 * configure: Regenerated.
1974
1975Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1976
1977 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1978
1979Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * gencode.c (print_igen_insn_models): Assume certain architectures
1982 include all mips* instructions.
1983 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1984 instruction.
1985
1986 * Makefile.in (tmp.igen): Add target. Generate igen input from
1987 gencode file.
1988
1989 * gencode.c (FEATURE_IGEN): Define.
1990 (main): Add --igen option. Generate output in igen format.
1991 (process_instructions): Format output according to igen option.
1992 (print_igen_insn_format): New function.
1993 (print_igen_insn_models): New function.
1994 (process_instructions): Only issue warnings and ignore
1995 instructions when no FEATURE_IGEN.
1996
1997Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2000 MIPS targets.
2001
2002Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * configure: Regenerated to track ../common/aclocal.m4 changes.
2005
2006Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2007
2008 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2009 SIM_RESERVED_BITS): Delete, moved to common.
2010 (SIM_EXTRA_CFLAGS): Update.
2011
2012Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * configure.in: Configure non-strict memory alignment.
2015 * configure: Regenerated to track ../common/aclocal.m4 changes.
2016
2017Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * configure: Regenerated to track ../common/aclocal.m4 changes.
2020
2021Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2022
2023 * gencode.c (SDBBP,DERET): Added (3900) insns.
2024 (RFE): Turn on for 3900.
2025 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2026 (dsstate): Made global.
2027 (SUBTARGET_R3900): Added.
2028 (CANCELDELAYSLOT): New.
2029 (SignalException): Ignore SystemCall rather than ignore and
2030 terminate. Add DebugBreakPoint handling.
2031 (decode_coproc): New insns RFE, DERET; and new registers Debug
2032 and DEPC protected by SUBTARGET_R3900.
2033 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2034 bits explicitly.
2035 * Makefile.in,configure.in: Add mips subtarget option.
2036 * configure: Update.
2037
2038Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2039
2040 * gencode.c: Add r3900 (tx39).
2041
2042
2043Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2044
2045 * gencode.c (build_instruction): Don't need to subtract 4 for
2046 JALR, just 2.
2047
2048Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2049
2050 * interp.c: Correct some HASFPU problems.
2051
2052Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2053
2054 * configure: Regenerated to track ../common/aclocal.m4 changes.
2055
2056Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2057
2058 * interp.c (mips_options): Fix samples option short form, should
2059 be `x'.
2060
2061Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2062
2063 * interp.c (sim_info): Enable info code. Was just returning.
2064
2065Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2066
2067 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2068 MFC0.
2069
2070Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2071
2072 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2073 constants.
2074 (build_instruction): Ditto for LL.
2075
2076Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2077
2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
2079
2080Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2081
2082 * configure: Regenerated to track ../common/aclocal.m4 changes.
2083 * config.in: Ditto.
2084
2085Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2086
2087 * interp.c (sim_open): Add call to sim_analyze_program, update
2088 call to sim_config.
2089
2090Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2091
2092 * interp.c (sim_kill): Delete.
2093 (sim_create_inferior): Add ABFD argument. Set PC from same.
2094 (sim_load): Move code initializing trap handlers from here.
2095 (sim_open): To here.
2096 (sim_load): Delete, use sim-hload.c.
2097
2098 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2099
2100Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * configure: Regenerated to track ../common/aclocal.m4 changes.
2103 * config.in: Ditto.
2104
2105Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * interp.c (sim_open): Add ABFD argument.
2108 (sim_load): Move call to sim_config from here.
2109 (sim_open): To here. Check return status.
2110
2111Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2112
2113 * gencode.c (build_instruction): Two arg MADD should
2114 not assign result to $0.
2115
2116Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2117
2118 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2119 * sim/mips/configure.in: Regenerate.
2120
2121Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2122
2123 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2124 signed8, unsigned8 et.al. types.
2125
2126 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2127 hosts when selecting subreg.
2128
2129Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2130
2131 * interp.c (sim_engine_run): Reset the ZERO register to zero
2132 regardless of FEATURE_WARN_ZERO.
2133 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2134
2135Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2136
2137 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2138 (SignalException): For BreakPoints ignore any mode bits and just
2139 save the PC.
2140 (SignalException): Always set the CAUSE register.
2141
2142Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143
2144 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2145 exception has been taken.
2146
2147 * interp.c: Implement the ERET and mt/f sr instructions.
2148
2149Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2150
2151 * interp.c (SignalException): Don't bother restarting an
2152 interrupt.
2153
2154Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155
2156 * interp.c (SignalException): Really take an interrupt.
2157 (interrupt_event): Only deliver interrupts when enabled.
2158
2159Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160
2161 * interp.c (sim_info): Only print info when verbose.
2162 (sim_info) Use sim_io_printf for output.
2163
2164Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165
2166 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2167 mips architectures.
2168
2169Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170
2171 * interp.c (sim_do_command): Check for common commands if a
2172 simulator specific command fails.
2173
2174Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2175
2176 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2177 and simBE when DEBUG is defined.
2178
2179Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * interp.c (interrupt_event): New function. Pass exception event
2182 onto exception handler.
2183
2184 * configure.in: Check for stdlib.h.
2185 * configure: Regenerate.
2186
2187 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2188 variable declaration.
2189 (build_instruction): Initialize memval1.
2190 (build_instruction): Add UNUSED attribute to byte, bigend,
2191 reverse.
2192 (build_operands): Ditto.
2193
2194 * interp.c: Fix GCC warnings.
2195 (sim_get_quit_code): Delete.
2196
2197 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2198 * Makefile.in: Ditto.
2199 * configure: Re-generate.
2200
2201 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2202
2203Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2204
2205 * interp.c (mips_option_handler): New function parse argumes using
2206 sim-options.
2207 (myname): Replace with STATE_MY_NAME.
2208 (sim_open): Delete check for host endianness - performed by
2209 sim_config.
2210 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2211 (sim_open): Move much of the initialization from here.
2212 (sim_load): To here. After the image has been loaded and
2213 endianness set.
2214 (sim_open): Move ColdReset from here.
2215 (sim_create_inferior): To here.
2216 (sim_open): Make FP check less dependant on host endianness.
2217
2218 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2219 run.
2220 * interp.c (sim_set_callbacks): Delete.
2221
2222 * interp.c (membank, membank_base, membank_size): Replace with
2223 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2224 (sim_open): Remove call to callback->init. gdb/run do this.
2225
2226 * interp.c: Update
2227
2228 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2229
2230 * interp.c (big_endian_p): Delete, replaced by
2231 current_target_byte_order.
2232
2233Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234
2235 * interp.c (host_read_long, host_read_word, host_swap_word,
2236 host_swap_long): Delete. Using common sim-endian.
2237 (sim_fetch_register, sim_store_register): Use H2T.
2238 (pipeline_ticks): Delete. Handled by sim-events.
2239 (sim_info): Update.
2240 (sim_engine_run): Update.
2241
2242Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2245 reason from here.
2246 (SignalException): To here. Signal using sim_engine_halt.
2247 (sim_stop_reason): Delete, moved to common.
2248
2249Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2250
2251 * interp.c (sim_open): Add callback argument.
2252 (sim_set_callbacks): Delete SIM_DESC argument.
2253 (sim_size): Ditto.
2254
2255Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2256
2257 * Makefile.in (SIM_OBJS): Add common modules.
2258
2259 * interp.c (sim_set_callbacks): Also set SD callback.
2260 (set_endianness, xfer_*, swap_*): Delete.
2261 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2262 Change to functions using sim-endian macros.
2263 (control_c, sim_stop): Delete, use common version.
2264 (simulate): Convert into.
2265 (sim_engine_run): This function.
2266 (sim_resume): Delete.
2267
2268 * interp.c (simulation): New variable - the simulator object.
2269 (sim_kind): Delete global - merged into simulation.
2270 (sim_load): Cleanup. Move PC assignment from here.
2271 (sim_create_inferior): To here.
2272
2273 * sim-main.h: New file.
2274 * interp.c (sim-main.h): Include.
2275
2276Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2277
2278 * configure: Regenerated to track ../common/aclocal.m4 changes.
2279
2280Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2281
2282 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2283
2284Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2285
2286 * gencode.c (build_instruction): DIV instructions: check
2287 for division by zero and integer overflow before using
2288 host's division operation.
2289
2290Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2291
2292 * Makefile.in (SIM_OBJS): Add sim-load.o.
2293 * interp.c: #include bfd.h.
2294 (target_byte_order): Delete.
2295 (sim_kind, myname, big_endian_p): New static locals.
2296 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2297 after argument parsing. Recognize -E arg, set endianness accordingly.
2298 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2299 load file into simulator. Set PC from bfd.
2300 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2301 (set_endianness): Use big_endian_p instead of target_byte_order.
2302
2303Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2304
2305 * interp.c (sim_size): Delete prototype - conflicts with
2306 definition in remote-sim.h. Correct definition.
2307
2308Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2309
2310 * configure: Regenerated to track ../common/aclocal.m4 changes.
2311 * config.in: Ditto.
2312
2313Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2314
2315 * interp.c (sim_open): New arg `kind'.
2316
2317 * configure: Regenerated to track ../common/aclocal.m4 changes.
2318
2319Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2320
2321 * configure: Regenerated to track ../common/aclocal.m4 changes.
2322
2323Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2324
2325 * interp.c (sim_open): Set optind to 0 before calling getopt.
2326
2327Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2328
2329 * configure: Regenerated to track ../common/aclocal.m4 changes.
2330
2331Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2332
2333 * interp.c : Replace uses of pr_addr with pr_uword64
2334 where the bit length is always 64 independent of SIM_ADDR.
2335 (pr_uword64) : added.
2336
2337Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2338
2339 * configure: Re-generate.
2340
2341Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2342
2343 * configure: Regenerate to track ../common/aclocal.m4 changes.
2344
2345Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2346
2347 * interp.c (sim_open): New SIM_DESC result. Argument is now
2348 in argv form.
2349 (other sim_*): New SIM_DESC argument.
2350
2351Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2352
2353 * interp.c: Fix printing of addresses for non-64-bit targets.
2354 (pr_addr): Add function to print address based on size.
2355
2356Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2357
2358 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2359
2360Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2361
2362 * gencode.c (build_mips16_operands): Correct computation of base
2363 address for extended PC relative instruction.
2364
2365Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2366
2367 * interp.c (mips16_entry): Add support for floating point cases.
2368 (SignalException): Pass floating point cases to mips16_entry.
2369 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2370 registers.
2371 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2372 or fmt_word.
2373 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2374 and then set the state to fmt_uninterpreted.
2375 (COP_SW): Temporarily set the state to fmt_word while calling
2376 ValueFPR.
2377
2378Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2379
2380 * gencode.c (build_instruction): The high order may be set in the
2381 comparison flags at any ISA level, not just ISA 4.
2382
2383Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2384
2385 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2386 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2387 * configure.in: sinclude ../common/aclocal.m4.
2388 * configure: Regenerated.
2389
2390Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2391
2392 * configure: Rebuild after change to aclocal.m4.
2393
2394Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2395
2396 * configure configure.in Makefile.in: Update to new configure
2397 scheme which is more compatible with WinGDB builds.
2398 * configure.in: Improve comment on how to run autoconf.
2399 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2400 * Makefile.in: Use autoconf substitution to install common
2401 makefile fragment.
2402
2403Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2404
2405 * gencode.c (build_instruction): Use BigEndianCPU instead of
2406 ByteSwapMem.
2407
2408Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2409
2410 * interp.c (sim_monitor): Make output to stdout visible in
2411 wingdb's I/O log window.
2412
2413Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2414
2415 * support.h: Undo previous change to SIGTRAP
2416 and SIGQUIT values.
2417
2418Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2419
2420 * interp.c (store_word, load_word): New static functions.
2421 (mips16_entry): New static function.
2422 (SignalException): Look for mips16 entry and exit instructions.
2423 (simulate): Use the correct index when setting fpr_state after
2424 doing a pending move.
2425
2426Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2427
2428 * interp.c: Fix byte-swapping code throughout to work on
2429 both little- and big-endian hosts.
2430
2431Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2432
2433 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2434 with gdb/config/i386/xm-windows.h.
2435
2436Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2437
2438 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2439 that messes up arithmetic shifts.
2440
2441Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2442
2443 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2444 SIGTRAP and SIGQUIT for _WIN32.
2445
2446Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2447
2448 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2449 force a 64 bit multiplication.
2450 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2451 destination register is 0, since that is the default mips16 nop
2452 instruction.
2453
2454Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2455
2456 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2457 (build_endian_shift): Don't check proc64.
2458 (build_instruction): Always set memval to uword64. Cast op2 to
2459 uword64 when shifting it left in memory instructions. Always use
2460 the same code for stores--don't special case proc64.
2461
2462 * gencode.c (build_mips16_operands): Fix base PC value for PC
2463 relative operands.
2464 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2465 jal instruction.
2466 * interp.c (simJALDELAYSLOT): Define.
2467 (JALDELAYSLOT): Define.
2468 (INDELAYSLOT, INJALDELAYSLOT): Define.
2469 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2470
2471Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2472
2473 * interp.c (sim_open): add flush_cache as a PMON routine
2474 (sim_monitor): handle flush_cache by ignoring it
2475
2476Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2477
2478 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2479 BigEndianMem.
2480 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2481 (BigEndianMem): Rename to ByteSwapMem and change sense.
2482 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2483 BigEndianMem references to !ByteSwapMem.
2484 (set_endianness): New function, with prototype.
2485 (sim_open): Call set_endianness.
2486 (sim_info): Use simBE instead of BigEndianMem.
2487 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2488 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2489 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2490 ifdefs, keeping the prototype declaration.
2491 (swap_word): Rewrite correctly.
2492 (ColdReset): Delete references to CONFIG. Delete endianness related
2493 code; moved to set_endianness.
2494
2495Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2496
2497 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2498 * interp.c (CHECKHILO): Define away.
2499 (simSIGINT): New macro.
2500 (membank_size): Increase from 1MB to 2MB.
2501 (control_c): New function.
2502 (sim_resume): Rename parameter signal to signal_number. Add local
2503 variable prev. Call signal before and after simulate.
2504 (sim_stop_reason): Add simSIGINT support.
2505 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2506 functions always.
2507 (sim_warning): Delete call to SignalException. Do call printf_filtered
2508 if logfh is NULL.
2509 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2510 a call to sim_warning.
2511
2512Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2513
2514 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2515 16 bit instructions.
2516
2517Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2518
2519 Add support for mips16 (16 bit MIPS implementation):
2520 * gencode.c (inst_type): Add mips16 instruction encoding types.
2521 (GETDATASIZEINSN): Define.
2522 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2523 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2524 mtlo.
2525 (MIPS16_DECODE): New table, for mips16 instructions.
2526 (bitmap_val): New static function.
2527 (struct mips16_op): Define.
2528 (mips16_op_table): New table, for mips16 operands.
2529 (build_mips16_operands): New static function.
2530 (process_instructions): If PC is odd, decode a mips16
2531 instruction. Break out instruction handling into new
2532 build_instruction function.
2533 (build_instruction): New static function, broken out of
2534 process_instructions. Check modifiers rather than flags for SHIFT
2535 bit count and m[ft]{hi,lo} direction.
2536 (usage): Pass program name to fprintf.
2537 (main): Remove unused variable this_option_optind. Change
2538 ``*loptarg++'' to ``loptarg++''.
2539 (my_strtoul): Parenthesize && within ||.
2540 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2541 (simulate): If PC is odd, fetch a 16 bit instruction, and
2542 increment PC by 2 rather than 4.
2543 * configure.in: Add case for mips16*-*-*.
2544 * configure: Rebuild.
2545
2546Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2547
2548 * interp.c: Allow -t to enable tracing in standalone simulator.
2549 Fix garbage output in trace file and error messages.
2550
2551Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2552
2553 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2554 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2555 * configure.in: Simplify using macros in ../common/aclocal.m4.
2556 * configure: Regenerated.
2557 * tconfig.in: New file.
2558
2559Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2560
2561 * interp.c: Fix bugs in 64-bit port.
2562 Use ansi function declarations for msvc compiler.
2563 Initialize and test file pointer in trace code.
2564 Prevent duplicate definition of LAST_EMED_REGNUM.
2565
2566Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2567
2568 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2569
2570Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2571
2572 * interp.c (SignalException): Check for explicit terminating
2573 breakpoint value.
2574 * gencode.c: Pass instruction value through SignalException()
2575 calls for Trap, Breakpoint and Syscall.
2576
2577Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2578
2579 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2580 only used on those hosts that provide it.
2581 * configure.in: Add sqrt() to list of functions to be checked for.
2582 * config.in: Re-generated.
2583 * configure: Re-generated.
2584
2585Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2586
2587 * gencode.c (process_instructions): Call build_endian_shift when
2588 expanding STORE RIGHT, to fix swr.
2589 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2590 clear the high bits.
2591 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2592 Fix float to int conversions to produce signed values.
2593
2594Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2595
2596 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2597 (process_instructions): Correct handling of nor instruction.
2598 Correct shift count for 32 bit shift instructions. Correct sign
2599 extension for arithmetic shifts to not shift the number of bits in
2600 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2601 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2602 Fix madd.
2603 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2604 It's OK to have a mult follow a mult. What's not OK is to have a
2605 mult follow an mfhi.
2606 (Convert): Comment out incorrect rounding code.
2607
2608Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2609
2610 * interp.c (sim_monitor): Improved monitor printf
2611 simulation. Tidied up simulator warnings, and added "--log" option
2612 for directing warning message output.
2613 * gencode.c: Use sim_warning() rather than WARNING macro.
2614
2615Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2616
2617 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2618 getopt1.o, rather than on gencode.c. Link objects together.
2619 Don't link against -liberty.
2620 (gencode.o, getopt.o, getopt1.o): New targets.
2621 * gencode.c: Include <ctype.h> and "ansidecl.h".
2622 (AND): Undefine after including "ansidecl.h".
2623 (ULONG_MAX): Define if not defined.
2624 (OP_*): Don't define macros; now defined in opcode/mips.h.
2625 (main): Call my_strtoul rather than strtoul.
2626 (my_strtoul): New static function.
2627
2628Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2629
2630 * gencode.c (process_instructions): Generate word64 and uword64
2631 instead of `long long' and `unsigned long long' data types.
2632 * interp.c: #include sysdep.h to get signals, and define default
2633 for SIGBUS.
2634 * (Convert): Work around for Visual-C++ compiler bug with type
2635 conversion.
2636 * support.h: Make things compile under Visual-C++ by using
2637 __int64 instead of `long long'. Change many refs to long long
2638 into word64/uword64 typedefs.
2639
2640Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2641
2642 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2643 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2644 (docdir): Removed.
2645 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2646 (AC_PROG_INSTALL): Added.
2647 (AC_PROG_CC): Moved to before configure.host call.
2648 * configure: Rebuilt.
2649
2650Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2651
2652 * configure.in: Define @SIMCONF@ depending on mips target.
2653 * configure: Rebuild.
2654 * Makefile.in (run): Add @SIMCONF@ to control simulator
2655 construction.
2656 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2657 * interp.c: Remove some debugging, provide more detailed error
2658 messages, update memory accesses to use LOADDRMASK.
2659
2660Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2661
2662 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2663 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2664 stamp-h.
2665 * configure: Rebuild.
2666 * config.in: New file, generated by autoheader.
2667 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2668 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2669 HAVE_ANINT and HAVE_AINT, as appropriate.
2670 * Makefile.in (run): Use @LIBS@ rather than -lm.
2671 (interp.o): Depend upon config.h.
2672 (Makefile): Just rebuild Makefile.
2673 (clean): Remove stamp-h.
2674 (mostlyclean): Make the same as clean, not as distclean.
2675 (config.h, stamp-h): New targets.
2676
2677Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2678
2679 * interp.c (ColdReset): Fix boolean test. Make all simulator
2680 globals static.
2681
2682Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2683
2684 * interp.c (xfer_direct_word, xfer_direct_long,
2685 swap_direct_word, swap_direct_long, xfer_big_word,
2686 xfer_big_long, xfer_little_word, xfer_little_long,
2687 swap_word,swap_long): Added.
2688 * interp.c (ColdReset): Provide function indirection to
2689 host<->simulated_target transfer routines.
2690 * interp.c (sim_store_register, sim_fetch_register): Updated to
2691 make use of indirected transfer routines.
2692
2693Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2694
2695 * gencode.c (process_instructions): Ensure FP ABS instruction
2696 recognised.
2697 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2698 system call support.
2699
2700Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2701
2702 * interp.c (sim_do_command): Complain if callback structure not
2703 initialised.
2704
2705Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2706
2707 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2708 support for Sun hosts.
2709 * Makefile.in (gencode): Ensure the host compiler and libraries
2710 used for cross-hosted build.
2711
2712Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2713
2714 * interp.c, gencode.c: Some more (TODO) tidying.
2715
2716Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2717
2718 * gencode.c, interp.c: Replaced explicit long long references with
2719 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2720 * support.h (SET64LO, SET64HI): Macros added.
2721
2722Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2723
2724 * configure: Regenerate with autoconf 2.7.
2725
2726Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2727
2728 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2729 * support.h: Remove superfluous "1" from #if.
2730 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2731
2732Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2733
2734 * interp.c (StoreFPR): Control UndefinedResult() call on
2735 WARN_RESULT manifest.
2736
2737Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2738
2739 * gencode.c: Tidied instruction decoding, and added FP instruction
2740 support.
2741
2742 * interp.c: Added dineroIII, and BSD profiling support. Also
2743 run-time FP handling.
2744
2745Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2746
2747 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2748 gencode.c, interp.c, support.h: created.
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