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b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
b90efa5b 2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
b99bd4ef
NC		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC		 6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC		 8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC		 14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC		 19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC		 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC		 31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b
RE		 34#include "opcode/arm.h"
35
b99bd4ef
NC		 36#ifdef OBJ_ELF
37#include "elf/arm.h"
a394c00f 38#include "dw2gencfi.h"
b99bd4ef
NC		 39#endif
40
f0927246
NC		 41#include "dwarf2dbg.h"
42
7ed4c4c5
NC		 43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
c19d1205
ZW		 51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
7ed4c4c5 55 /* The segment containing the function. */
c19d1205
ZW		 56 segT saved_seg;
57 subsegT saved_subseg;
7ed4c4c5
NC		 58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
c19d1205
ZW		 60 int opcode_count;
61 int opcode_alloc;
7ed4c4c5 62 /* The number of bytes pushed to the stack. */
c19d1205 63 offsetT frame_size;
7ed4c4c5
NC		 64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
c19d1205 67 offsetT pending_offset;
7ed4c4c5 68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW		 69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
7ed4c4c5 72 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 73 unsigned fp_used:1;
7ed4c4c5 74 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 75 unsigned sp_restored:1;
7ed4c4c5
NC		 76} unwind;
77
8b1ad454
NC		 78#endif /* OBJ_ELF */
79
4962c51a
MS		 80/* Results from operand parsing worker functions. */
81
82typedef enum
83{
84 PARSE_OPERAND_SUCCESS,
85 PARSE_OPERAND_FAIL,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87} parse_operand_result;
88
33a392fb
PB		 89enum arm_float_abi
90{
91 ARM_FLOAT_ABI_HARD,
92 ARM_FLOAT_ABI_SOFTFP,
93 ARM_FLOAT_ABI_SOFT
94};
95
c19d1205 96/* Types of processor to assemble for. */
b99bd4ef 97#ifndef CPU_DEFAULT
8a59fff3 98/* The code that was here used to select a default CPU depending on compiler
fa94de6b 99 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD		 100 changing gas' default behaviour depending upon the build host.
101
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
b99bd4ef
NC		 104#endif
105
106#ifndef FPU_DEFAULT
c820d418
MM		 107# ifdef TE_LINUX
108# define FPU_DEFAULT FPU_ARCH_FPA
109# elif defined (TE_NetBSD)
110# ifdef OBJ_ELF
111# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
112# else
113 /* Legacy a.out format. */
114# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
115# endif
4e7fd91e
PB		 116# elif defined (TE_VXWORKS)
117# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM		 118# else
119 /* For backwards compatibility, default to FPA. */
120# define FPU_DEFAULT FPU_ARCH_FPA
121# endif
122#endif /* ifndef FPU_DEFAULT */
b99bd4ef 123
c19d1205 124#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 125
e74cfd16
PB		 126static arm_feature_set cpu_variant;
127static arm_feature_set arm_arch_used;
128static arm_feature_set thumb_arch_used;
b99bd4ef 129
b99bd4ef 130/* Flags stored in private area of BFD structure. */
c19d1205
ZW		 131static int uses_apcs_26 = FALSE;
132static int atpcs = FALSE;
b34976b6
AM		 133static int support_interwork = FALSE;
134static int uses_apcs_float = FALSE;
c19d1205 135static int pic_code = FALSE;
845b51d6 136static int fix_v4bx = FALSE;
278df34e
NS		 137/* Warn on using deprecated features. */
138static int warn_on_deprecated = TRUE;
139
2e6976a8
DG		 140/* Understand CodeComposer Studio assembly syntax. */
141bfd_boolean codecomposer_syntax = FALSE;
03b1477f
RE		 142
143/* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
145 assembly flags. */
e74cfd16
PB		 146static const arm_feature_set *legacy_cpu = NULL;
147static const arm_feature_set *legacy_fpu = NULL;
148
149static const arm_feature_set *mcpu_cpu_opt = NULL;
150static const arm_feature_set *mcpu_fpu_opt = NULL;
151static const arm_feature_set *march_cpu_opt = NULL;
152static const arm_feature_set *march_fpu_opt = NULL;
153static const arm_feature_set *mfpu_opt = NULL;
7a1d4c38 154static const arm_feature_set *object_arch = NULL;
e74cfd16
PB		 155
156/* Constants for known architecture features. */
157static const arm_feature_set fpu_default = FPU_DEFAULT;
158static const arm_feature_set fpu_arch_vfp_v1 = FPU_ARCH_VFP_V1;
159static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
5287ad62
JB		 160static const arm_feature_set fpu_arch_vfp_v3 = FPU_ARCH_VFP_V3;
161static const arm_feature_set fpu_arch_neon_v1 = FPU_ARCH_NEON_V1;
e74cfd16
PB		 162static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
163static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
164static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
165static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
166
167#ifdef CPU_DEFAULT
168static const arm_feature_set cpu_default = CPU_DEFAULT;
169#endif
170
171static const arm_feature_set arm_ext_v1 = ARM_FEATURE (ARM_EXT_V1, 0);
172static const arm_feature_set arm_ext_v2 = ARM_FEATURE (ARM_EXT_V1, 0);
173static const arm_feature_set arm_ext_v2s = ARM_FEATURE (ARM_EXT_V2S, 0);
174static const arm_feature_set arm_ext_v3 = ARM_FEATURE (ARM_EXT_V3, 0);
175static const arm_feature_set arm_ext_v3m = ARM_FEATURE (ARM_EXT_V3M, 0);
176static const arm_feature_set arm_ext_v4 = ARM_FEATURE (ARM_EXT_V4, 0);
177static const arm_feature_set arm_ext_v4t = ARM_FEATURE (ARM_EXT_V4T, 0);
178static const arm_feature_set arm_ext_v5 = ARM_FEATURE (ARM_EXT_V5, 0);
179static const arm_feature_set arm_ext_v4t_5 =
180 ARM_FEATURE (ARM_EXT_V4T | ARM_EXT_V5, 0);
181static const arm_feature_set arm_ext_v5t = ARM_FEATURE (ARM_EXT_V5T, 0);
182static const arm_feature_set arm_ext_v5e = ARM_FEATURE (ARM_EXT_V5E, 0);
183static const arm_feature_set arm_ext_v5exp = ARM_FEATURE (ARM_EXT_V5ExP, 0);
184static const arm_feature_set arm_ext_v5j = ARM_FEATURE (ARM_EXT_V5J, 0);
185static const arm_feature_set arm_ext_v6 = ARM_FEATURE (ARM_EXT_V6, 0);
186static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
e74cfd16 187static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
b2a5fbdc 188static const arm_feature_set arm_ext_v6m = ARM_FEATURE (ARM_EXT_V6M, 0);
62b3e311 189static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
9e3c6df6 190static const arm_feature_set arm_ext_v6_dsp = ARM_FEATURE (ARM_EXT_V6_DSP, 0);
7e806470
PB		 191static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
192static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
62b3e311
PB		 193static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
194static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
195static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
196static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
9e3c6df6 197static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
bca38921 198static const arm_feature_set arm_ext_v8 = ARM_FEATURE (ARM_EXT_V8, 0);
7e806470 199static const arm_feature_set arm_ext_m =
b2a5fbdc 200 ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, 0);
60e5ef9f 201static const arm_feature_set arm_ext_mp = ARM_FEATURE (ARM_EXT_MP, 0);
f4c65163 202static const arm_feature_set arm_ext_sec = ARM_FEATURE (ARM_EXT_SEC, 0);
b2a5fbdc 203static const arm_feature_set arm_ext_os = ARM_FEATURE (ARM_EXT_OS, 0);
eea54501 204static const arm_feature_set arm_ext_adiv = ARM_FEATURE (ARM_EXT_ADIV, 0);
90ec0d68 205static const arm_feature_set arm_ext_virt = ARM_FEATURE (ARM_EXT_VIRT, 0);
e74cfd16
PB		 206
207static const arm_feature_set arm_arch_any = ARM_ANY;
208static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
209static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
210static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
251665fc 211static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
e74cfd16 212
2d447fca
JM		 213static const arm_feature_set arm_cext_iwmmxt2 =
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2);
e74cfd16
PB		 215static const arm_feature_set arm_cext_iwmmxt =
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT);
217static const arm_feature_set arm_cext_xscale =
218 ARM_FEATURE (0, ARM_CEXT_XSCALE);
219static const arm_feature_set arm_cext_maverick =
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK);
221static const arm_feature_set fpu_fpa_ext_v1 = ARM_FEATURE (0, FPU_FPA_EXT_V1);
222static const arm_feature_set fpu_fpa_ext_v2 = ARM_FEATURE (0, FPU_FPA_EXT_V2);
223static const arm_feature_set fpu_vfp_ext_v1xd =
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD);
225static const arm_feature_set fpu_vfp_ext_v1 = ARM_FEATURE (0, FPU_VFP_EXT_V1);
226static const arm_feature_set fpu_vfp_ext_v2 = ARM_FEATURE (0, FPU_VFP_EXT_V2);
62f3b8c8 227static const arm_feature_set fpu_vfp_ext_v3xd = ARM_FEATURE (0, FPU_VFP_EXT_V3xD);
5287ad62 228static const arm_feature_set fpu_vfp_ext_v3 = ARM_FEATURE (0, FPU_VFP_EXT_V3);
b1cc4aeb
PB		 229static const arm_feature_set fpu_vfp_ext_d32 =
230 ARM_FEATURE (0, FPU_VFP_EXT_D32);
5287ad62
JB		 231static const arm_feature_set fpu_neon_ext_v1 = ARM_FEATURE (0, FPU_NEON_EXT_V1);
232static const arm_feature_set fpu_vfp_v3_or_neon_ext =
233 ARM_FEATURE (0, FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
62f3b8c8
PB		 234static const arm_feature_set fpu_vfp_fp16 = ARM_FEATURE (0, FPU_VFP_EXT_FP16);
235static const arm_feature_set fpu_neon_ext_fma = ARM_FEATURE (0, FPU_NEON_EXT_FMA);
236static const arm_feature_set fpu_vfp_ext_fma = ARM_FEATURE (0, FPU_VFP_EXT_FMA);
bca38921
MGD		 237static const arm_feature_set fpu_vfp_ext_armv8 =
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8);
a715796b
TG		 239static const arm_feature_set fpu_vfp_ext_armv8xd =
240 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8xD);
bca38921
MGD		 241static const arm_feature_set fpu_neon_ext_armv8 =
242 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8);
243static const arm_feature_set fpu_crypto_ext_armv8 =
244 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8);
dd5181d5
KT		 245static const arm_feature_set crc_ext_armv8 =
246 ARM_FEATURE (0, CRC_EXT_ARMV8);
e74cfd16 247
33a392fb 248static int mfloat_abi_opt = -1;
e74cfd16
PB		 249/* Record user cpu selection for object attributes. */
250static arm_feature_set selected_cpu = ARM_ARCH_NONE;
ee065d83
PB		 251/* Must be long enough to hold any of the names in arm_cpus. */
252static char selected_cpu_name[16];
8d67f500 253
aacf0b33
KT		 254extern FLONUM_TYPE generic_floating_point_number;
255
8d67f500
NC		 256/* Return if no cpu was selected on command-line. */
257static bfd_boolean
258no_cpu_selected (void)
259{
260 return selected_cpu.core == arm_arch_none.core
261 && selected_cpu.coproc == arm_arch_none.coproc;
262}
263
7cc69913 264#ifdef OBJ_ELF
deeaaff8
DJ		 265# ifdef EABI_DEFAULT
266static int meabi_flags = EABI_DEFAULT;
267# else
d507cf36 268static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 269# endif
e1da3f5b 270
ee3c0378
AS		 271static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
272
e1da3f5b 273bfd_boolean
5f4273c7 274arm_is_eabi (void)
e1da3f5b
PB		 275{
276 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
277}
7cc69913 278#endif
b99bd4ef 279
b99bd4ef 280#ifdef OBJ_ELF
c19d1205 281/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC		 282symbolS * GOT_symbol;
283#endif
284
b99bd4ef
NC		 285/* 0: assemble for ARM,
286 1: assemble for Thumb,
287 2: assemble for Thumb even though target CPU does not support thumb
288 instructions. */
289static int thumb_mode = 0;
8dc2430f
NC		 290/* A value distinct from the possible values for thumb_mode that we
291 can use to record whether thumb_mode has been copied into the
292 tc_frag_data field of a frag. */
293#define MODE_RECORDED (1 << 4)
b99bd4ef 294
e07e6e58
NC		 295/* Specifies the intrinsic IT insn behavior mode. */
296enum implicit_it_mode
297{
298 IMPLICIT_IT_MODE_NEVER = 0x00,
299 IMPLICIT_IT_MODE_ARM = 0x01,
300 IMPLICIT_IT_MODE_THUMB = 0x02,
301 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
302};
303static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
304
c19d1205
ZW		 305/* If unified_syntax is true, we are processing the new unified
306 ARM/Thumb syntax. Important differences from the old ARM mode:
307
308 - Immediate operands do not require a # prefix.
309 - Conditional affixes always appear at the end of the
310 instruction. (For backward compatibility, those instructions
311 that formerly had them in the middle, continue to accept them
312 there.)
313 - The IT instruction may appear, and if it does is validated
314 against subsequent conditional affixes. It does not generate
315 machine code.
316
317 Important differences from the old Thumb mode:
318
319 - Immediate operands do not require a # prefix.
320 - Most of the V6T2 instructions are only available in unified mode.
321 - The .N and .W suffixes are recognized and honored (it is an error
322 if they cannot be honored).
323 - All instructions set the flags if and only if they have an 's' affix.
324 - Conditional affixes may be used. They are validated against
325 preceding IT instructions. Unlike ARM mode, you cannot use a
326 conditional affix except in the scope of an IT instruction. */
327
328static bfd_boolean unified_syntax = FALSE;
b99bd4ef 329
bacebabc
RM		 330/* An immediate operand can start with #, and ld*, st*, pld operands
331 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM		 332 before a [, which can appear as the first operand for pld.
333 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
334const char arm_symbol_chars[] = "#[]{}";
bacebabc 335
5287ad62
JB		 336enum neon_el_type
337{
dcbf9037 338 NT_invtype,
5287ad62
JB		 339 NT_untyped,
340 NT_integer,
341 NT_float,
342 NT_poly,
343 NT_signed,
dcbf9037 344 NT_unsigned
5287ad62
JB		 345};
346
347struct neon_type_el
348{
349 enum neon_el_type type;
350 unsigned size;
351};
352
353#define NEON_MAX_TYPE_ELS 4
354
355struct neon_type
356{
357 struct neon_type_el el[NEON_MAX_TYPE_ELS];
358 unsigned elems;
359};
360
e07e6e58
NC		 361enum it_instruction_type
362{
363 OUTSIDE_IT_INSN,
364 INSIDE_IT_INSN,
365 INSIDE_IT_LAST_INSN,
366 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 367 if inside, should be the last one. */
e07e6e58 368 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 369 i.e. BKPT and NOP. */
e07e6e58
NC		 370 IT_INSN /* The IT insn has been parsed. */
371};
372
ad6cec43
MGD		 373/* The maximum number of operands we need. */
374#define ARM_IT_MAX_OPERANDS 6
375
b99bd4ef
NC		 376struct arm_it
377{
c19d1205 378 const char * error;
b99bd4ef 379 unsigned long instruction;
c19d1205
ZW		 380 int size;
381 int size_req;
382 int cond;
037e8744
JB		 383 /* "uncond_value" is set to the value in place of the conditional field in
384 unconditional versions of the instruction, or -1 if nothing is
385 appropriate. */
386 int uncond_value;
5287ad62 387 struct neon_type vectype;
88714cb8
DG		 388 /* This does not indicate an actual NEON instruction, only that
389 the mnemonic accepts neon-style type suffixes. */
390 int is_neon;
0110f2b8
PB		 391 /* Set to the opcode if the instruction needs relaxation.
392 Zero if the instruction is not relaxed. */
393 unsigned long relax;
b99bd4ef
NC		 394 struct
395 {
396 bfd_reloc_code_real_type type;
c19d1205
ZW		 397 expressionS exp;
398 int pc_rel;
b99bd4ef 399 } reloc;
b99bd4ef 400
e07e6e58
NC		 401 enum it_instruction_type it_insn_type;
402
c19d1205
ZW		 403 struct
404 {
405 unsigned reg;
ca3f61f7 406 signed int imm;
dcbf9037 407 struct neon_type_el vectype;
ca3f61f7
NC		 408 unsigned present : 1; /* Operand present. */
409 unsigned isreg : 1; /* Operand was a register. */
410 unsigned immisreg : 1; /* .imm field is a second register. */
5287ad62
JB		 411 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
412 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 413 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB		 414 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
415 instructions. This allows us to disambiguate ARM <-> vector insns. */
416 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 417 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5287ad62 418 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
037e8744 419 unsigned issingle : 1; /* Operand is VFP single-precision register. */
ca3f61f7
NC		 420 unsigned hasreloc : 1; /* Operand has relocation suffix. */
421 unsigned writeback : 1; /* Operand has trailing ! */
422 unsigned preind : 1; /* Preindexed address. */
423 unsigned postind : 1; /* Postindexed address. */
424 unsigned negative : 1; /* Index register was negated. */
425 unsigned shifted : 1; /* Shift applied to operation. */
426 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 427 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC		 428};
429
c19d1205 430static struct arm_it inst;
b99bd4ef
NC		 431
432#define NUM_FLOAT_VALS 8
433
05d2d07e 434const char * fp_const[] =
b99bd4ef
NC		 435{
436 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
437};
438
c19d1205 439/* Number of littlenums required to hold an extended precision number. */
b99bd4ef
NC		 440#define MAX_LITTLENUMS 6
441
442LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
443
444#define FAIL (-1)
445#define SUCCESS (0)
446
447#define SUFF_S 1
448#define SUFF_D 2
449#define SUFF_E 3
450#define SUFF_P 4
451
c19d1205
ZW		 452#define CP_T_X 0x00008000
453#define CP_T_Y 0x00400000
b99bd4ef 454
c19d1205
ZW		 455#define CONDS_BIT 0x00100000
456#define LOAD_BIT 0x00100000
b99bd4ef
NC		 457
458#define DOUBLE_LOAD_FLAG 0x00000001
459
460struct asm_cond
461{
d3ce72d0 462 const char * template_name;
c921be7d 463 unsigned long value;
b99bd4ef
NC		 464};
465
c19d1205 466#define COND_ALWAYS 0xE
b99bd4ef 467
b99bd4ef
NC		 468struct asm_psr
469{
d3ce72d0 470 const char * template_name;
c921be7d 471 unsigned long field;
b99bd4ef
NC		 472};
473
62b3e311
PB		 474struct asm_barrier_opt
475{
e797f7e0
MGD		 476 const char * template_name;
477 unsigned long value;
478 const arm_feature_set arch;
62b3e311
PB		 479};
480
2d2255b5 481/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC		 482#define SPSR_BIT (1 << 22)
483
c19d1205
ZW		 484/* The individual PSR flag bits. */
485#define PSR_c (1 << 16)
486#define PSR_x (1 << 17)
487#define PSR_s (1 << 18)
488#define PSR_f (1 << 19)
b99bd4ef 489
c19d1205 490struct reloc_entry
bfae80f2 491{
c921be7d
NC		 492 char * name;
493 bfd_reloc_code_real_type reloc;
bfae80f2
RE		 494};
495
5287ad62 496enum vfp_reg_pos
bfae80f2 497{
5287ad62
JB		 498 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
499 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE		 500};
501
502enum vfp_ldstm_type
503{
504 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
505};
506
dcbf9037
JB		 507/* Bits for DEFINED field in neon_typed_alias. */
508#define NTA_HASTYPE 1
509#define NTA_HASINDEX 2
510
511struct neon_typed_alias
512{
c921be7d
NC		 513 unsigned char defined;
514 unsigned char index;
515 struct neon_type_el eltype;
dcbf9037
JB		 516};
517
c19d1205
ZW		 518/* ARM register categories. This includes coprocessor numbers and various
519 architecture extensions' registers. */
520enum arm_reg_type
bfae80f2 521{
c19d1205
ZW		 522 REG_TYPE_RN,
523 REG_TYPE_CP,
524 REG_TYPE_CN,
525 REG_TYPE_FN,
526 REG_TYPE_VFS,
527 REG_TYPE_VFD,
5287ad62 528 REG_TYPE_NQ,
037e8744 529 REG_TYPE_VFSD,
5287ad62 530 REG_TYPE_NDQ,
037e8744 531 REG_TYPE_NSDQ,
c19d1205
ZW		 532 REG_TYPE_VFC,
533 REG_TYPE_MVF,
534 REG_TYPE_MVD,
535 REG_TYPE_MVFX,
536 REG_TYPE_MVDX,
537 REG_TYPE_MVAX,
538 REG_TYPE_DSPSC,
539 REG_TYPE_MMXWR,
540 REG_TYPE_MMXWC,
541 REG_TYPE_MMXWCG,
542 REG_TYPE_XSCALE,
90ec0d68 543 REG_TYPE_RNB
bfae80f2
RE		 544};
545
dcbf9037
JB		 546/* Structure for a hash table entry for a register.
547 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
548 information which states whether a vector type or index is specified (for a
549 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE		 550struct reg_entry
551{
c921be7d 552 const char * name;
90ec0d68 553 unsigned int number;
c921be7d
NC		 554 unsigned char type;
555 unsigned char builtin;
556 struct neon_typed_alias * neon;
6c43fab6
RE		 557};
558
c19d1205 559/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 560const char * const reg_expected_msgs[] =
c19d1205
ZW		 561{
562 N_("ARM register expected"),
563 N_("bad or missing co-processor number"),
564 N_("co-processor register expected"),
565 N_("FPA register expected"),
566 N_("VFP single precision register expected"),
5287ad62
JB		 567 N_("VFP/Neon double precision register expected"),
568 N_("Neon quad precision register expected"),
037e8744 569 N_("VFP single or double precision register expected"),
5287ad62 570 N_("Neon double or quad precision register expected"),
037e8744 571 N_("VFP single, double or Neon quad precision register expected"),
c19d1205
ZW		 572 N_("VFP system register expected"),
573 N_("Maverick MVF register expected"),
574 N_("Maverick MVD register expected"),
575 N_("Maverick MVFX register expected"),
576 N_("Maverick MVDX register expected"),
577 N_("Maverick MVAX register expected"),
578 N_("Maverick DSPSC register expected"),
579 N_("iWMMXt data register expected"),
580 N_("iWMMXt control register expected"),
581 N_("iWMMXt scalar register expected"),
582 N_("XScale accumulator register expected"),
6c43fab6
RE		 583};
584
c19d1205 585/* Some well known registers that we refer to directly elsewhere. */
bd340a04 586#define REG_R12 12
c19d1205
ZW		 587#define REG_SP 13
588#define REG_LR 14
589#define REG_PC 15
404ff6b5 590
b99bd4ef
NC		 591/* ARM instructions take 4bytes in the object file, Thumb instructions
592 take 2: */
c19d1205 593#define INSN_SIZE 4
b99bd4ef
NC		 594
595struct asm_opcode
596{
597 /* Basic string to match. */
d3ce72d0 598 const char * template_name;
c19d1205
ZW		 599
600 /* Parameters to instruction. */
5be8be5d 601 unsigned int operands[8];
c19d1205
ZW		 602
603 /* Conditional tag - see opcode_lookup. */
604 unsigned int tag : 4;
b99bd4ef
NC		 605
606 /* Basic instruction code. */
c19d1205 607 unsigned int avalue : 28;
b99bd4ef 608
c19d1205
ZW		 609 /* Thumb-format instruction code. */
610 unsigned int tvalue;
b99bd4ef 611
90e4755a 612 /* Which architecture variant provides this instruction. */
c921be7d
NC		 613 const arm_feature_set * avariant;
614 const arm_feature_set * tvariant;
c19d1205
ZW		 615
616 /* Function to call to encode instruction in ARM format. */
617 void (* aencode) (void);
b99bd4ef 618
c19d1205
ZW		 619 /* Function to call to encode instruction in Thumb format. */
620 void (* tencode) (void);
b99bd4ef
NC		 621};
622
a737bd4d
NC		 623/* Defines for various bits that we will want to toggle. */
624#define INST_IMMEDIATE 0x02000000
625#define OFFSET_REG 0x02000000
c19d1205 626#define HWOFFSET_IMM 0x00400000
a737bd4d
NC		 627#define SHIFT_BY_REG 0x00000010
628#define PRE_INDEX 0x01000000
629#define INDEX_UP 0x00800000
630#define WRITE_BACK 0x00200000
631#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 632#define CPSI_MMOD 0x00020000
90e4755a 633
a737bd4d
NC		 634#define LITERAL_MASK 0xf000f000
635#define OPCODE_MASK 0xfe1fffff
636#define V4_STR_BIT 0x00000020
8335d6aa 637#define VLDR_VMOV_SAME 0x0040f000
90e4755a 638
efd81785
PB		 639#define T2_SUBS_PC_LR 0xf3de8f00
640
a737bd4d 641#define DATA_OP_SHIFT 21
90e4755a 642
ef8d22e6
PB		 643#define T2_OPCODE_MASK 0xfe1fffff
644#define T2_DATA_OP_SHIFT 21
645
6530b175
NC		 646#define A_COND_MASK 0xf0000000
647#define A_PUSH_POP_OP_MASK 0x0fff0000
648
649/* Opcodes for pushing/poping registers to/from the stack. */
650#define A1_OPCODE_PUSH 0x092d0000
651#define A2_OPCODE_PUSH 0x052d0004
652#define A2_OPCODE_POP 0x049d0004
653
a737bd4d
NC		 654/* Codes to distinguish the arithmetic instructions. */
655#define OPCODE_AND 0
656#define OPCODE_EOR 1
657#define OPCODE_SUB 2
658#define OPCODE_RSB 3
659#define OPCODE_ADD 4
660#define OPCODE_ADC 5
661#define OPCODE_SBC 6
662#define OPCODE_RSC 7
663#define OPCODE_TST 8
664#define OPCODE_TEQ 9
665#define OPCODE_CMP 10
666#define OPCODE_CMN 11
667#define OPCODE_ORR 12
668#define OPCODE_MOV 13
669#define OPCODE_BIC 14
670#define OPCODE_MVN 15
90e4755a 671
ef8d22e6
PB		 672#define T2_OPCODE_AND 0
673#define T2_OPCODE_BIC 1
674#define T2_OPCODE_ORR 2
675#define T2_OPCODE_ORN 3
676#define T2_OPCODE_EOR 4
677#define T2_OPCODE_ADD 8
678#define T2_OPCODE_ADC 10
679#define T2_OPCODE_SBC 11
680#define T2_OPCODE_SUB 13
681#define T2_OPCODE_RSB 14
682
a737bd4d
NC		 683#define T_OPCODE_MUL 0x4340
684#define T_OPCODE_TST 0x4200
685#define T_OPCODE_CMN 0x42c0
686#define T_OPCODE_NEG 0x4240
687#define T_OPCODE_MVN 0x43c0
90e4755a 688
a737bd4d
NC		 689#define T_OPCODE_ADD_R3 0x1800
690#define T_OPCODE_SUB_R3 0x1a00
691#define T_OPCODE_ADD_HI 0x4400
692#define T_OPCODE_ADD_ST 0xb000
693#define T_OPCODE_SUB_ST 0xb080
694#define T_OPCODE_ADD_SP 0xa800
695#define T_OPCODE_ADD_PC 0xa000
696#define T_OPCODE_ADD_I8 0x3000
697#define T_OPCODE_SUB_I8 0x3800
698#define T_OPCODE_ADD_I3 0x1c00
699#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 700
a737bd4d
NC		 701#define T_OPCODE_ASR_R 0x4100
702#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW		 703#define T_OPCODE_LSR_R 0x40c0
704#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC		 705#define T_OPCODE_ASR_I 0x1000
706#define T_OPCODE_LSL_I 0x0000
707#define T_OPCODE_LSR_I 0x0800
b99bd4ef 708
a737bd4d
NC		 709#define T_OPCODE_MOV_I8 0x2000
710#define T_OPCODE_CMP_I8 0x2800
711#define T_OPCODE_CMP_LR 0x4280
712#define T_OPCODE_MOV_HR 0x4600
713#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 714
a737bd4d
NC		 715#define T_OPCODE_LDR_PC 0x4800
716#define T_OPCODE_LDR_SP 0x9800
717#define T_OPCODE_STR_SP 0x9000
718#define T_OPCODE_LDR_IW 0x6800
719#define T_OPCODE_STR_IW 0x6000
720#define T_OPCODE_LDR_IH 0x8800
721#define T_OPCODE_STR_IH 0x8000
722#define T_OPCODE_LDR_IB 0x7800
723#define T_OPCODE_STR_IB 0x7000
724#define T_OPCODE_LDR_RW 0x5800
725#define T_OPCODE_STR_RW 0x5000
726#define T_OPCODE_LDR_RH 0x5a00
727#define T_OPCODE_STR_RH 0x5200
728#define T_OPCODE_LDR_RB 0x5c00
729#define T_OPCODE_STR_RB 0x5400
c9b604bd 730
a737bd4d
NC		 731#define T_OPCODE_PUSH 0xb400
732#define T_OPCODE_POP 0xbc00
b99bd4ef 733
2fc8bdac 734#define T_OPCODE_BRANCH 0xe000
b99bd4ef 735
a737bd4d 736#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 737#define THUMB_PP_PC_LR 0x0100
c19d1205 738#define THUMB_LOAD_BIT 0x0800
53365c0d 739#define THUMB2_LOAD_BIT 0x00100000
c19d1205
ZW		 740
741#define BAD_ARGS _("bad arguments to instruction")
fdfde340 742#define BAD_SP _("r13 not allowed here")
c19d1205
ZW		 743#define BAD_PC _("r15 not allowed here")
744#define BAD_COND _("instruction cannot be conditional")
745#define BAD_OVERLAP _("registers may not be the same")
746#define BAD_HIREG _("lo register required")
747#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
01cfc07f 748#define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
dfa9f0d5
PB		 749#define BAD_BRANCH _("branch must be last instruction in IT block")
750#define BAD_NOT_IT _("instruction not allowed in IT block")
037e8744 751#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58
NC		 752#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
753#define BAD_IT_COND _("incorrect condition in IT block")
754#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 755#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG		 756#define BAD_PC_ADDRESSING \
757 _("cannot use register index with PC-relative addressing")
758#define BAD_PC_WRITEBACK \
759 _("cannot use writeback with PC-relative addressing")
08f10d51 760#define BAD_RANGE _("branch out of range")
dd5181d5 761#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
c19d1205 762
c921be7d
NC		 763static struct hash_control * arm_ops_hsh;
764static struct hash_control * arm_cond_hsh;
765static struct hash_control * arm_shift_hsh;
766static struct hash_control * arm_psr_hsh;
767static struct hash_control * arm_v7m_psr_hsh;
768static struct hash_control * arm_reg_hsh;
769static struct hash_control * arm_reloc_hsh;
770static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 771
b99bd4ef
NC		 772/* Stuff needed to resolve the label ambiguity
773 As:
774 ...
775 label: <insn>
776 may differ from:
777 ...
778 label:
5f4273c7 779 <insn> */
b99bd4ef
NC		 780
781symbolS * last_label_seen;
b34976b6 782static int label_is_thumb_function_name = FALSE;
e07e6e58 783
3d0c9500
NC		 784/* Literal pool structure. Held on a per-section
785 and per-sub-section basis. */
a737bd4d 786
c19d1205 787#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 788typedef struct literal_pool
b99bd4ef 789{
c921be7d
NC		 790 expressionS literals [MAX_LITERAL_POOL_SIZE];
791 unsigned int next_free_entry;
792 unsigned int id;
793 symbolS * symbol;
794 segT section;
795 subsegT sub_section;
a8040cf2
NC		 796#ifdef OBJ_ELF
797 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
798#endif
c921be7d 799 struct literal_pool * next;
8335d6aa 800 unsigned int alignment;
3d0c9500 801} literal_pool;
b99bd4ef 802
3d0c9500
NC		 803/* Pointer to a linked list of literal pools. */
804literal_pool * list_of_pools = NULL;
e27ec89e 805
2e6976a8
DG		 806typedef enum asmfunc_states
807{
808 OUTSIDE_ASMFUNC,
809 WAITING_ASMFUNC_NAME,
810 WAITING_ENDASMFUNC
811} asmfunc_states;
812
813static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
814
e07e6e58
NC		 815#ifdef OBJ_ELF
816# define now_it seg_info (now_seg)->tc_segment_info_data.current_it
817#else
818static struct current_it now_it;
819#endif
820
821static inline int
822now_it_compatible (int cond)
823{
824 return (cond & ~1) == (now_it.cc & ~1);
825}
826
827static inline int
828conditional_insn (void)
829{
830 return inst.cond != COND_ALWAYS;
831}
832
833static int in_it_block (void);
834
835static int handle_it_state (void);
836
837static void force_automatic_it_block_close (void);
838
c921be7d
NC		 839static void it_fsm_post_encode (void);
840
e07e6e58
NC		 841#define set_it_insn_type(type) \
842 do \
843 { \
844 inst.it_insn_type = type; \
845 if (handle_it_state () == FAIL) \
477330fc 846 return; \
e07e6e58
NC		 847 } \
848 while (0)
849
c921be7d
NC		 850#define set_it_insn_type_nonvoid(type, failret) \
851 do \
852 { \
853 inst.it_insn_type = type; \
854 if (handle_it_state () == FAIL) \
477330fc 855 return failret; \
c921be7d
NC		 856 } \
857 while(0)
858
e07e6e58
NC		 859#define set_it_insn_type_last() \
860 do \
861 { \
862 if (inst.cond == COND_ALWAYS) \
477330fc 863 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 864 else \
477330fc 865 set_it_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC		 866 } \
867 while (0)
868
c19d1205 869/* Pure syntax. */
b99bd4ef 870
c19d1205
ZW		 871/* This array holds the chars that always start a comment. If the
872 pre-processor is disabled, these aren't very useful. */
2e6976a8 873char arm_comment_chars[] = "@";
3d0c9500 874
c19d1205
ZW		 875/* This array holds the chars that only start a comment at the beginning of
876 a line. If the line seems to have the form '# 123 filename'
877 .line and .file directives will appear in the pre-processed output. */
878/* Note that input_file.c hand checks for '#' at the beginning of the
879 first line of the input file. This is because the compiler outputs
880 #NO_APP at the beginning of its output. */
881/* Also note that comments like this one will always work. */
882const char line_comment_chars[] = "#";
3d0c9500 883
2e6976a8 884char arm_line_separator_chars[] = ";";
b99bd4ef 885
c19d1205
ZW		 886/* Chars that can be used to separate mant
887 from exp in floating point numbers. */
888const char EXP_CHARS[] = "eE";
3d0c9500 889
c19d1205
ZW		 890/* Chars that mean this number is a floating point constant. */
891/* As in 0f12.456 */
892/* or 0d1.2345e12 */
b99bd4ef 893
c19d1205 894const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
3d0c9500 895
c19d1205
ZW		 896/* Prefix characters that indicate the start of an immediate
897 value. */
898#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 899
c19d1205
ZW		 900/* Separator character handling. */
901
902#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
903
904static inline int
905skip_past_char (char ** str, char c)
906{
8ab8155f
NC		 907 /* PR gas/14987: Allow for whitespace before the expected character. */
908 skip_whitespace (*str);
427d0db6 909
c19d1205
ZW		 910 if (**str == c)
911 {
912 (*str)++;
913 return SUCCESS;
3d0c9500 914 }
c19d1205
ZW		 915 else
916 return FAIL;
917}
c921be7d 918
c19d1205 919#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 920
c19d1205
ZW		 921/* Arithmetic expressions (possibly involving symbols). */
922
923/* Return TRUE if anything in the expression is a bignum. */
924
925static int
926walk_no_bignums (symbolS * sp)
927{
928 if (symbol_get_value_expression (sp)->X_op == O_big)
929 return 1;
930
931 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 932 {
c19d1205
ZW		 933 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
934 || (symbol_get_value_expression (sp)->X_op_symbol
935 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC		 936 }
937
c19d1205 938 return 0;
3d0c9500
NC		 939}
940
c19d1205
ZW		 941static int in_my_get_expression = 0;
942
943/* Third argument to my_get_expression. */
944#define GE_NO_PREFIX 0
945#define GE_IMM_PREFIX 1
946#define GE_OPT_PREFIX 2
5287ad62
JB		 947/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
948 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
949#define GE_OPT_PREFIX_BIG 3
a737bd4d 950
b99bd4ef 951static int
c19d1205 952my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 953{
c19d1205
ZW		 954 char * save_in;
955 segT seg;
b99bd4ef 956
c19d1205
ZW		 957 /* In unified syntax, all prefixes are optional. */
958 if (unified_syntax)
5287ad62 959 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 960 : GE_OPT_PREFIX;
b99bd4ef 961
c19d1205 962 switch (prefix_mode)
b99bd4ef 963 {
c19d1205
ZW		 964 case GE_NO_PREFIX: break;
965 case GE_IMM_PREFIX:
966 if (!is_immediate_prefix (**str))
967 {
968 inst.error = _("immediate expression requires a # prefix");
969 return FAIL;
970 }
971 (*str)++;
972 break;
973 case GE_OPT_PREFIX:
5287ad62 974 case GE_OPT_PREFIX_BIG:
c19d1205
ZW		 975 if (is_immediate_prefix (**str))
976 (*str)++;
977 break;
978 default: abort ();
979 }
b99bd4ef 980
c19d1205 981 memset (ep, 0, sizeof (expressionS));
b99bd4ef 982
c19d1205
ZW		 983 save_in = input_line_pointer;
984 input_line_pointer = *str;
985 in_my_get_expression = 1;
986 seg = expression (ep);
987 in_my_get_expression = 0;
988
f86adc07 989 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 990 {
f86adc07 991 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW		 992 *str = input_line_pointer;
993 input_line_pointer = save_in;
994 if (inst.error == NULL)
f86adc07
NS		 995 inst.error = (ep->X_op == O_absent
996 ? _("missing expression") :_("bad expression"));
c19d1205
ZW		 997 return 1;
998 }
b99bd4ef 999
c19d1205
ZW		 1000#ifdef OBJ_AOUT
1001 if (seg != absolute_section
1002 && seg != text_section
1003 && seg != data_section
1004 && seg != bss_section
1005 && seg != undefined_section)
1006 {
1007 inst.error = _("bad segment");
1008 *str = input_line_pointer;
1009 input_line_pointer = save_in;
1010 return 1;
b99bd4ef 1011 }
87975d2a
AM		 1012#else
1013 (void) seg;
c19d1205 1014#endif
b99bd4ef 1015
c19d1205
ZW		 1016 /* Get rid of any bignums now, so that we don't generate an error for which
1017 we can't establish a line number later on. Big numbers are never valid
1018 in instructions, which is where this routine is always called. */
5287ad62
JB		 1019 if (prefix_mode != GE_OPT_PREFIX_BIG
1020 && (ep->X_op == O_big
477330fc 1021 || (ep->X_add_symbol
5287ad62 1022 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1023 || (ep->X_op_symbol
5287ad62 1024 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW		 1025 {
1026 inst.error = _("invalid constant");
1027 *str = input_line_pointer;
1028 input_line_pointer = save_in;
1029 return 1;
1030 }
b99bd4ef 1031
c19d1205
ZW		 1032 *str = input_line_pointer;
1033 input_line_pointer = save_in;
1034 return 0;
b99bd4ef
NC		 1035}
1036
c19d1205
ZW		 1037/* Turn a string in input_line_pointer into a floating point constant
1038 of type TYPE, and store the appropriate bytes in *LITP. The number
1039 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1040 returned, or NULL on OK.
b99bd4ef 1041
c19d1205
ZW		 1042 Note that fp constants aren't represent in the normal way on the ARM.
1043 In big endian mode, things are as expected. However, in little endian
1044 mode fp constants are big-endian word-wise, and little-endian byte-wise
1045 within the words. For example, (double) 1.1 in big endian mode is
1046 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1047 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1048
c19d1205 1049 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1050
c19d1205
ZW		 1051char *
1052md_atof (int type, char * litP, int * sizeP)
1053{
1054 int prec;
1055 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1056 char *t;
1057 int i;
b99bd4ef 1058
c19d1205
ZW		 1059 switch (type)
1060 {
1061 case 'f':
1062 case 'F':
1063 case 's':
1064 case 'S':
1065 prec = 2;
1066 break;
b99bd4ef 1067
c19d1205
ZW		 1068 case 'd':
1069 case 'D':
1070 case 'r':
1071 case 'R':
1072 prec = 4;
1073 break;
b99bd4ef 1074
c19d1205
ZW		 1075 case 'x':
1076 case 'X':
499ac353 1077 prec = 5;
c19d1205 1078 break;
b99bd4ef 1079
c19d1205
ZW		 1080 case 'p':
1081 case 'P':
499ac353 1082 prec = 5;
c19d1205 1083 break;
a737bd4d 1084
c19d1205
ZW		 1085 default:
1086 *sizeP = 0;
499ac353 1087 return _("Unrecognized or unsupported floating point constant");
c19d1205 1088 }
b99bd4ef 1089
c19d1205
ZW		 1090 t = atof_ieee (input_line_pointer, type, words);
1091 if (t)
1092 input_line_pointer = t;
499ac353 1093 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1094
c19d1205
ZW		 1095 if (target_big_endian)
1096 {
1097 for (i = 0; i < prec; i++)
1098 {
499ac353
NC		 1099 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1100 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1101 }
1102 }
1103 else
1104 {
e74cfd16 1105 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
c19d1205
ZW		 1106 for (i = prec - 1; i >= 0; i--)
1107 {
499ac353
NC		 1108 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1109 litP += sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1110 }
1111 else
1112 /* For a 4 byte float the order of elements in `words' is 1 0.
1113 For an 8 byte float the order is 1 0 3 2. */
1114 for (i = 0; i < prec; i += 2)
1115 {
499ac353
NC		 1116 md_number_to_chars (litP, (valueT) words[i + 1],
1117 sizeof (LITTLENUM_TYPE));
1118 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1119 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1120 litP += 2 * sizeof (LITTLENUM_TYPE);
c19d1205
ZW		 1121 }
1122 }
b99bd4ef 1123
499ac353 1124 return NULL;
c19d1205 1125}
b99bd4ef 1126
c19d1205
ZW		 1127/* We handle all bad expressions here, so that we can report the faulty
1128 instruction in the error message. */
1129void
91d6fa6a 1130md_operand (expressionS * exp)
c19d1205
ZW		 1131{
1132 if (in_my_get_expression)
91d6fa6a 1133 exp->X_op = O_illegal;
b99bd4ef
NC		 1134}
1135
c19d1205 1136/* Immediate values. */
b99bd4ef 1137
c19d1205
ZW		 1138/* Generic immediate-value read function for use in directives.
1139 Accepts anything that 'expression' can fold to a constant.
1140 *val receives the number. */
1141#ifdef OBJ_ELF
1142static int
1143immediate_for_directive (int *val)
b99bd4ef 1144{
c19d1205
ZW		 1145 expressionS exp;
1146 exp.X_op = O_illegal;
b99bd4ef 1147
c19d1205
ZW		 1148 if (is_immediate_prefix (*input_line_pointer))
1149 {
1150 input_line_pointer++;
1151 expression (&exp);
1152 }
b99bd4ef 1153
c19d1205
ZW		 1154 if (exp.X_op != O_constant)
1155 {
1156 as_bad (_("expected #constant"));
1157 ignore_rest_of_line ();
1158 return FAIL;
1159 }
1160 *val = exp.X_add_number;
1161 return SUCCESS;
b99bd4ef 1162}
c19d1205 1163#endif
b99bd4ef 1164
c19d1205 1165/* Register parsing. */
b99bd4ef 1166
c19d1205
ZW		 1167/* Generic register parser. CCP points to what should be the
1168 beginning of a register name. If it is indeed a valid register
1169 name, advance CCP over it and return the reg_entry structure;
1170 otherwise return NULL. Does not issue diagnostics. */
1171
1172static struct reg_entry *
1173arm_reg_parse_multi (char **ccp)
b99bd4ef 1174{
c19d1205
ZW		 1175 char *start = *ccp;
1176 char *p;
1177 struct reg_entry *reg;
b99bd4ef 1178
477330fc
RM		 1179 skip_whitespace (start);
1180
c19d1205
ZW		 1181#ifdef REGISTER_PREFIX
1182 if (*start != REGISTER_PREFIX)
01cfc07f 1183 return NULL;
c19d1205
ZW		 1184 start++;
1185#endif
1186#ifdef OPTIONAL_REGISTER_PREFIX
1187 if (*start == OPTIONAL_REGISTER_PREFIX)
1188 start++;
1189#endif
b99bd4ef 1190
c19d1205
ZW		 1191 p = start;
1192 if (!ISALPHA (*p) || !is_name_beginner (*p))
1193 return NULL;
b99bd4ef 1194
c19d1205
ZW		 1195 do
1196 p++;
1197 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1198
1199 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1200
1201 if (!reg)
1202 return NULL;
1203
1204 *ccp = p;
1205 return reg;
b99bd4ef
NC		 1206}
1207
1208static int
dcbf9037 1209arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1210 enum arm_reg_type type)
b99bd4ef 1211{
c19d1205
ZW		 1212 /* Alternative syntaxes are accepted for a few register classes. */
1213 switch (type)
1214 {
1215 case REG_TYPE_MVF:
1216 case REG_TYPE_MVD:
1217 case REG_TYPE_MVFX:
1218 case REG_TYPE_MVDX:
1219 /* Generic coprocessor register names are allowed for these. */
79134647 1220 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW		 1221 return reg->number;
1222 break;
69b97547 1223
c19d1205
ZW		 1224 case REG_TYPE_CP:
1225 /* For backward compatibility, a bare number is valid here. */
1226 {
1227 unsigned long processor = strtoul (start, ccp, 10);
1228 if (*ccp != start && processor <= 15)
1229 return processor;
1230 }
6057a28f 1231
c19d1205
ZW		 1232 case REG_TYPE_MMXWC:
1233 /* WC includes WCG. ??? I'm not sure this is true for all
1234 instructions that take WC registers. */
79134647 1235 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1236 return reg->number;
6057a28f 1237 break;
c19d1205 1238
6057a28f 1239 default:
c19d1205 1240 break;
6057a28f
NC		 1241 }
1242
dcbf9037
JB		 1243 return FAIL;
1244}
1245
1246/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1247 return value is the register number or FAIL. */
1248
1249static int
1250arm_reg_parse (char **ccp, enum arm_reg_type type)
1251{
1252 char *start = *ccp;
1253 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1254 int ret;
1255
1256 /* Do not allow a scalar (reg+index) to parse as a register. */
1257 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1258 return FAIL;
1259
1260 if (reg && reg->type == type)
1261 return reg->number;
1262
1263 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1264 return ret;
1265
c19d1205
ZW		 1266 *ccp = start;
1267 return FAIL;
1268}
69b97547 1269
dcbf9037
JB		 1270/* Parse a Neon type specifier. *STR should point at the leading '.'
1271 character. Does no verification at this stage that the type fits the opcode
1272 properly. E.g.,
1273
1274 .i32.i32.s16
1275 .s32.f32
1276 .u16
1277
1278 Can all be legally parsed by this function.
1279
1280 Fills in neon_type struct pointer with parsed information, and updates STR
1281 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1282 type, FAIL if not. */
1283
1284static int
1285parse_neon_type (struct neon_type *type, char **str)
1286{
1287 char *ptr = *str;
1288
1289 if (type)
1290 type->elems = 0;
1291
1292 while (type->elems < NEON_MAX_TYPE_ELS)
1293 {
1294 enum neon_el_type thistype = NT_untyped;
1295 unsigned thissize = -1u;
1296
1297 if (*ptr != '.')
1298 break;
1299
1300 ptr++;
1301
1302 /* Just a size without an explicit type. */
1303 if (ISDIGIT (*ptr))
1304 goto parsesize;
1305
1306 switch (TOLOWER (*ptr))
1307 {
1308 case 'i': thistype = NT_integer; break;
1309 case 'f': thistype = NT_float; break;
1310 case 'p': thistype = NT_poly; break;
1311 case 's': thistype = NT_signed; break;
1312 case 'u': thistype = NT_unsigned; break;
477330fc
RM		 1313 case 'd':
1314 thistype = NT_float;
1315 thissize = 64;
1316 ptr++;
1317 goto done;
dcbf9037
JB		 1318 default:
1319 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1320 return FAIL;
1321 }
1322
1323 ptr++;
1324
1325 /* .f is an abbreviation for .f32. */
1326 if (thistype == NT_float && !ISDIGIT (*ptr))
1327 thissize = 32;
1328 else
1329 {
1330 parsesize:
1331 thissize = strtoul (ptr, &ptr, 10);
1332
1333 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM		 1334 && thissize != 64)
1335 {
1336 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB		 1337 return FAIL;
1338 }
1339 }
1340
037e8744 1341 done:
dcbf9037 1342 if (type)
477330fc
RM		 1343 {
1344 type->el[type->elems].type = thistype;
dcbf9037
JB		 1345 type->el[type->elems].size = thissize;
1346 type->elems++;
1347 }
1348 }
1349
1350 /* Empty/missing type is not a successful parse. */
1351 if (type->elems == 0)
1352 return FAIL;
1353
1354 *str = ptr;
1355
1356 return SUCCESS;
1357}
1358
1359/* Errors may be set multiple times during parsing or bit encoding
1360 (particularly in the Neon bits), but usually the earliest error which is set
1361 will be the most meaningful. Avoid overwriting it with later (cascading)
1362 errors by calling this function. */
1363
1364static void
1365first_error (const char *err)
1366{
1367 if (!inst.error)
1368 inst.error = err;
1369}
1370
1371/* Parse a single type, e.g. ".s32", leading period included. */
1372static int
1373parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1374{
1375 char *str = *ccp;
1376 struct neon_type optype;
1377
1378 if (*str == '.')
1379 {
1380 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM		 1381 {
1382 if (optype.elems == 1)
1383 *vectype = optype.el[0];
1384 else
1385 {
1386 first_error (_("only one type should be specified for operand"));
1387 return FAIL;
1388 }
1389 }
dcbf9037 1390 else
477330fc
RM		 1391 {
1392 first_error (_("vector type expected"));
1393 return FAIL;
1394 }
dcbf9037
JB		 1395 }
1396 else
1397 return FAIL;
5f4273c7 1398
dcbf9037 1399 *ccp = str;
5f4273c7 1400
dcbf9037
JB		 1401 return SUCCESS;
1402}
1403
1404/* Special meanings for indices (which have a range of 0-7), which will fit into
1405 a 4-bit integer. */
1406
1407#define NEON_ALL_LANES 15
1408#define NEON_INTERLEAVE_LANES 14
1409
1410/* Parse either a register or a scalar, with an optional type. Return the
1411 register number, and optionally fill in the actual type of the register
1412 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1413 type/index information in *TYPEINFO. */
1414
1415static int
1416parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM		 1417 enum arm_reg_type *rtype,
1418 struct neon_typed_alias *typeinfo)
dcbf9037
JB		 1419{
1420 char *str = *ccp;
1421 struct reg_entry *reg = arm_reg_parse_multi (&str);
1422 struct neon_typed_alias atype;
1423 struct neon_type_el parsetype;
1424
1425 atype.defined = 0;
1426 atype.index = -1;
1427 atype.eltype.type = NT_invtype;
1428 atype.eltype.size = -1;
1429
1430 /* Try alternate syntax for some types of register. Note these are mutually
1431 exclusive with the Neon syntax extensions. */
1432 if (reg == NULL)
1433 {
1434 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1435 if (altreg != FAIL)
477330fc 1436 *ccp = str;
dcbf9037 1437 if (typeinfo)
477330fc 1438 *typeinfo = atype;
dcbf9037
JB		 1439 return altreg;
1440 }
1441
037e8744
JB		 1442 /* Undo polymorphism when a set of register types may be accepted. */
1443 if ((type == REG_TYPE_NDQ
1444 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1445 || (type == REG_TYPE_VFSD
477330fc 1446 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1447 || (type == REG_TYPE_NSDQ
477330fc
RM		 1448 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1449 || reg->type == REG_TYPE_NQ))
f512f76f
NC		 1450 || (type == REG_TYPE_MMXWC
1451 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1452 type = (enum arm_reg_type) reg->type;
dcbf9037
JB		 1453
1454 if (type != reg->type)
1455 return FAIL;
1456
1457 if (reg->neon)
1458 atype = *reg->neon;
5f4273c7 1459
dcbf9037
JB		 1460 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1461 {
1462 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM		 1463 {
1464 first_error (_("can't redefine type for operand"));
1465 return FAIL;
1466 }
dcbf9037
JB		 1467 atype.defined |= NTA_HASTYPE;
1468 atype.eltype = parsetype;
1469 }
5f4273c7 1470
dcbf9037
JB		 1471 if (skip_past_char (&str, '[') == SUCCESS)
1472 {
1473 if (type != REG_TYPE_VFD)
477330fc
RM		 1474 {
1475 first_error (_("only D registers may be indexed"));
1476 return FAIL;
1477 }
5f4273c7 1478
dcbf9037 1479 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 1480 {
1481 first_error (_("can't change index for operand"));
1482 return FAIL;
1483 }
dcbf9037
JB		 1484
1485 atype.defined |= NTA_HASINDEX;
1486
1487 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1488 atype.index = NEON_ALL_LANES;
dcbf9037 1489 else
477330fc
RM		 1490 {
1491 expressionS exp;
dcbf9037 1492
477330fc 1493 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1494
477330fc
RM		 1495 if (exp.X_op != O_constant)
1496 {
1497 first_error (_("constant expression required"));
1498 return FAIL;
1499 }
dcbf9037 1500
477330fc
RM		 1501 if (skip_past_char (&str, ']') == FAIL)
1502 return FAIL;
dcbf9037 1503
477330fc
RM		 1504 atype.index = exp.X_add_number;
1505 }
dcbf9037 1506 }
5f4273c7 1507
dcbf9037
JB		 1508 if (typeinfo)
1509 *typeinfo = atype;
5f4273c7 1510
dcbf9037
JB		 1511 if (rtype)
1512 *rtype = type;
5f4273c7 1513
dcbf9037 1514 *ccp = str;
5f4273c7 1515
dcbf9037
JB		 1516 return reg->number;
1517}
1518
1519/* Like arm_reg_parse, but allow allow the following extra features:
1520 - If RTYPE is non-zero, return the (possibly restricted) type of the
1521 register (e.g. Neon double or quad reg when either has been requested).
1522 - If this is a Neon vector type with additional type information, fill
1523 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1524 This function will fault on encountering a scalar. */
dcbf9037
JB		 1525
1526static int
1527arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1528 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB		 1529{
1530 struct neon_typed_alias atype;
1531 char *str = *ccp;
1532 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1533
1534 if (reg == FAIL)
1535 return FAIL;
1536
0855e32b
NS		 1537 /* Do not allow regname(... to parse as a register. */
1538 if (*str == '(')
1539 return FAIL;
1540
dcbf9037
JB		 1541 /* Do not allow a scalar (reg+index) to parse as a register. */
1542 if ((atype.defined & NTA_HASINDEX) != 0)
1543 {
1544 first_error (_("register operand expected, but got scalar"));
1545 return FAIL;
1546 }
1547
1548 if (vectype)
1549 *vectype = atype.eltype;
1550
1551 *ccp = str;
1552
1553 return reg;
1554}
1555
1556#define NEON_SCALAR_REG(X) ((X) >> 4)
1557#define NEON_SCALAR_INDEX(X) ((X) & 15)
1558
5287ad62
JB		 1559/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1560 have enough information to be able to do a good job bounds-checking. So, we
1561 just do easy checks here, and do further checks later. */
1562
1563static int
dcbf9037 1564parse_scalar (char **ccp, int elsize, struct neon_type_el *type)
5287ad62 1565{
dcbf9037 1566 int reg;
5287ad62 1567 char *str = *ccp;
dcbf9037 1568 struct neon_typed_alias atype;
5f4273c7 1569
dcbf9037 1570 reg = parse_typed_reg_or_scalar (&str, REG_TYPE_VFD, NULL, &atype);
5f4273c7 1571
dcbf9037 1572 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1573 return FAIL;
5f4273c7 1574
dcbf9037 1575 if (atype.index == NEON_ALL_LANES)
5287ad62 1576 {
dcbf9037 1577 first_error (_("scalar must have an index"));
5287ad62
JB		 1578 return FAIL;
1579 }
dcbf9037 1580 else if (atype.index >= 64 / elsize)
5287ad62 1581 {
dcbf9037 1582 first_error (_("scalar index out of range"));
5287ad62
JB		 1583 return FAIL;
1584 }
5f4273c7 1585
dcbf9037
JB		 1586 if (type)
1587 *type = atype.eltype;
5f4273c7 1588
5287ad62 1589 *ccp = str;
5f4273c7 1590
dcbf9037 1591 return reg * 16 + atype.index;
5287ad62
JB		 1592}
1593
c19d1205 1594/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1595
c19d1205
ZW		 1596static long
1597parse_reg_list (char ** strp)
1598{
1599 char * str = * strp;
1600 long range = 0;
1601 int another_range;
a737bd4d 1602
c19d1205
ZW		 1603 /* We come back here if we get ranges concatenated by '+' or '|'. */
1604 do
6057a28f 1605 {
477330fc
RM		 1606 skip_whitespace (str);
1607
c19d1205 1608 another_range = 0;
a737bd4d 1609
c19d1205
ZW		 1610 if (*str == '{')
1611 {
1612 int in_range = 0;
1613 int cur_reg = -1;
a737bd4d 1614
c19d1205
ZW		 1615 str++;
1616 do
1617 {
1618 int reg;
6057a28f 1619
dcbf9037 1620 if ((reg = arm_reg_parse (&str, REG_TYPE_RN)) == FAIL)
c19d1205 1621 {
dcbf9037 1622 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
c19d1205
ZW		 1623 return FAIL;
1624 }
a737bd4d 1625
c19d1205
ZW		 1626 if (in_range)
1627 {
1628 int i;
a737bd4d 1629
c19d1205
ZW		 1630 if (reg <= cur_reg)
1631 {
dcbf9037 1632 first_error (_("bad range in register list"));
c19d1205
ZW		 1633 return FAIL;
1634 }
40a18ebd 1635
c19d1205
ZW		 1636 for (i = cur_reg + 1; i < reg; i++)
1637 {
1638 if (range & (1 << i))
1639 as_tsktsk
1640 (_("Warning: duplicated register (r%d) in register list"),
1641 i);
1642 else
1643 range |= 1 << i;
1644 }
1645 in_range = 0;
1646 }
a737bd4d 1647
c19d1205
ZW		 1648 if (range & (1 << reg))
1649 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1650 reg);
1651 else if (reg <= cur_reg)
1652 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1653
c19d1205
ZW		 1654 range |= 1 << reg;
1655 cur_reg = reg;
1656 }
1657 while (skip_past_comma (&str) != FAIL
1658 || (in_range = 1, *str++ == '-'));
1659 str--;
a737bd4d 1660
d996d970 1661 if (skip_past_char (&str, '}') == FAIL)
c19d1205 1662 {
dcbf9037 1663 first_error (_("missing `}'"));
c19d1205
ZW		 1664 return FAIL;
1665 }
1666 }
1667 else
1668 {
91d6fa6a 1669 expressionS exp;
40a18ebd 1670
91d6fa6a 1671 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1672 return FAIL;
40a18ebd 1673
91d6fa6a 1674 if (exp.X_op == O_constant)
c19d1205 1675 {
91d6fa6a
NC		 1676 if (exp.X_add_number
1677 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW		 1678 {
1679 inst.error = _("invalid register mask");
1680 return FAIL;
1681 }
a737bd4d 1682
91d6fa6a 1683 if ((range & exp.X_add_number) != 0)
c19d1205 1684 {
91d6fa6a 1685 int regno = range & exp.X_add_number;
a737bd4d 1686
c19d1205
ZW		 1687 regno &= -regno;
1688 regno = (1 << regno) - 1;
1689 as_tsktsk
1690 (_("Warning: duplicated register (r%d) in register list"),
1691 regno);
1692 }
a737bd4d 1693
91d6fa6a 1694 range |= exp.X_add_number;
c19d1205
ZW		 1695 }
1696 else
1697 {
1698 if (inst.reloc.type != 0)
1699 {
1700 inst.error = _("expression too complex");
1701 return FAIL;
1702 }
a737bd4d 1703
91d6fa6a 1704 memcpy (&inst.reloc.exp, &exp, sizeof (expressionS));
c19d1205
ZW		 1705 inst.reloc.type = BFD_RELOC_ARM_MULTI;
1706 inst.reloc.pc_rel = 0;
1707 }
1708 }
a737bd4d 1709
c19d1205
ZW		 1710 if (*str == '|' || *str == '+')
1711 {
1712 str++;
1713 another_range = 1;
1714 }
a737bd4d 1715 }
c19d1205 1716 while (another_range);
a737bd4d 1717
c19d1205
ZW		 1718 *strp = str;
1719 return range;
a737bd4d
NC		 1720}
1721
5287ad62
JB		 1722/* Types of registers in a list. */
1723
1724enum reg_list_els
1725{
1726 REGLIST_VFP_S,
1727 REGLIST_VFP_D,
1728 REGLIST_NEON_D
1729};
1730
c19d1205
ZW		 1731/* Parse a VFP register list. If the string is invalid return FAIL.
1732 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB		 1733 register. Parses registers of type ETYPE.
1734 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1735 - Q registers can be used to specify pairs of D registers
1736 - { } can be omitted from around a singleton register list
477330fc
RM		 1737 FIXME: This is not implemented, as it would require backtracking in
1738 some cases, e.g.:
1739 vtbl.8 d3,d4,d5
1740 This could be done (the meaning isn't really ambiguous), but doesn't
1741 fit in well with the current parsing framework.
dcbf9037
JB		 1742 - 32 D registers may be used (also true for VFPv3).
1743 FIXME: Types are ignored in these register lists, which is probably a
1744 bug. */
6057a28f 1745
c19d1205 1746static int
037e8744 1747parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype)
6057a28f 1748{
037e8744 1749 char *str = *ccp;
c19d1205
ZW		 1750 int base_reg;
1751 int new_base;
21d799b5 1752 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 1753 int max_regs = 0;
c19d1205
ZW		 1754 int count = 0;
1755 int warned = 0;
1756 unsigned long mask = 0;
a737bd4d 1757 int i;
6057a28f 1758
477330fc 1759 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB		 1760 {
1761 inst.error = _("expecting {");
1762 return FAIL;
1763 }
6057a28f 1764
5287ad62 1765 switch (etype)
c19d1205 1766 {
5287ad62 1767 case REGLIST_VFP_S:
c19d1205
ZW		 1768 regtype = REG_TYPE_VFS;
1769 max_regs = 32;
5287ad62 1770 break;
5f4273c7 1771
5287ad62
JB		 1772 case REGLIST_VFP_D:
1773 regtype = REG_TYPE_VFD;
b7fc2769 1774 break;
5f4273c7 1775
b7fc2769
JB		 1776 case REGLIST_NEON_D:
1777 regtype = REG_TYPE_NDQ;
1778 break;
1779 }
1780
1781 if (etype != REGLIST_VFP_S)
1782 {
b1cc4aeb
PB		 1783 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1784 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 1785 {
1786 max_regs = 32;
1787 if (thumb_mode)
1788 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
1789 fpu_vfp_ext_d32);
1790 else
1791 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
1792 fpu_vfp_ext_d32);
1793 }
5287ad62 1794 else
477330fc 1795 max_regs = 16;
c19d1205 1796 }
6057a28f 1797
c19d1205 1798 base_reg = max_regs;
a737bd4d 1799
c19d1205
ZW		 1800 do
1801 {
5287ad62 1802 int setmask = 1, addregs = 1;
dcbf9037 1803
037e8744 1804 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 1805
c19d1205 1806 if (new_base == FAIL)
a737bd4d 1807 {
dcbf9037 1808 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW		 1809 return FAIL;
1810 }
5f4273c7 1811
b7fc2769 1812 if (new_base >= max_regs)
477330fc
RM		 1813 {
1814 first_error (_("register out of range in list"));
1815 return FAIL;
1816 }
5f4273c7 1817
5287ad62
JB		 1818 /* Note: a value of 2 * n is returned for the register Q<n>. */
1819 if (regtype == REG_TYPE_NQ)
477330fc
RM		 1820 {
1821 setmask = 3;
1822 addregs = 2;
1823 }
5287ad62 1824
c19d1205
ZW		 1825 if (new_base < base_reg)
1826 base_reg = new_base;
a737bd4d 1827
5287ad62 1828 if (mask & (setmask << new_base))
c19d1205 1829 {
dcbf9037 1830 first_error (_("invalid register list"));
c19d1205 1831 return FAIL;
a737bd4d 1832 }
a737bd4d 1833
c19d1205
ZW		 1834 if ((mask >> new_base) != 0 && ! warned)
1835 {
1836 as_tsktsk (_("register list not in ascending order"));
1837 warned = 1;
1838 }
0bbf2aa4 1839
5287ad62
JB		 1840 mask |= setmask << new_base;
1841 count += addregs;
0bbf2aa4 1842
037e8744 1843 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW		 1844 {
1845 int high_range;
0bbf2aa4 1846
037e8744 1847 str++;
0bbf2aa4 1848
037e8744 1849 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 1850 == FAIL)
c19d1205
ZW		 1851 {
1852 inst.error = gettext (reg_expected_msgs[regtype]);
1853 return FAIL;
1854 }
0bbf2aa4 1855
477330fc
RM		 1856 if (high_range >= max_regs)
1857 {
1858 first_error (_("register out of range in list"));
1859 return FAIL;
1860 }
b7fc2769 1861
477330fc
RM		 1862 if (regtype == REG_TYPE_NQ)
1863 high_range = high_range + 1;
5287ad62 1864
c19d1205
ZW		 1865 if (high_range <= new_base)
1866 {
1867 inst.error = _("register range not in ascending order");
1868 return FAIL;
1869 }
0bbf2aa4 1870
5287ad62 1871 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 1872 {
5287ad62 1873 if (mask & (setmask << new_base))
0bbf2aa4 1874 {
c19d1205
ZW		 1875 inst.error = _("invalid register list");
1876 return FAIL;
0bbf2aa4 1877 }
c19d1205 1878
5287ad62
JB		 1879 mask |= setmask << new_base;
1880 count += addregs;
0bbf2aa4 1881 }
0bbf2aa4 1882 }
0bbf2aa4 1883 }
037e8744 1884 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 1885
037e8744 1886 str++;
0bbf2aa4 1887
c19d1205
ZW		 1888 /* Sanity check -- should have raised a parse error above. */
1889 if (count == 0 || count > max_regs)
1890 abort ();
1891
1892 *pbase = base_reg;
1893
1894 /* Final test -- the registers must be consecutive. */
1895 mask >>= base_reg;
1896 for (i = 0; i < count; i++)
1897 {
1898 if ((mask & (1u << i)) == 0)
1899 {
1900 inst.error = _("non-contiguous register range");
1901 return FAIL;
1902 }
1903 }
1904
037e8744
JB		 1905 *ccp = str;
1906
c19d1205 1907 return count;
b99bd4ef
NC		 1908}
1909
dcbf9037
JB		 1910/* True if two alias types are the same. */
1911
c921be7d 1912static bfd_boolean
dcbf9037
JB		 1913neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
1914{
1915 if (!a && !b)
c921be7d 1916 return TRUE;
5f4273c7 1917
dcbf9037 1918 if (!a || !b)
c921be7d 1919 return FALSE;
dcbf9037
JB		 1920
1921 if (a->defined != b->defined)
c921be7d 1922 return FALSE;
5f4273c7 1923
dcbf9037
JB		 1924 if ((a->defined & NTA_HASTYPE) != 0
1925 && (a->eltype.type != b->eltype.type
477330fc 1926 || a->eltype.size != b->eltype.size))
c921be7d 1927 return FALSE;
dcbf9037
JB		 1928
1929 if ((a->defined & NTA_HASINDEX) != 0
1930 && (a->index != b->index))
c921be7d 1931 return FALSE;
5f4273c7 1932
c921be7d 1933 return TRUE;
dcbf9037
JB		 1934}
1935
5287ad62
JB		 1936/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1937 The base register is put in *PBASE.
dcbf9037 1938 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB		 1939 the return value.
1940 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB		 1941 Bits [6:5] encode the list length (minus one).
1942 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 1943
5287ad62 1944#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 1945#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB		 1946#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1947
1948static int
dcbf9037 1949parse_neon_el_struct_list (char **str, unsigned *pbase,
477330fc 1950 struct neon_type_el *eltype)
5287ad62
JB		 1951{
1952 char *ptr = *str;
1953 int base_reg = -1;
1954 int reg_incr = -1;
1955 int count = 0;
1956 int lane = -1;
1957 int leading_brace = 0;
1958 enum arm_reg_type rtype = REG_TYPE_NDQ;
20203fb9
NC		 1959 const char *const incr_error = _("register stride must be 1 or 2");
1960 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 1961 struct neon_typed_alias firsttype;
5f4273c7 1962
5287ad62
JB		 1963 if (skip_past_char (&ptr, '{') == SUCCESS)
1964 leading_brace = 1;
5f4273c7 1965
5287ad62
JB		 1966 do
1967 {
dcbf9037
JB		 1968 struct neon_typed_alias atype;
1969 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
1970
5287ad62 1971 if (getreg == FAIL)
477330fc
RM		 1972 {
1973 first_error (_(reg_expected_msgs[rtype]));
1974 return FAIL;
1975 }
5f4273c7 1976
5287ad62 1977 if (base_reg == -1)
477330fc
RM		 1978 {
1979 base_reg = getreg;
1980 if (rtype == REG_TYPE_NQ)
1981 {
1982 reg_incr = 1;
1983 }
1984 firsttype = atype;
1985 }
5287ad62 1986 else if (reg_incr == -1)
477330fc
RM		 1987 {
1988 reg_incr = getreg - base_reg;
1989 if (reg_incr < 1 || reg_incr > 2)
1990 {
1991 first_error (_(incr_error));
1992 return FAIL;
1993 }
1994 }
5287ad62 1995 else if (getreg != base_reg + reg_incr * count)
477330fc
RM		 1996 {
1997 first_error (_(incr_error));
1998 return FAIL;
1999 }
dcbf9037 2000
c921be7d 2001 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM		 2002 {
2003 first_error (_(type_error));
2004 return FAIL;
2005 }
5f4273c7 2006
5287ad62 2007 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 2008 modes. */
5287ad62 2009 if (ptr[0] == '-')
477330fc
RM		 2010 {
2011 struct neon_typed_alias htype;
2012 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2013 if (lane == -1)
2014 lane = NEON_INTERLEAVE_LANES;
2015 else if (lane != NEON_INTERLEAVE_LANES)
2016 {
2017 first_error (_(type_error));
2018 return FAIL;
2019 }
2020 if (reg_incr == -1)
2021 reg_incr = 1;
2022 else if (reg_incr != 1)
2023 {
2024 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2025 return FAIL;
2026 }
2027 ptr++;
2028 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2029 if (hireg == FAIL)
2030 {
2031 first_error (_(reg_expected_msgs[rtype]));
2032 return FAIL;
2033 }
2034 if (! neon_alias_types_same (&htype, &firsttype))
2035 {
2036 first_error (_(type_error));
2037 return FAIL;
2038 }
2039 count += hireg + dregs - getreg;
2040 continue;
2041 }
5f4273c7 2042
5287ad62
JB		 2043 /* If we're using Q registers, we can't use [] or [n] syntax. */
2044 if (rtype == REG_TYPE_NQ)
477330fc
RM		 2045 {
2046 count += 2;
2047 continue;
2048 }
5f4273c7 2049
dcbf9037 2050 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 2051 {
2052 if (lane == -1)
2053 lane = atype.index;
2054 else if (lane != atype.index)
2055 {
2056 first_error (_(type_error));
2057 return FAIL;
2058 }
2059 }
5287ad62 2060 else if (lane == -1)
477330fc 2061 lane = NEON_INTERLEAVE_LANES;
5287ad62 2062 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM		 2063 {
2064 first_error (_(type_error));
2065 return FAIL;
2066 }
5287ad62
JB		 2067 count++;
2068 }
2069 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2070
5287ad62
JB		 2071 /* No lane set by [x]. We must be interleaving structures. */
2072 if (lane == -1)
2073 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2074
5287ad62
JB		 2075 /* Sanity check. */
2076 if (lane == -1 || base_reg == -1 || count < 1 || count > 4
2077 || (count > 1 && reg_incr == -1))
2078 {
dcbf9037 2079 first_error (_("error parsing element/structure list"));
5287ad62
JB		 2080 return FAIL;
2081 }
2082
2083 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2084 {
dcbf9037 2085 first_error (_("expected }"));
5287ad62
JB		 2086 return FAIL;
2087 }
5f4273c7 2088
5287ad62
JB		 2089 if (reg_incr == -1)
2090 reg_incr = 1;
2091
dcbf9037
JB		 2092 if (eltype)
2093 *eltype = firsttype.eltype;
2094
5287ad62
JB		 2095 *pbase = base_reg;
2096 *str = ptr;
5f4273c7 2097
5287ad62
JB		 2098 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2099}
2100
c19d1205
ZW		 2101/* Parse an explicit relocation suffix on an expression. This is
2102 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2103 arm_reloc_hsh contains no entries, so this function can only
2104 succeed if there is no () after the word. Returns -1 on error,
2105 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2106
c19d1205
ZW		 2107static int
2108parse_reloc (char **str)
b99bd4ef 2109{
c19d1205
ZW		 2110 struct reloc_entry *r;
2111 char *p, *q;
b99bd4ef 2112
c19d1205
ZW		 2113 if (**str != '(')
2114 return BFD_RELOC_UNUSED;
b99bd4ef 2115
c19d1205
ZW		 2116 p = *str + 1;
2117 q = p;
2118
2119 while (*q && *q != ')' && *q != ',')
2120 q++;
2121 if (*q != ')')
2122 return -1;
2123
21d799b5
NC		 2124 if ((r = (struct reloc_entry *)
2125 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW		 2126 return -1;
2127
2128 *str = q + 1;
2129 return r->reloc;
b99bd4ef
NC		 2130}
2131
c19d1205
ZW		 2132/* Directives: register aliases. */
2133
dcbf9037 2134static struct reg_entry *
90ec0d68 2135insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2136{
d3ce72d0 2137 struct reg_entry *new_reg;
c19d1205 2138 const char *name;
b99bd4ef 2139
d3ce72d0 2140 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2141 {
d3ce72d0 2142 if (new_reg->builtin)
c19d1205 2143 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2144
c19d1205
ZW		 2145 /* Only warn about a redefinition if it's not defined as the
2146 same register. */
d3ce72d0 2147 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2148 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2149
d929913e 2150 return NULL;
c19d1205 2151 }
b99bd4ef 2152
c19d1205 2153 name = xstrdup (str);
d3ce72d0 2154 new_reg = (struct reg_entry *) xmalloc (sizeof (struct reg_entry));
b99bd4ef 2155
d3ce72d0
NC		 2156 new_reg->name = name;
2157 new_reg->number = number;
2158 new_reg->type = type;
2159 new_reg->builtin = FALSE;
2160 new_reg->neon = NULL;
b99bd4ef 2161
d3ce72d0 2162 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2163 abort ();
5f4273c7 2164
d3ce72d0 2165 return new_reg;
dcbf9037
JB		 2166}
2167
2168static void
2169insert_neon_reg_alias (char *str, int number, int type,
477330fc 2170 struct neon_typed_alias *atype)
dcbf9037
JB		 2171{
2172 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2173
dcbf9037
JB		 2174 if (!reg)
2175 {
2176 first_error (_("attempt to redefine typed alias"));
2177 return;
2178 }
5f4273c7 2179
dcbf9037
JB		 2180 if (atype)
2181 {
21d799b5 2182 reg->neon = (struct neon_typed_alias *)
477330fc 2183 xmalloc (sizeof (struct neon_typed_alias));
dcbf9037
JB		 2184 *reg->neon = *atype;
2185 }
c19d1205 2186}
b99bd4ef 2187
c19d1205 2188/* Look for the .req directive. This is of the form:
b99bd4ef 2189
c19d1205 2190 new_register_name .req existing_register_name
b99bd4ef 2191
c19d1205 2192 If we find one, or if it looks sufficiently like one that we want to
d929913e 2193 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2194
d929913e 2195static bfd_boolean
c19d1205
ZW		 2196create_register_alias (char * newname, char *p)
2197{
2198 struct reg_entry *old;
2199 char *oldname, *nbuf;
2200 size_t nlen;
b99bd4ef 2201
c19d1205
ZW		 2202 /* The input scrubber ensures that whitespace after the mnemonic is
2203 collapsed to single spaces. */
2204 oldname = p;
2205 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2206 return FALSE;
b99bd4ef 2207
c19d1205
ZW		 2208 oldname += 6;
2209 if (*oldname == '\0')
d929913e 2210 return FALSE;
b99bd4ef 2211
21d799b5 2212 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2213 if (!old)
b99bd4ef 2214 {
c19d1205 2215 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2216 return TRUE;
b99bd4ef
NC		 2217 }
2218
c19d1205
ZW		 2219 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2220 the desired alias name, and p points to its end. If not, then
2221 the desired alias name is in the global original_case_string. */
2222#ifdef TC_CASE_SENSITIVE
2223 nlen = p - newname;
2224#else
2225 newname = original_case_string;
2226 nlen = strlen (newname);
2227#endif
b99bd4ef 2228
21d799b5 2229 nbuf = (char *) alloca (nlen + 1);
c19d1205
ZW		 2230 memcpy (nbuf, newname, nlen);
2231 nbuf[nlen] = '\0';
b99bd4ef 2232
c19d1205
ZW		 2233 /* Create aliases under the new name as stated; an all-lowercase
2234 version of the new name; and an all-uppercase version of the new
2235 name. */
d929913e
NC		 2236 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2237 {
2238 for (p = nbuf; *p; p++)
2239 *p = TOUPPER (*p);
c19d1205 2240
d929913e
NC		 2241 if (strncmp (nbuf, newname, nlen))
2242 {
2243 /* If this attempt to create an additional alias fails, do not bother
2244 trying to create the all-lower case alias. We will fail and issue
2245 a second, duplicate error message. This situation arises when the
2246 programmer does something like:
2247 foo .req r0
2248 Foo .req r1
2249 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2250 the artificial FOO alias because it has already been created by the
d929913e
NC		 2251 first .req. */
2252 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
2253 return TRUE;
2254 }
c19d1205 2255
d929913e
NC		 2256 for (p = nbuf; *p; p++)
2257 *p = TOLOWER (*p);
c19d1205 2258
d929913e
NC		 2259 if (strncmp (nbuf, newname, nlen))
2260 insert_reg_alias (nbuf, old->number, old->type);
2261 }
c19d1205 2262
d929913e 2263 return TRUE;
b99bd4ef
NC		 2264}
2265
dcbf9037
JB		 2266/* Create a Neon typed/indexed register alias using directives, e.g.:
2267 X .dn d5.s32[1]
2268 Y .qn 6.s16
2269 Z .dn d7
2270 T .dn Z[0]
2271 These typed registers can be used instead of the types specified after the
2272 Neon mnemonic, so long as all operands given have types. Types can also be
2273 specified directly, e.g.:
5f4273c7 2274 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2275
c921be7d 2276static bfd_boolean
dcbf9037
JB		 2277create_neon_reg_alias (char *newname, char *p)
2278{
2279 enum arm_reg_type basetype;
2280 struct reg_entry *basereg;
2281 struct reg_entry mybasereg;
2282 struct neon_type ntype;
2283 struct neon_typed_alias typeinfo;
12d6b0b7 2284 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2285 int namelen;
5f4273c7 2286
dcbf9037
JB		 2287 typeinfo.defined = 0;
2288 typeinfo.eltype.type = NT_invtype;
2289 typeinfo.eltype.size = -1;
2290 typeinfo.index = -1;
5f4273c7 2291
dcbf9037 2292 nameend = p;
5f4273c7 2293
dcbf9037
JB		 2294 if (strncmp (p, " .dn ", 5) == 0)
2295 basetype = REG_TYPE_VFD;
2296 else if (strncmp (p, " .qn ", 5) == 0)
2297 basetype = REG_TYPE_NQ;
2298 else
c921be7d 2299 return FALSE;
5f4273c7 2300
dcbf9037 2301 p += 5;
5f4273c7 2302
dcbf9037 2303 if (*p == '\0')
c921be7d 2304 return FALSE;
5f4273c7 2305
dcbf9037
JB		 2306 basereg = arm_reg_parse_multi (&p);
2307
2308 if (basereg && basereg->type != basetype)
2309 {
2310 as_bad (_("bad type for register"));
c921be7d 2311 return FALSE;
dcbf9037
JB		 2312 }
2313
2314 if (basereg == NULL)
2315 {
2316 expressionS exp;
2317 /* Try parsing as an integer. */
2318 my_get_expression (&exp, &p, GE_NO_PREFIX);
2319 if (exp.X_op != O_constant)
477330fc
RM		 2320 {
2321 as_bad (_("expression must be constant"));
2322 return FALSE;
2323 }
dcbf9037
JB		 2324 basereg = &mybasereg;
2325 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2326 : exp.X_add_number;
dcbf9037
JB		 2327 basereg->neon = 0;
2328 }
2329
2330 if (basereg->neon)
2331 typeinfo = *basereg->neon;
2332
2333 if (parse_neon_type (&ntype, &p) == SUCCESS)
2334 {
2335 /* We got a type. */
2336 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM		 2337 {
2338 as_bad (_("can't redefine the type of a register alias"));
2339 return FALSE;
2340 }
5f4273c7 2341
dcbf9037
JB		 2342 typeinfo.defined |= NTA_HASTYPE;
2343 if (ntype.elems != 1)
477330fc
RM		 2344 {
2345 as_bad (_("you must specify a single type only"));
2346 return FALSE;
2347 }
dcbf9037
JB		 2348 typeinfo.eltype = ntype.el[0];
2349 }
5f4273c7 2350
dcbf9037
JB		 2351 if (skip_past_char (&p, '[') == SUCCESS)
2352 {
2353 expressionS exp;
2354 /* We got a scalar index. */
5f4273c7 2355
dcbf9037 2356 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM		 2357 {
2358 as_bad (_("can't redefine the index of a scalar alias"));
2359 return FALSE;
2360 }
5f4273c7 2361
dcbf9037 2362 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2363
dcbf9037 2364 if (exp.X_op != O_constant)
477330fc
RM		 2365 {
2366 as_bad (_("scalar index must be constant"));
2367 return FALSE;
2368 }
5f4273c7 2369
dcbf9037
JB		 2370 typeinfo.defined |= NTA_HASINDEX;
2371 typeinfo.index = exp.X_add_number;
5f4273c7 2372
dcbf9037 2373 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM		 2374 {
2375 as_bad (_("expecting ]"));
2376 return FALSE;
2377 }
dcbf9037
JB		 2378 }
2379
15735687
NS		 2380 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2381 the desired alias name, and p points to its end. If not, then
2382 the desired alias name is in the global original_case_string. */
2383#ifdef TC_CASE_SENSITIVE
dcbf9037 2384 namelen = nameend - newname;
15735687
NS		 2385#else
2386 newname = original_case_string;
2387 namelen = strlen (newname);
2388#endif
2389
21d799b5 2390 namebuf = (char *) alloca (namelen + 1);
dcbf9037
JB		 2391 strncpy (namebuf, newname, namelen);
2392 namebuf[namelen] = '\0';
5f4273c7 2393
dcbf9037 2394 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2395 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2396
dcbf9037
JB		 2397 /* Insert name in all uppercase. */
2398 for (p = namebuf; *p; p++)
2399 *p = TOUPPER (*p);
5f4273c7 2400
dcbf9037
JB		 2401 if (strncmp (namebuf, newname, namelen))
2402 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2403 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2404
dcbf9037
JB		 2405 /* Insert name in all lowercase. */
2406 for (p = namebuf; *p; p++)
2407 *p = TOLOWER (*p);
5f4273c7 2408
dcbf9037
JB		 2409 if (strncmp (namebuf, newname, namelen))
2410 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2411 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2412
c921be7d 2413 return TRUE;
dcbf9037
JB		 2414}
2415
c19d1205
ZW		 2416/* Should never be called, as .req goes between the alias and the
2417 register name, not at the beginning of the line. */
c921be7d 2418
b99bd4ef 2419static void
c19d1205 2420s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2421{
c19d1205
ZW		 2422 as_bad (_("invalid syntax for .req directive"));
2423}
b99bd4ef 2424
dcbf9037
JB		 2425static void
2426s_dn (int a ATTRIBUTE_UNUSED)
2427{
2428 as_bad (_("invalid syntax for .dn directive"));
2429}
2430
2431static void
2432s_qn (int a ATTRIBUTE_UNUSED)
2433{
2434 as_bad (_("invalid syntax for .qn directive"));
2435}
2436
c19d1205
ZW		 2437/* The .unreq directive deletes an alias which was previously defined
2438 by .req. For example:
b99bd4ef 2439
c19d1205
ZW		 2440 my_alias .req r11
2441 .unreq my_alias */
b99bd4ef
NC		 2442
2443static void
c19d1205 2444s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2445{
c19d1205
ZW		 2446 char * name;
2447 char saved_char;
b99bd4ef 2448
c19d1205
ZW		 2449 name = input_line_pointer;
2450
2451 while (*input_line_pointer != 0
2452 && *input_line_pointer != ' '
2453 && *input_line_pointer != '\n')
2454 ++input_line_pointer;
2455
2456 saved_char = *input_line_pointer;
2457 *input_line_pointer = 0;
2458
2459 if (!*name)
2460 as_bad (_("invalid syntax for .unreq directive"));
2461 else
2462 {
21d799b5 2463 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2464 name);
c19d1205
ZW		 2465
2466 if (!reg)
2467 as_bad (_("unknown register alias '%s'"), name);
2468 else if (reg->builtin)
a1727c1a 2469 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW		 2470 name);
2471 else
2472 {
d929913e
NC		 2473 char * p;
2474 char * nbuf;
2475
db0bc284 2476 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2477 free ((char *) reg->name);
477330fc
RM		 2478 if (reg->neon)
2479 free (reg->neon);
c19d1205 2480 free (reg);
d929913e
NC		 2481
2482 /* Also locate the all upper case and all lower case versions.
2483 Do not complain if we cannot find one or the other as it
2484 was probably deleted above. */
5f4273c7 2485
d929913e
NC		 2486 nbuf = strdup (name);
2487 for (p = nbuf; *p; p++)
2488 *p = TOUPPER (*p);
21d799b5 2489 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2490 if (reg)
2491 {
db0bc284 2492 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2493 free ((char *) reg->name);
2494 if (reg->neon)
2495 free (reg->neon);
2496 free (reg);
2497 }
2498
2499 for (p = nbuf; *p; p++)
2500 *p = TOLOWER (*p);
21d799b5 2501 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2502 if (reg)
2503 {
db0bc284 2504 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2505 free ((char *) reg->name);
2506 if (reg->neon)
2507 free (reg->neon);
2508 free (reg);
2509 }
2510
2511 free (nbuf);
c19d1205
ZW		 2512 }
2513 }
b99bd4ef 2514
c19d1205 2515 *input_line_pointer = saved_char;
b99bd4ef
NC		 2516 demand_empty_rest_of_line ();
2517}
2518
c19d1205
ZW		 2519/* Directives: Instruction set selection. */
2520
2521#ifdef OBJ_ELF
2522/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2523 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2524 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2525 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2526
cd000bff
DJ		 2527/* Create a new mapping symbol for the transition to STATE. */
2528
2529static void
2530make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2531{
a737bd4d 2532 symbolS * symbolP;
c19d1205
ZW		 2533 const char * symname;
2534 int type;
b99bd4ef 2535
c19d1205 2536 switch (state)
b99bd4ef 2537 {
c19d1205
ZW		 2538 case MAP_DATA:
2539 symname = "$d";
2540 type = BSF_NO_FLAGS;
2541 break;
2542 case MAP_ARM:
2543 symname = "$a";
2544 type = BSF_NO_FLAGS;
2545 break;
2546 case MAP_THUMB:
2547 symname = "$t";
2548 type = BSF_NO_FLAGS;
2549 break;
c19d1205
ZW		 2550 default:
2551 abort ();
2552 }
2553
cd000bff 2554 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW		 2555 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2556
2557 switch (state)
2558 {
2559 case MAP_ARM:
2560 THUMB_SET_FUNC (symbolP, 0);
2561 ARM_SET_THUMB (symbolP, 0);
2562 ARM_SET_INTERWORK (symbolP, support_interwork);
2563 break;
2564
2565 case MAP_THUMB:
2566 THUMB_SET_FUNC (symbolP, 1);
2567 ARM_SET_THUMB (symbolP, 1);
2568 ARM_SET_INTERWORK (symbolP, support_interwork);
2569 break;
2570
2571 case MAP_DATA:
2572 default:
cd000bff
DJ		 2573 break;
2574 }
2575
2576 /* Save the mapping symbols for future reference. Also check that
2577 we do not place two mapping symbols at the same offset within a
2578 frag. We'll handle overlap between frags in
2de7820f
JZ		 2579 check_mapping_symbols.
2580
2581 If .fill or other data filling directive generates zero sized data,
2582 the mapping symbol for the following code will have the same value
2583 as the one generated for the data filling directive. In this case,
2584 we replace the old symbol with the new one at the same address. */
cd000bff
DJ		 2585 if (value == 0)
2586 {
2de7820f
JZ		 2587 if (frag->tc_frag_data.first_map != NULL)
2588 {
2589 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2590 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2591 }
cd000bff
DJ		 2592 frag->tc_frag_data.first_map = symbolP;
2593 }
2594 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ		 2595 {
2596 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ		 2597 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2598 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2599 }
cd000bff
DJ		 2600 frag->tc_frag_data.last_map = symbolP;
2601}
2602
2603/* We must sometimes convert a region marked as code to data during
2604 code alignment, if an odd number of bytes have to be padded. The
2605 code mapping symbol is pushed to an aligned address. */
2606
2607static void
2608insert_data_mapping_symbol (enum mstate state,
2609 valueT value, fragS *frag, offsetT bytes)
2610{
2611 /* If there was already a mapping symbol, remove it. */
2612 if (frag->tc_frag_data.last_map != NULL
2613 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2614 {
2615 symbolS *symp = frag->tc_frag_data.last_map;
2616
2617 if (value == 0)
2618 {
2619 know (frag->tc_frag_data.first_map == symp);
2620 frag->tc_frag_data.first_map = NULL;
2621 }
2622 frag->tc_frag_data.last_map = NULL;
2623 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2624 }
cd000bff
DJ		 2625
2626 make_mapping_symbol (MAP_DATA, value, frag);
2627 make_mapping_symbol (state, value + bytes, frag);
2628}
2629
2630static void mapping_state_2 (enum mstate state, int max_chars);
2631
2632/* Set the mapping state to STATE. Only call this when about to
2633 emit some STATE bytes to the file. */
2634
4e9aaefb 2635#define TRANSITION(from, to) (mapstate == (from) && state == (to))
cd000bff
DJ		 2636void
2637mapping_state (enum mstate state)
2638{
940b5ce0
DJ		 2639 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2640
cd000bff
DJ		 2641 if (mapstate == state)
2642 /* The mapping symbol has already been emitted.
2643 There is nothing else to do. */
2644 return;
49c62a33
NC		 2645
2646 if (state == MAP_ARM || state == MAP_THUMB)
2647 /* PR gas/12931
2648 All ARM instructions require 4-byte alignment.
2649 (Almost) all Thumb instructions require 2-byte alignment.
2650
2651 When emitting instructions into any section, mark the section
2652 appropriately.
2653
2654 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2655 but themselves require 2-byte alignment; this applies to some
2656 PC- relative forms. However, these cases will invovle implicit
2657 literal pool generation or an explicit .align >=2, both of
2658 which will cause the section to me marked with sufficient
2659 alignment. Thus, we don't handle those cases here. */
2660 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2661
2662 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
4e9aaefb 2663 /* This case will be evaluated later. */
cd000bff 2664 return;
cd000bff
DJ		 2665
2666 mapping_state_2 (state, 0);
cd000bff
DJ		 2667}
2668
2669/* Same as mapping_state, but MAX_CHARS bytes have already been
2670 allocated. Put the mapping symbol that far back. */
2671
2672static void
2673mapping_state_2 (enum mstate state, int max_chars)
2674{
940b5ce0
DJ		 2675 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2676
2677 if (!SEG_NORMAL (now_seg))
2678 return;
2679
cd000bff
DJ		 2680 if (mapstate == state)
2681 /* The mapping symbol has already been emitted.
2682 There is nothing else to do. */
2683 return;
2684
4e9aaefb
SA		 2685 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2686 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
2687 {
2688 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
2689 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
2690
2691 if (add_symbol)
2692 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
2693 }
2694
cd000bff
DJ		 2695 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
2696 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205 2697}
4e9aaefb 2698#undef TRANSITION
c19d1205 2699#else
d3106081
NS		 2700#define mapping_state(x) ((void)0)
2701#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW		 2702#endif
2703
2704/* Find the real, Thumb encoded start of a Thumb function. */
2705
4343666d 2706#ifdef OBJ_COFF
c19d1205
ZW		 2707static symbolS *
2708find_real_start (symbolS * symbolP)
2709{
2710 char * real_start;
2711 const char * name = S_GET_NAME (symbolP);
2712 symbolS * new_target;
2713
2714 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2715#define STUB_NAME ".real_start_of"
2716
2717 if (name == NULL)
2718 abort ();
2719
37f6032b
ZW		 2720 /* The compiler may generate BL instructions to local labels because
2721 it needs to perform a branch to a far away location. These labels
2722 do not have a corresponding ".real_start_of" label. We check
2723 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2724 the ".real_start_of" convention for nonlocal branches. */
2725 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW		 2726 return symbolP;
2727
37f6032b 2728 real_start = ACONCAT ((STUB_NAME, name, NULL));
c19d1205
ZW		 2729 new_target = symbol_find (real_start);
2730
2731 if (new_target == NULL)
2732 {
bd3ba5d1 2733 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW		 2734 new_target = symbolP;
2735 }
2736
c19d1205
ZW		 2737 return new_target;
2738}
4343666d 2739#endif
c19d1205
ZW		 2740
2741static void
2742opcode_select (int width)
2743{
2744 switch (width)
2745 {
2746 case 16:
2747 if (! thumb_mode)
2748 {
e74cfd16 2749 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW		 2750 as_bad (_("selected processor does not support THUMB opcodes"));
2751
2752 thumb_mode = 1;
2753 /* No need to force the alignment, since we will have been
2754 coming from ARM mode, which is word-aligned. */
2755 record_alignment (now_seg, 1);
2756 }
c19d1205
ZW		 2757 break;
2758
2759 case 32:
2760 if (thumb_mode)
2761 {
e74cfd16 2762 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW		 2763 as_bad (_("selected processor does not support ARM opcodes"));
2764
2765 thumb_mode = 0;
2766
2767 if (!need_pass_2)
2768 frag_align (2, 0, 0);
2769
2770 record_alignment (now_seg, 1);
2771 }
c19d1205
ZW		 2772 break;
2773
2774 default:
2775 as_bad (_("invalid instruction size selected (%d)"), width);
2776 }
2777}
2778
2779static void
2780s_arm (int ignore ATTRIBUTE_UNUSED)
2781{
2782 opcode_select (32);
2783 demand_empty_rest_of_line ();
2784}
2785
2786static void
2787s_thumb (int ignore ATTRIBUTE_UNUSED)
2788{
2789 opcode_select (16);
2790 demand_empty_rest_of_line ();
2791}
2792
2793static void
2794s_code (int unused ATTRIBUTE_UNUSED)
2795{
2796 int temp;
2797
2798 temp = get_absolute_expression ();
2799 switch (temp)
2800 {
2801 case 16:
2802 case 32:
2803 opcode_select (temp);
2804 break;
2805
2806 default:
2807 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
2808 }
2809}
2810
2811static void
2812s_force_thumb (int ignore ATTRIBUTE_UNUSED)
2813{
2814 /* If we are not already in thumb mode go into it, EVEN if
2815 the target processor does not support thumb instructions.
2816 This is used by gcc/config/arm/lib1funcs.asm for example
2817 to compile interworking support functions even if the
2818 target processor should not support interworking. */
2819 if (! thumb_mode)
2820 {
2821 thumb_mode = 2;
2822 record_alignment (now_seg, 1);
2823 }
2824
2825 demand_empty_rest_of_line ();
2826}
2827
2828static void
2829s_thumb_func (int ignore ATTRIBUTE_UNUSED)
2830{
2831 s_thumb (0);
2832
2833 /* The following label is the name/address of the start of a Thumb function.
2834 We need to know this for the interworking support. */
2835 label_is_thumb_function_name = TRUE;
2836}
2837
2838/* Perform a .set directive, but also mark the alias as
2839 being a thumb function. */
2840
2841static void
2842s_thumb_set (int equiv)
2843{
2844 /* XXX the following is a duplicate of the code for s_set() in read.c
2845 We cannot just call that code as we need to get at the symbol that
2846 is created. */
2847 char * name;
2848 char delim;
2849 char * end_name;
2850 symbolS * symbolP;
2851
2852 /* Especial apologies for the random logic:
2853 This just grew, and could be parsed much more simply!
2854 Dean - in haste. */
2855 name = input_line_pointer;
2856 delim = get_symbol_end ();
2857 end_name = input_line_pointer;
2858 *end_name = delim;
2859
2860 if (*input_line_pointer != ',')
2861 {
2862 *end_name = 0;
2863 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC		 2864 *end_name = delim;
2865 ignore_rest_of_line ();
2866 return;
2867 }
2868
2869 input_line_pointer++;
2870 *end_name = 0;
2871
2872 if (name[0] == '.' && name[1] == '\0')
2873 {
2874 /* XXX - this should not happen to .thumb_set. */
2875 abort ();
2876 }
2877
2878 if ((symbolP = symbol_find (name)) == NULL
2879 && (symbolP = md_undefined_symbol (name)) == NULL)
2880 {
2881#ifndef NO_LISTING
2882 /* When doing symbol listings, play games with dummy fragments living
2883 outside the normal fragment chain to record the file and line info
c19d1205 2884 for this symbol. */
b99bd4ef
NC		 2885 if (listing & LISTING_SYMBOLS)
2886 {
2887 extern struct list_info_struct * listing_tail;
21d799b5 2888 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC		 2889
2890 memset (dummy_frag, 0, sizeof (fragS));
2891 dummy_frag->fr_type = rs_fill;
2892 dummy_frag->line = listing_tail;
2893 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
2894 dummy_frag->fr_symbol = symbolP;
2895 }
2896 else
2897#endif
2898 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
2899
2900#ifdef OBJ_COFF
2901 /* "set" symbols are local unless otherwise specified. */
2902 SF_SET_LOCAL (symbolP);
2903#endif /* OBJ_COFF */
2904 } /* Make a new symbol. */
2905
2906 symbol_table_insert (symbolP);
2907
2908 * end_name = delim;
2909
2910 if (equiv
2911 && S_IS_DEFINED (symbolP)
2912 && S_GET_SEGMENT (symbolP) != reg_section)
2913 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
2914
2915 pseudo_set (symbolP);
2916
2917 demand_empty_rest_of_line ();
2918
c19d1205 2919 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC		 2920
2921 THUMB_SET_FUNC (symbolP, 1);
2922 ARM_SET_THUMB (symbolP, 1);
2923#if defined OBJ_ELF || defined OBJ_COFF
2924 ARM_SET_INTERWORK (symbolP, support_interwork);
2925#endif
2926}
2927
c19d1205 2928/* Directives: Mode selection. */
b99bd4ef 2929
c19d1205
ZW		 2930/* .syntax [unified|divided] - choose the new unified syntax
2931 (same for Arm and Thumb encoding, modulo slight differences in what
2932 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 2933static void
c19d1205 2934s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2935{
c19d1205
ZW		 2936 char *name, delim;
2937
2938 name = input_line_pointer;
2939 delim = get_symbol_end ();
2940
2941 if (!strcasecmp (name, "unified"))
2942 unified_syntax = TRUE;
2943 else if (!strcasecmp (name, "divided"))
2944 unified_syntax = FALSE;
2945 else
2946 {
2947 as_bad (_("unrecognized syntax mode \"%s\""), name);
2948 return;
2949 }
2950 *input_line_pointer = delim;
b99bd4ef
NC		 2951 demand_empty_rest_of_line ();
2952}
2953
c19d1205
ZW		 2954/* Directives: sectioning and alignment. */
2955
2956/* Same as s_align_ptwo but align 0 => align 2. */
2957
b99bd4ef 2958static void
c19d1205 2959s_align (int unused ATTRIBUTE_UNUSED)
b99bd4ef 2960{
a737bd4d 2961 int temp;
dce323d1 2962 bfd_boolean fill_p;
c19d1205
ZW		 2963 long temp_fill;
2964 long max_alignment = 15;
b99bd4ef
NC		 2965
2966 temp = get_absolute_expression ();
c19d1205
ZW		 2967 if (temp > max_alignment)
2968 as_bad (_("alignment too large: %d assumed"), temp = max_alignment);
2969 else if (temp < 0)
b99bd4ef 2970 {
c19d1205
ZW		 2971 as_bad (_("alignment negative. 0 assumed."));
2972 temp = 0;
2973 }
b99bd4ef 2974
c19d1205
ZW		 2975 if (*input_line_pointer == ',')
2976 {
2977 input_line_pointer++;
2978 temp_fill = get_absolute_expression ();
dce323d1 2979 fill_p = TRUE;
b99bd4ef 2980 }
c19d1205 2981 else
dce323d1
PB		 2982 {
2983 fill_p = FALSE;
2984 temp_fill = 0;
2985 }
b99bd4ef 2986
c19d1205
ZW		 2987 if (!temp)
2988 temp = 2;
b99bd4ef 2989
c19d1205
ZW		 2990 /* Only make a frag if we HAVE to. */
2991 if (temp && !need_pass_2)
dce323d1
PB		 2992 {
2993 if (!fill_p && subseg_text_p (now_seg))
2994 frag_align_code (temp, 0);
2995 else
2996 frag_align (temp, (int) temp_fill, 0);
2997 }
c19d1205
ZW		 2998 demand_empty_rest_of_line ();
2999
3000 record_alignment (now_seg, temp);
b99bd4ef
NC		 3001}
3002
c19d1205
ZW		 3003static void
3004s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 3005{
c19d1205
ZW		 3006 /* We don't support putting frags in the BSS segment, we fake it by
3007 marking in_bss, then looking at s_skip for clues. */
3008 subseg_set (bss_section, 0);
3009 demand_empty_rest_of_line ();
cd000bff
DJ		 3010
3011#ifdef md_elf_section_change_hook
3012 md_elf_section_change_hook ();
3013#endif
c19d1205 3014}
b99bd4ef 3015
c19d1205
ZW		 3016static void
3017s_even (int ignore ATTRIBUTE_UNUSED)
3018{
3019 /* Never make frag if expect extra pass. */
3020 if (!need_pass_2)
3021 frag_align (1, 0, 0);
b99bd4ef 3022
c19d1205 3023 record_alignment (now_seg, 1);
b99bd4ef 3024
c19d1205 3025 demand_empty_rest_of_line ();
b99bd4ef
NC		 3026}
3027
2e6976a8
DG		 3028/* Directives: CodeComposer Studio. */
3029
3030/* .ref (for CodeComposer Studio syntax only). */
3031static void
3032s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3033{
3034 if (codecomposer_syntax)
3035 ignore_rest_of_line ();
3036 else
3037 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3038}
3039
3040/* If name is not NULL, then it is used for marking the beginning of a
3041 function, wherease if it is NULL then it means the function end. */
3042static void
3043asmfunc_debug (const char * name)
3044{
3045 static const char * last_name = NULL;
3046
3047 if (name != NULL)
3048 {
3049 gas_assert (last_name == NULL);
3050 last_name = name;
3051
3052 if (debug_type == DEBUG_STABS)
3053 stabs_generate_asm_func (name, name);
3054 }
3055 else
3056 {
3057 gas_assert (last_name != NULL);
3058
3059 if (debug_type == DEBUG_STABS)
3060 stabs_generate_asm_endfunc (last_name, last_name);
3061
3062 last_name = NULL;
3063 }
3064}
3065
3066static void
3067s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3068{
3069 if (codecomposer_syntax)
3070 {
3071 switch (asmfunc_state)
3072 {
3073 case OUTSIDE_ASMFUNC:
3074 asmfunc_state = WAITING_ASMFUNC_NAME;
3075 break;
3076
3077 case WAITING_ASMFUNC_NAME:
3078 as_bad (_(".asmfunc repeated."));
3079 break;
3080
3081 case WAITING_ENDASMFUNC:
3082 as_bad (_(".asmfunc without function."));
3083 break;
3084 }
3085 demand_empty_rest_of_line ();
3086 }
3087 else
3088 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3089}
3090
3091static void
3092s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3093{
3094 if (codecomposer_syntax)
3095 {
3096 switch (asmfunc_state)
3097 {
3098 case OUTSIDE_ASMFUNC:
3099 as_bad (_(".endasmfunc without a .asmfunc."));
3100 break;
3101
3102 case WAITING_ASMFUNC_NAME:
3103 as_bad (_(".endasmfunc without function."));
3104 break;
3105
3106 case WAITING_ENDASMFUNC:
3107 asmfunc_state = OUTSIDE_ASMFUNC;
3108 asmfunc_debug (NULL);
3109 break;
3110 }
3111 demand_empty_rest_of_line ();
3112 }
3113 else
3114 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3115}
3116
3117static void
3118s_ccs_def (int name)
3119{
3120 if (codecomposer_syntax)
3121 s_globl (name);
3122 else
3123 as_bad (_(".def pseudo-op only available with -mccs flag."));
3124}
3125
c19d1205 3126/* Directives: Literal pools. */
a737bd4d 3127
c19d1205
ZW		 3128static literal_pool *
3129find_literal_pool (void)
a737bd4d 3130{
c19d1205 3131 literal_pool * pool;
a737bd4d 3132
c19d1205 3133 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3134 {
c19d1205
ZW		 3135 if (pool->section == now_seg
3136 && pool->sub_section == now_subseg)
3137 break;
a737bd4d
NC		 3138 }
3139
c19d1205 3140 return pool;
a737bd4d
NC		 3141}
3142
c19d1205
ZW		 3143static literal_pool *
3144find_or_make_literal_pool (void)
a737bd4d 3145{
c19d1205
ZW		 3146 /* Next literal pool ID number. */
3147 static unsigned int latest_pool_num = 1;
3148 literal_pool * pool;
a737bd4d 3149
c19d1205 3150 pool = find_literal_pool ();
a737bd4d 3151
c19d1205 3152 if (pool == NULL)
a737bd4d 3153 {
c19d1205 3154 /* Create a new pool. */
21d799b5 3155 pool = (literal_pool *) xmalloc (sizeof (* pool));
c19d1205
ZW		 3156 if (! pool)
3157 return NULL;
a737bd4d 3158
c19d1205
ZW		 3159 pool->next_free_entry = 0;
3160 pool->section = now_seg;
3161 pool->sub_section = now_subseg;
3162 pool->next = list_of_pools;
3163 pool->symbol = NULL;
8335d6aa 3164 pool->alignment = 2;
c19d1205
ZW		 3165
3166 /* Add it to the list. */
3167 list_of_pools = pool;
a737bd4d 3168 }
a737bd4d 3169
c19d1205
ZW		 3170 /* New pools, and emptied pools, will have a NULL symbol. */
3171 if (pool->symbol == NULL)
a737bd4d 3172 {
c19d1205
ZW		 3173 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3174 (valueT) 0, &zero_address_frag);
3175 pool->id = latest_pool_num ++;
a737bd4d
NC		 3176 }
3177
c19d1205
ZW		 3178 /* Done. */
3179 return pool;
a737bd4d
NC		 3180}
3181
c19d1205 3182/* Add the literal in the global 'inst'
5f4273c7 3183 structure to the relevant literal pool. */
b99bd4ef
NC		 3184
3185static int
8335d6aa 3186add_to_lit_pool (unsigned int nbytes)
b99bd4ef 3187{
8335d6aa
JW		 3188#define PADDING_SLOT 0x1
3189#define LIT_ENTRY_SIZE_MASK 0xFF
c19d1205 3190 literal_pool * pool;
8335d6aa
JW		 3191 unsigned int entry, pool_size = 0;
3192 bfd_boolean padding_slot_p = FALSE;
e56c722b 3193 unsigned imm1 = 0;
8335d6aa
JW		 3194 unsigned imm2 = 0;
3195
3196 if (nbytes == 8)
3197 {
3198 imm1 = inst.operands[1].imm;
3199 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
3200 : inst.reloc.exp.X_unsigned ? 0
2569ceb0 3201 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
8335d6aa
JW		 3202 if (target_big_endian)
3203 {
3204 imm1 = imm2;
3205 imm2 = inst.operands[1].imm;
3206 }
3207 }
b99bd4ef 3208
c19d1205
ZW		 3209 pool = find_or_make_literal_pool ();
3210
3211 /* Check if this literal value is already in the pool. */
3212 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3213 {
8335d6aa
JW		 3214 if (nbytes == 4)
3215 {
3216 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3217 && (inst.reloc.exp.X_op == O_constant)
3218 && (pool->literals[entry].X_add_number
3219 == inst.reloc.exp.X_add_number)
3220 && (pool->literals[entry].X_md == nbytes)
3221 && (pool->literals[entry].X_unsigned
3222 == inst.reloc.exp.X_unsigned))
3223 break;
3224
3225 if ((pool->literals[entry].X_op == inst.reloc.exp.X_op)
3226 && (inst.reloc.exp.X_op == O_symbol)
3227 && (pool->literals[entry].X_add_number
3228 == inst.reloc.exp.X_add_number)
3229 && (pool->literals[entry].X_add_symbol
3230 == inst.reloc.exp.X_add_symbol)
3231 && (pool->literals[entry].X_op_symbol
3232 == inst.reloc.exp.X_op_symbol)
3233 && (pool->literals[entry].X_md == nbytes))
3234 break;
3235 }
3236 else if ((nbytes == 8)
3237 && !(pool_size & 0x7)
3238 && ((entry + 1) != pool->next_free_entry)
3239 && (pool->literals[entry].X_op == O_constant)
19f2f6a9 3240 && (pool->literals[entry].X_add_number == (offsetT) imm1)
8335d6aa
JW		 3241 && (pool->literals[entry].X_unsigned
3242 == inst.reloc.exp.X_unsigned)
3243 && (pool->literals[entry + 1].X_op == O_constant)
19f2f6a9 3244 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
8335d6aa
JW		 3245 && (pool->literals[entry + 1].X_unsigned
3246 == inst.reloc.exp.X_unsigned))
c19d1205
ZW		 3247 break;
3248
8335d6aa
JW		 3249 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3250 if (padding_slot_p && (nbytes == 4))
c19d1205 3251 break;
8335d6aa
JW		 3252
3253 pool_size += 4;
b99bd4ef
NC		 3254 }
3255
c19d1205
ZW		 3256 /* Do we need to create a new entry? */
3257 if (entry == pool->next_free_entry)
3258 {
3259 if (entry >= MAX_LITERAL_POOL_SIZE)
3260 {
3261 inst.error = _("literal pool overflow");
3262 return FAIL;
3263 }
3264
8335d6aa
JW		 3265 if (nbytes == 8)
3266 {
3267 /* For 8-byte entries, we align to an 8-byte boundary,
3268 and split it into two 4-byte entries, because on 32-bit
3269 host, 8-byte constants are treated as big num, thus
3270 saved in "generic_bignum" which will be overwritten
3271 by later assignments.
3272
3273 We also need to make sure there is enough space for
3274 the split.
3275
3276 We also check to make sure the literal operand is a
3277 constant number. */
19f2f6a9
JW		 3278 if (!(inst.reloc.exp.X_op == O_constant
3279 || inst.reloc.exp.X_op == O_big))
8335d6aa
JW		 3280 {
3281 inst.error = _("invalid type for literal pool");
3282 return FAIL;
3283 }
3284 else if (pool_size & 0x7)
3285 {
3286 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3287 {
3288 inst.error = _("literal pool overflow");
3289 return FAIL;
3290 }
3291
3292 pool->literals[entry] = inst.reloc.exp;
3293 pool->literals[entry].X_add_number = 0;
3294 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3295 pool->next_free_entry += 1;
3296 pool_size += 4;
3297 }
3298 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3299 {
3300 inst.error = _("literal pool overflow");
3301 return FAIL;
3302 }
3303
3304 pool->literals[entry] = inst.reloc.exp;
3305 pool->literals[entry].X_op = O_constant;
3306 pool->literals[entry].X_add_number = imm1;
3307 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3308 pool->literals[entry++].X_md = 4;
3309 pool->literals[entry] = inst.reloc.exp;
3310 pool->literals[entry].X_op = O_constant;
3311 pool->literals[entry].X_add_number = imm2;
3312 pool->literals[entry].X_unsigned = inst.reloc.exp.X_unsigned;
3313 pool->literals[entry].X_md = 4;
3314 pool->alignment = 3;
3315 pool->next_free_entry += 1;
3316 }
3317 else
3318 {
3319 pool->literals[entry] = inst.reloc.exp;
3320 pool->literals[entry].X_md = 4;
3321 }
3322
a8040cf2
NC		 3323#ifdef OBJ_ELF
3324 /* PR ld/12974: Record the location of the first source line to reference
3325 this entry in the literal pool. If it turns out during linking that the
3326 symbol does not exist we will be able to give an accurate line number for
3327 the (first use of the) missing reference. */
3328 if (debug_type == DEBUG_DWARF2)
3329 dwarf2_where (pool->locs + entry);
3330#endif
c19d1205
ZW		 3331 pool->next_free_entry += 1;
3332 }
8335d6aa
JW		 3333 else if (padding_slot_p)
3334 {
3335 pool->literals[entry] = inst.reloc.exp;
3336 pool->literals[entry].X_md = nbytes;
3337 }
b99bd4ef 3338
c19d1205 3339 inst.reloc.exp.X_op = O_symbol;
8335d6aa 3340 inst.reloc.exp.X_add_number = pool_size;
c19d1205 3341 inst.reloc.exp.X_add_symbol = pool->symbol;
b99bd4ef 3342
c19d1205 3343 return SUCCESS;
b99bd4ef
NC		 3344}
3345
2e6976a8
DG		 3346bfd_boolean
3347tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest)
3348{
3349 bfd_boolean ret = TRUE;
3350
3351 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3352 {
3353 const char *label = rest;
3354
3355 while (!is_end_of_line[(int) label[-1]])
3356 --label;
3357
3358 if (*label == '.')
3359 {
3360 as_bad (_("Invalid label '%s'"), label);
3361 ret = FALSE;
3362 }
3363
3364 asmfunc_debug (label);
3365
3366 asmfunc_state = WAITING_ENDASMFUNC;
3367 }
3368
3369 return ret;
3370}
3371
c19d1205
ZW		 3372/* Can't use symbol_new here, so have to create a symbol and then at
3373 a later date assign it a value. Thats what these functions do. */
e16bb312 3374
c19d1205
ZW		 3375static void
3376symbol_locate (symbolS * symbolP,
3377 const char * name, /* It is copied, the caller can modify. */
3378 segT segment, /* Segment identifier (SEG_<something>). */
3379 valueT valu, /* Symbol value. */
3380 fragS * frag) /* Associated fragment. */
3381{
e57e6ddc 3382 size_t name_length;
c19d1205 3383 char * preserved_copy_of_name;
e16bb312 3384
c19d1205
ZW		 3385 name_length = strlen (name) + 1; /* +1 for \0. */
3386 obstack_grow (&notes, name, name_length);
21d799b5 3387 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3388
c19d1205
ZW		 3389#ifdef tc_canonicalize_symbol_name
3390 preserved_copy_of_name =
3391 tc_canonicalize_symbol_name (preserved_copy_of_name);
3392#endif
b99bd4ef 3393
c19d1205 3394 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3395
c19d1205
ZW		 3396 S_SET_SEGMENT (symbolP, segment);
3397 S_SET_VALUE (symbolP, valu);
3398 symbol_clear_list_pointers (symbolP);
b99bd4ef 3399
c19d1205 3400 symbol_set_frag (symbolP, frag);
b99bd4ef 3401
c19d1205
ZW		 3402 /* Link to end of symbol chain. */
3403 {
3404 extern int symbol_table_frozen;
b99bd4ef 3405
c19d1205
ZW		 3406 if (symbol_table_frozen)
3407 abort ();
3408 }
b99bd4ef 3409
c19d1205 3410 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3411
c19d1205 3412 obj_symbol_new_hook (symbolP);
b99bd4ef 3413
c19d1205
ZW		 3414#ifdef tc_symbol_new_hook
3415 tc_symbol_new_hook (symbolP);
3416#endif
3417
3418#ifdef DEBUG_SYMS
3419 verify_symbol_chain (symbol_rootP, symbol_lastP);
3420#endif /* DEBUG_SYMS */
b99bd4ef
NC		 3421}
3422
c19d1205
ZW		 3423static void
3424s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3425{
c19d1205
ZW		 3426 unsigned int entry;
3427 literal_pool * pool;
3428 char sym_name[20];
b99bd4ef 3429
c19d1205
ZW		 3430 pool = find_literal_pool ();
3431 if (pool == NULL
3432 || pool->symbol == NULL
3433 || pool->next_free_entry == 0)
3434 return;
b99bd4ef 3435
c19d1205
ZW		 3436 /* Align pool as you have word accesses.
3437 Only make a frag if we have to. */
3438 if (!need_pass_2)
8335d6aa 3439 frag_align (pool->alignment, 0, 0);
b99bd4ef 3440
c19d1205 3441 record_alignment (now_seg, 2);
b99bd4ef 3442
aaca88ef 3443#ifdef OBJ_ELF
47fc6e36
WN		 3444 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3445 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
aaca88ef 3446#endif
c19d1205 3447 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3448
c19d1205
ZW		 3449 symbol_locate (pool->symbol, sym_name, now_seg,
3450 (valueT) frag_now_fix (), frag_now);
3451 symbol_table_insert (pool->symbol);
b99bd4ef 3452
c19d1205 3453 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3454
c19d1205
ZW		 3455#if defined OBJ_COFF || defined OBJ_ELF
3456 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3457#endif
6c43fab6 3458
c19d1205 3459 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC		 3460 {
3461#ifdef OBJ_ELF
3462 if (debug_type == DEBUG_DWARF2)
3463 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3464#endif
3465 /* First output the expression in the instruction to the pool. */
8335d6aa
JW		 3466 emit_expr (&(pool->literals[entry]),
3467 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
a8040cf2 3468 }
b99bd4ef 3469
c19d1205
ZW		 3470 /* Mark the pool as empty. */
3471 pool->next_free_entry = 0;
3472 pool->symbol = NULL;
b99bd4ef
NC		 3473}
3474
c19d1205
ZW		 3475#ifdef OBJ_ELF
3476/* Forward declarations for functions below, in the MD interface
3477 section. */
3478static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3479static valueT create_unwind_entry (int);
3480static void start_unwind_section (const segT, int);
3481static void add_unwind_opcode (valueT, int);
3482static void flush_pending_unwind (void);
b99bd4ef 3483
c19d1205 3484/* Directives: Data. */
b99bd4ef 3485
c19d1205
ZW		 3486static void
3487s_arm_elf_cons (int nbytes)
3488{
3489 expressionS exp;
b99bd4ef 3490
c19d1205
ZW		 3491#ifdef md_flush_pending_output
3492 md_flush_pending_output ();
3493#endif
b99bd4ef 3494
c19d1205 3495 if (is_it_end_of_statement ())
b99bd4ef 3496 {
c19d1205
ZW		 3497 demand_empty_rest_of_line ();
3498 return;
b99bd4ef
NC		 3499 }
3500
c19d1205
ZW		 3501#ifdef md_cons_align
3502 md_cons_align (nbytes);
3503#endif
b99bd4ef 3504
c19d1205
ZW		 3505 mapping_state (MAP_DATA);
3506 do
b99bd4ef 3507 {
c19d1205
ZW		 3508 int reloc;
3509 char *base = input_line_pointer;
b99bd4ef 3510
c19d1205 3511 expression (& exp);
b99bd4ef 3512
c19d1205
ZW		 3513 if (exp.X_op != O_symbol)
3514 emit_expr (&exp, (unsigned int) nbytes);
3515 else
3516 {
3517 char *before_reloc = input_line_pointer;
3518 reloc = parse_reloc (&input_line_pointer);
3519 if (reloc == -1)
3520 {
3521 as_bad (_("unrecognized relocation suffix"));
3522 ignore_rest_of_line ();
3523 return;
3524 }
3525 else if (reloc == BFD_RELOC_UNUSED)
3526 emit_expr (&exp, (unsigned int) nbytes);
3527 else
3528 {
21d799b5 3529 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM		 3530 bfd_reloc_type_lookup (stdoutput,
3531 (bfd_reloc_code_real_type) reloc);
c19d1205 3532 int size = bfd_get_reloc_size (howto);
b99bd4ef 3533
2fc8bdac
ZW		 3534 if (reloc == BFD_RELOC_ARM_PLT32)
3535 {
3536 as_bad (_("(plt) is only valid on branch targets"));
3537 reloc = BFD_RELOC_UNUSED;
3538 size = 0;
3539 }
3540
c19d1205 3541 if (size > nbytes)
2fc8bdac 3542 as_bad (_("%s relocations do not fit in %d bytes"),
c19d1205
ZW		 3543 howto->name, nbytes);
3544 else
3545 {
3546 /* We've parsed an expression stopping at O_symbol.
3547 But there may be more expression left now that we
3548 have parsed the relocation marker. Parse it again.
3549 XXX Surely there is a cleaner way to do this. */
3550 char *p = input_line_pointer;
3551 int offset;
21d799b5 3552 char *save_buf = (char *) alloca (input_line_pointer - base);
c19d1205
ZW		 3553 memcpy (save_buf, base, input_line_pointer - base);
3554 memmove (base + (input_line_pointer - before_reloc),
3555 base, before_reloc - base);
3556
3557 input_line_pointer = base + (input_line_pointer-before_reloc);
3558 expression (&exp);
3559 memcpy (base, save_buf, p - base);
3560
3561 offset = nbytes - size;
4b1a927e
AM		 3562 p = frag_more (nbytes);
3563 memset (p, 0, nbytes);
c19d1205 3564 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3565 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
c19d1205
ZW		 3566 }
3567 }
3568 }
b99bd4ef 3569 }
c19d1205 3570 while (*input_line_pointer++ == ',');
b99bd4ef 3571
c19d1205
ZW		 3572 /* Put terminator back into stream. */
3573 input_line_pointer --;
3574 demand_empty_rest_of_line ();
b99bd4ef
NC		 3575}
3576
c921be7d
NC		 3577/* Emit an expression containing a 32-bit thumb instruction.
3578 Implementation based on put_thumb32_insn. */
3579
3580static void
3581emit_thumb32_expr (expressionS * exp)
3582{
3583 expressionS exp_high = *exp;
3584
3585 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3586 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3587 exp->X_add_number &= 0xffff;
3588 emit_expr (exp, (unsigned int) THUMB_SIZE);
3589}
3590
3591/* Guess the instruction size based on the opcode. */
3592
3593static int
3594thumb_insn_size (int opcode)
3595{
3596 if ((unsigned int) opcode < 0xe800u)
3597 return 2;
3598 else if ((unsigned int) opcode >= 0xe8000000u)
3599 return 4;
3600 else
3601 return 0;
3602}
3603
3604static bfd_boolean
3605emit_insn (expressionS *exp, int nbytes)
3606{
3607 int size = 0;
3608
3609 if (exp->X_op == O_constant)
3610 {
3611 size = nbytes;
3612
3613 if (size == 0)
3614 size = thumb_insn_size (exp->X_add_number);
3615
3616 if (size != 0)
3617 {
3618 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3619 {
3620 as_bad (_(".inst.n operand too big. "\
3621 "Use .inst.w instead"));
3622 size = 0;
3623 }
3624 else
3625 {
3626 if (now_it.state == AUTOMATIC_IT_BLOCK)
3627 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN, 0);
3628 else
3629 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
3630
3631 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3632 emit_thumb32_expr (exp);
3633 else
3634 emit_expr (exp, (unsigned int) size);
3635
3636 it_fsm_post_encode ();
3637 }
3638 }
3639 else
3640 as_bad (_("cannot determine Thumb instruction size. " \
3641 "Use .inst.n/.inst.w instead"));
3642 }
3643 else
3644 as_bad (_("constant expression required"));
3645
3646 return (size != 0);
3647}
3648
3649/* Like s_arm_elf_cons but do not use md_cons_align and
3650 set the mapping state to MAP_ARM/MAP_THUMB. */
3651
3652static void
3653s_arm_elf_inst (int nbytes)
3654{
3655 if (is_it_end_of_statement ())
3656 {
3657 demand_empty_rest_of_line ();
3658 return;
3659 }
3660
3661 /* Calling mapping_state () here will not change ARM/THUMB,
3662 but will ensure not to be in DATA state. */
3663
3664 if (thumb_mode)
3665 mapping_state (MAP_THUMB);
3666 else
3667 {
3668 if (nbytes != 0)
3669 {
3670 as_bad (_("width suffixes are invalid in ARM mode"));
3671 ignore_rest_of_line ();
3672 return;
3673 }
3674
3675 nbytes = 4;
3676
3677 mapping_state (MAP_ARM);
3678 }
3679
3680 do
3681 {
3682 expressionS exp;
3683
3684 expression (& exp);
3685
3686 if (! emit_insn (& exp, nbytes))
3687 {
3688 ignore_rest_of_line ();
3689 return;
3690 }
3691 }
3692 while (*input_line_pointer++ == ',');
3693
3694 /* Put terminator back into stream. */
3695 input_line_pointer --;
3696 demand_empty_rest_of_line ();
3697}
b99bd4ef 3698
c19d1205 3699/* Parse a .rel31 directive. */
b99bd4ef 3700
c19d1205
ZW		 3701static void
3702s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3703{
3704 expressionS exp;
3705 char *p;
3706 valueT highbit;
b99bd4ef 3707
c19d1205
ZW		 3708 highbit = 0;
3709 if (*input_line_pointer == '1')
3710 highbit = 0x80000000;
3711 else if (*input_line_pointer != '0')
3712 as_bad (_("expected 0 or 1"));
b99bd4ef 3713
c19d1205
ZW		 3714 input_line_pointer++;
3715 if (*input_line_pointer != ',')
3716 as_bad (_("missing comma"));
3717 input_line_pointer++;
b99bd4ef 3718
c19d1205
ZW		 3719#ifdef md_flush_pending_output
3720 md_flush_pending_output ();
3721#endif
b99bd4ef 3722
c19d1205
ZW		 3723#ifdef md_cons_align
3724 md_cons_align (4);
3725#endif
b99bd4ef 3726
c19d1205 3727 mapping_state (MAP_DATA);
b99bd4ef 3728
c19d1205 3729 expression (&exp);
b99bd4ef 3730
c19d1205
ZW		 3731 p = frag_more (4);
3732 md_number_to_chars (p, highbit, 4);
3733 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
3734 BFD_RELOC_ARM_PREL31);
b99bd4ef 3735
c19d1205 3736 demand_empty_rest_of_line ();
b99bd4ef
NC		 3737}
3738
c19d1205 3739/* Directives: AEABI stack-unwind tables. */
b99bd4ef 3740
c19d1205 3741/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 3742
c19d1205
ZW		 3743static void
3744s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
3745{
3746 demand_empty_rest_of_line ();
921e5f0a
PB		 3747 if (unwind.proc_start)
3748 {
c921be7d 3749 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB		 3750 return;
3751 }
3752
c19d1205
ZW		 3753 /* Mark the start of the function. */
3754 unwind.proc_start = expr_build_dot ();
b99bd4ef 3755
c19d1205
ZW		 3756 /* Reset the rest of the unwind info. */
3757 unwind.opcode_count = 0;
3758 unwind.table_entry = NULL;
3759 unwind.personality_routine = NULL;
3760 unwind.personality_index = -1;
3761 unwind.frame_size = 0;
3762 unwind.fp_offset = 0;
fdfde340 3763 unwind.fp_reg = REG_SP;
c19d1205
ZW		 3764 unwind.fp_used = 0;
3765 unwind.sp_restored = 0;
3766}
b99bd4ef 3767
b99bd4ef 3768
c19d1205
ZW		 3769/* Parse a handlerdata directive. Creates the exception handling table entry
3770 for the function. */
b99bd4ef 3771
c19d1205
ZW		 3772static void
3773s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
3774{
3775 demand_empty_rest_of_line ();
921e5f0a 3776 if (!unwind.proc_start)
c921be7d 3777 as_bad (MISSING_FNSTART);
921e5f0a 3778
c19d1205 3779 if (unwind.table_entry)
6decc662 3780 as_bad (_("duplicate .handlerdata directive"));
f02232aa 3781
c19d1205
ZW		 3782 create_unwind_entry (1);
3783}
a737bd4d 3784
c19d1205 3785/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 3786
c19d1205
ZW		 3787static void
3788s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
3789{
3790 long where;
3791 char *ptr;
3792 valueT val;
940b5ce0 3793 unsigned int marked_pr_dependency;
f02232aa 3794
c19d1205 3795 demand_empty_rest_of_line ();
f02232aa 3796
921e5f0a
PB		 3797 if (!unwind.proc_start)
3798 {
c921be7d 3799 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB		 3800 return;
3801 }
3802
c19d1205
ZW		 3803 /* Add eh table entry. */
3804 if (unwind.table_entry == NULL)
3805 val = create_unwind_entry (0);
3806 else
3807 val = 0;
f02232aa 3808
c19d1205
ZW		 3809 /* Add index table entry. This is two words. */
3810 start_unwind_section (unwind.saved_seg, 1);
3811 frag_align (2, 0, 0);
3812 record_alignment (now_seg, 2);
b99bd4ef 3813
c19d1205 3814 ptr = frag_more (8);
5011093d 3815 memset (ptr, 0, 8);
c19d1205 3816 where = frag_now_fix () - 8;
f02232aa 3817
c19d1205
ZW		 3818 /* Self relative offset of the function start. */
3819 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
3820 BFD_RELOC_ARM_PREL31);
f02232aa 3821
c19d1205
ZW		 3822 /* Indicate dependency on EHABI-defined personality routines to the
3823 linker, if it hasn't been done already. */
940b5ce0
DJ		 3824 marked_pr_dependency
3825 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW		 3826 if (unwind.personality_index >= 0 && unwind.personality_index < 3
3827 && !(marked_pr_dependency & (1 << unwind.personality_index)))
3828 {
5f4273c7
NC		 3829 static const char *const name[] =
3830 {
3831 "__aeabi_unwind_cpp_pr0",
3832 "__aeabi_unwind_cpp_pr1",
3833 "__aeabi_unwind_cpp_pr2"
3834 };
c19d1205
ZW		 3835 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
3836 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 3837 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 3838 |= 1 << unwind.personality_index;
c19d1205 3839 }
f02232aa 3840
c19d1205
ZW		 3841 if (val)
3842 /* Inline exception table entry. */
3843 md_number_to_chars (ptr + 4, val, 4);
3844 else
3845 /* Self relative offset of the table entry. */
3846 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
3847 BFD_RELOC_ARM_PREL31);
f02232aa 3848
c19d1205
ZW		 3849 /* Restore the original section. */
3850 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB		 3851
3852 unwind.proc_start = NULL;
c19d1205 3853}
f02232aa 3854
f02232aa 3855
c19d1205 3856/* Parse an unwind_cantunwind directive. */
b99bd4ef 3857
c19d1205
ZW		 3858static void
3859s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
3860{
3861 demand_empty_rest_of_line ();
921e5f0a 3862 if (!unwind.proc_start)
c921be7d 3863 as_bad (MISSING_FNSTART);
921e5f0a 3864
c19d1205
ZW		 3865 if (unwind.personality_routine || unwind.personality_index != -1)
3866 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 3867
c19d1205
ZW		 3868 unwind.personality_index = -2;
3869}
b99bd4ef 3870
b99bd4ef 3871
c19d1205 3872/* Parse a personalityindex directive. */
b99bd4ef 3873
c19d1205
ZW		 3874static void
3875s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
3876{
3877 expressionS exp;
b99bd4ef 3878
921e5f0a 3879 if (!unwind.proc_start)
c921be7d 3880 as_bad (MISSING_FNSTART);
921e5f0a 3881
c19d1205
ZW		 3882 if (unwind.personality_routine || unwind.personality_index != -1)
3883 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 3884
c19d1205 3885 expression (&exp);
b99bd4ef 3886
c19d1205
ZW		 3887 if (exp.X_op != O_constant
3888 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 3889 {
c19d1205
ZW		 3890 as_bad (_("bad personality routine number"));
3891 ignore_rest_of_line ();
3892 return;
b99bd4ef
NC		 3893 }
3894
c19d1205 3895 unwind.personality_index = exp.X_add_number;
b99bd4ef 3896
c19d1205
ZW		 3897 demand_empty_rest_of_line ();
3898}
e16bb312 3899
e16bb312 3900
c19d1205 3901/* Parse a personality directive. */
e16bb312 3902
c19d1205
ZW		 3903static void
3904s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
3905{
3906 char *name, *p, c;
a737bd4d 3907
921e5f0a 3908 if (!unwind.proc_start)
c921be7d 3909 as_bad (MISSING_FNSTART);
921e5f0a 3910
c19d1205
ZW		 3911 if (unwind.personality_routine || unwind.personality_index != -1)
3912 as_bad (_("duplicate .personality directive"));
a737bd4d 3913
c19d1205
ZW		 3914 name = input_line_pointer;
3915 c = get_symbol_end ();
3916 p = input_line_pointer;
3917 unwind.personality_routine = symbol_find_or_make (name);
3918 *p = c;
3919 demand_empty_rest_of_line ();
3920}
e16bb312 3921
e16bb312 3922
c19d1205 3923/* Parse a directive saving core registers. */
e16bb312 3924
c19d1205
ZW		 3925static void
3926s_arm_unwind_save_core (void)
e16bb312 3927{
c19d1205
ZW		 3928 valueT op;
3929 long range;
3930 int n;
e16bb312 3931
c19d1205
ZW		 3932 range = parse_reg_list (&input_line_pointer);
3933 if (range == FAIL)
e16bb312 3934 {
c19d1205
ZW		 3935 as_bad (_("expected register list"));
3936 ignore_rest_of_line ();
3937 return;
3938 }
e16bb312 3939
c19d1205 3940 demand_empty_rest_of_line ();
e16bb312 3941
c19d1205
ZW		 3942 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3943 into .unwind_save {..., sp...}. We aren't bothered about the value of
3944 ip because it is clobbered by calls. */
3945 if (unwind.sp_restored && unwind.fp_reg == 12
3946 && (range & 0x3000) == 0x1000)
3947 {
3948 unwind.opcode_count--;
3949 unwind.sp_restored = 0;
3950 range = (range | 0x2000) & ~0x1000;
3951 unwind.pending_offset = 0;
3952 }
e16bb312 3953
01ae4198
DJ		 3954 /* Pop r4-r15. */
3955 if (range & 0xfff0)
c19d1205 3956 {
01ae4198
DJ		 3957 /* See if we can use the short opcodes. These pop a block of up to 8
3958 registers starting with r4, plus maybe r14. */
3959 for (n = 0; n < 8; n++)
3960 {
3961 /* Break at the first non-saved register. */
3962 if ((range & (1 << (n + 4))) == 0)
3963 break;
3964 }
3965 /* See if there are any other bits set. */
3966 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
3967 {
3968 /* Use the long form. */
3969 op = 0x8000 | ((range >> 4) & 0xfff);
3970 add_unwind_opcode (op, 2);
3971 }
0dd132b6 3972 else
01ae4198
DJ		 3973 {
3974 /* Use the short form. */
3975 if (range & 0x4000)
3976 op = 0xa8; /* Pop r14. */
3977 else
3978 op = 0xa0; /* Do not pop r14. */
3979 op |= (n - 1);
3980 add_unwind_opcode (op, 1);
3981 }
c19d1205 3982 }
0dd132b6 3983
c19d1205
ZW		 3984 /* Pop r0-r3. */
3985 if (range & 0xf)
3986 {
3987 op = 0xb100 | (range & 0xf);
3988 add_unwind_opcode (op, 2);
0dd132b6
NC		 3989 }
3990
c19d1205
ZW		 3991 /* Record the number of bytes pushed. */
3992 for (n = 0; n < 16; n++)
3993 {
3994 if (range & (1 << n))
3995 unwind.frame_size += 4;
3996 }
0dd132b6
NC		 3997}
3998
c19d1205
ZW		 3999
4000/* Parse a directive saving FPA registers. */
b99bd4ef
NC		 4001
4002static void
c19d1205 4003s_arm_unwind_save_fpa (int reg)
b99bd4ef 4004{
c19d1205
ZW		 4005 expressionS exp;
4006 int num_regs;
4007 valueT op;
b99bd4ef 4008
c19d1205
ZW		 4009 /* Get Number of registers to transfer. */
4010 if (skip_past_comma (&input_line_pointer) != FAIL)
4011 expression (&exp);
4012 else
4013 exp.X_op = O_illegal;
b99bd4ef 4014
c19d1205 4015 if (exp.X_op != O_constant)
b99bd4ef 4016 {
c19d1205
ZW		 4017 as_bad (_("expected , <constant>"));
4018 ignore_rest_of_line ();
b99bd4ef
NC		 4019 return;
4020 }
4021
c19d1205
ZW		 4022 num_regs = exp.X_add_number;
4023
4024 if (num_regs < 1 || num_regs > 4)
b99bd4ef 4025 {
c19d1205
ZW		 4026 as_bad (_("number of registers must be in the range [1:4]"));
4027 ignore_rest_of_line ();
b99bd4ef
NC		 4028 return;
4029 }
4030
c19d1205 4031 demand_empty_rest_of_line ();
b99bd4ef 4032
c19d1205
ZW		 4033 if (reg == 4)
4034 {
4035 /* Short form. */
4036 op = 0xb4 | (num_regs - 1);
4037 add_unwind_opcode (op, 1);
4038 }
b99bd4ef
NC		 4039 else
4040 {
c19d1205
ZW		 4041 /* Long form. */
4042 op = 0xc800 | (reg << 4) | (num_regs - 1);
4043 add_unwind_opcode (op, 2);
b99bd4ef 4044 }
c19d1205 4045 unwind.frame_size += num_regs * 12;
b99bd4ef
NC		 4046}
4047
c19d1205 4048
fa073d69
MS		 4049/* Parse a directive saving VFP registers for ARMv6 and above. */
4050
4051static void
4052s_arm_unwind_save_vfp_armv6 (void)
4053{
4054 int count;
4055 unsigned int start;
4056 valueT op;
4057 int num_vfpv3_regs = 0;
4058 int num_regs_below_16;
4059
4060 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D);
4061 if (count == FAIL)
4062 {
4063 as_bad (_("expected register list"));
4064 ignore_rest_of_line ();
4065 return;
4066 }
4067
4068 demand_empty_rest_of_line ();
4069
4070 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4071 than FSTMX/FLDMX-style ones). */
4072
4073 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4074 if (start >= 16)
4075 num_vfpv3_regs = count;
4076 else if (start + count > 16)
4077 num_vfpv3_regs = start + count - 16;
4078
4079 if (num_vfpv3_regs > 0)
4080 {
4081 int start_offset = start > 16 ? start - 16 : 0;
4082 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4083 add_unwind_opcode (op, 2);
4084 }
4085
4086 /* Generate opcode for registers numbered in the range 0 .. 15. */
4087 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 4088 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS		 4089 if (num_regs_below_16 > 0)
4090 {
4091 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4092 add_unwind_opcode (op, 2);
4093 }
4094
4095 unwind.frame_size += count * 8;
4096}
4097
4098
4099/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC		 4100
4101static void
c19d1205 4102s_arm_unwind_save_vfp (void)
b99bd4ef 4103{
c19d1205 4104 int count;
ca3f61f7 4105 unsigned int reg;
c19d1205 4106 valueT op;
b99bd4ef 4107
5287ad62 4108 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D);
c19d1205 4109 if (count == FAIL)
b99bd4ef 4110 {
c19d1205
ZW		 4111 as_bad (_("expected register list"));
4112 ignore_rest_of_line ();
b99bd4ef
NC		 4113 return;
4114 }
4115
c19d1205 4116 demand_empty_rest_of_line ();
b99bd4ef 4117
c19d1205 4118 if (reg == 8)
b99bd4ef 4119 {
c19d1205
ZW		 4120 /* Short form. */
4121 op = 0xb8 | (count - 1);
4122 add_unwind_opcode (op, 1);
b99bd4ef 4123 }
c19d1205 4124 else
b99bd4ef 4125 {
c19d1205
ZW		 4126 /* Long form. */
4127 op = 0xb300 | (reg << 4) | (count - 1);
4128 add_unwind_opcode (op, 2);
b99bd4ef 4129 }
c19d1205
ZW		 4130 unwind.frame_size += count * 8 + 4;
4131}
b99bd4ef 4132
b99bd4ef 4133
c19d1205
ZW		 4134/* Parse a directive saving iWMMXt data registers. */
4135
4136static void
4137s_arm_unwind_save_mmxwr (void)
4138{
4139 int reg;
4140 int hi_reg;
4141 int i;
4142 unsigned mask = 0;
4143 valueT op;
b99bd4ef 4144
c19d1205
ZW		 4145 if (*input_line_pointer == '{')
4146 input_line_pointer++;
b99bd4ef 4147
c19d1205 4148 do
b99bd4ef 4149 {
dcbf9037 4150 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 4151
c19d1205 4152 if (reg == FAIL)
b99bd4ef 4153 {
9b7132d3 4154 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 4155 goto error;
b99bd4ef
NC		 4156 }
4157
c19d1205
ZW		 4158 if (mask >> reg)
4159 as_tsktsk (_("register list not in ascending order"));
4160 mask |= 1 << reg;
b99bd4ef 4161
c19d1205
ZW		 4162 if (*input_line_pointer == '-')
4163 {
4164 input_line_pointer++;
dcbf9037 4165 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW		 4166 if (hi_reg == FAIL)
4167 {
9b7132d3 4168 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW		 4169 goto error;
4170 }
4171 else if (reg >= hi_reg)
4172 {
4173 as_bad (_("bad register range"));
4174 goto error;
4175 }
4176 for (; reg < hi_reg; reg++)
4177 mask |= 1 << reg;
4178 }
4179 }
4180 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4181
d996d970 4182 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4183
c19d1205 4184 demand_empty_rest_of_line ();
b99bd4ef 4185
708587a4 4186 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4187 the list. */
4188 flush_pending_unwind ();
b99bd4ef 4189
c19d1205 4190 for (i = 0; i < 16; i++)
b99bd4ef 4191 {
c19d1205
ZW		 4192 if (mask & (1 << i))
4193 unwind.frame_size += 8;
b99bd4ef
NC		 4194 }
4195
c19d1205
ZW		 4196 /* Attempt to combine with a previous opcode. We do this because gcc
4197 likes to output separate unwind directives for a single block of
4198 registers. */
4199 if (unwind.opcode_count > 0)
b99bd4ef 4200 {
c19d1205
ZW		 4201 i = unwind.opcodes[unwind.opcode_count - 1];
4202 if ((i & 0xf8) == 0xc0)
4203 {
4204 i &= 7;
4205 /* Only merge if the blocks are contiguous. */
4206 if (i < 6)
4207 {
4208 if ((mask & 0xfe00) == (1 << 9))
4209 {
4210 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4211 unwind.opcode_count--;
4212 }
4213 }
4214 else if (i == 6 && unwind.opcode_count >= 2)
4215 {
4216 i = unwind.opcodes[unwind.opcode_count - 2];
4217 reg = i >> 4;
4218 i &= 0xf;
b99bd4ef 4219
c19d1205
ZW		 4220 op = 0xffff << (reg - 1);
4221 if (reg > 0
87a1fd79 4222 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW		 4223 {
4224 op = (1 << (reg + i + 1)) - 1;
4225 op &= ~((1 << reg) - 1);
4226 mask |= op;
4227 unwind.opcode_count -= 2;
4228 }
4229 }
4230 }
b99bd4ef
NC		 4231 }
4232
c19d1205
ZW		 4233 hi_reg = 15;
4234 /* We want to generate opcodes in the order the registers have been
4235 saved, ie. descending order. */
4236 for (reg = 15; reg >= -1; reg--)
b99bd4ef 4237 {
c19d1205
ZW		 4238 /* Save registers in blocks. */
4239 if (reg < 0
4240 || !(mask & (1 << reg)))
4241 {
4242 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 4243 preceding block. */
c19d1205
ZW		 4244 if (reg != hi_reg)
4245 {
4246 if (reg == 9)
4247 {
4248 /* Short form. */
4249 op = 0xc0 | (hi_reg - 10);
4250 add_unwind_opcode (op, 1);
4251 }
4252 else
4253 {
4254 /* Long form. */
4255 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4256 add_unwind_opcode (op, 2);
4257 }
4258 }
4259 hi_reg = reg - 1;
4260 }
b99bd4ef
NC		 4261 }
4262
c19d1205
ZW		 4263 return;
4264error:
4265 ignore_rest_of_line ();
b99bd4ef
NC		 4266}
4267
4268static void
c19d1205 4269s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4270{
c19d1205
ZW		 4271 int reg;
4272 int hi_reg;
4273 unsigned mask = 0;
4274 valueT op;
b99bd4ef 4275
c19d1205
ZW		 4276 if (*input_line_pointer == '{')
4277 input_line_pointer++;
b99bd4ef 4278
477330fc
RM		 4279 skip_whitespace (input_line_pointer);
4280
c19d1205 4281 do
b99bd4ef 4282 {
dcbf9037 4283 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4284
c19d1205
ZW		 4285 if (reg == FAIL)
4286 {
9b7132d3 4287 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4288 goto error;
4289 }
b99bd4ef 4290
c19d1205
ZW		 4291 reg -= 8;
4292 if (mask >> reg)
4293 as_tsktsk (_("register list not in ascending order"));
4294 mask |= 1 << reg;
b99bd4ef 4295
c19d1205
ZW		 4296 if (*input_line_pointer == '-')
4297 {
4298 input_line_pointer++;
dcbf9037 4299 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW		 4300 if (hi_reg == FAIL)
4301 {
9b7132d3 4302 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4303 goto error;
4304 }
4305 else if (reg >= hi_reg)
4306 {
4307 as_bad (_("bad register range"));
4308 goto error;
4309 }
4310 for (; reg < hi_reg; reg++)
4311 mask |= 1 << reg;
4312 }
b99bd4ef 4313 }
c19d1205 4314 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4315
d996d970 4316 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4317
c19d1205
ZW		 4318 demand_empty_rest_of_line ();
4319
708587a4 4320 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4321 the list. */
4322 flush_pending_unwind ();
b99bd4ef 4323
c19d1205 4324 for (reg = 0; reg < 16; reg++)
b99bd4ef 4325 {
c19d1205
ZW		 4326 if (mask & (1 << reg))
4327 unwind.frame_size += 4;
b99bd4ef 4328 }
c19d1205
ZW		 4329 op = 0xc700 | mask;
4330 add_unwind_opcode (op, 2);
4331 return;
4332error:
4333 ignore_rest_of_line ();
b99bd4ef
NC		 4334}
4335
c19d1205 4336
fa073d69
MS		 4337/* Parse an unwind_save directive.
4338 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4339
b99bd4ef 4340static void
fa073d69 4341s_arm_unwind_save (int arch_v6)
b99bd4ef 4342{
c19d1205
ZW		 4343 char *peek;
4344 struct reg_entry *reg;
4345 bfd_boolean had_brace = FALSE;
b99bd4ef 4346
921e5f0a 4347 if (!unwind.proc_start)
c921be7d 4348 as_bad (MISSING_FNSTART);
921e5f0a 4349
c19d1205
ZW		 4350 /* Figure out what sort of save we have. */
4351 peek = input_line_pointer;
b99bd4ef 4352
c19d1205 4353 if (*peek == '{')
b99bd4ef 4354 {
c19d1205
ZW		 4355 had_brace = TRUE;
4356 peek++;
b99bd4ef
NC		 4357 }
4358
c19d1205 4359 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4360
c19d1205 4361 if (!reg)
b99bd4ef 4362 {
c19d1205
ZW		 4363 as_bad (_("register expected"));
4364 ignore_rest_of_line ();
b99bd4ef
NC		 4365 return;
4366 }
4367
c19d1205 4368 switch (reg->type)
b99bd4ef 4369 {
c19d1205
ZW		 4370 case REG_TYPE_FN:
4371 if (had_brace)
4372 {
4373 as_bad (_("FPA .unwind_save does not take a register list"));
4374 ignore_rest_of_line ();
4375 return;
4376 }
93ac2687 4377 input_line_pointer = peek;
c19d1205 4378 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4379 return;
c19d1205 4380
1f5afe1c
NC		 4381 case REG_TYPE_RN:
4382 s_arm_unwind_save_core ();
4383 return;
4384
fa073d69
MS		 4385 case REG_TYPE_VFD:
4386 if (arch_v6)
477330fc 4387 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4388 else
477330fc 4389 s_arm_unwind_save_vfp ();
fa073d69 4390 return;
1f5afe1c
NC		 4391
4392 case REG_TYPE_MMXWR:
4393 s_arm_unwind_save_mmxwr ();
4394 return;
4395
4396 case REG_TYPE_MMXWCG:
4397 s_arm_unwind_save_mmxwcg ();
4398 return;
c19d1205
ZW		 4399
4400 default:
4401 as_bad (_(".unwind_save does not support this kind of register"));
4402 ignore_rest_of_line ();
b99bd4ef 4403 }
c19d1205 4404}
b99bd4ef 4405
b99bd4ef 4406
c19d1205
ZW		 4407/* Parse an unwind_movsp directive. */
4408
4409static void
4410s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4411{
4412 int reg;
4413 valueT op;
4fa3602b 4414 int offset;
c19d1205 4415
921e5f0a 4416 if (!unwind.proc_start)
c921be7d 4417 as_bad (MISSING_FNSTART);
921e5f0a 4418
dcbf9037 4419 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4420 if (reg == FAIL)
b99bd4ef 4421 {
9b7132d3 4422 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4423 ignore_rest_of_line ();
b99bd4ef
NC		 4424 return;
4425 }
4fa3602b
PB		 4426
4427 /* Optional constant. */
4428 if (skip_past_comma (&input_line_pointer) != FAIL)
4429 {
4430 if (immediate_for_directive (&offset) == FAIL)
4431 return;
4432 }
4433 else
4434 offset = 0;
4435
c19d1205 4436 demand_empty_rest_of_line ();
b99bd4ef 4437
c19d1205 4438 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4439 {
c19d1205 4440 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC		 4441 return;
4442 }
4443
c19d1205
ZW		 4444 if (unwind.fp_reg != REG_SP)
4445 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4446
c19d1205
ZW		 4447 /* Generate opcode to restore the value. */
4448 op = 0x90 | reg;
4449 add_unwind_opcode (op, 1);
4450
4451 /* Record the information for later. */
4452 unwind.fp_reg = reg;
4fa3602b 4453 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4454 unwind.sp_restored = 1;
b05fe5cf
ZW		 4455}
4456
c19d1205
ZW		 4457/* Parse an unwind_pad directive. */
4458
b05fe5cf 4459static void
c19d1205 4460s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4461{
c19d1205 4462 int offset;
b05fe5cf 4463
921e5f0a 4464 if (!unwind.proc_start)
c921be7d 4465 as_bad (MISSING_FNSTART);
921e5f0a 4466
c19d1205
ZW		 4467 if (immediate_for_directive (&offset) == FAIL)
4468 return;
b99bd4ef 4469
c19d1205
ZW		 4470 if (offset & 3)
4471 {
4472 as_bad (_("stack increment must be multiple of 4"));
4473 ignore_rest_of_line ();
4474 return;
4475 }
b99bd4ef 4476
c19d1205
ZW		 4477 /* Don't generate any opcodes, just record the details for later. */
4478 unwind.frame_size += offset;
4479 unwind.pending_offset += offset;
4480
4481 demand_empty_rest_of_line ();
4482}
4483
4484/* Parse an unwind_setfp directive. */
4485
4486static void
4487s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4488{
c19d1205
ZW		 4489 int sp_reg;
4490 int fp_reg;
4491 int offset;
4492
921e5f0a 4493 if (!unwind.proc_start)
c921be7d 4494 as_bad (MISSING_FNSTART);
921e5f0a 4495
dcbf9037 4496 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW		 4497 if (skip_past_comma (&input_line_pointer) == FAIL)
4498 sp_reg = FAIL;
4499 else
dcbf9037 4500 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4501
c19d1205
ZW		 4502 if (fp_reg == FAIL || sp_reg == FAIL)
4503 {
4504 as_bad (_("expected <reg>, <reg>"));
4505 ignore_rest_of_line ();
4506 return;
4507 }
b99bd4ef 4508
c19d1205
ZW		 4509 /* Optional constant. */
4510 if (skip_past_comma (&input_line_pointer) != FAIL)
4511 {
4512 if (immediate_for_directive (&offset) == FAIL)
4513 return;
4514 }
4515 else
4516 offset = 0;
a737bd4d 4517
c19d1205 4518 demand_empty_rest_of_line ();
a737bd4d 4519
fdfde340 4520 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4521 {
c19d1205
ZW		 4522 as_bad (_("register must be either sp or set by a previous"
4523 "unwind_movsp directive"));
4524 return;
a737bd4d
NC		 4525 }
4526
c19d1205
ZW		 4527 /* Don't generate any opcodes, just record the information for later. */
4528 unwind.fp_reg = fp_reg;
4529 unwind.fp_used = 1;
fdfde340 4530 if (sp_reg == REG_SP)
c19d1205
ZW		 4531 unwind.fp_offset = unwind.frame_size - offset;
4532 else
4533 unwind.fp_offset -= offset;
a737bd4d
NC		 4534}
4535
c19d1205
ZW		 4536/* Parse an unwind_raw directive. */
4537
4538static void
4539s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4540{
c19d1205 4541 expressionS exp;
708587a4 4542 /* This is an arbitrary limit. */
c19d1205
ZW		 4543 unsigned char op[16];
4544 int count;
a737bd4d 4545
921e5f0a 4546 if (!unwind.proc_start)
c921be7d 4547 as_bad (MISSING_FNSTART);
921e5f0a 4548
c19d1205
ZW		 4549 expression (&exp);
4550 if (exp.X_op == O_constant
4551 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4552 {
c19d1205
ZW		 4553 unwind.frame_size += exp.X_add_number;
4554 expression (&exp);
4555 }
4556 else
4557 exp.X_op = O_illegal;
a737bd4d 4558
c19d1205
ZW		 4559 if (exp.X_op != O_constant)
4560 {
4561 as_bad (_("expected <offset>, <opcode>"));
4562 ignore_rest_of_line ();
4563 return;
4564 }
a737bd4d 4565
c19d1205 4566 count = 0;
a737bd4d 4567
c19d1205
ZW		 4568 /* Parse the opcode. */
4569 for (;;)
4570 {
4571 if (count >= 16)
4572 {
4573 as_bad (_("unwind opcode too long"));
4574 ignore_rest_of_line ();
a737bd4d 4575 }
c19d1205 4576 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4577 {
c19d1205
ZW		 4578 as_bad (_("invalid unwind opcode"));
4579 ignore_rest_of_line ();
4580 return;
a737bd4d 4581 }
c19d1205 4582 op[count++] = exp.X_add_number;
a737bd4d 4583
c19d1205
ZW		 4584 /* Parse the next byte. */
4585 if (skip_past_comma (&input_line_pointer) == FAIL)
4586 break;
a737bd4d 4587
c19d1205
ZW		 4588 expression (&exp);
4589 }
b99bd4ef 4590
c19d1205
ZW		 4591 /* Add the opcode bytes in reverse order. */
4592 while (count--)
4593 add_unwind_opcode (op[count], 1);
b99bd4ef 4594
c19d1205 4595 demand_empty_rest_of_line ();
b99bd4ef 4596}
ee065d83
PB		 4597
4598
4599/* Parse a .eabi_attribute directive. */
4600
4601static void
4602s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4603{
0420f52b 4604 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378
AS		 4605
4606 if (tag < NUM_KNOWN_OBJ_ATTRIBUTES)
4607 attributes_set_explicitly[tag] = 1;
ee065d83
PB		 4608}
4609
0855e32b
NS		 4610/* Emit a tls fix for the symbol. */
4611
4612static void
4613s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4614{
4615 char *p;
4616 expressionS exp;
4617#ifdef md_flush_pending_output
4618 md_flush_pending_output ();
4619#endif
4620
4621#ifdef md_cons_align
4622 md_cons_align (4);
4623#endif
4624
4625 /* Since we're just labelling the code, there's no need to define a
4626 mapping symbol. */
4627 expression (&exp);
4628 p = obstack_next_free (&frchain_now->frch_obstack);
4629 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4630 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4631 : BFD_RELOC_ARM_TLS_DESCSEQ);
4632}
cdf9ccec 4633#endif /* OBJ_ELF */
0855e32b 4634
ee065d83 4635static void s_arm_arch (int);
7a1d4c38 4636static void s_arm_object_arch (int);
ee065d83
PB		 4637static void s_arm_cpu (int);
4638static void s_arm_fpu (int);
69133863 4639static void s_arm_arch_extension (int);
b99bd4ef 4640
f0927246
NC		 4641#ifdef TE_PE
4642
4643static void
5f4273c7 4644pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC		 4645{
4646 expressionS exp;
4647
4648 do
4649 {
4650 expression (&exp);
4651 if (exp.X_op == O_symbol)
4652 exp.X_op = O_secrel;
4653
4654 emit_expr (&exp, 4);
4655 }
4656 while (*input_line_pointer++ == ',');
4657
4658 input_line_pointer--;
4659 demand_empty_rest_of_line ();
4660}
4661#endif /* TE_PE */
4662
c19d1205
ZW		 4663/* This table describes all the machine specific pseudo-ops the assembler
4664 has to support. The fields are:
4665 pseudo-op name without dot
4666 function to call to execute this pseudo-op
4667 Integer arg to pass to the function. */
b99bd4ef 4668
c19d1205 4669const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4670{
c19d1205
ZW		 4671 /* Never called because '.req' does not start a line. */
4672 { "req", s_req, 0 },
dcbf9037
JB		 4673 /* Following two are likewise never called. */
4674 { "dn", s_dn, 0 },
4675 { "qn", s_qn, 0 },
c19d1205
ZW		 4676 { "unreq", s_unreq, 0 },
4677 { "bss", s_bss, 0 },
4678 { "align", s_align, 0 },
4679 { "arm", s_arm, 0 },
4680 { "thumb", s_thumb, 0 },
4681 { "code", s_code, 0 },
4682 { "force_thumb", s_force_thumb, 0 },
4683 { "thumb_func", s_thumb_func, 0 },
4684 { "thumb_set", s_thumb_set, 0 },
4685 { "even", s_even, 0 },
4686 { "ltorg", s_ltorg, 0 },
4687 { "pool", s_ltorg, 0 },
4688 { "syntax", s_syntax, 0 },
8463be01
PB		 4689 { "cpu", s_arm_cpu, 0 },
4690 { "arch", s_arm_arch, 0 },
7a1d4c38 4691 { "object_arch", s_arm_object_arch, 0 },
8463be01 4692 { "fpu", s_arm_fpu, 0 },
69133863 4693 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 4694#ifdef OBJ_ELF
c921be7d
NC		 4695 { "word", s_arm_elf_cons, 4 },
4696 { "long", s_arm_elf_cons, 4 },
4697 { "inst.n", s_arm_elf_inst, 2 },
4698 { "inst.w", s_arm_elf_inst, 4 },
4699 { "inst", s_arm_elf_inst, 0 },
4700 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW		 4701 { "fnstart", s_arm_unwind_fnstart, 0 },
4702 { "fnend", s_arm_unwind_fnend, 0 },
4703 { "cantunwind", s_arm_unwind_cantunwind, 0 },
4704 { "personality", s_arm_unwind_personality, 0 },
4705 { "personalityindex", s_arm_unwind_personalityindex, 0 },
4706 { "handlerdata", s_arm_unwind_handlerdata, 0 },
4707 { "save", s_arm_unwind_save, 0 },
fa073d69 4708 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW		 4709 { "movsp", s_arm_unwind_movsp, 0 },
4710 { "pad", s_arm_unwind_pad, 0 },
4711 { "setfp", s_arm_unwind_setfp, 0 },
4712 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 4713 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 4714 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW		 4715#else
4716 { "word", cons, 4},
f0927246
NC		 4717
4718 /* These are used for dwarf. */
4719 {"2byte", cons, 2},
4720 {"4byte", cons, 4},
4721 {"8byte", cons, 8},
4722 /* These are used for dwarf2. */
4723 { "file", (void (*) (int)) dwarf2_directive_file, 0 },
4724 { "loc", dwarf2_directive_loc, 0 },
4725 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW		 4726#endif
4727 { "extend", float_cons, 'x' },
4728 { "ldouble", float_cons, 'x' },
4729 { "packed", float_cons, 'p' },
f0927246
NC		 4730#ifdef TE_PE
4731 {"secrel32", pe_directive_secrel, 0},
4732#endif
2e6976a8
DG		 4733
4734 /* These are for compatibility with CodeComposer Studio. */
4735 {"ref", s_ccs_ref, 0},
4736 {"def", s_ccs_def, 0},
4737 {"asmfunc", s_ccs_asmfunc, 0},
4738 {"endasmfunc", s_ccs_endasmfunc, 0},
4739
c19d1205
ZW		 4740 { 0, 0, 0 }
4741};
4742\f
4743/* Parser functions used exclusively in instruction operands. */
b99bd4ef 4744
c19d1205
ZW		 4745/* Generic immediate-value read function for use in insn parsing.
4746 STR points to the beginning of the immediate (the leading #);
4747 VAL receives the value; if the value is outside [MIN, MAX]
4748 issue an error. PREFIX_OPT is true if the immediate prefix is
4749 optional. */
b99bd4ef 4750
c19d1205
ZW		 4751static int
4752parse_immediate (char **str, int *val, int min, int max,
4753 bfd_boolean prefix_opt)
4754{
4755 expressionS exp;
4756 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
4757 if (exp.X_op != O_constant)
b99bd4ef 4758 {
c19d1205
ZW		 4759 inst.error = _("constant expression required");
4760 return FAIL;
4761 }
b99bd4ef 4762
c19d1205
ZW		 4763 if (exp.X_add_number < min || exp.X_add_number > max)
4764 {
4765 inst.error = _("immediate value out of range");
4766 return FAIL;
4767 }
b99bd4ef 4768
c19d1205
ZW		 4769 *val = exp.X_add_number;
4770 return SUCCESS;
4771}
b99bd4ef 4772
5287ad62 4773/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 4774 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB		 4775 instructions. Puts the result directly in inst.operands[i]. */
4776
4777static int
8335d6aa
JW		 4778parse_big_immediate (char **str, int i, expressionS *in_exp,
4779 bfd_boolean allow_symbol_p)
5287ad62
JB		 4780{
4781 expressionS exp;
8335d6aa 4782 expressionS *exp_p = in_exp ? in_exp : &exp;
5287ad62
JB		 4783 char *ptr = *str;
4784
8335d6aa 4785 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5287ad62 4786
8335d6aa 4787 if (exp_p->X_op == O_constant)
036dc3f7 4788 {
8335d6aa 4789 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
036dc3f7
PB		 4790 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4791 O_constant. We have to be careful not to break compilation for
4792 32-bit X_add_number, though. */
8335d6aa 4793 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 4794 {
8335d6aa
JW		 4795 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4796 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
4797 & 0xffffffff);
036dc3f7
PB		 4798 inst.operands[i].regisimm = 1;
4799 }
4800 }
8335d6aa
JW		 4801 else if (exp_p->X_op == O_big
4802 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5287ad62
JB		 4803 {
4804 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 4805
5287ad62 4806 /* Bignums have their least significant bits in
477330fc
RM		 4807 generic_bignum[0]. Make sure we put 32 bits in imm and
4808 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 4809 gas_assert (parts != 0);
95b75c01
NC		 4810
4811 /* Make sure that the number is not too big.
4812 PR 11972: Bignums can now be sign-extended to the
4813 size of a .octa so check that the out of range bits
4814 are all zero or all one. */
8335d6aa 4815 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
95b75c01
NC		 4816 {
4817 LITTLENUM_TYPE m = -1;
4818
4819 if (generic_bignum[parts * 2] != 0
4820 && generic_bignum[parts * 2] != m)
4821 return FAIL;
4822
8335d6aa 4823 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
95b75c01
NC		 4824 if (generic_bignum[j] != generic_bignum[j-1])
4825 return FAIL;
4826 }
4827
5287ad62
JB		 4828 inst.operands[i].imm = 0;
4829 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 4830 inst.operands[i].imm |= generic_bignum[idx]
4831 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 4832 inst.operands[i].reg = 0;
4833 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 4834 inst.operands[i].reg |= generic_bignum[idx]
4835 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 4836 inst.operands[i].regisimm = 1;
4837 }
8335d6aa 4838 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5287ad62 4839 return FAIL;
5f4273c7 4840
5287ad62
JB		 4841 *str = ptr;
4842
4843 return SUCCESS;
4844}
4845
c19d1205
ZW		 4846/* Returns the pseudo-register number of an FPA immediate constant,
4847 or FAIL if there isn't a valid constant here. */
b99bd4ef 4848
c19d1205
ZW		 4849static int
4850parse_fpa_immediate (char ** str)
4851{
4852 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4853 char * save_in;
4854 expressionS exp;
4855 int i;
4856 int j;
b99bd4ef 4857
c19d1205
ZW		 4858 /* First try and match exact strings, this is to guarantee
4859 that some formats will work even for cross assembly. */
b99bd4ef 4860
c19d1205
ZW		 4861 for (i = 0; fp_const[i]; i++)
4862 {
4863 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 4864 {
c19d1205 4865 char *start = *str;
b99bd4ef 4866
c19d1205
ZW		 4867 *str += strlen (fp_const[i]);
4868 if (is_end_of_line[(unsigned char) **str])
4869 return i + 8;
4870 *str = start;
4871 }
4872 }
b99bd4ef 4873
c19d1205
ZW		 4874 /* Just because we didn't get a match doesn't mean that the constant
4875 isn't valid, just that it is in a format that we don't
4876 automatically recognize. Try parsing it with the standard
4877 expression routines. */
b99bd4ef 4878
c19d1205 4879 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 4880
c19d1205
ZW		 4881 /* Look for a raw floating point number. */
4882 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
4883 && is_end_of_line[(unsigned char) *save_in])
4884 {
4885 for (i = 0; i < NUM_FLOAT_VALS; i++)
4886 {
4887 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 4888 {
c19d1205
ZW		 4889 if (words[j] != fp_values[i][j])
4890 break;
b99bd4ef
NC		 4891 }
4892
c19d1205 4893 if (j == MAX_LITTLENUMS)
b99bd4ef 4894 {
c19d1205
ZW		 4895 *str = save_in;
4896 return i + 8;
b99bd4ef
NC		 4897 }
4898 }
4899 }
b99bd4ef 4900
c19d1205
ZW		 4901 /* Try and parse a more complex expression, this will probably fail
4902 unless the code uses a floating point prefix (eg "0f"). */
4903 save_in = input_line_pointer;
4904 input_line_pointer = *str;
4905 if (expression (&exp) == absolute_section
4906 && exp.X_op == O_big
4907 && exp.X_add_number < 0)
4908 {
4909 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4910 Ditto for 15. */
4911 if (gen_to_words (words, 5, (long) 15) == 0)
4912 {
4913 for (i = 0; i < NUM_FLOAT_VALS; i++)
4914 {
4915 for (j = 0; j < MAX_LITTLENUMS; j++)
4916 {
4917 if (words[j] != fp_values[i][j])
4918 break;
4919 }
b99bd4ef 4920
c19d1205
ZW		 4921 if (j == MAX_LITTLENUMS)
4922 {
4923 *str = input_line_pointer;
4924 input_line_pointer = save_in;
4925 return i + 8;
4926 }
4927 }
4928 }
b99bd4ef
NC		 4929 }
4930
c19d1205
ZW		 4931 *str = input_line_pointer;
4932 input_line_pointer = save_in;
4933 inst.error = _("invalid FPA immediate expression");
4934 return FAIL;
b99bd4ef
NC		 4935}
4936
136da414
JB		 4937/* Returns 1 if a number has "quarter-precision" float format
4938 0baBbbbbbc defgh000 00000000 00000000. */
4939
4940static int
4941is_quarter_float (unsigned imm)
4942{
4943 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
4944 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
4945}
4946
aacf0b33
KT		 4947
4948/* Detect the presence of a floating point or integer zero constant,
4949 i.e. #0.0 or #0. */
4950
4951static bfd_boolean
4952parse_ifimm_zero (char **in)
4953{
4954 int error_code;
4955
4956 if (!is_immediate_prefix (**in))
4957 return FALSE;
4958
4959 ++*in;
0900a05b
JW		 4960
4961 /* Accept #0x0 as a synonym for #0. */
4962 if (strncmp (*in, "0x", 2) == 0)
4963 {
4964 int val;
4965 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
4966 return FALSE;
4967 return TRUE;
4968 }
4969
aacf0b33
KT		 4970 error_code = atof_generic (in, ".", EXP_CHARS,
4971 &generic_floating_point_number);
4972
4973 if (!error_code
4974 && generic_floating_point_number.sign == '+'
4975 && (generic_floating_point_number.low
4976 > generic_floating_point_number.leader))
4977 return TRUE;
4978
4979 return FALSE;
4980}
4981
136da414
JB		 4982/* Parse an 8-bit "quarter-precision" floating point number of the form:
4983 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB		 4984 The zero and minus-zero cases need special handling, since they can't be
4985 encoded in the "quarter-precision" float format, but can nonetheless be
4986 loaded as integer constants. */
136da414
JB		 4987
4988static unsigned
4989parse_qfloat_immediate (char **ccp, int *immed)
4990{
4991 char *str = *ccp;
c96612cc 4992 char *fpnum;
136da414 4993 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 4994 int found_fpchar = 0;
5f4273c7 4995
136da414 4996 skip_past_char (&str, '#');
5f4273c7 4997
c96612cc
JB		 4998 /* We must not accidentally parse an integer as a floating-point number. Make
4999 sure that the value we parse is not an integer by checking for special
5000 characters '.' or 'e'.
5001 FIXME: This is a horrible hack, but doing better is tricky because type
5002 information isn't in a very usable state at parse time. */
5003 fpnum = str;
5004 skip_whitespace (fpnum);
5005
5006 if (strncmp (fpnum, "0x", 2) == 0)
5007 return FAIL;
5008 else
5009 {
5010 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM		 5011 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5012 {
5013 found_fpchar = 1;
5014 break;
5015 }
c96612cc
JB		 5016
5017 if (!found_fpchar)
477330fc 5018 return FAIL;
c96612cc 5019 }
5f4273c7 5020
136da414
JB		 5021 if ((str = atof_ieee (str, 's', words)) != NULL)
5022 {
5023 unsigned fpword = 0;
5024 int i;
5f4273c7 5025
136da414
JB		 5026 /* Our FP word must be 32 bits (single-precision FP). */
5027 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM		 5028 {
5029 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5030 fpword |= words[i];
5031 }
5f4273c7 5032
c96612cc 5033 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 5034 *immed = fpword;
136da414 5035 else
477330fc 5036 return FAIL;
136da414
JB		 5037
5038 *ccp = str;
5f4273c7 5039
136da414
JB		 5040 return SUCCESS;
5041 }
5f4273c7 5042
136da414
JB		 5043 return FAIL;
5044}
5045
c19d1205
ZW		 5046/* Shift operands. */
5047enum shift_kind
b99bd4ef 5048{
c19d1205
ZW		 5049 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX
5050};
b99bd4ef 5051
c19d1205
ZW		 5052struct asm_shift_name
5053{
5054 const char *name;
5055 enum shift_kind kind;
5056};
b99bd4ef 5057
c19d1205
ZW		 5058/* Third argument to parse_shift. */
5059enum parse_shift_mode
5060{
5061 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5062 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5063 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5064 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5065 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
5066};
b99bd4ef 5067
c19d1205
ZW		 5068/* Parse a <shift> specifier on an ARM data processing instruction.
5069 This has three forms:
b99bd4ef 5070
c19d1205
ZW		 5071 (LSL|LSR|ASL|ASR|ROR) Rs
5072 (LSL|LSR|ASL|ASR|ROR) #imm
5073 RRX
b99bd4ef 5074
c19d1205
ZW		 5075 Note that ASL is assimilated to LSL in the instruction encoding, and
5076 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 5077
c19d1205
ZW		 5078static int
5079parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 5080{
c19d1205
ZW		 5081 const struct asm_shift_name *shift_name;
5082 enum shift_kind shift;
5083 char *s = *str;
5084 char *p = s;
5085 int reg;
b99bd4ef 5086
c19d1205
ZW		 5087 for (p = *str; ISALPHA (*p); p++)
5088 ;
b99bd4ef 5089
c19d1205 5090 if (p == *str)
b99bd4ef 5091 {
c19d1205
ZW		 5092 inst.error = _("shift expression expected");
5093 return FAIL;
b99bd4ef
NC		 5094 }
5095
21d799b5 5096 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 5097 p - *str);
c19d1205
ZW		 5098
5099 if (shift_name == NULL)
b99bd4ef 5100 {
c19d1205
ZW		 5101 inst.error = _("shift expression expected");
5102 return FAIL;
b99bd4ef
NC		 5103 }
5104
c19d1205 5105 shift = shift_name->kind;
b99bd4ef 5106
c19d1205
ZW		 5107 switch (mode)
5108 {
5109 case NO_SHIFT_RESTRICT:
5110 case SHIFT_IMMEDIATE: break;
b99bd4ef 5111
c19d1205
ZW		 5112 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5113 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5114 {
5115 inst.error = _("'LSL' or 'ASR' required");
5116 return FAIL;
5117 }
5118 break;
b99bd4ef 5119
c19d1205
ZW		 5120 case SHIFT_LSL_IMMEDIATE:
5121 if (shift != SHIFT_LSL)
5122 {
5123 inst.error = _("'LSL' required");
5124 return FAIL;
5125 }
5126 break;
b99bd4ef 5127
c19d1205
ZW		 5128 case SHIFT_ASR_IMMEDIATE:
5129 if (shift != SHIFT_ASR)
5130 {
5131 inst.error = _("'ASR' required");
5132 return FAIL;
5133 }
5134 break;
b99bd4ef 5135
c19d1205
ZW		 5136 default: abort ();
5137 }
b99bd4ef 5138
c19d1205
ZW		 5139 if (shift != SHIFT_RRX)
5140 {
5141 /* Whitespace can appear here if the next thing is a bare digit. */
5142 skip_whitespace (p);
b99bd4ef 5143
c19d1205 5144 if (mode == NO_SHIFT_RESTRICT
dcbf9037 5145 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5146 {
5147 inst.operands[i].imm = reg;
5148 inst.operands[i].immisreg = 1;
5149 }
5150 else if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5151 return FAIL;
5152 }
5153 inst.operands[i].shift_kind = shift;
5154 inst.operands[i].shifted = 1;
5155 *str = p;
5156 return SUCCESS;
b99bd4ef
NC		 5157}
5158
c19d1205 5159/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 5160
c19d1205
ZW		 5161 #<immediate>
5162 #<immediate>, <rotate>
5163 <Rm>
5164 <Rm>, <shift>
b99bd4ef 5165
c19d1205
ZW		 5166 where <shift> is defined by parse_shift above, and <rotate> is a
5167 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 5168 is deferred to md_apply_fix. */
b99bd4ef 5169
c19d1205
ZW		 5170static int
5171parse_shifter_operand (char **str, int i)
5172{
5173 int value;
91d6fa6a 5174 expressionS exp;
b99bd4ef 5175
dcbf9037 5176 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5177 {
5178 inst.operands[i].reg = value;
5179 inst.operands[i].isreg = 1;
b99bd4ef 5180
c19d1205
ZW		 5181 /* parse_shift will override this if appropriate */
5182 inst.reloc.exp.X_op = O_constant;
5183 inst.reloc.exp.X_add_number = 0;
b99bd4ef 5184
c19d1205
ZW		 5185 if (skip_past_comma (str) == FAIL)
5186 return SUCCESS;
b99bd4ef 5187
c19d1205
ZW		 5188 /* Shift operation on register. */
5189 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC		 5190 }
5191
c19d1205
ZW		 5192 if (my_get_expression (&inst.reloc.exp, str, GE_IMM_PREFIX))
5193 return FAIL;
b99bd4ef 5194
c19d1205 5195 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 5196 {
c19d1205 5197 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 5198 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 5199 return FAIL;
b99bd4ef 5200
91d6fa6a 5201 if (exp.X_op != O_constant || inst.reloc.exp.X_op != O_constant)
c19d1205
ZW		 5202 {
5203 inst.error = _("constant expression expected");
5204 return FAIL;
5205 }
b99bd4ef 5206
91d6fa6a 5207 value = exp.X_add_number;
c19d1205
ZW		 5208 if (value < 0 || value > 30 || value % 2 != 0)
5209 {
5210 inst.error = _("invalid rotation");
5211 return FAIL;
5212 }
5213 if (inst.reloc.exp.X_add_number < 0 || inst.reloc.exp.X_add_number > 255)
5214 {
5215 inst.error = _("invalid constant");
5216 return FAIL;
5217 }
09d92015 5218
a415b1cd
JB		 5219 /* Encode as specified. */
5220 inst.operands[i].imm = inst.reloc.exp.X_add_number | value << 7;
5221 return SUCCESS;
09d92015
MM		 5222 }
5223
c19d1205
ZW		 5224 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
5225 inst.reloc.pc_rel = 0;
5226 return SUCCESS;
09d92015
MM		 5227}
5228
4962c51a
MS		 5229/* Group relocation information. Each entry in the table contains the
5230 textual name of the relocation as may appear in assembler source
5231 and must end with a colon.
5232 Along with this textual name are the relocation codes to be used if
5233 the corresponding instruction is an ALU instruction (ADD or SUB only),
5234 an LDR, an LDRS, or an LDC. */
5235
5236struct group_reloc_table_entry
5237{
5238 const char *name;
5239 int alu_code;
5240 int ldr_code;
5241 int ldrs_code;
5242 int ldc_code;
5243};
5244
5245typedef enum
5246{
5247 /* Varieties of non-ALU group relocation. */
5248
5249 GROUP_LDR,
5250 GROUP_LDRS,
5251 GROUP_LDC
5252} group_reloc_type;
5253
5254static struct group_reloc_table_entry group_reloc_table[] =
5255 { /* Program counter relative: */
5256 { "pc_g0_nc",
5257 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5258 0, /* LDR */
5259 0, /* LDRS */
5260 0 }, /* LDC */
5261 { "pc_g0",
5262 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5263 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5264 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5265 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5266 { "pc_g1_nc",
5267 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5268 0, /* LDR */
5269 0, /* LDRS */
5270 0 }, /* LDC */
5271 { "pc_g1",
5272 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5273 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5274 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5275 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5276 { "pc_g2",
5277 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5278 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5279 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5280 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5281 /* Section base relative */
5282 { "sb_g0_nc",
5283 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5284 0, /* LDR */
5285 0, /* LDRS */
5286 0 }, /* LDC */
5287 { "sb_g0",
5288 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5289 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5290 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5291 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5292 { "sb_g1_nc",
5293 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5294 0, /* LDR */
5295 0, /* LDRS */
5296 0 }, /* LDC */
5297 { "sb_g1",
5298 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5299 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5300 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5301 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5302 { "sb_g2",
5303 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5304 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5305 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
5306 BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
5307
5308/* Given the address of a pointer pointing to the textual name of a group
5309 relocation as may appear in assembler source, attempt to find its details
5310 in group_reloc_table. The pointer will be updated to the character after
5311 the trailing colon. On failure, FAIL will be returned; SUCCESS
5312 otherwise. On success, *entry will be updated to point at the relevant
5313 group_reloc_table entry. */
5314
5315static int
5316find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5317{
5318 unsigned int i;
5319 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5320 {
5321 int length = strlen (group_reloc_table[i].name);
5322
5f4273c7
NC		 5323 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5324 && (*str)[length] == ':')
477330fc
RM		 5325 {
5326 *out = &group_reloc_table[i];
5327 *str += (length + 1);
5328 return SUCCESS;
5329 }
4962c51a
MS		 5330 }
5331
5332 return FAIL;
5333}
5334
5335/* Parse a <shifter_operand> for an ARM data processing instruction
5336 (as for parse_shifter_operand) where group relocations are allowed:
5337
5338 #<immediate>
5339 #<immediate>, <rotate>
5340 #:<group_reloc>:<expression>
5341 <Rm>
5342 <Rm>, <shift>
5343
5344 where <group_reloc> is one of the strings defined in group_reloc_table.
5345 The hashes are optional.
5346
5347 Everything else is as for parse_shifter_operand. */
5348
5349static parse_operand_result
5350parse_shifter_operand_group_reloc (char **str, int i)
5351{
5352 /* Determine if we have the sequence of characters #: or just :
5353 coming next. If we do, then we check for a group relocation.
5354 If we don't, punt the whole lot to parse_shifter_operand. */
5355
5356 if (((*str)[0] == '#' && (*str)[1] == ':')
5357 || (*str)[0] == ':')
5358 {
5359 struct group_reloc_table_entry *entry;
5360
5361 if ((*str)[0] == '#')
477330fc 5362 (*str) += 2;
4962c51a 5363 else
477330fc 5364 (*str)++;
4962c51a
MS		 5365
5366 /* Try to parse a group relocation. Anything else is an error. */
5367 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM		 5368 {
5369 inst.error = _("unknown group relocation");
5370 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5371 }
4962c51a
MS		 5372
5373 /* We now have the group relocation table entry corresponding to
477330fc 5374 the name in the assembler source. Next, we parse the expression. */
4962c51a 5375 if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
477330fc 5376 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS		 5377
5378 /* Record the relocation type (always the ALU variant here). */
21d799b5 5379 inst.reloc.type = (bfd_reloc_code_real_type) entry->alu_code;
9c2799c2 5380 gas_assert (inst.reloc.type != 0);
4962c51a
MS		 5381
5382 return PARSE_OPERAND_SUCCESS;
5383 }
5384 else
5385 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5386 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS		 5387
5388 /* Never reached. */
5389}
5390
8e560766
MGD		 5391/* Parse a Neon alignment expression. Information is written to
5392 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5393
8e560766
MGD		 5394 align .imm = align << 8, .immisalign=1, .preind=0 */
5395static parse_operand_result
5396parse_neon_alignment (char **str, int i)
5397{
5398 char *p = *str;
5399 expressionS exp;
5400
5401 my_get_expression (&exp, &p, GE_NO_PREFIX);
5402
5403 if (exp.X_op != O_constant)
5404 {
5405 inst.error = _("alignment must be constant");
5406 return PARSE_OPERAND_FAIL;
5407 }
5408
5409 inst.operands[i].imm = exp.X_add_number << 8;
5410 inst.operands[i].immisalign = 1;
5411 /* Alignments are not pre-indexes. */
5412 inst.operands[i].preind = 0;
5413
5414 *str = p;
5415 return PARSE_OPERAND_SUCCESS;
5416}
5417
c19d1205
ZW		 5418/* Parse all forms of an ARM address expression. Information is written
5419 to inst.operands[i] and/or inst.reloc.
09d92015 5420
c19d1205 5421 Preindexed addressing (.preind=1):
09d92015 5422
c19d1205
ZW		 5423 [Rn, #offset] .reg=Rn .reloc.exp=offset
5424 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5425 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5426 .shift_kind=shift .reloc.exp=shift_imm
09d92015 5427
c19d1205 5428 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5429
c19d1205 5430 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5431
c19d1205
ZW		 5432 [Rn], #offset .reg=Rn .reloc.exp=offset
5433 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5434 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5435 .shift_kind=shift .reloc.exp=shift_imm
09d92015 5436
c19d1205 5437 Unindexed addressing (.preind=0, .postind=0):
09d92015 5438
c19d1205 5439 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5440
c19d1205 5441 Other:
09d92015 5442
c19d1205
ZW		 5443 [Rn]{!} shorthand for [Rn,#0]{!}
5444 =immediate .isreg=0 .reloc.exp=immediate
5445 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
09d92015 5446
c19d1205
ZW		 5447 It is the caller's responsibility to check for addressing modes not
5448 supported by the instruction, and to set inst.reloc.type. */
5449
4962c51a
MS		 5450static parse_operand_result
5451parse_address_main (char **str, int i, int group_relocations,
477330fc 5452 group_reloc_type group_type)
09d92015 5453{
c19d1205
ZW		 5454 char *p = *str;
5455 int reg;
09d92015 5456
c19d1205 5457 if (skip_past_char (&p, '[') == FAIL)
09d92015 5458 {
c19d1205
ZW		 5459 if (skip_past_char (&p, '=') == FAIL)
5460 {
974da60d 5461 /* Bare address - translate to PC-relative offset. */
c19d1205
ZW		 5462 inst.reloc.pc_rel = 1;
5463 inst.operands[i].reg = REG_PC;
5464 inst.operands[i].isreg = 1;
5465 inst.operands[i].preind = 1;
09d92015 5466
8335d6aa
JW		 5467 if (my_get_expression (&inst.reloc.exp, &p, GE_OPT_PREFIX_BIG))
5468 return PARSE_OPERAND_FAIL;
5469 }
5470 else if (parse_big_immediate (&p, i, &inst.reloc.exp,
5471 /*allow_symbol_p=*/TRUE))
4962c51a 5472 return PARSE_OPERAND_FAIL;
09d92015 5473
c19d1205 5474 *str = p;
4962c51a 5475 return PARSE_OPERAND_SUCCESS;
09d92015
MM		 5476 }
5477
8ab8155f
NC		 5478 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5479 skip_whitespace (p);
5480
dcbf9037 5481 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5482 {
c19d1205 5483 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5484 return PARSE_OPERAND_FAIL;
09d92015 5485 }
c19d1205
ZW		 5486 inst.operands[i].reg = reg;
5487 inst.operands[i].isreg = 1;
09d92015 5488
c19d1205 5489 if (skip_past_comma (&p) == SUCCESS)
09d92015 5490 {
c19d1205 5491 inst.operands[i].preind = 1;
09d92015 5492
c19d1205
ZW		 5493 if (*p == '+') p++;
5494 else if (*p == '-') p++, inst.operands[i].negative = 1;
5495
dcbf9037 5496 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5497 {
c19d1205
ZW		 5498 inst.operands[i].imm = reg;
5499 inst.operands[i].immisreg = 1;
5500
5501 if (skip_past_comma (&p) == SUCCESS)
5502 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5503 return PARSE_OPERAND_FAIL;
c19d1205 5504 }
5287ad62 5505 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD		 5506 {
5507 /* FIXME: '@' should be used here, but it's filtered out by generic
5508 code before we get to see it here. This may be subject to
5509 change. */
5510 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5511
8e560766
MGD		 5512 if (result != PARSE_OPERAND_SUCCESS)
5513 return result;
5514 }
c19d1205
ZW		 5515 else
5516 {
5517 if (inst.operands[i].negative)
5518 {
5519 inst.operands[i].negative = 0;
5520 p--;
5521 }
4962c51a 5522
5f4273c7
NC		 5523 if (group_relocations
5524 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS		 5525 {
5526 struct group_reloc_table_entry *entry;
5527
477330fc
RM		 5528 /* Skip over the #: or : sequence. */
5529 if (*p == '#')
5530 p += 2;
5531 else
5532 p++;
4962c51a
MS		 5533
5534 /* Try to parse a group relocation. Anything else is an
477330fc 5535 error. */
4962c51a
MS		 5536 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5537 {
5538 inst.error = _("unknown group relocation");
5539 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5540 }
5541
5542 /* We now have the group relocation table entry corresponding to
5543 the name in the assembler source. Next, we parse the
477330fc 5544 expression. */
4962c51a
MS		 5545 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5546 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5547
5548 /* Record the relocation type. */
477330fc
RM		 5549 switch (group_type)
5550 {
5551 case GROUP_LDR:
5552 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldr_code;
5553 break;
4962c51a 5554
477330fc
RM		 5555 case GROUP_LDRS:
5556 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldrs_code;
5557 break;
4962c51a 5558
477330fc
RM		 5559 case GROUP_LDC:
5560 inst.reloc.type = (bfd_reloc_code_real_type) entry->ldc_code;
5561 break;
4962c51a 5562
477330fc
RM		 5563 default:
5564 gas_assert (0);
5565 }
4962c51a 5566
477330fc 5567 if (inst.reloc.type == 0)
4962c51a
MS		 5568 {
5569 inst.error = _("this group relocation is not allowed on this instruction");
5570 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5571 }
477330fc
RM		 5572 }
5573 else
26d97720
NS		 5574 {
5575 char *q = p;
5576 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
5577 return PARSE_OPERAND_FAIL;
5578 /* If the offset is 0, find out if it's a +0 or -0. */
5579 if (inst.reloc.exp.X_op == O_constant
5580 && inst.reloc.exp.X_add_number == 0)
5581 {
5582 skip_whitespace (q);
5583 if (*q == '#')
5584 {
5585 q++;
5586 skip_whitespace (q);
5587 }
5588 if (*q == '-')
5589 inst.operands[i].negative = 1;
5590 }
5591 }
09d92015
MM		 5592 }
5593 }
8e560766
MGD		 5594 else if (skip_past_char (&p, ':') == SUCCESS)
5595 {
5596 /* FIXME: '@' should be used here, but it's filtered out by generic code
5597 before we get to see it here. This may be subject to change. */
5598 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5599
8e560766
MGD		 5600 if (result != PARSE_OPERAND_SUCCESS)
5601 return result;
5602 }
09d92015 5603
c19d1205 5604 if (skip_past_char (&p, ']') == FAIL)
09d92015 5605 {
c19d1205 5606 inst.error = _("']' expected");
4962c51a 5607 return PARSE_OPERAND_FAIL;
09d92015
MM		 5608 }
5609
c19d1205
ZW		 5610 if (skip_past_char (&p, '!') == SUCCESS)
5611 inst.operands[i].writeback = 1;
09d92015 5612
c19d1205 5613 else if (skip_past_comma (&p) == SUCCESS)
09d92015 5614 {
c19d1205
ZW		 5615 if (skip_past_char (&p, '{') == SUCCESS)
5616 {
5617 /* [Rn], {expr} - unindexed, with option */
5618 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 5619 0, 255, TRUE) == FAIL)
4962c51a 5620 return PARSE_OPERAND_FAIL;
09d92015 5621
c19d1205
ZW		 5622 if (skip_past_char (&p, '}') == FAIL)
5623 {
5624 inst.error = _("'}' expected at end of 'option' field");
4962c51a 5625 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5626 }
5627 if (inst.operands[i].preind)
5628 {
5629 inst.error = _("cannot combine index with option");
4962c51a 5630 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5631 }
5632 *str = p;
4962c51a 5633 return PARSE_OPERAND_SUCCESS;
09d92015 5634 }
c19d1205
ZW		 5635 else
5636 {
5637 inst.operands[i].postind = 1;
5638 inst.operands[i].writeback = 1;
09d92015 5639
c19d1205
ZW		 5640 if (inst.operands[i].preind)
5641 {
5642 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 5643 return PARSE_OPERAND_FAIL;
c19d1205 5644 }
09d92015 5645
c19d1205
ZW		 5646 if (*p == '+') p++;
5647 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 5648
dcbf9037 5649 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 5650 {
477330fc
RM		 5651 /* We might be using the immediate for alignment already. If we
5652 are, OR the register number into the low-order bits. */
5653 if (inst.operands[i].immisalign)
5654 inst.operands[i].imm |= reg;
5655 else
5656 inst.operands[i].imm = reg;
c19d1205 5657 inst.operands[i].immisreg = 1;
a737bd4d 5658
c19d1205
ZW		 5659 if (skip_past_comma (&p) == SUCCESS)
5660 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5661 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 5662 }
5663 else
5664 {
26d97720 5665 char *q = p;
c19d1205
ZW		 5666 if (inst.operands[i].negative)
5667 {
5668 inst.operands[i].negative = 0;
5669 p--;
5670 }
5671 if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
4962c51a 5672 return PARSE_OPERAND_FAIL;
26d97720
NS		 5673 /* If the offset is 0, find out if it's a +0 or -0. */
5674 if (inst.reloc.exp.X_op == O_constant
5675 && inst.reloc.exp.X_add_number == 0)
5676 {
5677 skip_whitespace (q);
5678 if (*q == '#')
5679 {
5680 q++;
5681 skip_whitespace (q);
5682 }
5683 if (*q == '-')
5684 inst.operands[i].negative = 1;
5685 }
c19d1205
ZW		 5686 }
5687 }
a737bd4d
NC		 5688 }
5689
c19d1205
ZW		 5690 /* If at this point neither .preind nor .postind is set, we have a
5691 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5692 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
5693 {
5694 inst.operands[i].preind = 1;
5695 inst.reloc.exp.X_op = O_constant;
5696 inst.reloc.exp.X_add_number = 0;
5697 }
5698 *str = p;
4962c51a
MS		 5699 return PARSE_OPERAND_SUCCESS;
5700}
5701
5702static int
5703parse_address (char **str, int i)
5704{
21d799b5 5705 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 5706 ? SUCCESS : FAIL;
4962c51a
MS		 5707}
5708
5709static parse_operand_result
5710parse_address_group_reloc (char **str, int i, group_reloc_type type)
5711{
5712 return parse_address_main (str, i, 1, type);
a737bd4d
NC		 5713}
5714
b6895b4f
PB		 5715/* Parse an operand for a MOVW or MOVT instruction. */
5716static int
5717parse_half (char **str)
5718{
5719 char * p;
5f4273c7 5720
b6895b4f
PB		 5721 p = *str;
5722 skip_past_char (&p, '#');
5f4273c7 5723 if (strncasecmp (p, ":lower16:", 9) == 0)
b6895b4f
PB		 5724 inst.reloc.type = BFD_RELOC_ARM_MOVW;
5725 else if (strncasecmp (p, ":upper16:", 9) == 0)
5726 inst.reloc.type = BFD_RELOC_ARM_MOVT;
5727
5728 if (inst.reloc.type != BFD_RELOC_UNUSED)
5729 {
5730 p += 9;
5f4273c7 5731 skip_whitespace (p);
b6895b4f
PB		 5732 }
5733
5734 if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
5735 return FAIL;
5736
5737 if (inst.reloc.type == BFD_RELOC_UNUSED)
5738 {
5739 if (inst.reloc.exp.X_op != O_constant)
5740 {
5741 inst.error = _("constant expression expected");
5742 return FAIL;
5743 }
5744 if (inst.reloc.exp.X_add_number < 0
5745 || inst.reloc.exp.X_add_number > 0xffff)
5746 {
5747 inst.error = _("immediate value out of range");
5748 return FAIL;
5749 }
5750 }
5751 *str = p;
5752 return SUCCESS;
5753}
5754
c19d1205 5755/* Miscellaneous. */
a737bd4d 5756
c19d1205
ZW		 5757/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5758 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5759static int
d2cd1205 5760parse_psr (char **str, bfd_boolean lhs)
09d92015 5761{
c19d1205
ZW		 5762 char *p;
5763 unsigned long psr_field;
62b3e311
PB		 5764 const struct asm_psr *psr;
5765 char *start;
d2cd1205 5766 bfd_boolean is_apsr = FALSE;
ac7f631b 5767 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 5768
a4482bb6
NC		 5769 /* PR gas/12698: If the user has specified -march=all then m_profile will
5770 be TRUE, but we want to ignore it in this case as we are building for any
5771 CPU type, including non-m variants. */
5772 if (selected_cpu.core == arm_arch_any.core)
5773 m_profile = FALSE;
5774
c19d1205
ZW		 5775 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5776 feature for ease of use and backwards compatibility. */
5777 p = *str;
62b3e311 5778 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB		 5779 {
5780 if (m_profile)
5781 goto unsupported_psr;
fa94de6b 5782
d2cd1205
JB		 5783 psr_field = SPSR_BIT;
5784 }
5785 else if (strncasecmp (p, "CPSR", 4) == 0)
5786 {
5787 if (m_profile)
5788 goto unsupported_psr;
5789
5790 psr_field = 0;
5791 }
5792 else if (strncasecmp (p, "APSR", 4) == 0)
5793 {
5794 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5795 and ARMv7-R architecture CPUs. */
5796 is_apsr = TRUE;
5797 psr_field = 0;
5798 }
5799 else if (m_profile)
62b3e311
PB		 5800 {
5801 start = p;
5802 do
5803 p++;
5804 while (ISALNUM (*p) || *p == '_');
5805
d2cd1205
JB		 5806 if (strncasecmp (start, "iapsr", 5) == 0
5807 || strncasecmp (start, "eapsr", 5) == 0
5808 || strncasecmp (start, "xpsr", 4) == 0
5809 || strncasecmp (start, "psr", 3) == 0)
5810 p = start + strcspn (start, "rR") + 1;
5811
21d799b5 5812 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 5813 p - start);
d2cd1205 5814
62b3e311
PB		 5815 if (!psr)
5816 return FAIL;
09d92015 5817
d2cd1205
JB		 5818 /* If APSR is being written, a bitfield may be specified. Note that
5819 APSR itself is handled above. */
5820 if (psr->field <= 3)
5821 {
5822 psr_field = psr->field;
5823 is_apsr = TRUE;
5824 goto check_suffix;
5825 }
5826
62b3e311 5827 *str = p;
d2cd1205
JB		 5828 /* M-profile MSR instructions have the mask field set to "10", except
5829 *PSR variants which modify APSR, which may use a different mask (and
5830 have been handled already). Do that by setting the PSR_f field
5831 here. */
5832 return psr->field | (lhs ? PSR_f : 0);
62b3e311 5833 }
d2cd1205
JB		 5834 else
5835 goto unsupported_psr;
09d92015 5836
62b3e311 5837 p += 4;
d2cd1205 5838check_suffix:
c19d1205
ZW		 5839 if (*p == '_')
5840 {
5841 /* A suffix follows. */
c19d1205
ZW		 5842 p++;
5843 start = p;
a737bd4d 5844
c19d1205
ZW		 5845 do
5846 p++;
5847 while (ISALNUM (*p) || *p == '_');
a737bd4d 5848
d2cd1205
JB		 5849 if (is_apsr)
5850 {
5851 /* APSR uses a notation for bits, rather than fields. */
5852 unsigned int nzcvq_bits = 0;
5853 unsigned int g_bit = 0;
5854 char *bit;
fa94de6b 5855
d2cd1205
JB		 5856 for (bit = start; bit != p; bit++)
5857 {
5858 switch (TOLOWER (*bit))
477330fc 5859 {
d2cd1205
JB		 5860 case 'n':
5861 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
5862 break;
5863
5864 case 'z':
5865 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
5866 break;
5867
5868 case 'c':
5869 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
5870 break;
5871
5872 case 'v':
5873 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
5874 break;
fa94de6b 5875
d2cd1205
JB		 5876 case 'q':
5877 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
5878 break;
fa94de6b 5879
d2cd1205
JB		 5880 case 'g':
5881 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
5882 break;
fa94de6b 5883
d2cd1205
JB		 5884 default:
5885 inst.error = _("unexpected bit specified after APSR");
5886 return FAIL;
5887 }
5888 }
fa94de6b 5889
d2cd1205
JB		 5890 if (nzcvq_bits == 0x1f)
5891 psr_field |= PSR_f;
fa94de6b 5892
d2cd1205
JB		 5893 if (g_bit == 0x1)
5894 {
5895 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 5896 {
d2cd1205
JB		 5897 inst.error = _("selected processor does not "
5898 "support DSP extension");
5899 return FAIL;
5900 }
5901
5902 psr_field |= PSR_s;
5903 }
fa94de6b 5904
d2cd1205
JB		 5905 if ((nzcvq_bits & 0x20) != 0
5906 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
5907 || (g_bit & 0x2) != 0)
5908 {
5909 inst.error = _("bad bitmask specified after APSR");
5910 return FAIL;
5911 }
5912 }
5913 else
477330fc 5914 {
d2cd1205 5915 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 5916 p - start);
d2cd1205 5917 if (!psr)
477330fc 5918 goto error;
a737bd4d 5919
d2cd1205
JB		 5920 psr_field |= psr->field;
5921 }
a737bd4d 5922 }
c19d1205 5923 else
a737bd4d 5924 {
c19d1205
ZW		 5925 if (ISALNUM (*p))
5926 goto error; /* Garbage after "[CS]PSR". */
5927
d2cd1205 5928 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 5929 is deprecated, but allow it anyway. */
d2cd1205
JB		 5930 if (is_apsr && lhs)
5931 {
5932 psr_field |= PSR_f;
5933 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5934 "deprecated"));
5935 }
5936 else if (!m_profile)
5937 /* These bits are never right for M-profile devices: don't set them
5938 (only code paths which read/write APSR reach here). */
5939 psr_field |= (PSR_c | PSR_f);
a737bd4d 5940 }
c19d1205
ZW		 5941 *str = p;
5942 return psr_field;
a737bd4d 5943
d2cd1205
JB		 5944 unsupported_psr:
5945 inst.error = _("selected processor does not support requested special "
5946 "purpose register");
5947 return FAIL;
5948
c19d1205
ZW		 5949 error:
5950 inst.error = _("flag for {c}psr instruction expected");
5951 return FAIL;
a737bd4d
NC		 5952}
5953
c19d1205
ZW		 5954/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5955 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 5956
c19d1205
ZW		 5957static int
5958parse_cps_flags (char **str)
a737bd4d 5959{
c19d1205
ZW		 5960 int val = 0;
5961 int saw_a_flag = 0;
5962 char *s = *str;
a737bd4d 5963
c19d1205
ZW		 5964 for (;;)
5965 switch (*s++)
5966 {
5967 case '\0': case ',':
5968 goto done;
a737bd4d 5969
c19d1205
ZW		 5970 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
5971 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
5972 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 5973
c19d1205
ZW		 5974 default:
5975 inst.error = _("unrecognized CPS flag");
5976 return FAIL;
5977 }
a737bd4d 5978
c19d1205
ZW		 5979 done:
5980 if (saw_a_flag == 0)
a737bd4d 5981 {
c19d1205
ZW		 5982 inst.error = _("missing CPS flags");
5983 return FAIL;
a737bd4d 5984 }
a737bd4d 5985
c19d1205
ZW		 5986 *str = s - 1;
5987 return val;
a737bd4d
NC		 5988}
5989
c19d1205
ZW		 5990/* Parse an endian specifier ("BE" or "LE", case insensitive);
5991 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC		 5992
5993static int
c19d1205 5994parse_endian_specifier (char **str)
a737bd4d 5995{
c19d1205
ZW		 5996 int little_endian;
5997 char *s = *str;
a737bd4d 5998
c19d1205
ZW		 5999 if (strncasecmp (s, "BE", 2))
6000 little_endian = 0;
6001 else if (strncasecmp (s, "LE", 2))
6002 little_endian = 1;
6003 else
a737bd4d 6004 {
c19d1205 6005 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6006 return FAIL;
6007 }
6008
c19d1205 6009 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 6010 {
c19d1205 6011 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6012 return FAIL;
6013 }
6014
c19d1205
ZW		 6015 *str = s + 2;
6016 return little_endian;
6017}
a737bd4d 6018
c19d1205
ZW		 6019/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6020 value suitable for poking into the rotate field of an sxt or sxta
6021 instruction, or FAIL on error. */
6022
6023static int
6024parse_ror (char **str)
6025{
6026 int rot;
6027 char *s = *str;
6028
6029 if (strncasecmp (s, "ROR", 3) == 0)
6030 s += 3;
6031 else
a737bd4d 6032 {
c19d1205 6033 inst.error = _("missing rotation field after comma");
a737bd4d
NC		 6034 return FAIL;
6035 }
c19d1205
ZW		 6036
6037 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6038 return FAIL;
6039
6040 switch (rot)
a737bd4d 6041 {
c19d1205
ZW		 6042 case 0: *str = s; return 0x0;
6043 case 8: *str = s; return 0x1;
6044 case 16: *str = s; return 0x2;
6045 case 24: *str = s; return 0x3;
6046
6047 default:
6048 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC		 6049 return FAIL;
6050 }
c19d1205 6051}
a737bd4d 6052
c19d1205
ZW		 6053/* Parse a conditional code (from conds[] below). The value returned is in the
6054 range 0 .. 14, or FAIL. */
6055static int
6056parse_cond (char **str)
6057{
c462b453 6058 char *q;
c19d1205 6059 const struct asm_cond *c;
c462b453
PB		 6060 int n;
6061 /* Condition codes are always 2 characters, so matching up to
6062 3 characters is sufficient. */
6063 char cond[3];
a737bd4d 6064
c462b453
PB		 6065 q = *str;
6066 n = 0;
6067 while (ISALPHA (*q) && n < 3)
6068 {
e07e6e58 6069 cond[n] = TOLOWER (*q);
c462b453
PB		 6070 q++;
6071 n++;
6072 }
a737bd4d 6073
21d799b5 6074 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 6075 if (!c)
a737bd4d 6076 {
c19d1205 6077 inst.error = _("condition required");
a737bd4d
NC		 6078 return FAIL;
6079 }
6080
c19d1205
ZW		 6081 *str = q;
6082 return c->value;
6083}
6084
e797f7e0
MGD		 6085/* If the given feature available in the selected CPU, mark it as used.
6086 Returns TRUE iff feature is available. */
6087static bfd_boolean
6088mark_feature_used (const arm_feature_set *feature)
6089{
6090 /* Ensure the option is valid on the current architecture. */
6091 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
6092 return FALSE;
6093
6094 /* Add the appropriate architecture feature for the barrier option used.
6095 */
6096 if (thumb_mode)
6097 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
6098 else
6099 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
6100
6101 return TRUE;
6102}
6103
62b3e311
PB		 6104/* Parse an option for a barrier instruction. Returns the encoding for the
6105 option, or FAIL. */
6106static int
6107parse_barrier (char **str)
6108{
6109 char *p, *q;
6110 const struct asm_barrier_opt *o;
6111
6112 p = q = *str;
6113 while (ISALPHA (*q))
6114 q++;
6115
21d799b5 6116 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 6117 q - p);
62b3e311
PB		 6118 if (!o)
6119 return FAIL;
6120
e797f7e0
MGD		 6121 if (!mark_feature_used (&o->arch))
6122 return FAIL;
6123
62b3e311
PB		 6124 *str = q;
6125 return o->value;
6126}
6127
92e90b6e
PB		 6128/* Parse the operands of a table branch instruction. Similar to a memory
6129 operand. */
6130static int
6131parse_tb (char **str)
6132{
6133 char * p = *str;
6134 int reg;
6135
6136 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB		 6137 {
6138 inst.error = _("'[' expected");
6139 return FAIL;
6140 }
92e90b6e 6141
dcbf9037 6142 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6143 {
6144 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6145 return FAIL;
6146 }
6147 inst.operands[0].reg = reg;
6148
6149 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB		 6150 {
6151 inst.error = _("',' expected");
6152 return FAIL;
6153 }
5f4273c7 6154
dcbf9037 6155 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6156 {
6157 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6158 return FAIL;
6159 }
6160 inst.operands[0].imm = reg;
6161
6162 if (skip_past_comma (&p) == SUCCESS)
6163 {
6164 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6165 return FAIL;
6166 if (inst.reloc.exp.X_add_number != 1)
6167 {
6168 inst.error = _("invalid shift");
6169 return FAIL;
6170 }
6171 inst.operands[0].shifted = 1;
6172 }
6173
6174 if (skip_past_char (&p, ']') == FAIL)
6175 {
6176 inst.error = _("']' expected");
6177 return FAIL;
6178 }
6179 *str = p;
6180 return SUCCESS;
6181}
6182
5287ad62
JB		 6183/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6184 information on the types the operands can take and how they are encoded.
037e8744
JB		 6185 Up to four operands may be read; this function handles setting the
6186 ".present" field for each read operand itself.
5287ad62
JB		 6187 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6188 else returns FAIL. */
6189
6190static int
6191parse_neon_mov (char **str, int *which_operand)
6192{
6193 int i = *which_operand, val;
6194 enum arm_reg_type rtype;
6195 char *ptr = *str;
dcbf9037 6196 struct neon_type_el optype;
5f4273c7 6197
dcbf9037 6198 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
5287ad62
JB		 6199 {
6200 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6201 inst.operands[i].reg = val;
6202 inst.operands[i].isscalar = 1;
dcbf9037 6203 inst.operands[i].vectype = optype;
5287ad62
JB		 6204 inst.operands[i++].present = 1;
6205
6206 if (skip_past_comma (&ptr) == FAIL)
477330fc 6207 goto wanted_comma;
5f4273c7 6208
dcbf9037 6209 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 6210 goto wanted_arm;
5f4273c7 6211
5287ad62
JB		 6212 inst.operands[i].reg = val;
6213 inst.operands[i].isreg = 1;
6214 inst.operands[i].present = 1;
6215 }
037e8744 6216 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
477330fc 6217 != FAIL)
5287ad62
JB		 6218 {
6219 /* Cases 0, 1, 2, 3, 5 (D only). */
6220 if (skip_past_comma (&ptr) == FAIL)
477330fc 6221 goto wanted_comma;
5f4273c7 6222
5287ad62
JB		 6223 inst.operands[i].reg = val;
6224 inst.operands[i].isreg = 1;
6225 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB		 6226 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6227 inst.operands[i].isvec = 1;
dcbf9037 6228 inst.operands[i].vectype = optype;
5287ad62
JB		 6229 inst.operands[i++].present = 1;
6230
dcbf9037 6231 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6232 {
6233 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6234 Case 13: VMOV <Sd>, <Rm> */
6235 inst.operands[i].reg = val;
6236 inst.operands[i].isreg = 1;
6237 inst.operands[i].present = 1;
6238
6239 if (rtype == REG_TYPE_NQ)
6240 {
6241 first_error (_("can't use Neon quad register here"));
6242 return FAIL;
6243 }
6244 else if (rtype != REG_TYPE_VFS)
6245 {
6246 i++;
6247 if (skip_past_comma (&ptr) == FAIL)
6248 goto wanted_comma;
6249 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6250 goto wanted_arm;
6251 inst.operands[i].reg = val;
6252 inst.operands[i].isreg = 1;
6253 inst.operands[i].present = 1;
6254 }
6255 }
037e8744 6256 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
477330fc
RM		 6257 &optype)) != FAIL)
6258 {
6259 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6260 Case 1: VMOV<c><q> <Dd>, <Dm>
6261 Case 8: VMOV.F32 <Sd>, <Sm>
6262 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6263
6264 inst.operands[i].reg = val;
6265 inst.operands[i].isreg = 1;
6266 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6267 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6268 inst.operands[i].isvec = 1;
6269 inst.operands[i].vectype = optype;
6270 inst.operands[i].present = 1;
6271
6272 if (skip_past_comma (&ptr) == SUCCESS)
6273 {
6274 /* Case 15. */
6275 i++;
6276
6277 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6278 goto wanted_arm;
6279
6280 inst.operands[i].reg = val;
6281 inst.operands[i].isreg = 1;
6282 inst.operands[i++].present = 1;
6283
6284 if (skip_past_comma (&ptr) == FAIL)
6285 goto wanted_comma;
6286
6287 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6288 goto wanted_arm;
6289
6290 inst.operands[i].reg = val;
6291 inst.operands[i].isreg = 1;
6292 inst.operands[i].present = 1;
6293 }
6294 }
4641781c 6295 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM		 6296 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6297 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6298 Case 10: VMOV.F32 <Sd>, #<imm>
6299 Case 11: VMOV.F64 <Dd>, #<imm> */
6300 inst.operands[i].immisfloat = 1;
8335d6aa
JW		 6301 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6302 == SUCCESS)
477330fc
RM		 6303 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6304 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6305 ;
5287ad62 6306 else
477330fc
RM		 6307 {
6308 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6309 return FAIL;
6310 }
5287ad62 6311 }
dcbf9037 6312 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62
JB		 6313 {
6314 /* Cases 6, 7. */
6315 inst.operands[i].reg = val;
6316 inst.operands[i].isreg = 1;
6317 inst.operands[i++].present = 1;
5f4273c7 6318
5287ad62 6319 if (skip_past_comma (&ptr) == FAIL)
477330fc 6320 goto wanted_comma;
5f4273c7 6321
dcbf9037 6322 if ((val = parse_scalar (&ptr, 8, &optype)) != FAIL)
477330fc
RM		 6323 {
6324 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6325 inst.operands[i].reg = val;
6326 inst.operands[i].isscalar = 1;
6327 inst.operands[i].present = 1;
6328 inst.operands[i].vectype = optype;
6329 }
dcbf9037 6330 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6331 {
6332 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6333 inst.operands[i].reg = val;
6334 inst.operands[i].isreg = 1;
6335 inst.operands[i++].present = 1;
6336
6337 if (skip_past_comma (&ptr) == FAIL)
6338 goto wanted_comma;
6339
6340 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
6341 == FAIL)
6342 {
6343 first_error (_(reg_expected_msgs[REG_TYPE_VFSD]));
6344 return FAIL;
6345 }
6346
6347 inst.operands[i].reg = val;
6348 inst.operands[i].isreg = 1;
6349 inst.operands[i].isvec = 1;
6350 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6351 inst.operands[i].vectype = optype;
6352 inst.operands[i].present = 1;
6353
6354 if (rtype == REG_TYPE_VFS)
6355 {
6356 /* Case 14. */
6357 i++;
6358 if (skip_past_comma (&ptr) == FAIL)
6359 goto wanted_comma;
6360 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6361 &optype)) == FAIL)
6362 {
6363 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6364 return FAIL;
6365 }
6366 inst.operands[i].reg = val;
6367 inst.operands[i].isreg = 1;
6368 inst.operands[i].isvec = 1;
6369 inst.operands[i].issingle = 1;
6370 inst.operands[i].vectype = optype;
6371 inst.operands[i].present = 1;
6372 }
6373 }
037e8744 6374 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM		 6375 != FAIL)
6376 {
6377 /* Case 13. */
6378 inst.operands[i].reg = val;
6379 inst.operands[i].isreg = 1;
6380 inst.operands[i].isvec = 1;
6381 inst.operands[i].issingle = 1;
6382 inst.operands[i].vectype = optype;
6383 inst.operands[i].present = 1;
6384 }
5287ad62
JB		 6385 }
6386 else
6387 {
dcbf9037 6388 first_error (_("parse error"));
5287ad62
JB		 6389 return FAIL;
6390 }
6391
6392 /* Successfully parsed the operands. Update args. */
6393 *which_operand = i;
6394 *str = ptr;
6395 return SUCCESS;
6396
5f4273c7 6397 wanted_comma:
dcbf9037 6398 first_error (_("expected comma"));
5287ad62 6399 return FAIL;
5f4273c7
NC		 6400
6401 wanted_arm:
dcbf9037 6402 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 6403 return FAIL;
5287ad62
JB		 6404}
6405
5be8be5d
DG		 6406/* Use this macro when the operand constraints are different
6407 for ARM and THUMB (e.g. ldrd). */
6408#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6409 ((arm_operand) | ((thumb_operand) << 16))
6410
c19d1205
ZW		 6411/* Matcher codes for parse_operands. */
6412enum operand_parse_code
6413{
6414 OP_stop, /* end of line */
6415
6416 OP_RR, /* ARM register */
6417 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 6418 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 6419 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 6420 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 6421 optional trailing ! */
c19d1205
ZW		 6422 OP_RRw, /* ARM register, not r15, optional trailing ! */
6423 OP_RCP, /* Coprocessor number */
6424 OP_RCN, /* Coprocessor register */
6425 OP_RF, /* FPA register */
6426 OP_RVS, /* VFP single precision register */
5287ad62
JB		 6427 OP_RVD, /* VFP double precision register (0..15) */
6428 OP_RND, /* Neon double precision register (0..31) */
6429 OP_RNQ, /* Neon quad precision register */
037e8744 6430 OP_RVSD, /* VFP single or double precision register */
5287ad62 6431 OP_RNDQ, /* Neon double or quad precision register */
037e8744 6432 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 6433 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW		 6434 OP_RVC, /* VFP control register */
6435 OP_RMF, /* Maverick F register */
6436 OP_RMD, /* Maverick D register */
6437 OP_RMFX, /* Maverick FX register */
6438 OP_RMDX, /* Maverick DX register */
6439 OP_RMAX, /* Maverick AX register */
6440 OP_RMDS, /* Maverick DSPSC register */
6441 OP_RIWR, /* iWMMXt wR register */
6442 OP_RIWC, /* iWMMXt wC register */
6443 OP_RIWG, /* iWMMXt wCG register */
6444 OP_RXA, /* XScale accumulator register */
6445
6446 OP_REGLST, /* ARM register list */
6447 OP_VRSLST, /* VFP single-precision register list */
6448 OP_VRDLST, /* VFP double-precision register list */
037e8744 6449 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB		 6450 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
6451 OP_NSTRLST, /* Neon element/structure list */
6452
5287ad62 6453 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 6454 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
aacf0b33 6455 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
5287ad62 6456 OP_RR_RNSC, /* ARM reg or Neon scalar. */
037e8744 6457 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
5287ad62
JB		 6458 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
6459 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
6460 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 6461 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5287ad62 6462 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
2d447fca 6463 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5287ad62
JB		 6464
6465 OP_I0, /* immediate zero */
c19d1205
ZW		 6466 OP_I7, /* immediate value 0 .. 7 */
6467 OP_I15, /* 0 .. 15 */
6468 OP_I16, /* 1 .. 16 */
5287ad62 6469 OP_I16z, /* 0 .. 16 */
c19d1205
ZW		 6470 OP_I31, /* 0 .. 31 */
6471 OP_I31w, /* 0 .. 31, optional trailing ! */
6472 OP_I32, /* 1 .. 32 */
5287ad62
JB		 6473 OP_I32z, /* 0 .. 32 */
6474 OP_I63, /* 0 .. 63 */
c19d1205 6475 OP_I63s, /* -64 .. 63 */
5287ad62
JB		 6476 OP_I64, /* 1 .. 64 */
6477 OP_I64z, /* 0 .. 64 */
c19d1205 6478 OP_I255, /* 0 .. 255 */
c19d1205
ZW		 6479
6480 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
6481 OP_I7b, /* 0 .. 7 */
6482 OP_I15b, /* 0 .. 15 */
6483 OP_I31b, /* 0 .. 31 */
6484
6485 OP_SH, /* shifter operand */
4962c51a 6486 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 6487 OP_ADDR, /* Memory address expression (any mode) */
4962c51a
MS		 6488 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
6489 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
6490 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW		 6491 OP_EXP, /* arbitrary expression */
6492 OP_EXPi, /* same, with optional immediate prefix */
6493 OP_EXPr, /* same, with optional relocation suffix */
b6895b4f 6494 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c19d1205
ZW		 6495
6496 OP_CPSF, /* CPS flags */
6497 OP_ENDI, /* Endianness specifier */
d2cd1205
JB		 6498 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
6499 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 6500 OP_COND, /* conditional code */
92e90b6e 6501 OP_TB, /* Table branch. */
c19d1205 6502
037e8744
JB		 6503 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
6504
c19d1205
ZW		 6505 OP_RRnpc_I0, /* ARM register or literal 0 */
6506 OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
6507 OP_RR_EXi, /* ARM register or expression with imm prefix */
6508 OP_RF_IF, /* FPA register or immediate */
6509 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 6510 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW		 6511
6512 /* Optional operands. */
6513 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
6514 OP_oI31b, /* 0 .. 31 */
5287ad62 6515 OP_oI32b, /* 1 .. 32 */
5f1af56b 6516 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW		 6517 OP_oIffffb, /* 0 .. 65535 */
6518 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
6519
6520 OP_oRR, /* ARM register */
6521 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 6522 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 6523 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB		 6524 OP_oRND, /* Optional Neon double precision register */
6525 OP_oRNQ, /* Optional Neon quad precision register */
6526 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 6527 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
c19d1205
ZW		 6528 OP_oSHll, /* LSL immediate */
6529 OP_oSHar, /* ASR immediate */
6530 OP_oSHllar, /* LSL or ASR immediate */
6531 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 6532 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 6533
5be8be5d
DG		 6534 /* Some pre-defined mixed (ARM/THUMB) operands. */
6535 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
6536 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
6537 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
6538
c19d1205
ZW		 6539 OP_FIRST_OPTIONAL = OP_oI7b
6540};
a737bd4d 6541
c19d1205
ZW		 6542/* Generic instruction operand parser. This does no encoding and no
6543 semantic validation; it merely squirrels values away in the inst
6544 structure. Returns SUCCESS or FAIL depending on whether the
6545 specified grammar matched. */
6546static int
5be8be5d 6547parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 6548{
5be8be5d 6549 unsigned const int *upat = pattern;
c19d1205
ZW		 6550 char *backtrack_pos = 0;
6551 const char *backtrack_error = 0;
99aad254 6552 int i, val = 0, backtrack_index = 0;
5287ad62 6553 enum arm_reg_type rtype;
4962c51a 6554 parse_operand_result result;
5be8be5d 6555 unsigned int op_parse_code;
c19d1205 6556
e07e6e58
NC		 6557#define po_char_or_fail(chr) \
6558 do \
6559 { \
6560 if (skip_past_char (&str, chr) == FAIL) \
477330fc 6561 goto bad_args; \
e07e6e58
NC		 6562 } \
6563 while (0)
c19d1205 6564
e07e6e58
NC		 6565#define po_reg_or_fail(regtype) \
6566 do \
dcbf9037 6567 { \
e07e6e58 6568 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 6569 & inst.operands[i].vectype); \
e07e6e58 6570 if (val == FAIL) \
477330fc
RM		 6571 { \
6572 first_error (_(reg_expected_msgs[regtype])); \
6573 goto failure; \
6574 } \
e07e6e58
NC		 6575 inst.operands[i].reg = val; \
6576 inst.operands[i].isreg = 1; \
6577 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6578 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6579 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM		 6580 || rtype == REG_TYPE_VFD \
6581 || rtype == REG_TYPE_NQ); \
dcbf9037 6582 } \
e07e6e58
NC		 6583 while (0)
6584
6585#define po_reg_or_goto(regtype, label) \
6586 do \
6587 { \
6588 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6589 & inst.operands[i].vectype); \
6590 if (val == FAIL) \
6591 goto label; \
dcbf9037 6592 \
e07e6e58
NC		 6593 inst.operands[i].reg = val; \
6594 inst.operands[i].isreg = 1; \
6595 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6596 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6597 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 6598 || rtype == REG_TYPE_VFD \
e07e6e58
NC		 6599 || rtype == REG_TYPE_NQ); \
6600 } \
6601 while (0)
6602
6603#define po_imm_or_fail(min, max, popt) \
6604 do \
6605 { \
6606 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6607 goto failure; \
6608 inst.operands[i].imm = val; \
6609 } \
6610 while (0)
6611
6612#define po_scalar_or_goto(elsz, label) \
6613 do \
6614 { \
6615 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6616 if (val == FAIL) \
6617 goto label; \
6618 inst.operands[i].reg = val; \
6619 inst.operands[i].isscalar = 1; \
6620 } \
6621 while (0)
6622
6623#define po_misc_or_fail(expr) \
6624 do \
6625 { \
6626 if (expr) \
6627 goto failure; \
6628 } \
6629 while (0)
6630
6631#define po_misc_or_fail_no_backtrack(expr) \
6632 do \
6633 { \
6634 result = expr; \
6635 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6636 backtrack_pos = 0; \
6637 if (result != PARSE_OPERAND_SUCCESS) \
6638 goto failure; \
6639 } \
6640 while (0)
4962c51a 6641
52e7f43d
RE		 6642#define po_barrier_or_imm(str) \
6643 do \
6644 { \
6645 val = parse_barrier (&str); \
ccb84d65
JB		 6646 if (val == FAIL && ! ISALPHA (*str)) \
6647 goto immediate; \
6648 if (val == FAIL \
6649 /* ISB can only take SY as an option. */ \
6650 || ((inst.instruction & 0xf0) == 0x60 \
6651 && val != 0xf)) \
52e7f43d 6652 { \
ccb84d65
JB		 6653 inst.error = _("invalid barrier type"); \
6654 backtrack_pos = 0; \
6655 goto failure; \
52e7f43d
RE		 6656 } \
6657 } \
6658 while (0)
6659
c19d1205
ZW		 6660 skip_whitespace (str);
6661
6662 for (i = 0; upat[i] != OP_stop; i++)
6663 {
5be8be5d
DG		 6664 op_parse_code = upat[i];
6665 if (op_parse_code >= 1<<16)
6666 op_parse_code = thumb ? (op_parse_code >> 16)
6667 : (op_parse_code & ((1<<16)-1));
6668
6669 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW		 6670 {
6671 /* Remember where we are in case we need to backtrack. */
9c2799c2 6672 gas_assert (!backtrack_pos);
c19d1205
ZW		 6673 backtrack_pos = str;
6674 backtrack_error = inst.error;
6675 backtrack_index = i;
6676 }
6677
b6702015 6678 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW		 6679 po_char_or_fail (',');
6680
5be8be5d 6681 switch (op_parse_code)
c19d1205
ZW		 6682 {
6683 /* Registers */
6684 case OP_oRRnpc:
5be8be5d 6685 case OP_oRRnpcsp:
c19d1205 6686 case OP_RRnpc:
5be8be5d 6687 case OP_RRnpcsp:
c19d1205
ZW		 6688 case OP_oRR:
6689 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
6690 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
6691 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
6692 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
6693 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
6694 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 6695 case OP_oRND:
5287ad62 6696 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB		 6697 case OP_RVC:
6698 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
6699 break;
6700 /* Also accept generic coprocessor regs for unknown registers. */
6701 coproc_reg:
6702 po_reg_or_fail (REG_TYPE_CN);
6703 break;
c19d1205
ZW		 6704 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
6705 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
6706 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
6707 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
6708 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
6709 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
6710 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
6711 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
6712 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
6713 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 6714 case OP_oRNQ:
5287ad62 6715 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
477330fc 6716 case OP_oRNDQ:
5287ad62 6717 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
477330fc
RM		 6718 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
6719 case OP_oRNSDQ:
6720 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
6721
6722 /* Neon scalar. Using an element size of 8 means that some invalid
6723 scalars are accepted here, so deal with those in later code. */
6724 case OP_RNSC: po_scalar_or_goto (8, failure); break;
6725
6726 case OP_RNDQ_I0:
6727 {
6728 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
6729 break;
6730 try_imm0:
6731 po_imm_or_fail (0, 0, TRUE);
6732 }
6733 break;
6734
6735 case OP_RVSD_I0:
6736 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
6737 break;
6738
aacf0b33
KT		 6739 case OP_RSVD_FI0:
6740 {
6741 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
6742 break;
6743 try_ifimm0:
6744 if (parse_ifimm_zero (&str))
6745 inst.operands[i].imm = 0;
6746 else
6747 {
6748 inst.error
6749 = _("only floating point zero is allowed as immediate value");
6750 goto failure;
6751 }
6752 }
6753 break;
6754
477330fc
RM		 6755 case OP_RR_RNSC:
6756 {
6757 po_scalar_or_goto (8, try_rr);
6758 break;
6759 try_rr:
6760 po_reg_or_fail (REG_TYPE_RN);
6761 }
6762 break;
6763
6764 case OP_RNSDQ_RNSC:
6765 {
6766 po_scalar_or_goto (8, try_nsdq);
6767 break;
6768 try_nsdq:
6769 po_reg_or_fail (REG_TYPE_NSDQ);
6770 }
6771 break;
6772
6773 case OP_RNDQ_RNSC:
6774 {
6775 po_scalar_or_goto (8, try_ndq);
6776 break;
6777 try_ndq:
6778 po_reg_or_fail (REG_TYPE_NDQ);
6779 }
6780 break;
6781
6782 case OP_RND_RNSC:
6783 {
6784 po_scalar_or_goto (8, try_vfd);
6785 break;
6786 try_vfd:
6787 po_reg_or_fail (REG_TYPE_VFD);
6788 }
6789 break;
6790
6791 case OP_VMOV:
6792 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6793 not careful then bad things might happen. */
6794 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
6795 break;
6796
6797 case OP_RNDQ_Ibig:
6798 {
6799 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
6800 break;
6801 try_immbig:
6802 /* There's a possibility of getting a 64-bit immediate here, so
6803 we need special handling. */
8335d6aa
JW		 6804 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
6805 == FAIL)
477330fc
RM		 6806 {
6807 inst.error = _("immediate value is out of range");
6808 goto failure;
6809 }
6810 }
6811 break;
6812
6813 case OP_RNDQ_I63b:
6814 {
6815 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
6816 break;
6817 try_shimm:
6818 po_imm_or_fail (0, 63, TRUE);
6819 }
6820 break;
c19d1205
ZW		 6821
6822 case OP_RRnpcb:
6823 po_char_or_fail ('[');
6824 po_reg_or_fail (REG_TYPE_RN);
6825 po_char_or_fail (']');
6826 break;
a737bd4d 6827
55881a11 6828 case OP_RRnpctw:
c19d1205 6829 case OP_RRw:
b6702015 6830 case OP_oRRw:
c19d1205
ZW		 6831 po_reg_or_fail (REG_TYPE_RN);
6832 if (skip_past_char (&str, '!') == SUCCESS)
6833 inst.operands[i].writeback = 1;
6834 break;
6835
6836 /* Immediates */
6837 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
6838 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
6839 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 6840 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW		 6841 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
6842 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 6843 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
c19d1205 6844 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM		 6845 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
6846 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
6847 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 6848 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW		 6849
6850 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
6851 case OP_oI7b:
6852 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
6853 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
6854 case OP_oI31b:
6855 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM		 6856 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
6857 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW		 6858 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
6859
6860 /* Immediate variants */
6861 case OP_oI255c:
6862 po_char_or_fail ('{');
6863 po_imm_or_fail (0, 255, TRUE);
6864 po_char_or_fail ('}');
6865 break;
6866
6867 case OP_I31w:
6868 /* The expression parser chokes on a trailing !, so we have
6869 to find it first and zap it. */
6870 {
6871 char *s = str;
6872 while (*s && *s != ',')
6873 s++;
6874 if (s[-1] == '!')
6875 {
6876 s[-1] = '\0';
6877 inst.operands[i].writeback = 1;
6878 }
6879 po_imm_or_fail (0, 31, TRUE);
6880 if (str == s - 1)
6881 str = s;
6882 }
6883 break;
6884
6885 /* Expressions */
6886 case OP_EXPi: EXPi:
6887 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6888 GE_OPT_PREFIX));
6889 break;
6890
6891 case OP_EXP:
6892 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6893 GE_NO_PREFIX));
6894 break;
6895
6896 case OP_EXPr: EXPr:
6897 po_misc_or_fail (my_get_expression (&inst.reloc.exp, &str,
6898 GE_NO_PREFIX));
6899 if (inst.reloc.exp.X_op == O_symbol)
a737bd4d 6900 {
c19d1205
ZW		 6901 val = parse_reloc (&str);
6902 if (val == -1)
6903 {
6904 inst.error = _("unrecognized relocation suffix");
6905 goto failure;
6906 }
6907 else if (val != BFD_RELOC_UNUSED)
6908 {
6909 inst.operands[i].imm = val;
6910 inst.operands[i].hasreloc = 1;
6911 }
a737bd4d 6912 }
c19d1205 6913 break;
a737bd4d 6914
b6895b4f
PB		 6915 /* Operand for MOVW or MOVT. */
6916 case OP_HALF:
6917 po_misc_or_fail (parse_half (&str));
6918 break;
6919
e07e6e58 6920 /* Register or expression. */
c19d1205
ZW		 6921 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
6922 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 6923
e07e6e58 6924 /* Register or immediate. */
c19d1205
ZW		 6925 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
6926 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 6927
c19d1205
ZW		 6928 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
6929 IF:
6930 if (!is_immediate_prefix (*str))
6931 goto bad_args;
6932 str++;
6933 val = parse_fpa_immediate (&str);
6934 if (val == FAIL)
6935 goto failure;
6936 /* FPA immediates are encoded as registers 8-15.
6937 parse_fpa_immediate has already applied the offset. */
6938 inst.operands[i].reg = val;
6939 inst.operands[i].isreg = 1;
6940 break;
09d92015 6941
2d447fca
JM		 6942 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
6943 I32z: po_imm_or_fail (0, 32, FALSE); break;
6944
e07e6e58 6945 /* Two kinds of register. */
c19d1205
ZW		 6946 case OP_RIWR_RIWC:
6947 {
6948 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM		 6949 if (!rege
6950 || (rege->type != REG_TYPE_MMXWR
6951 && rege->type != REG_TYPE_MMXWC
6952 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW		 6953 {
6954 inst.error = _("iWMMXt data or control register expected");
6955 goto failure;
6956 }
6957 inst.operands[i].reg = rege->number;
6958 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
6959 }
6960 break;
09d92015 6961
41adaa5c
JM		 6962 case OP_RIWC_RIWG:
6963 {
6964 struct reg_entry *rege = arm_reg_parse_multi (&str);
6965 if (!rege
6966 || (rege->type != REG_TYPE_MMXWC
6967 && rege->type != REG_TYPE_MMXWCG))
6968 {
6969 inst.error = _("iWMMXt control register expected");
6970 goto failure;
6971 }
6972 inst.operands[i].reg = rege->number;
6973 inst.operands[i].isreg = 1;
6974 }
6975 break;
6976
c19d1205
ZW		 6977 /* Misc */
6978 case OP_CPSF: val = parse_cps_flags (&str); break;
6979 case OP_ENDI: val = parse_endian_specifier (&str); break;
6980 case OP_oROR: val = parse_ror (&str); break;
c19d1205 6981 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE		 6982 case OP_oBARRIER_I15:
6983 po_barrier_or_imm (str); break;
6984 immediate:
6985 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 6986 goto failure;
52e7f43d 6987 break;
c19d1205 6988
fa94de6b 6989 case OP_wPSR:
d2cd1205 6990 case OP_rPSR:
90ec0d68
MGD		 6991 po_reg_or_goto (REG_TYPE_RNB, try_psr);
6992 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
6993 {
6994 inst.error = _("Banked registers are not available with this "
6995 "architecture.");
6996 goto failure;
6997 }
6998 break;
d2cd1205
JB		 6999 try_psr:
7000 val = parse_psr (&str, op_parse_code == OP_wPSR);
7001 break;
037e8744 7002
477330fc
RM		 7003 case OP_APSR_RR:
7004 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7005 break;
7006 try_apsr:
7007 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7008 instruction). */
7009 if (strncasecmp (str, "APSR_", 5) == 0)
7010 {
7011 unsigned found = 0;
7012 str += 5;
7013 while (found < 15)
7014 switch (*str++)
7015 {
7016 case 'c': found = (found & 1) ? 16 : found | 1; break;
7017 case 'n': found = (found & 2) ? 16 : found | 2; break;
7018 case 'z': found = (found & 4) ? 16 : found | 4; break;
7019 case 'v': found = (found & 8) ? 16 : found | 8; break;
7020 default: found = 16;
7021 }
7022 if (found != 15)
7023 goto failure;
7024 inst.operands[i].isvec = 1;
f7c21dc7
NC		 7025 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7026 inst.operands[i].reg = REG_PC;
477330fc
RM		 7027 }
7028 else
7029 goto failure;
7030 break;
037e8744 7031
92e90b6e
PB		 7032 case OP_TB:
7033 po_misc_or_fail (parse_tb (&str));
7034 break;
7035
e07e6e58 7036 /* Register lists. */
c19d1205
ZW		 7037 case OP_REGLST:
7038 val = parse_reg_list (&str);
7039 if (*str == '^')
7040 {
5e0d7f77 7041 inst.operands[i].writeback = 1;
c19d1205
ZW		 7042 str++;
7043 }
7044 break;
09d92015 7045
c19d1205 7046 case OP_VRSLST:
5287ad62 7047 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S);
c19d1205 7048 break;
09d92015 7049
c19d1205 7050 case OP_VRDLST:
5287ad62 7051 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D);
c19d1205 7052 break;
a737bd4d 7053
477330fc
RM		 7054 case OP_VRSDLST:
7055 /* Allow Q registers too. */
7056 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7057 REGLIST_NEON_D);
7058 if (val == FAIL)
7059 {
7060 inst.error = NULL;
7061 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7062 REGLIST_VFP_S);
7063 inst.operands[i].issingle = 1;
7064 }
7065 break;
7066
7067 case OP_NRDLST:
7068 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7069 REGLIST_NEON_D);
7070 break;
5287ad62
JB		 7071
7072 case OP_NSTRLST:
477330fc
RM		 7073 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7074 &inst.operands[i].vectype);
7075 break;
5287ad62 7076
c19d1205
ZW		 7077 /* Addressing modes */
7078 case OP_ADDR:
7079 po_misc_or_fail (parse_address (&str, i));
7080 break;
09d92015 7081
4962c51a
MS		 7082 case OP_ADDRGLDR:
7083 po_misc_or_fail_no_backtrack (
477330fc 7084 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS		 7085 break;
7086
7087 case OP_ADDRGLDRS:
7088 po_misc_or_fail_no_backtrack (
477330fc 7089 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS		 7090 break;
7091
7092 case OP_ADDRGLDC:
7093 po_misc_or_fail_no_backtrack (
477330fc 7094 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS		 7095 break;
7096
c19d1205
ZW		 7097 case OP_SH:
7098 po_misc_or_fail (parse_shifter_operand (&str, i));
7099 break;
09d92015 7100
4962c51a
MS		 7101 case OP_SHG:
7102 po_misc_or_fail_no_backtrack (
477330fc 7103 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS		 7104 break;
7105
c19d1205
ZW		 7106 case OP_oSHll:
7107 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7108 break;
09d92015 7109
c19d1205
ZW		 7110 case OP_oSHar:
7111 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7112 break;
09d92015 7113
c19d1205
ZW		 7114 case OP_oSHllar:
7115 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7116 break;
09d92015 7117
c19d1205 7118 default:
5be8be5d 7119 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 7120 }
09d92015 7121
c19d1205
ZW		 7122 /* Various value-based sanity checks and shared operations. We
7123 do not signal immediate failures for the register constraints;
7124 this allows a syntax error to take precedence. */
5be8be5d 7125 switch (op_parse_code)
c19d1205
ZW		 7126 {
7127 case OP_oRRnpc:
7128 case OP_RRnpc:
7129 case OP_RRnpcb:
7130 case OP_RRw:
b6702015 7131 case OP_oRRw:
c19d1205
ZW		 7132 case OP_RRnpc_I0:
7133 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7134 inst.error = BAD_PC;
7135 break;
09d92015 7136
5be8be5d
DG		 7137 case OP_oRRnpcsp:
7138 case OP_RRnpcsp:
7139 if (inst.operands[i].isreg)
7140 {
7141 if (inst.operands[i].reg == REG_PC)
7142 inst.error = BAD_PC;
7143 else if (inst.operands[i].reg == REG_SP)
7144 inst.error = BAD_SP;
7145 }
7146 break;
7147
55881a11 7148 case OP_RRnpctw:
fa94de6b
RM		 7149 if (inst.operands[i].isreg
7150 && inst.operands[i].reg == REG_PC
55881a11
MGD		 7151 && (inst.operands[i].writeback || thumb))
7152 inst.error = BAD_PC;
7153 break;
7154
c19d1205
ZW		 7155 case OP_CPSF:
7156 case OP_ENDI:
7157 case OP_oROR:
d2cd1205
JB		 7158 case OP_wPSR:
7159 case OP_rPSR:
c19d1205 7160 case OP_COND:
52e7f43d 7161 case OP_oBARRIER_I15:
c19d1205
ZW		 7162 case OP_REGLST:
7163 case OP_VRSLST:
7164 case OP_VRDLST:
477330fc
RM		 7165 case OP_VRSDLST:
7166 case OP_NRDLST:
7167 case OP_NSTRLST:
c19d1205
ZW		 7168 if (val == FAIL)
7169 goto failure;
7170 inst.operands[i].imm = val;
7171 break;
a737bd4d 7172
c19d1205
ZW		 7173 default:
7174 break;
7175 }
09d92015 7176
c19d1205
ZW		 7177 /* If we get here, this operand was successfully parsed. */
7178 inst.operands[i].present = 1;
7179 continue;
09d92015 7180
c19d1205 7181 bad_args:
09d92015 7182 inst.error = BAD_ARGS;
c19d1205
ZW		 7183
7184 failure:
7185 if (!backtrack_pos)
d252fdde
PB		 7186 {
7187 /* The parse routine should already have set inst.error, but set a
5f4273c7 7188 default here just in case. */
d252fdde
PB		 7189 if (!inst.error)
7190 inst.error = _("syntax error");
7191 return FAIL;
7192 }
c19d1205
ZW		 7193
7194 /* Do not backtrack over a trailing optional argument that
7195 absorbed some text. We will only fail again, with the
7196 'garbage following instruction' error message, which is
7197 probably less helpful than the current one. */
7198 if (backtrack_index == i && backtrack_pos != str
7199 && upat[i+1] == OP_stop)
d252fdde
PB		 7200 {
7201 if (!inst.error)
7202 inst.error = _("syntax error");
7203 return FAIL;
7204 }
c19d1205
ZW		 7205
7206 /* Try again, skipping the optional argument at backtrack_pos. */
7207 str = backtrack_pos;
7208 inst.error = backtrack_error;
7209 inst.operands[backtrack_index].present = 0;
7210 i = backtrack_index;
7211 backtrack_pos = 0;
09d92015 7212 }
09d92015 7213
c19d1205
ZW		 7214 /* Check that we have parsed all the arguments. */
7215 if (*str != '\0' && !inst.error)
7216 inst.error = _("garbage following instruction");
09d92015 7217
c19d1205 7218 return inst.error ? FAIL : SUCCESS;
09d92015
MM		 7219}
7220
c19d1205
ZW		 7221#undef po_char_or_fail
7222#undef po_reg_or_fail
7223#undef po_reg_or_goto
7224#undef po_imm_or_fail
5287ad62 7225#undef po_scalar_or_fail
52e7f43d 7226#undef po_barrier_or_imm
e07e6e58 7227
c19d1205 7228/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC		 7229#define constraint(expr, err) \
7230 do \
c19d1205 7231 { \
e07e6e58
NC		 7232 if (expr) \
7233 { \
7234 inst.error = err; \
7235 return; \
7236 } \
c19d1205 7237 } \
e07e6e58 7238 while (0)
c19d1205 7239
fdfde340
JM		 7240/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7241 instructions are unpredictable if these registers are used. This
7242 is the BadReg predicate in ARM's Thumb-2 documentation. */
7243#define reject_bad_reg(reg) \
7244 do \
7245 if (reg == REG_SP || reg == REG_PC) \
7246 { \
7247 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7248 return; \
7249 } \
7250 while (0)
7251
94206790
MM		 7252/* If REG is R13 (the stack pointer), warn that its use is
7253 deprecated. */
7254#define warn_deprecated_sp(reg) \
7255 do \
7256 if (warn_on_deprecated && reg == REG_SP) \
5c3696f8 7257 as_tsktsk (_("use of r13 is deprecated")); \
94206790
MM		 7258 while (0)
7259
c19d1205
ZW		 7260/* Functions for operand encoding. ARM, then Thumb. */
7261
d840c081 7262#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
c19d1205
ZW		 7263
7264/* If VAL can be encoded in the immediate field of an ARM instruction,
7265 return the encoded form. Otherwise, return FAIL. */
7266
7267static unsigned int
7268encode_arm_immediate (unsigned int val)
09d92015 7269{
c19d1205
ZW		 7270 unsigned int a, i;
7271
7272 for (i = 0; i < 32; i += 2)
7273 if ((a = rotate_left (val, i)) <= 0xff)
7274 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
7275
7276 return FAIL;
09d92015
MM		 7277}
7278
c19d1205
ZW		 7279/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7280 return the encoded form. Otherwise, return FAIL. */
7281static unsigned int
7282encode_thumb32_immediate (unsigned int val)
09d92015 7283{
c19d1205 7284 unsigned int a, i;
09d92015 7285
9c3c69f2 7286 if (val <= 0xff)
c19d1205 7287 return val;
a737bd4d 7288
9c3c69f2 7289 for (i = 1; i <= 24; i++)
09d92015 7290 {
9c3c69f2
PB		 7291 a = val >> i;
7292 if ((val & ~(0xff << i)) == 0)
7293 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 7294 }
a737bd4d 7295
c19d1205
ZW		 7296 a = val & 0xff;
7297 if (val == ((a << 16) | a))
7298 return 0x100 | a;
7299 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
7300 return 0x300 | a;
09d92015 7301
c19d1205
ZW		 7302 a = val & 0xff00;
7303 if (val == ((a << 16) | a))
7304 return 0x200 | (a >> 8);
a737bd4d 7305
c19d1205 7306 return FAIL;
09d92015 7307}
5287ad62 7308/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM		 7309
7310static void
5287ad62
JB		 7311encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
7312{
7313 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
7314 && reg > 15)
7315 {
b1cc4aeb 7316 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 7317 {
7318 if (thumb_mode)
7319 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
7320 fpu_vfp_ext_d32);
7321 else
7322 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
7323 fpu_vfp_ext_d32);
7324 }
5287ad62 7325 else
477330fc
RM		 7326 {
7327 first_error (_("D register out of range for selected VFP version"));
7328 return;
7329 }
5287ad62
JB		 7330 }
7331
c19d1205 7332 switch (pos)
09d92015 7333 {
c19d1205
ZW		 7334 case VFP_REG_Sd:
7335 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
7336 break;
7337
7338 case VFP_REG_Sn:
7339 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
7340 break;
7341
7342 case VFP_REG_Sm:
7343 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
7344 break;
7345
5287ad62
JB		 7346 case VFP_REG_Dd:
7347 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
7348 break;
5f4273c7 7349
5287ad62
JB		 7350 case VFP_REG_Dn:
7351 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
7352 break;
5f4273c7 7353
5287ad62
JB		 7354 case VFP_REG_Dm:
7355 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
7356 break;
7357
c19d1205
ZW		 7358 default:
7359 abort ();
09d92015 7360 }
09d92015
MM		 7361}
7362
c19d1205 7363/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 7364 if any, is handled by md_apply_fix. */
09d92015 7365static void
c19d1205 7366encode_arm_shift (int i)
09d92015 7367{
c19d1205
ZW		 7368 if (inst.operands[i].shift_kind == SHIFT_RRX)
7369 inst.instruction |= SHIFT_ROR << 5;
7370 else
09d92015 7371 {
c19d1205
ZW		 7372 inst.instruction |= inst.operands[i].shift_kind << 5;
7373 if (inst.operands[i].immisreg)
7374 {
7375 inst.instruction |= SHIFT_BY_REG;
7376 inst.instruction |= inst.operands[i].imm << 8;
7377 }
7378 else
7379 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 7380 }
c19d1205 7381}
09d92015 7382
c19d1205
ZW		 7383static void
7384encode_arm_shifter_operand (int i)
7385{
7386 if (inst.operands[i].isreg)
09d92015 7387 {
c19d1205
ZW		 7388 inst.instruction |= inst.operands[i].reg;
7389 encode_arm_shift (i);
09d92015 7390 }
c19d1205 7391 else
a415b1cd
JB		 7392 {
7393 inst.instruction |= INST_IMMEDIATE;
7394 if (inst.reloc.type != BFD_RELOC_ARM_IMMEDIATE)
7395 inst.instruction |= inst.operands[i].imm;
7396 }
09d92015
MM		 7397}
7398
c19d1205 7399/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 7400static void
c19d1205 7401encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 7402{
2b2f5df9
NC		 7403 /* PR 14260:
7404 Generate an error if the operand is not a register. */
7405 constraint (!inst.operands[i].isreg,
7406 _("Instruction does not support =N addresses"));
7407
c19d1205 7408 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 7409
c19d1205 7410 if (inst.operands[i].preind)
09d92015 7411 {
c19d1205
ZW		 7412 if (is_t)
7413 {
7414 inst.error = _("instruction does not accept preindexed addressing");
7415 return;
7416 }
7417 inst.instruction |= PRE_INDEX;
7418 if (inst.operands[i].writeback)
7419 inst.instruction |= WRITE_BACK;
09d92015 7420
c19d1205
ZW		 7421 }
7422 else if (inst.operands[i].postind)
7423 {
9c2799c2 7424 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 7425 if (is_t)
7426 inst.instruction |= WRITE_BACK;
7427 }
7428 else /* unindexed - only for coprocessor */
09d92015 7429 {
c19d1205 7430 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM		 7431 return;
7432 }
7433
c19d1205
ZW		 7434 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
7435 && (((inst.instruction & 0x000f0000) >> 16)
7436 == ((inst.instruction & 0x0000f000) >> 12)))
7437 as_warn ((inst.instruction & LOAD_BIT)
7438 ? _("destination register same as write-back base")
7439 : _("source register same as write-back base"));
09d92015
MM		 7440}
7441
c19d1205
ZW		 7442/* inst.operands[i] was set up by parse_address. Encode it into an
7443 ARM-format mode 2 load or store instruction. If is_t is true,
7444 reject forms that cannot be used with a T instruction (i.e. not
7445 post-indexed). */
a737bd4d 7446static void
c19d1205 7447encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 7448{
5be8be5d
DG		 7449 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
7450
c19d1205 7451 encode_arm_addr_mode_common (i, is_t);
a737bd4d 7452
c19d1205 7453 if (inst.operands[i].immisreg)
09d92015 7454 {
5be8be5d
DG		 7455 constraint ((inst.operands[i].imm == REG_PC
7456 || (is_pc && inst.operands[i].writeback)),
7457 BAD_PC_ADDRESSING);
c19d1205
ZW		 7458 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
7459 inst.instruction |= inst.operands[i].imm;
7460 if (!inst.operands[i].negative)
7461 inst.instruction |= INDEX_UP;
7462 if (inst.operands[i].shifted)
7463 {
7464 if (inst.operands[i].shift_kind == SHIFT_RRX)
7465 inst.instruction |= SHIFT_ROR << 5;
7466 else
7467 {
7468 inst.instruction |= inst.operands[i].shift_kind << 5;
7469 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
7470 }
7471 }
09d92015 7472 }
c19d1205 7473 else /* immediate offset in inst.reloc */
09d92015 7474 {
5be8be5d
DG		 7475 if (is_pc && !inst.reloc.pc_rel)
7476 {
7477 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ		 7478
7479 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7480 cannot use PC in addressing.
7481 PC cannot be used in writeback addressing, either. */
7482 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 7483 BAD_PC_ADDRESSING);
23a10334 7484
dc5ec521 7485 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ		 7486 if (warn_on_deprecated
7487 && !is_load
7488 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
5c3696f8 7489 as_tsktsk (_("use of PC in this instruction is deprecated"));
5be8be5d
DG		 7490 }
7491
c19d1205 7492 if (inst.reloc.type == BFD_RELOC_UNUSED)
26d97720
NS		 7493 {
7494 /* Prefer + for zero encoded value. */
7495 if (!inst.operands[i].negative)
7496 inst.instruction |= INDEX_UP;
7497 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM;
7498 }
09d92015 7499 }
09d92015
MM		 7500}
7501
c19d1205
ZW		 7502/* inst.operands[i] was set up by parse_address. Encode it into an
7503 ARM-format mode 3 load or store instruction. Reject forms that
7504 cannot be used with such instructions. If is_t is true, reject
7505 forms that cannot be used with a T instruction (i.e. not
7506 post-indexed). */
7507static void
7508encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 7509{
c19d1205 7510 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 7511 {
c19d1205
ZW		 7512 inst.error = _("instruction does not accept scaled register index");
7513 return;
09d92015 7514 }
a737bd4d 7515
c19d1205 7516 encode_arm_addr_mode_common (i, is_t);
a737bd4d 7517
c19d1205
ZW		 7518 if (inst.operands[i].immisreg)
7519 {
5be8be5d 7520 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 7521 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 7522 BAD_PC_ADDRESSING);
eb9f3f00
JB		 7523 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
7524 BAD_PC_WRITEBACK);
c19d1205
ZW		 7525 inst.instruction |= inst.operands[i].imm;
7526 if (!inst.operands[i].negative)
7527 inst.instruction |= INDEX_UP;
7528 }
7529 else /* immediate offset in inst.reloc */
7530 {
5be8be5d
DG		 7531 constraint ((inst.operands[i].reg == REG_PC && !inst.reloc.pc_rel
7532 && inst.operands[i].writeback),
7533 BAD_PC_WRITEBACK);
c19d1205
ZW		 7534 inst.instruction |= HWOFFSET_IMM;
7535 if (inst.reloc.type == BFD_RELOC_UNUSED)
26d97720
NS		 7536 {
7537 /* Prefer + for zero encoded value. */
7538 if (!inst.operands[i].negative)
7539 inst.instruction |= INDEX_UP;
7540
7541 inst.reloc.type = BFD_RELOC_ARM_OFFSET_IMM8;
7542 }
c19d1205 7543 }
a737bd4d
NC		 7544}
7545
8335d6aa
JW		 7546/* Write immediate bits [7:0] to the following locations:
7547
7548 |28/24|23 19|18 16|15 4|3 0|
7549 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7550
7551 This function is used by VMOV/VMVN/VORR/VBIC. */
7552
7553static void
7554neon_write_immbits (unsigned immbits)
7555{
7556 inst.instruction |= immbits & 0xf;
7557 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
7558 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
7559}
7560
7561/* Invert low-order SIZE bits of XHI:XLO. */
7562
7563static void
7564neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
7565{
7566 unsigned immlo = xlo ? *xlo : 0;
7567 unsigned immhi = xhi ? *xhi : 0;
7568
7569 switch (size)
7570 {
7571 case 8:
7572 immlo = (~immlo) & 0xff;
7573 break;
7574
7575 case 16:
7576 immlo = (~immlo) & 0xffff;
7577 break;
7578
7579 case 64:
7580 immhi = (~immhi) & 0xffffffff;
7581 /* fall through. */
7582
7583 case 32:
7584 immlo = (~immlo) & 0xffffffff;
7585 break;
7586
7587 default:
7588 abort ();
7589 }
7590
7591 if (xlo)
7592 *xlo = immlo;
7593
7594 if (xhi)
7595 *xhi = immhi;
7596}
7597
7598/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7599 A, B, C, D. */
09d92015 7600
c19d1205 7601static int
8335d6aa 7602neon_bits_same_in_bytes (unsigned imm)
09d92015 7603{
8335d6aa
JW		 7604 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
7605 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
7606 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
7607 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
7608}
a737bd4d 7609
8335d6aa 7610/* For immediate of above form, return 0bABCD. */
09d92015 7611
8335d6aa
JW		 7612static unsigned
7613neon_squash_bits (unsigned imm)
7614{
7615 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
7616 | ((imm & 0x01000000) >> 21);
7617}
7618
7619/* Compress quarter-float representation to 0b...000 abcdefgh. */
7620
7621static unsigned
7622neon_qfloat_bits (unsigned imm)
7623{
7624 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
7625}
7626
7627/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7628 the instruction. *OP is passed as the initial value of the op field, and
7629 may be set to a different value depending on the constant (i.e.
7630 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7631 MVN). If the immediate looks like a repeated pattern then also
7632 try smaller element sizes. */
7633
7634static int
7635neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
7636 unsigned *immbits, int *op, int size,
7637 enum neon_el_type type)
7638{
7639 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7640 float. */
7641 if (type == NT_float && !float_p)
7642 return FAIL;
7643
7644 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
09d92015 7645 {
8335d6aa
JW		 7646 if (size != 32 || *op == 1)
7647 return FAIL;
7648 *immbits = neon_qfloat_bits (immlo);
7649 return 0xf;
7650 }
7651
7652 if (size == 64)
7653 {
7654 if (neon_bits_same_in_bytes (immhi)
7655 && neon_bits_same_in_bytes (immlo))
c19d1205 7656 {
8335d6aa
JW		 7657 if (*op == 1)
7658 return FAIL;
7659 *immbits = (neon_squash_bits (immhi) << 4)
7660 | neon_squash_bits (immlo);
7661 *op = 1;
7662 return 0xe;
c19d1205 7663 }
a737bd4d 7664
8335d6aa
JW		 7665 if (immhi != immlo)
7666 return FAIL;
7667 }
a737bd4d 7668
8335d6aa 7669 if (size >= 32)
09d92015 7670 {
8335d6aa 7671 if (immlo == (immlo & 0x000000ff))
c19d1205 7672 {
8335d6aa
JW		 7673 *immbits = immlo;
7674 return 0x0;
c19d1205 7675 }
8335d6aa 7676 else if (immlo == (immlo & 0x0000ff00))
c19d1205 7677 {
8335d6aa
JW		 7678 *immbits = immlo >> 8;
7679 return 0x2;
c19d1205 7680 }
8335d6aa
JW		 7681 else if (immlo == (immlo & 0x00ff0000))
7682 {
7683 *immbits = immlo >> 16;
7684 return 0x4;
7685 }
7686 else if (immlo == (immlo & 0xff000000))
7687 {
7688 *immbits = immlo >> 24;
7689 return 0x6;
7690 }
7691 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
7692 {
7693 *immbits = (immlo >> 8) & 0xff;
7694 return 0xc;
7695 }
7696 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
7697 {
7698 *immbits = (immlo >> 16) & 0xff;
7699 return 0xd;
7700 }
7701
7702 if ((immlo & 0xffff) != (immlo >> 16))
7703 return FAIL;
7704 immlo &= 0xffff;
09d92015 7705 }
a737bd4d 7706
8335d6aa 7707 if (size >= 16)
4962c51a 7708 {
8335d6aa
JW		 7709 if (immlo == (immlo & 0x000000ff))
7710 {
7711 *immbits = immlo;
7712 return 0x8;
7713 }
7714 else if (immlo == (immlo & 0x0000ff00))
7715 {
7716 *immbits = immlo >> 8;
7717 return 0xa;
7718 }
7719
7720 if ((immlo & 0xff) != (immlo >> 8))
7721 return FAIL;
7722 immlo &= 0xff;
4962c51a
MS		 7723 }
7724
8335d6aa
JW		 7725 if (immlo == (immlo & 0x000000ff))
7726 {
7727 /* Don't allow MVN with 8-bit immediate. */
7728 if (*op == 1)
7729 return FAIL;
7730 *immbits = immlo;
7731 return 0xe;
7732 }
26d97720 7733
8335d6aa 7734 return FAIL;
c19d1205 7735}
a737bd4d 7736
8335d6aa
JW		 7737enum lit_type
7738{
7739 CONST_THUMB,
7740 CONST_ARM,
7741 CONST_VEC
7742};
7743
c19d1205
ZW		 7744/* inst.reloc.exp describes an "=expr" load pseudo-operation.
7745 Determine whether it can be performed with a move instruction; if
7746 it can, convert inst.instruction to that move instruction and
c921be7d
NC		 7747 return TRUE; if it can't, convert inst.instruction to a literal-pool
7748 load and return FALSE. If this is not a valid thing to do in the
7749 current context, set inst.error and return TRUE.
a737bd4d 7750
c19d1205
ZW		 7751 inst.operands[i] describes the destination register. */
7752
c921be7d 7753static bfd_boolean
8335d6aa 7754move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
c19d1205 7755{
53365c0d 7756 unsigned long tbit;
8335d6aa
JW		 7757 bfd_boolean thumb_p = (t == CONST_THUMB);
7758 bfd_boolean arm_p = (t == CONST_ARM);
7759 bfd_boolean vec64_p = (t == CONST_VEC) && !inst.operands[i].issingle;
53365c0d
PB		 7760
7761 if (thumb_p)
7762 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
7763 else
7764 tbit = LOAD_BIT;
7765
7766 if ((inst.instruction & tbit) == 0)
09d92015 7767 {
c19d1205 7768 inst.error = _("invalid pseudo operation");
c921be7d 7769 return TRUE;
09d92015 7770 }
8335d6aa
JW		 7771 if (inst.reloc.exp.X_op != O_constant
7772 && inst.reloc.exp.X_op != O_symbol
7773 && inst.reloc.exp.X_op != O_big)
09d92015
MM		 7774 {
7775 inst.error = _("constant expression expected");
c921be7d 7776 return TRUE;
09d92015 7777 }
8335d6aa
JW		 7778 if ((inst.reloc.exp.X_op == O_constant
7779 || inst.reloc.exp.X_op == O_big)
7780 && !inst.operands[i].issingle)
7781 {
7782 if (thumb_p && inst.reloc.exp.X_op == O_constant)
7783 {
7784 if (!unified_syntax && (inst.reloc.exp.X_add_number & ~0xFF) == 0)
7785 {
7786 /* This can be done with a mov(1) instruction. */
7787 inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
7788 inst.instruction |= inst.reloc.exp.X_add_number;
7789 return TRUE;
7790 }
7791 }
7792 else if (arm_p && inst.reloc.exp.X_op == O_constant)
7793 {
7794 int value = encode_arm_immediate (inst.reloc.exp.X_add_number);
7795 if (value != FAIL)
7796 {
7797 /* This can be done with a mov instruction. */
7798 inst.instruction &= LITERAL_MASK;
7799 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
7800 inst.instruction |= value & 0xfff;
7801 return TRUE;
7802 }
7803
7804 value = encode_arm_immediate (~inst.reloc.exp.X_add_number);
7805 if (value != FAIL)
7806 {
7807 /* This can be done with a mvn instruction. */
7808 inst.instruction &= LITERAL_MASK;
7809 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
7810 inst.instruction |= value & 0xfff;
7811 return TRUE;
7812 }
7813 }
7814 else if (vec64_p)
7815 {
7816 int op = 0;
7817 unsigned immbits = 0;
7818 unsigned immlo = inst.operands[1].imm;
7819 unsigned immhi = inst.operands[1].regisimm
7820 ? inst.operands[1].reg
7821 : inst.reloc.exp.X_unsigned
7822 ? 0
2569ceb0 7823 : ((bfd_int64_t)((int) immlo)) >> 32;
8335d6aa
JW		 7824 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
7825 &op, 64, NT_invtype);
7826
7827 if (cmode == FAIL)
7828 {
7829 neon_invert_size (&immlo, &immhi, 64);
7830 op = !op;
7831 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
7832 &op, 64, NT_invtype);
7833 }
7834 if (cmode != FAIL)
7835 {
7836 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
7837 | (1 << 23)
7838 | (cmode << 8)
7839 | (op << 5)
7840 | (1 << 4);
7841 /* Fill other bits in vmov encoding for both thumb and arm. */
7842 if (thumb_mode)
7843 inst.instruction |= (0x7 << 29) | (0xF << 24);
7844 else
7845 inst.instruction |= (0xF << 28) | (0x1 << 25);
7846 neon_write_immbits (immbits);
7847 return TRUE;
7848 }
7849 }
7850 }
7851
7852 if (add_to_lit_pool ((!inst.operands[i].isvec
7853 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
7854 return TRUE;
7855
7856 inst.operands[1].reg = REG_PC;
7857 inst.operands[1].isreg = 1;
7858 inst.operands[1].preind = 1;
7859 inst.reloc.pc_rel = 1;
7860 inst.reloc.type = (thumb_p
7861 ? BFD_RELOC_ARM_THUMB_OFFSET
7862 : (mode_3
7863 ? BFD_RELOC_ARM_HWLITERAL
7864 : BFD_RELOC_ARM_LITERAL));
7865 return FALSE;
7866}
7867
7868/* inst.operands[i] was set up by parse_address. Encode it into an
7869 ARM-format instruction. Reject all forms which cannot be encoded
7870 into a coprocessor load/store instruction. If wb_ok is false,
7871 reject use of writeback; if unind_ok is false, reject use of
7872 unindexed addressing. If reloc_override is not 0, use it instead
7873 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7874 (in which case it is preserved). */
7875
7876static int
7877encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
7878{
7879 if (!inst.operands[i].isreg)
7880 {
7881 gas_assert (inst.operands[0].isvec);
7882 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
7883 return SUCCESS;
7884 }
7885
7886 inst.instruction |= inst.operands[i].reg << 16;
7887
7888 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
7889
7890 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
7891 {
7892 gas_assert (!inst.operands[i].writeback);
7893 if (!unind_ok)
7894 {
7895 inst.error = _("instruction does not support unindexed addressing");
7896 return FAIL;
7897 }
7898 inst.instruction |= inst.operands[i].imm;
7899 inst.instruction |= INDEX_UP;
7900 return SUCCESS;
7901 }
7902
7903 if (inst.operands[i].preind)
7904 inst.instruction |= PRE_INDEX;
7905
7906 if (inst.operands[i].writeback)
09d92015 7907 {
8335d6aa 7908 if (inst.operands[i].reg == REG_PC)
c19d1205 7909 {
8335d6aa
JW		 7910 inst.error = _("pc may not be used with write-back");
7911 return FAIL;
c19d1205 7912 }
8335d6aa 7913 if (!wb_ok)
c19d1205 7914 {
8335d6aa
JW		 7915 inst.error = _("instruction does not support writeback");
7916 return FAIL;
c19d1205 7917 }
8335d6aa 7918 inst.instruction |= WRITE_BACK;
09d92015
MM		 7919 }
7920
8335d6aa
JW		 7921 if (reloc_override)
7922 inst.reloc.type = (bfd_reloc_code_real_type) reloc_override;
7923 else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
7924 || inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
7925 && inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
c19d1205 7926 {
8335d6aa
JW		 7927 if (thumb_mode)
7928 inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
7929 else
7930 inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205 7931 }
8335d6aa
JW		 7932
7933 /* Prefer + for zero encoded value. */
7934 if (!inst.operands[i].negative)
7935 inst.instruction |= INDEX_UP;
7936
7937 return SUCCESS;
09d92015
MM		 7938}
7939
5f4273c7 7940/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW		 7941 First some generics; their names are taken from the conventional
7942 bit positions for register arguments in ARM format instructions. */
09d92015 7943
a737bd4d 7944static void
c19d1205 7945do_noargs (void)
09d92015 7946{
c19d1205 7947}
a737bd4d 7948
c19d1205
ZW		 7949static void
7950do_rd (void)
7951{
7952 inst.instruction |= inst.operands[0].reg << 12;
7953}
a737bd4d 7954
c19d1205
ZW		 7955static void
7956do_rd_rm (void)
7957{
7958 inst.instruction |= inst.operands[0].reg << 12;
7959 inst.instruction |= inst.operands[1].reg;
7960}
09d92015 7961
9eb6c0f1
MGD		 7962static void
7963do_rm_rn (void)
7964{
7965 inst.instruction |= inst.operands[0].reg;
7966 inst.instruction |= inst.operands[1].reg << 16;
7967}
7968
c19d1205
ZW		 7969static void
7970do_rd_rn (void)
7971{
7972 inst.instruction |= inst.operands[0].reg << 12;
7973 inst.instruction |= inst.operands[1].reg << 16;
7974}
a737bd4d 7975
c19d1205
ZW		 7976static void
7977do_rn_rd (void)
7978{
7979 inst.instruction |= inst.operands[0].reg << 16;
7980 inst.instruction |= inst.operands[1].reg << 12;
7981}
09d92015 7982
59d09be6
MGD		 7983static bfd_boolean
7984check_obsolete (const arm_feature_set *feature, const char *msg)
7985{
7986 if (ARM_CPU_IS_ANY (cpu_variant))
7987 {
5c3696f8 7988 as_tsktsk ("%s", msg);
59d09be6
MGD		 7989 return TRUE;
7990 }
7991 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
7992 {
7993 as_bad ("%s", msg);
7994 return TRUE;
7995 }
7996
7997 return FALSE;
7998}
7999
c19d1205
ZW		 8000static void
8001do_rd_rm_rn (void)
8002{
9a64e435 8003 unsigned Rn = inst.operands[2].reg;
708587a4 8004 /* Enforce restrictions on SWP instruction. */
9a64e435 8005 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG		 8006 {
8007 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
8008 _("Rn must not overlap other operands"));
8009
59d09be6
MGD		 8010 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8011 */
8012 if (!check_obsolete (&arm_ext_v8,
8013 _("swp{b} use is obsoleted for ARMv8 and later"))
8014 && warn_on_deprecated
8015 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
5c3696f8 8016 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 8017 }
59d09be6 8018
c19d1205
ZW		 8019 inst.instruction |= inst.operands[0].reg << 12;
8020 inst.instruction |= inst.operands[1].reg;
9a64e435 8021 inst.instruction |= Rn << 16;
c19d1205 8022}
09d92015 8023
c19d1205
ZW		 8024static void
8025do_rd_rn_rm (void)
8026{
8027 inst.instruction |= inst.operands[0].reg << 12;
8028 inst.instruction |= inst.operands[1].reg << 16;
8029 inst.instruction |= inst.operands[2].reg;
8030}
a737bd4d 8031
c19d1205
ZW		 8032static void
8033do_rm_rd_rn (void)
8034{
5be8be5d
DG		 8035 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
8036 constraint (((inst.reloc.exp.X_op != O_constant
8037 && inst.reloc.exp.X_op != O_illegal)
8038 || inst.reloc.exp.X_add_number != 0),
8039 BAD_ADDR_MODE);
c19d1205
ZW		 8040 inst.instruction |= inst.operands[0].reg;
8041 inst.instruction |= inst.operands[1].reg << 12;
8042 inst.instruction |= inst.operands[2].reg << 16;
8043}
09d92015 8044
c19d1205
ZW		 8045static void
8046do_imm0 (void)
8047{
8048 inst.instruction |= inst.operands[0].imm;
8049}
09d92015 8050
c19d1205
ZW		 8051static void
8052do_rd_cpaddr (void)
8053{
8054 inst.instruction |= inst.operands[0].reg << 12;
8055 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 8056}
a737bd4d 8057
c19d1205
ZW		 8058/* ARM instructions, in alphabetical order by function name (except
8059 that wrapper functions appear immediately after the function they
8060 wrap). */
09d92015 8061
c19d1205
ZW		 8062/* This is a pseudo-op of the form "adr rd, label" to be converted
8063 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM		 8064
8065static void
c19d1205 8066do_adr (void)
09d92015 8067{
c19d1205 8068 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 8069
c19d1205
ZW		 8070 /* Frag hacking will turn this into a sub instruction if the offset turns
8071 out to be negative. */
8072 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
c19d1205 8073 inst.reloc.pc_rel = 1;
2fc8bdac 8074 inst.reloc.exp.X_add_number -= 8;
c19d1205 8075}
b99bd4ef 8076
c19d1205
ZW		 8077/* This is a pseudo-op of the form "adrl rd, label" to be converted
8078 into a relative address of the form:
8079 add rd, pc, #low(label-.-8)"
8080 add rd, rd, #high(label-.-8)" */
b99bd4ef 8081
c19d1205
ZW		 8082static void
8083do_adrl (void)
8084{
8085 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 8086
c19d1205
ZW		 8087 /* Frag hacking will turn this into a sub instruction if the offset turns
8088 out to be negative. */
8089 inst.reloc.type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
c19d1205
ZW		 8090 inst.reloc.pc_rel = 1;
8091 inst.size = INSN_SIZE * 2;
2fc8bdac 8092 inst.reloc.exp.X_add_number -= 8;
b99bd4ef
NC		 8093}
8094
b99bd4ef 8095static void
c19d1205 8096do_arit (void)
b99bd4ef 8097{
c19d1205
ZW		 8098 if (!inst.operands[1].present)
8099 inst.operands[1].reg = inst.operands[0].reg;
8100 inst.instruction |= inst.operands[0].reg << 12;
8101 inst.instruction |= inst.operands[1].reg << 16;
8102 encode_arm_shifter_operand (2);
8103}
b99bd4ef 8104
62b3e311
PB		 8105static void
8106do_barrier (void)
8107{
8108 if (inst.operands[0].present)
ccb84d65 8109 inst.instruction |= inst.operands[0].imm;
62b3e311
PB		 8110 else
8111 inst.instruction |= 0xf;
8112}
8113
c19d1205
ZW		 8114static void
8115do_bfc (void)
8116{
8117 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
8118 constraint (msb > 32, _("bit-field extends past end of register"));
8119 /* The instruction encoding stores the LSB and MSB,
8120 not the LSB and width. */
8121 inst.instruction |= inst.operands[0].reg << 12;
8122 inst.instruction |= inst.operands[1].imm << 7;
8123 inst.instruction |= (msb - 1) << 16;
8124}
b99bd4ef 8125
c19d1205
ZW		 8126static void
8127do_bfi (void)
8128{
8129 unsigned int msb;
b99bd4ef 8130
c19d1205
ZW		 8131 /* #0 in second position is alternative syntax for bfc, which is
8132 the same instruction but with REG_PC in the Rm field. */
8133 if (!inst.operands[1].isreg)
8134 inst.operands[1].reg = REG_PC;
b99bd4ef 8135
c19d1205
ZW		 8136 msb = inst.operands[2].imm + inst.operands[3].imm;
8137 constraint (msb > 32, _("bit-field extends past end of register"));
8138 /* The instruction encoding stores the LSB and MSB,
8139 not the LSB and width. */
8140 inst.instruction |= inst.operands[0].reg << 12;
8141 inst.instruction |= inst.operands[1].reg;
8142 inst.instruction |= inst.operands[2].imm << 7;
8143 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC		 8144}
8145
b99bd4ef 8146static void
c19d1205 8147do_bfx (void)
b99bd4ef 8148{
c19d1205
ZW		 8149 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
8150 _("bit-field extends past end of register"));
8151 inst.instruction |= inst.operands[0].reg << 12;
8152 inst.instruction |= inst.operands[1].reg;
8153 inst.instruction |= inst.operands[2].imm << 7;
8154 inst.instruction |= (inst.operands[3].imm - 1) << 16;
8155}
09d92015 8156
c19d1205
ZW		 8157/* ARM V5 breakpoint instruction (argument parse)
8158 BKPT <16 bit unsigned immediate>
8159 Instruction is not conditional.
8160 The bit pattern given in insns[] has the COND_ALWAYS condition,
8161 and it is an error if the caller tried to override that. */
b99bd4ef 8162
c19d1205
ZW		 8163static void
8164do_bkpt (void)
8165{
8166 /* Top 12 of 16 bits to bits 19:8. */
8167 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 8168
c19d1205
ZW		 8169 /* Bottom 4 of 16 bits to bits 3:0. */
8170 inst.instruction |= inst.operands[0].imm & 0xf;
8171}
09d92015 8172
c19d1205
ZW		 8173static void
8174encode_branch (int default_reloc)
8175{
8176 if (inst.operands[0].hasreloc)
8177 {
0855e32b
NS		 8178 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
8179 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
8180 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8181 inst.reloc.type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
8182 ? BFD_RELOC_ARM_PLT32
8183 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 8184 }
b99bd4ef 8185 else
9ae92b05 8186 inst.reloc.type = (bfd_reloc_code_real_type) default_reloc;
2fc8bdac 8187 inst.reloc.pc_rel = 1;
b99bd4ef
NC		 8188}
8189
b99bd4ef 8190static void
c19d1205 8191do_branch (void)
b99bd4ef 8192{
39b41c9c
PB		 8193#ifdef OBJ_ELF
8194 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8195 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8196 else
8197#endif
8198 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
8199}
8200
8201static void
8202do_bl (void)
8203{
8204#ifdef OBJ_ELF
8205 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
8206 {
8207 if (inst.cond == COND_ALWAYS)
8208 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
8209 else
8210 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
8211 }
8212 else
8213#endif
8214 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 8215}
b99bd4ef 8216
c19d1205
ZW		 8217/* ARM V5 branch-link-exchange instruction (argument parse)
8218 BLX <target_addr> ie BLX(1)
8219 BLX{<condition>} <Rm> ie BLX(2)
8220 Unfortunately, there are two different opcodes for this mnemonic.
8221 So, the insns[].value is not used, and the code here zaps values
8222 into inst.instruction.
8223 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 8224
c19d1205
ZW		 8225static void
8226do_blx (void)
8227{
8228 if (inst.operands[0].isreg)
b99bd4ef 8229 {
c19d1205
ZW		 8230 /* Arg is a register; the opcode provided by insns[] is correct.
8231 It is not illegal to do "blx pc", just useless. */
8232 if (inst.operands[0].reg == REG_PC)
8233 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 8234
c19d1205
ZW		 8235 inst.instruction |= inst.operands[0].reg;
8236 }
8237 else
b99bd4ef 8238 {
c19d1205 8239 /* Arg is an address; this instruction cannot be executed
267bf995
RR		 8240 conditionally, and the opcode must be adjusted.
8241 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8242 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 8243 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 8244 inst.instruction = 0xfa000000;
267bf995 8245 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 8246 }
c19d1205
ZW		 8247}
8248
8249static void
8250do_bx (void)
8251{
845b51d6
PB		 8252 bfd_boolean want_reloc;
8253
c19d1205
ZW		 8254 if (inst.operands[0].reg == REG_PC)
8255 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 8256
c19d1205 8257 inst.instruction |= inst.operands[0].reg;
845b51d6
PB		 8258 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8259 it is for ARMv4t or earlier. */
8260 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
8261 if (object_arch && !ARM_CPU_HAS_FEATURE (*object_arch, arm_ext_v5))
8262 want_reloc = TRUE;
8263
5ad34203 8264#ifdef OBJ_ELF
845b51d6 8265 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 8266#endif
584206db 8267 want_reloc = FALSE;
845b51d6
PB		 8268
8269 if (want_reloc)
8270 inst.reloc.type = BFD_RELOC_ARM_V4BX;
09d92015
MM		 8271}
8272
c19d1205
ZW		 8273
8274/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC		 8275
8276static void
c19d1205 8277do_bxj (void)
a737bd4d 8278{
c19d1205
ZW		 8279 if (inst.operands[0].reg == REG_PC)
8280 as_tsktsk (_("use of r15 in bxj is not really useful"));
8281
8282 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC		 8283}
8284
c19d1205
ZW		 8285/* Co-processor data operation:
8286 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8287 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8288static void
8289do_cdp (void)
8290{
8291 inst.instruction |= inst.operands[0].reg << 8;
8292 inst.instruction |= inst.operands[1].imm << 20;
8293 inst.instruction |= inst.operands[2].reg << 12;
8294 inst.instruction |= inst.operands[3].reg << 16;
8295 inst.instruction |= inst.operands[4].reg;
8296 inst.instruction |= inst.operands[5].imm << 5;
8297}
a737bd4d
NC		 8298
8299static void
c19d1205 8300do_cmp (void)
a737bd4d 8301{
c19d1205
ZW		 8302 inst.instruction |= inst.operands[0].reg << 16;
8303 encode_arm_shifter_operand (1);
a737bd4d
NC		 8304}
8305
c19d1205
ZW		 8306/* Transfer between coprocessor and ARM registers.
8307 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8308 MRC2
8309 MCR{cond}
8310 MCR2
8311
8312 No special properties. */
09d92015 8313
dcbd0d71
MGD		 8314struct deprecated_coproc_regs_s
8315{
8316 unsigned cp;
8317 int opc1;
8318 unsigned crn;
8319 unsigned crm;
8320 int opc2;
8321 arm_feature_set deprecated;
8322 arm_feature_set obsoleted;
8323 const char *dep_msg;
8324 const char *obs_msg;
8325};
8326
8327#define DEPR_ACCESS_V8 \
8328 N_("This coprocessor register access is deprecated in ARMv8")
8329
8330/* Table of all deprecated coprocessor registers. */
8331static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
8332{
8333 {15, 0, 7, 10, 5, /* CP15DMB. */
8334 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8335 DEPR_ACCESS_V8, NULL},
8336 {15, 0, 7, 10, 4, /* CP15DSB. */
8337 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8338 DEPR_ACCESS_V8, NULL},
8339 {15, 0, 7, 5, 4, /* CP15ISB. */
8340 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8341 DEPR_ACCESS_V8, NULL},
8342 {14, 6, 1, 0, 0, /* TEEHBR. */
8343 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8344 DEPR_ACCESS_V8, NULL},
8345 {14, 6, 0, 0, 0, /* TEECR. */
8346 ARM_FEATURE (ARM_EXT_V8, 0), ARM_FEATURE (0, 0),
8347 DEPR_ACCESS_V8, NULL},
8348};
8349
8350#undef DEPR_ACCESS_V8
8351
8352static const size_t deprecated_coproc_reg_count =
8353 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
8354
09d92015 8355static void
c19d1205 8356do_co_reg (void)
09d92015 8357{
fdfde340 8358 unsigned Rd;
dcbd0d71 8359 size_t i;
fdfde340
JM		 8360
8361 Rd = inst.operands[2].reg;
8362 if (thumb_mode)
8363 {
8364 if (inst.instruction == 0xee000010
8365 || inst.instruction == 0xfe000010)
8366 /* MCR, MCR2 */
8367 reject_bad_reg (Rd);
8368 else
8369 /* MRC, MRC2 */
8370 constraint (Rd == REG_SP, BAD_SP);
8371 }
8372 else
8373 {
8374 /* MCR */
8375 if (inst.instruction == 0xe000010)
8376 constraint (Rd == REG_PC, BAD_PC);
8377 }
8378
dcbd0d71
MGD		 8379 for (i = 0; i < deprecated_coproc_reg_count; ++i)
8380 {
8381 const struct deprecated_coproc_regs_s *r =
8382 deprecated_coproc_regs + i;
8383
8384 if (inst.operands[0].reg == r->cp
8385 && inst.operands[1].imm == r->opc1
8386 && inst.operands[3].reg == r->crn
8387 && inst.operands[4].reg == r->crm
8388 && inst.operands[5].imm == r->opc2)
8389 {
b10bf8c5 8390 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 8391 && warn_on_deprecated
dcbd0d71 8392 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
5c3696f8 8393 as_tsktsk ("%s", r->dep_msg);
dcbd0d71
MGD		 8394 }
8395 }
fdfde340 8396
c19d1205
ZW		 8397 inst.instruction |= inst.operands[0].reg << 8;
8398 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 8399 inst.instruction |= Rd << 12;
c19d1205
ZW		 8400 inst.instruction |= inst.operands[3].reg << 16;
8401 inst.instruction |= inst.operands[4].reg;
8402 inst.instruction |= inst.operands[5].imm << 5;
8403}
09d92015 8404
c19d1205
ZW		 8405/* Transfer between coprocessor register and pair of ARM registers.
8406 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8407 MCRR2
8408 MRRC{cond}
8409 MRRC2
b99bd4ef 8410
c19d1205 8411 Two XScale instructions are special cases of these:
09d92015 8412
c19d1205
ZW		 8413 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8414 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 8415
5f4273c7 8416 Result unpredictable if Rd or Rn is R15. */
a737bd4d 8417
c19d1205
ZW		 8418static void
8419do_co_reg2c (void)
8420{
fdfde340
JM		 8421 unsigned Rd, Rn;
8422
8423 Rd = inst.operands[2].reg;
8424 Rn = inst.operands[3].reg;
8425
8426 if (thumb_mode)
8427 {
8428 reject_bad_reg (Rd);
8429 reject_bad_reg (Rn);
8430 }
8431 else
8432 {
8433 constraint (Rd == REG_PC, BAD_PC);
8434 constraint (Rn == REG_PC, BAD_PC);
8435 }
8436
c19d1205
ZW		 8437 inst.instruction |= inst.operands[0].reg << 8;
8438 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM		 8439 inst.instruction |= Rd << 12;
8440 inst.instruction |= Rn << 16;
c19d1205 8441 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC		 8442}
8443
c19d1205
ZW		 8444static void
8445do_cpsi (void)
8446{
8447 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB		 8448 if (inst.operands[1].present)
8449 {
8450 inst.instruction |= CPSI_MMOD;
8451 inst.instruction |= inst.operands[1].imm;
8452 }
c19d1205 8453}
b99bd4ef 8454
62b3e311
PB		 8455static void
8456do_dbg (void)
8457{
8458 inst.instruction |= inst.operands[0].imm;
8459}
8460
eea54501
MGD		 8461static void
8462do_div (void)
8463{
8464 unsigned Rd, Rn, Rm;
8465
8466 Rd = inst.operands[0].reg;
8467 Rn = (inst.operands[1].present
8468 ? inst.operands[1].reg : Rd);
8469 Rm = inst.operands[2].reg;
8470
8471 constraint ((Rd == REG_PC), BAD_PC);
8472 constraint ((Rn == REG_PC), BAD_PC);
8473 constraint ((Rm == REG_PC), BAD_PC);
8474
8475 inst.instruction |= Rd << 16;
8476 inst.instruction |= Rn << 0;
8477 inst.instruction |= Rm << 8;
8478}
8479
b99bd4ef 8480static void
c19d1205 8481do_it (void)
b99bd4ef 8482{
c19d1205 8483 /* There is no IT instruction in ARM mode. We
e07e6e58
NC		 8484 process it to do the validation as if in
8485 thumb mode, just in case the code gets
8486 assembled for thumb using the unified syntax. */
8487
c19d1205 8488 inst.size = 0;
e07e6e58
NC		 8489 if (unified_syntax)
8490 {
8491 set_it_insn_type (IT_INSN);
8492 now_it.mask = (inst.instruction & 0xf) | 0x10;
8493 now_it.cc = inst.operands[0].imm;
8494 }
09d92015 8495}
b99bd4ef 8496
6530b175
NC		 8497/* If there is only one register in the register list,
8498 then return its register number. Otherwise return -1. */
8499static int
8500only_one_reg_in_list (int range)
8501{
8502 int i = ffs (range) - 1;
8503 return (i > 15 || range != (1 << i)) ? -1 : i;
8504}
8505
09d92015 8506static void
6530b175 8507encode_ldmstm(int from_push_pop_mnem)
ea6ef066 8508{
c19d1205
ZW		 8509 int base_reg = inst.operands[0].reg;
8510 int range = inst.operands[1].imm;
6530b175 8511 int one_reg;
ea6ef066 8512
c19d1205
ZW		 8513 inst.instruction |= base_reg << 16;
8514 inst.instruction |= range;
ea6ef066 8515
c19d1205
ZW		 8516 if (inst.operands[1].writeback)
8517 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 8518
c19d1205 8519 if (inst.operands[0].writeback)
ea6ef066 8520 {
c19d1205
ZW		 8521 inst.instruction |= WRITE_BACK;
8522 /* Check for unpredictable uses of writeback. */
8523 if (inst.instruction & LOAD_BIT)
09d92015 8524 {
c19d1205
ZW		 8525 /* Not allowed in LDM type 2. */
8526 if ((inst.instruction & LDM_TYPE_2_OR_3)
8527 && ((range & (1 << REG_PC)) == 0))
8528 as_warn (_("writeback of base register is UNPREDICTABLE"));
8529 /* Only allowed if base reg not in list for other types. */
8530 else if (range & (1 << base_reg))
8531 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8532 }
8533 else /* STM. */
8534 {
8535 /* Not allowed for type 2. */
8536 if (inst.instruction & LDM_TYPE_2_OR_3)
8537 as_warn (_("writeback of base register is UNPREDICTABLE"));
8538 /* Only allowed if base reg not in list, or first in list. */
8539 else if ((range & (1 << base_reg))
8540 && (range & ((1 << base_reg) - 1)))
8541 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 8542 }
ea6ef066 8543 }
6530b175
NC		 8544
8545 /* If PUSH/POP has only one register, then use the A2 encoding. */
8546 one_reg = only_one_reg_in_list (range);
8547 if (from_push_pop_mnem && one_reg >= 0)
8548 {
8549 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
8550
8551 inst.instruction &= A_COND_MASK;
8552 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
8553 inst.instruction |= one_reg << 12;
8554 }
8555}
8556
8557static void
8558do_ldmstm (void)
8559{
8560 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC		 8561}
8562
c19d1205
ZW		 8563/* ARMv5TE load-consecutive (argument parse)
8564 Mode is like LDRH.
8565
8566 LDRccD R, mode
8567 STRccD R, mode. */
8568
a737bd4d 8569static void
c19d1205 8570do_ldrd (void)
a737bd4d 8571{
c19d1205 8572 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 8573 _("first transfer register must be even"));
c19d1205
ZW		 8574 constraint (inst.operands[1].present
8575 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 8576 _("can only transfer two consecutive registers"));
c19d1205
ZW		 8577 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
8578 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 8579
c19d1205
ZW		 8580 if (!inst.operands[1].present)
8581 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 8582
c56791bb
RE		 8583 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8584 register and the first register written; we have to diagnose
8585 overlap between the base and the second register written here. */
ea6ef066 8586
c56791bb
RE		 8587 if (inst.operands[2].reg == inst.operands[1].reg
8588 && (inst.operands[2].writeback || inst.operands[2].postind))
8589 as_warn (_("base register written back, and overlaps "
8590 "second transfer register"));
b05fe5cf 8591
c56791bb
RE		 8592 if (!(inst.instruction & V4_STR_BIT))
8593 {
c19d1205 8594 /* For an index-register load, the index register must not overlap the
c56791bb
RE		 8595 destination (even if not write-back). */
8596 if (inst.operands[2].immisreg
8597 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
8598 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
8599 as_warn (_("index register overlaps transfer register"));
b05fe5cf 8600 }
c19d1205
ZW		 8601 inst.instruction |= inst.operands[0].reg << 12;
8602 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW		 8603}
8604
8605static void
c19d1205 8606do_ldrex (void)
b05fe5cf 8607{
c19d1205
ZW		 8608 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
8609 || inst.operands[1].postind || inst.operands[1].writeback
8610 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC		 8611 || inst.operands[1].negative
8612 /* This can arise if the programmer has written
8613 strex rN, rM, foo
8614 or if they have mistakenly used a register name as the last
8615 operand, eg:
8616 strex rN, rM, rX
8617 It is very difficult to distinguish between these two cases
8618 because "rX" might actually be a label. ie the register
8619 name has been occluded by a symbol of the same name. So we
8620 just generate a general 'bad addressing mode' type error
8621 message and leave it up to the programmer to discover the
8622 true cause and fix their mistake. */
8623 || (inst.operands[1].reg == REG_PC),
8624 BAD_ADDR_MODE);
b05fe5cf 8625
c19d1205
ZW		 8626 constraint (inst.reloc.exp.X_op != O_constant
8627 || inst.reloc.exp.X_add_number != 0,
8628 _("offset must be zero in ARM encoding"));
b05fe5cf 8629
5be8be5d
DG		 8630 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
8631
c19d1205
ZW		 8632 inst.instruction |= inst.operands[0].reg << 12;
8633 inst.instruction |= inst.operands[1].reg << 16;
8634 inst.reloc.type = BFD_RELOC_UNUSED;
b05fe5cf
ZW		 8635}
8636
8637static void
c19d1205 8638do_ldrexd (void)
b05fe5cf 8639{
c19d1205
ZW		 8640 constraint (inst.operands[0].reg % 2 != 0,
8641 _("even register required"));
8642 constraint (inst.operands[1].present
8643 && inst.operands[1].reg != inst.operands[0].reg + 1,
8644 _("can only load two consecutive registers"));
8645 /* If op 1 were present and equal to PC, this function wouldn't
8646 have been called in the first place. */
8647 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 8648
c19d1205
ZW		 8649 inst.instruction |= inst.operands[0].reg << 12;
8650 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW		 8651}
8652
1be5fd2e
NC		 8653/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8654 which is not a multiple of four is UNPREDICTABLE. */
8655static void
8656check_ldr_r15_aligned (void)
8657{
8658 constraint (!(inst.operands[1].immisreg)
8659 && (inst.operands[0].reg == REG_PC
8660 && inst.operands[1].reg == REG_PC
8661 && (inst.reloc.exp.X_add_number & 0x3)),
8662 _("ldr to register 15 must be 4-byte alligned"));
8663}
8664
b05fe5cf 8665static void
c19d1205 8666do_ldst (void)
b05fe5cf 8667{
c19d1205
ZW		 8668 inst.instruction |= inst.operands[0].reg << 12;
8669 if (!inst.operands[1].isreg)
8335d6aa 8670 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
b05fe5cf 8671 return;
c19d1205 8672 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 8673 check_ldr_r15_aligned ();
b05fe5cf
ZW		 8674}
8675
8676static void
c19d1205 8677do_ldstt (void)
b05fe5cf 8678{
c19d1205
ZW		 8679 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8680 reject [Rn,...]. */
8681 if (inst.operands[1].preind)
b05fe5cf 8682 {
bd3ba5d1
NC		 8683 constraint (inst.reloc.exp.X_op != O_constant
8684 || inst.reloc.exp.X_add_number != 0,
c19d1205 8685 _("this instruction requires a post-indexed address"));
b05fe5cf 8686
c19d1205
ZW		 8687 inst.operands[1].preind = 0;
8688 inst.operands[1].postind = 1;
8689 inst.operands[1].writeback = 1;
b05fe5cf 8690 }
c19d1205
ZW		 8691 inst.instruction |= inst.operands[0].reg << 12;
8692 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
8693}
b05fe5cf 8694
c19d1205 8695/* Halfword and signed-byte load/store operations. */
b05fe5cf 8696
c19d1205
ZW		 8697static void
8698do_ldstv4 (void)
8699{
ff4a8d2b 8700 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW		 8701 inst.instruction |= inst.operands[0].reg << 12;
8702 if (!inst.operands[1].isreg)
8335d6aa 8703 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
b05fe5cf 8704 return;
c19d1205 8705 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW		 8706}
8707
8708static void
c19d1205 8709do_ldsttv4 (void)
b05fe5cf 8710{
c19d1205
ZW		 8711 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8712 reject [Rn,...]. */
8713 if (inst.operands[1].preind)
b05fe5cf 8714 {
bd3ba5d1
NC		 8715 constraint (inst.reloc.exp.X_op != O_constant
8716 || inst.reloc.exp.X_add_number != 0,
c19d1205 8717 _("this instruction requires a post-indexed address"));
b05fe5cf 8718
c19d1205
ZW		 8719 inst.operands[1].preind = 0;
8720 inst.operands[1].postind = 1;
8721 inst.operands[1].writeback = 1;
b05fe5cf 8722 }
c19d1205
ZW		 8723 inst.instruction |= inst.operands[0].reg << 12;
8724 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
8725}
b05fe5cf 8726
c19d1205
ZW		 8727/* Co-processor register load/store.
8728 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8729static void
8730do_lstc (void)
8731{
8732 inst.instruction |= inst.operands[0].reg << 8;
8733 inst.instruction |= inst.operands[1].reg << 12;
8734 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW		 8735}
8736
b05fe5cf 8737static void
c19d1205 8738do_mlas (void)
b05fe5cf 8739{
8fb9d7b9 8740 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 8741 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 8742 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 8743 && !(inst.instruction & 0x00400000))
8fb9d7b9 8744 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 8745
c19d1205
ZW		 8746 inst.instruction |= inst.operands[0].reg << 16;
8747 inst.instruction |= inst.operands[1].reg;
8748 inst.instruction |= inst.operands[2].reg << 8;
8749 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 8750}
b05fe5cf 8751
c19d1205
ZW		 8752static void
8753do_mov (void)
8754{
8755 inst.instruction |= inst.operands[0].reg << 12;
8756 encode_arm_shifter_operand (1);
8757}
b05fe5cf 8758
c19d1205
ZW		 8759/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8760static void
8761do_mov16 (void)
8762{
b6895b4f
PB		 8763 bfd_vma imm;
8764 bfd_boolean top;
8765
8766 top = (inst.instruction & 0x00400000) != 0;
8767 constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
8768 _(":lower16: not allowed this instruction"));
8769 constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
8770 _(":upper16: not allowed instruction"));
c19d1205 8771 inst.instruction |= inst.operands[0].reg << 12;
b6895b4f
PB		 8772 if (inst.reloc.type == BFD_RELOC_UNUSED)
8773 {
8774 imm = inst.reloc.exp.X_add_number;
8775 /* The value is in two pieces: 0:11, 16:19. */
8776 inst.instruction |= (imm & 0x00000fff);
8777 inst.instruction |= (imm & 0x0000f000) << 4;
8778 }
b05fe5cf 8779}
b99bd4ef 8780
037e8744
JB		 8781static void do_vfp_nsyn_opcode (const char *);
8782
8783static int
8784do_vfp_nsyn_mrs (void)
8785{
8786 if (inst.operands[0].isvec)
8787 {
8788 if (inst.operands[1].reg != 1)
477330fc 8789 first_error (_("operand 1 must be FPSCR"));
037e8744
JB		 8790 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
8791 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
8792 do_vfp_nsyn_opcode ("fmstat");
8793 }
8794 else if (inst.operands[1].isvec)
8795 do_vfp_nsyn_opcode ("fmrx");
8796 else
8797 return FAIL;
5f4273c7 8798
037e8744
JB		 8799 return SUCCESS;
8800}
8801
8802static int
8803do_vfp_nsyn_msr (void)
8804{
8805 if (inst.operands[0].isvec)
8806 do_vfp_nsyn_opcode ("fmxr");
8807 else
8808 return FAIL;
8809
8810 return SUCCESS;
8811}
8812
f7c21dc7
NC		 8813static void
8814do_vmrs (void)
8815{
8816 unsigned Rt = inst.operands[0].reg;
fa94de6b 8817
16d02dc9 8818 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC		 8819 {
8820 inst.error = BAD_SP;
8821 return;
8822 }
8823
8824 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 8825 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC		 8826 {
8827 inst.error = BAD_PC;
8828 return;
8829 }
8830
16d02dc9
JB		 8831 /* If we get through parsing the register name, we just insert the number
8832 generated into the instruction without further validation. */
8833 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC		 8834 inst.instruction |= (Rt << 12);
8835}
8836
8837static void
8838do_vmsr (void)
8839{
8840 unsigned Rt = inst.operands[1].reg;
fa94de6b 8841
f7c21dc7
NC		 8842 if (thumb_mode)
8843 reject_bad_reg (Rt);
8844 else if (Rt == REG_PC)
8845 {
8846 inst.error = BAD_PC;
8847 return;
8848 }
8849
16d02dc9
JB		 8850 /* If we get through parsing the register name, we just insert the number
8851 generated into the instruction without further validation. */
8852 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC		 8853 inst.instruction |= (Rt << 12);
8854}
8855
b99bd4ef 8856static void
c19d1205 8857do_mrs (void)
b99bd4ef 8858{
90ec0d68
MGD		 8859 unsigned br;
8860
037e8744
JB		 8861 if (do_vfp_nsyn_mrs () == SUCCESS)
8862 return;
8863
ff4a8d2b 8864 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 8865 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD		 8866
8867 if (inst.operands[1].isreg)
8868 {
8869 br = inst.operands[1].reg;
8870 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf000))
8871 as_bad (_("bad register for mrs"));
8872 }
8873 else
8874 {
8875 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8876 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
8877 != (PSR_c|PSR_f),
d2cd1205 8878 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD		 8879 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
8880 }
8881
8882 inst.instruction |= br;
c19d1205 8883}
b99bd4ef 8884
c19d1205
ZW		 8885/* Two possible forms:
8886 "{C|S}PSR_<field>, Rm",
8887 "{C|S}PSR_f, #expression". */
b99bd4ef 8888
c19d1205
ZW		 8889static void
8890do_msr (void)
8891{
037e8744
JB		 8892 if (do_vfp_nsyn_msr () == SUCCESS)
8893 return;
8894
c19d1205
ZW		 8895 inst.instruction |= inst.operands[0].imm;
8896 if (inst.operands[1].isreg)
8897 inst.instruction |= inst.operands[1].reg;
8898 else
b99bd4ef 8899 {
c19d1205
ZW		 8900 inst.instruction |= INST_IMMEDIATE;
8901 inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
8902 inst.reloc.pc_rel = 0;
b99bd4ef 8903 }
b99bd4ef
NC		 8904}
8905
c19d1205
ZW		 8906static void
8907do_mul (void)
a737bd4d 8908{
ff4a8d2b
NC		 8909 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
8910
c19d1205
ZW		 8911 if (!inst.operands[2].present)
8912 inst.operands[2].reg = inst.operands[0].reg;
8913 inst.instruction |= inst.operands[0].reg << 16;
8914 inst.instruction |= inst.operands[1].reg;
8915 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 8916
8fb9d7b9
MS		 8917 if (inst.operands[0].reg == inst.operands[1].reg
8918 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
8919 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC		 8920}
8921
c19d1205
ZW		 8922/* Long Multiply Parser
8923 UMULL RdLo, RdHi, Rm, Rs
8924 SMULL RdLo, RdHi, Rm, Rs
8925 UMLAL RdLo, RdHi, Rm, Rs
8926 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC		 8927
8928static void
c19d1205 8929do_mull (void)
b99bd4ef 8930{
c19d1205
ZW		 8931 inst.instruction |= inst.operands[0].reg << 12;
8932 inst.instruction |= inst.operands[1].reg << 16;
8933 inst.instruction |= inst.operands[2].reg;
8934 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 8935
682b27ad
PB		 8936 /* rdhi and rdlo must be different. */
8937 if (inst.operands[0].reg == inst.operands[1].reg)
8938 as_tsktsk (_("rdhi and rdlo must be different"));
8939
8940 /* rdhi, rdlo and rm must all be different before armv6. */
8941 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 8942 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 8943 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW		 8944 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8945}
b99bd4ef 8946
c19d1205
ZW		 8947static void
8948do_nop (void)
8949{
e7495e45
NS		 8950 if (inst.operands[0].present
8951 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW		 8952 {
8953 /* Architectural NOP hints are CPSR sets with no bits selected. */
8954 inst.instruction &= 0xf0000000;
e7495e45
NS		 8955 inst.instruction |= 0x0320f000;
8956 if (inst.operands[0].present)
8957 inst.instruction |= inst.operands[0].imm;
c19d1205 8958 }
b99bd4ef
NC		 8959}
8960
c19d1205
ZW		 8961/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8962 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8963 Condition defaults to COND_ALWAYS.
8964 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC		 8965
8966static void
c19d1205 8967do_pkhbt (void)
b99bd4ef 8968{
c19d1205
ZW		 8969 inst.instruction |= inst.operands[0].reg << 12;
8970 inst.instruction |= inst.operands[1].reg << 16;
8971 inst.instruction |= inst.operands[2].reg;
8972 if (inst.operands[3].present)
8973 encode_arm_shift (3);
8974}
b99bd4ef 8975
c19d1205 8976/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 8977
c19d1205
ZW		 8978static void
8979do_pkhtb (void)
8980{
8981 if (!inst.operands[3].present)
b99bd4ef 8982 {
c19d1205
ZW		 8983 /* If the shift specifier is omitted, turn the instruction
8984 into pkhbt rd, rm, rn. */
8985 inst.instruction &= 0xfff00010;
8986 inst.instruction |= inst.operands[0].reg << 12;
8987 inst.instruction |= inst.operands[1].reg;
8988 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 8989 }
8990 else
8991 {
c19d1205
ZW		 8992 inst.instruction |= inst.operands[0].reg << 12;
8993 inst.instruction |= inst.operands[1].reg << 16;
8994 inst.instruction |= inst.operands[2].reg;
8995 encode_arm_shift (3);
b99bd4ef
NC		 8996 }
8997}
8998
c19d1205 8999/* ARMv5TE: Preload-Cache
60e5ef9f 9000 MP Extensions: Preload for write
c19d1205 9001
60e5ef9f 9002 PLD(W) <addr_mode>
c19d1205
ZW		 9003
9004 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC		 9005
9006static void
c19d1205 9007do_pld (void)
b99bd4ef 9008{
c19d1205
ZW		 9009 constraint (!inst.operands[0].isreg,
9010 _("'[' expected after PLD mnemonic"));
9011 constraint (inst.operands[0].postind,
9012 _("post-indexed expression used in preload instruction"));
9013 constraint (inst.operands[0].writeback,
9014 _("writeback used in preload instruction"));
9015 constraint (!inst.operands[0].preind,
9016 _("unindexed addressing used in preload instruction"));
c19d1205
ZW		 9017 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9018}
b99bd4ef 9019
62b3e311
PB		 9020/* ARMv7: PLI <addr_mode> */
9021static void
9022do_pli (void)
9023{
9024 constraint (!inst.operands[0].isreg,
9025 _("'[' expected after PLI mnemonic"));
9026 constraint (inst.operands[0].postind,
9027 _("post-indexed expression used in preload instruction"));
9028 constraint (inst.operands[0].writeback,
9029 _("writeback used in preload instruction"));
9030 constraint (!inst.operands[0].preind,
9031 _("unindexed addressing used in preload instruction"));
9032 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
9033 inst.instruction &= ~PRE_INDEX;
9034}
9035
c19d1205
ZW		 9036static void
9037do_push_pop (void)
9038{
5e0d7f77
MP		 9039 constraint (inst.operands[0].writeback,
9040 _("push/pop do not support {reglist}^"));
c19d1205
ZW		 9041 inst.operands[1] = inst.operands[0];
9042 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
9043 inst.operands[0].isreg = 1;
9044 inst.operands[0].writeback = 1;
9045 inst.operands[0].reg = REG_SP;
6530b175 9046 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 9047}
b99bd4ef 9048
c19d1205
ZW		 9049/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9050 word at the specified address and the following word
9051 respectively.
9052 Unconditionally executed.
9053 Error if Rn is R15. */
b99bd4ef 9054
c19d1205
ZW		 9055static void
9056do_rfe (void)
9057{
9058 inst.instruction |= inst.operands[0].reg << 16;
9059 if (inst.operands[0].writeback)
9060 inst.instruction |= WRITE_BACK;
9061}
b99bd4ef 9062
c19d1205 9063/* ARM V6 ssat (argument parse). */
b99bd4ef 9064
c19d1205
ZW		 9065static void
9066do_ssat (void)
9067{
9068 inst.instruction |= inst.operands[0].reg << 12;
9069 inst.instruction |= (inst.operands[1].imm - 1) << 16;
9070 inst.instruction |= inst.operands[2].reg;
b99bd4ef 9071
c19d1205
ZW		 9072 if (inst.operands[3].present)
9073 encode_arm_shift (3);
b99bd4ef
NC		 9074}
9075
c19d1205 9076/* ARM V6 usat (argument parse). */
b99bd4ef
NC		 9077
9078static void
c19d1205 9079do_usat (void)
b99bd4ef 9080{
c19d1205
ZW		 9081 inst.instruction |= inst.operands[0].reg << 12;
9082 inst.instruction |= inst.operands[1].imm << 16;
9083 inst.instruction |= inst.operands[2].reg;
b99bd4ef 9084
c19d1205
ZW		 9085 if (inst.operands[3].present)
9086 encode_arm_shift (3);
b99bd4ef
NC		 9087}
9088
c19d1205 9089/* ARM V6 ssat16 (argument parse). */
09d92015
MM		 9090
9091static void
c19d1205 9092do_ssat16 (void)
09d92015 9093{
c19d1205
ZW		 9094 inst.instruction |= inst.operands[0].reg << 12;
9095 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
9096 inst.instruction |= inst.operands[2].reg;
09d92015
MM		 9097}
9098
c19d1205
ZW		 9099static void
9100do_usat16 (void)
a737bd4d 9101{
c19d1205
ZW		 9102 inst.instruction |= inst.operands[0].reg << 12;
9103 inst.instruction |= inst.operands[1].imm << 16;
9104 inst.instruction |= inst.operands[2].reg;
9105}
a737bd4d 9106
c19d1205
ZW		 9107/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9108 preserving the other bits.
a737bd4d 9109
c19d1205
ZW		 9110 setend <endian_specifier>, where <endian_specifier> is either
9111 BE or LE. */
a737bd4d 9112
c19d1205
ZW		 9113static void
9114do_setend (void)
9115{
12e37cbc
MGD		 9116 if (warn_on_deprecated
9117 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 9118 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 9119
c19d1205
ZW		 9120 if (inst.operands[0].imm)
9121 inst.instruction |= 0x200;
a737bd4d
NC		 9122}
9123
9124static void
c19d1205 9125do_shift (void)
a737bd4d 9126{
c19d1205
ZW		 9127 unsigned int Rm = (inst.operands[1].present
9128 ? inst.operands[1].reg
9129 : inst.operands[0].reg);
a737bd4d 9130
c19d1205
ZW		 9131 inst.instruction |= inst.operands[0].reg << 12;
9132 inst.instruction |= Rm;
9133 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 9134 {
c19d1205
ZW		 9135 inst.instruction |= inst.operands[2].reg << 8;
9136 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC		 9137 /* PR 12854: Error on extraneous shifts. */
9138 constraint (inst.operands[2].shifted,
9139 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC		 9140 }
9141 else
c19d1205 9142 inst.reloc.type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC		 9143}
9144
09d92015 9145static void
3eb17e6b 9146do_smc (void)
09d92015 9147{
3eb17e6b 9148 inst.reloc.type = BFD_RELOC_ARM_SMC;
c19d1205 9149 inst.reloc.pc_rel = 0;
09d92015
MM		 9150}
9151
90ec0d68
MGD		 9152static void
9153do_hvc (void)
9154{
9155 inst.reloc.type = BFD_RELOC_ARM_HVC;
9156 inst.reloc.pc_rel = 0;
9157}
9158
09d92015 9159static void
c19d1205 9160do_swi (void)
09d92015 9161{
c19d1205
ZW		 9162 inst.reloc.type = BFD_RELOC_ARM_SWI;
9163 inst.reloc.pc_rel = 0;
09d92015
MM		 9164}
9165
c19d1205
ZW		 9166/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9167 SMLAxy{cond} Rd,Rm,Rs,Rn
9168 SMLAWy{cond} Rd,Rm,Rs,Rn
9169 Error if any register is R15. */
e16bb312 9170
c19d1205
ZW		 9171static void
9172do_smla (void)
e16bb312 9173{
c19d1205
ZW		 9174 inst.instruction |= inst.operands[0].reg << 16;
9175 inst.instruction |= inst.operands[1].reg;
9176 inst.instruction |= inst.operands[2].reg << 8;
9177 inst.instruction |= inst.operands[3].reg << 12;
9178}
a737bd4d 9179
c19d1205
ZW		 9180/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9181 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9182 Error if any register is R15.
9183 Warning if Rdlo == Rdhi. */
a737bd4d 9184
c19d1205
ZW		 9185static void
9186do_smlal (void)
9187{
9188 inst.instruction |= inst.operands[0].reg << 12;
9189 inst.instruction |= inst.operands[1].reg << 16;
9190 inst.instruction |= inst.operands[2].reg;
9191 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 9192
c19d1205
ZW		 9193 if (inst.operands[0].reg == inst.operands[1].reg)
9194 as_tsktsk (_("rdhi and rdlo must be different"));
9195}
a737bd4d 9196
c19d1205
ZW		 9197/* ARM V5E (El Segundo) signed-multiply (argument parse)
9198 SMULxy{cond} Rd,Rm,Rs
9199 Error if any register is R15. */
a737bd4d 9200
c19d1205
ZW		 9201static void
9202do_smul (void)
9203{
9204 inst.instruction |= inst.operands[0].reg << 16;
9205 inst.instruction |= inst.operands[1].reg;
9206 inst.instruction |= inst.operands[2].reg << 8;
9207}
a737bd4d 9208
b6702015
PB		 9209/* ARM V6 srs (argument parse). The variable fields in the encoding are
9210 the same for both ARM and Thumb-2. */
a737bd4d 9211
c19d1205
ZW		 9212static void
9213do_srs (void)
9214{
b6702015
PB		 9215 int reg;
9216
9217 if (inst.operands[0].present)
9218 {
9219 reg = inst.operands[0].reg;
fdfde340 9220 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB		 9221 }
9222 else
fdfde340 9223 reg = REG_SP;
b6702015
PB		 9224
9225 inst.instruction |= reg << 16;
9226 inst.instruction |= inst.operands[1].imm;
9227 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW		 9228 inst.instruction |= WRITE_BACK;
9229}
a737bd4d 9230
c19d1205 9231/* ARM V6 strex (argument parse). */
a737bd4d 9232
c19d1205
ZW		 9233static void
9234do_strex (void)
9235{
9236 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9237 || inst.operands[2].postind || inst.operands[2].writeback
9238 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC		 9239 || inst.operands[2].negative
9240 /* See comment in do_ldrex(). */
9241 || (inst.operands[2].reg == REG_PC),
9242 BAD_ADDR_MODE);
a737bd4d 9243
c19d1205
ZW		 9244 constraint (inst.operands[0].reg == inst.operands[1].reg
9245 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 9246
c19d1205
ZW		 9247 constraint (inst.reloc.exp.X_op != O_constant
9248 || inst.reloc.exp.X_add_number != 0,
9249 _("offset must be zero in ARM encoding"));
a737bd4d 9250
c19d1205
ZW		 9251 inst.instruction |= inst.operands[0].reg << 12;
9252 inst.instruction |= inst.operands[1].reg;
9253 inst.instruction |= inst.operands[2].reg << 16;
9254 inst.reloc.type = BFD_RELOC_UNUSED;
e16bb312
NC		 9255}
9256
877807f8
NC		 9257static void
9258do_t_strexbh (void)
9259{
9260 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
9261 || inst.operands[2].postind || inst.operands[2].writeback
9262 || inst.operands[2].immisreg || inst.operands[2].shifted
9263 || inst.operands[2].negative,
9264 BAD_ADDR_MODE);
9265
9266 constraint (inst.operands[0].reg == inst.operands[1].reg
9267 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9268
9269 do_rm_rd_rn ();
9270}
9271
e16bb312 9272static void
c19d1205 9273do_strexd (void)
e16bb312 9274{
c19d1205
ZW		 9275 constraint (inst.operands[1].reg % 2 != 0,
9276 _("even register required"));
9277 constraint (inst.operands[2].present
9278 && inst.operands[2].reg != inst.operands[1].reg + 1,
9279 _("can only store two consecutive registers"));
9280 /* If op 2 were present and equal to PC, this function wouldn't
9281 have been called in the first place. */
9282 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 9283
c19d1205
ZW		 9284 constraint (inst.operands[0].reg == inst.operands[1].reg
9285 || inst.operands[0].reg == inst.operands[1].reg + 1
9286 || inst.operands[0].reg == inst.operands[3].reg,
9287 BAD_OVERLAP);
e16bb312 9288
c19d1205
ZW		 9289 inst.instruction |= inst.operands[0].reg << 12;
9290 inst.instruction |= inst.operands[1].reg;
9291 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC		 9292}
9293
9eb6c0f1
MGD		 9294/* ARM V8 STRL. */
9295static void
4b8c8c02 9296do_stlex (void)
9eb6c0f1
MGD		 9297{
9298 constraint (inst.operands[0].reg == inst.operands[1].reg
9299 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9300
9301 do_rd_rm_rn ();
9302}
9303
9304static void
4b8c8c02 9305do_t_stlex (void)
9eb6c0f1
MGD		 9306{
9307 constraint (inst.operands[0].reg == inst.operands[1].reg
9308 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
9309
9310 do_rm_rd_rn ();
9311}
9312
c19d1205
ZW		 9313/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9314 extends it to 32-bits, and adds the result to a value in another
9315 register. You can specify a rotation by 0, 8, 16, or 24 bits
9316 before extracting the 16-bit value.
9317 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9318 Condition defaults to COND_ALWAYS.
9319 Error if any register uses R15. */
9320
e16bb312 9321static void
c19d1205 9322do_sxtah (void)
e16bb312 9323{
c19d1205
ZW		 9324 inst.instruction |= inst.operands[0].reg << 12;
9325 inst.instruction |= inst.operands[1].reg << 16;
9326 inst.instruction |= inst.operands[2].reg;
9327 inst.instruction |= inst.operands[3].imm << 10;
9328}
e16bb312 9329
c19d1205 9330/* ARM V6 SXTH.
e16bb312 9331
c19d1205
ZW		 9332 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9333 Condition defaults to COND_ALWAYS.
9334 Error if any register uses R15. */
e16bb312
NC		 9335
9336static void
c19d1205 9337do_sxth (void)
e16bb312 9338{
c19d1205
ZW		 9339 inst.instruction |= inst.operands[0].reg << 12;
9340 inst.instruction |= inst.operands[1].reg;
9341 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 9342}
c19d1205
ZW		 9343\f
9344/* VFP instructions. In a logical order: SP variant first, monad
9345 before dyad, arithmetic then move then load/store. */
e16bb312
NC		 9346
9347static void
c19d1205 9348do_vfp_sp_monadic (void)
e16bb312 9349{
5287ad62
JB		 9350 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9351 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 9352}
9353
9354static void
c19d1205 9355do_vfp_sp_dyadic (void)
e16bb312 9356{
5287ad62
JB		 9357 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9358 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
9359 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 9360}
9361
9362static void
c19d1205 9363do_vfp_sp_compare_z (void)
e16bb312 9364{
5287ad62 9365 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC		 9366}
9367
9368static void
c19d1205 9369do_vfp_dp_sp_cvt (void)
e16bb312 9370{
5287ad62
JB		 9371 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9372 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 9373}
9374
9375static void
c19d1205 9376do_vfp_sp_dp_cvt (void)
e16bb312 9377{
5287ad62
JB		 9378 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9379 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC		 9380}
9381
9382static void
c19d1205 9383do_vfp_reg_from_sp (void)
e16bb312 9384{
c19d1205 9385 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 9386 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC		 9387}
9388
9389static void
c19d1205 9390do_vfp_reg2_from_sp2 (void)
e16bb312 9391{
c19d1205
ZW		 9392 constraint (inst.operands[2].imm != 2,
9393 _("only two consecutive VFP SP registers allowed here"));
9394 inst.instruction |= inst.operands[0].reg << 12;
9395 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 9396 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 9397}
9398
9399static void
c19d1205 9400do_vfp_sp_from_reg (void)
e16bb312 9401{
5287ad62 9402 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 9403 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC		 9404}
9405
9406static void
c19d1205 9407do_vfp_sp2_from_reg2 (void)
e16bb312 9408{
c19d1205
ZW		 9409 constraint (inst.operands[0].imm != 2,
9410 _("only two consecutive VFP SP registers allowed here"));
5287ad62 9411 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW		 9412 inst.instruction |= inst.operands[1].reg << 12;
9413 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC		 9414}
9415
9416static void
c19d1205 9417do_vfp_sp_ldst (void)
e16bb312 9418{
5287ad62 9419 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 9420 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 9421}
9422
9423static void
c19d1205 9424do_vfp_dp_ldst (void)
e16bb312 9425{
5287ad62 9426 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 9427 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 9428}
9429
c19d1205 9430
e16bb312 9431static void
c19d1205 9432vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 9433{
c19d1205
ZW		 9434 if (inst.operands[0].writeback)
9435 inst.instruction |= WRITE_BACK;
9436 else
9437 constraint (ldstm_type != VFP_LDSTMIA,
9438 _("this addressing mode requires base-register writeback"));
9439 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 9440 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 9441 inst.instruction |= inst.operands[1].imm;
e16bb312
NC		 9442}
9443
9444static void
c19d1205 9445vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 9446{
c19d1205 9447 int count;
e16bb312 9448
c19d1205
ZW		 9449 if (inst.operands[0].writeback)
9450 inst.instruction |= WRITE_BACK;
9451 else
9452 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
9453 _("this addressing mode requires base-register writeback"));
e16bb312 9454
c19d1205 9455 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 9456 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 9457
c19d1205
ZW		 9458 count = inst.operands[1].imm << 1;
9459 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
9460 count += 1;
e16bb312 9461
c19d1205 9462 inst.instruction |= count;
e16bb312
NC		 9463}
9464
9465static void
c19d1205 9466do_vfp_sp_ldstmia (void)
e16bb312 9467{
c19d1205 9468 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 9469}
9470
9471static void
c19d1205 9472do_vfp_sp_ldstmdb (void)
e16bb312 9473{
c19d1205 9474 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 9475}
9476
9477static void
c19d1205 9478do_vfp_dp_ldstmia (void)
e16bb312 9479{
c19d1205 9480 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 9481}
9482
9483static void
c19d1205 9484do_vfp_dp_ldstmdb (void)
e16bb312 9485{
c19d1205 9486 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 9487}
9488
9489static void
c19d1205 9490do_vfp_xp_ldstmia (void)
e16bb312 9491{
c19d1205
ZW		 9492 vfp_dp_ldstm (VFP_LDSTMIAX);
9493}
e16bb312 9494
c19d1205
ZW		 9495static void
9496do_vfp_xp_ldstmdb (void)
9497{
9498 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 9499}
5287ad62
JB		 9500
9501static void
9502do_vfp_dp_rd_rm (void)
9503{
9504 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9505 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
9506}
9507
9508static void
9509do_vfp_dp_rn_rd (void)
9510{
9511 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
9512 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9513}
9514
9515static void
9516do_vfp_dp_rd_rn (void)
9517{
9518 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9519 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9520}
9521
9522static void
9523do_vfp_dp_rd_rn_rm (void)
9524{
9525 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9526 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
9527 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
9528}
9529
9530static void
9531do_vfp_dp_rd (void)
9532{
9533 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9534}
9535
9536static void
9537do_vfp_dp_rm_rd_rn (void)
9538{
9539 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
9540 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
9541 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
9542}
9543
9544/* VFPv3 instructions. */
9545static void
9546do_vfp_sp_const (void)
9547{
9548 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB		 9549 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9550 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 9551}
9552
9553static void
9554do_vfp_dp_const (void)
9555{
9556 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB		 9557 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
9558 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 9559}
9560
9561static void
9562vfp_conv (int srcsize)
9563{
5f1af56b
MGD		 9564 int immbits = srcsize - inst.operands[1].imm;
9565
fa94de6b
RM		 9566 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
9567 {
5f1af56b 9568 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 9569 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD		 9570 inst.error = _("immediate value out of range, expected range [0, 16]");
9571 return;
9572 }
fa94de6b 9573 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD		 9574 {
9575 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 9576 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD		 9577 inst.error = _("immediate value out of range, expected range [1, 32]");
9578 return;
9579 }
9580
5287ad62
JB		 9581 inst.instruction |= (immbits & 1) << 5;
9582 inst.instruction |= (immbits >> 1);
9583}
9584
9585static void
9586do_vfp_sp_conv_16 (void)
9587{
9588 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9589 vfp_conv (16);
9590}
9591
9592static void
9593do_vfp_dp_conv_16 (void)
9594{
9595 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9596 vfp_conv (16);
9597}
9598
9599static void
9600do_vfp_sp_conv_32 (void)
9601{
9602 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
9603 vfp_conv (32);
9604}
9605
9606static void
9607do_vfp_dp_conv_32 (void)
9608{
9609 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
9610 vfp_conv (32);
9611}
c19d1205
ZW		 9612\f
9613/* FPA instructions. Also in a logical order. */
e16bb312 9614
c19d1205
ZW		 9615static void
9616do_fpa_cmp (void)
9617{
9618 inst.instruction |= inst.operands[0].reg << 16;
9619 inst.instruction |= inst.operands[1].reg;
9620}
b99bd4ef
NC		 9621
9622static void
c19d1205 9623do_fpa_ldmstm (void)
b99bd4ef 9624{
c19d1205
ZW		 9625 inst.instruction |= inst.operands[0].reg << 12;
9626 switch (inst.operands[1].imm)
9627 {
9628 case 1: inst.instruction |= CP_T_X; break;
9629 case 2: inst.instruction |= CP_T_Y; break;
9630 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
9631 case 4: break;
9632 default: abort ();
9633 }
b99bd4ef 9634
c19d1205
ZW		 9635 if (inst.instruction & (PRE_INDEX | INDEX_UP))
9636 {
9637 /* The instruction specified "ea" or "fd", so we can only accept
9638 [Rn]{!}. The instruction does not really support stacking or
9639 unstacking, so we have to emulate these by setting appropriate
9640 bits and offsets. */
9641 constraint (inst.reloc.exp.X_op != O_constant
9642 || inst.reloc.exp.X_add_number != 0,
9643 _("this instruction does not support indexing"));
b99bd4ef 9644
c19d1205
ZW		 9645 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
9646 inst.reloc.exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 9647
c19d1205
ZW		 9648 if (!(inst.instruction & INDEX_UP))
9649 inst.reloc.exp.X_add_number = -inst.reloc.exp.X_add_number;
b99bd4ef 9650
c19d1205
ZW		 9651 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
9652 {
9653 inst.operands[2].preind = 0;
9654 inst.operands[2].postind = 1;
9655 }
9656 }
b99bd4ef 9657
c19d1205 9658 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 9659}
c19d1205
ZW		 9660\f
9661/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 9662
c19d1205
ZW		 9663static void
9664do_iwmmxt_tandorc (void)
9665{
9666 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
9667}
b99bd4ef 9668
c19d1205
ZW		 9669static void
9670do_iwmmxt_textrc (void)
9671{
9672 inst.instruction |= inst.operands[0].reg << 12;
9673 inst.instruction |= inst.operands[1].imm;
9674}
b99bd4ef
NC		 9675
9676static void
c19d1205 9677do_iwmmxt_textrm (void)
b99bd4ef 9678{
c19d1205
ZW		 9679 inst.instruction |= inst.operands[0].reg << 12;
9680 inst.instruction |= inst.operands[1].reg << 16;
9681 inst.instruction |= inst.operands[2].imm;
9682}
b99bd4ef 9683
c19d1205
ZW		 9684static void
9685do_iwmmxt_tinsr (void)
9686{
9687 inst.instruction |= inst.operands[0].reg << 16;
9688 inst.instruction |= inst.operands[1].reg << 12;
9689 inst.instruction |= inst.operands[2].imm;
9690}
b99bd4ef 9691
c19d1205
ZW		 9692static void
9693do_iwmmxt_tmia (void)
9694{
9695 inst.instruction |= inst.operands[0].reg << 5;
9696 inst.instruction |= inst.operands[1].reg;
9697 inst.instruction |= inst.operands[2].reg << 12;
9698}
b99bd4ef 9699
c19d1205
ZW		 9700static void
9701do_iwmmxt_waligni (void)
9702{
9703 inst.instruction |= inst.operands[0].reg << 12;
9704 inst.instruction |= inst.operands[1].reg << 16;
9705 inst.instruction |= inst.operands[2].reg;
9706 inst.instruction |= inst.operands[3].imm << 20;
9707}
b99bd4ef 9708
2d447fca
JM		 9709static void
9710do_iwmmxt_wmerge (void)
9711{
9712 inst.instruction |= inst.operands[0].reg << 12;
9713 inst.instruction |= inst.operands[1].reg << 16;
9714 inst.instruction |= inst.operands[2].reg;
9715 inst.instruction |= inst.operands[3].imm << 21;
9716}
9717
c19d1205
ZW		 9718static void
9719do_iwmmxt_wmov (void)
9720{
9721 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9722 inst.instruction |= inst.operands[0].reg << 12;
9723 inst.instruction |= inst.operands[1].reg << 16;
9724 inst.instruction |= inst.operands[1].reg;
9725}
b99bd4ef 9726
c19d1205
ZW		 9727static void
9728do_iwmmxt_wldstbh (void)
9729{
8f06b2d8 9730 int reloc;
c19d1205 9731 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB		 9732 if (thumb_mode)
9733 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
9734 else
9735 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
9736 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC		 9737}
9738
c19d1205
ZW		 9739static void
9740do_iwmmxt_wldstw (void)
9741{
9742 /* RIWR_RIWC clears .isreg for a control register. */
9743 if (!inst.operands[0].isreg)
9744 {
9745 constraint (inst.cond != COND_ALWAYS, BAD_COND);
9746 inst.instruction |= 0xf0000000;
9747 }
b99bd4ef 9748
c19d1205
ZW		 9749 inst.instruction |= inst.operands[0].reg << 12;
9750 encode_arm_cp_address (1, TRUE, TRUE, 0);
9751}
b99bd4ef
NC		 9752
9753static void
c19d1205 9754do_iwmmxt_wldstd (void)
b99bd4ef 9755{
c19d1205 9756 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM		 9757 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
9758 && inst.operands[1].immisreg)
9759 {
9760 inst.instruction &= ~0x1a000ff;
9761 inst.instruction |= (0xf << 28);
9762 if (inst.operands[1].preind)
9763 inst.instruction |= PRE_INDEX;
9764 if (!inst.operands[1].negative)
9765 inst.instruction |= INDEX_UP;
9766 if (inst.operands[1].writeback)
9767 inst.instruction |= WRITE_BACK;
9768 inst.instruction |= inst.operands[1].reg << 16;
9769 inst.instruction |= inst.reloc.exp.X_add_number << 4;
9770 inst.instruction |= inst.operands[1].imm;
9771 }
9772 else
9773 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 9774}
b99bd4ef 9775
c19d1205
ZW		 9776static void
9777do_iwmmxt_wshufh (void)
9778{
9779 inst.instruction |= inst.operands[0].reg << 12;
9780 inst.instruction |= inst.operands[1].reg << 16;
9781 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
9782 inst.instruction |= (inst.operands[2].imm & 0x0f);
9783}
b99bd4ef 9784
c19d1205
ZW		 9785static void
9786do_iwmmxt_wzero (void)
9787{
9788 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9789 inst.instruction |= inst.operands[0].reg;
9790 inst.instruction |= inst.operands[0].reg << 12;
9791 inst.instruction |= inst.operands[0].reg << 16;
9792}
2d447fca
JM		 9793
9794static void
9795do_iwmmxt_wrwrwr_or_imm5 (void)
9796{
9797 if (inst.operands[2].isreg)
9798 do_rd_rn_rm ();
9799 else {
9800 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
9801 _("immediate operand requires iWMMXt2"));
9802 do_rd_rn ();
9803 if (inst.operands[2].imm == 0)
9804 {
9805 switch ((inst.instruction >> 20) & 0xf)
9806 {
9807 case 4:
9808 case 5:
9809 case 6:
5f4273c7 9810 case 7:
2d447fca
JM		 9811 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9812 inst.operands[2].imm = 16;
9813 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
9814 break;
9815 case 8:
9816 case 9:
9817 case 10:
9818 case 11:
9819 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9820 inst.operands[2].imm = 32;
9821 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
9822 break;
9823 case 12:
9824 case 13:
9825 case 14:
9826 case 15:
9827 {
9828 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9829 unsigned long wrn;
9830 wrn = (inst.instruction >> 16) & 0xf;
9831 inst.instruction &= 0xff0fff0f;
9832 inst.instruction |= wrn;
9833 /* Bail out here; the instruction is now assembled. */
9834 return;
9835 }
9836 }
9837 }
9838 /* Map 32 -> 0, etc. */
9839 inst.operands[2].imm &= 0x1f;
9840 inst.instruction |= (0xf << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
9841 }
9842}
c19d1205
ZW		 9843\f
9844/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9845 operations first, then control, shift, and load/store. */
b99bd4ef 9846
c19d1205 9847/* Insns like "foo X,Y,Z". */
b99bd4ef 9848
c19d1205
ZW		 9849static void
9850do_mav_triple (void)
9851{
9852 inst.instruction |= inst.operands[0].reg << 16;
9853 inst.instruction |= inst.operands[1].reg;
9854 inst.instruction |= inst.operands[2].reg << 12;
9855}
b99bd4ef 9856
c19d1205
ZW		 9857/* Insns like "foo W,X,Y,Z".
9858 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 9859
c19d1205
ZW		 9860static void
9861do_mav_quad (void)
9862{
9863 inst.instruction |= inst.operands[0].reg << 5;
9864 inst.instruction |= inst.operands[1].reg << 12;
9865 inst.instruction |= inst.operands[2].reg << 16;
9866 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC		 9867}
9868
c19d1205
ZW		 9869/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9870static void
9871do_mav_dspsc (void)
a737bd4d 9872{
c19d1205
ZW		 9873 inst.instruction |= inst.operands[1].reg << 12;
9874}
a737bd4d 9875
c19d1205
ZW		 9876/* Maverick shift immediate instructions.
9877 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9878 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 9879
c19d1205
ZW		 9880static void
9881do_mav_shift (void)
9882{
9883 int imm = inst.operands[2].imm;
a737bd4d 9884
c19d1205
ZW		 9885 inst.instruction |= inst.operands[0].reg << 12;
9886 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 9887
c19d1205
ZW		 9888 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9889 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9890 Bit 4 should be 0. */
9891 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 9892
c19d1205
ZW		 9893 inst.instruction |= imm;
9894}
9895\f
9896/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 9897
c19d1205
ZW		 9898/* Xscale multiply-accumulate (argument parse)
9899 MIAcc acc0,Rm,Rs
9900 MIAPHcc acc0,Rm,Rs
9901 MIAxycc acc0,Rm,Rs. */
a737bd4d 9902
c19d1205
ZW		 9903static void
9904do_xsc_mia (void)
9905{
9906 inst.instruction |= inst.operands[1].reg;
9907 inst.instruction |= inst.operands[2].reg << 12;
9908}
a737bd4d 9909
c19d1205 9910/* Xscale move-accumulator-register (argument parse)
a737bd4d 9911
c19d1205 9912 MARcc acc0,RdLo,RdHi. */
b99bd4ef 9913
c19d1205
ZW		 9914static void
9915do_xsc_mar (void)
9916{
9917 inst.instruction |= inst.operands[1].reg << 12;
9918 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 9919}
9920
c19d1205 9921/* Xscale move-register-accumulator (argument parse)
b99bd4ef 9922
c19d1205 9923 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC		 9924
9925static void
c19d1205 9926do_xsc_mra (void)
b99bd4ef 9927{
c19d1205
ZW		 9928 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
9929 inst.instruction |= inst.operands[0].reg << 12;
9930 inst.instruction |= inst.operands[1].reg << 16;
9931}
9932\f
9933/* Encoding functions relevant only to Thumb. */
b99bd4ef 9934
c19d1205
ZW		 9935/* inst.operands[i] is a shifted-register operand; encode
9936 it into inst.instruction in the format used by Thumb32. */
9937
9938static void
9939encode_thumb32_shifted_operand (int i)
9940{
9941 unsigned int value = inst.reloc.exp.X_add_number;
9942 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 9943
9c3c69f2
PB		 9944 constraint (inst.operands[i].immisreg,
9945 _("shift by register not allowed in thumb mode"));
c19d1205
ZW		 9946 inst.instruction |= inst.operands[i].reg;
9947 if (shift == SHIFT_RRX)
9948 inst.instruction |= SHIFT_ROR << 4;
9949 else
b99bd4ef 9950 {
c19d1205
ZW		 9951 constraint (inst.reloc.exp.X_op != O_constant,
9952 _("expression too complex"));
9953
9954 constraint (value > 32
9955 || (value == 32 && (shift == SHIFT_LSL
9956 || shift == SHIFT_ROR)),
9957 _("shift expression is too large"));
9958
9959 if (value == 0)
9960 shift = SHIFT_LSL;
9961 else if (value == 32)
9962 value = 0;
9963
9964 inst.instruction |= shift << 4;
9965 inst.instruction |= (value & 0x1c) << 10;
9966 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 9967 }
c19d1205 9968}
b99bd4ef 9969
b99bd4ef 9970
c19d1205
ZW		 9971/* inst.operands[i] was set up by parse_address. Encode it into a
9972 Thumb32 format load or store instruction. Reject forms that cannot
9973 be used with such instructions. If is_t is true, reject forms that
9974 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG		 9975 that cannot be used with a D instruction. If it is a store insn,
9976 reject PC in Rn. */
b99bd4ef 9977
c19d1205
ZW		 9978static void
9979encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
9980{
5be8be5d 9981 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW		 9982
9983 constraint (!inst.operands[i].isreg,
53365c0d 9984 _("Instruction does not support =N addresses"));
b99bd4ef 9985
c19d1205
ZW		 9986 inst.instruction |= inst.operands[i].reg << 16;
9987 if (inst.operands[i].immisreg)
b99bd4ef 9988 {
5be8be5d 9989 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW		 9990 constraint (is_t || is_d, _("cannot use register index with this instruction"));
9991 constraint (inst.operands[i].negative,
9992 _("Thumb does not support negative register indexing"));
9993 constraint (inst.operands[i].postind,
9994 _("Thumb does not support register post-indexing"));
9995 constraint (inst.operands[i].writeback,
9996 _("Thumb does not support register indexing with writeback"));
9997 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
9998 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 9999
f40d1643 10000 inst.instruction |= inst.operands[i].imm;
c19d1205 10001 if (inst.operands[i].shifted)
b99bd4ef 10002 {
c19d1205
ZW		 10003 constraint (inst.reloc.exp.X_op != O_constant,
10004 _("expression too complex"));
9c3c69f2
PB		 10005 constraint (inst.reloc.exp.X_add_number < 0
10006 || inst.reloc.exp.X_add_number > 3,
c19d1205 10007 _("shift out of range"));
9c3c69f2 10008 inst.instruction |= inst.reloc.exp.X_add_number << 4;
c19d1205
ZW		 10009 }
10010 inst.reloc.type = BFD_RELOC_UNUSED;
10011 }
10012 else if (inst.operands[i].preind)
10013 {
5be8be5d 10014 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 10015 constraint (is_t && inst.operands[i].writeback,
c19d1205 10016 _("cannot use writeback with this instruction"));
4755303e
WN		 10017 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
10018 BAD_PC_ADDRESSING);
c19d1205
ZW		 10019
10020 if (is_d)
10021 {
10022 inst.instruction |= 0x01000000;
10023 if (inst.operands[i].writeback)
10024 inst.instruction |= 0x00200000;
b99bd4ef 10025 }
c19d1205 10026 else
b99bd4ef 10027 {
c19d1205
ZW		 10028 inst.instruction |= 0x00000c00;
10029 if (inst.operands[i].writeback)
10030 inst.instruction |= 0x00000100;
b99bd4ef 10031 }
c19d1205 10032 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 10033 }
c19d1205 10034 else if (inst.operands[i].postind)
b99bd4ef 10035 {
9c2799c2 10036 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 10037 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
10038 constraint (is_t, _("cannot use post-indexing with this instruction"));
10039
10040 if (is_d)
10041 inst.instruction |= 0x00200000;
10042 else
10043 inst.instruction |= 0x00000900;
10044 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_IMM;
10045 }
10046 else /* unindexed - only for coprocessor */
10047 inst.error = _("instruction does not accept unindexed addressing");
10048}
10049
10050/* Table of Thumb instructions which exist in both 16- and 32-bit
10051 encodings (the latter only in post-V6T2 cores). The index is the
10052 value used in the insns table below. When there is more than one
10053 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB		 10054 holds variant (1).
10055 Also contains several pseudo-instructions used during relaxation. */
c19d1205 10056#define T16_32_TAB \
21d799b5
NC		 10057 X(_adc, 4140, eb400000), \
10058 X(_adcs, 4140, eb500000), \
10059 X(_add, 1c00, eb000000), \
10060 X(_adds, 1c00, eb100000), \
10061 X(_addi, 0000, f1000000), \
10062 X(_addis, 0000, f1100000), \
10063 X(_add_pc,000f, f20f0000), \
10064 X(_add_sp,000d, f10d0000), \
10065 X(_adr, 000f, f20f0000), \
10066 X(_and, 4000, ea000000), \
10067 X(_ands, 4000, ea100000), \
10068 X(_asr, 1000, fa40f000), \
10069 X(_asrs, 1000, fa50f000), \
10070 X(_b, e000, f000b000), \
10071 X(_bcond, d000, f0008000), \
10072 X(_bic, 4380, ea200000), \
10073 X(_bics, 4380, ea300000), \
10074 X(_cmn, 42c0, eb100f00), \
10075 X(_cmp, 2800, ebb00f00), \
10076 X(_cpsie, b660, f3af8400), \
10077 X(_cpsid, b670, f3af8600), \
10078 X(_cpy, 4600, ea4f0000), \
10079 X(_dec_sp,80dd, f1ad0d00), \
10080 X(_eor, 4040, ea800000), \
10081 X(_eors, 4040, ea900000), \
10082 X(_inc_sp,00dd, f10d0d00), \
10083 X(_ldmia, c800, e8900000), \
10084 X(_ldr, 6800, f8500000), \
10085 X(_ldrb, 7800, f8100000), \
10086 X(_ldrh, 8800, f8300000), \
10087 X(_ldrsb, 5600, f9100000), \
10088 X(_ldrsh, 5e00, f9300000), \
10089 X(_ldr_pc,4800, f85f0000), \
10090 X(_ldr_pc2,4800, f85f0000), \
10091 X(_ldr_sp,9800, f85d0000), \
10092 X(_lsl, 0000, fa00f000), \
10093 X(_lsls, 0000, fa10f000), \
10094 X(_lsr, 0800, fa20f000), \
10095 X(_lsrs, 0800, fa30f000), \
10096 X(_mov, 2000, ea4f0000), \
10097 X(_movs, 2000, ea5f0000), \
10098 X(_mul, 4340, fb00f000), \
10099 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10100 X(_mvn, 43c0, ea6f0000), \
10101 X(_mvns, 43c0, ea7f0000), \
10102 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10103 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10104 X(_orr, 4300, ea400000), \
10105 X(_orrs, 4300, ea500000), \
10106 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10107 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10108 X(_rev, ba00, fa90f080), \
10109 X(_rev16, ba40, fa90f090), \
10110 X(_revsh, bac0, fa90f0b0), \
10111 X(_ror, 41c0, fa60f000), \
10112 X(_rors, 41c0, fa70f000), \
10113 X(_sbc, 4180, eb600000), \
10114 X(_sbcs, 4180, eb700000), \
10115 X(_stmia, c000, e8800000), \
10116 X(_str, 6000, f8400000), \
10117 X(_strb, 7000, f8000000), \
10118 X(_strh, 8000, f8200000), \
10119 X(_str_sp,9000, f84d0000), \
10120 X(_sub, 1e00, eba00000), \
10121 X(_subs, 1e00, ebb00000), \
10122 X(_subi, 8000, f1a00000), \
10123 X(_subis, 8000, f1b00000), \
10124 X(_sxtb, b240, fa4ff080), \
10125 X(_sxth, b200, fa0ff080), \
10126 X(_tst, 4200, ea100f00), \
10127 X(_uxtb, b2c0, fa5ff080), \
10128 X(_uxth, b280, fa1ff080), \
10129 X(_nop, bf00, f3af8000), \
10130 X(_yield, bf10, f3af8001), \
10131 X(_wfe, bf20, f3af8002), \
10132 X(_wfi, bf30, f3af8003), \
53c4b28b 10133 X(_sev, bf40, f3af8004), \
74db7efb
NC		 10134 X(_sevl, bf50, f3af8005), \
10135 X(_udf, de00, f7f0a000)
c19d1205
ZW		 10136
10137/* To catch errors in encoding functions, the codes are all offset by
10138 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10139 as 16-bit instructions. */
21d799b5 10140#define X(a,b,c) T_MNEM##a
c19d1205
ZW		 10141enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
10142#undef X
10143
10144#define X(a,b,c) 0x##b
10145static const unsigned short thumb_op16[] = { T16_32_TAB };
10146#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10147#undef X
10148
10149#define X(a,b,c) 0x##c
10150static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC		 10151#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10152#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW		 10153#undef X
10154#undef T16_32_TAB
10155
10156/* Thumb instruction encoders, in alphabetical order. */
10157
92e90b6e 10158/* ADDW or SUBW. */
c921be7d 10159
92e90b6e
PB		 10160static void
10161do_t_add_sub_w (void)
10162{
10163 int Rd, Rn;
10164
10165 Rd = inst.operands[0].reg;
10166 Rn = inst.operands[1].reg;
10167
539d4391
NC		 10168 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10169 is the SP-{plus,minus}-immediate form of the instruction. */
10170 if (Rn == REG_SP)
10171 constraint (Rd == REG_PC, BAD_PC);
10172 else
10173 reject_bad_reg (Rd);
fdfde340 10174
92e90b6e
PB		 10175 inst.instruction |= (Rn << 16) | (Rd << 8);
10176 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10177}
10178
c19d1205
ZW		 10179/* Parse an add or subtract instruction. We get here with inst.instruction
10180 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10181
10182static void
10183do_t_add_sub (void)
10184{
10185 int Rd, Rs, Rn;
10186
10187 Rd = inst.operands[0].reg;
10188 Rs = (inst.operands[1].present
10189 ? inst.operands[1].reg /* Rd, Rs, foo */
10190 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10191
e07e6e58
NC		 10192 if (Rd == REG_PC)
10193 set_it_insn_type_last ();
10194
c19d1205
ZW		 10195 if (unified_syntax)
10196 {
0110f2b8
PB		 10197 bfd_boolean flags;
10198 bfd_boolean narrow;
10199 int opcode;
10200
10201 flags = (inst.instruction == T_MNEM_adds
10202 || inst.instruction == T_MNEM_subs);
10203 if (flags)
e07e6e58 10204 narrow = !in_it_block ();
0110f2b8 10205 else
e07e6e58 10206 narrow = in_it_block ();
c19d1205 10207 if (!inst.operands[2].isreg)
b99bd4ef 10208 {
16805f35
PB		 10209 int add;
10210
fdfde340
JM		 10211 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10212
16805f35
PB		 10213 add = (inst.instruction == T_MNEM_add
10214 || inst.instruction == T_MNEM_adds);
0110f2b8
PB		 10215 opcode = 0;
10216 if (inst.size_req != 4)
10217 {
0110f2b8 10218 /* Attempt to use a narrow opcode, with relaxation if
477330fc 10219 appropriate. */
0110f2b8
PB		 10220 if (Rd == REG_SP && Rs == REG_SP && !flags)
10221 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
10222 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
10223 opcode = T_MNEM_add_sp;
10224 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
10225 opcode = T_MNEM_add_pc;
10226 else if (Rd <= 7 && Rs <= 7 && narrow)
10227 {
10228 if (flags)
10229 opcode = add ? T_MNEM_addis : T_MNEM_subis;
10230 else
10231 opcode = add ? T_MNEM_addi : T_MNEM_subi;
10232 }
10233 if (opcode)
10234 {
10235 inst.instruction = THUMB_OP16(opcode);
10236 inst.instruction |= (Rd << 4) | Rs;
10237 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10238 if (inst.size_req != 2)
10239 inst.relax = opcode;
10240 }
10241 else
10242 constraint (inst.size_req == 2, BAD_HIREG);
10243 }
10244 if (inst.size_req == 4
10245 || (inst.size_req != 2 && !opcode))
10246 {
efd81785
PB		 10247 if (Rd == REG_PC)
10248 {
fdfde340 10249 constraint (add, BAD_PC);
efd81785
PB		 10250 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
10251 _("only SUBS PC, LR, #const allowed"));
10252 constraint (inst.reloc.exp.X_op != O_constant,
10253 _("expression too complex"));
10254 constraint (inst.reloc.exp.X_add_number < 0
10255 || inst.reloc.exp.X_add_number > 0xff,
10256 _("immediate value out of range"));
10257 inst.instruction = T2_SUBS_PC_LR
10258 | inst.reloc.exp.X_add_number;
10259 inst.reloc.type = BFD_RELOC_UNUSED;
10260 return;
10261 }
10262 else if (Rs == REG_PC)
16805f35
PB		 10263 {
10264 /* Always use addw/subw. */
10265 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
10266 inst.reloc.type = BFD_RELOC_ARM_T32_IMM12;
10267 }
10268 else
10269 {
10270 inst.instruction = THUMB_OP32 (inst.instruction);
10271 inst.instruction = (inst.instruction & 0xe1ffffff)
10272 | 0x10000000;
10273 if (flags)
10274 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10275 else
10276 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_IMM;
10277 }
dc4503c6
PB		 10278 inst.instruction |= Rd << 8;
10279 inst.instruction |= Rs << 16;
0110f2b8 10280 }
b99bd4ef 10281 }
c19d1205
ZW		 10282 else
10283 {
5f4cb198
NC		 10284 unsigned int value = inst.reloc.exp.X_add_number;
10285 unsigned int shift = inst.operands[2].shift_kind;
10286
c19d1205
ZW		 10287 Rn = inst.operands[2].reg;
10288 /* See if we can do this with a 16-bit instruction. */
10289 if (!inst.operands[2].shifted && inst.size_req != 4)
10290 {
e27ec89e
PB		 10291 if (Rd > 7 || Rs > 7 || Rn > 7)
10292 narrow = FALSE;
10293
10294 if (narrow)
c19d1205 10295 {
e27ec89e
PB		 10296 inst.instruction = ((inst.instruction == T_MNEM_adds
10297 || inst.instruction == T_MNEM_add)
c19d1205
ZW		 10298 ? T_OPCODE_ADD_R3
10299 : T_OPCODE_SUB_R3);
10300 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
10301 return;
10302 }
b99bd4ef 10303
7e806470 10304 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 10305 {
7e806470
PB		 10306 /* Thumb-1 cores (except v6-M) require at least one high
10307 register in a narrow non flag setting add. */
10308 if (Rd > 7 || Rn > 7
10309 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
10310 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 10311 {
7e806470
PB		 10312 if (Rd == Rn)
10313 {
10314 Rn = Rs;
10315 Rs = Rd;
10316 }
c19d1205
ZW		 10317 inst.instruction = T_OPCODE_ADD_HI;
10318 inst.instruction |= (Rd & 8) << 4;
10319 inst.instruction |= (Rd & 7);
10320 inst.instruction |= Rn << 3;
10321 return;
10322 }
c19d1205
ZW		 10323 }
10324 }
c921be7d 10325
fdfde340
JM		 10326 constraint (Rd == REG_PC, BAD_PC);
10327 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
10328 constraint (Rs == REG_PC, BAD_PC);
10329 reject_bad_reg (Rn);
10330
c19d1205
ZW		 10331 /* If we get here, it can't be done in 16 bits. */
10332 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
10333 _("shift must be constant"));
10334 inst.instruction = THUMB_OP32 (inst.instruction);
10335 inst.instruction |= Rd << 8;
10336 inst.instruction |= Rs << 16;
5f4cb198
NC		 10337 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
10338 _("shift value over 3 not allowed in thumb mode"));
10339 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
10340 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW		 10341 encode_thumb32_shifted_operand (2);
10342 }
10343 }
10344 else
10345 {
10346 constraint (inst.instruction == T_MNEM_adds
10347 || inst.instruction == T_MNEM_subs,
10348 BAD_THUMB32);
b99bd4ef 10349
c19d1205 10350 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 10351 {
c19d1205
ZW		 10352 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
10353 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
10354 BAD_HIREG);
10355
10356 inst.instruction = (inst.instruction == T_MNEM_add
10357 ? 0x0000 : 0x8000);
10358 inst.instruction |= (Rd << 4) | Rs;
10359 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC		 10360 return;
10361 }
10362
c19d1205
ZW		 10363 Rn = inst.operands[2].reg;
10364 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 10365
c19d1205
ZW		 10366 /* We now have Rd, Rs, and Rn set to registers. */
10367 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 10368 {
c19d1205
ZW		 10369 /* Can't do this for SUB. */
10370 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
10371 inst.instruction = T_OPCODE_ADD_HI;
10372 inst.instruction |= (Rd & 8) << 4;
10373 inst.instruction |= (Rd & 7);
10374 if (Rs == Rd)
10375 inst.instruction |= Rn << 3;
10376 else if (Rn == Rd)
10377 inst.instruction |= Rs << 3;
10378 else
10379 constraint (1, _("dest must overlap one source register"));
10380 }
10381 else
10382 {
10383 inst.instruction = (inst.instruction == T_MNEM_add
10384 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
10385 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 10386 }
b99bd4ef 10387 }
b99bd4ef
NC		 10388}
10389
c19d1205
ZW		 10390static void
10391do_t_adr (void)
10392{
fdfde340
JM		 10393 unsigned Rd;
10394
10395 Rd = inst.operands[0].reg;
10396 reject_bad_reg (Rd);
10397
10398 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB		 10399 {
10400 /* Defer to section relaxation. */
10401 inst.relax = inst.instruction;
10402 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 10403 inst.instruction |= Rd << 4;
0110f2b8
PB		 10404 }
10405 else if (unified_syntax && inst.size_req != 2)
e9f89963 10406 {
0110f2b8 10407 /* Generate a 32-bit opcode. */
e9f89963 10408 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 10409 inst.instruction |= Rd << 8;
e9f89963
PB		 10410 inst.reloc.type = BFD_RELOC_ARM_T32_ADD_PC12;
10411 inst.reloc.pc_rel = 1;
10412 }
10413 else
10414 {
0110f2b8 10415 /* Generate a 16-bit opcode. */
e9f89963
PB		 10416 inst.instruction = THUMB_OP16 (inst.instruction);
10417 inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
10418 inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
10419 inst.reloc.pc_rel = 1;
b99bd4ef 10420
fdfde340 10421 inst.instruction |= Rd << 4;
e9f89963 10422 }
c19d1205 10423}
b99bd4ef 10424
c19d1205
ZW		 10425/* Arithmetic instructions for which there is just one 16-bit
10426 instruction encoding, and it allows only two low registers.
10427 For maximal compatibility with ARM syntax, we allow three register
10428 operands even when Thumb-32 instructions are not available, as long
10429 as the first two are identical. For instance, both "sbc r0,r1" and
10430 "sbc r0,r0,r1" are allowed. */
b99bd4ef 10431static void
c19d1205 10432do_t_arit3 (void)
b99bd4ef 10433{
c19d1205 10434 int Rd, Rs, Rn;
b99bd4ef 10435
c19d1205
ZW		 10436 Rd = inst.operands[0].reg;
10437 Rs = (inst.operands[1].present
10438 ? inst.operands[1].reg /* Rd, Rs, foo */
10439 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10440 Rn = inst.operands[2].reg;
b99bd4ef 10441
fdfde340
JM		 10442 reject_bad_reg (Rd);
10443 reject_bad_reg (Rs);
10444 if (inst.operands[2].isreg)
10445 reject_bad_reg (Rn);
10446
c19d1205 10447 if (unified_syntax)
b99bd4ef 10448 {
c19d1205
ZW		 10449 if (!inst.operands[2].isreg)
10450 {
10451 /* For an immediate, we always generate a 32-bit opcode;
10452 section relaxation will shrink it later if possible. */
10453 inst.instruction = THUMB_OP32 (inst.instruction);
10454 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10455 inst.instruction |= Rd << 8;
10456 inst.instruction |= Rs << 16;
10457 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
10458 }
10459 else
10460 {
e27ec89e
PB		 10461 bfd_boolean narrow;
10462
c19d1205 10463 /* See if we can do this with a 16-bit instruction. */
e27ec89e 10464 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 10465 narrow = !in_it_block ();
e27ec89e 10466 else
e07e6e58 10467 narrow = in_it_block ();
e27ec89e
PB		 10468
10469 if (Rd > 7 || Rn > 7 || Rs > 7)
10470 narrow = FALSE;
10471 if (inst.operands[2].shifted)
10472 narrow = FALSE;
10473 if (inst.size_req == 4)
10474 narrow = FALSE;
10475
10476 if (narrow
c19d1205
ZW		 10477 && Rd == Rs)
10478 {
10479 inst.instruction = THUMB_OP16 (inst.instruction);
10480 inst.instruction |= Rd;
10481 inst.instruction |= Rn << 3;
10482 return;
10483 }
b99bd4ef 10484
c19d1205
ZW		 10485 /* If we get here, it can't be done in 16 bits. */
10486 constraint (inst.operands[2].shifted
10487 && inst.operands[2].immisreg,
10488 _("shift must be constant"));
10489 inst.instruction = THUMB_OP32 (inst.instruction);
10490 inst.instruction |= Rd << 8;
10491 inst.instruction |= Rs << 16;
10492 encode_thumb32_shifted_operand (2);
10493 }
a737bd4d 10494 }
c19d1205 10495 else
b99bd4ef 10496 {
c19d1205
ZW		 10497 /* On its face this is a lie - the instruction does set the
10498 flags. However, the only supported mnemonic in this mode
10499 says it doesn't. */
10500 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 10501
c19d1205
ZW		 10502 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10503 _("unshifted register required"));
10504 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10505 constraint (Rd != Rs,
10506 _("dest and source1 must be the same register"));
a737bd4d 10507
c19d1205
ZW		 10508 inst.instruction = THUMB_OP16 (inst.instruction);
10509 inst.instruction |= Rd;
10510 inst.instruction |= Rn << 3;
b99bd4ef 10511 }
a737bd4d 10512}
b99bd4ef 10513
c19d1205
ZW		 10514/* Similarly, but for instructions where the arithmetic operation is
10515 commutative, so we can allow either of them to be different from
10516 the destination operand in a 16-bit instruction. For instance, all
10517 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10518 accepted. */
10519static void
10520do_t_arit3c (void)
a737bd4d 10521{
c19d1205 10522 int Rd, Rs, Rn;
b99bd4ef 10523
c19d1205
ZW		 10524 Rd = inst.operands[0].reg;
10525 Rs = (inst.operands[1].present
10526 ? inst.operands[1].reg /* Rd, Rs, foo */
10527 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
10528 Rn = inst.operands[2].reg;
c921be7d 10529
fdfde340
JM		 10530 reject_bad_reg (Rd);
10531 reject_bad_reg (Rs);
10532 if (inst.operands[2].isreg)
10533 reject_bad_reg (Rn);
a737bd4d 10534
c19d1205 10535 if (unified_syntax)
a737bd4d 10536 {
c19d1205 10537 if (!inst.operands[2].isreg)
b99bd4ef 10538 {
c19d1205
ZW		 10539 /* For an immediate, we always generate a 32-bit opcode;
10540 section relaxation will shrink it later if possible. */
10541 inst.instruction = THUMB_OP32 (inst.instruction);
10542 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
10543 inst.instruction |= Rd << 8;
10544 inst.instruction |= Rs << 16;
10545 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 10546 }
c19d1205 10547 else
a737bd4d 10548 {
e27ec89e
PB		 10549 bfd_boolean narrow;
10550
c19d1205 10551 /* See if we can do this with a 16-bit instruction. */
e27ec89e 10552 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 10553 narrow = !in_it_block ();
e27ec89e 10554 else
e07e6e58 10555 narrow = in_it_block ();
e27ec89e
PB		 10556
10557 if (Rd > 7 || Rn > 7 || Rs > 7)
10558 narrow = FALSE;
10559 if (inst.operands[2].shifted)
10560 narrow = FALSE;
10561 if (inst.size_req == 4)
10562 narrow = FALSE;
10563
10564 if (narrow)
a737bd4d 10565 {
c19d1205 10566 if (Rd == Rs)
a737bd4d 10567 {
c19d1205
ZW		 10568 inst.instruction = THUMB_OP16 (inst.instruction);
10569 inst.instruction |= Rd;
10570 inst.instruction |= Rn << 3;
10571 return;
a737bd4d 10572 }
c19d1205 10573 if (Rd == Rn)
a737bd4d 10574 {
c19d1205
ZW		 10575 inst.instruction = THUMB_OP16 (inst.instruction);
10576 inst.instruction |= Rd;
10577 inst.instruction |= Rs << 3;
10578 return;
a737bd4d
NC		 10579 }
10580 }
c19d1205
ZW		 10581
10582 /* If we get here, it can't be done in 16 bits. */
10583 constraint (inst.operands[2].shifted
10584 && inst.operands[2].immisreg,
10585 _("shift must be constant"));
10586 inst.instruction = THUMB_OP32 (inst.instruction);
10587 inst.instruction |= Rd << 8;
10588 inst.instruction |= Rs << 16;
10589 encode_thumb32_shifted_operand (2);
a737bd4d 10590 }
b99bd4ef 10591 }
c19d1205
ZW		 10592 else
10593 {
10594 /* On its face this is a lie - the instruction does set the
10595 flags. However, the only supported mnemonic in this mode
10596 says it doesn't. */
10597 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 10598
c19d1205
ZW		 10599 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
10600 _("unshifted register required"));
10601 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
10602
10603 inst.instruction = THUMB_OP16 (inst.instruction);
10604 inst.instruction |= Rd;
10605
10606 if (Rd == Rs)
10607 inst.instruction |= Rn << 3;
10608 else if (Rd == Rn)
10609 inst.instruction |= Rs << 3;
10610 else
10611 constraint (1, _("dest must overlap one source register"));
10612 }
a737bd4d
NC		 10613}
10614
c19d1205
ZW		 10615static void
10616do_t_bfc (void)
a737bd4d 10617{
fdfde340 10618 unsigned Rd;
c19d1205
ZW		 10619 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
10620 constraint (msb > 32, _("bit-field extends past end of register"));
10621 /* The instruction encoding stores the LSB and MSB,
10622 not the LSB and width. */
fdfde340
JM		 10623 Rd = inst.operands[0].reg;
10624 reject_bad_reg (Rd);
10625 inst.instruction |= Rd << 8;
c19d1205
ZW		 10626 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
10627 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
10628 inst.instruction |= msb - 1;
b99bd4ef
NC		 10629}
10630
c19d1205
ZW		 10631static void
10632do_t_bfi (void)
b99bd4ef 10633{
fdfde340 10634 int Rd, Rn;
c19d1205 10635 unsigned int msb;
b99bd4ef 10636
fdfde340
JM		 10637 Rd = inst.operands[0].reg;
10638 reject_bad_reg (Rd);
10639
c19d1205
ZW		 10640 /* #0 in second position is alternative syntax for bfc, which is
10641 the same instruction but with REG_PC in the Rm field. */
10642 if (!inst.operands[1].isreg)
fdfde340
JM		 10643 Rn = REG_PC;
10644 else
10645 {
10646 Rn = inst.operands[1].reg;
10647 reject_bad_reg (Rn);
10648 }
b99bd4ef 10649
c19d1205
ZW		 10650 msb = inst.operands[2].imm + inst.operands[3].imm;
10651 constraint (msb > 32, _("bit-field extends past end of register"));
10652 /* The instruction encoding stores the LSB and MSB,
10653 not the LSB and width. */
fdfde340
JM		 10654 inst.instruction |= Rd << 8;
10655 inst.instruction |= Rn << 16;
c19d1205
ZW		 10656 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10657 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10658 inst.instruction |= msb - 1;
b99bd4ef
NC		 10659}
10660
c19d1205
ZW		 10661static void
10662do_t_bfx (void)
b99bd4ef 10663{
fdfde340
JM		 10664 unsigned Rd, Rn;
10665
10666 Rd = inst.operands[0].reg;
10667 Rn = inst.operands[1].reg;
10668
10669 reject_bad_reg (Rd);
10670 reject_bad_reg (Rn);
10671
c19d1205
ZW		 10672 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
10673 _("bit-field extends past end of register"));
fdfde340
JM		 10674 inst.instruction |= Rd << 8;
10675 inst.instruction |= Rn << 16;
c19d1205
ZW		 10676 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
10677 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
10678 inst.instruction |= inst.operands[3].imm - 1;
10679}
b99bd4ef 10680
c19d1205
ZW		 10681/* ARM V5 Thumb BLX (argument parse)
10682 BLX <target_addr> which is BLX(1)
10683 BLX <Rm> which is BLX(2)
10684 Unfortunately, there are two different opcodes for this mnemonic.
10685 So, the insns[].value is not used, and the code here zaps values
10686 into inst.instruction.
b99bd4ef 10687
c19d1205
ZW		 10688 ??? How to take advantage of the additional two bits of displacement
10689 available in Thumb32 mode? Need new relocation? */
b99bd4ef 10690
c19d1205
ZW		 10691static void
10692do_t_blx (void)
10693{
e07e6e58
NC		 10694 set_it_insn_type_last ();
10695
c19d1205 10696 if (inst.operands[0].isreg)
fdfde340
JM		 10697 {
10698 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
10699 /* We have a register, so this is BLX(2). */
10700 inst.instruction |= inst.operands[0].reg << 3;
10701 }
b99bd4ef
NC		 10702 else
10703 {
c19d1205 10704 /* No register. This must be BLX(1). */
2fc8bdac 10705 inst.instruction = 0xf000e800;
0855e32b 10706 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC		 10707 }
10708}
10709
c19d1205
ZW		 10710static void
10711do_t_branch (void)
b99bd4ef 10712{
0110f2b8 10713 int opcode;
dfa9f0d5 10714 int cond;
9ae92b05 10715 int reloc;
dfa9f0d5 10716
e07e6e58
NC		 10717 cond = inst.cond;
10718 set_it_insn_type (IF_INSIDE_IT_LAST_INSN);
10719
10720 if (in_it_block ())
dfa9f0d5
PB		 10721 {
10722 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 10723 branches. */
dfa9f0d5 10724 cond = COND_ALWAYS;
dfa9f0d5
PB		 10725 }
10726 else
10727 cond = inst.cond;
10728
10729 if (cond != COND_ALWAYS)
0110f2b8
PB		 10730 opcode = T_MNEM_bcond;
10731 else
10732 opcode = inst.instruction;
10733
12d6b0b7
RS		 10734 if (unified_syntax
10735 && (inst.size_req == 4
10960bfb
PB		 10736 || (inst.size_req != 2
10737 && (inst.operands[0].hasreloc
10738 || inst.reloc.exp.X_op == O_constant))))
c19d1205 10739 {
0110f2b8 10740 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 10741 if (cond == COND_ALWAYS)
9ae92b05 10742 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW		 10743 else
10744 {
9c2799c2 10745 gas_assert (cond != 0xF);
dfa9f0d5 10746 inst.instruction |= cond << 22;
9ae92b05 10747 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW		 10748 }
10749 }
b99bd4ef
NC		 10750 else
10751 {
0110f2b8 10752 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 10753 if (cond == COND_ALWAYS)
9ae92b05 10754 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 10755 else
b99bd4ef 10756 {
dfa9f0d5 10757 inst.instruction |= cond << 8;
9ae92b05 10758 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 10759 }
0110f2b8
PB		 10760 /* Allow section relaxation. */
10761 if (unified_syntax && inst.size_req != 2)
10762 inst.relax = opcode;
b99bd4ef 10763 }
9ae92b05 10764 inst.reloc.type = reloc;
c19d1205 10765 inst.reloc.pc_rel = 1;
b99bd4ef
NC		 10766}
10767
8884b720 10768/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 10769 between the two is the maximum immediate allowed - which is passed in
8884b720 10770 RANGE. */
b99bd4ef 10771static void
8884b720 10772do_t_bkpt_hlt1 (int range)
b99bd4ef 10773{
dfa9f0d5
PB		 10774 constraint (inst.cond != COND_ALWAYS,
10775 _("instruction is always unconditional"));
c19d1205 10776 if (inst.operands[0].present)
b99bd4ef 10777 {
8884b720 10778 constraint (inst.operands[0].imm > range,
c19d1205
ZW		 10779 _("immediate value out of range"));
10780 inst.instruction |= inst.operands[0].imm;
b99bd4ef 10781 }
8884b720
MGD		 10782
10783 set_it_insn_type (NEUTRAL_IT_INSN);
10784}
10785
10786static void
10787do_t_hlt (void)
10788{
10789 do_t_bkpt_hlt1 (63);
10790}
10791
10792static void
10793do_t_bkpt (void)
10794{
10795 do_t_bkpt_hlt1 (255);
b99bd4ef
NC		 10796}
10797
10798static void
c19d1205 10799do_t_branch23 (void)
b99bd4ef 10800{
e07e6e58 10801 set_it_insn_type_last ();
0855e32b 10802 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 10803
0855e32b
NS		 10804 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10805 this file. We used to simply ignore the PLT reloc type here --
10806 the branch encoding is now needed to deal with TLSCALL relocs.
10807 So if we see a PLT reloc now, put it back to how it used to be to
10808 keep the preexisting behaviour. */
10809 if (inst.reloc.type == BFD_RELOC_ARM_PLT32)
10810 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 10811
4343666d 10812#if defined(OBJ_COFF)
c19d1205
ZW		 10813 /* If the destination of the branch is a defined symbol which does not have
10814 the THUMB_FUNC attribute, then we must be calling a function which has
10815 the (interfacearm) attribute. We look for the Thumb entry point to that
10816 function and change the branch to refer to that function instead. */
10817 if ( inst.reloc.exp.X_op == O_symbol
10818 && inst.reloc.exp.X_add_symbol != NULL
10819 && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
10820 && ! THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
10821 inst.reloc.exp.X_add_symbol =
10822 find_real_start (inst.reloc.exp.X_add_symbol);
4343666d 10823#endif
90e4755a
RE		 10824}
10825
10826static void
c19d1205 10827do_t_bx (void)
90e4755a 10828{
e07e6e58 10829 set_it_insn_type_last ();
c19d1205
ZW		 10830 inst.instruction |= inst.operands[0].reg << 3;
10831 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10832 should cause the alignment to be checked once it is known. This is
10833 because BX PC only works if the instruction is word aligned. */
10834}
90e4755a 10835
c19d1205
ZW		 10836static void
10837do_t_bxj (void)
10838{
fdfde340 10839 int Rm;
90e4755a 10840
e07e6e58 10841 set_it_insn_type_last ();
fdfde340
JM		 10842 Rm = inst.operands[0].reg;
10843 reject_bad_reg (Rm);
10844 inst.instruction |= Rm << 16;
90e4755a
RE		 10845}
10846
10847static void
c19d1205 10848do_t_clz (void)
90e4755a 10849{
fdfde340
JM		 10850 unsigned Rd;
10851 unsigned Rm;
10852
10853 Rd = inst.operands[0].reg;
10854 Rm = inst.operands[1].reg;
10855
10856 reject_bad_reg (Rd);
10857 reject_bad_reg (Rm);
10858
10859 inst.instruction |= Rd << 8;
10860 inst.instruction |= Rm << 16;
10861 inst.instruction |= Rm;
c19d1205 10862}
90e4755a 10863
dfa9f0d5
PB		 10864static void
10865do_t_cps (void)
10866{
e07e6e58 10867 set_it_insn_type (OUTSIDE_IT_INSN);
dfa9f0d5
PB		 10868 inst.instruction |= inst.operands[0].imm;
10869}
10870
c19d1205
ZW		 10871static void
10872do_t_cpsi (void)
10873{
e07e6e58 10874 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205 10875 if (unified_syntax
62b3e311
PB		 10876 && (inst.operands[1].present || inst.size_req == 4)
10877 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 10878 {
c19d1205
ZW		 10879 unsigned int imod = (inst.instruction & 0x0030) >> 4;
10880 inst.instruction = 0xf3af8000;
10881 inst.instruction |= imod << 9;
10882 inst.instruction |= inst.operands[0].imm << 5;
10883 if (inst.operands[1].present)
10884 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 10885 }
c19d1205 10886 else
90e4755a 10887 {
62b3e311
PB		 10888 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
10889 && (inst.operands[0].imm & 4),
10890 _("selected processor does not support 'A' form "
10891 "of this instruction"));
10892 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW		 10893 _("Thumb does not support the 2-argument "
10894 "form of this instruction"));
10895 inst.instruction |= inst.operands[0].imm;
90e4755a 10896 }
90e4755a
RE		 10897}
10898
c19d1205
ZW		 10899/* THUMB CPY instruction (argument parse). */
10900
90e4755a 10901static void
c19d1205 10902do_t_cpy (void)
90e4755a 10903{
c19d1205 10904 if (inst.size_req == 4)
90e4755a 10905 {
c19d1205
ZW		 10906 inst.instruction = THUMB_OP32 (T_MNEM_mov);
10907 inst.instruction |= inst.operands[0].reg << 8;
10908 inst.instruction |= inst.operands[1].reg;
90e4755a 10909 }
c19d1205 10910 else
90e4755a 10911 {
c19d1205
ZW		 10912 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
10913 inst.instruction |= (inst.operands[0].reg & 0x7);
10914 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 10915 }
90e4755a
RE		 10916}
10917
90e4755a 10918static void
25fe350b 10919do_t_cbz (void)
90e4755a 10920{
e07e6e58 10921 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW		 10922 constraint (inst.operands[0].reg > 7, BAD_HIREG);
10923 inst.instruction |= inst.operands[0].reg;
10924 inst.reloc.pc_rel = 1;
10925 inst.reloc.type = BFD_RELOC_THUMB_PCREL_BRANCH7;
10926}
90e4755a 10927
62b3e311
PB		 10928static void
10929do_t_dbg (void)
10930{
10931 inst.instruction |= inst.operands[0].imm;
10932}
10933
10934static void
10935do_t_div (void)
10936{
fdfde340
JM		 10937 unsigned Rd, Rn, Rm;
10938
10939 Rd = inst.operands[0].reg;
10940 Rn = (inst.operands[1].present
10941 ? inst.operands[1].reg : Rd);
10942 Rm = inst.operands[2].reg;
10943
10944 reject_bad_reg (Rd);
10945 reject_bad_reg (Rn);
10946 reject_bad_reg (Rm);
10947
10948 inst.instruction |= Rd << 8;
10949 inst.instruction |= Rn << 16;
10950 inst.instruction |= Rm;
62b3e311
PB		 10951}
10952
c19d1205
ZW		 10953static void
10954do_t_hint (void)
10955{
10956 if (unified_syntax && inst.size_req == 4)
10957 inst.instruction = THUMB_OP32 (inst.instruction);
10958 else
10959 inst.instruction = THUMB_OP16 (inst.instruction);
10960}
90e4755a 10961
c19d1205
ZW		 10962static void
10963do_t_it (void)
10964{
10965 unsigned int cond = inst.operands[0].imm;
e27ec89e 10966
e07e6e58
NC		 10967 set_it_insn_type (IT_INSN);
10968 now_it.mask = (inst.instruction & 0xf) | 0x10;
10969 now_it.cc = cond;
5a01bb1d 10970 now_it.warn_deprecated = FALSE;
e27ec89e
PB		 10971
10972 /* If the condition is a negative condition, invert the mask. */
c19d1205 10973 if ((cond & 0x1) == 0x0)
90e4755a 10974 {
c19d1205 10975 unsigned int mask = inst.instruction & 0x000f;
90e4755a 10976
c19d1205 10977 if ((mask & 0x7) == 0)
5a01bb1d
MGD		 10978 {
10979 /* No conversion needed. */
10980 now_it.block_length = 1;
10981 }
c19d1205 10982 else if ((mask & 0x3) == 0)
5a01bb1d
MGD		 10983 {
10984 mask ^= 0x8;
10985 now_it.block_length = 2;
10986 }
e27ec89e 10987 else if ((mask & 0x1) == 0)
5a01bb1d
MGD		 10988 {
10989 mask ^= 0xC;
10990 now_it.block_length = 3;
10991 }
c19d1205 10992 else
5a01bb1d
MGD		 10993 {
10994 mask ^= 0xE;
10995 now_it.block_length = 4;
10996 }
90e4755a 10997
e27ec89e
PB		 10998 inst.instruction &= 0xfff0;
10999 inst.instruction |= mask;
c19d1205 11000 }
90e4755a 11001
c19d1205
ZW		 11002 inst.instruction |= cond << 4;
11003}
90e4755a 11004
3c707909
PB		 11005/* Helper function used for both push/pop and ldm/stm. */
11006static void
11007encode_thumb2_ldmstm (int base, unsigned mask, bfd_boolean writeback)
11008{
11009 bfd_boolean load;
11010
11011 load = (inst.instruction & (1 << 20)) != 0;
11012
11013 if (mask & (1 << 13))
11014 inst.error = _("SP not allowed in register list");
1e5b0379
NC		 11015
11016 if ((mask & (1 << base)) != 0
11017 && writeback)
11018 inst.error = _("having the base register in the register list when "
11019 "using write back is UNPREDICTABLE");
11020
3c707909
PB		 11021 if (load)
11022 {
e07e6e58 11023 if (mask & (1 << 15))
477330fc
RM		 11024 {
11025 if (mask & (1 << 14))
11026 inst.error = _("LR and PC should not both be in register list");
11027 else
11028 set_it_insn_type_last ();
11029 }
3c707909
PB		 11030 }
11031 else
11032 {
11033 if (mask & (1 << 15))
11034 inst.error = _("PC not allowed in register list");
3c707909
PB		 11035 }
11036
11037 if ((mask & (mask - 1)) == 0)
11038 {
11039 /* Single register transfers implemented as str/ldr. */
11040 if (writeback)
11041 {
11042 if (inst.instruction & (1 << 23))
11043 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
11044 else
11045 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
11046 }
11047 else
11048 {
11049 if (inst.instruction & (1 << 23))
11050 inst.instruction = 0x00800000; /* ia -> [base] */
11051 else
11052 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
11053 }
11054
11055 inst.instruction |= 0xf8400000;
11056 if (load)
11057 inst.instruction |= 0x00100000;
11058
5f4273c7 11059 mask = ffs (mask) - 1;
3c707909
PB		 11060 mask <<= 12;
11061 }
11062 else if (writeback)
11063 inst.instruction |= WRITE_BACK;
11064
11065 inst.instruction |= mask;
11066 inst.instruction |= base << 16;
11067}
11068
c19d1205
ZW		 11069static void
11070do_t_ldmstm (void)
11071{
11072 /* This really doesn't seem worth it. */
11073 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
11074 _("expression too complex"));
11075 constraint (inst.operands[1].writeback,
11076 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 11077
c19d1205
ZW		 11078 if (unified_syntax)
11079 {
3c707909
PB		 11080 bfd_boolean narrow;
11081 unsigned mask;
11082
11083 narrow = FALSE;
c19d1205
ZW		 11084 /* See if we can use a 16-bit instruction. */
11085 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
11086 && inst.size_req != 4
3c707909 11087 && !(inst.operands[1].imm & ~0xff))
90e4755a 11088 {
3c707909 11089 mask = 1 << inst.operands[0].reg;
90e4755a 11090
eab4f823 11091 if (inst.operands[0].reg <= 7)
90e4755a 11092 {
3c707909 11093 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD		 11094 ? inst.operands[0].writeback
11095 : (inst.operands[0].writeback
11096 == !(inst.operands[1].imm & mask)))
477330fc 11097 {
eab4f823
MGD		 11098 if (inst.instruction == T_MNEM_stmia
11099 && (inst.operands[1].imm & mask)
11100 && (inst.operands[1].imm & (mask - 1)))
11101 as_warn (_("value stored for r%d is UNKNOWN"),
11102 inst.operands[0].reg);
3c707909 11103
eab4f823
MGD		 11104 inst.instruction = THUMB_OP16 (inst.instruction);
11105 inst.instruction |= inst.operands[0].reg << 8;
11106 inst.instruction |= inst.operands[1].imm;
11107 narrow = TRUE;
11108 }
11109 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11110 {
11111 /* This means 1 register in reg list one of 3 situations:
11112 1. Instruction is stmia, but without writeback.
11113 2. lmdia without writeback, but with Rn not in
477330fc 11114 reglist.
eab4f823
MGD		 11115 3. ldmia with writeback, but with Rn in reglist.
11116 Case 3 is UNPREDICTABLE behaviour, so we handle
11117 case 1 and 2 which can be converted into a 16-bit
11118 str or ldr. The SP cases are handled below. */
11119 unsigned long opcode;
11120 /* First, record an error for Case 3. */
11121 if (inst.operands[1].imm & mask
11122 && inst.operands[0].writeback)
fa94de6b 11123 inst.error =
eab4f823
MGD		 11124 _("having the base register in the register list when "
11125 "using write back is UNPREDICTABLE");
fa94de6b
RM		 11126
11127 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD		 11128 : T_MNEM_ldr);
11129 inst.instruction = THUMB_OP16 (opcode);
11130 inst.instruction |= inst.operands[0].reg << 3;
11131 inst.instruction |= (ffs (inst.operands[1].imm)-1);
11132 narrow = TRUE;
11133 }
90e4755a 11134 }
eab4f823 11135 else if (inst.operands[0] .reg == REG_SP)
90e4755a 11136 {
eab4f823
MGD		 11137 if (inst.operands[0].writeback)
11138 {
fa94de6b 11139 inst.instruction =
eab4f823 11140 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 11141 ? T_MNEM_push : T_MNEM_pop);
eab4f823 11142 inst.instruction |= inst.operands[1].imm;
477330fc 11143 narrow = TRUE;
eab4f823
MGD		 11144 }
11145 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
11146 {
fa94de6b 11147 inst.instruction =
eab4f823 11148 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 11149 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 11150 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 11151 narrow = TRUE;
eab4f823 11152 }
90e4755a 11153 }
3c707909
PB		 11154 }
11155
11156 if (!narrow)
11157 {
c19d1205
ZW		 11158 if (inst.instruction < 0xffff)
11159 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 11160
5f4273c7
NC		 11161 encode_thumb2_ldmstm (inst.operands[0].reg, inst.operands[1].imm,
11162 inst.operands[0].writeback);
90e4755a
RE		 11163 }
11164 }
c19d1205 11165 else
90e4755a 11166 {
c19d1205
ZW		 11167 constraint (inst.operands[0].reg > 7
11168 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB		 11169 constraint (inst.instruction != T_MNEM_ldmia
11170 && inst.instruction != T_MNEM_stmia,
11171 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 11172 if (inst.instruction == T_MNEM_stmia)
f03698e6 11173 {
c19d1205
ZW		 11174 if (!inst.operands[0].writeback)
11175 as_warn (_("this instruction will write back the base register"));
11176 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
11177 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 11178 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 11179 inst.operands[0].reg);
f03698e6 11180 }
c19d1205 11181 else
90e4755a 11182 {
c19d1205
ZW		 11183 if (!inst.operands[0].writeback
11184 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
11185 as_warn (_("this instruction will write back the base register"));
11186 else if (inst.operands[0].writeback
11187 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
11188 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE		 11189 }
11190
c19d1205
ZW		 11191 inst.instruction = THUMB_OP16 (inst.instruction);
11192 inst.instruction |= inst.operands[0].reg << 8;
11193 inst.instruction |= inst.operands[1].imm;
11194 }
11195}
e28cd48c 11196
c19d1205
ZW		 11197static void
11198do_t_ldrex (void)
11199{
11200 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
11201 || inst.operands[1].postind || inst.operands[1].writeback
11202 || inst.operands[1].immisreg || inst.operands[1].shifted
11203 || inst.operands[1].negative,
01cfc07f 11204 BAD_ADDR_MODE);
e28cd48c 11205
5be8be5d
DG		 11206 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
11207
c19d1205
ZW		 11208 inst.instruction |= inst.operands[0].reg << 12;
11209 inst.instruction |= inst.operands[1].reg << 16;
11210 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
11211}
e28cd48c 11212
c19d1205
ZW		 11213static void
11214do_t_ldrexd (void)
11215{
11216 if (!inst.operands[1].present)
1cac9012 11217 {
c19d1205
ZW		 11218 constraint (inst.operands[0].reg == REG_LR,
11219 _("r14 not allowed as first register "
11220 "when second register is omitted"));
11221 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 11222 }
c19d1205
ZW		 11223 constraint (inst.operands[0].reg == inst.operands[1].reg,
11224 BAD_OVERLAP);
b99bd4ef 11225
c19d1205
ZW		 11226 inst.instruction |= inst.operands[0].reg << 12;
11227 inst.instruction |= inst.operands[1].reg << 8;
11228 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 11229}
11230
11231static void
c19d1205 11232do_t_ldst (void)
b99bd4ef 11233{
0110f2b8
PB		 11234 unsigned long opcode;
11235 int Rn;
11236
e07e6e58
NC		 11237 if (inst.operands[0].isreg
11238 && !inst.operands[0].preind
11239 && inst.operands[0].reg == REG_PC)
11240 set_it_insn_type_last ();
11241
0110f2b8 11242 opcode = inst.instruction;
c19d1205 11243 if (unified_syntax)
b99bd4ef 11244 {
53365c0d
PB		 11245 if (!inst.operands[1].isreg)
11246 {
11247 if (opcode <= 0xffff)
11248 inst.instruction = THUMB_OP32 (opcode);
8335d6aa 11249 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
53365c0d
PB		 11250 return;
11251 }
0110f2b8
PB		 11252 if (inst.operands[1].isreg
11253 && !inst.operands[1].writeback
c19d1205
ZW		 11254 && !inst.operands[1].shifted && !inst.operands[1].postind
11255 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB		 11256 && opcode <= 0xffff
11257 && inst.size_req != 4)
c19d1205 11258 {
0110f2b8
PB		 11259 /* Insn may have a 16-bit form. */
11260 Rn = inst.operands[1].reg;
11261 if (inst.operands[1].immisreg)
11262 {
11263 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 11264 /* [Rn, Rik] */
0110f2b8
PB		 11265 if (Rn <= 7 && inst.operands[1].imm <= 7)
11266 goto op16;
5be8be5d
DG		 11267 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
11268 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB		 11269 }
11270 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
11271 && opcode != T_MNEM_ldrsb)
11272 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
11273 || (Rn == REG_SP && opcode == T_MNEM_str))
11274 {
11275 /* [Rn, #const] */
11276 if (Rn > 7)
11277 {
11278 if (Rn == REG_PC)
11279 {
11280 if (inst.reloc.pc_rel)
11281 opcode = T_MNEM_ldr_pc2;
11282 else
11283 opcode = T_MNEM_ldr_pc;
11284 }
11285 else
11286 {
11287 if (opcode == T_MNEM_ldr)
11288 opcode = T_MNEM_ldr_sp;
11289 else
11290 opcode = T_MNEM_str_sp;
11291 }
11292 inst.instruction = inst.operands[0].reg << 8;
11293 }
11294 else
11295 {
11296 inst.instruction = inst.operands[0].reg;
11297 inst.instruction |= inst.operands[1].reg << 3;
11298 }
11299 inst.instruction |= THUMB_OP16 (opcode);
11300 if (inst.size_req == 2)
11301 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11302 else
11303 inst.relax = opcode;
11304 return;
11305 }
c19d1205 11306 }
0110f2b8 11307 /* Definitely a 32-bit variant. */
5be8be5d 11308
8d67f500
NC		 11309 /* Warning for Erratum 752419. */
11310 if (opcode == T_MNEM_ldr
11311 && inst.operands[0].reg == REG_SP
11312 && inst.operands[1].writeback == 1
11313 && !inst.operands[1].immisreg)
11314 {
11315 if (no_cpu_selected ()
11316 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM		 11317 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
11318 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC		 11319 as_warn (_("This instruction may be unpredictable "
11320 "if executed on M-profile cores "
11321 "with interrupts enabled."));
11322 }
11323
5be8be5d 11324 /* Do some validations regarding addressing modes. */
1be5fd2e 11325 if (inst.operands[1].immisreg)
5be8be5d
DG		 11326 reject_bad_reg (inst.operands[1].imm);
11327
1be5fd2e
NC		 11328 constraint (inst.operands[1].writeback == 1
11329 && inst.operands[0].reg == inst.operands[1].reg,
11330 BAD_OVERLAP);
11331
0110f2b8 11332 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW		 11333 inst.instruction |= inst.operands[0].reg << 12;
11334 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 11335 check_ldr_r15_aligned ();
b99bd4ef
NC		 11336 return;
11337 }
11338
c19d1205
ZW		 11339 constraint (inst.operands[0].reg > 7, BAD_HIREG);
11340
11341 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 11342 {
c19d1205
ZW		 11343 /* Only [Rn,Rm] is acceptable. */
11344 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
11345 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
11346 || inst.operands[1].postind || inst.operands[1].shifted
11347 || inst.operands[1].negative,
11348 _("Thumb does not support this addressing mode"));
11349 inst.instruction = THUMB_OP16 (inst.instruction);
11350 goto op16;
b99bd4ef 11351 }
5f4273c7 11352
c19d1205
ZW		 11353 inst.instruction = THUMB_OP16 (inst.instruction);
11354 if (!inst.operands[1].isreg)
8335d6aa 11355 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
c19d1205 11356 return;
b99bd4ef 11357
c19d1205
ZW		 11358 constraint (!inst.operands[1].preind
11359 || inst.operands[1].shifted
11360 || inst.operands[1].writeback,
11361 _("Thumb does not support this addressing mode"));
11362 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 11363 {
c19d1205
ZW		 11364 constraint (inst.instruction & 0x0600,
11365 _("byte or halfword not valid for base register"));
11366 constraint (inst.operands[1].reg == REG_PC
11367 && !(inst.instruction & THUMB_LOAD_BIT),
11368 _("r15 based store not allowed"));
11369 constraint (inst.operands[1].immisreg,
11370 _("invalid base register for register offset"));
b99bd4ef 11371
c19d1205
ZW		 11372 if (inst.operands[1].reg == REG_PC)
11373 inst.instruction = T_OPCODE_LDR_PC;
11374 else if (inst.instruction & THUMB_LOAD_BIT)
11375 inst.instruction = T_OPCODE_LDR_SP;
11376 else
11377 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 11378
c19d1205
ZW		 11379 inst.instruction |= inst.operands[0].reg << 8;
11380 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11381 return;
11382 }
90e4755a 11383
c19d1205
ZW		 11384 constraint (inst.operands[1].reg > 7, BAD_HIREG);
11385 if (!inst.operands[1].immisreg)
11386 {
11387 /* Immediate offset. */
11388 inst.instruction |= inst.operands[0].reg;
11389 inst.instruction |= inst.operands[1].reg << 3;
11390 inst.reloc.type = BFD_RELOC_ARM_THUMB_OFFSET;
11391 return;
11392 }
90e4755a 11393
c19d1205
ZW		 11394 /* Register offset. */
11395 constraint (inst.operands[1].imm > 7, BAD_HIREG);
11396 constraint (inst.operands[1].negative,
11397 _("Thumb does not support this addressing mode"));
90e4755a 11398
c19d1205
ZW		 11399 op16:
11400 switch (inst.instruction)
11401 {
11402 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
11403 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
11404 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
11405 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
11406 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
11407 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
11408 case 0x5600 /* ldrsb */:
11409 case 0x5e00 /* ldrsh */: break;
11410 default: abort ();
11411 }
90e4755a 11412
c19d1205
ZW		 11413 inst.instruction |= inst.operands[0].reg;
11414 inst.instruction |= inst.operands[1].reg << 3;
11415 inst.instruction |= inst.operands[1].imm << 6;
11416}
90e4755a 11417
c19d1205
ZW		 11418static void
11419do_t_ldstd (void)
11420{
11421 if (!inst.operands[1].present)
b99bd4ef 11422 {
c19d1205
ZW		 11423 inst.operands[1].reg = inst.operands[0].reg + 1;
11424 constraint (inst.operands[0].reg == REG_LR,
11425 _("r14 not allowed here"));
bd340a04 11426 constraint (inst.operands[0].reg == REG_R12,
477330fc 11427 _("r12 not allowed here"));
b99bd4ef 11428 }
bd340a04
MGD		 11429
11430 if (inst.operands[2].writeback
11431 && (inst.operands[0].reg == inst.operands[2].reg
11432 || inst.operands[1].reg == inst.operands[2].reg))
11433 as_warn (_("base register written back, and overlaps "
477330fc 11434 "one of transfer registers"));
bd340a04 11435
c19d1205
ZW		 11436 inst.instruction |= inst.operands[0].reg << 12;
11437 inst.instruction |= inst.operands[1].reg << 8;
11438 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC		 11439}
11440
c19d1205
ZW		 11441static void
11442do_t_ldstt (void)
11443{
11444 inst.instruction |= inst.operands[0].reg << 12;
11445 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
11446}
a737bd4d 11447
b99bd4ef 11448static void
c19d1205 11449do_t_mla (void)
b99bd4ef 11450{
fdfde340 11451 unsigned Rd, Rn, Rm, Ra;
c921be7d 11452
fdfde340
JM		 11453 Rd = inst.operands[0].reg;
11454 Rn = inst.operands[1].reg;
11455 Rm = inst.operands[2].reg;
11456 Ra = inst.operands[3].reg;
11457
11458 reject_bad_reg (Rd);
11459 reject_bad_reg (Rn);
11460 reject_bad_reg (Rm);
11461 reject_bad_reg (Ra);
11462
11463 inst.instruction |= Rd << 8;
11464 inst.instruction |= Rn << 16;
11465 inst.instruction |= Rm;
11466 inst.instruction |= Ra << 12;
c19d1205 11467}
b99bd4ef 11468
c19d1205
ZW		 11469static void
11470do_t_mlal (void)
11471{
fdfde340
JM		 11472 unsigned RdLo, RdHi, Rn, Rm;
11473
11474 RdLo = inst.operands[0].reg;
11475 RdHi = inst.operands[1].reg;
11476 Rn = inst.operands[2].reg;
11477 Rm = inst.operands[3].reg;
11478
11479 reject_bad_reg (RdLo);
11480 reject_bad_reg (RdHi);
11481 reject_bad_reg (Rn);
11482 reject_bad_reg (Rm);
11483
11484 inst.instruction |= RdLo << 12;
11485 inst.instruction |= RdHi << 8;
11486 inst.instruction |= Rn << 16;
11487 inst.instruction |= Rm;
c19d1205 11488}
b99bd4ef 11489
c19d1205
ZW		 11490static void
11491do_t_mov_cmp (void)
11492{
fdfde340
JM		 11493 unsigned Rn, Rm;
11494
11495 Rn = inst.operands[0].reg;
11496 Rm = inst.operands[1].reg;
11497
e07e6e58
NC		 11498 if (Rn == REG_PC)
11499 set_it_insn_type_last ();
11500
c19d1205 11501 if (unified_syntax)
b99bd4ef 11502 {
c19d1205
ZW		 11503 int r0off = (inst.instruction == T_MNEM_mov
11504 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 11505 unsigned long opcode;
3d388997
PB		 11506 bfd_boolean narrow;
11507 bfd_boolean low_regs;
11508
fdfde340 11509 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 11510 opcode = inst.instruction;
e07e6e58 11511 if (in_it_block ())
0110f2b8 11512 narrow = opcode != T_MNEM_movs;
3d388997 11513 else
0110f2b8 11514 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB		 11515 if (inst.size_req == 4
11516 || inst.operands[1].shifted)
11517 narrow = FALSE;
11518
efd81785
PB		 11519 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11520 if (opcode == T_MNEM_movs && inst.operands[1].isreg
11521 && !inst.operands[1].shifted
fdfde340
JM		 11522 && Rn == REG_PC
11523 && Rm == REG_LR)
efd81785
PB		 11524 {
11525 inst.instruction = T2_SUBS_PC_LR;
11526 return;
11527 }
11528
fdfde340
JM		 11529 if (opcode == T_MNEM_cmp)
11530 {
11531 constraint (Rn == REG_PC, BAD_PC);
94206790
MM		 11532 if (narrow)
11533 {
11534 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11535 but valid. */
11536 warn_deprecated_sp (Rm);
11537 /* R15 was documented as a valid choice for Rm in ARMv6,
11538 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11539 tools reject R15, so we do too. */
11540 constraint (Rm == REG_PC, BAD_PC);
11541 }
11542 else
11543 reject_bad_reg (Rm);
fdfde340
JM		 11544 }
11545 else if (opcode == T_MNEM_mov
11546 || opcode == T_MNEM_movs)
11547 {
11548 if (inst.operands[1].isreg)
11549 {
11550 if (opcode == T_MNEM_movs)
11551 {
11552 reject_bad_reg (Rn);
11553 reject_bad_reg (Rm);
11554 }
76fa04a4
MGD		 11555 else if (narrow)
11556 {
11557 /* This is mov.n. */
11558 if ((Rn == REG_SP || Rn == REG_PC)
11559 && (Rm == REG_SP || Rm == REG_PC))
11560 {
5c3696f8 11561 as_tsktsk (_("Use of r%u as a source register is "
76fa04a4
MGD		 11562 "deprecated when r%u is the destination "
11563 "register."), Rm, Rn);
11564 }
11565 }
11566 else
11567 {
11568 /* This is mov.w. */
11569 constraint (Rn == REG_PC, BAD_PC);
11570 constraint (Rm == REG_PC, BAD_PC);
11571 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
11572 }
fdfde340
JM		 11573 }
11574 else
11575 reject_bad_reg (Rn);
11576 }
11577
c19d1205
ZW		 11578 if (!inst.operands[1].isreg)
11579 {
0110f2b8 11580 /* Immediate operand. */
e07e6e58 11581 if (!in_it_block () && opcode == T_MNEM_mov)
0110f2b8
PB		 11582 narrow = 0;
11583 if (low_regs && narrow)
11584 {
11585 inst.instruction = THUMB_OP16 (opcode);
fdfde340 11586 inst.instruction |= Rn << 8;
0110f2b8
PB		 11587 if (inst.size_req == 2)
11588 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11589 else
11590 inst.relax = opcode;
11591 }
11592 else
11593 {
11594 inst.instruction = THUMB_OP32 (inst.instruction);
11595 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 11596 inst.instruction |= Rn << r0off;
0110f2b8
PB		 11597 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
11598 }
c19d1205 11599 }
728ca7c9
PB		 11600 else if (inst.operands[1].shifted && inst.operands[1].immisreg
11601 && (inst.instruction == T_MNEM_mov
11602 || inst.instruction == T_MNEM_movs))
11603 {
11604 /* Register shifts are encoded as separate shift instructions. */
11605 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
11606
e07e6e58 11607 if (in_it_block ())
728ca7c9
PB		 11608 narrow = !flags;
11609 else
11610 narrow = flags;
11611
11612 if (inst.size_req == 4)
11613 narrow = FALSE;
11614
11615 if (!low_regs || inst.operands[1].imm > 7)
11616 narrow = FALSE;
11617
fdfde340 11618 if (Rn != Rm)
728ca7c9
PB		 11619 narrow = FALSE;
11620
11621 switch (inst.operands[1].shift_kind)
11622 {
11623 case SHIFT_LSL:
11624 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
11625 break;
11626 case SHIFT_ASR:
11627 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
11628 break;
11629 case SHIFT_LSR:
11630 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
11631 break;
11632 case SHIFT_ROR:
11633 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
11634 break;
11635 default:
5f4273c7 11636 abort ();
728ca7c9
PB		 11637 }
11638
11639 inst.instruction = opcode;
11640 if (narrow)
11641 {
fdfde340 11642 inst.instruction |= Rn;
728ca7c9
PB		 11643 inst.instruction |= inst.operands[1].imm << 3;
11644 }
11645 else
11646 {
11647 if (flags)
11648 inst.instruction |= CONDS_BIT;
11649
fdfde340
JM		 11650 inst.instruction |= Rn << 8;
11651 inst.instruction |= Rm << 16;
728ca7c9
PB		 11652 inst.instruction |= inst.operands[1].imm;
11653 }
11654 }
3d388997 11655 else if (!narrow)
c19d1205 11656 {
728ca7c9
PB		 11657 /* Some mov with immediate shift have narrow variants.
11658 Register shifts are handled above. */
11659 if (low_regs && inst.operands[1].shifted
11660 && (inst.instruction == T_MNEM_mov
11661 || inst.instruction == T_MNEM_movs))
11662 {
e07e6e58 11663 if (in_it_block ())
728ca7c9
PB		 11664 narrow = (inst.instruction == T_MNEM_mov);
11665 else
11666 narrow = (inst.instruction == T_MNEM_movs);
11667 }
11668
11669 if (narrow)
11670 {
11671 switch (inst.operands[1].shift_kind)
11672 {
11673 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
11674 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
11675 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
11676 default: narrow = FALSE; break;
11677 }
11678 }
11679
11680 if (narrow)
11681 {
fdfde340
JM		 11682 inst.instruction |= Rn;
11683 inst.instruction |= Rm << 3;
728ca7c9
PB		 11684 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
11685 }
11686 else
11687 {
11688 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11689 inst.instruction |= Rn << r0off;
728ca7c9
PB		 11690 encode_thumb32_shifted_operand (1);
11691 }
c19d1205
ZW		 11692 }
11693 else
11694 switch (inst.instruction)
11695 {
11696 case T_MNEM_mov:
837b3435 11697 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD		 11698 results. Don't allow this. */
11699 if (low_regs)
11700 {
11701 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
11702 "MOV Rd, Rs with two low registers is not "
11703 "permitted on this architecture");
fa94de6b 11704 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD		 11705 arm_ext_v6);
11706 }
11707
c19d1205 11708 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM		 11709 inst.instruction |= (Rn & 0x8) << 4;
11710 inst.instruction |= (Rn & 0x7);
11711 inst.instruction |= Rm << 3;
c19d1205 11712 break;
b99bd4ef 11713
c19d1205
ZW		 11714 case T_MNEM_movs:
11715 /* We know we have low registers at this point.
941a8a52
MGD		 11716 Generate LSLS Rd, Rs, #0. */
11717 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM		 11718 inst.instruction |= Rn;
11719 inst.instruction |= Rm << 3;
c19d1205
ZW		 11720 break;
11721
11722 case T_MNEM_cmp:
3d388997 11723 if (low_regs)
c19d1205
ZW		 11724 {
11725 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM		 11726 inst.instruction |= Rn;
11727 inst.instruction |= Rm << 3;
c19d1205
ZW		 11728 }
11729 else
11730 {
11731 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM		 11732 inst.instruction |= (Rn & 0x8) << 4;
11733 inst.instruction |= (Rn & 0x7);
11734 inst.instruction |= Rm << 3;
c19d1205
ZW		 11735 }
11736 break;
11737 }
b99bd4ef
NC		 11738 return;
11739 }
11740
c19d1205 11741 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC		 11742
11743 /* PR 10443: Do not silently ignore shifted operands. */
11744 constraint (inst.operands[1].shifted,
11745 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11746
c19d1205 11747 if (inst.operands[1].isreg)
b99bd4ef 11748 {
fdfde340 11749 if (Rn < 8 && Rm < 8)
b99bd4ef 11750 {
c19d1205
ZW		 11751 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11752 since a MOV instruction produces unpredictable results. */
11753 if (inst.instruction == T_OPCODE_MOV_I8)
11754 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 11755 else
c19d1205 11756 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 11757
fdfde340
JM		 11758 inst.instruction |= Rn;
11759 inst.instruction |= Rm << 3;
b99bd4ef
NC		 11760 }
11761 else
11762 {
c19d1205
ZW		 11763 if (inst.instruction == T_OPCODE_MOV_I8)
11764 inst.instruction = T_OPCODE_MOV_HR;
11765 else
11766 inst.instruction = T_OPCODE_CMP_HR;
11767 do_t_cpy ();
b99bd4ef
NC		 11768 }
11769 }
c19d1205 11770 else
b99bd4ef 11771 {
fdfde340 11772 constraint (Rn > 7,
c19d1205 11773 _("only lo regs allowed with immediate"));
fdfde340 11774 inst.instruction |= Rn << 8;
c19d1205
ZW		 11775 inst.reloc.type = BFD_RELOC_ARM_THUMB_IMM;
11776 }
11777}
b99bd4ef 11778
c19d1205
ZW		 11779static void
11780do_t_mov16 (void)
11781{
fdfde340 11782 unsigned Rd;
b6895b4f
PB		 11783 bfd_vma imm;
11784 bfd_boolean top;
11785
11786 top = (inst.instruction & 0x00800000) != 0;
11787 if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
11788 {
11789 constraint (top, _(":lower16: not allowed this instruction"));
11790 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
11791 }
11792 else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
11793 {
11794 constraint (!top, _(":upper16: not allowed this instruction"));
11795 inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
11796 }
11797
fdfde340
JM		 11798 Rd = inst.operands[0].reg;
11799 reject_bad_reg (Rd);
11800
11801 inst.instruction |= Rd << 8;
b6895b4f
PB		 11802 if (inst.reloc.type == BFD_RELOC_UNUSED)
11803 {
11804 imm = inst.reloc.exp.X_add_number;
11805 inst.instruction |= (imm & 0xf000) << 4;
11806 inst.instruction |= (imm & 0x0800) << 15;
11807 inst.instruction |= (imm & 0x0700) << 4;
11808 inst.instruction |= (imm & 0x00ff);
11809 }
c19d1205 11810}
b99bd4ef 11811
c19d1205
ZW		 11812static void
11813do_t_mvn_tst (void)
11814{
fdfde340 11815 unsigned Rn, Rm;
c921be7d 11816
fdfde340
JM		 11817 Rn = inst.operands[0].reg;
11818 Rm = inst.operands[1].reg;
11819
11820 if (inst.instruction == T_MNEM_cmp
11821 || inst.instruction == T_MNEM_cmn)
11822 constraint (Rn == REG_PC, BAD_PC);
11823 else
11824 reject_bad_reg (Rn);
11825 reject_bad_reg (Rm);
11826
c19d1205
ZW		 11827 if (unified_syntax)
11828 {
11829 int r0off = (inst.instruction == T_MNEM_mvn
11830 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB		 11831 bfd_boolean narrow;
11832
11833 if (inst.size_req == 4
11834 || inst.instruction > 0xffff
11835 || inst.operands[1].shifted
fdfde340 11836 || Rn > 7 || Rm > 7)
3d388997 11837 narrow = FALSE;
fe8b4cc3
KT		 11838 else if (inst.instruction == T_MNEM_cmn
11839 || inst.instruction == T_MNEM_tst)
3d388997
PB		 11840 narrow = TRUE;
11841 else if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 11842 narrow = !in_it_block ();
3d388997 11843 else
e07e6e58 11844 narrow = in_it_block ();
3d388997 11845
c19d1205 11846 if (!inst.operands[1].isreg)
b99bd4ef 11847 {
c19d1205
ZW		 11848 /* For an immediate, we always generate a 32-bit opcode;
11849 section relaxation will shrink it later if possible. */
11850 if (inst.instruction < 0xffff)
11851 inst.instruction = THUMB_OP32 (inst.instruction);
11852 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 11853 inst.instruction |= Rn << r0off;
c19d1205 11854 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11855 }
c19d1205 11856 else
b99bd4ef 11857 {
c19d1205 11858 /* See if we can do this with a 16-bit instruction. */
3d388997 11859 if (narrow)
b99bd4ef 11860 {
c19d1205 11861 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11862 inst.instruction |= Rn;
11863 inst.instruction |= Rm << 3;
b99bd4ef 11864 }
c19d1205 11865 else
b99bd4ef 11866 {
c19d1205
ZW		 11867 constraint (inst.operands[1].shifted
11868 && inst.operands[1].immisreg,
11869 _("shift must be constant"));
11870 if (inst.instruction < 0xffff)
11871 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11872 inst.instruction |= Rn << r0off;
c19d1205 11873 encode_thumb32_shifted_operand (1);
b99bd4ef 11874 }
b99bd4ef
NC		 11875 }
11876 }
11877 else
11878 {
c19d1205
ZW		 11879 constraint (inst.instruction > 0xffff
11880 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
11881 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
11882 _("unshifted register required"));
fdfde340 11883 constraint (Rn > 7 || Rm > 7,
c19d1205 11884 BAD_HIREG);
b99bd4ef 11885
c19d1205 11886 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 11887 inst.instruction |= Rn;
11888 inst.instruction |= Rm << 3;
b99bd4ef 11889 }
b99bd4ef
NC		 11890}
11891
b05fe5cf 11892static void
c19d1205 11893do_t_mrs (void)
b05fe5cf 11894{
fdfde340 11895 unsigned Rd;
037e8744
JB		 11896
11897 if (do_vfp_nsyn_mrs () == SUCCESS)
11898 return;
11899
90ec0d68
MGD		 11900 Rd = inst.operands[0].reg;
11901 reject_bad_reg (Rd);
11902 inst.instruction |= Rd << 8;
11903
11904 if (inst.operands[1].isreg)
62b3e311 11905 {
90ec0d68
MGD		 11906 unsigned br = inst.operands[1].reg;
11907 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
11908 as_bad (_("bad register for mrs"));
11909
11910 inst.instruction |= br & (0xf << 16);
11911 inst.instruction |= (br & 0x300) >> 4;
11912 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB		 11913 }
11914 else
11915 {
90ec0d68 11916 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 11917
d2cd1205 11918 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC		 11919 {
11920 /* PR gas/12698: The constraint is only applied for m_profile.
11921 If the user has specified -march=all, we want to ignore it as
11922 we are building for any CPU type, including non-m variants. */
11923 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11924 constraint ((flags != 0) && m_profile, _("selected processor does "
11925 "not support requested special purpose register"));
11926 }
90ec0d68 11927 else
d2cd1205
JB		 11928 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11929 devices). */
11930 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
11931 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 11932
90ec0d68
MGD		 11933 inst.instruction |= (flags & SPSR_BIT) >> 2;
11934 inst.instruction |= inst.operands[1].imm & 0xff;
11935 inst.instruction |= 0xf0000;
11936 }
c19d1205 11937}
b05fe5cf 11938
c19d1205
ZW		 11939static void
11940do_t_msr (void)
11941{
62b3e311 11942 int flags;
fdfde340 11943 unsigned Rn;
62b3e311 11944
037e8744
JB		 11945 if (do_vfp_nsyn_msr () == SUCCESS)
11946 return;
11947
c19d1205
ZW		 11948 constraint (!inst.operands[1].isreg,
11949 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD		 11950
11951 if (inst.operands[0].isreg)
11952 flags = (int)(inst.operands[0].reg);
11953 else
11954 flags = inst.operands[0].imm;
11955
d2cd1205 11956 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 11957 {
d2cd1205
JB		 11958 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
11959
1a43faaf 11960 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM		 11961 If the user has specified -march=all, we want to ignore it as
11962 we are building for any CPU type, including non-m variants. */
1a43faaf
NC		 11963 bfd_boolean m_profile = selected_cpu.core != arm_arch_any.core;
11964 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM		 11965 && (bits & ~(PSR_s | PSR_f)) != 0)
11966 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
11967 && bits != PSR_f)) && m_profile,
11968 _("selected processor does not support requested special "
11969 "purpose register"));
62b3e311
PB		 11970 }
11971 else
d2cd1205
JB		 11972 constraint ((flags & 0xff) != 0, _("selected processor does not support "
11973 "requested special purpose register"));
c921be7d 11974
fdfde340
JM		 11975 Rn = inst.operands[1].reg;
11976 reject_bad_reg (Rn);
11977
62b3e311 11978 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD		 11979 inst.instruction |= (flags & 0xf0000) >> 8;
11980 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 11981 inst.instruction |= (flags & 0xff);
fdfde340 11982 inst.instruction |= Rn << 16;
c19d1205 11983}
b05fe5cf 11984
c19d1205
ZW		 11985static void
11986do_t_mul (void)
11987{
17828f45 11988 bfd_boolean narrow;
fdfde340 11989 unsigned Rd, Rn, Rm;
17828f45 11990
c19d1205
ZW		 11991 if (!inst.operands[2].present)
11992 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 11993
fdfde340
JM		 11994 Rd = inst.operands[0].reg;
11995 Rn = inst.operands[1].reg;
11996 Rm = inst.operands[2].reg;
11997
17828f45 11998 if (unified_syntax)
b05fe5cf 11999 {
17828f45 12000 if (inst.size_req == 4
fdfde340
JM		 12001 || (Rd != Rn
12002 && Rd != Rm)
12003 || Rn > 7
12004 || Rm > 7)
17828f45
JM		 12005 narrow = FALSE;
12006 else if (inst.instruction == T_MNEM_muls)
e07e6e58 12007 narrow = !in_it_block ();
17828f45 12008 else
e07e6e58 12009 narrow = in_it_block ();
b05fe5cf 12010 }
c19d1205 12011 else
b05fe5cf 12012 {
17828f45 12013 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 12014 constraint (Rn > 7 || Rm > 7,
c19d1205 12015 BAD_HIREG);
17828f45
JM		 12016 narrow = TRUE;
12017 }
b05fe5cf 12018
17828f45
JM		 12019 if (narrow)
12020 {
12021 /* 16-bit MULS/Conditional MUL. */
c19d1205 12022 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 12023 inst.instruction |= Rd;
b05fe5cf 12024
fdfde340
JM		 12025 if (Rd == Rn)
12026 inst.instruction |= Rm << 3;
12027 else if (Rd == Rm)
12028 inst.instruction |= Rn << 3;
c19d1205
ZW		 12029 else
12030 constraint (1, _("dest must overlap one source register"));
12031 }
17828f45
JM		 12032 else
12033 {
e07e6e58
NC		 12034 constraint (inst.instruction != T_MNEM_mul,
12035 _("Thumb-2 MUL must not set flags"));
17828f45
JM		 12036 /* 32-bit MUL. */
12037 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12038 inst.instruction |= Rd << 8;
12039 inst.instruction |= Rn << 16;
12040 inst.instruction |= Rm << 0;
12041
12042 reject_bad_reg (Rd);
12043 reject_bad_reg (Rn);
12044 reject_bad_reg (Rm);
17828f45 12045 }
c19d1205 12046}
b05fe5cf 12047
c19d1205
ZW		 12048static void
12049do_t_mull (void)
12050{
fdfde340 12051 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 12052
fdfde340
JM		 12053 RdLo = inst.operands[0].reg;
12054 RdHi = inst.operands[1].reg;
12055 Rn = inst.operands[2].reg;
12056 Rm = inst.operands[3].reg;
12057
12058 reject_bad_reg (RdLo);
12059 reject_bad_reg (RdHi);
12060 reject_bad_reg (Rn);
12061 reject_bad_reg (Rm);
12062
12063 inst.instruction |= RdLo << 12;
12064 inst.instruction |= RdHi << 8;
12065 inst.instruction |= Rn << 16;
12066 inst.instruction |= Rm;
12067
12068 if (RdLo == RdHi)
c19d1205
ZW		 12069 as_tsktsk (_("rdhi and rdlo must be different"));
12070}
b05fe5cf 12071
c19d1205
ZW		 12072static void
12073do_t_nop (void)
12074{
e07e6e58
NC		 12075 set_it_insn_type (NEUTRAL_IT_INSN);
12076
c19d1205
ZW		 12077 if (unified_syntax)
12078 {
12079 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 12080 {
c19d1205
ZW		 12081 inst.instruction = THUMB_OP32 (inst.instruction);
12082 inst.instruction |= inst.operands[0].imm;
12083 }
12084 else
12085 {
bc2d1808
NC		 12086 /* PR9722: Check for Thumb2 availability before
12087 generating a thumb2 nop instruction. */
afa62d5e 12088 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC		 12089 {
12090 inst.instruction = THUMB_OP16 (inst.instruction);
12091 inst.instruction |= inst.operands[0].imm << 4;
12092 }
12093 else
12094 inst.instruction = 0x46c0;
c19d1205
ZW		 12095 }
12096 }
12097 else
12098 {
12099 constraint (inst.operands[0].present,
12100 _("Thumb does not support NOP with hints"));
12101 inst.instruction = 0x46c0;
12102 }
12103}
b05fe5cf 12104
c19d1205
ZW		 12105static void
12106do_t_neg (void)
12107{
12108 if (unified_syntax)
12109 {
3d388997
PB		 12110 bfd_boolean narrow;
12111
12112 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 12113 narrow = !in_it_block ();
3d388997 12114 else
e07e6e58 12115 narrow = in_it_block ();
3d388997
PB		 12116 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12117 narrow = FALSE;
12118 if (inst.size_req == 4)
12119 narrow = FALSE;
12120
12121 if (!narrow)
c19d1205
ZW		 12122 {
12123 inst.instruction = THUMB_OP32 (inst.instruction);
12124 inst.instruction |= inst.operands[0].reg << 8;
12125 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW		 12126 }
12127 else
12128 {
c19d1205
ZW		 12129 inst.instruction = THUMB_OP16 (inst.instruction);
12130 inst.instruction |= inst.operands[0].reg;
12131 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW		 12132 }
12133 }
12134 else
12135 {
c19d1205
ZW		 12136 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
12137 BAD_HIREG);
12138 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
12139
12140 inst.instruction = THUMB_OP16 (inst.instruction);
12141 inst.instruction |= inst.operands[0].reg;
12142 inst.instruction |= inst.operands[1].reg << 3;
12143 }
12144}
12145
1c444d06
JM		 12146static void
12147do_t_orn (void)
12148{
12149 unsigned Rd, Rn;
12150
12151 Rd = inst.operands[0].reg;
12152 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
12153
fdfde340
JM		 12154 reject_bad_reg (Rd);
12155 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12156 reject_bad_reg (Rn);
12157
1c444d06
JM		 12158 inst.instruction |= Rd << 8;
12159 inst.instruction |= Rn << 16;
12160
12161 if (!inst.operands[2].isreg)
12162 {
12163 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12164 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12165 }
12166 else
12167 {
12168 unsigned Rm;
12169
12170 Rm = inst.operands[2].reg;
fdfde340 12171 reject_bad_reg (Rm);
1c444d06
JM		 12172
12173 constraint (inst.operands[2].shifted
12174 && inst.operands[2].immisreg,
12175 _("shift must be constant"));
12176 encode_thumb32_shifted_operand (2);
12177 }
12178}
12179
c19d1205
ZW		 12180static void
12181do_t_pkhbt (void)
12182{
fdfde340
JM		 12183 unsigned Rd, Rn, Rm;
12184
12185 Rd = inst.operands[0].reg;
12186 Rn = inst.operands[1].reg;
12187 Rm = inst.operands[2].reg;
12188
12189 reject_bad_reg (Rd);
12190 reject_bad_reg (Rn);
12191 reject_bad_reg (Rm);
12192
12193 inst.instruction |= Rd << 8;
12194 inst.instruction |= Rn << 16;
12195 inst.instruction |= Rm;
c19d1205
ZW		 12196 if (inst.operands[3].present)
12197 {
12198 unsigned int val = inst.reloc.exp.X_add_number;
12199 constraint (inst.reloc.exp.X_op != O_constant,
12200 _("expression too complex"));
12201 inst.instruction |= (val & 0x1c) << 10;
12202 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 12203 }
c19d1205 12204}
b05fe5cf 12205
c19d1205
ZW		 12206static void
12207do_t_pkhtb (void)
12208{
12209 if (!inst.operands[3].present)
1ef52f49
NC		 12210 {
12211 unsigned Rtmp;
12212
12213 inst.instruction &= ~0x00000020;
12214
12215 /* PR 10168. Swap the Rm and Rn registers. */
12216 Rtmp = inst.operands[1].reg;
12217 inst.operands[1].reg = inst.operands[2].reg;
12218 inst.operands[2].reg = Rtmp;
12219 }
c19d1205 12220 do_t_pkhbt ();
b05fe5cf
ZW		 12221}
12222
c19d1205
ZW		 12223static void
12224do_t_pld (void)
12225{
fdfde340
JM		 12226 if (inst.operands[0].immisreg)
12227 reject_bad_reg (inst.operands[0].imm);
12228
c19d1205
ZW		 12229 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
12230}
b05fe5cf 12231
c19d1205
ZW		 12232static void
12233do_t_push_pop (void)
b99bd4ef 12234{
e9f89963 12235 unsigned mask;
5f4273c7 12236
c19d1205
ZW		 12237 constraint (inst.operands[0].writeback,
12238 _("push/pop do not support {reglist}^"));
12239 constraint (inst.reloc.type != BFD_RELOC_UNUSED,
12240 _("expression too complex"));
b99bd4ef 12241
e9f89963 12242 mask = inst.operands[0].imm;
d3bfe16e 12243 if (inst.size_req != 4 && (mask & ~0xff) == 0)
3c707909 12244 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
d3bfe16e
JB		 12245 else if (inst.size_req != 4
12246 && (mask & ~0xff) == (1 << (inst.instruction == T_MNEM_push
12247 ? REG_LR : REG_PC)))
b99bd4ef 12248 {
c19d1205
ZW		 12249 inst.instruction = THUMB_OP16 (inst.instruction);
12250 inst.instruction |= THUMB_PP_PC_LR;
3c707909 12251 inst.instruction |= mask & 0xff;
c19d1205
ZW		 12252 }
12253 else if (unified_syntax)
12254 {
3c707909 12255 inst.instruction = THUMB_OP32 (inst.instruction);
5f4273c7 12256 encode_thumb2_ldmstm (13, mask, TRUE);
c19d1205
ZW		 12257 }
12258 else
12259 {
12260 inst.error = _("invalid register list to push/pop instruction");
12261 return;
12262 }
c19d1205 12263}
b99bd4ef 12264
c19d1205
ZW		 12265static void
12266do_t_rbit (void)
12267{
fdfde340
JM		 12268 unsigned Rd, Rm;
12269
12270 Rd = inst.operands[0].reg;
12271 Rm = inst.operands[1].reg;
12272
12273 reject_bad_reg (Rd);
12274 reject_bad_reg (Rm);
12275
12276 inst.instruction |= Rd << 8;
12277 inst.instruction |= Rm << 16;
12278 inst.instruction |= Rm;
c19d1205 12279}
b99bd4ef 12280
c19d1205
ZW		 12281static void
12282do_t_rev (void)
12283{
fdfde340
JM		 12284 unsigned Rd, Rm;
12285
12286 Rd = inst.operands[0].reg;
12287 Rm = inst.operands[1].reg;
12288
12289 reject_bad_reg (Rd);
12290 reject_bad_reg (Rm);
12291
12292 if (Rd <= 7 && Rm <= 7
c19d1205
ZW		 12293 && inst.size_req != 4)
12294 {
12295 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 12296 inst.instruction |= Rd;
12297 inst.instruction |= Rm << 3;
c19d1205
ZW		 12298 }
12299 else if (unified_syntax)
12300 {
12301 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12302 inst.instruction |= Rd << 8;
12303 inst.instruction |= Rm << 16;
12304 inst.instruction |= Rm;
c19d1205
ZW		 12305 }
12306 else
12307 inst.error = BAD_HIREG;
12308}
b99bd4ef 12309
1c444d06
JM		 12310static void
12311do_t_rrx (void)
12312{
12313 unsigned Rd, Rm;
12314
12315 Rd = inst.operands[0].reg;
12316 Rm = inst.operands[1].reg;
12317
fdfde340
JM		 12318 reject_bad_reg (Rd);
12319 reject_bad_reg (Rm);
c921be7d 12320
1c444d06
JM		 12321 inst.instruction |= Rd << 8;
12322 inst.instruction |= Rm;
12323}
12324
c19d1205
ZW		 12325static void
12326do_t_rsb (void)
12327{
fdfde340 12328 unsigned Rd, Rs;
b99bd4ef 12329
c19d1205
ZW		 12330 Rd = inst.operands[0].reg;
12331 Rs = (inst.operands[1].present
12332 ? inst.operands[1].reg /* Rd, Rs, foo */
12333 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 12334
fdfde340
JM		 12335 reject_bad_reg (Rd);
12336 reject_bad_reg (Rs);
12337 if (inst.operands[2].isreg)
12338 reject_bad_reg (inst.operands[2].reg);
12339
c19d1205
ZW		 12340 inst.instruction |= Rd << 8;
12341 inst.instruction |= Rs << 16;
12342 if (!inst.operands[2].isreg)
12343 {
026d3abb
PB		 12344 bfd_boolean narrow;
12345
12346 if ((inst.instruction & 0x00100000) != 0)
e07e6e58 12347 narrow = !in_it_block ();
026d3abb 12348 else
e07e6e58 12349 narrow = in_it_block ();
026d3abb
PB		 12350
12351 if (Rd > 7 || Rs > 7)
12352 narrow = FALSE;
12353
12354 if (inst.size_req == 4 || !unified_syntax)
12355 narrow = FALSE;
12356
12357 if (inst.reloc.exp.X_op != O_constant
12358 || inst.reloc.exp.X_add_number != 0)
12359 narrow = FALSE;
12360
12361 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 12362 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB		 12363 if (narrow)
12364 {
12365 inst.reloc.type = BFD_RELOC_UNUSED;
12366 inst.instruction = THUMB_OP16 (T_MNEM_negs);
12367 inst.instruction |= Rs << 3;
12368 inst.instruction |= Rd;
12369 }
12370 else
12371 {
12372 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
12373 inst.reloc.type = BFD_RELOC_ARM_T32_IMMEDIATE;
12374 }
c19d1205
ZW		 12375 }
12376 else
12377 encode_thumb32_shifted_operand (2);
12378}
b99bd4ef 12379
c19d1205
ZW		 12380static void
12381do_t_setend (void)
12382{
12e37cbc
MGD		 12383 if (warn_on_deprecated
12384 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 12385 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 12386
e07e6e58 12387 set_it_insn_type (OUTSIDE_IT_INSN);
c19d1205
ZW		 12388 if (inst.operands[0].imm)
12389 inst.instruction |= 0x8;
12390}
b99bd4ef 12391
c19d1205
ZW		 12392static void
12393do_t_shift (void)
12394{
12395 if (!inst.operands[1].present)
12396 inst.operands[1].reg = inst.operands[0].reg;
12397
12398 if (unified_syntax)
12399 {
3d388997
PB		 12400 bfd_boolean narrow;
12401 int shift_kind;
12402
12403 switch (inst.instruction)
12404 {
12405 case T_MNEM_asr:
12406 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
12407 case T_MNEM_lsl:
12408 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
12409 case T_MNEM_lsr:
12410 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
12411 case T_MNEM_ror:
12412 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
12413 default: abort ();
12414 }
12415
12416 if (THUMB_SETS_FLAGS (inst.instruction))
e07e6e58 12417 narrow = !in_it_block ();
3d388997 12418 else
e07e6e58 12419 narrow = in_it_block ();
3d388997
PB		 12420 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
12421 narrow = FALSE;
12422 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
12423 narrow = FALSE;
12424 if (inst.operands[2].isreg
12425 && (inst.operands[1].reg != inst.operands[0].reg
12426 || inst.operands[2].reg > 7))
12427 narrow = FALSE;
12428 if (inst.size_req == 4)
12429 narrow = FALSE;
12430
fdfde340
JM		 12431 reject_bad_reg (inst.operands[0].reg);
12432 reject_bad_reg (inst.operands[1].reg);
c921be7d 12433
3d388997 12434 if (!narrow)
c19d1205
ZW		 12435 {
12436 if (inst.operands[2].isreg)
b99bd4ef 12437 {
fdfde340 12438 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW		 12439 inst.instruction = THUMB_OP32 (inst.instruction);
12440 inst.instruction |= inst.operands[0].reg << 8;
12441 inst.instruction |= inst.operands[1].reg << 16;
12442 inst.instruction |= inst.operands[2].reg;
94342ec3
NC		 12443
12444 /* PR 12854: Error on extraneous shifts. */
12445 constraint (inst.operands[2].shifted,
12446 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 12447 }
12448 else
12449 {
12450 inst.operands[1].shifted = 1;
3d388997 12451 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW		 12452 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
12453 ? T_MNEM_movs : T_MNEM_mov);
12454 inst.instruction |= inst.operands[0].reg << 8;
12455 encode_thumb32_shifted_operand (1);
12456 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12457 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef
NC		 12458 }
12459 }
12460 else
12461 {
c19d1205 12462 if (inst.operands[2].isreg)
b99bd4ef 12463 {
3d388997 12464 switch (shift_kind)
b99bd4ef 12465 {
3d388997
PB		 12466 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
12467 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
12468 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
12469 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 12470 default: abort ();
b99bd4ef 12471 }
5f4273c7 12472
c19d1205
ZW		 12473 inst.instruction |= inst.operands[0].reg;
12474 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 12475
12476 /* PR 12854: Error on extraneous shifts. */
12477 constraint (inst.operands[2].shifted,
12478 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC		 12479 }
12480 else
12481 {
3d388997 12482 switch (shift_kind)
b99bd4ef 12483 {
3d388997
PB		 12484 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
12485 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
12486 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 12487 default: abort ();
b99bd4ef 12488 }
c19d1205
ZW		 12489 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12490 inst.instruction |= inst.operands[0].reg;
12491 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 12492 }
12493 }
c19d1205
ZW		 12494 }
12495 else
12496 {
12497 constraint (inst.operands[0].reg > 7
12498 || inst.operands[1].reg > 7, BAD_HIREG);
12499 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 12500
c19d1205
ZW		 12501 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
12502 {
12503 constraint (inst.operands[2].reg > 7, BAD_HIREG);
12504 constraint (inst.operands[0].reg != inst.operands[1].reg,
12505 _("source1 and dest must be same register"));
b99bd4ef 12506
c19d1205
ZW		 12507 switch (inst.instruction)
12508 {
12509 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
12510 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
12511 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
12512 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
12513 default: abort ();
12514 }
5f4273c7 12515
c19d1205
ZW		 12516 inst.instruction |= inst.operands[0].reg;
12517 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 12518
12519 /* PR 12854: Error on extraneous shifts. */
12520 constraint (inst.operands[2].shifted,
12521 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 12522 }
12523 else
b99bd4ef 12524 {
c19d1205
ZW		 12525 switch (inst.instruction)
12526 {
12527 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
12528 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
12529 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
12530 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
12531 default: abort ();
12532 }
12533 inst.reloc.type = BFD_RELOC_ARM_THUMB_SHIFT;
12534 inst.instruction |= inst.operands[0].reg;
12535 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 12536 }
12537 }
b99bd4ef
NC		 12538}
12539
12540static void
c19d1205 12541do_t_simd (void)
b99bd4ef 12542{
fdfde340
JM		 12543 unsigned Rd, Rn, Rm;
12544
12545 Rd = inst.operands[0].reg;
12546 Rn = inst.operands[1].reg;
12547 Rm = inst.operands[2].reg;
12548
12549 reject_bad_reg (Rd);
12550 reject_bad_reg (Rn);
12551 reject_bad_reg (Rm);
12552
12553 inst.instruction |= Rd << 8;
12554 inst.instruction |= Rn << 16;
12555 inst.instruction |= Rm;
c19d1205 12556}
b99bd4ef 12557
03ee1b7f
NC		 12558static void
12559do_t_simd2 (void)
12560{
12561 unsigned Rd, Rn, Rm;
12562
12563 Rd = inst.operands[0].reg;
12564 Rm = inst.operands[1].reg;
12565 Rn = inst.operands[2].reg;
12566
12567 reject_bad_reg (Rd);
12568 reject_bad_reg (Rn);
12569 reject_bad_reg (Rm);
12570
12571 inst.instruction |= Rd << 8;
12572 inst.instruction |= Rn << 16;
12573 inst.instruction |= Rm;
12574}
12575
c19d1205 12576static void
3eb17e6b 12577do_t_smc (void)
c19d1205
ZW		 12578{
12579 unsigned int value = inst.reloc.exp.X_add_number;
f4c65163
MGD		 12580 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
12581 _("SMC is not permitted on this architecture"));
c19d1205
ZW		 12582 constraint (inst.reloc.exp.X_op != O_constant,
12583 _("expression too complex"));
12584 inst.reloc.type = BFD_RELOC_UNUSED;
12585 inst.instruction |= (value & 0xf000) >> 12;
12586 inst.instruction |= (value & 0x0ff0);
12587 inst.instruction |= (value & 0x000f) << 16;
24382199
NC		 12588 /* PR gas/15623: SMC instructions must be last in an IT block. */
12589 set_it_insn_type_last ();
c19d1205 12590}
b99bd4ef 12591
90ec0d68
MGD		 12592static void
12593do_t_hvc (void)
12594{
12595 unsigned int value = inst.reloc.exp.X_add_number;
12596
12597 inst.reloc.type = BFD_RELOC_UNUSED;
12598 inst.instruction |= (value & 0x0fff);
12599 inst.instruction |= (value & 0xf000) << 4;
12600}
12601
c19d1205 12602static void
3a21c15a 12603do_t_ssat_usat (int bias)
c19d1205 12604{
fdfde340
JM		 12605 unsigned Rd, Rn;
12606
12607 Rd = inst.operands[0].reg;
12608 Rn = inst.operands[2].reg;
12609
12610 reject_bad_reg (Rd);
12611 reject_bad_reg (Rn);
12612
12613 inst.instruction |= Rd << 8;
3a21c15a 12614 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 12615 inst.instruction |= Rn << 16;
b99bd4ef 12616
c19d1205 12617 if (inst.operands[3].present)
b99bd4ef 12618 {
3a21c15a
NC		 12619 offsetT shift_amount = inst.reloc.exp.X_add_number;
12620
12621 inst.reloc.type = BFD_RELOC_UNUSED;
12622
c19d1205
ZW		 12623 constraint (inst.reloc.exp.X_op != O_constant,
12624 _("expression too complex"));
b99bd4ef 12625
3a21c15a 12626 if (shift_amount != 0)
6189168b 12627 {
3a21c15a
NC		 12628 constraint (shift_amount > 31,
12629 _("shift expression is too large"));
12630
c19d1205 12631 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC		 12632 inst.instruction |= 0x00200000; /* sh bit. */
12633
12634 inst.instruction |= (shift_amount & 0x1c) << 10;
12635 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC		 12636 }
12637 }
b99bd4ef 12638}
c921be7d 12639
3a21c15a
NC		 12640static void
12641do_t_ssat (void)
12642{
12643 do_t_ssat_usat (1);
12644}
b99bd4ef 12645
0dd132b6 12646static void
c19d1205 12647do_t_ssat16 (void)
0dd132b6 12648{
fdfde340
JM		 12649 unsigned Rd, Rn;
12650
12651 Rd = inst.operands[0].reg;
12652 Rn = inst.operands[2].reg;
12653
12654 reject_bad_reg (Rd);
12655 reject_bad_reg (Rn);
12656
12657 inst.instruction |= Rd << 8;
c19d1205 12658 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 12659 inst.instruction |= Rn << 16;
c19d1205 12660}
0dd132b6 12661
c19d1205
ZW		 12662static void
12663do_t_strex (void)
12664{
12665 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
12666 || inst.operands[2].postind || inst.operands[2].writeback
12667 || inst.operands[2].immisreg || inst.operands[2].shifted
12668 || inst.operands[2].negative,
01cfc07f 12669 BAD_ADDR_MODE);
0dd132b6 12670
5be8be5d
DG		 12671 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
12672
c19d1205
ZW		 12673 inst.instruction |= inst.operands[0].reg << 8;
12674 inst.instruction |= inst.operands[1].reg << 12;
12675 inst.instruction |= inst.operands[2].reg << 16;
12676 inst.reloc.type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC		 12677}
12678
b99bd4ef 12679static void
c19d1205 12680do_t_strexd (void)
b99bd4ef 12681{
c19d1205
ZW		 12682 if (!inst.operands[2].present)
12683 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 12684
c19d1205
ZW		 12685 constraint (inst.operands[0].reg == inst.operands[1].reg
12686 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 12687 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 12688 BAD_OVERLAP);
b99bd4ef 12689
c19d1205
ZW		 12690 inst.instruction |= inst.operands[0].reg;
12691 inst.instruction |= inst.operands[1].reg << 12;
12692 inst.instruction |= inst.operands[2].reg << 8;
12693 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC		 12694}
12695
12696static void
c19d1205 12697do_t_sxtah (void)
b99bd4ef 12698{
fdfde340
JM		 12699 unsigned Rd, Rn, Rm;
12700
12701 Rd = inst.operands[0].reg;
12702 Rn = inst.operands[1].reg;
12703 Rm = inst.operands[2].reg;
12704
12705 reject_bad_reg (Rd);
12706 reject_bad_reg (Rn);
12707 reject_bad_reg (Rm);
12708
12709 inst.instruction |= Rd << 8;
12710 inst.instruction |= Rn << 16;
12711 inst.instruction |= Rm;
c19d1205
ZW		 12712 inst.instruction |= inst.operands[3].imm << 4;
12713}
b99bd4ef 12714
c19d1205
ZW		 12715static void
12716do_t_sxth (void)
12717{
fdfde340
JM		 12718 unsigned Rd, Rm;
12719
12720 Rd = inst.operands[0].reg;
12721 Rm = inst.operands[1].reg;
12722
12723 reject_bad_reg (Rd);
12724 reject_bad_reg (Rm);
c921be7d
NC		 12725
12726 if (inst.instruction <= 0xffff
12727 && inst.size_req != 4
fdfde340 12728 && Rd <= 7 && Rm <= 7
c19d1205 12729 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 12730 {
c19d1205 12731 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 12732 inst.instruction |= Rd;
12733 inst.instruction |= Rm << 3;
b99bd4ef 12734 }
c19d1205 12735 else if (unified_syntax)
b99bd4ef 12736 {
c19d1205
ZW		 12737 if (inst.instruction <= 0xffff)
12738 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 12739 inst.instruction |= Rd << 8;
12740 inst.instruction |= Rm;
c19d1205 12741 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 12742 }
c19d1205 12743 else
b99bd4ef 12744 {
c19d1205
ZW		 12745 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
12746 _("Thumb encoding does not support rotation"));
12747 constraint (1, BAD_HIREG);
b99bd4ef 12748 }
c19d1205 12749}
b99bd4ef 12750
c19d1205
ZW		 12751static void
12752do_t_swi (void)
12753{
b2a5fbdc
MGD		 12754 /* We have to do the following check manually as ARM_EXT_OS only applies
12755 to ARM_EXT_V6M. */
12756 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
12757 {
ac7f631b
NC		 12758 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
12759 /* This only applies to the v6m howver, not later architectures. */
12760 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
b2a5fbdc
MGD		 12761 as_bad (_("SVC is not permitted on this architecture"));
12762 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
12763 }
12764
c19d1205
ZW		 12765 inst.reloc.type = BFD_RELOC_ARM_SWI;
12766}
b99bd4ef 12767
92e90b6e
PB		 12768static void
12769do_t_tb (void)
12770{
fdfde340 12771 unsigned Rn, Rm;
92e90b6e
PB		 12772 int half;
12773
12774 half = (inst.instruction & 0x10) != 0;
e07e6e58 12775 set_it_insn_type_last ();
dfa9f0d5
PB		 12776 constraint (inst.operands[0].immisreg,
12777 _("instruction requires register index"));
fdfde340
JM		 12778
12779 Rn = inst.operands[0].reg;
12780 Rm = inst.operands[0].imm;
c921be7d 12781
fdfde340
JM		 12782 constraint (Rn == REG_SP, BAD_SP);
12783 reject_bad_reg (Rm);
12784
92e90b6e
PB		 12785 constraint (!half && inst.operands[0].shifted,
12786 _("instruction does not allow shifted index"));
fdfde340 12787 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB		 12788}
12789
74db7efb
NC		 12790static void
12791do_t_udf (void)
12792{
12793 if (!inst.operands[0].present)
12794 inst.operands[0].imm = 0;
12795
12796 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
12797 {
12798 constraint (inst.size_req == 2,
12799 _("immediate value out of range"));
12800 inst.instruction = THUMB_OP32 (inst.instruction);
12801 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
12802 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
12803 }
12804 else
12805 {
12806 inst.instruction = THUMB_OP16 (inst.instruction);
12807 inst.instruction |= inst.operands[0].imm;
12808 }
12809
12810 set_it_insn_type (NEUTRAL_IT_INSN);
12811}
12812
12813
c19d1205
ZW		 12814static void
12815do_t_usat (void)
12816{
3a21c15a 12817 do_t_ssat_usat (0);
b99bd4ef
NC		 12818}
12819
12820static void
c19d1205 12821do_t_usat16 (void)
b99bd4ef 12822{
fdfde340
JM		 12823 unsigned Rd, Rn;
12824
12825 Rd = inst.operands[0].reg;
12826 Rn = inst.operands[2].reg;
12827
12828 reject_bad_reg (Rd);
12829 reject_bad_reg (Rn);
12830
12831 inst.instruction |= Rd << 8;
c19d1205 12832 inst.instruction |= inst.operands[1].imm;
fdfde340 12833 inst.instruction |= Rn << 16;
b99bd4ef 12834}
c19d1205 12835
5287ad62 12836/* Neon instruction encoder helpers. */
5f4273c7 12837
5287ad62 12838/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 12839
5287ad62
JB		 12840/* An "invalid" code for the following tables. */
12841#define N_INV -1u
12842
12843struct neon_tab_entry
b99bd4ef 12844{
5287ad62
JB		 12845 unsigned integer;
12846 unsigned float_or_poly;
12847 unsigned scalar_or_imm;
12848};
5f4273c7 12849
5287ad62
JB		 12850/* Map overloaded Neon opcodes to their respective encodings. */
12851#define NEON_ENC_TAB \
12852 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12853 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12854 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12855 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12856 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12857 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12858 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12859 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12860 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12861 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12862 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12863 /* Register variants of the following two instructions are encoded as
e07e6e58 12864 vcge / vcgt with the operands reversed. */ \
92559b5b
PB		 12865 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12866 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB		 12867 X(vfma, N_INV, 0x0000c10, N_INV), \
12868 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB		 12869 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12870 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12871 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12872 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12873 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12874 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12875 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12876 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12877 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12878 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12879 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12880 X(vshl, 0x0000400, N_INV, 0x0800510), \
12881 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12882 X(vand, 0x0000110, N_INV, 0x0800030), \
12883 X(vbic, 0x0100110, N_INV, 0x0800030), \
12884 X(veor, 0x1000110, N_INV, N_INV), \
12885 X(vorn, 0x0300110, N_INV, 0x0800010), \
12886 X(vorr, 0x0200110, N_INV, 0x0800010), \
12887 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12888 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12889 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12890 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12891 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12892 X(vst1, 0x0000000, 0x0800000, N_INV), \
12893 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12894 X(vst2, 0x0000100, 0x0800100, N_INV), \
12895 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12896 X(vst3, 0x0000200, 0x0800200, N_INV), \
12897 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12898 X(vst4, 0x0000300, 0x0800300, N_INV), \
12899 X(vmovn, 0x1b20200, N_INV, N_INV), \
12900 X(vtrn, 0x1b20080, N_INV, N_INV), \
12901 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB		 12902 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12903 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB		 12904 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12905 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB		 12906 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12907 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB		 12908 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12909 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12910 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD		 12911 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12912 X(vseleq, 0xe000a00, N_INV, N_INV), \
12913 X(vselvs, 0xe100a00, N_INV, N_INV), \
12914 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD		 12915 X(vselgt, 0xe300a00, N_INV, N_INV), \
12916 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 12917 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD		 12918 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12919 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 12920 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 12921 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD		 12922 X(sha3op, 0x2000c00, N_INV, N_INV), \
12923 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12924 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB		 12925
12926enum neon_opc
12927{
12928#define X(OPC,I,F,S) N_MNEM_##OPC
12929NEON_ENC_TAB
12930#undef X
12931};
b99bd4ef 12932
5287ad62
JB		 12933static const struct neon_tab_entry neon_enc_tab[] =
12934{
12935#define X(OPC,I,F,S) { (I), (F), (S) }
12936NEON_ENC_TAB
12937#undef X
12938};
b99bd4ef 12939
88714cb8
DG		 12940/* Do not use these macros; instead, use NEON_ENCODE defined below. */
12941#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12942#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12943#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12944#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12945#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12946#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12947#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12948#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12949#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12950#define NEON_ENC_SINGLE_(X) \
037e8744 12951 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 12952#define NEON_ENC_DOUBLE_(X) \
037e8744 12953 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD		 12954#define NEON_ENC_FPV8_(X) \
12955 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 12956
88714cb8
DG		 12957#define NEON_ENCODE(type, inst) \
12958 do \
12959 { \
12960 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12961 inst.is_neon = 1; \
12962 } \
12963 while (0)
12964
12965#define check_neon_suffixes \
12966 do \
12967 { \
12968 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12969 { \
12970 as_bad (_("invalid neon suffix for non neon instruction")); \
12971 return; \
12972 } \
12973 } \
12974 while (0)
12975
037e8744
JB		 12976/* Define shapes for instruction operands. The following mnemonic characters
12977 are used in this table:
5287ad62 12978
037e8744 12979 F - VFP S<n> register
5287ad62
JB		 12980 D - Neon D<n> register
12981 Q - Neon Q<n> register
12982 I - Immediate
12983 S - Scalar
12984 R - ARM register
12985 L - D<n> register list
5f4273c7 12986
037e8744
JB		 12987 This table is used to generate various data:
12988 - enumerations of the form NS_DDR to be used as arguments to
12989 neon_select_shape.
12990 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 12991 - a table used to drive neon_select_shape. */
b99bd4ef 12992
037e8744
JB		 12993#define NEON_SHAPE_DEF \
12994 X(3, (D, D, D), DOUBLE), \
12995 X(3, (Q, Q, Q), QUAD), \
12996 X(3, (D, D, I), DOUBLE), \
12997 X(3, (Q, Q, I), QUAD), \
12998 X(3, (D, D, S), DOUBLE), \
12999 X(3, (Q, Q, S), QUAD), \
13000 X(2, (D, D), DOUBLE), \
13001 X(2, (Q, Q), QUAD), \
13002 X(2, (D, S), DOUBLE), \
13003 X(2, (Q, S), QUAD), \
13004 X(2, (D, R), DOUBLE), \
13005 X(2, (Q, R), QUAD), \
13006 X(2, (D, I), DOUBLE), \
13007 X(2, (Q, I), QUAD), \
13008 X(3, (D, L, D), DOUBLE), \
13009 X(2, (D, Q), MIXED), \
13010 X(2, (Q, D), MIXED), \
13011 X(3, (D, Q, I), MIXED), \
13012 X(3, (Q, D, I), MIXED), \
13013 X(3, (Q, D, D), MIXED), \
13014 X(3, (D, Q, Q), MIXED), \
13015 X(3, (Q, Q, D), MIXED), \
13016 X(3, (Q, D, S), MIXED), \
13017 X(3, (D, Q, S), MIXED), \
13018 X(4, (D, D, D, I), DOUBLE), \
13019 X(4, (Q, Q, Q, I), QUAD), \
13020 X(2, (F, F), SINGLE), \
13021 X(3, (F, F, F), SINGLE), \
13022 X(2, (F, I), SINGLE), \
13023 X(2, (F, D), MIXED), \
13024 X(2, (D, F), MIXED), \
13025 X(3, (F, F, I), MIXED), \
13026 X(4, (R, R, F, F), SINGLE), \
13027 X(4, (F, F, R, R), SINGLE), \
13028 X(3, (D, R, R), DOUBLE), \
13029 X(3, (R, R, D), DOUBLE), \
13030 X(2, (S, R), SINGLE), \
13031 X(2, (R, S), SINGLE), \
13032 X(2, (F, R), SINGLE), \
13033 X(2, (R, F), SINGLE)
13034
13035#define S2(A,B) NS_##A##B
13036#define S3(A,B,C) NS_##A##B##C
13037#define S4(A,B,C,D) NS_##A##B##C##D
13038
13039#define X(N, L, C) S##N L
13040
5287ad62
JB		 13041enum neon_shape
13042{
037e8744
JB		 13043 NEON_SHAPE_DEF,
13044 NS_NULL
5287ad62 13045};
b99bd4ef 13046
037e8744
JB		 13047#undef X
13048#undef S2
13049#undef S3
13050#undef S4
13051
13052enum neon_shape_class
13053{
13054 SC_SINGLE,
13055 SC_DOUBLE,
13056 SC_QUAD,
13057 SC_MIXED
13058};
13059
13060#define X(N, L, C) SC_##C
13061
13062static enum neon_shape_class neon_shape_class[] =
13063{
13064 NEON_SHAPE_DEF
13065};
13066
13067#undef X
13068
13069enum neon_shape_el
13070{
13071 SE_F,
13072 SE_D,
13073 SE_Q,
13074 SE_I,
13075 SE_S,
13076 SE_R,
13077 SE_L
13078};
13079
13080/* Register widths of above. */
13081static unsigned neon_shape_el_size[] =
13082{
13083 32,
13084 64,
13085 128,
13086 0,
13087 32,
13088 32,
13089 0
13090};
13091
13092struct neon_shape_info
13093{
13094 unsigned els;
13095 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
13096};
13097
13098#define S2(A,B) { SE_##A, SE_##B }
13099#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13100#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13101
13102#define X(N, L, C) { N, S##N L }
13103
13104static struct neon_shape_info neon_shape_tab[] =
13105{
13106 NEON_SHAPE_DEF
13107};
13108
13109#undef X
13110#undef S2
13111#undef S3
13112#undef S4
13113
5287ad62
JB		 13114/* Bit masks used in type checking given instructions.
13115 'N_EQK' means the type must be the same as (or based on in some way) the key
13116 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13117 set, various other bits can be set as well in order to modify the meaning of
13118 the type constraint. */
13119
13120enum neon_type_mask
13121{
8e79c3df
CM		 13122 N_S8 = 0x0000001,
13123 N_S16 = 0x0000002,
13124 N_S32 = 0x0000004,
13125 N_S64 = 0x0000008,
13126 N_U8 = 0x0000010,
13127 N_U16 = 0x0000020,
13128 N_U32 = 0x0000040,
13129 N_U64 = 0x0000080,
13130 N_I8 = 0x0000100,
13131 N_I16 = 0x0000200,
13132 N_I32 = 0x0000400,
13133 N_I64 = 0x0000800,
13134 N_8 = 0x0001000,
13135 N_16 = 0x0002000,
13136 N_32 = 0x0004000,
13137 N_64 = 0x0008000,
13138 N_P8 = 0x0010000,
13139 N_P16 = 0x0020000,
13140 N_F16 = 0x0040000,
13141 N_F32 = 0x0080000,
13142 N_F64 = 0x0100000,
4f51b4bd 13143 N_P64 = 0x0200000,
c921be7d
NC		 13144 N_KEY = 0x1000000, /* Key element (main type specifier). */
13145 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 13146 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 13147 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC		 13148 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
13149 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
13150 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13151 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13152 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13153 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
13154 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 13155 N_UTYP = 0,
4f51b4bd 13156 N_MAX_NONSPECIAL = N_P64
5287ad62
JB		 13157};
13158
dcbf9037
JB		 13159#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13160
5287ad62
JB		 13161#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13162#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13163#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13164#define N_SUF_32 (N_SU_32 | N_F32)
13165#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13166#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
13167
13168/* Pass this as the first type argument to neon_check_type to ignore types
13169 altogether. */
13170#define N_IGNORE_TYPE (N_KEY | N_EQK)
13171
037e8744
JB		 13172/* Select a "shape" for the current instruction (describing register types or
13173 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13174 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13175 function of operand parsing, so this function doesn't need to be called.
13176 Shapes should be listed in order of decreasing length. */
5287ad62
JB		 13177
13178static enum neon_shape
037e8744 13179neon_select_shape (enum neon_shape shape, ...)
5287ad62 13180{
037e8744
JB		 13181 va_list ap;
13182 enum neon_shape first_shape = shape;
5287ad62
JB		 13183
13184 /* Fix missing optional operands. FIXME: we don't know at this point how
13185 many arguments we should have, so this makes the assumption that we have
13186 > 1. This is true of all current Neon opcodes, I think, but may not be
13187 true in the future. */
13188 if (!inst.operands[1].present)
13189 inst.operands[1] = inst.operands[0];
13190
037e8744 13191 va_start (ap, shape);
5f4273c7 13192
21d799b5 13193 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB		 13194 {
13195 unsigned j;
13196 int matches = 1;
13197
13198 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM		 13199 {
13200 if (!inst.operands[j].present)
13201 {
13202 matches = 0;
13203 break;
13204 }
13205
13206 switch (neon_shape_tab[shape].el[j])
13207 {
13208 case SE_F:
13209 if (!(inst.operands[j].isreg
13210 && inst.operands[j].isvec
13211 && inst.operands[j].issingle
13212 && !inst.operands[j].isquad))
13213 matches = 0;
13214 break;
13215
13216 case SE_D:
13217 if (!(inst.operands[j].isreg
13218 && inst.operands[j].isvec
13219 && !inst.operands[j].isquad
13220 && !inst.operands[j].issingle))
13221 matches = 0;
13222 break;
13223
13224 case SE_R:
13225 if (!(inst.operands[j].isreg
13226 && !inst.operands[j].isvec))
13227 matches = 0;
13228 break;
13229
13230 case SE_Q:
13231 if (!(inst.operands[j].isreg
13232 && inst.operands[j].isvec
13233 && inst.operands[j].isquad
13234 && !inst.operands[j].issingle))
13235 matches = 0;
13236 break;
13237
13238 case SE_I:
13239 if (!(!inst.operands[j].isreg
13240 && !inst.operands[j].isscalar))
13241 matches = 0;
13242 break;
13243
13244 case SE_S:
13245 if (!(!inst.operands[j].isreg
13246 && inst.operands[j].isscalar))
13247 matches = 0;
13248 break;
13249
13250 case SE_L:
13251 break;
13252 }
3fde54a2
JZ		 13253 if (!matches)
13254 break;
477330fc 13255 }
ad6cec43
MGD		 13256 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
13257 /* We've matched all the entries in the shape table, and we don't
13258 have any left over operands which have not been matched. */
477330fc 13259 break;
037e8744 13260 }
5f4273c7 13261
037e8744 13262 va_end (ap);
5287ad62 13263
037e8744
JB		 13264 if (shape == NS_NULL && first_shape != NS_NULL)
13265 first_error (_("invalid instruction shape"));
5287ad62 13266
037e8744
JB		 13267 return shape;
13268}
5287ad62 13269
037e8744
JB		 13270/* True if SHAPE is predominantly a quadword operation (most of the time, this
13271 means the Q bit should be set). */
13272
13273static int
13274neon_quad (enum neon_shape shape)
13275{
13276 return neon_shape_class[shape] == SC_QUAD;
5287ad62 13277}
037e8744 13278
5287ad62
JB		 13279static void
13280neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 13281 unsigned *g_size)
5287ad62
JB		 13282{
13283 /* Allow modification to be made to types which are constrained to be
13284 based on the key element, based on bits set alongside N_EQK. */
13285 if ((typebits & N_EQK) != 0)
13286 {
13287 if ((typebits & N_HLF) != 0)
13288 *g_size /= 2;
13289 else if ((typebits & N_DBL) != 0)
13290 *g_size *= 2;
13291 if ((typebits & N_SGN) != 0)
13292 *g_type = NT_signed;
13293 else if ((typebits & N_UNS) != 0)
477330fc 13294 *g_type = NT_unsigned;
5287ad62 13295 else if ((typebits & N_INT) != 0)
477330fc 13296 *g_type = NT_integer;
5287ad62 13297 else if ((typebits & N_FLT) != 0)
477330fc 13298 *g_type = NT_float;
dcbf9037 13299 else if ((typebits & N_SIZ) != 0)
477330fc 13300 *g_type = NT_untyped;
5287ad62
JB		 13301 }
13302}
5f4273c7 13303
5287ad62
JB		 13304/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13305 operand type, i.e. the single type specified in a Neon instruction when it
13306 is the only one given. */
13307
13308static struct neon_type_el
13309neon_type_promote (struct neon_type_el *key, unsigned thisarg)
13310{
13311 struct neon_type_el dest = *key;
5f4273c7 13312
9c2799c2 13313 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 13314
5287ad62
JB		 13315 neon_modify_type_size (thisarg, &dest.type, &dest.size);
13316
13317 return dest;
13318}
13319
13320/* Convert Neon type and size into compact bitmask representation. */
13321
13322static enum neon_type_mask
13323type_chk_of_el_type (enum neon_el_type type, unsigned size)
13324{
13325 switch (type)
13326 {
13327 case NT_untyped:
13328 switch (size)
477330fc
RM		 13329 {
13330 case 8: return N_8;
13331 case 16: return N_16;
13332 case 32: return N_32;
13333 case 64: return N_64;
13334 default: ;
13335 }
5287ad62
JB		 13336 break;
13337
13338 case NT_integer:
13339 switch (size)
477330fc
RM		 13340 {
13341 case 8: return N_I8;
13342 case 16: return N_I16;
13343 case 32: return N_I32;
13344 case 64: return N_I64;
13345 default: ;
13346 }
5287ad62
JB		 13347 break;
13348
13349 case NT_float:
037e8744 13350 switch (size)
477330fc 13351 {
8e79c3df 13352 case 16: return N_F16;
477330fc
RM		 13353 case 32: return N_F32;
13354 case 64: return N_F64;
13355 default: ;
13356 }
5287ad62
JB		 13357 break;
13358
13359 case NT_poly:
13360 switch (size)
477330fc
RM		 13361 {
13362 case 8: return N_P8;
13363 case 16: return N_P16;
4f51b4bd 13364 case 64: return N_P64;
477330fc
RM		 13365 default: ;
13366 }
5287ad62
JB		 13367 break;
13368
13369 case NT_signed:
13370 switch (size)
477330fc
RM		 13371 {
13372 case 8: return N_S8;
13373 case 16: return N_S16;
13374 case 32: return N_S32;
13375 case 64: return N_S64;
13376 default: ;
13377 }
5287ad62
JB		 13378 break;
13379
13380 case NT_unsigned:
13381 switch (size)
477330fc
RM		 13382 {
13383 case 8: return N_U8;
13384 case 16: return N_U16;
13385 case 32: return N_U32;
13386 case 64: return N_U64;
13387 default: ;
13388 }
5287ad62
JB		 13389 break;
13390
13391 default: ;
13392 }
5f4273c7 13393
5287ad62
JB		 13394 return N_UTYP;
13395}
13396
13397/* Convert compact Neon bitmask type representation to a type and size. Only
13398 handles the case where a single bit is set in the mask. */
13399
dcbf9037 13400static int
5287ad62 13401el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 13402 enum neon_type_mask mask)
5287ad62 13403{
dcbf9037
JB		 13404 if ((mask & N_EQK) != 0)
13405 return FAIL;
13406
5287ad62
JB		 13407 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
13408 *size = 8;
c70a8987 13409 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
5287ad62 13410 *size = 16;
dcbf9037 13411 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 13412 *size = 32;
4f51b4bd 13413 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 13414 *size = 64;
dcbf9037
JB		 13415 else
13416 return FAIL;
13417
5287ad62
JB		 13418 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
13419 *type = NT_signed;
dcbf9037 13420 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 13421 *type = NT_unsigned;
dcbf9037 13422 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 13423 *type = NT_integer;
dcbf9037 13424 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 13425 *type = NT_untyped;
4f51b4bd 13426 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 13427 *type = NT_poly;
c70a8987 13428 else if ((mask & (N_F16 | N_F32 | N_F64)) != 0)
5287ad62 13429 *type = NT_float;
dcbf9037
JB		 13430 else
13431 return FAIL;
5f4273c7 13432
dcbf9037 13433 return SUCCESS;
5287ad62
JB		 13434}
13435
13436/* Modify a bitmask of allowed types. This is only needed for type
13437 relaxation. */
13438
13439static unsigned
13440modify_types_allowed (unsigned allowed, unsigned mods)
13441{
13442 unsigned size;
13443 enum neon_el_type type;
13444 unsigned destmask;
13445 int i;
5f4273c7 13446
5287ad62 13447 destmask = 0;
5f4273c7 13448
5287ad62
JB		 13449 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
13450 {
21d799b5 13451 if (el_type_of_type_chk (&type, &size,
477330fc
RM		 13452 (enum neon_type_mask) (allowed & i)) == SUCCESS)
13453 {
13454 neon_modify_type_size (mods, &type, &size);
13455 destmask |= type_chk_of_el_type (type, size);
13456 }
5287ad62 13457 }
5f4273c7 13458
5287ad62
JB		 13459 return destmask;
13460}
13461
13462/* Check type and return type classification.
13463 The manual states (paraphrase): If one datatype is given, it indicates the
13464 type given in:
13465 - the second operand, if there is one
13466 - the operand, if there is no second operand
13467 - the result, if there are no operands.
13468 This isn't quite good enough though, so we use a concept of a "key" datatype
13469 which is set on a per-instruction basis, which is the one which matters when
13470 only one data type is written.
13471 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 13472 Neon instructions should call it before performing bit encoding. */
5287ad62
JB		 13473
13474static struct neon_type_el
13475neon_check_type (unsigned els, enum neon_shape ns, ...)
13476{
13477 va_list ap;
13478 unsigned i, pass, key_el = 0;
13479 unsigned types[NEON_MAX_TYPE_ELS];
13480 enum neon_el_type k_type = NT_invtype;
13481 unsigned k_size = -1u;
13482 struct neon_type_el badtype = {NT_invtype, -1};
13483 unsigned key_allowed = 0;
13484
13485 /* Optional registers in Neon instructions are always (not) in operand 1.
13486 Fill in the missing operand here, if it was omitted. */
13487 if (els > 1 && !inst.operands[1].present)
13488 inst.operands[1] = inst.operands[0];
13489
13490 /* Suck up all the varargs. */
13491 va_start (ap, ns);
13492 for (i = 0; i < els; i++)
13493 {
13494 unsigned thisarg = va_arg (ap, unsigned);
13495 if (thisarg == N_IGNORE_TYPE)
477330fc
RM		 13496 {
13497 va_end (ap);
13498 return badtype;
13499 }
5287ad62
JB		 13500 types[i] = thisarg;
13501 if ((thisarg & N_KEY) != 0)
477330fc 13502 key_el = i;
5287ad62
JB		 13503 }
13504 va_end (ap);
13505
dcbf9037
JB		 13506 if (inst.vectype.elems > 0)
13507 for (i = 0; i < els; i++)
13508 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM		 13509 {
13510 first_error (_("types specified in both the mnemonic and operands"));
13511 return badtype;
13512 }
dcbf9037 13513
5287ad62
JB		 13514 /* Duplicate inst.vectype elements here as necessary.
13515 FIXME: No idea if this is exactly the same as the ARM assembler,
13516 particularly when an insn takes one register and one non-register
13517 operand. */
13518 if (inst.vectype.elems == 1 && els > 1)
13519 {
13520 unsigned j;
13521 inst.vectype.elems = els;
13522 inst.vectype.el[key_el] = inst.vectype.el[0];
13523 for (j = 0; j < els; j++)
477330fc
RM		 13524 if (j != key_el)
13525 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13526 types[j]);
dcbf9037
JB		 13527 }
13528 else if (inst.vectype.elems == 0 && els > 0)
13529 {
13530 unsigned j;
13531 /* No types were given after the mnemonic, so look for types specified
477330fc
RM		 13532 after each operand. We allow some flexibility here; as long as the
13533 "key" operand has a type, we can infer the others. */
dcbf9037 13534 for (j = 0; j < els; j++)
477330fc
RM		 13535 if (inst.operands[j].vectype.type != NT_invtype)
13536 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB		 13537
13538 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM		 13539 {
13540 for (j = 0; j < els; j++)
13541 if (inst.operands[j].vectype.type == NT_invtype)
13542 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
13543 types[j]);
13544 }
dcbf9037 13545 else
477330fc
RM		 13546 {
13547 first_error (_("operand types can't be inferred"));
13548 return badtype;
13549 }
5287ad62
JB		 13550 }
13551 else if (inst.vectype.elems != els)
13552 {
dcbf9037 13553 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB		 13554 return badtype;
13555 }
13556
13557 for (pass = 0; pass < 2; pass++)
13558 {
13559 for (i = 0; i < els; i++)
477330fc
RM		 13560 {
13561 unsigned thisarg = types[i];
13562 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
13563 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
13564 enum neon_el_type g_type = inst.vectype.el[i].type;
13565 unsigned g_size = inst.vectype.el[i].size;
13566
13567 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 13568 integer types if sign-specific variants are unavailable. */
477330fc 13569 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB		 13570 && (types_allowed & N_SU_ALL) == 0)
13571 g_type = NT_integer;
13572
477330fc 13573 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB		 13574 them. Some instructions only care about signs for some element
13575 sizes, so handle that properly. */
477330fc 13576 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD		 13577 && ((g_size == 8 && (types_allowed & N_8) != 0)
13578 || (g_size == 16 && (types_allowed & N_16) != 0)
13579 || (g_size == 32 && (types_allowed & N_32) != 0)
13580 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB		 13581 g_type = NT_untyped;
13582
477330fc
RM		 13583 if (pass == 0)
13584 {
13585 if ((thisarg & N_KEY) != 0)
13586 {
13587 k_type = g_type;
13588 k_size = g_size;
13589 key_allowed = thisarg & ~N_KEY;
13590 }
13591 }
13592 else
13593 {
13594 if ((thisarg & N_VFP) != 0)
13595 {
13596 enum neon_shape_el regshape;
13597 unsigned regwidth, match;
99b253c5
NC		 13598
13599 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13600 if (ns == NS_NULL)
13601 {
13602 first_error (_("invalid instruction shape"));
13603 return badtype;
13604 }
477330fc
RM		 13605 regshape = neon_shape_tab[ns].el[i];
13606 regwidth = neon_shape_el_size[regshape];
13607
13608 /* In VFP mode, operands must match register widths. If we
13609 have a key operand, use its width, else use the width of
13610 the current operand. */
13611 if (k_size != -1u)
13612 match = k_size;
13613 else
13614 match = g_size;
13615
13616 if (regwidth != match)
13617 {
13618 first_error (_("operand size must match register width"));
13619 return badtype;
13620 }
13621 }
13622
13623 if ((thisarg & N_EQK) == 0)
13624 {
13625 unsigned given_type = type_chk_of_el_type (g_type, g_size);
13626
13627 if ((given_type & types_allowed) == 0)
13628 {
13629 first_error (_("bad type in Neon instruction"));
13630 return badtype;
13631 }
13632 }
13633 else
13634 {
13635 enum neon_el_type mod_k_type = k_type;
13636 unsigned mod_k_size = k_size;
13637 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
13638 if (g_type != mod_k_type || g_size != mod_k_size)
13639 {
13640 first_error (_("inconsistent types in Neon instruction"));
13641 return badtype;
13642 }
13643 }
13644 }
13645 }
5287ad62
JB		 13646 }
13647
13648 return inst.vectype.el[key_el];
13649}
13650
037e8744 13651/* Neon-style VFP instruction forwarding. */
5287ad62 13652
037e8744
JB		 13653/* Thumb VFP instructions have 0xE in the condition field. */
13654
13655static void
13656do_vfp_cond_or_thumb (void)
5287ad62 13657{
88714cb8
DG		 13658 inst.is_neon = 1;
13659
5287ad62 13660 if (thumb_mode)
037e8744 13661 inst.instruction |= 0xe0000000;
5287ad62 13662 else
037e8744 13663 inst.instruction |= inst.cond << 28;
5287ad62
JB		 13664}
13665
037e8744
JB		 13666/* Look up and encode a simple mnemonic, for use as a helper function for the
13667 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13668 etc. It is assumed that operand parsing has already been done, and that the
13669 operands are in the form expected by the given opcode (this isn't necessarily
13670 the same as the form in which they were parsed, hence some massaging must
13671 take place before this function is called).
13672 Checks current arch version against that in the looked-up opcode. */
5287ad62 13673
037e8744
JB		 13674static void
13675do_vfp_nsyn_opcode (const char *opname)
5287ad62 13676{
037e8744 13677 const struct asm_opcode *opcode;
5f4273c7 13678
21d799b5 13679 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 13680
037e8744
JB		 13681 if (!opcode)
13682 abort ();
5287ad62 13683
037e8744 13684 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM		 13685 thumb_mode ? *opcode->tvariant : *opcode->avariant),
13686 _(BAD_FPU));
5287ad62 13687
88714cb8
DG		 13688 inst.is_neon = 1;
13689
037e8744
JB		 13690 if (thumb_mode)
13691 {
13692 inst.instruction = opcode->tvalue;
13693 opcode->tencode ();
13694 }
13695 else
13696 {
13697 inst.instruction = (inst.cond << 28) | opcode->avalue;
13698 opcode->aencode ();
13699 }
13700}
5287ad62
JB		 13701
13702static void
037e8744 13703do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 13704{
037e8744
JB		 13705 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
13706
13707 if (rs == NS_FFF)
13708 {
13709 if (is_add)
477330fc 13710 do_vfp_nsyn_opcode ("fadds");
037e8744 13711 else
477330fc 13712 do_vfp_nsyn_opcode ("fsubs");
037e8744
JB		 13713 }
13714 else
13715 {
13716 if (is_add)
477330fc 13717 do_vfp_nsyn_opcode ("faddd");
037e8744 13718 else
477330fc 13719 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB		 13720 }
13721}
13722
13723/* Check operand types to see if this is a VFP instruction, and if so call
13724 PFN (). */
13725
13726static int
13727try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
13728{
13729 enum neon_shape rs;
13730 struct neon_type_el et;
13731
13732 switch (args)
13733 {
13734 case 2:
13735 rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13736 et = neon_check_type (2, rs,
477330fc 13737 N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
037e8744 13738 break;
5f4273c7 13739
037e8744
JB		 13740 case 3:
13741 rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13742 et = neon_check_type (3, rs,
477330fc 13743 N_EQK | N_VFP, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
037e8744
JB		 13744 break;
13745
13746 default:
13747 abort ();
13748 }
13749
13750 if (et.type != NT_invtype)
13751 {
13752 pfn (rs);
13753 return SUCCESS;
13754 }
037e8744 13755
99b253c5 13756 inst.error = NULL;
037e8744
JB		 13757 return FAIL;
13758}
13759
13760static void
13761do_vfp_nsyn_mla_mls (enum neon_shape rs)
13762{
13763 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 13764
037e8744
JB		 13765 if (rs == NS_FFF)
13766 {
13767 if (is_mla)
477330fc 13768 do_vfp_nsyn_opcode ("fmacs");
037e8744 13769 else
477330fc 13770 do_vfp_nsyn_opcode ("fnmacs");
037e8744
JB		 13771 }
13772 else
13773 {
13774 if (is_mla)
477330fc 13775 do_vfp_nsyn_opcode ("fmacd");
037e8744 13776 else
477330fc 13777 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB		 13778 }
13779}
13780
62f3b8c8
PB		 13781static void
13782do_vfp_nsyn_fma_fms (enum neon_shape rs)
13783{
13784 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
13785
13786 if (rs == NS_FFF)
13787 {
13788 if (is_fma)
477330fc 13789 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 13790 else
477330fc 13791 do_vfp_nsyn_opcode ("ffnmas");
62f3b8c8
PB		 13792 }
13793 else
13794 {
13795 if (is_fma)
477330fc 13796 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 13797 else
477330fc 13798 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB		 13799 }
13800}
13801
037e8744
JB		 13802static void
13803do_vfp_nsyn_mul (enum neon_shape rs)
13804{
13805 if (rs == NS_FFF)
13806 do_vfp_nsyn_opcode ("fmuls");
13807 else
13808 do_vfp_nsyn_opcode ("fmuld");
13809}
13810
13811static void
13812do_vfp_nsyn_abs_neg (enum neon_shape rs)
13813{
13814 int is_neg = (inst.instruction & 0x80) != 0;
13815 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_VFP | N_KEY);
13816
13817 if (rs == NS_FF)
13818 {
13819 if (is_neg)
477330fc 13820 do_vfp_nsyn_opcode ("fnegs");
037e8744 13821 else
477330fc 13822 do_vfp_nsyn_opcode ("fabss");
037e8744
JB		 13823 }
13824 else
13825 {
13826 if (is_neg)
477330fc 13827 do_vfp_nsyn_opcode ("fnegd");
037e8744 13828 else
477330fc 13829 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB		 13830 }
13831}
13832
13833/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13834 insns belong to Neon, and are handled elsewhere. */
13835
13836static void
13837do_vfp_nsyn_ldm_stm (int is_dbmode)
13838{
13839 int is_ldm = (inst.instruction & (1 << 20)) != 0;
13840 if (is_ldm)
13841 {
13842 if (is_dbmode)
477330fc 13843 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 13844 else
477330fc 13845 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB		 13846 }
13847 else
13848 {
13849 if (is_dbmode)
477330fc 13850 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 13851 else
477330fc 13852 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB		 13853 }
13854}
13855
037e8744
JB		 13856static void
13857do_vfp_nsyn_sqrt (void)
13858{
13859 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13860 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13861
037e8744
JB		 13862 if (rs == NS_FF)
13863 do_vfp_nsyn_opcode ("fsqrts");
13864 else
13865 do_vfp_nsyn_opcode ("fsqrtd");
13866}
13867
13868static void
13869do_vfp_nsyn_div (void)
13870{
13871 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13872 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13873 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13874
037e8744
JB		 13875 if (rs == NS_FFF)
13876 do_vfp_nsyn_opcode ("fdivs");
13877 else
13878 do_vfp_nsyn_opcode ("fdivd");
13879}
13880
13881static void
13882do_vfp_nsyn_nmul (void)
13883{
13884 enum neon_shape rs = neon_select_shape (NS_FFF, NS_DDD, NS_NULL);
13885 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
13886 N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13887
037e8744
JB		 13888 if (rs == NS_FFF)
13889 {
88714cb8 13890 NEON_ENCODE (SINGLE, inst);
037e8744
JB		 13891 do_vfp_sp_dyadic ();
13892 }
13893 else
13894 {
88714cb8 13895 NEON_ENCODE (DOUBLE, inst);
037e8744
JB		 13896 do_vfp_dp_rd_rn_rm ();
13897 }
13898 do_vfp_cond_or_thumb ();
13899}
13900
13901static void
13902do_vfp_nsyn_cmp (void)
13903{
13904 if (inst.operands[1].isreg)
13905 {
13906 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_NULL);
13907 neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
5f4273c7 13908
037e8744 13909 if (rs == NS_FF)
477330fc
RM		 13910 {
13911 NEON_ENCODE (SINGLE, inst);
13912 do_vfp_sp_monadic ();
13913 }
037e8744 13914 else
477330fc
RM		 13915 {
13916 NEON_ENCODE (DOUBLE, inst);
13917 do_vfp_dp_rd_rm ();
13918 }
037e8744
JB		 13919 }
13920 else
13921 {
13922 enum neon_shape rs = neon_select_shape (NS_FI, NS_DI, NS_NULL);
13923 neon_check_type (2, rs, N_F32 | N_F64 | N_KEY | N_VFP, N_EQK);
13924
13925 switch (inst.instruction & 0x0fffffff)
477330fc
RM		 13926 {
13927 case N_MNEM_vcmp:
13928 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
13929 break;
13930 case N_MNEM_vcmpe:
13931 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
13932 break;
13933 default:
13934 abort ();
13935 }
5f4273c7 13936
037e8744 13937 if (rs == NS_FI)
477330fc
RM		 13938 {
13939 NEON_ENCODE (SINGLE, inst);
13940 do_vfp_sp_compare_z ();
13941 }
037e8744 13942 else
477330fc
RM		 13943 {
13944 NEON_ENCODE (DOUBLE, inst);
13945 do_vfp_dp_rd ();
13946 }
037e8744
JB		 13947 }
13948 do_vfp_cond_or_thumb ();
13949}
13950
13951static void
13952nsyn_insert_sp (void)
13953{
13954 inst.operands[1] = inst.operands[0];
13955 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 13956 inst.operands[0].reg = REG_SP;
037e8744
JB		 13957 inst.operands[0].isreg = 1;
13958 inst.operands[0].writeback = 1;
13959 inst.operands[0].present = 1;
13960}
13961
13962static void
13963do_vfp_nsyn_push (void)
13964{
13965 nsyn_insert_sp ();
13966 if (inst.operands[1].issingle)
13967 do_vfp_nsyn_opcode ("fstmdbs");
13968 else
13969 do_vfp_nsyn_opcode ("fstmdbd");
13970}
13971
13972static void
13973do_vfp_nsyn_pop (void)
13974{
13975 nsyn_insert_sp ();
13976 if (inst.operands[1].issingle)
22b5b651 13977 do_vfp_nsyn_opcode ("fldmias");
037e8744 13978 else
22b5b651 13979 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB		 13980}
13981
13982/* Fix up Neon data-processing instructions, ORing in the correct bits for
13983 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13984
88714cb8
DG		 13985static void
13986neon_dp_fixup (struct arm_it* insn)
037e8744 13987{
88714cb8
DG		 13988 unsigned int i = insn->instruction;
13989 insn->is_neon = 1;
13990
037e8744
JB		 13991 if (thumb_mode)
13992 {
13993 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13994 if (i & (1 << 24))
477330fc 13995 i |= 1 << 28;
5f4273c7 13996
037e8744 13997 i &= ~(1 << 24);
5f4273c7 13998
037e8744
JB		 13999 i |= 0xef000000;
14000 }
14001 else
14002 i |= 0xf2000000;
5f4273c7 14003
88714cb8 14004 insn->instruction = i;
037e8744
JB		 14005}
14006
14007/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14008 (0, 1, 2, 3). */
14009
14010static unsigned
14011neon_logbits (unsigned x)
14012{
14013 return ffs (x) - 4;
14014}
14015
14016#define LOW4(R) ((R) & 0xf)
14017#define HI1(R) (((R) >> 4) & 1)
14018
14019/* Encode insns with bit pattern:
14020
14021 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14022 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 14023
037e8744
JB		 14024 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14025 different meaning for some instruction. */
14026
14027static void
14028neon_three_same (int isquad, int ubit, int size)
14029{
14030 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14031 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14032 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14033 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14034 inst.instruction |= LOW4 (inst.operands[2].reg);
14035 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
14036 inst.instruction |= (isquad != 0) << 6;
14037 inst.instruction |= (ubit != 0) << 24;
14038 if (size != -1)
14039 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 14040
88714cb8 14041 neon_dp_fixup (&inst);
037e8744
JB		 14042}
14043
14044/* Encode instructions of the form:
14045
14046 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14047 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB		 14048
14049 Don't write size if SIZE == -1. */
14050
14051static void
14052neon_two_same (int qbit, int ubit, int size)
14053{
14054 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14055 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14056 inst.instruction |= LOW4 (inst.operands[1].reg);
14057 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14058 inst.instruction |= (qbit != 0) << 6;
14059 inst.instruction |= (ubit != 0) << 24;
14060
14061 if (size != -1)
14062 inst.instruction |= neon_logbits (size) << 18;
14063
88714cb8 14064 neon_dp_fixup (&inst);
5287ad62
JB		 14065}
14066
14067/* Neon instruction encoders, in approximate order of appearance. */
14068
14069static void
14070do_neon_dyadic_i_su (void)
14071{
037e8744 14072 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14073 struct neon_type_el et = neon_check_type (3, rs,
14074 N_EQK, N_EQK, N_SU_32 | N_KEY);
037e8744 14075 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14076}
14077
14078static void
14079do_neon_dyadic_i64_su (void)
14080{
037e8744 14081 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14082 struct neon_type_el et = neon_check_type (3, rs,
14083 N_EQK, N_EQK, N_SU_ALL | N_KEY);
037e8744 14084 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14085}
14086
14087static void
14088neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 14089 unsigned immbits)
5287ad62
JB		 14090{
14091 unsigned size = et.size >> 3;
14092 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14093 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14094 inst.instruction |= LOW4 (inst.operands[1].reg);
14095 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14096 inst.instruction |= (isquad != 0) << 6;
14097 inst.instruction |= immbits << 16;
14098 inst.instruction |= (size >> 3) << 7;
14099 inst.instruction |= (size & 0x7) << 19;
14100 if (write_ubit)
14101 inst.instruction |= (uval != 0) << 24;
14102
88714cb8 14103 neon_dp_fixup (&inst);
5287ad62
JB		 14104}
14105
14106static void
14107do_neon_shl_imm (void)
14108{
14109 if (!inst.operands[2].isreg)
14110 {
037e8744 14111 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 14112 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
cb3b1e65
JB		 14113 int imm = inst.operands[2].imm;
14114
14115 constraint (imm < 0 || (unsigned)imm >= et.size,
14116 _("immediate out of range for shift"));
88714cb8 14117 NEON_ENCODE (IMMED, inst);
cb3b1e65 14118 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14119 }
14120 else
14121 {
037e8744 14122 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14123 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14124 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB		 14125 unsigned int tmp;
14126
14127 /* VSHL/VQSHL 3-register variants have syntax such as:
477330fc
RM		 14128 vshl.xx Dd, Dm, Dn
14129 whereas other 3-register operations encoded by neon_three_same have
14130 syntax like:
14131 vadd.xx Dd, Dn, Dm
14132 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14133 here. */
627907b7
JB		 14134 tmp = inst.operands[2].reg;
14135 inst.operands[2].reg = inst.operands[1].reg;
14136 inst.operands[1].reg = tmp;
88714cb8 14137 NEON_ENCODE (INTEGER, inst);
037e8744 14138 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14139 }
14140}
14141
14142static void
14143do_neon_qshl_imm (void)
14144{
14145 if (!inst.operands[2].isreg)
14146 {
037e8744 14147 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62 14148 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
cb3b1e65 14149 int imm = inst.operands[2].imm;
627907b7 14150
cb3b1e65
JB		 14151 constraint (imm < 0 || (unsigned)imm >= et.size,
14152 _("immediate out of range for shift"));
88714cb8 14153 NEON_ENCODE (IMMED, inst);
cb3b1e65 14154 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
5287ad62
JB		 14155 }
14156 else
14157 {
037e8744 14158 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14159 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14160 N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
627907b7
JB		 14161 unsigned int tmp;
14162
14163 /* See note in do_neon_shl_imm. */
14164 tmp = inst.operands[2].reg;
14165 inst.operands[2].reg = inst.operands[1].reg;
14166 inst.operands[1].reg = tmp;
88714cb8 14167 NEON_ENCODE (INTEGER, inst);
037e8744 14168 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 14169 }
14170}
14171
627907b7
JB		 14172static void
14173do_neon_rshl (void)
14174{
14175 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
14176 struct neon_type_el et = neon_check_type (3, rs,
14177 N_EQK, N_EQK, N_SU_ALL | N_KEY);
14178 unsigned int tmp;
14179
14180 tmp = inst.operands[2].reg;
14181 inst.operands[2].reg = inst.operands[1].reg;
14182 inst.operands[1].reg = tmp;
14183 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
14184}
14185
5287ad62
JB		 14186static int
14187neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
14188{
036dc3f7
PB		 14189 /* Handle .I8 pseudo-instructions. */
14190 if (size == 8)
5287ad62 14191 {
5287ad62 14192 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM		 14193 FIXME is this the intended semantics? There doesn't seem much point in
14194 accepting .I8 if so. */
5287ad62
JB		 14195 immediate |= immediate << 8;
14196 size = 16;
036dc3f7
PB		 14197 }
14198
14199 if (size >= 32)
14200 {
14201 if (immediate == (immediate & 0x000000ff))
14202 {
14203 *immbits = immediate;
14204 return 0x1;
14205 }
14206 else if (immediate == (immediate & 0x0000ff00))
14207 {
14208 *immbits = immediate >> 8;
14209 return 0x3;
14210 }
14211 else if (immediate == (immediate & 0x00ff0000))
14212 {
14213 *immbits = immediate >> 16;
14214 return 0x5;
14215 }
14216 else if (immediate == (immediate & 0xff000000))
14217 {
14218 *immbits = immediate >> 24;
14219 return 0x7;
14220 }
14221 if ((immediate & 0xffff) != (immediate >> 16))
14222 goto bad_immediate;
14223 immediate &= 0xffff;
5287ad62
JB		 14224 }
14225
14226 if (immediate == (immediate & 0x000000ff))
14227 {
14228 *immbits = immediate;
036dc3f7 14229 return 0x9;
5287ad62
JB		 14230 }
14231 else if (immediate == (immediate & 0x0000ff00))
14232 {
14233 *immbits = immediate >> 8;
036dc3f7 14234 return 0xb;
5287ad62
JB		 14235 }
14236
14237 bad_immediate:
dcbf9037 14238 first_error (_("immediate value out of range"));
5287ad62
JB		 14239 return FAIL;
14240}
14241
5287ad62
JB		 14242static void
14243do_neon_logic (void)
14244{
14245 if (inst.operands[2].present && inst.operands[2].isreg)
14246 {
037e8744 14247 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14248 neon_check_type (3, rs, N_IGNORE_TYPE);
14249 /* U bit and size field were set as part of the bitmask. */
88714cb8 14250 NEON_ENCODE (INTEGER, inst);
037e8744 14251 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14252 }
14253 else
14254 {
4316f0d2
DG		 14255 const int three_ops_form = (inst.operands[2].present
14256 && !inst.operands[2].isreg);
14257 const int immoperand = (three_ops_form ? 2 : 1);
14258 enum neon_shape rs = (three_ops_form
14259 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
14260 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
037e8744 14261 struct neon_type_el et = neon_check_type (2, rs,
477330fc 14262 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
21d799b5 14263 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB		 14264 unsigned immbits;
14265 int cmode;
5f4273c7 14266
5287ad62 14267 if (et.type == NT_invtype)
477330fc 14268 return;
5f4273c7 14269
4316f0d2
DG		 14270 if (three_ops_form)
14271 constraint (inst.operands[0].reg != inst.operands[1].reg,
14272 _("first and second operands shall be the same register"));
14273
88714cb8 14274 NEON_ENCODE (IMMED, inst);
5287ad62 14275
4316f0d2 14276 immbits = inst.operands[immoperand].imm;
036dc3f7
PB		 14277 if (et.size == 64)
14278 {
14279 /* .i64 is a pseudo-op, so the immediate must be a repeating
14280 pattern. */
4316f0d2
DG		 14281 if (immbits != (inst.operands[immoperand].regisimm ?
14282 inst.operands[immoperand].reg : 0))
036dc3f7
PB		 14283 {
14284 /* Set immbits to an invalid constant. */
14285 immbits = 0xdeadbeef;
14286 }
14287 }
14288
5287ad62 14289 switch (opcode)
477330fc
RM		 14290 {
14291 case N_MNEM_vbic:
14292 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14293 break;
14294
14295 case N_MNEM_vorr:
14296 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14297 break;
14298
14299 case N_MNEM_vand:
14300 /* Pseudo-instruction for VBIC. */
14301 neon_invert_size (&immbits, 0, et.size);
14302 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14303 break;
14304
14305 case N_MNEM_vorn:
14306 /* Pseudo-instruction for VORR. */
14307 neon_invert_size (&immbits, 0, et.size);
14308 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
14309 break;
14310
14311 default:
14312 abort ();
14313 }
5287ad62
JB		 14314
14315 if (cmode == FAIL)
477330fc 14316 return;
5287ad62 14317
037e8744 14318 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14319 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14320 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14321 inst.instruction |= cmode << 8;
14322 neon_write_immbits (immbits);
5f4273c7 14323
88714cb8 14324 neon_dp_fixup (&inst);
5287ad62
JB		 14325 }
14326}
14327
14328static void
14329do_neon_bitfield (void)
14330{
037e8744 14331 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 14332 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 14333 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14334}
14335
14336static void
dcbf9037 14337neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 14338 unsigned destbits)
5287ad62 14339{
037e8744 14340 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 14341 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 14342 types | N_KEY);
5287ad62
JB		 14343 if (et.type == NT_float)
14344 {
88714cb8 14345 NEON_ENCODE (FLOAT, inst);
037e8744 14346 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14347 }
14348 else
14349 {
88714cb8 14350 NEON_ENCODE (INTEGER, inst);
037e8744 14351 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB		 14352 }
14353}
14354
14355static void
14356do_neon_dyadic_if_su (void)
14357{
dcbf9037 14358 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 14359}
14360
14361static void
14362do_neon_dyadic_if_su_d (void)
14363{
14364 /* This version only allow D registers, but that constraint is enforced during
14365 operand parsing so we don't need to do anything extra here. */
dcbf9037 14366 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 14367}
14368
5287ad62
JB		 14369static void
14370do_neon_dyadic_if_i_d (void)
14371{
428e3f1f
PB		 14372 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14373 affected if we specify unsigned args. */
14374 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB		 14375}
14376
037e8744
JB		 14377enum vfp_or_neon_is_neon_bits
14378{
14379 NEON_CHECK_CC = 1,
73924fbc
MGD		 14380 NEON_CHECK_ARCH = 2,
14381 NEON_CHECK_ARCH8 = 4
037e8744
JB		 14382};
14383
14384/* Call this function if an instruction which may have belonged to the VFP or
14385 Neon instruction sets, but turned out to be a Neon instruction (due to the
14386 operand types involved, etc.). We have to check and/or fix-up a couple of
14387 things:
14388
14389 - Make sure the user hasn't attempted to make a Neon instruction
14390 conditional.
14391 - Alter the value in the condition code field if necessary.
14392 - Make sure that the arch supports Neon instructions.
14393
14394 Which of these operations take place depends on bits from enum
14395 vfp_or_neon_is_neon_bits.
14396
14397 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14398 current instruction's condition is COND_ALWAYS, the condition field is
14399 changed to inst.uncond_value. This is necessary because instructions shared
14400 between VFP and Neon may be conditional for the VFP variants only, and the
14401 unconditional Neon version must have, e.g., 0xF in the condition field. */
14402
14403static int
14404vfp_or_neon_is_neon (unsigned check)
14405{
14406 /* Conditions are always legal in Thumb mode (IT blocks). */
14407 if (!thumb_mode && (check & NEON_CHECK_CC))
14408 {
14409 if (inst.cond != COND_ALWAYS)
477330fc
RM		 14410 {
14411 first_error (_(BAD_COND));
14412 return FAIL;
14413 }
037e8744 14414 if (inst.uncond_value != -1)
477330fc 14415 inst.instruction |= inst.uncond_value << 28;
037e8744 14416 }
5f4273c7 14417
037e8744 14418 if ((check & NEON_CHECK_ARCH)
73924fbc
MGD		 14419 && !mark_feature_used (&fpu_neon_ext_v1))
14420 {
14421 first_error (_(BAD_FPU));
14422 return FAIL;
14423 }
14424
14425 if ((check & NEON_CHECK_ARCH8)
14426 && !mark_feature_used (&fpu_neon_ext_armv8))
037e8744
JB		 14427 {
14428 first_error (_(BAD_FPU));
14429 return FAIL;
14430 }
5f4273c7 14431
037e8744
JB		 14432 return SUCCESS;
14433}
14434
5287ad62
JB		 14435static void
14436do_neon_addsub_if_i (void)
14437{
037e8744
JB		 14438 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
14439 return;
14440
14441 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14442 return;
14443
5287ad62
JB		 14444 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14445 affected if we specify unsigned args. */
dcbf9037 14446 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB		 14447}
14448
14449/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14450 result to be:
14451 V<op> A,B (A is operand 0, B is operand 2)
14452 to mean:
14453 V<op> A,B,A
14454 not:
14455 V<op> A,B,B
14456 so handle that case specially. */
14457
14458static void
14459neon_exchange_operands (void)
14460{
14461 void *scratch = alloca (sizeof (inst.operands[0]));
14462 if (inst.operands[1].present)
14463 {
14464 /* Swap operands[1] and operands[2]. */
14465 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
14466 inst.operands[1] = inst.operands[2];
14467 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
14468 }
14469 else
14470 {
14471 inst.operands[1] = inst.operands[2];
14472 inst.operands[2] = inst.operands[0];
14473 }
14474}
14475
14476static void
14477neon_compare (unsigned regtypes, unsigned immtypes, int invert)
14478{
14479 if (inst.operands[2].isreg)
14480 {
14481 if (invert)
477330fc 14482 neon_exchange_operands ();
dcbf9037 14483 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB		 14484 }
14485 else
14486 {
037e8744 14487 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 14488 struct neon_type_el et = neon_check_type (2, rs,
477330fc 14489 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 14490
88714cb8 14491 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 14492 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14493 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14494 inst.instruction |= LOW4 (inst.operands[1].reg);
14495 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14496 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14497 inst.instruction |= (et.type == NT_float) << 10;
14498 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14499
88714cb8 14500 neon_dp_fixup (&inst);
5287ad62
JB		 14501 }
14502}
14503
14504static void
14505do_neon_cmp (void)
14506{
14507 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, FALSE);
14508}
14509
14510static void
14511do_neon_cmp_inv (void)
14512{
14513 neon_compare (N_SUF_32, N_S8 | N_S16 | N_S32 | N_F32, TRUE);
14514}
14515
14516static void
14517do_neon_ceq (void)
14518{
14519 neon_compare (N_IF_32, N_IF_32, FALSE);
14520}
14521
14522/* For multiply instructions, we have the possibility of 16-bit or 32-bit
14523 scalars, which are encoded in 5 bits, M : Rm.
14524 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14525 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14526 index in M. */
14527
14528static unsigned
14529neon_scalar_for_mul (unsigned scalar, unsigned elsize)
14530{
dcbf9037
JB		 14531 unsigned regno = NEON_SCALAR_REG (scalar);
14532 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB		 14533
14534 switch (elsize)
14535 {
14536 case 16:
14537 if (regno > 7 || elno > 3)
477330fc 14538 goto bad_scalar;
5287ad62 14539 return regno | (elno << 3);
5f4273c7 14540
5287ad62
JB		 14541 case 32:
14542 if (regno > 15 || elno > 1)
477330fc 14543 goto bad_scalar;
5287ad62
JB		 14544 return regno | (elno << 4);
14545
14546 default:
14547 bad_scalar:
dcbf9037 14548 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB		 14549 }
14550
14551 return 0;
14552}
14553
14554/* Encode multiply / multiply-accumulate scalar instructions. */
14555
14556static void
14557neon_mul_mac (struct neon_type_el et, int ubit)
14558{
dcbf9037
JB		 14559 unsigned scalar;
14560
14561 /* Give a more helpful error message if we have an invalid type. */
14562 if (et.type == NT_invtype)
14563 return;
5f4273c7 14564
dcbf9037 14565 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB		 14566 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14567 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14568 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
14569 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
14570 inst.instruction |= LOW4 (scalar);
14571 inst.instruction |= HI1 (scalar) << 5;
14572 inst.instruction |= (et.type == NT_float) << 8;
14573 inst.instruction |= neon_logbits (et.size) << 20;
14574 inst.instruction |= (ubit != 0) << 24;
14575
88714cb8 14576 neon_dp_fixup (&inst);
5287ad62
JB		 14577}
14578
14579static void
14580do_neon_mac_maybe_scalar (void)
14581{
037e8744
JB		 14582 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
14583 return;
14584
14585 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14586 return;
14587
5287ad62
JB		 14588 if (inst.operands[2].isscalar)
14589 {
037e8744 14590 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 14591 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14592 N_EQK, N_EQK, N_I16 | N_I32 | N_F32 | N_KEY);
88714cb8 14593 NEON_ENCODE (SCALAR, inst);
037e8744 14594 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 14595 }
14596 else
428e3f1f
PB		 14597 {
14598 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14599 affected if we specify unsigned args. */
14600 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14601 }
5287ad62
JB		 14602}
14603
62f3b8c8
PB		 14604static void
14605do_neon_fmac (void)
14606{
14607 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
14608 return;
14609
14610 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14611 return;
14612
14613 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
14614}
14615
5287ad62
JB		 14616static void
14617do_neon_tst (void)
14618{
037e8744 14619 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14620 struct neon_type_el et = neon_check_type (3, rs,
14621 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 14622 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 14623}
14624
14625/* VMUL with 3 registers allows the P8 type. The scalar version supports the
14626 same types as the MAC equivalents. The polynomial type for this instruction
14627 is encoded the same as the integer type. */
14628
14629static void
14630do_neon_mul (void)
14631{
037e8744
JB		 14632 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
14633 return;
14634
14635 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14636 return;
14637
5287ad62
JB		 14638 if (inst.operands[2].isscalar)
14639 do_neon_mac_maybe_scalar ();
14640 else
dcbf9037 14641 neon_dyadic_misc (NT_poly, N_I8 | N_I16 | N_I32 | N_F32 | N_P8, 0);
5287ad62
JB		 14642}
14643
14644static void
14645do_neon_qdmulh (void)
14646{
14647 if (inst.operands[2].isscalar)
14648 {
037e8744 14649 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 14650 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14651 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 14652 NEON_ENCODE (SCALAR, inst);
037e8744 14653 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 14654 }
14655 else
14656 {
037e8744 14657 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14658 struct neon_type_el et = neon_check_type (3, rs,
477330fc 14659 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 14660 NEON_ENCODE (INTEGER, inst);
5287ad62 14661 /* The U bit (rounding) comes from bit mask. */
037e8744 14662 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 14663 }
14664}
14665
14666static void
14667do_neon_fcmp_absolute (void)
14668{
037e8744 14669 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 14670 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
14671 /* Size field comes from bit mask. */
037e8744 14672 neon_three_same (neon_quad (rs), 1, -1);
5287ad62
JB		 14673}
14674
14675static void
14676do_neon_fcmp_absolute_inv (void)
14677{
14678 neon_exchange_operands ();
14679 do_neon_fcmp_absolute ();
14680}
14681
14682static void
14683do_neon_step (void)
14684{
037e8744 14685 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62 14686 neon_check_type (3, rs, N_EQK, N_EQK, N_F32 | N_KEY);
037e8744 14687 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 14688}
14689
14690static void
14691do_neon_abs_neg (void)
14692{
037e8744
JB		 14693 enum neon_shape rs;
14694 struct neon_type_el et;
5f4273c7 14695
037e8744
JB		 14696 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
14697 return;
14698
14699 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
14700 return;
14701
14702 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
14703 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_F32 | N_KEY);
5f4273c7 14704
5287ad62
JB		 14705 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14706 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14707 inst.instruction |= LOW4 (inst.operands[1].reg);
14708 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 14709 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 14710 inst.instruction |= (et.type == NT_float) << 10;
14711 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14712
88714cb8 14713 neon_dp_fixup (&inst);
5287ad62
JB		 14714}
14715
14716static void
14717do_neon_sli (void)
14718{
037e8744 14719 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14720 struct neon_type_el et = neon_check_type (2, rs,
14721 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14722 int imm = inst.operands[2].imm;
14723 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 14724 _("immediate out of range for insert"));
037e8744 14725 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14726}
14727
14728static void
14729do_neon_sri (void)
14730{
037e8744 14731 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14732 struct neon_type_el et = neon_check_type (2, rs,
14733 N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
14734 int imm = inst.operands[2].imm;
14735 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14736 _("immediate out of range for insert"));
037e8744 14737 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB		 14738}
14739
14740static void
14741do_neon_qshlu_imm (void)
14742{
037e8744 14743 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 14744 struct neon_type_el et = neon_check_type (2, rs,
14745 N_EQK | N_UNS, N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
14746 int imm = inst.operands[2].imm;
14747 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 14748 _("immediate out of range for shift"));
5287ad62
JB		 14749 /* Only encodes the 'U present' variant of the instruction.
14750 In this case, signed types have OP (bit 8) set to 0.
14751 Unsigned types have OP set to 1. */
14752 inst.instruction |= (et.type == NT_unsigned) << 8;
14753 /* The rest of the bits are the same as other immediate shifts. */
037e8744 14754 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 14755}
14756
14757static void
14758do_neon_qmovn (void)
14759{
14760 struct neon_type_el et = neon_check_type (2, NS_DQ,
14761 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14762 /* Saturating move where operands can be signed or unsigned, and the
14763 destination has the same signedness. */
88714cb8 14764 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14765 if (et.type == NT_unsigned)
14766 inst.instruction |= 0xc0;
14767 else
14768 inst.instruction |= 0x80;
14769 neon_two_same (0, 1, et.size / 2);
14770}
14771
14772static void
14773do_neon_qmovun (void)
14774{
14775 struct neon_type_el et = neon_check_type (2, NS_DQ,
14776 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14777 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 14778 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14779 neon_two_same (0, 1, et.size / 2);
14780}
14781
14782static void
14783do_neon_rshift_sat_narrow (void)
14784{
14785 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14786 or unsigned. If operands are unsigned, results must also be unsigned. */
14787 struct neon_type_el et = neon_check_type (2, NS_DQI,
14788 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
14789 int imm = inst.operands[2].imm;
14790 /* This gets the bounds check, size encoding and immediate bits calculation
14791 right. */
14792 et.size /= 2;
5f4273c7 14793
5287ad62
JB		 14794 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14795 VQMOVN.I<size> <Dd>, <Qm>. */
14796 if (imm == 0)
14797 {
14798 inst.operands[2].present = 0;
14799 inst.instruction = N_MNEM_vqmovn;
14800 do_neon_qmovn ();
14801 return;
14802 }
5f4273c7 14803
5287ad62 14804 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14805 _("immediate out of range"));
5287ad62
JB		 14806 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
14807}
14808
14809static void
14810do_neon_rshift_sat_narrow_u (void)
14811{
14812 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14813 or unsigned. If operands are unsigned, results must also be unsigned. */
14814 struct neon_type_el et = neon_check_type (2, NS_DQI,
14815 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
14816 int imm = inst.operands[2].imm;
14817 /* This gets the bounds check, size encoding and immediate bits calculation
14818 right. */
14819 et.size /= 2;
14820
14821 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14822 VQMOVUN.I<size> <Dd>, <Qm>. */
14823 if (imm == 0)
14824 {
14825 inst.operands[2].present = 0;
14826 inst.instruction = N_MNEM_vqmovun;
14827 do_neon_qmovun ();
14828 return;
14829 }
14830
14831 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14832 _("immediate out of range"));
5287ad62
JB		 14833 /* FIXME: The manual is kind of unclear about what value U should have in
14834 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14835 must be 1. */
14836 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
14837}
14838
14839static void
14840do_neon_movn (void)
14841{
14842 struct neon_type_el et = neon_check_type (2, NS_DQ,
14843 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 14844 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14845 neon_two_same (0, 1, et.size / 2);
14846}
14847
14848static void
14849do_neon_rshift_narrow (void)
14850{
14851 struct neon_type_el et = neon_check_type (2, NS_DQI,
14852 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
14853 int imm = inst.operands[2].imm;
14854 /* This gets the bounds check, size encoding and immediate bits calculation
14855 right. */
14856 et.size /= 2;
5f4273c7 14857
5287ad62
JB		 14858 /* If immediate is zero then we are a pseudo-instruction for
14859 VMOVN.I<size> <Dd>, <Qm> */
14860 if (imm == 0)
14861 {
14862 inst.operands[2].present = 0;
14863 inst.instruction = N_MNEM_vmovn;
14864 do_neon_movn ();
14865 return;
14866 }
5f4273c7 14867
5287ad62 14868 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 14869 _("immediate out of range for narrowing operation"));
5287ad62
JB		 14870 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
14871}
14872
14873static void
14874do_neon_shll (void)
14875{
14876 /* FIXME: Type checking when lengthening. */
14877 struct neon_type_el et = neon_check_type (2, NS_QDI,
14878 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
14879 unsigned imm = inst.operands[2].imm;
14880
14881 if (imm == et.size)
14882 {
14883 /* Maximum shift variant. */
88714cb8 14884 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 14885 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
14886 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
14887 inst.instruction |= LOW4 (inst.operands[1].reg);
14888 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
14889 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 14890
88714cb8 14891 neon_dp_fixup (&inst);
5287ad62
JB		 14892 }
14893 else
14894 {
14895 /* A more-specific type check for non-max versions. */
14896 et = neon_check_type (2, NS_QDI,
477330fc 14897 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 14898 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 14899 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
14900 }
14901}
14902
037e8744 14903/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB		 14904 the current instruction is. */
14905
6b9a8b67
MGD		 14906#define CVT_FLAVOUR_VAR \
14907 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14908 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14909 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14910 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14911 /* Half-precision conversions. */ \
14912 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14913 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14914 /* VFP instructions. */ \
14915 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14916 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14917 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14918 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14919 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14920 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14921 /* VFP instructions with bitshift. */ \
14922 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14923 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14924 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14925 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14926 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14927 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14928 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14929 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14930
14931#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14932 neon_cvt_flavour_##C,
14933
14934/* The different types of conversions we can do. */
14935enum neon_cvt_flavour
14936{
14937 CVT_FLAVOUR_VAR
14938 neon_cvt_flavour_invalid,
14939 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
14940};
14941
14942#undef CVT_VAR
14943
14944static enum neon_cvt_flavour
14945get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 14946{
6b9a8b67
MGD		 14947#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14948 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14949 if (et.type != NT_invtype) \
14950 { \
14951 inst.error = NULL; \
14952 return (neon_cvt_flavour_##C); \
5287ad62 14953 }
6b9a8b67 14954
5287ad62 14955 struct neon_type_el et;
037e8744 14956 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 14957 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB		 14958 /* The instruction versions which take an immediate take one register
14959 argument, which is extended to the width of the full register. Thus the
14960 "source" and "destination" registers must have the same width. Hack that
14961 here by making the size equal to the key (wider, in this case) operand. */
14962 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 14963
6b9a8b67
MGD		 14964 CVT_FLAVOUR_VAR;
14965
14966 return neon_cvt_flavour_invalid;
5287ad62
JB		 14967#undef CVT_VAR
14968}
14969
7e8e6784
MGD		 14970enum neon_cvt_mode
14971{
14972 neon_cvt_mode_a,
14973 neon_cvt_mode_n,
14974 neon_cvt_mode_p,
14975 neon_cvt_mode_m,
14976 neon_cvt_mode_z,
30bdf752
MGD		 14977 neon_cvt_mode_x,
14978 neon_cvt_mode_r
7e8e6784
MGD		 14979};
14980
037e8744
JB		 14981/* Neon-syntax VFP conversions. */
14982
5287ad62 14983static void
6b9a8b67 14984do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 14985{
037e8744 14986 const char *opname = 0;
5f4273c7 14987
037e8744 14988 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI)
5287ad62 14989 {
037e8744
JB		 14990 /* Conversions with immediate bitshift. */
14991 const char *enc[] =
477330fc 14992 {
6b9a8b67
MGD		 14993#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14994 CVT_FLAVOUR_VAR
14995 NULL
14996#undef CVT_VAR
477330fc 14997 };
037e8744 14998
6b9a8b67 14999 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM		 15000 {
15001 opname = enc[flavour];
15002 constraint (inst.operands[0].reg != inst.operands[1].reg,
15003 _("operands 0 and 1 must be the same register"));
15004 inst.operands[1] = inst.operands[2];
15005 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
15006 }
5287ad62
JB		 15007 }
15008 else
15009 {
037e8744
JB		 15010 /* Conversions without bitshift. */
15011 const char *enc[] =
477330fc 15012 {
6b9a8b67
MGD		 15013#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15014 CVT_FLAVOUR_VAR
15015 NULL
15016#undef CVT_VAR
477330fc 15017 };
037e8744 15018
6b9a8b67 15019 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 15020 opname = enc[flavour];
037e8744
JB		 15021 }
15022
15023 if (opname)
15024 do_vfp_nsyn_opcode (opname);
15025}
15026
15027static void
15028do_vfp_nsyn_cvtz (void)
15029{
15030 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_NULL);
6b9a8b67 15031 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB		 15032 const char *enc[] =
15033 {
6b9a8b67
MGD		 15034#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15035 CVT_FLAVOUR_VAR
15036 NULL
15037#undef CVT_VAR
037e8744
JB		 15038 };
15039
6b9a8b67 15040 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB		 15041 do_vfp_nsyn_opcode (enc[flavour]);
15042}
f31fef98 15043
037e8744 15044static void
bacebabc 15045do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD		 15046 enum neon_cvt_mode mode)
15047{
15048 int sz, op;
15049 int rm;
15050
a715796b
TG		 15051 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15052 D register operands. */
15053 if (flavour == neon_cvt_flavour_s32_f64
15054 || flavour == neon_cvt_flavour_u32_f64)
15055 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15056 _(BAD_FPU));
15057
7e8e6784
MGD		 15058 set_it_insn_type (OUTSIDE_IT_INSN);
15059
15060 switch (flavour)
15061 {
15062 case neon_cvt_flavour_s32_f64:
15063 sz = 1;
827f64ff 15064 op = 1;
7e8e6784
MGD		 15065 break;
15066 case neon_cvt_flavour_s32_f32:
15067 sz = 0;
15068 op = 1;
15069 break;
15070 case neon_cvt_flavour_u32_f64:
15071 sz = 1;
15072 op = 0;
15073 break;
15074 case neon_cvt_flavour_u32_f32:
15075 sz = 0;
15076 op = 0;
15077 break;
15078 default:
15079 first_error (_("invalid instruction shape"));
15080 return;
15081 }
15082
15083 switch (mode)
15084 {
15085 case neon_cvt_mode_a: rm = 0; break;
15086 case neon_cvt_mode_n: rm = 1; break;
15087 case neon_cvt_mode_p: rm = 2; break;
15088 case neon_cvt_mode_m: rm = 3; break;
15089 default: first_error (_("invalid rounding mode")); return;
15090 }
15091
15092 NEON_ENCODE (FPV8, inst);
15093 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
15094 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
15095 inst.instruction |= sz << 8;
15096 inst.instruction |= op << 7;
15097 inst.instruction |= rm << 16;
15098 inst.instruction |= 0xf0000000;
15099 inst.is_neon = TRUE;
15100}
15101
15102static void
15103do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB		 15104{
15105 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
8e79c3df 15106 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ, NS_NULL);
6b9a8b67 15107 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 15108
e3e535bc 15109 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 15110 if (mode == neon_cvt_mode_z
e3e535bc 15111 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
bacebabc
RM		 15112 && (flavour == neon_cvt_flavour_s32_f32
15113 || flavour == neon_cvt_flavour_u32_f32
15114 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 15115 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC		 15116 && (rs == NS_FD || rs == NS_FF))
15117 {
15118 do_vfp_nsyn_cvtz ();
15119 return;
15120 }
15121
037e8744 15122 /* VFP rather than Neon conversions. */
6b9a8b67 15123 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 15124 {
7e8e6784
MGD		 15125 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15126 do_vfp_nsyn_cvt (rs, flavour);
15127 else
15128 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
15129
037e8744
JB		 15130 return;
15131 }
15132
15133 switch (rs)
15134 {
15135 case NS_DDI:
15136 case NS_QQI:
15137 {
477330fc
RM		 15138 unsigned immbits;
15139 unsigned enctab[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
35997600 15140
477330fc
RM		 15141 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15142 return;
037e8744 15143
477330fc
RM		 15144 /* Fixed-point conversion with #0 immediate is encoded as an
15145 integer conversion. */
15146 if (inst.operands[2].present && inst.operands[2].imm == 0)
15147 goto int_encode;
35997600 15148 immbits = 32 - inst.operands[2].imm;
477330fc
RM		 15149 NEON_ENCODE (IMMED, inst);
15150 if (flavour != neon_cvt_flavour_invalid)
15151 inst.instruction |= enctab[flavour];
15152 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15153 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15154 inst.instruction |= LOW4 (inst.operands[1].reg);
15155 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15156 inst.instruction |= neon_quad (rs) << 6;
15157 inst.instruction |= 1 << 21;
15158 inst.instruction |= immbits << 16;
15159
15160 neon_dp_fixup (&inst);
037e8744
JB		 15161 }
15162 break;
15163
15164 case NS_DD:
15165 case NS_QQ:
7e8e6784
MGD		 15166 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
15167 {
15168 NEON_ENCODE (FLOAT, inst);
15169 set_it_insn_type (OUTSIDE_IT_INSN);
15170
15171 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
15172 return;
15173
15174 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15175 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15176 inst.instruction |= LOW4 (inst.operands[1].reg);
15177 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15178 inst.instruction |= neon_quad (rs) << 6;
15179 inst.instruction |= (flavour == neon_cvt_flavour_u32_f32) << 7;
15180 inst.instruction |= mode << 8;
15181 if (thumb_mode)
15182 inst.instruction |= 0xfc000000;
15183 else
15184 inst.instruction |= 0xf0000000;
15185 }
15186 else
15187 {
037e8744 15188 int_encode:
7e8e6784
MGD		 15189 {
15190 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080 };
037e8744 15191
7e8e6784 15192 NEON_ENCODE (INTEGER, inst);
037e8744 15193
7e8e6784
MGD		 15194 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15195 return;
037e8744 15196
7e8e6784
MGD		 15197 if (flavour != neon_cvt_flavour_invalid)
15198 inst.instruction |= enctab[flavour];
037e8744 15199
7e8e6784
MGD		 15200 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15201 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15202 inst.instruction |= LOW4 (inst.operands[1].reg);
15203 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15204 inst.instruction |= neon_quad (rs) << 6;
15205 inst.instruction |= 2 << 18;
037e8744 15206
7e8e6784
MGD		 15207 neon_dp_fixup (&inst);
15208 }
15209 }
15210 break;
037e8744 15211
8e79c3df
CM		 15212 /* Half-precision conversions for Advanced SIMD -- neon. */
15213 case NS_QD:
15214 case NS_DQ:
15215
15216 if ((rs == NS_DQ)
15217 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
15218 {
15219 as_bad (_("operand size must match register width"));
15220 break;
15221 }
15222
15223 if ((rs == NS_QD)
15224 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
15225 {
15226 as_bad (_("operand size must match register width"));
15227 break;
15228 }
15229
15230 if (rs == NS_DQ)
477330fc 15231 inst.instruction = 0x3b60600;
8e79c3df
CM		 15232 else
15233 inst.instruction = 0x3b60700;
15234
15235 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15236 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15237 inst.instruction |= LOW4 (inst.operands[1].reg);
15238 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 15239 neon_dp_fixup (&inst);
8e79c3df
CM		 15240 break;
15241
037e8744
JB		 15242 default:
15243 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD		 15244 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
15245 do_vfp_nsyn_cvt (rs, flavour);
15246 else
15247 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 15248 }
5287ad62
JB		 15249}
15250
e3e535bc
NC		 15251static void
15252do_neon_cvtr (void)
15253{
7e8e6784 15254 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC		 15255}
15256
15257static void
15258do_neon_cvt (void)
15259{
7e8e6784
MGD		 15260 do_neon_cvt_1 (neon_cvt_mode_z);
15261}
15262
15263static void
15264do_neon_cvta (void)
15265{
15266 do_neon_cvt_1 (neon_cvt_mode_a);
15267}
15268
15269static void
15270do_neon_cvtn (void)
15271{
15272 do_neon_cvt_1 (neon_cvt_mode_n);
15273}
15274
15275static void
15276do_neon_cvtp (void)
15277{
15278 do_neon_cvt_1 (neon_cvt_mode_p);
15279}
15280
15281static void
15282do_neon_cvtm (void)
15283{
15284 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC		 15285}
15286
8e79c3df 15287static void
c70a8987 15288do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 15289{
c70a8987
MGD		 15290 if (is_double)
15291 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 15292
c70a8987
MGD		 15293 encode_arm_vfp_reg (inst.operands[0].reg,
15294 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
15295 encode_arm_vfp_reg (inst.operands[1].reg,
15296 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
15297 inst.instruction |= to ? 0x10000 : 0;
15298 inst.instruction |= t ? 0x80 : 0;
15299 inst.instruction |= is_double ? 0x100 : 0;
15300 do_vfp_cond_or_thumb ();
15301}
8e79c3df 15302
c70a8987
MGD		 15303static void
15304do_neon_cvttb_1 (bfd_boolean t)
15305{
15306 enum neon_shape rs = neon_select_shape (NS_FF, NS_FD, NS_DF, NS_NULL);
8e79c3df 15307
c70a8987
MGD		 15308 if (rs == NS_NULL)
15309 return;
15310 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
15311 {
15312 inst.error = NULL;
15313 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
15314 }
15315 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
15316 {
15317 inst.error = NULL;
15318 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
15319 }
15320 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
15321 {
a715796b
TG		 15322 /* The VCVTB and VCVTT instructions with D-register operands
15323 don't work for SP only targets. */
15324 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15325 _(BAD_FPU));
15326
c70a8987
MGD		 15327 inst.error = NULL;
15328 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
15329 }
15330 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
15331 {
a715796b
TG		 15332 /* The VCVTB and VCVTT instructions with D-register operands
15333 don't work for SP only targets. */
15334 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
15335 _(BAD_FPU));
15336
c70a8987
MGD		 15337 inst.error = NULL;
15338 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
15339 }
15340 else
15341 return;
15342}
15343
15344static void
15345do_neon_cvtb (void)
15346{
15347 do_neon_cvttb_1 (FALSE);
8e79c3df
CM		 15348}
15349
15350
15351static void
15352do_neon_cvtt (void)
15353{
c70a8987 15354 do_neon_cvttb_1 (TRUE);
8e79c3df
CM		 15355}
15356
5287ad62
JB		 15357static void
15358neon_move_immediate (void)
15359{
037e8744
JB		 15360 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
15361 struct neon_type_el et = neon_check_type (2, rs,
15362 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 15363 unsigned immlo, immhi = 0, immbits;
c96612cc 15364 int op, cmode, float_p;
5287ad62 15365
037e8744 15366 constraint (et.type == NT_invtype,
477330fc 15367 _("operand size must be specified for immediate VMOV"));
037e8744 15368
5287ad62
JB		 15369 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15370 op = (inst.instruction & (1 << 5)) != 0;
15371
15372 immlo = inst.operands[1].imm;
15373 if (inst.operands[1].regisimm)
15374 immhi = inst.operands[1].reg;
15375
15376 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 15377 _("immediate has bits set outside the operand size"));
5287ad62 15378
c96612cc
JB		 15379 float_p = inst.operands[1].immisfloat;
15380
15381 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 15382 et.size, et.type)) == FAIL)
5287ad62
JB		 15383 {
15384 /* Invert relevant bits only. */
15385 neon_invert_size (&immlo, &immhi, et.size);
15386 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM		 15387 with one or the other; those cases are caught by
15388 neon_cmode_for_move_imm. */
5287ad62 15389 op = !op;
c96612cc
JB		 15390 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
15391 &op, et.size, et.type)) == FAIL)
477330fc
RM		 15392 {
15393 first_error (_("immediate out of range"));
15394 return;
15395 }
5287ad62
JB		 15396 }
15397
15398 inst.instruction &= ~(1 << 5);
15399 inst.instruction |= op << 5;
15400
15401 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15402 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 15403 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15404 inst.instruction |= cmode << 8;
15405
15406 neon_write_immbits (immbits);
15407}
15408
15409static void
15410do_neon_mvn (void)
15411{
15412 if (inst.operands[1].isreg)
15413 {
037e8744 15414 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 15415
88714cb8 15416 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 15417 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15418 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15419 inst.instruction |= LOW4 (inst.operands[1].reg);
15420 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 15421 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15422 }
15423 else
15424 {
88714cb8 15425 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 15426 neon_move_immediate ();
15427 }
15428
88714cb8 15429 neon_dp_fixup (&inst);
5287ad62
JB		 15430}
15431
15432/* Encode instructions of form:
15433
15434 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 15435 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB		 15436
15437static void
15438neon_mixed_length (struct neon_type_el et, unsigned size)
15439{
15440 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15441 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15442 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15443 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15444 inst.instruction |= LOW4 (inst.operands[2].reg);
15445 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15446 inst.instruction |= (et.type == NT_unsigned) << 24;
15447 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 15448
88714cb8 15449 neon_dp_fixup (&inst);
5287ad62
JB		 15450}
15451
15452static void
15453do_neon_dyadic_long (void)
15454{
15455 /* FIXME: Type checking for lengthening op. */
15456 struct neon_type_el et = neon_check_type (3, NS_QDD,
15457 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
15458 neon_mixed_length (et, et.size);
15459}
15460
15461static void
15462do_neon_abal (void)
15463{
15464 struct neon_type_el et = neon_check_type (3, NS_QDD,
15465 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
15466 neon_mixed_length (et, et.size);
15467}
15468
15469static void
15470neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
15471{
15472 if (inst.operands[2].isscalar)
15473 {
dcbf9037 15474 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 15475 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 15476 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 15477 neon_mul_mac (et, et.type == NT_unsigned);
15478 }
15479 else
15480 {
15481 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 15482 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 15483 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 15484 neon_mixed_length (et, et.size);
15485 }
15486}
15487
15488static void
15489do_neon_mac_maybe_scalar_long (void)
15490{
15491 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
15492}
15493
15494static void
15495do_neon_dyadic_wide (void)
15496{
15497 struct neon_type_el et = neon_check_type (3, NS_QQD,
15498 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
15499 neon_mixed_length (et, et.size);
15500}
15501
15502static void
15503do_neon_dyadic_narrow (void)
15504{
15505 struct neon_type_el et = neon_check_type (3, NS_QDD,
15506 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB		 15507 /* Operand sign is unimportant, and the U bit is part of the opcode,
15508 so force the operand type to integer. */
15509 et.type = NT_integer;
5287ad62
JB		 15510 neon_mixed_length (et, et.size / 2);
15511}
15512
15513static void
15514do_neon_mul_sat_scalar_long (void)
15515{
15516 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
15517}
15518
15519static void
15520do_neon_vmull (void)
15521{
15522 if (inst.operands[2].isscalar)
15523 do_neon_mac_maybe_scalar_long ();
15524 else
15525 {
15526 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 15527 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 15528
5287ad62 15529 if (et.type == NT_poly)
477330fc 15530 NEON_ENCODE (POLY, inst);
5287ad62 15531 else
477330fc 15532 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD		 15533
15534 /* For polynomial encoding the U bit must be zero, and the size must
15535 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15536 obviously, as 0b10). */
15537 if (et.size == 64)
15538 {
15539 /* Check we're on the correct architecture. */
15540 if (!mark_feature_used (&fpu_crypto_ext_armv8))
15541 inst.error =
15542 _("Instruction form not available on this architecture.");
15543
15544 et.size = 32;
15545 }
15546
5287ad62
JB		 15547 neon_mixed_length (et, et.size);
15548 }
15549}
15550
15551static void
15552do_neon_ext (void)
15553{
037e8744 15554 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB		 15555 struct neon_type_el et = neon_check_type (3, rs,
15556 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
15557 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC		 15558
15559 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
15560 _("shift out of range"));
5287ad62
JB		 15561 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15562 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15563 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15564 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15565 inst.instruction |= LOW4 (inst.operands[2].reg);
15566 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 15567 inst.instruction |= neon_quad (rs) << 6;
5287ad62 15568 inst.instruction |= imm << 8;
5f4273c7 15569
88714cb8 15570 neon_dp_fixup (&inst);
5287ad62
JB		 15571}
15572
15573static void
15574do_neon_rev (void)
15575{
037e8744 15576 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15577 struct neon_type_el et = neon_check_type (2, rs,
15578 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15579 unsigned op = (inst.instruction >> 7) & 3;
15580 /* N (width of reversed regions) is encoded as part of the bitmask. We
15581 extract it here to check the elements to be reversed are smaller.
15582 Otherwise we'd get a reserved instruction. */
15583 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
9c2799c2 15584 gas_assert (elsize != 0);
5287ad62 15585 constraint (et.size >= elsize,
477330fc 15586 _("elements must be smaller than reversal region"));
037e8744 15587 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15588}
15589
15590static void
15591do_neon_dup (void)
15592{
15593 if (inst.operands[1].isscalar)
15594 {
037e8744 15595 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 15596 struct neon_type_el et = neon_check_type (2, rs,
477330fc 15597 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 15598 unsigned sizebits = et.size >> 3;
dcbf9037 15599 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 15600 int logsize = neon_logbits (et.size);
dcbf9037 15601 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB		 15602
15603 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 15604 return;
037e8744 15605
88714cb8 15606 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 15607 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15608 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15609 inst.instruction |= LOW4 (dm);
15610 inst.instruction |= HI1 (dm) << 5;
037e8744 15611 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 15612 inst.instruction |= x << 17;
15613 inst.instruction |= sizebits << 16;
5f4273c7 15614
88714cb8 15615 neon_dp_fixup (&inst);
5287ad62
JB		 15616 }
15617 else
15618 {
037e8744
JB		 15619 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
15620 struct neon_type_el et = neon_check_type (2, rs,
477330fc 15621 N_8 | N_16 | N_32 | N_KEY, N_EQK);
5287ad62 15622 /* Duplicate ARM register to lanes of vector. */
88714cb8 15623 NEON_ENCODE (ARMREG, inst);
5287ad62 15624 switch (et.size)
477330fc
RM		 15625 {
15626 case 8: inst.instruction |= 0x400000; break;
15627 case 16: inst.instruction |= 0x000020; break;
15628 case 32: inst.instruction |= 0x000000; break;
15629 default: break;
15630 }
5287ad62
JB		 15631 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
15632 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
15633 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 15634 inst.instruction |= neon_quad (rs) << 21;
5287ad62 15635 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 15636 variants, except for the condition field. */
037e8744 15637 do_vfp_cond_or_thumb ();
5287ad62
JB		 15638 }
15639}
15640
15641/* VMOV has particularly many variations. It can be one of:
15642 0. VMOV<c><q> <Qd>, <Qm>
15643 1. VMOV<c><q> <Dd>, <Dm>
15644 (Register operations, which are VORR with Rm = Rn.)
15645 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15646 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15647 (Immediate loads.)
15648 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15649 (ARM register to scalar.)
15650 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15651 (Two ARM registers to vector.)
15652 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15653 (Scalar to ARM register.)
15654 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15655 (Vector to two ARM registers.)
037e8744
JB		 15656 8. VMOV.F32 <Sd>, <Sm>
15657 9. VMOV.F64 <Dd>, <Dm>
15658 (VFP register moves.)
15659 10. VMOV.F32 <Sd>, #imm
15660 11. VMOV.F64 <Dd>, #imm
15661 (VFP float immediate load.)
15662 12. VMOV <Rd>, <Sm>
15663 (VFP single to ARM reg.)
15664 13. VMOV <Sd>, <Rm>
15665 (ARM reg to VFP single.)
15666 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15667 (Two ARM regs to two VFP singles.)
15668 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15669 (Two VFP singles to two ARM regs.)
5f4273c7 15670
037e8744
JB		 15671 These cases can be disambiguated using neon_select_shape, except cases 1/9
15672 and 3/11 which depend on the operand type too.
5f4273c7 15673
5287ad62 15674 All the encoded bits are hardcoded by this function.
5f4273c7 15675
b7fc2769
JB		 15676 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15677 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 15678
5287ad62 15679 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 15680 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB		 15681
15682static void
15683do_neon_mov (void)
15684{
037e8744
JB		 15685 enum neon_shape rs = neon_select_shape (NS_RRFF, NS_FFRR, NS_DRR, NS_RRD,
15686 NS_QQ, NS_DD, NS_QI, NS_DI, NS_SR, NS_RS, NS_FF, NS_FI, NS_RF, NS_FR,
15687 NS_NULL);
15688 struct neon_type_el et;
15689 const char *ldconst = 0;
5287ad62 15690
037e8744 15691 switch (rs)
5287ad62 15692 {
037e8744
JB		 15693 case NS_DD: /* case 1/9. */
15694 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15695 /* It is not an error here if no type is given. */
15696 inst.error = NULL;
15697 if (et.type == NT_float && et.size == 64)
477330fc
RM		 15698 {
15699 do_vfp_nsyn_opcode ("fcpyd");
15700 break;
15701 }
037e8744 15702 /* fall through. */
5287ad62 15703
037e8744
JB		 15704 case NS_QQ: /* case 0/1. */
15705 {
477330fc
RM		 15706 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
15707 return;
15708 /* The architecture manual I have doesn't explicitly state which
15709 value the U bit should have for register->register moves, but
15710 the equivalent VORR instruction has U = 0, so do that. */
15711 inst.instruction = 0x0200110;
15712 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15713 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15714 inst.instruction |= LOW4 (inst.operands[1].reg);
15715 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15716 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15717 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15718 inst.instruction |= neon_quad (rs) << 6;
15719
15720 neon_dp_fixup (&inst);
037e8744
JB		 15721 }
15722 break;
5f4273c7 15723
037e8744
JB		 15724 case NS_DI: /* case 3/11. */
15725 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
15726 inst.error = NULL;
15727 if (et.type == NT_float && et.size == 64)
477330fc
RM		 15728 {
15729 /* case 11 (fconstd). */
15730 ldconst = "fconstd";
15731 goto encode_fconstd;
15732 }
037e8744
JB		 15733 /* fall through. */
15734
15735 case NS_QI: /* case 2/3. */
15736 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
477330fc 15737 return;
037e8744
JB		 15738 inst.instruction = 0x0800010;
15739 neon_move_immediate ();
88714cb8 15740 neon_dp_fixup (&inst);
5287ad62 15741 break;
5f4273c7 15742
037e8744
JB		 15743 case NS_SR: /* case 4. */
15744 {
477330fc
RM		 15745 unsigned bcdebits = 0;
15746 int logsize;
15747 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
15748 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 15749
05ac0ffb
JB		 15750 /* .<size> is optional here, defaulting to .32. */
15751 if (inst.vectype.elems == 0
15752 && inst.operands[0].vectype.type == NT_invtype
15753 && inst.operands[1].vectype.type == NT_invtype)
15754 {
15755 inst.vectype.el[0].type = NT_untyped;
15756 inst.vectype.el[0].size = 32;
15757 inst.vectype.elems = 1;
15758 }
15759
477330fc
RM		 15760 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
15761 logsize = neon_logbits (et.size);
15762
15763 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15764 _(BAD_FPU));
15765 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15766 && et.size != 32, _(BAD_FPU));
15767 constraint (et.type == NT_invtype, _("bad type for scalar"));
15768 constraint (x >= 64 / et.size, _("scalar index out of range"));
15769
15770 switch (et.size)
15771 {
15772 case 8: bcdebits = 0x8; break;
15773 case 16: bcdebits = 0x1; break;
15774 case 32: bcdebits = 0x0; break;
15775 default: ;
15776 }
15777
15778 bcdebits |= x << logsize;
15779
15780 inst.instruction = 0xe000b10;
15781 do_vfp_cond_or_thumb ();
15782 inst.instruction |= LOW4 (dn) << 16;
15783 inst.instruction |= HI1 (dn) << 7;
15784 inst.instruction |= inst.operands[1].reg << 12;
15785 inst.instruction |= (bcdebits & 3) << 5;
15786 inst.instruction |= (bcdebits >> 2) << 21;
037e8744
JB		 15787 }
15788 break;
5f4273c7 15789
037e8744 15790 case NS_DRR: /* case 5 (fmdrr). */
b7fc2769 15791 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
477330fc 15792 _(BAD_FPU));
b7fc2769 15793
037e8744
JB		 15794 inst.instruction = 0xc400b10;
15795 do_vfp_cond_or_thumb ();
15796 inst.instruction |= LOW4 (inst.operands[0].reg);
15797 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
15798 inst.instruction |= inst.operands[1].reg << 12;
15799 inst.instruction |= inst.operands[2].reg << 16;
15800 break;
5f4273c7 15801
037e8744
JB		 15802 case NS_RS: /* case 6. */
15803 {
477330fc
RM		 15804 unsigned logsize;
15805 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
15806 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
15807 unsigned abcdebits = 0;
037e8744 15808
05ac0ffb
JB		 15809 /* .<dt> is optional here, defaulting to .32. */
15810 if (inst.vectype.elems == 0
15811 && inst.operands[0].vectype.type == NT_invtype
15812 && inst.operands[1].vectype.type == NT_invtype)
15813 {
15814 inst.vectype.el[0].type = NT_untyped;
15815 inst.vectype.el[0].size = 32;
15816 inst.vectype.elems = 1;
15817 }
15818
91d6fa6a
NC		 15819 et = neon_check_type (2, NS_NULL,
15820 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM		 15821 logsize = neon_logbits (et.size);
15822
15823 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1),
15824 _(BAD_FPU));
15825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1)
15826 && et.size != 32, _(BAD_FPU));
15827 constraint (et.type == NT_invtype, _("bad type for scalar"));
15828 constraint (x >= 64 / et.size, _("scalar index out of range"));
15829
15830 switch (et.size)
15831 {
15832 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
15833 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
15834 case 32: abcdebits = 0x00; break;
15835 default: ;
15836 }
15837
15838 abcdebits |= x << logsize;
15839 inst.instruction = 0xe100b10;
15840 do_vfp_cond_or_thumb ();
15841 inst.instruction |= LOW4 (dn) << 16;
15842 inst.instruction |= HI1 (dn) << 7;
15843 inst.instruction |= inst.operands[0].reg << 12;
15844 inst.instruction |= (abcdebits & 3) << 5;
15845 inst.instruction |= (abcdebits >> 2) << 21;
037e8744
JB		 15846 }
15847 break;
5f4273c7 15848
037e8744
JB		 15849 case NS_RRD: /* case 7 (fmrrd). */
15850 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2),
477330fc 15851 _(BAD_FPU));
037e8744
JB		 15852
15853 inst.instruction = 0xc500b10;
15854 do_vfp_cond_or_thumb ();
15855 inst.instruction |= inst.operands[0].reg << 12;
15856 inst.instruction |= inst.operands[1].reg << 16;
15857 inst.instruction |= LOW4 (inst.operands[2].reg);
15858 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15859 break;
5f4273c7 15860
037e8744
JB		 15861 case NS_FF: /* case 8 (fcpys). */
15862 do_vfp_nsyn_opcode ("fcpys");
15863 break;
5f4273c7 15864
037e8744
JB		 15865 case NS_FI: /* case 10 (fconsts). */
15866 ldconst = "fconsts";
15867 encode_fconstd:
15868 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM		 15869 {
15870 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
15871 do_vfp_nsyn_opcode (ldconst);
15872 }
5287ad62 15873 else
477330fc 15874 first_error (_("immediate out of range"));
037e8744 15875 break;
5f4273c7 15876
037e8744
JB		 15877 case NS_RF: /* case 12 (fmrs). */
15878 do_vfp_nsyn_opcode ("fmrs");
15879 break;
5f4273c7 15880
037e8744
JB		 15881 case NS_FR: /* case 13 (fmsr). */
15882 do_vfp_nsyn_opcode ("fmsr");
15883 break;
5f4273c7 15884
037e8744
JB		 15885 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15886 (one of which is a list), but we have parsed four. Do some fiddling to
15887 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15888 expect. */
15889 case NS_RRFF: /* case 14 (fmrrs). */
15890 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 15891 _("VFP registers must be adjacent"));
037e8744
JB		 15892 inst.operands[2].imm = 2;
15893 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15894 do_vfp_nsyn_opcode ("fmrrs");
15895 break;
5f4273c7 15896
037e8744
JB		 15897 case NS_FFRR: /* case 15 (fmsrr). */
15898 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 15899 _("VFP registers must be adjacent"));
037e8744
JB		 15900 inst.operands[1] = inst.operands[2];
15901 inst.operands[2] = inst.operands[3];
15902 inst.operands[0].imm = 2;
15903 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
15904 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 15905 break;
5f4273c7 15906
4c261dff
NC		 15907 case NS_NULL:
15908 /* neon_select_shape has determined that the instruction
15909 shape is wrong and has already set the error message. */
15910 break;
15911
5287ad62
JB		 15912 default:
15913 abort ();
15914 }
15915}
15916
15917static void
15918do_neon_rshift_round_imm (void)
15919{
037e8744 15920 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
5287ad62
JB		 15921 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
15922 int imm = inst.operands[2].imm;
15923
15924 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15925 if (imm == 0)
15926 {
15927 inst.operands[2].present = 0;
15928 do_neon_mov ();
15929 return;
15930 }
15931
15932 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 15933 _("immediate out of range for shift"));
037e8744 15934 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 15935 et.size - imm);
5287ad62
JB		 15936}
15937
15938static void
15939do_neon_movl (void)
15940{
15941 struct neon_type_el et = neon_check_type (2, NS_QD,
15942 N_EQK | N_DBL, N_SU_32 | N_KEY);
15943 unsigned sizebits = et.size >> 3;
15944 inst.instruction |= sizebits << 19;
15945 neon_two_same (0, et.type == NT_unsigned, -1);
15946}
15947
15948static void
15949do_neon_trn (void)
15950{
037e8744 15951 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15952 struct neon_type_el et = neon_check_type (2, rs,
15953 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 15954 NEON_ENCODE (INTEGER, inst);
037e8744 15955 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15956}
15957
15958static void
15959do_neon_zip_uzp (void)
15960{
037e8744 15961 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15962 struct neon_type_el et = neon_check_type (2, rs,
15963 N_EQK, N_8 | N_16 | N_32 | N_KEY);
15964 if (rs == NS_DD && et.size == 32)
15965 {
15966 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15967 inst.instruction = N_MNEM_vtrn;
15968 do_neon_trn ();
15969 return;
15970 }
037e8744 15971 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15972}
15973
15974static void
15975do_neon_sat_abs_neg (void)
15976{
037e8744 15977 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15978 struct neon_type_el et = neon_check_type (2, rs,
15979 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 15980 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15981}
15982
15983static void
15984do_neon_pair_long (void)
15985{
037e8744 15986 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15987 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
15988 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15989 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 15990 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 15991}
15992
15993static void
15994do_neon_recip_est (void)
15995{
037e8744 15996 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 15997 struct neon_type_el et = neon_check_type (2, rs,
15998 N_EQK | N_FLT, N_F32 | N_U32 | N_KEY);
15999 inst.instruction |= (et.type == NT_float) << 8;
037e8744 16000 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 16001}
16002
16003static void
16004do_neon_cls (void)
16005{
037e8744 16006 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 16007 struct neon_type_el et = neon_check_type (2, rs,
16008 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 16009 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 16010}
16011
16012static void
16013do_neon_clz (void)
16014{
037e8744 16015 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 16016 struct neon_type_el et = neon_check_type (2, rs,
16017 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 16018 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 16019}
16020
16021static void
16022do_neon_cnt (void)
16023{
037e8744 16024 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 16025 struct neon_type_el et = neon_check_type (2, rs,
16026 N_EQK | N_INT, N_8 | N_KEY);
037e8744 16027 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 16028}
16029
16030static void
16031do_neon_swp (void)
16032{
037e8744
JB		 16033 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
16034 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB		 16035}
16036
16037static void
16038do_neon_tbl_tbx (void)
16039{
16040 unsigned listlenbits;
dcbf9037 16041 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 16042
5287ad62
JB		 16043 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
16044 {
dcbf9037 16045 first_error (_("bad list length for table lookup"));
5287ad62
JB		 16046 return;
16047 }
5f4273c7 16048
5287ad62
JB		 16049 listlenbits = inst.operands[1].imm - 1;
16050 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16051 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16052 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16053 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16054 inst.instruction |= LOW4 (inst.operands[2].reg);
16055 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16056 inst.instruction |= listlenbits << 8;
5f4273c7 16057
88714cb8 16058 neon_dp_fixup (&inst);
5287ad62
JB		 16059}
16060
16061static void
16062do_neon_ldm_stm (void)
16063{
16064 /* P, U and L bits are part of bitmask. */
16065 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
16066 unsigned offsetbits = inst.operands[1].imm * 2;
16067
037e8744
JB		 16068 if (inst.operands[1].issingle)
16069 {
16070 do_vfp_nsyn_ldm_stm (is_dbmode);
16071 return;
16072 }
16073
5287ad62 16074 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 16075 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB		 16076
16077 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM		 16078 _("register list must contain at least 1 and at most 16 "
16079 "registers"));
5287ad62
JB		 16080
16081 inst.instruction |= inst.operands[0].reg << 16;
16082 inst.instruction |= inst.operands[0].writeback << 21;
16083 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
16084 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
16085
16086 inst.instruction |= offsetbits;
5f4273c7 16087
037e8744 16088 do_vfp_cond_or_thumb ();
5287ad62
JB		 16089}
16090
16091static void
16092do_neon_ldr_str (void)
16093{
5287ad62 16094 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 16095
6844b2c2
MGD		 16096 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16097 And is UNPREDICTABLE in thumb mode. */
fa94de6b 16098 if (!is_ldr
6844b2c2 16099 && inst.operands[1].reg == REG_PC
ba86b375 16100 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 16101 {
94dcf8bf 16102 if (thumb_mode)
6844b2c2 16103 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf 16104 else if (warn_on_deprecated)
5c3696f8 16105 as_tsktsk (_("Use of PC here is deprecated"));
6844b2c2
MGD		 16106 }
16107
037e8744
JB		 16108 if (inst.operands[0].issingle)
16109 {
cd2f129f 16110 if (is_ldr)
477330fc 16111 do_vfp_nsyn_opcode ("flds");
cd2f129f 16112 else
477330fc 16113 do_vfp_nsyn_opcode ("fsts");
5287ad62
JB		 16114 }
16115 else
5287ad62 16116 {
cd2f129f 16117 if (is_ldr)
477330fc 16118 do_vfp_nsyn_opcode ("fldd");
5287ad62 16119 else
477330fc 16120 do_vfp_nsyn_opcode ("fstd");
5287ad62 16121 }
5287ad62
JB		 16122}
16123
16124/* "interleave" version also handles non-interleaving register VLD1/VST1
16125 instructions. */
16126
16127static void
16128do_neon_ld_st_interleave (void)
16129{
037e8744 16130 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 16131 N_8 | N_16 | N_32 | N_64);
5287ad62
JB		 16132 unsigned alignbits = 0;
16133 unsigned idx;
16134 /* The bits in this table go:
16135 0: register stride of one (0) or two (1)
16136 1,2: register list length, minus one (1, 2, 3, 4).
16137 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16138 We use -1 for invalid entries. */
16139 const int typetable[] =
16140 {
16141 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16142 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16143 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16144 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16145 };
16146 int typebits;
16147
dcbf9037
JB		 16148 if (et.type == NT_invtype)
16149 return;
16150
5287ad62
JB		 16151 if (inst.operands[1].immisalign)
16152 switch (inst.operands[1].imm >> 8)
16153 {
16154 case 64: alignbits = 1; break;
16155 case 128:
477330fc 16156 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 16157 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM		 16158 goto bad_alignment;
16159 alignbits = 2;
16160 break;
5287ad62 16161 case 256:
477330fc
RM		 16162 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
16163 goto bad_alignment;
16164 alignbits = 3;
16165 break;
5287ad62
JB		 16166 default:
16167 bad_alignment:
477330fc
RM		 16168 first_error (_("bad alignment"));
16169 return;
5287ad62
JB		 16170 }
16171
16172 inst.instruction |= alignbits << 4;
16173 inst.instruction |= neon_logbits (et.size) << 6;
16174
16175 /* Bits [4:6] of the immediate in a list specifier encode register stride
16176 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16177 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16178 up the right value for "type" in a table based on this value and the given
16179 list style, then stick it back. */
16180 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 16181 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB		 16182
16183 typebits = typetable[idx];
5f4273c7 16184
5287ad62 16185 constraint (typebits == -1, _("bad list type for instruction"));
1d50d57c
WN		 16186 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
16187 _("bad element type for instruction"));
5287ad62
JB		 16188
16189 inst.instruction &= ~0xf00;
16190 inst.instruction |= typebits << 8;
16191}
16192
16193/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16194 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16195 otherwise. The variable arguments are a list of pairs of legal (size, align)
16196 values, terminated with -1. */
16197
16198static int
16199neon_alignment_bit (int size, int align, int *do_align, ...)
16200{
16201 va_list ap;
16202 int result = FAIL, thissize, thisalign;
5f4273c7 16203
5287ad62
JB		 16204 if (!inst.operands[1].immisalign)
16205 {
16206 *do_align = 0;
16207 return SUCCESS;
16208 }
5f4273c7 16209
5287ad62
JB		 16210 va_start (ap, do_align);
16211
16212 do
16213 {
16214 thissize = va_arg (ap, int);
16215 if (thissize == -1)
477330fc 16216 break;
5287ad62
JB		 16217 thisalign = va_arg (ap, int);
16218
16219 if (size == thissize && align == thisalign)
477330fc 16220 result = SUCCESS;
5287ad62
JB		 16221 }
16222 while (result != SUCCESS);
16223
16224 va_end (ap);
16225
16226 if (result == SUCCESS)
16227 *do_align = 1;
16228 else
dcbf9037 16229 first_error (_("unsupported alignment for instruction"));
5f4273c7 16230
5287ad62
JB		 16231 return result;
16232}
16233
16234static void
16235do_neon_ld_st_lane (void)
16236{
037e8744 16237 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB		 16238 int align_good, do_align = 0;
16239 int logsize = neon_logbits (et.size);
16240 int align = inst.operands[1].imm >> 8;
16241 int n = (inst.instruction >> 8) & 3;
16242 int max_el = 64 / et.size;
5f4273c7 16243
dcbf9037
JB		 16244 if (et.type == NT_invtype)
16245 return;
5f4273c7 16246
5287ad62 16247 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 16248 _("bad list length"));
5287ad62 16249 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 16250 _("scalar index out of range"));
5287ad62 16251 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM		 16252 && et.size == 8,
16253 _("stride of 2 unavailable when element size is 8"));
5f4273c7 16254
5287ad62
JB		 16255 switch (n)
16256 {
16257 case 0: /* VLD1 / VST1. */
16258 align_good = neon_alignment_bit (et.size, align, &do_align, 16, 16,
477330fc 16259 32, 32, -1);
5287ad62 16260 if (align_good == FAIL)
477330fc 16261 return;
5287ad62 16262 if (do_align)
477330fc
RM		 16263 {
16264 unsigned alignbits = 0;
16265 switch (et.size)
16266 {
16267 case 16: alignbits = 0x1; break;
16268 case 32: alignbits = 0x3; break;
16269 default: ;
16270 }
16271 inst.instruction |= alignbits << 4;
16272 }
5287ad62
JB		 16273 break;
16274
16275 case 1: /* VLD2 / VST2. */
16276 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 16, 16, 32,
477330fc 16277 32, 64, -1);
5287ad62 16278 if (align_good == FAIL)
477330fc 16279 return;
5287ad62 16280 if (do_align)
477330fc 16281 inst.instruction |= 1 << 4;
5287ad62
JB		 16282 break;
16283
16284 case 2: /* VLD3 / VST3. */
16285 constraint (inst.operands[1].immisalign,
477330fc 16286 _("can't use alignment with this instruction"));
5287ad62
JB		 16287 break;
16288
16289 case 3: /* VLD4 / VST4. */
16290 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
477330fc 16291 16, 64, 32, 64, 32, 128, -1);
5287ad62 16292 if (align_good == FAIL)
477330fc 16293 return;
5287ad62 16294 if (do_align)
477330fc
RM		 16295 {
16296 unsigned alignbits = 0;
16297 switch (et.size)
16298 {
16299 case 8: alignbits = 0x1; break;
16300 case 16: alignbits = 0x1; break;
16301 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
16302 default: ;
16303 }
16304 inst.instruction |= alignbits << 4;
16305 }
5287ad62
JB		 16306 break;
16307
16308 default: ;
16309 }
16310
16311 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16312 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16313 inst.instruction |= 1 << (4 + logsize);
5f4273c7 16314
5287ad62
JB		 16315 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
16316 inst.instruction |= logsize << 10;
16317}
16318
16319/* Encode single n-element structure to all lanes VLD<n> instructions. */
16320
16321static void
16322do_neon_ld_dup (void)
16323{
037e8744 16324 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
5287ad62
JB		 16325 int align_good, do_align = 0;
16326
dcbf9037
JB		 16327 if (et.type == NT_invtype)
16328 return;
16329
5287ad62
JB		 16330 switch ((inst.instruction >> 8) & 3)
16331 {
16332 case 0: /* VLD1. */
9c2799c2 16333 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 16334 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
477330fc 16335 &do_align, 16, 16, 32, 32, -1);
5287ad62 16336 if (align_good == FAIL)
477330fc 16337 return;
5287ad62 16338 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM		 16339 {
16340 case 1: break;
16341 case 2: inst.instruction |= 1 << 5; break;
16342 default: first_error (_("bad list length")); return;
16343 }
5287ad62
JB		 16344 inst.instruction |= neon_logbits (et.size) << 6;
16345 break;
16346
16347 case 1: /* VLD2. */
16348 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
477330fc 16349 &do_align, 8, 16, 16, 32, 32, 64, -1);
5287ad62 16350 if (align_good == FAIL)
477330fc 16351 return;
5287ad62 16352 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 16353 _("bad list length"));
5287ad62 16354 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 16355 inst.instruction |= 1 << 5;
5287ad62
JB		 16356 inst.instruction |= neon_logbits (et.size) << 6;
16357 break;
16358
16359 case 2: /* VLD3. */
16360 constraint (inst.operands[1].immisalign,
477330fc 16361 _("can't use alignment with this instruction"));
5287ad62 16362 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 16363 _("bad list length"));
5287ad62 16364 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 16365 inst.instruction |= 1 << 5;
5287ad62
JB		 16366 inst.instruction |= neon_logbits (et.size) << 6;
16367 break;
16368
16369 case 3: /* VLD4. */
16370 {
477330fc
RM		 16371 int align = inst.operands[1].imm >> 8;
16372 align_good = neon_alignment_bit (et.size, align, &do_align, 8, 32,
16373 16, 64, 32, 64, 32, 128, -1);
16374 if (align_good == FAIL)
16375 return;
16376 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
16377 _("bad list length"));
16378 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
16379 inst.instruction |= 1 << 5;
16380 if (et.size == 32 && align == 128)
16381 inst.instruction |= 0x3 << 6;
16382 else
16383 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB		 16384 }
16385 break;
16386
16387 default: ;
16388 }
16389
16390 inst.instruction |= do_align << 4;
16391}
16392
16393/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16394 apart from bits [11:4]. */
16395
16396static void
16397do_neon_ldx_stx (void)
16398{
b1a769ed
DG		 16399 if (inst.operands[1].isreg)
16400 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16401
5287ad62
JB		 16402 switch (NEON_LANE (inst.operands[0].imm))
16403 {
16404 case NEON_INTERLEAVE_LANES:
88714cb8 16405 NEON_ENCODE (INTERLV, inst);
5287ad62
JB		 16406 do_neon_ld_st_interleave ();
16407 break;
5f4273c7 16408
5287ad62 16409 case NEON_ALL_LANES:
88714cb8 16410 NEON_ENCODE (DUP, inst);
2d51fb74
JB		 16411 if (inst.instruction == N_INV)
16412 {
16413 first_error ("only loads support such operands");
16414 break;
16415 }
5287ad62
JB		 16416 do_neon_ld_dup ();
16417 break;
5f4273c7 16418
5287ad62 16419 default:
88714cb8 16420 NEON_ENCODE (LANE, inst);
5287ad62
JB		 16421 do_neon_ld_st_lane ();
16422 }
16423
16424 /* L bit comes from bit mask. */
16425 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16426 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16427 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 16428
5287ad62
JB		 16429 if (inst.operands[1].postind)
16430 {
16431 int postreg = inst.operands[1].imm & 0xf;
16432 constraint (!inst.operands[1].immisreg,
477330fc 16433 _("post-index must be a register"));
5287ad62 16434 constraint (postreg == 0xd || postreg == 0xf,
477330fc 16435 _("bad register for post-index"));
5287ad62
JB		 16436 inst.instruction |= postreg;
16437 }
4f2374c7 16438 else
5287ad62 16439 {
4f2374c7
WN		 16440 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
16441 constraint (inst.reloc.exp.X_op != O_constant
16442 || inst.reloc.exp.X_add_number != 0,
16443 BAD_ADDR_MODE);
16444
16445 if (inst.operands[1].writeback)
16446 {
16447 inst.instruction |= 0xd;
16448 }
16449 else
16450 inst.instruction |= 0xf;
5287ad62 16451 }
5f4273c7 16452
5287ad62
JB		 16453 if (thumb_mode)
16454 inst.instruction |= 0xf9000000;
16455 else
16456 inst.instruction |= 0xf4000000;
16457}
33399f07
MGD		 16458
16459/* FP v8. */
16460static void
16461do_vfp_nsyn_fpv8 (enum neon_shape rs)
16462{
a715796b
TG		 16463 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16464 D register operands. */
16465 if (neon_shape_class[rs] == SC_DOUBLE)
16466 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16467 _(BAD_FPU));
16468
33399f07
MGD		 16469 NEON_ENCODE (FPV8, inst);
16470
16471 if (rs == NS_FFF)
16472 do_vfp_sp_dyadic ();
16473 else
16474 do_vfp_dp_rd_rn_rm ();
16475
16476 if (rs == NS_DDD)
16477 inst.instruction |= 0x100;
16478
16479 inst.instruction |= 0xf0000000;
16480}
16481
16482static void
16483do_vsel (void)
16484{
16485 set_it_insn_type (OUTSIDE_IT_INSN);
16486
16487 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
16488 first_error (_("invalid instruction shape"));
16489}
16490
73924fbc
MGD		 16491static void
16492do_vmaxnm (void)
16493{
16494 set_it_insn_type (OUTSIDE_IT_INSN);
16495
16496 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
16497 return;
16498
16499 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16500 return;
16501
16502 neon_dyadic_misc (NT_untyped, N_F32, 0);
16503}
16504
30bdf752
MGD		 16505static void
16506do_vrint_1 (enum neon_cvt_mode mode)
16507{
16508 enum neon_shape rs = neon_select_shape (NS_FF, NS_DD, NS_QQ, NS_NULL);
16509 struct neon_type_el et;
16510
16511 if (rs == NS_NULL)
16512 return;
16513
a715796b
TG		 16514 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
16515 D register operands. */
16516 if (neon_shape_class[rs] == SC_DOUBLE)
16517 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16518 _(BAD_FPU));
16519
30bdf752
MGD		 16520 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F32 | N_F64 | N_KEY | N_VFP);
16521 if (et.type != NT_invtype)
16522 {
16523 /* VFP encodings. */
16524 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
16525 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
16526 set_it_insn_type (OUTSIDE_IT_INSN);
16527
16528 NEON_ENCODE (FPV8, inst);
16529 if (rs == NS_FF)
16530 do_vfp_sp_monadic ();
16531 else
16532 do_vfp_dp_rd_rm ();
16533
16534 switch (mode)
16535 {
16536 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
16537 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
16538 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
16539 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
16540 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
16541 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
16542 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
16543 default: abort ();
16544 }
16545
16546 inst.instruction |= (rs == NS_DD) << 8;
16547 do_vfp_cond_or_thumb ();
16548 }
16549 else
16550 {
16551 /* Neon encodings (or something broken...). */
16552 inst.error = NULL;
16553 et = neon_check_type (2, rs, N_EQK, N_F32 | N_KEY);
16554
16555 if (et.type == NT_invtype)
16556 return;
16557
16558 set_it_insn_type (OUTSIDE_IT_INSN);
16559 NEON_ENCODE (FLOAT, inst);
16560
16561 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
16562 return;
16563
16564 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16565 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16566 inst.instruction |= LOW4 (inst.operands[1].reg);
16567 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16568 inst.instruction |= neon_quad (rs) << 6;
16569 switch (mode)
16570 {
16571 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
16572 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
16573 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
16574 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
16575 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
16576 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
16577 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
16578 default: abort ();
16579 }
16580
16581 if (thumb_mode)
16582 inst.instruction |= 0xfc000000;
16583 else
16584 inst.instruction |= 0xf0000000;
16585 }
16586}
16587
16588static void
16589do_vrintx (void)
16590{
16591 do_vrint_1 (neon_cvt_mode_x);
16592}
16593
16594static void
16595do_vrintz (void)
16596{
16597 do_vrint_1 (neon_cvt_mode_z);
16598}
16599
16600static void
16601do_vrintr (void)
16602{
16603 do_vrint_1 (neon_cvt_mode_r);
16604}
16605
16606static void
16607do_vrinta (void)
16608{
16609 do_vrint_1 (neon_cvt_mode_a);
16610}
16611
16612static void
16613do_vrintn (void)
16614{
16615 do_vrint_1 (neon_cvt_mode_n);
16616}
16617
16618static void
16619do_vrintp (void)
16620{
16621 do_vrint_1 (neon_cvt_mode_p);
16622}
16623
16624static void
16625do_vrintm (void)
16626{
16627 do_vrint_1 (neon_cvt_mode_m);
16628}
16629
91ff7894
MGD		 16630/* Crypto v1 instructions. */
16631static void
16632do_crypto_2op_1 (unsigned elttype, int op)
16633{
16634 set_it_insn_type (OUTSIDE_IT_INSN);
16635
16636 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
16637 == NT_invtype)
16638 return;
16639
16640 inst.error = NULL;
16641
16642 NEON_ENCODE (INTEGER, inst);
16643 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16644 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16645 inst.instruction |= LOW4 (inst.operands[1].reg);
16646 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16647 if (op != -1)
16648 inst.instruction |= op << 6;
16649
16650 if (thumb_mode)
16651 inst.instruction |= 0xfc000000;
16652 else
16653 inst.instruction |= 0xf0000000;
16654}
16655
48adcd8e
MGD		 16656static void
16657do_crypto_3op_1 (int u, int op)
16658{
16659 set_it_insn_type (OUTSIDE_IT_INSN);
16660
16661 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
16662 N_32 | N_UNT | N_KEY).type == NT_invtype)
16663 return;
16664
16665 inst.error = NULL;
16666
16667 NEON_ENCODE (INTEGER, inst);
16668 neon_three_same (1, u, 8 << op);
16669}
16670
91ff7894
MGD		 16671static void
16672do_aese (void)
16673{
16674 do_crypto_2op_1 (N_8, 0);
16675}
16676
16677static void
16678do_aesd (void)
16679{
16680 do_crypto_2op_1 (N_8, 1);
16681}
16682
16683static void
16684do_aesmc (void)
16685{
16686 do_crypto_2op_1 (N_8, 2);
16687}
16688
16689static void
16690do_aesimc (void)
16691{
16692 do_crypto_2op_1 (N_8, 3);
16693}
16694
48adcd8e
MGD		 16695static void
16696do_sha1c (void)
16697{
16698 do_crypto_3op_1 (0, 0);
16699}
16700
16701static void
16702do_sha1p (void)
16703{
16704 do_crypto_3op_1 (0, 1);
16705}
16706
16707static void
16708do_sha1m (void)
16709{
16710 do_crypto_3op_1 (0, 2);
16711}
16712
16713static void
16714do_sha1su0 (void)
16715{
16716 do_crypto_3op_1 (0, 3);
16717}
91ff7894 16718
48adcd8e
MGD		 16719static void
16720do_sha256h (void)
16721{
16722 do_crypto_3op_1 (1, 0);
16723}
16724
16725static void
16726do_sha256h2 (void)
16727{
16728 do_crypto_3op_1 (1, 1);
16729}
16730
16731static void
16732do_sha256su1 (void)
16733{
16734 do_crypto_3op_1 (1, 2);
16735}
3c9017d2
MGD		 16736
16737static void
16738do_sha1h (void)
16739{
16740 do_crypto_2op_1 (N_32, -1);
16741}
16742
16743static void
16744do_sha1su1 (void)
16745{
16746 do_crypto_2op_1 (N_32, 0);
16747}
16748
16749static void
16750do_sha256su0 (void)
16751{
16752 do_crypto_2op_1 (N_32, 1);
16753}
dd5181d5
KT		 16754
16755static void
16756do_crc32_1 (unsigned int poly, unsigned int sz)
16757{
16758 unsigned int Rd = inst.operands[0].reg;
16759 unsigned int Rn = inst.operands[1].reg;
16760 unsigned int Rm = inst.operands[2].reg;
16761
16762 set_it_insn_type (OUTSIDE_IT_INSN);
16763 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
16764 inst.instruction |= LOW4 (Rn) << 16;
16765 inst.instruction |= LOW4 (Rm);
16766 inst.instruction |= sz << (thumb_mode ? 4 : 21);
16767 inst.instruction |= poly << (thumb_mode ? 20 : 9);
16768
16769 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
16770 as_warn (UNPRED_REG ("r15"));
16771 if (thumb_mode && (Rd == REG_SP || Rn == REG_SP || Rm == REG_SP))
16772 as_warn (UNPRED_REG ("r13"));
16773}
16774
16775static void
16776do_crc32b (void)
16777{
16778 do_crc32_1 (0, 0);
16779}
16780
16781static void
16782do_crc32h (void)
16783{
16784 do_crc32_1 (0, 1);
16785}
16786
16787static void
16788do_crc32w (void)
16789{
16790 do_crc32_1 (0, 2);
16791}
16792
16793static void
16794do_crc32cb (void)
16795{
16796 do_crc32_1 (1, 0);
16797}
16798
16799static void
16800do_crc32ch (void)
16801{
16802 do_crc32_1 (1, 1);
16803}
16804
16805static void
16806do_crc32cw (void)
16807{
16808 do_crc32_1 (1, 2);
16809}
16810
5287ad62
JB		 16811\f
16812/* Overall per-instruction processing. */
16813
16814/* We need to be able to fix up arbitrary expressions in some statements.
16815 This is so that we can handle symbols that are an arbitrary distance from
16816 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16817 which returns part of an address in a form which will be valid for
16818 a data instruction. We do this by pushing the expression into a symbol
16819 in the expr_section, and creating a fix for that. */
16820
16821static void
16822fix_new_arm (fragS * frag,
16823 int where,
16824 short int size,
16825 expressionS * exp,
16826 int pc_rel,
16827 int reloc)
16828{
16829 fixS * new_fix;
16830
16831 switch (exp->X_op)
16832 {
16833 case O_constant:
6e7ce2cd
PB		 16834 if (pc_rel)
16835 {
16836 /* Create an absolute valued symbol, so we have something to
477330fc
RM		 16837 refer to in the object file. Unfortunately for us, gas's
16838 generic expression parsing will already have folded out
16839 any use of .set foo/.type foo %function that may have
16840 been used to set type information of the target location,
16841 that's being specified symbolically. We have to presume
16842 the user knows what they are doing. */
6e7ce2cd
PB		 16843 char name[16 + 8];
16844 symbolS *symbol;
16845
16846 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
16847
16848 symbol = symbol_find_or_make (name);
16849 S_SET_SEGMENT (symbol, absolute_section);
16850 symbol_set_frag (symbol, &zero_address_frag);
16851 S_SET_VALUE (symbol, exp->X_add_number);
16852 exp->X_op = O_symbol;
16853 exp->X_add_symbol = symbol;
16854 exp->X_add_number = 0;
16855 }
16856 /* FALLTHROUGH */
5287ad62
JB		 16857 case O_symbol:
16858 case O_add:
16859 case O_subtract:
21d799b5 16860 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 16861 (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 16862 break;
16863
16864 default:
21d799b5 16865 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 16866 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 16867 break;
16868 }
16869
16870 /* Mark whether the fix is to a THUMB instruction, or an ARM
16871 instruction. */
16872 new_fix->tc_fix_data = thumb_mode;
16873}
16874
16875/* Create a frg for an instruction requiring relaxation. */
16876static void
16877output_relax_insn (void)
16878{
16879 char * to;
16880 symbolS *sym;
0110f2b8
PB		 16881 int offset;
16882
6e1cb1a6
PB		 16883 /* The size of the instruction is unknown, so tie the debug info to the
16884 start of the instruction. */
16885 dwarf2_emit_insn (0);
6e1cb1a6 16886
0110f2b8
PB		 16887 switch (inst.reloc.exp.X_op)
16888 {
16889 case O_symbol:
16890 sym = inst.reloc.exp.X_add_symbol;
16891 offset = inst.reloc.exp.X_add_number;
16892 break;
16893 case O_constant:
16894 sym = NULL;
16895 offset = inst.reloc.exp.X_add_number;
16896 break;
16897 default:
16898 sym = make_expr_symbol (&inst.reloc.exp);
16899 offset = 0;
16900 break;
16901 }
16902 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
16903 inst.relax, sym, offset, NULL/*offset, opcode*/);
16904 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB		 16905}
16906
16907/* Write a 32-bit thumb instruction to buf. */
16908static void
16909put_thumb32_insn (char * buf, unsigned long insn)
16910{
16911 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
16912 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
16913}
16914
b99bd4ef 16915static void
c19d1205 16916output_inst (const char * str)
b99bd4ef 16917{
c19d1205 16918 char * to = NULL;
b99bd4ef 16919
c19d1205 16920 if (inst.error)
b99bd4ef 16921 {
c19d1205 16922 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC		 16923 return;
16924 }
5f4273c7
NC		 16925 if (inst.relax)
16926 {
16927 output_relax_insn ();
0110f2b8 16928 return;
5f4273c7 16929 }
c19d1205
ZW		 16930 if (inst.size == 0)
16931 return;
b99bd4ef 16932
c19d1205 16933 to = frag_more (inst.size);
8dc2430f
NC		 16934 /* PR 9814: Record the thumb mode into the current frag so that we know
16935 what type of NOP padding to use, if necessary. We override any previous
16936 setting so that if the mode has changed then the NOPS that we use will
16937 match the encoding of the last instruction in the frag. */
cd000bff 16938 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW		 16939
16940 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 16941 {
9c2799c2 16942 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 16943 put_thumb32_insn (to, inst.instruction);
b99bd4ef 16944 }
c19d1205 16945 else if (inst.size > INSN_SIZE)
b99bd4ef 16946 {
9c2799c2 16947 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW		 16948 md_number_to_chars (to, inst.instruction, INSN_SIZE);
16949 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 16950 }
c19d1205
ZW		 16951 else
16952 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 16953
c19d1205
ZW		 16954 if (inst.reloc.type != BFD_RELOC_UNUSED)
16955 fix_new_arm (frag_now, to - frag_now->fr_literal,
16956 inst.size, & inst.reloc.exp, inst.reloc.pc_rel,
16957 inst.reloc.type);
b99bd4ef 16958
c19d1205 16959 dwarf2_emit_insn (inst.size);
c19d1205 16960}
b99bd4ef 16961
e07e6e58
NC		 16962static char *
16963output_it_inst (int cond, int mask, char * to)
16964{
16965 unsigned long instruction = 0xbf00;
16966
16967 mask &= 0xf;
16968 instruction |= mask;
16969 instruction |= cond << 4;
16970
16971 if (to == NULL)
16972 {
16973 to = frag_more (2);
16974#ifdef OBJ_ELF
16975 dwarf2_emit_insn (2);
16976#endif
16977 }
16978
16979 md_number_to_chars (to, instruction, 2);
16980
16981 return to;
16982}
16983
c19d1205
ZW		 16984/* Tag values used in struct asm_opcode's tag field. */
16985enum opcode_tag
16986{
16987 OT_unconditional, /* Instruction cannot be conditionalized.
16988 The ARM condition field is still 0xE. */
16989 OT_unconditionalF, /* Instruction cannot be conditionalized
16990 and carries 0xF in its ARM condition field. */
16991 OT_csuffix, /* Instruction takes a conditional suffix. */
037e8744 16992 OT_csuffixF, /* Some forms of the instruction take a conditional
477330fc
RM		 16993 suffix, others place 0xF where the condition field
16994 would be. */
c19d1205
ZW		 16995 OT_cinfix3, /* Instruction takes a conditional infix,
16996 beginning at character index 3. (In
16997 unified mode, it becomes a suffix.) */
088fa78e
KH		 16998 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
16999 tsts, cmps, cmns, and teqs. */
e3cb604e
PB		 17000 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
17001 character index 3, even in unified mode. Used for
17002 legacy instructions where suffix and infix forms
17003 may be ambiguous. */
c19d1205 17004 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 17005 suffix or an infix at character index 3. */
c19d1205
ZW		 17006 OT_odd_infix_unc, /* This is the unconditional variant of an
17007 instruction that takes a conditional infix
17008 at an unusual position. In unified mode,
17009 this variant will accept a suffix. */
17010 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
17011 are the conditional variants of instructions that
17012 take conditional infixes in unusual positions.
17013 The infix appears at character index
17014 (tag - OT_odd_infix_0). These are not accepted
17015 in unified mode. */
17016};
b99bd4ef 17017
c19d1205
ZW		 17018/* Subroutine of md_assemble, responsible for looking up the primary
17019 opcode from the mnemonic the user wrote. STR points to the
17020 beginning of the mnemonic.
17021
17022 This is not simply a hash table lookup, because of conditional
17023 variants. Most instructions have conditional variants, which are
17024 expressed with a _conditional affix_ to the mnemonic. If we were
17025 to encode each conditional variant as a literal string in the opcode
17026 table, it would have approximately 20,000 entries.
17027
17028 Most mnemonics take this affix as a suffix, and in unified syntax,
17029 'most' is upgraded to 'all'. However, in the divided syntax, some
17030 instructions take the affix as an infix, notably the s-variants of
17031 the arithmetic instructions. Of those instructions, all but six
17032 have the infix appear after the third character of the mnemonic.
17033
17034 Accordingly, the algorithm for looking up primary opcodes given
17035 an identifier is:
17036
17037 1. Look up the identifier in the opcode table.
17038 If we find a match, go to step U.
17039
17040 2. Look up the last two characters of the identifier in the
17041 conditions table. If we find a match, look up the first N-2
17042 characters of the identifier in the opcode table. If we
17043 find a match, go to step CE.
17044
17045 3. Look up the fourth and fifth characters of the identifier in
17046 the conditions table. If we find a match, extract those
17047 characters from the identifier, and look up the remaining
17048 characters in the opcode table. If we find a match, go
17049 to step CM.
17050
17051 4. Fail.
17052
17053 U. Examine the tag field of the opcode structure, in case this is
17054 one of the six instructions with its conditional infix in an
17055 unusual place. If it is, the tag tells us where to find the
17056 infix; look it up in the conditions table and set inst.cond
17057 accordingly. Otherwise, this is an unconditional instruction.
17058 Again set inst.cond accordingly. Return the opcode structure.
17059
17060 CE. Examine the tag field to make sure this is an instruction that
17061 should receive a conditional suffix. If it is not, fail.
17062 Otherwise, set inst.cond from the suffix we already looked up,
17063 and return the opcode structure.
17064
17065 CM. Examine the tag field to make sure this is an instruction that
17066 should receive a conditional infix after the third character.
17067 If it is not, fail. Otherwise, undo the edits to the current
17068 line of input and proceed as for case CE. */
17069
17070static const struct asm_opcode *
17071opcode_lookup (char **str)
17072{
17073 char *end, *base;
17074 char *affix;
17075 const struct asm_opcode *opcode;
17076 const struct asm_cond *cond;
e3cb604e 17077 char save[2];
c19d1205
ZW		 17078
17079 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 17080 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 17081 for (base = end = *str; *end != '\0'; end++)
721a8186 17082 if (*end == ' ' || *end == '.')
c19d1205 17083 break;
b99bd4ef 17084
c19d1205 17085 if (end == base)
c921be7d 17086 return NULL;
b99bd4ef 17087
5287ad62 17088 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 17089 if (end[0] == '.')
b99bd4ef 17090 {
5287ad62 17091 int offset = 2;
5f4273c7 17092
267d2029 17093 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 17094 use. */
267d2029 17095 if (unified_syntax && end[1] == 'w')
c19d1205 17096 inst.size_req = 4;
267d2029 17097 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW		 17098 inst.size_req = 2;
17099 else
477330fc 17100 offset = 0;
5287ad62
JB		 17101
17102 inst.vectype.elems = 0;
17103
17104 *str = end + offset;
b99bd4ef 17105
5f4273c7 17106 if (end[offset] == '.')
5287ad62 17107 {
267d2029 17108 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM		 17109 non-unified ARM syntax mode). */
17110 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 17111 return NULL;
477330fc 17112 }
5287ad62 17113 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 17114 return NULL;
b99bd4ef 17115 }
c19d1205
ZW		 17116 else
17117 *str = end;
b99bd4ef 17118
c19d1205 17119 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 17120 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 17121 end - base);
c19d1205 17122 if (opcode)
b99bd4ef 17123 {
c19d1205
ZW		 17124 /* step U */
17125 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 17126 {
c19d1205
ZW		 17127 inst.cond = COND_ALWAYS;
17128 return opcode;
b99bd4ef 17129 }
b99bd4ef 17130
278df34e 17131 if (warn_on_deprecated && unified_syntax)
5c3696f8 17132 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205 17133 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 17134 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 17135 gas_assert (cond);
b99bd4ef 17136
c19d1205
ZW		 17137 inst.cond = cond->value;
17138 return opcode;
17139 }
b99bd4ef 17140
c19d1205
ZW		 17141 /* Cannot have a conditional suffix on a mnemonic of less than two
17142 characters. */
17143 if (end - base < 3)
c921be7d 17144 return NULL;
b99bd4ef 17145
c19d1205
ZW		 17146 /* Look for suffixed mnemonic. */
17147 affix = end - 2;
21d799b5
NC		 17148 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
17149 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 17150 affix - base);
c19d1205
ZW		 17151 if (opcode && cond)
17152 {
17153 /* step CE */
17154 switch (opcode->tag)
17155 {
e3cb604e
PB		 17156 case OT_cinfix3_legacy:
17157 /* Ignore conditional suffixes matched on infix only mnemonics. */
17158 break;
17159
c19d1205 17160 case OT_cinfix3:
088fa78e 17161 case OT_cinfix3_deprecated:
c19d1205
ZW		 17162 case OT_odd_infix_unc:
17163 if (!unified_syntax)
e3cb604e 17164 return 0;
c19d1205
ZW		 17165 /* else fall through */
17166
17167 case OT_csuffix:
477330fc 17168 case OT_csuffixF:
c19d1205
ZW		 17169 case OT_csuf_or_in3:
17170 inst.cond = cond->value;
17171 return opcode;
17172
17173 case OT_unconditional:
17174 case OT_unconditionalF:
dfa9f0d5 17175 if (thumb_mode)
c921be7d 17176 inst.cond = cond->value;
dfa9f0d5
PB		 17177 else
17178 {
c921be7d 17179 /* Delayed diagnostic. */
dfa9f0d5
PB		 17180 inst.error = BAD_COND;
17181 inst.cond = COND_ALWAYS;
17182 }
c19d1205 17183 return opcode;
b99bd4ef 17184
c19d1205 17185 default:
c921be7d 17186 return NULL;
c19d1205
ZW		 17187 }
17188 }
b99bd4ef 17189
c19d1205
ZW		 17190 /* Cannot have a usual-position infix on a mnemonic of less than
17191 six characters (five would be a suffix). */
17192 if (end - base < 6)
c921be7d 17193 return NULL;
b99bd4ef 17194
c19d1205
ZW		 17195 /* Look for infixed mnemonic in the usual position. */
17196 affix = base + 3;
21d799b5 17197 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 17198 if (!cond)
c921be7d 17199 return NULL;
e3cb604e
PB		 17200
17201 memcpy (save, affix, 2);
17202 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 17203 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 17204 (end - base) - 2);
e3cb604e
PB		 17205 memmove (affix + 2, affix, (end - affix) - 2);
17206 memcpy (affix, save, 2);
17207
088fa78e
KH		 17208 if (opcode
17209 && (opcode->tag == OT_cinfix3
17210 || opcode->tag == OT_cinfix3_deprecated
17211 || opcode->tag == OT_csuf_or_in3
17212 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 17213 {
c921be7d 17214 /* Step CM. */
278df34e 17215 if (warn_on_deprecated && unified_syntax
088fa78e
KH		 17216 && (opcode->tag == OT_cinfix3
17217 || opcode->tag == OT_cinfix3_deprecated))
5c3696f8 17218 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205
ZW		 17219
17220 inst.cond = cond->value;
17221 return opcode;
b99bd4ef
NC		 17222 }
17223
c921be7d 17224 return NULL;
b99bd4ef
NC		 17225}
17226
e07e6e58
NC		 17227/* This function generates an initial IT instruction, leaving its block
17228 virtually open for the new instructions. Eventually,
17229 the mask will be updated by now_it_add_mask () each time
17230 a new instruction needs to be included in the IT block.
17231 Finally, the block is closed with close_automatic_it_block ().
17232 The block closure can be requested either from md_assemble (),
17233 a tencode (), or due to a label hook. */
17234
17235static void
17236new_automatic_it_block (int cond)
17237{
17238 now_it.state = AUTOMATIC_IT_BLOCK;
17239 now_it.mask = 0x18;
17240 now_it.cc = cond;
17241 now_it.block_length = 1;
cd000bff 17242 mapping_state (MAP_THUMB);
e07e6e58 17243 now_it.insn = output_it_inst (cond, now_it.mask, NULL);
5a01bb1d
MGD		 17244 now_it.warn_deprecated = FALSE;
17245 now_it.insn_cond = TRUE;
e07e6e58
NC		 17246}
17247
17248/* Close an automatic IT block.
17249 See comments in new_automatic_it_block (). */
17250
17251static void
17252close_automatic_it_block (void)
17253{
17254 now_it.mask = 0x10;
17255 now_it.block_length = 0;
17256}
17257
17258/* Update the mask of the current automatically-generated IT
17259 instruction. See comments in new_automatic_it_block (). */
17260
17261static void
17262now_it_add_mask (int cond)
17263{
17264#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17265#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 17266 | ((bitvalue) << (nbit)))
e07e6e58 17267 const int resulting_bit = (cond & 1);
c921be7d 17268
e07e6e58
NC		 17269 now_it.mask &= 0xf;
17270 now_it.mask = SET_BIT_VALUE (now_it.mask,
477330fc
RM		 17271 resulting_bit,
17272 (5 - now_it.block_length));
e07e6e58 17273 now_it.mask = SET_BIT_VALUE (now_it.mask,
477330fc
RM		 17274 1,
17275 ((5 - now_it.block_length) - 1) );
e07e6e58
NC		 17276 output_it_inst (now_it.cc, now_it.mask, now_it.insn);
17277
17278#undef CLEAR_BIT
17279#undef SET_BIT_VALUE
e07e6e58
NC		 17280}
17281
17282/* The IT blocks handling machinery is accessed through the these functions:
17283 it_fsm_pre_encode () from md_assemble ()
17284 set_it_insn_type () optional, from the tencode functions
17285 set_it_insn_type_last () ditto
17286 in_it_block () ditto
17287 it_fsm_post_encode () from md_assemble ()
17288 force_automatic_it_block_close () from label habdling functions
17289
17290 Rationale:
17291 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM		 17292 initializing the IT insn type with a generic initial value depending
17293 on the inst.condition.
e07e6e58 17294 2) During the tencode function, two things may happen:
477330fc
RM		 17295 a) The tencode function overrides the IT insn type by
17296 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17297 b) The tencode function queries the IT block state by
17298 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17299
17300 Both set_it_insn_type and in_it_block run the internal FSM state
17301 handling function (handle_it_state), because: a) setting the IT insn
17302 type may incur in an invalid state (exiting the function),
17303 and b) querying the state requires the FSM to be updated.
17304 Specifically we want to avoid creating an IT block for conditional
17305 branches, so it_fsm_pre_encode is actually a guess and we can't
17306 determine whether an IT block is required until the tencode () routine
17307 has decided what type of instruction this actually it.
17308 Because of this, if set_it_insn_type and in_it_block have to be used,
17309 set_it_insn_type has to be called first.
17310
17311 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17312 determines the insn IT type depending on the inst.cond code.
17313 When a tencode () routine encodes an instruction that can be
17314 either outside an IT block, or, in the case of being inside, has to be
17315 the last one, set_it_insn_type_last () will determine the proper
17316 IT instruction type based on the inst.cond code. Otherwise,
17317 set_it_insn_type can be called for overriding that logic or
17318 for covering other cases.
17319
17320 Calling handle_it_state () may not transition the IT block state to
17321 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17322 still queried. Instead, if the FSM determines that the state should
17323 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17324 after the tencode () function: that's what it_fsm_post_encode () does.
17325
17326 Since in_it_block () calls the state handling function to get an
17327 updated state, an error may occur (due to invalid insns combination).
17328 In that case, inst.error is set.
17329 Therefore, inst.error has to be checked after the execution of
17330 the tencode () routine.
e07e6e58
NC		 17331
17332 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc
RM		 17333 any pending state change (if any) that didn't take place in
17334 handle_it_state () as explained above. */
e07e6e58
NC		 17335
17336static void
17337it_fsm_pre_encode (void)
17338{
17339 if (inst.cond != COND_ALWAYS)
17340 inst.it_insn_type = INSIDE_IT_INSN;
17341 else
17342 inst.it_insn_type = OUTSIDE_IT_INSN;
17343
17344 now_it.state_handled = 0;
17345}
17346
17347/* IT state FSM handling function. */
17348
17349static int
17350handle_it_state (void)
17351{
17352 now_it.state_handled = 1;
5a01bb1d 17353 now_it.insn_cond = FALSE;
e07e6e58
NC		 17354
17355 switch (now_it.state)
17356 {
17357 case OUTSIDE_IT_BLOCK:
17358 switch (inst.it_insn_type)
17359 {
17360 case OUTSIDE_IT_INSN:
17361 break;
17362
17363 case INSIDE_IT_INSN:
17364 case INSIDE_IT_LAST_INSN:
17365 if (thumb_mode == 0)
17366 {
c921be7d 17367 if (unified_syntax
e07e6e58
NC		 17368 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
17369 as_tsktsk (_("Warning: conditional outside an IT block"\
17370 " for Thumb."));
17371 }
17372 else
17373 {
17374 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
17375 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2))
17376 {
17377 /* Automatically generate the IT instruction. */
17378 new_automatic_it_block (inst.cond);
17379 if (inst.it_insn_type == INSIDE_IT_LAST_INSN)
17380 close_automatic_it_block ();
17381 }
17382 else
17383 {
17384 inst.error = BAD_OUT_IT;
17385 return FAIL;
17386 }
17387 }
17388 break;
17389
17390 case IF_INSIDE_IT_LAST_INSN:
17391 case NEUTRAL_IT_INSN:
17392 break;
17393
17394 case IT_INSN:
17395 now_it.state = MANUAL_IT_BLOCK;
17396 now_it.block_length = 0;
17397 break;
17398 }
17399 break;
17400
17401 case AUTOMATIC_IT_BLOCK:
17402 /* Three things may happen now:
17403 a) We should increment current it block size;
17404 b) We should close current it block (closing insn or 4 insns);
17405 c) We should close current it block and start a new one (due
17406 to incompatible conditions or
17407 4 insns-length block reached). */
17408
17409 switch (inst.it_insn_type)
17410 {
17411 case OUTSIDE_IT_INSN:
17412 /* The closure of the block shall happen immediatelly,
17413 so any in_it_block () call reports the block as closed. */
17414 force_automatic_it_block_close ();
17415 break;
17416
17417 case INSIDE_IT_INSN:
17418 case INSIDE_IT_LAST_INSN:
17419 case IF_INSIDE_IT_LAST_INSN:
17420 now_it.block_length++;
17421
17422 if (now_it.block_length > 4
17423 || !now_it_compatible (inst.cond))
17424 {
17425 force_automatic_it_block_close ();
17426 if (inst.it_insn_type != IF_INSIDE_IT_LAST_INSN)
17427 new_automatic_it_block (inst.cond);
17428 }
17429 else
17430 {
5a01bb1d 17431 now_it.insn_cond = TRUE;
e07e6e58
NC		 17432 now_it_add_mask (inst.cond);
17433 }
17434
17435 if (now_it.state == AUTOMATIC_IT_BLOCK
17436 && (inst.it_insn_type == INSIDE_IT_LAST_INSN
17437 || inst.it_insn_type == IF_INSIDE_IT_LAST_INSN))
17438 close_automatic_it_block ();
17439 break;
17440
17441 case NEUTRAL_IT_INSN:
17442 now_it.block_length++;
5a01bb1d 17443 now_it.insn_cond = TRUE;
e07e6e58
NC		 17444
17445 if (now_it.block_length > 4)
17446 force_automatic_it_block_close ();
17447 else
17448 now_it_add_mask (now_it.cc & 1);
17449 break;
17450
17451 case IT_INSN:
17452 close_automatic_it_block ();
17453 now_it.state = MANUAL_IT_BLOCK;
17454 break;
17455 }
17456 break;
17457
17458 case MANUAL_IT_BLOCK:
17459 {
17460 /* Check conditional suffixes. */
17461 const int cond = now_it.cc ^ ((now_it.mask >> 4) & 1) ^ 1;
17462 int is_last;
17463 now_it.mask <<= 1;
17464 now_it.mask &= 0x1f;
17465 is_last = (now_it.mask == 0x10);
5a01bb1d 17466 now_it.insn_cond = TRUE;
e07e6e58
NC		 17467
17468 switch (inst.it_insn_type)
17469 {
17470 case OUTSIDE_IT_INSN:
17471 inst.error = BAD_NOT_IT;
17472 return FAIL;
17473
17474 case INSIDE_IT_INSN:
17475 if (cond != inst.cond)
17476 {
17477 inst.error = BAD_IT_COND;
17478 return FAIL;
17479 }
17480 break;
17481
17482 case INSIDE_IT_LAST_INSN:
17483 case IF_INSIDE_IT_LAST_INSN:
17484 if (cond != inst.cond)
17485 {
17486 inst.error = BAD_IT_COND;
17487 return FAIL;
17488 }
17489 if (!is_last)
17490 {
17491 inst.error = BAD_BRANCH;
17492 return FAIL;
17493 }
17494 break;
17495
17496 case NEUTRAL_IT_INSN:
17497 /* The BKPT instruction is unconditional even in an IT block. */
17498 break;
17499
17500 case IT_INSN:
17501 inst.error = BAD_IT_IT;
17502 return FAIL;
17503 }
17504 }
17505 break;
17506 }
17507
17508 return SUCCESS;
17509}
17510
5a01bb1d
MGD		 17511struct depr_insn_mask
17512{
17513 unsigned long pattern;
17514 unsigned long mask;
17515 const char* description;
17516};
17517
17518/* List of 16-bit instruction patterns deprecated in an IT block in
17519 ARMv8. */
17520static const struct depr_insn_mask depr_it_insns[] = {
17521 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17522 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17523 { 0xa000, 0xb800, N_("ADR") },
17524 { 0x4800, 0xf800, N_("Literal loads") },
17525 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17526 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
c8de034b
JW		 17527 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
17528 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
17529 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
5a01bb1d
MGD		 17530 { 0, 0, NULL }
17531};
17532
e07e6e58
NC		 17533static void
17534it_fsm_post_encode (void)
17535{
17536 int is_last;
17537
17538 if (!now_it.state_handled)
17539 handle_it_state ();
17540
5a01bb1d
MGD		 17541 if (now_it.insn_cond
17542 && !now_it.warn_deprecated
17543 && warn_on_deprecated
17544 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
17545 {
17546 if (inst.instruction >= 0x10000)
17547 {
5c3696f8 17548 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
5a01bb1d
MGD		 17549 "deprecated in ARMv8"));
17550 now_it.warn_deprecated = TRUE;
17551 }
17552 else
17553 {
17554 const struct depr_insn_mask *p = depr_it_insns;
17555
17556 while (p->mask != 0)
17557 {
17558 if ((inst.instruction & p->mask) == p->pattern)
17559 {
5c3696f8 17560 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
5a01bb1d
MGD		 17561 "of the following class are deprecated in ARMv8: "
17562 "%s"), p->description);
17563 now_it.warn_deprecated = TRUE;
17564 break;
17565 }
17566
17567 ++p;
17568 }
17569 }
17570
17571 if (now_it.block_length > 1)
17572 {
5c3696f8 17573 as_tsktsk (_("IT blocks containing more than one conditional "
0a8897c7 17574 "instruction are deprecated in ARMv8"));
5a01bb1d
MGD		 17575 now_it.warn_deprecated = TRUE;
17576 }
17577 }
17578
e07e6e58
NC		 17579 is_last = (now_it.mask == 0x10);
17580 if (is_last)
17581 {
17582 now_it.state = OUTSIDE_IT_BLOCK;
17583 now_it.mask = 0;
17584 }
17585}
17586
17587static void
17588force_automatic_it_block_close (void)
17589{
17590 if (now_it.state == AUTOMATIC_IT_BLOCK)
17591 {
17592 close_automatic_it_block ();
17593 now_it.state = OUTSIDE_IT_BLOCK;
17594 now_it.mask = 0;
17595 }
17596}
17597
17598static int
17599in_it_block (void)
17600{
17601 if (!now_it.state_handled)
17602 handle_it_state ();
17603
17604 return now_it.state != OUTSIDE_IT_BLOCK;
17605}
17606
c19d1205
ZW		 17607void
17608md_assemble (char *str)
b99bd4ef 17609{
c19d1205
ZW		 17610 char *p = str;
17611 const struct asm_opcode * opcode;
b99bd4ef 17612
c19d1205
ZW		 17613 /* Align the previous label if needed. */
17614 if (last_label_seen != NULL)
b99bd4ef 17615 {
c19d1205
ZW		 17616 symbol_set_frag (last_label_seen, frag_now);
17617 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
17618 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC		 17619 }
17620
c19d1205
ZW		 17621 memset (&inst, '\0', sizeof (inst));
17622 inst.reloc.type = BFD_RELOC_UNUSED;
b99bd4ef 17623
c19d1205
ZW		 17624 opcode = opcode_lookup (&p);
17625 if (!opcode)
b99bd4ef 17626 {
c19d1205 17627 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 17628 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 17629 if (! create_register_alias (str, p)
477330fc 17630 && ! create_neon_reg_alias (str, p))
c19d1205 17631 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 17632
b99bd4ef
NC		 17633 return;
17634 }
17635
278df34e 17636 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
5c3696f8 17637 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
088fa78e 17638
037e8744
JB		 17639 /* The value which unconditional instructions should have in place of the
17640 condition field. */
17641 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
17642
c19d1205 17643 if (thumb_mode)
b99bd4ef 17644 {
e74cfd16 17645 arm_feature_set variant;
8f06b2d8
PB		 17646
17647 variant = cpu_variant;
17648 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB		 17649 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
17650 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 17651 /* Check that this instruction is supported for this CPU. */
62b3e311
PB		 17652 if (!opcode->tvariant
17653 || (thumb_mode == 1
17654 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 17655 {
bf3eeda7 17656 as_bad (_("selected processor does not support Thumb mode `%s'"), str);
b99bd4ef
NC		 17657 return;
17658 }
c19d1205
ZW		 17659 if (inst.cond != COND_ALWAYS && !unified_syntax
17660 && opcode->tencode != do_t_branch)
b99bd4ef 17661 {
c19d1205 17662 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC		 17663 return;
17664 }
17665
752d5da4 17666 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2))
076d447c 17667 {
7e806470 17668 if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
752d5da4
NC		 17669 && !(ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr)
17670 || ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_barrier)))
17671 {
17672 /* Two things are addressed here.
17673 1) Implicit require narrow instructions on Thumb-1.
17674 This avoids relaxation accidentally introducing Thumb-2
17675 instructions.
17676 2) Reject wide instructions in non Thumb-2 cores. */
17677 if (inst.size_req == 0)
17678 inst.size_req = 2;
17679 else if (inst.size_req == 4)
17680 {
bf3eeda7 17681 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str);
752d5da4
NC		 17682 return;
17683 }
17684 }
076d447c
PB		 17685 }
17686
c19d1205
ZW		 17687 inst.instruction = opcode->tvalue;
17688
5be8be5d 17689 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc
RM		 17690 {
17691 /* Prepare the it_insn_type for those encodings that don't set
17692 it. */
17693 it_fsm_pre_encode ();
c19d1205 17694
477330fc 17695 opcode->tencode ();
e07e6e58 17696
477330fc
RM		 17697 it_fsm_post_encode ();
17698 }
e27ec89e 17699
0110f2b8 17700 if (!(inst.error || inst.relax))
b99bd4ef 17701 {
9c2799c2 17702 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW		 17703 inst.size = (inst.instruction > 0xffff ? 4 : 2);
17704 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 17705 {
c19d1205 17706 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC		 17707 return;
17708 }
17709 }
076d447c
PB		 17710
17711 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 17712 instruction. */
9c2799c2 17713 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 17714
e74cfd16
PB		 17715 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17716 *opcode->tvariant);
ee065d83 17717 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
708587a4 17718 set those bits when Thumb-2 32-bit instructions are seen. ie.
7e806470 17719 anything other than bl/blx and v6-M instructions.
3cfdb781
TG		 17720 The impact of relaxable instructions will be considered later after we
17721 finish all relaxation. */
17722 if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
e07e6e58
NC		 17723 && !(ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
17724 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)))
e74cfd16
PB		 17725 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
17726 arm_ext_v6t2);
cd000bff 17727
88714cb8
DG		 17728 check_neon_suffixes;
17729
cd000bff 17730 if (!inst.error)
c877a2f2
NC		 17731 {
17732 mapping_state (MAP_THUMB);
17733 }
c19d1205 17734 }
3e9e4fcf 17735 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 17736 {
845b51d6
PB		 17737 bfd_boolean is_bx;
17738
17739 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17740 is_bx = (opcode->aencode == do_bx);
17741
c19d1205 17742 /* Check that this instruction is supported for this CPU. */
845b51d6
PB		 17743 if (!(is_bx && fix_v4bx)
17744 && !(opcode->avariant &&
17745 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 17746 {
bf3eeda7 17747 as_bad (_("selected processor does not support ARM mode `%s'"), str);
c19d1205 17748 return;
b99bd4ef 17749 }
c19d1205 17750 if (inst.size_req)
b99bd4ef 17751 {
c19d1205
ZW		 17752 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
17753 return;
b99bd4ef
NC		 17754 }
17755
c19d1205
ZW		 17756 inst.instruction = opcode->avalue;
17757 if (opcode->tag == OT_unconditionalF)
17758 inst.instruction |= 0xF << 28;
17759 else
17760 inst.instruction |= inst.cond << 28;
17761 inst.size = INSN_SIZE;
5be8be5d 17762 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM		 17763 {
17764 it_fsm_pre_encode ();
17765 opcode->aencode ();
17766 it_fsm_post_encode ();
17767 }
ee065d83 17768 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 17769 on a hypothetical non-thumb v5 core. */
845b51d6 17770 if (is_bx)
e74cfd16 17771 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 17772 else
e74cfd16
PB		 17773 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
17774 *opcode->avariant);
88714cb8
DG		 17775
17776 check_neon_suffixes;
17777
cd000bff 17778 if (!inst.error)
c877a2f2
NC		 17779 {
17780 mapping_state (MAP_ARM);
17781 }
b99bd4ef 17782 }
3e9e4fcf
JB		 17783 else
17784 {
17785 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17786 "-- `%s'"), str);
17787 return;
17788 }
c19d1205
ZW		 17789 output_inst (str);
17790}
b99bd4ef 17791
e07e6e58
NC		 17792static void
17793check_it_blocks_finished (void)
17794{
17795#ifdef OBJ_ELF
17796 asection *sect;
17797
17798 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
17799 if (seg_info (sect)->tc_segment_info_data.current_it.state
17800 == MANUAL_IT_BLOCK)
17801 {
17802 as_warn (_("section '%s' finished with an open IT block."),
17803 sect->name);
17804 }
17805#else
17806 if (now_it.state == MANUAL_IT_BLOCK)
17807 as_warn (_("file finished with an open IT block."));
17808#endif
17809}
17810
c19d1205
ZW		 17811/* Various frobbings of labels and their addresses. */
17812
17813void
17814arm_start_line_hook (void)
17815{
17816 last_label_seen = NULL;
b99bd4ef
NC		 17817}
17818
c19d1205
ZW		 17819void
17820arm_frob_label (symbolS * sym)
b99bd4ef 17821{
c19d1205 17822 last_label_seen = sym;
b99bd4ef 17823
c19d1205 17824 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 17825
c19d1205
ZW		 17826#if defined OBJ_COFF || defined OBJ_ELF
17827 ARM_SET_INTERWORK (sym, support_interwork);
17828#endif
b99bd4ef 17829
e07e6e58
NC		 17830 force_automatic_it_block_close ();
17831
5f4273c7 17832 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW		 17833 as Thumb functions. This is because these labels, whilst
17834 they exist inside Thumb code, are not the entry points for
17835 possible ARM->Thumb calls. Also, these labels can be used
17836 as part of a computed goto or switch statement. eg gcc
17837 can generate code that looks like this:
b99bd4ef 17838
c19d1205
ZW		 17839 ldr r2, [pc, .Laaa]
17840 lsl r3, r3, #2
17841 ldr r2, [r3, r2]
17842 mov pc, r2
b99bd4ef 17843
c19d1205
ZW		 17844 .Lbbb: .word .Lxxx
17845 .Lccc: .word .Lyyy
17846 ..etc...
17847 .Laaa: .word Lbbb
b99bd4ef 17848
c19d1205
ZW		 17849 The first instruction loads the address of the jump table.
17850 The second instruction converts a table index into a byte offset.
17851 The third instruction gets the jump address out of the table.
17852 The fourth instruction performs the jump.
b99bd4ef 17853
c19d1205
ZW		 17854 If the address stored at .Laaa is that of a symbol which has the
17855 Thumb_Func bit set, then the linker will arrange for this address
17856 to have the bottom bit set, which in turn would mean that the
17857 address computation performed by the third instruction would end
17858 up with the bottom bit set. Since the ARM is capable of unaligned
17859 word loads, the instruction would then load the incorrect address
17860 out of the jump table, and chaos would ensue. */
17861 if (label_is_thumb_function_name
17862 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
17863 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 17864 {
c19d1205
ZW		 17865 /* When the address of a Thumb function is taken the bottom
17866 bit of that address should be set. This will allow
17867 interworking between Arm and Thumb functions to work
17868 correctly. */
b99bd4ef 17869
c19d1205 17870 THUMB_SET_FUNC (sym, 1);
b99bd4ef 17871
c19d1205 17872 label_is_thumb_function_name = FALSE;
b99bd4ef 17873 }
07a53e5c 17874
07a53e5c 17875 dwarf2_emit_label (sym);
b99bd4ef
NC		 17876}
17877
c921be7d 17878bfd_boolean
c19d1205 17879arm_data_in_code (void)
b99bd4ef 17880{
c19d1205 17881 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 17882 {
c19d1205
ZW		 17883 *input_line_pointer = '/';
17884 input_line_pointer += 5;
17885 *input_line_pointer = 0;
c921be7d 17886 return TRUE;
b99bd4ef
NC		 17887 }
17888
c921be7d 17889 return FALSE;
b99bd4ef
NC		 17890}
17891
c19d1205
ZW		 17892char *
17893arm_canonicalize_symbol_name (char * name)
b99bd4ef 17894{
c19d1205 17895 int len;
b99bd4ef 17896
c19d1205
ZW		 17897 if (thumb_mode && (len = strlen (name)) > 5
17898 && streq (name + len - 5, "/data"))
17899 *(name + len - 5) = 0;
b99bd4ef 17900
c19d1205 17901 return name;
b99bd4ef 17902}
c19d1205
ZW		 17903\f
17904/* Table of all register names defined by default. The user can
17905 define additional names with .req. Note that all register names
17906 should appear in both upper and lowercase variants. Some registers
17907 also have mixed-case names. */
b99bd4ef 17908
dcbf9037 17909#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 17910#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 17911#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW		 17912#define REGSET(p,t) \
17913 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17914 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17915 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17916 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB		 17917#define REGSETH(p,t) \
17918 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17919 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17920 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17921 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17922#define REGSET2(p,t) \
17923 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17924 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17925 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17926 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD		 17927#define SPLRBANK(base,bank,t) \
17928 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17929 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17930 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17931 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17932 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17933 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 17934
c19d1205 17935static const struct reg_entry reg_names[] =
7ed4c4c5 17936{
c19d1205
ZW		 17937 /* ARM integer registers. */
17938 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 17939
c19d1205
ZW		 17940 /* ATPCS synonyms. */
17941 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
17942 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
17943 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 17944
c19d1205
ZW		 17945 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
17946 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
17947 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 17948
c19d1205
ZW		 17949 /* Well-known aliases. */
17950 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
17951 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
17952
17953 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
17954 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
17955
17956 /* Coprocessor numbers. */
17957 REGSET(p, CP), REGSET(P, CP),
17958
17959 /* Coprocessor register numbers. The "cr" variants are for backward
17960 compatibility. */
17961 REGSET(c, CN), REGSET(C, CN),
17962 REGSET(cr, CN), REGSET(CR, CN),
17963
90ec0d68
MGD		 17964 /* ARM banked registers. */
17965 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
17966 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
17967 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
17968 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
17969 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
17970 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
17971 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
17972
17973 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
17974 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
17975 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
17976 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
17977 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 17978 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD		 17979 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
17980 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
17981
17982 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
17983 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
17984 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
17985 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
17986 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
17987 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
17988 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 17989 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD		 17990 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
17991
c19d1205
ZW		 17992 /* FPA registers. */
17993 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
17994 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
17995
17996 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
17997 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
17998
17999 /* VFP SP registers. */
5287ad62
JB		 18000 REGSET(s,VFS), REGSET(S,VFS),
18001 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW		 18002
18003 /* VFP DP Registers. */
5287ad62
JB		 18004 REGSET(d,VFD), REGSET(D,VFD),
18005 /* Extra Neon DP registers. */
18006 REGSETH(d,VFD), REGSETH(D,VFD),
18007
18008 /* Neon QP registers. */
18009 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW		 18010
18011 /* VFP control registers. */
18012 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
18013 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB		 18014 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
18015 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
18016 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
18017 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
c19d1205
ZW		 18018
18019 /* Maverick DSP coprocessor registers. */
18020 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
18021 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
18022
18023 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
18024 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
18025 REGDEF(dspsc,0,DSPSC),
18026
18027 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
18028 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
18029 REGDEF(DSPSC,0,DSPSC),
18030
18031 /* iWMMXt data registers - p0, c0-15. */
18032 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
18033
18034 /* iWMMXt control registers - p1, c0-3. */
18035 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
18036 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
18037 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
18038 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
18039
18040 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18041 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
18042 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
18043 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
18044 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
18045
18046 /* XScale accumulator registers. */
18047 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
18048};
18049#undef REGDEF
18050#undef REGNUM
18051#undef REGSET
7ed4c4c5 18052
c19d1205
ZW		 18053/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18054 within psr_required_here. */
18055static const struct asm_psr psrs[] =
18056{
18057 /* Backward compatibility notation. Note that "all" is no longer
18058 truly all possible PSR bits. */
18059 {"all", PSR_c | PSR_f},
18060 {"flg", PSR_f},
18061 {"ctl", PSR_c},
18062
18063 /* Individual flags. */
18064 {"f", PSR_f},
18065 {"c", PSR_c},
18066 {"x", PSR_x},
18067 {"s", PSR_s},
59b42a0d 18068
c19d1205
ZW		 18069 /* Combinations of flags. */
18070 {"fs", PSR_f | PSR_s},
18071 {"fx", PSR_f | PSR_x},
18072 {"fc", PSR_f | PSR_c},
18073 {"sf", PSR_s | PSR_f},
18074 {"sx", PSR_s | PSR_x},
18075 {"sc", PSR_s | PSR_c},
18076 {"xf", PSR_x | PSR_f},
18077 {"xs", PSR_x | PSR_s},
18078 {"xc", PSR_x | PSR_c},
18079 {"cf", PSR_c | PSR_f},
18080 {"cs", PSR_c | PSR_s},
18081 {"cx", PSR_c | PSR_x},
18082 {"fsx", PSR_f | PSR_s | PSR_x},
18083 {"fsc", PSR_f | PSR_s | PSR_c},
18084 {"fxs", PSR_f | PSR_x | PSR_s},
18085 {"fxc", PSR_f | PSR_x | PSR_c},
18086 {"fcs", PSR_f | PSR_c | PSR_s},
18087 {"fcx", PSR_f | PSR_c | PSR_x},
18088 {"sfx", PSR_s | PSR_f | PSR_x},
18089 {"sfc", PSR_s | PSR_f | PSR_c},
18090 {"sxf", PSR_s | PSR_x | PSR_f},
18091 {"sxc", PSR_s | PSR_x | PSR_c},
18092 {"scf", PSR_s | PSR_c | PSR_f},
18093 {"scx", PSR_s | PSR_c | PSR_x},
18094 {"xfs", PSR_x | PSR_f | PSR_s},
18095 {"xfc", PSR_x | PSR_f | PSR_c},
18096 {"xsf", PSR_x | PSR_s | PSR_f},
18097 {"xsc", PSR_x | PSR_s | PSR_c},
18098 {"xcf", PSR_x | PSR_c | PSR_f},
18099 {"xcs", PSR_x | PSR_c | PSR_s},
18100 {"cfs", PSR_c | PSR_f | PSR_s},
18101 {"cfx", PSR_c | PSR_f | PSR_x},
18102 {"csf", PSR_c | PSR_s | PSR_f},
18103 {"csx", PSR_c | PSR_s | PSR_x},
18104 {"cxf", PSR_c | PSR_x | PSR_f},
18105 {"cxs", PSR_c | PSR_x | PSR_s},
18106 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
18107 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
18108 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
18109 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
18110 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
18111 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
18112 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
18113 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
18114 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
18115 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
18116 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
18117 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
18118 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
18119 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
18120 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
18121 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
18122 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
18123 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
18124 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
18125 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
18126 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
18127 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
18128 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
18129 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
18130};
18131
62b3e311
PB		 18132/* Table of V7M psr names. */
18133static const struct asm_psr v7m_psrs[] =
18134{
2b744c99
PB		 18135 {"apsr", 0 }, {"APSR", 0 },
18136 {"iapsr", 1 }, {"IAPSR", 1 },
18137 {"eapsr", 2 }, {"EAPSR", 2 },
18138 {"psr", 3 }, {"PSR", 3 },
18139 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18140 {"ipsr", 5 }, {"IPSR", 5 },
18141 {"epsr", 6 }, {"EPSR", 6 },
18142 {"iepsr", 7 }, {"IEPSR", 7 },
18143 {"msp", 8 }, {"MSP", 8 },
18144 {"psp", 9 }, {"PSP", 9 },
18145 {"primask", 16}, {"PRIMASK", 16},
18146 {"basepri", 17}, {"BASEPRI", 17},
00bbc0bd
NC		 18147 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18148 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
2b744c99
PB		 18149 {"faultmask", 19}, {"FAULTMASK", 19},
18150 {"control", 20}, {"CONTROL", 20}
62b3e311
PB		 18151};
18152
c19d1205
ZW		 18153/* Table of all shift-in-operand names. */
18154static const struct asm_shift_name shift_names [] =
b99bd4ef 18155{
c19d1205
ZW		 18156 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
18157 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
18158 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
18159 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
18160 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
18161 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX }
18162};
b99bd4ef 18163
c19d1205
ZW		 18164/* Table of all explicit relocation names. */
18165#ifdef OBJ_ELF
18166static struct reloc_entry reloc_names[] =
18167{
18168 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
18169 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
18170 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
18171 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
18172 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
18173 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
18174 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
18175 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
18176 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
18177 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 18178 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS		 18179 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
18180 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 18181 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 18182 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 18183 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 18184 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
477330fc 18185 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ}
c19d1205
ZW		 18186};
18187#endif
b99bd4ef 18188
c19d1205
ZW		 18189/* Table of all conditional affixes. 0xF is not defined as a condition code. */
18190static const struct asm_cond conds[] =
18191{
18192 {"eq", 0x0},
18193 {"ne", 0x1},
18194 {"cs", 0x2}, {"hs", 0x2},
18195 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18196 {"mi", 0x4},
18197 {"pl", 0x5},
18198 {"vs", 0x6},
18199 {"vc", 0x7},
18200 {"hi", 0x8},
18201 {"ls", 0x9},
18202 {"ge", 0xa},
18203 {"lt", 0xb},
18204 {"gt", 0xc},
18205 {"le", 0xd},
18206 {"al", 0xe}
18207};
bfae80f2 18208
e797f7e0
MGD		 18209#define UL_BARRIER(L,U,CODE,FEAT) \
18210 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
18211 { U, CODE, ARM_FEATURE (FEAT, 0) }
18212
62b3e311
PB		 18213static struct asm_barrier_opt barrier_opt_names[] =
18214{
e797f7e0
MGD		 18215 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
18216 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
18217 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
18218 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
18219 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
18220 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
18221 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
18222 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
18223 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
18224 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
18225 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
18226 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
18227 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
18228 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
18229 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
18230 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB		 18231};
18232
e797f7e0
MGD		 18233#undef UL_BARRIER
18234
c19d1205
ZW		 18235/* Table of ARM-format instructions. */
18236
18237/* Macros for gluing together operand strings. N.B. In all cases
18238 other than OPS0, the trailing OP_stop comes from default
18239 zero-initialization of the unspecified elements of the array. */
18240#define OPS0() { OP_stop, }
18241#define OPS1(a) { OP_##a, }
18242#define OPS2(a,b) { OP_##a,OP_##b, }
18243#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18244#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18245#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18246#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18247
5be8be5d
DG		 18248/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18249 This is useful when mixing operands for ARM and THUMB, i.e. using the
18250 MIX_ARM_THUMB_OPERANDS macro.
18251 In order to use these macros, prefix the number of operands with _
18252 e.g. _3. */
18253#define OPS_1(a) { a, }
18254#define OPS_2(a,b) { a,b, }
18255#define OPS_3(a,b,c) { a,b,c, }
18256#define OPS_4(a,b,c,d) { a,b,c,d, }
18257#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18258#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18259
c19d1205
ZW		 18260/* These macros abstract out the exact format of the mnemonic table and
18261 save some repeated characters. */
18262
18263/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18264#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 18265 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
1887dd22 18266 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW		 18267
18268/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18269 a T_MNEM_xyz enumerator. */
18270#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 18271 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 18272#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 18273 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW		 18274
18275/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18276 infix after the third character. */
18277#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 18278 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
1887dd22 18279 THUMB_VARIANT, do_##ae, do_##te }
088fa78e 18280#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 18281 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
088fa78e 18282 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 18283#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 18284 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 18285#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 18286 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 18287#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 18288 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 18289#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 18290 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 18291
c19d1205 18292/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB		 18293 field is still 0xE. Many of the Thumb variants can be executed
18294 conditionally, so this is checked separately. */
c19d1205 18295#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 18296 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 18297 THUMB_VARIANT, do_##ae, do_##te }
c19d1205 18298
dd5181d5
KT		 18299/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18300 Used by mnemonics that have very minimal differences in the encoding for
18301 ARM and Thumb variants and can be handled in a common function. */
18302#define TUEc(mnem, op, top, nops, ops, en) \
18303 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18304 THUMB_VARIANT, do_##en, do_##en }
18305
c19d1205
ZW		 18306/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18307 condition code field. */
18308#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 18309 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
1887dd22 18310 THUMB_VARIANT, do_##ae, do_##te }
c19d1205
ZW		 18311
18312/* ARM-only variants of all the above. */
6a86118a 18313#define CE(mnem, op, nops, ops, ae) \
21d799b5 18314 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
6a86118a
NC		 18315
18316#define C3(mnem, op, nops, ops, ae) \
18317 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18318
e3cb604e
PB		 18319/* Legacy mnemonics that always have conditional infix after the third
18320 character. */
18321#define CL(mnem, op, nops, ops, ae) \
21d799b5 18322 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB		 18323 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18324
8f06b2d8
PB		 18325/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18326#define cCE(mnem, op, nops, ops, ae) \
21d799b5 18327 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 18328
e3cb604e
PB		 18329/* Legacy coprocessor instructions where conditional infix and conditional
18330 suffix are ambiguous. For consistency this includes all FPA instructions,
18331 not just the potentially ambiguous ones. */
18332#define cCL(mnem, op, nops, ops, ae) \
21d799b5 18333 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
e3cb604e
PB		 18334 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18335
18336/* Coprocessor, takes either a suffix or a position-3 infix
18337 (for an FPA corner case). */
18338#define C3E(mnem, op, nops, ops, ae) \
21d799b5 18339 { mnem, OPS##nops ops, OT_csuf_or_in3, \
e3cb604e 18340 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
8f06b2d8 18341
6a86118a 18342#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC		 18343 { m1 #m2 m3, OPS##nops ops, \
18344 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
6a86118a
NC		 18345 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18346
18347#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC		 18348 xCM_ (m1, , m2, op, nops, ops, ae), \
18349 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18350 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18351 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18352 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18353 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18354 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18355 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18356 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18357 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18358 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18359 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18360 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18361 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18362 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18363 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18364 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18365 xCM_ (m1, le, m2, op, nops, ops, ae), \
18366 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC		 18367
18368#define UE(mnem, op, nops, ops, ae) \
18369 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18370
18371#define UF(mnem, op, nops, ops, ae) \
18372 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18373
5287ad62
JB		 18374/* Neon data-processing. ARM versions are unconditional with cond=0xf.
18375 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18376 use the same encoding function for each. */
18377#define NUF(mnem, op, nops, ops, enc) \
18378 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18379 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18380
18381/* Neon data processing, version which indirects through neon_enc_tab for
18382 the various overloaded versions of opcodes. */
18383#define nUF(mnem, op, nops, ops, enc) \
21d799b5 18384 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5287ad62
JB		 18385 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18386
18387/* Neon insn with conditional suffix for the ARM version, non-overloaded
18388 version. */
037e8744
JB		 18389#define NCE_tag(mnem, op, nops, ops, enc, tag) \
18390 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5287ad62
JB		 18391 THUMB_VARIANT, do_##enc, do_##enc }
18392
037e8744 18393#define NCE(mnem, op, nops, ops, enc) \
e07e6e58 18394 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB		 18395
18396#define NCEF(mnem, op, nops, ops, enc) \
e07e6e58 18397 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 18398
5287ad62 18399/* Neon insn with conditional suffix for the ARM version, overloaded types. */
037e8744 18400#define nCE_tag(mnem, op, nops, ops, enc, tag) \
21d799b5 18401 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5287ad62
JB		 18402 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18403
037e8744 18404#define nCE(mnem, op, nops, ops, enc) \
e07e6e58 18405 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
037e8744
JB		 18406
18407#define nCEF(mnem, op, nops, ops, enc) \
e07e6e58 18408 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
037e8744 18409
c19d1205
ZW		 18410#define do_0 0
18411
c19d1205 18412static const struct asm_opcode insns[] =
bfae80f2 18413{
74db7efb
NC		 18414#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18415#define THUMB_VARIANT & arm_ext_v4t
21d799b5
NC		 18416 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
18417 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
18418 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
18419 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
18420 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
18421 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
18422 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
18423 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
18424 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
18425 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
18426 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
18427 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
18428 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
18429 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
18430 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
18431 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW		 18432
18433 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18434 for setting PSR flag bits. They are obsolete in V6 and do not
18435 have Thumb equivalents. */
21d799b5
NC		 18436 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18437 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
18438 CL("tstp", 110f000, 2, (RR, SH), cmp),
18439 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18440 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
18441 CL("cmpp", 150f000, 2, (RR, SH), cmp),
18442 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18443 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
18444 CL("cmnp", 170f000, 2, (RR, SH), cmp),
18445
18446 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
18447 tC3("movs", 1b00000, _movs, 2, (RR, SH), mov, t_mov_cmp),
18448 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
18449 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
18450
18451 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG		 18452 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
18453 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
18454 OP_RRnpc),
18455 OP_ADDRGLDR),ldst, t_ldst),
18456 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC		 18457
18458 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18459 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18460 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18461 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18462 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18463 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18464
18465 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
18466 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
18467 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
18468 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 18469
c19d1205 18470 /* Pseudo ops. */
21d799b5 18471 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 18472 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 18473 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
74db7efb 18474 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
c19d1205
ZW		 18475
18476 /* Thumb-compatibility pseudo ops. */
21d799b5
NC		 18477 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
18478 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
18479 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
18480 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
18481 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
18482 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
18483 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
18484 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
18485 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
18486 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
18487 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
18488 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 18489
16a4cf17 18490 /* These may simplify to neg. */
21d799b5
NC		 18491 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
18492 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 18493
c921be7d
NC		 18494#undef THUMB_VARIANT
18495#define THUMB_VARIANT & arm_ext_v6
18496
21d799b5 18497 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW		 18498
18499 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC		 18500#undef THUMB_VARIANT
18501#define THUMB_VARIANT & arm_ext_v6t2
18502
21d799b5
NC		 18503 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18504 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
18505 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 18506
5be8be5d
DG		 18507 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18508 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
18509 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
18510 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 18511
21d799b5
NC		 18512 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18513 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 18514
21d799b5
NC		 18515 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
18516 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW		 18517
18518 /* V1 instructions with no Thumb analogue at all. */
21d799b5 18519 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW		 18520 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
18521
18522 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
18523 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
18524 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
18525 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
18526 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
18527 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
18528 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
18529 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
18530
c921be7d
NC		 18531#undef ARM_VARIANT
18532#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18533#undef THUMB_VARIANT
18534#define THUMB_VARIANT & arm_ext_v4t
18535
21d799b5
NC		 18536 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
18537 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 18538
c921be7d
NC		 18539#undef THUMB_VARIANT
18540#define THUMB_VARIANT & arm_ext_v6t2
18541
21d799b5 18542 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW		 18543 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
18544
18545 /* Generic coprocessor instructions. */
21d799b5
NC		 18546 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18547 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18548 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18549 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18550 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18551 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 18552 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 18553
c921be7d
NC		 18554#undef ARM_VARIANT
18555#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18556
21d799b5 18557 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW		 18558 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
18559
c921be7d
NC		 18560#undef ARM_VARIANT
18561#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18562#undef THUMB_VARIANT
18563#define THUMB_VARIANT & arm_ext_msr
18564
d2cd1205
JB		 18565 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
18566 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 18567
c921be7d
NC		 18568#undef ARM_VARIANT
18569#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18570#undef THUMB_VARIANT
18571#define THUMB_VARIANT & arm_ext_v6t2
18572
21d799b5
NC		 18573 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18574 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18575 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18576 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18577 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18578 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
18579 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
18580 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 18581
c921be7d
NC		 18582#undef ARM_VARIANT
18583#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18584#undef THUMB_VARIANT
18585#define THUMB_VARIANT & arm_ext_v4t
18586
5be8be5d
DG		 18587 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18588 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18589 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18590 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE		 18591 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
18592 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 18593
c921be7d
NC		 18594#undef ARM_VARIANT
18595#define ARM_VARIANT & arm_ext_v4t_5
18596
c19d1205
ZW		 18597 /* ARM Architecture 4T. */
18598 /* Note: bx (and blx) are required on V5, even if the processor does
18599 not support Thumb. */
21d799b5 18600 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 18601
c921be7d
NC		 18602#undef ARM_VARIANT
18603#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18604#undef THUMB_VARIANT
18605#define THUMB_VARIANT & arm_ext_v5t
18606
c19d1205
ZW		 18607 /* Note: blx has 2 variants; the .value coded here is for
18608 BLX(2). Only this variant has conditional execution. */
21d799b5
NC		 18609 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
18610 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 18611
c921be7d
NC		 18612#undef THUMB_VARIANT
18613#define THUMB_VARIANT & arm_ext_v6t2
18614
21d799b5
NC		 18615 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
18616 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18617 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18618 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18619 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
18620 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
18621 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
18622 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 18623
c921be7d 18624#undef ARM_VARIANT
74db7efb
NC		 18625#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18626#undef THUMB_VARIANT
18627#define THUMB_VARIANT & arm_ext_v5exp
c921be7d 18628
21d799b5
NC		 18629 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18630 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18631 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18632 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 18633
21d799b5
NC		 18634 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
18635 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 18636
21d799b5
NC		 18637 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18638 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18639 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
18640 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 18641
21d799b5
NC		 18642 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18643 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18644 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18645 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 18646
21d799b5
NC		 18647 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18648 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 18649
03ee1b7f
NC		 18650 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18651 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18652 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
18653 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 18654
c921be7d 18655#undef ARM_VARIANT
74db7efb
NC		 18656#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18657#undef THUMB_VARIANT
18658#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 18659
21d799b5 18660 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG		 18661 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
18662 ldrd, t_ldstd),
18663 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
18664 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 18665
21d799b5
NC		 18666 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18667 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 18668
c921be7d
NC		 18669#undef ARM_VARIANT
18670#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18671
21d799b5 18672 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 18673
c921be7d
NC		 18674#undef ARM_VARIANT
18675#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18676#undef THUMB_VARIANT
18677#define THUMB_VARIANT & arm_ext_v6
18678
21d799b5
NC		 18679 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
18680 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
18681 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18682 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18683 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
18684 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18685 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18686 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18687 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18688 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 18689
c921be7d
NC		 18690#undef THUMB_VARIANT
18691#define THUMB_VARIANT & arm_ext_v6t2
18692
5be8be5d
DG		 18693 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
18694 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
18695 strex, t_strex),
21d799b5
NC		 18696 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
18697 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 18698
21d799b5
NC		 18699 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
18700 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 18701
9e3c6df6 18702/* ARM V6 not included in V7M. */
c921be7d
NC		 18703#undef THUMB_VARIANT
18704#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 18705 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 18706 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB		 18707 UF(rfeib, 9900a00, 1, (RRw), rfe),
18708 UF(rfeda, 8100a00, 1, (RRw), rfe),
18709 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18710 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE		 18711 UF(rfefa, 8100a00, 1, (RRw), rfe),
18712 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
18713 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 18714 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE		 18715 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
18716 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 18717 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 18718 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 18719 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 18720 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 18721 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 18722 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
c921be7d 18723
9e3c6df6
PB		 18724/* ARM V6 not included in V7M (eg. integer SIMD). */
18725#undef THUMB_VARIANT
18726#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC		 18727 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
18728 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
18729 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
18730 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18731 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18732 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18733 /* Old name for QASX. */
74db7efb 18734 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 18735 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18736 /* Old name for QSAX. */
74db7efb 18737 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18738 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18739 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18740 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18741 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18742 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18743 /* Old name for SASX. */
74db7efb 18744 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18745 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18746 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18747 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18748 /* Old name for SHASX. */
21d799b5 18749 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18750 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18751 /* Old name for SHSAX. */
21d799b5
NC		 18752 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18753 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18754 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18755 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18756 /* Old name for SSAX. */
74db7efb 18757 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18758 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18759 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18760 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18761 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18762 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18763 /* Old name for UASX. */
74db7efb 18764 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18765 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18766 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18767 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18768 /* Old name for UHASX. */
21d799b5
NC		 18769 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18770 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18771 /* Old name for UHSAX. */
21d799b5
NC		 18772 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18773 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18774 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18775 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18776 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 18777 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18778 /* Old name for UQASX. */
21d799b5
NC		 18779 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18780 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18781 /* Old name for UQSAX. */
21d799b5
NC		 18782 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18783 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18784 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18785 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18786 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 18787 /* Old name for USAX. */
74db7efb 18788 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 18789 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 18790 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18791 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18792 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18793 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18794 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18795 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18796 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
18797 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
18798 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
18799 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18800 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18801 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18802 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18803 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18804 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18805 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18806 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
18807 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18808 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18809 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18810 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18811 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18812 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18813 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18814 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18815 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18816 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC		 18817 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
18818 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
18819 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
18820 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
18821 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 18822
c921be7d
NC		 18823#undef ARM_VARIANT
18824#define ARM_VARIANT & arm_ext_v6k
18825#undef THUMB_VARIANT
18826#define THUMB_VARIANT & arm_ext_v6k
18827
21d799b5
NC		 18828 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
18829 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
18830 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
18831 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 18832
c921be7d
NC		 18833#undef THUMB_VARIANT
18834#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG		 18835 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
18836 ldrexd, t_ldrexd),
18837 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
18838 RRnpcb), strexd, t_strexd),
ebdca51a 18839
c921be7d
NC		 18840#undef THUMB_VARIANT
18841#define THUMB_VARIANT & arm_ext_v6t2
5be8be5d
DG		 18842 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
18843 rd_rn, rd_rn),
18844 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
18845 rd_rn, rd_rn),
18846 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 18847 strex, t_strexbh),
5be8be5d 18848 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 18849 strex, t_strexbh),
21d799b5 18850 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 18851
c921be7d 18852#undef ARM_VARIANT
f4c65163 18853#define ARM_VARIANT & arm_ext_sec
74db7efb 18854#undef THUMB_VARIANT
f4c65163 18855#define THUMB_VARIANT & arm_ext_sec
c921be7d 18856
21d799b5 18857 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 18858
90ec0d68
MGD		 18859#undef ARM_VARIANT
18860#define ARM_VARIANT & arm_ext_virt
18861#undef THUMB_VARIANT
18862#define THUMB_VARIANT & arm_ext_virt
18863
18864 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
18865 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
18866
c921be7d 18867#undef ARM_VARIANT
74db7efb 18868#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD		 18869#undef THUMB_VARIANT
18870#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 18871
21d799b5
NC		 18872 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
18873 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
18874 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
18875 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 18876
21d799b5
NC		 18877 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
18878 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
18879 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
18880 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 18881
5be8be5d
DG		 18882 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18883 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18884 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
18885 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 18886
bf3eeda7 18887 /* Thumb-only instructions. */
74db7efb 18888#undef ARM_VARIANT
bf3eeda7
NS		 18889#define ARM_VARIANT NULL
18890 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
18891 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC		 18892
18893 /* ARM does not really have an IT instruction, so always allow it.
18894 The opcode is copied from Thumb in order to allow warnings in
18895 -mimplicit-it=[never | arm] modes. */
18896#undef ARM_VARIANT
18897#define ARM_VARIANT & arm_ext_v1
18898
21d799b5
NC		 18899 TUE("it", bf08, bf08, 1, (COND), it, t_it),
18900 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
18901 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
18902 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
18903 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
18904 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
18905 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
18906 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
18907 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
18908 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
18909 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
18910 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
18911 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
18912 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
18913 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 18914 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC		 18915 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
18916 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 18917
92e90b6e 18918 /* Thumb2 only instructions. */
c921be7d
NC		 18919#undef ARM_VARIANT
18920#define ARM_VARIANT NULL
92e90b6e 18921
21d799b5
NC		 18922 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18923 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
18924 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
18925 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
18926 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
18927 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 18928
eea54501
MGD		 18929 /* Hardware division instructions. */
18930#undef ARM_VARIANT
18931#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC		 18932#undef THUMB_VARIANT
18933#define THUMB_VARIANT & arm_ext_div
18934
eea54501
MGD		 18935 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
18936 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 18937
7e806470 18938 /* ARM V6M/V7 instructions. */
c921be7d
NC		 18939#undef ARM_VARIANT
18940#define ARM_VARIANT & arm_ext_barrier
18941#undef THUMB_VARIANT
18942#define THUMB_VARIANT & arm_ext_barrier
18943
ccb84d65
JB		 18944 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
18945 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
18946 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 18947
62b3e311 18948 /* ARM V7 instructions. */
c921be7d
NC		 18949#undef ARM_VARIANT
18950#define ARM_VARIANT & arm_ext_v7
18951#undef THUMB_VARIANT
18952#define THUMB_VARIANT & arm_ext_v7
18953
21d799b5
NC		 18954 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
18955 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 18956
74db7efb 18957#undef ARM_VARIANT
60e5ef9f 18958#define ARM_VARIANT & arm_ext_mp
74db7efb 18959#undef THUMB_VARIANT
60e5ef9f
MGD		 18960#define THUMB_VARIANT & arm_ext_mp
18961
18962 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
18963
53c4b28b
MGD		 18964 /* AArchv8 instructions. */
18965#undef ARM_VARIANT
18966#define ARM_VARIANT & arm_ext_v8
18967#undef THUMB_VARIANT
18968#define THUMB_VARIANT & arm_ext_v8
18969
18970 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
8884b720 18971 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
4b8c8c02
RE		 18972 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18973 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
9eb6c0f1 18974 ldrexd, t_ldrexd),
4b8c8c02
RE		 18975 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
18976 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18977 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
18978 stlex, t_stlex),
18979 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
9eb6c0f1 18980 strexd, t_strexd),
4b8c8c02
RE		 18981 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
18982 stlex, t_stlex),
18983 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
18984 stlex, t_stlex),
18985 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18986 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18987 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
18988 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18989 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
18990 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
53c4b28b 18991
8884b720 18992 /* ARMv8 T32 only. */
74db7efb 18993#undef ARM_VARIANT
b79f7053
MGD		 18994#define ARM_VARIANT NULL
18995 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
18996 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
18997 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
18998
33399f07
MGD		 18999 /* FP for ARMv8. */
19000#undef ARM_VARIANT
a715796b 19001#define ARM_VARIANT & fpu_vfp_ext_armv8xd
33399f07 19002#undef THUMB_VARIANT
a715796b 19003#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
33399f07
MGD		 19004
19005 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
19006 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
19007 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
19008 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
73924fbc
MGD		 19009 nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
19010 nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
7e8e6784
MGD		 19011 nUF(vcvta, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvta),
19012 nUF(vcvtn, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtn),
19013 nUF(vcvtp, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtp),
19014 nUF(vcvtm, _vcvta, 2, (RNSDQ, oRNSDQ), neon_cvtm),
30bdf752
MGD		 19015 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
19016 nCE(vrintz, _vrintr, 2, (RNSDQ, oRNSDQ), vrintz),
19017 nCE(vrintx, _vrintr, 2, (RNSDQ, oRNSDQ), vrintx),
19018 nUF(vrinta, _vrinta, 2, (RNSDQ, oRNSDQ), vrinta),
19019 nUF(vrintn, _vrinta, 2, (RNSDQ, oRNSDQ), vrintn),
19020 nUF(vrintp, _vrinta, 2, (RNSDQ, oRNSDQ), vrintp),
19021 nUF(vrintm, _vrinta, 2, (RNSDQ, oRNSDQ), vrintm),
33399f07 19022
91ff7894
MGD		 19023 /* Crypto v1 extensions. */
19024#undef ARM_VARIANT
19025#define ARM_VARIANT & fpu_crypto_ext_armv8
19026#undef THUMB_VARIANT
19027#define THUMB_VARIANT & fpu_crypto_ext_armv8
19028
19029 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
19030 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
19031 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
19032 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD		 19033 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
19034 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
19035 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
19036 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
19037 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
19038 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
19039 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD		 19040 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
19041 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
19042 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 19043
dd5181d5 19044#undef ARM_VARIANT
74db7efb 19045#define ARM_VARIANT & crc_ext_armv8
dd5181d5
KT		 19046#undef THUMB_VARIANT
19047#define THUMB_VARIANT & crc_ext_armv8
19048 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
19049 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
19050 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
19051 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
19052 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
19053 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
19054
c921be7d
NC		 19055#undef ARM_VARIANT
19056#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD		 19057#undef THUMB_VARIANT
19058#define THUMB_VARIANT NULL
c921be7d 19059
21d799b5
NC		 19060 cCE("wfs", e200110, 1, (RR), rd),
19061 cCE("rfs", e300110, 1, (RR), rd),
19062 cCE("wfc", e400110, 1, (RR), rd),
19063 cCE("rfc", e500110, 1, (RR), rd),
19064
19065 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
19066 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
19067 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
19068 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
19069
19070 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
19071 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
19072 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
19073 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
19074
19075 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
19076 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
19077 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
19078 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
19079 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
19080 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
19081 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
19082 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
19083 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
19084 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
19085 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
19086 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
19087
19088 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
19089 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
19090 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
19091 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
19092 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
19093 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
19094 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
19095 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
19096 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
19097 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
19098 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
19099 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
19100
19101 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
19102 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
19103 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
19104 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
19105 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
19106 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
19107 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
19108 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
19109 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
19110 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
19111 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
19112 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
19113
19114 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
19115 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
19116 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
19117 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
19118 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
19119 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
19120 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
19121 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
19122 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
19123 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
19124 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
19125 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
19126
19127 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
19128 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
19129 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
19130 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
19131 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
19132 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
19133 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
19134 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
19135 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
19136 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
19137 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
19138 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
19139
19140 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
19141 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
19142 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
19143 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
19144 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
19145 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
19146 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
19147 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
19148 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
19149 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
19150 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
19151 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
19152
19153 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
19154 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
19155 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
19156 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
19157 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
19158 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
19159 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
19160 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
19161 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
19162 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
19163 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
19164 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
19165
19166 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
19167 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
19168 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
19169 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
19170 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
19171 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
19172 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
19173 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
19174 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
19175 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
19176 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
19177 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
19178
19179 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
19180 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
19181 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
19182 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
19183 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
19184 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
19185 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
19186 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
19187 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
19188 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
19189 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
19190 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
19191
19192 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
19193 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
19194 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
19195 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
19196 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
19197 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
19198 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
19199 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
19200 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
19201 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
19202 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
19203 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
19204
19205 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
19206 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
19207 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
19208 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
19209 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
19210 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
19211 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
19212 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
19213 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
19214 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
19215 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
19216 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
19217
19218 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
19219 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
19220 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
19221 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
19222 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
19223 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
19224 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
19225 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
19226 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
19227 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
19228 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
19229 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
19230
19231 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
19232 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
19233 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
19234 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
19235 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
19236 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
19237 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
19238 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
19239 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
19240 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
19241 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
19242 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
19243
19244 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
19245 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
19246 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
19247 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
19248 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
19249 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
19250 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
19251 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
19252 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
19253 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
19254 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
19255 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
19256
19257 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
19258 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
19259 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
19260 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
19261 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
19262 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
19263 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
19264 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
19265 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
19266 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
19267 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
19268 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
19269
19270 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
19271 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
19272 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
19273 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
19274 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
19275 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
19276 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
19277 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
19278 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
19279 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
19280 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
19281 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
19282
19283 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
19284 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
19285 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
19286 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
19287 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
19288 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19289 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19290 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19291 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
19292 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
19293 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
19294 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
19295
19296 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
19297 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
19298 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
19299 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
19300 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
19301 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19302 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19303 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19304 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
19305 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
19306 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
19307 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
19308
19309 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
19310 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
19311 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
19312 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
19313 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
19314 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19315 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19316 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19317 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
19318 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
19319 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
19320 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
19321
19322 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
19323 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
19324 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
19325 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
19326 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
19327 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19328 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19329 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19330 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
19331 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
19332 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
19333 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
19334
19335 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
19336 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
19337 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
19338 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
19339 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
19340 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19341 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19342 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19343 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
19344 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
19345 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
19346 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
19347
19348 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
19349 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
19350 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
19351 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
19352 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
19353 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19354 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19355 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19356 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
19357 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
19358 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
19359 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
19360
19361 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
19362 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
19363 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
19364 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
19365 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
19366 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19367 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19368 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19369 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
19370 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
19371 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
19372 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
19373
19374 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
19375 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
19376 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
19377 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
19378 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
19379 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19380 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19381 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19382 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
19383 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
19384 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
19385 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
19386
19387 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
19388 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
19389 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
19390 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
19391 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
19392 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19393 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19394 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19395 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
19396 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
19397 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
19398 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
19399
19400 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
19401 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
19402 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
19403 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
19404 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
19405 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19406 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19407 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19408 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
19409 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
19410 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
19411 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
19412
19413 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19414 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19415 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19416 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19417 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19418 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19419 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19420 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19421 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19422 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19423 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19424 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19425
19426 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19427 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19428 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19429 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19430 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19431 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19432 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19433 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19434 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19435 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19436 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19437 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19438
19439 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
19440 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
19441 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
19442 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
19443 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
19444 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
19445 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
19446 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
19447 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
19448 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
19449 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
19450 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
19451
19452 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
19453 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
19454 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
19455 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
19456
19457 cCL("flts", e000110, 2, (RF, RR), rn_rd),
19458 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
19459 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
19460 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
19461 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
19462 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
19463 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
19464 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
19465 cCL("flte", e080110, 2, (RF, RR), rn_rd),
19466 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
19467 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
19468 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 19469
c19d1205
ZW		 19470 /* The implementation of the FIX instruction is broken on some
19471 assemblers, in that it accepts a precision specifier as well as a
19472 rounding specifier, despite the fact that this is meaningless.
19473 To be more compatible, we accept it as well, though of course it
19474 does not set any bits. */
21d799b5
NC		 19475 cCE("fix", e100110, 2, (RR, RF), rd_rm),
19476 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
19477 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
19478 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
19479 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
19480 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
19481 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
19482 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
19483 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
19484 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
19485 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
19486 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
19487 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 19488
c19d1205 19489 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC		 19490#undef ARM_VARIANT
19491#define ARM_VARIANT & fpu_fpa_ext_v2
19492
21d799b5
NC		 19493 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19494 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19495 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19496 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19497 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
19498 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 19499
c921be7d
NC		 19500#undef ARM_VARIANT
19501#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19502
c19d1205 19503 /* Moves and type conversions. */
21d799b5
NC		 19504 cCE("fcpys", eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
19505 cCE("fmrs", e100a10, 2, (RR, RVS), vfp_reg_from_sp),
19506 cCE("fmsr", e000a10, 2, (RVS, RR), vfp_sp_from_reg),
19507 cCE("fmstat", ef1fa10, 0, (), noargs),
7465e07a
NC		 19508 cCE("vmrs", ef00a10, 2, (APSR_RR, RVC), vmrs),
19509 cCE("vmsr", ee00a10, 2, (RVC, RR), vmsr),
21d799b5
NC		 19510 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
19511 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
19512 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
19513 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19514 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
19515 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
19516 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
19517 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW		 19518
19519 /* Memory operations. */
21d799b5
NC		 19520 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
19521 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD		 19522 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19523 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19524 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19525 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19526 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19527 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19528 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19529 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19530 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19531 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
19532 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19533 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
19534 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19535 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
19536 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
19537 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 19538
c19d1205 19539 /* Monadic operations. */
21d799b5
NC		 19540 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
19541 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
19542 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW		 19543
19544 /* Dyadic operations. */
21d799b5
NC		 19545 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19546 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19547 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19548 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19549 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19550 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19551 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19552 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19553 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 19554
c19d1205 19555 /* Comparisons. */
21d799b5
NC		 19556 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
19557 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
19558 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
19559 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 19560
62f3b8c8
PB		 19561 /* Double precision load/store are still present on single precision
19562 implementations. */
19563 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
19564 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD		 19565 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19566 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19567 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19568 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19569 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19570 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
19571 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
19572 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 19573
c921be7d
NC		 19574#undef ARM_VARIANT
19575#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19576
c19d1205 19577 /* Moves and type conversions. */
21d799b5
NC		 19578 cCE("fcpyd", eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19579 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19580 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19581 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
19582 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
19583 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
19584 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
19585 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
19586 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
19587 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19588 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
19589 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
19590 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 19591
c19d1205 19592 /* Monadic operations. */
21d799b5
NC		 19593 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19594 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19595 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW		 19596
19597 /* Dyadic operations. */
21d799b5
NC		 19598 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19599 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19600 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19601 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19602 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19603 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19604 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19605 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19606 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 19607
c19d1205 19608 /* Comparisons. */
21d799b5
NC		 19609 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
19610 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
19611 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
19612 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 19613
c921be7d
NC		 19614#undef ARM_VARIANT
19615#define ARM_VARIANT & fpu_vfp_ext_v2
19616
21d799b5
NC		 19617 cCE("fmsrr", c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
19618 cCE("fmrrs", c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
19619 cCE("fmdrr", c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
19620 cCE("fmrrd", c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
5287ad62 19621
037e8744
JB		 19622/* Instructions which may belong to either the Neon or VFP instruction sets.
19623 Individual encoder functions perform additional architecture checks. */
c921be7d
NC		 19624#undef ARM_VARIANT
19625#define ARM_VARIANT & fpu_vfp_ext_v1xd
19626#undef THUMB_VARIANT
19627#define THUMB_VARIANT & fpu_vfp_ext_v1xd
19628
037e8744
JB		 19629 /* These mnemonics are unique to VFP. */
19630 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
19631 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC		 19632 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19633 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19634 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
aacf0b33
KT		 19635 nCE(vcmp, _vcmp, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
19636 nCE(vcmpe, _vcmpe, 2, (RVSD, RSVD_FI0), vfp_nsyn_cmp),
037e8744
JB		 19637 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
19638 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
19639 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
19640
19641 /* Mnemonics shared by Neon and VFP. */
21d799b5
NC		 19642 nCEF(vmul, _vmul, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mul),
19643 nCEF(vmla, _vmla, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
19644 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 19645
21d799b5
NC		 19646 nCEF(vadd, _vadd, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
19647 nCEF(vsub, _vsub, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_addsub_if_i),
037e8744
JB		 19648
19649 NCEF(vabs, 1b10300, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19650 NCEF(vneg, 1b10380, 2, (RNSDQ, RNSDQ), neon_abs_neg),
19651
55881a11
MGD		 19652 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19653 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19654 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19655 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19656 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
19657 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
4962c51a
MS		 19658 NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
19659 NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
037e8744 19660
5f1af56b 19661 nCEF(vcvt, _vcvt, 3, (RNSDQ, RNSDQ, oI32z), neon_cvt),
e3e535bc 19662 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
c70a8987
MGD		 19663 NCEF(vcvtb, eb20a40, 2, (RVSD, RVSD), neon_cvtb),
19664 NCEF(vcvtt, eb20a40, 2, (RVSD, RVSD), neon_cvtt),
f31fef98 19665
037e8744
JB		 19666
19667 /* NOTE: All VMOV encoding is special-cased! */
19668 NCE(vmov, 0, 1, (VMOV), neon_mov),
19669 NCE(vmovq, 0, 1, (VMOV), neon_mov),
19670
c921be7d
NC		 19671#undef THUMB_VARIANT
19672#define THUMB_VARIANT & fpu_neon_ext_v1
19673#undef ARM_VARIANT
19674#define ARM_VARIANT & fpu_neon_ext_v1
19675
5287ad62
JB		 19676 /* Data processing with three registers of the same length. */
19677 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19678 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
19679 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
19680 NUF(vhadd, 0000000, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19681 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19682 NUF(vrhadd, 0000100, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19683 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19684 NUF(vhsub, 0000200, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i_su),
19685 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
19686 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19687 NUF(vqadd, 0000010, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19688 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
19689 NUF(vqsub, 0000210, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_i64_su),
19690 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7
JB		 19691 NUF(vrshl, 0000500, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19692 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
19693 NUF(vqrshl, 0000510, 3, (RNDQ, oRNDQ, RNDQ), neon_rshl),
19694 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62
JB		 19695 /* If not immediate, fall back to neon_dyadic_i64_su.
19696 shl_imm should accept I8 I16 I32 I64,
19697 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
21d799b5
NC		 19698 nUF(vshl, _vshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_shl_imm),
19699 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl_imm),
19700 nUF(vqshl, _vqshl, 3, (RNDQ, oRNDQ, RNDQ_I63b), neon_qshl_imm),
19701 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl_imm),
5287ad62 19702 /* Logic ops, types optional & ignored. */
4316f0d2
DG		 19703 nUF(vand, _vand, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19704 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19705 nUF(vbic, _vbic, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19706 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19707 nUF(vorr, _vorr, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19708 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19709 nUF(vorn, _vorn, 3, (RNDQ, oRNDQ, RNDQ_Ibig), neon_logic),
19710 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
19711 nUF(veor, _veor, 3, (RNDQ, oRNDQ, RNDQ), neon_logic),
19712 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB		 19713 /* Bitfield ops, untyped. */
19714 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19715 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19716 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19717 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19718 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
19719 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
19720 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
21d799b5
NC		 19721 nUF(vabd, _vabd, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19722 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19723 nUF(vmax, _vmax, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19724 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
19725 nUF(vmin, _vmin, 3, (RNDQ, oRNDQ, RNDQ), neon_dyadic_if_su),
19726 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB		 19727 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19728 back to neon_dyadic_if_su. */
21d799b5
NC		 19729 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19730 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19731 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
19732 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
19733 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19734 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
19735 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
19736 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 19737 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC		 19738 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
19739 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 19740 /* As above, D registers only. */
21d799b5
NC		 19741 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
19742 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 19743 /* Int and float variants, signedness unimportant. */
21d799b5
NC		 19744 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19745 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
19746 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 19747 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC		 19748 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
19749 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB		 19750 /* vtst takes sizes 8, 16, 32. */
19751 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
19752 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
19753 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 19754 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 19755 /* VQD{R}MULH takes S16 S32. */
21d799b5
NC		 19756 nUF(vqdmulh, _vqdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19757 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
19758 nUF(vqrdmulh, _vqrdmulh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qdmulh),
19759 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB		 19760 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19761 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
19762 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
19763 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB		 19764 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19765 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
19766 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
19767 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB		 19768 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19769 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19770 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
19771 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
19772
19773 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 19774 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB		 19775 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
19776
19777 /* Data processing with two registers and a shift amount. */
19778 /* Right shifts, and variants with rounding.
19779 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19780 NUF(vshr, 0800010, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19781 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19782 NUF(vrshr, 0800210, 3, (RNDQ, oRNDQ, I64z), neon_rshift_round_imm),
19783 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
19784 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19785 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19786 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
19787 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
19788 /* Shift and insert. Sizes accepted 8 16 32 64. */
19789 NUF(vsli, 1800510, 3, (RNDQ, oRNDQ, I63), neon_sli),
19790 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
19791 NUF(vsri, 1800410, 3, (RNDQ, oRNDQ, I64), neon_sri),
19792 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
19793 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19794 NUF(vqshlu, 1800610, 3, (RNDQ, oRNDQ, I63), neon_qshlu_imm),
19795 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
19796 /* Right shift immediate, saturating & narrowing, with rounding variants.
19797 Types accepted S16 S32 S64 U16 U32 U64. */
19798 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19799 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
19800 /* As above, unsigned. Types accepted S16 S32 S64. */
19801 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19802 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
19803 /* Right shift narrowing. Types accepted I16 I32 I64. */
19804 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19805 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
19806 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 19807 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 19808 /* CVT with optional immediate for fixed-point variant. */
21d799b5 19809 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 19810
4316f0d2
DG		 19811 nUF(vmvn, _vmvn, 2, (RNDQ, RNDQ_Ibig), neon_mvn),
19812 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB		 19813
19814 /* Data processing, three registers of different lengths. */
19815 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19816 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
19817 NUF(vabdl, 0800700, 3, (RNQ, RND, RND), neon_dyadic_long),
19818 NUF(vaddl, 0800000, 3, (RNQ, RND, RND), neon_dyadic_long),
19819 NUF(vsubl, 0800200, 3, (RNQ, RND, RND), neon_dyadic_long),
19820 /* If not scalar, fall back to neon_dyadic_long.
19821 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC		 19822 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
19823 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB		 19824 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19825 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19826 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
19827 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19828 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19829 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19830 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19831 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
19832 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC		 19833 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19834 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
19835 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB		 19836 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19837 S16 S32 U16 U32. */
21d799b5 19838 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB		 19839
19840 /* Extract. Size 8. */
3b8d421e
PB		 19841 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
19842 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB		 19843
19844 /* Two registers, miscellaneous. */
19845 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19846 NUF(vrev64, 1b00000, 2, (RNDQ, RNDQ), neon_rev),
19847 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
19848 NUF(vrev32, 1b00080, 2, (RNDQ, RNDQ), neon_rev),
19849 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
19850 NUF(vrev16, 1b00100, 2, (RNDQ, RNDQ), neon_rev),
19851 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
19852 /* Vector replicate. Sizes 8 16 32. */
21d799b5
NC		 19853 nCE(vdup, _vdup, 2, (RNDQ, RR_RNSC), neon_dup),
19854 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB		 19855 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19856 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
19857 /* VMOVN. Types I16 I32 I64. */
21d799b5 19858 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 19859 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 19860 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 19861 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 19862 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB		 19863 /* VZIP / VUZP. Sizes 8 16 32. */
19864 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
19865 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
19866 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
19867 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
19868 /* VQABS / VQNEG. Types S8 S16 S32. */
19869 NUF(vqabs, 1b00700, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19870 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
19871 NUF(vqneg, 1b00780, 2, (RNDQ, RNDQ), neon_sat_abs_neg),
19872 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
19873 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19874 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
19875 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
19876 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
19877 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
19878 /* Reciprocal estimates. Types U32 F32. */
19879 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
19880 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
19881 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
19882 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
19883 /* VCLS. Types S8 S16 S32. */
19884 NUF(vcls, 1b00400, 2, (RNDQ, RNDQ), neon_cls),
19885 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
19886 /* VCLZ. Types I8 I16 I32. */
19887 NUF(vclz, 1b00480, 2, (RNDQ, RNDQ), neon_clz),
19888 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
19889 /* VCNT. Size 8. */
19890 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
19891 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
19892 /* Two address, untyped. */
19893 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
19894 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
19895 /* VTRN. Sizes 8 16 32. */
21d799b5
NC		 19896 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
19897 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB		 19898
19899 /* Table lookup. Size 8. */
19900 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19901 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
19902
c921be7d
NC		 19903#undef THUMB_VARIANT
19904#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19905#undef ARM_VARIANT
19906#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19907
5287ad62 19908 /* Neon element/structure load/store. */
21d799b5
NC		 19909 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19910 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
19911 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19912 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
19913 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19914 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
19915 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
19916 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 19917
c921be7d 19918#undef THUMB_VARIANT
74db7efb
NC		 19919#define THUMB_VARIANT & fpu_vfp_ext_v3xd
19920#undef ARM_VARIANT
19921#define ARM_VARIANT & fpu_vfp_ext_v3xd
62f3b8c8
PB		 19922 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
19923 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19924 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19925 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19926 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19927 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19928 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19929 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
19930 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
19931
74db7efb 19932#undef THUMB_VARIANT
c921be7d
NC		 19933#define THUMB_VARIANT & fpu_vfp_ext_v3
19934#undef ARM_VARIANT
19935#define ARM_VARIANT & fpu_vfp_ext_v3
19936
21d799b5 19937 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 19938 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19939 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19940 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19941 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19942 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19943 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 19944 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 19945 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 19946
74db7efb
NC		 19947#undef ARM_VARIANT
19948#define ARM_VARIANT & fpu_vfp_ext_fma
19949#undef THUMB_VARIANT
19950#define THUMB_VARIANT & fpu_vfp_ext_fma
62f3b8c8
PB		 19951 /* Mnemonics shared by Neon and VFP. These are included in the
19952 VFP FMA variant; NEON and VFP FMA always includes the NEON
19953 FMA instructions. */
19954 nCEF(vfma, _vfma, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19955 nCEF(vfms, _vfms, 3, (RNSDQ, oRNSDQ, RNSDQ), neon_fmac),
19956 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19957 the v form should always be used. */
19958 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19959 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
19960 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19961 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
19962 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19963 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
19964
5287ad62 19965#undef THUMB_VARIANT
c921be7d
NC		 19966#undef ARM_VARIANT
19967#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19968
21d799b5
NC		 19969 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19970 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19971 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19972 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19973 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19974 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
19975 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
19976 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 19977
c921be7d
NC		 19978#undef ARM_VARIANT
19979#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19980
21d799b5
NC		 19981 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
19982 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
19983 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
19984 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
19985 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
19986 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
19987 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
19988 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
19989 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
74db7efb
NC		 19990 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19991 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19992 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
19993 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19994 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
19995 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21d799b5
NC		 19996 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19997 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19998 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
19999 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
20000 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
20001 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20002 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20003 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20004 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20005 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
20006 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
74db7efb
NC		 20007 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
20008 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
20009 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21d799b5
NC		 20010 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
20011 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
20012 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
20013 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
20014 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
20015 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
20016 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
20017 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
20018 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20019 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20020 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20021 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20022 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20023 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20024 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20025 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20026 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20027 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
74db7efb
NC		 20028 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20029 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20030 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20031 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 20032 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20033 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20034 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20035 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20036 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20037 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20038 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20039 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20040 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 20041 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20042 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20043 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20044 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20045 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20046 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 20047 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20048 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20049 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20050 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20051 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20052 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20053 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20054 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20055 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20056 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20057 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20058 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20059 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20060 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20061 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20062 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20063 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20064 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20065 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20066 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20067 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20068 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20069 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
20070 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20071 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20072 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20073 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20074 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 20075 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20076 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20077 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20078 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20079 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20080 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 20081 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20082 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20083 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20084 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20085 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20086 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20087 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20088 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20089 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20090 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20091 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
20092 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20093 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20094 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20095 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20096 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20097 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20098 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20099 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20100 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20101 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20102 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20103 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20104 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20105 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20106 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20107 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20108 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
20109 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
20110 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20111 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
20112 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
20113 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
20114 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20115 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20116 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20117 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20118 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20119 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20120 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20121 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20122 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20123 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
20124 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
20125 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
20126 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
20127 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
20128 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
20129 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20130 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20131 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20132 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
20133 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
20134 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
20135 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
20136 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
20137 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
20138 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20139 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20140 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20141 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20142 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 20143
c921be7d
NC		 20144#undef ARM_VARIANT
20145#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20146
21d799b5
NC		 20147 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
20148 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
20149 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
20150 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
20151 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
20152 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
20153 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20154 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20155 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20156 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20157 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20158 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20159 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20160 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20161 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20162 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20163 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20164 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20165 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20166 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20167 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
20168 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20169 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20170 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20171 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20172 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20173 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20174 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20175 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20176 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20177 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20178 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20179 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20180 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20181 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20182 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20183 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20184 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20185 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20186 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20187 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20188 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20189 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20190 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20191 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20192 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20193 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20194 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20195 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20196 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20197 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20198 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20199 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20200 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20201 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20202 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
20203 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 20204
c921be7d
NC		 20205#undef ARM_VARIANT
20206#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20207
21d799b5
NC		 20208 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20209 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20210 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20211 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20212 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
20213 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
20214 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
20215 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
20216 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
20217 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
20218 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
20219 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
20220 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
20221 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
74db7efb
NC		 20222 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
20223 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
20224 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
20225 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
20226 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
20227 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
20228 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
20229 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
20230 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
20231 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21d799b5
NC		 20232 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
20233 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
20234 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
20235 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
74db7efb
NC		 20236 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
20237 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21d799b5
NC		 20238 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
20239 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
20240 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
20241 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
74db7efb
NC		 20242 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
20243 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
20244 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
20245 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
20246 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
20247 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21d799b5
NC		 20248 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
20249 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
74db7efb
NC		 20250 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
20251 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21d799b5
NC		 20252 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
20253 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
20254 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
20255 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
20256 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
20257 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
20258 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
20259 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
20260 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
20261 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
20262 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
20263 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
20264 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
20265 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
20266 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
20267 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
20268 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
20269 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
20270 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
20271 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
20272 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20273 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20274 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20275 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20276 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20277 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
20278 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
20279 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
74db7efb
NC		 20280 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
20281 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21d799b5
NC		 20282 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
20283 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
c19d1205
ZW		 20284};
20285#undef ARM_VARIANT
20286#undef THUMB_VARIANT
20287#undef TCE
c19d1205
ZW		 20288#undef TUE
20289#undef TUF
20290#undef TCC
8f06b2d8 20291#undef cCE
e3cb604e
PB		 20292#undef cCL
20293#undef C3E
c19d1205
ZW		 20294#undef CE
20295#undef CM
20296#undef UE
20297#undef UF
20298#undef UT
5287ad62
JB		 20299#undef NUF
20300#undef nUF
20301#undef NCE
20302#undef nCE
c19d1205
ZW		 20303#undef OPS0
20304#undef OPS1
20305#undef OPS2
20306#undef OPS3
20307#undef OPS4
20308#undef OPS5
20309#undef OPS6
20310#undef do_0
20311\f
20312/* MD interface: bits in the object file. */
bfae80f2 20313
c19d1205
ZW		 20314/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20315 for use in the a.out file, and stores them in the array pointed to by buf.
20316 This knows about the endian-ness of the target machine and does
20317 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20318 2 (short) and 4 (long) Floating numbers are put out as a series of
20319 LITTLENUMS (shorts, here at least). */
b99bd4ef 20320
c19d1205
ZW		 20321void
20322md_number_to_chars (char * buf, valueT val, int n)
20323{
20324 if (target_big_endian)
20325 number_to_chars_bigendian (buf, val, n);
20326 else
20327 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE		 20328}
20329
c19d1205
ZW		 20330static valueT
20331md_chars_to_number (char * buf, int n)
bfae80f2 20332{
c19d1205
ZW		 20333 valueT result = 0;
20334 unsigned char * where = (unsigned char *) buf;
bfae80f2 20335
c19d1205 20336 if (target_big_endian)
b99bd4ef 20337 {
c19d1205
ZW		 20338 while (n--)
20339 {
20340 result <<= 8;
20341 result |= (*where++ & 255);
20342 }
b99bd4ef 20343 }
c19d1205 20344 else
b99bd4ef 20345 {
c19d1205
ZW		 20346 while (n--)
20347 {
20348 result <<= 8;
20349 result |= (where[n] & 255);
20350 }
bfae80f2 20351 }
b99bd4ef 20352
c19d1205 20353 return result;
bfae80f2 20354}
b99bd4ef 20355
c19d1205 20356/* MD interface: Sections. */
b99bd4ef 20357
fa94de6b
RM		 20358/* Calculate the maximum variable size (i.e., excluding fr_fix)
20359 that an rs_machine_dependent frag may reach. */
20360
20361unsigned int
20362arm_frag_max_var (fragS *fragp)
20363{
20364 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20365 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20366
20367 Note that we generate relaxable instructions even for cases that don't
20368 really need it, like an immediate that's a trivial constant. So we're
20369 overestimating the instruction size for some of those cases. Rather
20370 than putting more intelligence here, it would probably be better to
20371 avoid generating a relaxation frag in the first place when it can be
20372 determined up front that a short instruction will suffice. */
20373
20374 gas_assert (fragp->fr_type == rs_machine_dependent);
20375 return INSN_SIZE;
20376}
20377
0110f2b8
PB		 20378/* Estimate the size of a frag before relaxing. Assume everything fits in
20379 2 bytes. */
20380
c19d1205 20381int
0110f2b8 20382md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW		 20383 segT segtype ATTRIBUTE_UNUSED)
20384{
0110f2b8
PB		 20385 fragp->fr_var = 2;
20386 return 2;
20387}
20388
20389/* Convert a machine dependent frag. */
20390
20391void
20392md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
20393{
20394 unsigned long insn;
20395 unsigned long old_op;
20396 char *buf;
20397 expressionS exp;
20398 fixS *fixp;
20399 int reloc_type;
20400 int pc_rel;
20401 int opcode;
20402
20403 buf = fragp->fr_literal + fragp->fr_fix;
20404
20405 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC		 20406 if (fragp->fr_symbol)
20407 {
0110f2b8
PB		 20408 exp.X_op = O_symbol;
20409 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC		 20410 }
20411 else
20412 {
0110f2b8 20413 exp.X_op = O_constant;
5f4273c7 20414 }
0110f2b8
PB		 20415 exp.X_add_number = fragp->fr_offset;
20416 opcode = fragp->fr_subtype;
20417 switch (opcode)
20418 {
20419 case T_MNEM_ldr_pc:
20420 case T_MNEM_ldr_pc2:
20421 case T_MNEM_ldr_sp:
20422 case T_MNEM_str_sp:
20423 case T_MNEM_ldr:
20424 case T_MNEM_ldrb:
20425 case T_MNEM_ldrh:
20426 case T_MNEM_str:
20427 case T_MNEM_strb:
20428 case T_MNEM_strh:
20429 if (fragp->fr_var == 4)
20430 {
5f4273c7 20431 insn = THUMB_OP32 (opcode);
0110f2b8
PB		 20432 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
20433 {
20434 insn |= (old_op & 0x700) << 4;
20435 }
20436 else
20437 {
20438 insn |= (old_op & 7) << 12;
20439 insn |= (old_op & 0x38) << 13;
20440 }
20441 insn |= 0x00000c00;
20442 put_thumb32_insn (buf, insn);
20443 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
20444 }
20445 else
20446 {
20447 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
20448 }
20449 pc_rel = (opcode == T_MNEM_ldr_pc2);
20450 break;
20451 case T_MNEM_adr:
20452 if (fragp->fr_var == 4)
20453 {
20454 insn = THUMB_OP32 (opcode);
20455 insn |= (old_op & 0xf0) << 4;
20456 put_thumb32_insn (buf, insn);
20457 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
20458 }
20459 else
20460 {
20461 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20462 exp.X_add_number -= 4;
20463 }
20464 pc_rel = 1;
20465 break;
20466 case T_MNEM_mov:
20467 case T_MNEM_movs:
20468 case T_MNEM_cmp:
20469 case T_MNEM_cmn:
20470 if (fragp->fr_var == 4)
20471 {
20472 int r0off = (opcode == T_MNEM_mov
20473 || opcode == T_MNEM_movs) ? 0 : 8;
20474 insn = THUMB_OP32 (opcode);
20475 insn = (insn & 0xe1ffffff) | 0x10000000;
20476 insn |= (old_op & 0x700) << r0off;
20477 put_thumb32_insn (buf, insn);
20478 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
20479 }
20480 else
20481 {
20482 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
20483 }
20484 pc_rel = 0;
20485 break;
20486 case T_MNEM_b:
20487 if (fragp->fr_var == 4)
20488 {
20489 insn = THUMB_OP32(opcode);
20490 put_thumb32_insn (buf, insn);
20491 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
20492 }
20493 else
20494 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
20495 pc_rel = 1;
20496 break;
20497 case T_MNEM_bcond:
20498 if (fragp->fr_var == 4)
20499 {
20500 insn = THUMB_OP32(opcode);
20501 insn |= (old_op & 0xf00) << 14;
20502 put_thumb32_insn (buf, insn);
20503 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
20504 }
20505 else
20506 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
20507 pc_rel = 1;
20508 break;
20509 case T_MNEM_add_sp:
20510 case T_MNEM_add_pc:
20511 case T_MNEM_inc_sp:
20512 case T_MNEM_dec_sp:
20513 if (fragp->fr_var == 4)
20514 {
20515 /* ??? Choose between add and addw. */
20516 insn = THUMB_OP32 (opcode);
20517 insn |= (old_op & 0xf0) << 4;
20518 put_thumb32_insn (buf, insn);
16805f35
PB		 20519 if (opcode == T_MNEM_add_pc)
20520 reloc_type = BFD_RELOC_ARM_T32_IMM12;
20521 else
20522 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB		 20523 }
20524 else
20525 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20526 pc_rel = 0;
20527 break;
20528
20529 case T_MNEM_addi:
20530 case T_MNEM_addis:
20531 case T_MNEM_subi:
20532 case T_MNEM_subis:
20533 if (fragp->fr_var == 4)
20534 {
20535 insn = THUMB_OP32 (opcode);
20536 insn |= (old_op & 0xf0) << 4;
20537 insn |= (old_op & 0xf) << 16;
20538 put_thumb32_insn (buf, insn);
16805f35
PB		 20539 if (insn & (1 << 20))
20540 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
20541 else
20542 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB		 20543 }
20544 else
20545 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
20546 pc_rel = 0;
20547 break;
20548 default:
5f4273c7 20549 abort ();
0110f2b8
PB		 20550 }
20551 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 20552 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB		 20553 fixp->fx_file = fragp->fr_file;
20554 fixp->fx_line = fragp->fr_line;
20555 fragp->fr_fix += fragp->fr_var;
3cfdb781
TG		 20556
20557 /* Set whether we use thumb-2 ISA based on final relaxation results. */
20558 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
20559 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
20560 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
0110f2b8
PB		 20561}
20562
20563/* Return the size of a relaxable immediate operand instruction.
20564 SHIFT and SIZE specify the form of the allowable immediate. */
20565static int
20566relax_immediate (fragS *fragp, int size, int shift)
20567{
20568 offsetT offset;
20569 offsetT mask;
20570 offsetT low;
20571
20572 /* ??? Should be able to do better than this. */
20573 if (fragp->fr_symbol)
20574 return 4;
20575
20576 low = (1 << shift) - 1;
20577 mask = (1 << (shift + size)) - (1 << shift);
20578 offset = fragp->fr_offset;
20579 /* Force misaligned offsets to 32-bit variant. */
20580 if (offset & low)
5e77afaa 20581 return 4;
0110f2b8
PB		 20582 if (offset & ~mask)
20583 return 4;
20584 return 2;
20585}
20586
5e77afaa
PB		 20587/* Get the address of a symbol during relaxation. */
20588static addressT
5f4273c7 20589relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB		 20590{
20591 fragS *sym_frag;
20592 addressT addr;
20593 symbolS *sym;
20594
20595 sym = fragp->fr_symbol;
20596 sym_frag = symbol_get_frag (sym);
20597 know (S_GET_SEGMENT (sym) != absolute_section
20598 || sym_frag == &zero_address_frag);
20599 addr = S_GET_VALUE (sym) + fragp->fr_offset;
20600
20601 /* If frag has yet to be reached on this pass, assume it will
20602 move by STRETCH just as we did. If this is not so, it will
20603 be because some frag between grows, and that will force
20604 another pass. */
20605
20606 if (stretch != 0
20607 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB		 20608 {
20609 fragS *f;
20610
20611 /* Adjust stretch for any alignment frag. Note that if have
20612 been expanding the earlier code, the symbol may be
20613 defined in what appears to be an earlier frag. FIXME:
20614 This doesn't handle the fr_subtype field, which specifies
20615 a maximum number of bytes to skip when doing an
20616 alignment. */
20617 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
20618 {
20619 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
20620 {
20621 if (stretch < 0)
20622 stretch = - ((- stretch)
20623 & ~ ((1 << (int) f->fr_offset) - 1));
20624 else
20625 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
20626 if (stretch == 0)
20627 break;
20628 }
20629 }
20630 if (f != NULL)
20631 addr += stretch;
20632 }
5e77afaa
PB		 20633
20634 return addr;
20635}
20636
0110f2b8
PB		 20637/* Return the size of a relaxable adr pseudo-instruction or PC-relative
20638 load. */
20639static int
5e77afaa 20640relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB		 20641{
20642 addressT addr;
20643 offsetT val;
20644
20645 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC		 20646 if (fragp->fr_symbol == NULL
20647 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 20648 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20649 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 20650 return 4;
20651
5f4273c7 20652 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 20653 addr = fragp->fr_address + fragp->fr_fix;
20654 addr = (addr + 4) & ~3;
5e77afaa 20655 /* Force misaligned targets to 32-bit variant. */
0110f2b8 20656 if (val & 3)
5e77afaa 20657 return 4;
0110f2b8
PB		 20658 val -= addr;
20659 if (val < 0 || val > 1020)
20660 return 4;
20661 return 2;
20662}
20663
20664/* Return the size of a relaxable add/sub immediate instruction. */
20665static int
20666relax_addsub (fragS *fragp, asection *sec)
20667{
20668 char *buf;
20669 int op;
20670
20671 buf = fragp->fr_literal + fragp->fr_fix;
20672 op = bfd_get_16(sec->owner, buf);
20673 if ((op & 0xf) == ((op >> 4) & 0xf))
20674 return relax_immediate (fragp, 8, 0);
20675 else
20676 return relax_immediate (fragp, 3, 0);
20677}
20678
e83a675f
RE		 20679/* Return TRUE iff the definition of symbol S could be pre-empted
20680 (overridden) at link or load time. */
20681static bfd_boolean
20682symbol_preemptible (symbolS *s)
20683{
20684 /* Weak symbols can always be pre-empted. */
20685 if (S_IS_WEAK (s))
20686 return TRUE;
20687
20688 /* Non-global symbols cannot be pre-empted. */
20689 if (! S_IS_EXTERNAL (s))
20690 return FALSE;
20691
20692#ifdef OBJ_ELF
20693 /* In ELF, a global symbol can be marked protected, or private. In that
20694 case it can't be pre-empted (other definitions in the same link unit
20695 would violate the ODR). */
20696 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
20697 return FALSE;
20698#endif
20699
20700 /* Other global symbols might be pre-empted. */
20701 return TRUE;
20702}
0110f2b8
PB		 20703
20704/* Return the size of a relaxable branch instruction. BITS is the
20705 size of the offset field in the narrow instruction. */
20706
20707static int
5e77afaa 20708relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB		 20709{
20710 addressT addr;
20711 offsetT val;
20712 offsetT limit;
20713
20714 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 20715 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 20716 || sec != S_GET_SEGMENT (fragp->fr_symbol)
20717 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 20718 return 4;
20719
267bf995 20720#ifdef OBJ_ELF
e83a675f 20721 /* A branch to a function in ARM state will require interworking. */
267bf995
RR		 20722 if (S_IS_DEFINED (fragp->fr_symbol)
20723 && ARM_IS_FUNC (fragp->fr_symbol))
20724 return 4;
e83a675f 20725#endif
0d9b4b55 20726
e83a675f 20727 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 20728 return 4;
267bf995 20729
5f4273c7 20730 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 20731 addr = fragp->fr_address + fragp->fr_fix + 4;
20732 val -= addr;
20733
20734 /* Offset is a signed value *2 */
20735 limit = 1 << bits;
20736 if (val >= limit || val < -limit)
20737 return 4;
20738 return 2;
20739}
20740
20741
20742/* Relax a machine dependent frag. This returns the amount by which
20743 the current size of the frag should change. */
20744
20745int
5e77afaa 20746arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB		 20747{
20748 int oldsize;
20749 int newsize;
20750
20751 oldsize = fragp->fr_var;
20752 switch (fragp->fr_subtype)
20753 {
20754 case T_MNEM_ldr_pc2:
5f4273c7 20755 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 20756 break;
20757 case T_MNEM_ldr_pc:
20758 case T_MNEM_ldr_sp:
20759 case T_MNEM_str_sp:
5f4273c7 20760 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB		 20761 break;
20762 case T_MNEM_ldr:
20763 case T_MNEM_str:
5f4273c7 20764 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB		 20765 break;
20766 case T_MNEM_ldrh:
20767 case T_MNEM_strh:
5f4273c7 20768 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB		 20769 break;
20770 case T_MNEM_ldrb:
20771 case T_MNEM_strb:
5f4273c7 20772 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB		 20773 break;
20774 case T_MNEM_adr:
5f4273c7 20775 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 20776 break;
20777 case T_MNEM_mov:
20778 case T_MNEM_movs:
20779 case T_MNEM_cmp:
20780 case T_MNEM_cmn:
5f4273c7 20781 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB		 20782 break;
20783 case T_MNEM_b:
5f4273c7 20784 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB		 20785 break;
20786 case T_MNEM_bcond:
5f4273c7 20787 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB		 20788 break;
20789 case T_MNEM_add_sp:
20790 case T_MNEM_add_pc:
20791 newsize = relax_immediate (fragp, 8, 2);
20792 break;
20793 case T_MNEM_inc_sp:
20794 case T_MNEM_dec_sp:
20795 newsize = relax_immediate (fragp, 7, 2);
20796 break;
20797 case T_MNEM_addi:
20798 case T_MNEM_addis:
20799 case T_MNEM_subi:
20800 case T_MNEM_subis:
20801 newsize = relax_addsub (fragp, sec);
20802 break;
20803 default:
5f4273c7 20804 abort ();
0110f2b8 20805 }
5e77afaa
PB		 20806
20807 fragp->fr_var = newsize;
20808 /* Freeze wide instructions that are at or before the same location as
20809 in the previous pass. This avoids infinite loops.
5f4273c7
NC		 20810 Don't freeze them unconditionally because targets may be artificially
20811 misaligned by the expansion of preceding frags. */
5e77afaa 20812 if (stretch <= 0 && newsize > 2)
0110f2b8 20813 {
0110f2b8 20814 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 20815 frag_wane (fragp);
0110f2b8 20816 }
5e77afaa 20817
0110f2b8 20818 return newsize - oldsize;
c19d1205 20819}
b99bd4ef 20820
c19d1205 20821/* Round up a section size to the appropriate boundary. */
b99bd4ef 20822
c19d1205
ZW		 20823valueT
20824md_section_align (segT segment ATTRIBUTE_UNUSED,
20825 valueT size)
20826{
f0927246
NC		 20827#if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20828 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
20829 {
20830 /* For a.out, force the section size to be aligned. If we don't do
20831 this, BFD will align it for us, but it will not write out the
20832 final bytes of the section. This may be a bug in BFD, but it is
20833 easier to fix it here since that is how the other a.out targets
20834 work. */
20835 int align;
20836
20837 align = bfd_get_section_alignment (stdoutput, segment);
20838 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
20839 }
c19d1205 20840#endif
f0927246
NC		 20841
20842 return size;
bfae80f2 20843}
b99bd4ef 20844
c19d1205
ZW		 20845/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20846 of an rs_align_code fragment. */
20847
20848void
20849arm_handle_align (fragS * fragP)
bfae80f2 20850{
e7495e45
NS		 20851 static char const arm_noop[2][2][4] =
20852 {
20853 { /* ARMv1 */
20854 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20855 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20856 },
20857 { /* ARMv6k */
20858 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20859 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20860 },
20861 };
20862 static char const thumb_noop[2][2][2] =
20863 {
20864 { /* Thumb-1 */
20865 {0xc0, 0x46}, /* LE */
20866 {0x46, 0xc0}, /* BE */
20867 },
20868 { /* Thumb-2 */
20869 {0x00, 0xbf}, /* LE */
20870 {0xbf, 0x00} /* BE */
20871 }
20872 };
20873 static char const wide_thumb_noop[2][4] =
20874 { /* Wide Thumb-2 */
20875 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20876 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20877 };
c921be7d 20878
e7495e45 20879 unsigned bytes, fix, noop_size;
c19d1205
ZW		 20880 char * p;
20881 const char * noop;
e7495e45 20882 const char *narrow_noop = NULL;
cd000bff
DJ		 20883#ifdef OBJ_ELF
20884 enum mstate state;
20885#endif
bfae80f2 20886
c19d1205 20887 if (fragP->fr_type != rs_align_code)
bfae80f2
RE		 20888 return;
20889
c19d1205
ZW		 20890 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
20891 p = fragP->fr_literal + fragP->fr_fix;
20892 fix = 0;
bfae80f2 20893
c19d1205
ZW		 20894 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
20895 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 20896
cd000bff 20897 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 20898
cd000bff 20899 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 20900 {
7f78eb34
JW		 20901 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
20902 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
e7495e45
NS		 20903 {
20904 narrow_noop = thumb_noop[1][target_big_endian];
20905 noop = wide_thumb_noop[target_big_endian];
20906 }
c19d1205 20907 else
e7495e45
NS		 20908 noop = thumb_noop[0][target_big_endian];
20909 noop_size = 2;
cd000bff
DJ		 20910#ifdef OBJ_ELF
20911 state = MAP_THUMB;
20912#endif
7ed4c4c5
NC		 20913 }
20914 else
20915 {
7f78eb34
JW		 20916 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
20917 ? selected_cpu : arm_arch_none,
20918 arm_ext_v6k) != 0]
e7495e45
NS		 20919 [target_big_endian];
20920 noop_size = 4;
cd000bff
DJ		 20921#ifdef OBJ_ELF
20922 state = MAP_ARM;
20923#endif
7ed4c4c5 20924 }
c921be7d 20925
e7495e45 20926 fragP->fr_var = noop_size;
c921be7d 20927
c19d1205 20928 if (bytes & (noop_size - 1))
7ed4c4c5 20929 {
c19d1205 20930 fix = bytes & (noop_size - 1);
cd000bff
DJ		 20931#ifdef OBJ_ELF
20932 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
20933#endif
c19d1205
ZW		 20934 memset (p, 0, fix);
20935 p += fix;
20936 bytes -= fix;
a737bd4d 20937 }
a737bd4d 20938
e7495e45
NS		 20939 if (narrow_noop)
20940 {
20941 if (bytes & noop_size)
20942 {
20943 /* Insert a narrow noop. */
20944 memcpy (p, narrow_noop, noop_size);
20945 p += noop_size;
20946 bytes -= noop_size;
20947 fix += noop_size;
20948 }
20949
20950 /* Use wide noops for the remainder */
20951 noop_size = 4;
20952 }
20953
c19d1205 20954 while (bytes >= noop_size)
a737bd4d 20955 {
c19d1205
ZW		 20956 memcpy (p, noop, noop_size);
20957 p += noop_size;
20958 bytes -= noop_size;
20959 fix += noop_size;
a737bd4d
NC		 20960 }
20961
c19d1205 20962 fragP->fr_fix += fix;
a737bd4d
NC		 20963}
20964
c19d1205
ZW		 20965/* Called from md_do_align. Used to create an alignment
20966 frag in a code section. */
20967
20968void
20969arm_frag_align_code (int n, int max)
bfae80f2 20970{
c19d1205 20971 char * p;
7ed4c4c5 20972
c19d1205 20973 /* We assume that there will never be a requirement
6ec8e702 20974 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 20975 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC		 20976 {
20977 char err_msg[128];
20978
fa94de6b 20979 sprintf (err_msg,
477330fc
RM		 20980 _("alignments greater than %d bytes not supported in .text sections."),
20981 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 20982 as_fatal ("%s", err_msg);
6ec8e702 20983 }
bfae80f2 20984
c19d1205
ZW		 20985 p = frag_var (rs_align_code,
20986 MAX_MEM_FOR_RS_ALIGN_CODE,
20987 1,
20988 (relax_substateT) max,
20989 (symbolS *) NULL,
20990 (offsetT) n,
20991 (char *) NULL);
20992 *p = 0;
20993}
bfae80f2 20994
8dc2430f
NC		 20995/* Perform target specific initialisation of a frag.
20996 Note - despite the name this initialisation is not done when the frag
20997 is created, but only when its type is assigned. A frag can be created
20998 and used a long time before its type is set, so beware of assuming that
20999 this initialisationis performed first. */
bfae80f2 21000
cd000bff
DJ		 21001#ifndef OBJ_ELF
21002void
21003arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
21004{
21005 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 21006 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ		 21007}
21008
21009#else /* OBJ_ELF is defined. */
c19d1205 21010void
cd000bff 21011arm_init_frag (fragS * fragP, int max_chars)
c19d1205 21012{
8dc2430f
NC		 21013 /* If the current ARM vs THUMB mode has not already
21014 been recorded into this frag then do so now. */
cd000bff
DJ		 21015 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
21016 {
21017 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
21018
21019 /* Record a mapping symbol for alignment frags. We will delete this
21020 later if the alignment ends up empty. */
21021 switch (fragP->fr_type)
21022 {
21023 case rs_align:
21024 case rs_align_test:
21025 case rs_fill:
21026 mapping_state_2 (MAP_DATA, max_chars);
21027 break;
21028 case rs_align_code:
21029 mapping_state_2 (thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
21030 break;
21031 default:
21032 break;
21033 }
21034 }
bfae80f2
RE		 21035}
21036
c19d1205
ZW		 21037/* When we change sections we need to issue a new mapping symbol. */
21038
21039void
21040arm_elf_change_section (void)
bfae80f2 21041{
c19d1205
ZW		 21042 /* Link an unlinked unwind index table section to the .text section. */
21043 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
21044 && elf_linked_to_section (now_seg) == NULL)
21045 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE		 21046}
21047
c19d1205
ZW		 21048int
21049arm_elf_section_type (const char * str, size_t len)
e45d0630 21050{
c19d1205
ZW		 21051 if (len == 5 && strncmp (str, "exidx", 5) == 0)
21052 return SHT_ARM_EXIDX;
e45d0630 21053
c19d1205
ZW		 21054 return -1;
21055}
21056\f
21057/* Code to deal with unwinding tables. */
e45d0630 21058
c19d1205 21059static void add_unwind_adjustsp (offsetT);
e45d0630 21060
5f4273c7 21061/* Generate any deferred unwind frame offset. */
e45d0630 21062
bfae80f2 21063static void
c19d1205 21064flush_pending_unwind (void)
bfae80f2 21065{
c19d1205 21066 offsetT offset;
bfae80f2 21067
c19d1205
ZW		 21068 offset = unwind.pending_offset;
21069 unwind.pending_offset = 0;
21070 if (offset != 0)
21071 add_unwind_adjustsp (offset);
bfae80f2
RE		 21072}
21073
c19d1205
ZW		 21074/* Add an opcode to this list for this function. Two-byte opcodes should
21075 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21076 order. */
21077
bfae80f2 21078static void
c19d1205 21079add_unwind_opcode (valueT op, int length)
bfae80f2 21080{
c19d1205
ZW		 21081 /* Add any deferred stack adjustment. */
21082 if (unwind.pending_offset)
21083 flush_pending_unwind ();
bfae80f2 21084
c19d1205 21085 unwind.sp_restored = 0;
bfae80f2 21086
c19d1205 21087 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 21088 {
c19d1205
ZW		 21089 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
21090 if (unwind.opcodes)
21d799b5 21091 unwind.opcodes = (unsigned char *) xrealloc (unwind.opcodes,
477330fc 21092 unwind.opcode_alloc);
c19d1205 21093 else
21d799b5 21094 unwind.opcodes = (unsigned char *) xmalloc (unwind.opcode_alloc);
bfae80f2 21095 }
c19d1205 21096 while (length > 0)
bfae80f2 21097 {
c19d1205
ZW		 21098 length--;
21099 unwind.opcodes[unwind.opcode_count] = op & 0xff;
21100 op >>= 8;
21101 unwind.opcode_count++;
bfae80f2 21102 }
bfae80f2
RE		 21103}
21104
c19d1205
ZW		 21105/* Add unwind opcodes to adjust the stack pointer. */
21106
bfae80f2 21107static void
c19d1205 21108add_unwind_adjustsp (offsetT offset)
bfae80f2 21109{
c19d1205 21110 valueT op;
bfae80f2 21111
c19d1205 21112 if (offset > 0x200)
bfae80f2 21113 {
c19d1205
ZW		 21114 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21115 char bytes[5];
21116 int n;
21117 valueT o;
bfae80f2 21118
c19d1205
ZW		 21119 /* Long form: 0xb2, uleb128. */
21120 /* This might not fit in a word so add the individual bytes,
21121 remembering the list is built in reverse order. */
21122 o = (valueT) ((offset - 0x204) >> 2);
21123 if (o == 0)
21124 add_unwind_opcode (0, 1);
bfae80f2 21125
c19d1205
ZW		 21126 /* Calculate the uleb128 encoding of the offset. */
21127 n = 0;
21128 while (o)
21129 {
21130 bytes[n] = o & 0x7f;
21131 o >>= 7;
21132 if (o)
21133 bytes[n] |= 0x80;
21134 n++;
21135 }
21136 /* Add the insn. */
21137 for (; n; n--)
21138 add_unwind_opcode (bytes[n - 1], 1);
21139 add_unwind_opcode (0xb2, 1);
21140 }
21141 else if (offset > 0x100)
bfae80f2 21142 {
c19d1205
ZW		 21143 /* Two short opcodes. */
21144 add_unwind_opcode (0x3f, 1);
21145 op = (offset - 0x104) >> 2;
21146 add_unwind_opcode (op, 1);
bfae80f2 21147 }
c19d1205
ZW		 21148 else if (offset > 0)
21149 {
21150 /* Short opcode. */
21151 op = (offset - 4) >> 2;
21152 add_unwind_opcode (op, 1);
21153 }
21154 else if (offset < 0)
bfae80f2 21155 {
c19d1205
ZW		 21156 offset = -offset;
21157 while (offset > 0x100)
bfae80f2 21158 {
c19d1205
ZW		 21159 add_unwind_opcode (0x7f, 1);
21160 offset -= 0x100;
bfae80f2 21161 }
c19d1205
ZW		 21162 op = ((offset - 4) >> 2) | 0x40;
21163 add_unwind_opcode (op, 1);
bfae80f2 21164 }
bfae80f2
RE		 21165}
21166
c19d1205
ZW		 21167/* Finish the list of unwind opcodes for this function. */
21168static void
21169finish_unwind_opcodes (void)
bfae80f2 21170{
c19d1205 21171 valueT op;
bfae80f2 21172
c19d1205 21173 if (unwind.fp_used)
bfae80f2 21174 {
708587a4 21175 /* Adjust sp as necessary. */
c19d1205
ZW		 21176 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
21177 flush_pending_unwind ();
bfae80f2 21178
c19d1205
ZW		 21179 /* After restoring sp from the frame pointer. */
21180 op = 0x90 | unwind.fp_reg;
21181 add_unwind_opcode (op, 1);
21182 }
21183 else
21184 flush_pending_unwind ();
bfae80f2
RE		 21185}
21186
bfae80f2 21187
c19d1205
ZW		 21188/* Start an exception table entry. If idx is nonzero this is an index table
21189 entry. */
bfae80f2
RE		 21190
21191static void
c19d1205 21192start_unwind_section (const segT text_seg, int idx)
bfae80f2 21193{
c19d1205
ZW		 21194 const char * text_name;
21195 const char * prefix;
21196 const char * prefix_once;
21197 const char * group_name;
21198 size_t prefix_len;
21199 size_t text_len;
21200 char * sec_name;
21201 size_t sec_name_len;
21202 int type;
21203 int flags;
21204 int linkonce;
bfae80f2 21205
c19d1205 21206 if (idx)
bfae80f2 21207 {
c19d1205
ZW		 21208 prefix = ELF_STRING_ARM_unwind;
21209 prefix_once = ELF_STRING_ARM_unwind_once;
21210 type = SHT_ARM_EXIDX;
bfae80f2 21211 }
c19d1205 21212 else
bfae80f2 21213 {
c19d1205
ZW		 21214 prefix = ELF_STRING_ARM_unwind_info;
21215 prefix_once = ELF_STRING_ARM_unwind_info_once;
21216 type = SHT_PROGBITS;
bfae80f2
RE		 21217 }
21218
c19d1205
ZW		 21219 text_name = segment_name (text_seg);
21220 if (streq (text_name, ".text"))
21221 text_name = "";
21222
21223 if (strncmp (text_name, ".gnu.linkonce.t.",
21224 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 21225 {
c19d1205
ZW		 21226 prefix = prefix_once;
21227 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE		 21228 }
21229
c19d1205
ZW		 21230 prefix_len = strlen (prefix);
21231 text_len = strlen (text_name);
21232 sec_name_len = prefix_len + text_len;
21d799b5 21233 sec_name = (char *) xmalloc (sec_name_len + 1);
c19d1205
ZW		 21234 memcpy (sec_name, prefix, prefix_len);
21235 memcpy (sec_name + prefix_len, text_name, text_len);
21236 sec_name[prefix_len + text_len] = '\0';
bfae80f2 21237
c19d1205
ZW		 21238 flags = SHF_ALLOC;
21239 linkonce = 0;
21240 group_name = 0;
bfae80f2 21241
c19d1205
ZW		 21242 /* Handle COMDAT group. */
21243 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 21244 {
c19d1205
ZW		 21245 group_name = elf_group_name (text_seg);
21246 if (group_name == NULL)
21247 {
bd3ba5d1 21248 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW		 21249 segment_name (text_seg));
21250 ignore_rest_of_line ();
21251 return;
21252 }
21253 flags |= SHF_GROUP;
21254 linkonce = 1;
bfae80f2
RE		 21255 }
21256
c19d1205 21257 obj_elf_change_section (sec_name, type, flags, 0, group_name, linkonce, 0);
bfae80f2 21258
5f4273c7 21259 /* Set the section link for index tables. */
c19d1205
ZW		 21260 if (idx)
21261 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE		 21262}
21263
bfae80f2 21264
c19d1205
ZW		 21265/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21266 personality routine data. Returns zero, or the index table value for
cad0da33 21267 an inline entry. */
c19d1205
ZW		 21268
21269static valueT
21270create_unwind_entry (int have_data)
bfae80f2 21271{
c19d1205
ZW		 21272 int size;
21273 addressT where;
21274 char *ptr;
21275 /* The current word of data. */
21276 valueT data;
21277 /* The number of bytes left in this word. */
21278 int n;
bfae80f2 21279
c19d1205 21280 finish_unwind_opcodes ();
bfae80f2 21281
c19d1205
ZW		 21282 /* Remember the current text section. */
21283 unwind.saved_seg = now_seg;
21284 unwind.saved_subseg = now_subseg;
bfae80f2 21285
c19d1205 21286 start_unwind_section (now_seg, 0);
bfae80f2 21287
c19d1205 21288 if (unwind.personality_routine == NULL)
bfae80f2 21289 {
c19d1205
ZW		 21290 if (unwind.personality_index == -2)
21291 {
21292 if (have_data)
5f4273c7 21293 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW		 21294 return 1; /* EXIDX_CANTUNWIND. */
21295 }
bfae80f2 21296
c19d1205
ZW		 21297 /* Use a default personality routine if none is specified. */
21298 if (unwind.personality_index == -1)
21299 {
21300 if (unwind.opcode_count > 3)
21301 unwind.personality_index = 1;
21302 else
21303 unwind.personality_index = 0;
21304 }
bfae80f2 21305
c19d1205
ZW		 21306 /* Space for the personality routine entry. */
21307 if (unwind.personality_index == 0)
21308 {
21309 if (unwind.opcode_count > 3)
21310 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 21311
c19d1205
ZW		 21312 if (!have_data)
21313 {
21314 /* All the data is inline in the index table. */
21315 data = 0x80;
21316 n = 3;
21317 while (unwind.opcode_count > 0)
21318 {
21319 unwind.opcode_count--;
21320 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21321 n--;
21322 }
bfae80f2 21323
c19d1205
ZW		 21324 /* Pad with "finish" opcodes. */
21325 while (n--)
21326 data = (data << 8) | 0xb0;
bfae80f2 21327
c19d1205
ZW		 21328 return data;
21329 }
21330 size = 0;
21331 }
21332 else
21333 /* We get two opcodes "free" in the first word. */
21334 size = unwind.opcode_count - 2;
21335 }
21336 else
5011093d 21337 {
cad0da33
NC		 21338 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21339 if (unwind.personality_index != -1)
21340 {
21341 as_bad (_("attempt to recreate an unwind entry"));
21342 return 1;
21343 }
5011093d
NC		 21344
21345 /* An extra byte is required for the opcode count. */
21346 size = unwind.opcode_count + 1;
21347 }
bfae80f2 21348
c19d1205
ZW		 21349 size = (size + 3) >> 2;
21350 if (size > 0xff)
21351 as_bad (_("too many unwind opcodes"));
bfae80f2 21352
c19d1205
ZW		 21353 frag_align (2, 0, 0);
21354 record_alignment (now_seg, 2);
21355 unwind.table_entry = expr_build_dot ();
21356
21357 /* Allocate the table entry. */
21358 ptr = frag_more ((size << 2) + 4);
74929e7b
NC		 21359 /* PR 13449: Zero the table entries in case some of them are not used. */
21360 memset (ptr, 0, (size << 2) + 4);
c19d1205 21361 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 21362
c19d1205 21363 switch (unwind.personality_index)
bfae80f2 21364 {
c19d1205
ZW		 21365 case -1:
21366 /* ??? Should this be a PLT generating relocation? */
21367 /* Custom personality routine. */
21368 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
21369 BFD_RELOC_ARM_PREL31);
bfae80f2 21370
c19d1205
ZW		 21371 where += 4;
21372 ptr += 4;
bfae80f2 21373
c19d1205 21374 /* Set the first byte to the number of additional words. */
5011093d 21375 data = size > 0 ? size - 1 : 0;
c19d1205
ZW		 21376 n = 3;
21377 break;
bfae80f2 21378
c19d1205
ZW		 21379 /* ABI defined personality routines. */
21380 case 0:
21381 /* Three opcodes bytes are packed into the first word. */
21382 data = 0x80;
21383 n = 3;
21384 break;
bfae80f2 21385
c19d1205
ZW		 21386 case 1:
21387 case 2:
21388 /* The size and first two opcode bytes go in the first word. */
21389 data = ((0x80 + unwind.personality_index) << 8) | size;
21390 n = 2;
21391 break;
bfae80f2 21392
c19d1205
ZW		 21393 default:
21394 /* Should never happen. */
21395 abort ();
21396 }
bfae80f2 21397
c19d1205
ZW		 21398 /* Pack the opcodes into words (MSB first), reversing the list at the same
21399 time. */
21400 while (unwind.opcode_count > 0)
21401 {
21402 if (n == 0)
21403 {
21404 md_number_to_chars (ptr, data, 4);
21405 ptr += 4;
21406 n = 4;
21407 data = 0;
21408 }
21409 unwind.opcode_count--;
21410 n--;
21411 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
21412 }
21413
21414 /* Finish off the last word. */
21415 if (n < 4)
21416 {
21417 /* Pad with "finish" opcodes. */
21418 while (n--)
21419 data = (data << 8) | 0xb0;
21420
21421 md_number_to_chars (ptr, data, 4);
21422 }
21423
21424 if (!have_data)
21425 {
21426 /* Add an empty descriptor if there is no user-specified data. */
21427 ptr = frag_more (4);
21428 md_number_to_chars (ptr, 0, 4);
21429 }
21430
21431 return 0;
bfae80f2
RE		 21432}
21433
f0927246
NC		 21434
21435/* Initialize the DWARF-2 unwind information for this procedure. */
21436
21437void
21438tc_arm_frame_initial_instructions (void)
21439{
21440 cfi_add_CFA_def_cfa (REG_SP, 0);
21441}
21442#endif /* OBJ_ELF */
21443
c19d1205
ZW		 21444/* Convert REGNAME to a DWARF-2 register number. */
21445
21446int
1df69f4f 21447tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 21448{
1df69f4f 21449 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
1f5afe1c
NC		 21450 if (reg != FAIL)
21451 return reg;
c19d1205 21452
1f5afe1c
NC		 21453 /* PR 16694: Allow VFP registers as well. */
21454 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
21455 if (reg != FAIL)
21456 return 64 + reg;
c19d1205 21457
1f5afe1c
NC		 21458 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
21459 if (reg != FAIL)
21460 return reg + 256;
21461
21462 return -1;
bfae80f2
RE		 21463}
21464
f0927246 21465#ifdef TE_PE
c19d1205 21466void
f0927246 21467tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 21468{
91d6fa6a 21469 expressionS exp;
bfae80f2 21470
91d6fa6a
NC		 21471 exp.X_op = O_secrel;
21472 exp.X_add_symbol = symbol;
21473 exp.X_add_number = 0;
21474 emit_expr (&exp, size);
f0927246
NC		 21475}
21476#endif
bfae80f2 21477
c19d1205 21478/* MD interface: Symbol and relocation handling. */
bfae80f2 21479
2fc8bdac
ZW		 21480/* Return the address within the segment that a PC-relative fixup is
21481 relative to. For ARM, PC-relative fixups applied to instructions
21482 are generally relative to the location of the fixup plus 8 bytes.
21483 Thumb branches are offset by 4, and Thumb loads relative to PC
21484 require special handling. */
bfae80f2 21485
c19d1205 21486long
2fc8bdac 21487md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 21488{
2fc8bdac
ZW		 21489 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
21490
21491 /* If this is pc-relative and we are going to emit a relocation
21492 then we just want to put out any pipeline compensation that the linker
53baae48
NC		 21493 will need. Otherwise we want to use the calculated base.
21494 For WinCE we skip the bias for externals as well, since this
21495 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 21496 if (fixP->fx_pcrel
2fc8bdac 21497 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC		 21498 || (arm_force_relocation (fixP)
21499#ifdef TE_WINCE
21500 && !S_IS_EXTERNAL (fixP->fx_addsy)
21501#endif
21502 )))
2fc8bdac 21503 base = 0;
bfae80f2 21504
267bf995 21505
c19d1205 21506 switch (fixP->fx_r_type)
bfae80f2 21507 {
2fc8bdac
ZW		 21508 /* PC relative addressing on the Thumb is slightly odd as the
21509 bottom two bits of the PC are forced to zero for the
21510 calculation. This happens *after* application of the
21511 pipeline offset. However, Thumb adrl already adjusts for
21512 this, so we need not do it again. */
c19d1205 21513 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 21514 return base & ~3;
c19d1205
ZW		 21515
21516 case BFD_RELOC_ARM_THUMB_OFFSET:
21517 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 21518 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 21519 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 21520 return (base + 4) & ~3;
c19d1205 21521
2fc8bdac
ZW		 21522 /* Thumb branches are simply offset by +4. */
21523 case BFD_RELOC_THUMB_PCREL_BRANCH7:
21524 case BFD_RELOC_THUMB_PCREL_BRANCH9:
21525 case BFD_RELOC_THUMB_PCREL_BRANCH12:
21526 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 21527 case BFD_RELOC_THUMB_PCREL_BRANCH25:
2fc8bdac 21528 return base + 4;
bfae80f2 21529
267bf995 21530 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL		 21531 if (fixP->fx_addsy
21532 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21533 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 21534 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM		 21535 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21536 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR		 21537 return base + 4;
21538
00adf2d4
JB		 21539 /* BLX is like branches above, but forces the low two bits of PC to
21540 zero. */
486499d0
CL		 21541 case BFD_RELOC_THUMB_PCREL_BLX:
21542 if (fixP->fx_addsy
21543 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21544 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21545 && THUMB_IS_FUNC (fixP->fx_addsy)
21546 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21547 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB		 21548 return (base + 4) & ~3;
21549
2fc8bdac
ZW		 21550 /* ARM mode branches are offset by +8. However, the Windows CE
21551 loader expects the relocation not to take this into account. */
267bf995 21552 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL		 21553 if (fixP->fx_addsy
21554 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21555 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21556 && ARM_IS_FUNC (fixP->fx_addsy)
21557 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21558 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 21559 return base + 8;
267bf995 21560
486499d0
CL		 21561 case BFD_RELOC_ARM_PCREL_CALL:
21562 if (fixP->fx_addsy
21563 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 21564 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 21565 && THUMB_IS_FUNC (fixP->fx_addsy)
21566 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
21567 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 21568 return base + 8;
267bf995 21569
2fc8bdac 21570 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 21571 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 21572 case BFD_RELOC_ARM_PLT32:
c19d1205 21573#ifdef TE_WINCE
5f4273c7 21574 /* When handling fixups immediately, because we have already
477330fc 21575 discovered the value of a symbol, or the address of the frag involved
53baae48 21576 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM		 21577 see fixup_segment() in write.c
21578 The S_IS_EXTERNAL test handles the case of global symbols.
21579 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC		 21580 if (fixP->fx_pcrel
21581 && fixP->fx_addsy != NULL
21582 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
21583 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
21584 return base + 8;
2fc8bdac 21585 return base;
c19d1205 21586#else
2fc8bdac 21587 return base + 8;
c19d1205 21588#endif
2fc8bdac 21589
267bf995 21590
2fc8bdac
ZW		 21591 /* ARM mode loads relative to PC are also offset by +8. Unlike
21592 branches, the Windows CE loader *does* expect the relocation
21593 to take this into account. */
21594 case BFD_RELOC_ARM_OFFSET_IMM:
21595 case BFD_RELOC_ARM_OFFSET_IMM8:
21596 case BFD_RELOC_ARM_HWLITERAL:
21597 case BFD_RELOC_ARM_LITERAL:
21598 case BFD_RELOC_ARM_CP_OFF_IMM:
21599 return base + 8;
21600
21601
21602 /* Other PC-relative relocations are un-offset. */
21603 default:
21604 return base;
21605 }
bfae80f2
RE		 21606}
21607
c19d1205
ZW		 21608/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21609 Otherwise we have no need to default values of symbols. */
21610
21611symbolS *
21612md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
bfae80f2 21613{
c19d1205
ZW		 21614#ifdef OBJ_ELF
21615 if (name[0] == '_' && name[1] == 'G'
21616 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
21617 {
21618 if (!GOT_symbol)
21619 {
21620 if (symbol_find (name))
bd3ba5d1 21621 as_bad (_("GOT already in the symbol table"));
bfae80f2 21622
c19d1205
ZW		 21623 GOT_symbol = symbol_new (name, undefined_section,
21624 (valueT) 0, & zero_address_frag);
21625 }
bfae80f2 21626
c19d1205 21627 return GOT_symbol;
bfae80f2 21628 }
c19d1205 21629#endif
bfae80f2 21630
c921be7d 21631 return NULL;
bfae80f2
RE		 21632}
21633
55cf6793 21634/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW		 21635 computed as two separate immediate values, added together. We
21636 already know that this value cannot be computed by just one ARM
21637 instruction. */
21638
21639static unsigned int
21640validate_immediate_twopart (unsigned int val,
21641 unsigned int * highpart)
bfae80f2 21642{
c19d1205
ZW		 21643 unsigned int a;
21644 unsigned int i;
bfae80f2 21645
c19d1205
ZW		 21646 for (i = 0; i < 32; i += 2)
21647 if (((a = rotate_left (val, i)) & 0xff) != 0)
21648 {
21649 if (a & 0xff00)
21650 {
21651 if (a & ~ 0xffff)
21652 continue;
21653 * highpart = (a >> 8) | ((i + 24) << 7);
21654 }
21655 else if (a & 0xff0000)
21656 {
21657 if (a & 0xff000000)
21658 continue;
21659 * highpart = (a >> 16) | ((i + 16) << 7);
21660 }
21661 else
21662 {
9c2799c2 21663 gas_assert (a & 0xff000000);
c19d1205
ZW		 21664 * highpart = (a >> 24) | ((i + 8) << 7);
21665 }
bfae80f2 21666
c19d1205
ZW		 21667 return (a & 0xff) | (i << 7);
21668 }
bfae80f2 21669
c19d1205 21670 return FAIL;
bfae80f2
RE		 21671}
21672
c19d1205
ZW		 21673static int
21674validate_offset_imm (unsigned int val, int hwse)
21675{
21676 if ((hwse && val > 255) || val > 4095)
21677 return FAIL;
21678 return val;
21679}
bfae80f2 21680
55cf6793 21681/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW		 21682 negative immediate constant by altering the instruction. A bit of
21683 a hack really.
21684 MOV <-> MVN
21685 AND <-> BIC
21686 ADC <-> SBC
21687 by inverting the second operand, and
21688 ADD <-> SUB
21689 CMP <-> CMN
21690 by negating the second operand. */
bfae80f2 21691
c19d1205
ZW		 21692static int
21693negate_data_op (unsigned long * instruction,
21694 unsigned long value)
bfae80f2 21695{
c19d1205
ZW		 21696 int op, new_inst;
21697 unsigned long negated, inverted;
bfae80f2 21698
c19d1205
ZW		 21699 negated = encode_arm_immediate (-value);
21700 inverted = encode_arm_immediate (~value);
bfae80f2 21701
c19d1205
ZW		 21702 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
21703 switch (op)
bfae80f2 21704 {
c19d1205
ZW		 21705 /* First negates. */
21706 case OPCODE_SUB: /* ADD <-> SUB */
21707 new_inst = OPCODE_ADD;
21708 value = negated;
21709 break;
bfae80f2 21710
c19d1205
ZW		 21711 case OPCODE_ADD:
21712 new_inst = OPCODE_SUB;
21713 value = negated;
21714 break;
bfae80f2 21715
c19d1205
ZW		 21716 case OPCODE_CMP: /* CMP <-> CMN */
21717 new_inst = OPCODE_CMN;
21718 value = negated;
21719 break;
bfae80f2 21720
c19d1205
ZW		 21721 case OPCODE_CMN:
21722 new_inst = OPCODE_CMP;
21723 value = negated;
21724 break;
bfae80f2 21725
c19d1205
ZW		 21726 /* Now Inverted ops. */
21727 case OPCODE_MOV: /* MOV <-> MVN */
21728 new_inst = OPCODE_MVN;
21729 value = inverted;
21730 break;
bfae80f2 21731
c19d1205
ZW		 21732 case OPCODE_MVN:
21733 new_inst = OPCODE_MOV;
21734 value = inverted;
21735 break;
bfae80f2 21736
c19d1205
ZW		 21737 case OPCODE_AND: /* AND <-> BIC */
21738 new_inst = OPCODE_BIC;
21739 value = inverted;
21740 break;
bfae80f2 21741
c19d1205
ZW		 21742 case OPCODE_BIC:
21743 new_inst = OPCODE_AND;
21744 value = inverted;
21745 break;
bfae80f2 21746
c19d1205
ZW		 21747 case OPCODE_ADC: /* ADC <-> SBC */
21748 new_inst = OPCODE_SBC;
21749 value = inverted;
21750 break;
bfae80f2 21751
c19d1205
ZW		 21752 case OPCODE_SBC:
21753 new_inst = OPCODE_ADC;
21754 value = inverted;
21755 break;
bfae80f2 21756
c19d1205
ZW		 21757 /* We cannot do anything. */
21758 default:
21759 return FAIL;
b99bd4ef
NC		 21760 }
21761
c19d1205
ZW		 21762 if (value == (unsigned) FAIL)
21763 return FAIL;
21764
21765 *instruction &= OPCODE_MASK;
21766 *instruction |= new_inst << DATA_OP_SHIFT;
21767 return value;
b99bd4ef
NC		 21768}
21769
ef8d22e6
PB		 21770/* Like negate_data_op, but for Thumb-2. */
21771
21772static unsigned int
16dd5e42 21773thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB		 21774{
21775 int op, new_inst;
21776 int rd;
16dd5e42 21777 unsigned int negated, inverted;
ef8d22e6
PB		 21778
21779 negated = encode_thumb32_immediate (-value);
21780 inverted = encode_thumb32_immediate (~value);
21781
21782 rd = (*instruction >> 8) & 0xf;
21783 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
21784 switch (op)
21785 {
21786 /* ADD <-> SUB. Includes CMP <-> CMN. */
21787 case T2_OPCODE_SUB:
21788 new_inst = T2_OPCODE_ADD;
21789 value = negated;
21790 break;
21791
21792 case T2_OPCODE_ADD:
21793 new_inst = T2_OPCODE_SUB;
21794 value = negated;
21795 break;
21796
21797 /* ORR <-> ORN. Includes MOV <-> MVN. */
21798 case T2_OPCODE_ORR:
21799 new_inst = T2_OPCODE_ORN;
21800 value = inverted;
21801 break;
21802
21803 case T2_OPCODE_ORN:
21804 new_inst = T2_OPCODE_ORR;
21805 value = inverted;
21806 break;
21807
21808 /* AND <-> BIC. TST has no inverted equivalent. */
21809 case T2_OPCODE_AND:
21810 new_inst = T2_OPCODE_BIC;
21811 if (rd == 15)
21812 value = FAIL;
21813 else
21814 value = inverted;
21815 break;
21816
21817 case T2_OPCODE_BIC:
21818 new_inst = T2_OPCODE_AND;
21819 value = inverted;
21820 break;
21821
21822 /* ADC <-> SBC */
21823 case T2_OPCODE_ADC:
21824 new_inst = T2_OPCODE_SBC;
21825 value = inverted;
21826 break;
21827
21828 case T2_OPCODE_SBC:
21829 new_inst = T2_OPCODE_ADC;
21830 value = inverted;
21831 break;
21832
21833 /* We cannot do anything. */
21834 default:
21835 return FAIL;
21836 }
21837
16dd5e42 21838 if (value == (unsigned int)FAIL)
ef8d22e6
PB		 21839 return FAIL;
21840
21841 *instruction &= T2_OPCODE_MASK;
21842 *instruction |= new_inst << T2_DATA_OP_SHIFT;
21843 return value;
21844}
21845
8f06b2d8
PB		 21846/* Read a 32-bit thumb instruction from buf. */
21847static unsigned long
21848get_thumb32_insn (char * buf)
21849{
21850 unsigned long insn;
21851 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
21852 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21853
21854 return insn;
21855}
21856
a8bc6c78
PB		 21857
21858/* We usually want to set the low bit on the address of thumb function
21859 symbols. In particular .word foo - . should have the low bit set.
21860 Generic code tries to fold the difference of two symbols to
21861 a constant. Prevent this and force a relocation when the first symbols
21862 is a thumb function. */
c921be7d
NC		 21863
21864bfd_boolean
a8bc6c78
PB		 21865arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
21866{
21867 if (op == O_subtract
21868 && l->X_op == O_symbol
21869 && r->X_op == O_symbol
21870 && THUMB_IS_FUNC (l->X_add_symbol))
21871 {
21872 l->X_op = O_subtract;
21873 l->X_op_symbol = r->X_add_symbol;
21874 l->X_add_number -= r->X_add_number;
c921be7d 21875 return TRUE;
a8bc6c78 21876 }
c921be7d 21877
a8bc6c78 21878 /* Process as normal. */
c921be7d 21879 return FALSE;
a8bc6c78
PB		 21880}
21881
4a42ebbc
RR		 21882/* Encode Thumb2 unconditional branches and calls. The encoding
21883 for the 2 are identical for the immediate values. */
21884
21885static void
21886encode_thumb2_b_bl_offset (char * buf, offsetT value)
21887{
21888#define T2I1I2MASK ((1 << 13) | (1 << 11))
21889 offsetT newval;
21890 offsetT newval2;
21891 addressT S, I1, I2, lo, hi;
21892
21893 S = (value >> 24) & 0x01;
21894 I1 = (value >> 23) & 0x01;
21895 I2 = (value >> 22) & 0x01;
21896 hi = (value >> 12) & 0x3ff;
fa94de6b 21897 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR		 21898 newval = md_chars_to_number (buf, THUMB_SIZE);
21899 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
21900 newval |= (S << 10) | hi;
21901 newval2 &= ~T2I1I2MASK;
21902 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
21903 md_number_to_chars (buf, newval, THUMB_SIZE);
21904 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
21905}
21906
c19d1205 21907void
55cf6793 21908md_apply_fix (fixS * fixP,
c19d1205
ZW		 21909 valueT * valP,
21910 segT seg)
21911{
21912 offsetT value = * valP;
21913 offsetT newval;
21914 unsigned int newimm;
21915 unsigned long temp;
21916 int sign;
21917 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 21918
9c2799c2 21919 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 21920
c19d1205 21921 /* Note whether this will delete the relocation. */
4962c51a 21922
c19d1205
ZW		 21923 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
21924 fixP->fx_done = 1;
b99bd4ef 21925
adbaf948 21926 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 21927 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW		 21928 for emit_reloc. */
21929 value &= 0xffffffff;
21930 value ^= 0x80000000;
5f4273c7 21931 value -= 0x80000000;
adbaf948
ZW		 21932
21933 *valP = value;
c19d1205 21934 fixP->fx_addnumber = value;
b99bd4ef 21935
adbaf948
ZW		 21936 /* Same treatment for fixP->fx_offset. */
21937 fixP->fx_offset &= 0xffffffff;
21938 fixP->fx_offset ^= 0x80000000;
21939 fixP->fx_offset -= 0x80000000;
21940
c19d1205 21941 switch (fixP->fx_r_type)
b99bd4ef 21942 {
c19d1205
ZW		 21943 case BFD_RELOC_NONE:
21944 /* This will need to go in the object file. */
21945 fixP->fx_done = 0;
21946 break;
b99bd4ef 21947
c19d1205
ZW		 21948 case BFD_RELOC_ARM_IMMEDIATE:
21949 /* We claim that this fixup has been processed here,
21950 even if in fact we generate an error because we do
21951 not have a reloc for it, so tc_gen_reloc will reject it. */
21952 fixP->fx_done = 1;
b99bd4ef 21953
77db8e2e 21954 if (fixP->fx_addsy)
b99bd4ef 21955 {
77db8e2e 21956 const char *msg = 0;
b99bd4ef 21957
77db8e2e
NC		 21958 if (! S_IS_DEFINED (fixP->fx_addsy))
21959 msg = _("undefined symbol %s used as an immediate value");
21960 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
21961 msg = _("symbol %s is in a different section");
21962 else if (S_IS_WEAK (fixP->fx_addsy))
21963 msg = _("symbol %s is weak and may be overridden later");
21964
21965 if (msg)
21966 {
21967 as_bad_where (fixP->fx_file, fixP->fx_line,
21968 msg, S_GET_NAME (fixP->fx_addsy));
21969 break;
21970 }
42e5fcbf
AS		 21971 }
21972
c19d1205
ZW		 21973 temp = md_chars_to_number (buf, INSN_SIZE);
21974
5e73442d
SL		 21975 /* If the offset is negative, we should use encoding A2 for ADR. */
21976 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
21977 newimm = negate_data_op (&temp, value);
21978 else
21979 {
21980 newimm = encode_arm_immediate (value);
21981
21982 /* If the instruction will fail, see if we can fix things up by
21983 changing the opcode. */
21984 if (newimm == (unsigned int) FAIL)
21985 newimm = negate_data_op (&temp, value);
21986 }
21987
21988 if (newimm == (unsigned int) FAIL)
b99bd4ef 21989 {
c19d1205
ZW		 21990 as_bad_where (fixP->fx_file, fixP->fx_line,
21991 _("invalid constant (%lx) after fixup"),
21992 (unsigned long) value);
21993 break;
b99bd4ef 21994 }
b99bd4ef 21995
c19d1205
ZW		 21996 newimm |= (temp & 0xfffff000);
21997 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
21998 break;
b99bd4ef 21999
c19d1205
ZW		 22000 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
22001 {
22002 unsigned int highpart = 0;
22003 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 22004
77db8e2e 22005 if (fixP->fx_addsy)
42e5fcbf 22006 {
77db8e2e 22007 const char *msg = 0;
42e5fcbf 22008
77db8e2e
NC		 22009 if (! S_IS_DEFINED (fixP->fx_addsy))
22010 msg = _("undefined symbol %s used as an immediate value");
22011 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
22012 msg = _("symbol %s is in a different section");
22013 else if (S_IS_WEAK (fixP->fx_addsy))
22014 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 22015
77db8e2e
NC		 22016 if (msg)
22017 {
22018 as_bad_where (fixP->fx_file, fixP->fx_line,
22019 msg, S_GET_NAME (fixP->fx_addsy));
22020 break;
22021 }
22022 }
fa94de6b 22023
c19d1205
ZW		 22024 newimm = encode_arm_immediate (value);
22025 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 22026
c19d1205
ZW		 22027 /* If the instruction will fail, see if we can fix things up by
22028 changing the opcode. */
22029 if (newimm == (unsigned int) FAIL
22030 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
22031 {
22032 /* No ? OK - try using two ADD instructions to generate
22033 the value. */
22034 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 22035
c19d1205
ZW		 22036 /* Yes - then make sure that the second instruction is
22037 also an add. */
22038 if (newimm != (unsigned int) FAIL)
22039 newinsn = temp;
22040 /* Still No ? Try using a negated value. */
22041 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
22042 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
22043 /* Otherwise - give up. */
22044 else
22045 {
22046 as_bad_where (fixP->fx_file, fixP->fx_line,
22047 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22048 (long) value);
22049 break;
22050 }
b99bd4ef 22051
c19d1205
ZW		 22052 /* Replace the first operand in the 2nd instruction (which
22053 is the PC) with the destination register. We have
22054 already added in the PC in the first instruction and we
22055 do not want to do it again. */
22056 newinsn &= ~ 0xf0000;
22057 newinsn |= ((newinsn & 0x0f000) << 4);
22058 }
b99bd4ef 22059
c19d1205
ZW		 22060 newimm |= (temp & 0xfffff000);
22061 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 22062
c19d1205
ZW		 22063 highpart |= (newinsn & 0xfffff000);
22064 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
22065 }
22066 break;
b99bd4ef 22067
c19d1205 22068 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 22069 if (!fixP->fx_done && seg->use_rela_p)
22070 value = 0;
22071
c19d1205 22072 case BFD_RELOC_ARM_LITERAL:
26d97720 22073 sign = value > 0;
b99bd4ef 22074
c19d1205
ZW		 22075 if (value < 0)
22076 value = - value;
b99bd4ef 22077
c19d1205 22078 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 22079 {
c19d1205
ZW		 22080 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
22081 as_bad_where (fixP->fx_file, fixP->fx_line,
22082 _("invalid literal constant: pool needs to be closer"));
22083 else
22084 as_bad_where (fixP->fx_file, fixP->fx_line,
22085 _("bad immediate value for offset (%ld)"),
22086 (long) value);
22087 break;
f03698e6
RE		 22088 }
22089
c19d1205 22090 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 22091 if (value == 0)
22092 newval &= 0xfffff000;
22093 else
22094 {
22095 newval &= 0xff7ff000;
22096 newval |= value | (sign ? INDEX_UP : 0);
22097 }
c19d1205
ZW		 22098 md_number_to_chars (buf, newval, INSN_SIZE);
22099 break;
b99bd4ef 22100
c19d1205
ZW		 22101 case BFD_RELOC_ARM_OFFSET_IMM8:
22102 case BFD_RELOC_ARM_HWLITERAL:
26d97720 22103 sign = value > 0;
b99bd4ef 22104
c19d1205
ZW		 22105 if (value < 0)
22106 value = - value;
b99bd4ef 22107
c19d1205 22108 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 22109 {
c19d1205
ZW		 22110 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
22111 as_bad_where (fixP->fx_file, fixP->fx_line,
22112 _("invalid literal constant: pool needs to be closer"));
22113 else
427d0db6
RM		 22114 as_bad_where (fixP->fx_file, fixP->fx_line,
22115 _("bad immediate value for 8-bit offset (%ld)"),
22116 (long) value);
c19d1205 22117 break;
b99bd4ef
NC		 22118 }
22119
c19d1205 22120 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 22121 if (value == 0)
22122 newval &= 0xfffff0f0;
22123 else
22124 {
22125 newval &= 0xff7ff0f0;
22126 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
22127 }
c19d1205
ZW		 22128 md_number_to_chars (buf, newval, INSN_SIZE);
22129 break;
b99bd4ef 22130
c19d1205
ZW		 22131 case BFD_RELOC_ARM_T32_OFFSET_U8:
22132 if (value < 0 || value > 1020 || value % 4 != 0)
22133 as_bad_where (fixP->fx_file, fixP->fx_line,
22134 _("bad immediate value for offset (%ld)"), (long) value);
22135 value /= 4;
b99bd4ef 22136
c19d1205 22137 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW		 22138 newval |= value;
22139 md_number_to_chars (buf+2, newval, THUMB_SIZE);
22140 break;
b99bd4ef 22141
c19d1205
ZW		 22142 case BFD_RELOC_ARM_T32_OFFSET_IMM:
22143 /* This is a complicated relocation used for all varieties of Thumb32
22144 load/store instruction with immediate offset:
22145
22146 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 22147 *4, optional writeback(W)
c19d1205
ZW		 22148 (doubleword load/store)
22149
22150 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22151 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22152 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22153 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22154 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22155
22156 Uppercase letters indicate bits that are already encoded at
22157 this point. Lowercase letters are our problem. For the
22158 second block of instructions, the secondary opcode nybble
22159 (bits 8..11) is present, and bit 23 is zero, even if this is
22160 a PC-relative operation. */
22161 newval = md_chars_to_number (buf, THUMB_SIZE);
22162 newval <<= 16;
22163 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 22164
c19d1205 22165 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 22166 {
c19d1205
ZW		 22167 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22168 if (value >= 0)
22169 newval |= (1 << 23);
22170 else
22171 value = -value;
22172 if (value % 4 != 0)
22173 {
22174 as_bad_where (fixP->fx_file, fixP->fx_line,
22175 _("offset not a multiple of 4"));
22176 break;
22177 }
22178 value /= 4;
216d22bc 22179 if (value > 0xff)
c19d1205
ZW		 22180 {
22181 as_bad_where (fixP->fx_file, fixP->fx_line,
22182 _("offset out of range"));
22183 break;
22184 }
22185 newval &= ~0xff;
b99bd4ef 22186 }
c19d1205 22187 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 22188 {
c19d1205
ZW		 22189 /* PC-relative, 12-bit offset. */
22190 if (value >= 0)
22191 newval |= (1 << 23);
22192 else
22193 value = -value;
216d22bc 22194 if (value > 0xfff)
c19d1205
ZW		 22195 {
22196 as_bad_where (fixP->fx_file, fixP->fx_line,
22197 _("offset out of range"));
22198 break;
22199 }
22200 newval &= ~0xfff;
b99bd4ef 22201 }
c19d1205 22202 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 22203 {
c19d1205
ZW		 22204 /* Writeback: 8-bit, +/- offset. */
22205 if (value >= 0)
22206 newval |= (1 << 9);
22207 else
22208 value = -value;
216d22bc 22209 if (value > 0xff)
c19d1205
ZW		 22210 {
22211 as_bad_where (fixP->fx_file, fixP->fx_line,
22212 _("offset out of range"));
22213 break;
22214 }
22215 newval &= ~0xff;
b99bd4ef 22216 }
c19d1205 22217 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 22218 {
c19d1205 22219 /* T-instruction: positive 8-bit offset. */
216d22bc 22220 if (value < 0 || value > 0xff)
b99bd4ef 22221 {
c19d1205
ZW		 22222 as_bad_where (fixP->fx_file, fixP->fx_line,
22223 _("offset out of range"));
22224 break;
b99bd4ef 22225 }
c19d1205
ZW		 22226 newval &= ~0xff;
22227 newval |= value;
b99bd4ef
NC		 22228 }
22229 else
b99bd4ef 22230 {
c19d1205
ZW		 22231 /* Positive 12-bit or negative 8-bit offset. */
22232 int limit;
22233 if (value >= 0)
b99bd4ef 22234 {
c19d1205
ZW		 22235 newval |= (1 << 23);
22236 limit = 0xfff;
22237 }
22238 else
22239 {
22240 value = -value;
22241 limit = 0xff;
22242 }
22243 if (value > limit)
22244 {
22245 as_bad_where (fixP->fx_file, fixP->fx_line,
22246 _("offset out of range"));
22247 break;
b99bd4ef 22248 }
c19d1205 22249 newval &= ~limit;
b99bd4ef 22250 }
b99bd4ef 22251
c19d1205
ZW		 22252 newval |= value;
22253 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
22254 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
22255 break;
404ff6b5 22256
c19d1205
ZW		 22257 case BFD_RELOC_ARM_SHIFT_IMM:
22258 newval = md_chars_to_number (buf, INSN_SIZE);
22259 if (((unsigned long) value) > 32
22260 || (value == 32
22261 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
22262 {
22263 as_bad_where (fixP->fx_file, fixP->fx_line,
22264 _("shift expression is too large"));
22265 break;
22266 }
404ff6b5 22267
c19d1205
ZW		 22268 if (value == 0)
22269 /* Shifts of zero must be done as lsl. */
22270 newval &= ~0x60;
22271 else if (value == 32)
22272 value = 0;
22273 newval &= 0xfffff07f;
22274 newval |= (value & 0x1f) << 7;
22275 md_number_to_chars (buf, newval, INSN_SIZE);
22276 break;
404ff6b5 22277
c19d1205 22278 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 22279 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 22280 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 22281 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW		 22282 /* We claim that this fixup has been processed here,
22283 even if in fact we generate an error because we do
22284 not have a reloc for it, so tc_gen_reloc will reject it. */
22285 fixP->fx_done = 1;
404ff6b5 22286
c19d1205
ZW		 22287 if (fixP->fx_addsy
22288 && ! S_IS_DEFINED (fixP->fx_addsy))
22289 {
22290 as_bad_where (fixP->fx_file, fixP->fx_line,
22291 _("undefined symbol %s used as an immediate value"),
22292 S_GET_NAME (fixP->fx_addsy));
22293 break;
22294 }
404ff6b5 22295
c19d1205
ZW		 22296 newval = md_chars_to_number (buf, THUMB_SIZE);
22297 newval <<= 16;
22298 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 22299
16805f35
PB		 22300 newimm = FAIL;
22301 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
22302 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB		 22303 {
22304 newimm = encode_thumb32_immediate (value);
22305 if (newimm == (unsigned int) FAIL)
22306 newimm = thumb32_negate_data_op (&newval, value);
22307 }
16805f35
PB		 22308 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
22309 && newimm == (unsigned int) FAIL)
92e90b6e 22310 {
16805f35
PB		 22311 /* Turn add/sum into addw/subw. */
22312 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
22313 newval = (newval & 0xfeffffff) | 0x02000000;
40f246e3
NC		 22314 /* No flat 12-bit imm encoding for addsw/subsw. */
22315 if ((newval & 0x00100000) == 0)
e9f89963 22316 {
40f246e3
NC		 22317 /* 12 bit immediate for addw/subw. */
22318 if (value < 0)
22319 {
22320 value = -value;
22321 newval ^= 0x00a00000;
22322 }
22323 if (value > 0xfff)
22324 newimm = (unsigned int) FAIL;
22325 else
22326 newimm = value;
e9f89963 22327 }
92e90b6e 22328 }
cc8a6dd0 22329
c19d1205 22330 if (newimm == (unsigned int)FAIL)
3631a3c8 22331 {
c19d1205
ZW		 22332 as_bad_where (fixP->fx_file, fixP->fx_line,
22333 _("invalid constant (%lx) after fixup"),
22334 (unsigned long) value);
22335 break;
3631a3c8
NC		 22336 }
22337
c19d1205
ZW		 22338 newval |= (newimm & 0x800) << 15;
22339 newval |= (newimm & 0x700) << 4;
22340 newval |= (newimm & 0x0ff);
cc8a6dd0 22341
c19d1205
ZW		 22342 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
22343 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
22344 break;
a737bd4d 22345
3eb17e6b 22346 case BFD_RELOC_ARM_SMC:
c19d1205
ZW		 22347 if (((unsigned long) value) > 0xffff)
22348 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 22349 _("invalid smc expression"));
2fc8bdac 22350 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 22351 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
22352 md_number_to_chars (buf, newval, INSN_SIZE);
22353 break;
a737bd4d 22354
90ec0d68
MGD		 22355 case BFD_RELOC_ARM_HVC:
22356 if (((unsigned long) value) > 0xffff)
22357 as_bad_where (fixP->fx_file, fixP->fx_line,
22358 _("invalid hvc expression"));
22359 newval = md_chars_to_number (buf, INSN_SIZE);
22360 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
22361 md_number_to_chars (buf, newval, INSN_SIZE);
22362 break;
22363
c19d1205 22364 case BFD_RELOC_ARM_SWI:
adbaf948 22365 if (fixP->tc_fix_data != 0)
c19d1205
ZW		 22366 {
22367 if (((unsigned long) value) > 0xff)
22368 as_bad_where (fixP->fx_file, fixP->fx_line,
22369 _("invalid swi expression"));
2fc8bdac 22370 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW		 22371 newval |= value;
22372 md_number_to_chars (buf, newval, THUMB_SIZE);
22373 }
22374 else
22375 {
22376 if (((unsigned long) value) > 0x00ffffff)
22377 as_bad_where (fixP->fx_file, fixP->fx_line,
22378 _("invalid swi expression"));
2fc8bdac 22379 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 22380 newval |= value;
22381 md_number_to_chars (buf, newval, INSN_SIZE);
22382 }
22383 break;
a737bd4d 22384
c19d1205
ZW		 22385 case BFD_RELOC_ARM_MULTI:
22386 if (((unsigned long) value) > 0xffff)
22387 as_bad_where (fixP->fx_file, fixP->fx_line,
22388 _("invalid expression in load/store multiple"));
22389 newval = value | md_chars_to_number (buf, INSN_SIZE);
22390 md_number_to_chars (buf, newval, INSN_SIZE);
22391 break;
a737bd4d 22392
c19d1205 22393#ifdef OBJ_ELF
39b41c9c 22394 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR		 22395
22396 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22397 && fixP->fx_addsy
34e77a92 22398 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22399 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22400 && THUMB_IS_FUNC (fixP->fx_addsy))
22401 /* Flip the bl to blx. This is a simple flip
22402 bit here because we generate PCREL_CALL for
22403 unconditional bls. */
22404 {
22405 newval = md_chars_to_number (buf, INSN_SIZE);
22406 newval = newval | 0x10000000;
22407 md_number_to_chars (buf, newval, INSN_SIZE);
22408 temp = 1;
22409 fixP->fx_done = 1;
22410 }
39b41c9c
PB		 22411 else
22412 temp = 3;
22413 goto arm_branch_common;
22414
22415 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR		 22416 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22417 && fixP->fx_addsy
34e77a92 22418 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22419 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22420 && THUMB_IS_FUNC (fixP->fx_addsy))
22421 {
22422 /* This would map to a bl<cond>, b<cond>,
22423 b<always> to a Thumb function. We
22424 need to force a relocation for this particular
22425 case. */
22426 newval = md_chars_to_number (buf, INSN_SIZE);
22427 fixP->fx_done = 0;
22428 }
22429
2fc8bdac 22430 case BFD_RELOC_ARM_PLT32:
c19d1205 22431#endif
39b41c9c
PB		 22432 case BFD_RELOC_ARM_PCREL_BRANCH:
22433 temp = 3;
22434 goto arm_branch_common;
a737bd4d 22435
39b41c9c 22436 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 22437
39b41c9c 22438 temp = 1;
267bf995
RR		 22439 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
22440 && fixP->fx_addsy
34e77a92 22441 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22442 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22443 && ARM_IS_FUNC (fixP->fx_addsy))
22444 {
22445 /* Flip the blx to a bl and warn. */
22446 const char *name = S_GET_NAME (fixP->fx_addsy);
22447 newval = 0xeb000000;
22448 as_warn_where (fixP->fx_file, fixP->fx_line,
22449 _("blx to '%s' an ARM ISA state function changed to bl"),
22450 name);
22451 md_number_to_chars (buf, newval, INSN_SIZE);
22452 temp = 3;
22453 fixP->fx_done = 1;
22454 }
22455
22456#ifdef OBJ_ELF
22457 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 22458 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR		 22459#endif
22460
39b41c9c 22461 arm_branch_common:
c19d1205 22462 /* We are going to store value (shifted right by two) in the
39b41c9c
PB		 22463 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22464 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22465 also be be clear. */
22466 if (value & temp)
c19d1205 22467 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW		 22468 _("misaligned branch destination"));
22469 if ((value & (offsetT)0xfe000000) != (offsetT)0
22470 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 22471 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22472
2fc8bdac 22473 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 22474 {
2fc8bdac
ZW		 22475 newval = md_chars_to_number (buf, INSN_SIZE);
22476 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB		 22477 /* Set the H bit on BLX instructions. */
22478 if (temp == 1)
22479 {
22480 if (value & 2)
22481 newval |= 0x01000000;
22482 else
22483 newval &= ~0x01000000;
22484 }
2fc8bdac 22485 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 22486 }
c19d1205 22487 break;
a737bd4d 22488
25fe350b
MS		 22489 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
22490 /* CBZ can only branch forward. */
a737bd4d 22491
738755b0 22492 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM		 22493 (which, strictly speaking, are prohibited) will be turned into
22494 no-ops.
738755b0
MS		 22495
22496 FIXME: It may be better to remove the instruction completely and
22497 perform relaxation. */
22498 if (value == -2)
2fc8bdac
ZW		 22499 {
22500 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 22501 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW		 22502 md_number_to_chars (buf, newval, THUMB_SIZE);
22503 }
738755b0
MS		 22504 else
22505 {
22506 if (value & ~0x7e)
08f10d51 22507 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 22508
477330fc 22509 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS		 22510 {
22511 newval = md_chars_to_number (buf, THUMB_SIZE);
22512 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
22513 md_number_to_chars (buf, newval, THUMB_SIZE);
22514 }
22515 }
c19d1205 22516 break;
a737bd4d 22517
c19d1205 22518 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac 22519 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
08f10d51 22520 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22521
2fc8bdac
ZW		 22522 if (fixP->fx_done || !seg->use_rela_p)
22523 {
22524 newval = md_chars_to_number (buf, THUMB_SIZE);
22525 newval |= (value & 0x1ff) >> 1;
22526 md_number_to_chars (buf, newval, THUMB_SIZE);
22527 }
c19d1205 22528 break;
a737bd4d 22529
c19d1205 22530 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac 22531 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
08f10d51 22532 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 22533
2fc8bdac
ZW		 22534 if (fixP->fx_done || !seg->use_rela_p)
22535 {
22536 newval = md_chars_to_number (buf, THUMB_SIZE);
22537 newval |= (value & 0xfff) >> 1;
22538 md_number_to_chars (buf, newval, THUMB_SIZE);
22539 }
c19d1205 22540 break;
a737bd4d 22541
c19d1205 22542 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR		 22543 if (fixP->fx_addsy
22544 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 22545 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22546 && ARM_IS_FUNC (fixP->fx_addsy)
22547 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22548 {
22549 /* Force a relocation for a branch 20 bits wide. */
22550 fixP->fx_done = 0;
22551 }
08f10d51 22552 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
2fc8bdac
ZW		 22553 as_bad_where (fixP->fx_file, fixP->fx_line,
22554 _("conditional branch out of range"));
404ff6b5 22555
2fc8bdac
ZW		 22556 if (fixP->fx_done || !seg->use_rela_p)
22557 {
22558 offsetT newval2;
22559 addressT S, J1, J2, lo, hi;
404ff6b5 22560
2fc8bdac
ZW		 22561 S = (value & 0x00100000) >> 20;
22562 J2 = (value & 0x00080000) >> 19;
22563 J1 = (value & 0x00040000) >> 18;
22564 hi = (value & 0x0003f000) >> 12;
22565 lo = (value & 0x00000ffe) >> 1;
6c43fab6 22566
2fc8bdac
ZW		 22567 newval = md_chars_to_number (buf, THUMB_SIZE);
22568 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22569 newval |= (S << 10) | hi;
22570 newval2 |= (J1 << 13) | (J2 << 11) | lo;
22571 md_number_to_chars (buf, newval, THUMB_SIZE);
22572 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
22573 }
c19d1205 22574 break;
6c43fab6 22575
c19d1205 22576 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR		 22577 /* If there is a blx from a thumb state function to
22578 another thumb function flip this to a bl and warn
22579 about it. */
22580
22581 if (fixP->fx_addsy
34e77a92 22582 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22583 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
22584 && THUMB_IS_FUNC (fixP->fx_addsy))
22585 {
22586 const char *name = S_GET_NAME (fixP->fx_addsy);
22587 as_warn_where (fixP->fx_file, fixP->fx_line,
22588 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22589 name);
22590 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22591 newval = newval | 0x1000;
22592 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22593 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22594 fixP->fx_done = 1;
22595 }
22596
22597
22598 goto thumb_bl_common;
22599
c19d1205 22600 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR		 22601 /* A bl from Thumb state ISA to an internal ARM state function
22602 is converted to a blx. */
22603 if (fixP->fx_addsy
22604 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 22605 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 22606 && ARM_IS_FUNC (fixP->fx_addsy)
22607 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
22608 {
22609 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
22610 newval = newval & ~0x1000;
22611 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
22612 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
22613 fixP->fx_done = 1;
22614 }
22615
22616 thumb_bl_common:
22617
2fc8bdac
ZW		 22618 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22619 /* For a BLX instruction, make sure that the relocation is rounded up
22620 to a word boundary. This follows the semantics of the instruction
22621 which specifies that bit 1 of the target address will come from bit
22622 1 of the base address. */
d406f3e4
JB		 22623 value = (value + 3) & ~ 3;
22624
22625#ifdef OBJ_ELF
22626 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
22627 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
22628 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
22629#endif
404ff6b5 22630
2b2f5df9
NC		 22631 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
22632 {
22633 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_arch_t2)))
22634 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
22635 else if ((value & ~0x1ffffff)
22636 && ((value & ~0x1ffffff) != ~0x1ffffff))
22637 as_bad_where (fixP->fx_file, fixP->fx_line,
22638 _("Thumb2 branch out of range"));
22639 }
4a42ebbc
RR		 22640
22641 if (fixP->fx_done || !seg->use_rela_p)
22642 encode_thumb2_b_bl_offset (buf, value);
22643
c19d1205 22644 break;
404ff6b5 22645
c19d1205 22646 case BFD_RELOC_THUMB_PCREL_BRANCH25:
08f10d51
NC		 22647 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
22648 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 22649
2fc8bdac 22650 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 22651 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 22652
2fc8bdac 22653 break;
a737bd4d 22654
2fc8bdac
ZW		 22655 case BFD_RELOC_8:
22656 if (fixP->fx_done || !seg->use_rela_p)
4b1a927e 22657 *buf = value;
c19d1205 22658 break;
a737bd4d 22659
c19d1205 22660 case BFD_RELOC_16:
2fc8bdac 22661 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 22662 md_number_to_chars (buf, value, 2);
c19d1205 22663 break;
a737bd4d 22664
c19d1205 22665#ifdef OBJ_ELF
0855e32b
NS		 22666 case BFD_RELOC_ARM_TLS_CALL:
22667 case BFD_RELOC_ARM_THM_TLS_CALL:
22668 case BFD_RELOC_ARM_TLS_DESCSEQ:
22669 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
0855e32b 22670 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 22671 case BFD_RELOC_ARM_TLS_GD32:
22672 case BFD_RELOC_ARM_TLS_LE32:
22673 case BFD_RELOC_ARM_TLS_IE32:
22674 case BFD_RELOC_ARM_TLS_LDM32:
22675 case BFD_RELOC_ARM_TLS_LDO32:
22676 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4b1a927e 22677 break;
6c43fab6 22678
c19d1205
ZW		 22679 case BFD_RELOC_ARM_GOT32:
22680 case BFD_RELOC_ARM_GOTOFF:
c19d1205 22681 break;
b43420e6
NC		 22682
22683 case BFD_RELOC_ARM_GOT_PREL:
22684 if (fixP->fx_done || !seg->use_rela_p)
477330fc 22685 md_number_to_chars (buf, value, 4);
b43420e6
NC		 22686 break;
22687
9a6f4e97
NS		 22688 case BFD_RELOC_ARM_TARGET2:
22689 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM		 22690 addend here for REL targets, because it won't be written out
22691 during reloc processing later. */
9a6f4e97
NS		 22692 if (fixP->fx_done || !seg->use_rela_p)
22693 md_number_to_chars (buf, fixP->fx_offset, 4);
22694 break;
c19d1205 22695#endif
6c43fab6 22696
c19d1205
ZW		 22697 case BFD_RELOC_RVA:
22698 case BFD_RELOC_32:
22699 case BFD_RELOC_ARM_TARGET1:
22700 case BFD_RELOC_ARM_ROSEGREL32:
22701 case BFD_RELOC_ARM_SBREL32:
22702 case BFD_RELOC_32_PCREL:
f0927246
NC		 22703#ifdef TE_PE
22704 case BFD_RELOC_32_SECREL:
22705#endif
2fc8bdac 22706 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC		 22707#ifdef TE_WINCE
22708 /* For WinCE we only do this for pcrel fixups. */
22709 if (fixP->fx_done || fixP->fx_pcrel)
22710#endif
22711 md_number_to_chars (buf, value, 4);
c19d1205 22712 break;
6c43fab6 22713
c19d1205
ZW		 22714#ifdef OBJ_ELF
22715 case BFD_RELOC_ARM_PREL31:
2fc8bdac 22716 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW		 22717 {
22718 newval = md_chars_to_number (buf, 4) & 0x80000000;
22719 if ((value ^ (value >> 1)) & 0x40000000)
22720 {
22721 as_bad_where (fixP->fx_file, fixP->fx_line,
22722 _("rel31 relocation overflow"));
22723 }
22724 newval |= value & 0x7fffffff;
22725 md_number_to_chars (buf, newval, 4);
22726 }
22727 break;
c19d1205 22728#endif
a737bd4d 22729
c19d1205 22730 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 22731 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
c19d1205
ZW		 22732 if (value < -1023 || value > 1023 || (value & 3))
22733 as_bad_where (fixP->fx_file, fixP->fx_line,
22734 _("co-processor offset out of range"));
22735 cp_off_common:
26d97720 22736 sign = value > 0;
c19d1205
ZW		 22737 if (value < 0)
22738 value = -value;
8f06b2d8
PB		 22739 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22740 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22741 newval = md_chars_to_number (buf, INSN_SIZE);
22742 else
22743 newval = get_thumb32_insn (buf);
26d97720
NS		 22744 if (value == 0)
22745 newval &= 0xffffff00;
22746 else
22747 {
22748 newval &= 0xff7fff00;
22749 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
22750 }
8f06b2d8
PB		 22751 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
22752 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
22753 md_number_to_chars (buf, newval, INSN_SIZE);
22754 else
22755 put_thumb32_insn (buf, newval);
c19d1205 22756 break;
a737bd4d 22757
c19d1205 22758 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 22759 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW		 22760 if (value < -255 || value > 255)
22761 as_bad_where (fixP->fx_file, fixP->fx_line,
22762 _("co-processor offset out of range"));
df7849c5 22763 value *= 4;
c19d1205 22764 goto cp_off_common;
6c43fab6 22765
c19d1205
ZW		 22766 case BFD_RELOC_ARM_THUMB_OFFSET:
22767 newval = md_chars_to_number (buf, THUMB_SIZE);
22768 /* Exactly what ranges, and where the offset is inserted depends
22769 on the type of instruction, we can establish this from the
22770 top 4 bits. */
22771 switch (newval >> 12)
22772 {
22773 case 4: /* PC load. */
22774 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22775 forced to zero for these loads; md_pcrel_from has already
22776 compensated for this. */
22777 if (value & 3)
22778 as_bad_where (fixP->fx_file, fixP->fx_line,
22779 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC		 22780 (((unsigned long) fixP->fx_frag->fr_address
22781 + (unsigned long) fixP->fx_where) & ~3)
22782 + (unsigned long) value);
a737bd4d 22783
c19d1205
ZW		 22784 if (value & ~0x3fc)
22785 as_bad_where (fixP->fx_file, fixP->fx_line,
22786 _("invalid offset, value too big (0x%08lX)"),
22787 (long) value);
a737bd4d 22788
c19d1205
ZW		 22789 newval |= value >> 2;
22790 break;
a737bd4d 22791
c19d1205
ZW		 22792 case 9: /* SP load/store. */
22793 if (value & ~0x3fc)
22794 as_bad_where (fixP->fx_file, fixP->fx_line,
22795 _("invalid offset, value too big (0x%08lX)"),
22796 (long) value);
22797 newval |= value >> 2;
22798 break;
6c43fab6 22799
c19d1205
ZW		 22800 case 6: /* Word load/store. */
22801 if (value & ~0x7c)
22802 as_bad_where (fixP->fx_file, fixP->fx_line,
22803 _("invalid offset, value too big (0x%08lX)"),
22804 (long) value);
22805 newval |= value << 4; /* 6 - 2. */
22806 break;
a737bd4d 22807
c19d1205
ZW		 22808 case 7: /* Byte load/store. */
22809 if (value & ~0x1f)
22810 as_bad_where (fixP->fx_file, fixP->fx_line,
22811 _("invalid offset, value too big (0x%08lX)"),
22812 (long) value);
22813 newval |= value << 6;
22814 break;
a737bd4d 22815
c19d1205
ZW		 22816 case 8: /* Halfword load/store. */
22817 if (value & ~0x3e)
22818 as_bad_where (fixP->fx_file, fixP->fx_line,
22819 _("invalid offset, value too big (0x%08lX)"),
22820 (long) value);
22821 newval |= value << 5; /* 6 - 1. */
22822 break;
a737bd4d 22823
c19d1205
ZW		 22824 default:
22825 as_bad_where (fixP->fx_file, fixP->fx_line,
22826 "Unable to process relocation for thumb opcode: %lx",
22827 (unsigned long) newval);
22828 break;
22829 }
22830 md_number_to_chars (buf, newval, THUMB_SIZE);
22831 break;
a737bd4d 22832
c19d1205
ZW		 22833 case BFD_RELOC_ARM_THUMB_ADD:
22834 /* This is a complicated relocation, since we use it for all of
22835 the following immediate relocations:
a737bd4d 22836
c19d1205
ZW		 22837 3bit ADD/SUB
22838 8bit ADD/SUB
22839 9bit ADD/SUB SP word-aligned
22840 10bit ADD PC/SP word-aligned
a737bd4d 22841
c19d1205
ZW		 22842 The type of instruction being processed is encoded in the
22843 instruction field:
a737bd4d 22844
c19d1205
ZW		 22845 0x8000 SUB
22846 0x00F0 Rd
22847 0x000F Rs
22848 */
22849 newval = md_chars_to_number (buf, THUMB_SIZE);
22850 {
22851 int rd = (newval >> 4) & 0xf;
22852 int rs = newval & 0xf;
22853 int subtract = !!(newval & 0x8000);
a737bd4d 22854
c19d1205
ZW		 22855 /* Check for HI regs, only very restricted cases allowed:
22856 Adjusting SP, and using PC or SP to get an address. */
22857 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
22858 || (rs > 7 && rs != REG_SP && rs != REG_PC))
22859 as_bad_where (fixP->fx_file, fixP->fx_line,
22860 _("invalid Hi register with immediate"));
a737bd4d 22861
c19d1205
ZW		 22862 /* If value is negative, choose the opposite instruction. */
22863 if (value < 0)
22864 {
22865 value = -value;
22866 subtract = !subtract;
22867 if (value < 0)
22868 as_bad_where (fixP->fx_file, fixP->fx_line,
22869 _("immediate value out of range"));
22870 }
a737bd4d 22871
c19d1205
ZW		 22872 if (rd == REG_SP)
22873 {
22874 if (value & ~0x1fc)
22875 as_bad_where (fixP->fx_file, fixP->fx_line,
22876 _("invalid immediate for stack address calculation"));
22877 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
22878 newval |= value >> 2;
22879 }
22880 else if (rs == REG_PC || rs == REG_SP)
22881 {
22882 if (subtract || value & ~0x3fc)
22883 as_bad_where (fixP->fx_file, fixP->fx_line,
22884 _("invalid immediate for address calculation (value = 0x%08lX)"),
22885 (unsigned long) value);
22886 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
22887 newval |= rd << 8;
22888 newval |= value >> 2;
22889 }
22890 else if (rs == rd)
22891 {
22892 if (value & ~0xff)
22893 as_bad_where (fixP->fx_file, fixP->fx_line,
22894 _("immediate value out of range"));
22895 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
22896 newval |= (rd << 8) | value;
22897 }
22898 else
22899 {
22900 if (value & ~0x7)
22901 as_bad_where (fixP->fx_file, fixP->fx_line,
22902 _("immediate value out of range"));
22903 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
22904 newval |= rd | (rs << 3) | (value << 6);
22905 }
22906 }
22907 md_number_to_chars (buf, newval, THUMB_SIZE);
22908 break;
a737bd4d 22909
c19d1205
ZW		 22910 case BFD_RELOC_ARM_THUMB_IMM:
22911 newval = md_chars_to_number (buf, THUMB_SIZE);
22912 if (value < 0 || value > 255)
22913 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 22914 _("invalid immediate: %ld is out of range"),
c19d1205
ZW		 22915 (long) value);
22916 newval |= value;
22917 md_number_to_chars (buf, newval, THUMB_SIZE);
22918 break;
a737bd4d 22919
c19d1205
ZW		 22920 case BFD_RELOC_ARM_THUMB_SHIFT:
22921 /* 5bit shift value (0..32). LSL cannot take 32. */
22922 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
22923 temp = newval & 0xf800;
22924 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
22925 as_bad_where (fixP->fx_file, fixP->fx_line,
22926 _("invalid shift value: %ld"), (long) value);
22927 /* Shifts of zero must be encoded as LSL. */
22928 if (value == 0)
22929 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
22930 /* Shifts of 32 are encoded as zero. */
22931 else if (value == 32)
22932 value = 0;
22933 newval |= value << 6;
22934 md_number_to_chars (buf, newval, THUMB_SIZE);
22935 break;
a737bd4d 22936
c19d1205
ZW		 22937 case BFD_RELOC_VTABLE_INHERIT:
22938 case BFD_RELOC_VTABLE_ENTRY:
22939 fixP->fx_done = 0;
22940 return;
6c43fab6 22941
b6895b4f
PB		 22942 case BFD_RELOC_ARM_MOVW:
22943 case BFD_RELOC_ARM_MOVT:
22944 case BFD_RELOC_ARM_THUMB_MOVW:
22945 case BFD_RELOC_ARM_THUMB_MOVT:
22946 if (fixP->fx_done || !seg->use_rela_p)
22947 {
22948 /* REL format relocations are limited to a 16-bit addend. */
22949 if (!fixP->fx_done)
22950 {
39623e12 22951 if (value < -0x8000 || value > 0x7fff)
b6895b4f 22952 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 22953 _("offset out of range"));
b6895b4f
PB		 22954 }
22955 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
22956 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22957 {
22958 value >>= 16;
22959 }
22960
22961 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
22962 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
22963 {
22964 newval = get_thumb32_insn (buf);
22965 newval &= 0xfbf08f00;
22966 newval |= (value & 0xf000) << 4;
22967 newval |= (value & 0x0800) << 15;
22968 newval |= (value & 0x0700) << 4;
22969 newval |= (value & 0x00ff);
22970 put_thumb32_insn (buf, newval);
22971 }
22972 else
22973 {
22974 newval = md_chars_to_number (buf, 4);
22975 newval &= 0xfff0f000;
22976 newval |= value & 0x0fff;
22977 newval |= (value & 0xf000) << 4;
22978 md_number_to_chars (buf, newval, 4);
22979 }
22980 }
22981 return;
22982
4962c51a
MS		 22983 case BFD_RELOC_ARM_ALU_PC_G0_NC:
22984 case BFD_RELOC_ARM_ALU_PC_G0:
22985 case BFD_RELOC_ARM_ALU_PC_G1_NC:
22986 case BFD_RELOC_ARM_ALU_PC_G1:
22987 case BFD_RELOC_ARM_ALU_PC_G2:
22988 case BFD_RELOC_ARM_ALU_SB_G0_NC:
22989 case BFD_RELOC_ARM_ALU_SB_G0:
22990 case BFD_RELOC_ARM_ALU_SB_G1_NC:
22991 case BFD_RELOC_ARM_ALU_SB_G1:
22992 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 22993 gas_assert (!fixP->fx_done);
4962c51a
MS		 22994 if (!seg->use_rela_p)
22995 {
477330fc
RM		 22996 bfd_vma insn;
22997 bfd_vma encoded_addend;
22998 bfd_vma addend_abs = abs (value);
22999
23000 /* Check that the absolute value of the addend can be
23001 expressed as an 8-bit constant plus a rotation. */
23002 encoded_addend = encode_arm_immediate (addend_abs);
23003 if (encoded_addend == (unsigned int) FAIL)
4962c51a 23004 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23005 _("the offset 0x%08lX is not representable"),
23006 (unsigned long) addend_abs);
23007
23008 /* Extract the instruction. */
23009 insn = md_chars_to_number (buf, INSN_SIZE);
23010
23011 /* If the addend is positive, use an ADD instruction.
23012 Otherwise use a SUB. Take care not to destroy the S bit. */
23013 insn &= 0xff1fffff;
23014 if (value < 0)
23015 insn |= 1 << 22;
23016 else
23017 insn |= 1 << 23;
23018
23019 /* Place the encoded addend into the first 12 bits of the
23020 instruction. */
23021 insn &= 0xfffff000;
23022 insn |= encoded_addend;
23023
23024 /* Update the instruction. */
23025 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS		 23026 }
23027 break;
23028
23029 case BFD_RELOC_ARM_LDR_PC_G0:
23030 case BFD_RELOC_ARM_LDR_PC_G1:
23031 case BFD_RELOC_ARM_LDR_PC_G2:
23032 case BFD_RELOC_ARM_LDR_SB_G0:
23033 case BFD_RELOC_ARM_LDR_SB_G1:
23034 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 23035 gas_assert (!fixP->fx_done);
4962c51a 23036 if (!seg->use_rela_p)
477330fc
RM		 23037 {
23038 bfd_vma insn;
23039 bfd_vma addend_abs = abs (value);
4962c51a 23040
477330fc
RM		 23041 /* Check that the absolute value of the addend can be
23042 encoded in 12 bits. */
23043 if (addend_abs >= 0x1000)
4962c51a 23044 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23045 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23046 (unsigned long) addend_abs);
23047
23048 /* Extract the instruction. */
23049 insn = md_chars_to_number (buf, INSN_SIZE);
23050
23051 /* If the addend is negative, clear bit 23 of the instruction.
23052 Otherwise set it. */
23053 if (value < 0)
23054 insn &= ~(1 << 23);
23055 else
23056 insn |= 1 << 23;
23057
23058 /* Place the absolute value of the addend into the first 12 bits
23059 of the instruction. */
23060 insn &= 0xfffff000;
23061 insn |= addend_abs;
23062
23063 /* Update the instruction. */
23064 md_number_to_chars (buf, insn, INSN_SIZE);
23065 }
4962c51a
MS		 23066 break;
23067
23068 case BFD_RELOC_ARM_LDRS_PC_G0:
23069 case BFD_RELOC_ARM_LDRS_PC_G1:
23070 case BFD_RELOC_ARM_LDRS_PC_G2:
23071 case BFD_RELOC_ARM_LDRS_SB_G0:
23072 case BFD_RELOC_ARM_LDRS_SB_G1:
23073 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 23074 gas_assert (!fixP->fx_done);
4962c51a 23075 if (!seg->use_rela_p)
477330fc
RM		 23076 {
23077 bfd_vma insn;
23078 bfd_vma addend_abs = abs (value);
4962c51a 23079
477330fc
RM		 23080 /* Check that the absolute value of the addend can be
23081 encoded in 8 bits. */
23082 if (addend_abs >= 0x100)
4962c51a 23083 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23084 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23085 (unsigned long) addend_abs);
23086
23087 /* Extract the instruction. */
23088 insn = md_chars_to_number (buf, INSN_SIZE);
23089
23090 /* If the addend is negative, clear bit 23 of the instruction.
23091 Otherwise set it. */
23092 if (value < 0)
23093 insn &= ~(1 << 23);
23094 else
23095 insn |= 1 << 23;
23096
23097 /* Place the first four bits of the absolute value of the addend
23098 into the first 4 bits of the instruction, and the remaining
23099 four into bits 8 .. 11. */
23100 insn &= 0xfffff0f0;
23101 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
23102
23103 /* Update the instruction. */
23104 md_number_to_chars (buf, insn, INSN_SIZE);
23105 }
4962c51a
MS		 23106 break;
23107
23108 case BFD_RELOC_ARM_LDC_PC_G0:
23109 case BFD_RELOC_ARM_LDC_PC_G1:
23110 case BFD_RELOC_ARM_LDC_PC_G2:
23111 case BFD_RELOC_ARM_LDC_SB_G0:
23112 case BFD_RELOC_ARM_LDC_SB_G1:
23113 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 23114 gas_assert (!fixP->fx_done);
4962c51a 23115 if (!seg->use_rela_p)
477330fc
RM		 23116 {
23117 bfd_vma insn;
23118 bfd_vma addend_abs = abs (value);
4962c51a 23119
477330fc
RM		 23120 /* Check that the absolute value of the addend is a multiple of
23121 four and, when divided by four, fits in 8 bits. */
23122 if (addend_abs & 0x3)
4962c51a 23123 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23124 _("bad offset 0x%08lX (must be word-aligned)"),
23125 (unsigned long) addend_abs);
4962c51a 23126
477330fc 23127 if ((addend_abs >> 2) > 0xff)
4962c51a 23128 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 23129 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23130 (unsigned long) addend_abs);
23131
23132 /* Extract the instruction. */
23133 insn = md_chars_to_number (buf, INSN_SIZE);
23134
23135 /* If the addend is negative, clear bit 23 of the instruction.
23136 Otherwise set it. */
23137 if (value < 0)
23138 insn &= ~(1 << 23);
23139 else
23140 insn |= 1 << 23;
23141
23142 /* Place the addend (divided by four) into the first eight
23143 bits of the instruction. */
23144 insn &= 0xfffffff0;
23145 insn |= addend_abs >> 2;
23146
23147 /* Update the instruction. */
23148 md_number_to_chars (buf, insn, INSN_SIZE);
23149 }
4962c51a
MS		 23150 break;
23151
845b51d6
PB		 23152 case BFD_RELOC_ARM_V4BX:
23153 /* This will need to go in the object file. */
23154 fixP->fx_done = 0;
23155 break;
23156
c19d1205
ZW		 23157 case BFD_RELOC_UNUSED:
23158 default:
23159 as_bad_where (fixP->fx_file, fixP->fx_line,
23160 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
23161 }
6c43fab6
RE		 23162}
23163
c19d1205
ZW		 23164/* Translate internal representation of relocation info to BFD target
23165 format. */
a737bd4d 23166
c19d1205 23167arelent *
00a97672 23168tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 23169{
c19d1205
ZW		 23170 arelent * reloc;
23171 bfd_reloc_code_real_type code;
a737bd4d 23172
21d799b5 23173 reloc = (arelent *) xmalloc (sizeof (arelent));
a737bd4d 23174
21d799b5 23175 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
c19d1205
ZW		 23176 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
23177 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 23178
2fc8bdac 23179 if (fixp->fx_pcrel)
00a97672
RS		 23180 {
23181 if (section->use_rela_p)
23182 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
23183 else
23184 fixp->fx_offset = reloc->address;
23185 }
c19d1205 23186 reloc->addend = fixp->fx_offset;
a737bd4d 23187
c19d1205 23188 switch (fixp->fx_r_type)
a737bd4d 23189 {
c19d1205
ZW		 23190 case BFD_RELOC_8:
23191 if (fixp->fx_pcrel)
23192 {
23193 code = BFD_RELOC_8_PCREL;
23194 break;
23195 }
a737bd4d 23196
c19d1205
ZW		 23197 case BFD_RELOC_16:
23198 if (fixp->fx_pcrel)
23199 {
23200 code = BFD_RELOC_16_PCREL;
23201 break;
23202 }
6c43fab6 23203
c19d1205
ZW		 23204 case BFD_RELOC_32:
23205 if (fixp->fx_pcrel)
23206 {
23207 code = BFD_RELOC_32_PCREL;
23208 break;
23209 }
a737bd4d 23210
b6895b4f
PB		 23211 case BFD_RELOC_ARM_MOVW:
23212 if (fixp->fx_pcrel)
23213 {
23214 code = BFD_RELOC_ARM_MOVW_PCREL;
23215 break;
23216 }
23217
23218 case BFD_RELOC_ARM_MOVT:
23219 if (fixp->fx_pcrel)
23220 {
23221 code = BFD_RELOC_ARM_MOVT_PCREL;
23222 break;
23223 }
23224
23225 case BFD_RELOC_ARM_THUMB_MOVW:
23226 if (fixp->fx_pcrel)
23227 {
23228 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
23229 break;
23230 }
23231
23232 case BFD_RELOC_ARM_THUMB_MOVT:
23233 if (fixp->fx_pcrel)
23234 {
23235 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
23236 break;
23237 }
23238
c19d1205
ZW		 23239 case BFD_RELOC_NONE:
23240 case BFD_RELOC_ARM_PCREL_BRANCH:
23241 case BFD_RELOC_ARM_PCREL_BLX:
23242 case BFD_RELOC_RVA:
23243 case BFD_RELOC_THUMB_PCREL_BRANCH7:
23244 case BFD_RELOC_THUMB_PCREL_BRANCH9:
23245 case BFD_RELOC_THUMB_PCREL_BRANCH12:
23246 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23247 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23248 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW		 23249 case BFD_RELOC_VTABLE_ENTRY:
23250 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC		 23251#ifdef TE_PE
23252 case BFD_RELOC_32_SECREL:
23253#endif
c19d1205
ZW		 23254 code = fixp->fx_r_type;
23255 break;
a737bd4d 23256
00adf2d4
JB		 23257 case BFD_RELOC_THUMB_PCREL_BLX:
23258#ifdef OBJ_ELF
23259 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
23260 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
23261 else
23262#endif
23263 code = BFD_RELOC_THUMB_PCREL_BLX;
23264 break;
23265
c19d1205
ZW		 23266 case BFD_RELOC_ARM_LITERAL:
23267 case BFD_RELOC_ARM_HWLITERAL:
23268 /* If this is called then the a literal has
23269 been referenced across a section boundary. */
23270 as_bad_where (fixp->fx_file, fixp->fx_line,
23271 _("literal referenced across section boundary"));
23272 return NULL;
a737bd4d 23273
c19d1205 23274#ifdef OBJ_ELF
0855e32b
NS		 23275 case BFD_RELOC_ARM_TLS_CALL:
23276 case BFD_RELOC_ARM_THM_TLS_CALL:
23277 case BFD_RELOC_ARM_TLS_DESCSEQ:
23278 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW		 23279 case BFD_RELOC_ARM_GOT32:
23280 case BFD_RELOC_ARM_GOTOFF:
b43420e6 23281 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW		 23282 case BFD_RELOC_ARM_PLT32:
23283 case BFD_RELOC_ARM_TARGET1:
23284 case BFD_RELOC_ARM_ROSEGREL32:
23285 case BFD_RELOC_ARM_SBREL32:
23286 case BFD_RELOC_ARM_PREL31:
23287 case BFD_RELOC_ARM_TARGET2:
23288 case BFD_RELOC_ARM_TLS_LE32:
23289 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB		 23290 case BFD_RELOC_ARM_PCREL_CALL:
23291 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS		 23292 case BFD_RELOC_ARM_ALU_PC_G0_NC:
23293 case BFD_RELOC_ARM_ALU_PC_G0:
23294 case BFD_RELOC_ARM_ALU_PC_G1_NC:
23295 case BFD_RELOC_ARM_ALU_PC_G1:
23296 case BFD_RELOC_ARM_ALU_PC_G2:
23297 case BFD_RELOC_ARM_LDR_PC_G0:
23298 case BFD_RELOC_ARM_LDR_PC_G1:
23299 case BFD_RELOC_ARM_LDR_PC_G2:
23300 case BFD_RELOC_ARM_LDRS_PC_G0:
23301 case BFD_RELOC_ARM_LDRS_PC_G1:
23302 case BFD_RELOC_ARM_LDRS_PC_G2:
23303 case BFD_RELOC_ARM_LDC_PC_G0:
23304 case BFD_RELOC_ARM_LDC_PC_G1:
23305 case BFD_RELOC_ARM_LDC_PC_G2:
23306 case BFD_RELOC_ARM_ALU_SB_G0_NC:
23307 case BFD_RELOC_ARM_ALU_SB_G0:
23308 case BFD_RELOC_ARM_ALU_SB_G1_NC:
23309 case BFD_RELOC_ARM_ALU_SB_G1:
23310 case BFD_RELOC_ARM_ALU_SB_G2:
23311 case BFD_RELOC_ARM_LDR_SB_G0:
23312 case BFD_RELOC_ARM_LDR_SB_G1:
23313 case BFD_RELOC_ARM_LDR_SB_G2:
23314 case BFD_RELOC_ARM_LDRS_SB_G0:
23315 case BFD_RELOC_ARM_LDRS_SB_G1:
23316 case BFD_RELOC_ARM_LDRS_SB_G2:
23317 case BFD_RELOC_ARM_LDC_SB_G0:
23318 case BFD_RELOC_ARM_LDC_SB_G1:
23319 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 23320 case BFD_RELOC_ARM_V4BX:
c19d1205
ZW		 23321 code = fixp->fx_r_type;
23322 break;
a737bd4d 23323
0855e32b 23324 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 23325 case BFD_RELOC_ARM_TLS_GD32:
23326 case BFD_RELOC_ARM_TLS_IE32:
23327 case BFD_RELOC_ARM_TLS_LDM32:
23328 /* BFD will include the symbol's address in the addend.
23329 But we don't want that, so subtract it out again here. */
23330 if (!S_IS_COMMON (fixp->fx_addsy))
23331 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
23332 code = fixp->fx_r_type;
23333 break;
23334#endif
a737bd4d 23335
c19d1205
ZW		 23336 case BFD_RELOC_ARM_IMMEDIATE:
23337 as_bad_where (fixp->fx_file, fixp->fx_line,
23338 _("internal relocation (type: IMMEDIATE) not fixed up"));
23339 return NULL;
a737bd4d 23340
c19d1205
ZW		 23341 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
23342 as_bad_where (fixp->fx_file, fixp->fx_line,
23343 _("ADRL used for a symbol not defined in the same file"));
23344 return NULL;
a737bd4d 23345
c19d1205 23346 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 23347 if (section->use_rela_p)
23348 {
23349 code = fixp->fx_r_type;
23350 break;
23351 }
23352
c19d1205
ZW		 23353 if (fixp->fx_addsy != NULL
23354 && !S_IS_DEFINED (fixp->fx_addsy)
23355 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 23356 {
c19d1205
ZW		 23357 as_bad_where (fixp->fx_file, fixp->fx_line,
23358 _("undefined local label `%s'"),
23359 S_GET_NAME (fixp->fx_addsy));
23360 return NULL;
a737bd4d
NC		 23361 }
23362
c19d1205
ZW		 23363 as_bad_where (fixp->fx_file, fixp->fx_line,
23364 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23365 return NULL;
a737bd4d 23366
c19d1205
ZW		 23367 default:
23368 {
23369 char * type;
6c43fab6 23370
c19d1205
ZW		 23371 switch (fixp->fx_r_type)
23372 {
23373 case BFD_RELOC_NONE: type = "NONE"; break;
23374 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
23375 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 23376 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW		 23377 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
23378 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
23379 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 23380 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 23381 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW		 23382 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
23383 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
23384 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
23385 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
23386 default: type = _("<unknown>"); break;
23387 }
23388 as_bad_where (fixp->fx_file, fixp->fx_line,
23389 _("cannot represent %s relocation in this object file format"),
23390 type);
23391 return NULL;
23392 }
a737bd4d 23393 }
6c43fab6 23394
c19d1205
ZW		 23395#ifdef OBJ_ELF
23396 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
23397 && GOT_symbol
23398 && fixp->fx_addsy == GOT_symbol)
23399 {
23400 code = BFD_RELOC_ARM_GOTPC;
23401 reloc->addend = fixp->fx_offset = reloc->address;
23402 }
23403#endif
6c43fab6 23404
c19d1205 23405 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 23406
c19d1205
ZW		 23407 if (reloc->howto == NULL)
23408 {
23409 as_bad_where (fixp->fx_file, fixp->fx_line,
23410 _("cannot represent %s relocation in this object file format"),
23411 bfd_get_reloc_code_name (code));
23412 return NULL;
23413 }
6c43fab6 23414
c19d1205
ZW		 23415 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23416 vtable entry to be used in the relocation's section offset. */
23417 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
23418 reloc->address = fixp->fx_offset;
6c43fab6 23419
c19d1205 23420 return reloc;
6c43fab6
RE		 23421}
23422
c19d1205 23423/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 23424
c19d1205
ZW		 23425void
23426cons_fix_new_arm (fragS * frag,
23427 int where,
23428 int size,
62ebcb5c
AM		 23429 expressionS * exp,
23430 bfd_reloc_code_real_type reloc)
6c43fab6 23431{
c19d1205 23432 int pcrel = 0;
6c43fab6 23433
c19d1205
ZW		 23434 /* Pick a reloc.
23435 FIXME: @@ Should look at CPU word size. */
23436 switch (size)
23437 {
23438 case 1:
62ebcb5c 23439 reloc = BFD_RELOC_8;
c19d1205
ZW		 23440 break;
23441 case 2:
62ebcb5c 23442 reloc = BFD_RELOC_16;
c19d1205
ZW		 23443 break;
23444 case 4:
23445 default:
62ebcb5c 23446 reloc = BFD_RELOC_32;
c19d1205
ZW		 23447 break;
23448 case 8:
62ebcb5c 23449 reloc = BFD_RELOC_64;
c19d1205
ZW		 23450 break;
23451 }
6c43fab6 23452
f0927246
NC		 23453#ifdef TE_PE
23454 if (exp->X_op == O_secrel)
23455 {
23456 exp->X_op = O_symbol;
62ebcb5c 23457 reloc = BFD_RELOC_32_SECREL;
f0927246
NC		 23458 }
23459#endif
23460
62ebcb5c 23461 fix_new_exp (frag, where, size, exp, pcrel, reloc);
c19d1205 23462}
6c43fab6 23463
4343666d 23464#if defined (OBJ_COFF)
c19d1205
ZW		 23465void
23466arm_validate_fix (fixS * fixP)
6c43fab6 23467{
c19d1205
ZW		 23468 /* If the destination of the branch is a defined symbol which does not have
23469 the THUMB_FUNC attribute, then we must be calling a function which has
23470 the (interfacearm) attribute. We look for the Thumb entry point to that
23471 function and change the branch to refer to that function instead. */
23472 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
23473 && fixP->fx_addsy != NULL
23474 && S_IS_DEFINED (fixP->fx_addsy)
23475 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 23476 {
c19d1205 23477 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 23478 }
c19d1205
ZW		 23479}
23480#endif
6c43fab6 23481
267bf995 23482
c19d1205
ZW		 23483int
23484arm_force_relocation (struct fix * fixp)
23485{
23486#if defined (OBJ_COFF) && defined (TE_PE)
23487 if (fixp->fx_r_type == BFD_RELOC_RVA)
23488 return 1;
23489#endif
6c43fab6 23490
267bf995
RR		 23491 /* In case we have a call or a branch to a function in ARM ISA mode from
23492 a thumb function or vice-versa force the relocation. These relocations
23493 are cleared off for some cores that might have blx and simple transformations
23494 are possible. */
23495
23496#ifdef OBJ_ELF
23497 switch (fixp->fx_r_type)
23498 {
23499 case BFD_RELOC_ARM_PCREL_JUMP:
23500 case BFD_RELOC_ARM_PCREL_CALL:
23501 case BFD_RELOC_THUMB_PCREL_BLX:
23502 if (THUMB_IS_FUNC (fixp->fx_addsy))
23503 return 1;
23504 break;
23505
23506 case BFD_RELOC_ARM_PCREL_BLX:
23507 case BFD_RELOC_THUMB_PCREL_BRANCH25:
23508 case BFD_RELOC_THUMB_PCREL_BRANCH20:
23509 case BFD_RELOC_THUMB_PCREL_BRANCH23:
23510 if (ARM_IS_FUNC (fixp->fx_addsy))
23511 return 1;
23512 break;
23513
23514 default:
23515 break;
23516 }
23517#endif
23518
b5884301
PB		 23519 /* Resolve these relocations even if the symbol is extern or weak.
23520 Technically this is probably wrong due to symbol preemption.
23521 In practice these relocations do not have enough range to be useful
23522 at dynamic link time, and some code (e.g. in the Linux kernel)
23523 expects these references to be resolved. */
c19d1205
ZW		 23524 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
23525 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 23526 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 23527 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB		 23528 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
23529 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
23530 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 23531 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB		 23532 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
23533 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB		 23534 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
23535 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
23536 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
23537 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 23538 return 0;
a737bd4d 23539
4962c51a
MS		 23540 /* Always leave these relocations for the linker. */
23541 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23542 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23543 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
23544 return 1;
23545
f0291e4c
PB		 23546 /* Always generate relocations against function symbols. */
23547 if (fixp->fx_r_type == BFD_RELOC_32
23548 && fixp->fx_addsy
23549 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
23550 return 1;
23551
c19d1205 23552 return generic_force_reloc (fixp);
404ff6b5
AH		 23553}
23554
0ffdc86c 23555#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB		 23556/* Relocations against function names must be left unadjusted,
23557 so that the linker can use this information to generate interworking
23558 stubs. The MIPS version of this function
c19d1205
ZW		 23559 also prevents relocations that are mips-16 specific, but I do not
23560 know why it does this.
404ff6b5 23561
c19d1205
ZW		 23562 FIXME:
23563 There is one other problem that ought to be addressed here, but
23564 which currently is not: Taking the address of a label (rather
23565 than a function) and then later jumping to that address. Such
23566 addresses also ought to have their bottom bit set (assuming that
23567 they reside in Thumb code), but at the moment they will not. */
404ff6b5 23568
c19d1205
ZW		 23569bfd_boolean
23570arm_fix_adjustable (fixS * fixP)
404ff6b5 23571{
c19d1205
ZW		 23572 if (fixP->fx_addsy == NULL)
23573 return 1;
404ff6b5 23574
e28387c3
PB		 23575 /* Preserve relocations against symbols with function type. */
23576 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 23577 return FALSE;
e28387c3 23578
c19d1205
ZW		 23579 if (THUMB_IS_FUNC (fixP->fx_addsy)
23580 && fixP->fx_subsy == NULL)
c921be7d 23581 return FALSE;
a737bd4d 23582
c19d1205
ZW		 23583 /* We need the symbol name for the VTABLE entries. */
23584 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
23585 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 23586 return FALSE;
404ff6b5 23587
c19d1205
ZW		 23588 /* Don't allow symbols to be discarded on GOT related relocs. */
23589 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
23590 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
23591 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
23592 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
23593 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
23594 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
23595 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
23596 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS		 23597 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
23598 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
23599 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
23600 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
23601 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 23602 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 23603 return FALSE;
a737bd4d 23604
4962c51a
MS		 23605 /* Similarly for group relocations. */
23606 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
23607 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
23608 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 23609 return FALSE;
4962c51a 23610
79947c54
CD		 23611 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23612 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
23613 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
23614 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
23615 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
23616 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
23617 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
23618 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
23619 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 23620 return FALSE;
79947c54 23621
c921be7d 23622 return TRUE;
a737bd4d 23623}
0ffdc86c
NC		 23624#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23625
23626#ifdef OBJ_ELF
404ff6b5 23627
c19d1205
ZW		 23628const char *
23629elf32_arm_target_format (void)
404ff6b5 23630{
c19d1205
ZW		 23631#ifdef TE_SYMBIAN
23632 return (target_big_endian
23633 ? "elf32-bigarm-symbian"
23634 : "elf32-littlearm-symbian");
23635#elif defined (TE_VXWORKS)
23636 return (target_big_endian
23637 ? "elf32-bigarm-vxworks"
23638 : "elf32-littlearm-vxworks");
b38cadfb
NC		 23639#elif defined (TE_NACL)
23640 return (target_big_endian
23641 ? "elf32-bigarm-nacl"
23642 : "elf32-littlearm-nacl");
c19d1205
ZW		 23643#else
23644 if (target_big_endian)
23645 return "elf32-bigarm";
23646 else
23647 return "elf32-littlearm";
23648#endif
404ff6b5
AH		 23649}
23650
c19d1205
ZW		 23651void
23652armelf_frob_symbol (symbolS * symp,
23653 int * puntp)
404ff6b5 23654{
c19d1205
ZW		 23655 elf_frob_symbol (symp, puntp);
23656}
23657#endif
404ff6b5 23658
c19d1205 23659/* MD interface: Finalization. */
a737bd4d 23660
c19d1205
ZW		 23661void
23662arm_cleanup (void)
23663{
23664 literal_pool * pool;
a737bd4d 23665
e07e6e58
NC		 23666 /* Ensure that all the IT blocks are properly closed. */
23667 check_it_blocks_finished ();
23668
c19d1205
ZW		 23669 for (pool = list_of_pools; pool; pool = pool->next)
23670 {
5f4273c7 23671 /* Put it at the end of the relevant section. */
c19d1205
ZW		 23672 subseg_set (pool->section, pool->sub_section);
23673#ifdef OBJ_ELF
23674 arm_elf_change_section ();
23675#endif
23676 s_ltorg (0);
23677 }
404ff6b5
AH		 23678}
23679
cd000bff
DJ		 23680#ifdef OBJ_ELF
23681/* Remove any excess mapping symbols generated for alignment frags in
23682 SEC. We may have created a mapping symbol before a zero byte
23683 alignment; remove it if there's a mapping symbol after the
23684 alignment. */
23685static void
23686check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
23687 void *dummy ATTRIBUTE_UNUSED)
23688{
23689 segment_info_type *seginfo = seg_info (sec);
23690 fragS *fragp;
23691
23692 if (seginfo == NULL || seginfo->frchainP == NULL)
23693 return;
23694
23695 for (fragp = seginfo->frchainP->frch_root;
23696 fragp != NULL;
23697 fragp = fragp->fr_next)
23698 {
23699 symbolS *sym = fragp->tc_frag_data.last_map;
23700 fragS *next = fragp->fr_next;
23701
23702 /* Variable-sized frags have been converted to fixed size by
23703 this point. But if this was variable-sized to start with,
23704 there will be a fixed-size frag after it. So don't handle
23705 next == NULL. */
23706 if (sym == NULL || next == NULL)
23707 continue;
23708
23709 if (S_GET_VALUE (sym) < next->fr_address)
23710 /* Not at the end of this frag. */
23711 continue;
23712 know (S_GET_VALUE (sym) == next->fr_address);
23713
23714 do
23715 {
23716 if (next->tc_frag_data.first_map != NULL)
23717 {
23718 /* Next frag starts with a mapping symbol. Discard this
23719 one. */
23720 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23721 break;
23722 }
23723
23724 if (next->fr_next == NULL)
23725 {
23726 /* This mapping symbol is at the end of the section. Discard
23727 it. */
23728 know (next->fr_fix == 0 && next->fr_var == 0);
23729 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
23730 break;
23731 }
23732
23733 /* As long as we have empty frags without any mapping symbols,
23734 keep looking. */
23735 /* If the next frag is non-empty and does not start with a
23736 mapping symbol, then this mapping symbol is required. */
23737 if (next->fr_address != next->fr_next->fr_address)
23738 break;
23739
23740 next = next->fr_next;
23741 }
23742 while (next != NULL);
23743 }
23744}
23745#endif
23746
c19d1205
ZW		 23747/* Adjust the symbol table. This marks Thumb symbols as distinct from
23748 ARM ones. */
404ff6b5 23749
c19d1205
ZW		 23750void
23751arm_adjust_symtab (void)
404ff6b5 23752{
c19d1205
ZW		 23753#ifdef OBJ_COFF
23754 symbolS * sym;
404ff6b5 23755
c19d1205
ZW		 23756 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
23757 {
23758 if (ARM_IS_THUMB (sym))
23759 {
23760 if (THUMB_IS_FUNC (sym))
23761 {
23762 /* Mark the symbol as a Thumb function. */
23763 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
23764 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
23765 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 23766
c19d1205
ZW		 23767 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
23768 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
23769 else
23770 as_bad (_("%s: unexpected function type: %d"),
23771 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
23772 }
23773 else switch (S_GET_STORAGE_CLASS (sym))
23774 {
23775 case C_EXT:
23776 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
23777 break;
23778 case C_STAT:
23779 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
23780 break;
23781 case C_LABEL:
23782 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
23783 break;
23784 default:
23785 /* Do nothing. */
23786 break;
23787 }
23788 }
a737bd4d 23789
c19d1205
ZW		 23790 if (ARM_IS_INTERWORK (sym))
23791 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 23792 }
c19d1205
ZW		 23793#endif
23794#ifdef OBJ_ELF
23795 symbolS * sym;
23796 char bind;
404ff6b5 23797
c19d1205 23798 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 23799 {
c19d1205
ZW		 23800 if (ARM_IS_THUMB (sym))
23801 {
23802 elf_symbol_type * elf_sym;
404ff6b5 23803
c19d1205
ZW		 23804 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
23805 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 23806
b0796911
PB		 23807 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
23808 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW		 23809 {
23810 /* If it's a .thumb_func, declare it as so,
23811 otherwise tag label as .code 16. */
23812 if (THUMB_IS_FUNC (sym))
35fc36a8
RS		 23813 elf_sym->internal_elf_sym.st_target_internal
23814 = ST_BRANCH_TO_THUMB;
3ba67470 23815 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW		 23816 elf_sym->internal_elf_sym.st_info =
23817 ELF_ST_INFO (bind, STT_ARM_16BIT);
23818 }
23819 }
23820 }
cd000bff
DJ		 23821
23822 /* Remove any overlapping mapping symbols generated by alignment frags. */
23823 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM		 23824 /* Now do generic ELF adjustments. */
23825 elf_adjust_symtab ();
c19d1205 23826#endif
404ff6b5
AH		 23827}
23828
c19d1205 23829/* MD interface: Initialization. */
404ff6b5 23830
a737bd4d 23831static void
c19d1205 23832set_constant_flonums (void)
a737bd4d 23833{
c19d1205 23834 int i;
404ff6b5 23835
c19d1205
ZW		 23836 for (i = 0; i < NUM_FLOAT_VALS; i++)
23837 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
23838 abort ();
a737bd4d 23839}
404ff6b5 23840
3e9e4fcf
JB		 23841/* Auto-select Thumb mode if it's the only available instruction set for the
23842 given architecture. */
23843
23844static void
23845autoselect_thumb_from_cpu_variant (void)
23846{
23847 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
23848 opcode_select (16);
23849}
23850
c19d1205
ZW		 23851void
23852md_begin (void)
a737bd4d 23853{
c19d1205
ZW		 23854 unsigned mach;
23855 unsigned int i;
404ff6b5 23856
c19d1205
ZW		 23857 if ( (arm_ops_hsh = hash_new ()) == NULL
23858 || (arm_cond_hsh = hash_new ()) == NULL
23859 || (arm_shift_hsh = hash_new ()) == NULL
23860 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 23861 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 23862 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB		 23863 || (arm_reloc_hsh = hash_new ()) == NULL
23864 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW		 23865 as_fatal (_("virtual memory exhausted"));
23866
23867 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 23868 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 23869 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 23870 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
c19d1205 23871 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 23872 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 23873 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 23874 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 23875 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 23876 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 23877 (void *) (v7m_psrs + i));
c19d1205 23878 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 23879 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB		 23880 for (i = 0;
23881 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
23882 i++)
d3ce72d0 23883 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 23884 (void *) (barrier_opt_names + i));
c19d1205 23885#ifdef OBJ_ELF
3da1d841
NC		 23886 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
23887 {
23888 struct reloc_entry * entry = reloc_names + i;
23889
23890 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
23891 /* This makes encode_branch() use the EABI versions of this relocation. */
23892 entry->reloc = BFD_RELOC_UNUSED;
23893
23894 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
23895 }
c19d1205
ZW		 23896#endif
23897
23898 set_constant_flonums ();
404ff6b5 23899
c19d1205
ZW		 23900 /* Set the cpu variant based on the command-line options. We prefer
23901 -mcpu= over -march= if both are set (as for GCC); and we prefer
23902 -mfpu= over any other way of setting the floating point unit.
23903 Use of legacy options with new options are faulted. */
e74cfd16 23904 if (legacy_cpu)
404ff6b5 23905 {
e74cfd16 23906 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW		 23907 as_bad (_("use of old and new-style options to set CPU type"));
23908
23909 mcpu_cpu_opt = legacy_cpu;
404ff6b5 23910 }
e74cfd16 23911 else if (!mcpu_cpu_opt)
c19d1205 23912 mcpu_cpu_opt = march_cpu_opt;
404ff6b5 23913
e74cfd16 23914 if (legacy_fpu)
c19d1205 23915 {
e74cfd16 23916 if (mfpu_opt)
c19d1205 23917 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f
RE		 23918
23919 mfpu_opt = legacy_fpu;
23920 }
e74cfd16 23921 else if (!mfpu_opt)
03b1477f 23922 {
45eb4c1b
NS		 23923#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23924 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE		 23925 /* Some environments specify a default FPU. If they don't, infer it
23926 from the processor. */
e74cfd16 23927 if (mcpu_fpu_opt)
03b1477f
RE		 23928 mfpu_opt = mcpu_fpu_opt;
23929 else
23930 mfpu_opt = march_fpu_opt;
39c2da32 23931#else
e74cfd16 23932 mfpu_opt = &fpu_default;
39c2da32 23933#endif
03b1477f
RE		 23934 }
23935
e74cfd16 23936 if (!mfpu_opt)
03b1477f 23937 {
493cb6ef 23938 if (mcpu_cpu_opt != NULL)
e74cfd16 23939 mfpu_opt = &fpu_default;
493cb6ef 23940 else if (mcpu_fpu_opt != NULL && ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt, arm_ext_v5))
e74cfd16 23941 mfpu_opt = &fpu_arch_vfp_v2;
03b1477f 23942 else
e74cfd16 23943 mfpu_opt = &fpu_arch_fpa;
03b1477f
RE		 23944 }
23945
ee065d83 23946#ifdef CPU_DEFAULT
e74cfd16 23947 if (!mcpu_cpu_opt)
ee065d83 23948 {
e74cfd16
PB		 23949 mcpu_cpu_opt = &cpu_default;
23950 selected_cpu = cpu_default;
ee065d83 23951 }
73f43896
NC		 23952 else if (no_cpu_selected ())
23953 selected_cpu = cpu_default;
e74cfd16
PB		 23954#else
23955 if (mcpu_cpu_opt)
23956 selected_cpu = *mcpu_cpu_opt;
ee065d83 23957 else
e74cfd16 23958 mcpu_cpu_opt = &arm_arch_any;
ee065d83 23959#endif
03b1477f 23960
e74cfd16 23961 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
03b1477f 23962
3e9e4fcf
JB		 23963 autoselect_thumb_from_cpu_variant ();
23964
e74cfd16 23965 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 23966
f17c130b 23967#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 23968 {
7cc69913
NC		 23969 unsigned int flags = 0;
23970
23971#if defined OBJ_ELF
23972 flags = meabi_flags;
d507cf36
PB		 23973
23974 switch (meabi_flags)
33a392fb 23975 {
d507cf36 23976 case EF_ARM_EABI_UNKNOWN:
7cc69913 23977#endif
d507cf36
PB		 23978 /* Set the flags in the private structure. */
23979 if (uses_apcs_26) flags |= F_APCS26;
23980 if (support_interwork) flags |= F_INTERWORK;
23981 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 23982 if (pic_code) flags |= F_PIC;
e74cfd16 23983 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC		 23984 flags |= F_SOFT_FLOAT;
23985
d507cf36
PB		 23986 switch (mfloat_abi_opt)
23987 {
23988 case ARM_FLOAT_ABI_SOFT:
23989 case ARM_FLOAT_ABI_SOFTFP:
23990 flags |= F_SOFT_FLOAT;
23991 break;
33a392fb 23992
d507cf36
PB		 23993 case ARM_FLOAT_ABI_HARD:
23994 if (flags & F_SOFT_FLOAT)
23995 as_bad (_("hard-float conflicts with specified fpu"));
23996 break;
23997 }
03b1477f 23998
e74cfd16
PB		 23999 /* Using pure-endian doubles (even if soft-float). */
24000 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 24001 flags |= F_VFP_FLOAT;
f17c130b 24002
fde78edd 24003#if defined OBJ_ELF
e74cfd16 24004 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 24005 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB		 24006 break;
24007
8cb51566 24008 case EF_ARM_EABI_VER4:
3a4a14e9 24009 case EF_ARM_EABI_VER5:
c19d1205 24010 /* No additional flags to set. */
d507cf36
PB		 24011 break;
24012
24013 default:
24014 abort ();
24015 }
7cc69913 24016#endif
b99bd4ef
NC		 24017 bfd_set_private_flags (stdoutput, flags);
24018
24019 /* We have run out flags in the COFF header to encode the
24020 status of ATPCS support, so instead we create a dummy,
c19d1205 24021 empty, debug section called .arm.atpcs. */
b99bd4ef
NC		 24022 if (atpcs)
24023 {
24024 asection * sec;
24025
24026 sec = bfd_make_section (stdoutput, ".arm.atpcs");
24027
24028 if (sec != NULL)
24029 {
24030 bfd_set_section_flags
24031 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
24032 bfd_set_section_size (stdoutput, sec, 0);
24033 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
24034 }
24035 }
7cc69913 24036 }
f17c130b 24037#endif
b99bd4ef
NC		 24038
24039 /* Record the CPU type as well. */
2d447fca
JM		 24040 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
24041 mach = bfd_mach_arm_iWMMXt2;
24042 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 24043 mach = bfd_mach_arm_iWMMXt;
e74cfd16 24044 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 24045 mach = bfd_mach_arm_XScale;
e74cfd16 24046 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 24047 mach = bfd_mach_arm_ep9312;
e74cfd16 24048 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 24049 mach = bfd_mach_arm_5TE;
e74cfd16 24050 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 24051 {
e74cfd16 24052 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 24053 mach = bfd_mach_arm_5T;
24054 else
24055 mach = bfd_mach_arm_5;
24056 }
e74cfd16 24057 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 24058 {
e74cfd16 24059 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 24060 mach = bfd_mach_arm_4T;
24061 else
24062 mach = bfd_mach_arm_4;
24063 }
e74cfd16 24064 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 24065 mach = bfd_mach_arm_3M;
e74cfd16
PB		 24066 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
24067 mach = bfd_mach_arm_3;
24068 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
24069 mach = bfd_mach_arm_2a;
24070 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
24071 mach = bfd_mach_arm_2;
24072 else
24073 mach = bfd_mach_arm_unknown;
b99bd4ef
NC		 24074
24075 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
24076}
24077
c19d1205 24078/* Command line processing. */
b99bd4ef 24079
c19d1205
ZW		 24080/* md_parse_option
24081 Invocation line includes a switch not recognized by the base assembler.
24082 See if it's a processor-specific option.
b99bd4ef 24083
c19d1205
ZW		 24084 This routine is somewhat complicated by the need for backwards
24085 compatibility (since older releases of gcc can't be changed).
24086 The new options try to make the interface as compatible as
24087 possible with GCC.
b99bd4ef 24088
c19d1205 24089 New options (supported) are:
b99bd4ef 24090
c19d1205
ZW		 24091 -mcpu=<cpu name> Assemble for selected processor
24092 -march=<architecture name> Assemble for selected architecture
24093 -mfpu=<fpu architecture> Assemble for selected FPU.
24094 -EB/-mbig-endian Big-endian
24095 -EL/-mlittle-endian Little-endian
24096 -k Generate PIC code
24097 -mthumb Start in Thumb mode
24098 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 24099
278df34e 24100 -m[no-]warn-deprecated Warn about deprecated features
267bf995 24101
c19d1205 24102 For now we will also provide support for:
b99bd4ef 24103
c19d1205
ZW		 24104 -mapcs-32 32-bit Program counter
24105 -mapcs-26 26-bit Program counter
24106 -macps-float Floats passed in FP registers
24107 -mapcs-reentrant Reentrant code
24108 -matpcs
24109 (sometime these will probably be replaced with -mapcs=<list of options>
24110 and -matpcs=<list of options>)
b99bd4ef 24111
c19d1205
ZW		 24112 The remaining options are only supported for back-wards compatibility.
24113 Cpu variants, the arm part is optional:
24114 -m[arm]1 Currently not supported.
24115 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24116 -m[arm]3 Arm 3 processor
24117 -m[arm]6[xx], Arm 6 processors
24118 -m[arm]7[xx][t][[d]m] Arm 7 processors
24119 -m[arm]8[10] Arm 8 processors
24120 -m[arm]9[20][tdmi] Arm 9 processors
24121 -mstrongarm[110[0]] StrongARM processors
24122 -mxscale XScale processors
24123 -m[arm]v[2345[t[e]]] Arm architectures
24124 -mall All (except the ARM1)
24125 FP variants:
24126 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24127 -mfpe-old (No float load/store multiples)
24128 -mvfpxd VFP Single precision
24129 -mvfp All VFP
24130 -mno-fpu Disable all floating point instructions
b99bd4ef 24131
c19d1205
ZW		 24132 The following CPU names are recognized:
24133 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24134 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24135 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24136 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24137 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24138 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24139 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 24140
c19d1205 24141 */
b99bd4ef 24142
c19d1205 24143const char * md_shortopts = "m:k";
b99bd4ef 24144
c19d1205
ZW		 24145#ifdef ARM_BI_ENDIAN
24146#define OPTION_EB (OPTION_MD_BASE + 0)
24147#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 24148#else
c19d1205
ZW		 24149#if TARGET_BYTES_BIG_ENDIAN
24150#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 24151#else
c19d1205
ZW		 24152#define OPTION_EL (OPTION_MD_BASE + 1)
24153#endif
b99bd4ef 24154#endif
845b51d6 24155#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
b99bd4ef 24156
c19d1205 24157struct option md_longopts[] =
b99bd4ef 24158{
c19d1205
ZW		 24159#ifdef OPTION_EB
24160 {"EB", no_argument, NULL, OPTION_EB},
24161#endif
24162#ifdef OPTION_EL
24163 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 24164#endif
845b51d6 24165 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
c19d1205
ZW		 24166 {NULL, no_argument, NULL, 0}
24167};
b99bd4ef 24168
c19d1205 24169size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 24170
c19d1205 24171struct arm_option_table
b99bd4ef 24172{
c19d1205
ZW		 24173 char *option; /* Option name to match. */
24174 char *help; /* Help information. */
24175 int *var; /* Variable to change. */
24176 int value; /* What to change it to. */
24177 char *deprecated; /* If non-null, print this message. */
24178};
b99bd4ef 24179
c19d1205
ZW		 24180struct arm_option_table arm_opts[] =
24181{
24182 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
24183 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
24184 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
24185 &support_interwork, 1, NULL},
24186 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
24187 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
24188 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
24189 1, NULL},
24190 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
24191 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
24192 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
24193 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
24194 NULL},
b99bd4ef 24195
c19d1205
ZW		 24196 /* These are recognized by the assembler, but have no affect on code. */
24197 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
24198 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS		 24199
24200 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
24201 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
24202 &warn_on_deprecated, 0, NULL},
e74cfd16
PB		 24203 {NULL, NULL, NULL, 0, NULL}
24204};
24205
24206struct arm_legacy_option_table
24207{
24208 char *option; /* Option name to match. */
24209 const arm_feature_set **var; /* Variable to change. */
24210 const arm_feature_set value; /* What to change it to. */
24211 char *deprecated; /* If non-null, print this message. */
24212};
b99bd4ef 24213
e74cfd16
PB		 24214const struct arm_legacy_option_table arm_legacy_opts[] =
24215{
c19d1205
ZW		 24216 /* DON'T add any new processors to this list -- we want the whole list
24217 to go away... Add them to the processors table instead. */
e74cfd16
PB		 24218 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
24219 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
24220 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
24221 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
24222 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
24223 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
24224 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
24225 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
24226 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
24227 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
24228 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
24229 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
24230 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
24231 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
24232 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
24233 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
24234 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
24235 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
24236 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
24237 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
24238 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
24239 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
24240 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
24241 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
24242 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
24243 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
24244 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
24245 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
24246 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
24247 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
24248 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
24249 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
24250 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
24251 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
24252 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
24253 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
24254 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
24255 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
24256 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
24257 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
24258 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
24259 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
24260 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
24261 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
24262 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
24263 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
24264 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24265 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24266 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24267 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
24268 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
24269 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
24270 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
24271 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
24272 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
24273 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
24274 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
24275 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
24276 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
24277 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
24278 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
24279 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
24280 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
24281 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
24282 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
24283 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
24284 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
24285 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
24286 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
24287 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 24288 N_("use -mcpu=strongarm110")},
e74cfd16 24289 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 24290 N_("use -mcpu=strongarm1100")},
e74cfd16 24291 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 24292 N_("use -mcpu=strongarm1110")},
e74cfd16
PB		 24293 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
24294 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
24295 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 24296
c19d1205 24297 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB		 24298 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
24299 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
24300 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
24301 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
24302 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
24303 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
24304 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
24305 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
24306 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
24307 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
24308 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
24309 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
24310 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
24311 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
24312 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
24313 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
24314 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
24315 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 24316
c19d1205 24317 /* Floating point variants -- don't add any more to this list either. */
e74cfd16
PB		 24318 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
24319 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
24320 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
24321 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 24322 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 24323
e74cfd16 24324 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 24325};
7ed4c4c5 24326
c19d1205 24327struct arm_cpu_option_table
7ed4c4c5 24328{
c19d1205 24329 char *name;
f3bad469 24330 size_t name_len;
e74cfd16 24331 const arm_feature_set value;
c19d1205
ZW		 24332 /* For some CPUs we assume an FPU unless the user explicitly sets
24333 -mfpu=... */
e74cfd16 24334 const arm_feature_set default_fpu;
ee065d83
PB		 24335 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24336 case. */
24337 const char *canonical_name;
c19d1205 24338};
7ed4c4c5 24339
c19d1205
ZW		 24340/* This list should, at a minimum, contain all the cpu names
24341 recognized by GCC. */
f3bad469 24342#define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
e74cfd16 24343static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 24344{
f3bad469
MGD		 24345 ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
24346 ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
24347 ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
24348 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
24349 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
24350 ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24351 ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24352 ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24353 ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24354 ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24355 ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24356 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24357 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24358 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24359 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24360 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
24361 ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24362 ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24363 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24364 ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24365 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24366 ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24367 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24368 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24369 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24370 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24371 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24372 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
24373 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24374 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24375 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24376 ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24377 ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24378 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24379 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24380 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24381 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24382 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24383 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24384 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
24385 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24386 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24387 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24388 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
24389 ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
24390 ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
c19d1205
ZW		 24391 /* For V5 or later processors we default to using VFP; but the user
24392 should really set the FPU type explicitly. */
f3bad469
MGD		 24393 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24394 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24395 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
24396 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
24397 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
24398 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24399 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
24400 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24401 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
24402 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
24403 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24404 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24405 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24406 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24407 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24408 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
24409 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
24410 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24411 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24412 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
24413 "ARM1026EJ-S"),
24414 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
24415 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24416 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24417 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24418 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24419 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
24420 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
24421 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
24422 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
24423 "ARM1136JF-S"),
24424 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
24425 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
24426 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
24427 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
24428 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
24429 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK, FPU_NONE, NULL),
24430 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK, FPU_ARCH_VFP_V2, NULL),
24431 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
24432 FPU_NONE, "Cortex-A5"),
c9fb6e58 24433 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
f3bad469
MGD		 24434 "Cortex-A7"),
24435 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
24436 ARM_FEATURE (0, FPU_VFP_V3
477330fc 24437 | FPU_NEON_EXT_V1),
f3bad469
MGD		 24438 "Cortex-A8"),
24439 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
24440 ARM_FEATURE (0, FPU_VFP_V3
477330fc 24441 | FPU_NEON_EXT_V1),
f3bad469 24442 "Cortex-A9"),
c9fb6e58 24443 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
63a4bc21 24444 "Cortex-A12"),
c9fb6e58 24445 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
f3bad469 24446 "Cortex-A15"),
d7adf960
KT		 24447 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
24448 "Cortex-A17"),
92eb40d9 24449 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
477330fc 24450 "Cortex-A53"),
92eb40d9 24451 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
477330fc 24452 "Cortex-A57"),
b19f47ad
JW		 24453 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24454 "Cortex-A72"),
f3bad469
MGD		 24455 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
24456 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
24457 "Cortex-R4F"),
24458 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
24459 FPU_NONE, "Cortex-R5"),
70a8bc5b 24460 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
24461 FPU_ARCH_VFP_V3D16,
24462 "Cortex-R7"),
a715796b 24463 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"),
f3bad469
MGD		 24464 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
24465 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
24466 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
24467 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
ce32bd10 24468 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
c19d1205 24469 /* ??? XSCALE is really an architecture. */
f3bad469 24470 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
c19d1205 24471 /* ??? iwmmxt is not a processor. */
f3bad469
MGD		 24472 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
24473 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
24474 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
c19d1205 24475 /* Maverick */
f3bad469 24476 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
da4339ed
NC		 24477 FPU_ARCH_MAVERICK, "ARM920T"),
24478 /* Marvell processors. */
4a81b02a 24479 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, 0),
477330fc 24480 FPU_ARCH_VFP_V3D16, NULL),
4347085a
NC		 24481 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP
24482 | ARM_EXT_SEC, 0),
24483 FPU_ARCH_NEON_VFP_V4, NULL),
ea0d6bb9
PT		 24484 /* APM X-Gene family. */
24485 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24486 "APM X-Gene 1"),
24487 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
24488 "APM X-Gene 2"),
da4339ed 24489
f3bad469 24490 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 24491};
f3bad469 24492#undef ARM_CPU_OPT
7ed4c4c5 24493
c19d1205 24494struct arm_arch_option_table
7ed4c4c5 24495{
c19d1205 24496 char *name;
f3bad469 24497 size_t name_len;
e74cfd16
PB		 24498 const arm_feature_set value;
24499 const arm_feature_set default_fpu;
c19d1205 24500};
7ed4c4c5 24501
c19d1205
ZW		 24502/* This list should, at a minimum, contain all the architecture names
24503 recognized by GCC. */
f3bad469 24504#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
e74cfd16 24505static const struct arm_arch_option_table arm_archs[] =
c19d1205 24506{
f3bad469
MGD		 24507 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
24508 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
24509 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
24510 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
24511 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
24512 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
24513 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
24514 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
24515 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
24516 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
24517 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
24518 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
24519 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
24520 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
24521 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP),
24522 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP),
24523 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP),
24524 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP),
24525 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP),
24526 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP),
24527 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP),
24528 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK, FPU_ARCH_VFP),
24529 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP),
24530 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP),
24531 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP),
24532 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP),
24533 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
24534 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
24535 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP),
c450d570
PB		 24536 /* The official spelling of the ARMv7 profile variants is the dashed form.
24537 Accept the non-dashed form for compatibility with old toolchains. */
f3bad469 24538 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP),
c9fb6e58 24539 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP),
f3bad469
MGD		 24540 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24541 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24542 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP),
24543 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP),
24544 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
24545 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP),
bca38921 24546 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
f3bad469
MGD		 24547 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
24548 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
24549 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
24550 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 24551};
f3bad469 24552#undef ARM_ARCH_OPT
7ed4c4c5 24553
69133863
MGD		 24554/* ISA extensions in the co-processor and main instruction set space. */
24555struct arm_option_extension_value_table
c19d1205
ZW		 24556{
24557 char *name;
f3bad469 24558 size_t name_len;
5a70a223
JB		 24559 const arm_feature_set merge_value;
24560 const arm_feature_set clear_value;
69133863 24561 const arm_feature_set allowed_archs;
c19d1205 24562};
7ed4c4c5 24563
69133863
MGD		 24564/* The following table must be in alphabetical order with a NULL last entry.
24565 */
5a70a223 24566#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
69133863 24567static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 24568{
5a70a223
JB		 24569 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE (0, CRC_EXT_ARMV8),
24570 ARM_FEATURE (ARM_EXT_V8, 0)),
bca38921 24571 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
5a70a223 24572 ARM_FEATURE (0, FPU_CRYPTO_ARMV8),
bca38921 24573 ARM_FEATURE (ARM_EXT_V8, 0)),
5a70a223 24574 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE (0, FPU_VFP_ARMV8),
bca38921 24575 ARM_FEATURE (ARM_EXT_V8, 0)),
f3bad469 24576 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
5a70a223 24577 ARM_FEATURE (ARM_EXT_ADIV | ARM_EXT_DIV, 0),
f3bad469 24578 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
5a70a223
JB		 24579 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT),
24580 ARM_FEATURE (0, ARM_CEXT_IWMMXT), ARM_ANY),
24581 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2),
24582 ARM_FEATURE (0, ARM_CEXT_IWMMXT2), ARM_ANY),
24583 ARM_EXT_OPT ("maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK),
24584 ARM_FEATURE (0, ARM_CEXT_MAVERICK), ARM_ANY),
f3bad469 24585 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP, 0),
5a70a223 24586 ARM_FEATURE (ARM_EXT_MP, 0),
f3bad469 24587 ARM_FEATURE (ARM_EXT_V7A | ARM_EXT_V7R, 0)),
bca38921 24588 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
5a70a223 24589 ARM_FEATURE(0, FPU_NEON_ARMV8),
bca38921 24590 ARM_FEATURE (ARM_EXT_V8, 0)),
f3bad469 24591 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS, 0),
5a70a223 24592 ARM_FEATURE (ARM_EXT_OS, 0),
f3bad469
MGD		 24593 ARM_FEATURE (ARM_EXT_V6M, 0)),
24594 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC, 0),
5a70a223 24595 ARM_FEATURE (ARM_EXT_SEC, 0),
f3bad469
MGD		 24596 ARM_FEATURE (ARM_EXT_V6K | ARM_EXT_V7A, 0)),
24597 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT | ARM_EXT_ADIV
24598 | ARM_EXT_DIV, 0),
5a70a223 24599 ARM_FEATURE (ARM_EXT_VIRT, 0),
f3bad469 24600 ARM_FEATURE (ARM_EXT_V7A, 0)),
5a70a223
JB		 24601 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE),
24602 ARM_FEATURE (0, ARM_CEXT_XSCALE), ARM_ANY),
24603 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE }
69133863 24604};
f3bad469 24605#undef ARM_EXT_OPT
69133863
MGD		 24606
24607/* ISA floating-point and Advanced SIMD extensions. */
24608struct arm_option_fpu_value_table
24609{
24610 char *name;
24611 const arm_feature_set value;
c19d1205 24612};
7ed4c4c5 24613
c19d1205
ZW		 24614/* This list should, at a minimum, contain all the fpu names
24615 recognized by GCC. */
69133863 24616static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW		 24617{
24618 {"softfpa", FPU_NONE},
24619 {"fpe", FPU_ARCH_FPE},
24620 {"fpe2", FPU_ARCH_FPE},
24621 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
24622 {"fpa", FPU_ARCH_FPA},
24623 {"fpa10", FPU_ARCH_FPA},
24624 {"fpa11", FPU_ARCH_FPA},
24625 {"arm7500fe", FPU_ARCH_FPA},
24626 {"softvfp", FPU_ARCH_VFP},
24627 {"softvfp+vfp", FPU_ARCH_VFP_V2},
24628 {"vfp", FPU_ARCH_VFP_V2},
24629 {"vfp9", FPU_ARCH_VFP_V2},
b1cc4aeb 24630 {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
c19d1205
ZW		 24631 {"vfp10", FPU_ARCH_VFP_V2},
24632 {"vfp10-r0", FPU_ARCH_VFP_V1},
24633 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB		 24634 {"vfpv2", FPU_ARCH_VFP_V2},
24635 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 24636 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 24637 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB		 24638 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
24639 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
24640 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW		 24641 {"arm1020t", FPU_ARCH_VFP_V1},
24642 {"arm1020e", FPU_ARCH_VFP_V2},
24643 {"arm1136jfs", FPU_ARCH_VFP_V2},
24644 {"arm1136jf-s", FPU_ARCH_VFP_V2},
24645 {"maverick", FPU_ARCH_MAVERICK},
5287ad62 24646 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 24647 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB		 24648 {"vfpv4", FPU_ARCH_VFP_V4},
24649 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 24650 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
a715796b
TG		 24651 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
24652 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
62f3b8c8 24653 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD		 24654 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
24655 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
24656 {"crypto-neon-fp-armv8",
24657 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
e74cfd16
PB		 24658 {NULL, ARM_ARCH_NONE}
24659};
24660
24661struct arm_option_value_table
24662{
24663 char *name;
24664 long value;
c19d1205 24665};
7ed4c4c5 24666
e74cfd16 24667static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW		 24668{
24669 {"hard", ARM_FLOAT_ABI_HARD},
24670 {"softfp", ARM_FLOAT_ABI_SOFTFP},
24671 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 24672 {NULL, 0}
c19d1205 24673};
7ed4c4c5 24674
c19d1205 24675#ifdef OBJ_ELF
3a4a14e9 24676/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 24677static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW		 24678{
24679 {"gnu", EF_ARM_EABI_UNKNOWN},
24680 {"4", EF_ARM_EABI_VER4},
3a4a14e9 24681 {"5", EF_ARM_EABI_VER5},
e74cfd16 24682 {NULL, 0}
c19d1205
ZW		 24683};
24684#endif
7ed4c4c5 24685
c19d1205
ZW		 24686struct arm_long_option_table
24687{
24688 char * option; /* Substring to match. */
24689 char * help; /* Help information. */
24690 int (* func) (char * subopt); /* Function to decode sub-option. */
24691 char * deprecated; /* If non-null, print this message. */
24692};
7ed4c4c5 24693
c921be7d 24694static bfd_boolean
f3bad469 24695arm_parse_extension (char *str, const arm_feature_set **opt_p)
7ed4c4c5 24696{
21d799b5
NC		 24697 arm_feature_set *ext_set = (arm_feature_set *)
24698 xmalloc (sizeof (arm_feature_set));
e74cfd16 24699
69133863 24700 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM		 24701 extensions being added before being removed. We achieve this by having
24702 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 24703 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 24704 or removing it (0) and only allowing it to change in the order
69133863
MGD		 24705 -1 -> 1 -> 0. */
24706 const struct arm_option_extension_value_table * opt = NULL;
24707 int adding_value = -1;
24708
e74cfd16
PB		 24709 /* Copy the feature set, so that we can modify it. */
24710 *ext_set = **opt_p;
24711 *opt_p = ext_set;
24712
c19d1205 24713 while (str != NULL && *str != 0)
7ed4c4c5 24714 {
f3bad469
MGD		 24715 char *ext;
24716 size_t len;
7ed4c4c5 24717
c19d1205
ZW		 24718 if (*str != '+')
24719 {
24720 as_bad (_("invalid architectural extension"));
c921be7d 24721 return FALSE;
c19d1205 24722 }
7ed4c4c5 24723
c19d1205
ZW		 24724 str++;
24725 ext = strchr (str, '+');
7ed4c4c5 24726
c19d1205 24727 if (ext != NULL)
f3bad469 24728 len = ext - str;
c19d1205 24729 else
f3bad469 24730 len = strlen (str);
7ed4c4c5 24731
f3bad469 24732 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD		 24733 {
24734 if (adding_value != 0)
24735 {
24736 adding_value = 0;
24737 opt = arm_extensions;
24738 }
24739
f3bad469 24740 len -= 2;
69133863
MGD		 24741 str += 2;
24742 }
f3bad469 24743 else if (len > 0)
69133863
MGD		 24744 {
24745 if (adding_value == -1)
24746 {
24747 adding_value = 1;
24748 opt = arm_extensions;
24749 }
24750 else if (adding_value != 1)
24751 {
24752 as_bad (_("must specify extensions to add before specifying "
24753 "those to remove"));
24754 return FALSE;
24755 }
24756 }
24757
f3bad469 24758 if (len == 0)
c19d1205
ZW		 24759 {
24760 as_bad (_("missing architectural extension"));
c921be7d 24761 return FALSE;
c19d1205 24762 }
7ed4c4c5 24763
69133863
MGD		 24764 gas_assert (adding_value != -1);
24765 gas_assert (opt != NULL);
24766
24767 /* Scan over the options table trying to find an exact match. */
24768 for (; opt->name != NULL; opt++)
f3bad469 24769 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24770 {
69133863
MGD		 24771 /* Check we can apply the extension to this architecture. */
24772 if (!ARM_CPU_HAS_FEATURE (*ext_set, opt->allowed_archs))
24773 {
24774 as_bad (_("extension does not apply to the base architecture"));
24775 return FALSE;
24776 }
24777
24778 /* Add or remove the extension. */
24779 if (adding_value)
5a70a223 24780 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
69133863 24781 else
5a70a223 24782 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
69133863 24783
c19d1205
ZW		 24784 break;
24785 }
7ed4c4c5 24786
c19d1205
ZW		 24787 if (opt->name == NULL)
24788 {
69133863
MGD		 24789 /* Did we fail to find an extension because it wasn't specified in
24790 alphabetical order, or because it does not exist? */
24791
24792 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 24793 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD		 24794 break;
24795
24796 if (opt->name == NULL)
24797 as_bad (_("unknown architectural extension `%s'"), str);
24798 else
24799 as_bad (_("architectural extensions must be specified in "
24800 "alphabetical order"));
24801
c921be7d 24802 return FALSE;
c19d1205 24803 }
69133863
MGD		 24804 else
24805 {
24806 /* We should skip the extension we've just matched the next time
24807 round. */
24808 opt++;
24809 }
7ed4c4c5 24810
c19d1205
ZW		 24811 str = ext;
24812 };
7ed4c4c5 24813
c921be7d 24814 return TRUE;
c19d1205 24815}
7ed4c4c5 24816
c921be7d 24817static bfd_boolean
f3bad469 24818arm_parse_cpu (char *str)
7ed4c4c5 24819{
f3bad469
MGD		 24820 const struct arm_cpu_option_table *opt;
24821 char *ext = strchr (str, '+');
24822 size_t len;
7ed4c4c5 24823
c19d1205 24824 if (ext != NULL)
f3bad469 24825 len = ext - str;
7ed4c4c5 24826 else
f3bad469 24827 len = strlen (str);
7ed4c4c5 24828
f3bad469 24829 if (len == 0)
7ed4c4c5 24830 {
c19d1205 24831 as_bad (_("missing cpu name `%s'"), str);
c921be7d 24832 return FALSE;
7ed4c4c5
NC		 24833 }
24834
c19d1205 24835 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 24836 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24837 {
e74cfd16
PB		 24838 mcpu_cpu_opt = &opt->value;
24839 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 24840 if (opt->canonical_name)
5f4273c7 24841 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 24842 else
24843 {
f3bad469 24844 size_t i;
c921be7d 24845
f3bad469 24846 for (i = 0; i < len; i++)
ee065d83
PB		 24847 selected_cpu_name[i] = TOUPPER (opt->name[i]);
24848 selected_cpu_name[i] = 0;
24849 }
7ed4c4c5 24850
c19d1205
ZW		 24851 if (ext != NULL)
24852 return arm_parse_extension (ext, &mcpu_cpu_opt);
7ed4c4c5 24853
c921be7d 24854 return TRUE;
c19d1205 24855 }
7ed4c4c5 24856
c19d1205 24857 as_bad (_("unknown cpu `%s'"), str);
c921be7d 24858 return FALSE;
7ed4c4c5
NC		 24859}
24860
c921be7d 24861static bfd_boolean
f3bad469 24862arm_parse_arch (char *str)
7ed4c4c5 24863{
e74cfd16 24864 const struct arm_arch_option_table *opt;
c19d1205 24865 char *ext = strchr (str, '+');
f3bad469 24866 size_t len;
7ed4c4c5 24867
c19d1205 24868 if (ext != NULL)
f3bad469 24869 len = ext - str;
7ed4c4c5 24870 else
f3bad469 24871 len = strlen (str);
7ed4c4c5 24872
f3bad469 24873 if (len == 0)
7ed4c4c5 24874 {
c19d1205 24875 as_bad (_("missing architecture name `%s'"), str);
c921be7d 24876 return FALSE;
7ed4c4c5
NC		 24877 }
24878
c19d1205 24879 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 24880 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 24881 {
e74cfd16
PB		 24882 march_cpu_opt = &opt->value;
24883 march_fpu_opt = &opt->default_fpu;
5f4273c7 24884 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 24885
c19d1205
ZW		 24886 if (ext != NULL)
24887 return arm_parse_extension (ext, &march_cpu_opt);
7ed4c4c5 24888
c921be7d 24889 return TRUE;
c19d1205
ZW		 24890 }
24891
24892 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 24893 return FALSE;
7ed4c4c5 24894}
eb043451 24895
c921be7d 24896static bfd_boolean
c19d1205
ZW		 24897arm_parse_fpu (char * str)
24898{
69133863 24899 const struct arm_option_fpu_value_table * opt;
b99bd4ef 24900
c19d1205
ZW		 24901 for (opt = arm_fpus; opt->name != NULL; opt++)
24902 if (streq (opt->name, str))
24903 {
e74cfd16 24904 mfpu_opt = &opt->value;
c921be7d 24905 return TRUE;
c19d1205 24906 }
b99bd4ef 24907
c19d1205 24908 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 24909 return FALSE;
c19d1205
ZW		 24910}
24911
c921be7d 24912static bfd_boolean
c19d1205 24913arm_parse_float_abi (char * str)
b99bd4ef 24914{
e74cfd16 24915 const struct arm_option_value_table * opt;
b99bd4ef 24916
c19d1205
ZW		 24917 for (opt = arm_float_abis; opt->name != NULL; opt++)
24918 if (streq (opt->name, str))
24919 {
24920 mfloat_abi_opt = opt->value;
c921be7d 24921 return TRUE;
c19d1205 24922 }
cc8a6dd0 24923
c19d1205 24924 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 24925 return FALSE;
c19d1205 24926}
b99bd4ef 24927
c19d1205 24928#ifdef OBJ_ELF
c921be7d 24929static bfd_boolean
c19d1205
ZW		 24930arm_parse_eabi (char * str)
24931{
e74cfd16 24932 const struct arm_option_value_table *opt;
cc8a6dd0 24933
c19d1205
ZW		 24934 for (opt = arm_eabis; opt->name != NULL; opt++)
24935 if (streq (opt->name, str))
24936 {
24937 meabi_flags = opt->value;
c921be7d 24938 return TRUE;
c19d1205
ZW		 24939 }
24940 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 24941 return FALSE;
c19d1205
ZW		 24942}
24943#endif
cc8a6dd0 24944
c921be7d 24945static bfd_boolean
e07e6e58
NC		 24946arm_parse_it_mode (char * str)
24947{
c921be7d 24948 bfd_boolean ret = TRUE;
e07e6e58
NC		 24949
24950 if (streq ("arm", str))
24951 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
24952 else if (streq ("thumb", str))
24953 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
24954 else if (streq ("always", str))
24955 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
24956 else if (streq ("never", str))
24957 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
24958 else
24959 {
24960 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 24961 "arm, thumb, always, or never."), str);
c921be7d 24962 ret = FALSE;
e07e6e58
NC		 24963 }
24964
24965 return ret;
24966}
24967
2e6976a8
DG		 24968static bfd_boolean
24969arm_ccs_mode (char * unused ATTRIBUTE_UNUSED)
24970{
24971 codecomposer_syntax = TRUE;
24972 arm_comment_chars[0] = ';';
24973 arm_line_separator_chars[0] = 0;
24974 return TRUE;
24975}
24976
c19d1205
ZW		 24977struct arm_long_option_table arm_long_opts[] =
24978{
24979 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24980 arm_parse_cpu, NULL},
24981 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24982 arm_parse_arch, NULL},
24983 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24984 arm_parse_fpu, NULL},
24985 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24986 arm_parse_float_abi, NULL},
24987#ifdef OBJ_ELF
7fac0536 24988 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW		 24989 arm_parse_eabi, NULL},
24990#endif
e07e6e58
NC		 24991 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24992 arm_parse_it_mode, NULL},
2e6976a8
DG		 24993 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24994 arm_ccs_mode, NULL},
c19d1205
ZW		 24995 {NULL, NULL, 0, NULL}
24996};
cc8a6dd0 24997
c19d1205
ZW		 24998int
24999md_parse_option (int c, char * arg)
25000{
25001 struct arm_option_table *opt;
e74cfd16 25002 const struct arm_legacy_option_table *fopt;
c19d1205 25003 struct arm_long_option_table *lopt;
b99bd4ef 25004
c19d1205 25005 switch (c)
b99bd4ef 25006 {
c19d1205
ZW		 25007#ifdef OPTION_EB
25008 case OPTION_EB:
25009 target_big_endian = 1;
25010 break;
25011#endif
cc8a6dd0 25012
c19d1205
ZW		 25013#ifdef OPTION_EL
25014 case OPTION_EL:
25015 target_big_endian = 0;
25016 break;
25017#endif
b99bd4ef 25018
845b51d6
PB		 25019 case OPTION_FIX_V4BX:
25020 fix_v4bx = TRUE;
25021 break;
25022
c19d1205
ZW		 25023 case 'a':
25024 /* Listing option. Just ignore these, we don't support additional
25025 ones. */
25026 return 0;
b99bd4ef 25027
c19d1205
ZW		 25028 default:
25029 for (opt = arm_opts; opt->option != NULL; opt++)
25030 {
25031 if (c == opt->option[0]
25032 && ((arg == NULL && opt->option[1] == 0)
25033 || streq (arg, opt->option + 1)))
25034 {
c19d1205 25035 /* If the option is deprecated, tell the user. */
278df34e 25036 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW		 25037 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25038 arg ? arg : "", _(opt->deprecated));
b99bd4ef 25039
c19d1205
ZW		 25040 if (opt->var != NULL)
25041 *opt->var = opt->value;
cc8a6dd0 25042
c19d1205
ZW		 25043 return 1;
25044 }
25045 }
b99bd4ef 25046
e74cfd16
PB		 25047 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
25048 {
25049 if (c == fopt->option[0]
25050 && ((arg == NULL && fopt->option[1] == 0)
25051 || streq (arg, fopt->option + 1)))
25052 {
e74cfd16 25053 /* If the option is deprecated, tell the user. */
278df34e 25054 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB		 25055 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
25056 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB		 25057
25058 if (fopt->var != NULL)
25059 *fopt->var = &fopt->value;
25060
25061 return 1;
25062 }
25063 }
25064
c19d1205
ZW		 25065 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25066 {
25067 /* These options are expected to have an argument. */
25068 if (c == lopt->option[0]
25069 && arg != NULL
25070 && strncmp (arg, lopt->option + 1,
25071 strlen (lopt->option + 1)) == 0)
25072 {
c19d1205 25073 /* If the option is deprecated, tell the user. */
278df34e 25074 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW		 25075 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
25076 _(lopt->deprecated));
b99bd4ef 25077
c19d1205
ZW		 25078 /* Call the sup-option parser. */
25079 return lopt->func (arg + strlen (lopt->option) - 1);
25080 }
25081 }
a737bd4d 25082
c19d1205
ZW		 25083 return 0;
25084 }
a394c00f 25085
c19d1205
ZW		 25086 return 1;
25087}
a394c00f 25088
c19d1205
ZW		 25089void
25090md_show_usage (FILE * fp)
a394c00f 25091{
c19d1205
ZW		 25092 struct arm_option_table *opt;
25093 struct arm_long_option_table *lopt;
a394c00f 25094
c19d1205 25095 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 25096
c19d1205
ZW		 25097 for (opt = arm_opts; opt->option != NULL; opt++)
25098 if (opt->help != NULL)
25099 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 25100
c19d1205
ZW		 25101 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
25102 if (lopt->help != NULL)
25103 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 25104
c19d1205
ZW		 25105#ifdef OPTION_EB
25106 fprintf (fp, _("\
25107 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC		 25108#endif
25109
c19d1205
ZW		 25110#ifdef OPTION_EL
25111 fprintf (fp, _("\
25112 -EL assemble code for a little-endian cpu\n"));
a737bd4d 25113#endif
845b51d6
PB		 25114
25115 fprintf (fp, _("\
25116 --fix-v4bx Allow BX in ARMv4 code\n"));
c19d1205 25117}
ee065d83
PB		 25118
25119
25120#ifdef OBJ_ELF
62b3e311
PB		 25121typedef struct
25122{
25123 int val;
25124 arm_feature_set flags;
25125} cpu_arch_ver_table;
25126
25127/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
25128 least features first. */
25129static const cpu_arch_ver_table cpu_arch_ver[] =
25130{
25131 {1, ARM_ARCH_V4},
25132 {2, ARM_ARCH_V4T},
25133 {3, ARM_ARCH_V5},
ee3c0378 25134 {3, ARM_ARCH_V5T},
62b3e311
PB		 25135 {4, ARM_ARCH_V5TE},
25136 {5, ARM_ARCH_V5TEJ},
25137 {6, ARM_ARCH_V6},
7e806470 25138 {9, ARM_ARCH_V6K},
f4c65163 25139 {7, ARM_ARCH_V6Z},
91e22acd 25140 {11, ARM_ARCH_V6M},
b2a5fbdc 25141 {12, ARM_ARCH_V6SM},
7e806470 25142 {8, ARM_ARCH_V6T2},
c9fb6e58 25143 {10, ARM_ARCH_V7VE},
62b3e311
PB		 25144 {10, ARM_ARCH_V7R},
25145 {10, ARM_ARCH_V7M},
bca38921 25146 {14, ARM_ARCH_V8A},
62b3e311
PB		 25147 {0, ARM_ARCH_NONE}
25148};
25149
ee3c0378
AS		 25150/* Set an attribute if it has not already been set by the user. */
25151static void
25152aeabi_set_attribute_int (int tag, int value)
25153{
25154 if (tag < 1
25155 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
25156 || !attributes_set_explicitly[tag])
25157 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
25158}
25159
25160static void
25161aeabi_set_attribute_string (int tag, const char *value)
25162{
25163 if (tag < 1
25164 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
25165 || !attributes_set_explicitly[tag])
25166 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
25167}
25168
ee065d83 25169/* Set the public EABI object attributes. */
3cfdb781 25170void
ee065d83
PB		 25171aeabi_set_public_attributes (void)
25172{
25173 int arch;
69239280 25174 char profile;
90ec0d68 25175 int virt_sec = 0;
bca38921 25176 int fp16_optional = 0;
e74cfd16 25177 arm_feature_set flags;
62b3e311
PB		 25178 arm_feature_set tmp;
25179 const cpu_arch_ver_table *p;
ee065d83
PB		 25180
25181 /* Choose the architecture based on the capabilities of the requested cpu
25182 (if any) and/or the instructions actually used. */
e74cfd16
PB		 25183 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
25184 ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
25185 ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
ddd7f988
RE		 25186
25187 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
25188 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
25189
25190 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
25191 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
25192
7f78eb34
JW		 25193 selected_cpu = flags;
25194
ddd7f988 25195 /* Allow the user to override the reported architecture. */
7a1d4c38
PB		 25196 if (object_arch)
25197 {
25198 ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
25199 ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
25200 }
25201
251665fc
MGD		 25202 /* We need to make sure that the attributes do not identify us as v6S-M
25203 when the only v6S-M feature in use is the Operating System Extensions. */
25204 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
25205 if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
477330fc 25206 ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
251665fc 25207
62b3e311
PB		 25208 tmp = flags;
25209 arch = 0;
25210 for (p = cpu_arch_ver; p->val; p++)
25211 {
25212 if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
25213 {
25214 arch = p->val;
25215 ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
25216 }
25217 }
ee065d83 25218
9e3c6df6
PB		 25219 /* The table lookup above finds the last architecture to contribute
25220 a new feature. Unfortunately, Tag13 is a subset of the union of
25221 v6T2 and v7-M, so it is never seen as contributing a new feature.
25222 We can not search for the last entry which is entirely used,
25223 because if no CPU is specified we build up only those flags
25224 actually used. Perhaps we should separate out the specified
25225 and implicit cases. Avoid taking this path for -march=all by
25226 checking for contradictory v7-A / v7-M features. */
25227 if (arch == 10
25228 && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
25229 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
25230 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
25231 arch = 13;
25232
ee065d83
PB		 25233 /* Tag_CPU_name. */
25234 if (selected_cpu_name[0])
25235 {
91d6fa6a 25236 char *q;
ee065d83 25237
91d6fa6a
NC		 25238 q = selected_cpu_name;
25239 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB		 25240 {
25241 int i;
5f4273c7 25242
91d6fa6a
NC		 25243 q += 4;
25244 for (i = 0; q[i]; i++)
25245 q[i] = TOUPPER (q[i]);
ee065d83 25246 }
91d6fa6a 25247 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 25248 }
62f3b8c8 25249
ee065d83 25250 /* Tag_CPU_arch. */
ee3c0378 25251 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 25252
62b3e311
PB		 25253 /* Tag_CPU_arch_profile. */
25254 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a))
69239280 25255 profile = 'A';
62b3e311 25256 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
69239280 25257 profile = 'R';
7e806470 25258 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
69239280
MGD		 25259 profile = 'M';
25260 else
25261 profile = '\0';
25262
25263 if (profile != '\0')
25264 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 25265
ee065d83 25266 /* Tag_ARM_ISA_use. */
ee3c0378
AS		 25267 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
25268 || arch == 0)
25269 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 25270
ee065d83 25271 /* Tag_THUMB_ISA_use. */
ee3c0378
AS		 25272 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
25273 || arch == 0)
25274 aeabi_set_attribute_int (Tag_THUMB_ISA_use,
25275 ARM_CPU_HAS_FEATURE (flags, arm_arch_t2) ? 2 : 1);
62f3b8c8 25276
ee065d83 25277 /* Tag_VFP_arch. */
a715796b
TG		 25278 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
25279 aeabi_set_attribute_int (Tag_VFP_arch,
25280 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
25281 ? 7 : 8);
bca38921 25282 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB		 25283 aeabi_set_attribute_int (Tag_VFP_arch,
25284 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
25285 ? 5 : 6);
25286 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD		 25287 {
25288 fp16_optional = 1;
25289 aeabi_set_attribute_int (Tag_VFP_arch, 3);
25290 }
ada65aa3 25291 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD		 25292 {
25293 aeabi_set_attribute_int (Tag_VFP_arch, 4);
25294 fp16_optional = 1;
25295 }
ee3c0378
AS		 25296 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
25297 aeabi_set_attribute_int (Tag_VFP_arch, 2);
25298 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 25299 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 25300 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 25301
4547cb56
NC		 25302 /* Tag_ABI_HardFP_use. */
25303 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
25304 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
25305 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
25306
ee065d83 25307 /* Tag_WMMX_arch. */
ee3c0378
AS		 25308 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
25309 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
25310 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
25311 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 25312
ee3c0378 25313 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
bca38921
MGD		 25314 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
25315 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
25316 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
25317 {
25318 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
25319 {
25320 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
25321 }
25322 else
25323 {
25324 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
25325 fp16_optional = 1;
25326 }
25327 }
fa94de6b 25328
ee3c0378 25329 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 25330 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 25331 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 25332
69239280
MGD		 25333 /* Tag_DIV_use.
25334
25335 We set Tag_DIV_use to two when integer divide instructions have been used
25336 in ARM state, or when Thumb integer divide instructions have been used,
25337 but we have no architecture profile set, nor have we any ARM instructions.
25338
bca38921
MGD		 25339 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25340 architecture.
25341
69239280 25342 For new architectures we will have to check these tests. */
bca38921
MGD		 25343 gas_assert (arch <= TAG_CPU_ARCH_V8);
25344 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8))
25345 aeabi_set_attribute_int (Tag_DIV_use, 0);
25346 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
25347 || (profile == '\0'
25348 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
25349 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 25350 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD		 25351
25352 /* Tag_MP_extension_use. */
25353 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
25354 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD		 25355
25356 /* Tag Virtualization_use. */
25357 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD		 25358 virt_sec |= 1;
25359 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
25360 virt_sec |= 2;
25361 if (virt_sec != 0)
25362 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
ee065d83
PB		 25363}
25364
104d59d1 25365/* Add the default contents for the .ARM.attributes section. */
ee065d83
PB		 25366void
25367arm_md_end (void)
25368{
ee065d83
PB		 25369 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
25370 return;
25371
25372 aeabi_set_public_attributes ();
ee065d83 25373}
8463be01 25374#endif /* OBJ_ELF */
ee065d83
PB		 25375
25376
25377/* Parse a .cpu directive. */
25378
25379static void
25380s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
25381{
e74cfd16 25382 const struct arm_cpu_option_table *opt;
ee065d83
PB		 25383 char *name;
25384 char saved_char;
25385
25386 name = input_line_pointer;
5f4273c7 25387 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25388 input_line_pointer++;
25389 saved_char = *input_line_pointer;
25390 *input_line_pointer = 0;
25391
25392 /* Skip the first "all" entry. */
25393 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
25394 if (streq (opt->name, name))
25395 {
e74cfd16
PB		 25396 mcpu_cpu_opt = &opt->value;
25397 selected_cpu = opt->value;
ee065d83 25398 if (opt->canonical_name)
5f4273c7 25399 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 25400 else
25401 {
25402 int i;
25403 for (i = 0; opt->name[i]; i++)
25404 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 25405
ee065d83
PB		 25406 selected_cpu_name[i] = 0;
25407 }
e74cfd16 25408 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25409 *input_line_pointer = saved_char;
25410 demand_empty_rest_of_line ();
25411 return;
25412 }
25413 as_bad (_("unknown cpu `%s'"), name);
25414 *input_line_pointer = saved_char;
25415 ignore_rest_of_line ();
25416}
25417
25418
25419/* Parse a .arch directive. */
25420
25421static void
25422s_arm_arch (int ignored ATTRIBUTE_UNUSED)
25423{
e74cfd16 25424 const struct arm_arch_option_table *opt;
ee065d83
PB		 25425 char saved_char;
25426 char *name;
25427
25428 name = input_line_pointer;
5f4273c7 25429 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25430 input_line_pointer++;
25431 saved_char = *input_line_pointer;
25432 *input_line_pointer = 0;
25433
25434 /* Skip the first "all" entry. */
25435 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25436 if (streq (opt->name, name))
25437 {
e74cfd16
PB		 25438 mcpu_cpu_opt = &opt->value;
25439 selected_cpu = opt->value;
5f4273c7 25440 strcpy (selected_cpu_name, opt->name);
e74cfd16 25441 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25442 *input_line_pointer = saved_char;
25443 demand_empty_rest_of_line ();
25444 return;
25445 }
25446
25447 as_bad (_("unknown architecture `%s'\n"), name);
25448 *input_line_pointer = saved_char;
25449 ignore_rest_of_line ();
25450}
25451
25452
7a1d4c38
PB		 25453/* Parse a .object_arch directive. */
25454
25455static void
25456s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
25457{
25458 const struct arm_arch_option_table *opt;
25459 char saved_char;
25460 char *name;
25461
25462 name = input_line_pointer;
5f4273c7 25463 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB		 25464 input_line_pointer++;
25465 saved_char = *input_line_pointer;
25466 *input_line_pointer = 0;
25467
25468 /* Skip the first "all" entry. */
25469 for (opt = arm_archs + 1; opt->name != NULL; opt++)
25470 if (streq (opt->name, name))
25471 {
25472 object_arch = &opt->value;
25473 *input_line_pointer = saved_char;
25474 demand_empty_rest_of_line ();
25475 return;
25476 }
25477
25478 as_bad (_("unknown architecture `%s'\n"), name);
25479 *input_line_pointer = saved_char;
25480 ignore_rest_of_line ();
25481}
25482
69133863
MGD		 25483/* Parse a .arch_extension directive. */
25484
25485static void
25486s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
25487{
25488 const struct arm_option_extension_value_table *opt;
25489 char saved_char;
25490 char *name;
25491 int adding_value = 1;
25492
25493 name = input_line_pointer;
25494 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
25495 input_line_pointer++;
25496 saved_char = *input_line_pointer;
25497 *input_line_pointer = 0;
25498
25499 if (strlen (name) >= 2
25500 && strncmp (name, "no", 2) == 0)
25501 {
25502 adding_value = 0;
25503 name += 2;
25504 }
25505
25506 for (opt = arm_extensions; opt->name != NULL; opt++)
25507 if (streq (opt->name, name))
25508 {
25509 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt, opt->allowed_archs))
25510 {
25511 as_bad (_("architectural extension `%s' is not allowed for the "
25512 "current base architecture"), name);
25513 break;
25514 }
25515
25516 if (adding_value)
5a70a223
JB		 25517 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
25518 opt->merge_value);
69133863 25519 else
5a70a223 25520 ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
69133863
MGD		 25521
25522 mcpu_cpu_opt = &selected_cpu;
25523 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
25524 *input_line_pointer = saved_char;
25525 demand_empty_rest_of_line ();
25526 return;
25527 }
25528
25529 if (opt->name == NULL)
e673710a 25530 as_bad (_("unknown architecture extension `%s'\n"), name);
69133863
MGD		 25531
25532 *input_line_pointer = saved_char;
25533 ignore_rest_of_line ();
25534}
25535
ee065d83
PB		 25536/* Parse a .fpu directive. */
25537
25538static void
25539s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
25540{
69133863 25541 const struct arm_option_fpu_value_table *opt;
ee065d83
PB		 25542 char saved_char;
25543 char *name;
25544
25545 name = input_line_pointer;
5f4273c7 25546 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 25547 input_line_pointer++;
25548 saved_char = *input_line_pointer;
25549 *input_line_pointer = 0;
5f4273c7 25550
ee065d83
PB		 25551 for (opt = arm_fpus; opt->name != NULL; opt++)
25552 if (streq (opt->name, name))
25553 {
e74cfd16
PB		 25554 mfpu_opt = &opt->value;
25555 ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
ee065d83
PB		 25556 *input_line_pointer = saved_char;
25557 demand_empty_rest_of_line ();
25558 return;
25559 }
25560
25561 as_bad (_("unknown floating point format `%s'\n"), name);
25562 *input_line_pointer = saved_char;
25563 ignore_rest_of_line ();
25564}
ee065d83 25565
794ba86a 25566/* Copy symbol information. */
f31fef98 25567
794ba86a
DJ		 25568void
25569arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
25570{
25571 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
25572}
e04befd0 25573
f31fef98 25574#ifdef OBJ_ELF
e04befd0
AS		 25575/* Given a symbolic attribute NAME, return the proper integer value.
25576 Returns -1 if the attribute is not known. */
f31fef98 25577
e04befd0
AS		 25578int
25579arm_convert_symbolic_attribute (const char *name)
25580{
f31fef98
NC		 25581 static const struct
25582 {
25583 const char * name;
25584 const int tag;
25585 }
25586 attribute_table[] =
25587 {
25588 /* When you modify this table you should
25589 also modify the list in doc/c-arm.texi. */
e04befd0 25590#define T(tag) {#tag, tag}
f31fef98
NC		 25591 T (Tag_CPU_raw_name),
25592 T (Tag_CPU_name),
25593 T (Tag_CPU_arch),
25594 T (Tag_CPU_arch_profile),
25595 T (Tag_ARM_ISA_use),
25596 T (Tag_THUMB_ISA_use),
75375b3e 25597 T (Tag_FP_arch),
f31fef98
NC		 25598 T (Tag_VFP_arch),
25599 T (Tag_WMMX_arch),
25600 T (Tag_Advanced_SIMD_arch),
25601 T (Tag_PCS_config),
25602 T (Tag_ABI_PCS_R9_use),
25603 T (Tag_ABI_PCS_RW_data),
25604 T (Tag_ABI_PCS_RO_data),
25605 T (Tag_ABI_PCS_GOT_use),
25606 T (Tag_ABI_PCS_wchar_t),
25607 T (Tag_ABI_FP_rounding),
25608 T (Tag_ABI_FP_denormal),
25609 T (Tag_ABI_FP_exceptions),
25610 T (Tag_ABI_FP_user_exceptions),
25611 T (Tag_ABI_FP_number_model),
75375b3e 25612 T (Tag_ABI_align_needed),
f31fef98 25613 T (Tag_ABI_align8_needed),
75375b3e 25614 T (Tag_ABI_align_preserved),
f31fef98
NC		 25615 T (Tag_ABI_align8_preserved),
25616 T (Tag_ABI_enum_size),
25617 T (Tag_ABI_HardFP_use),
25618 T (Tag_ABI_VFP_args),
25619 T (Tag_ABI_WMMX_args),
25620 T (Tag_ABI_optimization_goals),
25621 T (Tag_ABI_FP_optimization_goals),
25622 T (Tag_compatibility),
25623 T (Tag_CPU_unaligned_access),
75375b3e 25624 T (Tag_FP_HP_extension),
f31fef98
NC		 25625 T (Tag_VFP_HP_extension),
25626 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD		 25627 T (Tag_MPextension_use),
25628 T (Tag_DIV_use),
f31fef98
NC		 25629 T (Tag_nodefaults),
25630 T (Tag_also_compatible_with),
25631 T (Tag_conformance),
25632 T (Tag_T2EE_use),
25633 T (Tag_Virtualization_use),
cd21e546 25634 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 25635#undef T
f31fef98 25636 };
e04befd0
AS		 25637 unsigned int i;
25638
25639 if (name == NULL)
25640 return -1;
25641
f31fef98 25642 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 25643 if (streq (name, attribute_table[i].name))
e04befd0
AS		 25644 return attribute_table[i].tag;
25645
25646 return -1;
25647}
267bf995
RR		 25648
25649
93ef582d
NC		 25650/* Apply sym value for relocations only in the case that they are for
25651 local symbols in the same segment as the fixup and you have the
25652 respective architectural feature for blx and simple switches. */
267bf995 25653int
93ef582d 25654arm_apply_sym_value (struct fix * fixP, segT this_seg)
267bf995
RR		 25655{
25656 if (fixP->fx_addsy
25657 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
93ef582d
NC		 25658 /* PR 17444: If the local symbol is in a different section then a reloc
25659 will always be generated for it, so applying the symbol value now
25660 will result in a double offset being stored in the relocation. */
25661 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
34e77a92 25662 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR		 25663 {
25664 switch (fixP->fx_r_type)
25665 {
25666 case BFD_RELOC_ARM_PCREL_BLX:
25667 case BFD_RELOC_THUMB_PCREL_BRANCH23:
25668 if (ARM_IS_FUNC (fixP->fx_addsy))
25669 return 1;
25670 break;
25671
25672 case BFD_RELOC_ARM_PCREL_CALL:
25673 case BFD_RELOC_THUMB_PCREL_BLX:
25674 if (THUMB_IS_FUNC (fixP->fx_addsy))
93ef582d 25675 return 1;
267bf995
RR		 25676 break;
25677
25678 default:
25679 break;
25680 }
25681
25682 }
25683 return 0;
25684}
f31fef98 25685#endif /* OBJ_ELF */
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