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[gdb/testsuite] Fix clone-new-thread-event.c with glibc 2.30
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7531c613
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
4 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
5 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
6 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
7 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
8 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
9 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
10 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
11 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
12 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
13 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
14 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
15 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
16 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
17 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
18 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
19 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
20 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
21 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
22 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
23 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
24 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
25 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
26 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
27 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
28 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
29 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
30 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
31 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
32 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
33 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
34 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
35 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
36 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
37 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
38 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
39 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
40 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
41 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
42 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
43 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
44 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
45 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
46 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
47 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
48 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
49 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
50 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
51 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
52 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
53 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
54 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
55 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
56 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
57 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
58 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
59 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
60 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
61 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
62 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
63 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
64 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
65 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
66 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
67 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
68 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
69 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
70 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
71 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
72 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
73 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
74 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
75 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
76 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
77 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
78 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
79 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
80 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
81 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
82 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
83 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
84 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
85 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
86 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
87 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
88 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
89 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
90 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
91 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
92 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
93 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
94 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
95 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
96 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
97 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
98 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
99 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
100 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
101 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
102 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
103 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
104 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
105 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
106 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
107 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
108 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
109 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
110 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
111 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
112 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
113 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
114 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
115 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
116 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
117 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
118 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
119 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
120 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
121 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
122 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
123 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
124 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
125 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
126 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
127 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
128 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
129 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
130 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
131 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
132 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
133 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
134 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
135 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
136 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
137 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
138 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
139 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
140 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
141 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
142 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
143 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
144 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
145 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
146 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
147 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
148 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
149 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
150 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
151 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
152 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
153 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
154 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
155 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
156 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
157 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
158 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
159 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
160 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
161 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
162 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
163 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
164 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
165 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
166 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
167 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
168 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
169 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
170 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
171 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
172 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
173 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
174 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
175 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
176 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
177 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
178 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
179 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
180 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
181 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
182 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
183 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
184 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
185 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
186 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
187 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
188 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
189 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
190 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
191 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
192 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
193 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
194 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
195 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
196 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
197 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
198 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
199 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
200 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
201 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
202 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
203 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
204 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
205 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
206 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
207 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
208 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
209 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
210 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
211 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
212 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
213 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
214 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
215 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
216 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
217 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
218 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
219 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
220 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
221 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
222 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
223 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
224 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
225 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
226 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
227 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
228 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
229 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
230 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
231 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
232 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
233 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
234 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
235 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
236 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
237 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
238 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
239 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
240 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
241 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
242 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
243 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
244 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
245 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
246 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
247 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
248 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
249 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
250 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
251 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
252 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
253 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
254 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
255 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
256 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
257 EVEX_W_0F3A72_P_2): Rename to ...
258 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
259 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
260 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
261 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
262 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
263 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
264 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
265 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
266 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
267 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
268 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
269 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
270 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
271 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
272 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
273 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
274 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
275 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
276 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
277 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
278 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
279 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
280 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
281 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
282 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
283 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
284 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
285 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
286 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
287 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
288 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
289 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
290 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
291 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
292 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
293 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
294 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
295 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
296 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
297 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
298 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
299 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
300 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
301 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
302 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
303 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
304 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
305 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
306 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
307 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
308 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
309 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
310 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
311 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
312 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
313 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
314 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
315 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
316 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
317 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
318 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
319 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
320 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
321 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
322 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
323 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
324 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
325 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
326 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
327 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
328 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
329 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
330 respectively.
331 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
332 vex_w_table, mod_table): Replace / remove respective entries.
333 (print_insn): Move up dp->prefix_requirement handling. Handle
334 PREFIX_DATA.
335 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
336 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
337 Replace / remove respective entries.
338
17d3c7ec
JB		 3392020-07-14 Jan Beulich <jbeulich@suse.com>
340
341 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
342 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
343 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
344 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
345 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
346 the latter two.
347 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
348 0F2C, 0F2D, 0F2E, and 0F2F.
349 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
350 0F2F table entries.
351
41f5efc6
JB		 3522020-07-14 Jan Beulich <jbeulich@suse.com>
353
354 * i386-dis.c (OP_VexR, VexScalarR): New.
355 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
356 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
357 need_vex_reg): Delete.
358 (prefix_table): Replace VexScalar by VexScalarR and
359 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
360 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
361 (vex_len_table): Replace EXqVexScalarS by EXqS.
362 (get_valid_dis386): Don't set need_vex_reg.
363 (print_insn): Don't initialize need_vex_reg.
364 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
365 q_scalar_swap_mode cases.
366 (OP_EX): Don't check for d_scalar_swap_mode and
367 q_scalar_swap_mode.
368 (OP_VEX): Done check need_vex_reg.
369 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
370 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
371 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
372
89e65d17
JB		 3732020-07-14 Jan Beulich <jbeulich@suse.com>
374
375 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
376 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
377 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
378 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
379 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
380 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
381 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
382 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
383 (vex_table): Replace Vex128 by Vex.
384 (vex_len_table): Likewise. Adjust referenced enum names.
385 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
386 referenced enum names.
387 (OP_VEX): Drop vex128_mode and vex256_mode cases.
388 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
389
492a76aa
JB		 3902020-07-14 Jan Beulich <jbeulich@suse.com>
391
392 * i386-dis.c (dis386): "LW" description now applies to "DQ".
393 (putop): Handle "DQ". Don't handle "LW" anymore.
394 (prefix_table, mod_table): Replace %LW by %DQ.
395 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
396
059edf8b
JB		 3972020-07-14 Jan Beulich <jbeulich@suse.com>
398
399 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
400 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
401 d_scalar_swap_mode case handling. Move shift adjsutment into
402 the case its applicable to.
403
4726e9a4
JB		 4042020-07-14 Jan Beulich <jbeulich@suse.com>
405
406 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
407 (EXbScalar, EXwScalar): Fold to ...
408 (EXbwUnit): ... this.
409 (b_scalar_mode, w_scalar_mode): Fold to ...
410 (bw_unit_mode): ... this.
411 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
412 w_scalar_mode handling by bw_unit_mode one.
413 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
414 ...
415 * i386-dis-evex-prefix.h: ... here.
416
b24d668c
JB		 4172020-07-14 Jan Beulich <jbeulich@suse.com>
418
419 * i386-dis.c (PCMPESTR_Fixup): Delete.
420 (dis386): Adjust "LQ" description.
421 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
422 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
423 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
424 vpcmpestrm, and vpcmpestri.
425 (putop): Honor "cond" when handling LQ.
426 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
427 vcvtsi2ss and vcvtusi2ss.
428 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
429 vcvtsi2sd and vcvtusi2sd.
430
c4de7606
JB		 4312020-07-14 Jan Beulich <jbeulich@suse.com>
432
433 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
434 (simd_cmp_op): Add const.
435 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
436 (CMP_Fixup): Handle VEX case.
437 (prefix_table): Replace VCMP by CMP.
438 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
439
9ab00b61
JB		 4402020-07-14 Jan Beulich <jbeulich@suse.com>
441
442 * i386-dis.c (MOVBE_Fixup): Delete.
443 (Mv): Define.
444 (prefix_table): Use Mv for movbe entries.
445
2875b28a
JB		 4462020-07-14 Jan Beulich <jbeulich@suse.com>
447
448 * i386-dis.c (CRC32_Fixup): Delete.
449 (prefix_table): Use Eb/Ev for crc32 entries.
450
e184e611
JB		 4512020-07-14 Jan Beulich <jbeulich@suse.com>
452
453 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
454 Conditionalize invocations of "USED_REX (0)".
455
e8b5d5f9
JB		 4562020-07-14 Jan Beulich <jbeulich@suse.com>
457
458 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
459 CH, DH, BH, AX, DX): Delete.
460 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
461 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
462 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
463
260cd341
LC		 4642020-07-10 Lili Cui <lili.cui@intel.com>
465
466 * i386-dis.c (TMM): New.
467 (EXtmm): Likewise.
468 (VexTmm): Likewise.
469 (MVexSIBMEM): Likewise.
470 (tmm_mode): Likewise.
471 (vex_sibmem_mode): Likewise.
472 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
473 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
474 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
475 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
476 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
477 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
478 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
479 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
480 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
481 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
482 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
483 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
484 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
485 (PREFIX_VEX_0F3849_X86_64): Likewise.
486 (PREFIX_VEX_0F384B_X86_64): Likewise.
487 (PREFIX_VEX_0F385C_X86_64): Likewise.
488 (PREFIX_VEX_0F385E_X86_64): Likewise.
489 (X86_64_VEX_0F3849): Likewise.
490 (X86_64_VEX_0F384B): Likewise.
491 (X86_64_VEX_0F385C): Likewise.
492 (X86_64_VEX_0F385E): Likewise.
493 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
494 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
495 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
496 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
497 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
498 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
499 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
500 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
501 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
502 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
503 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
504 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
505 (VEX_W_0F3849_X86_64_P_0): Likewise.
506 (VEX_W_0F3849_X86_64_P_2): Likewise.
507 (VEX_W_0F3849_X86_64_P_3): Likewise.
508 (VEX_W_0F384B_X86_64_P_1): Likewise.
509 (VEX_W_0F384B_X86_64_P_2): Likewise.
510 (VEX_W_0F384B_X86_64_P_3): Likewise.
511 (VEX_W_0F385C_X86_64_P_1): Likewise.
512 (VEX_W_0F385E_X86_64_P_0): Likewise.
513 (VEX_W_0F385E_X86_64_P_1): Likewise.
514 (VEX_W_0F385E_X86_64_P_2): Likewise.
515 (VEX_W_0F385E_X86_64_P_3): Likewise.
516 (names_tmm): Likewise.
517 (att_names_tmm): Likewise.
518 (intel_operand_size): Handle void_mode.
519 (OP_XMM): Handle tmm_mode.
520 (OP_EX): Likewise.
521 (OP_VEX): Likewise.
522 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
523 CpuAMX_BF16 and CpuAMX_TILE.
524 (operand_type_shorthands): Add RegTMM.
525 (operand_type_init): Likewise.
526 (operand_types): Add Tmmword.
527 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
528 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
529 * i386-opc.h (CpuAMX_INT8): New.
530 (CpuAMX_BF16): Likewise.
531 (CpuAMX_TILE): Likewise.
532 (SIBMEM): Likewise.
533 (Tmmword): Likewise.
534 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
535 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
536 (i386_operand_type): Add tmmword.
537 * i386-opc.tbl: Add AMX instructions.
538 * i386-reg.tbl: Add AMX registers.
539 * i386-init.h: Regenerated.
540 * i386-tbl.h: Likewise.
541
467bbef0
JB		 5422020-07-08 Jan Beulich <jbeulich@suse.com>
543
544 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
545 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
546 Rename to ...
547 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
548 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
549 respectively.
550 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
551 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
552 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
553 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
554 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
555 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
556 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
557 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
558 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
559 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
560 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
561 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
562 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
563 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
564 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
565 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
566 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
567 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
568 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
569 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
570 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
571 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
572 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
573 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
574 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
575 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
576 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
577 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
578 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
579 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
580 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
581 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
582 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
583 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
584 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
585 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
586 (reg_table): Re-order XOP entries. Adjust their operands.
587 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
588 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
589 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
590 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
591 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
592 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
593 entries by references ...
594 (vex_len_table): ... to resepctive new entries here. For several
595 new and existing entries reference ...
596 (vex_w_table): ... new entries here.
597 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
598
6384fd9e
JB		 5992020-07-08 Jan Beulich <jbeulich@suse.com>
600
601 * i386-dis.c (XMVexScalarI4): Define.
602 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
603 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
604 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
605 (vex_len_table): Move scalar FMA4 entries ...
606 (prefix_table): ... here.
607 (OP_REG_VexI4): Handle scalar_mode.
608 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
609 * i386-tbl.h: Re-generate.
610
e6123d0c
JB		 6112020-07-08 Jan Beulich <jbeulich@suse.com>
612
613 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
614 Vex_2src_2): Delete.
615 (OP_VexW, VexW): New.
616 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
617 for shifts and rotates by register.
618
93abb146
JB		 6192020-07-08 Jan Beulich <jbeulich@suse.com>
620
621 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
622 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
623 OP_EX_VexReg): Delete.
624 (OP_VexI4, VexI4): New.
625 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
626 (prefix_table): ... here.
627 (print_insn): Drop setting of vex_w_done.
628
b13b1bc0
JB		 6292020-07-08 Jan Beulich <jbeulich@suse.com>
630
631 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
632 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
633 (xop_table): Replace operands of 4-operand insns.
634 (OP_REG_VexI4): Move VEX.W based operand swaping here.
635
f337259f
CZ		 6362020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
637
638 * arc-opc.c (insert_rbd): New function.
639 (RBD): Define.
640 (RBDdup): Likewise.
641 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
642 instructions.
643
931452b6
JB		 6442020-07-07 Jan Beulich <jbeulich@suse.com>
645
646 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
647 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
648 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
649 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
650 Delete.
651 (putop): Handle "BW".
652 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
653 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
654 and 0F3A3F ...
655 * i386-dis-evex-prefix.h: ... here.
656
b5b098c2
JB		 6572020-07-06 Jan Beulich <jbeulich@suse.com>
658
659 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
660 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
661 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
662 VEX_W_0FXOP_09_83): New enumerators.
663 (xop_table): Reference the above.
664 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
665 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
666 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
667 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
668
21a3faeb
JB		 6692020-07-06 Jan Beulich <jbeulich@suse.com>
670
671 * i386-dis.c (EVEX_W_0F3838_P_1,
672 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
673 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
674 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
675 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
676 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
677 (putop): Centralize management of last[]. Delete SAVE_LAST.
678 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
679 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
680 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
681 * i386-dis-evex-prefix.h: here.
682
bc152a17
JB		 6832020-07-06 Jan Beulich <jbeulich@suse.com>
684
685 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
686 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
687 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
688 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
689 enumerators.
690 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
691 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
692 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
693 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
694 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
695 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
696 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
697 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
698 these, respectively.
699 * i386-dis-evex-len.h: Adjust comments.
700 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
701 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
702 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
703 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
704 MOD_EVEX_0F385B_P_2_W_1 table entries.
705 * i386-dis-evex-w.h: Reference mod_table[] for
706 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
707 EVEX_W_0F385B_P_2.
708
c82a99a0
JB		 7092020-07-06 Jan Beulich <jbeulich@suse.com>
710
711 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
712 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
713 EXymm.
714 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
715 Likewise. Mark 256-bit entries invalid.
716
fedfb81e
JB		 7172020-07-06 Jan Beulich <jbeulich@suse.com>
718
719 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
720 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
721 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
722 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
723 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
724 PREFIX_EVEX_0F382B): Delete.
725 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
726 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
727 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
728 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
729 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
730 to ...
731 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
732 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
733 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
734 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
735 respectively.
736 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
737 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
738 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
739 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
740 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
741 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
742 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
743 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
744 PREFIX_EVEX_0F382B): Remove table entries.
745 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
746 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
747 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
748
3a57774c
JB		 7492020-07-06 Jan Beulich <jbeulich@suse.com>
750
751 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
752 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
753 enumerators.
754 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
755 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
756 EVEX_LEN_0F3A01_P_2_W_1 table entries.
757 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
758 entries.
759
e74d9fa9
JB		 7602020-07-06 Jan Beulich <jbeulich@suse.com>
761
762 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
763 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
764 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
765 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
766 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
767 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
768 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
769 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
770 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
771 entries.
772
6431c801
JB		 7732020-07-06 Jan Beulich <jbeulich@suse.com>
774
775 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
776 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
777 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
778 respectively.
779 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
780 entries.
781 * i386-dis-evex.h (evex_table): Reference VEX table entry for
782 opcode 0F3A1D.
783 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
784 entry.
785 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
786
6df22cf6
JB		 7872020-07-06 Jan Beulich <jbeulich@suse.com>
788
789 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
790 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
791 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
792 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
793 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
794 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
795 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
796 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
797 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
798 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
799 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
800 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
801 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
802 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
803 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
804 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
805 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
806 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
807 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
808 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
809 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
810 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
811 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
812 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
813 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
814 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
815 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
816 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
817 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
818 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
819 (prefix_table): Add EXxEVexR to FMA table entries.
820 (OP_Rounding): Move abort() invocation.
821 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
822 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
823 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
824 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
825 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
826 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
827 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
828 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
829 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
830 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
831 0F3ACE, 0F3ACF.
832 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
833 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
834 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
835 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
836 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
837 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
838 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
839 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
840 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
841 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
842 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
843 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
844 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
845 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
846 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
847 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
848 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
849 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
850 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
851 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
852 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
853 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
854 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
855 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
856 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
857 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
858 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
859 Delete table entries.
860 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
861 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
862 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
863 Likewise.
864
39e0f456
JB		 8652020-07-06 Jan Beulich <jbeulich@suse.com>
866
867 * i386-dis.c (EXqScalarS): Delete.
868 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
869 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
870
5b872f7d
JB		 8712020-07-06 Jan Beulich <jbeulich@suse.com>
872
873 * i386-dis.c (safe-ctype.h): Include.
874 (EXdScalar, EXqScalar): Delete.
875 (d_scalar_mode, q_scalar_mode): Delete.
876 (prefix_table, vex_len_table): Use EXxmm_md in place of
877 EXdScalar and EXxmm_mq in place of EXqScalar.
878 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
879 d_scalar_mode and q_scalar_mode.
880 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
881 (vmovsd): Use EXxmm_mq.
882
ddc73fa9
NC		 8832020-07-06 Yuri Chornoivan <yurchor@ukr.net>
884
885 PR 26204
886 * arc-dis.c: Fix spelling mistake.
887 * po/opcodes.pot: Regenerate.
888
17550be7
NC		 8892020-07-06 Nick Clifton <nickc@redhat.com>
890
891 * po/pt_BR.po: Updated Brazilian Portugugese translation.
892 * po/uk.po: Updated Ukranian translation.
893
b19d852d
NC		 8942020-07-04 Nick Clifton <nickc@redhat.com>
895
896 * configure: Regenerate.
897 * po/opcodes.pot: Regenerate.
898
b115b9fd
NC		 8992020-07-04 Nick Clifton <nickc@redhat.com>
900
901 Binutils 2.35 branch created.
902
c2ecccb3
L		 9032020-07-02 H.J. Lu <hongjiu.lu@intel.com>
904
905 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
906 * i386-opc.h (VexSwapSources): New.
907 (i386_opcode_modifier): Add vexswapsources.
908 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
909 with two source operands swapped.
910 * i386-tbl.h: Regenerated.
911
08ccfccf
NC		 9122020-06-30 Nelson Chu <nelson.chu@sifive.com>
913
914 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
915 unprivileged CSR can also be initialized.
916
279edac5
AM		 9172020-06-29 Alan Modra <amodra@gmail.com>
918
919 * arm-dis.c: Use C style comments.
920 * cr16-opc.c: Likewise.
921 * ft32-dis.c: Likewise.
922 * moxie-opc.c: Likewise.
923 * tic54x-dis.c: Likewise.
924 * s12z-opc.c: Remove useless comment.
925 * xgate-dis.c: Likewise.
926
e978ad62
L		 9272020-06-26 H.J. Lu <hongjiu.lu@intel.com>
928
929 * i386-opc.tbl: Add a blank line.
930
63112cd6
L		 9312020-06-26 H.J. Lu <hongjiu.lu@intel.com>
932
933 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
934 (VecSIB128): Renamed to ...
935 (VECSIB128): This.
936 (VecSIB256): Renamed to ...
937 (VECSIB256): This.
938 (VecSIB512): Renamed to ...
939 (VECSIB512): This.
940 (VecSIB): Renamed to ...
941 (SIB): This.
942 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 943 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 944 (VecSIB256): Likewise.
945 (VecSIB512): Likewise.
79b32e73 946 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 947 and VecSIB512, respectively.
948
d1c36125
JB		 9492020-06-26 Jan Beulich <jbeulich@suse.com>
950
951 * i386-dis.c: Adjust description of I macro.
952 (x86_64_table): Drop use of I.
953 (float_mem): Replace use of I.
954 (putop): Remove handling of I. Adjust setting/clearing of "alt".
955
2a1bb84c
JB		 9562020-06-26 Jan Beulich <jbeulich@suse.com>
957
958 * i386-dis.c: (print_insn): Avoid straight assignment to
959 priv.orig_sizeflag when processing -M sub-options.
960
8f570d62
JB		 9612020-06-25 Jan Beulich <jbeulich@suse.com>
962
963 * i386-dis.c: Adjust description of J macro.
964 (dis386, x86_64_table, mod_table): Replace J.
965 (putop): Remove handling of J.
966
464dc4af
JB		 9672020-06-25 Jan Beulich <jbeulich@suse.com>
968
969 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
970
589958d6
JB		 9712020-06-25 Jan Beulich <jbeulich@suse.com>
972
973 * i386-dis.c: Adjust description of "LQ" macro.
974 (dis386_twobyte): Use LQ for sysret.
975 (putop): Adjust handling of LQ.
976
39ff0b81
NC		 9772020-06-22 Nelson Chu <nelson.chu@sifive.com>
978
979 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
980 * riscv-dis.c: Include elfxx-riscv.h.
981
d27c357a
JB		 9822020-06-18 H.J. Lu <hongjiu.lu@intel.com>
983
984 * i386-dis.c (prefix_table): Revert the last vmgexit change.
985
6fde587f
CL		 9862020-06-17 Lili Cui <lili.cui@intel.com>
987
988 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
989
efe30057
L		 9902020-06-14 H.J. Lu <hongjiu.lu@intel.com>
991
992 PR gas/26115
993 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
994 * i386-opc.tbl: Likewise.
995 * i386-tbl.h: Regenerated.
996
d8af286f
NC		 9972020-06-12 Nelson Chu <nelson.chu@sifive.com>
998
999 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1000
14962256
AC		 10012020-06-11 Alex Coplan <alex.coplan@arm.com>
1002
1003 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1004 (SR_CORE): Likewise.
1005 (SR_FEAT): Likewise.
1006 (SR_RNG): Likewise.
1007 (SR_V8_1): Likewise.
1008 (SR_V8_2): Likewise.
1009 (SR_V8_3): Likewise.
1010 (SR_V8_4): Likewise.
1011 (SR_PAN): Likewise.
1012 (SR_RAS): Likewise.
1013 (SR_SSBS): Likewise.
1014 (SR_SVE): Likewise.
1015 (SR_ID_PFR2): Likewise.
1016 (SR_PROFILE): Likewise.
1017 (SR_MEMTAG): Likewise.
1018 (SR_SCXTNUM): Likewise.
1019 (aarch64_sys_regs): Refactor to store feature information in the table.
1020 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1021 that now describe their own features.
1022 (aarch64_pstatefield_supported_p): Likewise.
1023
f9630fa6
L		 10242020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1025
1026 * i386-dis.c (prefix_table): Fix a typo in comments.
1027
73239888
JB		 10282020-06-09 Jan Beulich <jbeulich@suse.com>
1029
1030 * i386-dis.c (rex_ignored): Delete.
1031 (ckprefix): Drop rex_ignored initialization.
1032 (get_valid_dis386): Drop setting of rex_ignored.
1033 (print_insn): Drop checking of rex_ignored. Don't record data
1034 size prefix as used with VEX-and-alike encodings.
1035
18897deb
JB		 10362020-06-09 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1039 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1040 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1041 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1042 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1043 VEX_0F12, and VEX_0F16.
1044 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1045 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1046 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1047 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1048 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1049 MOD_VEX_0F16_PREFIX_2 entries.
1050
97e6786a
JB		 10512020-06-09 Jan Beulich <jbeulich@suse.com>
1052
1053 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1054 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1055 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1056 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1057 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1058 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1059 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1060 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1061 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1062 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1063 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1064 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1065 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1066 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1067 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1068 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1069 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1070 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1071 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1072 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1073 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1074 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1075 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1076 EVEX_W_0FC6_P_2): Delete.
1077 (print_insn): Add EVEX.W vs embedded prefix consistency check
1078 to prefix validation.
1079 * i386-dis-evex.h (evex_table): Don't further descend for
1080 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1081 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1082 and 0F2B.
1083 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1084 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1085 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1086 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1087 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1088 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1089 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1090 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1091 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1092 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1093 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1094 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1095 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1096 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1097 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1098 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1099 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1100 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1101 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1102 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1103 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1104 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1105 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1106 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1107 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1108 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1109 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1110
bf926894
JB		 11112020-06-09 Jan Beulich <jbeulich@suse.com>
1112
1113 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1114 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1115 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1116 vmovmskpX.
1117 (print_insn): Drop pointless check against bad_opcode. Split
1118 prefix validation into legacy and VEX-and-alike parts.
1119 (putop): Re-work 'X' macro handling.
1120
a5aaedb9
JB		 11212020-06-09 Jan Beulich <jbeulich@suse.com>
1122
1123 * i386-dis.c (MOD_0F51): Rename to ...
1124 (MOD_0F50): ... this.
1125
26417f19
AC		 11262020-06-08 Alex Coplan <alex.coplan@arm.com>
1127
1128 * arm-dis.c (arm_opcodes): Add dfb.
1129 (thumb32_opcodes): Add dfb.
1130
8a6fb3f9
JB		 11312020-06-08 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1134
1424c35d
AM		 11352020-06-06 Alan Modra <amodra@gmail.com>
1136
1137 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1138
d3d1cc7b
AM		 11392020-06-05 Alan Modra <amodra@gmail.com>
1140
1141 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1142 size is large enough.
1143
d8740be1
JM		 11442020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1145
1146 * disassemble.c (disassemble_init_for_target): Set endian_code for
1147 bpf targets.
1148 * bpf-desc.c: Regenerate.
1149 * bpf-opc.c: Likewise.
1150 * bpf-dis.c: Likewise.
1151
e9bffec9
JM		 11522020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1153
1154 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1155 (cgen_put_insn_value): Likewise.
1156 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1157 * cgen-dis.in (print_insn): Likewise.
1158 * cgen-ibld.in (insert_1): Likewise.
1159 (insert_1): Likewise.
1160 (insert_insn_normal): Likewise.
1161 (extract_1): Likewise.
1162 * bpf-dis.c: Regenerate.
1163 * bpf-ibld.c: Likewise.
1164 * bpf-ibld.c: Likewise.
1165 * cgen-dis.in: Likewise.
1166 * cgen-ibld.in: Likewise.
1167 * cgen-opc.c: Likewise.
1168 * epiphany-dis.c: Likewise.
1169 * epiphany-ibld.c: Likewise.
1170 * fr30-dis.c: Likewise.
1171 * fr30-ibld.c: Likewise.
1172 * frv-dis.c: Likewise.
1173 * frv-ibld.c: Likewise.
1174 * ip2k-dis.c: Likewise.
1175 * ip2k-ibld.c: Likewise.
1176 * iq2000-dis.c: Likewise.
1177 * iq2000-ibld.c: Likewise.
1178 * lm32-dis.c: Likewise.
1179 * lm32-ibld.c: Likewise.
1180 * m32c-dis.c: Likewise.
1181 * m32c-ibld.c: Likewise.
1182 * m32r-dis.c: Likewise.
1183 * m32r-ibld.c: Likewise.
1184 * mep-dis.c: Likewise.
1185 * mep-ibld.c: Likewise.
1186 * mt-dis.c: Likewise.
1187 * mt-ibld.c: Likewise.
1188 * or1k-dis.c: Likewise.
1189 * or1k-ibld.c: Likewise.
1190 * xc16x-dis.c: Likewise.
1191 * xc16x-ibld.c: Likewise.
1192 * xstormy16-dis.c: Likewise.
1193 * xstormy16-ibld.c: Likewise.
1194
b3db6d07
JM		 11952020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1196
1197 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1198 (print_insn_): Handle instruction endian.
1199 * bpf-dis.c: Regenerate.
1200 * bpf-desc.c: Regenerate.
1201 * epiphany-dis.c: Likewise.
1202 * epiphany-desc.c: Likewise.
1203 * fr30-dis.c: Likewise.
1204 * fr30-desc.c: Likewise.
1205 * frv-dis.c: Likewise.
1206 * frv-desc.c: Likewise.
1207 * ip2k-dis.c: Likewise.
1208 * ip2k-desc.c: Likewise.
1209 * iq2000-dis.c: Likewise.
1210 * iq2000-desc.c: Likewise.
1211 * lm32-dis.c: Likewise.
1212 * lm32-desc.c: Likewise.
1213 * m32c-dis.c: Likewise.
1214 * m32c-desc.c: Likewise.
1215 * m32r-dis.c: Likewise.
1216 * m32r-desc.c: Likewise.
1217 * mep-dis.c: Likewise.
1218 * mep-desc.c: Likewise.
1219 * mt-dis.c: Likewise.
1220 * mt-desc.c: Likewise.
1221 * or1k-dis.c: Likewise.
1222 * or1k-desc.c: Likewise.
1223 * xc16x-dis.c: Likewise.
1224 * xc16x-desc.c: Likewise.
1225 * xstormy16-dis.c: Likewise.
1226 * xstormy16-desc.c: Likewise.
1227
4ee4189f
NC		 12282020-06-03 Nick Clifton <nickc@redhat.com>
1229
1230 * po/sr.po: Updated Serbian translation.
1231
44730156
NC		 12322020-06-03 Nelson Chu <nelson.chu@sifive.com>
1233
1234 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1235 (riscv_get_priv_spec_class): Likewise.
1236
3c3d0376
AM		 12372020-06-01 Alan Modra <amodra@gmail.com>
1238
1239 * bpf-desc.c: Regenerate.
1240
78c1c354
JM		 12412020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1242 David Faust <david.faust@oracle.com>
1243
1244 * bpf-desc.c: Regenerate.
1245 * bpf-opc.h: Likewise.
1246 * bpf-opc.c: Likewise.
1247 * bpf-dis.c: Likewise.
1248
efcf5fb5
AM		 12492020-05-28 Alan Modra <amodra@gmail.com>
1250
1251 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1252 values.
1253
ab382d64
AM		 12542020-05-28 Alan Modra <amodra@gmail.com>
1255
1256 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1257 immediates.
1258 (print_insn_ns32k): Revert last change.
1259
151f5de4
NC		 12602020-05-28 Nick Clifton <nickc@redhat.com>
1261
1262 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1263 static.
1264
25e1eca8
SL		 12652020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1266
1267 Fix extraction of signed constants in nios2 disassembler (again).
1268
1269 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1270 extractions of signed fields.
1271
57b17940
SSF		 12722020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1273
1274 * s390-opc.txt: Relocate vector load/store instructions with
1275 additional alignment parameter and change architecture level
1276 constraint from z14 to z13.
1277
d96bf37b
AM		 12782020-05-21 Alan Modra <amodra@gmail.com>
1279
1280 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1281 * sparc-dis.c: Likewise.
1282 * tic4x-dis.c: Likewise.
1283 * xtensa-dis.c: Likewise.
1284 * bpf-desc.c: Regenerate.
1285 * epiphany-desc.c: Regenerate.
1286 * fr30-desc.c: Regenerate.
1287 * frv-desc.c: Regenerate.
1288 * ip2k-desc.c: Regenerate.
1289 * iq2000-desc.c: Regenerate.
1290 * lm32-desc.c: Regenerate.
1291 * m32c-desc.c: Regenerate.
1292 * m32r-desc.c: Regenerate.
1293 * mep-asm.c: Regenerate.
1294 * mep-desc.c: Regenerate.
1295 * mt-desc.c: Regenerate.
1296 * or1k-desc.c: Regenerate.
1297 * xc16x-desc.c: Regenerate.
1298 * xstormy16-desc.c: Regenerate.
1299
8f595e9b
NC		 13002020-05-20 Nelson Chu <nelson.chu@sifive.com>
1301
1302 * riscv-opc.c (riscv_ext_version_table): The table used to store
1303 all information about the supported spec and the corresponding ISA
1304 versions. Currently, only Zicsr is supported to verify the
1305 correctness of Z sub extension settings. Others will be supported
1306 in the future patches.
1307 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1308 classes and the corresponding strings.
1309 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1310 spec class by giving a ISA spec string.
1311 * riscv-opc.c (struct priv_spec_t): New structure.
1312 (struct priv_spec_t priv_specs): List for all supported privilege spec
1313 classes and the corresponding strings.
1314 (riscv_get_priv_spec_class): New function. Get the corresponding
1315 privilege spec class by giving a spec string.
1316 (riscv_get_priv_spec_name): New function. Get the corresponding
1317 privilege spec string by giving a CSR version class.
1318 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1319 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1320 according to the chosen version. Build a hash table riscv_csr_hash to
1321 store the valid CSR for the chosen pirv verison. Dump the direct
1322 CSR address rather than it's name if it is invalid.
1323 (parse_riscv_dis_option_without_args): New function. Parse the options
1324 without arguments.
1325 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1326 parse the options without arguments first, and then handle the options
1327 with arguments. Add the new option -Mpriv-spec, which has argument.
1328 * riscv-dis.c (print_riscv_disassembler_options): Add description
1329 about the new OBJDUMP option.
1330
3d205eb4
PB		 13312020-05-19 Peter Bergner <bergner@linux.ibm.com>
1332
1333 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1334 WC values on POWER10 sync, dcbf and wait instructions.
1335 (insert_pl, extract_pl): New functions.
1336 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1337 (LS3): New , 3-bit L for sync.
1338 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1339 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1340 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1341 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1342 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1343 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1344 <wait>: Enable PL operand on POWER10.
1345 <dcbf>: Enable L3OPT operand on POWER10.
1346 <sync>: Enable SC2 operand on POWER10.
1347
a501eb44
SH		 13482020-05-19 Stafford Horne <shorne@gmail.com>
1349
1350 PR 25184
1351 * or1k-asm.c: Regenerate.
1352 * or1k-desc.c: Regenerate.
1353 * or1k-desc.h: Regenerate.
1354 * or1k-dis.c: Regenerate.
1355 * or1k-ibld.c: Regenerate.
1356 * or1k-opc.c: Regenerate.
1357 * or1k-opc.h: Regenerate.
1358 * or1k-opinst.c: Regenerate.
1359
3b646889
AM		 13602020-05-11 Alan Modra <amodra@gmail.com>
1361
1362 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1363 xsmaxcqp, xsmincqp.
1364
9cc4ce88
AM		 13652020-05-11 Alan Modra <amodra@gmail.com>
1366
1367 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1368 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1369
5d57bc3f
AM		 13702020-05-11 Alan Modra <amodra@gmail.com>
1371
1372 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1373
66ef5847
AM		 13742020-05-11 Alan Modra <amodra@gmail.com>
1375
1376 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1377 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1378
4f3e9537
PB		 13792020-05-11 Peter Bergner <bergner@linux.ibm.com>
1380
1381 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1382 mnemonics.
1383
ec40e91c
AM		 13842020-05-11 Alan Modra <amodra@gmail.com>
1385
1386 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1387 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1388 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1389 (prefix_opcodes): Add xxeval.
1390
d7e97a76
AM		 13912020-05-11 Alan Modra <amodra@gmail.com>
1392
1393 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1394 xxgenpcvwm, xxgenpcvdm.
1395
fdefed7c
AM		 13962020-05-11 Alan Modra <amodra@gmail.com>
1397
1398 * ppc-opc.c (MP, VXVAM_MASK): Define.
1399 (VXVAPS_MASK): Use VXVA_MASK.
1400 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1401 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1402 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1403 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1404
aa3c112f
AM		 14052020-05-11 Alan Modra <amodra@gmail.com>
1406 Peter Bergner <bergner@linux.ibm.com>
1407
1408 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1409 New functions.
1410 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1411 YMSK2, XA6a, XA6ap, XB6a entries.
1412 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1413 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1414 (PPCVSX4): Define.
1415 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1416 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1417 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1418 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1419 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1420 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1421 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1422 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1423 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1424 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1425 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1426 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1427 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1428 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1429
6edbfd3b
AM		 14302020-05-11 Alan Modra <amodra@gmail.com>
1431
1432 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1433 (insert_xts, extract_xts): New functions.
1434 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1435 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1436 (VXRC_MASK, VXSH_MASK): Define.
1437 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1438 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1439 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1440 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1441 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1442 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1443 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1444
c7d7aea2
AM		 14452020-05-11 Alan Modra <amodra@gmail.com>
1446
1447 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1448 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1449 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1450 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1451 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1452
94ba9882
AM		 14532020-05-11 Alan Modra <amodra@gmail.com>
1454
1455 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1456 (XTP, DQXP, DQXP_MASK): Define.
1457 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1458 (prefix_opcodes): Add plxvp and pstxvp.
1459
f4791f1a
AM		 14602020-05-11 Alan Modra <amodra@gmail.com>
1461
1462 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1463 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1464 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1465
3ff0a5ba
PB		 14662020-05-11 Peter Bergner <bergner@linux.ibm.com>
1467
1468 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1469
afef4fe9
PB		 14702020-05-11 Peter Bergner <bergner@linux.ibm.com>
1471
1472 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1473 (L1OPT): Define.
1474 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1475
1224c05d
PB		 14762020-05-11 Peter Bergner <bergner@linux.ibm.com>
1477
1478 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1479
6bbb0c05
AM		 14802020-05-11 Alan Modra <amodra@gmail.com>
1481
1482 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1483
7c1f4227
AM		 14842020-05-11 Alan Modra <amodra@gmail.com>
1485
1486 * ppc-dis.c (ppc_opts): Add "power10" entry.
1487 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1488 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1489
73199c2b
NC		 14902020-05-11 Nick Clifton <nickc@redhat.com>
1491
1492 * po/fr.po: Updated French translation.
1493
09c1e68a
AC		 14942020-04-30 Alex Coplan <alex.coplan@arm.com>
1495
1496 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1497 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1498 (operand_general_constraint_met_p): validate
1499 AARCH64_OPND_UNDEFINED.
1500 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1501 for FLD_imm16_2.
1502 * aarch64-asm-2.c: Regenerated.
1503 * aarch64-dis-2.c: Regenerated.
1504 * aarch64-opc-2.c: Regenerated.
1505
9654d51a
NC		 15062020-04-29 Nick Clifton <nickc@redhat.com>
1507
1508 PR 22699
1509 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1510 and SETRC insns.
1511
c2e71e57
NC		 15122020-04-29 Nick Clifton <nickc@redhat.com>
1513
1514 * po/sv.po: Updated Swedish translation.
1515
5c936ef5
NC		 15162020-04-29 Nick Clifton <nickc@redhat.com>
1517
1518 PR 22699
1519 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1520 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1521 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1522 IMM0_8U case.
1523
bb2a1453
AS		 15242020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1525
1526 PR 25848
1527 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1528 cmpi only on m68020up and cpu32.
1529
c2e5c986
SD		 15302020-04-20 Sudakshina Das <sudi.das@arm.com>
1531
1532 * aarch64-asm.c (aarch64_ins_none): New.
1533 * aarch64-asm.h (ins_none): New declaration.
1534 * aarch64-dis.c (aarch64_ext_none): New.
1535 * aarch64-dis.h (ext_none): New declaration.
1536 * aarch64-opc.c (aarch64_print_operand): Update case for
1537 AARCH64_OPND_BARRIER_PSB.
1538 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1539 (AARCH64_OPERANDS): Update inserter/extracter for
1540 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1541 * aarch64-asm-2.c: Regenerated.
1542 * aarch64-dis-2.c: Regenerated.
1543 * aarch64-opc-2.c: Regenerated.
1544
8a6e1d1d
SD		 15452020-04-20 Sudakshina Das <sudi.das@arm.com>
1546
1547 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1548 (aarch64_feature_ras, RAS): Likewise.
1549 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1550 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1551 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1552 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1553 * aarch64-asm-2.c: Regenerated.
1554 * aarch64-dis-2.c: Regenerated.
1555 * aarch64-opc-2.c: Regenerated.
1556
e409955d
FS		 15572020-04-17 Fredrik Strupe <fredrik@strupe.net>
1558
1559 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1560 (print_insn_neon): Support disassembly of conditional
1561 instructions.
1562
c54a9b56
DF		 15632020-02-16 David Faust <david.faust@oracle.com>
1564
1565 * bpf-desc.c: Regenerate.
1566 * bpf-desc.h: Likewise.
1567 * bpf-opc.c: Regenerate.
1568 * bpf-opc.h: Likewise.
1569
bb651e8b
CL		 15702020-04-07 Lili Cui <lili.cui@intel.com>
1571
1572 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1573 (prefix_table): New instructions (see prefixes above).
1574 (rm_table): Likewise
1575 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1576 CPU_ANY_TSXLDTRK_FLAGS.
1577 (cpu_flags): Add CpuTSXLDTRK.
1578 * i386-opc.h (enum): Add CpuTSXLDTRK.
1579 (i386_cpu_flags): Add cputsxldtrk.
1580 * i386-opc.tbl: Add XSUSPLDTRK insns.
1581 * i386-init.h: Regenerate.
1582 * i386-tbl.h: Likewise.
1583
4b27d27c
L		 15842020-04-02 Lili Cui <lili.cui@intel.com>
1585
1586 * i386-dis.c (prefix_table): New instructions serialize.
1587 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1588 CPU_ANY_SERIALIZE_FLAGS.
1589 (cpu_flags): Add CpuSERIALIZE.
1590 * i386-opc.h (enum): Add CpuSERIALIZE.
1591 (i386_cpu_flags): Add cpuserialize.
1592 * i386-opc.tbl: Add SERIALIZE insns.
1593 * i386-init.h: Regenerate.
1594 * i386-tbl.h: Likewise.
1595
832a5807
AM		 15962020-03-26 Alan Modra <amodra@gmail.com>
1597
1598 * disassemble.h (opcodes_assert): Declare.
1599 (OPCODES_ASSERT): Define.
1600 * disassemble.c: Don't include assert.h. Include opintl.h.
1601 (opcodes_assert): New function.
1602 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1603 (bfd_h8_disassemble): Reduce size of data array. Correctly
1604 calculate maxlen. Omit insn decoding when insn length exceeds
1605 maxlen. Exit from nibble loop when looking for E, before
1606 accessing next data byte. Move processing of E outside loop.
1607 Replace tests of maxlen in loop with assertions.
1608
4c4addbe
AM		 16092020-03-26 Alan Modra <amodra@gmail.com>
1610
1611 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1612
a18cd0ca
AM		 16132020-03-25 Alan Modra <amodra@gmail.com>
1614
1615 * z80-dis.c (suffix): Init mybuf.
1616
57cb32b3
AM		 16172020-03-22 Alan Modra <amodra@gmail.com>
1618
1619 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1620 successflly read from section.
1621
beea5cc1
AM		 16222020-03-22 Alan Modra <amodra@gmail.com>
1623
1624 * arc-dis.c (find_format): Use ISO C string concatenation rather
1625 than line continuation within a string. Don't access needs_limm
1626 before testing opcode != NULL.
1627
03704c77
AM		 16282020-03-22 Alan Modra <amodra@gmail.com>
1629
1630 * ns32k-dis.c (print_insn_arg): Update comment.
1631 (print_insn_ns32k): Reduce size of index_offset array, and
1632 initialize, passing -1 to print_insn_arg for args that are not
1633 an index. Don't exit arg loop early. Abort on bad arg number.
1634
d1023b5d
AM		 16352020-03-22 Alan Modra <amodra@gmail.com>
1636
1637 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1638 * s12z-opc.c: Formatting.
1639 (operands_f): Return an int.
1640 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1641 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1642 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1643 (exg_sex_discrim): Likewise.
1644 (create_immediate_operand, create_bitfield_operand),
1645 (create_register_operand_with_size, create_register_all_operand),
1646 (create_register_all16_operand, create_simple_memory_operand),
1647 (create_memory_operand, create_memory_auto_operand): Don't
1648 segfault on malloc failure.
1649 (z_ext24_decode): Return an int status, negative on fail, zero
1650 on success.
1651 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1652 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1653 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1654 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1655 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1656 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1657 (loop_primitive_decode, shift_decode, psh_pul_decode),
1658 (bit_field_decode): Similarly.
1659 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1660 to return value, update callers.
1661 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1662 Don't segfault on NULL operand.
1663 (decode_operation): Return OP_INVALID on first fail.
1664 (decode_s12z): Check all reads, returning -1 on fail.
1665
340f3ac8
AM		 16662020-03-20 Alan Modra <amodra@gmail.com>
1667
1668 * metag-dis.c (print_insn_metag): Don't ignore status from
1669 read_memory_func.
1670
fe90ae8a
AM		 16712020-03-20 Alan Modra <amodra@gmail.com>
1672
1673 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1674 Initialize parts of buffer not written when handling a possible
1675 2-byte insn at end of section. Don't attempt decoding of such
1676 an insn by the 4-byte machinery.
1677
833d919c
AM		 16782020-03-20 Alan Modra <amodra@gmail.com>
1679
1680 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1681 partially filled buffer. Prevent lookup of 4-byte insns when
1682 only VLE 2-byte insns are possible due to section size. Print
1683 ".word" rather than ".long" for 2-byte leftovers.
1684
327ef784
NC		 16852020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1686
1687 PR 25641
1688 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1689
1673df32
JB		 16902020-03-13 Jan Beulich <jbeulich@suse.com>
1691
1692 * i386-dis.c (X86_64_0D): Rename to ...
1693 (X86_64_0E): ... this.
1694
384f3689
L		 16952020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1696
1697 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1698 * Makefile.in: Regenerated.
1699
865e2027
JB		 17002020-03-09 Jan Beulich <jbeulich@suse.com>
1701
1702 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1703 3-operand pseudos.
1704 * i386-tbl.h: Re-generate.
1705
2f13234b
JB		 17062020-03-09 Jan Beulich <jbeulich@suse.com>
1707
1708 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1709 vprot*, vpsha*, and vpshl*.
1710 * i386-tbl.h: Re-generate.
1711
3fabc179
JB		 17122020-03-09 Jan Beulich <jbeulich@suse.com>
1713
1714 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1715 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1716 * i386-tbl.h: Re-generate.
1717
3677e4c1
JB		 17182020-03-09 Jan Beulich <jbeulich@suse.com>
1719
1720 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1721 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1722 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1723 * i386-tbl.h: Re-generate.
1724
4c4898e8
JB		 17252020-03-09 Jan Beulich <jbeulich@suse.com>
1726
1727 * i386-gen.c (struct template_arg, struct template_instance,
1728 struct template_param, struct template, templates,
1729 parse_template, expand_templates): New.
1730 (process_i386_opcodes): Various local variables moved to
1731 expand_templates. Call parse_template and expand_templates.
1732 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1733 * i386-tbl.h: Re-generate.
1734
bc49bfd8
JB		 17352020-03-06 Jan Beulich <jbeulich@suse.com>
1736
1737 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1738 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1739 register and memory source templates. Replace VexW= by VexW*
1740 where applicable.
1741 * i386-tbl.h: Re-generate.
1742
4873e243
JB		 17432020-03-06 Jan Beulich <jbeulich@suse.com>
1744
1745 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1746 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1747 * i386-tbl.h: Re-generate.
1748
672a349b
JB		 17492020-03-06 Jan Beulich <jbeulich@suse.com>
1750
1751 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1752 * i386-tbl.h: Re-generate.
1753
4ed21b58
JB		 17542020-03-06 Jan Beulich <jbeulich@suse.com>
1755
1756 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1757 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1758 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1759 VexW0 on SSE2AVX variants.
1760 (vmovq): Drop NoRex64 from XMM/XMM variants.
1761 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1762 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1763 applicable use VexW0.
1764 * i386-tbl.h: Re-generate.
1765
643bb870
JB		 17662020-03-06 Jan Beulich <jbeulich@suse.com>
1767
1768 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1769 * i386-opc.h (Rex64): Delete.
1770 (struct i386_opcode_modifier): Remove rex64 field.
1771 * i386-opc.tbl (crc32): Drop Rex64.
1772 Replace Rex64 with Size64 everywhere else.
1773 * i386-tbl.h: Re-generate.
1774
a23b33b3
JB		 17752020-03-06 Jan Beulich <jbeulich@suse.com>
1776
1777 * i386-dis.c (OP_E_memory): Exclude recording of used address
1778 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1779 addressed memory operands for MPX insns.
1780
a0497384
JB		 17812020-03-06 Jan Beulich <jbeulich@suse.com>
1782
1783 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1784 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1785 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1786 (ptwrite): Split into non-64-bit and 64-bit forms.
1787 * i386-tbl.h: Re-generate.
1788
b630c145
JB		 17892020-03-06 Jan Beulich <jbeulich@suse.com>
1790
1791 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1792 template.
1793 * i386-tbl.h: Re-generate.
1794
a847e322
JB		 17952020-03-04 Jan Beulich <jbeulich@suse.com>
1796
1797 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1798 (prefix_table): Move vmmcall here. Add vmgexit.
1799 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1800 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1801 (cpu_flags): Add CpuSEV_ES entry.
1802 * i386-opc.h (CpuSEV_ES): New.
1803 (union i386_cpu_flags): Add cpusev_es field.
1804 * i386-opc.tbl (vmgexit): New.
1805 * i386-init.h, i386-tbl.h: Re-generate.
1806
3cd7f3e3
L		 18072020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1808
1809 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1810 with MnemonicSize.
1811 * i386-opc.h (IGNORESIZE): New.
1812 (DEFAULTSIZE): Likewise.
1813 (IgnoreSize): Removed.
1814 (DefaultSize): Likewise.
1815 (MnemonicSize): New.
1816 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1817 mnemonicsize.
1818 * i386-opc.tbl (IgnoreSize): New.
1819 (DefaultSize): Likewise.
1820 * i386-tbl.h: Regenerated.
1821
b8ba1385
SB		 18222020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1823
1824 PR 25627
1825 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1826 instructions.
1827
10d97a0f
L		 18282020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1829
1830 PR gas/25622
1831 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1832 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1833 * i386-tbl.h: Regenerated.
1834
dc1e8a47
AM		 18352020-02-26 Alan Modra <amodra@gmail.com>
1836
1837 * aarch64-asm.c: Indent labels correctly.
1838 * aarch64-dis.c: Likewise.
1839 * aarch64-gen.c: Likewise.
1840 * aarch64-opc.c: Likewise.
1841 * alpha-dis.c: Likewise.
1842 * i386-dis.c: Likewise.
1843 * nds32-asm.c: Likewise.
1844 * nfp-dis.c: Likewise.
1845 * visium-dis.c: Likewise.
1846
265b4673
CZ		 18472020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1848
1849 * arc-regs.h (int_vector_base): Make it available for all ARC
1850 CPUs.
1851
bd0cf5a6
NC		 18522020-02-20 Nelson Chu <nelson.chu@sifive.com>
1853
1854 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1855 changed.
1856
fa164239
JW		 18572020-02-19 Nelson Chu <nelson.chu@sifive.com>
1858
1859 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1860 c.mv/c.li if rs1 is zero.
1861
272a84b1
L		 18622020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1863
1864 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1865 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1866 CPU_POPCNT_FLAGS.
1867 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1868 * i386-opc.h (CpuABM): Removed.
1869 (CpuPOPCNT): New.
1870 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1871 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1872 popcnt. Remove CpuABM from lzcnt.
1873 * i386-init.h: Regenerated.
1874 * i386-tbl.h: Likewise.
1875
1f730c46
JB		 18762020-02-17 Jan Beulich <jbeulich@suse.com>
1877
1878 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1879 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1880 VexW1 instead of open-coding them.
1881 * i386-tbl.h: Re-generate.
1882
c8f8eebc
JB		 18832020-02-17 Jan Beulich <jbeulich@suse.com>
1884
1885 * i386-opc.tbl (AddrPrefixOpReg): Define.
1886 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1887 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1888 templates. Drop NoRex64.
1889 * i386-tbl.h: Re-generate.
1890
b9915cbc
JB		 18912020-02-17 Jan Beulich <jbeulich@suse.com>
1892
1893 PR gas/6518
1894 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1895 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1896 into Intel syntax instance (with Unpsecified) and AT&T one
1897 (without).
1898 (vcvtneps2bf16): Likewise, along with folding the two so far
1899 separate ones.
1900 * i386-tbl.h: Re-generate.
1901
ce504911
L		 19022020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1903
1904 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1905 CPU_ANY_SSE4A_FLAGS.
1906
dabec65d
AM		 19072020-02-17 Alan Modra <amodra@gmail.com>
1908
1909 * i386-gen.c (cpu_flag_init): Correct last change.
1910
af5c13b0
L		 19112020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1912
1913 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1914 CPU_ANY_SSE4_FLAGS.
1915
6867aac0
L		 19162020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1917
1918 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1919 (movzx): Likewise.
1920
65fca059
JB		 19212020-02-14 Jan Beulich <jbeulich@suse.com>
1922
1923 PR gas/25438
1924 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1925 destination for Cpu64-only variant.
1926 (movzx): Fold patterns.
1927 * i386-tbl.h: Re-generate.
1928
7deea9aa
JB		 19292020-02-13 Jan Beulich <jbeulich@suse.com>
1930
1931 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1932 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1933 CPU_ANY_SSE4_FLAGS entry.
1934 * i386-init.h: Re-generate.
1935
6c0946d0
JB		 19362020-02-12 Jan Beulich <jbeulich@suse.com>
1937
1938 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1939 with Unspecified, making the present one AT&T syntax only.
1940 * i386-tbl.h: Re-generate.
1941
ddb56fe6
JB		 19422020-02-12 Jan Beulich <jbeulich@suse.com>
1943
1944 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1945 * i386-tbl.h: Re-generate.
1946
5990e377
JB		 19472020-02-12 Jan Beulich <jbeulich@suse.com>
1948
1949 PR gas/24546
1950 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1951 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1952 Amd64 and Intel64 templates.
1953 (call, jmp): Likewise for far indirect variants. Dro
1954 Unspecified.
1955 * i386-tbl.h: Re-generate.
1956
50128d0c
JB		 19572020-02-11 Jan Beulich <jbeulich@suse.com>
1958
1959 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1960 * i386-opc.h (ShortForm): Delete.
1961 (struct i386_opcode_modifier): Remove shortform field.
1962 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1963 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1964 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1965 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1966 Drop ShortForm.
1967 * i386-tbl.h: Re-generate.
1968
1e05b5c4
JB		 19692020-02-11 Jan Beulich <jbeulich@suse.com>
1970
1971 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1972 fucompi): Drop ShortForm from operand-less templates.
1973 * i386-tbl.h: Re-generate.
1974
2f5dd314
AM		 19752020-02-11 Alan Modra <amodra@gmail.com>
1976
1977 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1978 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1979 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1980 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1981 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1982
5aae9ae9
MM		 19832020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1984
1985 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1986 (cde_opcodes): Add VCX* instructions.
1987
4934a27c
MM		 19882020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1989 Matthew Malcomson <matthew.malcomson@arm.com>
1990
1991 * arm-dis.c (struct cdeopcode32): New.
1992 (CDE_OPCODE): New macro.
1993 (cde_opcodes): New disassembly table.
1994 (regnames): New option to table.
1995 (cde_coprocs): New global variable.
1996 (print_insn_cde): New
1997 (print_insn_thumb32): Use print_insn_cde.
1998 (parse_arm_disassembler_options): Parse coprocN args.
1999
4b5aaf5f
L		 20002020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2001
2002 PR gas/25516
2003 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2004 with ISA64.
2005 * i386-opc.h (AMD64): Removed.
2006 (Intel64): Likewose.
2007 (AMD64): New.
2008 (INTEL64): Likewise.
2009 (INTEL64ONLY): Likewise.
2010 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2011 * i386-opc.tbl (Amd64): New.
2012 (Intel64): Likewise.
2013 (Intel64Only): Likewise.
2014 Replace AMD64 with Amd64. Update sysenter/sysenter with
2015 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2016 * i386-tbl.h: Regenerated.
2017
9fc0b501
SB		 20182020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2019
2020 PR 25469
2021 * z80-dis.c: Add support for GBZ80 opcodes.
2022
c5d7be0c
AM		 20232020-02-04 Alan Modra <amodra@gmail.com>
2024
2025 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2026
44e4546f
AM		 20272020-02-03 Alan Modra <amodra@gmail.com>
2028
2029 * m32c-ibld.c: Regenerate.
2030
b2b1453a
AM		 20312020-02-01 Alan Modra <amodra@gmail.com>
2032
2033 * frv-ibld.c: Regenerate.
2034
4102be5c
JB		 20352020-01-31 Jan Beulich <jbeulich@suse.com>
2036
2037 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2038 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2039 (OP_E_memory): Replace xmm_mdq_mode case label by
2040 vex_scalar_w_dq_mode one.
2041 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2042
825bd36c
JB		 20432020-01-31 Jan Beulich <jbeulich@suse.com>
2044
2045 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2046 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2047 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2048 (intel_operand_size): Drop vex_w_dq_mode case label.
2049
c3036ed0
RS		 20502020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2051
2052 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2053 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2054
0c115f84
AM		 20552020-01-30 Alan Modra <amodra@gmail.com>
2056
2057 * m32c-ibld.c: Regenerate.
2058
bd434cc4
JM		 20592020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2060
2061 * bpf-opc.c: Regenerate.
2062
aeab2b26
JB		 20632020-01-30 Jan Beulich <jbeulich@suse.com>
2064
2065 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2066 (dis386): Use them to replace C2/C3 table entries.
2067 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2068 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2069 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2070 * i386-tbl.h: Re-generate.
2071
62b3f548
JB		 20722020-01-30 Jan Beulich <jbeulich@suse.com>
2073
2074 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2075 forms.
2076 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2077 DefaultSize.
2078 * i386-tbl.h: Re-generate.
2079
1bd8ae10
AM		 20802020-01-30 Alan Modra <amodra@gmail.com>
2081
2082 * tic4x-dis.c (tic4x_dp): Make unsigned.
2083
bc31405e
L		 20842020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2085 Jan Beulich <jbeulich@suse.com>
2086
2087 PR binutils/25445
2088 * i386-dis.c (MOVSXD_Fixup): New function.
2089 (movsxd_mode): New enum.
2090 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2091 (intel_operand_size): Handle movsxd_mode.
2092 (OP_E_register): Likewise.
2093 (OP_G): Likewise.
2094 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2095 register on movsxd. Add movsxd with 16-bit destination register
2096 for AMD64 and Intel64 ISAs.
2097 * i386-tbl.h: Regenerated.
2098
7568c93b
TC		 20992020-01-27 Tamar Christina <tamar.christina@arm.com>
2100
2101 PR 25403
2102 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2103 * aarch64-asm-2.c: Regenerate
2104 * aarch64-dis-2.c: Likewise.
2105 * aarch64-opc-2.c: Likewise.
2106
c006a730
JB		 21072020-01-21 Jan Beulich <jbeulich@suse.com>
2108
2109 * i386-opc.tbl (sysret): Drop DefaultSize.
2110 * i386-tbl.h: Re-generate.
2111
c906a69a
JB		 21122020-01-21 Jan Beulich <jbeulich@suse.com>
2113
2114 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2115 Dword.
2116 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2117 * i386-tbl.h: Re-generate.
2118
26916852
NC		 21192020-01-20 Nick Clifton <nickc@redhat.com>
2120
2121 * po/de.po: Updated German translation.
2122 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2123 * po/uk.po: Updated Ukranian translation.
2124
4d6cbb64
AM		 21252020-01-20 Alan Modra <amodra@gmail.com>
2126
2127 * hppa-dis.c (fput_const): Remove useless cast.
2128
2bddb71a
AM		 21292020-01-20 Alan Modra <amodra@gmail.com>
2130
2131 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2132
1b1bb2c6
NC		 21332020-01-18 Nick Clifton <nickc@redhat.com>
2134
2135 * configure: Regenerate.
2136 * po/opcodes.pot: Regenerate.
2137
ae774686
NC		 21382020-01-18 Nick Clifton <nickc@redhat.com>
2139
2140 Binutils 2.34 branch created.
2141
07f1f3aa
CB		 21422020-01-17 Christian Biesinger <cbiesinger@google.com>
2143
2144 * opintl.h: Fix spelling error (seperate).
2145
42e04b36
L		 21462020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2147
2148 * i386-opc.tbl: Add {vex} pseudo prefix.
2149 * i386-tbl.h: Regenerated.
2150
2da2eaf4
AV		 21512020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2152
2153 PR 25376
2154 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2155 (neon_opcodes): Likewise.
2156 (select_arm_features): Make sure we enable MVE bits when selecting
2157 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2158 any architecture.
2159
d0849eed
JB		 21602020-01-16 Jan Beulich <jbeulich@suse.com>
2161
2162 * i386-opc.tbl: Drop stale comment from XOP section.
2163
9cf70a44
JB		 21642020-01-16 Jan Beulich <jbeulich@suse.com>
2165
2166 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2167 (extractps): Add VexWIG to SSE2AVX forms.
2168 * i386-tbl.h: Re-generate.
2169
4814632e
JB		 21702020-01-16 Jan Beulich <jbeulich@suse.com>
2171
2172 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2173 Size64 from and use VexW1 on SSE2AVX forms.
2174 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2175 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2176 * i386-tbl.h: Re-generate.
2177
aad09917
AM		 21782020-01-15 Alan Modra <amodra@gmail.com>
2179
2180 * tic4x-dis.c (tic4x_version): Make unsigned long.
2181 (optab, optab_special, registernames): New file scope vars.
2182 (tic4x_print_register): Set up registernames rather than
2183 malloc'd registertable.
2184 (tic4x_disassemble): Delete optable and optable_special. Use
2185 optab and optab_special instead. Throw away old optab,
2186 optab_special and registernames when info->mach changes.
2187
7a6bf3be
SB		 21882020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2189
2190 PR 25377
2191 * z80-dis.c (suffix): Use .db instruction to generate double
2192 prefix.
2193
ca1eaac0
AM		 21942020-01-14 Alan Modra <amodra@gmail.com>
2195
2196 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2197 values to unsigned before shifting.
2198
1d67fe3b
TT		 21992020-01-13 Thomas Troeger <tstroege@gmx.de>
2200
2201 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2202 flow instructions.
2203 (print_insn_thumb16, print_insn_thumb32): Likewise.
2204 (print_insn): Initialize the insn info.
2205 * i386-dis.c (print_insn): Initialize the insn info fields, and
2206 detect jumps.
2207
5e4f7e05
CZ		 22082012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2209
2210 * arc-opc.c (C_NE): Make it required.
2211
b9fe6b8a
CZ		 22122012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2213
2214 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2215 reserved register name.
2216
90dee485
AM		 22172020-01-13 Alan Modra <amodra@gmail.com>
2218
2219 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2220 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2221
febda64f
AM		 22222020-01-13 Alan Modra <amodra@gmail.com>
2223
2224 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2225 result of wasm_read_leb128 in a uint64_t and check that bits
2226 are not lost when copying to other locals. Use uint32_t for
2227 most locals. Use PRId64 when printing int64_t.
2228
df08b588
AM		 22292020-01-13 Alan Modra <amodra@gmail.com>
2230
2231 * score-dis.c: Formatting.
2232 * score7-dis.c: Formatting.
2233
b2c759ce
AM		 22342020-01-13 Alan Modra <amodra@gmail.com>
2235
2236 * score-dis.c (print_insn_score48): Use unsigned variables for
2237 unsigned values. Don't left shift negative values.
2238 (print_insn_score32): Likewise.
2239 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2240
5496abe1
AM		 22412020-01-13 Alan Modra <amodra@gmail.com>
2242
2243 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2244
202e762b
AM		 22452020-01-13 Alan Modra <amodra@gmail.com>
2246
2247 * fr30-ibld.c: Regenerate.
2248
7ef412cf
AM		 22492020-01-13 Alan Modra <amodra@gmail.com>
2250
2251 * xgate-dis.c (print_insn): Don't left shift signed value.
2252 (ripBits): Formatting, use 1u.
2253
7f578b95
AM		 22542020-01-10 Alan Modra <amodra@gmail.com>
2255
2256 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2257 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2258
441af85b
AM		 22592020-01-10 Alan Modra <amodra@gmail.com>
2260
2261 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2262 and XRREG value earlier to avoid a shift with negative exponent.
2263 * m10200-dis.c (disassemble): Similarly.
2264
bce58db4
NC		 22652020-01-09 Nick Clifton <nickc@redhat.com>
2266
2267 PR 25224
2268 * z80-dis.c (ld_ii_ii): Use correct cast.
2269
40c75bc8
SB		 22702020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2271
2272 PR 25224
2273 * z80-dis.c (ld_ii_ii): Use character constant when checking
2274 opcode byte value.
2275
d835a58b
JB		 22762020-01-09 Jan Beulich <jbeulich@suse.com>
2277
2278 * i386-dis.c (SEP_Fixup): New.
2279 (SEP): Define.
2280 (dis386_twobyte): Use it for sysenter/sysexit.
2281 (enum x86_64_isa): Change amd64 enumerator to value 1.
2282 (OP_J): Compare isa64 against intel64 instead of amd64.
2283 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2284 forms.
2285 * i386-tbl.h: Re-generate.
2286
030a2e78
AM		 22872020-01-08 Alan Modra <amodra@gmail.com>
2288
2289 * z8k-dis.c: Include libiberty.h
2290 (instr_data_s): Make max_fetched unsigned.
2291 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2292 Don't exceed byte_info bounds.
2293 (output_instr): Make num_bytes unsigned.
2294 (unpack_instr): Likewise for nibl_count and loop.
2295 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2296 idx unsigned.
2297 * z8k-opc.h: Regenerate.
2298
bb82aefe
SV		 22992020-01-07 Shahab Vahedi <shahab@synopsys.com>
2300
2301 * arc-tbl.h (llock): Use 'LLOCK' as class.
2302 (llockd): Likewise.
2303 (scond): Use 'SCOND' as class.
2304 (scondd): Likewise.
2305 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2306 (scondd): Likewise.
2307
cc6aa1a6
AM		 23082020-01-06 Alan Modra <amodra@gmail.com>
2309
2310 * m32c-ibld.c: Regenerate.
2311
660e62b1
AM		 23122020-01-06 Alan Modra <amodra@gmail.com>
2313
2314 PR 25344
2315 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2316 Peek at next byte to prevent recursion on repeated prefix bytes.
2317 Ensure uninitialised "mybuf" is not accessed.
2318 (print_insn_z80): Don't zero n_fetch and n_used here,..
2319 (print_insn_z80_buf): ..do it here instead.
2320
c9ae58fe
AM		 23212020-01-04 Alan Modra <amodra@gmail.com>
2322
2323 * m32r-ibld.c: Regenerate.
2324
5f57d4ec
AM		 23252020-01-04 Alan Modra <amodra@gmail.com>
2326
2327 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2328
2c5c1196
AM		 23292020-01-04 Alan Modra <amodra@gmail.com>
2330
2331 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2332
2e98c6c5
AM		 23332020-01-04 Alan Modra <amodra@gmail.com>
2334
2335 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2336
567dfba2
JB		 23372020-01-03 Jan Beulich <jbeulich@suse.com>
2338
5437a02a
JB		 2339 * aarch64-tbl.h (aarch64_opcode_table): Use
2340 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2341
23422020-01-03 Jan Beulich <jbeulich@suse.com>
2343
2344 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2345 forms of SUDOT and USDOT.
2346
8c45011a
JB		 23472020-01-03 Jan Beulich <jbeulich@suse.com>
2348
5437a02a 2349 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2350 uzip{1,2}.
2351 * opcodes/aarch64-dis-2.c: Re-generate.
2352
f4950f76
JB		 23532020-01-03 Jan Beulich <jbeulich@suse.com>
2354
5437a02a 2355 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2356 FMMLA encoding.
2357 * opcodes/aarch64-dis-2.c: Re-generate.
2358
6655dba2
SB		 23592020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2360
2361 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2362
b14ce8bf
AM		 23632020-01-01 Alan Modra <amodra@gmail.com>
2364
2365 Update year range in copyright notice of all files.
2366
0b114740 2367For older changes see ChangeLog-2019
3499769a 2368\f
0b114740 2369Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2370
2371Copying and distribution of this file, with or without modification,
2372are permitted in any medium without royalty provided the copyright
2373notice and this notice are preserved.
2374
2375Local Variables:
2376mode: change-log
2377left-margin: 8
2378fill-column: 74
2379version-control: never
2380End:
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