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* gdb.threads/killed.exp: Use KFAIL for gdb/568.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
80551777
CD		 12003-01-05 Richard Sandiford <rsandifo@redhat.com>
2
3 * Makefile.in (tmp-run-multi): Fix mips16 filter.
4
4c54fc26
CD		 52003-01-04 Richard Sandiford <rsandifo@redhat.com>
6 Andrew Cagney <ac131313@redhat.com>
7 Gavin Romig-Koch <gavin@redhat.com>
8 Graydon Hoare <graydon@redhat.com>
9 Aldy Hernandez <aldyh@redhat.com>
10 Dave Brolley <brolley@redhat.com>
11 Chris Demetriou <cgd@broadcom.com>
12
13 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
14 (sim_mach_default): New variable.
15 (mips64vr-*-*, mips64vrel-*-*): New configurations.
16 Add a new simulator generator, MULTI.
17 * configure: Regenerate.
18 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
19 (multi-run.o): New dependency.
20 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
21 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
22 (tmp-multi): Combine them.
23 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
24 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
25 (distclean-extra): New rule.
26 * sim-main.h: Include bfd.h.
27 (MIPS_MACH): New macro.
28 * mips.igen (vr4120, vr5400, vr5500): New models.
29 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
30 * vr.igen: Replace with new version.
31
e6c674b8
CD		 322003-01-04 Chris Demetriou <cgd@broadcom.com>
33
34 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
35 * configure: Regenerate.
36
28f50ac8
CD		 372002-12-31 Chris Demetriou <cgd@broadcom.com>
38
39 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
40 * mips.igen: Remove all invocations of check_branch_bug and
41 mark_branch_bug.
42
5071ffe6
CD		 432002-12-16 Chris Demetriou <cgd@broadcom.com>
44
45 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
46
06e7837e
CD		 472002-07-30 Chris Demetriou <cgd@broadcom.com>
48
49 * mips.igen (do_load_double, do_store_double): New functions.
50 (LDC1, SDC1): Rename to...
51 (LDC1b, SDC1b): respectively.
52 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
53
2265c243
MS		 542002-07-29 Michael Snyder <msnyder@redhat.com>
55
56 * cp1.c (fp_recip2): Modify initialization expression so that
57 GCC will recognize it as constant.
58
a2f8b4f3
CD		 592002-06-18 Chris Demetriou <cgd@broadcom.com>
60
61 * mdmx.c (SD_): Delete.
62 (Unpredictable): Re-define, for now, to directly invoke
63 unpredictable_action().
64 (mdmx_acc_op): Fix error in .ob immediate handling.
65
b4b6c939
AC		 662002-06-18 Andrew Cagney <cagney@redhat.com>
67
68 * interp.c (sim_firmware_command): Initialize `address'.
69
c8cca39f
AC		 702002-06-16 Andrew Cagney <ac131313@redhat.com>
71
72 * configure: Regenerated to track ../common/aclocal.m4 changes.
73
e7e81181
CD		 742002-06-14 Chris Demetriou <cgd@broadcom.com>
75 Ed Satterthwaite <ehs@broadcom.com>
76
77 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
78 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
79 * mips.igen: Include mips3d.igen.
80 (mips3d): New model name for MIPS-3D ASE instructions.
81 (CVT.W.fmt): Don't use this instruction for word (source) format
82 instructions.
83 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
84 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
85 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
86 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
87 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
88 (RSquareRoot1, RSquareRoot2): New macros.
89 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
90 (fp_rsqrt2): New functions.
91 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
92 * configure: Regenerate.
93
3a2b820e 942002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 95 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 96
97 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
98 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
99 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
100 (convert): Note that this function is not used for paired-single
101 format conversions.
102 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
103 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
104 (check_fmt_p): Enable paired-single support.
105 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
106 (PUU.PS): New instructions.
107 (CVT.S.fmt): Don't use this instruction for paired-single format
108 destinations.
109 * sim-main.h (FP_formats): New value 'fmt_ps.'
110 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
111 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
112
d18ea9c2
CD		 1132002-06-12 Chris Demetriou <cgd@broadcom.com>
114
115 * mips.igen: Fix formatting of function calls in
116 many FP operations.
117
95fd5cee
CD		 1182002-06-12 Chris Demetriou <cgd@broadcom.com>
119
120 * mips.igen (MOVN, MOVZ): Trace result.
121 (TNEI): Print "tnei" as the opcode name in traces.
122 (CEIL.W): Add disassembly string for traces.
123 (RSQRT.fmt): Make location of disassembly string consistent
124 with other instructions.
125
4f0d55ae
CD		 1262002-06-12 Chris Demetriou <cgd@broadcom.com>
127
128 * mips.igen (X): Delete unused function.
129
3c25f8c7
AC		 1302002-06-08 Andrew Cagney <cagney@redhat.com>
131
132 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
133
f3c08b7e
CD		 1342002-06-07 Chris Demetriou <cgd@broadcom.com>
135 Ed Satterthwaite <ehs@broadcom.com>
136
137 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
138 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
139 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
140 (fp_nmsub): New prototypes.
141 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
142 (NegMultiplySub): New defines.
143 * mips.igen (RSQRT.fmt): Use RSquareRoot().
144 (MADD.D, MADD.S): Replace with...
145 (MADD.fmt): New instruction.
146 (MSUB.D, MSUB.S): Replace with...
147 (MSUB.fmt): New instruction.
148 (NMADD.D, NMADD.S): Replace with...
149 (NMADD.fmt): New instruction.
150 (NMSUB.D, MSUB.S): Replace with...
151 (NMSUB.fmt): New instruction.
152
52714ff9
CD		 1532002-06-07 Chris Demetriou <cgd@broadcom.com>
154 Ed Satterthwaite <ehs@broadcom.com>
155
156 * cp1.c: Fix more comment spelling and formatting.
157 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
158 (denorm_mode): New function.
159 (fpu_unary, fpu_binary): Round results after operation, collect
160 status from rounding operations, and update the FCSR.
161 (convert): Collect status from integer conversions and rounding
162 operations, and update the FCSR. Adjust NaN values that result
163 from conversions. Convert to use sim_io_eprintf rather than
164 fprintf, and remove some debugging code.
165 * cp1.h (fenr_FS): New define.
166
577d8c4b
CD		 1672002-06-07 Chris Demetriou <cgd@broadcom.com>
168
169 * cp1.c (convert): Remove unusable debugging code, and move MIPS
170 rounding mode to sim FP rounding mode flag conversion code into...
171 (rounding_mode): New function.
172
196496ed
CD		 1732002-06-07 Chris Demetriou <cgd@broadcom.com>
174
175 * cp1.c: Clean up formatting of a few comments.
176 (value_fpr): Reformat switch statement.
177
cfe9ea23
CD		 1782002-06-06 Chris Demetriou <cgd@broadcom.com>
179 Ed Satterthwaite <ehs@broadcom.com>
180
181 * cp1.h: New file.
182 * sim-main.h: Include cp1.h.
183 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
184 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
185 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
186 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
187 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
188 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
189 * cp1.c: Don't include sim-fpu.h; already included by
190 sim-main.h. Clean up formatting of some comments.
191 (NaN, Equal, Less): Remove.
192 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
193 (fp_cmp): New functions.
194 * mips.igen (do_c_cond_fmt): Remove.
195 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
196 Compare. Add result tracing.
197 (CxC1): Remove, replace with...
198 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
199 (DMxC1): Remove, replace with...
200 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
201 (MxC1): Remove, replace with...
202 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
203
ee7254b0
CD		 2042002-06-04 Chris Demetriou <cgd@broadcom.com>
205
206 * sim-main.h (FGRIDX): Remove, replace all uses with...
207 (FGR_BASE): New macro.
208 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
209 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
210 (NR_FGR, FGR): Likewise.
211 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
212 * mips.igen: Likewise.
213
d3eb724f
CD		 2142002-06-04 Chris Demetriou <cgd@broadcom.com>
215
216 * cp1.c: Add an FSF Copyright notice to this file.
217
ba46ddd0
CD		 2182002-06-04 Chris Demetriou <cgd@broadcom.com>
219 Ed Satterthwaite <ehs@broadcom.com>
220
221 * cp1.c (Infinity): Remove.
222 * sim-main.h (Infinity): Likewise.
223
224 * cp1.c (fp_unary, fp_binary): New functions.
225 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
226 (fp_sqrt): New functions, implemented in terms of the above.
227 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
228 (Recip, SquareRoot): Remove (replaced by functions above).
229 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
230 (fp_recip, fp_sqrt): New prototypes.
231 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
232 (Recip, SquareRoot): Replace prototypes with #defines which
233 invoke the functions above.
234
18d8a52d
CD		 2352002-06-03 Chris Demetriou <cgd@broadcom.com>
236
237 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
238 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
239 file, remove PARAMS from prototypes.
240 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
241 simulator state arguments.
242 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
243 pass simulator state arguments.
244 * cp1.c (SD): Redefine as CPU_STATE(cpu).
245 (store_fpr, convert): Remove 'sd' argument.
246 (value_fpr): Likewise. Convert to use 'SD' instead.
247
0f154cbd
CD		 2482002-06-03 Chris Demetriou <cgd@broadcom.com>
249
250 * cp1.c (Min, Max): Remove #if 0'd functions.
251 * sim-main.h (Min, Max): Remove.
252
e80fc152
CD		 2532002-06-03 Chris Demetriou <cgd@broadcom.com>
254
255 * cp1.c: fix formatting of switch case and default labels.
256 * interp.c: Likewise.
257 * sim-main.c: Likewise.
258
bad673a9
CD		 2592002-06-03 Chris Demetriou <cgd@broadcom.com>
260
261 * cp1.c: Clean up comments which describe FP formats.
262 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
263
7cbea089
CD		 2642002-06-03 Chris Demetriou <cgd@broadcom.com>
265 Ed Satterthwaite <ehs@broadcom.com>
266
267 * configure.in (mipsisa64sb1*-*-*): New target for supporting
268 Broadcom SiByte SB-1 processor configurations.
269 * configure: Regenerate.
270 * sb1.igen: New file.
271 * mips.igen: Include sb1.igen.
272 (sb1): New model.
273 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
274 * mdmx.igen: Add "sb1" model to all appropriate functions and
275 instructions.
276 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
277 (ob_func, ob_acc): Reference the above.
278 (qh_acc): Adjust to keep the same size as ob_acc.
279 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
280 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
281
909daa82
CD		 2822002-06-03 Chris Demetriou <cgd@broadcom.com>
283
284 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
285
f4f1b9f1
CD		 2862002-06-02 Chris Demetriou <cgd@broadcom.com>
287 Ed Satterthwaite <ehs@broadcom.com>
288
289 * mips.igen (mdmx): New (pseudo-)model.
290 * mdmx.c, mdmx.igen: New files.
291 * Makefile.in (SIM_OBJS): Add mdmx.o.
292 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
293 New typedefs.
294 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
295 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
296 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
297 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
298 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
299 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
300 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
301 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
302 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
303 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
304 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
305 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
306 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
307 (qh_fmtsel): New macros.
308 (_sim_cpu): New member "acc".
309 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
310 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
311
5accf1ff
CD		 3122002-05-01 Chris Demetriou <cgd@broadcom.com>
313
314 * interp.c: Use 'deprecated' rather than 'depreciated.'
315 * sim-main.h: Likewise.
316
402586aa
CD		 3172002-05-01 Chris Demetriou <cgd@broadcom.com>
318
319 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
320 which wouldn't compile anyway.
321 * sim-main.h (unpredictable_action): New function prototype.
322 (Unpredictable): Define to call igen function unpredictable().
323 (NotWordValue): New macro to call igen function not_word_value().
324 (UndefinedResult): Remove.
325 * interp.c (undefined_result): Remove.
326 (unpredictable_action): New function.
327 * mips.igen (not_word_value, unpredictable): New functions.
328 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
329 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
330 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
331 NotWordValue() to check for unpredictable inputs, then
332 Unpredictable() to handle them.
333
c9b9995a
CD		 3342002-02-24 Chris Demetriou <cgd@broadcom.com>
335
336 * mips.igen: Fix formatting of calls to Unpredictable().
337
e1015982
AC		 3382002-04-20 Andrew Cagney <ac131313@redhat.com>
339
340 * interp.c (sim_open): Revert previous change.
341
b882a66b
AO		 3422002-04-18 Alexandre Oliva <aoliva@redhat.com>
343
344 * interp.c (sim_open): Disable chunk of code that wrote code in
345 vector table entries.
346
c429b7dd
CD		 3472002-03-19 Chris Demetriou <cgd@broadcom.com>
348
349 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
350 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
351 unused definitions.
352
37d146fa
CD		 3532002-03-19 Chris Demetriou <cgd@broadcom.com>
354
355 * cp1.c: Fix many formatting issues.
356
07892c0b
CD		 3572002-03-19 Chris G. Demetriou <cgd@broadcom.com>
358
359 * cp1.c (fpu_format_name): New function to replace...
360 (DOFMT): This. Delete, and update all callers.
361 (fpu_rounding_mode_name): New function to replace...
362 (RMMODE): This. Delete, and update all callers.
363
487f79b7
CD		 3642002-03-19 Chris G. Demetriou <cgd@broadcom.com>
365
366 * interp.c: Move FPU support routines from here to...
367 * cp1.c: Here. New file.
368 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
369 (cp1.o): New target.
370
1e799e28
CD		 3712002-03-12 Chris Demetriou <cgd@broadcom.com>
372
373 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
374 * mips.igen (mips32, mips64): New models, add to all instructions
375 and functions as appropriate.
376 (loadstore_ea, check_u64): New variant for model mips64.
377 (check_fmt_p): New variant for models mipsV and mips64, remove
378 mipsV model marking fro other variant.
379 (SLL) Rename to...
380 (SLLa) this.
381 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
382 for mips32 and mips64.
383 (DCLO, DCLZ): New instructions for mips64.
384
82f728db
CD		 3852002-03-07 Chris Demetriou <cgd@broadcom.com>
386
387 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
388 immediate or code as a hex value with the "%#lx" format.
389 (ANDI): Likewise, and fix printed instruction name.
390
b96e7ef1
CD		 3912002-03-05 Chris Demetriou <cgd@broadcom.com>
392
393 * sim-main.h (UndefinedResult, Unpredictable): New macros
394 which currently do nothing.
395
d35d4f70
CD		 3962002-03-05 Chris Demetriou <cgd@broadcom.com>
397
398 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
399 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
400 (status_CU3): New definitions.
401
402 * sim-main.h (ExceptionCause): Add new values for MIPS32
403 and MIPS64: MDMX, MCheck, CacheErr. Update comments
404 for DebugBreakPoint and NMIReset to note their status in
405 MIPS32 and MIPS64.
406 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
407 (SignalExceptionCacheErr): New exception macros.
408
3ad6f714
CD		 4092002-03-05 Chris Demetriou <cgd@broadcom.com>
410
411 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
412 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
413 is always enabled.
414 (SignalExceptionCoProcessorUnusable): Take as argument the
415 unusable coprocessor number.
416
86b77b47
CD		 4172002-03-05 Chris Demetriou <cgd@broadcom.com>
418
419 * mips.igen: Fix formatting of all SignalException calls.
420
97a88e93 4212002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 422
423 * sim-main.h (SIGNEXTEND): Remove.
424
97a88e93 4252002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 426
427 * mips.igen: Remove gencode comment from top of file, fix
428 spelling in another comment.
429
97a88e93 4302002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 431
432 * mips.igen (check_fmt, check_fmt_p): New functions to check
433 whether specific floating point formats are usable.
434 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
435 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
436 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
437 Use the new functions.
438 (do_c_cond_fmt): Remove format checks...
439 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
440
97a88e93 4412002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 442
443 * mips.igen: Fix formatting of check_fpu calls.
444
41774c9d
CD		 4452002-03-03 Chris Demetriou <cgd@broadcom.com>
446
447 * mips.igen (FLOOR.L.fmt): Store correct destination register.
448
4a0bd876
CD		 4492002-03-03 Chris Demetriou <cgd@broadcom.com>
450
451 * mips.igen: Remove whitespace at end of lines.
452
09297648
CD		 4532002-03-02 Chris Demetriou <cgd@broadcom.com>
454
455 * mips.igen (loadstore_ea): New function to do effective
456 address calculations.
457 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
458 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
459 CACHE): Use loadstore_ea to do effective address computations.
460
043b7057
CD		 4612002-03-02 Chris Demetriou <cgd@broadcom.com>
462
463 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
464 * mips.igen (LL, CxC1, MxC1): Likewise.
465
c1e8ada4
CD		 4662002-03-02 Chris Demetriou <cgd@broadcom.com>
467
468 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
469 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
470 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
471 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
472 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
473 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
474 Don't split opcode fields by hand, use the opcode field values
475 provided by igen.
476
3e1dca16
CD		 4772002-03-01 Chris Demetriou <cgd@broadcom.com>
478
479 * mips.igen (do_divu): Fix spacing.
480
481 * mips.igen (do_dsllv): Move to be right before DSLLV,
482 to match the rest of the do_<shift> functions.
483
fff8d27d
CD		 4842002-03-01 Chris Demetriou <cgd@broadcom.com>
485
486 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
487 DSRL32, do_dsrlv): Trace inputs and results.
488
0d3e762b
CD		 4892002-03-01 Chris Demetriou <cgd@broadcom.com>
490
491 * mips.igen (CACHE): Provide instruction-printing string.
492
493 * interp.c (signal_exception): Comment tokens after #endif.
494
eb5fcf93
CD		 4952002-02-28 Chris Demetriou <cgd@broadcom.com>
496
497 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
498 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
499 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
500 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
501 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
502 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
503 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
504 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
505
bb22bd7d
CD		 5062002-02-28 Chris Demetriou <cgd@broadcom.com>
507
508 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
509 instruction-printing string.
510 (LWU): Use '64' as the filter flag.
511
91a177cf
CD		 5122002-02-28 Chris Demetriou <cgd@broadcom.com>
513
514 * mips.igen (SDXC1): Fix instruction-printing string.
515
387f484a
CD		 5162002-02-28 Chris Demetriou <cgd@broadcom.com>
517
518 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
519 filter flags "32,f".
520
3d81f391
CD		 5212002-02-27 Chris Demetriou <cgd@broadcom.com>
522
523 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
524 as the filter flag.
525
af5107af
CD		 5262002-02-27 Chris Demetriou <cgd@broadcom.com>
527
528 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
529 add a comma) so that it more closely match the MIPS ISA
530 documentation opcode partitioning.
531 (PREF): Put useful names on opcode fields, and include
532 instruction-printing string.
533
ca971540
CD		 5342002-02-27 Chris Demetriou <cgd@broadcom.com>
535
536 * mips.igen (check_u64): New function which in the future will
537 check whether 64-bit instructions are usable and signal an
538 exception if not. Currently a no-op.
539 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
540 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
541 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
542 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
543
544 * mips.igen (check_fpu): New function which in the future will
545 check whether FPU instructions are usable and signal an exception
546 if not. Currently a no-op.
547 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
548 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
549 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
550 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
551 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
552 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
553 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
554 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
555
1c47a468
CD		 5562002-02-27 Chris Demetriou <cgd@broadcom.com>
557
558 * mips.igen (do_load_left, do_load_right): Move to be immediately
559 following do_load.
560 (do_store_left, do_store_right): Move to be immediately following
561 do_store.
562
603a98e7
CD		 5632002-02-27 Chris Demetriou <cgd@broadcom.com>
564
565 * mips.igen (mipsV): New model name. Also, add it to
566 all instructions and functions where it is appropriate.
567
c5d00cc7
CD		 5682002-02-18 Chris Demetriou <cgd@broadcom.com>
569
570 * mips.igen: For all functions and instructions, list model
571 names that support that instruction one per line.
572
074e9cb8
CD		 5732002-02-11 Chris Demetriou <cgd@broadcom.com>
574
575 * mips.igen: Add some additional comments about supported
576 models, and about which instructions go where.
577 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
578 order as is used in the rest of the file.
579
9805e229
CD		 5802002-02-11 Chris Demetriou <cgd@broadcom.com>
581
582 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
583 indicating that ALU32_END or ALU64_END are there to check
584 for overflow.
585 (DADD): Likewise, but also remove previous comment about
586 overflow checking.
587
f701dad2
CD		 5882002-02-10 Chris Demetriou <cgd@broadcom.com>
589
590 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
591 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
592 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
593 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
594 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
595 fields (i.e., add and move commas) so that they more closely
596 match the MIPS ISA documentation opcode partitioning.
597
5982002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 599
600 * mips.igen (ADDI): Print immediate value.
601 (BREAK): Print code.
602 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
603 (SLL): Print "nop" specially, and don't run the code
604 that does the shift for the "nop" case.
605
9e52972e
FF		 6062001-11-17 Fred Fish <fnf@redhat.com>
607
608 * sim-main.h (float_operation): Move enum declaration outside
609 of _sim_cpu struct declaration.
610
c0efbca4
JB		 6112001-04-12 Jim Blandy <jimb@redhat.com>
612
613 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
614 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
615 set of the FCSR.
616 * sim-main.h (COCIDX): Remove definition; this isn't supported by
617 PENDING_FILL, and you can get the intended effect gracefully by
618 calling PENDING_SCHED directly.
619
fb891446
BE		 6202001-02-23 Ben Elliston <bje@redhat.com>
621
622 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
623 already defined elsewhere.
624
8030f857
BE		 6252001-02-19 Ben Elliston <bje@redhat.com>
626
627 * sim-main.h (sim_monitor): Return an int.
628 * interp.c (sim_monitor): Add return values.
629 (signal_exception): Handle error conditions from sim_monitor.
630
56b48a7a
CD		 6312001-02-08 Ben Elliston <bje@redhat.com>
632
633 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
634 (store_memory): Likewise, pass cia to sim_core_write*.
635
d3ee60d9
FCE		 6362000-10-19 Frank Ch. Eigler <fche@redhat.com>
637
638 On advice from Chris G. Demetriou <cgd@sibyte.com>:
639 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
640
071da002
AC		 641Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
642
643 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
644 * Makefile.in: Don't delete *.igen when cleaning directory.
645
a28c02cd
AC		 646Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
647
648 * m16.igen (break): Call SignalException not sim_engine_halt.
649
80ee11fa
AC		 650Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
651
652 From Jason Eckhardt:
653 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
654
673388c0
AC		 655Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
656
657 * mips.igen (MxC1, DMxC1): Fix printf formatting.
658
4c0deff4
NC		 6592000-05-24 Michael Hayes <mhayes@cygnus.com>
660
661 * mips.igen (do_dmultx): Fix typo.
662
eb2d80b4
AC		 663Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
664
665 * configure: Regenerated to track ../common/aclocal.m4 changes.
666
dd37a34b
AC		 667Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
668
669 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
670
4c0deff4
NC		 6712000-04-12 Frank Ch. Eigler <fche@redhat.com>
672
673 * sim-main.h (GPR_CLEAR): Define macro.
674
e30db738
AC		 675Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
676
677 * interp.c (decode_coproc): Output long using %lx and not %s.
678
cb7450ea
FCE		 6792000-03-21 Frank Ch. Eigler <fche@redhat.com>
680
681 * interp.c (sim_open): Sort & extend dummy memory regions for
682 --board=jmr3904 for eCos.
683
a3027dd7
FCE		 6842000-03-02 Frank Ch. Eigler <fche@redhat.com>
685
686 * configure: Regenerated.
687
688Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
689
690 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
691 calls, conditional on the simulator being in verbose mode.
692
dfcd3bfb
JM		 693Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
694
695 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
696 cache don't get ReservedInstruction traps.
697
c2d11a7d
JM		 6981999-11-29 Mark Salter <msalter@cygnus.com>
699
700 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
701 to clear status bits in sdisr register. This is how the hardware works.
702
703 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
704 being used by cygmon.
705
4ce44c66
JM		 7061999-11-11 Andrew Haley <aph@cygnus.com>
707
708 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
709 instructions.
710
cff3e48b
JM		 711Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
712
713 * mips.igen (MULT): Correct previous mis-applied patch.
714
d4f3574e
SS		 715Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
716
717 * mips.igen (delayslot32): Handle sequence like
718 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
719 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
720 (MULT): Actually pass the third register...
721
7221999-09-03 Mark Salter <msalter@cygnus.com>
723
724 * interp.c (sim_open): Added more memory aliases for additional
725 hardware being touched by cygmon on jmr3904 board.
726
727Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
728
729 * configure: Regenerated to track ../common/aclocal.m4 changes.
730
a0b3c4fd
JM		 731Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
732
733 * interp.c (sim_store_register): Handle case where client - GDB -
734 specifies that a 4 byte register is 8 bytes in size.
735 (sim_fetch_register): Ditto.
736
adf40b2e
JM		 7371999-07-14 Frank Ch. Eigler <fche@cygnus.com>
738
739 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
740 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
741 (idt_monitor_base): Base address for IDT monitor traps.
742 (pmon_monitor_base): Ditto for PMON.
743 (lsipmon_monitor_base): Ditto for LSI PMON.
744 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
745 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
746 (sim_firmware_command): New function.
747 (mips_option_handler): Call it for OPTION_FIRMWARE.
748 (sim_open): Allocate memory for idt_monitor region. If "--board"
749 option was given, add no monitor by default. Add BREAK hooks only if
750 monitors are also there.
751
43e526b9
JM		 752Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
753
754 * interp.c (sim_monitor): Flush output before reading input.
755
756Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
757
758 * tconfig.in (SIM_HANDLES_LMA): Always define.
759
760Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
761
762 From Mark Salter <msalter@cygnus.com>:
763 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
764 (sim_open): Add setup for BSP board.
765
9846de1b
JM		 766Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
767
768 * mips.igen (MULT, MULTU): Add syntax for two operand version.
769 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
770 them as unimplemented.
771
cd0fc7c3
SS		 7721999-05-08 Felix Lee <flee@cygnus.com>
773
774 * configure: Regenerated to track ../common/aclocal.m4 changes.
775
7a292a7a
SS		 7761999-04-21 Frank Ch. Eigler <fche@cygnus.com>
777
778 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
779
780Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
781
782 * configure.in: Any mips64vr5*-*-* target should have
783 -DTARGET_ENABLE_FR=1.
784 (default_endian): Any mips64vr*el-*-* target should default to
785 LITTLE_ENDIAN.
786 * configure: Re-generate.
787
7881999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
789
790 * mips.igen (ldl): Extend from _16_, not 32.
791
792Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
793
794 * interp.c (sim_store_register): Force registers written to by GDB
795 into an un-interpreted state.
796
c906108c
SS		 7971999-02-05 Frank Ch. Eigler <fche@cygnus.com>
798
799 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
800 CPU, start periodic background I/O polls.
801 (tx3904sio_poll): New function: periodic I/O poller.
802
8031998-12-30 Frank Ch. Eigler <fche@cygnus.com>
804
805 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
806
807Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
808
809 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
810 case statement.
811
8121998-12-29 Frank Ch. Eigler <fche@cygnus.com>
813
814 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
815 (load_word): Call SIM_CORE_SIGNAL hook on error.
816 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
817 starting. For exception dispatching, pass PC instead of NULL_CIA.
818 (decode_coproc): Use COP0_BADVADDR to store faulting address.
819 * sim-main.h (COP0_BADVADDR): Define.
820 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
821 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
822 (_sim_cpu): Add exc_* fields to store register value snapshots.
823 * mips.igen (*): Replace memory-related SignalException* calls
824 with references to SIM_CORE_SIGNAL hook.
825
826 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
827 fix.
828 * sim-main.c (*): Minor warning cleanups.
829
8301998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
831
832 * m16.igen (DADDIU5): Correct type-o.
833
834Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
835
836 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
837 variables.
838
839Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
840
841 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
842 to include path.
843 (interp.o): Add dependency on itable.h
844 (oengine.c, gencode): Delete remaining references.
845 (BUILT_SRC_FROM_GEN): Clean up.
846
8471998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
848
849 * vr4run.c: New.
850 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
851 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
852 tmp-run-hack) : New.
853 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
854 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
855 Drop the "64" qualifier to get the HACK generator working.
856 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
857 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
858 qualifier to get the hack generator working.
859 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
860 (DSLL): Use do_dsll.
861 (DSLLV): Use do_dsllv.
862 (DSRA): Use do_dsra.
863 (DSRL): Use do_dsrl.
864 (DSRLV): Use do_dsrlv.
865 (BC1): Move *vr4100 to get the HACK generator working.
866 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
867 get the HACK generator working.
868 (MACC) Rename to get the HACK generator working.
869 (DMACC,MACCS,DMACCS): Add the 64.
870
8711998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
872
873 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
874 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
875
8761998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
877
878 * mips/interp.c (DEBUG): Cleanups.
879
8801998-12-10 Frank Ch. Eigler <fche@cygnus.com>
881
882 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
883 (tx3904sio_tickle): fflush after a stdout character output.
884
8851998-12-03 Frank Ch. Eigler <fche@cygnus.com>
886
887 * interp.c (sim_close): Uninstall modules.
888
889Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
890
891 * sim-main.h, interp.c (sim_monitor): Change to global
892 function.
893
894Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
895
896 * configure.in (vr4100): Only include vr4100 instructions in
897 simulator.
898 * configure: Re-generate.
899 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
900
901Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
902
903 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
904 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
905 true alternative.
906
907 * configure.in (sim_default_gen, sim_use_gen): Replace with
908 sim_gen.
909 (--enable-sim-igen): Delete config option. Always using IGEN.
910 * configure: Re-generate.
911
912 * Makefile.in (gencode): Kill, kill, kill.
913 * gencode.c: Ditto.
914
915Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
916
917 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
918 bit mips16 igen simulator.
919 * configure: Re-generate.
920
921 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
922 as part of vr4100 ISA.
923 * vr.igen: Mark all instructions as 64 bit only.
924
925Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
926
927 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
928 Pacify GCC.
929
930Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
931
932 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
933 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
934 * configure: Re-generate.
935
936 * m16.igen (BREAK): Define breakpoint instruction.
937 (JALX32): Mark instruction as mips16 and not r3900.
938 * mips.igen (C.cond.fmt): Fix typo in instruction format.
939
940 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
941
942Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
943
944 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
945 insn as a debug breakpoint.
946
947 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
948 pending.slot_size.
949 (PENDING_SCHED): Clean up trace statement.
950 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
951 (PENDING_FILL): Delay write by only one cycle.
952 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
953
954 * sim-main.c (pending_tick): Clean up trace statements. Add trace
955 of pending writes.
956 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
957 32 & 64.
958 (pending_tick): Move incrementing of index to FOR statement.
959 (pending_tick): Only update PENDING_OUT after a write has occured.
960
961 * configure.in: Add explicit mips-lsi-* target. Use gencode to
962 build simulator.
963 * configure: Re-generate.
964
965 * interp.c (sim_engine_run OLD): Delete explicit call to
966 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
967
968Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
969
970 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
971 interrupt level number to match changed SignalExceptionInterrupt
972 macro.
973
974Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
975
976 * interp.c: #include "itable.h" if WITH_IGEN.
977 (get_insn_name): New function.
978 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
979 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
980
981Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
982
983 * configure: Rebuilt to inhale new common/aclocal.m4.
984
985Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
986
987 * dv-tx3904sio.c: Include sim-assert.h.
988
989Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
990
991 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
992 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
993 Reorganize target-specific sim-hardware checks.
994 * configure: rebuilt.
995 * interp.c (sim_open): For tx39 target boards, set
996 OPERATING_ENVIRONMENT, add tx3904sio devices.
997 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
998 ROM executables. Install dv-sockser into sim-modules list.
999
1000 * dv-tx3904irc.c: Compiler warning clean-up.
1001 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1002 frequent hw-trace messages.
1003
1004Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1005
1006 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1007
1008Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1009
1010 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1011
1012 * vr.igen: New file.
1013 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1014 * mips.igen: Define vr4100 model. Include vr.igen.
1015Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1016
1017 * mips.igen (check_mf_hilo): Correct check.
1018
1019Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1020
1021 * sim-main.h (interrupt_event): Add prototype.
1022
1023 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1024 register_ptr, register_value.
1025 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1026
1027 * sim-main.h (tracefh): Make extern.
1028
1029Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1030
1031 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1032 Reduce unnecessarily high timer event frequency.
1033 * dv-tx3904cpu.c: Ditto for interrupt event.
1034
1035Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1036
1037 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1038 to allay warnings.
1039 (interrupt_event): Made non-static.
1040
1041 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1042 interchange of configuration values for external vs. internal
1043 clock dividers.
1044
1045Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1046
1047 * mips.igen (BREAK): Moved code to here for
1048 simulator-reserved break instructions.
1049 * gencode.c (build_instruction): Ditto.
1050 * interp.c (signal_exception): Code moved from here. Non-
1051 reserved instructions now use exception vector, rather
1052 than halting sim.
1053 * sim-main.h: Moved magic constants to here.
1054
1055Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1056
1057 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1058 register upon non-zero interrupt event level, clear upon zero
1059 event value.
1060 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1061 by passing zero event value.
1062 (*_io_{read,write}_buffer): Endianness fixes.
1063 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1064 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1065
1066 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1067 serial I/O and timer module at base address 0xFFFF0000.
1068
1069Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1070
1071 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1072 and BigEndianCPU.
1073
1074Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1075
1076 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1077 parts.
1078 * configure: Update.
1079
1080Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1081
1082 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1083 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1084 * configure.in: Include tx3904tmr in hw_device list.
1085 * configure: Rebuilt.
1086 * interp.c (sim_open): Instantiate three timer instances.
1087 Fix address typo of tx3904irc instance.
1088
1089Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1090
1091 * interp.c (signal_exception): SystemCall exception now uses
1092 the exception vector.
1093
1094Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1095
1096 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1097 to allay warnings.
1098
1099Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1100
1101 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1102
1103Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1106
1107 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1108 sim-main.h. Declare a struct hw_descriptor instead of struct
1109 hw_device_descriptor.
1110
1111Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1112
1113 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1114 right bits and then re-align left hand bytes to correct byte
1115 lanes. Fix incorrect computation in do_store_left when loading
1116 bytes from second word.
1117
1118Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1119
1120 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1121 * interp.c (sim_open): Only create a device tree when HW is
1122 enabled.
1123
1124 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1125 * interp.c (signal_exception): Ditto.
1126
1127Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1128
1129 * gencode.c: Mark BEGEZALL as LIKELY.
1130
1131Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1132
1133 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1134 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1135
1136Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1137
1138 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1139 modules. Recognize TX39 target with "mips*tx39" pattern.
1140 * configure: Rebuilt.
1141 * sim-main.h (*): Added many macros defining bits in
1142 TX39 control registers.
1143 (SignalInterrupt): Send actual PC instead of NULL.
1144 (SignalNMIReset): New exception type.
1145 * interp.c (board): New variable for future use to identify
1146 a particular board being simulated.
1147 (mips_option_handler,mips_options): Added "--board" option.
1148 (interrupt_event): Send actual PC.
1149 (sim_open): Make memory layout conditional on board setting.
1150 (signal_exception): Initial implementation of hardware interrupt
1151 handling. Accept another break instruction variant for simulator
1152 exit.
1153 (decode_coproc): Implement RFE instruction for TX39.
1154 (mips.igen): Decode RFE instruction as such.
1155 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1156 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1157 bbegin to implement memory map.
1158 * dv-tx3904cpu.c: New file.
1159 * dv-tx3904irc.c: New file.
1160
1161Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1162
1163 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1164
1165Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1166
1167 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1168 with calls to check_div_hilo.
1169
1170Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1171
1172 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1173 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1174 Add special r3900 version of do_mult_hilo.
1175 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1176 with calls to check_mult_hilo.
1177 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1178 with calls to check_div_hilo.
1179
1180Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1181
1182 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1183 Document a replacement.
1184
1185Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1186
1187 * interp.c (sim_monitor): Make mon_printf work.
1188
1189Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1190
1191 * sim-main.h (INSN_NAME): New arg `cpu'.
1192
1193Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1194
1195 * configure: Regenerated to track ../common/aclocal.m4 changes.
1196
1197Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1198
1199 * configure: Regenerated to track ../common/aclocal.m4 changes.
1200 * config.in: Ditto.
1201
1202Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1203
1204 * acconfig.h: New file.
1205 * configure.in: Reverted change of Apr 24; use sinclude again.
1206
1207Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1208
1209 * configure: Regenerated to track ../common/aclocal.m4 changes.
1210 * config.in: Ditto.
1211
1212Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1213
1214 * configure.in: Don't call sinclude.
1215
1216Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1217
1218 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1219
1220Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1221
1222 * mips.igen (ERET): Implement.
1223
1224 * interp.c (decode_coproc): Return sign-extended EPC.
1225
1226 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1227
1228 * interp.c (signal_exception): Do not ignore Trap.
1229 (signal_exception): On TRAP, restart at exception address.
1230 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1231 (signal_exception): Update.
1232 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1233 so that TRAP instructions are caught.
1234
1235Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1236
1237 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1238 contains HI/LO access history.
1239 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1240 (HIACCESS, LOACCESS): Delete, replace with
1241 (HIHISTORY, LOHISTORY): New macros.
1242 (CHECKHILO): Delete all, moved to mips.igen
1243
1244 * gencode.c (build_instruction): Do not generate checks for
1245 correct HI/LO register usage.
1246
1247 * interp.c (old_engine_run): Delete checks for correct HI/LO
1248 register usage.
1249
1250 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1251 check_mf_cycles): New functions.
1252 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1253 do_divu, domultx, do_mult, do_multu): Use.
1254
1255 * tx.igen ("madd", "maddu"): Use.
1256
1257Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1258
1259 * mips.igen (DSRAV): Use function do_dsrav.
1260 (SRAV): Use new function do_srav.
1261
1262 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1263 (B): Sign extend 11 bit immediate.
1264 (EXT-B*): Shift 16 bit immediate left by 1.
1265 (ADDIU*): Don't sign extend immediate value.
1266
1267Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1268
1269 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1270
1271 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1272 functions.
1273
1274 * mips.igen (delayslot32, nullify_next_insn): New functions.
1275 (m16.igen): Always include.
1276 (do_*): Add more tracing.
1277
1278 * m16.igen (delayslot16): Add NIA argument, could be called by a
1279 32 bit MIPS16 instruction.
1280
1281 * interp.c (ifetch16): Move function from here.
1282 * sim-main.c (ifetch16): To here.
1283
1284 * sim-main.c (ifetch16, ifetch32): Update to match current
1285 implementations of LH, LW.
1286 (signal_exception): Don't print out incorrect hex value of illegal
1287 instruction.
1288
1289Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1290
1291 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1292 instruction.
1293
1294 * m16.igen: Implement MIPS16 instructions.
1295
1296 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1297 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1298 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1299 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1300 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1301 bodies of corresponding code from 32 bit insn to these. Also used
1302 by MIPS16 versions of functions.
1303
1304 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1305 (IMEM16): Drop NR argument from macro.
1306
1307Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1308
1309 * Makefile.in (SIM_OBJS): Add sim-main.o.
1310
1311 * sim-main.h (address_translation, load_memory, store_memory,
1312 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1313 as INLINE_SIM_MAIN.
1314 (pr_addr, pr_uword64): Declare.
1315 (sim-main.c): Include when H_REVEALS_MODULE_P.
1316
1317 * interp.c (address_translation, load_memory, store_memory,
1318 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1319 from here.
1320 * sim-main.c: To here. Fix compilation problems.
1321
1322 * configure.in: Enable inlining.
1323 * configure: Re-config.
1324
1325Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * configure: Regenerated to track ../common/aclocal.m4 changes.
1328
1329Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1330
1331 * mips.igen: Include tx.igen.
1332 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1333 * tx.igen: New file, contains MADD and MADDU.
1334
1335 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1336 the hardwired constant `7'.
1337 (store_memory): Ditto.
1338 (LOADDRMASK): Move definition to sim-main.h.
1339
1340 mips.igen (MTC0): Enable for r3900.
1341 (ADDU): Add trace.
1342
1343 mips.igen (do_load_byte): Delete.
1344 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1345 do_store_right): New functions.
1346 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1347
1348 configure.in: Let the tx39 use igen again.
1349 configure: Update.
1350
1351Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1352
1353 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1354 not an address sized quantity. Return zero for cache sizes.
1355
1356Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1357
1358 * mips.igen (r3900): r3900 does not support 64 bit integer
1359 operations.
1360
1361Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1362
1363 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1364 than igen one.
1365 * configure : Rebuild.
1366
1367Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1368
1369 * configure: Regenerated to track ../common/aclocal.m4 changes.
1370
1371Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1372
1373 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1374
1375Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1376
1377 * configure: Regenerated to track ../common/aclocal.m4 changes.
1378 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1379
1380Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * configure: Regenerated to track ../common/aclocal.m4 changes.
1383
1384Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * interp.c (Max, Min): Comment out functions. Not yet used.
1387
1388Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1389
1390 * configure: Regenerated to track ../common/aclocal.m4 changes.
1391
1392Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1393
1394 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1395 configurable settings for stand-alone simulator.
1396
1397 * configure.in: Added X11 search, just in case.
1398
1399 * configure: Regenerated.
1400
1401Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * interp.c (sim_write, sim_read, load_memory, store_memory):
1404 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1405
1406Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1407
1408 * sim-main.h (GETFCC): Return an unsigned value.
1409
1410Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1413 (DADD): Result destination is RD not RT.
1414
1415Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1416
1417 * sim-main.h (HIACCESS, LOACCESS): Always define.
1418
1419 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1420
1421 * interp.c (sim_info): Delete.
1422
1423Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1424
1425 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1426 (mips_option_handler): New argument `cpu'.
1427 (sim_open): Update call to sim_add_option_table.
1428
1429Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1430
1431 * mips.igen (CxC1): Add tracing.
1432
1433Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * sim-main.h (Max, Min): Declare.
1436
1437 * interp.c (Max, Min): New functions.
1438
1439 * mips.igen (BC1): Add tracing.
1440
1441Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1442
1443 * interp.c Added memory map for stack in vr4100
1444
1445Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1446
1447 * interp.c (load_memory): Add missing "break"'s.
1448
1449Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1450
1451 * interp.c (sim_store_register, sim_fetch_register): Pass in
1452 length parameter. Return -1.
1453
1454Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1455
1456 * interp.c: Added hardware init hook, fixed warnings.
1457
1458Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459
1460 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1461
1462Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * interp.c (ifetch16): New function.
1465
1466 * sim-main.h (IMEM32): Rename IMEM.
1467 (IMEM16_IMMED): Define.
1468 (IMEM16): Define.
1469 (DELAY_SLOT): Update.
1470
1471 * m16run.c (sim_engine_run): New file.
1472
1473 * m16.igen: All instructions except LB.
1474 (LB): Call do_load_byte.
1475 * mips.igen (do_load_byte): New function.
1476 (LB): Call do_load_byte.
1477
1478 * mips.igen: Move spec for insn bit size and high bit from here.
1479 * Makefile.in (tmp-igen, tmp-m16): To here.
1480
1481 * m16.dc: New file, decode mips16 instructions.
1482
1483 * Makefile.in (SIM_NO_ALL): Define.
1484 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1485
1486Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1489 point unit to 32 bit registers.
1490 * configure: Re-generate.
1491
1492Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1493
1494 * configure.in (sim_use_gen): Make IGEN the default simulator
1495 generator for generic 32 and 64 bit mips targets.
1496 * configure: Re-generate.
1497
1498Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1501 bitsize.
1502
1503 * interp.c (sim_fetch_register, sim_store_register): Read/write
1504 FGR from correct location.
1505 (sim_open): Set size of FGR's according to
1506 WITH_TARGET_FLOATING_POINT_BITSIZE.
1507
1508 * sim-main.h (FGR): Store floating point registers in a separate
1509 array.
1510
1511Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * configure: Regenerated to track ../common/aclocal.m4 changes.
1514
1515Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1518
1519 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1520
1521 * interp.c (pending_tick): New function. Deliver pending writes.
1522
1523 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1524 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1525 it can handle mixed sized quantites and single bits.
1526
1527Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1528
1529 * interp.c (oengine.h): Do not include when building with IGEN.
1530 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1531 (sim_info): Ditto for PROCESSOR_64BIT.
1532 (sim_monitor): Replace ut_reg with unsigned_word.
1533 (*): Ditto for t_reg.
1534 (LOADDRMASK): Define.
1535 (sim_open): Remove defunct check that host FP is IEEE compliant,
1536 using software to emulate floating point.
1537 (value_fpr, ...): Always compile, was conditional on HASFPU.
1538
1539Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1542 size.
1543
1544 * interp.c (SD, CPU): Define.
1545 (mips_option_handler): Set flags in each CPU.
1546 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1547 (sim_close): Do not clear STATE, deleted anyway.
1548 (sim_write, sim_read): Assume CPU zero's vm should be used for
1549 data transfers.
1550 (sim_create_inferior): Set the PC for all processors.
1551 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1552 argument.
1553 (mips16_entry): Pass correct nr of args to store_word, load_word.
1554 (ColdReset): Cold reset all cpu's.
1555 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1556 (sim_monitor, load_memory, store_memory, signal_exception): Use
1557 `CPU' instead of STATE_CPU.
1558
1559
1560 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1561 SD or CPU_.
1562
1563 * sim-main.h (signal_exception): Add sim_cpu arg.
1564 (SignalException*): Pass both SD and CPU to signal_exception.
1565 * interp.c (signal_exception): Update.
1566
1567 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1568 Ditto
1569 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1570 address_translation): Ditto
1571 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1572
1573Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1574
1575 * configure: Regenerated to track ../common/aclocal.m4 changes.
1576
1577Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1580
1581 * mips.igen (model): Map processor names onto BFD name.
1582
1583 * sim-main.h (CPU_CIA): Delete.
1584 (SET_CIA, GET_CIA): Define
1585
1586Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1587
1588 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1589 regiser.
1590
1591 * configure.in (default_endian): Configure a big-endian simulator
1592 by default.
1593 * configure: Re-generate.
1594
1595Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1596
1597 * configure: Regenerated to track ../common/aclocal.m4 changes.
1598
1599Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1600
1601 * interp.c (sim_monitor): Handle Densan monitor outbyte
1602 and inbyte functions.
1603
16041997-12-29 Felix Lee <flee@cygnus.com>
1605
1606 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1607
1608Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1609
1610 * Makefile.in (tmp-igen): Arrange for $zero to always be
1611 reset to zero after every instruction.
1612
1613Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * configure: Regenerated to track ../common/aclocal.m4 changes.
1616 * config.in: Ditto.
1617
1618Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1619
1620 * mips.igen (MSUB): Fix to work like MADD.
1621 * gencode.c (MSUB): Similarly.
1622
1623Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1624
1625 * configure: Regenerated to track ../common/aclocal.m4 changes.
1626
1627Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1628
1629 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1630
1631Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * sim-main.h (sim-fpu.h): Include.
1634
1635 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1636 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1637 using host independant sim_fpu module.
1638
1639Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * interp.c (signal_exception): Report internal errors with SIGABRT
1642 not SIGQUIT.
1643
1644 * sim-main.h (C0_CONFIG): New register.
1645 (signal.h): No longer include.
1646
1647 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1648
1649Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1650
1651 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1652
1653Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1654
1655 * mips.igen: Tag vr5000 instructions.
1656 (ANDI): Was missing mipsIV model, fix assembler syntax.
1657 (do_c_cond_fmt): New function.
1658 (C.cond.fmt): Handle mips I-III which do not support CC field
1659 separatly.
1660 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1661 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1662 in IV3.2 spec.
1663 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1664 vr5000 which saves LO in a GPR separatly.
1665
1666 * configure.in (enable-sim-igen): For vr5000, select vr5000
1667 specific instructions.
1668 * configure: Re-generate.
1669
1670Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1671
1672 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1673
1674 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1675 fmt_uninterpreted_64 bit cases to switch. Convert to
1676 fmt_formatted,
1677
1678 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1679
1680 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1681 as specified in IV3.2 spec.
1682 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1683
1684Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1685
1686 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1687 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1688 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1689 PENDING_FILL versions of instructions. Simplify.
1690 (X): New function.
1691 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1692 instructions.
1693 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1694 a signed value.
1695 (MTHI, MFHI): Disable code checking HI-LO.
1696
1697 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1698 global.
1699 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1700
1701Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1702
1703 * gencode.c (build_mips16_operands): Replace IPC with cia.
1704
1705 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1706 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1707 IPC to `cia'.
1708 (UndefinedResult): Replace function with macro/function
1709 combination.
1710 (sim_engine_run): Don't save PC in IPC.
1711
1712 * sim-main.h (IPC): Delete.
1713
1714
1715 * interp.c (signal_exception, store_word, load_word,
1716 address_translation, load_memory, store_memory, cache_op,
1717 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1718 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1719 current instruction address - cia - argument.
1720 (sim_read, sim_write): Call address_translation directly.
1721 (sim_engine_run): Rename variable vaddr to cia.
1722 (signal_exception): Pass cia to sim_monitor
1723
1724 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1725 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1726 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1727
1728 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1729 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1730 SIM_ASSERT.
1731
1732 * interp.c (signal_exception): Pass restart address to
1733 sim_engine_restart.
1734
1735 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1736 idecode.o): Add dependency.
1737
1738 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1739 Delete definitions
1740 (DELAY_SLOT): Update NIA not PC with branch address.
1741 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1742
1743 * mips.igen: Use CIA not PC in branch calculations.
1744 (illegal): Call SignalException.
1745 (BEQ, ADDIU): Fix assembler.
1746
1747Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1748
1749 * m16.igen (JALX): Was missing.
1750
1751 * configure.in (enable-sim-igen): New configuration option.
1752 * configure: Re-generate.
1753
1754 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1755
1756 * interp.c (load_memory, store_memory): Delete parameter RAW.
1757 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1758 bypassing {load,store}_memory.
1759
1760 * sim-main.h (ByteSwapMem): Delete definition.
1761
1762 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1763
1764 * interp.c (sim_do_command, sim_commands): Delete mips specific
1765 commands. Handled by module sim-options.
1766
1767 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1768 (WITH_MODULO_MEMORY): Define.
1769
1770 * interp.c (sim_info): Delete code printing memory size.
1771
1772 * interp.c (mips_size): Nee sim_size, delete function.
1773 (power2): Delete.
1774 (monitor, monitor_base, monitor_size): Delete global variables.
1775 (sim_open, sim_close): Delete code creating monitor and other
1776 memory regions. Use sim-memopts module, via sim_do_commandf, to
1777 manage memory regions.
1778 (load_memory, store_memory): Use sim-core for memory model.
1779
1780 * interp.c (address_translation): Delete all memory map code
1781 except line forcing 32 bit addresses.
1782
1783Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1786 trace options.
1787
1788 * interp.c (logfh, logfile): Delete globals.
1789 (sim_open, sim_close): Delete code opening & closing log file.
1790 (mips_option_handler): Delete -l and -n options.
1791 (OPTION mips_options): Ditto.
1792
1793 * interp.c (OPTION mips_options): Rename option trace to dinero.
1794 (mips_option_handler): Update.
1795
1796Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797
1798 * interp.c (fetch_str): New function.
1799 (sim_monitor): Rewrite using sim_read & sim_write.
1800 (sim_open): Check magic number.
1801 (sim_open): Write monitor vectors into memory using sim_write.
1802 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1803 (sim_read, sim_write): Simplify - transfer data one byte at a
1804 time.
1805 (load_memory, store_memory): Clarify meaning of parameter RAW.
1806
1807 * sim-main.h (isHOST): Defete definition.
1808 (isTARGET): Mark as depreciated.
1809 (address_translation): Delete parameter HOST.
1810
1811 * interp.c (address_translation): Delete parameter HOST.
1812
1813Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1814
1815 * mips.igen:
1816
1817 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1818 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1819
1820Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1821
1822 * mips.igen: Add model filter field to records.
1823
1824Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1827
1828 interp.c (sim_engine_run): Do not compile function sim_engine_run
1829 when WITH_IGEN == 1.
1830
1831 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1832 target architecture.
1833
1834 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1835 igen. Replace with configuration variables sim_igen_flags /
1836 sim_m16_flags.
1837
1838 * m16.igen: New file. Copy mips16 insns here.
1839 * mips.igen: From here.
1840
1841Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1842
1843 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1844 to top.
1845 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1846
1847Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1848
1849 * gencode.c (build_instruction): Follow sim_write's lead in using
1850 BigEndianMem instead of !ByteSwapMem.
1851
1852Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * configure.in (sim_gen): Dependent on target, select type of
1855 generator. Always select old style generator.
1856
1857 configure: Re-generate.
1858
1859 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1860 targets.
1861 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1862 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1863 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1864 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1865 SIM_@sim_gen@_*, set by autoconf.
1866
1867Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1870
1871 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1872 CURRENT_FLOATING_POINT instead.
1873
1874 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1875 (address_translation): Raise exception InstructionFetch when
1876 translation fails and isINSTRUCTION.
1877
1878 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1879 sim_engine_run): Change type of of vaddr and paddr to
1880 address_word.
1881 (address_translation, prefetch, load_memory, store_memory,
1882 cache_op): Change type of vAddr and pAddr to address_word.
1883
1884 * gencode.c (build_instruction): Change type of vaddr and paddr to
1885 address_word.
1886
1887Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1888
1889 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1890 macro to obtain result of ALU op.
1891
1892Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1893
1894 * interp.c (sim_info): Call profile_print.
1895
1896Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1899
1900 * sim-main.h (WITH_PROFILE): Do not define, defined in
1901 common/sim-config.h. Use sim-profile module.
1902 (simPROFILE): Delete defintion.
1903
1904 * interp.c (PROFILE): Delete definition.
1905 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1906 (sim_close): Delete code writing profile histogram.
1907 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1908 Delete.
1909 (sim_engine_run): Delete code profiling the PC.
1910
1911Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1912
1913 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1914
1915 * interp.c (sim_monitor): Make register pointers of type
1916 unsigned_word*.
1917
1918 * sim-main.h: Make registers of type unsigned_word not
1919 signed_word.
1920
1921Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * interp.c (sync_operation): Rename from SyncOperation, make
1924 global, add SD argument.
1925 (prefetch): Rename from Prefetch, make global, add SD argument.
1926 (decode_coproc): Make global.
1927
1928 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1929
1930 * gencode.c (build_instruction): Generate DecodeCoproc not
1931 decode_coproc calls.
1932
1933 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1934 (SizeFGR): Move to sim-main.h
1935 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1936 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1937 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1938 sim-main.h.
1939 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1940 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1941 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1942 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1943 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1944 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1945
1946 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1947 exception.
1948 (sim-alu.h): Include.
1949 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1950 (sim_cia): Typedef to instruction_address.
1951
1952Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1953
1954 * Makefile.in (interp.o): Rename generated file engine.c to
1955 oengine.c.
1956
1957 * interp.c: Update.
1958
1959Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1962
1963Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1964
1965 * gencode.c (build_instruction): For "FPSQRT", output correct
1966 number of arguments to Recip.
1967
1968Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * Makefile.in (interp.o): Depends on sim-main.h
1971
1972 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1973
1974 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1975 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1976 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1977 STATE, DSSTATE): Define
1978 (GPR, FGRIDX, ..): Define.
1979
1980 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1981 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1982 (GPR, FGRIDX, ...): Delete macros.
1983
1984 * interp.c: Update names to match defines from sim-main.h
1985
1986Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * interp.c (sim_monitor): Add SD argument.
1989 (sim_warning): Delete. Replace calls with calls to
1990 sim_io_eprintf.
1991 (sim_error): Delete. Replace calls with sim_io_error.
1992 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1993 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1994 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1995 argument.
1996 (mips_size): Rename from sim_size. Add SD argument.
1997
1998 * interp.c (simulator): Delete global variable.
1999 (callback): Delete global variable.
2000 (mips_option_handler, sim_open, sim_write, sim_read,
2001 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2002 sim_size,sim_monitor): Use sim_io_* not callback->*.
2003 (sim_open): ZALLOC simulator struct.
2004 (PROFILE): Do not define.
2005
2006Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2007
2008 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2009 support.h with corresponding code.
2010
2011 * sim-main.h (word64, uword64), support.h: Move definition to
2012 sim-main.h.
2013 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2014
2015 * support.h: Delete
2016 * Makefile.in: Update dependencies
2017 * interp.c: Do not include.
2018
2019Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2020
2021 * interp.c (address_translation, load_memory, store_memory,
2022 cache_op): Rename to from AddressTranslation et.al., make global,
2023 add SD argument
2024
2025 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2026 CacheOp): Define.
2027
2028 * interp.c (SignalException): Rename to signal_exception, make
2029 global.
2030
2031 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2032
2033 * sim-main.h (SignalException, SignalExceptionInterrupt,
2034 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2035 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2036 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2037 Define.
2038
2039 * interp.c, support.h: Use.
2040
2041Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2042
2043 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2044 to value_fpr / store_fpr. Add SD argument.
2045 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2046 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2047
2048 * sim-main.h (ValueFPR, StoreFPR): Define.
2049
2050Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * interp.c (sim_engine_run): Check consistency between configure
2053 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2054 and HASFPU.
2055
2056 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2057 (mips_fpu): Configure WITH_FLOATING_POINT.
2058 (mips_endian): Configure WITH_TARGET_ENDIAN.
2059 * configure: Update.
2060
2061Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2062
2063 * configure: Regenerated to track ../common/aclocal.m4 changes.
2064
2065Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2066
2067 * configure: Regenerated.
2068
2069Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2070
2071 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2072
2073Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2074
2075 * gencode.c (print_igen_insn_models): Assume certain architectures
2076 include all mips* instructions.
2077 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2078 instruction.
2079
2080 * Makefile.in (tmp.igen): Add target. Generate igen input from
2081 gencode file.
2082
2083 * gencode.c (FEATURE_IGEN): Define.
2084 (main): Add --igen option. Generate output in igen format.
2085 (process_instructions): Format output according to igen option.
2086 (print_igen_insn_format): New function.
2087 (print_igen_insn_models): New function.
2088 (process_instructions): Only issue warnings and ignore
2089 instructions when no FEATURE_IGEN.
2090
2091Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2094 MIPS targets.
2095
2096Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2097
2098 * configure: Regenerated to track ../common/aclocal.m4 changes.
2099
2100Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2103 SIM_RESERVED_BITS): Delete, moved to common.
2104 (SIM_EXTRA_CFLAGS): Update.
2105
2106Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * configure.in: Configure non-strict memory alignment.
2109 * configure: Regenerated to track ../common/aclocal.m4 changes.
2110
2111Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2112
2113 * configure: Regenerated to track ../common/aclocal.m4 changes.
2114
2115Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2116
2117 * gencode.c (SDBBP,DERET): Added (3900) insns.
2118 (RFE): Turn on for 3900.
2119 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2120 (dsstate): Made global.
2121 (SUBTARGET_R3900): Added.
2122 (CANCELDELAYSLOT): New.
2123 (SignalException): Ignore SystemCall rather than ignore and
2124 terminate. Add DebugBreakPoint handling.
2125 (decode_coproc): New insns RFE, DERET; and new registers Debug
2126 and DEPC protected by SUBTARGET_R3900.
2127 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2128 bits explicitly.
2129 * Makefile.in,configure.in: Add mips subtarget option.
2130 * configure: Update.
2131
2132Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2133
2134 * gencode.c: Add r3900 (tx39).
2135
2136
2137Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2138
2139 * gencode.c (build_instruction): Don't need to subtract 4 for
2140 JALR, just 2.
2141
2142Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2143
2144 * interp.c: Correct some HASFPU problems.
2145
2146Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * configure: Regenerated to track ../common/aclocal.m4 changes.
2149
2150Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * interp.c (mips_options): Fix samples option short form, should
2153 be `x'.
2154
2155Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2156
2157 * interp.c (sim_info): Enable info code. Was just returning.
2158
2159Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160
2161 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2162 MFC0.
2163
2164Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2165
2166 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2167 constants.
2168 (build_instruction): Ditto for LL.
2169
2170Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2171
2172 * configure: Regenerated to track ../common/aclocal.m4 changes.
2173
2174Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175
2176 * configure: Regenerated to track ../common/aclocal.m4 changes.
2177 * config.in: Ditto.
2178
2179Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * interp.c (sim_open): Add call to sim_analyze_program, update
2182 call to sim_config.
2183
2184Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185
2186 * interp.c (sim_kill): Delete.
2187 (sim_create_inferior): Add ABFD argument. Set PC from same.
2188 (sim_load): Move code initializing trap handlers from here.
2189 (sim_open): To here.
2190 (sim_load): Delete, use sim-hload.c.
2191
2192 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2193
2194Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2195
2196 * configure: Regenerated to track ../common/aclocal.m4 changes.
2197 * config.in: Ditto.
2198
2199Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * interp.c (sim_open): Add ABFD argument.
2202 (sim_load): Move call to sim_config from here.
2203 (sim_open): To here. Check return status.
2204
2205Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2206
2207 * gencode.c (build_instruction): Two arg MADD should
2208 not assign result to $0.
2209
2210Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2211
2212 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2213 * sim/mips/configure.in: Regenerate.
2214
2215Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2216
2217 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2218 signed8, unsigned8 et.al. types.
2219
2220 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2221 hosts when selecting subreg.
2222
2223Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2224
2225 * interp.c (sim_engine_run): Reset the ZERO register to zero
2226 regardless of FEATURE_WARN_ZERO.
2227 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2228
2229Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2230
2231 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2232 (SignalException): For BreakPoints ignore any mode bits and just
2233 save the PC.
2234 (SignalException): Always set the CAUSE register.
2235
2236Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2239 exception has been taken.
2240
2241 * interp.c: Implement the ERET and mt/f sr instructions.
2242
2243Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2244
2245 * interp.c (SignalException): Don't bother restarting an
2246 interrupt.
2247
2248Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2249
2250 * interp.c (SignalException): Really take an interrupt.
2251 (interrupt_event): Only deliver interrupts when enabled.
2252
2253Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2254
2255 * interp.c (sim_info): Only print info when verbose.
2256 (sim_info) Use sim_io_printf for output.
2257
2258Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2261 mips architectures.
2262
2263Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2264
2265 * interp.c (sim_do_command): Check for common commands if a
2266 simulator specific command fails.
2267
2268Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2269
2270 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2271 and simBE when DEBUG is defined.
2272
2273Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2274
2275 * interp.c (interrupt_event): New function. Pass exception event
2276 onto exception handler.
2277
2278 * configure.in: Check for stdlib.h.
2279 * configure: Regenerate.
2280
2281 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2282 variable declaration.
2283 (build_instruction): Initialize memval1.
2284 (build_instruction): Add UNUSED attribute to byte, bigend,
2285 reverse.
2286 (build_operands): Ditto.
2287
2288 * interp.c: Fix GCC warnings.
2289 (sim_get_quit_code): Delete.
2290
2291 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2292 * Makefile.in: Ditto.
2293 * configure: Re-generate.
2294
2295 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2296
2297Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2298
2299 * interp.c (mips_option_handler): New function parse argumes using
2300 sim-options.
2301 (myname): Replace with STATE_MY_NAME.
2302 (sim_open): Delete check for host endianness - performed by
2303 sim_config.
2304 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2305 (sim_open): Move much of the initialization from here.
2306 (sim_load): To here. After the image has been loaded and
2307 endianness set.
2308 (sim_open): Move ColdReset from here.
2309 (sim_create_inferior): To here.
2310 (sim_open): Make FP check less dependant on host endianness.
2311
2312 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2313 run.
2314 * interp.c (sim_set_callbacks): Delete.
2315
2316 * interp.c (membank, membank_base, membank_size): Replace with
2317 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2318 (sim_open): Remove call to callback->init. gdb/run do this.
2319
2320 * interp.c: Update
2321
2322 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2323
2324 * interp.c (big_endian_p): Delete, replaced by
2325 current_target_byte_order.
2326
2327Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2328
2329 * interp.c (host_read_long, host_read_word, host_swap_word,
2330 host_swap_long): Delete. Using common sim-endian.
2331 (sim_fetch_register, sim_store_register): Use H2T.
2332 (pipeline_ticks): Delete. Handled by sim-events.
2333 (sim_info): Update.
2334 (sim_engine_run): Update.
2335
2336Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2337
2338 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2339 reason from here.
2340 (SignalException): To here. Signal using sim_engine_halt.
2341 (sim_stop_reason): Delete, moved to common.
2342
2343Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2344
2345 * interp.c (sim_open): Add callback argument.
2346 (sim_set_callbacks): Delete SIM_DESC argument.
2347 (sim_size): Ditto.
2348
2349Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * Makefile.in (SIM_OBJS): Add common modules.
2352
2353 * interp.c (sim_set_callbacks): Also set SD callback.
2354 (set_endianness, xfer_*, swap_*): Delete.
2355 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2356 Change to functions using sim-endian macros.
2357 (control_c, sim_stop): Delete, use common version.
2358 (simulate): Convert into.
2359 (sim_engine_run): This function.
2360 (sim_resume): Delete.
2361
2362 * interp.c (simulation): New variable - the simulator object.
2363 (sim_kind): Delete global - merged into simulation.
2364 (sim_load): Cleanup. Move PC assignment from here.
2365 (sim_create_inferior): To here.
2366
2367 * sim-main.h: New file.
2368 * interp.c (sim-main.h): Include.
2369
2370Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2371
2372 * configure: Regenerated to track ../common/aclocal.m4 changes.
2373
2374Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2375
2376 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2377
2378Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2379
2380 * gencode.c (build_instruction): DIV instructions: check
2381 for division by zero and integer overflow before using
2382 host's division operation.
2383
2384Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2385
2386 * Makefile.in (SIM_OBJS): Add sim-load.o.
2387 * interp.c: #include bfd.h.
2388 (target_byte_order): Delete.
2389 (sim_kind, myname, big_endian_p): New static locals.
2390 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2391 after argument parsing. Recognize -E arg, set endianness accordingly.
2392 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2393 load file into simulator. Set PC from bfd.
2394 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2395 (set_endianness): Use big_endian_p instead of target_byte_order.
2396
2397Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2398
2399 * interp.c (sim_size): Delete prototype - conflicts with
2400 definition in remote-sim.h. Correct definition.
2401
2402Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2403
2404 * configure: Regenerated to track ../common/aclocal.m4 changes.
2405 * config.in: Ditto.
2406
2407Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2408
2409 * interp.c (sim_open): New arg `kind'.
2410
2411 * configure: Regenerated to track ../common/aclocal.m4 changes.
2412
2413Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2414
2415 * configure: Regenerated to track ../common/aclocal.m4 changes.
2416
2417Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2418
2419 * interp.c (sim_open): Set optind to 0 before calling getopt.
2420
2421Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2422
2423 * configure: Regenerated to track ../common/aclocal.m4 changes.
2424
2425Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2426
2427 * interp.c : Replace uses of pr_addr with pr_uword64
2428 where the bit length is always 64 independent of SIM_ADDR.
2429 (pr_uword64) : added.
2430
2431Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2432
2433 * configure: Re-generate.
2434
2435Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2436
2437 * configure: Regenerate to track ../common/aclocal.m4 changes.
2438
2439Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2440
2441 * interp.c (sim_open): New SIM_DESC result. Argument is now
2442 in argv form.
2443 (other sim_*): New SIM_DESC argument.
2444
2445Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2446
2447 * interp.c: Fix printing of addresses for non-64-bit targets.
2448 (pr_addr): Add function to print address based on size.
2449
2450Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2451
2452 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2453
2454Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2455
2456 * gencode.c (build_mips16_operands): Correct computation of base
2457 address for extended PC relative instruction.
2458
2459Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2460
2461 * interp.c (mips16_entry): Add support for floating point cases.
2462 (SignalException): Pass floating point cases to mips16_entry.
2463 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2464 registers.
2465 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2466 or fmt_word.
2467 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2468 and then set the state to fmt_uninterpreted.
2469 (COP_SW): Temporarily set the state to fmt_word while calling
2470 ValueFPR.
2471
2472Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2473
2474 * gencode.c (build_instruction): The high order may be set in the
2475 comparison flags at any ISA level, not just ISA 4.
2476
2477Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2478
2479 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2480 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2481 * configure.in: sinclude ../common/aclocal.m4.
2482 * configure: Regenerated.
2483
2484Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2485
2486 * configure: Rebuild after change to aclocal.m4.
2487
2488Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2489
2490 * configure configure.in Makefile.in: Update to new configure
2491 scheme which is more compatible with WinGDB builds.
2492 * configure.in: Improve comment on how to run autoconf.
2493 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2494 * Makefile.in: Use autoconf substitution to install common
2495 makefile fragment.
2496
2497Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2498
2499 * gencode.c (build_instruction): Use BigEndianCPU instead of
2500 ByteSwapMem.
2501
2502Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2503
2504 * interp.c (sim_monitor): Make output to stdout visible in
2505 wingdb's I/O log window.
2506
2507Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2508
2509 * support.h: Undo previous change to SIGTRAP
2510 and SIGQUIT values.
2511
2512Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2513
2514 * interp.c (store_word, load_word): New static functions.
2515 (mips16_entry): New static function.
2516 (SignalException): Look for mips16 entry and exit instructions.
2517 (simulate): Use the correct index when setting fpr_state after
2518 doing a pending move.
2519
2520Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2521
2522 * interp.c: Fix byte-swapping code throughout to work on
2523 both little- and big-endian hosts.
2524
2525Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2526
2527 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2528 with gdb/config/i386/xm-windows.h.
2529
2530Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2531
2532 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2533 that messes up arithmetic shifts.
2534
2535Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2536
2537 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2538 SIGTRAP and SIGQUIT for _WIN32.
2539
2540Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2541
2542 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2543 force a 64 bit multiplication.
2544 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2545 destination register is 0, since that is the default mips16 nop
2546 instruction.
2547
2548Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2549
2550 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2551 (build_endian_shift): Don't check proc64.
2552 (build_instruction): Always set memval to uword64. Cast op2 to
2553 uword64 when shifting it left in memory instructions. Always use
2554 the same code for stores--don't special case proc64.
2555
2556 * gencode.c (build_mips16_operands): Fix base PC value for PC
2557 relative operands.
2558 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2559 jal instruction.
2560 * interp.c (simJALDELAYSLOT): Define.
2561 (JALDELAYSLOT): Define.
2562 (INDELAYSLOT, INJALDELAYSLOT): Define.
2563 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2564
2565Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2566
2567 * interp.c (sim_open): add flush_cache as a PMON routine
2568 (sim_monitor): handle flush_cache by ignoring it
2569
2570Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2571
2572 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2573 BigEndianMem.
2574 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2575 (BigEndianMem): Rename to ByteSwapMem and change sense.
2576 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2577 BigEndianMem references to !ByteSwapMem.
2578 (set_endianness): New function, with prototype.
2579 (sim_open): Call set_endianness.
2580 (sim_info): Use simBE instead of BigEndianMem.
2581 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2582 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2583 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2584 ifdefs, keeping the prototype declaration.
2585 (swap_word): Rewrite correctly.
2586 (ColdReset): Delete references to CONFIG. Delete endianness related
2587 code; moved to set_endianness.
2588
2589Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2590
2591 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2592 * interp.c (CHECKHILO): Define away.
2593 (simSIGINT): New macro.
2594 (membank_size): Increase from 1MB to 2MB.
2595 (control_c): New function.
2596 (sim_resume): Rename parameter signal to signal_number. Add local
2597 variable prev. Call signal before and after simulate.
2598 (sim_stop_reason): Add simSIGINT support.
2599 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2600 functions always.
2601 (sim_warning): Delete call to SignalException. Do call printf_filtered
2602 if logfh is NULL.
2603 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2604 a call to sim_warning.
2605
2606Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2607
2608 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2609 16 bit instructions.
2610
2611Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2612
2613 Add support for mips16 (16 bit MIPS implementation):
2614 * gencode.c (inst_type): Add mips16 instruction encoding types.
2615 (GETDATASIZEINSN): Define.
2616 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2617 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2618 mtlo.
2619 (MIPS16_DECODE): New table, for mips16 instructions.
2620 (bitmap_val): New static function.
2621 (struct mips16_op): Define.
2622 (mips16_op_table): New table, for mips16 operands.
2623 (build_mips16_operands): New static function.
2624 (process_instructions): If PC is odd, decode a mips16
2625 instruction. Break out instruction handling into new
2626 build_instruction function.
2627 (build_instruction): New static function, broken out of
2628 process_instructions. Check modifiers rather than flags for SHIFT
2629 bit count and m[ft]{hi,lo} direction.
2630 (usage): Pass program name to fprintf.
2631 (main): Remove unused variable this_option_optind. Change
2632 ``*loptarg++'' to ``loptarg++''.
2633 (my_strtoul): Parenthesize && within ||.
2634 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2635 (simulate): If PC is odd, fetch a 16 bit instruction, and
2636 increment PC by 2 rather than 4.
2637 * configure.in: Add case for mips16*-*-*.
2638 * configure: Rebuild.
2639
2640Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2641
2642 * interp.c: Allow -t to enable tracing in standalone simulator.
2643 Fix garbage output in trace file and error messages.
2644
2645Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2646
2647 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2648 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2649 * configure.in: Simplify using macros in ../common/aclocal.m4.
2650 * configure: Regenerated.
2651 * tconfig.in: New file.
2652
2653Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2654
2655 * interp.c: Fix bugs in 64-bit port.
2656 Use ansi function declarations for msvc compiler.
2657 Initialize and test file pointer in trace code.
2658 Prevent duplicate definition of LAST_EMED_REGNUM.
2659
2660Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2661
2662 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2663
2664Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2665
2666 * interp.c (SignalException): Check for explicit terminating
2667 breakpoint value.
2668 * gencode.c: Pass instruction value through SignalException()
2669 calls for Trap, Breakpoint and Syscall.
2670
2671Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2672
2673 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2674 only used on those hosts that provide it.
2675 * configure.in: Add sqrt() to list of functions to be checked for.
2676 * config.in: Re-generated.
2677 * configure: Re-generated.
2678
2679Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2680
2681 * gencode.c (process_instructions): Call build_endian_shift when
2682 expanding STORE RIGHT, to fix swr.
2683 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2684 clear the high bits.
2685 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2686 Fix float to int conversions to produce signed values.
2687
2688Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2689
2690 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2691 (process_instructions): Correct handling of nor instruction.
2692 Correct shift count for 32 bit shift instructions. Correct sign
2693 extension for arithmetic shifts to not shift the number of bits in
2694 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2695 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2696 Fix madd.
2697 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2698 It's OK to have a mult follow a mult. What's not OK is to have a
2699 mult follow an mfhi.
2700 (Convert): Comment out incorrect rounding code.
2701
2702Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2703
2704 * interp.c (sim_monitor): Improved monitor printf
2705 simulation. Tidied up simulator warnings, and added "--log" option
2706 for directing warning message output.
2707 * gencode.c: Use sim_warning() rather than WARNING macro.
2708
2709Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2710
2711 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2712 getopt1.o, rather than on gencode.c. Link objects together.
2713 Don't link against -liberty.
2714 (gencode.o, getopt.o, getopt1.o): New targets.
2715 * gencode.c: Include <ctype.h> and "ansidecl.h".
2716 (AND): Undefine after including "ansidecl.h".
2717 (ULONG_MAX): Define if not defined.
2718 (OP_*): Don't define macros; now defined in opcode/mips.h.
2719 (main): Call my_strtoul rather than strtoul.
2720 (my_strtoul): New static function.
2721
2722Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2723
2724 * gencode.c (process_instructions): Generate word64 and uword64
2725 instead of `long long' and `unsigned long long' data types.
2726 * interp.c: #include sysdep.h to get signals, and define default
2727 for SIGBUS.
2728 * (Convert): Work around for Visual-C++ compiler bug with type
2729 conversion.
2730 * support.h: Make things compile under Visual-C++ by using
2731 __int64 instead of `long long'. Change many refs to long long
2732 into word64/uword64 typedefs.
2733
2734Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2735
2736 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2737 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2738 (docdir): Removed.
2739 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2740 (AC_PROG_INSTALL): Added.
2741 (AC_PROG_CC): Moved to before configure.host call.
2742 * configure: Rebuilt.
2743
2744Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2745
2746 * configure.in: Define @SIMCONF@ depending on mips target.
2747 * configure: Rebuild.
2748 * Makefile.in (run): Add @SIMCONF@ to control simulator
2749 construction.
2750 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2751 * interp.c: Remove some debugging, provide more detailed error
2752 messages, update memory accesses to use LOADDRMASK.
2753
2754Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2755
2756 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2757 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2758 stamp-h.
2759 * configure: Rebuild.
2760 * config.in: New file, generated by autoheader.
2761 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2762 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2763 HAVE_ANINT and HAVE_AINT, as appropriate.
2764 * Makefile.in (run): Use @LIBS@ rather than -lm.
2765 (interp.o): Depend upon config.h.
2766 (Makefile): Just rebuild Makefile.
2767 (clean): Remove stamp-h.
2768 (mostlyclean): Make the same as clean, not as distclean.
2769 (config.h, stamp-h): New targets.
2770
2771Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2772
2773 * interp.c (ColdReset): Fix boolean test. Make all simulator
2774 globals static.
2775
2776Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2777
2778 * interp.c (xfer_direct_word, xfer_direct_long,
2779 swap_direct_word, swap_direct_long, xfer_big_word,
2780 xfer_big_long, xfer_little_word, xfer_little_long,
2781 swap_word,swap_long): Added.
2782 * interp.c (ColdReset): Provide function indirection to
2783 host<->simulated_target transfer routines.
2784 * interp.c (sim_store_register, sim_fetch_register): Updated to
2785 make use of indirected transfer routines.
2786
2787Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2788
2789 * gencode.c (process_instructions): Ensure FP ABS instruction
2790 recognised.
2791 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2792 system call support.
2793
2794Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2795
2796 * interp.c (sim_do_command): Complain if callback structure not
2797 initialised.
2798
2799Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2800
2801 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2802 support for Sun hosts.
2803 * Makefile.in (gencode): Ensure the host compiler and libraries
2804 used for cross-hosted build.
2805
2806Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2807
2808 * interp.c, gencode.c: Some more (TODO) tidying.
2809
2810Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2811
2812 * gencode.c, interp.c: Replaced explicit long long references with
2813 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2814 * support.h (SET64LO, SET64HI): Macros added.
2815
2816Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2817
2818 * configure: Regenerate with autoconf 2.7.
2819
2820Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2821
2822 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2823 * support.h: Remove superfluous "1" from #if.
2824 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2825
2826Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2827
2828 * interp.c (StoreFPR): Control UndefinedResult() call on
2829 WARN_RESULT manifest.
2830
2831Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2832
2833 * gencode.c: Tidied instruction decoding, and added FP instruction
2834 support.
2835
2836 * interp.c: Added dineroIII, and BSD profiling support. Also
2837 run-time FP handling.
2838
2839Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2840
2841 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2842 gencode.c, interp.c, support.h: created.
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