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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
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c8cca39f
AC		 12002-06-16 Andrew Cagney <ac131313@redhat.com>
2
3 * configure: Regenerated to track ../common/aclocal.m4 changes.
4
e7e81181
CD		 52002-06-14 Chris Demetriou <cgd@broadcom.com>
6 Ed Satterthwaite <ehs@broadcom.com>
7
8 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
9 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
10 * mips.igen: Include mips3d.igen.
11 (mips3d): New model name for MIPS-3D ASE instructions.
12 (CVT.W.fmt): Don't use this instruction for word (source) format
13 instructions.
14 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
15 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
16 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
17 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
18 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
19 (RSquareRoot1, RSquareRoot2): New macros.
20 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
21 (fp_rsqrt2): New functions.
22 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
23 * configure: Regenerate.
24
3a2b820e 252002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 26 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 27
28 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
29 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
30 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
31 (convert): Note that this function is not used for paired-single
32 format conversions.
33 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
34 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
35 (check_fmt_p): Enable paired-single support.
36 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
37 (PUU.PS): New instructions.
38 (CVT.S.fmt): Don't use this instruction for paired-single format
39 destinations.
40 * sim-main.h (FP_formats): New value 'fmt_ps.'
41 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
42 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
43
d18ea9c2
CD		 442002-06-12 Chris Demetriou <cgd@broadcom.com>
45
46 * mips.igen: Fix formatting of function calls in
47 many FP operations.
48
95fd5cee
CD		 492002-06-12 Chris Demetriou <cgd@broadcom.com>
50
51 * mips.igen (MOVN, MOVZ): Trace result.
52 (TNEI): Print "tnei" as the opcode name in traces.
53 (CEIL.W): Add disassembly string for traces.
54 (RSQRT.fmt): Make location of disassembly string consistent
55 with other instructions.
56
4f0d55ae
CD		 572002-06-12 Chris Demetriou <cgd@broadcom.com>
58
59 * mips.igen (X): Delete unused function.
60
3c25f8c7
AC		 612002-06-08 Andrew Cagney <cagney@redhat.com>
62
63 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
64
f3c08b7e
CD		 652002-06-07 Chris Demetriou <cgd@broadcom.com>
66 Ed Satterthwaite <ehs@broadcom.com>
67
68 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
69 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
70 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
71 (fp_nmsub): New prototypes.
72 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
73 (NegMultiplySub): New defines.
74 * mips.igen (RSQRT.fmt): Use RSquareRoot().
75 (MADD.D, MADD.S): Replace with...
76 (MADD.fmt): New instruction.
77 (MSUB.D, MSUB.S): Replace with...
78 (MSUB.fmt): New instruction.
79 (NMADD.D, NMADD.S): Replace with...
80 (NMADD.fmt): New instruction.
81 (NMSUB.D, MSUB.S): Replace with...
82 (NMSUB.fmt): New instruction.
83
52714ff9
CD		 842002-06-07 Chris Demetriou <cgd@broadcom.com>
85 Ed Satterthwaite <ehs@broadcom.com>
86
87 * cp1.c: Fix more comment spelling and formatting.
88 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
89 (denorm_mode): New function.
90 (fpu_unary, fpu_binary): Round results after operation, collect
91 status from rounding operations, and update the FCSR.
92 (convert): Collect status from integer conversions and rounding
93 operations, and update the FCSR. Adjust NaN values that result
94 from conversions. Convert to use sim_io_eprintf rather than
95 fprintf, and remove some debugging code.
96 * cp1.h (fenr_FS): New define.
97
577d8c4b
CD		 982002-06-07 Chris Demetriou <cgd@broadcom.com>
99
100 * cp1.c (convert): Remove unusable debugging code, and move MIPS
101 rounding mode to sim FP rounding mode flag conversion code into...
102 (rounding_mode): New function.
103
196496ed
CD		 1042002-06-07 Chris Demetriou <cgd@broadcom.com>
105
106 * cp1.c: Clean up formatting of a few comments.
107 (value_fpr): Reformat switch statement.
108
cfe9ea23
CD		 1092002-06-06 Chris Demetriou <cgd@broadcom.com>
110 Ed Satterthwaite <ehs@broadcom.com>
111
112 * cp1.h: New file.
113 * sim-main.h: Include cp1.h.
114 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
115 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
116 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
117 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
118 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
119 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
120 * cp1.c: Don't include sim-fpu.h; already included by
121 sim-main.h. Clean up formatting of some comments.
122 (NaN, Equal, Less): Remove.
123 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
124 (fp_cmp): New functions.
125 * mips.igen (do_c_cond_fmt): Remove.
126 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
127 Compare. Add result tracing.
128 (CxC1): Remove, replace with...
129 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
130 (DMxC1): Remove, replace with...
131 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
132 (MxC1): Remove, replace with...
133 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
134
ee7254b0
CD		 1352002-06-04 Chris Demetriou <cgd@broadcom.com>
136
137 * sim-main.h (FGRIDX): Remove, replace all uses with...
138 (FGR_BASE): New macro.
139 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
140 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
141 (NR_FGR, FGR): Likewise.
142 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
143 * mips.igen: Likewise.
144
d3eb724f
CD		 1452002-06-04 Chris Demetriou <cgd@broadcom.com>
146
147 * cp1.c: Add an FSF Copyright notice to this file.
148
ba46ddd0
CD		 1492002-06-04 Chris Demetriou <cgd@broadcom.com>
150 Ed Satterthwaite <ehs@broadcom.com>
151
152 * cp1.c (Infinity): Remove.
153 * sim-main.h (Infinity): Likewise.
154
155 * cp1.c (fp_unary, fp_binary): New functions.
156 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
157 (fp_sqrt): New functions, implemented in terms of the above.
158 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
159 (Recip, SquareRoot): Remove (replaced by functions above).
160 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
161 (fp_recip, fp_sqrt): New prototypes.
162 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
163 (Recip, SquareRoot): Replace prototypes with #defines which
164 invoke the functions above.
165
18d8a52d
CD		 1662002-06-03 Chris Demetriou <cgd@broadcom.com>
167
168 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
169 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
170 file, remove PARAMS from prototypes.
171 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
172 simulator state arguments.
173 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
174 pass simulator state arguments.
175 * cp1.c (SD): Redefine as CPU_STATE(cpu).
176 (store_fpr, convert): Remove 'sd' argument.
177 (value_fpr): Likewise. Convert to use 'SD' instead.
178
0f154cbd
CD		 1792002-06-03 Chris Demetriou <cgd@broadcom.com>
180
181 * cp1.c (Min, Max): Remove #if 0'd functions.
182 * sim-main.h (Min, Max): Remove.
183
e80fc152
CD		 1842002-06-03 Chris Demetriou <cgd@broadcom.com>
185
186 * cp1.c: fix formatting of switch case and default labels.
187 * interp.c: Likewise.
188 * sim-main.c: Likewise.
189
bad673a9
CD		 1902002-06-03 Chris Demetriou <cgd@broadcom.com>
191
192 * cp1.c: Clean up comments which describe FP formats.
193 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
194
7cbea089
CD		 1952002-06-03 Chris Demetriou <cgd@broadcom.com>
196 Ed Satterthwaite <ehs@broadcom.com>
197
198 * configure.in (mipsisa64sb1*-*-*): New target for supporting
199 Broadcom SiByte SB-1 processor configurations.
200 * configure: Regenerate.
201 * sb1.igen: New file.
202 * mips.igen: Include sb1.igen.
203 (sb1): New model.
204 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
205 * mdmx.igen: Add "sb1" model to all appropriate functions and
206 instructions.
207 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
208 (ob_func, ob_acc): Reference the above.
209 (qh_acc): Adjust to keep the same size as ob_acc.
210 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
211 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
212
909daa82
CD		 2132002-06-03 Chris Demetriou <cgd@broadcom.com>
214
215 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
216
f4f1b9f1
CD		 2172002-06-02 Chris Demetriou <cgd@broadcom.com>
218 Ed Satterthwaite <ehs@broadcom.com>
219
220 * mips.igen (mdmx): New (pseudo-)model.
221 * mdmx.c, mdmx.igen: New files.
222 * Makefile.in (SIM_OBJS): Add mdmx.o.
223 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
224 New typedefs.
225 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
226 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
227 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
228 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
229 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
230 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
231 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
232 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
233 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
234 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
235 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
236 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
237 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
238 (qh_fmtsel): New macros.
239 (_sim_cpu): New member "acc".
240 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
241 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
242
5accf1ff
CD		 2432002-05-01 Chris Demetriou <cgd@broadcom.com>
244
245 * interp.c: Use 'deprecated' rather than 'depreciated.'
246 * sim-main.h: Likewise.
247
402586aa
CD		 2482002-05-01 Chris Demetriou <cgd@broadcom.com>
249
250 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
251 which wouldn't compile anyway.
252 * sim-main.h (unpredictable_action): New function prototype.
253 (Unpredictable): Define to call igen function unpredictable().
254 (NotWordValue): New macro to call igen function not_word_value().
255 (UndefinedResult): Remove.
256 * interp.c (undefined_result): Remove.
257 (unpredictable_action): New function.
258 * mips.igen (not_word_value, unpredictable): New functions.
259 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
260 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
261 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
262 NotWordValue() to check for unpredictable inputs, then
263 Unpredictable() to handle them.
264
c9b9995a
CD		 2652002-02-24 Chris Demetriou <cgd@broadcom.com>
266
267 * mips.igen: Fix formatting of calls to Unpredictable().
268
e1015982
AC		 2692002-04-20 Andrew Cagney <ac131313@redhat.com>
270
271 * interp.c (sim_open): Revert previous change.
272
b882a66b
AO		 2732002-04-18 Alexandre Oliva <aoliva@redhat.com>
274
275 * interp.c (sim_open): Disable chunk of code that wrote code in
276 vector table entries.
277
c429b7dd
CD		 2782002-03-19 Chris Demetriou <cgd@broadcom.com>
279
280 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
281 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
282 unused definitions.
283
37d146fa
CD		 2842002-03-19 Chris Demetriou <cgd@broadcom.com>
285
286 * cp1.c: Fix many formatting issues.
287
07892c0b
CD		 2882002-03-19 Chris G. Demetriou <cgd@broadcom.com>
289
290 * cp1.c (fpu_format_name): New function to replace...
291 (DOFMT): This. Delete, and update all callers.
292 (fpu_rounding_mode_name): New function to replace...
293 (RMMODE): This. Delete, and update all callers.
294
487f79b7
CD		 2952002-03-19 Chris G. Demetriou <cgd@broadcom.com>
296
297 * interp.c: Move FPU support routines from here to...
298 * cp1.c: Here. New file.
299 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
300 (cp1.o): New target.
301
1e799e28
CD		 3022002-03-12 Chris Demetriou <cgd@broadcom.com>
303
304 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
305 * mips.igen (mips32, mips64): New models, add to all instructions
306 and functions as appropriate.
307 (loadstore_ea, check_u64): New variant for model mips64.
308 (check_fmt_p): New variant for models mipsV and mips64, remove
309 mipsV model marking fro other variant.
310 (SLL) Rename to...
311 (SLLa) this.
312 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
313 for mips32 and mips64.
314 (DCLO, DCLZ): New instructions for mips64.
315
82f728db
CD		 3162002-03-07 Chris Demetriou <cgd@broadcom.com>
317
318 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
319 immediate or code as a hex value with the "%#lx" format.
320 (ANDI): Likewise, and fix printed instruction name.
321
b96e7ef1
CD		 3222002-03-05 Chris Demetriou <cgd@broadcom.com>
323
324 * sim-main.h (UndefinedResult, Unpredictable): New macros
325 which currently do nothing.
326
d35d4f70
CD		 3272002-03-05 Chris Demetriou <cgd@broadcom.com>
328
329 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
330 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
331 (status_CU3): New definitions.
332
333 * sim-main.h (ExceptionCause): Add new values for MIPS32
334 and MIPS64: MDMX, MCheck, CacheErr. Update comments
335 for DebugBreakPoint and NMIReset to note their status in
336 MIPS32 and MIPS64.
337 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
338 (SignalExceptionCacheErr): New exception macros.
339
3ad6f714
CD		 3402002-03-05 Chris Demetriou <cgd@broadcom.com>
341
342 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
343 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
344 is always enabled.
345 (SignalExceptionCoProcessorUnusable): Take as argument the
346 unusable coprocessor number.
347
86b77b47
CD		 3482002-03-05 Chris Demetriou <cgd@broadcom.com>
349
350 * mips.igen: Fix formatting of all SignalException calls.
351
97a88e93 3522002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 353
354 * sim-main.h (SIGNEXTEND): Remove.
355
97a88e93 3562002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 357
358 * mips.igen: Remove gencode comment from top of file, fix
359 spelling in another comment.
360
97a88e93 3612002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 362
363 * mips.igen (check_fmt, check_fmt_p): New functions to check
364 whether specific floating point formats are usable.
365 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
366 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
367 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
368 Use the new functions.
369 (do_c_cond_fmt): Remove format checks...
370 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
371
97a88e93 3722002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 373
374 * mips.igen: Fix formatting of check_fpu calls.
375
41774c9d
CD		 3762002-03-03 Chris Demetriou <cgd@broadcom.com>
377
378 * mips.igen (FLOOR.L.fmt): Store correct destination register.
379
4a0bd876
CD		 3802002-03-03 Chris Demetriou <cgd@broadcom.com>
381
382 * mips.igen: Remove whitespace at end of lines.
383
09297648
CD		 3842002-03-02 Chris Demetriou <cgd@broadcom.com>
385
386 * mips.igen (loadstore_ea): New function to do effective
387 address calculations.
388 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
389 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
390 CACHE): Use loadstore_ea to do effective address computations.
391
043b7057
CD		 3922002-03-02 Chris Demetriou <cgd@broadcom.com>
393
394 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
395 * mips.igen (LL, CxC1, MxC1): Likewise.
396
c1e8ada4
CD		 3972002-03-02 Chris Demetriou <cgd@broadcom.com>
398
399 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
400 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
401 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
402 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
403 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
404 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
405 Don't split opcode fields by hand, use the opcode field values
406 provided by igen.
407
3e1dca16
CD		 4082002-03-01 Chris Demetriou <cgd@broadcom.com>
409
410 * mips.igen (do_divu): Fix spacing.
411
412 * mips.igen (do_dsllv): Move to be right before DSLLV,
413 to match the rest of the do_<shift> functions.
414
fff8d27d
CD		 4152002-03-01 Chris Demetriou <cgd@broadcom.com>
416
417 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
418 DSRL32, do_dsrlv): Trace inputs and results.
419
0d3e762b
CD		 4202002-03-01 Chris Demetriou <cgd@broadcom.com>
421
422 * mips.igen (CACHE): Provide instruction-printing string.
423
424 * interp.c (signal_exception): Comment tokens after #endif.
425
eb5fcf93
CD		 4262002-02-28 Chris Demetriou <cgd@broadcom.com>
427
428 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
429 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
430 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
431 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
432 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
433 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
434 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
435 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
436
bb22bd7d
CD		 4372002-02-28 Chris Demetriou <cgd@broadcom.com>
438
439 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
440 instruction-printing string.
441 (LWU): Use '64' as the filter flag.
442
91a177cf
CD		 4432002-02-28 Chris Demetriou <cgd@broadcom.com>
444
445 * mips.igen (SDXC1): Fix instruction-printing string.
446
387f484a
CD		 4472002-02-28 Chris Demetriou <cgd@broadcom.com>
448
449 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
450 filter flags "32,f".
451
3d81f391
CD		 4522002-02-27 Chris Demetriou <cgd@broadcom.com>
453
454 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
455 as the filter flag.
456
af5107af
CD		 4572002-02-27 Chris Demetriou <cgd@broadcom.com>
458
459 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
460 add a comma) so that it more closely match the MIPS ISA
461 documentation opcode partitioning.
462 (PREF): Put useful names on opcode fields, and include
463 instruction-printing string.
464
ca971540
CD		 4652002-02-27 Chris Demetriou <cgd@broadcom.com>
466
467 * mips.igen (check_u64): New function which in the future will
468 check whether 64-bit instructions are usable and signal an
469 exception if not. Currently a no-op.
470 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
471 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
472 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
473 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
474
475 * mips.igen (check_fpu): New function which in the future will
476 check whether FPU instructions are usable and signal an exception
477 if not. Currently a no-op.
478 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
479 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
480 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
481 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
482 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
483 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
484 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
485 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
486
1c47a468
CD		 4872002-02-27 Chris Demetriou <cgd@broadcom.com>
488
489 * mips.igen (do_load_left, do_load_right): Move to be immediately
490 following do_load.
491 (do_store_left, do_store_right): Move to be immediately following
492 do_store.
493
603a98e7
CD		 4942002-02-27 Chris Demetriou <cgd@broadcom.com>
495
496 * mips.igen (mipsV): New model name. Also, add it to
497 all instructions and functions where it is appropriate.
498
c5d00cc7
CD		 4992002-02-18 Chris Demetriou <cgd@broadcom.com>
500
501 * mips.igen: For all functions and instructions, list model
502 names that support that instruction one per line.
503
074e9cb8
CD		 5042002-02-11 Chris Demetriou <cgd@broadcom.com>
505
506 * mips.igen: Add some additional comments about supported
507 models, and about which instructions go where.
508 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
509 order as is used in the rest of the file.
510
9805e229
CD		 5112002-02-11 Chris Demetriou <cgd@broadcom.com>
512
513 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
514 indicating that ALU32_END or ALU64_END are there to check
515 for overflow.
516 (DADD): Likewise, but also remove previous comment about
517 overflow checking.
518
f701dad2
CD		 5192002-02-10 Chris Demetriou <cgd@broadcom.com>
520
521 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
522 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
523 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
524 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
525 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
526 fields (i.e., add and move commas) so that they more closely
527 match the MIPS ISA documentation opcode partitioning.
528
5292002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 530
531 * mips.igen (ADDI): Print immediate value.
532 (BREAK): Print code.
533 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
534 (SLL): Print "nop" specially, and don't run the code
535 that does the shift for the "nop" case.
536
9e52972e
FF		 5372001-11-17 Fred Fish <fnf@redhat.com>
538
539 * sim-main.h (float_operation): Move enum declaration outside
540 of _sim_cpu struct declaration.
541
c0efbca4
JB		 5422001-04-12 Jim Blandy <jimb@redhat.com>
543
544 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
545 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
546 set of the FCSR.
547 * sim-main.h (COCIDX): Remove definition; this isn't supported by
548 PENDING_FILL, and you can get the intended effect gracefully by
549 calling PENDING_SCHED directly.
550
fb891446
BE		 5512001-02-23 Ben Elliston <bje@redhat.com>
552
553 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
554 already defined elsewhere.
555
8030f857
BE		 5562001-02-19 Ben Elliston <bje@redhat.com>
557
558 * sim-main.h (sim_monitor): Return an int.
559 * interp.c (sim_monitor): Add return values.
560 (signal_exception): Handle error conditions from sim_monitor.
561
56b48a7a
CD		 5622001-02-08 Ben Elliston <bje@redhat.com>
563
564 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
565 (store_memory): Likewise, pass cia to sim_core_write*.
566
d3ee60d9
FCE		 5672000-10-19 Frank Ch. Eigler <fche@redhat.com>
568
569 On advice from Chris G. Demetriou <cgd@sibyte.com>:
570 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
571
071da002
AC		 572Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
573
574 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
575 * Makefile.in: Don't delete *.igen when cleaning directory.
576
a28c02cd
AC		 577Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
578
579 * m16.igen (break): Call SignalException not sim_engine_halt.
580
80ee11fa
AC		 581Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
582
583 From Jason Eckhardt:
584 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
585
673388c0
AC		 586Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
587
588 * mips.igen (MxC1, DMxC1): Fix printf formatting.
589
4c0deff4
NC		 5902000-05-24 Michael Hayes <mhayes@cygnus.com>
591
592 * mips.igen (do_dmultx): Fix typo.
593
eb2d80b4
AC		 594Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
595
596 * configure: Regenerated to track ../common/aclocal.m4 changes.
597
dd37a34b
AC		 598Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
599
600 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
601
4c0deff4
NC		 6022000-04-12 Frank Ch. Eigler <fche@redhat.com>
603
604 * sim-main.h (GPR_CLEAR): Define macro.
605
e30db738
AC		 606Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
607
608 * interp.c (decode_coproc): Output long using %lx and not %s.
609
cb7450ea
FCE		 6102000-03-21 Frank Ch. Eigler <fche@redhat.com>
611
612 * interp.c (sim_open): Sort & extend dummy memory regions for
613 --board=jmr3904 for eCos.
614
a3027dd7
FCE		 6152000-03-02 Frank Ch. Eigler <fche@redhat.com>
616
617 * configure: Regenerated.
618
619Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
620
621 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
622 calls, conditional on the simulator being in verbose mode.
623
dfcd3bfb
JM		 624Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
625
626 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
627 cache don't get ReservedInstruction traps.
628
c2d11a7d
JM		 6291999-11-29 Mark Salter <msalter@cygnus.com>
630
631 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
632 to clear status bits in sdisr register. This is how the hardware works.
633
634 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
635 being used by cygmon.
636
4ce44c66
JM		 6371999-11-11 Andrew Haley <aph@cygnus.com>
638
639 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
640 instructions.
641
cff3e48b
JM		 642Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
643
644 * mips.igen (MULT): Correct previous mis-applied patch.
645
d4f3574e
SS		 646Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
647
648 * mips.igen (delayslot32): Handle sequence like
649 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
650 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
651 (MULT): Actually pass the third register...
652
6531999-09-03 Mark Salter <msalter@cygnus.com>
654
655 * interp.c (sim_open): Added more memory aliases for additional
656 hardware being touched by cygmon on jmr3904 board.
657
658Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
659
660 * configure: Regenerated to track ../common/aclocal.m4 changes.
661
a0b3c4fd
JM		 662Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
663
664 * interp.c (sim_store_register): Handle case where client - GDB -
665 specifies that a 4 byte register is 8 bytes in size.
666 (sim_fetch_register): Ditto.
667
adf40b2e
JM		 6681999-07-14 Frank Ch. Eigler <fche@cygnus.com>
669
670 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
671 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
672 (idt_monitor_base): Base address for IDT monitor traps.
673 (pmon_monitor_base): Ditto for PMON.
674 (lsipmon_monitor_base): Ditto for LSI PMON.
675 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
676 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
677 (sim_firmware_command): New function.
678 (mips_option_handler): Call it for OPTION_FIRMWARE.
679 (sim_open): Allocate memory for idt_monitor region. If "--board"
680 option was given, add no monitor by default. Add BREAK hooks only if
681 monitors are also there.
682
43e526b9
JM		 683Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
684
685 * interp.c (sim_monitor): Flush output before reading input.
686
687Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
688
689 * tconfig.in (SIM_HANDLES_LMA): Always define.
690
691Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
692
693 From Mark Salter <msalter@cygnus.com>:
694 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
695 (sim_open): Add setup for BSP board.
696
9846de1b
JM		 697Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
698
699 * mips.igen (MULT, MULTU): Add syntax for two operand version.
700 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
701 them as unimplemented.
702
cd0fc7c3
SS		 7031999-05-08 Felix Lee <flee@cygnus.com>
704
705 * configure: Regenerated to track ../common/aclocal.m4 changes.
706
7a292a7a
SS		 7071999-04-21 Frank Ch. Eigler <fche@cygnus.com>
708
709 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
710
711Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
712
713 * configure.in: Any mips64vr5*-*-* target should have
714 -DTARGET_ENABLE_FR=1.
715 (default_endian): Any mips64vr*el-*-* target should default to
716 LITTLE_ENDIAN.
717 * configure: Re-generate.
718
7191999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
720
721 * mips.igen (ldl): Extend from _16_, not 32.
722
723Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
724
725 * interp.c (sim_store_register): Force registers written to by GDB
726 into an un-interpreted state.
727
c906108c
SS		 7281999-02-05 Frank Ch. Eigler <fche@cygnus.com>
729
730 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
731 CPU, start periodic background I/O polls.
732 (tx3904sio_poll): New function: periodic I/O poller.
733
7341998-12-30 Frank Ch. Eigler <fche@cygnus.com>
735
736 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
737
738Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
739
740 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
741 case statement.
742
7431998-12-29 Frank Ch. Eigler <fche@cygnus.com>
744
745 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
746 (load_word): Call SIM_CORE_SIGNAL hook on error.
747 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
748 starting. For exception dispatching, pass PC instead of NULL_CIA.
749 (decode_coproc): Use COP0_BADVADDR to store faulting address.
750 * sim-main.h (COP0_BADVADDR): Define.
751 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
752 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
753 (_sim_cpu): Add exc_* fields to store register value snapshots.
754 * mips.igen (*): Replace memory-related SignalException* calls
755 with references to SIM_CORE_SIGNAL hook.
756
757 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
758 fix.
759 * sim-main.c (*): Minor warning cleanups.
760
7611998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
762
763 * m16.igen (DADDIU5): Correct type-o.
764
765Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
766
767 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
768 variables.
769
770Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
771
772 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
773 to include path.
774 (interp.o): Add dependency on itable.h
775 (oengine.c, gencode): Delete remaining references.
776 (BUILT_SRC_FROM_GEN): Clean up.
777
7781998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
779
780 * vr4run.c: New.
781 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
782 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
783 tmp-run-hack) : New.
784 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
785 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
786 Drop the "64" qualifier to get the HACK generator working.
787 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
788 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
789 qualifier to get the hack generator working.
790 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
791 (DSLL): Use do_dsll.
792 (DSLLV): Use do_dsllv.
793 (DSRA): Use do_dsra.
794 (DSRL): Use do_dsrl.
795 (DSRLV): Use do_dsrlv.
796 (BC1): Move *vr4100 to get the HACK generator working.
797 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
798 get the HACK generator working.
799 (MACC) Rename to get the HACK generator working.
800 (DMACC,MACCS,DMACCS): Add the 64.
801
8021998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
803
804 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
805 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
806
8071998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
808
809 * mips/interp.c (DEBUG): Cleanups.
810
8111998-12-10 Frank Ch. Eigler <fche@cygnus.com>
812
813 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
814 (tx3904sio_tickle): fflush after a stdout character output.
815
8161998-12-03 Frank Ch. Eigler <fche@cygnus.com>
817
818 * interp.c (sim_close): Uninstall modules.
819
820Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
821
822 * sim-main.h, interp.c (sim_monitor): Change to global
823 function.
824
825Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
826
827 * configure.in (vr4100): Only include vr4100 instructions in
828 simulator.
829 * configure: Re-generate.
830 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
831
832Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
833
834 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
835 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
836 true alternative.
837
838 * configure.in (sim_default_gen, sim_use_gen): Replace with
839 sim_gen.
840 (--enable-sim-igen): Delete config option. Always using IGEN.
841 * configure: Re-generate.
842
843 * Makefile.in (gencode): Kill, kill, kill.
844 * gencode.c: Ditto.
845
846Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
847
848 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
849 bit mips16 igen simulator.
850 * configure: Re-generate.
851
852 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
853 as part of vr4100 ISA.
854 * vr.igen: Mark all instructions as 64 bit only.
855
856Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
857
858 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
859 Pacify GCC.
860
861Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
862
863 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
864 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
865 * configure: Re-generate.
866
867 * m16.igen (BREAK): Define breakpoint instruction.
868 (JALX32): Mark instruction as mips16 and not r3900.
869 * mips.igen (C.cond.fmt): Fix typo in instruction format.
870
871 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
872
873Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
874
875 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
876 insn as a debug breakpoint.
877
878 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
879 pending.slot_size.
880 (PENDING_SCHED): Clean up trace statement.
881 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
882 (PENDING_FILL): Delay write by only one cycle.
883 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
884
885 * sim-main.c (pending_tick): Clean up trace statements. Add trace
886 of pending writes.
887 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
888 32 & 64.
889 (pending_tick): Move incrementing of index to FOR statement.
890 (pending_tick): Only update PENDING_OUT after a write has occured.
891
892 * configure.in: Add explicit mips-lsi-* target. Use gencode to
893 build simulator.
894 * configure: Re-generate.
895
896 * interp.c (sim_engine_run OLD): Delete explicit call to
897 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
898
899Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
900
901 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
902 interrupt level number to match changed SignalExceptionInterrupt
903 macro.
904
905Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
906
907 * interp.c: #include "itable.h" if WITH_IGEN.
908 (get_insn_name): New function.
909 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
910 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
911
912Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
913
914 * configure: Rebuilt to inhale new common/aclocal.m4.
915
916Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
917
918 * dv-tx3904sio.c: Include sim-assert.h.
919
920Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
921
922 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
923 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
924 Reorganize target-specific sim-hardware checks.
925 * configure: rebuilt.
926 * interp.c (sim_open): For tx39 target boards, set
927 OPERATING_ENVIRONMENT, add tx3904sio devices.
928 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
929 ROM executables. Install dv-sockser into sim-modules list.
930
931 * dv-tx3904irc.c: Compiler warning clean-up.
932 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
933 frequent hw-trace messages.
934
935Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
936
937 * vr.igen (MulAcc): Identify as a vr4100 specific function.
938
939Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
940
941 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
942
943 * vr.igen: New file.
944 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
945 * mips.igen: Define vr4100 model. Include vr.igen.
946Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
947
948 * mips.igen (check_mf_hilo): Correct check.
949
950Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
951
952 * sim-main.h (interrupt_event): Add prototype.
953
954 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
955 register_ptr, register_value.
956 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
957
958 * sim-main.h (tracefh): Make extern.
959
960Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
961
962 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
963 Reduce unnecessarily high timer event frequency.
964 * dv-tx3904cpu.c: Ditto for interrupt event.
965
966Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
967
968 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
969 to allay warnings.
970 (interrupt_event): Made non-static.
971
972 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
973 interchange of configuration values for external vs. internal
974 clock dividers.
975
976Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
977
978 * mips.igen (BREAK): Moved code to here for
979 simulator-reserved break instructions.
980 * gencode.c (build_instruction): Ditto.
981 * interp.c (signal_exception): Code moved from here. Non-
982 reserved instructions now use exception vector, rather
983 than halting sim.
984 * sim-main.h: Moved magic constants to here.
985
986Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
987
988 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
989 register upon non-zero interrupt event level, clear upon zero
990 event value.
991 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
992 by passing zero event value.
993 (*_io_{read,write}_buffer): Endianness fixes.
994 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
995 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
996
997 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
998 serial I/O and timer module at base address 0xFFFF0000.
999
1000Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1001
1002 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1003 and BigEndianCPU.
1004
1005Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1006
1007 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1008 parts.
1009 * configure: Update.
1010
1011Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1012
1013 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1014 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1015 * configure.in: Include tx3904tmr in hw_device list.
1016 * configure: Rebuilt.
1017 * interp.c (sim_open): Instantiate three timer instances.
1018 Fix address typo of tx3904irc instance.
1019
1020Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1021
1022 * interp.c (signal_exception): SystemCall exception now uses
1023 the exception vector.
1024
1025Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1026
1027 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1028 to allay warnings.
1029
1030Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1031
1032 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1033
1034Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1035
1036 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1037
1038 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1039 sim-main.h. Declare a struct hw_descriptor instead of struct
1040 hw_device_descriptor.
1041
1042Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1043
1044 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1045 right bits and then re-align left hand bytes to correct byte
1046 lanes. Fix incorrect computation in do_store_left when loading
1047 bytes from second word.
1048
1049Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1050
1051 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1052 * interp.c (sim_open): Only create a device tree when HW is
1053 enabled.
1054
1055 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1056 * interp.c (signal_exception): Ditto.
1057
1058Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1059
1060 * gencode.c: Mark BEGEZALL as LIKELY.
1061
1062Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1063
1064 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1065 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1066
1067Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1068
1069 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1070 modules. Recognize TX39 target with "mips*tx39" pattern.
1071 * configure: Rebuilt.
1072 * sim-main.h (*): Added many macros defining bits in
1073 TX39 control registers.
1074 (SignalInterrupt): Send actual PC instead of NULL.
1075 (SignalNMIReset): New exception type.
1076 * interp.c (board): New variable for future use to identify
1077 a particular board being simulated.
1078 (mips_option_handler,mips_options): Added "--board" option.
1079 (interrupt_event): Send actual PC.
1080 (sim_open): Make memory layout conditional on board setting.
1081 (signal_exception): Initial implementation of hardware interrupt
1082 handling. Accept another break instruction variant for simulator
1083 exit.
1084 (decode_coproc): Implement RFE instruction for TX39.
1085 (mips.igen): Decode RFE instruction as such.
1086 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1087 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1088 bbegin to implement memory map.
1089 * dv-tx3904cpu.c: New file.
1090 * dv-tx3904irc.c: New file.
1091
1092Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1093
1094 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1095
1096Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1097
1098 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1099 with calls to check_div_hilo.
1100
1101Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1102
1103 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1104 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1105 Add special r3900 version of do_mult_hilo.
1106 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1107 with calls to check_mult_hilo.
1108 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1109 with calls to check_div_hilo.
1110
1111Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1112
1113 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1114 Document a replacement.
1115
1116Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1117
1118 * interp.c (sim_monitor): Make mon_printf work.
1119
1120Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1121
1122 * sim-main.h (INSN_NAME): New arg `cpu'.
1123
1124Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1125
1126 * configure: Regenerated to track ../common/aclocal.m4 changes.
1127
1128Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1129
1130 * configure: Regenerated to track ../common/aclocal.m4 changes.
1131 * config.in: Ditto.
1132
1133Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1134
1135 * acconfig.h: New file.
1136 * configure.in: Reverted change of Apr 24; use sinclude again.
1137
1138Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1139
1140 * configure: Regenerated to track ../common/aclocal.m4 changes.
1141 * config.in: Ditto.
1142
1143Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1144
1145 * configure.in: Don't call sinclude.
1146
1147Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1148
1149 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1150
1151Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1152
1153 * mips.igen (ERET): Implement.
1154
1155 * interp.c (decode_coproc): Return sign-extended EPC.
1156
1157 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1158
1159 * interp.c (signal_exception): Do not ignore Trap.
1160 (signal_exception): On TRAP, restart at exception address.
1161 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1162 (signal_exception): Update.
1163 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1164 so that TRAP instructions are caught.
1165
1166Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1167
1168 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1169 contains HI/LO access history.
1170 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1171 (HIACCESS, LOACCESS): Delete, replace with
1172 (HIHISTORY, LOHISTORY): New macros.
1173 (CHECKHILO): Delete all, moved to mips.igen
1174
1175 * gencode.c (build_instruction): Do not generate checks for
1176 correct HI/LO register usage.
1177
1178 * interp.c (old_engine_run): Delete checks for correct HI/LO
1179 register usage.
1180
1181 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1182 check_mf_cycles): New functions.
1183 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1184 do_divu, domultx, do_mult, do_multu): Use.
1185
1186 * tx.igen ("madd", "maddu"): Use.
1187
1188Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1189
1190 * mips.igen (DSRAV): Use function do_dsrav.
1191 (SRAV): Use new function do_srav.
1192
1193 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1194 (B): Sign extend 11 bit immediate.
1195 (EXT-B*): Shift 16 bit immediate left by 1.
1196 (ADDIU*): Don't sign extend immediate value.
1197
1198Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1199
1200 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1201
1202 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1203 functions.
1204
1205 * mips.igen (delayslot32, nullify_next_insn): New functions.
1206 (m16.igen): Always include.
1207 (do_*): Add more tracing.
1208
1209 * m16.igen (delayslot16): Add NIA argument, could be called by a
1210 32 bit MIPS16 instruction.
1211
1212 * interp.c (ifetch16): Move function from here.
1213 * sim-main.c (ifetch16): To here.
1214
1215 * sim-main.c (ifetch16, ifetch32): Update to match current
1216 implementations of LH, LW.
1217 (signal_exception): Don't print out incorrect hex value of illegal
1218 instruction.
1219
1220Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1221
1222 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1223 instruction.
1224
1225 * m16.igen: Implement MIPS16 instructions.
1226
1227 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1228 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1229 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1230 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1231 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1232 bodies of corresponding code from 32 bit insn to these. Also used
1233 by MIPS16 versions of functions.
1234
1235 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1236 (IMEM16): Drop NR argument from macro.
1237
1238Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 * Makefile.in (SIM_OBJS): Add sim-main.o.
1241
1242 * sim-main.h (address_translation, load_memory, store_memory,
1243 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1244 as INLINE_SIM_MAIN.
1245 (pr_addr, pr_uword64): Declare.
1246 (sim-main.c): Include when H_REVEALS_MODULE_P.
1247
1248 * interp.c (address_translation, load_memory, store_memory,
1249 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1250 from here.
1251 * sim-main.c: To here. Fix compilation problems.
1252
1253 * configure.in: Enable inlining.
1254 * configure: Re-config.
1255
1256Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1257
1258 * configure: Regenerated to track ../common/aclocal.m4 changes.
1259
1260Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1261
1262 * mips.igen: Include tx.igen.
1263 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1264 * tx.igen: New file, contains MADD and MADDU.
1265
1266 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1267 the hardwired constant `7'.
1268 (store_memory): Ditto.
1269 (LOADDRMASK): Move definition to sim-main.h.
1270
1271 mips.igen (MTC0): Enable for r3900.
1272 (ADDU): Add trace.
1273
1274 mips.igen (do_load_byte): Delete.
1275 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1276 do_store_right): New functions.
1277 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1278
1279 configure.in: Let the tx39 use igen again.
1280 configure: Update.
1281
1282Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1283
1284 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1285 not an address sized quantity. Return zero for cache sizes.
1286
1287Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1288
1289 * mips.igen (r3900): r3900 does not support 64 bit integer
1290 operations.
1291
1292Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1293
1294 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1295 than igen one.
1296 * configure : Rebuild.
1297
1298Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 * configure: Regenerated to track ../common/aclocal.m4 changes.
1301
1302Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1303
1304 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1305
1306Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1307
1308 * configure: Regenerated to track ../common/aclocal.m4 changes.
1309 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1310
1311Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312
1313 * configure: Regenerated to track ../common/aclocal.m4 changes.
1314
1315Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1316
1317 * interp.c (Max, Min): Comment out functions. Not yet used.
1318
1319Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1320
1321 * configure: Regenerated to track ../common/aclocal.m4 changes.
1322
1323Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1324
1325 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1326 configurable settings for stand-alone simulator.
1327
1328 * configure.in: Added X11 search, just in case.
1329
1330 * configure: Regenerated.
1331
1332Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1333
1334 * interp.c (sim_write, sim_read, load_memory, store_memory):
1335 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1336
1337Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1338
1339 * sim-main.h (GETFCC): Return an unsigned value.
1340
1341Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1344 (DADD): Result destination is RD not RT.
1345
1346Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1347
1348 * sim-main.h (HIACCESS, LOACCESS): Always define.
1349
1350 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1351
1352 * interp.c (sim_info): Delete.
1353
1354Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1355
1356 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1357 (mips_option_handler): New argument `cpu'.
1358 (sim_open): Update call to sim_add_option_table.
1359
1360Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * mips.igen (CxC1): Add tracing.
1363
1364Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1365
1366 * sim-main.h (Max, Min): Declare.
1367
1368 * interp.c (Max, Min): New functions.
1369
1370 * mips.igen (BC1): Add tracing.
1371
1372Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1373
1374 * interp.c Added memory map for stack in vr4100
1375
1376Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1377
1378 * interp.c (load_memory): Add missing "break"'s.
1379
1380Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1381
1382 * interp.c (sim_store_register, sim_fetch_register): Pass in
1383 length parameter. Return -1.
1384
1385Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1386
1387 * interp.c: Added hardware init hook, fixed warnings.
1388
1389Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1390
1391 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1392
1393Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1394
1395 * interp.c (ifetch16): New function.
1396
1397 * sim-main.h (IMEM32): Rename IMEM.
1398 (IMEM16_IMMED): Define.
1399 (IMEM16): Define.
1400 (DELAY_SLOT): Update.
1401
1402 * m16run.c (sim_engine_run): New file.
1403
1404 * m16.igen: All instructions except LB.
1405 (LB): Call do_load_byte.
1406 * mips.igen (do_load_byte): New function.
1407 (LB): Call do_load_byte.
1408
1409 * mips.igen: Move spec for insn bit size and high bit from here.
1410 * Makefile.in (tmp-igen, tmp-m16): To here.
1411
1412 * m16.dc: New file, decode mips16 instructions.
1413
1414 * Makefile.in (SIM_NO_ALL): Define.
1415 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1416
1417Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1418
1419 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1420 point unit to 32 bit registers.
1421 * configure: Re-generate.
1422
1423Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * configure.in (sim_use_gen): Make IGEN the default simulator
1426 generator for generic 32 and 64 bit mips targets.
1427 * configure: Re-generate.
1428
1429Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1430
1431 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1432 bitsize.
1433
1434 * interp.c (sim_fetch_register, sim_store_register): Read/write
1435 FGR from correct location.
1436 (sim_open): Set size of FGR's according to
1437 WITH_TARGET_FLOATING_POINT_BITSIZE.
1438
1439 * sim-main.h (FGR): Store floating point registers in a separate
1440 array.
1441
1442Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * configure: Regenerated to track ../common/aclocal.m4 changes.
1445
1446Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1449
1450 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1451
1452 * interp.c (pending_tick): New function. Deliver pending writes.
1453
1454 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1455 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1456 it can handle mixed sized quantites and single bits.
1457
1458Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1459
1460 * interp.c (oengine.h): Do not include when building with IGEN.
1461 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1462 (sim_info): Ditto for PROCESSOR_64BIT.
1463 (sim_monitor): Replace ut_reg with unsigned_word.
1464 (*): Ditto for t_reg.
1465 (LOADDRMASK): Define.
1466 (sim_open): Remove defunct check that host FP is IEEE compliant,
1467 using software to emulate floating point.
1468 (value_fpr, ...): Always compile, was conditional on HASFPU.
1469
1470Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1471
1472 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1473 size.
1474
1475 * interp.c (SD, CPU): Define.
1476 (mips_option_handler): Set flags in each CPU.
1477 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1478 (sim_close): Do not clear STATE, deleted anyway.
1479 (sim_write, sim_read): Assume CPU zero's vm should be used for
1480 data transfers.
1481 (sim_create_inferior): Set the PC for all processors.
1482 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1483 argument.
1484 (mips16_entry): Pass correct nr of args to store_word, load_word.
1485 (ColdReset): Cold reset all cpu's.
1486 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1487 (sim_monitor, load_memory, store_memory, signal_exception): Use
1488 `CPU' instead of STATE_CPU.
1489
1490
1491 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1492 SD or CPU_.
1493
1494 * sim-main.h (signal_exception): Add sim_cpu arg.
1495 (SignalException*): Pass both SD and CPU to signal_exception.
1496 * interp.c (signal_exception): Update.
1497
1498 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1499 Ditto
1500 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1501 address_translation): Ditto
1502 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1503
1504Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1505
1506 * configure: Regenerated to track ../common/aclocal.m4 changes.
1507
1508Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1509
1510 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1511
1512 * mips.igen (model): Map processor names onto BFD name.
1513
1514 * sim-main.h (CPU_CIA): Delete.
1515 (SET_CIA, GET_CIA): Define
1516
1517Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1520 regiser.
1521
1522 * configure.in (default_endian): Configure a big-endian simulator
1523 by default.
1524 * configure: Re-generate.
1525
1526Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1527
1528 * configure: Regenerated to track ../common/aclocal.m4 changes.
1529
1530Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1531
1532 * interp.c (sim_monitor): Handle Densan monitor outbyte
1533 and inbyte functions.
1534
15351997-12-29 Felix Lee <flee@cygnus.com>
1536
1537 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1538
1539Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1540
1541 * Makefile.in (tmp-igen): Arrange for $zero to always be
1542 reset to zero after every instruction.
1543
1544Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1545
1546 * configure: Regenerated to track ../common/aclocal.m4 changes.
1547 * config.in: Ditto.
1548
1549Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1550
1551 * mips.igen (MSUB): Fix to work like MADD.
1552 * gencode.c (MSUB): Similarly.
1553
1554Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1555
1556 * configure: Regenerated to track ../common/aclocal.m4 changes.
1557
1558Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1561
1562Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1563
1564 * sim-main.h (sim-fpu.h): Include.
1565
1566 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1567 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1568 using host independant sim_fpu module.
1569
1570Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * interp.c (signal_exception): Report internal errors with SIGABRT
1573 not SIGQUIT.
1574
1575 * sim-main.h (C0_CONFIG): New register.
1576 (signal.h): No longer include.
1577
1578 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1579
1580Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1581
1582 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1583
1584Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1585
1586 * mips.igen: Tag vr5000 instructions.
1587 (ANDI): Was missing mipsIV model, fix assembler syntax.
1588 (do_c_cond_fmt): New function.
1589 (C.cond.fmt): Handle mips I-III which do not support CC field
1590 separatly.
1591 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1592 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1593 in IV3.2 spec.
1594 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1595 vr5000 which saves LO in a GPR separatly.
1596
1597 * configure.in (enable-sim-igen): For vr5000, select vr5000
1598 specific instructions.
1599 * configure: Re-generate.
1600
1601Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1602
1603 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1604
1605 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1606 fmt_uninterpreted_64 bit cases to switch. Convert to
1607 fmt_formatted,
1608
1609 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1610
1611 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1612 as specified in IV3.2 spec.
1613 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1614
1615Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1616
1617 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1618 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1619 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1620 PENDING_FILL versions of instructions. Simplify.
1621 (X): New function.
1622 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1623 instructions.
1624 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1625 a signed value.
1626 (MTHI, MFHI): Disable code checking HI-LO.
1627
1628 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1629 global.
1630 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1631
1632Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * gencode.c (build_mips16_operands): Replace IPC with cia.
1635
1636 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1637 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1638 IPC to `cia'.
1639 (UndefinedResult): Replace function with macro/function
1640 combination.
1641 (sim_engine_run): Don't save PC in IPC.
1642
1643 * sim-main.h (IPC): Delete.
1644
1645
1646 * interp.c (signal_exception, store_word, load_word,
1647 address_translation, load_memory, store_memory, cache_op,
1648 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1649 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1650 current instruction address - cia - argument.
1651 (sim_read, sim_write): Call address_translation directly.
1652 (sim_engine_run): Rename variable vaddr to cia.
1653 (signal_exception): Pass cia to sim_monitor
1654
1655 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1656 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1657 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1658
1659 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1660 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1661 SIM_ASSERT.
1662
1663 * interp.c (signal_exception): Pass restart address to
1664 sim_engine_restart.
1665
1666 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1667 idecode.o): Add dependency.
1668
1669 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1670 Delete definitions
1671 (DELAY_SLOT): Update NIA not PC with branch address.
1672 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1673
1674 * mips.igen: Use CIA not PC in branch calculations.
1675 (illegal): Call SignalException.
1676 (BEQ, ADDIU): Fix assembler.
1677
1678Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * m16.igen (JALX): Was missing.
1681
1682 * configure.in (enable-sim-igen): New configuration option.
1683 * configure: Re-generate.
1684
1685 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1686
1687 * interp.c (load_memory, store_memory): Delete parameter RAW.
1688 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1689 bypassing {load,store}_memory.
1690
1691 * sim-main.h (ByteSwapMem): Delete definition.
1692
1693 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1694
1695 * interp.c (sim_do_command, sim_commands): Delete mips specific
1696 commands. Handled by module sim-options.
1697
1698 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1699 (WITH_MODULO_MEMORY): Define.
1700
1701 * interp.c (sim_info): Delete code printing memory size.
1702
1703 * interp.c (mips_size): Nee sim_size, delete function.
1704 (power2): Delete.
1705 (monitor, monitor_base, monitor_size): Delete global variables.
1706 (sim_open, sim_close): Delete code creating monitor and other
1707 memory regions. Use sim-memopts module, via sim_do_commandf, to
1708 manage memory regions.
1709 (load_memory, store_memory): Use sim-core for memory model.
1710
1711 * interp.c (address_translation): Delete all memory map code
1712 except line forcing 32 bit addresses.
1713
1714Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1717 trace options.
1718
1719 * interp.c (logfh, logfile): Delete globals.
1720 (sim_open, sim_close): Delete code opening & closing log file.
1721 (mips_option_handler): Delete -l and -n options.
1722 (OPTION mips_options): Ditto.
1723
1724 * interp.c (OPTION mips_options): Rename option trace to dinero.
1725 (mips_option_handler): Update.
1726
1727Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1728
1729 * interp.c (fetch_str): New function.
1730 (sim_monitor): Rewrite using sim_read & sim_write.
1731 (sim_open): Check magic number.
1732 (sim_open): Write monitor vectors into memory using sim_write.
1733 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1734 (sim_read, sim_write): Simplify - transfer data one byte at a
1735 time.
1736 (load_memory, store_memory): Clarify meaning of parameter RAW.
1737
1738 * sim-main.h (isHOST): Defete definition.
1739 (isTARGET): Mark as depreciated.
1740 (address_translation): Delete parameter HOST.
1741
1742 * interp.c (address_translation): Delete parameter HOST.
1743
1744Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1745
1746 * mips.igen:
1747
1748 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1749 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1750
1751Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * mips.igen: Add model filter field to records.
1754
1755Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1756
1757 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1758
1759 interp.c (sim_engine_run): Do not compile function sim_engine_run
1760 when WITH_IGEN == 1.
1761
1762 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1763 target architecture.
1764
1765 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1766 igen. Replace with configuration variables sim_igen_flags /
1767 sim_m16_flags.
1768
1769 * m16.igen: New file. Copy mips16 insns here.
1770 * mips.igen: From here.
1771
1772Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1775 to top.
1776 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1777
1778Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1779
1780 * gencode.c (build_instruction): Follow sim_write's lead in using
1781 BigEndianMem instead of !ByteSwapMem.
1782
1783Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * configure.in (sim_gen): Dependent on target, select type of
1786 generator. Always select old style generator.
1787
1788 configure: Re-generate.
1789
1790 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1791 targets.
1792 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1793 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1794 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1795 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1796 SIM_@sim_gen@_*, set by autoconf.
1797
1798Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1799
1800 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1801
1802 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1803 CURRENT_FLOATING_POINT instead.
1804
1805 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1806 (address_translation): Raise exception InstructionFetch when
1807 translation fails and isINSTRUCTION.
1808
1809 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1810 sim_engine_run): Change type of of vaddr and paddr to
1811 address_word.
1812 (address_translation, prefetch, load_memory, store_memory,
1813 cache_op): Change type of vAddr and pAddr to address_word.
1814
1815 * gencode.c (build_instruction): Change type of vaddr and paddr to
1816 address_word.
1817
1818Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1821 macro to obtain result of ALU op.
1822
1823Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 * interp.c (sim_info): Call profile_print.
1826
1827Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1828
1829 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1830
1831 * sim-main.h (WITH_PROFILE): Do not define, defined in
1832 common/sim-config.h. Use sim-profile module.
1833 (simPROFILE): Delete defintion.
1834
1835 * interp.c (PROFILE): Delete definition.
1836 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1837 (sim_close): Delete code writing profile histogram.
1838 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1839 Delete.
1840 (sim_engine_run): Delete code profiling the PC.
1841
1842Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1843
1844 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1845
1846 * interp.c (sim_monitor): Make register pointers of type
1847 unsigned_word*.
1848
1849 * sim-main.h: Make registers of type unsigned_word not
1850 signed_word.
1851
1852Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * interp.c (sync_operation): Rename from SyncOperation, make
1855 global, add SD argument.
1856 (prefetch): Rename from Prefetch, make global, add SD argument.
1857 (decode_coproc): Make global.
1858
1859 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1860
1861 * gencode.c (build_instruction): Generate DecodeCoproc not
1862 decode_coproc calls.
1863
1864 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1865 (SizeFGR): Move to sim-main.h
1866 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1867 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1868 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1869 sim-main.h.
1870 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1871 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1872 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1873 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1874 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1875 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1876
1877 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1878 exception.
1879 (sim-alu.h): Include.
1880 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1881 (sim_cia): Typedef to instruction_address.
1882
1883Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1884
1885 * Makefile.in (interp.o): Rename generated file engine.c to
1886 oengine.c.
1887
1888 * interp.c: Update.
1889
1890Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1891
1892 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1893
1894Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * gencode.c (build_instruction): For "FPSQRT", output correct
1897 number of arguments to Recip.
1898
1899Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * Makefile.in (interp.o): Depends on sim-main.h
1902
1903 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1904
1905 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1906 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1907 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1908 STATE, DSSTATE): Define
1909 (GPR, FGRIDX, ..): Define.
1910
1911 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1912 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1913 (GPR, FGRIDX, ...): Delete macros.
1914
1915 * interp.c: Update names to match defines from sim-main.h
1916
1917Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * interp.c (sim_monitor): Add SD argument.
1920 (sim_warning): Delete. Replace calls with calls to
1921 sim_io_eprintf.
1922 (sim_error): Delete. Replace calls with sim_io_error.
1923 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1924 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1925 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1926 argument.
1927 (mips_size): Rename from sim_size. Add SD argument.
1928
1929 * interp.c (simulator): Delete global variable.
1930 (callback): Delete global variable.
1931 (mips_option_handler, sim_open, sim_write, sim_read,
1932 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1933 sim_size,sim_monitor): Use sim_io_* not callback->*.
1934 (sim_open): ZALLOC simulator struct.
1935 (PROFILE): Do not define.
1936
1937Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1938
1939 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1940 support.h with corresponding code.
1941
1942 * sim-main.h (word64, uword64), support.h: Move definition to
1943 sim-main.h.
1944 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1945
1946 * support.h: Delete
1947 * Makefile.in: Update dependencies
1948 * interp.c: Do not include.
1949
1950Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1951
1952 * interp.c (address_translation, load_memory, store_memory,
1953 cache_op): Rename to from AddressTranslation et.al., make global,
1954 add SD argument
1955
1956 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1957 CacheOp): Define.
1958
1959 * interp.c (SignalException): Rename to signal_exception, make
1960 global.
1961
1962 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1963
1964 * sim-main.h (SignalException, SignalExceptionInterrupt,
1965 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1966 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1967 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1968 Define.
1969
1970 * interp.c, support.h: Use.
1971
1972Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1975 to value_fpr / store_fpr. Add SD argument.
1976 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1977 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1978
1979 * sim-main.h (ValueFPR, StoreFPR): Define.
1980
1981Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1982
1983 * interp.c (sim_engine_run): Check consistency between configure
1984 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1985 and HASFPU.
1986
1987 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1988 (mips_fpu): Configure WITH_FLOATING_POINT.
1989 (mips_endian): Configure WITH_TARGET_ENDIAN.
1990 * configure: Update.
1991
1992Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1993
1994 * configure: Regenerated to track ../common/aclocal.m4 changes.
1995
1996Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1997
1998 * configure: Regenerated.
1999
2000Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2001
2002 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2003
2004Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005
2006 * gencode.c (print_igen_insn_models): Assume certain architectures
2007 include all mips* instructions.
2008 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2009 instruction.
2010
2011 * Makefile.in (tmp.igen): Add target. Generate igen input from
2012 gencode file.
2013
2014 * gencode.c (FEATURE_IGEN): Define.
2015 (main): Add --igen option. Generate output in igen format.
2016 (process_instructions): Format output according to igen option.
2017 (print_igen_insn_format): New function.
2018 (print_igen_insn_models): New function.
2019 (process_instructions): Only issue warnings and ignore
2020 instructions when no FEATURE_IGEN.
2021
2022Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2025 MIPS targets.
2026
2027Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * configure: Regenerated to track ../common/aclocal.m4 changes.
2030
2031Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2034 SIM_RESERVED_BITS): Delete, moved to common.
2035 (SIM_EXTRA_CFLAGS): Update.
2036
2037Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2038
2039 * configure.in: Configure non-strict memory alignment.
2040 * configure: Regenerated to track ../common/aclocal.m4 changes.
2041
2042Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043
2044 * configure: Regenerated to track ../common/aclocal.m4 changes.
2045
2046Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2047
2048 * gencode.c (SDBBP,DERET): Added (3900) insns.
2049 (RFE): Turn on for 3900.
2050 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2051 (dsstate): Made global.
2052 (SUBTARGET_R3900): Added.
2053 (CANCELDELAYSLOT): New.
2054 (SignalException): Ignore SystemCall rather than ignore and
2055 terminate. Add DebugBreakPoint handling.
2056 (decode_coproc): New insns RFE, DERET; and new registers Debug
2057 and DEPC protected by SUBTARGET_R3900.
2058 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2059 bits explicitly.
2060 * Makefile.in,configure.in: Add mips subtarget option.
2061 * configure: Update.
2062
2063Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2064
2065 * gencode.c: Add r3900 (tx39).
2066
2067
2068Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2069
2070 * gencode.c (build_instruction): Don't need to subtract 4 for
2071 JALR, just 2.
2072
2073Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2074
2075 * interp.c: Correct some HASFPU problems.
2076
2077Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * configure: Regenerated to track ../common/aclocal.m4 changes.
2080
2081Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2082
2083 * interp.c (mips_options): Fix samples option short form, should
2084 be `x'.
2085
2086Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * interp.c (sim_info): Enable info code. Was just returning.
2089
2090Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2091
2092 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2093 MFC0.
2094
2095Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2096
2097 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2098 constants.
2099 (build_instruction): Ditto for LL.
2100
2101Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2102
2103 * configure: Regenerated to track ../common/aclocal.m4 changes.
2104
2105Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * configure: Regenerated to track ../common/aclocal.m4 changes.
2108 * config.in: Ditto.
2109
2110Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * interp.c (sim_open): Add call to sim_analyze_program, update
2113 call to sim_config.
2114
2115Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * interp.c (sim_kill): Delete.
2118 (sim_create_inferior): Add ABFD argument. Set PC from same.
2119 (sim_load): Move code initializing trap handlers from here.
2120 (sim_open): To here.
2121 (sim_load): Delete, use sim-hload.c.
2122
2123 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2124
2125Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2126
2127 * configure: Regenerated to track ../common/aclocal.m4 changes.
2128 * config.in: Ditto.
2129
2130Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2131
2132 * interp.c (sim_open): Add ABFD argument.
2133 (sim_load): Move call to sim_config from here.
2134 (sim_open): To here. Check return status.
2135
2136Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2137
2138 * gencode.c (build_instruction): Two arg MADD should
2139 not assign result to $0.
2140
2141Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2142
2143 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2144 * sim/mips/configure.in: Regenerate.
2145
2146Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2147
2148 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2149 signed8, unsigned8 et.al. types.
2150
2151 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2152 hosts when selecting subreg.
2153
2154Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2155
2156 * interp.c (sim_engine_run): Reset the ZERO register to zero
2157 regardless of FEATURE_WARN_ZERO.
2158 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2159
2160Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2161
2162 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2163 (SignalException): For BreakPoints ignore any mode bits and just
2164 save the PC.
2165 (SignalException): Always set the CAUSE register.
2166
2167Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2168
2169 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2170 exception has been taken.
2171
2172 * interp.c: Implement the ERET and mt/f sr instructions.
2173
2174Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175
2176 * interp.c (SignalException): Don't bother restarting an
2177 interrupt.
2178
2179Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * interp.c (SignalException): Really take an interrupt.
2182 (interrupt_event): Only deliver interrupts when enabled.
2183
2184Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2185
2186 * interp.c (sim_info): Only print info when verbose.
2187 (sim_info) Use sim_io_printf for output.
2188
2189Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2190
2191 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2192 mips architectures.
2193
2194Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2195
2196 * interp.c (sim_do_command): Check for common commands if a
2197 simulator specific command fails.
2198
2199Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2200
2201 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2202 and simBE when DEBUG is defined.
2203
2204Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2205
2206 * interp.c (interrupt_event): New function. Pass exception event
2207 onto exception handler.
2208
2209 * configure.in: Check for stdlib.h.
2210 * configure: Regenerate.
2211
2212 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2213 variable declaration.
2214 (build_instruction): Initialize memval1.
2215 (build_instruction): Add UNUSED attribute to byte, bigend,
2216 reverse.
2217 (build_operands): Ditto.
2218
2219 * interp.c: Fix GCC warnings.
2220 (sim_get_quit_code): Delete.
2221
2222 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2223 * Makefile.in: Ditto.
2224 * configure: Re-generate.
2225
2226 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2227
2228Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * interp.c (mips_option_handler): New function parse argumes using
2231 sim-options.
2232 (myname): Replace with STATE_MY_NAME.
2233 (sim_open): Delete check for host endianness - performed by
2234 sim_config.
2235 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2236 (sim_open): Move much of the initialization from here.
2237 (sim_load): To here. After the image has been loaded and
2238 endianness set.
2239 (sim_open): Move ColdReset from here.
2240 (sim_create_inferior): To here.
2241 (sim_open): Make FP check less dependant on host endianness.
2242
2243 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2244 run.
2245 * interp.c (sim_set_callbacks): Delete.
2246
2247 * interp.c (membank, membank_base, membank_size): Replace with
2248 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2249 (sim_open): Remove call to callback->init. gdb/run do this.
2250
2251 * interp.c: Update
2252
2253 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2254
2255 * interp.c (big_endian_p): Delete, replaced by
2256 current_target_byte_order.
2257
2258Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * interp.c (host_read_long, host_read_word, host_swap_word,
2261 host_swap_long): Delete. Using common sim-endian.
2262 (sim_fetch_register, sim_store_register): Use H2T.
2263 (pipeline_ticks): Delete. Handled by sim-events.
2264 (sim_info): Update.
2265 (sim_engine_run): Update.
2266
2267Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2270 reason from here.
2271 (SignalException): To here. Signal using sim_engine_halt.
2272 (sim_stop_reason): Delete, moved to common.
2273
2274Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2275
2276 * interp.c (sim_open): Add callback argument.
2277 (sim_set_callbacks): Delete SIM_DESC argument.
2278 (sim_size): Ditto.
2279
2280Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * Makefile.in (SIM_OBJS): Add common modules.
2283
2284 * interp.c (sim_set_callbacks): Also set SD callback.
2285 (set_endianness, xfer_*, swap_*): Delete.
2286 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2287 Change to functions using sim-endian macros.
2288 (control_c, sim_stop): Delete, use common version.
2289 (simulate): Convert into.
2290 (sim_engine_run): This function.
2291 (sim_resume): Delete.
2292
2293 * interp.c (simulation): New variable - the simulator object.
2294 (sim_kind): Delete global - merged into simulation.
2295 (sim_load): Cleanup. Move PC assignment from here.
2296 (sim_create_inferior): To here.
2297
2298 * sim-main.h: New file.
2299 * interp.c (sim-main.h): Include.
2300
2301Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2302
2303 * configure: Regenerated to track ../common/aclocal.m4 changes.
2304
2305Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2306
2307 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2308
2309Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2310
2311 * gencode.c (build_instruction): DIV instructions: check
2312 for division by zero and integer overflow before using
2313 host's division operation.
2314
2315Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2316
2317 * Makefile.in (SIM_OBJS): Add sim-load.o.
2318 * interp.c: #include bfd.h.
2319 (target_byte_order): Delete.
2320 (sim_kind, myname, big_endian_p): New static locals.
2321 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2322 after argument parsing. Recognize -E arg, set endianness accordingly.
2323 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2324 load file into simulator. Set PC from bfd.
2325 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2326 (set_endianness): Use big_endian_p instead of target_byte_order.
2327
2328Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2329
2330 * interp.c (sim_size): Delete prototype - conflicts with
2331 definition in remote-sim.h. Correct definition.
2332
2333Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2334
2335 * configure: Regenerated to track ../common/aclocal.m4 changes.
2336 * config.in: Ditto.
2337
2338Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2339
2340 * interp.c (sim_open): New arg `kind'.
2341
2342 * configure: Regenerated to track ../common/aclocal.m4 changes.
2343
2344Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2345
2346 * configure: Regenerated to track ../common/aclocal.m4 changes.
2347
2348Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2349
2350 * interp.c (sim_open): Set optind to 0 before calling getopt.
2351
2352Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2353
2354 * configure: Regenerated to track ../common/aclocal.m4 changes.
2355
2356Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2357
2358 * interp.c : Replace uses of pr_addr with pr_uword64
2359 where the bit length is always 64 independent of SIM_ADDR.
2360 (pr_uword64) : added.
2361
2362Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2363
2364 * configure: Re-generate.
2365
2366Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2367
2368 * configure: Regenerate to track ../common/aclocal.m4 changes.
2369
2370Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2371
2372 * interp.c (sim_open): New SIM_DESC result. Argument is now
2373 in argv form.
2374 (other sim_*): New SIM_DESC argument.
2375
2376Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2377
2378 * interp.c: Fix printing of addresses for non-64-bit targets.
2379 (pr_addr): Add function to print address based on size.
2380
2381Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2382
2383 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2384
2385Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2386
2387 * gencode.c (build_mips16_operands): Correct computation of base
2388 address for extended PC relative instruction.
2389
2390Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2391
2392 * interp.c (mips16_entry): Add support for floating point cases.
2393 (SignalException): Pass floating point cases to mips16_entry.
2394 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2395 registers.
2396 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2397 or fmt_word.
2398 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2399 and then set the state to fmt_uninterpreted.
2400 (COP_SW): Temporarily set the state to fmt_word while calling
2401 ValueFPR.
2402
2403Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2404
2405 * gencode.c (build_instruction): The high order may be set in the
2406 comparison flags at any ISA level, not just ISA 4.
2407
2408Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2409
2410 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2411 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2412 * configure.in: sinclude ../common/aclocal.m4.
2413 * configure: Regenerated.
2414
2415Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2416
2417 * configure: Rebuild after change to aclocal.m4.
2418
2419Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2420
2421 * configure configure.in Makefile.in: Update to new configure
2422 scheme which is more compatible with WinGDB builds.
2423 * configure.in: Improve comment on how to run autoconf.
2424 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2425 * Makefile.in: Use autoconf substitution to install common
2426 makefile fragment.
2427
2428Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2429
2430 * gencode.c (build_instruction): Use BigEndianCPU instead of
2431 ByteSwapMem.
2432
2433Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2434
2435 * interp.c (sim_monitor): Make output to stdout visible in
2436 wingdb's I/O log window.
2437
2438Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2439
2440 * support.h: Undo previous change to SIGTRAP
2441 and SIGQUIT values.
2442
2443Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2444
2445 * interp.c (store_word, load_word): New static functions.
2446 (mips16_entry): New static function.
2447 (SignalException): Look for mips16 entry and exit instructions.
2448 (simulate): Use the correct index when setting fpr_state after
2449 doing a pending move.
2450
2451Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2452
2453 * interp.c: Fix byte-swapping code throughout to work on
2454 both little- and big-endian hosts.
2455
2456Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2457
2458 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2459 with gdb/config/i386/xm-windows.h.
2460
2461Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2462
2463 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2464 that messes up arithmetic shifts.
2465
2466Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2467
2468 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2469 SIGTRAP and SIGQUIT for _WIN32.
2470
2471Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2472
2473 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2474 force a 64 bit multiplication.
2475 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2476 destination register is 0, since that is the default mips16 nop
2477 instruction.
2478
2479Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2480
2481 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2482 (build_endian_shift): Don't check proc64.
2483 (build_instruction): Always set memval to uword64. Cast op2 to
2484 uword64 when shifting it left in memory instructions. Always use
2485 the same code for stores--don't special case proc64.
2486
2487 * gencode.c (build_mips16_operands): Fix base PC value for PC
2488 relative operands.
2489 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2490 jal instruction.
2491 * interp.c (simJALDELAYSLOT): Define.
2492 (JALDELAYSLOT): Define.
2493 (INDELAYSLOT, INJALDELAYSLOT): Define.
2494 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2495
2496Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2497
2498 * interp.c (sim_open): add flush_cache as a PMON routine
2499 (sim_monitor): handle flush_cache by ignoring it
2500
2501Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2502
2503 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2504 BigEndianMem.
2505 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2506 (BigEndianMem): Rename to ByteSwapMem and change sense.
2507 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2508 BigEndianMem references to !ByteSwapMem.
2509 (set_endianness): New function, with prototype.
2510 (sim_open): Call set_endianness.
2511 (sim_info): Use simBE instead of BigEndianMem.
2512 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2513 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2514 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2515 ifdefs, keeping the prototype declaration.
2516 (swap_word): Rewrite correctly.
2517 (ColdReset): Delete references to CONFIG. Delete endianness related
2518 code; moved to set_endianness.
2519
2520Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2521
2522 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2523 * interp.c (CHECKHILO): Define away.
2524 (simSIGINT): New macro.
2525 (membank_size): Increase from 1MB to 2MB.
2526 (control_c): New function.
2527 (sim_resume): Rename parameter signal to signal_number. Add local
2528 variable prev. Call signal before and after simulate.
2529 (sim_stop_reason): Add simSIGINT support.
2530 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2531 functions always.
2532 (sim_warning): Delete call to SignalException. Do call printf_filtered
2533 if logfh is NULL.
2534 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2535 a call to sim_warning.
2536
2537Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2538
2539 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2540 16 bit instructions.
2541
2542Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2543
2544 Add support for mips16 (16 bit MIPS implementation):
2545 * gencode.c (inst_type): Add mips16 instruction encoding types.
2546 (GETDATASIZEINSN): Define.
2547 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2548 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2549 mtlo.
2550 (MIPS16_DECODE): New table, for mips16 instructions.
2551 (bitmap_val): New static function.
2552 (struct mips16_op): Define.
2553 (mips16_op_table): New table, for mips16 operands.
2554 (build_mips16_operands): New static function.
2555 (process_instructions): If PC is odd, decode a mips16
2556 instruction. Break out instruction handling into new
2557 build_instruction function.
2558 (build_instruction): New static function, broken out of
2559 process_instructions. Check modifiers rather than flags for SHIFT
2560 bit count and m[ft]{hi,lo} direction.
2561 (usage): Pass program name to fprintf.
2562 (main): Remove unused variable this_option_optind. Change
2563 ``*loptarg++'' to ``loptarg++''.
2564 (my_strtoul): Parenthesize && within ||.
2565 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2566 (simulate): If PC is odd, fetch a 16 bit instruction, and
2567 increment PC by 2 rather than 4.
2568 * configure.in: Add case for mips16*-*-*.
2569 * configure: Rebuild.
2570
2571Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2572
2573 * interp.c: Allow -t to enable tracing in standalone simulator.
2574 Fix garbage output in trace file and error messages.
2575
2576Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2577
2578 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2579 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2580 * configure.in: Simplify using macros in ../common/aclocal.m4.
2581 * configure: Regenerated.
2582 * tconfig.in: New file.
2583
2584Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2585
2586 * interp.c: Fix bugs in 64-bit port.
2587 Use ansi function declarations for msvc compiler.
2588 Initialize and test file pointer in trace code.
2589 Prevent duplicate definition of LAST_EMED_REGNUM.
2590
2591Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2592
2593 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2594
2595Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2596
2597 * interp.c (SignalException): Check for explicit terminating
2598 breakpoint value.
2599 * gencode.c: Pass instruction value through SignalException()
2600 calls for Trap, Breakpoint and Syscall.
2601
2602Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2603
2604 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2605 only used on those hosts that provide it.
2606 * configure.in: Add sqrt() to list of functions to be checked for.
2607 * config.in: Re-generated.
2608 * configure: Re-generated.
2609
2610Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2611
2612 * gencode.c (process_instructions): Call build_endian_shift when
2613 expanding STORE RIGHT, to fix swr.
2614 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2615 clear the high bits.
2616 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2617 Fix float to int conversions to produce signed values.
2618
2619Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2620
2621 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2622 (process_instructions): Correct handling of nor instruction.
2623 Correct shift count for 32 bit shift instructions. Correct sign
2624 extension for arithmetic shifts to not shift the number of bits in
2625 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2626 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2627 Fix madd.
2628 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2629 It's OK to have a mult follow a mult. What's not OK is to have a
2630 mult follow an mfhi.
2631 (Convert): Comment out incorrect rounding code.
2632
2633Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2634
2635 * interp.c (sim_monitor): Improved monitor printf
2636 simulation. Tidied up simulator warnings, and added "--log" option
2637 for directing warning message output.
2638 * gencode.c: Use sim_warning() rather than WARNING macro.
2639
2640Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2641
2642 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2643 getopt1.o, rather than on gencode.c. Link objects together.
2644 Don't link against -liberty.
2645 (gencode.o, getopt.o, getopt1.o): New targets.
2646 * gencode.c: Include <ctype.h> and "ansidecl.h".
2647 (AND): Undefine after including "ansidecl.h".
2648 (ULONG_MAX): Define if not defined.
2649 (OP_*): Don't define macros; now defined in opcode/mips.h.
2650 (main): Call my_strtoul rather than strtoul.
2651 (my_strtoul): New static function.
2652
2653Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2654
2655 * gencode.c (process_instructions): Generate word64 and uword64
2656 instead of `long long' and `unsigned long long' data types.
2657 * interp.c: #include sysdep.h to get signals, and define default
2658 for SIGBUS.
2659 * (Convert): Work around for Visual-C++ compiler bug with type
2660 conversion.
2661 * support.h: Make things compile under Visual-C++ by using
2662 __int64 instead of `long long'. Change many refs to long long
2663 into word64/uword64 typedefs.
2664
2665Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2666
2667 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2668 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2669 (docdir): Removed.
2670 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2671 (AC_PROG_INSTALL): Added.
2672 (AC_PROG_CC): Moved to before configure.host call.
2673 * configure: Rebuilt.
2674
2675Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2676
2677 * configure.in: Define @SIMCONF@ depending on mips target.
2678 * configure: Rebuild.
2679 * Makefile.in (run): Add @SIMCONF@ to control simulator
2680 construction.
2681 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2682 * interp.c: Remove some debugging, provide more detailed error
2683 messages, update memory accesses to use LOADDRMASK.
2684
2685Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2686
2687 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2688 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2689 stamp-h.
2690 * configure: Rebuild.
2691 * config.in: New file, generated by autoheader.
2692 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2693 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2694 HAVE_ANINT and HAVE_AINT, as appropriate.
2695 * Makefile.in (run): Use @LIBS@ rather than -lm.
2696 (interp.o): Depend upon config.h.
2697 (Makefile): Just rebuild Makefile.
2698 (clean): Remove stamp-h.
2699 (mostlyclean): Make the same as clean, not as distclean.
2700 (config.h, stamp-h): New targets.
2701
2702Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2703
2704 * interp.c (ColdReset): Fix boolean test. Make all simulator
2705 globals static.
2706
2707Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2708
2709 * interp.c (xfer_direct_word, xfer_direct_long,
2710 swap_direct_word, swap_direct_long, xfer_big_word,
2711 xfer_big_long, xfer_little_word, xfer_little_long,
2712 swap_word,swap_long): Added.
2713 * interp.c (ColdReset): Provide function indirection to
2714 host<->simulated_target transfer routines.
2715 * interp.c (sim_store_register, sim_fetch_register): Updated to
2716 make use of indirected transfer routines.
2717
2718Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2719
2720 * gencode.c (process_instructions): Ensure FP ABS instruction
2721 recognised.
2722 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2723 system call support.
2724
2725Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2726
2727 * interp.c (sim_do_command): Complain if callback structure not
2728 initialised.
2729
2730Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2731
2732 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2733 support for Sun hosts.
2734 * Makefile.in (gencode): Ensure the host compiler and libraries
2735 used for cross-hosted build.
2736
2737Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2738
2739 * interp.c, gencode.c: Some more (TODO) tidying.
2740
2741Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2742
2743 * gencode.c, interp.c: Replaced explicit long long references with
2744 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2745 * support.h (SET64LO, SET64HI): Macros added.
2746
2747Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2748
2749 * configure: Regenerate with autoconf 2.7.
2750
2751Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2752
2753 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2754 * support.h: Remove superfluous "1" from #if.
2755 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2756
2757Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2758
2759 * interp.c (StoreFPR): Control UndefinedResult() call on
2760 WARN_RESULT manifest.
2761
2762Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2763
2764 * gencode.c: Tidied instruction decoding, and added FP instruction
2765 support.
2766
2767 * interp.c: Added dineroIII, and BSD profiling support. Also
2768 run-time FP handling.
2769
2770Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2771
2772 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2773 gencode.c, interp.c, support.h: created.
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