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0b23fb36 IY |
1 | /* |
2 | * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com> | |
3 | * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org> | |
4 | * (C) Copyright 2008 Armadeus Systems nc | |
5 | * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> | |
6 | * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de> | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
0b23fb36 IY |
9 | */ |
10 | ||
11 | #include <common.h> | |
60752ca8 | 12 | #include <dm.h> |
0b23fb36 | 13 | #include <malloc.h> |
cf92e05c | 14 | #include <memalign.h> |
567173a6 | 15 | #include <miiphy.h> |
0b23fb36 | 16 | #include <net.h> |
84f64c8b | 17 | #include <netdev.h> |
0b23fb36 IY |
18 | #include "fec_mxc.h" |
19 | ||
0b23fb36 | 20 | #include <asm/io.h> |
1221ce45 | 21 | #include <linux/errno.h> |
e2a66e60 | 22 | #include <linux/compiler.h> |
0b23fb36 | 23 | |
567173a6 JT |
24 | #include <asm/arch/clock.h> |
25 | #include <asm/arch/imx-regs.h> | |
552a848e | 26 | #include <asm/mach-imx/sys_proto.h> |
567173a6 | 27 | |
0b23fb36 IY |
28 | DECLARE_GLOBAL_DATA_PTR; |
29 | ||
bc1ce150 MV |
30 | /* |
31 | * Timeout the transfer after 5 mS. This is usually a bit more, since | |
32 | * the code in the tightloops this timeout is used in adds some overhead. | |
33 | */ | |
34 | #define FEC_XFER_TIMEOUT 5000 | |
35 | ||
db5b7f56 FE |
36 | /* |
37 | * The standard 32-byte DMA alignment does not work on mx6solox, which requires | |
38 | * 64-byte alignment in the DMA RX FEC buffer. | |
39 | * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also | |
40 | * satisfies the alignment on other SoCs (32-bytes) | |
41 | */ | |
42 | #define FEC_DMA_RX_MINALIGN 64 | |
43 | ||
0b23fb36 IY |
44 | #ifndef CONFIG_MII |
45 | #error "CONFIG_MII has to be defined!" | |
46 | #endif | |
47 | ||
5c1ad3e6 EN |
48 | #ifndef CONFIG_FEC_XCV_TYPE |
49 | #define CONFIG_FEC_XCV_TYPE MII100 | |
392b8502 MV |
50 | #endif |
51 | ||
be7e87e2 MV |
52 | /* |
53 | * The i.MX28 operates with packets in big endian. We need to swap them before | |
54 | * sending and after receiving. | |
55 | */ | |
5c1ad3e6 EN |
56 | #ifdef CONFIG_MX28 |
57 | #define CONFIG_FEC_MXC_SWAP_PACKET | |
58 | #endif | |
59 | ||
60 | #define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd)) | |
61 | ||
62 | /* Check various alignment issues at compile time */ | |
63 | #if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0)) | |
64 | #error "ARCH_DMA_MINALIGN must be multiple of 16!" | |
65 | #endif | |
66 | ||
67 | #if ((PKTALIGN < ARCH_DMA_MINALIGN) || \ | |
68 | (PKTALIGN % ARCH_DMA_MINALIGN != 0)) | |
69 | #error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!" | |
be7e87e2 MV |
70 | #endif |
71 | ||
0b23fb36 IY |
72 | #undef DEBUG |
73 | ||
5c1ad3e6 | 74 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
75 | static void swap_packet(uint32_t *packet, int length) |
76 | { | |
77 | int i; | |
78 | ||
79 | for (i = 0; i < DIV_ROUND_UP(length, 4); i++) | |
80 | packet[i] = __swab32(packet[i]); | |
81 | } | |
82 | #endif | |
83 | ||
567173a6 JT |
84 | /* MII-interface related functions */ |
85 | static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr, | |
86 | uint8_t regaddr) | |
0b23fb36 | 87 | { |
0b23fb36 IY |
88 | uint32_t reg; /* convenient holder for the PHY register */ |
89 | uint32_t phy; /* convenient holder for the PHY */ | |
90 | uint32_t start; | |
13947f43 | 91 | int val; |
0b23fb36 IY |
92 | |
93 | /* | |
94 | * reading from any PHY's register is done by properly | |
95 | * programming the FEC's MII data register. | |
96 | */ | |
d133b881 | 97 | writel(FEC_IEVENT_MII, ð->ievent); |
567173a6 JT |
98 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
99 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; | |
0b23fb36 IY |
100 | |
101 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | | |
d133b881 | 102 | phy | reg, ð->mii_data); |
0b23fb36 | 103 | |
567173a6 | 104 | /* wait for the related interrupt */ |
a60d1e5b | 105 | start = get_timer(0); |
d133b881 | 106 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
107 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
108 | printf("Read MDIO failed...\n"); | |
109 | return -1; | |
110 | } | |
111 | } | |
112 | ||
567173a6 | 113 | /* clear mii interrupt bit */ |
d133b881 | 114 | writel(FEC_IEVENT_MII, ð->ievent); |
0b23fb36 | 115 | |
567173a6 | 116 | /* it's now safe to read the PHY's register */ |
13947f43 | 117 | val = (unsigned short)readl(ð->mii_data); |
567173a6 JT |
118 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
119 | regaddr, val); | |
13947f43 | 120 | return val; |
0b23fb36 IY |
121 | } |
122 | ||
575c5cc0 | 123 | static void fec_mii_setspeed(struct ethernet_regs *eth) |
4294b248 SB |
124 | { |
125 | /* | |
126 | * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock | |
127 | * and do not drop the Preamble. | |
843a3e58 MR |
128 | * |
129 | * The i.MX28 and i.MX6 types have another field in the MSCR (aka | |
130 | * MII_SPEED) register that defines the MDIO output hold time. Earlier | |
131 | * versions are RAZ there, so just ignore the difference and write the | |
132 | * register always. | |
133 | * The minimal hold time according to IEE802.3 (clause 22) is 10 ns. | |
134 | * HOLDTIME + 1 is the number of clk cycles the fec is holding the | |
135 | * output. | |
136 | * The HOLDTIME bitfield takes values between 0 and 7 (inclusive). | |
137 | * Given that ceil(clkrate / 5000000) <= 64, the calculation for | |
138 | * holdtime cannot result in a value greater than 3. | |
4294b248 | 139 | */ |
843a3e58 MR |
140 | u32 pclk = imx_get_fecclk(); |
141 | u32 speed = DIV_ROUND_UP(pclk, 5000000); | |
142 | u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1; | |
6ba45cc0 MN |
143 | #ifdef FEC_QUIRK_ENET_MAC |
144 | speed--; | |
145 | #endif | |
843a3e58 | 146 | writel(speed << 1 | hold << 8, ð->mii_speed); |
575c5cc0 | 147 | debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed)); |
4294b248 | 148 | } |
0b23fb36 | 149 | |
567173a6 JT |
150 | static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr, |
151 | uint8_t regaddr, uint16_t data) | |
13947f43 | 152 | { |
0b23fb36 IY |
153 | uint32_t reg; /* convenient holder for the PHY register */ |
154 | uint32_t phy; /* convenient holder for the PHY */ | |
155 | uint32_t start; | |
156 | ||
567173a6 JT |
157 | reg = regaddr << FEC_MII_DATA_RA_SHIFT; |
158 | phy = phyaddr << FEC_MII_DATA_PA_SHIFT; | |
0b23fb36 IY |
159 | |
160 | writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR | | |
d133b881 | 161 | FEC_MII_DATA_TA | phy | reg | data, ð->mii_data); |
0b23fb36 | 162 | |
567173a6 | 163 | /* wait for the MII interrupt */ |
a60d1e5b | 164 | start = get_timer(0); |
d133b881 | 165 | while (!(readl(ð->ievent) & FEC_IEVENT_MII)) { |
0b23fb36 IY |
166 | if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { |
167 | printf("Write MDIO failed...\n"); | |
168 | return -1; | |
169 | } | |
170 | } | |
171 | ||
567173a6 | 172 | /* clear MII interrupt bit */ |
d133b881 | 173 | writel(FEC_IEVENT_MII, ð->ievent); |
567173a6 JT |
174 | debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr, |
175 | regaddr, data); | |
0b23fb36 IY |
176 | |
177 | return 0; | |
178 | } | |
179 | ||
567173a6 JT |
180 | static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr, |
181 | int regaddr) | |
13947f43 | 182 | { |
567173a6 | 183 | return fec_mdio_read(bus->priv, phyaddr, regaddr); |
13947f43 TK |
184 | } |
185 | ||
567173a6 JT |
186 | static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr, |
187 | int regaddr, u16 data) | |
13947f43 | 188 | { |
567173a6 | 189 | return fec_mdio_write(bus->priv, phyaddr, regaddr, data); |
13947f43 TK |
190 | } |
191 | ||
192 | #ifndef CONFIG_PHYLIB | |
0b23fb36 IY |
193 | static int miiphy_restart_aneg(struct eth_device *dev) |
194 | { | |
b774fe9d SB |
195 | int ret = 0; |
196 | #if !defined(CONFIG_FEC_MXC_NO_ANEG) | |
9e27e9dc | 197 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 198 | struct ethernet_regs *eth = fec->bus->priv; |
9e27e9dc | 199 | |
0b23fb36 IY |
200 | /* |
201 | * Wake up from sleep if necessary | |
202 | * Reset PHY, then delay 300ns | |
203 | */ | |
cb17b92d | 204 | #ifdef CONFIG_MX27 |
13947f43 | 205 | fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF); |
cb17b92d | 206 | #endif |
13947f43 | 207 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET); |
0b23fb36 IY |
208 | udelay(1000); |
209 | ||
567173a6 | 210 | /* Set the auto-negotiation advertisement register bits */ |
13947f43 | 211 | fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE, |
567173a6 JT |
212 | LPA_100FULL | LPA_100HALF | LPA_10FULL | |
213 | LPA_10HALF | PHY_ANLPAR_PSB_802_3); | |
13947f43 | 214 | fec_mdio_write(eth, fec->phy_id, MII_BMCR, |
567173a6 | 215 | BMCR_ANENABLE | BMCR_ANRESTART); |
2e5f4421 MV |
216 | |
217 | if (fec->mii_postcall) | |
218 | ret = fec->mii_postcall(fec->phy_id); | |
219 | ||
b774fe9d | 220 | #endif |
2e5f4421 | 221 | return ret; |
0b23fb36 IY |
222 | } |
223 | ||
0750701a | 224 | #ifndef CONFIG_FEC_FIXED_SPEED |
0b23fb36 IY |
225 | static int miiphy_wait_aneg(struct eth_device *dev) |
226 | { | |
227 | uint32_t start; | |
13947f43 | 228 | int status; |
9e27e9dc | 229 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
13947f43 | 230 | struct ethernet_regs *eth = fec->bus->priv; |
0b23fb36 | 231 | |
567173a6 | 232 | /* Wait for AN completion */ |
a60d1e5b | 233 | start = get_timer(0); |
0b23fb36 IY |
234 | do { |
235 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
236 | printf("%s: Autonegotiation timeout\n", dev->name); | |
237 | return -1; | |
238 | } | |
239 | ||
13947f43 TK |
240 | status = fec_mdio_read(eth, fec->phy_id, MII_BMSR); |
241 | if (status < 0) { | |
242 | printf("%s: Autonegotiation failed. status: %d\n", | |
567173a6 | 243 | dev->name, status); |
0b23fb36 IY |
244 | return -1; |
245 | } | |
8ef583a0 | 246 | } while (!(status & BMSR_LSTATUS)); |
0b23fb36 IY |
247 | |
248 | return 0; | |
249 | } | |
0750701a | 250 | #endif /* CONFIG_FEC_FIXED_SPEED */ |
13947f43 TK |
251 | #endif |
252 | ||
0b23fb36 IY |
253 | static int fec_rx_task_enable(struct fec_priv *fec) |
254 | { | |
c0b5a3bb | 255 | writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active); |
0b23fb36 IY |
256 | return 0; |
257 | } | |
258 | ||
259 | static int fec_rx_task_disable(struct fec_priv *fec) | |
260 | { | |
261 | return 0; | |
262 | } | |
263 | ||
264 | static int fec_tx_task_enable(struct fec_priv *fec) | |
265 | { | |
c0b5a3bb | 266 | writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active); |
0b23fb36 IY |
267 | return 0; |
268 | } | |
269 | ||
270 | static int fec_tx_task_disable(struct fec_priv *fec) | |
271 | { | |
272 | return 0; | |
273 | } | |
274 | ||
275 | /** | |
276 | * Initialize receive task's buffer descriptors | |
277 | * @param[in] fec all we know about the device yet | |
278 | * @param[in] count receive buffer count to be allocated | |
5c1ad3e6 | 279 | * @param[in] dsize desired size of each receive buffer |
0b23fb36 IY |
280 | * @return 0 on success |
281 | * | |
79e5f27b | 282 | * Init all RX descriptors to default values. |
0b23fb36 | 283 | */ |
79e5f27b | 284 | static void fec_rbd_init(struct fec_priv *fec, int count, int dsize) |
0b23fb36 | 285 | { |
5c1ad3e6 | 286 | uint32_t size; |
79e5f27b | 287 | uint8_t *data; |
5c1ad3e6 EN |
288 | int i; |
289 | ||
0b23fb36 | 290 | /* |
79e5f27b MV |
291 | * Reload the RX descriptors with default values and wipe |
292 | * the RX buffers. | |
0b23fb36 | 293 | */ |
5c1ad3e6 EN |
294 | size = roundup(dsize, ARCH_DMA_MINALIGN); |
295 | for (i = 0; i < count; i++) { | |
79e5f27b MV |
296 | data = (uint8_t *)fec->rbd_base[i].data_pointer; |
297 | memset(data, 0, dsize); | |
298 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
299 | ||
300 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
301 | fec->rbd_base[i].data_length = 0; | |
5c1ad3e6 EN |
302 | } |
303 | ||
304 | /* Mark the last RBD to close the ring. */ | |
79e5f27b | 305 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; |
0b23fb36 IY |
306 | fec->rbd_index = 0; |
307 | ||
79e5f27b MV |
308 | flush_dcache_range((unsigned)fec->rbd_base, |
309 | (unsigned)fec->rbd_base + size); | |
0b23fb36 IY |
310 | } |
311 | ||
312 | /** | |
313 | * Initialize transmit task's buffer descriptors | |
314 | * @param[in] fec all we know about the device yet | |
315 | * | |
316 | * Transmit buffers are created externally. We only have to init the BDs here.\n | |
317 | * Note: There is a race condition in the hardware. When only one BD is in | |
318 | * use it must be marked with the WRAP bit to use it for every transmitt. | |
319 | * This bit in combination with the READY bit results into double transmit | |
320 | * of each data buffer. It seems the state machine checks READY earlier then | |
321 | * resetting it after the first transfer. | |
322 | * Using two BDs solves this issue. | |
323 | */ | |
324 | static void fec_tbd_init(struct fec_priv *fec) | |
325 | { | |
5c1ad3e6 EN |
326 | unsigned addr = (unsigned)fec->tbd_base; |
327 | unsigned size = roundup(2 * sizeof(struct fec_bd), | |
328 | ARCH_DMA_MINALIGN); | |
79e5f27b MV |
329 | |
330 | memset(fec->tbd_base, 0, size); | |
331 | fec->tbd_base[0].status = 0; | |
332 | fec->tbd_base[1].status = FEC_TBD_WRAP; | |
0b23fb36 | 333 | fec->tbd_index = 0; |
79e5f27b | 334 | flush_dcache_range(addr, addr + size); |
0b23fb36 IY |
335 | } |
336 | ||
337 | /** | |
338 | * Mark the given read buffer descriptor as free | |
339 | * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0 | |
567173a6 | 340 | * @param[in] prbd buffer descriptor to mark free again |
0b23fb36 | 341 | */ |
567173a6 | 342 | static void fec_rbd_clean(int last, struct fec_bd *prbd) |
0b23fb36 | 343 | { |
5c1ad3e6 | 344 | unsigned short flags = FEC_RBD_EMPTY; |
0b23fb36 | 345 | if (last) |
5c1ad3e6 | 346 | flags |= FEC_RBD_WRAP; |
567173a6 JT |
347 | writew(flags, &prbd->status); |
348 | writew(0, &prbd->data_length); | |
0b23fb36 IY |
349 | } |
350 | ||
f54183e6 | 351 | static int fec_get_hwaddr(int dev_id, unsigned char *mac) |
0b23fb36 | 352 | { |
be252b65 | 353 | imx_get_mac_from_fuse(dev_id, mac); |
0adb5b76 | 354 | return !is_valid_ethaddr(mac); |
0b23fb36 IY |
355 | } |
356 | ||
60752ca8 JT |
357 | #ifdef CONFIG_DM_ETH |
358 | static int fecmxc_set_hwaddr(struct udevice *dev) | |
359 | #else | |
4294b248 | 360 | static int fec_set_hwaddr(struct eth_device *dev) |
60752ca8 | 361 | #endif |
0b23fb36 | 362 | { |
60752ca8 JT |
363 | #ifdef CONFIG_DM_ETH |
364 | struct fec_priv *fec = dev_get_priv(dev); | |
365 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
366 | uchar *mac = pdata->enetaddr; | |
367 | #else | |
4294b248 | 368 | uchar *mac = dev->enetaddr; |
0b23fb36 | 369 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 370 | #endif |
0b23fb36 IY |
371 | |
372 | writel(0, &fec->eth->iaddr1); | |
373 | writel(0, &fec->eth->iaddr2); | |
374 | writel(0, &fec->eth->gaddr1); | |
375 | writel(0, &fec->eth->gaddr2); | |
376 | ||
567173a6 | 377 | /* Set physical address */ |
0b23fb36 | 378 | writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], |
567173a6 | 379 | &fec->eth->paddr1); |
0b23fb36 IY |
380 | writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2); |
381 | ||
382 | return 0; | |
383 | } | |
384 | ||
567173a6 | 385 | /* Do initial configuration of the FEC registers */ |
a5990b26 MV |
386 | static void fec_reg_setup(struct fec_priv *fec) |
387 | { | |
388 | uint32_t rcntrl; | |
389 | ||
567173a6 | 390 | /* Set interrupt mask register */ |
a5990b26 MV |
391 | writel(0x00000000, &fec->eth->imask); |
392 | ||
567173a6 | 393 | /* Clear FEC-Lite interrupt event register(IEVENT) */ |
a5990b26 MV |
394 | writel(0xffffffff, &fec->eth->ievent); |
395 | ||
567173a6 | 396 | /* Set FEC-Lite receive control register(R_CNTRL): */ |
a5990b26 MV |
397 | |
398 | /* Start with frame length = 1518, common for all modes. */ | |
399 | rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT; | |
9d2d924a | 400 | if (fec->xcv_type != SEVENWIRE) /* xMII modes */ |
401 | rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE; | |
402 | if (fec->xcv_type == RGMII) | |
a5990b26 MV |
403 | rcntrl |= FEC_RCNTRL_RGMII; |
404 | else if (fec->xcv_type == RMII) | |
405 | rcntrl |= FEC_RCNTRL_RMII; | |
a5990b26 MV |
406 | |
407 | writel(rcntrl, &fec->eth->r_cntrl); | |
408 | } | |
409 | ||
0b23fb36 IY |
410 | /** |
411 | * Start the FEC engine | |
412 | * @param[in] dev Our device to handle | |
413 | */ | |
60752ca8 JT |
414 | #ifdef CONFIG_DM_ETH |
415 | static int fec_open(struct udevice *dev) | |
416 | #else | |
0b23fb36 | 417 | static int fec_open(struct eth_device *edev) |
60752ca8 | 418 | #endif |
0b23fb36 | 419 | { |
60752ca8 JT |
420 | #ifdef CONFIG_DM_ETH |
421 | struct fec_priv *fec = dev_get_priv(dev); | |
422 | #else | |
0b23fb36 | 423 | struct fec_priv *fec = (struct fec_priv *)edev->priv; |
60752ca8 | 424 | #endif |
28774cba | 425 | int speed; |
5c1ad3e6 EN |
426 | uint32_t addr, size; |
427 | int i; | |
0b23fb36 IY |
428 | |
429 | debug("fec_open: fec_open(dev)\n"); | |
430 | /* full-duplex, heartbeat disabled */ | |
431 | writel(1 << 2, &fec->eth->x_cntrl); | |
432 | fec->rbd_index = 0; | |
433 | ||
5c1ad3e6 EN |
434 | /* Invalidate all descriptors */ |
435 | for (i = 0; i < FEC_RBD_NUM - 1; i++) | |
436 | fec_rbd_clean(0, &fec->rbd_base[i]); | |
437 | fec_rbd_clean(1, &fec->rbd_base[i]); | |
438 | ||
439 | /* Flush the descriptors into RAM */ | |
440 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), | |
441 | ARCH_DMA_MINALIGN); | |
442 | addr = (uint32_t)fec->rbd_base; | |
443 | flush_dcache_range(addr, addr + size); | |
444 | ||
28774cba | 445 | #ifdef FEC_QUIRK_ENET_MAC |
2ef2b950 JL |
446 | /* Enable ENET HW endian SWAP */ |
447 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP, | |
567173a6 | 448 | &fec->eth->ecntrl); |
2ef2b950 JL |
449 | /* Enable ENET store and forward mode */ |
450 | writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD, | |
567173a6 | 451 | &fec->eth->x_wmrk); |
2ef2b950 | 452 | #endif |
567173a6 | 453 | /* Enable FEC-Lite controller */ |
cb17b92d | 454 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN, |
567173a6 JT |
455 | &fec->eth->ecntrl); |
456 | ||
7df51fd8 | 457 | #if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) |
740d6ae5 | 458 | udelay(100); |
740d6ae5 | 459 | |
567173a6 | 460 | /* setup the MII gasket for RMII mode */ |
740d6ae5 JR |
461 | /* disable the gasket */ |
462 | writew(0, &fec->eth->miigsk_enr); | |
463 | ||
464 | /* wait for the gasket to be disabled */ | |
465 | while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) | |
466 | udelay(2); | |
467 | ||
468 | /* configure gasket for RMII, 50 MHz, no loopback, and no echo */ | |
469 | writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr); | |
470 | ||
471 | /* re-enable the gasket */ | |
472 | writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr); | |
473 | ||
474 | /* wait until MII gasket is ready */ | |
475 | int max_loops = 10; | |
476 | while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) { | |
477 | if (--max_loops <= 0) { | |
478 | printf("WAIT for MII Gasket ready timed out\n"); | |
479 | break; | |
480 | } | |
481 | } | |
482 | #endif | |
0b23fb36 | 483 | |
13947f43 | 484 | #ifdef CONFIG_PHYLIB |
4dc27eed | 485 | { |
13947f43 | 486 | /* Start up the PHY */ |
11af8d65 TT |
487 | int ret = phy_startup(fec->phydev); |
488 | ||
489 | if (ret) { | |
490 | printf("Could not initialize PHY %s\n", | |
491 | fec->phydev->dev->name); | |
492 | return ret; | |
493 | } | |
13947f43 | 494 | speed = fec->phydev->speed; |
13947f43 | 495 | } |
0750701a HS |
496 | #elif CONFIG_FEC_FIXED_SPEED |
497 | speed = CONFIG_FEC_FIXED_SPEED; | |
13947f43 | 498 | #else |
0b23fb36 | 499 | miiphy_wait_aneg(edev); |
28774cba | 500 | speed = miiphy_speed(edev->name, fec->phy_id); |
9e27e9dc | 501 | miiphy_duplex(edev->name, fec->phy_id); |
13947f43 | 502 | #endif |
0b23fb36 | 503 | |
28774cba TK |
504 | #ifdef FEC_QUIRK_ENET_MAC |
505 | { | |
506 | u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED; | |
bcb6e902 | 507 | u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T; |
28774cba TK |
508 | if (speed == _1000BASET) |
509 | ecr |= FEC_ECNTRL_SPEED; | |
510 | else if (speed != _100BASET) | |
511 | rcr |= FEC_RCNTRL_RMII_10T; | |
512 | writel(ecr, &fec->eth->ecntrl); | |
513 | writel(rcr, &fec->eth->r_cntrl); | |
514 | } | |
515 | #endif | |
516 | debug("%s:Speed=%i\n", __func__, speed); | |
517 | ||
567173a6 | 518 | /* Enable SmartDMA receive task */ |
0b23fb36 IY |
519 | fec_rx_task_enable(fec); |
520 | ||
521 | udelay(100000); | |
522 | return 0; | |
523 | } | |
524 | ||
60752ca8 JT |
525 | #ifdef CONFIG_DM_ETH |
526 | static int fecmxc_init(struct udevice *dev) | |
527 | #else | |
567173a6 | 528 | static int fec_init(struct eth_device *dev, bd_t *bd) |
60752ca8 | 529 | #endif |
0b23fb36 | 530 | { |
60752ca8 JT |
531 | #ifdef CONFIG_DM_ETH |
532 | struct fec_priv *fec = dev_get_priv(dev); | |
533 | #else | |
0b23fb36 | 534 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 535 | #endif |
9e27e9dc | 536 | uint32_t mib_ptr = (uint32_t)&fec->eth->rmon_t_drop; |
79e5f27b | 537 | int i; |
0b23fb36 | 538 | |
e9319f11 | 539 | /* Initialize MAC address */ |
60752ca8 JT |
540 | #ifdef CONFIG_DM_ETH |
541 | fecmxc_set_hwaddr(dev); | |
542 | #else | |
e9319f11 | 543 | fec_set_hwaddr(dev); |
60752ca8 | 544 | #endif |
e9319f11 | 545 | |
567173a6 | 546 | /* Setup transmit descriptors, there are two in total. */ |
79e5f27b | 547 | fec_tbd_init(fec); |
0b23fb36 | 548 | |
79e5f27b MV |
549 | /* Setup receive descriptors. */ |
550 | fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE); | |
0b23fb36 | 551 | |
a5990b26 | 552 | fec_reg_setup(fec); |
9eb3770b | 553 | |
f41471e6 | 554 | if (fec->xcv_type != SEVENWIRE) |
575c5cc0 | 555 | fec_mii_setspeed(fec->bus->priv); |
9eb3770b | 556 | |
567173a6 | 557 | /* Set Opcode/Pause Duration Register */ |
0b23fb36 IY |
558 | writel(0x00010020, &fec->eth->op_pause); /* FIXME 0xffff0020; */ |
559 | writel(0x2, &fec->eth->x_wmrk); | |
567173a6 JT |
560 | |
561 | /* Set multicast address filter */ | |
0b23fb36 IY |
562 | writel(0x00000000, &fec->eth->gaddr1); |
563 | writel(0x00000000, &fec->eth->gaddr2); | |
564 | ||
fbecbaa1 | 565 | /* Do not access reserved register for i.MX6UL */ |
27255fe8 | 566 | if (!is_mx6ul() && !is_mx6ull()) { |
fbecbaa1 PF |
567 | /* clear MIB RAM */ |
568 | for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) | |
569 | writel(0, i); | |
0b23fb36 | 570 | |
fbecbaa1 PF |
571 | /* FIFO receive start register */ |
572 | writel(0x520, &fec->eth->r_fstart); | |
573 | } | |
0b23fb36 IY |
574 | |
575 | /* size and address of each buffer */ | |
576 | writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr); | |
577 | writel((uint32_t)fec->tbd_base, &fec->eth->etdsr); | |
578 | writel((uint32_t)fec->rbd_base, &fec->eth->erdsr); | |
579 | ||
13947f43 | 580 | #ifndef CONFIG_PHYLIB |
0b23fb36 IY |
581 | if (fec->xcv_type != SEVENWIRE) |
582 | miiphy_restart_aneg(dev); | |
13947f43 | 583 | #endif |
0b23fb36 IY |
584 | fec_open(dev); |
585 | return 0; | |
586 | } | |
587 | ||
588 | /** | |
589 | * Halt the FEC engine | |
590 | * @param[in] dev Our device to handle | |
591 | */ | |
60752ca8 JT |
592 | #ifdef CONFIG_DM_ETH |
593 | static void fecmxc_halt(struct udevice *dev) | |
594 | #else | |
0b23fb36 | 595 | static void fec_halt(struct eth_device *dev) |
60752ca8 | 596 | #endif |
0b23fb36 | 597 | { |
60752ca8 JT |
598 | #ifdef CONFIG_DM_ETH |
599 | struct fec_priv *fec = dev_get_priv(dev); | |
600 | #else | |
9e27e9dc | 601 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 602 | #endif |
0b23fb36 IY |
603 | int counter = 0xffff; |
604 | ||
567173a6 | 605 | /* issue graceful stop command to the FEC transmitter if necessary */ |
cb17b92d | 606 | writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl), |
567173a6 | 607 | &fec->eth->x_cntrl); |
0b23fb36 IY |
608 | |
609 | debug("eth_halt: wait for stop regs\n"); | |
567173a6 | 610 | /* wait for graceful stop to register */ |
0b23fb36 | 611 | while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA))) |
cb17b92d | 612 | udelay(1); |
0b23fb36 | 613 | |
567173a6 | 614 | /* Disable SmartDMA tasks */ |
0b23fb36 IY |
615 | fec_tx_task_disable(fec); |
616 | fec_rx_task_disable(fec); | |
617 | ||
618 | /* | |
619 | * Disable the Ethernet Controller | |
620 | * Note: this will also reset the BD index counter! | |
621 | */ | |
740d6ae5 | 622 | writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN, |
567173a6 | 623 | &fec->eth->ecntrl); |
0b23fb36 IY |
624 | fec->rbd_index = 0; |
625 | fec->tbd_index = 0; | |
0b23fb36 IY |
626 | debug("eth_halt: done\n"); |
627 | } | |
628 | ||
629 | /** | |
630 | * Transmit one frame | |
631 | * @param[in] dev Our ethernet device to handle | |
632 | * @param[in] packet Pointer to the data to be transmitted | |
633 | * @param[in] length Data count in bytes | |
634 | * @return 0 on success | |
635 | */ | |
60752ca8 JT |
636 | #ifdef CONFIG_DM_ETH |
637 | static int fecmxc_send(struct udevice *dev, void *packet, int length) | |
638 | #else | |
442dac4c | 639 | static int fec_send(struct eth_device *dev, void *packet, int length) |
60752ca8 | 640 | #endif |
0b23fb36 IY |
641 | { |
642 | unsigned int status; | |
efe24d2e | 643 | uint32_t size, end; |
5c1ad3e6 | 644 | uint32_t addr; |
bc1ce150 MV |
645 | int timeout = FEC_XFER_TIMEOUT; |
646 | int ret = 0; | |
0b23fb36 IY |
647 | |
648 | /* | |
649 | * This routine transmits one frame. This routine only accepts | |
650 | * 6-byte Ethernet addresses. | |
651 | */ | |
60752ca8 JT |
652 | #ifdef CONFIG_DM_ETH |
653 | struct fec_priv *fec = dev_get_priv(dev); | |
654 | #else | |
0b23fb36 | 655 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 656 | #endif |
0b23fb36 IY |
657 | |
658 | /* | |
659 | * Check for valid length of data. | |
660 | */ | |
661 | if ((length > 1500) || (length <= 0)) { | |
4294b248 | 662 | printf("Payload (%d) too large\n", length); |
0b23fb36 IY |
663 | return -1; |
664 | } | |
665 | ||
666 | /* | |
5c1ad3e6 EN |
667 | * Setup the transmit buffer. We are always using the first buffer for |
668 | * transmission, the second will be empty and only used to stop the DMA | |
669 | * engine. We also flush the packet to RAM here to avoid cache trouble. | |
0b23fb36 | 670 | */ |
5c1ad3e6 | 671 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
be7e87e2 MV |
672 | swap_packet((uint32_t *)packet, length); |
673 | #endif | |
5c1ad3e6 EN |
674 | |
675 | addr = (uint32_t)packet; | |
efe24d2e MV |
676 | end = roundup(addr + length, ARCH_DMA_MINALIGN); |
677 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
678 | flush_dcache_range(addr, end); | |
5c1ad3e6 | 679 | |
0b23fb36 | 680 | writew(length, &fec->tbd_base[fec->tbd_index].data_length); |
5c1ad3e6 EN |
681 | writel(addr, &fec->tbd_base[fec->tbd_index].data_pointer); |
682 | ||
0b23fb36 IY |
683 | /* |
684 | * update BD's status now | |
685 | * This block: | |
686 | * - is always the last in a chain (means no chain) | |
687 | * - should transmitt the CRC | |
688 | * - might be the last BD in the list, so the address counter should | |
689 | * wrap (-> keep the WRAP flag) | |
690 | */ | |
691 | status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP; | |
692 | status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY; | |
693 | writew(status, &fec->tbd_base[fec->tbd_index].status); | |
694 | ||
5c1ad3e6 EN |
695 | /* |
696 | * Flush data cache. This code flushes both TX descriptors to RAM. | |
697 | * After this code, the descriptors will be safely in RAM and we | |
698 | * can start DMA. | |
699 | */ | |
700 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
701 | addr = (uint32_t)fec->tbd_base; | |
702 | flush_dcache_range(addr, addr + size); | |
703 | ||
ab94cd49 MV |
704 | /* |
705 | * Below we read the DMA descriptor's last four bytes back from the | |
706 | * DRAM. This is important in order to make sure that all WRITE | |
707 | * operations on the bus that were triggered by previous cache FLUSH | |
708 | * have completed. | |
709 | * | |
710 | * Otherwise, on MX28, it is possible to observe a corruption of the | |
711 | * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM | |
712 | * for the bus structure of MX28. The scenario is as follows: | |
713 | * | |
714 | * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going | |
715 | * to DRAM due to flush_dcache_range() | |
716 | * 2) ARM core writes the FEC registers via AHB_ARB2 | |
717 | * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3 | |
718 | * | |
719 | * Note that 2) does sometimes finish before 1) due to reordering of | |
720 | * WRITE accesses on the AHB bus, therefore triggering 3) before the | |
721 | * DMA descriptor is fully written into DRAM. This results in occasional | |
722 | * corruption of the DMA descriptor. | |
723 | */ | |
724 | readl(addr + size - 4); | |
725 | ||
567173a6 | 726 | /* Enable SmartDMA transmit task */ |
0b23fb36 IY |
727 | fec_tx_task_enable(fec); |
728 | ||
729 | /* | |
5c1ad3e6 EN |
730 | * Wait until frame is sent. On each turn of the wait cycle, we must |
731 | * invalidate data cache to see what's really in RAM. Also, we need | |
732 | * barrier here. | |
0b23fb36 | 733 | */ |
67449098 | 734 | while (--timeout) { |
c0b5a3bb | 735 | if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR)) |
bc1ce150 | 736 | break; |
0b23fb36 | 737 | } |
5c1ad3e6 | 738 | |
f599288d | 739 | if (!timeout) { |
67449098 | 740 | ret = -EINVAL; |
f599288d FE |
741 | goto out; |
742 | } | |
743 | ||
744 | /* | |
745 | * The TDAR bit is cleared when the descriptors are all out from TX | |
746 | * but on mx6solox we noticed that the READY bit is still not cleared | |
747 | * right after TDAR. | |
748 | * These are two distinct signals, and in IC simulation, we found that | |
749 | * TDAR always gets cleared prior than the READY bit of last BD becomes | |
750 | * cleared. | |
751 | * In mx6solox, we use a later version of FEC IP. It looks like that | |
752 | * this intrinsic behaviour of TDAR bit has changed in this newer FEC | |
753 | * version. | |
754 | * | |
755 | * Fix this by polling the READY bit of BD after the TDAR polling, | |
756 | * which covers the mx6solox case and does not harm the other SoCs. | |
757 | */ | |
758 | timeout = FEC_XFER_TIMEOUT; | |
759 | while (--timeout) { | |
760 | invalidate_dcache_range(addr, addr + size); | |
761 | if (!(readw(&fec->tbd_base[fec->tbd_index].status) & | |
762 | FEC_TBD_READY)) | |
763 | break; | |
764 | } | |
67449098 | 765 | |
f599288d | 766 | if (!timeout) |
67449098 MV |
767 | ret = -EINVAL; |
768 | ||
f599288d | 769 | out: |
67449098 | 770 | debug("fec_send: status 0x%x index %d ret %i\n", |
567173a6 JT |
771 | readw(&fec->tbd_base[fec->tbd_index].status), |
772 | fec->tbd_index, ret); | |
0b23fb36 IY |
773 | /* for next transmission use the other buffer */ |
774 | if (fec->tbd_index) | |
775 | fec->tbd_index = 0; | |
776 | else | |
777 | fec->tbd_index = 1; | |
778 | ||
bc1ce150 | 779 | return ret; |
0b23fb36 IY |
780 | } |
781 | ||
782 | /** | |
783 | * Pull one frame from the card | |
784 | * @param[in] dev Our ethernet device to handle | |
785 | * @return Length of packet read | |
786 | */ | |
60752ca8 JT |
787 | #ifdef CONFIG_DM_ETH |
788 | static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp) | |
789 | #else | |
0b23fb36 | 790 | static int fec_recv(struct eth_device *dev) |
60752ca8 | 791 | #endif |
0b23fb36 | 792 | { |
60752ca8 JT |
793 | #ifdef CONFIG_DM_ETH |
794 | struct fec_priv *fec = dev_get_priv(dev); | |
795 | #else | |
0b23fb36 | 796 | struct fec_priv *fec = (struct fec_priv *)dev->priv; |
60752ca8 | 797 | #endif |
0b23fb36 IY |
798 | struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index]; |
799 | unsigned long ievent; | |
800 | int frame_length, len = 0; | |
0b23fb36 | 801 | uint16_t bd_status; |
efe24d2e | 802 | uint32_t addr, size, end; |
5c1ad3e6 | 803 | int i; |
fd37f195 | 804 | ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE); |
0b23fb36 | 805 | |
567173a6 | 806 | /* Check if any critical events have happened */ |
0b23fb36 IY |
807 | ievent = readl(&fec->eth->ievent); |
808 | writel(ievent, &fec->eth->ievent); | |
eda959f3 | 809 | debug("fec_recv: ievent 0x%lx\n", ievent); |
0b23fb36 | 810 | if (ievent & FEC_IEVENT_BABR) { |
60752ca8 JT |
811 | #ifdef CONFIG_DM_ETH |
812 | fecmxc_halt(dev); | |
813 | fecmxc_init(dev); | |
814 | #else | |
0b23fb36 IY |
815 | fec_halt(dev); |
816 | fec_init(dev, fec->bd); | |
60752ca8 | 817 | #endif |
0b23fb36 IY |
818 | printf("some error: 0x%08lx\n", ievent); |
819 | return 0; | |
820 | } | |
821 | if (ievent & FEC_IEVENT_HBERR) { | |
822 | /* Heartbeat error */ | |
823 | writel(0x00000001 | readl(&fec->eth->x_cntrl), | |
567173a6 | 824 | &fec->eth->x_cntrl); |
0b23fb36 IY |
825 | } |
826 | if (ievent & FEC_IEVENT_GRA) { | |
827 | /* Graceful stop complete */ | |
828 | if (readl(&fec->eth->x_cntrl) & 0x00000001) { | |
60752ca8 JT |
829 | #ifdef CONFIG_DM_ETH |
830 | fecmxc_halt(dev); | |
831 | #else | |
0b23fb36 | 832 | fec_halt(dev); |
60752ca8 | 833 | #endif |
0b23fb36 | 834 | writel(~0x00000001 & readl(&fec->eth->x_cntrl), |
567173a6 | 835 | &fec->eth->x_cntrl); |
60752ca8 JT |
836 | #ifdef CONFIG_DM_ETH |
837 | fecmxc_init(dev); | |
838 | #else | |
0b23fb36 | 839 | fec_init(dev, fec->bd); |
60752ca8 | 840 | #endif |
0b23fb36 IY |
841 | } |
842 | } | |
843 | ||
844 | /* | |
5c1ad3e6 EN |
845 | * Read the buffer status. Before the status can be read, the data cache |
846 | * must be invalidated, because the data in RAM might have been changed | |
847 | * by DMA. The descriptors are properly aligned to cachelines so there's | |
848 | * no need to worry they'd overlap. | |
849 | * | |
850 | * WARNING: By invalidating the descriptor here, we also invalidate | |
851 | * the descriptors surrounding this one. Therefore we can NOT change the | |
852 | * contents of this descriptor nor the surrounding ones. The problem is | |
853 | * that in order to mark the descriptor as processed, we need to change | |
854 | * the descriptor. The solution is to mark the whole cache line when all | |
855 | * descriptors in the cache line are processed. | |
0b23fb36 | 856 | */ |
5c1ad3e6 EN |
857 | addr = (uint32_t)rbd; |
858 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
859 | size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
860 | invalidate_dcache_range(addr, addr + size); | |
861 | ||
0b23fb36 IY |
862 | bd_status = readw(&rbd->status); |
863 | debug("fec_recv: status 0x%x\n", bd_status); | |
864 | ||
865 | if (!(bd_status & FEC_RBD_EMPTY)) { | |
866 | if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) && | |
567173a6 JT |
867 | ((readw(&rbd->data_length) - 4) > 14)) { |
868 | /* Get buffer address and size */ | |
b189584b | 869 | addr = readl(&rbd->data_pointer); |
0b23fb36 | 870 | frame_length = readw(&rbd->data_length) - 4; |
567173a6 | 871 | /* Invalidate data cache over the buffer */ |
efe24d2e MV |
872 | end = roundup(addr + frame_length, ARCH_DMA_MINALIGN); |
873 | addr &= ~(ARCH_DMA_MINALIGN - 1); | |
874 | invalidate_dcache_range(addr, end); | |
5c1ad3e6 | 875 | |
567173a6 | 876 | /* Fill the buffer and pass it to upper layers */ |
5c1ad3e6 | 877 | #ifdef CONFIG_FEC_MXC_SWAP_PACKET |
b189584b | 878 | swap_packet((uint32_t *)addr, frame_length); |
be7e87e2 | 879 | #endif |
b189584b | 880 | memcpy(buff, (char *)addr, frame_length); |
1fd92db8 | 881 | net_process_received_packet(buff, frame_length); |
0b23fb36 IY |
882 | len = frame_length; |
883 | } else { | |
884 | if (bd_status & FEC_RBD_ERR) | |
41b93679 | 885 | debug("error frame: 0x%08x 0x%08x\n", |
b189584b | 886 | addr, bd_status); |
0b23fb36 | 887 | } |
5c1ad3e6 | 888 | |
0b23fb36 | 889 | /* |
5c1ad3e6 EN |
890 | * Free the current buffer, restart the engine and move forward |
891 | * to the next buffer. Here we check if the whole cacheline of | |
892 | * descriptors was already processed and if so, we mark it free | |
893 | * as whole. | |
0b23fb36 | 894 | */ |
5c1ad3e6 EN |
895 | size = RXDESC_PER_CACHELINE - 1; |
896 | if ((fec->rbd_index & size) == size) { | |
897 | i = fec->rbd_index - size; | |
898 | addr = (uint32_t)&fec->rbd_base[i]; | |
899 | for (; i <= fec->rbd_index ; i++) { | |
900 | fec_rbd_clean(i == (FEC_RBD_NUM - 1), | |
901 | &fec->rbd_base[i]); | |
902 | } | |
903 | flush_dcache_range(addr, | |
567173a6 | 904 | addr + ARCH_DMA_MINALIGN); |
5c1ad3e6 EN |
905 | } |
906 | ||
0b23fb36 IY |
907 | fec_rx_task_enable(fec); |
908 | fec->rbd_index = (fec->rbd_index + 1) % FEC_RBD_NUM; | |
909 | } | |
910 | debug("fec_recv: stop\n"); | |
911 | ||
912 | return len; | |
913 | } | |
914 | ||
ef8e3a3b TK |
915 | static void fec_set_dev_name(char *dest, int dev_id) |
916 | { | |
917 | sprintf(dest, (dev_id == -1) ? "FEC" : "FEC%i", dev_id); | |
918 | } | |
919 | ||
79e5f27b MV |
920 | static int fec_alloc_descs(struct fec_priv *fec) |
921 | { | |
922 | unsigned int size; | |
923 | int i; | |
924 | uint8_t *data; | |
925 | ||
926 | /* Allocate TX descriptors. */ | |
927 | size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
928 | fec->tbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
929 | if (!fec->tbd_base) | |
930 | goto err_tx; | |
931 | ||
932 | /* Allocate RX descriptors. */ | |
933 | size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd), ARCH_DMA_MINALIGN); | |
934 | fec->rbd_base = memalign(ARCH_DMA_MINALIGN, size); | |
935 | if (!fec->rbd_base) | |
936 | goto err_rx; | |
937 | ||
938 | memset(fec->rbd_base, 0, size); | |
939 | ||
940 | /* Allocate RX buffers. */ | |
941 | ||
942 | /* Maximum RX buffer size. */ | |
db5b7f56 | 943 | size = roundup(FEC_MAX_PKT_SIZE, FEC_DMA_RX_MINALIGN); |
79e5f27b | 944 | for (i = 0; i < FEC_RBD_NUM; i++) { |
db5b7f56 | 945 | data = memalign(FEC_DMA_RX_MINALIGN, size); |
79e5f27b MV |
946 | if (!data) { |
947 | printf("%s: error allocating rxbuf %d\n", __func__, i); | |
948 | goto err_ring; | |
949 | } | |
950 | ||
951 | memset(data, 0, size); | |
952 | ||
953 | fec->rbd_base[i].data_pointer = (uint32_t)data; | |
954 | fec->rbd_base[i].status = FEC_RBD_EMPTY; | |
955 | fec->rbd_base[i].data_length = 0; | |
956 | /* Flush the buffer to memory. */ | |
957 | flush_dcache_range((uint32_t)data, (uint32_t)data + size); | |
958 | } | |
959 | ||
960 | /* Mark the last RBD to close the ring. */ | |
961 | fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY; | |
962 | ||
963 | fec->rbd_index = 0; | |
964 | fec->tbd_index = 0; | |
965 | ||
966 | return 0; | |
967 | ||
968 | err_ring: | |
969 | for (; i >= 0; i--) | |
970 | free((void *)fec->rbd_base[i].data_pointer); | |
971 | free(fec->rbd_base); | |
972 | err_rx: | |
973 | free(fec->tbd_base); | |
974 | err_tx: | |
975 | return -ENOMEM; | |
976 | } | |
977 | ||
978 | static void fec_free_descs(struct fec_priv *fec) | |
979 | { | |
980 | int i; | |
981 | ||
982 | for (i = 0; i < FEC_RBD_NUM; i++) | |
983 | free((void *)fec->rbd_base[i].data_pointer); | |
984 | free(fec->rbd_base); | |
985 | free(fec->tbd_base); | |
986 | } | |
987 | ||
cb5761f7 LW |
988 | #ifdef CONFIG_DM_ETH |
989 | struct mii_dev *fec_get_miibus(struct udevice *dev, int dev_id) | |
990 | #else | |
60752ca8 | 991 | struct mii_dev *fec_get_miibus(uint32_t base_addr, int dev_id) |
cb5761f7 | 992 | #endif |
60752ca8 | 993 | { |
cb5761f7 LW |
994 | #ifdef CONFIG_DM_ETH |
995 | struct fec_priv *priv = dev_get_priv(dev); | |
996 | struct ethernet_regs *eth = priv->eth; | |
997 | #else | |
60752ca8 | 998 | struct ethernet_regs *eth = (struct ethernet_regs *)base_addr; |
cb5761f7 | 999 | #endif |
60752ca8 JT |
1000 | struct mii_dev *bus; |
1001 | int ret; | |
1002 | ||
1003 | bus = mdio_alloc(); | |
1004 | if (!bus) { | |
1005 | printf("mdio_alloc failed\n"); | |
1006 | return NULL; | |
1007 | } | |
1008 | bus->read = fec_phy_read; | |
1009 | bus->write = fec_phy_write; | |
1010 | bus->priv = eth; | |
1011 | fec_set_dev_name(bus->name, dev_id); | |
1012 | ||
1013 | ret = mdio_register(bus); | |
1014 | if (ret) { | |
1015 | printf("mdio_register failed\n"); | |
1016 | free(bus); | |
1017 | return NULL; | |
1018 | } | |
1019 | fec_mii_setspeed(eth); | |
1020 | return bus; | |
1021 | } | |
1022 | ||
1023 | #ifndef CONFIG_DM_ETH | |
fe428b90 TK |
1024 | #ifdef CONFIG_PHYLIB |
1025 | int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
1026 | struct mii_dev *bus, struct phy_device *phydev) | |
1027 | #else | |
1028 | static int fec_probe(bd_t *bd, int dev_id, uint32_t base_addr, | |
1029 | struct mii_dev *bus, int phy_id) | |
1030 | #endif | |
0b23fb36 | 1031 | { |
0b23fb36 | 1032 | struct eth_device *edev; |
9e27e9dc | 1033 | struct fec_priv *fec; |
0b23fb36 | 1034 | unsigned char ethaddr[6]; |
979a5893 | 1035 | char mac[16]; |
e382fb48 MV |
1036 | uint32_t start; |
1037 | int ret = 0; | |
0b23fb36 IY |
1038 | |
1039 | /* create and fill edev struct */ | |
1040 | edev = (struct eth_device *)malloc(sizeof(struct eth_device)); | |
1041 | if (!edev) { | |
9e27e9dc | 1042 | puts("fec_mxc: not enough malloc memory for eth_device\n"); |
e382fb48 MV |
1043 | ret = -ENOMEM; |
1044 | goto err1; | |
9e27e9dc MV |
1045 | } |
1046 | ||
1047 | fec = (struct fec_priv *)malloc(sizeof(struct fec_priv)); | |
1048 | if (!fec) { | |
1049 | puts("fec_mxc: not enough malloc memory for fec_priv\n"); | |
e382fb48 MV |
1050 | ret = -ENOMEM; |
1051 | goto err2; | |
0b23fb36 | 1052 | } |
9e27e9dc | 1053 | |
de0b9576 | 1054 | memset(edev, 0, sizeof(*edev)); |
9e27e9dc MV |
1055 | memset(fec, 0, sizeof(*fec)); |
1056 | ||
79e5f27b MV |
1057 | ret = fec_alloc_descs(fec); |
1058 | if (ret) | |
1059 | goto err3; | |
1060 | ||
0b23fb36 IY |
1061 | edev->priv = fec; |
1062 | edev->init = fec_init; | |
1063 | edev->send = fec_send; | |
1064 | edev->recv = fec_recv; | |
1065 | edev->halt = fec_halt; | |
fb57ec97 | 1066 | edev->write_hwaddr = fec_set_hwaddr; |
0b23fb36 | 1067 | |
9e27e9dc | 1068 | fec->eth = (struct ethernet_regs *)base_addr; |
0b23fb36 IY |
1069 | fec->bd = bd; |
1070 | ||
392b8502 | 1071 | fec->xcv_type = CONFIG_FEC_XCV_TYPE; |
0b23fb36 IY |
1072 | |
1073 | /* Reset chip. */ | |
cb17b92d | 1074 | writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_RESET, &fec->eth->ecntrl); |
e382fb48 MV |
1075 | start = get_timer(0); |
1076 | while (readl(&fec->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1077 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
3450a859 | 1078 | printf("FEC MXC: Timeout resetting chip\n"); |
79e5f27b | 1079 | goto err4; |
e382fb48 | 1080 | } |
0b23fb36 | 1081 | udelay(10); |
e382fb48 | 1082 | } |
0b23fb36 | 1083 | |
a5990b26 | 1084 | fec_reg_setup(fec); |
ef8e3a3b TK |
1085 | fec_set_dev_name(edev->name, dev_id); |
1086 | fec->dev_id = (dev_id == -1) ? 0 : dev_id; | |
fe428b90 TK |
1087 | fec->bus = bus; |
1088 | fec_mii_setspeed(bus->priv); | |
1089 | #ifdef CONFIG_PHYLIB | |
1090 | fec->phydev = phydev; | |
1091 | phy_connect_dev(phydev, edev); | |
1092 | /* Configure phy */ | |
1093 | phy_config(phydev); | |
1094 | #else | |
9e27e9dc | 1095 | fec->phy_id = phy_id; |
fe428b90 TK |
1096 | #endif |
1097 | eth_register(edev); | |
979a5893 AD |
1098 | /* only support one eth device, the index number pointed by dev_id */ |
1099 | edev->index = fec->dev_id; | |
fe428b90 | 1100 | |
f01e4e1e AD |
1101 | if (fec_get_hwaddr(fec->dev_id, ethaddr) == 0) { |
1102 | debug("got MAC%d address from fuse: %pM\n", fec->dev_id, ethaddr); | |
fe428b90 | 1103 | memcpy(edev->enetaddr, ethaddr, 6); |
979a5893 AD |
1104 | if (fec->dev_id) |
1105 | sprintf(mac, "eth%daddr", fec->dev_id); | |
1106 | else | |
1107 | strcpy(mac, "ethaddr"); | |
00caae6d | 1108 | if (!env_get(mac)) |
fd1e959e | 1109 | eth_env_set_enetaddr(mac, ethaddr); |
fe428b90 TK |
1110 | } |
1111 | return ret; | |
79e5f27b MV |
1112 | err4: |
1113 | fec_free_descs(fec); | |
fe428b90 TK |
1114 | err3: |
1115 | free(fec); | |
1116 | err2: | |
1117 | free(edev); | |
1118 | err1: | |
1119 | return ret; | |
1120 | } | |
1121 | ||
fe428b90 TK |
1122 | int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr) |
1123 | { | |
1124 | uint32_t base_mii; | |
1125 | struct mii_dev *bus = NULL; | |
1126 | #ifdef CONFIG_PHYLIB | |
1127 | struct phy_device *phydev = NULL; | |
1128 | #endif | |
1129 | int ret; | |
1130 | ||
5c1ad3e6 | 1131 | #ifdef CONFIG_MX28 |
13947f43 TK |
1132 | /* |
1133 | * The i.MX28 has two ethernet interfaces, but they are not equal. | |
1134 | * Only the first one can access the MDIO bus. | |
1135 | */ | |
fe428b90 | 1136 | base_mii = MXS_ENET0_BASE; |
13947f43 | 1137 | #else |
fe428b90 | 1138 | base_mii = addr; |
13947f43 | 1139 | #endif |
fe428b90 TK |
1140 | debug("eth_init: fec_probe(bd, %i, %i) @ %08x\n", dev_id, phy_id, addr); |
1141 | bus = fec_get_miibus(base_mii, dev_id); | |
1142 | if (!bus) | |
1143 | return -ENOMEM; | |
4dc27eed | 1144 | #ifdef CONFIG_PHYLIB |
fe428b90 | 1145 | phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII); |
4dc27eed | 1146 | if (!phydev) { |
845a57b4 | 1147 | mdio_unregister(bus); |
4dc27eed | 1148 | free(bus); |
fe428b90 | 1149 | return -ENOMEM; |
4dc27eed | 1150 | } |
fe428b90 TK |
1151 | ret = fec_probe(bd, dev_id, addr, bus, phydev); |
1152 | #else | |
1153 | ret = fec_probe(bd, dev_id, addr, bus, phy_id); | |
4dc27eed | 1154 | #endif |
fe428b90 TK |
1155 | if (ret) { |
1156 | #ifdef CONFIG_PHYLIB | |
1157 | free(phydev); | |
1158 | #endif | |
845a57b4 | 1159 | mdio_unregister(bus); |
fe428b90 TK |
1160 | free(bus); |
1161 | } | |
e382fb48 | 1162 | return ret; |
eef24480 | 1163 | } |
0b23fb36 | 1164 | |
eef24480 TK |
1165 | #ifdef CONFIG_FEC_MXC_PHYADDR |
1166 | int fecmxc_initialize(bd_t *bd) | |
1167 | { | |
1168 | return fecmxc_initialize_multi(bd, -1, CONFIG_FEC_MXC_PHYADDR, | |
1169 | IMX_FEC_BASE); | |
0b23fb36 | 1170 | } |
eef24480 | 1171 | #endif |
2e5f4421 | 1172 | |
13947f43 | 1173 | #ifndef CONFIG_PHYLIB |
2e5f4421 MV |
1174 | int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)) |
1175 | { | |
1176 | struct fec_priv *fec = (struct fec_priv *)dev->priv; | |
1177 | fec->mii_postcall = cb; | |
1178 | return 0; | |
1179 | } | |
13947f43 | 1180 | #endif |
60752ca8 JT |
1181 | |
1182 | #else | |
1183 | ||
1ed2570f JT |
1184 | static int fecmxc_read_rom_hwaddr(struct udevice *dev) |
1185 | { | |
1186 | struct fec_priv *priv = dev_get_priv(dev); | |
1187 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1188 | ||
1189 | return fec_get_hwaddr(priv->dev_id, pdata->enetaddr); | |
1190 | } | |
1191 | ||
60752ca8 JT |
1192 | static const struct eth_ops fecmxc_ops = { |
1193 | .start = fecmxc_init, | |
1194 | .send = fecmxc_send, | |
1195 | .recv = fecmxc_recv, | |
1196 | .stop = fecmxc_halt, | |
1197 | .write_hwaddr = fecmxc_set_hwaddr, | |
1ed2570f | 1198 | .read_rom_hwaddr = fecmxc_read_rom_hwaddr, |
60752ca8 JT |
1199 | }; |
1200 | ||
1201 | static int fec_phy_init(struct fec_priv *priv, struct udevice *dev) | |
1202 | { | |
1203 | struct phy_device *phydev; | |
1204 | int mask = 0xffffffff; | |
1205 | ||
1206 | #ifdef CONFIG_PHYLIB | |
1207 | mask = 1 << CONFIG_FEC_MXC_PHYADDR; | |
1208 | #endif | |
1209 | ||
1210 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); | |
1211 | if (!phydev) | |
1212 | return -ENODEV; | |
1213 | ||
1214 | phy_connect_dev(phydev, dev); | |
1215 | ||
1216 | priv->phydev = phydev; | |
1217 | phy_config(phydev); | |
1218 | ||
1219 | return 0; | |
1220 | } | |
1221 | ||
1222 | static int fecmxc_probe(struct udevice *dev) | |
1223 | { | |
1224 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1225 | struct fec_priv *priv = dev_get_priv(dev); | |
1226 | struct mii_dev *bus = NULL; | |
1227 | int dev_id = -1; | |
60752ca8 JT |
1228 | uint32_t start; |
1229 | int ret; | |
1230 | ||
1231 | ret = fec_alloc_descs(priv); | |
1232 | if (ret) | |
1233 | return ret; | |
1234 | ||
60752ca8 | 1235 | /* Reset chip. */ |
567173a6 JT |
1236 | writel(readl(&priv->eth->ecntrl) | FEC_ECNTRL_RESET, |
1237 | &priv->eth->ecntrl); | |
60752ca8 JT |
1238 | start = get_timer(0); |
1239 | while (readl(&priv->eth->ecntrl) & FEC_ECNTRL_RESET) { | |
1240 | if (get_timer(start) > (CONFIG_SYS_HZ * 5)) { | |
1241 | printf("FEC MXC: Timeout reseting chip\n"); | |
1242 | goto err_timeout; | |
1243 | } | |
1244 | udelay(10); | |
1245 | } | |
1246 | ||
1247 | fec_reg_setup(priv); | |
60752ca8 JT |
1248 | priv->dev_id = (dev_id == -1) ? 0 : dev_id; |
1249 | ||
306dd7da LW |
1250 | bus = fec_get_miibus(dev, dev_id); |
1251 | if (!bus) { | |
1252 | ret = -ENOMEM; | |
1253 | goto err_mii; | |
1254 | } | |
1255 | ||
1256 | priv->bus = bus; | |
1257 | priv->xcv_type = CONFIG_FEC_XCV_TYPE; | |
1258 | priv->interface = pdata->phy_interface; | |
1259 | ret = fec_phy_init(priv, dev); | |
1260 | if (ret) | |
1261 | goto err_phy; | |
1262 | ||
60752ca8 JT |
1263 | return 0; |
1264 | ||
1265 | err_timeout: | |
1266 | free(priv->phydev); | |
1267 | err_phy: | |
1268 | mdio_unregister(bus); | |
1269 | free(bus); | |
1270 | err_mii: | |
1271 | fec_free_descs(priv); | |
1272 | return ret; | |
1273 | } | |
1274 | ||
1275 | static int fecmxc_remove(struct udevice *dev) | |
1276 | { | |
1277 | struct fec_priv *priv = dev_get_priv(dev); | |
1278 | ||
1279 | free(priv->phydev); | |
1280 | fec_free_descs(priv); | |
1281 | mdio_unregister(priv->bus); | |
1282 | mdio_free(priv->bus); | |
1283 | ||
1284 | return 0; | |
1285 | } | |
1286 | ||
1287 | static int fecmxc_ofdata_to_platdata(struct udevice *dev) | |
1288 | { | |
1289 | struct eth_pdata *pdata = dev_get_platdata(dev); | |
1290 | struct fec_priv *priv = dev_get_priv(dev); | |
1291 | const char *phy_mode; | |
1292 | ||
a821c4af | 1293 | pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); |
60752ca8 JT |
1294 | priv->eth = (struct ethernet_regs *)pdata->iobase; |
1295 | ||
1296 | pdata->phy_interface = -1; | |
e160f7d4 SG |
1297 | phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode", |
1298 | NULL); | |
60752ca8 JT |
1299 | if (phy_mode) |
1300 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); | |
1301 | if (pdata->phy_interface == -1) { | |
1302 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); | |
1303 | return -EINVAL; | |
1304 | } | |
1305 | ||
1306 | /* TODO | |
1307 | * Need to get the reset-gpio and related properties from DT | |
1308 | * and implemet the enet reset code on .probe call | |
1309 | */ | |
1310 | ||
1311 | return 0; | |
1312 | } | |
1313 | ||
1314 | static const struct udevice_id fecmxc_ids[] = { | |
1315 | { .compatible = "fsl,imx6q-fec" }, | |
1316 | { } | |
1317 | }; | |
1318 | ||
1319 | U_BOOT_DRIVER(fecmxc_gem) = { | |
1320 | .name = "fecmxc", | |
1321 | .id = UCLASS_ETH, | |
1322 | .of_match = fecmxc_ids, | |
1323 | .ofdata_to_platdata = fecmxc_ofdata_to_platdata, | |
1324 | .probe = fecmxc_probe, | |
1325 | .remove = fecmxc_remove, | |
1326 | .ops = &fecmxc_ops, | |
1327 | .priv_auto_alloc_size = sizeof(struct fec_priv), | |
1328 | .platdata_auto_alloc_size = sizeof(struct eth_pdata), | |
1329 | }; | |
1330 | #endif |