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Commit | Line | Data |
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272cc70b AF |
1 | /* |
2 | * Copyright 2008, Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based vaguely on the Linux code | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
272cc70b AF |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <common.h> | |
12 | #include <command.h> | |
13 | #include <mmc.h> | |
14 | #include <part.h> | |
15 | #include <malloc.h> | |
16 | #include <linux/list.h> | |
9b1f942c | 17 | #include <div64.h> |
da61fa5f | 18 | #include "mmc_private.h" |
272cc70b AF |
19 | |
20 | static struct list_head mmc_devices; | |
21 | static int cur_dev_num = -1; | |
22 | ||
d23d8d7e NK |
23 | int __weak board_mmc_getwp(struct mmc *mmc) |
24 | { | |
25 | return -1; | |
26 | } | |
27 | ||
28 | int mmc_getwp(struct mmc *mmc) | |
29 | { | |
30 | int wp; | |
31 | ||
32 | wp = board_mmc_getwp(mmc); | |
33 | ||
d4e1da4e | 34 | if (wp < 0) { |
93bfd616 PA |
35 | if (mmc->cfg->ops->getwp) |
36 | wp = mmc->cfg->ops->getwp(mmc); | |
d4e1da4e PK |
37 | else |
38 | wp = 0; | |
39 | } | |
d23d8d7e NK |
40 | |
41 | return wp; | |
42 | } | |
43 | ||
314284b1 | 44 | int __board_mmc_getcd(struct mmc *mmc) { |
11fdade2 SB |
45 | return -1; |
46 | } | |
47 | ||
314284b1 | 48 | int board_mmc_getcd(struct mmc *mmc)__attribute__((weak, |
11fdade2 SB |
49 | alias("__board_mmc_getcd"))); |
50 | ||
da61fa5f | 51 | int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
272cc70b | 52 | { |
5db2fe3a | 53 | int ret; |
8635ff9e | 54 | |
8635ff9e | 55 | #ifdef CONFIG_MMC_TRACE |
5db2fe3a RR |
56 | int i; |
57 | u8 *ptr; | |
58 | ||
59 | printf("CMD_SEND:%d\n", cmd->cmdidx); | |
60 | printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); | |
93bfd616 | 61 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a RR |
62 | switch (cmd->resp_type) { |
63 | case MMC_RSP_NONE: | |
64 | printf("\t\tMMC_RSP_NONE\n"); | |
65 | break; | |
66 | case MMC_RSP_R1: | |
67 | printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", | |
68 | cmd->response[0]); | |
69 | break; | |
70 | case MMC_RSP_R1b: | |
71 | printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", | |
72 | cmd->response[0]); | |
73 | break; | |
74 | case MMC_RSP_R2: | |
75 | printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", | |
76 | cmd->response[0]); | |
77 | printf("\t\t \t\t 0x%08X \n", | |
78 | cmd->response[1]); | |
79 | printf("\t\t \t\t 0x%08X \n", | |
80 | cmd->response[2]); | |
81 | printf("\t\t \t\t 0x%08X \n", | |
82 | cmd->response[3]); | |
83 | printf("\n"); | |
84 | printf("\t\t\t\t\tDUMPING DATA\n"); | |
85 | for (i = 0; i < 4; i++) { | |
86 | int j; | |
87 | printf("\t\t\t\t\t%03d - ", i*4); | |
146bec79 | 88 | ptr = (u8 *)&cmd->response[i]; |
5db2fe3a RR |
89 | ptr += 3; |
90 | for (j = 0; j < 4; j++) | |
91 | printf("%02X ", *ptr--); | |
92 | printf("\n"); | |
93 | } | |
94 | break; | |
95 | case MMC_RSP_R3: | |
96 | printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", | |
97 | cmd->response[0]); | |
98 | break; | |
99 | default: | |
100 | printf("\t\tERROR MMC rsp not supported\n"); | |
101 | break; | |
102 | } | |
5db2fe3a | 103 | #else |
93bfd616 | 104 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a | 105 | #endif |
8635ff9e | 106 | return ret; |
272cc70b AF |
107 | } |
108 | ||
da61fa5f | 109 | int mmc_send_status(struct mmc *mmc, int timeout) |
5d4fc8d9 RR |
110 | { |
111 | struct mmc_cmd cmd; | |
d617c426 | 112 | int err, retries = 5; |
5d4fc8d9 RR |
113 | #ifdef CONFIG_MMC_TRACE |
114 | int status; | |
115 | #endif | |
116 | ||
117 | cmd.cmdidx = MMC_CMD_SEND_STATUS; | |
118 | cmd.resp_type = MMC_RSP_R1; | |
aaf3d41a MV |
119 | if (!mmc_host_is_spi(mmc)) |
120 | cmd.cmdarg = mmc->rca << 16; | |
5d4fc8d9 RR |
121 | |
122 | do { | |
123 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
d617c426 JK |
124 | if (!err) { |
125 | if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && | |
126 | (cmd.response[0] & MMC_STATUS_CURR_STATE) != | |
127 | MMC_STATE_PRG) | |
128 | break; | |
129 | else if (cmd.response[0] & MMC_STATUS_MASK) { | |
56196826 | 130 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
d617c426 JK |
131 | printf("Status Error: 0x%08X\n", |
132 | cmd.response[0]); | |
56196826 | 133 | #endif |
d617c426 JK |
134 | return COMM_ERR; |
135 | } | |
136 | } else if (--retries < 0) | |
5d4fc8d9 | 137 | return err; |
5d4fc8d9 RR |
138 | |
139 | udelay(1000); | |
140 | ||
5d4fc8d9 RR |
141 | } while (timeout--); |
142 | ||
5db2fe3a RR |
143 | #ifdef CONFIG_MMC_TRACE |
144 | status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; | |
145 | printf("CURR STATE:%d\n", status); | |
146 | #endif | |
5b0c942f | 147 | if (timeout <= 0) { |
56196826 | 148 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
5d4fc8d9 | 149 | printf("Timeout waiting card ready\n"); |
56196826 | 150 | #endif |
5d4fc8d9 RR |
151 | return TIMEOUT; |
152 | } | |
153 | ||
154 | return 0; | |
155 | } | |
156 | ||
da61fa5f | 157 | int mmc_set_blocklen(struct mmc *mmc, int len) |
272cc70b AF |
158 | { |
159 | struct mmc_cmd cmd; | |
160 | ||
d22e3d46 JC |
161 | if (mmc->card_caps & MMC_MODE_DDR_52MHz) |
162 | return 0; | |
163 | ||
272cc70b AF |
164 | cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; |
165 | cmd.resp_type = MMC_RSP_R1; | |
166 | cmd.cmdarg = len; | |
272cc70b AF |
167 | |
168 | return mmc_send_cmd(mmc, &cmd, NULL); | |
169 | } | |
170 | ||
171 | struct mmc *find_mmc_device(int dev_num) | |
172 | { | |
173 | struct mmc *m; | |
174 | struct list_head *entry; | |
175 | ||
176 | list_for_each(entry, &mmc_devices) { | |
177 | m = list_entry(entry, struct mmc, link); | |
178 | ||
179 | if (m->block_dev.dev == dev_num) | |
180 | return m; | |
181 | } | |
182 | ||
56196826 | 183 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 184 | printf("MMC Device %d not found\n", dev_num); |
56196826 | 185 | #endif |
272cc70b AF |
186 | |
187 | return NULL; | |
188 | } | |
189 | ||
ff8fef56 | 190 | static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, |
fdbb873e | 191 | lbaint_t blkcnt) |
272cc70b AF |
192 | { |
193 | struct mmc_cmd cmd; | |
194 | struct mmc_data data; | |
195 | ||
4a1a06bc AS |
196 | if (blkcnt > 1) |
197 | cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; | |
198 | else | |
199 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; | |
272cc70b AF |
200 | |
201 | if (mmc->high_capacity) | |
4a1a06bc | 202 | cmd.cmdarg = start; |
272cc70b | 203 | else |
4a1a06bc | 204 | cmd.cmdarg = start * mmc->read_bl_len; |
272cc70b AF |
205 | |
206 | cmd.resp_type = MMC_RSP_R1; | |
272cc70b AF |
207 | |
208 | data.dest = dst; | |
4a1a06bc | 209 | data.blocks = blkcnt; |
272cc70b AF |
210 | data.blocksize = mmc->read_bl_len; |
211 | data.flags = MMC_DATA_READ; | |
212 | ||
4a1a06bc AS |
213 | if (mmc_send_cmd(mmc, &cmd, &data)) |
214 | return 0; | |
272cc70b | 215 | |
4a1a06bc AS |
216 | if (blkcnt > 1) { |
217 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
218 | cmd.cmdarg = 0; | |
219 | cmd.resp_type = MMC_RSP_R1b; | |
4a1a06bc | 220 | if (mmc_send_cmd(mmc, &cmd, NULL)) { |
56196826 | 221 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
4a1a06bc | 222 | printf("mmc fail to send stop cmd\n"); |
56196826 | 223 | #endif |
4a1a06bc AS |
224 | return 0; |
225 | } | |
272cc70b AF |
226 | } |
227 | ||
4a1a06bc | 228 | return blkcnt; |
272cc70b AF |
229 | } |
230 | ||
ff8fef56 | 231 | static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) |
272cc70b | 232 | { |
4a1a06bc AS |
233 | lbaint_t cur, blocks_todo = blkcnt; |
234 | ||
235 | if (blkcnt == 0) | |
236 | return 0; | |
272cc70b | 237 | |
4a1a06bc | 238 | struct mmc *mmc = find_mmc_device(dev_num); |
272cc70b AF |
239 | if (!mmc) |
240 | return 0; | |
241 | ||
d2bf29e3 | 242 | if ((start + blkcnt) > mmc->block_dev.lba) { |
56196826 | 243 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
ff8fef56 | 244 | printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", |
d2bf29e3 | 245 | start + blkcnt, mmc->block_dev.lba); |
56196826 | 246 | #endif |
d2bf29e3 LW |
247 | return 0; |
248 | } | |
272cc70b | 249 | |
4a1a06bc | 250 | if (mmc_set_blocklen(mmc, mmc->read_bl_len)) |
272cc70b | 251 | return 0; |
272cc70b | 252 | |
4a1a06bc | 253 | do { |
93bfd616 PA |
254 | cur = (blocks_todo > mmc->cfg->b_max) ? |
255 | mmc->cfg->b_max : blocks_todo; | |
4a1a06bc AS |
256 | if(mmc_read_blocks(mmc, dst, start, cur) != cur) |
257 | return 0; | |
258 | blocks_todo -= cur; | |
259 | start += cur; | |
260 | dst += cur * mmc->read_bl_len; | |
261 | } while (blocks_todo > 0); | |
272cc70b AF |
262 | |
263 | return blkcnt; | |
264 | } | |
265 | ||
fdbb873e | 266 | static int mmc_go_idle(struct mmc *mmc) |
272cc70b AF |
267 | { |
268 | struct mmc_cmd cmd; | |
269 | int err; | |
270 | ||
271 | udelay(1000); | |
272 | ||
273 | cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; | |
274 | cmd.cmdarg = 0; | |
275 | cmd.resp_type = MMC_RSP_NONE; | |
272cc70b AF |
276 | |
277 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
278 | ||
279 | if (err) | |
280 | return err; | |
281 | ||
282 | udelay(2000); | |
283 | ||
284 | return 0; | |
285 | } | |
286 | ||
fdbb873e | 287 | static int sd_send_op_cond(struct mmc *mmc) |
272cc70b AF |
288 | { |
289 | int timeout = 1000; | |
290 | int err; | |
291 | struct mmc_cmd cmd; | |
292 | ||
293 | do { | |
294 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
295 | cmd.resp_type = MMC_RSP_R1; | |
296 | cmd.cmdarg = 0; | |
272cc70b AF |
297 | |
298 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
299 | ||
300 | if (err) | |
301 | return err; | |
302 | ||
303 | cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; | |
304 | cmd.resp_type = MMC_RSP_R3; | |
250de12b SB |
305 | |
306 | /* | |
307 | * Most cards do not answer if some reserved bits | |
308 | * in the ocr are set. However, Some controller | |
309 | * can set bit 7 (reserved for low voltages), but | |
310 | * how to manage low voltages SD card is not yet | |
311 | * specified. | |
312 | */ | |
d52ebf10 | 313 | cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : |
93bfd616 | 314 | (mmc->cfg->voltages & 0xff8000); |
272cc70b AF |
315 | |
316 | if (mmc->version == SD_VERSION_2) | |
317 | cmd.cmdarg |= OCR_HCS; | |
318 | ||
319 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
320 | ||
321 | if (err) | |
322 | return err; | |
323 | ||
324 | udelay(1000); | |
325 | } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--); | |
326 | ||
327 | if (timeout <= 0) | |
328 | return UNUSABLE_ERR; | |
329 | ||
330 | if (mmc->version != SD_VERSION_2) | |
331 | mmc->version = SD_VERSION_1_0; | |
332 | ||
d52ebf10 TC |
333 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
334 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
335 | cmd.resp_type = MMC_RSP_R3; | |
336 | cmd.cmdarg = 0; | |
d52ebf10 TC |
337 | |
338 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
339 | ||
340 | if (err) | |
341 | return err; | |
342 | } | |
343 | ||
998be3dd | 344 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
345 | |
346 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
347 | mmc->rca = 0; | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
e9550449 CLC |
352 | /* We pass in the cmd since otherwise the init seems to fail */ |
353 | static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, | |
354 | int use_arg) | |
272cc70b | 355 | { |
272cc70b AF |
356 | int err; |
357 | ||
e9550449 CLC |
358 | cmd->cmdidx = MMC_CMD_SEND_OP_COND; |
359 | cmd->resp_type = MMC_RSP_R3; | |
360 | cmd->cmdarg = 0; | |
361 | if (use_arg && !mmc_host_is_spi(mmc)) { | |
362 | cmd->cmdarg = | |
93bfd616 | 363 | (mmc->cfg->voltages & |
e9550449 CLC |
364 | (mmc->op_cond_response & OCR_VOLTAGE_MASK)) | |
365 | (mmc->op_cond_response & OCR_ACCESS_MODE); | |
366 | ||
93bfd616 | 367 | if (mmc->cfg->host_caps & MMC_MODE_HC) |
e9550449 CLC |
368 | cmd->cmdarg |= OCR_HCS; |
369 | } | |
370 | err = mmc_send_cmd(mmc, cmd, NULL); | |
371 | if (err) | |
372 | return err; | |
373 | mmc->op_cond_response = cmd->response[0]; | |
374 | return 0; | |
375 | } | |
376 | ||
377 | int mmc_send_op_cond(struct mmc *mmc) | |
378 | { | |
379 | struct mmc_cmd cmd; | |
380 | int err, i; | |
381 | ||
272cc70b AF |
382 | /* Some cards seem to need this */ |
383 | mmc_go_idle(mmc); | |
384 | ||
31cacbab | 385 | /* Asking to the card its capabilities */ |
e9550449 CLC |
386 | mmc->op_cond_pending = 1; |
387 | for (i = 0; i < 2; i++) { | |
388 | err = mmc_send_op_cond_iter(mmc, &cmd, i != 0); | |
389 | if (err) | |
390 | return err; | |
cd6881b5 | 391 | |
e9550449 CLC |
392 | /* exit if not busy (flag seems to be inverted) */ |
393 | if (mmc->op_cond_response & OCR_BUSY) | |
394 | return 0; | |
395 | } | |
396 | return IN_PROGRESS; | |
397 | } | |
cd6881b5 | 398 | |
e9550449 CLC |
399 | int mmc_complete_op_cond(struct mmc *mmc) |
400 | { | |
401 | struct mmc_cmd cmd; | |
402 | int timeout = 1000; | |
403 | uint start; | |
404 | int err; | |
cd6881b5 | 405 | |
e9550449 CLC |
406 | mmc->op_cond_pending = 0; |
407 | start = get_timer(0); | |
272cc70b | 408 | do { |
e9550449 | 409 | err = mmc_send_op_cond_iter(mmc, &cmd, 1); |
272cc70b AF |
410 | if (err) |
411 | return err; | |
e9550449 CLC |
412 | if (get_timer(start) > timeout) |
413 | return UNUSABLE_ERR; | |
414 | udelay(100); | |
415 | } while (!(mmc->op_cond_response & OCR_BUSY)); | |
272cc70b | 416 | |
d52ebf10 TC |
417 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
418 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
419 | cmd.resp_type = MMC_RSP_R3; | |
420 | cmd.cmdarg = 0; | |
d52ebf10 TC |
421 | |
422 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
423 | ||
424 | if (err) | |
425 | return err; | |
426 | } | |
427 | ||
272cc70b | 428 | mmc->version = MMC_VERSION_UNKNOWN; |
998be3dd | 429 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
430 | |
431 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
def816a2 | 432 | mmc->rca = 1; |
272cc70b AF |
433 | |
434 | return 0; | |
435 | } | |
436 | ||
437 | ||
fdbb873e | 438 | static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) |
272cc70b AF |
439 | { |
440 | struct mmc_cmd cmd; | |
441 | struct mmc_data data; | |
442 | int err; | |
443 | ||
444 | /* Get the Card Status Register */ | |
445 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; | |
446 | cmd.resp_type = MMC_RSP_R1; | |
447 | cmd.cmdarg = 0; | |
272cc70b | 448 | |
cdfd1ac6 | 449 | data.dest = (char *)ext_csd; |
272cc70b | 450 | data.blocks = 1; |
8bfa195e | 451 | data.blocksize = MMC_MAX_BLOCK_LEN; |
272cc70b AF |
452 | data.flags = MMC_DATA_READ; |
453 | ||
454 | err = mmc_send_cmd(mmc, &cmd, &data); | |
455 | ||
456 | return err; | |
457 | } | |
458 | ||
459 | ||
fdbb873e | 460 | static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) |
272cc70b AF |
461 | { |
462 | struct mmc_cmd cmd; | |
5d4fc8d9 RR |
463 | int timeout = 1000; |
464 | int ret; | |
272cc70b AF |
465 | |
466 | cmd.cmdidx = MMC_CMD_SWITCH; | |
467 | cmd.resp_type = MMC_RSP_R1b; | |
468 | cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | | |
5d4fc8d9 RR |
469 | (index << 16) | |
470 | (value << 8); | |
272cc70b | 471 | |
5d4fc8d9 RR |
472 | ret = mmc_send_cmd(mmc, &cmd, NULL); |
473 | ||
474 | /* Waiting for the ready status */ | |
93ad0d18 JK |
475 | if (!ret) |
476 | ret = mmc_send_status(mmc, timeout); | |
5d4fc8d9 RR |
477 | |
478 | return ret; | |
479 | ||
272cc70b AF |
480 | } |
481 | ||
fdbb873e | 482 | static int mmc_change_freq(struct mmc *mmc) |
272cc70b | 483 | { |
8bfa195e | 484 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
272cc70b AF |
485 | char cardtype; |
486 | int err; | |
487 | ||
488 | mmc->card_caps = 0; | |
489 | ||
d52ebf10 TC |
490 | if (mmc_host_is_spi(mmc)) |
491 | return 0; | |
492 | ||
272cc70b AF |
493 | /* Only version 4 supports high-speed */ |
494 | if (mmc->version < MMC_VERSION_4) | |
495 | return 0; | |
496 | ||
272cc70b AF |
497 | err = mmc_send_ext_csd(mmc, ext_csd); |
498 | ||
499 | if (err) | |
500 | return err; | |
501 | ||
0560db18 | 502 | cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; |
272cc70b AF |
503 | |
504 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); | |
505 | ||
506 | if (err) | |
507 | return err; | |
508 | ||
509 | /* Now check to see that it worked */ | |
510 | err = mmc_send_ext_csd(mmc, ext_csd); | |
511 | ||
512 | if (err) | |
513 | return err; | |
514 | ||
515 | /* No high-speed support */ | |
0560db18 | 516 | if (!ext_csd[EXT_CSD_HS_TIMING]) |
272cc70b AF |
517 | return 0; |
518 | ||
519 | /* High Speed is set, there are two types: 52MHz and 26MHz */ | |
d22e3d46 JC |
520 | if (cardtype & EXT_CSD_CARD_TYPE_52) { |
521 | if (cardtype & EXT_CSD_CARD_TYPE_DDR_52) | |
522 | mmc->card_caps |= MMC_MODE_DDR_52MHz; | |
272cc70b | 523 | mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
d22e3d46 | 524 | } else { |
272cc70b | 525 | mmc->card_caps |= MMC_MODE_HS; |
d22e3d46 | 526 | } |
272cc70b AF |
527 | |
528 | return 0; | |
529 | } | |
530 | ||
f866a46d SW |
531 | static int mmc_set_capacity(struct mmc *mmc, int part_num) |
532 | { | |
533 | switch (part_num) { | |
534 | case 0: | |
535 | mmc->capacity = mmc->capacity_user; | |
536 | break; | |
537 | case 1: | |
538 | case 2: | |
539 | mmc->capacity = mmc->capacity_boot; | |
540 | break; | |
541 | case 3: | |
542 | mmc->capacity = mmc->capacity_rpmb; | |
543 | break; | |
544 | case 4: | |
545 | case 5: | |
546 | case 6: | |
547 | case 7: | |
548 | mmc->capacity = mmc->capacity_gp[part_num - 4]; | |
549 | break; | |
550 | default: | |
551 | return -1; | |
552 | } | |
553 | ||
554 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
bc897b1d LW |
559 | int mmc_switch_part(int dev_num, unsigned int part_num) |
560 | { | |
561 | struct mmc *mmc = find_mmc_device(dev_num); | |
f866a46d | 562 | int ret; |
bc897b1d LW |
563 | |
564 | if (!mmc) | |
565 | return -1; | |
566 | ||
f866a46d SW |
567 | ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, |
568 | (mmc->part_config & ~PART_ACCESS_MASK) | |
569 | | (part_num & PART_ACCESS_MASK)); | |
570 | if (ret) | |
571 | return ret; | |
572 | ||
573 | return mmc_set_capacity(mmc, part_num); | |
bc897b1d LW |
574 | } |
575 | ||
48972d90 TR |
576 | int mmc_getcd(struct mmc *mmc) |
577 | { | |
578 | int cd; | |
579 | ||
580 | cd = board_mmc_getcd(mmc); | |
581 | ||
d4e1da4e | 582 | if (cd < 0) { |
93bfd616 PA |
583 | if (mmc->cfg->ops->getcd) |
584 | cd = mmc->cfg->ops->getcd(mmc); | |
d4e1da4e PK |
585 | else |
586 | cd = 1; | |
587 | } | |
48972d90 TR |
588 | |
589 | return cd; | |
590 | } | |
591 | ||
fdbb873e | 592 | static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) |
272cc70b AF |
593 | { |
594 | struct mmc_cmd cmd; | |
595 | struct mmc_data data; | |
596 | ||
597 | /* Switch the frequency */ | |
598 | cmd.cmdidx = SD_CMD_SWITCH_FUNC; | |
599 | cmd.resp_type = MMC_RSP_R1; | |
600 | cmd.cmdarg = (mode << 31) | 0xffffff; | |
601 | cmd.cmdarg &= ~(0xf << (group * 4)); | |
602 | cmd.cmdarg |= value << (group * 4); | |
272cc70b AF |
603 | |
604 | data.dest = (char *)resp; | |
605 | data.blocksize = 64; | |
606 | data.blocks = 1; | |
607 | data.flags = MMC_DATA_READ; | |
608 | ||
609 | return mmc_send_cmd(mmc, &cmd, &data); | |
610 | } | |
611 | ||
612 | ||
fdbb873e | 613 | static int sd_change_freq(struct mmc *mmc) |
272cc70b AF |
614 | { |
615 | int err; | |
616 | struct mmc_cmd cmd; | |
f781dd38 A |
617 | ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); |
618 | ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); | |
272cc70b AF |
619 | struct mmc_data data; |
620 | int timeout; | |
621 | ||
622 | mmc->card_caps = 0; | |
623 | ||
d52ebf10 TC |
624 | if (mmc_host_is_spi(mmc)) |
625 | return 0; | |
626 | ||
272cc70b AF |
627 | /* Read the SCR to find out if this card supports higher speeds */ |
628 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
629 | cmd.resp_type = MMC_RSP_R1; | |
630 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
631 | |
632 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
633 | ||
634 | if (err) | |
635 | return err; | |
636 | ||
637 | cmd.cmdidx = SD_CMD_APP_SEND_SCR; | |
638 | cmd.resp_type = MMC_RSP_R1; | |
639 | cmd.cmdarg = 0; | |
272cc70b AF |
640 | |
641 | timeout = 3; | |
642 | ||
643 | retry_scr: | |
f781dd38 | 644 | data.dest = (char *)scr; |
272cc70b AF |
645 | data.blocksize = 8; |
646 | data.blocks = 1; | |
647 | data.flags = MMC_DATA_READ; | |
648 | ||
649 | err = mmc_send_cmd(mmc, &cmd, &data); | |
650 | ||
651 | if (err) { | |
652 | if (timeout--) | |
653 | goto retry_scr; | |
654 | ||
655 | return err; | |
656 | } | |
657 | ||
4e3d89ba YK |
658 | mmc->scr[0] = __be32_to_cpu(scr[0]); |
659 | mmc->scr[1] = __be32_to_cpu(scr[1]); | |
272cc70b AF |
660 | |
661 | switch ((mmc->scr[0] >> 24) & 0xf) { | |
662 | case 0: | |
663 | mmc->version = SD_VERSION_1_0; | |
664 | break; | |
665 | case 1: | |
666 | mmc->version = SD_VERSION_1_10; | |
667 | break; | |
668 | case 2: | |
669 | mmc->version = SD_VERSION_2; | |
1741c64d JC |
670 | if ((mmc->scr[0] >> 15) & 0x1) |
671 | mmc->version = SD_VERSION_3; | |
272cc70b AF |
672 | break; |
673 | default: | |
674 | mmc->version = SD_VERSION_1_0; | |
675 | break; | |
676 | } | |
677 | ||
b44c7083 AS |
678 | if (mmc->scr[0] & SD_DATA_4BIT) |
679 | mmc->card_caps |= MMC_MODE_4BIT; | |
680 | ||
272cc70b AF |
681 | /* Version 1.0 doesn't support switching */ |
682 | if (mmc->version == SD_VERSION_1_0) | |
683 | return 0; | |
684 | ||
685 | timeout = 4; | |
686 | while (timeout--) { | |
687 | err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, | |
f781dd38 | 688 | (u8 *)switch_status); |
272cc70b AF |
689 | |
690 | if (err) | |
691 | return err; | |
692 | ||
693 | /* The high-speed function is busy. Try again */ | |
4e3d89ba | 694 | if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) |
272cc70b AF |
695 | break; |
696 | } | |
697 | ||
272cc70b | 698 | /* If high-speed isn't supported, we return */ |
4e3d89ba | 699 | if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) |
272cc70b AF |
700 | return 0; |
701 | ||
2c3fbf4c ML |
702 | /* |
703 | * If the host doesn't support SD_HIGHSPEED, do not switch card to | |
704 | * HIGHSPEED mode even if the card support SD_HIGHSPPED. | |
705 | * This can avoid furthur problem when the card runs in different | |
706 | * mode between the host. | |
707 | */ | |
93bfd616 PA |
708 | if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && |
709 | (mmc->cfg->host_caps & MMC_MODE_HS))) | |
2c3fbf4c ML |
710 | return 0; |
711 | ||
f781dd38 | 712 | err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); |
272cc70b AF |
713 | |
714 | if (err) | |
715 | return err; | |
716 | ||
4e3d89ba | 717 | if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) |
272cc70b AF |
718 | mmc->card_caps |= MMC_MODE_HS; |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
723 | /* frequency bases */ | |
724 | /* divided by 10 to be nice to platforms without floating point */ | |
5f837c2c | 725 | static const int fbase[] = { |
272cc70b AF |
726 | 10000, |
727 | 100000, | |
728 | 1000000, | |
729 | 10000000, | |
730 | }; | |
731 | ||
732 | /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice | |
733 | * to platforms without floating point. | |
734 | */ | |
5f837c2c | 735 | static const int multipliers[] = { |
272cc70b AF |
736 | 0, /* reserved */ |
737 | 10, | |
738 | 12, | |
739 | 13, | |
740 | 15, | |
741 | 20, | |
742 | 25, | |
743 | 30, | |
744 | 35, | |
745 | 40, | |
746 | 45, | |
747 | 50, | |
748 | 55, | |
749 | 60, | |
750 | 70, | |
751 | 80, | |
752 | }; | |
753 | ||
fdbb873e | 754 | static void mmc_set_ios(struct mmc *mmc) |
272cc70b | 755 | { |
93bfd616 PA |
756 | if (mmc->cfg->ops->set_ios) |
757 | mmc->cfg->ops->set_ios(mmc); | |
272cc70b AF |
758 | } |
759 | ||
760 | void mmc_set_clock(struct mmc *mmc, uint clock) | |
761 | { | |
93bfd616 PA |
762 | if (clock > mmc->cfg->f_max) |
763 | clock = mmc->cfg->f_max; | |
272cc70b | 764 | |
93bfd616 PA |
765 | if (clock < mmc->cfg->f_min) |
766 | clock = mmc->cfg->f_min; | |
272cc70b AF |
767 | |
768 | mmc->clock = clock; | |
769 | ||
770 | mmc_set_ios(mmc); | |
771 | } | |
772 | ||
fdbb873e | 773 | static void mmc_set_bus_width(struct mmc *mmc, uint width) |
272cc70b AF |
774 | { |
775 | mmc->bus_width = width; | |
776 | ||
777 | mmc_set_ios(mmc); | |
778 | } | |
779 | ||
fdbb873e | 780 | static int mmc_startup(struct mmc *mmc) |
272cc70b | 781 | { |
f866a46d | 782 | int err, i; |
272cc70b | 783 | uint mult, freq; |
639b7827 | 784 | u64 cmult, csize, capacity; |
272cc70b | 785 | struct mmc_cmd cmd; |
8bfa195e SG |
786 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
787 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); | |
5d4fc8d9 | 788 | int timeout = 1000; |
272cc70b | 789 | |
d52ebf10 TC |
790 | #ifdef CONFIG_MMC_SPI_CRC_ON |
791 | if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ | |
792 | cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; | |
793 | cmd.resp_type = MMC_RSP_R1; | |
794 | cmd.cmdarg = 1; | |
d52ebf10 TC |
795 | err = mmc_send_cmd(mmc, &cmd, NULL); |
796 | ||
797 | if (err) | |
798 | return err; | |
799 | } | |
800 | #endif | |
801 | ||
272cc70b | 802 | /* Put the Card in Identify Mode */ |
d52ebf10 TC |
803 | cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : |
804 | MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ | |
272cc70b AF |
805 | cmd.resp_type = MMC_RSP_R2; |
806 | cmd.cmdarg = 0; | |
272cc70b AF |
807 | |
808 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
809 | ||
810 | if (err) | |
811 | return err; | |
812 | ||
813 | memcpy(mmc->cid, cmd.response, 16); | |
814 | ||
815 | /* | |
816 | * For MMC cards, set the Relative Address. | |
817 | * For SD cards, get the Relatvie Address. | |
818 | * This also puts the cards into Standby State | |
819 | */ | |
d52ebf10 TC |
820 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
821 | cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; | |
822 | cmd.cmdarg = mmc->rca << 16; | |
823 | cmd.resp_type = MMC_RSP_R6; | |
272cc70b | 824 | |
d52ebf10 | 825 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 826 | |
d52ebf10 TC |
827 | if (err) |
828 | return err; | |
272cc70b | 829 | |
d52ebf10 TC |
830 | if (IS_SD(mmc)) |
831 | mmc->rca = (cmd.response[0] >> 16) & 0xffff; | |
832 | } | |
272cc70b AF |
833 | |
834 | /* Get the Card-Specific Data */ | |
835 | cmd.cmdidx = MMC_CMD_SEND_CSD; | |
836 | cmd.resp_type = MMC_RSP_R2; | |
837 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
838 | |
839 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
840 | ||
5d4fc8d9 RR |
841 | /* Waiting for the ready status */ |
842 | mmc_send_status(mmc, timeout); | |
843 | ||
272cc70b AF |
844 | if (err) |
845 | return err; | |
846 | ||
998be3dd RV |
847 | mmc->csd[0] = cmd.response[0]; |
848 | mmc->csd[1] = cmd.response[1]; | |
849 | mmc->csd[2] = cmd.response[2]; | |
850 | mmc->csd[3] = cmd.response[3]; | |
272cc70b AF |
851 | |
852 | if (mmc->version == MMC_VERSION_UNKNOWN) { | |
0b453ffe | 853 | int version = (cmd.response[0] >> 26) & 0xf; |
272cc70b AF |
854 | |
855 | switch (version) { | |
856 | case 0: | |
857 | mmc->version = MMC_VERSION_1_2; | |
858 | break; | |
859 | case 1: | |
860 | mmc->version = MMC_VERSION_1_4; | |
861 | break; | |
862 | case 2: | |
863 | mmc->version = MMC_VERSION_2_2; | |
864 | break; | |
865 | case 3: | |
866 | mmc->version = MMC_VERSION_3; | |
867 | break; | |
868 | case 4: | |
869 | mmc->version = MMC_VERSION_4; | |
870 | break; | |
871 | default: | |
872 | mmc->version = MMC_VERSION_1_2; | |
873 | break; | |
874 | } | |
875 | } | |
876 | ||
877 | /* divide frequency by 10, since the mults are 10x bigger */ | |
0b453ffe RV |
878 | freq = fbase[(cmd.response[0] & 0x7)]; |
879 | mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; | |
272cc70b AF |
880 | |
881 | mmc->tran_speed = freq * mult; | |
882 | ||
ab71188c | 883 | mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); |
998be3dd | 884 | mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); |
272cc70b AF |
885 | |
886 | if (IS_SD(mmc)) | |
887 | mmc->write_bl_len = mmc->read_bl_len; | |
888 | else | |
998be3dd | 889 | mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); |
272cc70b AF |
890 | |
891 | if (mmc->high_capacity) { | |
892 | csize = (mmc->csd[1] & 0x3f) << 16 | |
893 | | (mmc->csd[2] & 0xffff0000) >> 16; | |
894 | cmult = 8; | |
895 | } else { | |
896 | csize = (mmc->csd[1] & 0x3ff) << 2 | |
897 | | (mmc->csd[2] & 0xc0000000) >> 30; | |
898 | cmult = (mmc->csd[2] & 0x00038000) >> 15; | |
899 | } | |
900 | ||
f866a46d SW |
901 | mmc->capacity_user = (csize + 1) << (cmult + 2); |
902 | mmc->capacity_user *= mmc->read_bl_len; | |
903 | mmc->capacity_boot = 0; | |
904 | mmc->capacity_rpmb = 0; | |
905 | for (i = 0; i < 4; i++) | |
906 | mmc->capacity_gp[i] = 0; | |
272cc70b | 907 | |
8bfa195e SG |
908 | if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) |
909 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 910 | |
8bfa195e SG |
911 | if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) |
912 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 913 | |
ab71188c MN |
914 | if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { |
915 | cmd.cmdidx = MMC_CMD_SET_DSR; | |
916 | cmd.cmdarg = (mmc->dsr & 0xffff) << 16; | |
917 | cmd.resp_type = MMC_RSP_NONE; | |
918 | if (mmc_send_cmd(mmc, &cmd, NULL)) | |
919 | printf("MMC: SET_DSR failed\n"); | |
920 | } | |
921 | ||
272cc70b | 922 | /* Select the card, and put it into Transfer Mode */ |
d52ebf10 TC |
923 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
924 | cmd.cmdidx = MMC_CMD_SELECT_CARD; | |
fe8f7066 | 925 | cmd.resp_type = MMC_RSP_R1; |
d52ebf10 | 926 | cmd.cmdarg = mmc->rca << 16; |
d52ebf10 | 927 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 928 | |
d52ebf10 TC |
929 | if (err) |
930 | return err; | |
931 | } | |
272cc70b | 932 | |
e6f99a56 LW |
933 | /* |
934 | * For SD, its erase group is always one sector | |
935 | */ | |
936 | mmc->erase_grp_size = 1; | |
bc897b1d | 937 | mmc->part_config = MMCPART_NOAVAILABLE; |
d23e2c09 SG |
938 | if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { |
939 | /* check ext_csd version and capacity */ | |
940 | err = mmc_send_ext_csd(mmc, ext_csd); | |
fdbb873e | 941 | if (!err && (ext_csd[EXT_CSD_REV] >= 2)) { |
639b7827 YS |
942 | /* |
943 | * According to the JEDEC Standard, the value of | |
944 | * ext_csd's capacity is valid if the value is more | |
945 | * than 2GB | |
946 | */ | |
0560db18 LW |
947 | capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 |
948 | | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | |
949 | | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | |
950 | | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; | |
8bfa195e | 951 | capacity *= MMC_MAX_BLOCK_LEN; |
b1f1e821 | 952 | if ((capacity >> 20) > 2 * 1024) |
f866a46d | 953 | mmc->capacity_user = capacity; |
d23e2c09 | 954 | } |
bc897b1d | 955 | |
64f4a619 JC |
956 | switch (ext_csd[EXT_CSD_REV]) { |
957 | case 1: | |
958 | mmc->version = MMC_VERSION_4_1; | |
959 | break; | |
960 | case 2: | |
961 | mmc->version = MMC_VERSION_4_2; | |
962 | break; | |
963 | case 3: | |
964 | mmc->version = MMC_VERSION_4_3; | |
965 | break; | |
966 | case 5: | |
967 | mmc->version = MMC_VERSION_4_41; | |
968 | break; | |
969 | case 6: | |
970 | mmc->version = MMC_VERSION_4_5; | |
971 | break; | |
972 | } | |
973 | ||
e6f99a56 | 974 | /* |
1937e5aa OM |
975 | * Host needs to enable ERASE_GRP_DEF bit if device is |
976 | * partitioned. This bit will be lost every time after a reset | |
977 | * or power off. This will affect erase size. | |
e6f99a56 | 978 | */ |
1937e5aa OM |
979 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && |
980 | (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) { | |
981 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
982 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
983 | ||
984 | if (err) | |
985 | return err; | |
986 | ||
987 | /* Read out group size from ext_csd */ | |
0560db18 | 988 | mmc->erase_grp_size = |
8bfa195e SG |
989 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * |
990 | MMC_MAX_BLOCK_LEN * 1024; | |
991 | } else { | |
1937e5aa | 992 | /* Calculate the group size from the csd value. */ |
e6f99a56 LW |
993 | int erase_gsz, erase_gmul; |
994 | erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; | |
995 | erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; | |
996 | mmc->erase_grp_size = (erase_gsz + 1) | |
997 | * (erase_gmul + 1); | |
998 | } | |
999 | ||
bc897b1d | 1000 | /* store the partition info of emmc */ |
8948ea83 SW |
1001 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || |
1002 | ext_csd[EXT_CSD_BOOT_MULT]) | |
0560db18 | 1003 | mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; |
f866a46d SW |
1004 | |
1005 | mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; | |
1006 | ||
1007 | mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; | |
1008 | ||
1009 | for (i = 0; i < 4; i++) { | |
1010 | int idx = EXT_CSD_GP_SIZE_MULT + i * 3; | |
1011 | mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) + | |
1012 | (ext_csd[idx + 1] << 8) + ext_csd[idx]; | |
1013 | mmc->capacity_gp[i] *= | |
1014 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1015 | mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1016 | } | |
d23e2c09 SG |
1017 | } |
1018 | ||
f866a46d SW |
1019 | err = mmc_set_capacity(mmc, mmc->part_num); |
1020 | if (err) | |
1021 | return err; | |
1022 | ||
272cc70b AF |
1023 | if (IS_SD(mmc)) |
1024 | err = sd_change_freq(mmc); | |
1025 | else | |
1026 | err = mmc_change_freq(mmc); | |
1027 | ||
1028 | if (err) | |
1029 | return err; | |
1030 | ||
1031 | /* Restrict card's capabilities by what the host can do */ | |
93bfd616 | 1032 | mmc->card_caps &= mmc->cfg->host_caps; |
272cc70b AF |
1033 | |
1034 | if (IS_SD(mmc)) { | |
1035 | if (mmc->card_caps & MMC_MODE_4BIT) { | |
1036 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1037 | cmd.resp_type = MMC_RSP_R1; | |
1038 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1039 | |
1040 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1041 | if (err) | |
1042 | return err; | |
1043 | ||
1044 | cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; | |
1045 | cmd.resp_type = MMC_RSP_R1; | |
1046 | cmd.cmdarg = 2; | |
272cc70b AF |
1047 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1048 | if (err) | |
1049 | return err; | |
1050 | ||
1051 | mmc_set_bus_width(mmc, 4); | |
1052 | } | |
1053 | ||
1054 | if (mmc->card_caps & MMC_MODE_HS) | |
ad5fd922 | 1055 | mmc->tran_speed = 50000000; |
272cc70b | 1056 | else |
ad5fd922 | 1057 | mmc->tran_speed = 25000000; |
272cc70b | 1058 | } else { |
7798f6db AF |
1059 | int idx; |
1060 | ||
1061 | /* An array of possible bus widths in order of preference */ | |
1062 | static unsigned ext_csd_bits[] = { | |
d22e3d46 JC |
1063 | EXT_CSD_DDR_BUS_WIDTH_8, |
1064 | EXT_CSD_DDR_BUS_WIDTH_4, | |
7798f6db AF |
1065 | EXT_CSD_BUS_WIDTH_8, |
1066 | EXT_CSD_BUS_WIDTH_4, | |
1067 | EXT_CSD_BUS_WIDTH_1, | |
1068 | }; | |
1069 | ||
1070 | /* An array to map CSD bus widths to host cap bits */ | |
1071 | static unsigned ext_to_hostcaps[] = { | |
d22e3d46 JC |
1072 | [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz, |
1073 | [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz, | |
7798f6db AF |
1074 | [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, |
1075 | [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, | |
1076 | }; | |
1077 | ||
1078 | /* An array to map chosen bus width to an integer */ | |
1079 | static unsigned widths[] = { | |
d22e3d46 | 1080 | 8, 4, 8, 4, 1, |
7798f6db AF |
1081 | }; |
1082 | ||
1083 | for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { | |
1084 | unsigned int extw = ext_csd_bits[idx]; | |
1085 | ||
1086 | /* | |
1087 | * Check to make sure the controller supports | |
1088 | * this bus width, if it's more than 1 | |
1089 | */ | |
1090 | if (extw != EXT_CSD_BUS_WIDTH_1 && | |
93bfd616 | 1091 | !(mmc->cfg->host_caps & ext_to_hostcaps[extw])) |
7798f6db AF |
1092 | continue; |
1093 | ||
272cc70b | 1094 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
7798f6db | 1095 | EXT_CSD_BUS_WIDTH, extw); |
272cc70b AF |
1096 | |
1097 | if (err) | |
4137894e | 1098 | continue; |
272cc70b | 1099 | |
7798f6db | 1100 | mmc_set_bus_width(mmc, widths[idx]); |
4137894e LW |
1101 | |
1102 | err = mmc_send_ext_csd(mmc, test_csd); | |
1103 | if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \ | |
1104 | == test_csd[EXT_CSD_PARTITIONING_SUPPORT] | |
1105 | && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \ | |
1106 | == test_csd[EXT_CSD_ERASE_GROUP_DEF] \ | |
1107 | && ext_csd[EXT_CSD_REV] \ | |
1108 | == test_csd[EXT_CSD_REV] | |
1109 | && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \ | |
1110 | == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1111 | && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \ | |
1112 | &test_csd[EXT_CSD_SEC_CNT], 4) == 0) { | |
1113 | ||
7798f6db | 1114 | mmc->card_caps |= ext_to_hostcaps[extw]; |
4137894e LW |
1115 | break; |
1116 | } | |
272cc70b AF |
1117 | } |
1118 | ||
1119 | if (mmc->card_caps & MMC_MODE_HS) { | |
1120 | if (mmc->card_caps & MMC_MODE_HS_52MHz) | |
ad5fd922 | 1121 | mmc->tran_speed = 52000000; |
272cc70b | 1122 | else |
ad5fd922 JC |
1123 | mmc->tran_speed = 26000000; |
1124 | } | |
272cc70b AF |
1125 | } |
1126 | ||
ad5fd922 JC |
1127 | mmc_set_clock(mmc, mmc->tran_speed); |
1128 | ||
272cc70b AF |
1129 | /* fill in device description */ |
1130 | mmc->block_dev.lun = 0; | |
1131 | mmc->block_dev.type = 0; | |
1132 | mmc->block_dev.blksz = mmc->read_bl_len; | |
0472fbfd | 1133 | mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); |
9b1f942c | 1134 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); |
56196826 | 1135 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
babce5f6 TH |
1136 | sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", |
1137 | mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), | |
1138 | (mmc->cid[3] >> 16) & 0xffff); | |
1139 | sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, | |
1140 | (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, | |
1141 | (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, | |
1142 | (mmc->cid[2] >> 24) & 0xff); | |
1143 | sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, | |
1144 | (mmc->cid[2] >> 16) & 0xf); | |
56196826 PB |
1145 | #else |
1146 | mmc->block_dev.vendor[0] = 0; | |
1147 | mmc->block_dev.product[0] = 0; | |
1148 | mmc->block_dev.revision[0] = 0; | |
1149 | #endif | |
122efd43 | 1150 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) |
272cc70b | 1151 | init_part(&mmc->block_dev); |
122efd43 | 1152 | #endif |
272cc70b AF |
1153 | |
1154 | return 0; | |
1155 | } | |
1156 | ||
fdbb873e | 1157 | static int mmc_send_if_cond(struct mmc *mmc) |
272cc70b AF |
1158 | { |
1159 | struct mmc_cmd cmd; | |
1160 | int err; | |
1161 | ||
1162 | cmd.cmdidx = SD_CMD_SEND_IF_COND; | |
1163 | /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ | |
93bfd616 | 1164 | cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; |
272cc70b | 1165 | cmd.resp_type = MMC_RSP_R7; |
272cc70b AF |
1166 | |
1167 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1168 | ||
1169 | if (err) | |
1170 | return err; | |
1171 | ||
998be3dd | 1172 | if ((cmd.response[0] & 0xff) != 0xaa) |
272cc70b AF |
1173 | return UNUSABLE_ERR; |
1174 | else | |
1175 | mmc->version = SD_VERSION_2; | |
1176 | ||
1177 | return 0; | |
1178 | } | |
1179 | ||
93bfd616 PA |
1180 | /* not used any more */ |
1181 | int __deprecated mmc_register(struct mmc *mmc) | |
1182 | { | |
1183 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) | |
1184 | printf("%s is deprecated! use mmc_create() instead.\n", __func__); | |
1185 | #endif | |
1186 | return -1; | |
1187 | } | |
1188 | ||
1189 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) | |
272cc70b | 1190 | { |
93bfd616 PA |
1191 | struct mmc *mmc; |
1192 | ||
1193 | /* quick validation */ | |
1194 | if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || | |
1195 | cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) | |
1196 | return NULL; | |
1197 | ||
1198 | mmc = calloc(1, sizeof(*mmc)); | |
1199 | if (mmc == NULL) | |
1200 | return NULL; | |
1201 | ||
1202 | mmc->cfg = cfg; | |
1203 | mmc->priv = priv; | |
1204 | ||
1205 | /* the following chunk was mmc_register() */ | |
1206 | ||
ab71188c MN |
1207 | /* Setup dsr related values */ |
1208 | mmc->dsr_imp = 0; | |
1209 | mmc->dsr = 0xffffffff; | |
272cc70b AF |
1210 | /* Setup the universal parts of the block interface just once */ |
1211 | mmc->block_dev.if_type = IF_TYPE_MMC; | |
1212 | mmc->block_dev.dev = cur_dev_num++; | |
1213 | mmc->block_dev.removable = 1; | |
1214 | mmc->block_dev.block_read = mmc_bread; | |
1215 | mmc->block_dev.block_write = mmc_bwrite; | |
e6f99a56 | 1216 | mmc->block_dev.block_erase = mmc_berase; |
272cc70b | 1217 | |
93bfd616 PA |
1218 | /* setup initial part type */ |
1219 | mmc->block_dev.part_type = mmc->cfg->part_type; | |
272cc70b | 1220 | |
93bfd616 | 1221 | INIT_LIST_HEAD(&mmc->link); |
272cc70b | 1222 | |
93bfd616 PA |
1223 | list_add_tail(&mmc->link, &mmc_devices); |
1224 | ||
1225 | return mmc; | |
1226 | } | |
1227 | ||
1228 | void mmc_destroy(struct mmc *mmc) | |
1229 | { | |
1230 | /* only freeing memory for now */ | |
1231 | free(mmc); | |
272cc70b AF |
1232 | } |
1233 | ||
df3fc526 | 1234 | #ifdef CONFIG_PARTITIONS |
272cc70b AF |
1235 | block_dev_desc_t *mmc_get_dev(int dev) |
1236 | { | |
1237 | struct mmc *mmc = find_mmc_device(dev); | |
6bb4b4bc | 1238 | if (!mmc || mmc_init(mmc)) |
40242bc3 | 1239 | return NULL; |
272cc70b | 1240 | |
40242bc3 | 1241 | return &mmc->block_dev; |
272cc70b | 1242 | } |
df3fc526 | 1243 | #endif |
272cc70b | 1244 | |
e9550449 | 1245 | int mmc_start_init(struct mmc *mmc) |
272cc70b | 1246 | { |
afd5932b | 1247 | int err; |
272cc70b | 1248 | |
ab769f22 | 1249 | /* we pretend there's no card when init is NULL */ |
93bfd616 | 1250 | if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { |
48972d90 | 1251 | mmc->has_init = 0; |
56196826 | 1252 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
48972d90 | 1253 | printf("MMC: no card present\n"); |
56196826 | 1254 | #endif |
48972d90 TR |
1255 | return NO_CARD_ERR; |
1256 | } | |
1257 | ||
bc897b1d LW |
1258 | if (mmc->has_init) |
1259 | return 0; | |
1260 | ||
ab769f22 | 1261 | /* made sure it's not NULL earlier */ |
93bfd616 | 1262 | err = mmc->cfg->ops->init(mmc); |
272cc70b AF |
1263 | |
1264 | if (err) | |
1265 | return err; | |
1266 | ||
b86b85e2 IY |
1267 | mmc_set_bus_width(mmc, 1); |
1268 | mmc_set_clock(mmc, 1); | |
1269 | ||
272cc70b AF |
1270 | /* Reset the Card */ |
1271 | err = mmc_go_idle(mmc); | |
1272 | ||
1273 | if (err) | |
1274 | return err; | |
1275 | ||
bc897b1d LW |
1276 | /* The internal partition reset to user partition(0) at every CMD0*/ |
1277 | mmc->part_num = 0; | |
1278 | ||
272cc70b | 1279 | /* Test for SD version 2 */ |
afd5932b | 1280 | err = mmc_send_if_cond(mmc); |
272cc70b | 1281 | |
272cc70b AF |
1282 | /* Now try to get the SD card's operating condition */ |
1283 | err = sd_send_op_cond(mmc); | |
1284 | ||
1285 | /* If the command timed out, we check for an MMC card */ | |
1286 | if (err == TIMEOUT) { | |
1287 | err = mmc_send_op_cond(mmc); | |
1288 | ||
e9550449 | 1289 | if (err && err != IN_PROGRESS) { |
56196826 | 1290 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 1291 | printf("Card did not respond to voltage select!\n"); |
56196826 | 1292 | #endif |
272cc70b AF |
1293 | return UNUSABLE_ERR; |
1294 | } | |
1295 | } | |
1296 | ||
e9550449 CLC |
1297 | if (err == IN_PROGRESS) |
1298 | mmc->init_in_progress = 1; | |
1299 | ||
1300 | return err; | |
1301 | } | |
1302 | ||
1303 | static int mmc_complete_init(struct mmc *mmc) | |
1304 | { | |
1305 | int err = 0; | |
1306 | ||
1307 | if (mmc->op_cond_pending) | |
1308 | err = mmc_complete_op_cond(mmc); | |
1309 | ||
1310 | if (!err) | |
1311 | err = mmc_startup(mmc); | |
bc897b1d LW |
1312 | if (err) |
1313 | mmc->has_init = 0; | |
1314 | else | |
1315 | mmc->has_init = 1; | |
e9550449 CLC |
1316 | mmc->init_in_progress = 0; |
1317 | return err; | |
1318 | } | |
1319 | ||
1320 | int mmc_init(struct mmc *mmc) | |
1321 | { | |
1322 | int err = IN_PROGRESS; | |
1323 | unsigned start = get_timer(0); | |
1324 | ||
1325 | if (mmc->has_init) | |
1326 | return 0; | |
1327 | if (!mmc->init_in_progress) | |
1328 | err = mmc_start_init(mmc); | |
1329 | ||
1330 | if (!err || err == IN_PROGRESS) | |
1331 | err = mmc_complete_init(mmc); | |
1332 | debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); | |
bc897b1d | 1333 | return err; |
272cc70b AF |
1334 | } |
1335 | ||
ab71188c MN |
1336 | int mmc_set_dsr(struct mmc *mmc, u16 val) |
1337 | { | |
1338 | mmc->dsr = val; | |
1339 | return 0; | |
1340 | } | |
1341 | ||
272cc70b AF |
1342 | /* |
1343 | * CPU and board-specific MMC initializations. Aliased function | |
1344 | * signals caller to move on | |
1345 | */ | |
1346 | static int __def_mmc_init(bd_t *bis) | |
1347 | { | |
1348 | return -1; | |
1349 | } | |
1350 | ||
f9a109b3 PT |
1351 | int cpu_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init"))); |
1352 | int board_mmc_init(bd_t *bis) __attribute__((weak, alias("__def_mmc_init"))); | |
272cc70b | 1353 | |
56196826 PB |
1354 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
1355 | ||
272cc70b AF |
1356 | void print_mmc_devices(char separator) |
1357 | { | |
1358 | struct mmc *m; | |
1359 | struct list_head *entry; | |
1360 | ||
1361 | list_for_each(entry, &mmc_devices) { | |
1362 | m = list_entry(entry, struct mmc, link); | |
1363 | ||
93bfd616 | 1364 | printf("%s: %d", m->cfg->name, m->block_dev.dev); |
272cc70b AF |
1365 | |
1366 | if (entry->next != &mmc_devices) | |
1367 | printf("%c ", separator); | |
1368 | } | |
1369 | ||
1370 | printf("\n"); | |
1371 | } | |
1372 | ||
56196826 PB |
1373 | #else |
1374 | void print_mmc_devices(char separator) { } | |
1375 | #endif | |
1376 | ||
ea6ebe21 LW |
1377 | int get_mmc_num(void) |
1378 | { | |
1379 | return cur_dev_num; | |
1380 | } | |
1381 | ||
e9550449 CLC |
1382 | void mmc_set_preinit(struct mmc *mmc, int preinit) |
1383 | { | |
1384 | mmc->preinit = preinit; | |
1385 | } | |
1386 | ||
1387 | static void do_preinit(void) | |
1388 | { | |
1389 | struct mmc *m; | |
1390 | struct list_head *entry; | |
1391 | ||
1392 | list_for_each(entry, &mmc_devices) { | |
1393 | m = list_entry(entry, struct mmc, link); | |
1394 | ||
1395 | if (m->preinit) | |
1396 | mmc_start_init(m); | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | ||
272cc70b AF |
1401 | int mmc_initialize(bd_t *bis) |
1402 | { | |
1403 | INIT_LIST_HEAD (&mmc_devices); | |
1404 | cur_dev_num = 0; | |
1405 | ||
1406 | if (board_mmc_init(bis) < 0) | |
1407 | cpu_mmc_init(bis); | |
1408 | ||
bb0dc108 | 1409 | #ifndef CONFIG_SPL_BUILD |
272cc70b | 1410 | print_mmc_devices(','); |
bb0dc108 | 1411 | #endif |
272cc70b | 1412 | |
e9550449 | 1413 | do_preinit(); |
272cc70b AF |
1414 | return 0; |
1415 | } | |
3690d6d6 A |
1416 | |
1417 | #ifdef CONFIG_SUPPORT_EMMC_BOOT | |
1418 | /* | |
1419 | * This function changes the size of boot partition and the size of rpmb | |
1420 | * partition present on EMMC devices. | |
1421 | * | |
1422 | * Input Parameters: | |
1423 | * struct *mmc: pointer for the mmc device strcuture | |
1424 | * bootsize: size of boot partition | |
1425 | * rpmbsize: size of rpmb partition | |
1426 | * | |
1427 | * Returns 0 on success. | |
1428 | */ | |
1429 | ||
1430 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
1431 | unsigned long rpmbsize) | |
1432 | { | |
1433 | int err; | |
1434 | struct mmc_cmd cmd; | |
1435 | ||
1436 | /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ | |
1437 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1438 | cmd.resp_type = MMC_RSP_R1b; | |
1439 | cmd.cmdarg = MMC_CMD62_ARG1; | |
1440 | ||
1441 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1442 | if (err) { | |
1443 | debug("mmc_boot_partition_size_change: Error1 = %d\n", err); | |
1444 | return err; | |
1445 | } | |
1446 | ||
1447 | /* Boot partition changing mode */ | |
1448 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1449 | cmd.resp_type = MMC_RSP_R1b; | |
1450 | cmd.cmdarg = MMC_CMD62_ARG2; | |
1451 | ||
1452 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1453 | if (err) { | |
1454 | debug("mmc_boot_partition_size_change: Error2 = %d\n", err); | |
1455 | return err; | |
1456 | } | |
1457 | /* boot partition size is multiple of 128KB */ | |
1458 | bootsize = (bootsize * 1024) / 128; | |
1459 | ||
1460 | /* Arg: boot partition size */ | |
1461 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1462 | cmd.resp_type = MMC_RSP_R1b; | |
1463 | cmd.cmdarg = bootsize; | |
1464 | ||
1465 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1466 | if (err) { | |
1467 | debug("mmc_boot_partition_size_change: Error3 = %d\n", err); | |
1468 | return err; | |
1469 | } | |
1470 | /* RPMB partition size is multiple of 128KB */ | |
1471 | rpmbsize = (rpmbsize * 1024) / 128; | |
1472 | /* Arg: RPMB partition size */ | |
1473 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1474 | cmd.resp_type = MMC_RSP_R1b; | |
1475 | cmd.cmdarg = rpmbsize; | |
1476 | ||
1477 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1478 | if (err) { | |
1479 | debug("mmc_boot_partition_size_change: Error4 = %d\n", err); | |
1480 | return err; | |
1481 | } | |
1482 | return 0; | |
1483 | } | |
1484 | ||
5a99b9de TR |
1485 | /* |
1486 | * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH | |
1487 | * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH | |
1488 | * and BOOT_MODE. | |
1489 | * | |
1490 | * Returns 0 on success. | |
1491 | */ | |
1492 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) | |
1493 | { | |
1494 | int err; | |
1495 | ||
1496 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, | |
1497 | EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | | |
1498 | EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | | |
1499 | EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); | |
1500 | ||
1501 | if (err) | |
1502 | return err; | |
1503 | return 0; | |
1504 | } | |
1505 | ||
792970b0 TR |
1506 | /* |
1507 | * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) | |
1508 | * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and | |
1509 | * PARTITION_ACCESS. | |
1510 | * | |
1511 | * Returns 0 on success. | |
1512 | */ | |
1513 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) | |
1514 | { | |
1515 | int err; | |
1516 | ||
1517 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, | |
1518 | EXT_CSD_BOOT_ACK(ack) | | |
1519 | EXT_CSD_BOOT_PART_NUM(part_num) | | |
1520 | EXT_CSD_PARTITION_ACCESS(access)); | |
1521 | ||
1522 | if (err) | |
1523 | return err; | |
1524 | return 0; | |
1525 | } | |
33ace362 TR |
1526 | |
1527 | /* | |
1528 | * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value | |
1529 | * for enable. Note that this is a write-once field for non-zero values. | |
1530 | * | |
1531 | * Returns 0 on success. | |
1532 | */ | |
1533 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) | |
1534 | { | |
1535 | return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, | |
1536 | enable); | |
1537 | } | |
3690d6d6 | 1538 | #endif |