]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86: also use %BW / %DQ for kshift*
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
bb5b3501
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
4 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
5 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
6 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
7 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
8 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
9 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
10 VEX_W_0F3A33_L_0): Delete.
11 (dis386): Adjust "BW" description.
12 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
13 0F3A31, 0F3A32, and 0F3A33.
14 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
15 entries.
16 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
17 entries.
18
7531c613
JB		 192020-07-14 Jan Beulich <jbeulich@suse.com>
20
21 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
22 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
23 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
24 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
25 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
26 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
27 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
28 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
29 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
30 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
31 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
32 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
33 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
34 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
35 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
36 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
37 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
38 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
39 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
40 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
41 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
42 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
43 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
44 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
45 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
46 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
47 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
48 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
49 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
50 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
51 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
52 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
53 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
54 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
55 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
56 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
57 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
58 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
59 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
60 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
61 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
62 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
63 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
64 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
65 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
66 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
67 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
68 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
69 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
70 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
71 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
72 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
73 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
74 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
75 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
76 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
77 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
78 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
79 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
80 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
81 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
82 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
83 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
84 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
85 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
86 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
87 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
88 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
89 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
90 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
91 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
92 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
93 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
94 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
95 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
96 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
97 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
98 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
99 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
100 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
101 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
102 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
103 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
104 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
105 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
106 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
107 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
108 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
109 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
110 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
111 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
112 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
113 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
114 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
115 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
116 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
117 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
118 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
119 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
120 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
121 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
122 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
123 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
124 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
125 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
126 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
127 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
128 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
129 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
130 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
131 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
132 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
133 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
134 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
135 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
136 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
137 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
138 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
139 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
140 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
141 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
142 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
143 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
144 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
145 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
146 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
147 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
148 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
149 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
150 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
151 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
152 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
153 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
154 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
155 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
156 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
157 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
158 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
159 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
160 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
161 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
162 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
163 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
164 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
165 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
166 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
167 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
168 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
169 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
170 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
171 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
172 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
173 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
174 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
175 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
176 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
177 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
178 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
179 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
180 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
181 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
182 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
183 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
184 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
185 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
186 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
187 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
188 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
189 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
190 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
191 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
192 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
193 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
194 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
195 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
196 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
197 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
198 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
199 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
200 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
201 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
202 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
203 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
204 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
205 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
206 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
207 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
208 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
209 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
210 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
211 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
212 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
213 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
214 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
215 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
216 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
217 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
218 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
219 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
220 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
221 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
222 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
223 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
224 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
225 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
226 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
227 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
228 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
229 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
230 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
231 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
232 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
233 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
234 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
235 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
236 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
237 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
238 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
239 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
240 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
241 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
242 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
243 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
244 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
245 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
246 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
247 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
248 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
249 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
250 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
251 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
252 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
253 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
254 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
255 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
256 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
257 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
258 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
259 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
260 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
261 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
262 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
263 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
264 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
265 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
266 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
267 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
268 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
269 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
270 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
271 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
272 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
273 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
274 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
275 EVEX_W_0F3A72_P_2): Rename to ...
276 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
277 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
278 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
279 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
280 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
281 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
282 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
283 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
284 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
285 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
286 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
287 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
288 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
289 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
290 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
291 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
292 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
293 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
294 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
295 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
296 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
297 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
298 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
299 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
300 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
301 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
302 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
303 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
304 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
305 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
306 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
307 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
308 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
309 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
310 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
311 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
312 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
313 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
314 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
315 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
316 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
317 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
318 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
319 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
320 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
321 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
322 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
323 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
324 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
325 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
326 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
327 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
328 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
329 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
330 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
331 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
332 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
333 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
334 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
335 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
336 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
337 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
338 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
339 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
340 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
341 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
342 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
343 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
344 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
345 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
346 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
347 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
348 respectively.
349 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
350 vex_w_table, mod_table): Replace / remove respective entries.
351 (print_insn): Move up dp->prefix_requirement handling. Handle
352 PREFIX_DATA.
353 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
354 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
355 Replace / remove respective entries.
356
17d3c7ec
JB		 3572020-07-14 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
360 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
361 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
362 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
363 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
364 the latter two.
365 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
366 0F2C, 0F2D, 0F2E, and 0F2F.
367 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
368 0F2F table entries.
369
41f5efc6
JB		 3702020-07-14 Jan Beulich <jbeulich@suse.com>
371
372 * i386-dis.c (OP_VexR, VexScalarR): New.
373 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
374 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
375 need_vex_reg): Delete.
376 (prefix_table): Replace VexScalar by VexScalarR and
377 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
378 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
379 (vex_len_table): Replace EXqVexScalarS by EXqS.
380 (get_valid_dis386): Don't set need_vex_reg.
381 (print_insn): Don't initialize need_vex_reg.
382 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
383 q_scalar_swap_mode cases.
384 (OP_EX): Don't check for d_scalar_swap_mode and
385 q_scalar_swap_mode.
386 (OP_VEX): Done check need_vex_reg.
387 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
388 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
389 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
390
89e65d17
JB		 3912020-07-14 Jan Beulich <jbeulich@suse.com>
392
393 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
394 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
395 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
396 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
397 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
398 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
399 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
400 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
401 (vex_table): Replace Vex128 by Vex.
402 (vex_len_table): Likewise. Adjust referenced enum names.
403 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
404 referenced enum names.
405 (OP_VEX): Drop vex128_mode and vex256_mode cases.
406 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
407
492a76aa
JB		 4082020-07-14 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (dis386): "LW" description now applies to "DQ".
411 (putop): Handle "DQ". Don't handle "LW" anymore.
412 (prefix_table, mod_table): Replace %LW by %DQ.
413 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
414
059edf8b
JB		 4152020-07-14 Jan Beulich <jbeulich@suse.com>
416
417 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
418 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
419 d_scalar_swap_mode case handling. Move shift adjsutment into
420 the case its applicable to.
421
4726e9a4
JB		 4222020-07-14 Jan Beulich <jbeulich@suse.com>
423
424 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
425 (EXbScalar, EXwScalar): Fold to ...
426 (EXbwUnit): ... this.
427 (b_scalar_mode, w_scalar_mode): Fold to ...
428 (bw_unit_mode): ... this.
429 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
430 w_scalar_mode handling by bw_unit_mode one.
431 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
432 ...
433 * i386-dis-evex-prefix.h: ... here.
434
b24d668c
JB		 4352020-07-14 Jan Beulich <jbeulich@suse.com>
436
437 * i386-dis.c (PCMPESTR_Fixup): Delete.
438 (dis386): Adjust "LQ" description.
439 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
440 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
441 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
442 vpcmpestrm, and vpcmpestri.
443 (putop): Honor "cond" when handling LQ.
444 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
445 vcvtsi2ss and vcvtusi2ss.
446 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
447 vcvtsi2sd and vcvtusi2sd.
448
c4de7606
JB		 4492020-07-14 Jan Beulich <jbeulich@suse.com>
450
451 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
452 (simd_cmp_op): Add const.
453 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
454 (CMP_Fixup): Handle VEX case.
455 (prefix_table): Replace VCMP by CMP.
456 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
457
9ab00b61
JB		 4582020-07-14 Jan Beulich <jbeulich@suse.com>
459
460 * i386-dis.c (MOVBE_Fixup): Delete.
461 (Mv): Define.
462 (prefix_table): Use Mv for movbe entries.
463
2875b28a
JB		 4642020-07-14 Jan Beulich <jbeulich@suse.com>
465
466 * i386-dis.c (CRC32_Fixup): Delete.
467 (prefix_table): Use Eb/Ev for crc32 entries.
468
e184e611
JB		 4692020-07-14 Jan Beulich <jbeulich@suse.com>
470
471 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
472 Conditionalize invocations of "USED_REX (0)".
473
e8b5d5f9
JB		 4742020-07-14 Jan Beulich <jbeulich@suse.com>
475
476 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
477 CH, DH, BH, AX, DX): Delete.
478 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
479 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
480 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
481
260cd341
LC		 4822020-07-10 Lili Cui <lili.cui@intel.com>
483
484 * i386-dis.c (TMM): New.
485 (EXtmm): Likewise.
486 (VexTmm): Likewise.
487 (MVexSIBMEM): Likewise.
488 (tmm_mode): Likewise.
489 (vex_sibmem_mode): Likewise.
490 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
491 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
492 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
493 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
494 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
495 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
496 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
497 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
498 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
499 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
500 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
501 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
502 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
503 (PREFIX_VEX_0F3849_X86_64): Likewise.
504 (PREFIX_VEX_0F384B_X86_64): Likewise.
505 (PREFIX_VEX_0F385C_X86_64): Likewise.
506 (PREFIX_VEX_0F385E_X86_64): Likewise.
507 (X86_64_VEX_0F3849): Likewise.
508 (X86_64_VEX_0F384B): Likewise.
509 (X86_64_VEX_0F385C): Likewise.
510 (X86_64_VEX_0F385E): Likewise.
511 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
512 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
513 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
514 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
515 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
516 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
517 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
518 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
519 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
520 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
521 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
522 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
523 (VEX_W_0F3849_X86_64_P_0): Likewise.
524 (VEX_W_0F3849_X86_64_P_2): Likewise.
525 (VEX_W_0F3849_X86_64_P_3): Likewise.
526 (VEX_W_0F384B_X86_64_P_1): Likewise.
527 (VEX_W_0F384B_X86_64_P_2): Likewise.
528 (VEX_W_0F384B_X86_64_P_3): Likewise.
529 (VEX_W_0F385C_X86_64_P_1): Likewise.
530 (VEX_W_0F385E_X86_64_P_0): Likewise.
531 (VEX_W_0F385E_X86_64_P_1): Likewise.
532 (VEX_W_0F385E_X86_64_P_2): Likewise.
533 (VEX_W_0F385E_X86_64_P_3): Likewise.
534 (names_tmm): Likewise.
535 (att_names_tmm): Likewise.
536 (intel_operand_size): Handle void_mode.
537 (OP_XMM): Handle tmm_mode.
538 (OP_EX): Likewise.
539 (OP_VEX): Likewise.
540 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
541 CpuAMX_BF16 and CpuAMX_TILE.
542 (operand_type_shorthands): Add RegTMM.
543 (operand_type_init): Likewise.
544 (operand_types): Add Tmmword.
545 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
546 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
547 * i386-opc.h (CpuAMX_INT8): New.
548 (CpuAMX_BF16): Likewise.
549 (CpuAMX_TILE): Likewise.
550 (SIBMEM): Likewise.
551 (Tmmword): Likewise.
552 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
553 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
554 (i386_operand_type): Add tmmword.
555 * i386-opc.tbl: Add AMX instructions.
556 * i386-reg.tbl: Add AMX registers.
557 * i386-init.h: Regenerated.
558 * i386-tbl.h: Likewise.
559
467bbef0
JB		 5602020-07-08 Jan Beulich <jbeulich@suse.com>
561
562 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
563 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
564 Rename to ...
565 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
566 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
567 respectively.
568 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
569 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
570 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
571 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
572 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
573 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
574 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
575 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
576 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
577 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
578 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
579 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
580 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
581 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
582 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
583 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
584 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
585 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
586 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
587 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
588 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
589 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
590 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
591 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
592 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
593 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
594 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
595 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
596 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
597 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
598 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
599 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
600 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
601 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
602 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
603 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
604 (reg_table): Re-order XOP entries. Adjust their operands.
605 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
606 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
607 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
608 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
609 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
610 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
611 entries by references ...
612 (vex_len_table): ... to resepctive new entries here. For several
613 new and existing entries reference ...
614 (vex_w_table): ... new entries here.
615 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
616
6384fd9e
JB		 6172020-07-08 Jan Beulich <jbeulich@suse.com>
618
619 * i386-dis.c (XMVexScalarI4): Define.
620 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
621 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
622 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
623 (vex_len_table): Move scalar FMA4 entries ...
624 (prefix_table): ... here.
625 (OP_REG_VexI4): Handle scalar_mode.
626 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
627 * i386-tbl.h: Re-generate.
628
e6123d0c
JB		 6292020-07-08 Jan Beulich <jbeulich@suse.com>
630
631 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
632 Vex_2src_2): Delete.
633 (OP_VexW, VexW): New.
634 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
635 for shifts and rotates by register.
636
93abb146
JB		 6372020-07-08 Jan Beulich <jbeulich@suse.com>
638
639 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
640 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
641 OP_EX_VexReg): Delete.
642 (OP_VexI4, VexI4): New.
643 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
644 (prefix_table): ... here.
645 (print_insn): Drop setting of vex_w_done.
646
b13b1bc0
JB		 6472020-07-08 Jan Beulich <jbeulich@suse.com>
648
649 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
650 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
651 (xop_table): Replace operands of 4-operand insns.
652 (OP_REG_VexI4): Move VEX.W based operand swaping here.
653
f337259f
CZ		 6542020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
655
656 * arc-opc.c (insert_rbd): New function.
657 (RBD): Define.
658 (RBDdup): Likewise.
659 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
660 instructions.
661
931452b6
JB		 6622020-07-07 Jan Beulich <jbeulich@suse.com>
663
664 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
665 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
666 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
667 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
668 Delete.
669 (putop): Handle "BW".
670 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
671 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
672 and 0F3A3F ...
673 * i386-dis-evex-prefix.h: ... here.
674
b5b098c2
JB		 6752020-07-06 Jan Beulich <jbeulich@suse.com>
676
677 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
678 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
679 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
680 VEX_W_0FXOP_09_83): New enumerators.
681 (xop_table): Reference the above.
682 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
683 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
684 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
685 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
686
21a3faeb
JB		 6872020-07-06 Jan Beulich <jbeulich@suse.com>
688
689 * i386-dis.c (EVEX_W_0F3838_P_1,
690 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
691 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
692 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
693 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
694 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
695 (putop): Centralize management of last[]. Delete SAVE_LAST.
696 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
697 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
698 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
699 * i386-dis-evex-prefix.h: here.
700
bc152a17
JB		 7012020-07-06 Jan Beulich <jbeulich@suse.com>
702
703 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
704 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
705 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
706 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
707 enumerators.
708 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
709 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
710 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
711 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
712 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
713 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
714 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
715 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
716 these, respectively.
717 * i386-dis-evex-len.h: Adjust comments.
718 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
719 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
720 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
721 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
722 MOD_EVEX_0F385B_P_2_W_1 table entries.
723 * i386-dis-evex-w.h: Reference mod_table[] for
724 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
725 EVEX_W_0F385B_P_2.
726
c82a99a0
JB		 7272020-07-06 Jan Beulich <jbeulich@suse.com>
728
729 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
730 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
731 EXymm.
732 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
733 Likewise. Mark 256-bit entries invalid.
734
fedfb81e
JB		 7352020-07-06 Jan Beulich <jbeulich@suse.com>
736
737 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
738 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
739 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
740 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
741 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
742 PREFIX_EVEX_0F382B): Delete.
743 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
744 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
745 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
746 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
747 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
748 to ...
749 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
750 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
751 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
752 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
753 respectively.
754 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
755 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
756 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
757 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
758 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
759 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
760 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
761 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
762 PREFIX_EVEX_0F382B): Remove table entries.
763 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
764 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
765 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
766
3a57774c
JB		 7672020-07-06 Jan Beulich <jbeulich@suse.com>
768
769 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
770 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
771 enumerators.
772 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
773 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
774 EVEX_LEN_0F3A01_P_2_W_1 table entries.
775 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
776 entries.
777
e74d9fa9
JB		 7782020-07-06 Jan Beulich <jbeulich@suse.com>
779
780 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
781 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
782 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
783 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
784 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
785 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
786 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
787 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
788 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
789 entries.
790
6431c801
JB		 7912020-07-06 Jan Beulich <jbeulich@suse.com>
792
793 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
794 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
795 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
796 respectively.
797 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
798 entries.
799 * i386-dis-evex.h (evex_table): Reference VEX table entry for
800 opcode 0F3A1D.
801 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
802 entry.
803 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
804
6df22cf6
JB		 8052020-07-06 Jan Beulich <jbeulich@suse.com>
806
807 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
808 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
809 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
810 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
811 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
812 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
813 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
814 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
815 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
816 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
817 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
818 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
819 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
820 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
821 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
822 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
823 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
824 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
825 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
826 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
827 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
828 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
829 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
830 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
831 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
832 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
833 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
834 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
835 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
836 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
837 (prefix_table): Add EXxEVexR to FMA table entries.
838 (OP_Rounding): Move abort() invocation.
839 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
840 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
841 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
842 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
843 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
844 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
845 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
846 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
847 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
848 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
849 0F3ACE, 0F3ACF.
850 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
851 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
852 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
853 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
854 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
855 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
856 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
857 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
858 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
859 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
860 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
861 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
862 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
863 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
864 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
865 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
866 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
867 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
868 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
869 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
870 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
871 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
872 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
873 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
874 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
875 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
876 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
877 Delete table entries.
878 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
879 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
880 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
881 Likewise.
882
39e0f456
JB		 8832020-07-06 Jan Beulich <jbeulich@suse.com>
884
885 * i386-dis.c (EXqScalarS): Delete.
886 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
887 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
888
5b872f7d
JB		 8892020-07-06 Jan Beulich <jbeulich@suse.com>
890
891 * i386-dis.c (safe-ctype.h): Include.
892 (EXdScalar, EXqScalar): Delete.
893 (d_scalar_mode, q_scalar_mode): Delete.
894 (prefix_table, vex_len_table): Use EXxmm_md in place of
895 EXdScalar and EXxmm_mq in place of EXqScalar.
896 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
897 d_scalar_mode and q_scalar_mode.
898 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
899 (vmovsd): Use EXxmm_mq.
900
ddc73fa9
NC		 9012020-07-06 Yuri Chornoivan <yurchor@ukr.net>
902
903 PR 26204
904 * arc-dis.c: Fix spelling mistake.
905 * po/opcodes.pot: Regenerate.
906
17550be7
NC		 9072020-07-06 Nick Clifton <nickc@redhat.com>
908
909 * po/pt_BR.po: Updated Brazilian Portugugese translation.
910 * po/uk.po: Updated Ukranian translation.
911
b19d852d
NC		 9122020-07-04 Nick Clifton <nickc@redhat.com>
913
914 * configure: Regenerate.
915 * po/opcodes.pot: Regenerate.
916
b115b9fd
NC		 9172020-07-04 Nick Clifton <nickc@redhat.com>
918
919 Binutils 2.35 branch created.
920
c2ecccb3
L		 9212020-07-02 H.J. Lu <hongjiu.lu@intel.com>
922
923 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
924 * i386-opc.h (VexSwapSources): New.
925 (i386_opcode_modifier): Add vexswapsources.
926 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
927 with two source operands swapped.
928 * i386-tbl.h: Regenerated.
929
08ccfccf
NC		 9302020-06-30 Nelson Chu <nelson.chu@sifive.com>
931
932 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
933 unprivileged CSR can also be initialized.
934
279edac5
AM		 9352020-06-29 Alan Modra <amodra@gmail.com>
936
937 * arm-dis.c: Use C style comments.
938 * cr16-opc.c: Likewise.
939 * ft32-dis.c: Likewise.
940 * moxie-opc.c: Likewise.
941 * tic54x-dis.c: Likewise.
942 * s12z-opc.c: Remove useless comment.
943 * xgate-dis.c: Likewise.
944
e978ad62
L		 9452020-06-26 H.J. Lu <hongjiu.lu@intel.com>
946
947 * i386-opc.tbl: Add a blank line.
948
63112cd6
L		 9492020-06-26 H.J. Lu <hongjiu.lu@intel.com>
950
951 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
952 (VecSIB128): Renamed to ...
953 (VECSIB128): This.
954 (VecSIB256): Renamed to ...
955 (VECSIB256): This.
956 (VecSIB512): Renamed to ...
957 (VECSIB512): This.
958 (VecSIB): Renamed to ...
959 (SIB): This.
960 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 961 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 962 (VecSIB256): Likewise.
963 (VecSIB512): Likewise.
79b32e73 964 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 965 and VecSIB512, respectively.
966
d1c36125
JB		 9672020-06-26 Jan Beulich <jbeulich@suse.com>
968
969 * i386-dis.c: Adjust description of I macro.
970 (x86_64_table): Drop use of I.
971 (float_mem): Replace use of I.
972 (putop): Remove handling of I. Adjust setting/clearing of "alt".
973
2a1bb84c
JB		 9742020-06-26 Jan Beulich <jbeulich@suse.com>
975
976 * i386-dis.c: (print_insn): Avoid straight assignment to
977 priv.orig_sizeflag when processing -M sub-options.
978
8f570d62
JB		 9792020-06-25 Jan Beulich <jbeulich@suse.com>
980
981 * i386-dis.c: Adjust description of J macro.
982 (dis386, x86_64_table, mod_table): Replace J.
983 (putop): Remove handling of J.
984
464dc4af
JB		 9852020-06-25 Jan Beulich <jbeulich@suse.com>
986
987 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
988
589958d6
JB		 9892020-06-25 Jan Beulich <jbeulich@suse.com>
990
991 * i386-dis.c: Adjust description of "LQ" macro.
992 (dis386_twobyte): Use LQ for sysret.
993 (putop): Adjust handling of LQ.
994
39ff0b81
NC		 9952020-06-22 Nelson Chu <nelson.chu@sifive.com>
996
997 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
998 * riscv-dis.c: Include elfxx-riscv.h.
999
d27c357a
JB		 10002020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1001
1002 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1003
6fde587f
CL		 10042020-06-17 Lili Cui <lili.cui@intel.com>
1005
1006 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1007
efe30057
L		 10082020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1009
1010 PR gas/26115
1011 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1012 * i386-opc.tbl: Likewise.
1013 * i386-tbl.h: Regenerated.
1014
d8af286f
NC		 10152020-06-12 Nelson Chu <nelson.chu@sifive.com>
1016
1017 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1018
14962256
AC		 10192020-06-11 Alex Coplan <alex.coplan@arm.com>
1020
1021 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1022 (SR_CORE): Likewise.
1023 (SR_FEAT): Likewise.
1024 (SR_RNG): Likewise.
1025 (SR_V8_1): Likewise.
1026 (SR_V8_2): Likewise.
1027 (SR_V8_3): Likewise.
1028 (SR_V8_4): Likewise.
1029 (SR_PAN): Likewise.
1030 (SR_RAS): Likewise.
1031 (SR_SSBS): Likewise.
1032 (SR_SVE): Likewise.
1033 (SR_ID_PFR2): Likewise.
1034 (SR_PROFILE): Likewise.
1035 (SR_MEMTAG): Likewise.
1036 (SR_SCXTNUM): Likewise.
1037 (aarch64_sys_regs): Refactor to store feature information in the table.
1038 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1039 that now describe their own features.
1040 (aarch64_pstatefield_supported_p): Likewise.
1041
f9630fa6
L		 10422020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1043
1044 * i386-dis.c (prefix_table): Fix a typo in comments.
1045
73239888
JB		 10462020-06-09 Jan Beulich <jbeulich@suse.com>
1047
1048 * i386-dis.c (rex_ignored): Delete.
1049 (ckprefix): Drop rex_ignored initialization.
1050 (get_valid_dis386): Drop setting of rex_ignored.
1051 (print_insn): Drop checking of rex_ignored. Don't record data
1052 size prefix as used with VEX-and-alike encodings.
1053
18897deb
JB		 10542020-06-09 Jan Beulich <jbeulich@suse.com>
1055
1056 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1057 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1058 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1059 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1060 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1061 VEX_0F12, and VEX_0F16.
1062 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1063 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1064 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1065 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1066 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1067 MOD_VEX_0F16_PREFIX_2 entries.
1068
97e6786a
JB		 10692020-06-09 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1072 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1073 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1074 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1075 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1076 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1077 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1078 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1079 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1080 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1081 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1082 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1083 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1084 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1085 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1086 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1087 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1088 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1089 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1090 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1091 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1092 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1093 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1094 EVEX_W_0FC6_P_2): Delete.
1095 (print_insn): Add EVEX.W vs embedded prefix consistency check
1096 to prefix validation.
1097 * i386-dis-evex.h (evex_table): Don't further descend for
1098 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1099 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1100 and 0F2B.
1101 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1102 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1103 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1104 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1105 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1106 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1107 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1108 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1109 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1110 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1111 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1112 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1113 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1114 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1115 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1116 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1117 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1118 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1119 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1120 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1121 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1122 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1123 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1124 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1125 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1126 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1127 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1128
bf926894
JB		 11292020-06-09 Jan Beulich <jbeulich@suse.com>
1130
1131 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1132 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1133 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1134 vmovmskpX.
1135 (print_insn): Drop pointless check against bad_opcode. Split
1136 prefix validation into legacy and VEX-and-alike parts.
1137 (putop): Re-work 'X' macro handling.
1138
a5aaedb9
JB		 11392020-06-09 Jan Beulich <jbeulich@suse.com>
1140
1141 * i386-dis.c (MOD_0F51): Rename to ...
1142 (MOD_0F50): ... this.
1143
26417f19
AC		 11442020-06-08 Alex Coplan <alex.coplan@arm.com>
1145
1146 * arm-dis.c (arm_opcodes): Add dfb.
1147 (thumb32_opcodes): Add dfb.
1148
8a6fb3f9
JB		 11492020-06-08 Jan Beulich <jbeulich@suse.com>
1150
1151 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1152
1424c35d
AM		 11532020-06-06 Alan Modra <amodra@gmail.com>
1154
1155 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1156
d3d1cc7b
AM		 11572020-06-05 Alan Modra <amodra@gmail.com>
1158
1159 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1160 size is large enough.
1161
d8740be1
JM		 11622020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1163
1164 * disassemble.c (disassemble_init_for_target): Set endian_code for
1165 bpf targets.
1166 * bpf-desc.c: Regenerate.
1167 * bpf-opc.c: Likewise.
1168 * bpf-dis.c: Likewise.
1169
e9bffec9
JM		 11702020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1171
1172 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1173 (cgen_put_insn_value): Likewise.
1174 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1175 * cgen-dis.in (print_insn): Likewise.
1176 * cgen-ibld.in (insert_1): Likewise.
1177 (insert_1): Likewise.
1178 (insert_insn_normal): Likewise.
1179 (extract_1): Likewise.
1180 * bpf-dis.c: Regenerate.
1181 * bpf-ibld.c: Likewise.
1182 * bpf-ibld.c: Likewise.
1183 * cgen-dis.in: Likewise.
1184 * cgen-ibld.in: Likewise.
1185 * cgen-opc.c: Likewise.
1186 * epiphany-dis.c: Likewise.
1187 * epiphany-ibld.c: Likewise.
1188 * fr30-dis.c: Likewise.
1189 * fr30-ibld.c: Likewise.
1190 * frv-dis.c: Likewise.
1191 * frv-ibld.c: Likewise.
1192 * ip2k-dis.c: Likewise.
1193 * ip2k-ibld.c: Likewise.
1194 * iq2000-dis.c: Likewise.
1195 * iq2000-ibld.c: Likewise.
1196 * lm32-dis.c: Likewise.
1197 * lm32-ibld.c: Likewise.
1198 * m32c-dis.c: Likewise.
1199 * m32c-ibld.c: Likewise.
1200 * m32r-dis.c: Likewise.
1201 * m32r-ibld.c: Likewise.
1202 * mep-dis.c: Likewise.
1203 * mep-ibld.c: Likewise.
1204 * mt-dis.c: Likewise.
1205 * mt-ibld.c: Likewise.
1206 * or1k-dis.c: Likewise.
1207 * or1k-ibld.c: Likewise.
1208 * xc16x-dis.c: Likewise.
1209 * xc16x-ibld.c: Likewise.
1210 * xstormy16-dis.c: Likewise.
1211 * xstormy16-ibld.c: Likewise.
1212
b3db6d07
JM		 12132020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1214
1215 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1216 (print_insn_): Handle instruction endian.
1217 * bpf-dis.c: Regenerate.
1218 * bpf-desc.c: Regenerate.
1219 * epiphany-dis.c: Likewise.
1220 * epiphany-desc.c: Likewise.
1221 * fr30-dis.c: Likewise.
1222 * fr30-desc.c: Likewise.
1223 * frv-dis.c: Likewise.
1224 * frv-desc.c: Likewise.
1225 * ip2k-dis.c: Likewise.
1226 * ip2k-desc.c: Likewise.
1227 * iq2000-dis.c: Likewise.
1228 * iq2000-desc.c: Likewise.
1229 * lm32-dis.c: Likewise.
1230 * lm32-desc.c: Likewise.
1231 * m32c-dis.c: Likewise.
1232 * m32c-desc.c: Likewise.
1233 * m32r-dis.c: Likewise.
1234 * m32r-desc.c: Likewise.
1235 * mep-dis.c: Likewise.
1236 * mep-desc.c: Likewise.
1237 * mt-dis.c: Likewise.
1238 * mt-desc.c: Likewise.
1239 * or1k-dis.c: Likewise.
1240 * or1k-desc.c: Likewise.
1241 * xc16x-dis.c: Likewise.
1242 * xc16x-desc.c: Likewise.
1243 * xstormy16-dis.c: Likewise.
1244 * xstormy16-desc.c: Likewise.
1245
4ee4189f
NC		 12462020-06-03 Nick Clifton <nickc@redhat.com>
1247
1248 * po/sr.po: Updated Serbian translation.
1249
44730156
NC		 12502020-06-03 Nelson Chu <nelson.chu@sifive.com>
1251
1252 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1253 (riscv_get_priv_spec_class): Likewise.
1254
3c3d0376
AM		 12552020-06-01 Alan Modra <amodra@gmail.com>
1256
1257 * bpf-desc.c: Regenerate.
1258
78c1c354
JM		 12592020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1260 David Faust <david.faust@oracle.com>
1261
1262 * bpf-desc.c: Regenerate.
1263 * bpf-opc.h: Likewise.
1264 * bpf-opc.c: Likewise.
1265 * bpf-dis.c: Likewise.
1266
efcf5fb5
AM		 12672020-05-28 Alan Modra <amodra@gmail.com>
1268
1269 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1270 values.
1271
ab382d64
AM		 12722020-05-28 Alan Modra <amodra@gmail.com>
1273
1274 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1275 immediates.
1276 (print_insn_ns32k): Revert last change.
1277
151f5de4
NC		 12782020-05-28 Nick Clifton <nickc@redhat.com>
1279
1280 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1281 static.
1282
25e1eca8
SL		 12832020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1284
1285 Fix extraction of signed constants in nios2 disassembler (again).
1286
1287 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1288 extractions of signed fields.
1289
57b17940
SSF		 12902020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1291
1292 * s390-opc.txt: Relocate vector load/store instructions with
1293 additional alignment parameter and change architecture level
1294 constraint from z14 to z13.
1295
d96bf37b
AM		 12962020-05-21 Alan Modra <amodra@gmail.com>
1297
1298 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1299 * sparc-dis.c: Likewise.
1300 * tic4x-dis.c: Likewise.
1301 * xtensa-dis.c: Likewise.
1302 * bpf-desc.c: Regenerate.
1303 * epiphany-desc.c: Regenerate.
1304 * fr30-desc.c: Regenerate.
1305 * frv-desc.c: Regenerate.
1306 * ip2k-desc.c: Regenerate.
1307 * iq2000-desc.c: Regenerate.
1308 * lm32-desc.c: Regenerate.
1309 * m32c-desc.c: Regenerate.
1310 * m32r-desc.c: Regenerate.
1311 * mep-asm.c: Regenerate.
1312 * mep-desc.c: Regenerate.
1313 * mt-desc.c: Regenerate.
1314 * or1k-desc.c: Regenerate.
1315 * xc16x-desc.c: Regenerate.
1316 * xstormy16-desc.c: Regenerate.
1317
8f595e9b
NC		 13182020-05-20 Nelson Chu <nelson.chu@sifive.com>
1319
1320 * riscv-opc.c (riscv_ext_version_table): The table used to store
1321 all information about the supported spec and the corresponding ISA
1322 versions. Currently, only Zicsr is supported to verify the
1323 correctness of Z sub extension settings. Others will be supported
1324 in the future patches.
1325 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1326 classes and the corresponding strings.
1327 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1328 spec class by giving a ISA spec string.
1329 * riscv-opc.c (struct priv_spec_t): New structure.
1330 (struct priv_spec_t priv_specs): List for all supported privilege spec
1331 classes and the corresponding strings.
1332 (riscv_get_priv_spec_class): New function. Get the corresponding
1333 privilege spec class by giving a spec string.
1334 (riscv_get_priv_spec_name): New function. Get the corresponding
1335 privilege spec string by giving a CSR version class.
1336 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1337 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1338 according to the chosen version. Build a hash table riscv_csr_hash to
1339 store the valid CSR for the chosen pirv verison. Dump the direct
1340 CSR address rather than it's name if it is invalid.
1341 (parse_riscv_dis_option_without_args): New function. Parse the options
1342 without arguments.
1343 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1344 parse the options without arguments first, and then handle the options
1345 with arguments. Add the new option -Mpriv-spec, which has argument.
1346 * riscv-dis.c (print_riscv_disassembler_options): Add description
1347 about the new OBJDUMP option.
1348
3d205eb4
PB		 13492020-05-19 Peter Bergner <bergner@linux.ibm.com>
1350
1351 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1352 WC values on POWER10 sync, dcbf and wait instructions.
1353 (insert_pl, extract_pl): New functions.
1354 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1355 (LS3): New , 3-bit L for sync.
1356 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1357 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1358 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1359 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1360 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1361 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1362 <wait>: Enable PL operand on POWER10.
1363 <dcbf>: Enable L3OPT operand on POWER10.
1364 <sync>: Enable SC2 operand on POWER10.
1365
a501eb44
SH		 13662020-05-19 Stafford Horne <shorne@gmail.com>
1367
1368 PR 25184
1369 * or1k-asm.c: Regenerate.
1370 * or1k-desc.c: Regenerate.
1371 * or1k-desc.h: Regenerate.
1372 * or1k-dis.c: Regenerate.
1373 * or1k-ibld.c: Regenerate.
1374 * or1k-opc.c: Regenerate.
1375 * or1k-opc.h: Regenerate.
1376 * or1k-opinst.c: Regenerate.
1377
3b646889
AM		 13782020-05-11 Alan Modra <amodra@gmail.com>
1379
1380 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1381 xsmaxcqp, xsmincqp.
1382
9cc4ce88
AM		 13832020-05-11 Alan Modra <amodra@gmail.com>
1384
1385 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1386 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1387
5d57bc3f
AM		 13882020-05-11 Alan Modra <amodra@gmail.com>
1389
1390 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1391
66ef5847
AM		 13922020-05-11 Alan Modra <amodra@gmail.com>
1393
1394 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1395 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1396
4f3e9537
PB		 13972020-05-11 Peter Bergner <bergner@linux.ibm.com>
1398
1399 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1400 mnemonics.
1401
ec40e91c
AM		 14022020-05-11 Alan Modra <amodra@gmail.com>
1403
1404 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1405 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1406 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1407 (prefix_opcodes): Add xxeval.
1408
d7e97a76
AM		 14092020-05-11 Alan Modra <amodra@gmail.com>
1410
1411 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1412 xxgenpcvwm, xxgenpcvdm.
1413
fdefed7c
AM		 14142020-05-11 Alan Modra <amodra@gmail.com>
1415
1416 * ppc-opc.c (MP, VXVAM_MASK): Define.
1417 (VXVAPS_MASK): Use VXVA_MASK.
1418 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1419 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1420 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1421 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1422
aa3c112f
AM		 14232020-05-11 Alan Modra <amodra@gmail.com>
1424 Peter Bergner <bergner@linux.ibm.com>
1425
1426 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1427 New functions.
1428 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1429 YMSK2, XA6a, XA6ap, XB6a entries.
1430 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1431 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1432 (PPCVSX4): Define.
1433 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1434 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1435 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1436 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1437 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1438 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1439 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1440 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1441 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1442 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1443 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1444 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1445 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1446 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1447
6edbfd3b
AM		 14482020-05-11 Alan Modra <amodra@gmail.com>
1449
1450 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1451 (insert_xts, extract_xts): New functions.
1452 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1453 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1454 (VXRC_MASK, VXSH_MASK): Define.
1455 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1456 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1457 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1458 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1459 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1460 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1461 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1462
c7d7aea2
AM		 14632020-05-11 Alan Modra <amodra@gmail.com>
1464
1465 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1466 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1467 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1468 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1469 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1470
94ba9882
AM		 14712020-05-11 Alan Modra <amodra@gmail.com>
1472
1473 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1474 (XTP, DQXP, DQXP_MASK): Define.
1475 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1476 (prefix_opcodes): Add plxvp and pstxvp.
1477
f4791f1a
AM		 14782020-05-11 Alan Modra <amodra@gmail.com>
1479
1480 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1481 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1482 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1483
3ff0a5ba
PB		 14842020-05-11 Peter Bergner <bergner@linux.ibm.com>
1485
1486 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1487
afef4fe9
PB		 14882020-05-11 Peter Bergner <bergner@linux.ibm.com>
1489
1490 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1491 (L1OPT): Define.
1492 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1493
1224c05d
PB		 14942020-05-11 Peter Bergner <bergner@linux.ibm.com>
1495
1496 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1497
6bbb0c05
AM		 14982020-05-11 Alan Modra <amodra@gmail.com>
1499
1500 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1501
7c1f4227
AM		 15022020-05-11 Alan Modra <amodra@gmail.com>
1503
1504 * ppc-dis.c (ppc_opts): Add "power10" entry.
1505 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1506 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1507
73199c2b
NC		 15082020-05-11 Nick Clifton <nickc@redhat.com>
1509
1510 * po/fr.po: Updated French translation.
1511
09c1e68a
AC		 15122020-04-30 Alex Coplan <alex.coplan@arm.com>
1513
1514 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1515 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1516 (operand_general_constraint_met_p): validate
1517 AARCH64_OPND_UNDEFINED.
1518 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1519 for FLD_imm16_2.
1520 * aarch64-asm-2.c: Regenerated.
1521 * aarch64-dis-2.c: Regenerated.
1522 * aarch64-opc-2.c: Regenerated.
1523
9654d51a
NC		 15242020-04-29 Nick Clifton <nickc@redhat.com>
1525
1526 PR 22699
1527 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1528 and SETRC insns.
1529
c2e71e57
NC		 15302020-04-29 Nick Clifton <nickc@redhat.com>
1531
1532 * po/sv.po: Updated Swedish translation.
1533
5c936ef5
NC		 15342020-04-29 Nick Clifton <nickc@redhat.com>
1535
1536 PR 22699
1537 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1538 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1539 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1540 IMM0_8U case.
1541
bb2a1453
AS		 15422020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1543
1544 PR 25848
1545 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1546 cmpi only on m68020up and cpu32.
1547
c2e5c986
SD		 15482020-04-20 Sudakshina Das <sudi.das@arm.com>
1549
1550 * aarch64-asm.c (aarch64_ins_none): New.
1551 * aarch64-asm.h (ins_none): New declaration.
1552 * aarch64-dis.c (aarch64_ext_none): New.
1553 * aarch64-dis.h (ext_none): New declaration.
1554 * aarch64-opc.c (aarch64_print_operand): Update case for
1555 AARCH64_OPND_BARRIER_PSB.
1556 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1557 (AARCH64_OPERANDS): Update inserter/extracter for
1558 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1559 * aarch64-asm-2.c: Regenerated.
1560 * aarch64-dis-2.c: Regenerated.
1561 * aarch64-opc-2.c: Regenerated.
1562
8a6e1d1d
SD		 15632020-04-20 Sudakshina Das <sudi.das@arm.com>
1564
1565 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1566 (aarch64_feature_ras, RAS): Likewise.
1567 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1568 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1569 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1570 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1571 * aarch64-asm-2.c: Regenerated.
1572 * aarch64-dis-2.c: Regenerated.
1573 * aarch64-opc-2.c: Regenerated.
1574
e409955d
FS		 15752020-04-17 Fredrik Strupe <fredrik@strupe.net>
1576
1577 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1578 (print_insn_neon): Support disassembly of conditional
1579 instructions.
1580
c54a9b56
DF		 15812020-02-16 David Faust <david.faust@oracle.com>
1582
1583 * bpf-desc.c: Regenerate.
1584 * bpf-desc.h: Likewise.
1585 * bpf-opc.c: Regenerate.
1586 * bpf-opc.h: Likewise.
1587
bb651e8b
CL		 15882020-04-07 Lili Cui <lili.cui@intel.com>
1589
1590 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1591 (prefix_table): New instructions (see prefixes above).
1592 (rm_table): Likewise
1593 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1594 CPU_ANY_TSXLDTRK_FLAGS.
1595 (cpu_flags): Add CpuTSXLDTRK.
1596 * i386-opc.h (enum): Add CpuTSXLDTRK.
1597 (i386_cpu_flags): Add cputsxldtrk.
1598 * i386-opc.tbl: Add XSUSPLDTRK insns.
1599 * i386-init.h: Regenerate.
1600 * i386-tbl.h: Likewise.
1601
4b27d27c
L		 16022020-04-02 Lili Cui <lili.cui@intel.com>
1603
1604 * i386-dis.c (prefix_table): New instructions serialize.
1605 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1606 CPU_ANY_SERIALIZE_FLAGS.
1607 (cpu_flags): Add CpuSERIALIZE.
1608 * i386-opc.h (enum): Add CpuSERIALIZE.
1609 (i386_cpu_flags): Add cpuserialize.
1610 * i386-opc.tbl: Add SERIALIZE insns.
1611 * i386-init.h: Regenerate.
1612 * i386-tbl.h: Likewise.
1613
832a5807
AM		 16142020-03-26 Alan Modra <amodra@gmail.com>
1615
1616 * disassemble.h (opcodes_assert): Declare.
1617 (OPCODES_ASSERT): Define.
1618 * disassemble.c: Don't include assert.h. Include opintl.h.
1619 (opcodes_assert): New function.
1620 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1621 (bfd_h8_disassemble): Reduce size of data array. Correctly
1622 calculate maxlen. Omit insn decoding when insn length exceeds
1623 maxlen. Exit from nibble loop when looking for E, before
1624 accessing next data byte. Move processing of E outside loop.
1625 Replace tests of maxlen in loop with assertions.
1626
4c4addbe
AM		 16272020-03-26 Alan Modra <amodra@gmail.com>
1628
1629 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1630
a18cd0ca
AM		 16312020-03-25 Alan Modra <amodra@gmail.com>
1632
1633 * z80-dis.c (suffix): Init mybuf.
1634
57cb32b3
AM		 16352020-03-22 Alan Modra <amodra@gmail.com>
1636
1637 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1638 successflly read from section.
1639
beea5cc1
AM		 16402020-03-22 Alan Modra <amodra@gmail.com>
1641
1642 * arc-dis.c (find_format): Use ISO C string concatenation rather
1643 than line continuation within a string. Don't access needs_limm
1644 before testing opcode != NULL.
1645
03704c77
AM		 16462020-03-22 Alan Modra <amodra@gmail.com>
1647
1648 * ns32k-dis.c (print_insn_arg): Update comment.
1649 (print_insn_ns32k): Reduce size of index_offset array, and
1650 initialize, passing -1 to print_insn_arg for args that are not
1651 an index. Don't exit arg loop early. Abort on bad arg number.
1652
d1023b5d
AM		 16532020-03-22 Alan Modra <amodra@gmail.com>
1654
1655 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1656 * s12z-opc.c: Formatting.
1657 (operands_f): Return an int.
1658 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1659 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1660 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1661 (exg_sex_discrim): Likewise.
1662 (create_immediate_operand, create_bitfield_operand),
1663 (create_register_operand_with_size, create_register_all_operand),
1664 (create_register_all16_operand, create_simple_memory_operand),
1665 (create_memory_operand, create_memory_auto_operand): Don't
1666 segfault on malloc failure.
1667 (z_ext24_decode): Return an int status, negative on fail, zero
1668 on success.
1669 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1670 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1671 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1672 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1673 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1674 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1675 (loop_primitive_decode, shift_decode, psh_pul_decode),
1676 (bit_field_decode): Similarly.
1677 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1678 to return value, update callers.
1679 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1680 Don't segfault on NULL operand.
1681 (decode_operation): Return OP_INVALID on first fail.
1682 (decode_s12z): Check all reads, returning -1 on fail.
1683
340f3ac8
AM		 16842020-03-20 Alan Modra <amodra@gmail.com>
1685
1686 * metag-dis.c (print_insn_metag): Don't ignore status from
1687 read_memory_func.
1688
fe90ae8a
AM		 16892020-03-20 Alan Modra <amodra@gmail.com>
1690
1691 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1692 Initialize parts of buffer not written when handling a possible
1693 2-byte insn at end of section. Don't attempt decoding of such
1694 an insn by the 4-byte machinery.
1695
833d919c
AM		 16962020-03-20 Alan Modra <amodra@gmail.com>
1697
1698 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1699 partially filled buffer. Prevent lookup of 4-byte insns when
1700 only VLE 2-byte insns are possible due to section size. Print
1701 ".word" rather than ".long" for 2-byte leftovers.
1702
327ef784
NC		 17032020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1704
1705 PR 25641
1706 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1707
1673df32
JB		 17082020-03-13 Jan Beulich <jbeulich@suse.com>
1709
1710 * i386-dis.c (X86_64_0D): Rename to ...
1711 (X86_64_0E): ... this.
1712
384f3689
L		 17132020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1714
1715 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1716 * Makefile.in: Regenerated.
1717
865e2027
JB		 17182020-03-09 Jan Beulich <jbeulich@suse.com>
1719
1720 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1721 3-operand pseudos.
1722 * i386-tbl.h: Re-generate.
1723
2f13234b
JB		 17242020-03-09 Jan Beulich <jbeulich@suse.com>
1725
1726 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1727 vprot*, vpsha*, and vpshl*.
1728 * i386-tbl.h: Re-generate.
1729
3fabc179
JB		 17302020-03-09 Jan Beulich <jbeulich@suse.com>
1731
1732 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1733 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1734 * i386-tbl.h: Re-generate.
1735
3677e4c1
JB		 17362020-03-09 Jan Beulich <jbeulich@suse.com>
1737
1738 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1739 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1740 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1741 * i386-tbl.h: Re-generate.
1742
4c4898e8
JB		 17432020-03-09 Jan Beulich <jbeulich@suse.com>
1744
1745 * i386-gen.c (struct template_arg, struct template_instance,
1746 struct template_param, struct template, templates,
1747 parse_template, expand_templates): New.
1748 (process_i386_opcodes): Various local variables moved to
1749 expand_templates. Call parse_template and expand_templates.
1750 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1751 * i386-tbl.h: Re-generate.
1752
bc49bfd8
JB		 17532020-03-06 Jan Beulich <jbeulich@suse.com>
1754
1755 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1756 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1757 register and memory source templates. Replace VexW= by VexW*
1758 where applicable.
1759 * i386-tbl.h: Re-generate.
1760
4873e243
JB		 17612020-03-06 Jan Beulich <jbeulich@suse.com>
1762
1763 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1764 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1765 * i386-tbl.h: Re-generate.
1766
672a349b
JB		 17672020-03-06 Jan Beulich <jbeulich@suse.com>
1768
1769 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1770 * i386-tbl.h: Re-generate.
1771
4ed21b58
JB		 17722020-03-06 Jan Beulich <jbeulich@suse.com>
1773
1774 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1775 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1776 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1777 VexW0 on SSE2AVX variants.
1778 (vmovq): Drop NoRex64 from XMM/XMM variants.
1779 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1780 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1781 applicable use VexW0.
1782 * i386-tbl.h: Re-generate.
1783
643bb870
JB		 17842020-03-06 Jan Beulich <jbeulich@suse.com>
1785
1786 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1787 * i386-opc.h (Rex64): Delete.
1788 (struct i386_opcode_modifier): Remove rex64 field.
1789 * i386-opc.tbl (crc32): Drop Rex64.
1790 Replace Rex64 with Size64 everywhere else.
1791 * i386-tbl.h: Re-generate.
1792
a23b33b3
JB		 17932020-03-06 Jan Beulich <jbeulich@suse.com>
1794
1795 * i386-dis.c (OP_E_memory): Exclude recording of used address
1796 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1797 addressed memory operands for MPX insns.
1798
a0497384
JB		 17992020-03-06 Jan Beulich <jbeulich@suse.com>
1800
1801 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1802 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1803 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1804 (ptwrite): Split into non-64-bit and 64-bit forms.
1805 * i386-tbl.h: Re-generate.
1806
b630c145
JB		 18072020-03-06 Jan Beulich <jbeulich@suse.com>
1808
1809 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1810 template.
1811 * i386-tbl.h: Re-generate.
1812
a847e322
JB		 18132020-03-04 Jan Beulich <jbeulich@suse.com>
1814
1815 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1816 (prefix_table): Move vmmcall here. Add vmgexit.
1817 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1818 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1819 (cpu_flags): Add CpuSEV_ES entry.
1820 * i386-opc.h (CpuSEV_ES): New.
1821 (union i386_cpu_flags): Add cpusev_es field.
1822 * i386-opc.tbl (vmgexit): New.
1823 * i386-init.h, i386-tbl.h: Re-generate.
1824
3cd7f3e3
L		 18252020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1826
1827 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1828 with MnemonicSize.
1829 * i386-opc.h (IGNORESIZE): New.
1830 (DEFAULTSIZE): Likewise.
1831 (IgnoreSize): Removed.
1832 (DefaultSize): Likewise.
1833 (MnemonicSize): New.
1834 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1835 mnemonicsize.
1836 * i386-opc.tbl (IgnoreSize): New.
1837 (DefaultSize): Likewise.
1838 * i386-tbl.h: Regenerated.
1839
b8ba1385
SB		 18402020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1841
1842 PR 25627
1843 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1844 instructions.
1845
10d97a0f
L		 18462020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1847
1848 PR gas/25622
1849 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1850 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1851 * i386-tbl.h: Regenerated.
1852
dc1e8a47
AM		 18532020-02-26 Alan Modra <amodra@gmail.com>
1854
1855 * aarch64-asm.c: Indent labels correctly.
1856 * aarch64-dis.c: Likewise.
1857 * aarch64-gen.c: Likewise.
1858 * aarch64-opc.c: Likewise.
1859 * alpha-dis.c: Likewise.
1860 * i386-dis.c: Likewise.
1861 * nds32-asm.c: Likewise.
1862 * nfp-dis.c: Likewise.
1863 * visium-dis.c: Likewise.
1864
265b4673
CZ		 18652020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1866
1867 * arc-regs.h (int_vector_base): Make it available for all ARC
1868 CPUs.
1869
bd0cf5a6
NC		 18702020-02-20 Nelson Chu <nelson.chu@sifive.com>
1871
1872 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1873 changed.
1874
fa164239
JW		 18752020-02-19 Nelson Chu <nelson.chu@sifive.com>
1876
1877 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1878 c.mv/c.li if rs1 is zero.
1879
272a84b1
L		 18802020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1881
1882 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1883 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1884 CPU_POPCNT_FLAGS.
1885 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1886 * i386-opc.h (CpuABM): Removed.
1887 (CpuPOPCNT): New.
1888 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1889 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1890 popcnt. Remove CpuABM from lzcnt.
1891 * i386-init.h: Regenerated.
1892 * i386-tbl.h: Likewise.
1893
1f730c46
JB		 18942020-02-17 Jan Beulich <jbeulich@suse.com>
1895
1896 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1897 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1898 VexW1 instead of open-coding them.
1899 * i386-tbl.h: Re-generate.
1900
c8f8eebc
JB		 19012020-02-17 Jan Beulich <jbeulich@suse.com>
1902
1903 * i386-opc.tbl (AddrPrefixOpReg): Define.
1904 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1905 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1906 templates. Drop NoRex64.
1907 * i386-tbl.h: Re-generate.
1908
b9915cbc
JB		 19092020-02-17 Jan Beulich <jbeulich@suse.com>
1910
1911 PR gas/6518
1912 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1913 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1914 into Intel syntax instance (with Unpsecified) and AT&T one
1915 (without).
1916 (vcvtneps2bf16): Likewise, along with folding the two so far
1917 separate ones.
1918 * i386-tbl.h: Re-generate.
1919
ce504911
L		 19202020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1921
1922 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1923 CPU_ANY_SSE4A_FLAGS.
1924
dabec65d
AM		 19252020-02-17 Alan Modra <amodra@gmail.com>
1926
1927 * i386-gen.c (cpu_flag_init): Correct last change.
1928
af5c13b0
L		 19292020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1930
1931 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1932 CPU_ANY_SSE4_FLAGS.
1933
6867aac0
L		 19342020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1935
1936 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1937 (movzx): Likewise.
1938
65fca059
JB		 19392020-02-14 Jan Beulich <jbeulich@suse.com>
1940
1941 PR gas/25438
1942 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1943 destination for Cpu64-only variant.
1944 (movzx): Fold patterns.
1945 * i386-tbl.h: Re-generate.
1946
7deea9aa
JB		 19472020-02-13 Jan Beulich <jbeulich@suse.com>
1948
1949 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1950 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1951 CPU_ANY_SSE4_FLAGS entry.
1952 * i386-init.h: Re-generate.
1953
6c0946d0
JB		 19542020-02-12 Jan Beulich <jbeulich@suse.com>
1955
1956 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1957 with Unspecified, making the present one AT&T syntax only.
1958 * i386-tbl.h: Re-generate.
1959
ddb56fe6
JB		 19602020-02-12 Jan Beulich <jbeulich@suse.com>
1961
1962 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1963 * i386-tbl.h: Re-generate.
1964
5990e377
JB		 19652020-02-12 Jan Beulich <jbeulich@suse.com>
1966
1967 PR gas/24546
1968 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1969 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1970 Amd64 and Intel64 templates.
1971 (call, jmp): Likewise for far indirect variants. Dro
1972 Unspecified.
1973 * i386-tbl.h: Re-generate.
1974
50128d0c
JB		 19752020-02-11 Jan Beulich <jbeulich@suse.com>
1976
1977 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1978 * i386-opc.h (ShortForm): Delete.
1979 (struct i386_opcode_modifier): Remove shortform field.
1980 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1981 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1982 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1983 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1984 Drop ShortForm.
1985 * i386-tbl.h: Re-generate.
1986
1e05b5c4
JB		 19872020-02-11 Jan Beulich <jbeulich@suse.com>
1988
1989 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1990 fucompi): Drop ShortForm from operand-less templates.
1991 * i386-tbl.h: Re-generate.
1992
2f5dd314
AM		 19932020-02-11 Alan Modra <amodra@gmail.com>
1994
1995 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1996 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1997 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1998 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1999 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2000
5aae9ae9
MM		 20012020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2002
2003 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2004 (cde_opcodes): Add VCX* instructions.
2005
4934a27c
MM		 20062020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2007 Matthew Malcomson <matthew.malcomson@arm.com>
2008
2009 * arm-dis.c (struct cdeopcode32): New.
2010 (CDE_OPCODE): New macro.
2011 (cde_opcodes): New disassembly table.
2012 (regnames): New option to table.
2013 (cde_coprocs): New global variable.
2014 (print_insn_cde): New
2015 (print_insn_thumb32): Use print_insn_cde.
2016 (parse_arm_disassembler_options): Parse coprocN args.
2017
4b5aaf5f
L		 20182020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2019
2020 PR gas/25516
2021 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2022 with ISA64.
2023 * i386-opc.h (AMD64): Removed.
2024 (Intel64): Likewose.
2025 (AMD64): New.
2026 (INTEL64): Likewise.
2027 (INTEL64ONLY): Likewise.
2028 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2029 * i386-opc.tbl (Amd64): New.
2030 (Intel64): Likewise.
2031 (Intel64Only): Likewise.
2032 Replace AMD64 with Amd64. Update sysenter/sysenter with
2033 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2034 * i386-tbl.h: Regenerated.
2035
9fc0b501
SB		 20362020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2037
2038 PR 25469
2039 * z80-dis.c: Add support for GBZ80 opcodes.
2040
c5d7be0c
AM		 20412020-02-04 Alan Modra <amodra@gmail.com>
2042
2043 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2044
44e4546f
AM		 20452020-02-03 Alan Modra <amodra@gmail.com>
2046
2047 * m32c-ibld.c: Regenerate.
2048
b2b1453a
AM		 20492020-02-01 Alan Modra <amodra@gmail.com>
2050
2051 * frv-ibld.c: Regenerate.
2052
4102be5c
JB		 20532020-01-31 Jan Beulich <jbeulich@suse.com>
2054
2055 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2056 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2057 (OP_E_memory): Replace xmm_mdq_mode case label by
2058 vex_scalar_w_dq_mode one.
2059 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2060
825bd36c
JB		 20612020-01-31 Jan Beulich <jbeulich@suse.com>
2062
2063 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2064 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2065 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2066 (intel_operand_size): Drop vex_w_dq_mode case label.
2067
c3036ed0
RS		 20682020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2069
2070 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2071 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2072
0c115f84
AM		 20732020-01-30 Alan Modra <amodra@gmail.com>
2074
2075 * m32c-ibld.c: Regenerate.
2076
bd434cc4
JM		 20772020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2078
2079 * bpf-opc.c: Regenerate.
2080
aeab2b26
JB		 20812020-01-30 Jan Beulich <jbeulich@suse.com>
2082
2083 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2084 (dis386): Use them to replace C2/C3 table entries.
2085 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2086 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2087 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2088 * i386-tbl.h: Re-generate.
2089
62b3f548
JB		 20902020-01-30 Jan Beulich <jbeulich@suse.com>
2091
2092 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2093 forms.
2094 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2095 DefaultSize.
2096 * i386-tbl.h: Re-generate.
2097
1bd8ae10
AM		 20982020-01-30 Alan Modra <amodra@gmail.com>
2099
2100 * tic4x-dis.c (tic4x_dp): Make unsigned.
2101
bc31405e
L		 21022020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2103 Jan Beulich <jbeulich@suse.com>
2104
2105 PR binutils/25445
2106 * i386-dis.c (MOVSXD_Fixup): New function.
2107 (movsxd_mode): New enum.
2108 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2109 (intel_operand_size): Handle movsxd_mode.
2110 (OP_E_register): Likewise.
2111 (OP_G): Likewise.
2112 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2113 register on movsxd. Add movsxd with 16-bit destination register
2114 for AMD64 and Intel64 ISAs.
2115 * i386-tbl.h: Regenerated.
2116
7568c93b
TC		 21172020-01-27 Tamar Christina <tamar.christina@arm.com>
2118
2119 PR 25403
2120 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2121 * aarch64-asm-2.c: Regenerate
2122 * aarch64-dis-2.c: Likewise.
2123 * aarch64-opc-2.c: Likewise.
2124
c006a730
JB		 21252020-01-21 Jan Beulich <jbeulich@suse.com>
2126
2127 * i386-opc.tbl (sysret): Drop DefaultSize.
2128 * i386-tbl.h: Re-generate.
2129
c906a69a
JB		 21302020-01-21 Jan Beulich <jbeulich@suse.com>
2131
2132 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2133 Dword.
2134 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2135 * i386-tbl.h: Re-generate.
2136
26916852
NC		 21372020-01-20 Nick Clifton <nickc@redhat.com>
2138
2139 * po/de.po: Updated German translation.
2140 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2141 * po/uk.po: Updated Ukranian translation.
2142
4d6cbb64
AM		 21432020-01-20 Alan Modra <amodra@gmail.com>
2144
2145 * hppa-dis.c (fput_const): Remove useless cast.
2146
2bddb71a
AM		 21472020-01-20 Alan Modra <amodra@gmail.com>
2148
2149 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2150
1b1bb2c6
NC		 21512020-01-18 Nick Clifton <nickc@redhat.com>
2152
2153 * configure: Regenerate.
2154 * po/opcodes.pot: Regenerate.
2155
ae774686
NC		 21562020-01-18 Nick Clifton <nickc@redhat.com>
2157
2158 Binutils 2.34 branch created.
2159
07f1f3aa
CB		 21602020-01-17 Christian Biesinger <cbiesinger@google.com>
2161
2162 * opintl.h: Fix spelling error (seperate).
2163
42e04b36
L		 21642020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2165
2166 * i386-opc.tbl: Add {vex} pseudo prefix.
2167 * i386-tbl.h: Regenerated.
2168
2da2eaf4
AV		 21692020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2170
2171 PR 25376
2172 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2173 (neon_opcodes): Likewise.
2174 (select_arm_features): Make sure we enable MVE bits when selecting
2175 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2176 any architecture.
2177
d0849eed
JB		 21782020-01-16 Jan Beulich <jbeulich@suse.com>
2179
2180 * i386-opc.tbl: Drop stale comment from XOP section.
2181
9cf70a44
JB		 21822020-01-16 Jan Beulich <jbeulich@suse.com>
2183
2184 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2185 (extractps): Add VexWIG to SSE2AVX forms.
2186 * i386-tbl.h: Re-generate.
2187
4814632e
JB		 21882020-01-16 Jan Beulich <jbeulich@suse.com>
2189
2190 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2191 Size64 from and use VexW1 on SSE2AVX forms.
2192 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2193 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2194 * i386-tbl.h: Re-generate.
2195
aad09917
AM		 21962020-01-15 Alan Modra <amodra@gmail.com>
2197
2198 * tic4x-dis.c (tic4x_version): Make unsigned long.
2199 (optab, optab_special, registernames): New file scope vars.
2200 (tic4x_print_register): Set up registernames rather than
2201 malloc'd registertable.
2202 (tic4x_disassemble): Delete optable and optable_special. Use
2203 optab and optab_special instead. Throw away old optab,
2204 optab_special and registernames when info->mach changes.
2205
7a6bf3be
SB		 22062020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2207
2208 PR 25377
2209 * z80-dis.c (suffix): Use .db instruction to generate double
2210 prefix.
2211
ca1eaac0
AM		 22122020-01-14 Alan Modra <amodra@gmail.com>
2213
2214 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2215 values to unsigned before shifting.
2216
1d67fe3b
TT		 22172020-01-13 Thomas Troeger <tstroege@gmx.de>
2218
2219 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2220 flow instructions.
2221 (print_insn_thumb16, print_insn_thumb32): Likewise.
2222 (print_insn): Initialize the insn info.
2223 * i386-dis.c (print_insn): Initialize the insn info fields, and
2224 detect jumps.
2225
5e4f7e05
CZ		 22262012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2227
2228 * arc-opc.c (C_NE): Make it required.
2229
b9fe6b8a
CZ		 22302012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2231
2232 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2233 reserved register name.
2234
90dee485
AM		 22352020-01-13 Alan Modra <amodra@gmail.com>
2236
2237 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2238 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2239
febda64f
AM		 22402020-01-13 Alan Modra <amodra@gmail.com>
2241
2242 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2243 result of wasm_read_leb128 in a uint64_t and check that bits
2244 are not lost when copying to other locals. Use uint32_t for
2245 most locals. Use PRId64 when printing int64_t.
2246
df08b588
AM		 22472020-01-13 Alan Modra <amodra@gmail.com>
2248
2249 * score-dis.c: Formatting.
2250 * score7-dis.c: Formatting.
2251
b2c759ce
AM		 22522020-01-13 Alan Modra <amodra@gmail.com>
2253
2254 * score-dis.c (print_insn_score48): Use unsigned variables for
2255 unsigned values. Don't left shift negative values.
2256 (print_insn_score32): Likewise.
2257 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2258
5496abe1
AM		 22592020-01-13 Alan Modra <amodra@gmail.com>
2260
2261 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2262
202e762b
AM		 22632020-01-13 Alan Modra <amodra@gmail.com>
2264
2265 * fr30-ibld.c: Regenerate.
2266
7ef412cf
AM		 22672020-01-13 Alan Modra <amodra@gmail.com>
2268
2269 * xgate-dis.c (print_insn): Don't left shift signed value.
2270 (ripBits): Formatting, use 1u.
2271
7f578b95
AM		 22722020-01-10 Alan Modra <amodra@gmail.com>
2273
2274 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2275 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2276
441af85b
AM		 22772020-01-10 Alan Modra <amodra@gmail.com>
2278
2279 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2280 and XRREG value earlier to avoid a shift with negative exponent.
2281 * m10200-dis.c (disassemble): Similarly.
2282
bce58db4
NC		 22832020-01-09 Nick Clifton <nickc@redhat.com>
2284
2285 PR 25224
2286 * z80-dis.c (ld_ii_ii): Use correct cast.
2287
40c75bc8
SB		 22882020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2289
2290 PR 25224
2291 * z80-dis.c (ld_ii_ii): Use character constant when checking
2292 opcode byte value.
2293
d835a58b
JB		 22942020-01-09 Jan Beulich <jbeulich@suse.com>
2295
2296 * i386-dis.c (SEP_Fixup): New.
2297 (SEP): Define.
2298 (dis386_twobyte): Use it for sysenter/sysexit.
2299 (enum x86_64_isa): Change amd64 enumerator to value 1.
2300 (OP_J): Compare isa64 against intel64 instead of amd64.
2301 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2302 forms.
2303 * i386-tbl.h: Re-generate.
2304
030a2e78
AM		 23052020-01-08 Alan Modra <amodra@gmail.com>
2306
2307 * z8k-dis.c: Include libiberty.h
2308 (instr_data_s): Make max_fetched unsigned.
2309 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2310 Don't exceed byte_info bounds.
2311 (output_instr): Make num_bytes unsigned.
2312 (unpack_instr): Likewise for nibl_count and loop.
2313 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2314 idx unsigned.
2315 * z8k-opc.h: Regenerate.
2316
bb82aefe
SV		 23172020-01-07 Shahab Vahedi <shahab@synopsys.com>
2318
2319 * arc-tbl.h (llock): Use 'LLOCK' as class.
2320 (llockd): Likewise.
2321 (scond): Use 'SCOND' as class.
2322 (scondd): Likewise.
2323 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2324 (scondd): Likewise.
2325
cc6aa1a6
AM		 23262020-01-06 Alan Modra <amodra@gmail.com>
2327
2328 * m32c-ibld.c: Regenerate.
2329
660e62b1
AM		 23302020-01-06 Alan Modra <amodra@gmail.com>
2331
2332 PR 25344
2333 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2334 Peek at next byte to prevent recursion on repeated prefix bytes.
2335 Ensure uninitialised "mybuf" is not accessed.
2336 (print_insn_z80): Don't zero n_fetch and n_used here,..
2337 (print_insn_z80_buf): ..do it here instead.
2338
c9ae58fe
AM		 23392020-01-04 Alan Modra <amodra@gmail.com>
2340
2341 * m32r-ibld.c: Regenerate.
2342
5f57d4ec
AM		 23432020-01-04 Alan Modra <amodra@gmail.com>
2344
2345 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2346
2c5c1196
AM		 23472020-01-04 Alan Modra <amodra@gmail.com>
2348
2349 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2350
2e98c6c5
AM		 23512020-01-04 Alan Modra <amodra@gmail.com>
2352
2353 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2354
567dfba2
JB		 23552020-01-03 Jan Beulich <jbeulich@suse.com>
2356
5437a02a
JB		 2357 * aarch64-tbl.h (aarch64_opcode_table): Use
2358 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2359
23602020-01-03 Jan Beulich <jbeulich@suse.com>
2361
2362 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2363 forms of SUDOT and USDOT.
2364
8c45011a
JB		 23652020-01-03 Jan Beulich <jbeulich@suse.com>
2366
5437a02a 2367 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2368 uzip{1,2}.
2369 * opcodes/aarch64-dis-2.c: Re-generate.
2370
f4950f76
JB		 23712020-01-03 Jan Beulich <jbeulich@suse.com>
2372
5437a02a 2373 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2374 FMMLA encoding.
2375 * opcodes/aarch64-dis-2.c: Re-generate.
2376
6655dba2
SB		 23772020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2378
2379 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2380
b14ce8bf
AM		 23812020-01-01 Alan Modra <amodra@gmail.com>
2382
2383 Update year range in copyright notice of all files.
2384
0b114740 2385For older changes see ChangeLog-2019
3499769a 2386\f
0b114740 2387Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2388
2389Copying and distribution of this file, with or without modification,
2390are permitted in any medium without royalty provided the copyright
2391notice and this notice are preserved.
2392
2393Local Variables:
2394mode: change-log
2395left-margin: 8
2396fill-column: 74
2397version-control: never
2398End:
A mirror of the official binutils-gdb repository