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[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
a2353a08
CD		 12003-01-14 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen (EI, DI): Remove.
4
80551777
CD		 52003-01-05 Richard Sandiford <rsandifo@redhat.com>
6
7 * Makefile.in (tmp-run-multi): Fix mips16 filter.
8
4c54fc26
CD		 92003-01-04 Richard Sandiford <rsandifo@redhat.com>
10 Andrew Cagney <ac131313@redhat.com>
11 Gavin Romig-Koch <gavin@redhat.com>
12 Graydon Hoare <graydon@redhat.com>
13 Aldy Hernandez <aldyh@redhat.com>
14 Dave Brolley <brolley@redhat.com>
15 Chris Demetriou <cgd@broadcom.com>
16
17 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
18 (sim_mach_default): New variable.
19 (mips64vr-*-*, mips64vrel-*-*): New configurations.
20 Add a new simulator generator, MULTI.
21 * configure: Regenerate.
22 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
23 (multi-run.o): New dependency.
24 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
25 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
26 (tmp-multi): Combine them.
27 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
28 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
29 (distclean-extra): New rule.
30 * sim-main.h: Include bfd.h.
31 (MIPS_MACH): New macro.
32 * mips.igen (vr4120, vr5400, vr5500): New models.
33 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
34 * vr.igen: Replace with new version.
35
e6c674b8
CD		 362003-01-04 Chris Demetriou <cgd@broadcom.com>
37
38 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
39 * configure: Regenerate.
40
28f50ac8
CD		 412002-12-31 Chris Demetriou <cgd@broadcom.com>
42
43 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
44 * mips.igen: Remove all invocations of check_branch_bug and
45 mark_branch_bug.
46
5071ffe6
CD		 472002-12-16 Chris Demetriou <cgd@broadcom.com>
48
49 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
50
06e7837e
CD		 512002-07-30 Chris Demetriou <cgd@broadcom.com>
52
53 * mips.igen (do_load_double, do_store_double): New functions.
54 (LDC1, SDC1): Rename to...
55 (LDC1b, SDC1b): respectively.
56 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
57
2265c243
MS		 582002-07-29 Michael Snyder <msnyder@redhat.com>
59
60 * cp1.c (fp_recip2): Modify initialization expression so that
61 GCC will recognize it as constant.
62
a2f8b4f3
CD		 632002-06-18 Chris Demetriou <cgd@broadcom.com>
64
65 * mdmx.c (SD_): Delete.
66 (Unpredictable): Re-define, for now, to directly invoke
67 unpredictable_action().
68 (mdmx_acc_op): Fix error in .ob immediate handling.
69
b4b6c939
AC		 702002-06-18 Andrew Cagney <cagney@redhat.com>
71
72 * interp.c (sim_firmware_command): Initialize `address'.
73
c8cca39f
AC		 742002-06-16 Andrew Cagney <ac131313@redhat.com>
75
76 * configure: Regenerated to track ../common/aclocal.m4 changes.
77
e7e81181
CD		 782002-06-14 Chris Demetriou <cgd@broadcom.com>
79 Ed Satterthwaite <ehs@broadcom.com>
80
81 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
82 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
83 * mips.igen: Include mips3d.igen.
84 (mips3d): New model name for MIPS-3D ASE instructions.
85 (CVT.W.fmt): Don't use this instruction for word (source) format
86 instructions.
87 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
88 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
89 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
90 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
91 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
92 (RSquareRoot1, RSquareRoot2): New macros.
93 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
94 (fp_rsqrt2): New functions.
95 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
96 * configure: Regenerate.
97
3a2b820e 982002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 99 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 100
101 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
102 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
103 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
104 (convert): Note that this function is not used for paired-single
105 format conversions.
106 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
107 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
108 (check_fmt_p): Enable paired-single support.
109 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
110 (PUU.PS): New instructions.
111 (CVT.S.fmt): Don't use this instruction for paired-single format
112 destinations.
113 * sim-main.h (FP_formats): New value 'fmt_ps.'
114 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
115 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
116
d18ea9c2
CD		 1172002-06-12 Chris Demetriou <cgd@broadcom.com>
118
119 * mips.igen: Fix formatting of function calls in
120 many FP operations.
121
95fd5cee
CD		 1222002-06-12 Chris Demetriou <cgd@broadcom.com>
123
124 * mips.igen (MOVN, MOVZ): Trace result.
125 (TNEI): Print "tnei" as the opcode name in traces.
126 (CEIL.W): Add disassembly string for traces.
127 (RSQRT.fmt): Make location of disassembly string consistent
128 with other instructions.
129
4f0d55ae
CD		 1302002-06-12 Chris Demetriou <cgd@broadcom.com>
131
132 * mips.igen (X): Delete unused function.
133
3c25f8c7
AC		 1342002-06-08 Andrew Cagney <cagney@redhat.com>
135
136 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
137
f3c08b7e
CD		 1382002-06-07 Chris Demetriou <cgd@broadcom.com>
139 Ed Satterthwaite <ehs@broadcom.com>
140
141 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
142 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
143 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
144 (fp_nmsub): New prototypes.
145 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
146 (NegMultiplySub): New defines.
147 * mips.igen (RSQRT.fmt): Use RSquareRoot().
148 (MADD.D, MADD.S): Replace with...
149 (MADD.fmt): New instruction.
150 (MSUB.D, MSUB.S): Replace with...
151 (MSUB.fmt): New instruction.
152 (NMADD.D, NMADD.S): Replace with...
153 (NMADD.fmt): New instruction.
154 (NMSUB.D, MSUB.S): Replace with...
155 (NMSUB.fmt): New instruction.
156
52714ff9
CD		 1572002-06-07 Chris Demetriou <cgd@broadcom.com>
158 Ed Satterthwaite <ehs@broadcom.com>
159
160 * cp1.c: Fix more comment spelling and formatting.
161 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
162 (denorm_mode): New function.
163 (fpu_unary, fpu_binary): Round results after operation, collect
164 status from rounding operations, and update the FCSR.
165 (convert): Collect status from integer conversions and rounding
166 operations, and update the FCSR. Adjust NaN values that result
167 from conversions. Convert to use sim_io_eprintf rather than
168 fprintf, and remove some debugging code.
169 * cp1.h (fenr_FS): New define.
170
577d8c4b
CD		 1712002-06-07 Chris Demetriou <cgd@broadcom.com>
172
173 * cp1.c (convert): Remove unusable debugging code, and move MIPS
174 rounding mode to sim FP rounding mode flag conversion code into...
175 (rounding_mode): New function.
176
196496ed
CD		 1772002-06-07 Chris Demetriou <cgd@broadcom.com>
178
179 * cp1.c: Clean up formatting of a few comments.
180 (value_fpr): Reformat switch statement.
181
cfe9ea23
CD		 1822002-06-06 Chris Demetriou <cgd@broadcom.com>
183 Ed Satterthwaite <ehs@broadcom.com>
184
185 * cp1.h: New file.
186 * sim-main.h: Include cp1.h.
187 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
188 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
189 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
190 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
191 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
192 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
193 * cp1.c: Don't include sim-fpu.h; already included by
194 sim-main.h. Clean up formatting of some comments.
195 (NaN, Equal, Less): Remove.
196 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
197 (fp_cmp): New functions.
198 * mips.igen (do_c_cond_fmt): Remove.
199 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
200 Compare. Add result tracing.
201 (CxC1): Remove, replace with...
202 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
203 (DMxC1): Remove, replace with...
204 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
205 (MxC1): Remove, replace with...
206 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
207
ee7254b0
CD		 2082002-06-04 Chris Demetriou <cgd@broadcom.com>
209
210 * sim-main.h (FGRIDX): Remove, replace all uses with...
211 (FGR_BASE): New macro.
212 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
213 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
214 (NR_FGR, FGR): Likewise.
215 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
216 * mips.igen: Likewise.
217
d3eb724f
CD		 2182002-06-04 Chris Demetriou <cgd@broadcom.com>
219
220 * cp1.c: Add an FSF Copyright notice to this file.
221
ba46ddd0
CD		 2222002-06-04 Chris Demetriou <cgd@broadcom.com>
223 Ed Satterthwaite <ehs@broadcom.com>
224
225 * cp1.c (Infinity): Remove.
226 * sim-main.h (Infinity): Likewise.
227
228 * cp1.c (fp_unary, fp_binary): New functions.
229 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
230 (fp_sqrt): New functions, implemented in terms of the above.
231 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
232 (Recip, SquareRoot): Remove (replaced by functions above).
233 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
234 (fp_recip, fp_sqrt): New prototypes.
235 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
236 (Recip, SquareRoot): Replace prototypes with #defines which
237 invoke the functions above.
238
18d8a52d
CD		 2392002-06-03 Chris Demetriou <cgd@broadcom.com>
240
241 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
242 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
243 file, remove PARAMS from prototypes.
244 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
245 simulator state arguments.
246 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
247 pass simulator state arguments.
248 * cp1.c (SD): Redefine as CPU_STATE(cpu).
249 (store_fpr, convert): Remove 'sd' argument.
250 (value_fpr): Likewise. Convert to use 'SD' instead.
251
0f154cbd
CD		 2522002-06-03 Chris Demetriou <cgd@broadcom.com>
253
254 * cp1.c (Min, Max): Remove #if 0'd functions.
255 * sim-main.h (Min, Max): Remove.
256
e80fc152
CD		 2572002-06-03 Chris Demetriou <cgd@broadcom.com>
258
259 * cp1.c: fix formatting of switch case and default labels.
260 * interp.c: Likewise.
261 * sim-main.c: Likewise.
262
bad673a9
CD		 2632002-06-03 Chris Demetriou <cgd@broadcom.com>
264
265 * cp1.c: Clean up comments which describe FP formats.
266 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
267
7cbea089
CD		 2682002-06-03 Chris Demetriou <cgd@broadcom.com>
269 Ed Satterthwaite <ehs@broadcom.com>
270
271 * configure.in (mipsisa64sb1*-*-*): New target for supporting
272 Broadcom SiByte SB-1 processor configurations.
273 * configure: Regenerate.
274 * sb1.igen: New file.
275 * mips.igen: Include sb1.igen.
276 (sb1): New model.
277 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
278 * mdmx.igen: Add "sb1" model to all appropriate functions and
279 instructions.
280 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
281 (ob_func, ob_acc): Reference the above.
282 (qh_acc): Adjust to keep the same size as ob_acc.
283 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
284 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
285
909daa82
CD		 2862002-06-03 Chris Demetriou <cgd@broadcom.com>
287
288 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
289
f4f1b9f1
CD		 2902002-06-02 Chris Demetriou <cgd@broadcom.com>
291 Ed Satterthwaite <ehs@broadcom.com>
292
293 * mips.igen (mdmx): New (pseudo-)model.
294 * mdmx.c, mdmx.igen: New files.
295 * Makefile.in (SIM_OBJS): Add mdmx.o.
296 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
297 New typedefs.
298 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
299 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
300 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
301 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
302 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
303 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
304 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
305 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
306 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
307 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
308 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
309 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
310 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
311 (qh_fmtsel): New macros.
312 (_sim_cpu): New member "acc".
313 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
314 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
315
5accf1ff
CD		 3162002-05-01 Chris Demetriou <cgd@broadcom.com>
317
318 * interp.c: Use 'deprecated' rather than 'depreciated.'
319 * sim-main.h: Likewise.
320
402586aa
CD		 3212002-05-01 Chris Demetriou <cgd@broadcom.com>
322
323 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
324 which wouldn't compile anyway.
325 * sim-main.h (unpredictable_action): New function prototype.
326 (Unpredictable): Define to call igen function unpredictable().
327 (NotWordValue): New macro to call igen function not_word_value().
328 (UndefinedResult): Remove.
329 * interp.c (undefined_result): Remove.
330 (unpredictable_action): New function.
331 * mips.igen (not_word_value, unpredictable): New functions.
332 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
333 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
334 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
335 NotWordValue() to check for unpredictable inputs, then
336 Unpredictable() to handle them.
337
c9b9995a
CD		 3382002-02-24 Chris Demetriou <cgd@broadcom.com>
339
340 * mips.igen: Fix formatting of calls to Unpredictable().
341
e1015982
AC		 3422002-04-20 Andrew Cagney <ac131313@redhat.com>
343
344 * interp.c (sim_open): Revert previous change.
345
b882a66b
AO		 3462002-04-18 Alexandre Oliva <aoliva@redhat.com>
347
348 * interp.c (sim_open): Disable chunk of code that wrote code in
349 vector table entries.
350
c429b7dd
CD		 3512002-03-19 Chris Demetriou <cgd@broadcom.com>
352
353 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
354 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
355 unused definitions.
356
37d146fa
CD		 3572002-03-19 Chris Demetriou <cgd@broadcom.com>
358
359 * cp1.c: Fix many formatting issues.
360
07892c0b
CD		 3612002-03-19 Chris G. Demetriou <cgd@broadcom.com>
362
363 * cp1.c (fpu_format_name): New function to replace...
364 (DOFMT): This. Delete, and update all callers.
365 (fpu_rounding_mode_name): New function to replace...
366 (RMMODE): This. Delete, and update all callers.
367
487f79b7
CD		 3682002-03-19 Chris G. Demetriou <cgd@broadcom.com>
369
370 * interp.c: Move FPU support routines from here to...
371 * cp1.c: Here. New file.
372 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
373 (cp1.o): New target.
374
1e799e28
CD		 3752002-03-12 Chris Demetriou <cgd@broadcom.com>
376
377 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
378 * mips.igen (mips32, mips64): New models, add to all instructions
379 and functions as appropriate.
380 (loadstore_ea, check_u64): New variant for model mips64.
381 (check_fmt_p): New variant for models mipsV and mips64, remove
382 mipsV model marking fro other variant.
383 (SLL) Rename to...
384 (SLLa) this.
385 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
386 for mips32 and mips64.
387 (DCLO, DCLZ): New instructions for mips64.
388
82f728db
CD		 3892002-03-07 Chris Demetriou <cgd@broadcom.com>
390
391 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
392 immediate or code as a hex value with the "%#lx" format.
393 (ANDI): Likewise, and fix printed instruction name.
394
b96e7ef1
CD		 3952002-03-05 Chris Demetriou <cgd@broadcom.com>
396
397 * sim-main.h (UndefinedResult, Unpredictable): New macros
398 which currently do nothing.
399
d35d4f70
CD		 4002002-03-05 Chris Demetriou <cgd@broadcom.com>
401
402 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
403 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
404 (status_CU3): New definitions.
405
406 * sim-main.h (ExceptionCause): Add new values for MIPS32
407 and MIPS64: MDMX, MCheck, CacheErr. Update comments
408 for DebugBreakPoint and NMIReset to note their status in
409 MIPS32 and MIPS64.
410 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
411 (SignalExceptionCacheErr): New exception macros.
412
3ad6f714
CD		 4132002-03-05 Chris Demetriou <cgd@broadcom.com>
414
415 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
416 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
417 is always enabled.
418 (SignalExceptionCoProcessorUnusable): Take as argument the
419 unusable coprocessor number.
420
86b77b47
CD		 4212002-03-05 Chris Demetriou <cgd@broadcom.com>
422
423 * mips.igen: Fix formatting of all SignalException calls.
424
97a88e93 4252002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 426
427 * sim-main.h (SIGNEXTEND): Remove.
428
97a88e93 4292002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 430
431 * mips.igen: Remove gencode comment from top of file, fix
432 spelling in another comment.
433
97a88e93 4342002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 435
436 * mips.igen (check_fmt, check_fmt_p): New functions to check
437 whether specific floating point formats are usable.
438 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
439 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
440 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
441 Use the new functions.
442 (do_c_cond_fmt): Remove format checks...
443 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
444
97a88e93 4452002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 446
447 * mips.igen: Fix formatting of check_fpu calls.
448
41774c9d
CD		 4492002-03-03 Chris Demetriou <cgd@broadcom.com>
450
451 * mips.igen (FLOOR.L.fmt): Store correct destination register.
452
4a0bd876
CD		 4532002-03-03 Chris Demetriou <cgd@broadcom.com>
454
455 * mips.igen: Remove whitespace at end of lines.
456
09297648
CD		 4572002-03-02 Chris Demetriou <cgd@broadcom.com>
458
459 * mips.igen (loadstore_ea): New function to do effective
460 address calculations.
461 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
462 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
463 CACHE): Use loadstore_ea to do effective address computations.
464
043b7057
CD		 4652002-03-02 Chris Demetriou <cgd@broadcom.com>
466
467 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
468 * mips.igen (LL, CxC1, MxC1): Likewise.
469
c1e8ada4
CD		 4702002-03-02 Chris Demetriou <cgd@broadcom.com>
471
472 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
473 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
474 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
475 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
476 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
477 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
478 Don't split opcode fields by hand, use the opcode field values
479 provided by igen.
480
3e1dca16
CD		 4812002-03-01 Chris Demetriou <cgd@broadcom.com>
482
483 * mips.igen (do_divu): Fix spacing.
484
485 * mips.igen (do_dsllv): Move to be right before DSLLV,
486 to match the rest of the do_<shift> functions.
487
fff8d27d
CD		 4882002-03-01 Chris Demetriou <cgd@broadcom.com>
489
490 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
491 DSRL32, do_dsrlv): Trace inputs and results.
492
0d3e762b
CD		 4932002-03-01 Chris Demetriou <cgd@broadcom.com>
494
495 * mips.igen (CACHE): Provide instruction-printing string.
496
497 * interp.c (signal_exception): Comment tokens after #endif.
498
eb5fcf93
CD		 4992002-02-28 Chris Demetriou <cgd@broadcom.com>
500
501 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
502 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
503 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
504 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
505 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
506 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
507 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
508 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
509
bb22bd7d
CD		 5102002-02-28 Chris Demetriou <cgd@broadcom.com>
511
512 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
513 instruction-printing string.
514 (LWU): Use '64' as the filter flag.
515
91a177cf
CD		 5162002-02-28 Chris Demetriou <cgd@broadcom.com>
517
518 * mips.igen (SDXC1): Fix instruction-printing string.
519
387f484a
CD		 5202002-02-28 Chris Demetriou <cgd@broadcom.com>
521
522 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
523 filter flags "32,f".
524
3d81f391
CD		 5252002-02-27 Chris Demetriou <cgd@broadcom.com>
526
527 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
528 as the filter flag.
529
af5107af
CD		 5302002-02-27 Chris Demetriou <cgd@broadcom.com>
531
532 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
533 add a comma) so that it more closely match the MIPS ISA
534 documentation opcode partitioning.
535 (PREF): Put useful names on opcode fields, and include
536 instruction-printing string.
537
ca971540
CD		 5382002-02-27 Chris Demetriou <cgd@broadcom.com>
539
540 * mips.igen (check_u64): New function which in the future will
541 check whether 64-bit instructions are usable and signal an
542 exception if not. Currently a no-op.
543 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
544 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
545 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
546 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
547
548 * mips.igen (check_fpu): New function which in the future will
549 check whether FPU instructions are usable and signal an exception
550 if not. Currently a no-op.
551 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
552 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
553 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
554 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
555 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
556 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
557 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
558 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
559
1c47a468
CD		 5602002-02-27 Chris Demetriou <cgd@broadcom.com>
561
562 * mips.igen (do_load_left, do_load_right): Move to be immediately
563 following do_load.
564 (do_store_left, do_store_right): Move to be immediately following
565 do_store.
566
603a98e7
CD		 5672002-02-27 Chris Demetriou <cgd@broadcom.com>
568
569 * mips.igen (mipsV): New model name. Also, add it to
570 all instructions and functions where it is appropriate.
571
c5d00cc7
CD		 5722002-02-18 Chris Demetriou <cgd@broadcom.com>
573
574 * mips.igen: For all functions and instructions, list model
575 names that support that instruction one per line.
576
074e9cb8
CD		 5772002-02-11 Chris Demetriou <cgd@broadcom.com>
578
579 * mips.igen: Add some additional comments about supported
580 models, and about which instructions go where.
581 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
582 order as is used in the rest of the file.
583
9805e229
CD		 5842002-02-11 Chris Demetriou <cgd@broadcom.com>
585
586 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
587 indicating that ALU32_END or ALU64_END are there to check
588 for overflow.
589 (DADD): Likewise, but also remove previous comment about
590 overflow checking.
591
f701dad2
CD		 5922002-02-10 Chris Demetriou <cgd@broadcom.com>
593
594 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
595 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
596 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
597 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
598 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
599 fields (i.e., add and move commas) so that they more closely
600 match the MIPS ISA documentation opcode partitioning.
601
6022002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 603
604 * mips.igen (ADDI): Print immediate value.
605 (BREAK): Print code.
606 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
607 (SLL): Print "nop" specially, and don't run the code
608 that does the shift for the "nop" case.
609
9e52972e
FF		 6102001-11-17 Fred Fish <fnf@redhat.com>
611
612 * sim-main.h (float_operation): Move enum declaration outside
613 of _sim_cpu struct declaration.
614
c0efbca4
JB		 6152001-04-12 Jim Blandy <jimb@redhat.com>
616
617 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
618 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
619 set of the FCSR.
620 * sim-main.h (COCIDX): Remove definition; this isn't supported by
621 PENDING_FILL, and you can get the intended effect gracefully by
622 calling PENDING_SCHED directly.
623
fb891446
BE		 6242001-02-23 Ben Elliston <bje@redhat.com>
625
626 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
627 already defined elsewhere.
628
8030f857
BE		 6292001-02-19 Ben Elliston <bje@redhat.com>
630
631 * sim-main.h (sim_monitor): Return an int.
632 * interp.c (sim_monitor): Add return values.
633 (signal_exception): Handle error conditions from sim_monitor.
634
56b48a7a
CD		 6352001-02-08 Ben Elliston <bje@redhat.com>
636
637 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
638 (store_memory): Likewise, pass cia to sim_core_write*.
639
d3ee60d9
FCE		 6402000-10-19 Frank Ch. Eigler <fche@redhat.com>
641
642 On advice from Chris G. Demetriou <cgd@sibyte.com>:
643 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
644
071da002
AC		 645Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
646
647 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
648 * Makefile.in: Don't delete *.igen when cleaning directory.
649
a28c02cd
AC		 650Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
651
652 * m16.igen (break): Call SignalException not sim_engine_halt.
653
80ee11fa
AC		 654Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
655
656 From Jason Eckhardt:
657 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
658
673388c0
AC		 659Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
660
661 * mips.igen (MxC1, DMxC1): Fix printf formatting.
662
4c0deff4
NC		 6632000-05-24 Michael Hayes <mhayes@cygnus.com>
664
665 * mips.igen (do_dmultx): Fix typo.
666
eb2d80b4
AC		 667Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
668
669 * configure: Regenerated to track ../common/aclocal.m4 changes.
670
dd37a34b
AC		 671Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
672
673 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
674
4c0deff4
NC		 6752000-04-12 Frank Ch. Eigler <fche@redhat.com>
676
677 * sim-main.h (GPR_CLEAR): Define macro.
678
e30db738
AC		 679Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
680
681 * interp.c (decode_coproc): Output long using %lx and not %s.
682
cb7450ea
FCE		 6832000-03-21 Frank Ch. Eigler <fche@redhat.com>
684
685 * interp.c (sim_open): Sort & extend dummy memory regions for
686 --board=jmr3904 for eCos.
687
a3027dd7
FCE		 6882000-03-02 Frank Ch. Eigler <fche@redhat.com>
689
690 * configure: Regenerated.
691
692Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
693
694 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
695 calls, conditional on the simulator being in verbose mode.
696
dfcd3bfb
JM		 697Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
698
699 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
700 cache don't get ReservedInstruction traps.
701
c2d11a7d
JM		 7021999-11-29 Mark Salter <msalter@cygnus.com>
703
704 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
705 to clear status bits in sdisr register. This is how the hardware works.
706
707 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
708 being used by cygmon.
709
4ce44c66
JM		 7101999-11-11 Andrew Haley <aph@cygnus.com>
711
712 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
713 instructions.
714
cff3e48b
JM		 715Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
716
717 * mips.igen (MULT): Correct previous mis-applied patch.
718
d4f3574e
SS		 719Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
720
721 * mips.igen (delayslot32): Handle sequence like
722 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
723 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
724 (MULT): Actually pass the third register...
725
7261999-09-03 Mark Salter <msalter@cygnus.com>
727
728 * interp.c (sim_open): Added more memory aliases for additional
729 hardware being touched by cygmon on jmr3904 board.
730
731Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
732
733 * configure: Regenerated to track ../common/aclocal.m4 changes.
734
a0b3c4fd
JM		 735Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
736
737 * interp.c (sim_store_register): Handle case where client - GDB -
738 specifies that a 4 byte register is 8 bytes in size.
739 (sim_fetch_register): Ditto.
740
adf40b2e
JM		 7411999-07-14 Frank Ch. Eigler <fche@cygnus.com>
742
743 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
744 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
745 (idt_monitor_base): Base address for IDT monitor traps.
746 (pmon_monitor_base): Ditto for PMON.
747 (lsipmon_monitor_base): Ditto for LSI PMON.
748 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
749 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
750 (sim_firmware_command): New function.
751 (mips_option_handler): Call it for OPTION_FIRMWARE.
752 (sim_open): Allocate memory for idt_monitor region. If "--board"
753 option was given, add no monitor by default. Add BREAK hooks only if
754 monitors are also there.
755
43e526b9
JM		 756Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
757
758 * interp.c (sim_monitor): Flush output before reading input.
759
760Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
761
762 * tconfig.in (SIM_HANDLES_LMA): Always define.
763
764Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
765
766 From Mark Salter <msalter@cygnus.com>:
767 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
768 (sim_open): Add setup for BSP board.
769
9846de1b
JM		 770Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
771
772 * mips.igen (MULT, MULTU): Add syntax for two operand version.
773 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
774 them as unimplemented.
775
cd0fc7c3
SS		 7761999-05-08 Felix Lee <flee@cygnus.com>
777
778 * configure: Regenerated to track ../common/aclocal.m4 changes.
779
7a292a7a
SS		 7801999-04-21 Frank Ch. Eigler <fche@cygnus.com>
781
782 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
783
784Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
785
786 * configure.in: Any mips64vr5*-*-* target should have
787 -DTARGET_ENABLE_FR=1.
788 (default_endian): Any mips64vr*el-*-* target should default to
789 LITTLE_ENDIAN.
790 * configure: Re-generate.
791
7921999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
793
794 * mips.igen (ldl): Extend from _16_, not 32.
795
796Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
797
798 * interp.c (sim_store_register): Force registers written to by GDB
799 into an un-interpreted state.
800
c906108c
SS		 8011999-02-05 Frank Ch. Eigler <fche@cygnus.com>
802
803 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
804 CPU, start periodic background I/O polls.
805 (tx3904sio_poll): New function: periodic I/O poller.
806
8071998-12-30 Frank Ch. Eigler <fche@cygnus.com>
808
809 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
810
811Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
812
813 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
814 case statement.
815
8161998-12-29 Frank Ch. Eigler <fche@cygnus.com>
817
818 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
819 (load_word): Call SIM_CORE_SIGNAL hook on error.
820 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
821 starting. For exception dispatching, pass PC instead of NULL_CIA.
822 (decode_coproc): Use COP0_BADVADDR to store faulting address.
823 * sim-main.h (COP0_BADVADDR): Define.
824 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
825 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
826 (_sim_cpu): Add exc_* fields to store register value snapshots.
827 * mips.igen (*): Replace memory-related SignalException* calls
828 with references to SIM_CORE_SIGNAL hook.
829
830 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
831 fix.
832 * sim-main.c (*): Minor warning cleanups.
833
8341998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
835
836 * m16.igen (DADDIU5): Correct type-o.
837
838Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
839
840 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
841 variables.
842
843Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
844
845 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
846 to include path.
847 (interp.o): Add dependency on itable.h
848 (oengine.c, gencode): Delete remaining references.
849 (BUILT_SRC_FROM_GEN): Clean up.
850
8511998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
852
853 * vr4run.c: New.
854 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
855 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
856 tmp-run-hack) : New.
857 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
858 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
859 Drop the "64" qualifier to get the HACK generator working.
860 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
861 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
862 qualifier to get the hack generator working.
863 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
864 (DSLL): Use do_dsll.
865 (DSLLV): Use do_dsllv.
866 (DSRA): Use do_dsra.
867 (DSRL): Use do_dsrl.
868 (DSRLV): Use do_dsrlv.
869 (BC1): Move *vr4100 to get the HACK generator working.
870 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
871 get the HACK generator working.
872 (MACC) Rename to get the HACK generator working.
873 (DMACC,MACCS,DMACCS): Add the 64.
874
8751998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
876
877 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
878 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
879
8801998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
881
882 * mips/interp.c (DEBUG): Cleanups.
883
8841998-12-10 Frank Ch. Eigler <fche@cygnus.com>
885
886 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
887 (tx3904sio_tickle): fflush after a stdout character output.
888
8891998-12-03 Frank Ch. Eigler <fche@cygnus.com>
890
891 * interp.c (sim_close): Uninstall modules.
892
893Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
894
895 * sim-main.h, interp.c (sim_monitor): Change to global
896 function.
897
898Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
899
900 * configure.in (vr4100): Only include vr4100 instructions in
901 simulator.
902 * configure: Re-generate.
903 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
904
905Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
906
907 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
908 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
909 true alternative.
910
911 * configure.in (sim_default_gen, sim_use_gen): Replace with
912 sim_gen.
913 (--enable-sim-igen): Delete config option. Always using IGEN.
914 * configure: Re-generate.
915
916 * Makefile.in (gencode): Kill, kill, kill.
917 * gencode.c: Ditto.
918
919Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
920
921 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
922 bit mips16 igen simulator.
923 * configure: Re-generate.
924
925 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
926 as part of vr4100 ISA.
927 * vr.igen: Mark all instructions as 64 bit only.
928
929Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
930
931 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
932 Pacify GCC.
933
934Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
935
936 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
937 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
938 * configure: Re-generate.
939
940 * m16.igen (BREAK): Define breakpoint instruction.
941 (JALX32): Mark instruction as mips16 and not r3900.
942 * mips.igen (C.cond.fmt): Fix typo in instruction format.
943
944 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
945
946Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
947
948 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
949 insn as a debug breakpoint.
950
951 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
952 pending.slot_size.
953 (PENDING_SCHED): Clean up trace statement.
954 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
955 (PENDING_FILL): Delay write by only one cycle.
956 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
957
958 * sim-main.c (pending_tick): Clean up trace statements. Add trace
959 of pending writes.
960 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
961 32 & 64.
962 (pending_tick): Move incrementing of index to FOR statement.
963 (pending_tick): Only update PENDING_OUT after a write has occured.
964
965 * configure.in: Add explicit mips-lsi-* target. Use gencode to
966 build simulator.
967 * configure: Re-generate.
968
969 * interp.c (sim_engine_run OLD): Delete explicit call to
970 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
971
972Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
973
974 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
975 interrupt level number to match changed SignalExceptionInterrupt
976 macro.
977
978Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
979
980 * interp.c: #include "itable.h" if WITH_IGEN.
981 (get_insn_name): New function.
982 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
983 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
984
985Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
986
987 * configure: Rebuilt to inhale new common/aclocal.m4.
988
989Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
990
991 * dv-tx3904sio.c: Include sim-assert.h.
992
993Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
994
995 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
996 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
997 Reorganize target-specific sim-hardware checks.
998 * configure: rebuilt.
999 * interp.c (sim_open): For tx39 target boards, set
1000 OPERATING_ENVIRONMENT, add tx3904sio devices.
1001 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1002 ROM executables. Install dv-sockser into sim-modules list.
1003
1004 * dv-tx3904irc.c: Compiler warning clean-up.
1005 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1006 frequent hw-trace messages.
1007
1008Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1009
1010 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1011
1012Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1013
1014 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1015
1016 * vr.igen: New file.
1017 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1018 * mips.igen: Define vr4100 model. Include vr.igen.
1019Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1020
1021 * mips.igen (check_mf_hilo): Correct check.
1022
1023Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1024
1025 * sim-main.h (interrupt_event): Add prototype.
1026
1027 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1028 register_ptr, register_value.
1029 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1030
1031 * sim-main.h (tracefh): Make extern.
1032
1033Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1034
1035 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1036 Reduce unnecessarily high timer event frequency.
1037 * dv-tx3904cpu.c: Ditto for interrupt event.
1038
1039Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1040
1041 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1042 to allay warnings.
1043 (interrupt_event): Made non-static.
1044
1045 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1046 interchange of configuration values for external vs. internal
1047 clock dividers.
1048
1049Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1050
1051 * mips.igen (BREAK): Moved code to here for
1052 simulator-reserved break instructions.
1053 * gencode.c (build_instruction): Ditto.
1054 * interp.c (signal_exception): Code moved from here. Non-
1055 reserved instructions now use exception vector, rather
1056 than halting sim.
1057 * sim-main.h: Moved magic constants to here.
1058
1059Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1060
1061 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1062 register upon non-zero interrupt event level, clear upon zero
1063 event value.
1064 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1065 by passing zero event value.
1066 (*_io_{read,write}_buffer): Endianness fixes.
1067 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1068 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1069
1070 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1071 serial I/O and timer module at base address 0xFFFF0000.
1072
1073Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1074
1075 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1076 and BigEndianCPU.
1077
1078Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1079
1080 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1081 parts.
1082 * configure: Update.
1083
1084Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1085
1086 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1087 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1088 * configure.in: Include tx3904tmr in hw_device list.
1089 * configure: Rebuilt.
1090 * interp.c (sim_open): Instantiate three timer instances.
1091 Fix address typo of tx3904irc instance.
1092
1093Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1094
1095 * interp.c (signal_exception): SystemCall exception now uses
1096 the exception vector.
1097
1098Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1099
1100 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1101 to allay warnings.
1102
1103Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1104
1105 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1106
1107Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1108
1109 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1110
1111 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1112 sim-main.h. Declare a struct hw_descriptor instead of struct
1113 hw_device_descriptor.
1114
1115Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1116
1117 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1118 right bits and then re-align left hand bytes to correct byte
1119 lanes. Fix incorrect computation in do_store_left when loading
1120 bytes from second word.
1121
1122Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1123
1124 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1125 * interp.c (sim_open): Only create a device tree when HW is
1126 enabled.
1127
1128 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1129 * interp.c (signal_exception): Ditto.
1130
1131Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1132
1133 * gencode.c: Mark BEGEZALL as LIKELY.
1134
1135Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136
1137 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1138 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1139
1140Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1141
1142 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1143 modules. Recognize TX39 target with "mips*tx39" pattern.
1144 * configure: Rebuilt.
1145 * sim-main.h (*): Added many macros defining bits in
1146 TX39 control registers.
1147 (SignalInterrupt): Send actual PC instead of NULL.
1148 (SignalNMIReset): New exception type.
1149 * interp.c (board): New variable for future use to identify
1150 a particular board being simulated.
1151 (mips_option_handler,mips_options): Added "--board" option.
1152 (interrupt_event): Send actual PC.
1153 (sim_open): Make memory layout conditional on board setting.
1154 (signal_exception): Initial implementation of hardware interrupt
1155 handling. Accept another break instruction variant for simulator
1156 exit.
1157 (decode_coproc): Implement RFE instruction for TX39.
1158 (mips.igen): Decode RFE instruction as such.
1159 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1160 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1161 bbegin to implement memory map.
1162 * dv-tx3904cpu.c: New file.
1163 * dv-tx3904irc.c: New file.
1164
1165Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1166
1167 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1168
1169Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1170
1171 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1172 with calls to check_div_hilo.
1173
1174Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1175
1176 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1177 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1178 Add special r3900 version of do_mult_hilo.
1179 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1180 with calls to check_mult_hilo.
1181 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1182 with calls to check_div_hilo.
1183
1184Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1187 Document a replacement.
1188
1189Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1190
1191 * interp.c (sim_monitor): Make mon_printf work.
1192
1193Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1194
1195 * sim-main.h (INSN_NAME): New arg `cpu'.
1196
1197Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1198
1199 * configure: Regenerated to track ../common/aclocal.m4 changes.
1200
1201Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1202
1203 * configure: Regenerated to track ../common/aclocal.m4 changes.
1204 * config.in: Ditto.
1205
1206Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1207
1208 * acconfig.h: New file.
1209 * configure.in: Reverted change of Apr 24; use sinclude again.
1210
1211Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1212
1213 * configure: Regenerated to track ../common/aclocal.m4 changes.
1214 * config.in: Ditto.
1215
1216Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1217
1218 * configure.in: Don't call sinclude.
1219
1220Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1221
1222 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1223
1224Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1225
1226 * mips.igen (ERET): Implement.
1227
1228 * interp.c (decode_coproc): Return sign-extended EPC.
1229
1230 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1231
1232 * interp.c (signal_exception): Do not ignore Trap.
1233 (signal_exception): On TRAP, restart at exception address.
1234 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1235 (signal_exception): Update.
1236 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1237 so that TRAP instructions are caught.
1238
1239Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1240
1241 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1242 contains HI/LO access history.
1243 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1244 (HIACCESS, LOACCESS): Delete, replace with
1245 (HIHISTORY, LOHISTORY): New macros.
1246 (CHECKHILO): Delete all, moved to mips.igen
1247
1248 * gencode.c (build_instruction): Do not generate checks for
1249 correct HI/LO register usage.
1250
1251 * interp.c (old_engine_run): Delete checks for correct HI/LO
1252 register usage.
1253
1254 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1255 check_mf_cycles): New functions.
1256 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1257 do_divu, domultx, do_mult, do_multu): Use.
1258
1259 * tx.igen ("madd", "maddu"): Use.
1260
1261Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1262
1263 * mips.igen (DSRAV): Use function do_dsrav.
1264 (SRAV): Use new function do_srav.
1265
1266 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1267 (B): Sign extend 11 bit immediate.
1268 (EXT-B*): Shift 16 bit immediate left by 1.
1269 (ADDIU*): Don't sign extend immediate value.
1270
1271Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1272
1273 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1274
1275 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1276 functions.
1277
1278 * mips.igen (delayslot32, nullify_next_insn): New functions.
1279 (m16.igen): Always include.
1280 (do_*): Add more tracing.
1281
1282 * m16.igen (delayslot16): Add NIA argument, could be called by a
1283 32 bit MIPS16 instruction.
1284
1285 * interp.c (ifetch16): Move function from here.
1286 * sim-main.c (ifetch16): To here.
1287
1288 * sim-main.c (ifetch16, ifetch32): Update to match current
1289 implementations of LH, LW.
1290 (signal_exception): Don't print out incorrect hex value of illegal
1291 instruction.
1292
1293Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1294
1295 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1296 instruction.
1297
1298 * m16.igen: Implement MIPS16 instructions.
1299
1300 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1301 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1302 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1303 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1304 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1305 bodies of corresponding code from 32 bit insn to these. Also used
1306 by MIPS16 versions of functions.
1307
1308 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1309 (IMEM16): Drop NR argument from macro.
1310
1311Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1312
1313 * Makefile.in (SIM_OBJS): Add sim-main.o.
1314
1315 * sim-main.h (address_translation, load_memory, store_memory,
1316 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1317 as INLINE_SIM_MAIN.
1318 (pr_addr, pr_uword64): Declare.
1319 (sim-main.c): Include when H_REVEALS_MODULE_P.
1320
1321 * interp.c (address_translation, load_memory, store_memory,
1322 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1323 from here.
1324 * sim-main.c: To here. Fix compilation problems.
1325
1326 * configure.in: Enable inlining.
1327 * configure: Re-config.
1328
1329Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1330
1331 * configure: Regenerated to track ../common/aclocal.m4 changes.
1332
1333Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1334
1335 * mips.igen: Include tx.igen.
1336 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1337 * tx.igen: New file, contains MADD and MADDU.
1338
1339 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1340 the hardwired constant `7'.
1341 (store_memory): Ditto.
1342 (LOADDRMASK): Move definition to sim-main.h.
1343
1344 mips.igen (MTC0): Enable for r3900.
1345 (ADDU): Add trace.
1346
1347 mips.igen (do_load_byte): Delete.
1348 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1349 do_store_right): New functions.
1350 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1351
1352 configure.in: Let the tx39 use igen again.
1353 configure: Update.
1354
1355Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1356
1357 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1358 not an address sized quantity. Return zero for cache sizes.
1359
1360Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1361
1362 * mips.igen (r3900): r3900 does not support 64 bit integer
1363 operations.
1364
1365Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1366
1367 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1368 than igen one.
1369 * configure : Rebuild.
1370
1371Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1372
1373 * configure: Regenerated to track ../common/aclocal.m4 changes.
1374
1375Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1376
1377 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1378
1379Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1380
1381 * configure: Regenerated to track ../common/aclocal.m4 changes.
1382 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1383
1384Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1385
1386 * configure: Regenerated to track ../common/aclocal.m4 changes.
1387
1388Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1389
1390 * interp.c (Max, Min): Comment out functions. Not yet used.
1391
1392Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * configure: Regenerated to track ../common/aclocal.m4 changes.
1395
1396Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1397
1398 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1399 configurable settings for stand-alone simulator.
1400
1401 * configure.in: Added X11 search, just in case.
1402
1403 * configure: Regenerated.
1404
1405Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1406
1407 * interp.c (sim_write, sim_read, load_memory, store_memory):
1408 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1409
1410Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1411
1412 * sim-main.h (GETFCC): Return an unsigned value.
1413
1414Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1415
1416 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1417 (DADD): Result destination is RD not RT.
1418
1419Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1420
1421 * sim-main.h (HIACCESS, LOACCESS): Always define.
1422
1423 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1424
1425 * interp.c (sim_info): Delete.
1426
1427Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1428
1429 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1430 (mips_option_handler): New argument `cpu'.
1431 (sim_open): Update call to sim_add_option_table.
1432
1433Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1434
1435 * mips.igen (CxC1): Add tracing.
1436
1437Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * sim-main.h (Max, Min): Declare.
1440
1441 * interp.c (Max, Min): New functions.
1442
1443 * mips.igen (BC1): Add tracing.
1444
1445Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1446
1447 * interp.c Added memory map for stack in vr4100
1448
1449Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1450
1451 * interp.c (load_memory): Add missing "break"'s.
1452
1453Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * interp.c (sim_store_register, sim_fetch_register): Pass in
1456 length parameter. Return -1.
1457
1458Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1459
1460 * interp.c: Added hardware init hook, fixed warnings.
1461
1462Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1465
1466Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1467
1468 * interp.c (ifetch16): New function.
1469
1470 * sim-main.h (IMEM32): Rename IMEM.
1471 (IMEM16_IMMED): Define.
1472 (IMEM16): Define.
1473 (DELAY_SLOT): Update.
1474
1475 * m16run.c (sim_engine_run): New file.
1476
1477 * m16.igen: All instructions except LB.
1478 (LB): Call do_load_byte.
1479 * mips.igen (do_load_byte): New function.
1480 (LB): Call do_load_byte.
1481
1482 * mips.igen: Move spec for insn bit size and high bit from here.
1483 * Makefile.in (tmp-igen, tmp-m16): To here.
1484
1485 * m16.dc: New file, decode mips16 instructions.
1486
1487 * Makefile.in (SIM_NO_ALL): Define.
1488 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1489
1490Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1491
1492 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1493 point unit to 32 bit registers.
1494 * configure: Re-generate.
1495
1496Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1497
1498 * configure.in (sim_use_gen): Make IGEN the default simulator
1499 generator for generic 32 and 64 bit mips targets.
1500 * configure: Re-generate.
1501
1502Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1505 bitsize.
1506
1507 * interp.c (sim_fetch_register, sim_store_register): Read/write
1508 FGR from correct location.
1509 (sim_open): Set size of FGR's according to
1510 WITH_TARGET_FLOATING_POINT_BITSIZE.
1511
1512 * sim-main.h (FGR): Store floating point registers in a separate
1513 array.
1514
1515Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * configure: Regenerated to track ../common/aclocal.m4 changes.
1518
1519Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1520
1521 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1522
1523 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1524
1525 * interp.c (pending_tick): New function. Deliver pending writes.
1526
1527 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1528 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1529 it can handle mixed sized quantites and single bits.
1530
1531Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1532
1533 * interp.c (oengine.h): Do not include when building with IGEN.
1534 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1535 (sim_info): Ditto for PROCESSOR_64BIT.
1536 (sim_monitor): Replace ut_reg with unsigned_word.
1537 (*): Ditto for t_reg.
1538 (LOADDRMASK): Define.
1539 (sim_open): Remove defunct check that host FP is IEEE compliant,
1540 using software to emulate floating point.
1541 (value_fpr, ...): Always compile, was conditional on HASFPU.
1542
1543Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1544
1545 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1546 size.
1547
1548 * interp.c (SD, CPU): Define.
1549 (mips_option_handler): Set flags in each CPU.
1550 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1551 (sim_close): Do not clear STATE, deleted anyway.
1552 (sim_write, sim_read): Assume CPU zero's vm should be used for
1553 data transfers.
1554 (sim_create_inferior): Set the PC for all processors.
1555 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1556 argument.
1557 (mips16_entry): Pass correct nr of args to store_word, load_word.
1558 (ColdReset): Cold reset all cpu's.
1559 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1560 (sim_monitor, load_memory, store_memory, signal_exception): Use
1561 `CPU' instead of STATE_CPU.
1562
1563
1564 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1565 SD or CPU_.
1566
1567 * sim-main.h (signal_exception): Add sim_cpu arg.
1568 (SignalException*): Pass both SD and CPU to signal_exception.
1569 * interp.c (signal_exception): Update.
1570
1571 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1572 Ditto
1573 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1574 address_translation): Ditto
1575 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1576
1577Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * configure: Regenerated to track ../common/aclocal.m4 changes.
1580
1581Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582
1583 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1584
1585 * mips.igen (model): Map processor names onto BFD name.
1586
1587 * sim-main.h (CPU_CIA): Delete.
1588 (SET_CIA, GET_CIA): Define
1589
1590Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1591
1592 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1593 regiser.
1594
1595 * configure.in (default_endian): Configure a big-endian simulator
1596 by default.
1597 * configure: Re-generate.
1598
1599Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1600
1601 * configure: Regenerated to track ../common/aclocal.m4 changes.
1602
1603Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1604
1605 * interp.c (sim_monitor): Handle Densan monitor outbyte
1606 and inbyte functions.
1607
16081997-12-29 Felix Lee <flee@cygnus.com>
1609
1610 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1611
1612Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1613
1614 * Makefile.in (tmp-igen): Arrange for $zero to always be
1615 reset to zero after every instruction.
1616
1617Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * configure: Regenerated to track ../common/aclocal.m4 changes.
1620 * config.in: Ditto.
1621
1622Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1623
1624 * mips.igen (MSUB): Fix to work like MADD.
1625 * gencode.c (MSUB): Similarly.
1626
1627Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1628
1629 * configure: Regenerated to track ../common/aclocal.m4 changes.
1630
1631Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1632
1633 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1634
1635Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636
1637 * sim-main.h (sim-fpu.h): Include.
1638
1639 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1640 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1641 using host independant sim_fpu module.
1642
1643Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 * interp.c (signal_exception): Report internal errors with SIGABRT
1646 not SIGQUIT.
1647
1648 * sim-main.h (C0_CONFIG): New register.
1649 (signal.h): No longer include.
1650
1651 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1652
1653Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1654
1655 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1656
1657Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1658
1659 * mips.igen: Tag vr5000 instructions.
1660 (ANDI): Was missing mipsIV model, fix assembler syntax.
1661 (do_c_cond_fmt): New function.
1662 (C.cond.fmt): Handle mips I-III which do not support CC field
1663 separatly.
1664 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1665 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1666 in IV3.2 spec.
1667 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1668 vr5000 which saves LO in a GPR separatly.
1669
1670 * configure.in (enable-sim-igen): For vr5000, select vr5000
1671 specific instructions.
1672 * configure: Re-generate.
1673
1674Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1677
1678 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1679 fmt_uninterpreted_64 bit cases to switch. Convert to
1680 fmt_formatted,
1681
1682 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1683
1684 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1685 as specified in IV3.2 spec.
1686 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1687
1688Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1689
1690 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1691 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1692 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1693 PENDING_FILL versions of instructions. Simplify.
1694 (X): New function.
1695 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1696 instructions.
1697 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1698 a signed value.
1699 (MTHI, MFHI): Disable code checking HI-LO.
1700
1701 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1702 global.
1703 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1704
1705Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 * gencode.c (build_mips16_operands): Replace IPC with cia.
1708
1709 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1710 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1711 IPC to `cia'.
1712 (UndefinedResult): Replace function with macro/function
1713 combination.
1714 (sim_engine_run): Don't save PC in IPC.
1715
1716 * sim-main.h (IPC): Delete.
1717
1718
1719 * interp.c (signal_exception, store_word, load_word,
1720 address_translation, load_memory, store_memory, cache_op,
1721 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1722 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1723 current instruction address - cia - argument.
1724 (sim_read, sim_write): Call address_translation directly.
1725 (sim_engine_run): Rename variable vaddr to cia.
1726 (signal_exception): Pass cia to sim_monitor
1727
1728 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1729 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1730 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1731
1732 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1733 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1734 SIM_ASSERT.
1735
1736 * interp.c (signal_exception): Pass restart address to
1737 sim_engine_restart.
1738
1739 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1740 idecode.o): Add dependency.
1741
1742 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1743 Delete definitions
1744 (DELAY_SLOT): Update NIA not PC with branch address.
1745 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1746
1747 * mips.igen: Use CIA not PC in branch calculations.
1748 (illegal): Call SignalException.
1749 (BEQ, ADDIU): Fix assembler.
1750
1751Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * m16.igen (JALX): Was missing.
1754
1755 * configure.in (enable-sim-igen): New configuration option.
1756 * configure: Re-generate.
1757
1758 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1759
1760 * interp.c (load_memory, store_memory): Delete parameter RAW.
1761 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1762 bypassing {load,store}_memory.
1763
1764 * sim-main.h (ByteSwapMem): Delete definition.
1765
1766 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1767
1768 * interp.c (sim_do_command, sim_commands): Delete mips specific
1769 commands. Handled by module sim-options.
1770
1771 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1772 (WITH_MODULO_MEMORY): Define.
1773
1774 * interp.c (sim_info): Delete code printing memory size.
1775
1776 * interp.c (mips_size): Nee sim_size, delete function.
1777 (power2): Delete.
1778 (monitor, monitor_base, monitor_size): Delete global variables.
1779 (sim_open, sim_close): Delete code creating monitor and other
1780 memory regions. Use sim-memopts module, via sim_do_commandf, to
1781 manage memory regions.
1782 (load_memory, store_memory): Use sim-core for memory model.
1783
1784 * interp.c (address_translation): Delete all memory map code
1785 except line forcing 32 bit addresses.
1786
1787Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1788
1789 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1790 trace options.
1791
1792 * interp.c (logfh, logfile): Delete globals.
1793 (sim_open, sim_close): Delete code opening & closing log file.
1794 (mips_option_handler): Delete -l and -n options.
1795 (OPTION mips_options): Ditto.
1796
1797 * interp.c (OPTION mips_options): Rename option trace to dinero.
1798 (mips_option_handler): Update.
1799
1800Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1801
1802 * interp.c (fetch_str): New function.
1803 (sim_monitor): Rewrite using sim_read & sim_write.
1804 (sim_open): Check magic number.
1805 (sim_open): Write monitor vectors into memory using sim_write.
1806 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1807 (sim_read, sim_write): Simplify - transfer data one byte at a
1808 time.
1809 (load_memory, store_memory): Clarify meaning of parameter RAW.
1810
1811 * sim-main.h (isHOST): Defete definition.
1812 (isTARGET): Mark as depreciated.
1813 (address_translation): Delete parameter HOST.
1814
1815 * interp.c (address_translation): Delete parameter HOST.
1816
1817Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1818
1819 * mips.igen:
1820
1821 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1822 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1823
1824Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1825
1826 * mips.igen: Add model filter field to records.
1827
1828Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1829
1830 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1831
1832 interp.c (sim_engine_run): Do not compile function sim_engine_run
1833 when WITH_IGEN == 1.
1834
1835 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1836 target architecture.
1837
1838 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1839 igen. Replace with configuration variables sim_igen_flags /
1840 sim_m16_flags.
1841
1842 * m16.igen: New file. Copy mips16 insns here.
1843 * mips.igen: From here.
1844
1845Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1846
1847 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1848 to top.
1849 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1850
1851Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1852
1853 * gencode.c (build_instruction): Follow sim_write's lead in using
1854 BigEndianMem instead of !ByteSwapMem.
1855
1856Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 * configure.in (sim_gen): Dependent on target, select type of
1859 generator. Always select old style generator.
1860
1861 configure: Re-generate.
1862
1863 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1864 targets.
1865 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1866 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1867 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1868 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1869 SIM_@sim_gen@_*, set by autoconf.
1870
1871Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1872
1873 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1874
1875 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1876 CURRENT_FLOATING_POINT instead.
1877
1878 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1879 (address_translation): Raise exception InstructionFetch when
1880 translation fails and isINSTRUCTION.
1881
1882 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1883 sim_engine_run): Change type of of vaddr and paddr to
1884 address_word.
1885 (address_translation, prefetch, load_memory, store_memory,
1886 cache_op): Change type of vAddr and pAddr to address_word.
1887
1888 * gencode.c (build_instruction): Change type of vaddr and paddr to
1889 address_word.
1890
1891Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1892
1893 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1894 macro to obtain result of ALU op.
1895
1896Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * interp.c (sim_info): Call profile_print.
1899
1900Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1901
1902 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1903
1904 * sim-main.h (WITH_PROFILE): Do not define, defined in
1905 common/sim-config.h. Use sim-profile module.
1906 (simPROFILE): Delete defintion.
1907
1908 * interp.c (PROFILE): Delete definition.
1909 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1910 (sim_close): Delete code writing profile histogram.
1911 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1912 Delete.
1913 (sim_engine_run): Delete code profiling the PC.
1914
1915Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1916
1917 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1918
1919 * interp.c (sim_monitor): Make register pointers of type
1920 unsigned_word*.
1921
1922 * sim-main.h: Make registers of type unsigned_word not
1923 signed_word.
1924
1925Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * interp.c (sync_operation): Rename from SyncOperation, make
1928 global, add SD argument.
1929 (prefetch): Rename from Prefetch, make global, add SD argument.
1930 (decode_coproc): Make global.
1931
1932 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1933
1934 * gencode.c (build_instruction): Generate DecodeCoproc not
1935 decode_coproc calls.
1936
1937 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1938 (SizeFGR): Move to sim-main.h
1939 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1940 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1941 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1942 sim-main.h.
1943 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1944 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1945 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1946 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1947 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1948 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1949
1950 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1951 exception.
1952 (sim-alu.h): Include.
1953 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1954 (sim_cia): Typedef to instruction_address.
1955
1956Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1957
1958 * Makefile.in (interp.o): Rename generated file engine.c to
1959 oengine.c.
1960
1961 * interp.c: Update.
1962
1963Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1964
1965 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1966
1967Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1968
1969 * gencode.c (build_instruction): For "FPSQRT", output correct
1970 number of arguments to Recip.
1971
1972Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1973
1974 * Makefile.in (interp.o): Depends on sim-main.h
1975
1976 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1977
1978 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1979 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1980 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1981 STATE, DSSTATE): Define
1982 (GPR, FGRIDX, ..): Define.
1983
1984 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1985 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1986 (GPR, FGRIDX, ...): Delete macros.
1987
1988 * interp.c: Update names to match defines from sim-main.h
1989
1990Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * interp.c (sim_monitor): Add SD argument.
1993 (sim_warning): Delete. Replace calls with calls to
1994 sim_io_eprintf.
1995 (sim_error): Delete. Replace calls with sim_io_error.
1996 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1997 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1998 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1999 argument.
2000 (mips_size): Rename from sim_size. Add SD argument.
2001
2002 * interp.c (simulator): Delete global variable.
2003 (callback): Delete global variable.
2004 (mips_option_handler, sim_open, sim_write, sim_read,
2005 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2006 sim_size,sim_monitor): Use sim_io_* not callback->*.
2007 (sim_open): ZALLOC simulator struct.
2008 (PROFILE): Do not define.
2009
2010Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2011
2012 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2013 support.h with corresponding code.
2014
2015 * sim-main.h (word64, uword64), support.h: Move definition to
2016 sim-main.h.
2017 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2018
2019 * support.h: Delete
2020 * Makefile.in: Update dependencies
2021 * interp.c: Do not include.
2022
2023Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2024
2025 * interp.c (address_translation, load_memory, store_memory,
2026 cache_op): Rename to from AddressTranslation et.al., make global,
2027 add SD argument
2028
2029 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2030 CacheOp): Define.
2031
2032 * interp.c (SignalException): Rename to signal_exception, make
2033 global.
2034
2035 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2036
2037 * sim-main.h (SignalException, SignalExceptionInterrupt,
2038 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2039 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2040 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2041 Define.
2042
2043 * interp.c, support.h: Use.
2044
2045Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2046
2047 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2048 to value_fpr / store_fpr. Add SD argument.
2049 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2050 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2051
2052 * sim-main.h (ValueFPR, StoreFPR): Define.
2053
2054Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2055
2056 * interp.c (sim_engine_run): Check consistency between configure
2057 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2058 and HASFPU.
2059
2060 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2061 (mips_fpu): Configure WITH_FLOATING_POINT.
2062 (mips_endian): Configure WITH_TARGET_ENDIAN.
2063 * configure: Update.
2064
2065Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2066
2067 * configure: Regenerated to track ../common/aclocal.m4 changes.
2068
2069Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2070
2071 * configure: Regenerated.
2072
2073Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2074
2075 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2076
2077Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * gencode.c (print_igen_insn_models): Assume certain architectures
2080 include all mips* instructions.
2081 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2082 instruction.
2083
2084 * Makefile.in (tmp.igen): Add target. Generate igen input from
2085 gencode file.
2086
2087 * gencode.c (FEATURE_IGEN): Define.
2088 (main): Add --igen option. Generate output in igen format.
2089 (process_instructions): Format output according to igen option.
2090 (print_igen_insn_format): New function.
2091 (print_igen_insn_models): New function.
2092 (process_instructions): Only issue warnings and ignore
2093 instructions when no FEATURE_IGEN.
2094
2095Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2096
2097 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2098 MIPS targets.
2099
2100Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2101
2102 * configure: Regenerated to track ../common/aclocal.m4 changes.
2103
2104Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2105
2106 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2107 SIM_RESERVED_BITS): Delete, moved to common.
2108 (SIM_EXTRA_CFLAGS): Update.
2109
2110Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2111
2112 * configure.in: Configure non-strict memory alignment.
2113 * configure: Regenerated to track ../common/aclocal.m4 changes.
2114
2115Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * configure: Regenerated to track ../common/aclocal.m4 changes.
2118
2119Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2120
2121 * gencode.c (SDBBP,DERET): Added (3900) insns.
2122 (RFE): Turn on for 3900.
2123 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2124 (dsstate): Made global.
2125 (SUBTARGET_R3900): Added.
2126 (CANCELDELAYSLOT): New.
2127 (SignalException): Ignore SystemCall rather than ignore and
2128 terminate. Add DebugBreakPoint handling.
2129 (decode_coproc): New insns RFE, DERET; and new registers Debug
2130 and DEPC protected by SUBTARGET_R3900.
2131 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2132 bits explicitly.
2133 * Makefile.in,configure.in: Add mips subtarget option.
2134 * configure: Update.
2135
2136Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2137
2138 * gencode.c: Add r3900 (tx39).
2139
2140
2141Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2142
2143 * gencode.c (build_instruction): Don't need to subtract 4 for
2144 JALR, just 2.
2145
2146Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2147
2148 * interp.c: Correct some HASFPU problems.
2149
2150Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * configure: Regenerated to track ../common/aclocal.m4 changes.
2153
2154Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2155
2156 * interp.c (mips_options): Fix samples option short form, should
2157 be `x'.
2158
2159Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2160
2161 * interp.c (sim_info): Enable info code. Was just returning.
2162
2163Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2166 MFC0.
2167
2168Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169
2170 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2171 constants.
2172 (build_instruction): Ditto for LL.
2173
2174Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2175
2176 * configure: Regenerated to track ../common/aclocal.m4 changes.
2177
2178Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2179
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2181 * config.in: Ditto.
2182
2183Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * interp.c (sim_open): Add call to sim_analyze_program, update
2186 call to sim_config.
2187
2188Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2189
2190 * interp.c (sim_kill): Delete.
2191 (sim_create_inferior): Add ABFD argument. Set PC from same.
2192 (sim_load): Move code initializing trap handlers from here.
2193 (sim_open): To here.
2194 (sim_load): Delete, use sim-hload.c.
2195
2196 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2197
2198Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2199
2200 * configure: Regenerated to track ../common/aclocal.m4 changes.
2201 * config.in: Ditto.
2202
2203Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2204
2205 * interp.c (sim_open): Add ABFD argument.
2206 (sim_load): Move call to sim_config from here.
2207 (sim_open): To here. Check return status.
2208
2209Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2210
2211 * gencode.c (build_instruction): Two arg MADD should
2212 not assign result to $0.
2213
2214Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2215
2216 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2217 * sim/mips/configure.in: Regenerate.
2218
2219Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2220
2221 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2222 signed8, unsigned8 et.al. types.
2223
2224 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2225 hosts when selecting subreg.
2226
2227Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2228
2229 * interp.c (sim_engine_run): Reset the ZERO register to zero
2230 regardless of FEATURE_WARN_ZERO.
2231 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2232
2233Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2234
2235 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2236 (SignalException): For BreakPoints ignore any mode bits and just
2237 save the PC.
2238 (SignalException): Always set the CAUSE register.
2239
2240Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2241
2242 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2243 exception has been taken.
2244
2245 * interp.c: Implement the ERET and mt/f sr instructions.
2246
2247Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248
2249 * interp.c (SignalException): Don't bother restarting an
2250 interrupt.
2251
2252Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253
2254 * interp.c (SignalException): Really take an interrupt.
2255 (interrupt_event): Only deliver interrupts when enabled.
2256
2257Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2258
2259 * interp.c (sim_info): Only print info when verbose.
2260 (sim_info) Use sim_io_printf for output.
2261
2262Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2263
2264 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2265 mips architectures.
2266
2267Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * interp.c (sim_do_command): Check for common commands if a
2270 simulator specific command fails.
2271
2272Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2273
2274 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2275 and simBE when DEBUG is defined.
2276
2277Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2278
2279 * interp.c (interrupt_event): New function. Pass exception event
2280 onto exception handler.
2281
2282 * configure.in: Check for stdlib.h.
2283 * configure: Regenerate.
2284
2285 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2286 variable declaration.
2287 (build_instruction): Initialize memval1.
2288 (build_instruction): Add UNUSED attribute to byte, bigend,
2289 reverse.
2290 (build_operands): Ditto.
2291
2292 * interp.c: Fix GCC warnings.
2293 (sim_get_quit_code): Delete.
2294
2295 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2296 * Makefile.in: Ditto.
2297 * configure: Re-generate.
2298
2299 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2300
2301Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2302
2303 * interp.c (mips_option_handler): New function parse argumes using
2304 sim-options.
2305 (myname): Replace with STATE_MY_NAME.
2306 (sim_open): Delete check for host endianness - performed by
2307 sim_config.
2308 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2309 (sim_open): Move much of the initialization from here.
2310 (sim_load): To here. After the image has been loaded and
2311 endianness set.
2312 (sim_open): Move ColdReset from here.
2313 (sim_create_inferior): To here.
2314 (sim_open): Make FP check less dependant on host endianness.
2315
2316 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2317 run.
2318 * interp.c (sim_set_callbacks): Delete.
2319
2320 * interp.c (membank, membank_base, membank_size): Replace with
2321 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2322 (sim_open): Remove call to callback->init. gdb/run do this.
2323
2324 * interp.c: Update
2325
2326 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2327
2328 * interp.c (big_endian_p): Delete, replaced by
2329 current_target_byte_order.
2330
2331Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2332
2333 * interp.c (host_read_long, host_read_word, host_swap_word,
2334 host_swap_long): Delete. Using common sim-endian.
2335 (sim_fetch_register, sim_store_register): Use H2T.
2336 (pipeline_ticks): Delete. Handled by sim-events.
2337 (sim_info): Update.
2338 (sim_engine_run): Update.
2339
2340Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2343 reason from here.
2344 (SignalException): To here. Signal using sim_engine_halt.
2345 (sim_stop_reason): Delete, moved to common.
2346
2347Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2348
2349 * interp.c (sim_open): Add callback argument.
2350 (sim_set_callbacks): Delete SIM_DESC argument.
2351 (sim_size): Ditto.
2352
2353Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * Makefile.in (SIM_OBJS): Add common modules.
2356
2357 * interp.c (sim_set_callbacks): Also set SD callback.
2358 (set_endianness, xfer_*, swap_*): Delete.
2359 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2360 Change to functions using sim-endian macros.
2361 (control_c, sim_stop): Delete, use common version.
2362 (simulate): Convert into.
2363 (sim_engine_run): This function.
2364 (sim_resume): Delete.
2365
2366 * interp.c (simulation): New variable - the simulator object.
2367 (sim_kind): Delete global - merged into simulation.
2368 (sim_load): Cleanup. Move PC assignment from here.
2369 (sim_create_inferior): To here.
2370
2371 * sim-main.h: New file.
2372 * interp.c (sim-main.h): Include.
2373
2374Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2375
2376 * configure: Regenerated to track ../common/aclocal.m4 changes.
2377
2378Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2379
2380 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2381
2382Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2383
2384 * gencode.c (build_instruction): DIV instructions: check
2385 for division by zero and integer overflow before using
2386 host's division operation.
2387
2388Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2389
2390 * Makefile.in (SIM_OBJS): Add sim-load.o.
2391 * interp.c: #include bfd.h.
2392 (target_byte_order): Delete.
2393 (sim_kind, myname, big_endian_p): New static locals.
2394 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2395 after argument parsing. Recognize -E arg, set endianness accordingly.
2396 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2397 load file into simulator. Set PC from bfd.
2398 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2399 (set_endianness): Use big_endian_p instead of target_byte_order.
2400
2401Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * interp.c (sim_size): Delete prototype - conflicts with
2404 definition in remote-sim.h. Correct definition.
2405
2406Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2407
2408 * configure: Regenerated to track ../common/aclocal.m4 changes.
2409 * config.in: Ditto.
2410
2411Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2412
2413 * interp.c (sim_open): New arg `kind'.
2414
2415 * configure: Regenerated to track ../common/aclocal.m4 changes.
2416
2417Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2418
2419 * configure: Regenerated to track ../common/aclocal.m4 changes.
2420
2421Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2422
2423 * interp.c (sim_open): Set optind to 0 before calling getopt.
2424
2425Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2426
2427 * configure: Regenerated to track ../common/aclocal.m4 changes.
2428
2429Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2430
2431 * interp.c : Replace uses of pr_addr with pr_uword64
2432 where the bit length is always 64 independent of SIM_ADDR.
2433 (pr_uword64) : added.
2434
2435Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2436
2437 * configure: Re-generate.
2438
2439Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2440
2441 * configure: Regenerate to track ../common/aclocal.m4 changes.
2442
2443Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2444
2445 * interp.c (sim_open): New SIM_DESC result. Argument is now
2446 in argv form.
2447 (other sim_*): New SIM_DESC argument.
2448
2449Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2450
2451 * interp.c: Fix printing of addresses for non-64-bit targets.
2452 (pr_addr): Add function to print address based on size.
2453
2454Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2455
2456 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2457
2458Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2459
2460 * gencode.c (build_mips16_operands): Correct computation of base
2461 address for extended PC relative instruction.
2462
2463Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2464
2465 * interp.c (mips16_entry): Add support for floating point cases.
2466 (SignalException): Pass floating point cases to mips16_entry.
2467 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2468 registers.
2469 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2470 or fmt_word.
2471 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2472 and then set the state to fmt_uninterpreted.
2473 (COP_SW): Temporarily set the state to fmt_word while calling
2474 ValueFPR.
2475
2476Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2477
2478 * gencode.c (build_instruction): The high order may be set in the
2479 comparison flags at any ISA level, not just ISA 4.
2480
2481Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2482
2483 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2484 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2485 * configure.in: sinclude ../common/aclocal.m4.
2486 * configure: Regenerated.
2487
2488Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2489
2490 * configure: Rebuild after change to aclocal.m4.
2491
2492Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2493
2494 * configure configure.in Makefile.in: Update to new configure
2495 scheme which is more compatible with WinGDB builds.
2496 * configure.in: Improve comment on how to run autoconf.
2497 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2498 * Makefile.in: Use autoconf substitution to install common
2499 makefile fragment.
2500
2501Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2502
2503 * gencode.c (build_instruction): Use BigEndianCPU instead of
2504 ByteSwapMem.
2505
2506Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2507
2508 * interp.c (sim_monitor): Make output to stdout visible in
2509 wingdb's I/O log window.
2510
2511Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2512
2513 * support.h: Undo previous change to SIGTRAP
2514 and SIGQUIT values.
2515
2516Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2517
2518 * interp.c (store_word, load_word): New static functions.
2519 (mips16_entry): New static function.
2520 (SignalException): Look for mips16 entry and exit instructions.
2521 (simulate): Use the correct index when setting fpr_state after
2522 doing a pending move.
2523
2524Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2525
2526 * interp.c: Fix byte-swapping code throughout to work on
2527 both little- and big-endian hosts.
2528
2529Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2530
2531 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2532 with gdb/config/i386/xm-windows.h.
2533
2534Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2535
2536 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2537 that messes up arithmetic shifts.
2538
2539Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2540
2541 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2542 SIGTRAP and SIGQUIT for _WIN32.
2543
2544Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2545
2546 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2547 force a 64 bit multiplication.
2548 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2549 destination register is 0, since that is the default mips16 nop
2550 instruction.
2551
2552Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2553
2554 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2555 (build_endian_shift): Don't check proc64.
2556 (build_instruction): Always set memval to uword64. Cast op2 to
2557 uword64 when shifting it left in memory instructions. Always use
2558 the same code for stores--don't special case proc64.
2559
2560 * gencode.c (build_mips16_operands): Fix base PC value for PC
2561 relative operands.
2562 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2563 jal instruction.
2564 * interp.c (simJALDELAYSLOT): Define.
2565 (JALDELAYSLOT): Define.
2566 (INDELAYSLOT, INJALDELAYSLOT): Define.
2567 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2568
2569Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2570
2571 * interp.c (sim_open): add flush_cache as a PMON routine
2572 (sim_monitor): handle flush_cache by ignoring it
2573
2574Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2575
2576 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2577 BigEndianMem.
2578 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2579 (BigEndianMem): Rename to ByteSwapMem and change sense.
2580 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2581 BigEndianMem references to !ByteSwapMem.
2582 (set_endianness): New function, with prototype.
2583 (sim_open): Call set_endianness.
2584 (sim_info): Use simBE instead of BigEndianMem.
2585 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2586 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2587 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2588 ifdefs, keeping the prototype declaration.
2589 (swap_word): Rewrite correctly.
2590 (ColdReset): Delete references to CONFIG. Delete endianness related
2591 code; moved to set_endianness.
2592
2593Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2594
2595 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2596 * interp.c (CHECKHILO): Define away.
2597 (simSIGINT): New macro.
2598 (membank_size): Increase from 1MB to 2MB.
2599 (control_c): New function.
2600 (sim_resume): Rename parameter signal to signal_number. Add local
2601 variable prev. Call signal before and after simulate.
2602 (sim_stop_reason): Add simSIGINT support.
2603 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2604 functions always.
2605 (sim_warning): Delete call to SignalException. Do call printf_filtered
2606 if logfh is NULL.
2607 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2608 a call to sim_warning.
2609
2610Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2611
2612 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2613 16 bit instructions.
2614
2615Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2616
2617 Add support for mips16 (16 bit MIPS implementation):
2618 * gencode.c (inst_type): Add mips16 instruction encoding types.
2619 (GETDATASIZEINSN): Define.
2620 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2621 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2622 mtlo.
2623 (MIPS16_DECODE): New table, for mips16 instructions.
2624 (bitmap_val): New static function.
2625 (struct mips16_op): Define.
2626 (mips16_op_table): New table, for mips16 operands.
2627 (build_mips16_operands): New static function.
2628 (process_instructions): If PC is odd, decode a mips16
2629 instruction. Break out instruction handling into new
2630 build_instruction function.
2631 (build_instruction): New static function, broken out of
2632 process_instructions. Check modifiers rather than flags for SHIFT
2633 bit count and m[ft]{hi,lo} direction.
2634 (usage): Pass program name to fprintf.
2635 (main): Remove unused variable this_option_optind. Change
2636 ``*loptarg++'' to ``loptarg++''.
2637 (my_strtoul): Parenthesize && within ||.
2638 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2639 (simulate): If PC is odd, fetch a 16 bit instruction, and
2640 increment PC by 2 rather than 4.
2641 * configure.in: Add case for mips16*-*-*.
2642 * configure: Rebuild.
2643
2644Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2645
2646 * interp.c: Allow -t to enable tracing in standalone simulator.
2647 Fix garbage output in trace file and error messages.
2648
2649Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2650
2651 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2652 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2653 * configure.in: Simplify using macros in ../common/aclocal.m4.
2654 * configure: Regenerated.
2655 * tconfig.in: New file.
2656
2657Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2658
2659 * interp.c: Fix bugs in 64-bit port.
2660 Use ansi function declarations for msvc compiler.
2661 Initialize and test file pointer in trace code.
2662 Prevent duplicate definition of LAST_EMED_REGNUM.
2663
2664Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2665
2666 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2667
2668Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2669
2670 * interp.c (SignalException): Check for explicit terminating
2671 breakpoint value.
2672 * gencode.c: Pass instruction value through SignalException()
2673 calls for Trap, Breakpoint and Syscall.
2674
2675Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2676
2677 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2678 only used on those hosts that provide it.
2679 * configure.in: Add sqrt() to list of functions to be checked for.
2680 * config.in: Re-generated.
2681 * configure: Re-generated.
2682
2683Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2684
2685 * gencode.c (process_instructions): Call build_endian_shift when
2686 expanding STORE RIGHT, to fix swr.
2687 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2688 clear the high bits.
2689 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2690 Fix float to int conversions to produce signed values.
2691
2692Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2693
2694 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2695 (process_instructions): Correct handling of nor instruction.
2696 Correct shift count for 32 bit shift instructions. Correct sign
2697 extension for arithmetic shifts to not shift the number of bits in
2698 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2699 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2700 Fix madd.
2701 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2702 It's OK to have a mult follow a mult. What's not OK is to have a
2703 mult follow an mfhi.
2704 (Convert): Comment out incorrect rounding code.
2705
2706Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2707
2708 * interp.c (sim_monitor): Improved monitor printf
2709 simulation. Tidied up simulator warnings, and added "--log" option
2710 for directing warning message output.
2711 * gencode.c: Use sim_warning() rather than WARNING macro.
2712
2713Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2714
2715 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2716 getopt1.o, rather than on gencode.c. Link objects together.
2717 Don't link against -liberty.
2718 (gencode.o, getopt.o, getopt1.o): New targets.
2719 * gencode.c: Include <ctype.h> and "ansidecl.h".
2720 (AND): Undefine after including "ansidecl.h".
2721 (ULONG_MAX): Define if not defined.
2722 (OP_*): Don't define macros; now defined in opcode/mips.h.
2723 (main): Call my_strtoul rather than strtoul.
2724 (my_strtoul): New static function.
2725
2726Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2727
2728 * gencode.c (process_instructions): Generate word64 and uword64
2729 instead of `long long' and `unsigned long long' data types.
2730 * interp.c: #include sysdep.h to get signals, and define default
2731 for SIGBUS.
2732 * (Convert): Work around for Visual-C++ compiler bug with type
2733 conversion.
2734 * support.h: Make things compile under Visual-C++ by using
2735 __int64 instead of `long long'. Change many refs to long long
2736 into word64/uword64 typedefs.
2737
2738Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2739
2740 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2741 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2742 (docdir): Removed.
2743 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2744 (AC_PROG_INSTALL): Added.
2745 (AC_PROG_CC): Moved to before configure.host call.
2746 * configure: Rebuilt.
2747
2748Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2749
2750 * configure.in: Define @SIMCONF@ depending on mips target.
2751 * configure: Rebuild.
2752 * Makefile.in (run): Add @SIMCONF@ to control simulator
2753 construction.
2754 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2755 * interp.c: Remove some debugging, provide more detailed error
2756 messages, update memory accesses to use LOADDRMASK.
2757
2758Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2759
2760 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2761 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2762 stamp-h.
2763 * configure: Rebuild.
2764 * config.in: New file, generated by autoheader.
2765 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2766 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2767 HAVE_ANINT and HAVE_AINT, as appropriate.
2768 * Makefile.in (run): Use @LIBS@ rather than -lm.
2769 (interp.o): Depend upon config.h.
2770 (Makefile): Just rebuild Makefile.
2771 (clean): Remove stamp-h.
2772 (mostlyclean): Make the same as clean, not as distclean.
2773 (config.h, stamp-h): New targets.
2774
2775Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2776
2777 * interp.c (ColdReset): Fix boolean test. Make all simulator
2778 globals static.
2779
2780Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2781
2782 * interp.c (xfer_direct_word, xfer_direct_long,
2783 swap_direct_word, swap_direct_long, xfer_big_word,
2784 xfer_big_long, xfer_little_word, xfer_little_long,
2785 swap_word,swap_long): Added.
2786 * interp.c (ColdReset): Provide function indirection to
2787 host<->simulated_target transfer routines.
2788 * interp.c (sim_store_register, sim_fetch_register): Updated to
2789 make use of indirected transfer routines.
2790
2791Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2792
2793 * gencode.c (process_instructions): Ensure FP ABS instruction
2794 recognised.
2795 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2796 system call support.
2797
2798Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2799
2800 * interp.c (sim_do_command): Complain if callback structure not
2801 initialised.
2802
2803Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2804
2805 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2806 support for Sun hosts.
2807 * Makefile.in (gencode): Ensure the host compiler and libraries
2808 used for cross-hosted build.
2809
2810Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2811
2812 * interp.c, gencode.c: Some more (TODO) tidying.
2813
2814Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2815
2816 * gencode.c, interp.c: Replaced explicit long long references with
2817 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2818 * support.h (SET64LO, SET64HI): Macros added.
2819
2820Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2821
2822 * configure: Regenerate with autoconf 2.7.
2823
2824Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2825
2826 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2827 * support.h: Remove superfluous "1" from #if.
2828 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2829
2830Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2831
2832 * interp.c (StoreFPR): Control UndefinedResult() call on
2833 WARN_RESULT manifest.
2834
2835Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2836
2837 * gencode.c: Tidied instruction decoding, and added FP instruction
2838 support.
2839
2840 * interp.c: Added dineroIII, and BSD profiling support. Also
2841 run-time FP handling.
2842
2843Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2844
2845 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2846 gencode.c, interp.c, support.h: created.
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