]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/mmc.c
mmc: set correct block size value in bfin sdh driver
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF
8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF
14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF
20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK
25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK
38 else
39 wp = 0;
40 }
d23d8d7e
NK
41
42 return wp;
43}
44
cee9ab7c
JH
45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB
47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR
55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR
61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR
88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF
106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR
109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR
112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR
120
121 do {
122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK
123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK
130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK
133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9
RR
137
138 udelay(1000);
139
5d4fc8d9
RR
140 } while (timeout--);
141
5db2fe3a
RR
142#ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
145#endif
5b0c942f 146 if (timeout <= 0) {
56196826 147#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 148 printf("Timeout waiting card ready\n");
56196826 149#endif
5d4fc8d9
RR
150 return TIMEOUT;
151 }
6b2221b0
AG
152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
153 return SWITCH_ERR;
5d4fc8d9
RR
154
155 return 0;
156}
157
da61fa5f 158int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF
159{
160 struct mmc_cmd cmd;
161
d22e3d46
JC
162 if (mmc->card_caps & MMC_MODE_DDR_52MHz)
163 return 0;
164
272cc70b
AF
165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
167 cmd.cmdarg = len;
272cc70b
AF
168
169 return mmc_send_cmd(mmc, &cmd, NULL);
170}
171
172struct mmc *find_mmc_device(int dev_num)
173{
174 struct mmc *m;
175 struct list_head *entry;
176
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
179
180 if (m->block_dev.dev == dev_num)
181 return m;
182 }
183
56196826 184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 185 printf("MMC Device %d not found\n", dev_num);
56196826 186#endif
272cc70b
AF
187
188 return NULL;
189}
190
ff8fef56 191static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 192 lbaint_t blkcnt)
272cc70b
AF
193{
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
4a1a06bc
AS
197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF
201
202 if (mmc->high_capacity)
4a1a06bc 203 cmd.cmdarg = start;
272cc70b 204 else
4a1a06bc 205 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF
206
207 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF
208
209 data.dest = dst;
4a1a06bc 210 data.blocks = blkcnt;
272cc70b
AF
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
4a1a06bc
AS
214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
272cc70b 216
4a1a06bc
AS
217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 222#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 223 printf("mmc fail to send stop cmd\n");
56196826 224#endif
4a1a06bc
AS
225 return 0;
226 }
272cc70b
AF
227 }
228
4a1a06bc 229 return blkcnt;
272cc70b
AF
230}
231
ff8fef56 232static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 233{
4a1a06bc
AS
234 lbaint_t cur, blocks_todo = blkcnt;
235
236 if (blkcnt == 0)
237 return 0;
272cc70b 238
4a1a06bc 239 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF
240 if (!mmc)
241 return 0;
242
d2bf29e3 243 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 244#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 246 start + blkcnt, mmc->block_dev.lba);
56196826 247#endif
d2bf29e3
LW
248 return 0;
249 }
272cc70b 250
4a1a06bc 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 252 return 0;
272cc70b 253
4a1a06bc 254 do {
93bfd616
PA
255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF
263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF
268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF
277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF
289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF
298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB
306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 315 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF
316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC
338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF
346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC
353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF
357 int err;
358
e9550449
CLC
359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
93bfd616 364 (mmc->cfg->voltages &
e9550449
CLC
365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
93bfd616 368 if (mmc->cfg->host_caps & MMC_MODE_HC)
e9550449
CLC
369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
750121c3 378static int mmc_send_op_cond(struct mmc *mmc)
e9550449
CLC
379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF
383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC
387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC
401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC
407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF
411 if (err)
412 return err;
e9550449
CLC
413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC
422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF
431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF
434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF
440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF
453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF
462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR
464 int timeout = 1000;
465 int ret;
272cc70b
AF
466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR
470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR
473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK
476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR
478
479 return ret;
480
272cc70b
AF
481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF
486 char cardtype;
487 int err;
488
489 mmc->card_caps = 0;
490
d52ebf10
TC
491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF
494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
272cc70b
AF
498 err = mmc_send_ext_csd(mmc, ext_csd);
499
500 if (err)
501 return err;
502
0560db18 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF
504
505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
506
507 if (err)
6b2221b0 508 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF
509
510 /* Now check to see that it worked */
511 err = mmc_send_ext_csd(mmc, ext_csd);
512
513 if (err)
514 return err;
515
516 /* No high-speed support */
0560db18 517 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF
518 return 0;
519
520 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46
JC
521 if (cardtype & EXT_CSD_CARD_TYPE_52) {
522 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
523 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 524 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 525 } else {
272cc70b 526 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 527 }
272cc70b
AF
528
529 return 0;
530}
531
f866a46d
SW
532static int mmc_set_capacity(struct mmc *mmc, int part_num)
533{
534 switch (part_num) {
535 case 0:
536 mmc->capacity = mmc->capacity_user;
537 break;
538 case 1:
539 case 2:
540 mmc->capacity = mmc->capacity_boot;
541 break;
542 case 3:
543 mmc->capacity = mmc->capacity_rpmb;
544 break;
545 case 4:
546 case 5:
547 case 6:
548 case 7:
549 mmc->capacity = mmc->capacity_gp[part_num - 4];
550 break;
551 default:
552 return -1;
553 }
554
555 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
556
557 return 0;
558}
559
d2356284
SW
560int mmc_select_hwpart(int dev_num, int hwpart)
561{
562 struct mmc *mmc = find_mmc_device(dev_num);
563 int ret;
564
565 if (!mmc)
d4622df3 566 return -ENODEV;
d2356284
SW
567
568 if (mmc->part_num == hwpart)
569 return 0;
570
571 if (mmc->part_config == MMCPART_NOAVAILABLE) {
572 printf("Card doesn't support part_switch\n");
d4622df3 573 return -EMEDIUMTYPE;
d2356284
SW
574 }
575
576 ret = mmc_switch_part(dev_num, hwpart);
577 if (ret)
d4622df3 578 return ret;
d2356284
SW
579
580 mmc->part_num = hwpart;
581
582 return 0;
583}
584
585
bc897b1d
LW
586int mmc_switch_part(int dev_num, unsigned int part_num)
587{
588 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 589 int ret;
bc897b1d
LW
590
591 if (!mmc)
592 return -1;
593
f866a46d
SW
594 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
595 (mmc->part_config & ~PART_ACCESS_MASK)
596 | (part_num & PART_ACCESS_MASK));
597 if (ret)
598 return ret;
599
600 return mmc_set_capacity(mmc, part_num);
bc897b1d
LW
601}
602
48972d90
TR
603int mmc_getcd(struct mmc *mmc)
604{
605 int cd;
606
607 cd = board_mmc_getcd(mmc);
608
d4e1da4e 609 if (cd < 0) {
93bfd616
PA
610 if (mmc->cfg->ops->getcd)
611 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK
612 else
613 cd = 1;
614 }
48972d90
TR
615
616 return cd;
617}
618
fdbb873e 619static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF
620{
621 struct mmc_cmd cmd;
622 struct mmc_data data;
623
624 /* Switch the frequency */
625 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
626 cmd.resp_type = MMC_RSP_R1;
627 cmd.cmdarg = (mode << 31) | 0xffffff;
628 cmd.cmdarg &= ~(0xf << (group * 4));
629 cmd.cmdarg |= value << (group * 4);
272cc70b
AF
630
631 data.dest = (char *)resp;
632 data.blocksize = 64;
633 data.blocks = 1;
634 data.flags = MMC_DATA_READ;
635
636 return mmc_send_cmd(mmc, &cmd, &data);
637}
638
639
fdbb873e 640static int sd_change_freq(struct mmc *mmc)
272cc70b
AF
641{
642 int err;
643 struct mmc_cmd cmd;
f781dd38
A
644 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
645 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF
646 struct mmc_data data;
647 int timeout;
648
649 mmc->card_caps = 0;
650
d52ebf10
TC
651 if (mmc_host_is_spi(mmc))
652 return 0;
653
272cc70b
AF
654 /* Read the SCR to find out if this card supports higher speeds */
655 cmd.cmdidx = MMC_CMD_APP_CMD;
656 cmd.resp_type = MMC_RSP_R1;
657 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
658
659 err = mmc_send_cmd(mmc, &cmd, NULL);
660
661 if (err)
662 return err;
663
664 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
665 cmd.resp_type = MMC_RSP_R1;
666 cmd.cmdarg = 0;
272cc70b
AF
667
668 timeout = 3;
669
670retry_scr:
f781dd38 671 data.dest = (char *)scr;
272cc70b
AF
672 data.blocksize = 8;
673 data.blocks = 1;
674 data.flags = MMC_DATA_READ;
675
676 err = mmc_send_cmd(mmc, &cmd, &data);
677
678 if (err) {
679 if (timeout--)
680 goto retry_scr;
681
682 return err;
683 }
684
4e3d89ba
YK
685 mmc->scr[0] = __be32_to_cpu(scr[0]);
686 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF
687
688 switch ((mmc->scr[0] >> 24) & 0xf) {
689 case 0:
690 mmc->version = SD_VERSION_1_0;
691 break;
692 case 1:
693 mmc->version = SD_VERSION_1_10;
694 break;
695 case 2:
696 mmc->version = SD_VERSION_2;
1741c64d
JC
697 if ((mmc->scr[0] >> 15) & 0x1)
698 mmc->version = SD_VERSION_3;
272cc70b
AF
699 break;
700 default:
701 mmc->version = SD_VERSION_1_0;
702 break;
703 }
704
b44c7083
AS
705 if (mmc->scr[0] & SD_DATA_4BIT)
706 mmc->card_caps |= MMC_MODE_4BIT;
707
272cc70b
AF
708 /* Version 1.0 doesn't support switching */
709 if (mmc->version == SD_VERSION_1_0)
710 return 0;
711
712 timeout = 4;
713 while (timeout--) {
714 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 715 (u8 *)switch_status);
272cc70b
AF
716
717 if (err)
718 return err;
719
720 /* The high-speed function is busy. Try again */
4e3d89ba 721 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF
722 break;
723 }
724
272cc70b 725 /* If high-speed isn't supported, we return */
4e3d89ba 726 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF
727 return 0;
728
2c3fbf4c
ML
729 /*
730 * If the host doesn't support SD_HIGHSPEED, do not switch card to
731 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
732 * This can avoid furthur problem when the card runs in different
733 * mode between the host.
734 */
93bfd616
PA
735 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
736 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML
737 return 0;
738
f781dd38 739 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF
740
741 if (err)
742 return err;
743
4e3d89ba 744 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF
745 mmc->card_caps |= MMC_MODE_HS;
746
747 return 0;
748}
749
750/* frequency bases */
751/* divided by 10 to be nice to platforms without floating point */
5f837c2c 752static const int fbase[] = {
272cc70b
AF
753 10000,
754 100000,
755 1000000,
756 10000000,
757};
758
759/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
760 * to platforms without floating point.
761 */
5f837c2c 762static const int multipliers[] = {
272cc70b
AF
763 0, /* reserved */
764 10,
765 12,
766 13,
767 15,
768 20,
769 25,
770 30,
771 35,
772 40,
773 45,
774 50,
775 55,
776 60,
777 70,
778 80,
779};
780
fdbb873e 781static void mmc_set_ios(struct mmc *mmc)
272cc70b 782{
93bfd616
PA
783 if (mmc->cfg->ops->set_ios)
784 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF
785}
786
787void mmc_set_clock(struct mmc *mmc, uint clock)
788{
93bfd616
PA
789 if (clock > mmc->cfg->f_max)
790 clock = mmc->cfg->f_max;
272cc70b 791
93bfd616
PA
792 if (clock < mmc->cfg->f_min)
793 clock = mmc->cfg->f_min;
272cc70b
AF
794
795 mmc->clock = clock;
796
797 mmc_set_ios(mmc);
798}
799
fdbb873e 800static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF
801{
802 mmc->bus_width = width;
803
804 mmc_set_ios(mmc);
805}
806
fdbb873e 807static int mmc_startup(struct mmc *mmc)
272cc70b 808{
f866a46d 809 int err, i;
272cc70b 810 uint mult, freq;
639b7827 811 u64 cmult, csize, capacity;
272cc70b 812 struct mmc_cmd cmd;
8bfa195e
SG
813 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
814 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 815 int timeout = 1000;
272cc70b 816
d52ebf10
TC
817#ifdef CONFIG_MMC_SPI_CRC_ON
818 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
819 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
820 cmd.resp_type = MMC_RSP_R1;
821 cmd.cmdarg = 1;
d52ebf10
TC
822 err = mmc_send_cmd(mmc, &cmd, NULL);
823
824 if (err)
825 return err;
826 }
827#endif
828
272cc70b 829 /* Put the Card in Identify Mode */
d52ebf10
TC
830 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
831 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF
832 cmd.resp_type = MMC_RSP_R2;
833 cmd.cmdarg = 0;
272cc70b
AF
834
835 err = mmc_send_cmd(mmc, &cmd, NULL);
836
837 if (err)
838 return err;
839
840 memcpy(mmc->cid, cmd.response, 16);
841
842 /*
843 * For MMC cards, set the Relative Address.
844 * For SD cards, get the Relatvie Address.
845 * This also puts the cards into Standby State
846 */
d52ebf10
TC
847 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
848 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
849 cmd.cmdarg = mmc->rca << 16;
850 cmd.resp_type = MMC_RSP_R6;
272cc70b 851
d52ebf10 852 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 853
d52ebf10
TC
854 if (err)
855 return err;
272cc70b 856
d52ebf10
TC
857 if (IS_SD(mmc))
858 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
859 }
272cc70b
AF
860
861 /* Get the Card-Specific Data */
862 cmd.cmdidx = MMC_CMD_SEND_CSD;
863 cmd.resp_type = MMC_RSP_R2;
864 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
865
866 err = mmc_send_cmd(mmc, &cmd, NULL);
867
5d4fc8d9
RR
868 /* Waiting for the ready status */
869 mmc_send_status(mmc, timeout);
870
272cc70b
AF
871 if (err)
872 return err;
873
998be3dd
RV
874 mmc->csd[0] = cmd.response[0];
875 mmc->csd[1] = cmd.response[1];
876 mmc->csd[2] = cmd.response[2];
877 mmc->csd[3] = cmd.response[3];
272cc70b
AF
878
879 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 880 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF
881
882 switch (version) {
883 case 0:
884 mmc->version = MMC_VERSION_1_2;
885 break;
886 case 1:
887 mmc->version = MMC_VERSION_1_4;
888 break;
889 case 2:
890 mmc->version = MMC_VERSION_2_2;
891 break;
892 case 3:
893 mmc->version = MMC_VERSION_3;
894 break;
895 case 4:
896 mmc->version = MMC_VERSION_4;
897 break;
898 default:
899 mmc->version = MMC_VERSION_1_2;
900 break;
901 }
902 }
903
904 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV
905 freq = fbase[(cmd.response[0] & 0x7)];
906 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF
907
908 mmc->tran_speed = freq * mult;
909
ab71188c 910 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 911 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF
912
913 if (IS_SD(mmc))
914 mmc->write_bl_len = mmc->read_bl_len;
915 else
998be3dd 916 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF
917
918 if (mmc->high_capacity) {
919 csize = (mmc->csd[1] & 0x3f) << 16
920 | (mmc->csd[2] & 0xffff0000) >> 16;
921 cmult = 8;
922 } else {
923 csize = (mmc->csd[1] & 0x3ff) << 2
924 | (mmc->csd[2] & 0xc0000000) >> 30;
925 cmult = (mmc->csd[2] & 0x00038000) >> 15;
926 }
927
f866a46d
SW
928 mmc->capacity_user = (csize + 1) << (cmult + 2);
929 mmc->capacity_user *= mmc->read_bl_len;
930 mmc->capacity_boot = 0;
931 mmc->capacity_rpmb = 0;
932 for (i = 0; i < 4; i++)
933 mmc->capacity_gp[i] = 0;
272cc70b 934
8bfa195e
SG
935 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
936 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 937
8bfa195e
SG
938 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
939 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 940
ab71188c
MN
941 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
942 cmd.cmdidx = MMC_CMD_SET_DSR;
943 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
944 cmd.resp_type = MMC_RSP_NONE;
945 if (mmc_send_cmd(mmc, &cmd, NULL))
946 printf("MMC: SET_DSR failed\n");
947 }
948
272cc70b 949 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC
950 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
951 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 952 cmd.resp_type = MMC_RSP_R1;
d52ebf10 953 cmd.cmdarg = mmc->rca << 16;
d52ebf10 954 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 955
d52ebf10
TC
956 if (err)
957 return err;
958 }
272cc70b 959
e6f99a56
LW
960 /*
961 * For SD, its erase group is always one sector
962 */
963 mmc->erase_grp_size = 1;
bc897b1d 964 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG
965 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
966 /* check ext_csd version and capacity */
967 err = mmc_send_ext_csd(mmc, ext_csd);
fdbb873e 968 if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
639b7827
YS
969 /*
970 * According to the JEDEC Standard, the value of
971 * ext_csd's capacity is valid if the value is more
972 * than 2GB
973 */
0560db18
LW
974 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
975 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
976 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
977 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 978 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 979 if ((capacity >> 20) > 2 * 1024)
f866a46d 980 mmc->capacity_user = capacity;
d23e2c09 981 }
bc897b1d 982
64f4a619
JC
983 switch (ext_csd[EXT_CSD_REV]) {
984 case 1:
985 mmc->version = MMC_VERSION_4_1;
986 break;
987 case 2:
988 mmc->version = MMC_VERSION_4_2;
989 break;
990 case 3:
991 mmc->version = MMC_VERSION_4_3;
992 break;
993 case 5:
994 mmc->version = MMC_VERSION_4_41;
995 break;
996 case 6:
997 mmc->version = MMC_VERSION_4_5;
998 break;
999 }
1000
e6f99a56 1001 /*
1937e5aa
OM
1002 * Host needs to enable ERASE_GRP_DEF bit if device is
1003 * partitioned. This bit will be lost every time after a reset
1004 * or power off. This will affect erase size.
e6f99a56 1005 */
1937e5aa
OM
1006 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1007 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
1008 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1009 EXT_CSD_ERASE_GROUP_DEF, 1);
1010
1011 if (err)
1012 return err;
1013
1014 /* Read out group size from ext_csd */
0560db18 1015 mmc->erase_grp_size =
8bfa195e
SG
1016 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
1017 MMC_MAX_BLOCK_LEN * 1024;
1018 } else {
1937e5aa 1019 /* Calculate the group size from the csd value. */
e6f99a56
LW
1020 int erase_gsz, erase_gmul;
1021 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1022 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1023 mmc->erase_grp_size = (erase_gsz + 1)
1024 * (erase_gmul + 1);
1025 }
1026
bc897b1d 1027 /* store the partition info of emmc */
8948ea83
SW
1028 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1029 ext_csd[EXT_CSD_BOOT_MULT])
0560db18 1030 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
f866a46d
SW
1031
1032 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1033
1034 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1035
1036 for (i = 0; i < 4; i++) {
1037 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1038 mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
1039 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1040 mmc->capacity_gp[i] *=
1041 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1042 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1043 }
d23e2c09
SG
1044 }
1045
f866a46d
SW
1046 err = mmc_set_capacity(mmc, mmc->part_num);
1047 if (err)
1048 return err;
1049
272cc70b
AF
1050 if (IS_SD(mmc))
1051 err = sd_change_freq(mmc);
1052 else
1053 err = mmc_change_freq(mmc);
1054
1055 if (err)
1056 return err;
1057
1058 /* Restrict card's capabilities by what the host can do */
93bfd616 1059 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF
1060
1061 if (IS_SD(mmc)) {
1062 if (mmc->card_caps & MMC_MODE_4BIT) {
1063 cmd.cmdidx = MMC_CMD_APP_CMD;
1064 cmd.resp_type = MMC_RSP_R1;
1065 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1066
1067 err = mmc_send_cmd(mmc, &cmd, NULL);
1068 if (err)
1069 return err;
1070
1071 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1072 cmd.resp_type = MMC_RSP_R1;
1073 cmd.cmdarg = 2;
272cc70b
AF
1074 err = mmc_send_cmd(mmc, &cmd, NULL);
1075 if (err)
1076 return err;
1077
1078 mmc_set_bus_width(mmc, 4);
1079 }
1080
1081 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1082 mmc->tran_speed = 50000000;
272cc70b 1083 else
ad5fd922 1084 mmc->tran_speed = 25000000;
272cc70b 1085 } else {
7798f6db
AF
1086 int idx;
1087
1088 /* An array of possible bus widths in order of preference */
1089 static unsigned ext_csd_bits[] = {
d22e3d46
JC
1090 EXT_CSD_DDR_BUS_WIDTH_8,
1091 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF
1092 EXT_CSD_BUS_WIDTH_8,
1093 EXT_CSD_BUS_WIDTH_4,
1094 EXT_CSD_BUS_WIDTH_1,
1095 };
1096
1097 /* An array to map CSD bus widths to host cap bits */
1098 static unsigned ext_to_hostcaps[] = {
d22e3d46
JC
1099 [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
1100 [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
7798f6db
AF
1101 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1102 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1103 };
1104
1105 /* An array to map chosen bus width to an integer */
1106 static unsigned widths[] = {
d22e3d46 1107 8, 4, 8, 4, 1,
7798f6db
AF
1108 };
1109
1110 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1111 unsigned int extw = ext_csd_bits[idx];
1112
1113 /*
1114 * Check to make sure the controller supports
1115 * this bus width, if it's more than 1
1116 */
1117 if (extw != EXT_CSD_BUS_WIDTH_1 &&
93bfd616 1118 !(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
7798f6db
AF
1119 continue;
1120
272cc70b 1121 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1122 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF
1123
1124 if (err)
4137894e 1125 continue;
272cc70b 1126
7798f6db 1127 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW
1128
1129 err = mmc_send_ext_csd(mmc, test_csd);
1130 if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
1131 == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
1132 && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
1133 == test_csd[EXT_CSD_ERASE_GROUP_DEF] \
1134 && ext_csd[EXT_CSD_REV] \
1135 == test_csd[EXT_CSD_REV]
1136 && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
1137 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1138 && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
1139 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
1140
7798f6db 1141 mmc->card_caps |= ext_to_hostcaps[extw];
4137894e
LW
1142 break;
1143 }
272cc70b
AF
1144 }
1145
1146 if (mmc->card_caps & MMC_MODE_HS) {
1147 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1148 mmc->tran_speed = 52000000;
272cc70b 1149 else
ad5fd922
JC
1150 mmc->tran_speed = 26000000;
1151 }
272cc70b
AF
1152 }
1153
ad5fd922
JC
1154 mmc_set_clock(mmc, mmc->tran_speed);
1155
272cc70b
AF
1156 /* fill in device description */
1157 mmc->block_dev.lun = 0;
1158 mmc->block_dev.type = 0;
1159 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1160 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1161 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1162#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH
1163 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1164 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1165 (mmc->cid[3] >> 16) & 0xffff);
1166 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1167 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1168 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1169 (mmc->cid[2] >> 24) & 0xff);
1170 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1171 (mmc->cid[2] >> 16) & 0xf);
56196826
PB
1172#else
1173 mmc->block_dev.vendor[0] = 0;
1174 mmc->block_dev.product[0] = 0;
1175 mmc->block_dev.revision[0] = 0;
1176#endif
122efd43 1177#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1178 init_part(&mmc->block_dev);
122efd43 1179#endif
272cc70b
AF
1180
1181 return 0;
1182}
1183
fdbb873e 1184static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF
1185{
1186 struct mmc_cmd cmd;
1187 int err;
1188
1189 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1190 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1191 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1192 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF
1193
1194 err = mmc_send_cmd(mmc, &cmd, NULL);
1195
1196 if (err)
1197 return err;
1198
998be3dd 1199 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF
1200 return UNUSABLE_ERR;
1201 else
1202 mmc->version = SD_VERSION_2;
1203
1204 return 0;
1205}
1206
93bfd616
PA
1207/* not used any more */
1208int __deprecated mmc_register(struct mmc *mmc)
1209{
1210#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1211 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1212#endif
1213 return -1;
1214}
1215
1216struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1217{
93bfd616
PA
1218 struct mmc *mmc;
1219
1220 /* quick validation */
1221 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1222 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1223 return NULL;
1224
1225 mmc = calloc(1, sizeof(*mmc));
1226 if (mmc == NULL)
1227 return NULL;
1228
1229 mmc->cfg = cfg;
1230 mmc->priv = priv;
1231
1232 /* the following chunk was mmc_register() */
1233
ab71188c
MN
1234 /* Setup dsr related values */
1235 mmc->dsr_imp = 0;
1236 mmc->dsr = 0xffffffff;
272cc70b
AF
1237 /* Setup the universal parts of the block interface just once */
1238 mmc->block_dev.if_type = IF_TYPE_MMC;
1239 mmc->block_dev.dev = cur_dev_num++;
1240 mmc->block_dev.removable = 1;
1241 mmc->block_dev.block_read = mmc_bread;
1242 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1243 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1244
93bfd616
PA
1245 /* setup initial part type */
1246 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1247
93bfd616 1248 INIT_LIST_HEAD(&mmc->link);
272cc70b 1249
93bfd616
PA
1250 list_add_tail(&mmc->link, &mmc_devices);
1251
1252 return mmc;
1253}
1254
1255void mmc_destroy(struct mmc *mmc)
1256{
1257 /* only freeing memory for now */
1258 free(mmc);
272cc70b
AF
1259}
1260
df3fc526 1261#ifdef CONFIG_PARTITIONS
272cc70b
AF
1262block_dev_desc_t *mmc_get_dev(int dev)
1263{
1264 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1265 if (!mmc || mmc_init(mmc))
40242bc3 1266 return NULL;
272cc70b 1267
40242bc3 1268 return &mmc->block_dev;
272cc70b 1269}
df3fc526 1270#endif
272cc70b 1271
e9550449 1272int mmc_start_init(struct mmc *mmc)
272cc70b 1273{
afd5932b 1274 int err;
272cc70b 1275
ab769f22 1276 /* we pretend there's no card when init is NULL */
93bfd616 1277 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1278 mmc->has_init = 0;
56196826 1279#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1280 printf("MMC: no card present\n");
56196826 1281#endif
48972d90
TR
1282 return NO_CARD_ERR;
1283 }
1284
bc897b1d
LW
1285 if (mmc->has_init)
1286 return 0;
1287
ab769f22 1288 /* made sure it's not NULL earlier */
93bfd616 1289 err = mmc->cfg->ops->init(mmc);
272cc70b
AF
1290
1291 if (err)
1292 return err;
1293
b86b85e2
IY
1294 mmc_set_bus_width(mmc, 1);
1295 mmc_set_clock(mmc, 1);
1296
272cc70b
AF
1297 /* Reset the Card */
1298 err = mmc_go_idle(mmc);
1299
1300 if (err)
1301 return err;
1302
bc897b1d
LW
1303 /* The internal partition reset to user partition(0) at every CMD0*/
1304 mmc->part_num = 0;
1305
272cc70b 1306 /* Test for SD version 2 */
afd5932b 1307 err = mmc_send_if_cond(mmc);
272cc70b 1308
272cc70b
AF
1309 /* Now try to get the SD card's operating condition */
1310 err = sd_send_op_cond(mmc);
1311
1312 /* If the command timed out, we check for an MMC card */
1313 if (err == TIMEOUT) {
1314 err = mmc_send_op_cond(mmc);
1315
e9550449 1316 if (err && err != IN_PROGRESS) {
56196826 1317#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1318 printf("Card did not respond to voltage select!\n");
56196826 1319#endif
272cc70b
AF
1320 return UNUSABLE_ERR;
1321 }
1322 }
1323
e9550449
CLC
1324 if (err == IN_PROGRESS)
1325 mmc->init_in_progress = 1;
1326
1327 return err;
1328}
1329
1330static int mmc_complete_init(struct mmc *mmc)
1331{
1332 int err = 0;
1333
1334 if (mmc->op_cond_pending)
1335 err = mmc_complete_op_cond(mmc);
1336
1337 if (!err)
1338 err = mmc_startup(mmc);
bc897b1d
LW
1339 if (err)
1340 mmc->has_init = 0;
1341 else
1342 mmc->has_init = 1;
e9550449
CLC
1343 mmc->init_in_progress = 0;
1344 return err;
1345}
1346
1347int mmc_init(struct mmc *mmc)
1348{
1349 int err = IN_PROGRESS;
d803fea5 1350 unsigned start;
e9550449
CLC
1351
1352 if (mmc->has_init)
1353 return 0;
d803fea5
MZ
1354
1355 start = get_timer(0);
1356
e9550449
CLC
1357 if (!mmc->init_in_progress)
1358 err = mmc_start_init(mmc);
1359
1360 if (!err || err == IN_PROGRESS)
1361 err = mmc_complete_init(mmc);
1362 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1363 return err;
272cc70b
AF
1364}
1365
ab71188c
MN
1366int mmc_set_dsr(struct mmc *mmc, u16 val)
1367{
1368 mmc->dsr = val;
1369 return 0;
1370}
1371
cee9ab7c
JH
1372/* CPU-specific MMC initializations */
1373__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF
1374{
1375 return -1;
1376}
1377
cee9ab7c
JH
1378/* board-specific MMC initializations. */
1379__weak int board_mmc_init(bd_t *bis)
1380{
1381 return -1;
1382}
272cc70b 1383
56196826
PB
1384#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1385
272cc70b
AF
1386void print_mmc_devices(char separator)
1387{
1388 struct mmc *m;
1389 struct list_head *entry;
1390
1391 list_for_each(entry, &mmc_devices) {
1392 m = list_entry(entry, struct mmc, link);
1393
93bfd616 1394 printf("%s: %d", m->cfg->name, m->block_dev.dev);
272cc70b
AF
1395
1396 if (entry->next != &mmc_devices)
1397 printf("%c ", separator);
1398 }
1399
1400 printf("\n");
1401}
1402
56196826
PB
1403#else
1404void print_mmc_devices(char separator) { }
1405#endif
1406
ea6ebe21
LW
1407int get_mmc_num(void)
1408{
1409 return cur_dev_num;
1410}
1411
e9550449
CLC
1412void mmc_set_preinit(struct mmc *mmc, int preinit)
1413{
1414 mmc->preinit = preinit;
1415}
1416
1417static void do_preinit(void)
1418{
1419 struct mmc *m;
1420 struct list_head *entry;
1421
1422 list_for_each(entry, &mmc_devices) {
1423 m = list_entry(entry, struct mmc, link);
1424
1425 if (m->preinit)
1426 mmc_start_init(m);
1427 }
1428}
1429
1430
272cc70b
AF
1431int mmc_initialize(bd_t *bis)
1432{
1433 INIT_LIST_HEAD (&mmc_devices);
1434 cur_dev_num = 0;
1435
1436 if (board_mmc_init(bis) < 0)
1437 cpu_mmc_init(bis);
1438
bb0dc108 1439#ifndef CONFIG_SPL_BUILD
272cc70b 1440 print_mmc_devices(',');
bb0dc108 1441#endif
272cc70b 1442
e9550449 1443 do_preinit();
272cc70b
AF
1444 return 0;
1445}
3690d6d6
A
1446
1447#ifdef CONFIG_SUPPORT_EMMC_BOOT
1448/*
1449 * This function changes the size of boot partition and the size of rpmb
1450 * partition present on EMMC devices.
1451 *
1452 * Input Parameters:
1453 * struct *mmc: pointer for the mmc device strcuture
1454 * bootsize: size of boot partition
1455 * rpmbsize: size of rpmb partition
1456 *
1457 * Returns 0 on success.
1458 */
1459
1460int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1461 unsigned long rpmbsize)
1462{
1463 int err;
1464 struct mmc_cmd cmd;
1465
1466 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1467 cmd.cmdidx = MMC_CMD_RES_MAN;
1468 cmd.resp_type = MMC_RSP_R1b;
1469 cmd.cmdarg = MMC_CMD62_ARG1;
1470
1471 err = mmc_send_cmd(mmc, &cmd, NULL);
1472 if (err) {
1473 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1474 return err;
1475 }
1476
1477 /* Boot partition changing mode */
1478 cmd.cmdidx = MMC_CMD_RES_MAN;
1479 cmd.resp_type = MMC_RSP_R1b;
1480 cmd.cmdarg = MMC_CMD62_ARG2;
1481
1482 err = mmc_send_cmd(mmc, &cmd, NULL);
1483 if (err) {
1484 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1485 return err;
1486 }
1487 /* boot partition size is multiple of 128KB */
1488 bootsize = (bootsize * 1024) / 128;
1489
1490 /* Arg: boot partition size */
1491 cmd.cmdidx = MMC_CMD_RES_MAN;
1492 cmd.resp_type = MMC_RSP_R1b;
1493 cmd.cmdarg = bootsize;
1494
1495 err = mmc_send_cmd(mmc, &cmd, NULL);
1496 if (err) {
1497 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1498 return err;
1499 }
1500 /* RPMB partition size is multiple of 128KB */
1501 rpmbsize = (rpmbsize * 1024) / 128;
1502 /* Arg: RPMB partition size */
1503 cmd.cmdidx = MMC_CMD_RES_MAN;
1504 cmd.resp_type = MMC_RSP_R1b;
1505 cmd.cmdarg = rpmbsize;
1506
1507 err = mmc_send_cmd(mmc, &cmd, NULL);
1508 if (err) {
1509 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1510 return err;
1511 }
1512 return 0;
1513}
1514
5a99b9de
TR
1515/*
1516 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1517 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1518 * and BOOT_MODE.
1519 *
1520 * Returns 0 on success.
1521 */
1522int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1523{
1524 int err;
1525
1526 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1527 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1528 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1529 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1530
1531 if (err)
1532 return err;
1533 return 0;
1534}
1535
792970b0
TR
1536/*
1537 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1538 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1539 * PARTITION_ACCESS.
1540 *
1541 * Returns 0 on success.
1542 */
1543int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1544{
1545 int err;
1546
1547 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1548 EXT_CSD_BOOT_ACK(ack) |
1549 EXT_CSD_BOOT_PART_NUM(part_num) |
1550 EXT_CSD_PARTITION_ACCESS(access));
1551
1552 if (err)
1553 return err;
1554 return 0;
1555}
33ace362
TR
1556
1557/*
1558 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1559 * for enable. Note that this is a write-once field for non-zero values.
1560 *
1561 * Returns 0 on success.
1562 */
1563int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1564{
1565 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1566 enable);
1567}
3690d6d6 1568#endif