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aarch64: Add support for MPAM system registers
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2e49fd1e
AC		 12020-08-12 Alex Coplan <alex.coplan@arm.com>
2
3 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
4
79ddc884
NC		 52020-08-12 Nick Clifton <nickc@redhat.com>
6
7 * po/sr.po: Updated Serbian translation.
8
08770ec2
AM		 92020-08-11 Alan Modra <amodra@gmail.com>
10
11 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
12
f7cb161e
PW		 132020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
14
15 * aarch64-opc.c (aarch64_print_operand):
16 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
17 (aarch64_sys_reg_supported_p): Function removed.
18 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
19 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
20 into this function.
21
3eb65174
AM		 222020-08-10 Alan Modra <amodra@gmail.com>
23
24 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
25 instructions.
26
8b2742a1
AM		 272020-08-10 Alan Modra <amodra@gmail.com>
28
29 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
30 Enable icbt for power5, miso for power8.
31
5fbec329
AM		 322020-08-10 Alan Modra <amodra@gmail.com>
33
34 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
35 mtvsrd, and similarly for mfvsrd.
36
563a3225
CG		 372020-08-04 Christian Groessler <chris@groessler.org>
38 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
39
40 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
41 opcodes (special "out" to absolute address).
42 * z8k-opc.h: Regenerate.
43
41eb8e88
L		 442020-07-30 H.J. Lu <hongjiu.lu@intel.com>
45
46 PR gas/26305
47 * i386-opc.h (Prefix_Disp8): New.
48 (Prefix_Disp16): Likewise.
49 (Prefix_Disp32): Likewise.
50 (Prefix_Load): Likewise.
51 (Prefix_Store): Likewise.
52 (Prefix_VEX): Likewise.
53 (Prefix_VEX3): Likewise.
54 (Prefix_EVEX): Likewise.
55 (Prefix_REX): Likewise.
56 (Prefix_NoOptimize): Likewise.
57 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
58 * i386-tbl.h: Regenerated.
59
98116973
AA		 602020-07-29 Andreas Arnez <arnez@linux.ibm.com>
61
62 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
63 default case with abort() instead of printing an error message and
64 continuing, to avoid a maybe-uninitialized warning.
65
2dddfa20
NC		 662020-07-24 Nick Clifton <nickc@redhat.com>
67
68 * po/de.po: Updated German translation.
69
bf4ba07c
JB		 702020-07-21 Jan Beulich <jbeulich@suse.com>
71
72 * i386-dis.c (OP_E_memory): Revert previous change.
73
04c662e2
L		 742020-07-15 H.J. Lu <hongjiu.lu@intel.com>
75
76 PR gas/26237
77 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
78 without base nor index registers.
79
f0e8d0ba
JB		 802020-07-15 Jan Beulich <jbeulich@suse.com>
81
82 * i386-dis.c (putop): Move 'V' and 'W' handling.
83
c3f5525f
JB		 842020-07-15 Jan Beulich <jbeulich@suse.com>
85
86 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
87 construct for push/pop of register.
88 (putop): Honor cond when handling 'P'. Drop handling of plain
89 'V'.
90
36938cab
JB		 912020-07-15 Jan Beulich <jbeulich@suse.com>
92
93 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
94 description. Drop '&' description. Use P for push of immediate,
95 pushf/popf, enter, and leave. Use %LP for lret/retf.
96 (dis386_twobyte): Use P for push/pop of fs/gs.
97 (reg_table): Use P for push/pop. Use @ for near call/jmp.
98 (x86_64_table): Use P for far call/jmp.
99 (putop): Drop handling of 'U' and '&'. Move and adjust handling
100 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
101 labels.
102 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
103 and dqw_mode (unconditional).
104
8e58ef80
L		 1052020-07-14 H.J. Lu <hongjiu.lu@intel.com>
106
107 PR gas/26237
108 * i386-dis.c (OP_E_memory): Without base nor index registers,
109 32-bit displacement to 64 bits.
110
570b0ed6
CZ		 1112020-07-14 Claudiu Zissulescu <claziss@gmail.com>
112
113 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
114 faulty double register pair is detected.
115
bfbd9438
JB		 1162020-07-14 Jan Beulich <jbeulich@suse.com>
117
118 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
119
78467458
JB		 1202020-07-14 Jan Beulich <jbeulich@suse.com>
121
122 * i386-dis.c (OP_R, Rm): Delete.
123 (MOD_0F24, MOD_0F26): Rename to ...
124 (X86_64_0F24, X86_64_0F26): ... respectively.
125 (dis386): Update 'L' and 'Z' comments.
126 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
127 table references.
128 (mod_table): Move opcode 0F24 and 0F26 entries ...
129 (x86_64_table): ... here.
130 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
131 'Z' case block.
132
464d2b65
JB		 1332020-07-14 Jan Beulich <jbeulich@suse.com>
134
135 * i386-dis.c (Rd, Rdq, MaskR): Delete.
136 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
137 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
138 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
139 MOD_EVEX_0F387C): New enumerators.
140 (reg_table): Use Edq for rdssp.
141 (prefix_table): Use Edq for incssp.
142 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
143 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
144 ktest*, and kshift*. Use Edq / MaskE for kmov*.
145 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
146 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
147 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
148 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
149 0F3828_P_1 and 0F3838_P_1.
150 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
151 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
152
035e7389
JB		 1532020-07-14 Jan Beulich <jbeulich@suse.com>
154
155 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
156 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
157 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
158 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
159 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
160 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
161 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
162 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
163 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
164 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
165 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
166 (reg_table, prefix_table, three_byte_table, vex_table,
167 vex_len_table, mod_table, rm_table): Replace / remove respective
168 entries.
169 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
170 of PREFIX_DATA in used_prefixes.
171
bb5b3501
JB		 1722020-07-14 Jan Beulich <jbeulich@suse.com>
173
174 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
175 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
176 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
177 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
178 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
179 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
180 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
181 VEX_W_0F3A33_L_0): Delete.
182 (dis386): Adjust "BW" description.
183 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
184 0F3A31, 0F3A32, and 0F3A33.
185 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
186 entries.
187 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
188 entries.
189
7531c613
JB		 1902020-07-14 Jan Beulich <jbeulich@suse.com>
191
192 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
193 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
194 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
195 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
196 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
197 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
198 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
199 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
200 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
201 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
202 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
203 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
204 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
205 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
206 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
207 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
208 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
209 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
210 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
211 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
212 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
213 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
214 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
215 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
216 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
217 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
218 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
219 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
220 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
221 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
222 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
223 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
224 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
225 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
226 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
227 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
228 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
229 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
230 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
231 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
232 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
233 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
234 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
235 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
236 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
237 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
238 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
239 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
240 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
241 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
242 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
243 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
244 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
245 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
246 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
247 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
248 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
249 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
250 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
251 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
252 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
253 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
254 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
255 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
256 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
257 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
258 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
259 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
260 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
261 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
262 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
263 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
264 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
265 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
266 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
267 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
268 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
269 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
270 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
271 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
272 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
273 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
274 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
275 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
276 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
277 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
278 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
279 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
280 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
281 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
282 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
283 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
284 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
285 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
286 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
287 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
288 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
289 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
290 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
291 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
292 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
293 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
294 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
295 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
296 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
297 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
298 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
299 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
300 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
301 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
302 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
303 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
304 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
305 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
306 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
307 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
308 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
309 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
310 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
311 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
312 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
313 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
314 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
315 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
316 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
317 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
318 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
319 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
320 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
321 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
322 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
323 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
324 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
325 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
326 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
327 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
328 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
329 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
330 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
331 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
332 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
333 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
334 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
335 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
336 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
337 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
338 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
339 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
340 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
341 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
342 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
343 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
344 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
345 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
346 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
347 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
348 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
349 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
350 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
351 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
352 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
353 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
354 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
355 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
356 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
357 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
358 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
359 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
360 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
361 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
362 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
363 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
364 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
365 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
366 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
367 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
368 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
369 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
370 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
371 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
372 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
373 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
374 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
375 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
376 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
377 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
378 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
379 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
380 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
381 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
382 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
383 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
384 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
385 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
386 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
387 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
388 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
389 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
390 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
391 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
392 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
393 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
394 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
395 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
396 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
397 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
398 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
399 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
400 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
401 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
402 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
403 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
404 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
405 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
406 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
407 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
408 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
409 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
410 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
411 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
412 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
413 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
414 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
415 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
416 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
417 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
418 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
419 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
420 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
421 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
422 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
423 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
424 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
425 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
426 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
427 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
428 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
429 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
430 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
431 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
432 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
433 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
434 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
435 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
436 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
437 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
438 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
439 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
440 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
441 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
442 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
443 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
444 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
445 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
446 EVEX_W_0F3A72_P_2): Rename to ...
447 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
448 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
449 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
450 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
451 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
452 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
453 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
454 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
455 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
456 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
457 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
458 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
459 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
460 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
461 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
462 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
463 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
464 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
465 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
466 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
467 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
468 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
469 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
470 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
471 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
472 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
473 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
474 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
475 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
476 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
477 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
478 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
479 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
480 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
481 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
482 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
483 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
484 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
485 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
486 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
487 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
488 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
489 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
490 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
491 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
492 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
493 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
494 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
495 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
496 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
497 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
498 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
499 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
500 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
501 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
502 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
503 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
504 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
505 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
506 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
507 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
508 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
509 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
510 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
511 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
512 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
513 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
514 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
515 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
516 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
517 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
518 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
519 respectively.
520 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
521 vex_w_table, mod_table): Replace / remove respective entries.
522 (print_insn): Move up dp->prefix_requirement handling. Handle
523 PREFIX_DATA.
524 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
525 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
526 Replace / remove respective entries.
527
17d3c7ec
JB		 5282020-07-14 Jan Beulich <jbeulich@suse.com>
529
530 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
531 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
532 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
533 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
534 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
535 the latter two.
536 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
537 0F2C, 0F2D, 0F2E, and 0F2F.
538 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
539 0F2F table entries.
540
41f5efc6
JB		 5412020-07-14 Jan Beulich <jbeulich@suse.com>
542
543 * i386-dis.c (OP_VexR, VexScalarR): New.
544 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
545 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
546 need_vex_reg): Delete.
547 (prefix_table): Replace VexScalar by VexScalarR and
548 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
549 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
550 (vex_len_table): Replace EXqVexScalarS by EXqS.
551 (get_valid_dis386): Don't set need_vex_reg.
552 (print_insn): Don't initialize need_vex_reg.
553 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
554 q_scalar_swap_mode cases.
555 (OP_EX): Don't check for d_scalar_swap_mode and
556 q_scalar_swap_mode.
557 (OP_VEX): Done check need_vex_reg.
558 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
559 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
560 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
561
89e65d17
JB		 5622020-07-14 Jan Beulich <jbeulich@suse.com>
563
564 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
565 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
566 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
567 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
568 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
569 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
570 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
571 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
572 (vex_table): Replace Vex128 by Vex.
573 (vex_len_table): Likewise. Adjust referenced enum names.
574 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
575 referenced enum names.
576 (OP_VEX): Drop vex128_mode and vex256_mode cases.
577 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
578
492a76aa
JB		 5792020-07-14 Jan Beulich <jbeulich@suse.com>
580
581 * i386-dis.c (dis386): "LW" description now applies to "DQ".
582 (putop): Handle "DQ". Don't handle "LW" anymore.
583 (prefix_table, mod_table): Replace %LW by %DQ.
584 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
585
059edf8b
JB		 5862020-07-14 Jan Beulich <jbeulich@suse.com>
587
588 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
589 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
590 d_scalar_swap_mode case handling. Move shift adjsutment into
591 the case its applicable to.
592
4726e9a4
JB		 5932020-07-14 Jan Beulich <jbeulich@suse.com>
594
595 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
596 (EXbScalar, EXwScalar): Fold to ...
597 (EXbwUnit): ... this.
598 (b_scalar_mode, w_scalar_mode): Fold to ...
599 (bw_unit_mode): ... this.
600 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
601 w_scalar_mode handling by bw_unit_mode one.
602 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
603 ...
604 * i386-dis-evex-prefix.h: ... here.
605
b24d668c
JB		 6062020-07-14 Jan Beulich <jbeulich@suse.com>
607
608 * i386-dis.c (PCMPESTR_Fixup): Delete.
609 (dis386): Adjust "LQ" description.
610 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
611 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
612 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
613 vpcmpestrm, and vpcmpestri.
614 (putop): Honor "cond" when handling LQ.
615 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
616 vcvtsi2ss and vcvtusi2ss.
617 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
618 vcvtsi2sd and vcvtusi2sd.
619
c4de7606
JB		 6202020-07-14 Jan Beulich <jbeulich@suse.com>
621
622 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
623 (simd_cmp_op): Add const.
624 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
625 (CMP_Fixup): Handle VEX case.
626 (prefix_table): Replace VCMP by CMP.
627 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
628
9ab00b61
JB		 6292020-07-14 Jan Beulich <jbeulich@suse.com>
630
631 * i386-dis.c (MOVBE_Fixup): Delete.
632 (Mv): Define.
633 (prefix_table): Use Mv for movbe entries.
634
2875b28a
JB		 6352020-07-14 Jan Beulich <jbeulich@suse.com>
636
637 * i386-dis.c (CRC32_Fixup): Delete.
638 (prefix_table): Use Eb/Ev for crc32 entries.
639
e184e611
JB		 6402020-07-14 Jan Beulich <jbeulich@suse.com>
641
642 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
643 Conditionalize invocations of "USED_REX (0)".
644
e8b5d5f9
JB		 6452020-07-14 Jan Beulich <jbeulich@suse.com>
646
647 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
648 CH, DH, BH, AX, DX): Delete.
649 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
650 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
651 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
652
260cd341
LC		 6532020-07-10 Lili Cui <lili.cui@intel.com>
654
655 * i386-dis.c (TMM): New.
656 (EXtmm): Likewise.
657 (VexTmm): Likewise.
658 (MVexSIBMEM): Likewise.
659 (tmm_mode): Likewise.
660 (vex_sibmem_mode): Likewise.
661 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
662 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
663 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
664 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
665 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
666 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
667 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
668 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
669 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
670 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
671 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
672 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
673 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
674 (PREFIX_VEX_0F3849_X86_64): Likewise.
675 (PREFIX_VEX_0F384B_X86_64): Likewise.
676 (PREFIX_VEX_0F385C_X86_64): Likewise.
677 (PREFIX_VEX_0F385E_X86_64): Likewise.
678 (X86_64_VEX_0F3849): Likewise.
679 (X86_64_VEX_0F384B): Likewise.
680 (X86_64_VEX_0F385C): Likewise.
681 (X86_64_VEX_0F385E): Likewise.
682 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
683 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
684 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
685 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
686 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
687 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
688 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
689 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
690 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
691 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
692 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
693 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
694 (VEX_W_0F3849_X86_64_P_0): Likewise.
695 (VEX_W_0F3849_X86_64_P_2): Likewise.
696 (VEX_W_0F3849_X86_64_P_3): Likewise.
697 (VEX_W_0F384B_X86_64_P_1): Likewise.
698 (VEX_W_0F384B_X86_64_P_2): Likewise.
699 (VEX_W_0F384B_X86_64_P_3): Likewise.
700 (VEX_W_0F385C_X86_64_P_1): Likewise.
701 (VEX_W_0F385E_X86_64_P_0): Likewise.
702 (VEX_W_0F385E_X86_64_P_1): Likewise.
703 (VEX_W_0F385E_X86_64_P_2): Likewise.
704 (VEX_W_0F385E_X86_64_P_3): Likewise.
705 (names_tmm): Likewise.
706 (att_names_tmm): Likewise.
707 (intel_operand_size): Handle void_mode.
708 (OP_XMM): Handle tmm_mode.
709 (OP_EX): Likewise.
710 (OP_VEX): Likewise.
711 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
712 CpuAMX_BF16 and CpuAMX_TILE.
713 (operand_type_shorthands): Add RegTMM.
714 (operand_type_init): Likewise.
715 (operand_types): Add Tmmword.
716 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
717 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
718 * i386-opc.h (CpuAMX_INT8): New.
719 (CpuAMX_BF16): Likewise.
720 (CpuAMX_TILE): Likewise.
721 (SIBMEM): Likewise.
722 (Tmmword): Likewise.
723 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
724 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
725 (i386_operand_type): Add tmmword.
726 * i386-opc.tbl: Add AMX instructions.
727 * i386-reg.tbl: Add AMX registers.
728 * i386-init.h: Regenerated.
729 * i386-tbl.h: Likewise.
730
467bbef0
JB		 7312020-07-08 Jan Beulich <jbeulich@suse.com>
732
733 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
734 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
735 Rename to ...
736 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
737 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
738 respectively.
739 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
740 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
741 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
742 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
743 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
744 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
745 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
746 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
747 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
748 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
749 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
750 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
751 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
752 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
753 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
754 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
755 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
756 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
757 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
758 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
759 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
760 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
761 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
762 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
763 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
764 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
765 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
766 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
767 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
768 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
769 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
770 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
771 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
772 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
773 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
774 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
775 (reg_table): Re-order XOP entries. Adjust their operands.
776 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
777 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
778 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
779 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
780 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
781 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
782 entries by references ...
783 (vex_len_table): ... to resepctive new entries here. For several
784 new and existing entries reference ...
785 (vex_w_table): ... new entries here.
786 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
787
6384fd9e
JB		 7882020-07-08 Jan Beulich <jbeulich@suse.com>
789
790 * i386-dis.c (XMVexScalarI4): Define.
791 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
792 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
793 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
794 (vex_len_table): Move scalar FMA4 entries ...
795 (prefix_table): ... here.
796 (OP_REG_VexI4): Handle scalar_mode.
797 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
798 * i386-tbl.h: Re-generate.
799
e6123d0c
JB		 8002020-07-08 Jan Beulich <jbeulich@suse.com>
801
802 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
803 Vex_2src_2): Delete.
804 (OP_VexW, VexW): New.
805 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
806 for shifts and rotates by register.
807
93abb146
JB		 8082020-07-08 Jan Beulich <jbeulich@suse.com>
809
810 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
811 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
812 OP_EX_VexReg): Delete.
813 (OP_VexI4, VexI4): New.
814 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
815 (prefix_table): ... here.
816 (print_insn): Drop setting of vex_w_done.
817
b13b1bc0
JB		 8182020-07-08 Jan Beulich <jbeulich@suse.com>
819
820 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
821 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
822 (xop_table): Replace operands of 4-operand insns.
823 (OP_REG_VexI4): Move VEX.W based operand swaping here.
824
f337259f
CZ		 8252020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
826
827 * arc-opc.c (insert_rbd): New function.
828 (RBD): Define.
829 (RBDdup): Likewise.
830 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
831 instructions.
832
931452b6
JB		 8332020-07-07 Jan Beulich <jbeulich@suse.com>
834
835 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
836 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
837 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
838 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
839 Delete.
840 (putop): Handle "BW".
841 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
842 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
843 and 0F3A3F ...
844 * i386-dis-evex-prefix.h: ... here.
845
b5b098c2
JB		 8462020-07-06 Jan Beulich <jbeulich@suse.com>
847
848 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
849 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
850 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
851 VEX_W_0FXOP_09_83): New enumerators.
852 (xop_table): Reference the above.
853 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
854 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
855 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
856 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
857
21a3faeb
JB		 8582020-07-06 Jan Beulich <jbeulich@suse.com>
859
860 * i386-dis.c (EVEX_W_0F3838_P_1,
861 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
862 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
863 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
864 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
865 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
866 (putop): Centralize management of last[]. Delete SAVE_LAST.
867 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
868 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
869 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
870 * i386-dis-evex-prefix.h: here.
871
bc152a17
JB		 8722020-07-06 Jan Beulich <jbeulich@suse.com>
873
874 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
875 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
876 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
877 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
878 enumerators.
879 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
880 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
881 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
882 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
883 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
884 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
885 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
886 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
887 these, respectively.
888 * i386-dis-evex-len.h: Adjust comments.
889 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
890 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
891 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
892 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
893 MOD_EVEX_0F385B_P_2_W_1 table entries.
894 * i386-dis-evex-w.h: Reference mod_table[] for
895 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
896 EVEX_W_0F385B_P_2.
897
c82a99a0
JB		 8982020-07-06 Jan Beulich <jbeulich@suse.com>
899
900 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
901 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
902 EXymm.
903 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
904 Likewise. Mark 256-bit entries invalid.
905
fedfb81e
JB		 9062020-07-06 Jan Beulich <jbeulich@suse.com>
907
908 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
909 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
910 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
911 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
912 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
913 PREFIX_EVEX_0F382B): Delete.
914 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
915 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
916 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
917 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
918 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
919 to ...
920 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
921 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
922 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
923 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
924 respectively.
925 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
926 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
927 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
928 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
929 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
930 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
931 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
932 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
933 PREFIX_EVEX_0F382B): Remove table entries.
934 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
935 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
936 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
937
3a57774c
JB		 9382020-07-06 Jan Beulich <jbeulich@suse.com>
939
940 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
941 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
942 enumerators.
943 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
944 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
945 EVEX_LEN_0F3A01_P_2_W_1 table entries.
946 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
947 entries.
948
e74d9fa9
JB		 9492020-07-06 Jan Beulich <jbeulich@suse.com>
950
951 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
952 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
953 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
954 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
955 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
956 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
957 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
958 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
959 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
960 entries.
961
6431c801
JB		 9622020-07-06 Jan Beulich <jbeulich@suse.com>
963
964 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
965 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
966 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
967 respectively.
968 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
969 entries.
970 * i386-dis-evex.h (evex_table): Reference VEX table entry for
971 opcode 0F3A1D.
972 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
973 entry.
974 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
975
6df22cf6
JB		 9762020-07-06 Jan Beulich <jbeulich@suse.com>
977
978 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
979 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
980 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
981 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
982 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
983 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
984 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
985 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
986 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
987 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
988 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
989 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
990 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
991 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
992 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
993 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
994 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
995 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
996 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
997 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
998 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
999 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1000 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1001 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1002 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1003 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1004 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1005 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1006 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1007 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1008 (prefix_table): Add EXxEVexR to FMA table entries.
1009 (OP_Rounding): Move abort() invocation.
1010 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1011 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1012 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1013 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1014 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1015 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1016 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1017 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1018 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1019 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1020 0F3ACE, 0F3ACF.
1021 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1022 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1023 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1024 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1025 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1026 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1027 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1028 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1029 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1030 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1031 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1032 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1033 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1034 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1035 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1036 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1037 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1038 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1039 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1040 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1041 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1042 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1043 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1044 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1045 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1046 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1047 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1048 Delete table entries.
1049 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1050 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1051 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1052 Likewise.
1053
39e0f456
JB		 10542020-07-06 Jan Beulich <jbeulich@suse.com>
1055
1056 * i386-dis.c (EXqScalarS): Delete.
1057 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1058 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1059
5b872f7d
JB		 10602020-07-06 Jan Beulich <jbeulich@suse.com>
1061
1062 * i386-dis.c (safe-ctype.h): Include.
1063 (EXdScalar, EXqScalar): Delete.
1064 (d_scalar_mode, q_scalar_mode): Delete.
1065 (prefix_table, vex_len_table): Use EXxmm_md in place of
1066 EXdScalar and EXxmm_mq in place of EXqScalar.
1067 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1068 d_scalar_mode and q_scalar_mode.
1069 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1070 (vmovsd): Use EXxmm_mq.
1071
ddc73fa9
NC		 10722020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1073
1074 PR 26204
1075 * arc-dis.c: Fix spelling mistake.
1076 * po/opcodes.pot: Regenerate.
1077
17550be7
NC		 10782020-07-06 Nick Clifton <nickc@redhat.com>
1079
1080 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1081 * po/uk.po: Updated Ukranian translation.
1082
b19d852d
NC		 10832020-07-04 Nick Clifton <nickc@redhat.com>
1084
1085 * configure: Regenerate.
1086 * po/opcodes.pot: Regenerate.
1087
b115b9fd
NC		 10882020-07-04 Nick Clifton <nickc@redhat.com>
1089
1090 Binutils 2.35 branch created.
1091
c2ecccb3
L		 10922020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1093
1094 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1095 * i386-opc.h (VexSwapSources): New.
1096 (i386_opcode_modifier): Add vexswapsources.
1097 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1098 with two source operands swapped.
1099 * i386-tbl.h: Regenerated.
1100
08ccfccf
NC		 11012020-06-30 Nelson Chu <nelson.chu@sifive.com>
1102
1103 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1104 unprivileged CSR can also be initialized.
1105
279edac5
AM		 11062020-06-29 Alan Modra <amodra@gmail.com>
1107
1108 * arm-dis.c: Use C style comments.
1109 * cr16-opc.c: Likewise.
1110 * ft32-dis.c: Likewise.
1111 * moxie-opc.c: Likewise.
1112 * tic54x-dis.c: Likewise.
1113 * s12z-opc.c: Remove useless comment.
1114 * xgate-dis.c: Likewise.
1115
e978ad62
L		 11162020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 * i386-opc.tbl: Add a blank line.
1119
63112cd6
L		 11202020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1121
1122 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1123 (VecSIB128): Renamed to ...
1124 (VECSIB128): This.
1125 (VecSIB256): Renamed to ...
1126 (VECSIB256): This.
1127 (VecSIB512): Renamed to ...
1128 (VECSIB512): This.
1129 (VecSIB): Renamed to ...
1130 (SIB): This.
1131 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1132 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1133 (VecSIB256): Likewise.
1134 (VecSIB512): Likewise.
79b32e73 1135 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1136 and VecSIB512, respectively.
1137
d1c36125
JB		 11382020-06-26 Jan Beulich <jbeulich@suse.com>
1139
1140 * i386-dis.c: Adjust description of I macro.
1141 (x86_64_table): Drop use of I.
1142 (float_mem): Replace use of I.
1143 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1144
2a1bb84c
JB		 11452020-06-26 Jan Beulich <jbeulich@suse.com>
1146
1147 * i386-dis.c: (print_insn): Avoid straight assignment to
1148 priv.orig_sizeflag when processing -M sub-options.
1149
8f570d62
JB		 11502020-06-25 Jan Beulich <jbeulich@suse.com>
1151
1152 * i386-dis.c: Adjust description of J macro.
1153 (dis386, x86_64_table, mod_table): Replace J.
1154 (putop): Remove handling of J.
1155
464dc4af
JB		 11562020-06-25 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1159
589958d6
JB		 11602020-06-25 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-dis.c: Adjust description of "LQ" macro.
1163 (dis386_twobyte): Use LQ for sysret.
1164 (putop): Adjust handling of LQ.
1165
39ff0b81
NC		 11662020-06-22 Nelson Chu <nelson.chu@sifive.com>
1167
1168 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1169 * riscv-dis.c: Include elfxx-riscv.h.
1170
d27c357a
JB		 11712020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1172
1173 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1174
6fde587f
CL		 11752020-06-17 Lili Cui <lili.cui@intel.com>
1176
1177 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1178
efe30057
L		 11792020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1180
1181 PR gas/26115
1182 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1183 * i386-opc.tbl: Likewise.
1184 * i386-tbl.h: Regenerated.
1185
d8af286f
NC		 11862020-06-12 Nelson Chu <nelson.chu@sifive.com>
1187
1188 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1189
14962256
AC		 11902020-06-11 Alex Coplan <alex.coplan@arm.com>
1191
1192 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1193 (SR_CORE): Likewise.
1194 (SR_FEAT): Likewise.
1195 (SR_RNG): Likewise.
1196 (SR_V8_1): Likewise.
1197 (SR_V8_2): Likewise.
1198 (SR_V8_3): Likewise.
1199 (SR_V8_4): Likewise.
1200 (SR_PAN): Likewise.
1201 (SR_RAS): Likewise.
1202 (SR_SSBS): Likewise.
1203 (SR_SVE): Likewise.
1204 (SR_ID_PFR2): Likewise.
1205 (SR_PROFILE): Likewise.
1206 (SR_MEMTAG): Likewise.
1207 (SR_SCXTNUM): Likewise.
1208 (aarch64_sys_regs): Refactor to store feature information in the table.
1209 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1210 that now describe their own features.
1211 (aarch64_pstatefield_supported_p): Likewise.
1212
f9630fa6
L		 12132020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1214
1215 * i386-dis.c (prefix_table): Fix a typo in comments.
1216
73239888
JB		 12172020-06-09 Jan Beulich <jbeulich@suse.com>
1218
1219 * i386-dis.c (rex_ignored): Delete.
1220 (ckprefix): Drop rex_ignored initialization.
1221 (get_valid_dis386): Drop setting of rex_ignored.
1222 (print_insn): Drop checking of rex_ignored. Don't record data
1223 size prefix as used with VEX-and-alike encodings.
1224
18897deb
JB		 12252020-06-09 Jan Beulich <jbeulich@suse.com>
1226
1227 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1228 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1229 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1230 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1231 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1232 VEX_0F12, and VEX_0F16.
1233 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1234 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1235 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1236 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1237 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1238 MOD_VEX_0F16_PREFIX_2 entries.
1239
97e6786a
JB		 12402020-06-09 Jan Beulich <jbeulich@suse.com>
1241
1242 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1243 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1244 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1245 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1246 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1247 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1248 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1249 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1250 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1251 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1252 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1253 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1254 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1255 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1256 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1257 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1258 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1259 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1260 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1261 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1262 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1263 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1264 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1265 EVEX_W_0FC6_P_2): Delete.
1266 (print_insn): Add EVEX.W vs embedded prefix consistency check
1267 to prefix validation.
1268 * i386-dis-evex.h (evex_table): Don't further descend for
1269 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1270 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1271 and 0F2B.
1272 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1273 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1274 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1275 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1276 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1277 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1278 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1279 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1280 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1281 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1282 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1283 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1284 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1285 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1286 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1287 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1288 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1289 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1290 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1291 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1292 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1293 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1294 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1295 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1296 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1297 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1298 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1299
bf926894
JB		 13002020-06-09 Jan Beulich <jbeulich@suse.com>
1301
1302 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1303 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1304 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1305 vmovmskpX.
1306 (print_insn): Drop pointless check against bad_opcode. Split
1307 prefix validation into legacy and VEX-and-alike parts.
1308 (putop): Re-work 'X' macro handling.
1309
a5aaedb9
JB		 13102020-06-09 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-dis.c (MOD_0F51): Rename to ...
1313 (MOD_0F50): ... this.
1314
26417f19
AC		 13152020-06-08 Alex Coplan <alex.coplan@arm.com>
1316
1317 * arm-dis.c (arm_opcodes): Add dfb.
1318 (thumb32_opcodes): Add dfb.
1319
8a6fb3f9
JB		 13202020-06-08 Jan Beulich <jbeulich@suse.com>
1321
1322 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1323
1424c35d
AM		 13242020-06-06 Alan Modra <amodra@gmail.com>
1325
1326 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1327
d3d1cc7b
AM		 13282020-06-05 Alan Modra <amodra@gmail.com>
1329
1330 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1331 size is large enough.
1332
d8740be1
JM		 13332020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1334
1335 * disassemble.c (disassemble_init_for_target): Set endian_code for
1336 bpf targets.
1337 * bpf-desc.c: Regenerate.
1338 * bpf-opc.c: Likewise.
1339 * bpf-dis.c: Likewise.
1340
e9bffec9
JM		 13412020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1342
1343 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1344 (cgen_put_insn_value): Likewise.
1345 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1346 * cgen-dis.in (print_insn): Likewise.
1347 * cgen-ibld.in (insert_1): Likewise.
1348 (insert_1): Likewise.
1349 (insert_insn_normal): Likewise.
1350 (extract_1): Likewise.
1351 * bpf-dis.c: Regenerate.
1352 * bpf-ibld.c: Likewise.
1353 * bpf-ibld.c: Likewise.
1354 * cgen-dis.in: Likewise.
1355 * cgen-ibld.in: Likewise.
1356 * cgen-opc.c: Likewise.
1357 * epiphany-dis.c: Likewise.
1358 * epiphany-ibld.c: Likewise.
1359 * fr30-dis.c: Likewise.
1360 * fr30-ibld.c: Likewise.
1361 * frv-dis.c: Likewise.
1362 * frv-ibld.c: Likewise.
1363 * ip2k-dis.c: Likewise.
1364 * ip2k-ibld.c: Likewise.
1365 * iq2000-dis.c: Likewise.
1366 * iq2000-ibld.c: Likewise.
1367 * lm32-dis.c: Likewise.
1368 * lm32-ibld.c: Likewise.
1369 * m32c-dis.c: Likewise.
1370 * m32c-ibld.c: Likewise.
1371 * m32r-dis.c: Likewise.
1372 * m32r-ibld.c: Likewise.
1373 * mep-dis.c: Likewise.
1374 * mep-ibld.c: Likewise.
1375 * mt-dis.c: Likewise.
1376 * mt-ibld.c: Likewise.
1377 * or1k-dis.c: Likewise.
1378 * or1k-ibld.c: Likewise.
1379 * xc16x-dis.c: Likewise.
1380 * xc16x-ibld.c: Likewise.
1381 * xstormy16-dis.c: Likewise.
1382 * xstormy16-ibld.c: Likewise.
1383
b3db6d07
JM		 13842020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1385
1386 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1387 (print_insn_): Handle instruction endian.
1388 * bpf-dis.c: Regenerate.
1389 * bpf-desc.c: Regenerate.
1390 * epiphany-dis.c: Likewise.
1391 * epiphany-desc.c: Likewise.
1392 * fr30-dis.c: Likewise.
1393 * fr30-desc.c: Likewise.
1394 * frv-dis.c: Likewise.
1395 * frv-desc.c: Likewise.
1396 * ip2k-dis.c: Likewise.
1397 * ip2k-desc.c: Likewise.
1398 * iq2000-dis.c: Likewise.
1399 * iq2000-desc.c: Likewise.
1400 * lm32-dis.c: Likewise.
1401 * lm32-desc.c: Likewise.
1402 * m32c-dis.c: Likewise.
1403 * m32c-desc.c: Likewise.
1404 * m32r-dis.c: Likewise.
1405 * m32r-desc.c: Likewise.
1406 * mep-dis.c: Likewise.
1407 * mep-desc.c: Likewise.
1408 * mt-dis.c: Likewise.
1409 * mt-desc.c: Likewise.
1410 * or1k-dis.c: Likewise.
1411 * or1k-desc.c: Likewise.
1412 * xc16x-dis.c: Likewise.
1413 * xc16x-desc.c: Likewise.
1414 * xstormy16-dis.c: Likewise.
1415 * xstormy16-desc.c: Likewise.
1416
4ee4189f
NC		 14172020-06-03 Nick Clifton <nickc@redhat.com>
1418
1419 * po/sr.po: Updated Serbian translation.
1420
44730156
NC		 14212020-06-03 Nelson Chu <nelson.chu@sifive.com>
1422
1423 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1424 (riscv_get_priv_spec_class): Likewise.
1425
3c3d0376
AM		 14262020-06-01 Alan Modra <amodra@gmail.com>
1427
1428 * bpf-desc.c: Regenerate.
1429
78c1c354
JM		 14302020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1431 David Faust <david.faust@oracle.com>
1432
1433 * bpf-desc.c: Regenerate.
1434 * bpf-opc.h: Likewise.
1435 * bpf-opc.c: Likewise.
1436 * bpf-dis.c: Likewise.
1437
efcf5fb5
AM		 14382020-05-28 Alan Modra <amodra@gmail.com>
1439
1440 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1441 values.
1442
ab382d64
AM		 14432020-05-28 Alan Modra <amodra@gmail.com>
1444
1445 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1446 immediates.
1447 (print_insn_ns32k): Revert last change.
1448
151f5de4
NC		 14492020-05-28 Nick Clifton <nickc@redhat.com>
1450
1451 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1452 static.
1453
25e1eca8
SL		 14542020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1455
1456 Fix extraction of signed constants in nios2 disassembler (again).
1457
1458 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1459 extractions of signed fields.
1460
57b17940
SSF		 14612020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1462
1463 * s390-opc.txt: Relocate vector load/store instructions with
1464 additional alignment parameter and change architecture level
1465 constraint from z14 to z13.
1466
d96bf37b
AM		 14672020-05-21 Alan Modra <amodra@gmail.com>
1468
1469 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1470 * sparc-dis.c: Likewise.
1471 * tic4x-dis.c: Likewise.
1472 * xtensa-dis.c: Likewise.
1473 * bpf-desc.c: Regenerate.
1474 * epiphany-desc.c: Regenerate.
1475 * fr30-desc.c: Regenerate.
1476 * frv-desc.c: Regenerate.
1477 * ip2k-desc.c: Regenerate.
1478 * iq2000-desc.c: Regenerate.
1479 * lm32-desc.c: Regenerate.
1480 * m32c-desc.c: Regenerate.
1481 * m32r-desc.c: Regenerate.
1482 * mep-asm.c: Regenerate.
1483 * mep-desc.c: Regenerate.
1484 * mt-desc.c: Regenerate.
1485 * or1k-desc.c: Regenerate.
1486 * xc16x-desc.c: Regenerate.
1487 * xstormy16-desc.c: Regenerate.
1488
8f595e9b
NC		 14892020-05-20 Nelson Chu <nelson.chu@sifive.com>
1490
1491 * riscv-opc.c (riscv_ext_version_table): The table used to store
1492 all information about the supported spec and the corresponding ISA
1493 versions. Currently, only Zicsr is supported to verify the
1494 correctness of Z sub extension settings. Others will be supported
1495 in the future patches.
1496 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1497 classes and the corresponding strings.
1498 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1499 spec class by giving a ISA spec string.
1500 * riscv-opc.c (struct priv_spec_t): New structure.
1501 (struct priv_spec_t priv_specs): List for all supported privilege spec
1502 classes and the corresponding strings.
1503 (riscv_get_priv_spec_class): New function. Get the corresponding
1504 privilege spec class by giving a spec string.
1505 (riscv_get_priv_spec_name): New function. Get the corresponding
1506 privilege spec string by giving a CSR version class.
1507 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1508 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1509 according to the chosen version. Build a hash table riscv_csr_hash to
1510 store the valid CSR for the chosen pirv verison. Dump the direct
1511 CSR address rather than it's name if it is invalid.
1512 (parse_riscv_dis_option_without_args): New function. Parse the options
1513 without arguments.
1514 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1515 parse the options without arguments first, and then handle the options
1516 with arguments. Add the new option -Mpriv-spec, which has argument.
1517 * riscv-dis.c (print_riscv_disassembler_options): Add description
1518 about the new OBJDUMP option.
1519
3d205eb4
PB		 15202020-05-19 Peter Bergner <bergner@linux.ibm.com>
1521
1522 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1523 WC values on POWER10 sync, dcbf and wait instructions.
1524 (insert_pl, extract_pl): New functions.
1525 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1526 (LS3): New , 3-bit L for sync.
1527 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1528 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1529 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1530 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1531 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1532 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1533 <wait>: Enable PL operand on POWER10.
1534 <dcbf>: Enable L3OPT operand on POWER10.
1535 <sync>: Enable SC2 operand on POWER10.
1536
a501eb44
SH		 15372020-05-19 Stafford Horne <shorne@gmail.com>
1538
1539 PR 25184
1540 * or1k-asm.c: Regenerate.
1541 * or1k-desc.c: Regenerate.
1542 * or1k-desc.h: Regenerate.
1543 * or1k-dis.c: Regenerate.
1544 * or1k-ibld.c: Regenerate.
1545 * or1k-opc.c: Regenerate.
1546 * or1k-opc.h: Regenerate.
1547 * or1k-opinst.c: Regenerate.
1548
3b646889
AM		 15492020-05-11 Alan Modra <amodra@gmail.com>
1550
1551 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1552 xsmaxcqp, xsmincqp.
1553
9cc4ce88
AM		 15542020-05-11 Alan Modra <amodra@gmail.com>
1555
1556 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1557 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1558
5d57bc3f
AM		 15592020-05-11 Alan Modra <amodra@gmail.com>
1560
1561 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1562
66ef5847
AM		 15632020-05-11 Alan Modra <amodra@gmail.com>
1564
1565 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1566 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1567
4f3e9537
PB		 15682020-05-11 Peter Bergner <bergner@linux.ibm.com>
1569
1570 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1571 mnemonics.
1572
ec40e91c
AM		 15732020-05-11 Alan Modra <amodra@gmail.com>
1574
1575 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1576 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1577 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1578 (prefix_opcodes): Add xxeval.
1579
d7e97a76
AM		 15802020-05-11 Alan Modra <amodra@gmail.com>
1581
1582 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1583 xxgenpcvwm, xxgenpcvdm.
1584
fdefed7c
AM		 15852020-05-11 Alan Modra <amodra@gmail.com>
1586
1587 * ppc-opc.c (MP, VXVAM_MASK): Define.
1588 (VXVAPS_MASK): Use VXVA_MASK.
1589 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1590 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1591 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1592 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1593
aa3c112f
AM		 15942020-05-11 Alan Modra <amodra@gmail.com>
1595 Peter Bergner <bergner@linux.ibm.com>
1596
1597 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1598 New functions.
1599 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1600 YMSK2, XA6a, XA6ap, XB6a entries.
1601 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1602 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1603 (PPCVSX4): Define.
1604 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1605 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1606 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1607 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1608 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1609 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1610 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1611 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1612 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1613 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1614 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1615 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1616 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1617 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1618
6edbfd3b
AM		 16192020-05-11 Alan Modra <amodra@gmail.com>
1620
1621 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1622 (insert_xts, extract_xts): New functions.
1623 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1624 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1625 (VXRC_MASK, VXSH_MASK): Define.
1626 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1627 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1628 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1629 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1630 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1631 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1632 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1633
c7d7aea2
AM		 16342020-05-11 Alan Modra <amodra@gmail.com>
1635
1636 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1637 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1638 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1639 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1640 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1641
94ba9882
AM		 16422020-05-11 Alan Modra <amodra@gmail.com>
1643
1644 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1645 (XTP, DQXP, DQXP_MASK): Define.
1646 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1647 (prefix_opcodes): Add plxvp and pstxvp.
1648
f4791f1a
AM		 16492020-05-11 Alan Modra <amodra@gmail.com>
1650
1651 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1652 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1653 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1654
3ff0a5ba
PB		 16552020-05-11 Peter Bergner <bergner@linux.ibm.com>
1656
1657 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1658
afef4fe9
PB		 16592020-05-11 Peter Bergner <bergner@linux.ibm.com>
1660
1661 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1662 (L1OPT): Define.
1663 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1664
1224c05d
PB		 16652020-05-11 Peter Bergner <bergner@linux.ibm.com>
1666
1667 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1668
6bbb0c05
AM		 16692020-05-11 Alan Modra <amodra@gmail.com>
1670
1671 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1672
7c1f4227
AM		 16732020-05-11 Alan Modra <amodra@gmail.com>
1674
1675 * ppc-dis.c (ppc_opts): Add "power10" entry.
1676 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1677 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1678
73199c2b
NC		 16792020-05-11 Nick Clifton <nickc@redhat.com>
1680
1681 * po/fr.po: Updated French translation.
1682
09c1e68a
AC		 16832020-04-30 Alex Coplan <alex.coplan@arm.com>
1684
1685 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1686 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1687 (operand_general_constraint_met_p): validate
1688 AARCH64_OPND_UNDEFINED.
1689 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1690 for FLD_imm16_2.
1691 * aarch64-asm-2.c: Regenerated.
1692 * aarch64-dis-2.c: Regenerated.
1693 * aarch64-opc-2.c: Regenerated.
1694
9654d51a
NC		 16952020-04-29 Nick Clifton <nickc@redhat.com>
1696
1697 PR 22699
1698 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1699 and SETRC insns.
1700
c2e71e57
NC		 17012020-04-29 Nick Clifton <nickc@redhat.com>
1702
1703 * po/sv.po: Updated Swedish translation.
1704
5c936ef5
NC		 17052020-04-29 Nick Clifton <nickc@redhat.com>
1706
1707 PR 22699
1708 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1709 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1710 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1711 IMM0_8U case.
1712
bb2a1453
AS		 17132020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1714
1715 PR 25848
1716 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1717 cmpi only on m68020up and cpu32.
1718
c2e5c986
SD		 17192020-04-20 Sudakshina Das <sudi.das@arm.com>
1720
1721 * aarch64-asm.c (aarch64_ins_none): New.
1722 * aarch64-asm.h (ins_none): New declaration.
1723 * aarch64-dis.c (aarch64_ext_none): New.
1724 * aarch64-dis.h (ext_none): New declaration.
1725 * aarch64-opc.c (aarch64_print_operand): Update case for
1726 AARCH64_OPND_BARRIER_PSB.
1727 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1728 (AARCH64_OPERANDS): Update inserter/extracter for
1729 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1730 * aarch64-asm-2.c: Regenerated.
1731 * aarch64-dis-2.c: Regenerated.
1732 * aarch64-opc-2.c: Regenerated.
1733
8a6e1d1d
SD		 17342020-04-20 Sudakshina Das <sudi.das@arm.com>
1735
1736 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1737 (aarch64_feature_ras, RAS): Likewise.
1738 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1739 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1740 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1741 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1742 * aarch64-asm-2.c: Regenerated.
1743 * aarch64-dis-2.c: Regenerated.
1744 * aarch64-opc-2.c: Regenerated.
1745
e409955d
FS		 17462020-04-17 Fredrik Strupe <fredrik@strupe.net>
1747
1748 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1749 (print_insn_neon): Support disassembly of conditional
1750 instructions.
1751
c54a9b56
DF		 17522020-02-16 David Faust <david.faust@oracle.com>
1753
1754 * bpf-desc.c: Regenerate.
1755 * bpf-desc.h: Likewise.
1756 * bpf-opc.c: Regenerate.
1757 * bpf-opc.h: Likewise.
1758
bb651e8b
CL		 17592020-04-07 Lili Cui <lili.cui@intel.com>
1760
1761 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1762 (prefix_table): New instructions (see prefixes above).
1763 (rm_table): Likewise
1764 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1765 CPU_ANY_TSXLDTRK_FLAGS.
1766 (cpu_flags): Add CpuTSXLDTRK.
1767 * i386-opc.h (enum): Add CpuTSXLDTRK.
1768 (i386_cpu_flags): Add cputsxldtrk.
1769 * i386-opc.tbl: Add XSUSPLDTRK insns.
1770 * i386-init.h: Regenerate.
1771 * i386-tbl.h: Likewise.
1772
4b27d27c
L		 17732020-04-02 Lili Cui <lili.cui@intel.com>
1774
1775 * i386-dis.c (prefix_table): New instructions serialize.
1776 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1777 CPU_ANY_SERIALIZE_FLAGS.
1778 (cpu_flags): Add CpuSERIALIZE.
1779 * i386-opc.h (enum): Add CpuSERIALIZE.
1780 (i386_cpu_flags): Add cpuserialize.
1781 * i386-opc.tbl: Add SERIALIZE insns.
1782 * i386-init.h: Regenerate.
1783 * i386-tbl.h: Likewise.
1784
832a5807
AM		 17852020-03-26 Alan Modra <amodra@gmail.com>
1786
1787 * disassemble.h (opcodes_assert): Declare.
1788 (OPCODES_ASSERT): Define.
1789 * disassemble.c: Don't include assert.h. Include opintl.h.
1790 (opcodes_assert): New function.
1791 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1792 (bfd_h8_disassemble): Reduce size of data array. Correctly
1793 calculate maxlen. Omit insn decoding when insn length exceeds
1794 maxlen. Exit from nibble loop when looking for E, before
1795 accessing next data byte. Move processing of E outside loop.
1796 Replace tests of maxlen in loop with assertions.
1797
4c4addbe
AM		 17982020-03-26 Alan Modra <amodra@gmail.com>
1799
1800 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1801
a18cd0ca
AM		 18022020-03-25 Alan Modra <amodra@gmail.com>
1803
1804 * z80-dis.c (suffix): Init mybuf.
1805
57cb32b3
AM		 18062020-03-22 Alan Modra <amodra@gmail.com>
1807
1808 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1809 successflly read from section.
1810
beea5cc1
AM		 18112020-03-22 Alan Modra <amodra@gmail.com>
1812
1813 * arc-dis.c (find_format): Use ISO C string concatenation rather
1814 than line continuation within a string. Don't access needs_limm
1815 before testing opcode != NULL.
1816
03704c77
AM		 18172020-03-22 Alan Modra <amodra@gmail.com>
1818
1819 * ns32k-dis.c (print_insn_arg): Update comment.
1820 (print_insn_ns32k): Reduce size of index_offset array, and
1821 initialize, passing -1 to print_insn_arg for args that are not
1822 an index. Don't exit arg loop early. Abort on bad arg number.
1823
d1023b5d
AM		 18242020-03-22 Alan Modra <amodra@gmail.com>
1825
1826 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1827 * s12z-opc.c: Formatting.
1828 (operands_f): Return an int.
1829 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1830 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1831 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1832 (exg_sex_discrim): Likewise.
1833 (create_immediate_operand, create_bitfield_operand),
1834 (create_register_operand_with_size, create_register_all_operand),
1835 (create_register_all16_operand, create_simple_memory_operand),
1836 (create_memory_operand, create_memory_auto_operand): Don't
1837 segfault on malloc failure.
1838 (z_ext24_decode): Return an int status, negative on fail, zero
1839 on success.
1840 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1841 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1842 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1843 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1844 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1845 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1846 (loop_primitive_decode, shift_decode, psh_pul_decode),
1847 (bit_field_decode): Similarly.
1848 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1849 to return value, update callers.
1850 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1851 Don't segfault on NULL operand.
1852 (decode_operation): Return OP_INVALID on first fail.
1853 (decode_s12z): Check all reads, returning -1 on fail.
1854
340f3ac8
AM		 18552020-03-20 Alan Modra <amodra@gmail.com>
1856
1857 * metag-dis.c (print_insn_metag): Don't ignore status from
1858 read_memory_func.
1859
fe90ae8a
AM		 18602020-03-20 Alan Modra <amodra@gmail.com>
1861
1862 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1863 Initialize parts of buffer not written when handling a possible
1864 2-byte insn at end of section. Don't attempt decoding of such
1865 an insn by the 4-byte machinery.
1866
833d919c
AM		 18672020-03-20 Alan Modra <amodra@gmail.com>
1868
1869 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1870 partially filled buffer. Prevent lookup of 4-byte insns when
1871 only VLE 2-byte insns are possible due to section size. Print
1872 ".word" rather than ".long" for 2-byte leftovers.
1873
327ef784
NC		 18742020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1875
1876 PR 25641
1877 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1878
1673df32
JB		 18792020-03-13 Jan Beulich <jbeulich@suse.com>
1880
1881 * i386-dis.c (X86_64_0D): Rename to ...
1882 (X86_64_0E): ... this.
1883
384f3689
L		 18842020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1885
1886 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1887 * Makefile.in: Regenerated.
1888
865e2027
JB		 18892020-03-09 Jan Beulich <jbeulich@suse.com>
1890
1891 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1892 3-operand pseudos.
1893 * i386-tbl.h: Re-generate.
1894
2f13234b
JB		 18952020-03-09 Jan Beulich <jbeulich@suse.com>
1896
1897 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1898 vprot*, vpsha*, and vpshl*.
1899 * i386-tbl.h: Re-generate.
1900
3fabc179
JB		 19012020-03-09 Jan Beulich <jbeulich@suse.com>
1902
1903 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1904 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1905 * i386-tbl.h: Re-generate.
1906
3677e4c1
JB		 19072020-03-09 Jan Beulich <jbeulich@suse.com>
1908
1909 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1910 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1911 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1912 * i386-tbl.h: Re-generate.
1913
4c4898e8
JB		 19142020-03-09 Jan Beulich <jbeulich@suse.com>
1915
1916 * i386-gen.c (struct template_arg, struct template_instance,
1917 struct template_param, struct template, templates,
1918 parse_template, expand_templates): New.
1919 (process_i386_opcodes): Various local variables moved to
1920 expand_templates. Call parse_template and expand_templates.
1921 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1922 * i386-tbl.h: Re-generate.
1923
bc49bfd8
JB		 19242020-03-06 Jan Beulich <jbeulich@suse.com>
1925
1926 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1927 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1928 register and memory source templates. Replace VexW= by VexW*
1929 where applicable.
1930 * i386-tbl.h: Re-generate.
1931
4873e243
JB		 19322020-03-06 Jan Beulich <jbeulich@suse.com>
1933
1934 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1935 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1936 * i386-tbl.h: Re-generate.
1937
672a349b
JB		 19382020-03-06 Jan Beulich <jbeulich@suse.com>
1939
1940 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1941 * i386-tbl.h: Re-generate.
1942
4ed21b58
JB		 19432020-03-06 Jan Beulich <jbeulich@suse.com>
1944
1945 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1946 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1947 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1948 VexW0 on SSE2AVX variants.
1949 (vmovq): Drop NoRex64 from XMM/XMM variants.
1950 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1951 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1952 applicable use VexW0.
1953 * i386-tbl.h: Re-generate.
1954
643bb870
JB		 19552020-03-06 Jan Beulich <jbeulich@suse.com>
1956
1957 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1958 * i386-opc.h (Rex64): Delete.
1959 (struct i386_opcode_modifier): Remove rex64 field.
1960 * i386-opc.tbl (crc32): Drop Rex64.
1961 Replace Rex64 with Size64 everywhere else.
1962 * i386-tbl.h: Re-generate.
1963
a23b33b3
JB		 19642020-03-06 Jan Beulich <jbeulich@suse.com>
1965
1966 * i386-dis.c (OP_E_memory): Exclude recording of used address
1967 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1968 addressed memory operands for MPX insns.
1969
a0497384
JB		 19702020-03-06 Jan Beulich <jbeulich@suse.com>
1971
1972 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1973 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1974 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1975 (ptwrite): Split into non-64-bit and 64-bit forms.
1976 * i386-tbl.h: Re-generate.
1977
b630c145
JB		 19782020-03-06 Jan Beulich <jbeulich@suse.com>
1979
1980 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1981 template.
1982 * i386-tbl.h: Re-generate.
1983
a847e322
JB		 19842020-03-04 Jan Beulich <jbeulich@suse.com>
1985
1986 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1987 (prefix_table): Move vmmcall here. Add vmgexit.
1988 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1989 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1990 (cpu_flags): Add CpuSEV_ES entry.
1991 * i386-opc.h (CpuSEV_ES): New.
1992 (union i386_cpu_flags): Add cpusev_es field.
1993 * i386-opc.tbl (vmgexit): New.
1994 * i386-init.h, i386-tbl.h: Re-generate.
1995
3cd7f3e3
L		 19962020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1997
1998 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1999 with MnemonicSize.
2000 * i386-opc.h (IGNORESIZE): New.
2001 (DEFAULTSIZE): Likewise.
2002 (IgnoreSize): Removed.
2003 (DefaultSize): Likewise.
2004 (MnemonicSize): New.
2005 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2006 mnemonicsize.
2007 * i386-opc.tbl (IgnoreSize): New.
2008 (DefaultSize): Likewise.
2009 * i386-tbl.h: Regenerated.
2010
b8ba1385
SB		 20112020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2012
2013 PR 25627
2014 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2015 instructions.
2016
10d97a0f
L		 20172020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2018
2019 PR gas/25622
2020 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2021 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2022 * i386-tbl.h: Regenerated.
2023
dc1e8a47
AM		 20242020-02-26 Alan Modra <amodra@gmail.com>
2025
2026 * aarch64-asm.c: Indent labels correctly.
2027 * aarch64-dis.c: Likewise.
2028 * aarch64-gen.c: Likewise.
2029 * aarch64-opc.c: Likewise.
2030 * alpha-dis.c: Likewise.
2031 * i386-dis.c: Likewise.
2032 * nds32-asm.c: Likewise.
2033 * nfp-dis.c: Likewise.
2034 * visium-dis.c: Likewise.
2035
265b4673
CZ		 20362020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2037
2038 * arc-regs.h (int_vector_base): Make it available for all ARC
2039 CPUs.
2040
bd0cf5a6
NC		 20412020-02-20 Nelson Chu <nelson.chu@sifive.com>
2042
2043 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2044 changed.
2045
fa164239
JW		 20462020-02-19 Nelson Chu <nelson.chu@sifive.com>
2047
2048 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2049 c.mv/c.li if rs1 is zero.
2050
272a84b1
L		 20512020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2052
2053 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2054 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2055 CPU_POPCNT_FLAGS.
2056 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2057 * i386-opc.h (CpuABM): Removed.
2058 (CpuPOPCNT): New.
2059 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2060 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2061 popcnt. Remove CpuABM from lzcnt.
2062 * i386-init.h: Regenerated.
2063 * i386-tbl.h: Likewise.
2064
1f730c46
JB		 20652020-02-17 Jan Beulich <jbeulich@suse.com>
2066
2067 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2068 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2069 VexW1 instead of open-coding them.
2070 * i386-tbl.h: Re-generate.
2071
c8f8eebc
JB		 20722020-02-17 Jan Beulich <jbeulich@suse.com>
2073
2074 * i386-opc.tbl (AddrPrefixOpReg): Define.
2075 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2076 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2077 templates. Drop NoRex64.
2078 * i386-tbl.h: Re-generate.
2079
b9915cbc
JB		 20802020-02-17 Jan Beulich <jbeulich@suse.com>
2081
2082 PR gas/6518
2083 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2084 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2085 into Intel syntax instance (with Unpsecified) and AT&T one
2086 (without).
2087 (vcvtneps2bf16): Likewise, along with folding the two so far
2088 separate ones.
2089 * i386-tbl.h: Re-generate.
2090
ce504911
L		 20912020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2092
2093 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2094 CPU_ANY_SSE4A_FLAGS.
2095
dabec65d
AM		 20962020-02-17 Alan Modra <amodra@gmail.com>
2097
2098 * i386-gen.c (cpu_flag_init): Correct last change.
2099
af5c13b0
L		 21002020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2101
2102 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2103 CPU_ANY_SSE4_FLAGS.
2104
6867aac0
L		 21052020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2106
2107 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2108 (movzx): Likewise.
2109
65fca059
JB		 21102020-02-14 Jan Beulich <jbeulich@suse.com>
2111
2112 PR gas/25438
2113 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2114 destination for Cpu64-only variant.
2115 (movzx): Fold patterns.
2116 * i386-tbl.h: Re-generate.
2117
7deea9aa
JB		 21182020-02-13 Jan Beulich <jbeulich@suse.com>
2119
2120 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2121 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2122 CPU_ANY_SSE4_FLAGS entry.
2123 * i386-init.h: Re-generate.
2124
6c0946d0
JB		 21252020-02-12 Jan Beulich <jbeulich@suse.com>
2126
2127 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2128 with Unspecified, making the present one AT&T syntax only.
2129 * i386-tbl.h: Re-generate.
2130
ddb56fe6
JB		 21312020-02-12 Jan Beulich <jbeulich@suse.com>
2132
2133 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2134 * i386-tbl.h: Re-generate.
2135
5990e377
JB		 21362020-02-12 Jan Beulich <jbeulich@suse.com>
2137
2138 PR gas/24546
2139 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2140 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2141 Amd64 and Intel64 templates.
2142 (call, jmp): Likewise for far indirect variants. Dro
2143 Unspecified.
2144 * i386-tbl.h: Re-generate.
2145
50128d0c
JB		 21462020-02-11 Jan Beulich <jbeulich@suse.com>
2147
2148 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2149 * i386-opc.h (ShortForm): Delete.
2150 (struct i386_opcode_modifier): Remove shortform field.
2151 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2152 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2153 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2154 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2155 Drop ShortForm.
2156 * i386-tbl.h: Re-generate.
2157
1e05b5c4
JB		 21582020-02-11 Jan Beulich <jbeulich@suse.com>
2159
2160 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2161 fucompi): Drop ShortForm from operand-less templates.
2162 * i386-tbl.h: Re-generate.
2163
2f5dd314
AM		 21642020-02-11 Alan Modra <amodra@gmail.com>
2165
2166 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2167 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2168 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2169 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2170 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2171
5aae9ae9
MM		 21722020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2173
2174 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2175 (cde_opcodes): Add VCX* instructions.
2176
4934a27c
MM		 21772020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2178 Matthew Malcomson <matthew.malcomson@arm.com>
2179
2180 * arm-dis.c (struct cdeopcode32): New.
2181 (CDE_OPCODE): New macro.
2182 (cde_opcodes): New disassembly table.
2183 (regnames): New option to table.
2184 (cde_coprocs): New global variable.
2185 (print_insn_cde): New
2186 (print_insn_thumb32): Use print_insn_cde.
2187 (parse_arm_disassembler_options): Parse coprocN args.
2188
4b5aaf5f
L		 21892020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2190
2191 PR gas/25516
2192 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2193 with ISA64.
2194 * i386-opc.h (AMD64): Removed.
2195 (Intel64): Likewose.
2196 (AMD64): New.
2197 (INTEL64): Likewise.
2198 (INTEL64ONLY): Likewise.
2199 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2200 * i386-opc.tbl (Amd64): New.
2201 (Intel64): Likewise.
2202 (Intel64Only): Likewise.
2203 Replace AMD64 with Amd64. Update sysenter/sysenter with
2204 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2205 * i386-tbl.h: Regenerated.
2206
9fc0b501
SB		 22072020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2208
2209 PR 25469
2210 * z80-dis.c: Add support for GBZ80 opcodes.
2211
c5d7be0c
AM		 22122020-02-04 Alan Modra <amodra@gmail.com>
2213
2214 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2215
44e4546f
AM		 22162020-02-03 Alan Modra <amodra@gmail.com>
2217
2218 * m32c-ibld.c: Regenerate.
2219
b2b1453a
AM		 22202020-02-01 Alan Modra <amodra@gmail.com>
2221
2222 * frv-ibld.c: Regenerate.
2223
4102be5c
JB		 22242020-01-31 Jan Beulich <jbeulich@suse.com>
2225
2226 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2227 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2228 (OP_E_memory): Replace xmm_mdq_mode case label by
2229 vex_scalar_w_dq_mode one.
2230 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2231
825bd36c
JB		 22322020-01-31 Jan Beulich <jbeulich@suse.com>
2233
2234 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2235 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2236 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2237 (intel_operand_size): Drop vex_w_dq_mode case label.
2238
c3036ed0
RS		 22392020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2240
2241 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2242 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2243
0c115f84
AM		 22442020-01-30 Alan Modra <amodra@gmail.com>
2245
2246 * m32c-ibld.c: Regenerate.
2247
bd434cc4
JM		 22482020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2249
2250 * bpf-opc.c: Regenerate.
2251
aeab2b26
JB		 22522020-01-30 Jan Beulich <jbeulich@suse.com>
2253
2254 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2255 (dis386): Use them to replace C2/C3 table entries.
2256 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2257 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2258 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2259 * i386-tbl.h: Re-generate.
2260
62b3f548
JB		 22612020-01-30 Jan Beulich <jbeulich@suse.com>
2262
2263 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2264 forms.
2265 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2266 DefaultSize.
2267 * i386-tbl.h: Re-generate.
2268
1bd8ae10
AM		 22692020-01-30 Alan Modra <amodra@gmail.com>
2270
2271 * tic4x-dis.c (tic4x_dp): Make unsigned.
2272
bc31405e
L		 22732020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2274 Jan Beulich <jbeulich@suse.com>
2275
2276 PR binutils/25445
2277 * i386-dis.c (MOVSXD_Fixup): New function.
2278 (movsxd_mode): New enum.
2279 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2280 (intel_operand_size): Handle movsxd_mode.
2281 (OP_E_register): Likewise.
2282 (OP_G): Likewise.
2283 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2284 register on movsxd. Add movsxd with 16-bit destination register
2285 for AMD64 and Intel64 ISAs.
2286 * i386-tbl.h: Regenerated.
2287
7568c93b
TC		 22882020-01-27 Tamar Christina <tamar.christina@arm.com>
2289
2290 PR 25403
2291 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2292 * aarch64-asm-2.c: Regenerate
2293 * aarch64-dis-2.c: Likewise.
2294 * aarch64-opc-2.c: Likewise.
2295
c006a730
JB		 22962020-01-21 Jan Beulich <jbeulich@suse.com>
2297
2298 * i386-opc.tbl (sysret): Drop DefaultSize.
2299 * i386-tbl.h: Re-generate.
2300
c906a69a
JB		 23012020-01-21 Jan Beulich <jbeulich@suse.com>
2302
2303 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2304 Dword.
2305 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2306 * i386-tbl.h: Re-generate.
2307
26916852
NC		 23082020-01-20 Nick Clifton <nickc@redhat.com>
2309
2310 * po/de.po: Updated German translation.
2311 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2312 * po/uk.po: Updated Ukranian translation.
2313
4d6cbb64
AM		 23142020-01-20 Alan Modra <amodra@gmail.com>
2315
2316 * hppa-dis.c (fput_const): Remove useless cast.
2317
2bddb71a
AM		 23182020-01-20 Alan Modra <amodra@gmail.com>
2319
2320 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2321
1b1bb2c6
NC		 23222020-01-18 Nick Clifton <nickc@redhat.com>
2323
2324 * configure: Regenerate.
2325 * po/opcodes.pot: Regenerate.
2326
ae774686
NC		 23272020-01-18 Nick Clifton <nickc@redhat.com>
2328
2329 Binutils 2.34 branch created.
2330
07f1f3aa
CB		 23312020-01-17 Christian Biesinger <cbiesinger@google.com>
2332
2333 * opintl.h: Fix spelling error (seperate).
2334
42e04b36
L		 23352020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2336
2337 * i386-opc.tbl: Add {vex} pseudo prefix.
2338 * i386-tbl.h: Regenerated.
2339
2da2eaf4
AV		 23402020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2341
2342 PR 25376
2343 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2344 (neon_opcodes): Likewise.
2345 (select_arm_features): Make sure we enable MVE bits when selecting
2346 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2347 any architecture.
2348
d0849eed
JB		 23492020-01-16 Jan Beulich <jbeulich@suse.com>
2350
2351 * i386-opc.tbl: Drop stale comment from XOP section.
2352
9cf70a44
JB		 23532020-01-16 Jan Beulich <jbeulich@suse.com>
2354
2355 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2356 (extractps): Add VexWIG to SSE2AVX forms.
2357 * i386-tbl.h: Re-generate.
2358
4814632e
JB		 23592020-01-16 Jan Beulich <jbeulich@suse.com>
2360
2361 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2362 Size64 from and use VexW1 on SSE2AVX forms.
2363 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2364 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2365 * i386-tbl.h: Re-generate.
2366
aad09917
AM		 23672020-01-15 Alan Modra <amodra@gmail.com>
2368
2369 * tic4x-dis.c (tic4x_version): Make unsigned long.
2370 (optab, optab_special, registernames): New file scope vars.
2371 (tic4x_print_register): Set up registernames rather than
2372 malloc'd registertable.
2373 (tic4x_disassemble): Delete optable and optable_special. Use
2374 optab and optab_special instead. Throw away old optab,
2375 optab_special and registernames when info->mach changes.
2376
7a6bf3be
SB		 23772020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2378
2379 PR 25377
2380 * z80-dis.c (suffix): Use .db instruction to generate double
2381 prefix.
2382
ca1eaac0
AM		 23832020-01-14 Alan Modra <amodra@gmail.com>
2384
2385 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2386 values to unsigned before shifting.
2387
1d67fe3b
TT		 23882020-01-13 Thomas Troeger <tstroege@gmx.de>
2389
2390 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2391 flow instructions.
2392 (print_insn_thumb16, print_insn_thumb32): Likewise.
2393 (print_insn): Initialize the insn info.
2394 * i386-dis.c (print_insn): Initialize the insn info fields, and
2395 detect jumps.
2396
5e4f7e05
CZ		 23972012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2398
2399 * arc-opc.c (C_NE): Make it required.
2400
b9fe6b8a
CZ		 24012012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2402
2403 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2404 reserved register name.
2405
90dee485
AM		 24062020-01-13 Alan Modra <amodra@gmail.com>
2407
2408 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2409 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2410
febda64f
AM		 24112020-01-13 Alan Modra <amodra@gmail.com>
2412
2413 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2414 result of wasm_read_leb128 in a uint64_t and check that bits
2415 are not lost when copying to other locals. Use uint32_t for
2416 most locals. Use PRId64 when printing int64_t.
2417
df08b588
AM		 24182020-01-13 Alan Modra <amodra@gmail.com>
2419
2420 * score-dis.c: Formatting.
2421 * score7-dis.c: Formatting.
2422
b2c759ce
AM		 24232020-01-13 Alan Modra <amodra@gmail.com>
2424
2425 * score-dis.c (print_insn_score48): Use unsigned variables for
2426 unsigned values. Don't left shift negative values.
2427 (print_insn_score32): Likewise.
2428 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2429
5496abe1
AM		 24302020-01-13 Alan Modra <amodra@gmail.com>
2431
2432 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2433
202e762b
AM		 24342020-01-13 Alan Modra <amodra@gmail.com>
2435
2436 * fr30-ibld.c: Regenerate.
2437
7ef412cf
AM		 24382020-01-13 Alan Modra <amodra@gmail.com>
2439
2440 * xgate-dis.c (print_insn): Don't left shift signed value.
2441 (ripBits): Formatting, use 1u.
2442
7f578b95
AM		 24432020-01-10 Alan Modra <amodra@gmail.com>
2444
2445 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2446 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2447
441af85b
AM		 24482020-01-10 Alan Modra <amodra@gmail.com>
2449
2450 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2451 and XRREG value earlier to avoid a shift with negative exponent.
2452 * m10200-dis.c (disassemble): Similarly.
2453
bce58db4
NC		 24542020-01-09 Nick Clifton <nickc@redhat.com>
2455
2456 PR 25224
2457 * z80-dis.c (ld_ii_ii): Use correct cast.
2458
40c75bc8
SB		 24592020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2460
2461 PR 25224
2462 * z80-dis.c (ld_ii_ii): Use character constant when checking
2463 opcode byte value.
2464
d835a58b
JB		 24652020-01-09 Jan Beulich <jbeulich@suse.com>
2466
2467 * i386-dis.c (SEP_Fixup): New.
2468 (SEP): Define.
2469 (dis386_twobyte): Use it for sysenter/sysexit.
2470 (enum x86_64_isa): Change amd64 enumerator to value 1.
2471 (OP_J): Compare isa64 against intel64 instead of amd64.
2472 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2473 forms.
2474 * i386-tbl.h: Re-generate.
2475
030a2e78
AM		 24762020-01-08 Alan Modra <amodra@gmail.com>
2477
2478 * z8k-dis.c: Include libiberty.h
2479 (instr_data_s): Make max_fetched unsigned.
2480 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2481 Don't exceed byte_info bounds.
2482 (output_instr): Make num_bytes unsigned.
2483 (unpack_instr): Likewise for nibl_count and loop.
2484 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2485 idx unsigned.
2486 * z8k-opc.h: Regenerate.
2487
bb82aefe
SV		 24882020-01-07 Shahab Vahedi <shahab@synopsys.com>
2489
2490 * arc-tbl.h (llock): Use 'LLOCK' as class.
2491 (llockd): Likewise.
2492 (scond): Use 'SCOND' as class.
2493 (scondd): Likewise.
2494 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2495 (scondd): Likewise.
2496
cc6aa1a6
AM		 24972020-01-06 Alan Modra <amodra@gmail.com>
2498
2499 * m32c-ibld.c: Regenerate.
2500
660e62b1
AM		 25012020-01-06 Alan Modra <amodra@gmail.com>
2502
2503 PR 25344
2504 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2505 Peek at next byte to prevent recursion on repeated prefix bytes.
2506 Ensure uninitialised "mybuf" is not accessed.
2507 (print_insn_z80): Don't zero n_fetch and n_used here,..
2508 (print_insn_z80_buf): ..do it here instead.
2509
c9ae58fe
AM		 25102020-01-04 Alan Modra <amodra@gmail.com>
2511
2512 * m32r-ibld.c: Regenerate.
2513
5f57d4ec
AM		 25142020-01-04 Alan Modra <amodra@gmail.com>
2515
2516 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2517
2c5c1196
AM		 25182020-01-04 Alan Modra <amodra@gmail.com>
2519
2520 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2521
2e98c6c5
AM		 25222020-01-04 Alan Modra <amodra@gmail.com>
2523
2524 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2525
567dfba2
JB		 25262020-01-03 Jan Beulich <jbeulich@suse.com>
2527
5437a02a
JB		 2528 * aarch64-tbl.h (aarch64_opcode_table): Use
2529 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2530
25312020-01-03 Jan Beulich <jbeulich@suse.com>
2532
2533 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2534 forms of SUDOT and USDOT.
2535
8c45011a
JB		 25362020-01-03 Jan Beulich <jbeulich@suse.com>
2537
5437a02a 2538 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2539 uzip{1,2}.
2540 * opcodes/aarch64-dis-2.c: Re-generate.
2541
f4950f76
JB		 25422020-01-03 Jan Beulich <jbeulich@suse.com>
2543
5437a02a 2544 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2545 FMMLA encoding.
2546 * opcodes/aarch64-dis-2.c: Re-generate.
2547
6655dba2
SB		 25482020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2549
2550 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2551
b14ce8bf
AM		 25522020-01-01 Alan Modra <amodra@gmail.com>
2553
2554 Update year range in copyright notice of all files.
2555
0b114740 2556For older changes see ChangeLog-2019
3499769a 2557\f
0b114740 2558Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2559
2560Copying and distribution of this file, with or without modification,
2561are permitted in any medium without royalty provided the copyright
2562notice and this notice are preserved.
2563
2564Local Variables:
2565mode: change-log
2566left-margin: 8
2567fill-column: 74
2568version-control: never
2569End:
A mirror of the official binutils-gdb repository