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2004-01-19 Jeff Johnston <jjohnstn@redhat.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
9a1d84fb
CD		 12003-06-17 Richard Sandiford <rsandifo@redhat.com>
2
3 * mips.igen (do_dmultx): Fix check for negative operands.
4
ae451ac6
ILT		 52003-05-16 Ian Lance Taylor <ian@airs.com>
6
7 * Makefile.in (SHELL): Make sure this is defined.
8 (various): Use $(SHELL) whenever we invoke move-if-change.
9
dd69d292
CD		 102003-05-03 Chris Demetriou <cgd@broadcom.com>
11
12 * cp1.c: Tweak attribution slightly.
13 * cp1.h: Likewise.
14 * mdmx.c: Likewise.
15 * mdmx.igen: Likewise.
16 * mips3d.igen: Likewise.
17 * sb1.igen: Likewise.
18
bcd0068e
CD		 192003-04-15 Richard Sandiford <rsandifo@redhat.com>
20
21 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
22 unsigned operands.
23
6b4a8935
AC		 242003-02-27 Andrew Cagney <cagney@redhat.com>
25
601da316
AC		 26 * interp.c (sim_open): Rename _bfd to bfd.
27 (sim_create_inferior): Ditto.
6b4a8935 28
d29e330f
CD		 292003-01-14 Chris Demetriou <cgd@broadcom.com>
30
31 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
32
a2353a08
CD		 332003-01-14 Chris Demetriou <cgd@broadcom.com>
34
35 * mips.igen (EI, DI): Remove.
36
80551777
CD		 372003-01-05 Richard Sandiford <rsandifo@redhat.com>
38
39 * Makefile.in (tmp-run-multi): Fix mips16 filter.
40
4c54fc26
CD		 412003-01-04 Richard Sandiford <rsandifo@redhat.com>
42 Andrew Cagney <ac131313@redhat.com>
43 Gavin Romig-Koch <gavin@redhat.com>
44 Graydon Hoare <graydon@redhat.com>
45 Aldy Hernandez <aldyh@redhat.com>
46 Dave Brolley <brolley@redhat.com>
47 Chris Demetriou <cgd@broadcom.com>
48
49 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
50 (sim_mach_default): New variable.
51 (mips64vr-*-*, mips64vrel-*-*): New configurations.
52 Add a new simulator generator, MULTI.
53 * configure: Regenerate.
54 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
55 (multi-run.o): New dependency.
56 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
57 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
58 (tmp-multi): Combine them.
59 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
60 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
61 (distclean-extra): New rule.
62 * sim-main.h: Include bfd.h.
63 (MIPS_MACH): New macro.
64 * mips.igen (vr4120, vr5400, vr5500): New models.
65 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
66 * vr.igen: Replace with new version.
67
e6c674b8
CD		 682003-01-04 Chris Demetriou <cgd@broadcom.com>
69
70 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
71 * configure: Regenerate.
72
28f50ac8
CD		 732002-12-31 Chris Demetriou <cgd@broadcom.com>
74
75 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
76 * mips.igen: Remove all invocations of check_branch_bug and
77 mark_branch_bug.
78
5071ffe6
CD		 792002-12-16 Chris Demetriou <cgd@broadcom.com>
80
81 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
82
06e7837e
CD		 832002-07-30 Chris Demetriou <cgd@broadcom.com>
84
85 * mips.igen (do_load_double, do_store_double): New functions.
86 (LDC1, SDC1): Rename to...
87 (LDC1b, SDC1b): respectively.
88 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
89
2265c243
MS		 902002-07-29 Michael Snyder <msnyder@redhat.com>
91
92 * cp1.c (fp_recip2): Modify initialization expression so that
93 GCC will recognize it as constant.
94
a2f8b4f3
CD		 952002-06-18 Chris Demetriou <cgd@broadcom.com>
96
97 * mdmx.c (SD_): Delete.
98 (Unpredictable): Re-define, for now, to directly invoke
99 unpredictable_action().
100 (mdmx_acc_op): Fix error in .ob immediate handling.
101
b4b6c939
AC		 1022002-06-18 Andrew Cagney <cagney@redhat.com>
103
104 * interp.c (sim_firmware_command): Initialize `address'.
105
c8cca39f
AC		 1062002-06-16 Andrew Cagney <ac131313@redhat.com>
107
108 * configure: Regenerated to track ../common/aclocal.m4 changes.
109
e7e81181
CD		 1102002-06-14 Chris Demetriou <cgd@broadcom.com>
111 Ed Satterthwaite <ehs@broadcom.com>
112
113 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
114 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
115 * mips.igen: Include mips3d.igen.
116 (mips3d): New model name for MIPS-3D ASE instructions.
117 (CVT.W.fmt): Don't use this instruction for word (source) format
118 instructions.
119 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
120 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
121 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
122 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
123 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
124 (RSquareRoot1, RSquareRoot2): New macros.
125 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
126 (fp_rsqrt2): New functions.
127 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
128 * configure: Regenerate.
129
3a2b820e 1302002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 131 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 132
133 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
134 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
135 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
136 (convert): Note that this function is not used for paired-single
137 format conversions.
138 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
139 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
140 (check_fmt_p): Enable paired-single support.
141 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
142 (PUU.PS): New instructions.
143 (CVT.S.fmt): Don't use this instruction for paired-single format
144 destinations.
145 * sim-main.h (FP_formats): New value 'fmt_ps.'
146 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
147 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
148
d18ea9c2
CD		 1492002-06-12 Chris Demetriou <cgd@broadcom.com>
150
151 * mips.igen: Fix formatting of function calls in
152 many FP operations.
153
95fd5cee
CD		 1542002-06-12 Chris Demetriou <cgd@broadcom.com>
155
156 * mips.igen (MOVN, MOVZ): Trace result.
157 (TNEI): Print "tnei" as the opcode name in traces.
158 (CEIL.W): Add disassembly string for traces.
159 (RSQRT.fmt): Make location of disassembly string consistent
160 with other instructions.
161
4f0d55ae
CD		 1622002-06-12 Chris Demetriou <cgd@broadcom.com>
163
164 * mips.igen (X): Delete unused function.
165
3c25f8c7
AC		 1662002-06-08 Andrew Cagney <cagney@redhat.com>
167
168 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
169
f3c08b7e
CD		 1702002-06-07 Chris Demetriou <cgd@broadcom.com>
171 Ed Satterthwaite <ehs@broadcom.com>
172
173 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
174 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
175 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
176 (fp_nmsub): New prototypes.
177 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
178 (NegMultiplySub): New defines.
179 * mips.igen (RSQRT.fmt): Use RSquareRoot().
180 (MADD.D, MADD.S): Replace with...
181 (MADD.fmt): New instruction.
182 (MSUB.D, MSUB.S): Replace with...
183 (MSUB.fmt): New instruction.
184 (NMADD.D, NMADD.S): Replace with...
185 (NMADD.fmt): New instruction.
186 (NMSUB.D, MSUB.S): Replace with...
187 (NMSUB.fmt): New instruction.
188
52714ff9
CD		 1892002-06-07 Chris Demetriou <cgd@broadcom.com>
190 Ed Satterthwaite <ehs@broadcom.com>
191
192 * cp1.c: Fix more comment spelling and formatting.
193 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
194 (denorm_mode): New function.
195 (fpu_unary, fpu_binary): Round results after operation, collect
196 status from rounding operations, and update the FCSR.
197 (convert): Collect status from integer conversions and rounding
198 operations, and update the FCSR. Adjust NaN values that result
199 from conversions. Convert to use sim_io_eprintf rather than
200 fprintf, and remove some debugging code.
201 * cp1.h (fenr_FS): New define.
202
577d8c4b
CD		 2032002-06-07 Chris Demetriou <cgd@broadcom.com>
204
205 * cp1.c (convert): Remove unusable debugging code, and move MIPS
206 rounding mode to sim FP rounding mode flag conversion code into...
207 (rounding_mode): New function.
208
196496ed
CD		 2092002-06-07 Chris Demetriou <cgd@broadcom.com>
210
211 * cp1.c: Clean up formatting of a few comments.
212 (value_fpr): Reformat switch statement.
213
cfe9ea23
CD		 2142002-06-06 Chris Demetriou <cgd@broadcom.com>
215 Ed Satterthwaite <ehs@broadcom.com>
216
217 * cp1.h: New file.
218 * sim-main.h: Include cp1.h.
219 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
220 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
221 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
222 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
223 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
224 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
225 * cp1.c: Don't include sim-fpu.h; already included by
226 sim-main.h. Clean up formatting of some comments.
227 (NaN, Equal, Less): Remove.
228 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
229 (fp_cmp): New functions.
230 * mips.igen (do_c_cond_fmt): Remove.
231 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
232 Compare. Add result tracing.
233 (CxC1): Remove, replace with...
234 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
235 (DMxC1): Remove, replace with...
236 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
237 (MxC1): Remove, replace with...
238 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
239
ee7254b0
CD		 2402002-06-04 Chris Demetriou <cgd@broadcom.com>
241
242 * sim-main.h (FGRIDX): Remove, replace all uses with...
243 (FGR_BASE): New macro.
244 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
245 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
246 (NR_FGR, FGR): Likewise.
247 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
248 * mips.igen: Likewise.
249
d3eb724f
CD		 2502002-06-04 Chris Demetriou <cgd@broadcom.com>
251
252 * cp1.c: Add an FSF Copyright notice to this file.
253
ba46ddd0
CD		 2542002-06-04 Chris Demetriou <cgd@broadcom.com>
255 Ed Satterthwaite <ehs@broadcom.com>
256
257 * cp1.c (Infinity): Remove.
258 * sim-main.h (Infinity): Likewise.
259
260 * cp1.c (fp_unary, fp_binary): New functions.
261 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
262 (fp_sqrt): New functions, implemented in terms of the above.
263 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
264 (Recip, SquareRoot): Remove (replaced by functions above).
265 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
266 (fp_recip, fp_sqrt): New prototypes.
267 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
268 (Recip, SquareRoot): Replace prototypes with #defines which
269 invoke the functions above.
270
18d8a52d
CD		 2712002-06-03 Chris Demetriou <cgd@broadcom.com>
272
273 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
274 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
275 file, remove PARAMS from prototypes.
276 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
277 simulator state arguments.
278 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
279 pass simulator state arguments.
280 * cp1.c (SD): Redefine as CPU_STATE(cpu).
281 (store_fpr, convert): Remove 'sd' argument.
282 (value_fpr): Likewise. Convert to use 'SD' instead.
283
0f154cbd
CD		 2842002-06-03 Chris Demetriou <cgd@broadcom.com>
285
286 * cp1.c (Min, Max): Remove #if 0'd functions.
287 * sim-main.h (Min, Max): Remove.
288
e80fc152
CD		 2892002-06-03 Chris Demetriou <cgd@broadcom.com>
290
291 * cp1.c: fix formatting of switch case and default labels.
292 * interp.c: Likewise.
293 * sim-main.c: Likewise.
294
bad673a9
CD		 2952002-06-03 Chris Demetriou <cgd@broadcom.com>
296
297 * cp1.c: Clean up comments which describe FP formats.
298 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
299
7cbea089
CD		 3002002-06-03 Chris Demetriou <cgd@broadcom.com>
301 Ed Satterthwaite <ehs@broadcom.com>
302
303 * configure.in (mipsisa64sb1*-*-*): New target for supporting
304 Broadcom SiByte SB-1 processor configurations.
305 * configure: Regenerate.
306 * sb1.igen: New file.
307 * mips.igen: Include sb1.igen.
308 (sb1): New model.
309 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
310 * mdmx.igen: Add "sb1" model to all appropriate functions and
311 instructions.
312 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
313 (ob_func, ob_acc): Reference the above.
314 (qh_acc): Adjust to keep the same size as ob_acc.
315 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
316 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
317
909daa82
CD		 3182002-06-03 Chris Demetriou <cgd@broadcom.com>
319
320 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
321
f4f1b9f1
CD		 3222002-06-02 Chris Demetriou <cgd@broadcom.com>
323 Ed Satterthwaite <ehs@broadcom.com>
324
325 * mips.igen (mdmx): New (pseudo-)model.
326 * mdmx.c, mdmx.igen: New files.
327 * Makefile.in (SIM_OBJS): Add mdmx.o.
328 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
329 New typedefs.
330 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
331 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
332 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
333 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
334 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
335 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
336 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
337 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
338 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
339 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
340 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
341 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
342 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
343 (qh_fmtsel): New macros.
344 (_sim_cpu): New member "acc".
345 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
346 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
347
5accf1ff
CD		 3482002-05-01 Chris Demetriou <cgd@broadcom.com>
349
350 * interp.c: Use 'deprecated' rather than 'depreciated.'
351 * sim-main.h: Likewise.
352
402586aa
CD		 3532002-05-01 Chris Demetriou <cgd@broadcom.com>
354
355 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
356 which wouldn't compile anyway.
357 * sim-main.h (unpredictable_action): New function prototype.
358 (Unpredictable): Define to call igen function unpredictable().
359 (NotWordValue): New macro to call igen function not_word_value().
360 (UndefinedResult): Remove.
361 * interp.c (undefined_result): Remove.
362 (unpredictable_action): New function.
363 * mips.igen (not_word_value, unpredictable): New functions.
364 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
365 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
366 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
367 NotWordValue() to check for unpredictable inputs, then
368 Unpredictable() to handle them.
369
c9b9995a
CD		 3702002-02-24 Chris Demetriou <cgd@broadcom.com>
371
372 * mips.igen: Fix formatting of calls to Unpredictable().
373
e1015982
AC		 3742002-04-20 Andrew Cagney <ac131313@redhat.com>
375
376 * interp.c (sim_open): Revert previous change.
377
b882a66b
AO		 3782002-04-18 Alexandre Oliva <aoliva@redhat.com>
379
380 * interp.c (sim_open): Disable chunk of code that wrote code in
381 vector table entries.
382
c429b7dd
CD		 3832002-03-19 Chris Demetriou <cgd@broadcom.com>
384
385 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
386 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
387 unused definitions.
388
37d146fa
CD		 3892002-03-19 Chris Demetriou <cgd@broadcom.com>
390
391 * cp1.c: Fix many formatting issues.
392
07892c0b
CD		 3932002-03-19 Chris G. Demetriou <cgd@broadcom.com>
394
395 * cp1.c (fpu_format_name): New function to replace...
396 (DOFMT): This. Delete, and update all callers.
397 (fpu_rounding_mode_name): New function to replace...
398 (RMMODE): This. Delete, and update all callers.
399
487f79b7
CD		 4002002-03-19 Chris G. Demetriou <cgd@broadcom.com>
401
402 * interp.c: Move FPU support routines from here to...
403 * cp1.c: Here. New file.
404 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
405 (cp1.o): New target.
406
1e799e28
CD		 4072002-03-12 Chris Demetriou <cgd@broadcom.com>
408
409 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
410 * mips.igen (mips32, mips64): New models, add to all instructions
411 and functions as appropriate.
412 (loadstore_ea, check_u64): New variant for model mips64.
413 (check_fmt_p): New variant for models mipsV and mips64, remove
414 mipsV model marking fro other variant.
415 (SLL) Rename to...
416 (SLLa) this.
417 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
418 for mips32 and mips64.
419 (DCLO, DCLZ): New instructions for mips64.
420
82f728db
CD		 4212002-03-07 Chris Demetriou <cgd@broadcom.com>
422
423 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
424 immediate or code as a hex value with the "%#lx" format.
425 (ANDI): Likewise, and fix printed instruction name.
426
b96e7ef1
CD		 4272002-03-05 Chris Demetriou <cgd@broadcom.com>
428
429 * sim-main.h (UndefinedResult, Unpredictable): New macros
430 which currently do nothing.
431
d35d4f70
CD		 4322002-03-05 Chris Demetriou <cgd@broadcom.com>
433
434 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
435 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
436 (status_CU3): New definitions.
437
438 * sim-main.h (ExceptionCause): Add new values for MIPS32
439 and MIPS64: MDMX, MCheck, CacheErr. Update comments
440 for DebugBreakPoint and NMIReset to note their status in
441 MIPS32 and MIPS64.
442 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
443 (SignalExceptionCacheErr): New exception macros.
444
3ad6f714
CD		 4452002-03-05 Chris Demetriou <cgd@broadcom.com>
446
447 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
448 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
449 is always enabled.
450 (SignalExceptionCoProcessorUnusable): Take as argument the
451 unusable coprocessor number.
452
86b77b47
CD		 4532002-03-05 Chris Demetriou <cgd@broadcom.com>
454
455 * mips.igen: Fix formatting of all SignalException calls.
456
97a88e93 4572002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 458
459 * sim-main.h (SIGNEXTEND): Remove.
460
97a88e93 4612002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 462
463 * mips.igen: Remove gencode comment from top of file, fix
464 spelling in another comment.
465
97a88e93 4662002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 467
468 * mips.igen (check_fmt, check_fmt_p): New functions to check
469 whether specific floating point formats are usable.
470 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
471 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
472 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
473 Use the new functions.
474 (do_c_cond_fmt): Remove format checks...
475 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
476
97a88e93 4772002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 478
479 * mips.igen: Fix formatting of check_fpu calls.
480
41774c9d
CD		 4812002-03-03 Chris Demetriou <cgd@broadcom.com>
482
483 * mips.igen (FLOOR.L.fmt): Store correct destination register.
484
4a0bd876
CD		 4852002-03-03 Chris Demetriou <cgd@broadcom.com>
486
487 * mips.igen: Remove whitespace at end of lines.
488
09297648
CD		 4892002-03-02 Chris Demetriou <cgd@broadcom.com>
490
491 * mips.igen (loadstore_ea): New function to do effective
492 address calculations.
493 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
494 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
495 CACHE): Use loadstore_ea to do effective address computations.
496
043b7057
CD		 4972002-03-02 Chris Demetriou <cgd@broadcom.com>
498
499 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
500 * mips.igen (LL, CxC1, MxC1): Likewise.
501
c1e8ada4
CD		 5022002-03-02 Chris Demetriou <cgd@broadcom.com>
503
504 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
505 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
506 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
507 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
508 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
509 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
510 Don't split opcode fields by hand, use the opcode field values
511 provided by igen.
512
3e1dca16
CD		 5132002-03-01 Chris Demetriou <cgd@broadcom.com>
514
515 * mips.igen (do_divu): Fix spacing.
516
517 * mips.igen (do_dsllv): Move to be right before DSLLV,
518 to match the rest of the do_<shift> functions.
519
fff8d27d
CD		 5202002-03-01 Chris Demetriou <cgd@broadcom.com>
521
522 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
523 DSRL32, do_dsrlv): Trace inputs and results.
524
0d3e762b
CD		 5252002-03-01 Chris Demetriou <cgd@broadcom.com>
526
527 * mips.igen (CACHE): Provide instruction-printing string.
528
529 * interp.c (signal_exception): Comment tokens after #endif.
530
eb5fcf93
CD		 5312002-02-28 Chris Demetriou <cgd@broadcom.com>
532
533 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
534 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
535 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
536 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
537 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
538 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
539 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
540 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
541
bb22bd7d
CD		 5422002-02-28 Chris Demetriou <cgd@broadcom.com>
543
544 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
545 instruction-printing string.
546 (LWU): Use '64' as the filter flag.
547
91a177cf
CD		 5482002-02-28 Chris Demetriou <cgd@broadcom.com>
549
550 * mips.igen (SDXC1): Fix instruction-printing string.
551
387f484a
CD		 5522002-02-28 Chris Demetriou <cgd@broadcom.com>
553
554 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
555 filter flags "32,f".
556
3d81f391
CD		 5572002-02-27 Chris Demetriou <cgd@broadcom.com>
558
559 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
560 as the filter flag.
561
af5107af
CD		 5622002-02-27 Chris Demetriou <cgd@broadcom.com>
563
564 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
565 add a comma) so that it more closely match the MIPS ISA
566 documentation opcode partitioning.
567 (PREF): Put useful names on opcode fields, and include
568 instruction-printing string.
569
ca971540
CD		 5702002-02-27 Chris Demetriou <cgd@broadcom.com>
571
572 * mips.igen (check_u64): New function which in the future will
573 check whether 64-bit instructions are usable and signal an
574 exception if not. Currently a no-op.
575 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
576 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
577 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
578 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
579
580 * mips.igen (check_fpu): New function which in the future will
581 check whether FPU instructions are usable and signal an exception
582 if not. Currently a no-op.
583 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
584 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
585 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
586 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
587 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
588 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
589 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
590 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
591
1c47a468
CD		 5922002-02-27 Chris Demetriou <cgd@broadcom.com>
593
594 * mips.igen (do_load_left, do_load_right): Move to be immediately
595 following do_load.
596 (do_store_left, do_store_right): Move to be immediately following
597 do_store.
598
603a98e7
CD		 5992002-02-27 Chris Demetriou <cgd@broadcom.com>
600
601 * mips.igen (mipsV): New model name. Also, add it to
602 all instructions and functions where it is appropriate.
603
c5d00cc7
CD		 6042002-02-18 Chris Demetriou <cgd@broadcom.com>
605
606 * mips.igen: For all functions and instructions, list model
607 names that support that instruction one per line.
608
074e9cb8
CD		 6092002-02-11 Chris Demetriou <cgd@broadcom.com>
610
611 * mips.igen: Add some additional comments about supported
612 models, and about which instructions go where.
613 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
614 order as is used in the rest of the file.
615
9805e229
CD		 6162002-02-11 Chris Demetriou <cgd@broadcom.com>
617
618 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
619 indicating that ALU32_END or ALU64_END are there to check
620 for overflow.
621 (DADD): Likewise, but also remove previous comment about
622 overflow checking.
623
f701dad2
CD		 6242002-02-10 Chris Demetriou <cgd@broadcom.com>
625
626 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
627 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
628 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
629 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
630 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
631 fields (i.e., add and move commas) so that they more closely
632 match the MIPS ISA documentation opcode partitioning.
633
6342002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 635
636 * mips.igen (ADDI): Print immediate value.
637 (BREAK): Print code.
638 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
639 (SLL): Print "nop" specially, and don't run the code
640 that does the shift for the "nop" case.
641
9e52972e
FF		 6422001-11-17 Fred Fish <fnf@redhat.com>
643
644 * sim-main.h (float_operation): Move enum declaration outside
645 of _sim_cpu struct declaration.
646
c0efbca4
JB		 6472001-04-12 Jim Blandy <jimb@redhat.com>
648
649 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
650 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
651 set of the FCSR.
652 * sim-main.h (COCIDX): Remove definition; this isn't supported by
653 PENDING_FILL, and you can get the intended effect gracefully by
654 calling PENDING_SCHED directly.
655
fb891446
BE		 6562001-02-23 Ben Elliston <bje@redhat.com>
657
658 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
659 already defined elsewhere.
660
8030f857
BE		 6612001-02-19 Ben Elliston <bje@redhat.com>
662
663 * sim-main.h (sim_monitor): Return an int.
664 * interp.c (sim_monitor): Add return values.
665 (signal_exception): Handle error conditions from sim_monitor.
666
56b48a7a
CD		 6672001-02-08 Ben Elliston <bje@redhat.com>
668
669 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
670 (store_memory): Likewise, pass cia to sim_core_write*.
671
d3ee60d9
FCE		 6722000-10-19 Frank Ch. Eigler <fche@redhat.com>
673
674 On advice from Chris G. Demetriou <cgd@sibyte.com>:
675 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
676
071da002
AC		 677Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
678
679 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
680 * Makefile.in: Don't delete *.igen when cleaning directory.
681
a28c02cd
AC		 682Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
683
684 * m16.igen (break): Call SignalException not sim_engine_halt.
685
80ee11fa
AC		 686Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
687
688 From Jason Eckhardt:
689 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
690
673388c0
AC		 691Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
692
693 * mips.igen (MxC1, DMxC1): Fix printf formatting.
694
4c0deff4
NC		 6952000-05-24 Michael Hayes <mhayes@cygnus.com>
696
697 * mips.igen (do_dmultx): Fix typo.
698
eb2d80b4
AC		 699Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
700
701 * configure: Regenerated to track ../common/aclocal.m4 changes.
702
dd37a34b
AC		 703Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
704
705 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
706
4c0deff4
NC		 7072000-04-12 Frank Ch. Eigler <fche@redhat.com>
708
709 * sim-main.h (GPR_CLEAR): Define macro.
710
e30db738
AC		 711Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
712
713 * interp.c (decode_coproc): Output long using %lx and not %s.
714
cb7450ea
FCE		 7152000-03-21 Frank Ch. Eigler <fche@redhat.com>
716
717 * interp.c (sim_open): Sort & extend dummy memory regions for
718 --board=jmr3904 for eCos.
719
a3027dd7
FCE		 7202000-03-02 Frank Ch. Eigler <fche@redhat.com>
721
722 * configure: Regenerated.
723
724Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
725
726 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
727 calls, conditional on the simulator being in verbose mode.
728
dfcd3bfb
JM		 729Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
730
731 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
732 cache don't get ReservedInstruction traps.
733
c2d11a7d
JM		 7341999-11-29 Mark Salter <msalter@cygnus.com>
735
736 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
737 to clear status bits in sdisr register. This is how the hardware works.
738
739 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
740 being used by cygmon.
741
4ce44c66
JM		 7421999-11-11 Andrew Haley <aph@cygnus.com>
743
744 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
745 instructions.
746
cff3e48b
JM		 747Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
748
749 * mips.igen (MULT): Correct previous mis-applied patch.
750
d4f3574e
SS		 751Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
752
753 * mips.igen (delayslot32): Handle sequence like
754 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
755 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
756 (MULT): Actually pass the third register...
757
7581999-09-03 Mark Salter <msalter@cygnus.com>
759
760 * interp.c (sim_open): Added more memory aliases for additional
761 hardware being touched by cygmon on jmr3904 board.
762
763Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
764
765 * configure: Regenerated to track ../common/aclocal.m4 changes.
766
a0b3c4fd
JM		 767Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
768
769 * interp.c (sim_store_register): Handle case where client - GDB -
770 specifies that a 4 byte register is 8 bytes in size.
771 (sim_fetch_register): Ditto.
772
adf40b2e
JM		 7731999-07-14 Frank Ch. Eigler <fche@cygnus.com>
774
775 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
776 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
777 (idt_monitor_base): Base address for IDT monitor traps.
778 (pmon_monitor_base): Ditto for PMON.
779 (lsipmon_monitor_base): Ditto for LSI PMON.
780 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
781 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
782 (sim_firmware_command): New function.
783 (mips_option_handler): Call it for OPTION_FIRMWARE.
784 (sim_open): Allocate memory for idt_monitor region. If "--board"
785 option was given, add no monitor by default. Add BREAK hooks only if
786 monitors are also there.
787
43e526b9
JM		 788Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
789
790 * interp.c (sim_monitor): Flush output before reading input.
791
792Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
793
794 * tconfig.in (SIM_HANDLES_LMA): Always define.
795
796Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
797
798 From Mark Salter <msalter@cygnus.com>:
799 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
800 (sim_open): Add setup for BSP board.
801
9846de1b
JM		 802Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
803
804 * mips.igen (MULT, MULTU): Add syntax for two operand version.
805 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
806 them as unimplemented.
807
cd0fc7c3
SS		 8081999-05-08 Felix Lee <flee@cygnus.com>
809
810 * configure: Regenerated to track ../common/aclocal.m4 changes.
811
7a292a7a
SS		 8121999-04-21 Frank Ch. Eigler <fche@cygnus.com>
813
814 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
815
816Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
817
818 * configure.in: Any mips64vr5*-*-* target should have
819 -DTARGET_ENABLE_FR=1.
820 (default_endian): Any mips64vr*el-*-* target should default to
821 LITTLE_ENDIAN.
822 * configure: Re-generate.
823
8241999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
825
826 * mips.igen (ldl): Extend from _16_, not 32.
827
828Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
829
830 * interp.c (sim_store_register): Force registers written to by GDB
831 into an un-interpreted state.
832
c906108c
SS		 8331999-02-05 Frank Ch. Eigler <fche@cygnus.com>
834
835 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
836 CPU, start periodic background I/O polls.
837 (tx3904sio_poll): New function: periodic I/O poller.
838
8391998-12-30 Frank Ch. Eigler <fche@cygnus.com>
840
841 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
842
843Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
844
845 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
846 case statement.
847
8481998-12-29 Frank Ch. Eigler <fche@cygnus.com>
849
850 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
851 (load_word): Call SIM_CORE_SIGNAL hook on error.
852 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
853 starting. For exception dispatching, pass PC instead of NULL_CIA.
854 (decode_coproc): Use COP0_BADVADDR to store faulting address.
855 * sim-main.h (COP0_BADVADDR): Define.
856 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
857 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
858 (_sim_cpu): Add exc_* fields to store register value snapshots.
859 * mips.igen (*): Replace memory-related SignalException* calls
860 with references to SIM_CORE_SIGNAL hook.
861
862 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
863 fix.
864 * sim-main.c (*): Minor warning cleanups.
865
8661998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
867
868 * m16.igen (DADDIU5): Correct type-o.
869
870Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
871
872 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
873 variables.
874
875Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
876
877 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
878 to include path.
879 (interp.o): Add dependency on itable.h
880 (oengine.c, gencode): Delete remaining references.
881 (BUILT_SRC_FROM_GEN): Clean up.
882
8831998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
884
885 * vr4run.c: New.
886 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
887 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
888 tmp-run-hack) : New.
889 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
890 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
891 Drop the "64" qualifier to get the HACK generator working.
892 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
893 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
894 qualifier to get the hack generator working.
895 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
896 (DSLL): Use do_dsll.
897 (DSLLV): Use do_dsllv.
898 (DSRA): Use do_dsra.
899 (DSRL): Use do_dsrl.
900 (DSRLV): Use do_dsrlv.
901 (BC1): Move *vr4100 to get the HACK generator working.
902 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
903 get the HACK generator working.
904 (MACC) Rename to get the HACK generator working.
905 (DMACC,MACCS,DMACCS): Add the 64.
906
9071998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
908
909 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
910 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
911
9121998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
913
914 * mips/interp.c (DEBUG): Cleanups.
915
9161998-12-10 Frank Ch. Eigler <fche@cygnus.com>
917
918 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
919 (tx3904sio_tickle): fflush after a stdout character output.
920
9211998-12-03 Frank Ch. Eigler <fche@cygnus.com>
922
923 * interp.c (sim_close): Uninstall modules.
924
925Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
926
927 * sim-main.h, interp.c (sim_monitor): Change to global
928 function.
929
930Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
931
932 * configure.in (vr4100): Only include vr4100 instructions in
933 simulator.
934 * configure: Re-generate.
935 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
936
937Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
938
939 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
940 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
941 true alternative.
942
943 * configure.in (sim_default_gen, sim_use_gen): Replace with
944 sim_gen.
945 (--enable-sim-igen): Delete config option. Always using IGEN.
946 * configure: Re-generate.
947
948 * Makefile.in (gencode): Kill, kill, kill.
949 * gencode.c: Ditto.
950
951Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
952
953 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
954 bit mips16 igen simulator.
955 * configure: Re-generate.
956
957 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
958 as part of vr4100 ISA.
959 * vr.igen: Mark all instructions as 64 bit only.
960
961Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
962
963 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
964 Pacify GCC.
965
966Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
969 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
970 * configure: Re-generate.
971
972 * m16.igen (BREAK): Define breakpoint instruction.
973 (JALX32): Mark instruction as mips16 and not r3900.
974 * mips.igen (C.cond.fmt): Fix typo in instruction format.
975
976 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
977
978Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
979
980 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
981 insn as a debug breakpoint.
982
983 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
984 pending.slot_size.
985 (PENDING_SCHED): Clean up trace statement.
986 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
987 (PENDING_FILL): Delay write by only one cycle.
988 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
989
990 * sim-main.c (pending_tick): Clean up trace statements. Add trace
991 of pending writes.
992 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
993 32 & 64.
994 (pending_tick): Move incrementing of index to FOR statement.
995 (pending_tick): Only update PENDING_OUT after a write has occured.
996
997 * configure.in: Add explicit mips-lsi-* target. Use gencode to
998 build simulator.
999 * configure: Re-generate.
1000
1001 * interp.c (sim_engine_run OLD): Delete explicit call to
1002 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1003
1004Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1005
1006 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1007 interrupt level number to match changed SignalExceptionInterrupt
1008 macro.
1009
1010Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1011
1012 * interp.c: #include "itable.h" if WITH_IGEN.
1013 (get_insn_name): New function.
1014 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1015 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1016
1017Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1018
1019 * configure: Rebuilt to inhale new common/aclocal.m4.
1020
1021Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1022
1023 * dv-tx3904sio.c: Include sim-assert.h.
1024
1025Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1026
1027 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1028 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1029 Reorganize target-specific sim-hardware checks.
1030 * configure: rebuilt.
1031 * interp.c (sim_open): For tx39 target boards, set
1032 OPERATING_ENVIRONMENT, add tx3904sio devices.
1033 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1034 ROM executables. Install dv-sockser into sim-modules list.
1035
1036 * dv-tx3904irc.c: Compiler warning clean-up.
1037 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1038 frequent hw-trace messages.
1039
1040Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1041
1042 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1043
1044Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1045
1046 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1047
1048 * vr.igen: New file.
1049 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1050 * mips.igen: Define vr4100 model. Include vr.igen.
1051Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1052
1053 * mips.igen (check_mf_hilo): Correct check.
1054
1055Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1056
1057 * sim-main.h (interrupt_event): Add prototype.
1058
1059 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1060 register_ptr, register_value.
1061 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1062
1063 * sim-main.h (tracefh): Make extern.
1064
1065Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1066
1067 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1068 Reduce unnecessarily high timer event frequency.
1069 * dv-tx3904cpu.c: Ditto for interrupt event.
1070
1071Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1072
1073 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1074 to allay warnings.
1075 (interrupt_event): Made non-static.
1076
1077 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1078 interchange of configuration values for external vs. internal
1079 clock dividers.
1080
1081Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1082
1083 * mips.igen (BREAK): Moved code to here for
1084 simulator-reserved break instructions.
1085 * gencode.c (build_instruction): Ditto.
1086 * interp.c (signal_exception): Code moved from here. Non-
1087 reserved instructions now use exception vector, rather
1088 than halting sim.
1089 * sim-main.h: Moved magic constants to here.
1090
1091Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1092
1093 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1094 register upon non-zero interrupt event level, clear upon zero
1095 event value.
1096 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1097 by passing zero event value.
1098 (*_io_{read,write}_buffer): Endianness fixes.
1099 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1100 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1101
1102 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1103 serial I/O and timer module at base address 0xFFFF0000.
1104
1105Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1106
1107 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1108 and BigEndianCPU.
1109
1110Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1111
1112 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1113 parts.
1114 * configure: Update.
1115
1116Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1117
1118 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1119 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1120 * configure.in: Include tx3904tmr in hw_device list.
1121 * configure: Rebuilt.
1122 * interp.c (sim_open): Instantiate three timer instances.
1123 Fix address typo of tx3904irc instance.
1124
1125Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1126
1127 * interp.c (signal_exception): SystemCall exception now uses
1128 the exception vector.
1129
1130Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1131
1132 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1133 to allay warnings.
1134
1135Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1136
1137 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1138
1139Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1140
1141 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1142
1143 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1144 sim-main.h. Declare a struct hw_descriptor instead of struct
1145 hw_device_descriptor.
1146
1147Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1148
1149 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1150 right bits and then re-align left hand bytes to correct byte
1151 lanes. Fix incorrect computation in do_store_left when loading
1152 bytes from second word.
1153
1154Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1155
1156 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1157 * interp.c (sim_open): Only create a device tree when HW is
1158 enabled.
1159
1160 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1161 * interp.c (signal_exception): Ditto.
1162
1163Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1164
1165 * gencode.c: Mark BEGEZALL as LIKELY.
1166
1167Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1168
1169 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1170 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1171
1172Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1173
1174 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1175 modules. Recognize TX39 target with "mips*tx39" pattern.
1176 * configure: Rebuilt.
1177 * sim-main.h (*): Added many macros defining bits in
1178 TX39 control registers.
1179 (SignalInterrupt): Send actual PC instead of NULL.
1180 (SignalNMIReset): New exception type.
1181 * interp.c (board): New variable for future use to identify
1182 a particular board being simulated.
1183 (mips_option_handler,mips_options): Added "--board" option.
1184 (interrupt_event): Send actual PC.
1185 (sim_open): Make memory layout conditional on board setting.
1186 (signal_exception): Initial implementation of hardware interrupt
1187 handling. Accept another break instruction variant for simulator
1188 exit.
1189 (decode_coproc): Implement RFE instruction for TX39.
1190 (mips.igen): Decode RFE instruction as such.
1191 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1192 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1193 bbegin to implement memory map.
1194 * dv-tx3904cpu.c: New file.
1195 * dv-tx3904irc.c: New file.
1196
1197Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1198
1199 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1200
1201Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1202
1203 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1204 with calls to check_div_hilo.
1205
1206Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1207
1208 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1209 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1210 Add special r3900 version of do_mult_hilo.
1211 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1212 with calls to check_mult_hilo.
1213 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1214 with calls to check_div_hilo.
1215
1216Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1217
1218 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1219 Document a replacement.
1220
1221Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1222
1223 * interp.c (sim_monitor): Make mon_printf work.
1224
1225Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1226
1227 * sim-main.h (INSN_NAME): New arg `cpu'.
1228
1229Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1230
1231 * configure: Regenerated to track ../common/aclocal.m4 changes.
1232
1233Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1234
1235 * configure: Regenerated to track ../common/aclocal.m4 changes.
1236 * config.in: Ditto.
1237
1238Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1239
1240 * acconfig.h: New file.
1241 * configure.in: Reverted change of Apr 24; use sinclude again.
1242
1243Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1244
1245 * configure: Regenerated to track ../common/aclocal.m4 changes.
1246 * config.in: Ditto.
1247
1248Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1249
1250 * configure.in: Don't call sinclude.
1251
1252Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1253
1254 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1255
1256Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1257
1258 * mips.igen (ERET): Implement.
1259
1260 * interp.c (decode_coproc): Return sign-extended EPC.
1261
1262 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1263
1264 * interp.c (signal_exception): Do not ignore Trap.
1265 (signal_exception): On TRAP, restart at exception address.
1266 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1267 (signal_exception): Update.
1268 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1269 so that TRAP instructions are caught.
1270
1271Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1272
1273 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1274 contains HI/LO access history.
1275 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1276 (HIACCESS, LOACCESS): Delete, replace with
1277 (HIHISTORY, LOHISTORY): New macros.
1278 (CHECKHILO): Delete all, moved to mips.igen
1279
1280 * gencode.c (build_instruction): Do not generate checks for
1281 correct HI/LO register usage.
1282
1283 * interp.c (old_engine_run): Delete checks for correct HI/LO
1284 register usage.
1285
1286 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1287 check_mf_cycles): New functions.
1288 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1289 do_divu, domultx, do_mult, do_multu): Use.
1290
1291 * tx.igen ("madd", "maddu"): Use.
1292
1293Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1294
1295 * mips.igen (DSRAV): Use function do_dsrav.
1296 (SRAV): Use new function do_srav.
1297
1298 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1299 (B): Sign extend 11 bit immediate.
1300 (EXT-B*): Shift 16 bit immediate left by 1.
1301 (ADDIU*): Don't sign extend immediate value.
1302
1303Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1304
1305 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1306
1307 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1308 functions.
1309
1310 * mips.igen (delayslot32, nullify_next_insn): New functions.
1311 (m16.igen): Always include.
1312 (do_*): Add more tracing.
1313
1314 * m16.igen (delayslot16): Add NIA argument, could be called by a
1315 32 bit MIPS16 instruction.
1316
1317 * interp.c (ifetch16): Move function from here.
1318 * sim-main.c (ifetch16): To here.
1319
1320 * sim-main.c (ifetch16, ifetch32): Update to match current
1321 implementations of LH, LW.
1322 (signal_exception): Don't print out incorrect hex value of illegal
1323 instruction.
1324
1325Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1326
1327 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1328 instruction.
1329
1330 * m16.igen: Implement MIPS16 instructions.
1331
1332 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1333 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1334 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1335 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1336 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1337 bodies of corresponding code from 32 bit insn to these. Also used
1338 by MIPS16 versions of functions.
1339
1340 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1341 (IMEM16): Drop NR argument from macro.
1342
1343Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1344
1345 * Makefile.in (SIM_OBJS): Add sim-main.o.
1346
1347 * sim-main.h (address_translation, load_memory, store_memory,
1348 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1349 as INLINE_SIM_MAIN.
1350 (pr_addr, pr_uword64): Declare.
1351 (sim-main.c): Include when H_REVEALS_MODULE_P.
1352
1353 * interp.c (address_translation, load_memory, store_memory,
1354 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1355 from here.
1356 * sim-main.c: To here. Fix compilation problems.
1357
1358 * configure.in: Enable inlining.
1359 * configure: Re-config.
1360
1361Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362
1363 * configure: Regenerated to track ../common/aclocal.m4 changes.
1364
1365Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1366
1367 * mips.igen: Include tx.igen.
1368 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1369 * tx.igen: New file, contains MADD and MADDU.
1370
1371 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1372 the hardwired constant `7'.
1373 (store_memory): Ditto.
1374 (LOADDRMASK): Move definition to sim-main.h.
1375
1376 mips.igen (MTC0): Enable for r3900.
1377 (ADDU): Add trace.
1378
1379 mips.igen (do_load_byte): Delete.
1380 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1381 do_store_right): New functions.
1382 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1383
1384 configure.in: Let the tx39 use igen again.
1385 configure: Update.
1386
1387Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1388
1389 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1390 not an address sized quantity. Return zero for cache sizes.
1391
1392Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1393
1394 * mips.igen (r3900): r3900 does not support 64 bit integer
1395 operations.
1396
1397Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1398
1399 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1400 than igen one.
1401 * configure : Rebuild.
1402
1403Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1404
1405 * configure: Regenerated to track ../common/aclocal.m4 changes.
1406
1407Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1408
1409 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1410
1411Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1412
1413 * configure: Regenerated to track ../common/aclocal.m4 changes.
1414 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1415
1416Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1417
1418 * configure: Regenerated to track ../common/aclocal.m4 changes.
1419
1420Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1421
1422 * interp.c (Max, Min): Comment out functions. Not yet used.
1423
1424Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1425
1426 * configure: Regenerated to track ../common/aclocal.m4 changes.
1427
1428Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1429
1430 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1431 configurable settings for stand-alone simulator.
1432
1433 * configure.in: Added X11 search, just in case.
1434
1435 * configure: Regenerated.
1436
1437Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1438
1439 * interp.c (sim_write, sim_read, load_memory, store_memory):
1440 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1441
1442Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1443
1444 * sim-main.h (GETFCC): Return an unsigned value.
1445
1446Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1447
1448 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1449 (DADD): Result destination is RD not RT.
1450
1451Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1452
1453 * sim-main.h (HIACCESS, LOACCESS): Always define.
1454
1455 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1456
1457 * interp.c (sim_info): Delete.
1458
1459Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1460
1461 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1462 (mips_option_handler): New argument `cpu'.
1463 (sim_open): Update call to sim_add_option_table.
1464
1465Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1466
1467 * mips.igen (CxC1): Add tracing.
1468
1469Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1470
1471 * sim-main.h (Max, Min): Declare.
1472
1473 * interp.c (Max, Min): New functions.
1474
1475 * mips.igen (BC1): Add tracing.
1476
1477Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1478
1479 * interp.c Added memory map for stack in vr4100
1480
1481Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1482
1483 * interp.c (load_memory): Add missing "break"'s.
1484
1485Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * interp.c (sim_store_register, sim_fetch_register): Pass in
1488 length parameter. Return -1.
1489
1490Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1491
1492 * interp.c: Added hardware init hook, fixed warnings.
1493
1494Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1497
1498Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 * interp.c (ifetch16): New function.
1501
1502 * sim-main.h (IMEM32): Rename IMEM.
1503 (IMEM16_IMMED): Define.
1504 (IMEM16): Define.
1505 (DELAY_SLOT): Update.
1506
1507 * m16run.c (sim_engine_run): New file.
1508
1509 * m16.igen: All instructions except LB.
1510 (LB): Call do_load_byte.
1511 * mips.igen (do_load_byte): New function.
1512 (LB): Call do_load_byte.
1513
1514 * mips.igen: Move spec for insn bit size and high bit from here.
1515 * Makefile.in (tmp-igen, tmp-m16): To here.
1516
1517 * m16.dc: New file, decode mips16 instructions.
1518
1519 * Makefile.in (SIM_NO_ALL): Define.
1520 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1521
1522Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1523
1524 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1525 point unit to 32 bit registers.
1526 * configure: Re-generate.
1527
1528Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1529
1530 * configure.in (sim_use_gen): Make IGEN the default simulator
1531 generator for generic 32 and 64 bit mips targets.
1532 * configure: Re-generate.
1533
1534Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1535
1536 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1537 bitsize.
1538
1539 * interp.c (sim_fetch_register, sim_store_register): Read/write
1540 FGR from correct location.
1541 (sim_open): Set size of FGR's according to
1542 WITH_TARGET_FLOATING_POINT_BITSIZE.
1543
1544 * sim-main.h (FGR): Store floating point registers in a separate
1545 array.
1546
1547Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1548
1549 * configure: Regenerated to track ../common/aclocal.m4 changes.
1550
1551Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1552
1553 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1554
1555 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1556
1557 * interp.c (pending_tick): New function. Deliver pending writes.
1558
1559 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1560 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1561 it can handle mixed sized quantites and single bits.
1562
1563Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1564
1565 * interp.c (oengine.h): Do not include when building with IGEN.
1566 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1567 (sim_info): Ditto for PROCESSOR_64BIT.
1568 (sim_monitor): Replace ut_reg with unsigned_word.
1569 (*): Ditto for t_reg.
1570 (LOADDRMASK): Define.
1571 (sim_open): Remove defunct check that host FP is IEEE compliant,
1572 using software to emulate floating point.
1573 (value_fpr, ...): Always compile, was conditional on HASFPU.
1574
1575Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1578 size.
1579
1580 * interp.c (SD, CPU): Define.
1581 (mips_option_handler): Set flags in each CPU.
1582 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1583 (sim_close): Do not clear STATE, deleted anyway.
1584 (sim_write, sim_read): Assume CPU zero's vm should be used for
1585 data transfers.
1586 (sim_create_inferior): Set the PC for all processors.
1587 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1588 argument.
1589 (mips16_entry): Pass correct nr of args to store_word, load_word.
1590 (ColdReset): Cold reset all cpu's.
1591 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1592 (sim_monitor, load_memory, store_memory, signal_exception): Use
1593 `CPU' instead of STATE_CPU.
1594
1595
1596 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1597 SD or CPU_.
1598
1599 * sim-main.h (signal_exception): Add sim_cpu arg.
1600 (SignalException*): Pass both SD and CPU to signal_exception.
1601 * interp.c (signal_exception): Update.
1602
1603 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1604 Ditto
1605 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1606 address_translation): Ditto
1607 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1608
1609Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * configure: Regenerated to track ../common/aclocal.m4 changes.
1612
1613Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1616
1617 * mips.igen (model): Map processor names onto BFD name.
1618
1619 * sim-main.h (CPU_CIA): Delete.
1620 (SET_CIA, GET_CIA): Define
1621
1622Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1623
1624 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1625 regiser.
1626
1627 * configure.in (default_endian): Configure a big-endian simulator
1628 by default.
1629 * configure: Re-generate.
1630
1631Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1632
1633 * configure: Regenerated to track ../common/aclocal.m4 changes.
1634
1635Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1636
1637 * interp.c (sim_monitor): Handle Densan monitor outbyte
1638 and inbyte functions.
1639
16401997-12-29 Felix Lee <flee@cygnus.com>
1641
1642 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1643
1644Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1645
1646 * Makefile.in (tmp-igen): Arrange for $zero to always be
1647 reset to zero after every instruction.
1648
1649Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * configure: Regenerated to track ../common/aclocal.m4 changes.
1652 * config.in: Ditto.
1653
1654Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1655
1656 * mips.igen (MSUB): Fix to work like MADD.
1657 * gencode.c (MSUB): Similarly.
1658
1659Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1660
1661 * configure: Regenerated to track ../common/aclocal.m4 changes.
1662
1663Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1664
1665 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1666
1667Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1668
1669 * sim-main.h (sim-fpu.h): Include.
1670
1671 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1672 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1673 using host independant sim_fpu module.
1674
1675Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1676
1677 * interp.c (signal_exception): Report internal errors with SIGABRT
1678 not SIGQUIT.
1679
1680 * sim-main.h (C0_CONFIG): New register.
1681 (signal.h): No longer include.
1682
1683 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1684
1685Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1686
1687 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1688
1689Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1690
1691 * mips.igen: Tag vr5000 instructions.
1692 (ANDI): Was missing mipsIV model, fix assembler syntax.
1693 (do_c_cond_fmt): New function.
1694 (C.cond.fmt): Handle mips I-III which do not support CC field
1695 separatly.
1696 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1697 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1698 in IV3.2 spec.
1699 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1700 vr5000 which saves LO in a GPR separatly.
1701
1702 * configure.in (enable-sim-igen): For vr5000, select vr5000
1703 specific instructions.
1704 * configure: Re-generate.
1705
1706Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1707
1708 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1709
1710 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1711 fmt_uninterpreted_64 bit cases to switch. Convert to
1712 fmt_formatted,
1713
1714 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1715
1716 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1717 as specified in IV3.2 spec.
1718 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1719
1720Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1721
1722 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1723 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1724 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1725 PENDING_FILL versions of instructions. Simplify.
1726 (X): New function.
1727 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1728 instructions.
1729 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1730 a signed value.
1731 (MTHI, MFHI): Disable code checking HI-LO.
1732
1733 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1734 global.
1735 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1736
1737Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1738
1739 * gencode.c (build_mips16_operands): Replace IPC with cia.
1740
1741 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1742 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1743 IPC to `cia'.
1744 (UndefinedResult): Replace function with macro/function
1745 combination.
1746 (sim_engine_run): Don't save PC in IPC.
1747
1748 * sim-main.h (IPC): Delete.
1749
1750
1751 * interp.c (signal_exception, store_word, load_word,
1752 address_translation, load_memory, store_memory, cache_op,
1753 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1754 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1755 current instruction address - cia - argument.
1756 (sim_read, sim_write): Call address_translation directly.
1757 (sim_engine_run): Rename variable vaddr to cia.
1758 (signal_exception): Pass cia to sim_monitor
1759
1760 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1761 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1762 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1763
1764 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1765 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1766 SIM_ASSERT.
1767
1768 * interp.c (signal_exception): Pass restart address to
1769 sim_engine_restart.
1770
1771 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1772 idecode.o): Add dependency.
1773
1774 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1775 Delete definitions
1776 (DELAY_SLOT): Update NIA not PC with branch address.
1777 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1778
1779 * mips.igen: Use CIA not PC in branch calculations.
1780 (illegal): Call SignalException.
1781 (BEQ, ADDIU): Fix assembler.
1782
1783Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1784
1785 * m16.igen (JALX): Was missing.
1786
1787 * configure.in (enable-sim-igen): New configuration option.
1788 * configure: Re-generate.
1789
1790 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1791
1792 * interp.c (load_memory, store_memory): Delete parameter RAW.
1793 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1794 bypassing {load,store}_memory.
1795
1796 * sim-main.h (ByteSwapMem): Delete definition.
1797
1798 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1799
1800 * interp.c (sim_do_command, sim_commands): Delete mips specific
1801 commands. Handled by module sim-options.
1802
1803 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1804 (WITH_MODULO_MEMORY): Define.
1805
1806 * interp.c (sim_info): Delete code printing memory size.
1807
1808 * interp.c (mips_size): Nee sim_size, delete function.
1809 (power2): Delete.
1810 (monitor, monitor_base, monitor_size): Delete global variables.
1811 (sim_open, sim_close): Delete code creating monitor and other
1812 memory regions. Use sim-memopts module, via sim_do_commandf, to
1813 manage memory regions.
1814 (load_memory, store_memory): Use sim-core for memory model.
1815
1816 * interp.c (address_translation): Delete all memory map code
1817 except line forcing 32 bit addresses.
1818
1819Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1820
1821 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1822 trace options.
1823
1824 * interp.c (logfh, logfile): Delete globals.
1825 (sim_open, sim_close): Delete code opening & closing log file.
1826 (mips_option_handler): Delete -l and -n options.
1827 (OPTION mips_options): Ditto.
1828
1829 * interp.c (OPTION mips_options): Rename option trace to dinero.
1830 (mips_option_handler): Update.
1831
1832Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1833
1834 * interp.c (fetch_str): New function.
1835 (sim_monitor): Rewrite using sim_read & sim_write.
1836 (sim_open): Check magic number.
1837 (sim_open): Write monitor vectors into memory using sim_write.
1838 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1839 (sim_read, sim_write): Simplify - transfer data one byte at a
1840 time.
1841 (load_memory, store_memory): Clarify meaning of parameter RAW.
1842
1843 * sim-main.h (isHOST): Defete definition.
1844 (isTARGET): Mark as depreciated.
1845 (address_translation): Delete parameter HOST.
1846
1847 * interp.c (address_translation): Delete parameter HOST.
1848
1849Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1850
1851 * mips.igen:
1852
1853 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1854 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1855
1856Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 * mips.igen: Add model filter field to records.
1859
1860Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1861
1862 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1863
1864 interp.c (sim_engine_run): Do not compile function sim_engine_run
1865 when WITH_IGEN == 1.
1866
1867 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1868 target architecture.
1869
1870 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1871 igen. Replace with configuration variables sim_igen_flags /
1872 sim_m16_flags.
1873
1874 * m16.igen: New file. Copy mips16 insns here.
1875 * mips.igen: From here.
1876
1877Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1878
1879 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1880 to top.
1881 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1882
1883Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1884
1885 * gencode.c (build_instruction): Follow sim_write's lead in using
1886 BigEndianMem instead of !ByteSwapMem.
1887
1888Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * configure.in (sim_gen): Dependent on target, select type of
1891 generator. Always select old style generator.
1892
1893 configure: Re-generate.
1894
1895 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1896 targets.
1897 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1898 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1899 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1900 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1901 SIM_@sim_gen@_*, set by autoconf.
1902
1903Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1904
1905 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1906
1907 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1908 CURRENT_FLOATING_POINT instead.
1909
1910 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1911 (address_translation): Raise exception InstructionFetch when
1912 translation fails and isINSTRUCTION.
1913
1914 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1915 sim_engine_run): Change type of of vaddr and paddr to
1916 address_word.
1917 (address_translation, prefetch, load_memory, store_memory,
1918 cache_op): Change type of vAddr and pAddr to address_word.
1919
1920 * gencode.c (build_instruction): Change type of vaddr and paddr to
1921 address_word.
1922
1923Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1924
1925 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1926 macro to obtain result of ALU op.
1927
1928Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1929
1930 * interp.c (sim_info): Call profile_print.
1931
1932Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1935
1936 * sim-main.h (WITH_PROFILE): Do not define, defined in
1937 common/sim-config.h. Use sim-profile module.
1938 (simPROFILE): Delete defintion.
1939
1940 * interp.c (PROFILE): Delete definition.
1941 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1942 (sim_close): Delete code writing profile histogram.
1943 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1944 Delete.
1945 (sim_engine_run): Delete code profiling the PC.
1946
1947Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1950
1951 * interp.c (sim_monitor): Make register pointers of type
1952 unsigned_word*.
1953
1954 * sim-main.h: Make registers of type unsigned_word not
1955 signed_word.
1956
1957Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1958
1959 * interp.c (sync_operation): Rename from SyncOperation, make
1960 global, add SD argument.
1961 (prefetch): Rename from Prefetch, make global, add SD argument.
1962 (decode_coproc): Make global.
1963
1964 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1965
1966 * gencode.c (build_instruction): Generate DecodeCoproc not
1967 decode_coproc calls.
1968
1969 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1970 (SizeFGR): Move to sim-main.h
1971 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1972 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1973 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1974 sim-main.h.
1975 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1976 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1977 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1978 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1979 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1980 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1981
1982 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1983 exception.
1984 (sim-alu.h): Include.
1985 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1986 (sim_cia): Typedef to instruction_address.
1987
1988Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * Makefile.in (interp.o): Rename generated file engine.c to
1991 oengine.c.
1992
1993 * interp.c: Update.
1994
1995Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1996
1997 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1998
1999Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2000
2001 * gencode.c (build_instruction): For "FPSQRT", output correct
2002 number of arguments to Recip.
2003
2004Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2005
2006 * Makefile.in (interp.o): Depends on sim-main.h
2007
2008 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2009
2010 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2011 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2012 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2013 STATE, DSSTATE): Define
2014 (GPR, FGRIDX, ..): Define.
2015
2016 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2017 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2018 (GPR, FGRIDX, ...): Delete macros.
2019
2020 * interp.c: Update names to match defines from sim-main.h
2021
2022Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * interp.c (sim_monitor): Add SD argument.
2025 (sim_warning): Delete. Replace calls with calls to
2026 sim_io_eprintf.
2027 (sim_error): Delete. Replace calls with sim_io_error.
2028 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2029 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2030 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2031 argument.
2032 (mips_size): Rename from sim_size. Add SD argument.
2033
2034 * interp.c (simulator): Delete global variable.
2035 (callback): Delete global variable.
2036 (mips_option_handler, sim_open, sim_write, sim_read,
2037 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2038 sim_size,sim_monitor): Use sim_io_* not callback->*.
2039 (sim_open): ZALLOC simulator struct.
2040 (PROFILE): Do not define.
2041
2042Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2043
2044 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2045 support.h with corresponding code.
2046
2047 * sim-main.h (word64, uword64), support.h: Move definition to
2048 sim-main.h.
2049 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2050
2051 * support.h: Delete
2052 * Makefile.in: Update dependencies
2053 * interp.c: Do not include.
2054
2055Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2056
2057 * interp.c (address_translation, load_memory, store_memory,
2058 cache_op): Rename to from AddressTranslation et.al., make global,
2059 add SD argument
2060
2061 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2062 CacheOp): Define.
2063
2064 * interp.c (SignalException): Rename to signal_exception, make
2065 global.
2066
2067 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2068
2069 * sim-main.h (SignalException, SignalExceptionInterrupt,
2070 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2071 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2072 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2073 Define.
2074
2075 * interp.c, support.h: Use.
2076
2077Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2080 to value_fpr / store_fpr. Add SD argument.
2081 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2082 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2083
2084 * sim-main.h (ValueFPR, StoreFPR): Define.
2085
2086Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2087
2088 * interp.c (sim_engine_run): Check consistency between configure
2089 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2090 and HASFPU.
2091
2092 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2093 (mips_fpu): Configure WITH_FLOATING_POINT.
2094 (mips_endian): Configure WITH_TARGET_ENDIAN.
2095 * configure: Update.
2096
2097Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2098
2099 * configure: Regenerated to track ../common/aclocal.m4 changes.
2100
2101Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2102
2103 * configure: Regenerated.
2104
2105Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2106
2107 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2108
2109Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2110
2111 * gencode.c (print_igen_insn_models): Assume certain architectures
2112 include all mips* instructions.
2113 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2114 instruction.
2115
2116 * Makefile.in (tmp.igen): Add target. Generate igen input from
2117 gencode file.
2118
2119 * gencode.c (FEATURE_IGEN): Define.
2120 (main): Add --igen option. Generate output in igen format.
2121 (process_instructions): Format output according to igen option.
2122 (print_igen_insn_format): New function.
2123 (print_igen_insn_models): New function.
2124 (process_instructions): Only issue warnings and ignore
2125 instructions when no FEATURE_IGEN.
2126
2127Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2128
2129 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2130 MIPS targets.
2131
2132Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2133
2134 * configure: Regenerated to track ../common/aclocal.m4 changes.
2135
2136Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2137
2138 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2139 SIM_RESERVED_BITS): Delete, moved to common.
2140 (SIM_EXTRA_CFLAGS): Update.
2141
2142Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143
2144 * configure.in: Configure non-strict memory alignment.
2145 * configure: Regenerated to track ../common/aclocal.m4 changes.
2146
2147Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2148
2149 * configure: Regenerated to track ../common/aclocal.m4 changes.
2150
2151Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2152
2153 * gencode.c (SDBBP,DERET): Added (3900) insns.
2154 (RFE): Turn on for 3900.
2155 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2156 (dsstate): Made global.
2157 (SUBTARGET_R3900): Added.
2158 (CANCELDELAYSLOT): New.
2159 (SignalException): Ignore SystemCall rather than ignore and
2160 terminate. Add DebugBreakPoint handling.
2161 (decode_coproc): New insns RFE, DERET; and new registers Debug
2162 and DEPC protected by SUBTARGET_R3900.
2163 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2164 bits explicitly.
2165 * Makefile.in,configure.in: Add mips subtarget option.
2166 * configure: Update.
2167
2168Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2169
2170 * gencode.c: Add r3900 (tx39).
2171
2172
2173Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2174
2175 * gencode.c (build_instruction): Don't need to subtract 4 for
2176 JALR, just 2.
2177
2178Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2179
2180 * interp.c: Correct some HASFPU problems.
2181
2182Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * configure: Regenerated to track ../common/aclocal.m4 changes.
2185
2186Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * interp.c (mips_options): Fix samples option short form, should
2189 be `x'.
2190
2191Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192
2193 * interp.c (sim_info): Enable info code. Was just returning.
2194
2195Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2196
2197 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2198 MFC0.
2199
2200Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2203 constants.
2204 (build_instruction): Ditto for LL.
2205
2206Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2207
2208 * configure: Regenerated to track ../common/aclocal.m4 changes.
2209
2210Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2211
2212 * configure: Regenerated to track ../common/aclocal.m4 changes.
2213 * config.in: Ditto.
2214
2215Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2216
2217 * interp.c (sim_open): Add call to sim_analyze_program, update
2218 call to sim_config.
2219
2220Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * interp.c (sim_kill): Delete.
2223 (sim_create_inferior): Add ABFD argument. Set PC from same.
2224 (sim_load): Move code initializing trap handlers from here.
2225 (sim_open): To here.
2226 (sim_load): Delete, use sim-hload.c.
2227
2228 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2229
2230Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2231
2232 * configure: Regenerated to track ../common/aclocal.m4 changes.
2233 * config.in: Ditto.
2234
2235Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * interp.c (sim_open): Add ABFD argument.
2238 (sim_load): Move call to sim_config from here.
2239 (sim_open): To here. Check return status.
2240
2241Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2242
2243 * gencode.c (build_instruction): Two arg MADD should
2244 not assign result to $0.
2245
2246Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2247
2248 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2249 * sim/mips/configure.in: Regenerate.
2250
2251Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2252
2253 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2254 signed8, unsigned8 et.al. types.
2255
2256 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2257 hosts when selecting subreg.
2258
2259Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2260
2261 * interp.c (sim_engine_run): Reset the ZERO register to zero
2262 regardless of FEATURE_WARN_ZERO.
2263 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2264
2265Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266
2267 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2268 (SignalException): For BreakPoints ignore any mode bits and just
2269 save the PC.
2270 (SignalException): Always set the CAUSE register.
2271
2272Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2273
2274 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2275 exception has been taken.
2276
2277 * interp.c: Implement the ERET and mt/f sr instructions.
2278
2279Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2280
2281 * interp.c (SignalException): Don't bother restarting an
2282 interrupt.
2283
2284Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2285
2286 * interp.c (SignalException): Really take an interrupt.
2287 (interrupt_event): Only deliver interrupts when enabled.
2288
2289Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2290
2291 * interp.c (sim_info): Only print info when verbose.
2292 (sim_info) Use sim_io_printf for output.
2293
2294Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2295
2296 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2297 mips architectures.
2298
2299Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2300
2301 * interp.c (sim_do_command): Check for common commands if a
2302 simulator specific command fails.
2303
2304Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2305
2306 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2307 and simBE when DEBUG is defined.
2308
2309Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2310
2311 * interp.c (interrupt_event): New function. Pass exception event
2312 onto exception handler.
2313
2314 * configure.in: Check for stdlib.h.
2315 * configure: Regenerate.
2316
2317 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2318 variable declaration.
2319 (build_instruction): Initialize memval1.
2320 (build_instruction): Add UNUSED attribute to byte, bigend,
2321 reverse.
2322 (build_operands): Ditto.
2323
2324 * interp.c: Fix GCC warnings.
2325 (sim_get_quit_code): Delete.
2326
2327 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2328 * Makefile.in: Ditto.
2329 * configure: Re-generate.
2330
2331 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2332
2333Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2334
2335 * interp.c (mips_option_handler): New function parse argumes using
2336 sim-options.
2337 (myname): Replace with STATE_MY_NAME.
2338 (sim_open): Delete check for host endianness - performed by
2339 sim_config.
2340 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2341 (sim_open): Move much of the initialization from here.
2342 (sim_load): To here. After the image has been loaded and
2343 endianness set.
2344 (sim_open): Move ColdReset from here.
2345 (sim_create_inferior): To here.
2346 (sim_open): Make FP check less dependant on host endianness.
2347
2348 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2349 run.
2350 * interp.c (sim_set_callbacks): Delete.
2351
2352 * interp.c (membank, membank_base, membank_size): Replace with
2353 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2354 (sim_open): Remove call to callback->init. gdb/run do this.
2355
2356 * interp.c: Update
2357
2358 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2359
2360 * interp.c (big_endian_p): Delete, replaced by
2361 current_target_byte_order.
2362
2363Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * interp.c (host_read_long, host_read_word, host_swap_word,
2366 host_swap_long): Delete. Using common sim-endian.
2367 (sim_fetch_register, sim_store_register): Use H2T.
2368 (pipeline_ticks): Delete. Handled by sim-events.
2369 (sim_info): Update.
2370 (sim_engine_run): Update.
2371
2372Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2373
2374 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2375 reason from here.
2376 (SignalException): To here. Signal using sim_engine_halt.
2377 (sim_stop_reason): Delete, moved to common.
2378
2379Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2380
2381 * interp.c (sim_open): Add callback argument.
2382 (sim_set_callbacks): Delete SIM_DESC argument.
2383 (sim_size): Ditto.
2384
2385Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2386
2387 * Makefile.in (SIM_OBJS): Add common modules.
2388
2389 * interp.c (sim_set_callbacks): Also set SD callback.
2390 (set_endianness, xfer_*, swap_*): Delete.
2391 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2392 Change to functions using sim-endian macros.
2393 (control_c, sim_stop): Delete, use common version.
2394 (simulate): Convert into.
2395 (sim_engine_run): This function.
2396 (sim_resume): Delete.
2397
2398 * interp.c (simulation): New variable - the simulator object.
2399 (sim_kind): Delete global - merged into simulation.
2400 (sim_load): Cleanup. Move PC assignment from here.
2401 (sim_create_inferior): To here.
2402
2403 * sim-main.h: New file.
2404 * interp.c (sim-main.h): Include.
2405
2406Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2407
2408 * configure: Regenerated to track ../common/aclocal.m4 changes.
2409
2410Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2411
2412 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2413
2414Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2415
2416 * gencode.c (build_instruction): DIV instructions: check
2417 for division by zero and integer overflow before using
2418 host's division operation.
2419
2420Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2421
2422 * Makefile.in (SIM_OBJS): Add sim-load.o.
2423 * interp.c: #include bfd.h.
2424 (target_byte_order): Delete.
2425 (sim_kind, myname, big_endian_p): New static locals.
2426 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2427 after argument parsing. Recognize -E arg, set endianness accordingly.
2428 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2429 load file into simulator. Set PC from bfd.
2430 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2431 (set_endianness): Use big_endian_p instead of target_byte_order.
2432
2433Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434
2435 * interp.c (sim_size): Delete prototype - conflicts with
2436 definition in remote-sim.h. Correct definition.
2437
2438Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2439
2440 * configure: Regenerated to track ../common/aclocal.m4 changes.
2441 * config.in: Ditto.
2442
2443Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2444
2445 * interp.c (sim_open): New arg `kind'.
2446
2447 * configure: Regenerated to track ../common/aclocal.m4 changes.
2448
2449Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2450
2451 * configure: Regenerated to track ../common/aclocal.m4 changes.
2452
2453Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2454
2455 * interp.c (sim_open): Set optind to 0 before calling getopt.
2456
2457Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2458
2459 * configure: Regenerated to track ../common/aclocal.m4 changes.
2460
2461Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2462
2463 * interp.c : Replace uses of pr_addr with pr_uword64
2464 where the bit length is always 64 independent of SIM_ADDR.
2465 (pr_uword64) : added.
2466
2467Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2468
2469 * configure: Re-generate.
2470
2471Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2472
2473 * configure: Regenerate to track ../common/aclocal.m4 changes.
2474
2475Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2476
2477 * interp.c (sim_open): New SIM_DESC result. Argument is now
2478 in argv form.
2479 (other sim_*): New SIM_DESC argument.
2480
2481Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2482
2483 * interp.c: Fix printing of addresses for non-64-bit targets.
2484 (pr_addr): Add function to print address based on size.
2485
2486Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2487
2488 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2489
2490Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2491
2492 * gencode.c (build_mips16_operands): Correct computation of base
2493 address for extended PC relative instruction.
2494
2495Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2496
2497 * interp.c (mips16_entry): Add support for floating point cases.
2498 (SignalException): Pass floating point cases to mips16_entry.
2499 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2500 registers.
2501 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2502 or fmt_word.
2503 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2504 and then set the state to fmt_uninterpreted.
2505 (COP_SW): Temporarily set the state to fmt_word while calling
2506 ValueFPR.
2507
2508Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2509
2510 * gencode.c (build_instruction): The high order may be set in the
2511 comparison flags at any ISA level, not just ISA 4.
2512
2513Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2514
2515 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2516 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2517 * configure.in: sinclude ../common/aclocal.m4.
2518 * configure: Regenerated.
2519
2520Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2521
2522 * configure: Rebuild after change to aclocal.m4.
2523
2524Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2525
2526 * configure configure.in Makefile.in: Update to new configure
2527 scheme which is more compatible with WinGDB builds.
2528 * configure.in: Improve comment on how to run autoconf.
2529 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2530 * Makefile.in: Use autoconf substitution to install common
2531 makefile fragment.
2532
2533Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2534
2535 * gencode.c (build_instruction): Use BigEndianCPU instead of
2536 ByteSwapMem.
2537
2538Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2539
2540 * interp.c (sim_monitor): Make output to stdout visible in
2541 wingdb's I/O log window.
2542
2543Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2544
2545 * support.h: Undo previous change to SIGTRAP
2546 and SIGQUIT values.
2547
2548Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2549
2550 * interp.c (store_word, load_word): New static functions.
2551 (mips16_entry): New static function.
2552 (SignalException): Look for mips16 entry and exit instructions.
2553 (simulate): Use the correct index when setting fpr_state after
2554 doing a pending move.
2555
2556Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2557
2558 * interp.c: Fix byte-swapping code throughout to work on
2559 both little- and big-endian hosts.
2560
2561Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2562
2563 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2564 with gdb/config/i386/xm-windows.h.
2565
2566Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2567
2568 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2569 that messes up arithmetic shifts.
2570
2571Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2572
2573 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2574 SIGTRAP and SIGQUIT for _WIN32.
2575
2576Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2577
2578 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2579 force a 64 bit multiplication.
2580 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2581 destination register is 0, since that is the default mips16 nop
2582 instruction.
2583
2584Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2585
2586 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2587 (build_endian_shift): Don't check proc64.
2588 (build_instruction): Always set memval to uword64. Cast op2 to
2589 uword64 when shifting it left in memory instructions. Always use
2590 the same code for stores--don't special case proc64.
2591
2592 * gencode.c (build_mips16_operands): Fix base PC value for PC
2593 relative operands.
2594 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2595 jal instruction.
2596 * interp.c (simJALDELAYSLOT): Define.
2597 (JALDELAYSLOT): Define.
2598 (INDELAYSLOT, INJALDELAYSLOT): Define.
2599 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2600
2601Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2602
2603 * interp.c (sim_open): add flush_cache as a PMON routine
2604 (sim_monitor): handle flush_cache by ignoring it
2605
2606Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2607
2608 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2609 BigEndianMem.
2610 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2611 (BigEndianMem): Rename to ByteSwapMem and change sense.
2612 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2613 BigEndianMem references to !ByteSwapMem.
2614 (set_endianness): New function, with prototype.
2615 (sim_open): Call set_endianness.
2616 (sim_info): Use simBE instead of BigEndianMem.
2617 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2618 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2619 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2620 ifdefs, keeping the prototype declaration.
2621 (swap_word): Rewrite correctly.
2622 (ColdReset): Delete references to CONFIG. Delete endianness related
2623 code; moved to set_endianness.
2624
2625Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2626
2627 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2628 * interp.c (CHECKHILO): Define away.
2629 (simSIGINT): New macro.
2630 (membank_size): Increase from 1MB to 2MB.
2631 (control_c): New function.
2632 (sim_resume): Rename parameter signal to signal_number. Add local
2633 variable prev. Call signal before and after simulate.
2634 (sim_stop_reason): Add simSIGINT support.
2635 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2636 functions always.
2637 (sim_warning): Delete call to SignalException. Do call printf_filtered
2638 if logfh is NULL.
2639 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2640 a call to sim_warning.
2641
2642Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2643
2644 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2645 16 bit instructions.
2646
2647Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2648
2649 Add support for mips16 (16 bit MIPS implementation):
2650 * gencode.c (inst_type): Add mips16 instruction encoding types.
2651 (GETDATASIZEINSN): Define.
2652 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2653 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2654 mtlo.
2655 (MIPS16_DECODE): New table, for mips16 instructions.
2656 (bitmap_val): New static function.
2657 (struct mips16_op): Define.
2658 (mips16_op_table): New table, for mips16 operands.
2659 (build_mips16_operands): New static function.
2660 (process_instructions): If PC is odd, decode a mips16
2661 instruction. Break out instruction handling into new
2662 build_instruction function.
2663 (build_instruction): New static function, broken out of
2664 process_instructions. Check modifiers rather than flags for SHIFT
2665 bit count and m[ft]{hi,lo} direction.
2666 (usage): Pass program name to fprintf.
2667 (main): Remove unused variable this_option_optind. Change
2668 ``*loptarg++'' to ``loptarg++''.
2669 (my_strtoul): Parenthesize && within ||.
2670 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2671 (simulate): If PC is odd, fetch a 16 bit instruction, and
2672 increment PC by 2 rather than 4.
2673 * configure.in: Add case for mips16*-*-*.
2674 * configure: Rebuild.
2675
2676Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2677
2678 * interp.c: Allow -t to enable tracing in standalone simulator.
2679 Fix garbage output in trace file and error messages.
2680
2681Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2682
2683 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2684 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2685 * configure.in: Simplify using macros in ../common/aclocal.m4.
2686 * configure: Regenerated.
2687 * tconfig.in: New file.
2688
2689Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2690
2691 * interp.c: Fix bugs in 64-bit port.
2692 Use ansi function declarations for msvc compiler.
2693 Initialize and test file pointer in trace code.
2694 Prevent duplicate definition of LAST_EMED_REGNUM.
2695
2696Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2697
2698 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2699
2700Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2701
2702 * interp.c (SignalException): Check for explicit terminating
2703 breakpoint value.
2704 * gencode.c: Pass instruction value through SignalException()
2705 calls for Trap, Breakpoint and Syscall.
2706
2707Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2708
2709 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2710 only used on those hosts that provide it.
2711 * configure.in: Add sqrt() to list of functions to be checked for.
2712 * config.in: Re-generated.
2713 * configure: Re-generated.
2714
2715Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2716
2717 * gencode.c (process_instructions): Call build_endian_shift when
2718 expanding STORE RIGHT, to fix swr.
2719 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2720 clear the high bits.
2721 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2722 Fix float to int conversions to produce signed values.
2723
2724Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2725
2726 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2727 (process_instructions): Correct handling of nor instruction.
2728 Correct shift count for 32 bit shift instructions. Correct sign
2729 extension for arithmetic shifts to not shift the number of bits in
2730 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2731 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2732 Fix madd.
2733 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2734 It's OK to have a mult follow a mult. What's not OK is to have a
2735 mult follow an mfhi.
2736 (Convert): Comment out incorrect rounding code.
2737
2738Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2739
2740 * interp.c (sim_monitor): Improved monitor printf
2741 simulation. Tidied up simulator warnings, and added "--log" option
2742 for directing warning message output.
2743 * gencode.c: Use sim_warning() rather than WARNING macro.
2744
2745Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2746
2747 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2748 getopt1.o, rather than on gencode.c. Link objects together.
2749 Don't link against -liberty.
2750 (gencode.o, getopt.o, getopt1.o): New targets.
2751 * gencode.c: Include <ctype.h> and "ansidecl.h".
2752 (AND): Undefine after including "ansidecl.h".
2753 (ULONG_MAX): Define if not defined.
2754 (OP_*): Don't define macros; now defined in opcode/mips.h.
2755 (main): Call my_strtoul rather than strtoul.
2756 (my_strtoul): New static function.
2757
2758Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2759
2760 * gencode.c (process_instructions): Generate word64 and uword64
2761 instead of `long long' and `unsigned long long' data types.
2762 * interp.c: #include sysdep.h to get signals, and define default
2763 for SIGBUS.
2764 * (Convert): Work around for Visual-C++ compiler bug with type
2765 conversion.
2766 * support.h: Make things compile under Visual-C++ by using
2767 __int64 instead of `long long'. Change many refs to long long
2768 into word64/uword64 typedefs.
2769
2770Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2771
2772 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2773 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2774 (docdir): Removed.
2775 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2776 (AC_PROG_INSTALL): Added.
2777 (AC_PROG_CC): Moved to before configure.host call.
2778 * configure: Rebuilt.
2779
2780Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2781
2782 * configure.in: Define @SIMCONF@ depending on mips target.
2783 * configure: Rebuild.
2784 * Makefile.in (run): Add @SIMCONF@ to control simulator
2785 construction.
2786 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2787 * interp.c: Remove some debugging, provide more detailed error
2788 messages, update memory accesses to use LOADDRMASK.
2789
2790Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2791
2792 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2793 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2794 stamp-h.
2795 * configure: Rebuild.
2796 * config.in: New file, generated by autoheader.
2797 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2798 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2799 HAVE_ANINT and HAVE_AINT, as appropriate.
2800 * Makefile.in (run): Use @LIBS@ rather than -lm.
2801 (interp.o): Depend upon config.h.
2802 (Makefile): Just rebuild Makefile.
2803 (clean): Remove stamp-h.
2804 (mostlyclean): Make the same as clean, not as distclean.
2805 (config.h, stamp-h): New targets.
2806
2807Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2808
2809 * interp.c (ColdReset): Fix boolean test. Make all simulator
2810 globals static.
2811
2812Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2813
2814 * interp.c (xfer_direct_word, xfer_direct_long,
2815 swap_direct_word, swap_direct_long, xfer_big_word,
2816 xfer_big_long, xfer_little_word, xfer_little_long,
2817 swap_word,swap_long): Added.
2818 * interp.c (ColdReset): Provide function indirection to
2819 host<->simulated_target transfer routines.
2820 * interp.c (sim_store_register, sim_fetch_register): Updated to
2821 make use of indirected transfer routines.
2822
2823Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2824
2825 * gencode.c (process_instructions): Ensure FP ABS instruction
2826 recognised.
2827 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2828 system call support.
2829
2830Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2831
2832 * interp.c (sim_do_command): Complain if callback structure not
2833 initialised.
2834
2835Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2836
2837 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2838 support for Sun hosts.
2839 * Makefile.in (gencode): Ensure the host compiler and libraries
2840 used for cross-hosted build.
2841
2842Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2843
2844 * interp.c, gencode.c: Some more (TODO) tidying.
2845
2846Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2847
2848 * gencode.c, interp.c: Replaced explicit long long references with
2849 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2850 * support.h (SET64LO, SET64HI): Macros added.
2851
2852Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2853
2854 * configure: Regenerate with autoconf 2.7.
2855
2856Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2857
2858 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2859 * support.h: Remove superfluous "1" from #if.
2860 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2861
2862Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2863
2864 * interp.c (StoreFPR): Control UndefinedResult() call on
2865 WARN_RESULT manifest.
2866
2867Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2868
2869 * gencode.c: Tidied instruction decoding, and added FP instruction
2870 support.
2871
2872 * interp.c: Added dineroIII, and BSD profiling support. Also
2873 run-time FP handling.
2874
2875Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2876
2877 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2878 gencode.c, interp.c, support.h: created.
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