]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/mmc.c
mvebu_mmc: Driver addition
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF
8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF
14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF
20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK
25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK
38 else
39 wp = 0;
40 }
d23d8d7e
NK
41
42 return wp;
43}
44
cee9ab7c
JH
45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB
47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR
55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR
61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR
88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF
106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR
109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR
112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR
120
121 do {
122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK
123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK
130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK
133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9
RR
137
138 udelay(1000);
139
5d4fc8d9
RR
140 } while (timeout--);
141
5db2fe3a
RR
142#ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
145#endif
5b0c942f 146 if (timeout <= 0) {
56196826 147#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 148 printf("Timeout waiting card ready\n");
56196826 149#endif
5d4fc8d9
RR
150 return TIMEOUT;
151 }
6b2221b0
AG
152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
153 return SWITCH_ERR;
5d4fc8d9
RR
154
155 return 0;
156}
157
da61fa5f 158int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF
159{
160 struct mmc_cmd cmd;
161
d22e3d46
JC
162 if (mmc->card_caps & MMC_MODE_DDR_52MHz)
163 return 0;
164
272cc70b
AF
165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
167 cmd.cmdarg = len;
272cc70b
AF
168
169 return mmc_send_cmd(mmc, &cmd, NULL);
170}
171
172struct mmc *find_mmc_device(int dev_num)
173{
174 struct mmc *m;
175 struct list_head *entry;
176
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
179
180 if (m->block_dev.dev == dev_num)
181 return m;
182 }
183
56196826 184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 185 printf("MMC Device %d not found\n", dev_num);
56196826 186#endif
272cc70b
AF
187
188 return NULL;
189}
190
ff8fef56 191static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 192 lbaint_t blkcnt)
272cc70b
AF
193{
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
4a1a06bc
AS
197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF
201
202 if (mmc->high_capacity)
4a1a06bc 203 cmd.cmdarg = start;
272cc70b 204 else
4a1a06bc 205 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF
206
207 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF
208
209 data.dest = dst;
4a1a06bc 210 data.blocks = blkcnt;
272cc70b
AF
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
4a1a06bc
AS
214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
272cc70b 216
4a1a06bc
AS
217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 222#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 223 printf("mmc fail to send stop cmd\n");
56196826 224#endif
4a1a06bc
AS
225 return 0;
226 }
272cc70b
AF
227 }
228
4a1a06bc 229 return blkcnt;
272cc70b
AF
230}
231
ff8fef56 232static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 233{
4a1a06bc
AS
234 lbaint_t cur, blocks_todo = blkcnt;
235
236 if (blkcnt == 0)
237 return 0;
272cc70b 238
4a1a06bc 239 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF
240 if (!mmc)
241 return 0;
242
d2bf29e3 243 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 244#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 246 start + blkcnt, mmc->block_dev.lba);
56196826 247#endif
d2bf29e3
LW
248 return 0;
249 }
272cc70b 250
4a1a06bc 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 252 return 0;
272cc70b 253
4a1a06bc 254 do {
93bfd616
PA
255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF
263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF
268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF
277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF
289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF
298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB
306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 315 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF
316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC
338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF
346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC
353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF
357 int err;
358
e9550449
CLC
359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
93bfd616 364 (mmc->cfg->voltages &
e9550449
CLC
365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
93bfd616 368 if (mmc->cfg->host_caps & MMC_MODE_HC)
e9550449
CLC
369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
750121c3 378static int mmc_send_op_cond(struct mmc *mmc)
e9550449
CLC
379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF
383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC
387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC
401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC
407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF
411 if (err)
412 return err;
e9550449
CLC
413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC
422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF
431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF
434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF
440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF
453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF
462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR
464 int timeout = 1000;
465 int ret;
272cc70b
AF
466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR
470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR
473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK
476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR
478
479 return ret;
480
272cc70b
AF
481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF
486 char cardtype;
487 int err;
488
489 mmc->card_caps = 0;
490
d52ebf10
TC
491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF
494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
272cc70b
AF
498 err = mmc_send_ext_csd(mmc, ext_csd);
499
500 if (err)
501 return err;
502
0560db18 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF
504
505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
506
507 if (err)
6b2221b0 508 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF
509
510 /* Now check to see that it worked */
511 err = mmc_send_ext_csd(mmc, ext_csd);
512
513 if (err)
514 return err;
515
516 /* No high-speed support */
0560db18 517 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF
518 return 0;
519
520 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46
JC
521 if (cardtype & EXT_CSD_CARD_TYPE_52) {
522 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
523 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 524 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 525 } else {
272cc70b 526 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 527 }
272cc70b
AF
528
529 return 0;
530}
531
f866a46d
SW
532static int mmc_set_capacity(struct mmc *mmc, int part_num)
533{
534 switch (part_num) {
535 case 0:
536 mmc->capacity = mmc->capacity_user;
537 break;
538 case 1:
539 case 2:
540 mmc->capacity = mmc->capacity_boot;
541 break;
542 case 3:
543 mmc->capacity = mmc->capacity_rpmb;
544 break;
545 case 4:
546 case 5:
547 case 6:
548 case 7:
549 mmc->capacity = mmc->capacity_gp[part_num - 4];
550 break;
551 default:
552 return -1;
553 }
554
555 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
556
557 return 0;
558}
559
d2356284
SW
560int mmc_select_hwpart(int dev_num, int hwpart)
561{
562 struct mmc *mmc = find_mmc_device(dev_num);
563 int ret;
564
565 if (!mmc)
d4622df3 566 return -ENODEV;
d2356284
SW
567
568 if (mmc->part_num == hwpart)
569 return 0;
570
571 if (mmc->part_config == MMCPART_NOAVAILABLE) {
572 printf("Card doesn't support part_switch\n");
d4622df3 573 return -EMEDIUMTYPE;
d2356284
SW
574 }
575
576 ret = mmc_switch_part(dev_num, hwpart);
577 if (ret)
d4622df3 578 return ret;
d2356284
SW
579
580 mmc->part_num = hwpart;
581
582 return 0;
583}
584
585
bc897b1d
LW
586int mmc_switch_part(int dev_num, unsigned int part_num)
587{
588 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 589 int ret;
bc897b1d
LW
590
591 if (!mmc)
592 return -1;
593
f866a46d
SW
594 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
595 (mmc->part_config & ~PART_ACCESS_MASK)
596 | (part_num & PART_ACCESS_MASK));
f866a46d 597
6dc93e70
PB
598 /*
599 * Set the capacity if the switch succeeded or was intended
600 * to return to representing the raw device.
601 */
602 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
603 ret = mmc_set_capacity(mmc, part_num);
604
605 return ret;
bc897b1d
LW
606}
607
48972d90
TR
608int mmc_getcd(struct mmc *mmc)
609{
610 int cd;
611
612 cd = board_mmc_getcd(mmc);
613
d4e1da4e 614 if (cd < 0) {
93bfd616
PA
615 if (mmc->cfg->ops->getcd)
616 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK
617 else
618 cd = 1;
619 }
48972d90
TR
620
621 return cd;
622}
623
fdbb873e 624static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF
625{
626 struct mmc_cmd cmd;
627 struct mmc_data data;
628
629 /* Switch the frequency */
630 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
631 cmd.resp_type = MMC_RSP_R1;
632 cmd.cmdarg = (mode << 31) | 0xffffff;
633 cmd.cmdarg &= ~(0xf << (group * 4));
634 cmd.cmdarg |= value << (group * 4);
272cc70b
AF
635
636 data.dest = (char *)resp;
637 data.blocksize = 64;
638 data.blocks = 1;
639 data.flags = MMC_DATA_READ;
640
641 return mmc_send_cmd(mmc, &cmd, &data);
642}
643
644
fdbb873e 645static int sd_change_freq(struct mmc *mmc)
272cc70b
AF
646{
647 int err;
648 struct mmc_cmd cmd;
f781dd38
A
649 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
650 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF
651 struct mmc_data data;
652 int timeout;
653
654 mmc->card_caps = 0;
655
d52ebf10
TC
656 if (mmc_host_is_spi(mmc))
657 return 0;
658
272cc70b
AF
659 /* Read the SCR to find out if this card supports higher speeds */
660 cmd.cmdidx = MMC_CMD_APP_CMD;
661 cmd.resp_type = MMC_RSP_R1;
662 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
663
664 err = mmc_send_cmd(mmc, &cmd, NULL);
665
666 if (err)
667 return err;
668
669 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
670 cmd.resp_type = MMC_RSP_R1;
671 cmd.cmdarg = 0;
272cc70b
AF
672
673 timeout = 3;
674
675retry_scr:
f781dd38 676 data.dest = (char *)scr;
272cc70b
AF
677 data.blocksize = 8;
678 data.blocks = 1;
679 data.flags = MMC_DATA_READ;
680
681 err = mmc_send_cmd(mmc, &cmd, &data);
682
683 if (err) {
684 if (timeout--)
685 goto retry_scr;
686
687 return err;
688 }
689
4e3d89ba
YK
690 mmc->scr[0] = __be32_to_cpu(scr[0]);
691 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF
692
693 switch ((mmc->scr[0] >> 24) & 0xf) {
694 case 0:
695 mmc->version = SD_VERSION_1_0;
696 break;
697 case 1:
698 mmc->version = SD_VERSION_1_10;
699 break;
700 case 2:
701 mmc->version = SD_VERSION_2;
1741c64d
JC
702 if ((mmc->scr[0] >> 15) & 0x1)
703 mmc->version = SD_VERSION_3;
272cc70b
AF
704 break;
705 default:
706 mmc->version = SD_VERSION_1_0;
707 break;
708 }
709
b44c7083
AS
710 if (mmc->scr[0] & SD_DATA_4BIT)
711 mmc->card_caps |= MMC_MODE_4BIT;
712
272cc70b
AF
713 /* Version 1.0 doesn't support switching */
714 if (mmc->version == SD_VERSION_1_0)
715 return 0;
716
717 timeout = 4;
718 while (timeout--) {
719 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 720 (u8 *)switch_status);
272cc70b
AF
721
722 if (err)
723 return err;
724
725 /* The high-speed function is busy. Try again */
4e3d89ba 726 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF
727 break;
728 }
729
272cc70b 730 /* If high-speed isn't supported, we return */
4e3d89ba 731 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF
732 return 0;
733
2c3fbf4c
ML
734 /*
735 * If the host doesn't support SD_HIGHSPEED, do not switch card to
736 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
737 * This can avoid furthur problem when the card runs in different
738 * mode between the host.
739 */
93bfd616
PA
740 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
741 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML
742 return 0;
743
f781dd38 744 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF
745
746 if (err)
747 return err;
748
4e3d89ba 749 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF
750 mmc->card_caps |= MMC_MODE_HS;
751
752 return 0;
753}
754
755/* frequency bases */
756/* divided by 10 to be nice to platforms without floating point */
5f837c2c 757static const int fbase[] = {
272cc70b
AF
758 10000,
759 100000,
760 1000000,
761 10000000,
762};
763
764/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
765 * to platforms without floating point.
766 */
5f837c2c 767static const int multipliers[] = {
272cc70b
AF
768 0, /* reserved */
769 10,
770 12,
771 13,
772 15,
773 20,
774 25,
775 30,
776 35,
777 40,
778 45,
779 50,
780 55,
781 60,
782 70,
783 80,
784};
785
fdbb873e 786static void mmc_set_ios(struct mmc *mmc)
272cc70b 787{
93bfd616
PA
788 if (mmc->cfg->ops->set_ios)
789 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF
790}
791
792void mmc_set_clock(struct mmc *mmc, uint clock)
793{
93bfd616
PA
794 if (clock > mmc->cfg->f_max)
795 clock = mmc->cfg->f_max;
272cc70b 796
93bfd616
PA
797 if (clock < mmc->cfg->f_min)
798 clock = mmc->cfg->f_min;
272cc70b
AF
799
800 mmc->clock = clock;
801
802 mmc_set_ios(mmc);
803}
804
fdbb873e 805static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF
806{
807 mmc->bus_width = width;
808
809 mmc_set_ios(mmc);
810}
811
fdbb873e 812static int mmc_startup(struct mmc *mmc)
272cc70b 813{
f866a46d 814 int err, i;
272cc70b 815 uint mult, freq;
639b7827 816 u64 cmult, csize, capacity;
272cc70b 817 struct mmc_cmd cmd;
8bfa195e
SG
818 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
819 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 820 int timeout = 1000;
272cc70b 821
d52ebf10
TC
822#ifdef CONFIG_MMC_SPI_CRC_ON
823 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
824 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
825 cmd.resp_type = MMC_RSP_R1;
826 cmd.cmdarg = 1;
d52ebf10
TC
827 err = mmc_send_cmd(mmc, &cmd, NULL);
828
829 if (err)
830 return err;
831 }
832#endif
833
272cc70b 834 /* Put the Card in Identify Mode */
d52ebf10
TC
835 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
836 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF
837 cmd.resp_type = MMC_RSP_R2;
838 cmd.cmdarg = 0;
272cc70b
AF
839
840 err = mmc_send_cmd(mmc, &cmd, NULL);
841
842 if (err)
843 return err;
844
845 memcpy(mmc->cid, cmd.response, 16);
846
847 /*
848 * For MMC cards, set the Relative Address.
849 * For SD cards, get the Relatvie Address.
850 * This also puts the cards into Standby State
851 */
d52ebf10
TC
852 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
853 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
854 cmd.cmdarg = mmc->rca << 16;
855 cmd.resp_type = MMC_RSP_R6;
272cc70b 856
d52ebf10 857 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 858
d52ebf10
TC
859 if (err)
860 return err;
272cc70b 861
d52ebf10
TC
862 if (IS_SD(mmc))
863 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
864 }
272cc70b
AF
865
866 /* Get the Card-Specific Data */
867 cmd.cmdidx = MMC_CMD_SEND_CSD;
868 cmd.resp_type = MMC_RSP_R2;
869 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
870
871 err = mmc_send_cmd(mmc, &cmd, NULL);
872
5d4fc8d9
RR
873 /* Waiting for the ready status */
874 mmc_send_status(mmc, timeout);
875
272cc70b
AF
876 if (err)
877 return err;
878
998be3dd
RV
879 mmc->csd[0] = cmd.response[0];
880 mmc->csd[1] = cmd.response[1];
881 mmc->csd[2] = cmd.response[2];
882 mmc->csd[3] = cmd.response[3];
272cc70b
AF
883
884 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 885 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF
886
887 switch (version) {
888 case 0:
889 mmc->version = MMC_VERSION_1_2;
890 break;
891 case 1:
892 mmc->version = MMC_VERSION_1_4;
893 break;
894 case 2:
895 mmc->version = MMC_VERSION_2_2;
896 break;
897 case 3:
898 mmc->version = MMC_VERSION_3;
899 break;
900 case 4:
901 mmc->version = MMC_VERSION_4;
902 break;
903 default:
904 mmc->version = MMC_VERSION_1_2;
905 break;
906 }
907 }
908
909 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV
910 freq = fbase[(cmd.response[0] & 0x7)];
911 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF
912
913 mmc->tran_speed = freq * mult;
914
ab71188c 915 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 916 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF
917
918 if (IS_SD(mmc))
919 mmc->write_bl_len = mmc->read_bl_len;
920 else
998be3dd 921 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF
922
923 if (mmc->high_capacity) {
924 csize = (mmc->csd[1] & 0x3f) << 16
925 | (mmc->csd[2] & 0xffff0000) >> 16;
926 cmult = 8;
927 } else {
928 csize = (mmc->csd[1] & 0x3ff) << 2
929 | (mmc->csd[2] & 0xc0000000) >> 30;
930 cmult = (mmc->csd[2] & 0x00038000) >> 15;
931 }
932
f866a46d
SW
933 mmc->capacity_user = (csize + 1) << (cmult + 2);
934 mmc->capacity_user *= mmc->read_bl_len;
935 mmc->capacity_boot = 0;
936 mmc->capacity_rpmb = 0;
937 for (i = 0; i < 4; i++)
938 mmc->capacity_gp[i] = 0;
272cc70b 939
8bfa195e
SG
940 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
941 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 942
8bfa195e
SG
943 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
944 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 945
ab71188c
MN
946 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
947 cmd.cmdidx = MMC_CMD_SET_DSR;
948 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
949 cmd.resp_type = MMC_RSP_NONE;
950 if (mmc_send_cmd(mmc, &cmd, NULL))
951 printf("MMC: SET_DSR failed\n");
952 }
953
272cc70b 954 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC
955 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
956 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 957 cmd.resp_type = MMC_RSP_R1;
d52ebf10 958 cmd.cmdarg = mmc->rca << 16;
d52ebf10 959 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 960
d52ebf10
TC
961 if (err)
962 return err;
963 }
272cc70b 964
e6f99a56
LW
965 /*
966 * For SD, its erase group is always one sector
967 */
968 mmc->erase_grp_size = 1;
bc897b1d 969 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG
970 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
971 /* check ext_csd version and capacity */
972 err = mmc_send_ext_csd(mmc, ext_csd);
fdbb873e 973 if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
639b7827
YS
974 /*
975 * According to the JEDEC Standard, the value of
976 * ext_csd's capacity is valid if the value is more
977 * than 2GB
978 */
0560db18
LW
979 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
980 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
981 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
982 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 983 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 984 if ((capacity >> 20) > 2 * 1024)
f866a46d 985 mmc->capacity_user = capacity;
d23e2c09 986 }
bc897b1d 987
64f4a619
JC
988 switch (ext_csd[EXT_CSD_REV]) {
989 case 1:
990 mmc->version = MMC_VERSION_4_1;
991 break;
992 case 2:
993 mmc->version = MMC_VERSION_4_2;
994 break;
995 case 3:
996 mmc->version = MMC_VERSION_4_3;
997 break;
998 case 5:
999 mmc->version = MMC_VERSION_4_41;
1000 break;
1001 case 6:
1002 mmc->version = MMC_VERSION_4_5;
1003 break;
1004 }
1005
e6f99a56 1006 /*
1937e5aa
OM
1007 * Host needs to enable ERASE_GRP_DEF bit if device is
1008 * partitioned. This bit will be lost every time after a reset
1009 * or power off. This will affect erase size.
e6f99a56 1010 */
1937e5aa
OM
1011 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1012 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) {
1013 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1014 EXT_CSD_ERASE_GROUP_DEF, 1);
1015
1016 if (err)
1017 return err;
021a8055
HP
1018 else
1019 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1937e5aa
OM
1020
1021 /* Read out group size from ext_csd */
0560db18 1022 mmc->erase_grp_size =
8bfa195e
SG
1023 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
1024 MMC_MAX_BLOCK_LEN * 1024;
1025 } else {
1937e5aa 1026 /* Calculate the group size from the csd value. */
e6f99a56
LW
1027 int erase_gsz, erase_gmul;
1028 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1029 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1030 mmc->erase_grp_size = (erase_gsz + 1)
1031 * (erase_gmul + 1);
1032 }
1033
bc897b1d 1034 /* store the partition info of emmc */
8948ea83
SW
1035 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1036 ext_csd[EXT_CSD_BOOT_MULT])
0560db18 1037 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
f866a46d
SW
1038
1039 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1040
1041 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1042
1043 for (i = 0; i < 4; i++) {
1044 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1045 mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
1046 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1047 mmc->capacity_gp[i] *=
1048 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1049 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1050 }
d23e2c09
SG
1051 }
1052
f866a46d
SW
1053 err = mmc_set_capacity(mmc, mmc->part_num);
1054 if (err)
1055 return err;
1056
272cc70b
AF
1057 if (IS_SD(mmc))
1058 err = sd_change_freq(mmc);
1059 else
1060 err = mmc_change_freq(mmc);
1061
1062 if (err)
1063 return err;
1064
1065 /* Restrict card's capabilities by what the host can do */
93bfd616 1066 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF
1067
1068 if (IS_SD(mmc)) {
1069 if (mmc->card_caps & MMC_MODE_4BIT) {
1070 cmd.cmdidx = MMC_CMD_APP_CMD;
1071 cmd.resp_type = MMC_RSP_R1;
1072 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1073
1074 err = mmc_send_cmd(mmc, &cmd, NULL);
1075 if (err)
1076 return err;
1077
1078 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1079 cmd.resp_type = MMC_RSP_R1;
1080 cmd.cmdarg = 2;
272cc70b
AF
1081 err = mmc_send_cmd(mmc, &cmd, NULL);
1082 if (err)
1083 return err;
1084
1085 mmc_set_bus_width(mmc, 4);
1086 }
1087
1088 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1089 mmc->tran_speed = 50000000;
272cc70b 1090 else
ad5fd922 1091 mmc->tran_speed = 25000000;
272cc70b 1092 } else {
7798f6db
AF
1093 int idx;
1094
1095 /* An array of possible bus widths in order of preference */
1096 static unsigned ext_csd_bits[] = {
d22e3d46
JC
1097 EXT_CSD_DDR_BUS_WIDTH_8,
1098 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF
1099 EXT_CSD_BUS_WIDTH_8,
1100 EXT_CSD_BUS_WIDTH_4,
1101 EXT_CSD_BUS_WIDTH_1,
1102 };
1103
1104 /* An array to map CSD bus widths to host cap bits */
1105 static unsigned ext_to_hostcaps[] = {
d22e3d46
JC
1106 [EXT_CSD_DDR_BUS_WIDTH_4] = MMC_MODE_DDR_52MHz,
1107 [EXT_CSD_DDR_BUS_WIDTH_8] = MMC_MODE_DDR_52MHz,
7798f6db
AF
1108 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1109 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1110 };
1111
1112 /* An array to map chosen bus width to an integer */
1113 static unsigned widths[] = {
d22e3d46 1114 8, 4, 8, 4, 1,
7798f6db
AF
1115 };
1116
1117 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1118 unsigned int extw = ext_csd_bits[idx];
1119
1120 /*
1121 * Check to make sure the controller supports
1122 * this bus width, if it's more than 1
1123 */
1124 if (extw != EXT_CSD_BUS_WIDTH_1 &&
93bfd616 1125 !(mmc->cfg->host_caps & ext_to_hostcaps[extw]))
7798f6db
AF
1126 continue;
1127
272cc70b 1128 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1129 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF
1130
1131 if (err)
4137894e 1132 continue;
272cc70b 1133
7798f6db 1134 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW
1135
1136 err = mmc_send_ext_csd(mmc, test_csd);
1137 if (!err && ext_csd[EXT_CSD_PARTITIONING_SUPPORT] \
1138 == test_csd[EXT_CSD_PARTITIONING_SUPPORT]
1139 && ext_csd[EXT_CSD_ERASE_GROUP_DEF] \
1140 == test_csd[EXT_CSD_ERASE_GROUP_DEF] \
1141 && ext_csd[EXT_CSD_REV] \
1142 == test_csd[EXT_CSD_REV]
1143 && ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] \
1144 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1145 && memcmp(&ext_csd[EXT_CSD_SEC_CNT], \
1146 &test_csd[EXT_CSD_SEC_CNT], 4) == 0) {
1147
7798f6db 1148 mmc->card_caps |= ext_to_hostcaps[extw];
4137894e
LW
1149 break;
1150 }
272cc70b
AF
1151 }
1152
1153 if (mmc->card_caps & MMC_MODE_HS) {
1154 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1155 mmc->tran_speed = 52000000;
272cc70b 1156 else
ad5fd922
JC
1157 mmc->tran_speed = 26000000;
1158 }
272cc70b
AF
1159 }
1160
ad5fd922
JC
1161 mmc_set_clock(mmc, mmc->tran_speed);
1162
272cc70b
AF
1163 /* fill in device description */
1164 mmc->block_dev.lun = 0;
1165 mmc->block_dev.type = 0;
1166 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1167 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1168 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1169#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH
1170 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1171 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1172 (mmc->cid[3] >> 16) & 0xffff);
1173 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1174 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1175 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1176 (mmc->cid[2] >> 24) & 0xff);
1177 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1178 (mmc->cid[2] >> 16) & 0xf);
56196826
PB
1179#else
1180 mmc->block_dev.vendor[0] = 0;
1181 mmc->block_dev.product[0] = 0;
1182 mmc->block_dev.revision[0] = 0;
1183#endif
122efd43 1184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1185 init_part(&mmc->block_dev);
122efd43 1186#endif
272cc70b
AF
1187
1188 return 0;
1189}
1190
fdbb873e 1191static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF
1192{
1193 struct mmc_cmd cmd;
1194 int err;
1195
1196 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1197 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1198 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1199 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF
1200
1201 err = mmc_send_cmd(mmc, &cmd, NULL);
1202
1203 if (err)
1204 return err;
1205
998be3dd 1206 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF
1207 return UNUSABLE_ERR;
1208 else
1209 mmc->version = SD_VERSION_2;
1210
1211 return 0;
1212}
1213
93bfd616
PA
1214/* not used any more */
1215int __deprecated mmc_register(struct mmc *mmc)
1216{
1217#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1218 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1219#endif
1220 return -1;
1221}
1222
1223struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1224{
93bfd616
PA
1225 struct mmc *mmc;
1226
1227 /* quick validation */
1228 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1229 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1230 return NULL;
1231
1232 mmc = calloc(1, sizeof(*mmc));
1233 if (mmc == NULL)
1234 return NULL;
1235
1236 mmc->cfg = cfg;
1237 mmc->priv = priv;
1238
1239 /* the following chunk was mmc_register() */
1240
ab71188c
MN
1241 /* Setup dsr related values */
1242 mmc->dsr_imp = 0;
1243 mmc->dsr = 0xffffffff;
272cc70b
AF
1244 /* Setup the universal parts of the block interface just once */
1245 mmc->block_dev.if_type = IF_TYPE_MMC;
1246 mmc->block_dev.dev = cur_dev_num++;
1247 mmc->block_dev.removable = 1;
1248 mmc->block_dev.block_read = mmc_bread;
1249 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1250 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1251
93bfd616
PA
1252 /* setup initial part type */
1253 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1254
93bfd616 1255 INIT_LIST_HEAD(&mmc->link);
272cc70b 1256
93bfd616
PA
1257 list_add_tail(&mmc->link, &mmc_devices);
1258
1259 return mmc;
1260}
1261
1262void mmc_destroy(struct mmc *mmc)
1263{
1264 /* only freeing memory for now */
1265 free(mmc);
272cc70b
AF
1266}
1267
df3fc526 1268#ifdef CONFIG_PARTITIONS
272cc70b
AF
1269block_dev_desc_t *mmc_get_dev(int dev)
1270{
1271 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1272 if (!mmc || mmc_init(mmc))
40242bc3 1273 return NULL;
272cc70b 1274
40242bc3 1275 return &mmc->block_dev;
272cc70b 1276}
df3fc526 1277#endif
272cc70b 1278
e9550449 1279int mmc_start_init(struct mmc *mmc)
272cc70b 1280{
afd5932b 1281 int err;
272cc70b 1282
ab769f22 1283 /* we pretend there's no card when init is NULL */
93bfd616 1284 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1285 mmc->has_init = 0;
56196826 1286#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1287 printf("MMC: no card present\n");
56196826 1288#endif
48972d90
TR
1289 return NO_CARD_ERR;
1290 }
1291
bc897b1d
LW
1292 if (mmc->has_init)
1293 return 0;
1294
ab769f22 1295 /* made sure it's not NULL earlier */
93bfd616 1296 err = mmc->cfg->ops->init(mmc);
272cc70b
AF
1297
1298 if (err)
1299 return err;
1300
b86b85e2
IY
1301 mmc_set_bus_width(mmc, 1);
1302 mmc_set_clock(mmc, 1);
1303
272cc70b
AF
1304 /* Reset the Card */
1305 err = mmc_go_idle(mmc);
1306
1307 if (err)
1308 return err;
1309
bc897b1d
LW
1310 /* The internal partition reset to user partition(0) at every CMD0*/
1311 mmc->part_num = 0;
1312
272cc70b 1313 /* Test for SD version 2 */
afd5932b 1314 err = mmc_send_if_cond(mmc);
272cc70b 1315
272cc70b
AF
1316 /* Now try to get the SD card's operating condition */
1317 err = sd_send_op_cond(mmc);
1318
1319 /* If the command timed out, we check for an MMC card */
1320 if (err == TIMEOUT) {
1321 err = mmc_send_op_cond(mmc);
1322
e9550449 1323 if (err && err != IN_PROGRESS) {
56196826 1324#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1325 printf("Card did not respond to voltage select!\n");
56196826 1326#endif
272cc70b
AF
1327 return UNUSABLE_ERR;
1328 }
1329 }
1330
e9550449
CLC
1331 if (err == IN_PROGRESS)
1332 mmc->init_in_progress = 1;
1333
1334 return err;
1335}
1336
1337static int mmc_complete_init(struct mmc *mmc)
1338{
1339 int err = 0;
1340
1341 if (mmc->op_cond_pending)
1342 err = mmc_complete_op_cond(mmc);
1343
1344 if (!err)
1345 err = mmc_startup(mmc);
bc897b1d
LW
1346 if (err)
1347 mmc->has_init = 0;
1348 else
1349 mmc->has_init = 1;
e9550449
CLC
1350 mmc->init_in_progress = 0;
1351 return err;
1352}
1353
1354int mmc_init(struct mmc *mmc)
1355{
1356 int err = IN_PROGRESS;
d803fea5 1357 unsigned start;
e9550449
CLC
1358
1359 if (mmc->has_init)
1360 return 0;
d803fea5
MZ
1361
1362 start = get_timer(0);
1363
e9550449
CLC
1364 if (!mmc->init_in_progress)
1365 err = mmc_start_init(mmc);
1366
1367 if (!err || err == IN_PROGRESS)
1368 err = mmc_complete_init(mmc);
1369 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1370 return err;
272cc70b
AF
1371}
1372
ab71188c
MN
1373int mmc_set_dsr(struct mmc *mmc, u16 val)
1374{
1375 mmc->dsr = val;
1376 return 0;
1377}
1378
cee9ab7c
JH
1379/* CPU-specific MMC initializations */
1380__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF
1381{
1382 return -1;
1383}
1384
cee9ab7c
JH
1385/* board-specific MMC initializations. */
1386__weak int board_mmc_init(bd_t *bis)
1387{
1388 return -1;
1389}
272cc70b 1390
56196826
PB
1391#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1392
272cc70b
AF
1393void print_mmc_devices(char separator)
1394{
1395 struct mmc *m;
1396 struct list_head *entry;
1397
1398 list_for_each(entry, &mmc_devices) {
1399 m = list_entry(entry, struct mmc, link);
1400
93bfd616 1401 printf("%s: %d", m->cfg->name, m->block_dev.dev);
272cc70b
AF
1402
1403 if (entry->next != &mmc_devices)
1404 printf("%c ", separator);
1405 }
1406
1407 printf("\n");
1408}
1409
56196826
PB
1410#else
1411void print_mmc_devices(char separator) { }
1412#endif
1413
ea6ebe21
LW
1414int get_mmc_num(void)
1415{
1416 return cur_dev_num;
1417}
1418
e9550449
CLC
1419void mmc_set_preinit(struct mmc *mmc, int preinit)
1420{
1421 mmc->preinit = preinit;
1422}
1423
1424static void do_preinit(void)
1425{
1426 struct mmc *m;
1427 struct list_head *entry;
1428
1429 list_for_each(entry, &mmc_devices) {
1430 m = list_entry(entry, struct mmc, link);
1431
1432 if (m->preinit)
1433 mmc_start_init(m);
1434 }
1435}
1436
1437
272cc70b
AF
1438int mmc_initialize(bd_t *bis)
1439{
1440 INIT_LIST_HEAD (&mmc_devices);
1441 cur_dev_num = 0;
1442
1443 if (board_mmc_init(bis) < 0)
1444 cpu_mmc_init(bis);
1445
bb0dc108 1446#ifndef CONFIG_SPL_BUILD
272cc70b 1447 print_mmc_devices(',');
bb0dc108 1448#endif
272cc70b 1449
e9550449 1450 do_preinit();
272cc70b
AF
1451 return 0;
1452}
3690d6d6
A
1453
1454#ifdef CONFIG_SUPPORT_EMMC_BOOT
1455/*
1456 * This function changes the size of boot partition and the size of rpmb
1457 * partition present on EMMC devices.
1458 *
1459 * Input Parameters:
1460 * struct *mmc: pointer for the mmc device strcuture
1461 * bootsize: size of boot partition
1462 * rpmbsize: size of rpmb partition
1463 *
1464 * Returns 0 on success.
1465 */
1466
1467int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1468 unsigned long rpmbsize)
1469{
1470 int err;
1471 struct mmc_cmd cmd;
1472
1473 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1474 cmd.cmdidx = MMC_CMD_RES_MAN;
1475 cmd.resp_type = MMC_RSP_R1b;
1476 cmd.cmdarg = MMC_CMD62_ARG1;
1477
1478 err = mmc_send_cmd(mmc, &cmd, NULL);
1479 if (err) {
1480 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1481 return err;
1482 }
1483
1484 /* Boot partition changing mode */
1485 cmd.cmdidx = MMC_CMD_RES_MAN;
1486 cmd.resp_type = MMC_RSP_R1b;
1487 cmd.cmdarg = MMC_CMD62_ARG2;
1488
1489 err = mmc_send_cmd(mmc, &cmd, NULL);
1490 if (err) {
1491 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1492 return err;
1493 }
1494 /* boot partition size is multiple of 128KB */
1495 bootsize = (bootsize * 1024) / 128;
1496
1497 /* Arg: boot partition size */
1498 cmd.cmdidx = MMC_CMD_RES_MAN;
1499 cmd.resp_type = MMC_RSP_R1b;
1500 cmd.cmdarg = bootsize;
1501
1502 err = mmc_send_cmd(mmc, &cmd, NULL);
1503 if (err) {
1504 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1505 return err;
1506 }
1507 /* RPMB partition size is multiple of 128KB */
1508 rpmbsize = (rpmbsize * 1024) / 128;
1509 /* Arg: RPMB partition size */
1510 cmd.cmdidx = MMC_CMD_RES_MAN;
1511 cmd.resp_type = MMC_RSP_R1b;
1512 cmd.cmdarg = rpmbsize;
1513
1514 err = mmc_send_cmd(mmc, &cmd, NULL);
1515 if (err) {
1516 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1517 return err;
1518 }
1519 return 0;
1520}
1521
5a99b9de
TR
1522/*
1523 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1524 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1525 * and BOOT_MODE.
1526 *
1527 * Returns 0 on success.
1528 */
1529int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1530{
1531 int err;
1532
1533 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1534 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1535 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1536 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1537
1538 if (err)
1539 return err;
1540 return 0;
1541}
1542
792970b0
TR
1543/*
1544 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1545 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1546 * PARTITION_ACCESS.
1547 *
1548 * Returns 0 on success.
1549 */
1550int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1551{
1552 int err;
1553
1554 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1555 EXT_CSD_BOOT_ACK(ack) |
1556 EXT_CSD_BOOT_PART_NUM(part_num) |
1557 EXT_CSD_PARTITION_ACCESS(access));
1558
1559 if (err)
1560 return err;
1561 return 0;
1562}
33ace362
TR
1563
1564/*
1565 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1566 * for enable. Note that this is a write-once field for non-zero values.
1567 *
1568 * Returns 0 on success.
1569 */
1570int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1571{
1572 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1573 enable);
1574}
3690d6d6 1575#endif