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* gdb.base/fileio.c: Include unistd.h as required for lseek(2).
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
379832de
HPN		 12004-12-08 Hans-Peter Nilsson <hp@axis.com>
2
3 * configure: Regenerate for ../common/aclocal.m4 update.
4
cd62154c
AC		 52004-09-24 Monika Chaddha <monika@acmet.com>
6
7 Committed by Andrew Cagney.
8 * m16.igen (CMP, CMPI): Fix assembler.
9
e5da76ec
CD		 102004-08-18 Chris Demetriou <cgd@broadcom.com>
11
12 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
13 * configure: Regenerate.
14
139181c8
CD		 152004-06-25 Chris Demetriou <cgd@broadcom.com>
16
17 * configure.in (sim_m16_machine): Include mipsIII.
18 * configure: Regenerate.
19
1a27f959
CD		 202004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
21
22 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
23 from COP0_BADVADDR.
24 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
25
5dbb7b5a
CD		 262004-04-10 Chris Demetriou <cgd@broadcom.com>
27
28 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
29
14234056
CD		 302004-04-09 Chris Demetriou <cgd@broadcom.com>
31
32 * mips.igen (check_fmt): Remove.
33 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
34 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
35 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
36 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
37 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
38 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
39 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
40 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
41 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
42 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
43
c6f9085c
CD		 442004-04-09 Chris Demetriou <cgd@broadcom.com>
45
46 * sb1.igen (check_sbx): New function.
47 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
48
11d66e66 492004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 50 Richard Sandiford <rsandifo@redhat.com>
51
52 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
53 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
54 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
55 separate implementations for mipsIV and mipsV. Use new macros to
56 determine whether the restrictions apply.
57
b3208fb8
CD		 582004-01-19 Chris Demetriou <cgd@broadcom.com>
59
60 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
61 (check_mult_hilo): Improve comments.
62 (check_div_hilo): Likewise. Also, fork off a new version
63 to handle mips32/mips64 (since there are no hazards to check
64 in MIPS32/MIPS64).
65
9a1d84fb
CD		 662003-06-17 Richard Sandiford <rsandifo@redhat.com>
67
68 * mips.igen (do_dmultx): Fix check for negative operands.
69
ae451ac6
ILT		 702003-05-16 Ian Lance Taylor <ian@airs.com>
71
72 * Makefile.in (SHELL): Make sure this is defined.
73 (various): Use $(SHELL) whenever we invoke move-if-change.
74
dd69d292
CD		 752003-05-03 Chris Demetriou <cgd@broadcom.com>
76
77 * cp1.c: Tweak attribution slightly.
78 * cp1.h: Likewise.
79 * mdmx.c: Likewise.
80 * mdmx.igen: Likewise.
81 * mips3d.igen: Likewise.
82 * sb1.igen: Likewise.
83
bcd0068e
CD		 842003-04-15 Richard Sandiford <rsandifo@redhat.com>
85
86 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
87 unsigned operands.
88
6b4a8935
AC		 892003-02-27 Andrew Cagney <cagney@redhat.com>
90
601da316
AC		 91 * interp.c (sim_open): Rename _bfd to bfd.
92 (sim_create_inferior): Ditto.
6b4a8935 93
d29e330f
CD		 942003-01-14 Chris Demetriou <cgd@broadcom.com>
95
96 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
97
a2353a08
CD		 982003-01-14 Chris Demetriou <cgd@broadcom.com>
99
100 * mips.igen (EI, DI): Remove.
101
80551777
CD		 1022003-01-05 Richard Sandiford <rsandifo@redhat.com>
103
104 * Makefile.in (tmp-run-multi): Fix mips16 filter.
105
4c54fc26
CD		 1062003-01-04 Richard Sandiford <rsandifo@redhat.com>
107 Andrew Cagney <ac131313@redhat.com>
108 Gavin Romig-Koch <gavin@redhat.com>
109 Graydon Hoare <graydon@redhat.com>
110 Aldy Hernandez <aldyh@redhat.com>
111 Dave Brolley <brolley@redhat.com>
112 Chris Demetriou <cgd@broadcom.com>
113
114 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
115 (sim_mach_default): New variable.
116 (mips64vr-*-*, mips64vrel-*-*): New configurations.
117 Add a new simulator generator, MULTI.
118 * configure: Regenerate.
119 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
120 (multi-run.o): New dependency.
121 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
122 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
123 (tmp-multi): Combine them.
124 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
125 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
126 (distclean-extra): New rule.
127 * sim-main.h: Include bfd.h.
128 (MIPS_MACH): New macro.
129 * mips.igen (vr4120, vr5400, vr5500): New models.
130 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
131 * vr.igen: Replace with new version.
132
e6c674b8
CD		 1332003-01-04 Chris Demetriou <cgd@broadcom.com>
134
135 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
136 * configure: Regenerate.
137
28f50ac8
CD		 1382002-12-31 Chris Demetriou <cgd@broadcom.com>
139
140 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
141 * mips.igen: Remove all invocations of check_branch_bug and
142 mark_branch_bug.
143
5071ffe6
CD		 1442002-12-16 Chris Demetriou <cgd@broadcom.com>
145
146 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
147
06e7837e
CD		 1482002-07-30 Chris Demetriou <cgd@broadcom.com>
149
150 * mips.igen (do_load_double, do_store_double): New functions.
151 (LDC1, SDC1): Rename to...
152 (LDC1b, SDC1b): respectively.
153 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
154
2265c243
MS		 1552002-07-29 Michael Snyder <msnyder@redhat.com>
156
157 * cp1.c (fp_recip2): Modify initialization expression so that
158 GCC will recognize it as constant.
159
a2f8b4f3
CD		 1602002-06-18 Chris Demetriou <cgd@broadcom.com>
161
162 * mdmx.c (SD_): Delete.
163 (Unpredictable): Re-define, for now, to directly invoke
164 unpredictable_action().
165 (mdmx_acc_op): Fix error in .ob immediate handling.
166
b4b6c939
AC		 1672002-06-18 Andrew Cagney <cagney@redhat.com>
168
169 * interp.c (sim_firmware_command): Initialize `address'.
170
c8cca39f
AC		 1712002-06-16 Andrew Cagney <ac131313@redhat.com>
172
173 * configure: Regenerated to track ../common/aclocal.m4 changes.
174
e7e81181
CD		 1752002-06-14 Chris Demetriou <cgd@broadcom.com>
176 Ed Satterthwaite <ehs@broadcom.com>
177
178 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
179 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
180 * mips.igen: Include mips3d.igen.
181 (mips3d): New model name for MIPS-3D ASE instructions.
182 (CVT.W.fmt): Don't use this instruction for word (source) format
183 instructions.
184 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
185 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
186 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
187 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
188 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
189 (RSquareRoot1, RSquareRoot2): New macros.
190 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
191 (fp_rsqrt2): New functions.
192 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
193 * configure: Regenerate.
194
3a2b820e 1952002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 196 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 197
198 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
199 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
200 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
201 (convert): Note that this function is not used for paired-single
202 format conversions.
203 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
204 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
205 (check_fmt_p): Enable paired-single support.
206 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
207 (PUU.PS): New instructions.
208 (CVT.S.fmt): Don't use this instruction for paired-single format
209 destinations.
210 * sim-main.h (FP_formats): New value 'fmt_ps.'
211 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
212 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
213
d18ea9c2
CD		 2142002-06-12 Chris Demetriou <cgd@broadcom.com>
215
216 * mips.igen: Fix formatting of function calls in
217 many FP operations.
218
95fd5cee
CD		 2192002-06-12 Chris Demetriou <cgd@broadcom.com>
220
221 * mips.igen (MOVN, MOVZ): Trace result.
222 (TNEI): Print "tnei" as the opcode name in traces.
223 (CEIL.W): Add disassembly string for traces.
224 (RSQRT.fmt): Make location of disassembly string consistent
225 with other instructions.
226
4f0d55ae
CD		 2272002-06-12 Chris Demetriou <cgd@broadcom.com>
228
229 * mips.igen (X): Delete unused function.
230
3c25f8c7
AC		 2312002-06-08 Andrew Cagney <cagney@redhat.com>
232
233 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
234
f3c08b7e
CD		 2352002-06-07 Chris Demetriou <cgd@broadcom.com>
236 Ed Satterthwaite <ehs@broadcom.com>
237
238 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
239 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
240 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
241 (fp_nmsub): New prototypes.
242 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
243 (NegMultiplySub): New defines.
244 * mips.igen (RSQRT.fmt): Use RSquareRoot().
245 (MADD.D, MADD.S): Replace with...
246 (MADD.fmt): New instruction.
247 (MSUB.D, MSUB.S): Replace with...
248 (MSUB.fmt): New instruction.
249 (NMADD.D, NMADD.S): Replace with...
250 (NMADD.fmt): New instruction.
251 (NMSUB.D, MSUB.S): Replace with...
252 (NMSUB.fmt): New instruction.
253
52714ff9
CD		 2542002-06-07 Chris Demetriou <cgd@broadcom.com>
255 Ed Satterthwaite <ehs@broadcom.com>
256
257 * cp1.c: Fix more comment spelling and formatting.
258 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
259 (denorm_mode): New function.
260 (fpu_unary, fpu_binary): Round results after operation, collect
261 status from rounding operations, and update the FCSR.
262 (convert): Collect status from integer conversions and rounding
263 operations, and update the FCSR. Adjust NaN values that result
264 from conversions. Convert to use sim_io_eprintf rather than
265 fprintf, and remove some debugging code.
266 * cp1.h (fenr_FS): New define.
267
577d8c4b
CD		 2682002-06-07 Chris Demetriou <cgd@broadcom.com>
269
270 * cp1.c (convert): Remove unusable debugging code, and move MIPS
271 rounding mode to sim FP rounding mode flag conversion code into...
272 (rounding_mode): New function.
273
196496ed
CD		 2742002-06-07 Chris Demetriou <cgd@broadcom.com>
275
276 * cp1.c: Clean up formatting of a few comments.
277 (value_fpr): Reformat switch statement.
278
cfe9ea23
CD		 2792002-06-06 Chris Demetriou <cgd@broadcom.com>
280 Ed Satterthwaite <ehs@broadcom.com>
281
282 * cp1.h: New file.
283 * sim-main.h: Include cp1.h.
284 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
285 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
286 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
287 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
288 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
289 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
290 * cp1.c: Don't include sim-fpu.h; already included by
291 sim-main.h. Clean up formatting of some comments.
292 (NaN, Equal, Less): Remove.
293 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
294 (fp_cmp): New functions.
295 * mips.igen (do_c_cond_fmt): Remove.
296 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
297 Compare. Add result tracing.
298 (CxC1): Remove, replace with...
299 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
300 (DMxC1): Remove, replace with...
301 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
302 (MxC1): Remove, replace with...
303 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
304
ee7254b0
CD		 3052002-06-04 Chris Demetriou <cgd@broadcom.com>
306
307 * sim-main.h (FGRIDX): Remove, replace all uses with...
308 (FGR_BASE): New macro.
309 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
310 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
311 (NR_FGR, FGR): Likewise.
312 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
313 * mips.igen: Likewise.
314
d3eb724f
CD		 3152002-06-04 Chris Demetriou <cgd@broadcom.com>
316
317 * cp1.c: Add an FSF Copyright notice to this file.
318
ba46ddd0
CD		 3192002-06-04 Chris Demetriou <cgd@broadcom.com>
320 Ed Satterthwaite <ehs@broadcom.com>
321
322 * cp1.c (Infinity): Remove.
323 * sim-main.h (Infinity): Likewise.
324
325 * cp1.c (fp_unary, fp_binary): New functions.
326 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
327 (fp_sqrt): New functions, implemented in terms of the above.
328 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
329 (Recip, SquareRoot): Remove (replaced by functions above).
330 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
331 (fp_recip, fp_sqrt): New prototypes.
332 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
333 (Recip, SquareRoot): Replace prototypes with #defines which
334 invoke the functions above.
335
18d8a52d
CD		 3362002-06-03 Chris Demetriou <cgd@broadcom.com>
337
338 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
339 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
340 file, remove PARAMS from prototypes.
341 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
342 simulator state arguments.
343 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
344 pass simulator state arguments.
345 * cp1.c (SD): Redefine as CPU_STATE(cpu).
346 (store_fpr, convert): Remove 'sd' argument.
347 (value_fpr): Likewise. Convert to use 'SD' instead.
348
0f154cbd
CD		 3492002-06-03 Chris Demetriou <cgd@broadcom.com>
350
351 * cp1.c (Min, Max): Remove #if 0'd functions.
352 * sim-main.h (Min, Max): Remove.
353
e80fc152
CD		 3542002-06-03 Chris Demetriou <cgd@broadcom.com>
355
356 * cp1.c: fix formatting of switch case and default labels.
357 * interp.c: Likewise.
358 * sim-main.c: Likewise.
359
bad673a9
CD		 3602002-06-03 Chris Demetriou <cgd@broadcom.com>
361
362 * cp1.c: Clean up comments which describe FP formats.
363 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
364
7cbea089
CD		 3652002-06-03 Chris Demetriou <cgd@broadcom.com>
366 Ed Satterthwaite <ehs@broadcom.com>
367
368 * configure.in (mipsisa64sb1*-*-*): New target for supporting
369 Broadcom SiByte SB-1 processor configurations.
370 * configure: Regenerate.
371 * sb1.igen: New file.
372 * mips.igen: Include sb1.igen.
373 (sb1): New model.
374 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
375 * mdmx.igen: Add "sb1" model to all appropriate functions and
376 instructions.
377 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
378 (ob_func, ob_acc): Reference the above.
379 (qh_acc): Adjust to keep the same size as ob_acc.
380 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
381 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
382
909daa82
CD		 3832002-06-03 Chris Demetriou <cgd@broadcom.com>
384
385 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
386
f4f1b9f1
CD		 3872002-06-02 Chris Demetriou <cgd@broadcom.com>
388 Ed Satterthwaite <ehs@broadcom.com>
389
390 * mips.igen (mdmx): New (pseudo-)model.
391 * mdmx.c, mdmx.igen: New files.
392 * Makefile.in (SIM_OBJS): Add mdmx.o.
393 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
394 New typedefs.
395 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
396 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
397 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
398 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
399 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
400 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
401 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
402 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
403 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
404 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
405 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
406 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
407 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
408 (qh_fmtsel): New macros.
409 (_sim_cpu): New member "acc".
410 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
411 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
412
5accf1ff
CD		 4132002-05-01 Chris Demetriou <cgd@broadcom.com>
414
415 * interp.c: Use 'deprecated' rather than 'depreciated.'
416 * sim-main.h: Likewise.
417
402586aa
CD		 4182002-05-01 Chris Demetriou <cgd@broadcom.com>
419
420 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
421 which wouldn't compile anyway.
422 * sim-main.h (unpredictable_action): New function prototype.
423 (Unpredictable): Define to call igen function unpredictable().
424 (NotWordValue): New macro to call igen function not_word_value().
425 (UndefinedResult): Remove.
426 * interp.c (undefined_result): Remove.
427 (unpredictable_action): New function.
428 * mips.igen (not_word_value, unpredictable): New functions.
429 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
430 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
431 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
432 NotWordValue() to check for unpredictable inputs, then
433 Unpredictable() to handle them.
434
c9b9995a
CD		 4352002-02-24 Chris Demetriou <cgd@broadcom.com>
436
437 * mips.igen: Fix formatting of calls to Unpredictable().
438
e1015982
AC		 4392002-04-20 Andrew Cagney <ac131313@redhat.com>
440
441 * interp.c (sim_open): Revert previous change.
442
b882a66b
AO		 4432002-04-18 Alexandre Oliva <aoliva@redhat.com>
444
445 * interp.c (sim_open): Disable chunk of code that wrote code in
446 vector table entries.
447
c429b7dd
CD		 4482002-03-19 Chris Demetriou <cgd@broadcom.com>
449
450 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
451 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
452 unused definitions.
453
37d146fa
CD		 4542002-03-19 Chris Demetriou <cgd@broadcom.com>
455
456 * cp1.c: Fix many formatting issues.
457
07892c0b
CD		 4582002-03-19 Chris G. Demetriou <cgd@broadcom.com>
459
460 * cp1.c (fpu_format_name): New function to replace...
461 (DOFMT): This. Delete, and update all callers.
462 (fpu_rounding_mode_name): New function to replace...
463 (RMMODE): This. Delete, and update all callers.
464
487f79b7
CD		 4652002-03-19 Chris G. Demetriou <cgd@broadcom.com>
466
467 * interp.c: Move FPU support routines from here to...
468 * cp1.c: Here. New file.
469 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
470 (cp1.o): New target.
471
1e799e28
CD		 4722002-03-12 Chris Demetriou <cgd@broadcom.com>
473
474 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
475 * mips.igen (mips32, mips64): New models, add to all instructions
476 and functions as appropriate.
477 (loadstore_ea, check_u64): New variant for model mips64.
478 (check_fmt_p): New variant for models mipsV and mips64, remove
479 mipsV model marking fro other variant.
480 (SLL) Rename to...
481 (SLLa) this.
482 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
483 for mips32 and mips64.
484 (DCLO, DCLZ): New instructions for mips64.
485
82f728db
CD		 4862002-03-07 Chris Demetriou <cgd@broadcom.com>
487
488 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
489 immediate or code as a hex value with the "%#lx" format.
490 (ANDI): Likewise, and fix printed instruction name.
491
b96e7ef1
CD		 4922002-03-05 Chris Demetriou <cgd@broadcom.com>
493
494 * sim-main.h (UndefinedResult, Unpredictable): New macros
495 which currently do nothing.
496
d35d4f70
CD		 4972002-03-05 Chris Demetriou <cgd@broadcom.com>
498
499 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
500 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
501 (status_CU3): New definitions.
502
503 * sim-main.h (ExceptionCause): Add new values for MIPS32
504 and MIPS64: MDMX, MCheck, CacheErr. Update comments
505 for DebugBreakPoint and NMIReset to note their status in
506 MIPS32 and MIPS64.
507 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
508 (SignalExceptionCacheErr): New exception macros.
509
3ad6f714
CD		 5102002-03-05 Chris Demetriou <cgd@broadcom.com>
511
512 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
513 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
514 is always enabled.
515 (SignalExceptionCoProcessorUnusable): Take as argument the
516 unusable coprocessor number.
517
86b77b47
CD		 5182002-03-05 Chris Demetriou <cgd@broadcom.com>
519
520 * mips.igen: Fix formatting of all SignalException calls.
521
97a88e93 5222002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 523
524 * sim-main.h (SIGNEXTEND): Remove.
525
97a88e93 5262002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 527
528 * mips.igen: Remove gencode comment from top of file, fix
529 spelling in another comment.
530
97a88e93 5312002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 532
533 * mips.igen (check_fmt, check_fmt_p): New functions to check
534 whether specific floating point formats are usable.
535 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
536 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
537 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
538 Use the new functions.
539 (do_c_cond_fmt): Remove format checks...
540 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
541
97a88e93 5422002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 543
544 * mips.igen: Fix formatting of check_fpu calls.
545
41774c9d
CD		 5462002-03-03 Chris Demetriou <cgd@broadcom.com>
547
548 * mips.igen (FLOOR.L.fmt): Store correct destination register.
549
4a0bd876
CD		 5502002-03-03 Chris Demetriou <cgd@broadcom.com>
551
552 * mips.igen: Remove whitespace at end of lines.
553
09297648
CD		 5542002-03-02 Chris Demetriou <cgd@broadcom.com>
555
556 * mips.igen (loadstore_ea): New function to do effective
557 address calculations.
558 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
559 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
560 CACHE): Use loadstore_ea to do effective address computations.
561
043b7057
CD		 5622002-03-02 Chris Demetriou <cgd@broadcom.com>
563
564 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
565 * mips.igen (LL, CxC1, MxC1): Likewise.
566
c1e8ada4
CD		 5672002-03-02 Chris Demetriou <cgd@broadcom.com>
568
569 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
570 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
571 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
572 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
573 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
574 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
575 Don't split opcode fields by hand, use the opcode field values
576 provided by igen.
577
3e1dca16
CD		 5782002-03-01 Chris Demetriou <cgd@broadcom.com>
579
580 * mips.igen (do_divu): Fix spacing.
581
582 * mips.igen (do_dsllv): Move to be right before DSLLV,
583 to match the rest of the do_<shift> functions.
584
fff8d27d
CD		 5852002-03-01 Chris Demetriou <cgd@broadcom.com>
586
587 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
588 DSRL32, do_dsrlv): Trace inputs and results.
589
0d3e762b
CD		 5902002-03-01 Chris Demetriou <cgd@broadcom.com>
591
592 * mips.igen (CACHE): Provide instruction-printing string.
593
594 * interp.c (signal_exception): Comment tokens after #endif.
595
eb5fcf93
CD		 5962002-02-28 Chris Demetriou <cgd@broadcom.com>
597
598 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
599 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
600 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
601 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
602 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
603 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
604 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
605 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
606
bb22bd7d
CD		 6072002-02-28 Chris Demetriou <cgd@broadcom.com>
608
609 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
610 instruction-printing string.
611 (LWU): Use '64' as the filter flag.
612
91a177cf
CD		 6132002-02-28 Chris Demetriou <cgd@broadcom.com>
614
615 * mips.igen (SDXC1): Fix instruction-printing string.
616
387f484a
CD		 6172002-02-28 Chris Demetriou <cgd@broadcom.com>
618
619 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
620 filter flags "32,f".
621
3d81f391
CD		 6222002-02-27 Chris Demetriou <cgd@broadcom.com>
623
624 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
625 as the filter flag.
626
af5107af
CD		 6272002-02-27 Chris Demetriou <cgd@broadcom.com>
628
629 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
630 add a comma) so that it more closely match the MIPS ISA
631 documentation opcode partitioning.
632 (PREF): Put useful names on opcode fields, and include
633 instruction-printing string.
634
ca971540
CD		 6352002-02-27 Chris Demetriou <cgd@broadcom.com>
636
637 * mips.igen (check_u64): New function which in the future will
638 check whether 64-bit instructions are usable and signal an
639 exception if not. Currently a no-op.
640 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
641 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
642 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
643 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
644
645 * mips.igen (check_fpu): New function which in the future will
646 check whether FPU instructions are usable and signal an exception
647 if not. Currently a no-op.
648 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
649 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
650 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
651 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
652 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
653 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
654 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
655 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
656
1c47a468
CD		 6572002-02-27 Chris Demetriou <cgd@broadcom.com>
658
659 * mips.igen (do_load_left, do_load_right): Move to be immediately
660 following do_load.
661 (do_store_left, do_store_right): Move to be immediately following
662 do_store.
663
603a98e7
CD		 6642002-02-27 Chris Demetriou <cgd@broadcom.com>
665
666 * mips.igen (mipsV): New model name. Also, add it to
667 all instructions and functions where it is appropriate.
668
c5d00cc7
CD		 6692002-02-18 Chris Demetriou <cgd@broadcom.com>
670
671 * mips.igen: For all functions and instructions, list model
672 names that support that instruction one per line.
673
074e9cb8
CD		 6742002-02-11 Chris Demetriou <cgd@broadcom.com>
675
676 * mips.igen: Add some additional comments about supported
677 models, and about which instructions go where.
678 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
679 order as is used in the rest of the file.
680
9805e229
CD		 6812002-02-11 Chris Demetriou <cgd@broadcom.com>
682
683 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
684 indicating that ALU32_END or ALU64_END are there to check
685 for overflow.
686 (DADD): Likewise, but also remove previous comment about
687 overflow checking.
688
f701dad2
CD		 6892002-02-10 Chris Demetriou <cgd@broadcom.com>
690
691 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
692 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
693 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
694 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
695 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
696 fields (i.e., add and move commas) so that they more closely
697 match the MIPS ISA documentation opcode partitioning.
698
6992002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 700
701 * mips.igen (ADDI): Print immediate value.
702 (BREAK): Print code.
703 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
704 (SLL): Print "nop" specially, and don't run the code
705 that does the shift for the "nop" case.
706
9e52972e
FF		 7072001-11-17 Fred Fish <fnf@redhat.com>
708
709 * sim-main.h (float_operation): Move enum declaration outside
710 of _sim_cpu struct declaration.
711
c0efbca4
JB		 7122001-04-12 Jim Blandy <jimb@redhat.com>
713
714 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
715 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
716 set of the FCSR.
717 * sim-main.h (COCIDX): Remove definition; this isn't supported by
718 PENDING_FILL, and you can get the intended effect gracefully by
719 calling PENDING_SCHED directly.
720
fb891446
BE		 7212001-02-23 Ben Elliston <bje@redhat.com>
722
723 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
724 already defined elsewhere.
725
8030f857
BE		 7262001-02-19 Ben Elliston <bje@redhat.com>
727
728 * sim-main.h (sim_monitor): Return an int.
729 * interp.c (sim_monitor): Add return values.
730 (signal_exception): Handle error conditions from sim_monitor.
731
56b48a7a
CD		 7322001-02-08 Ben Elliston <bje@redhat.com>
733
734 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
735 (store_memory): Likewise, pass cia to sim_core_write*.
736
d3ee60d9
FCE		 7372000-10-19 Frank Ch. Eigler <fche@redhat.com>
738
739 On advice from Chris G. Demetriou <cgd@sibyte.com>:
740 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
741
071da002
AC		 742Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
743
744 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
745 * Makefile.in: Don't delete *.igen when cleaning directory.
746
a28c02cd
AC		 747Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
748
749 * m16.igen (break): Call SignalException not sim_engine_halt.
750
80ee11fa
AC		 751Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
752
753 From Jason Eckhardt:
754 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
755
673388c0
AC		 756Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
757
758 * mips.igen (MxC1, DMxC1): Fix printf formatting.
759
4c0deff4
NC		 7602000-05-24 Michael Hayes <mhayes@cygnus.com>
761
762 * mips.igen (do_dmultx): Fix typo.
763
eb2d80b4
AC		 764Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
765
766 * configure: Regenerated to track ../common/aclocal.m4 changes.
767
dd37a34b
AC		 768Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
769
770 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
771
4c0deff4
NC		 7722000-04-12 Frank Ch. Eigler <fche@redhat.com>
773
774 * sim-main.h (GPR_CLEAR): Define macro.
775
e30db738
AC		 776Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
777
778 * interp.c (decode_coproc): Output long using %lx and not %s.
779
cb7450ea
FCE		 7802000-03-21 Frank Ch. Eigler <fche@redhat.com>
781
782 * interp.c (sim_open): Sort & extend dummy memory regions for
783 --board=jmr3904 for eCos.
784
a3027dd7
FCE		 7852000-03-02 Frank Ch. Eigler <fche@redhat.com>
786
787 * configure: Regenerated.
788
789Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
790
791 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
792 calls, conditional on the simulator being in verbose mode.
793
dfcd3bfb
JM		 794Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
795
796 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
797 cache don't get ReservedInstruction traps.
798
c2d11a7d
JM		 7991999-11-29 Mark Salter <msalter@cygnus.com>
800
801 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
802 to clear status bits in sdisr register. This is how the hardware works.
803
804 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
805 being used by cygmon.
806
4ce44c66
JM		 8071999-11-11 Andrew Haley <aph@cygnus.com>
808
809 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
810 instructions.
811
cff3e48b
JM		 812Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
813
814 * mips.igen (MULT): Correct previous mis-applied patch.
815
d4f3574e
SS		 816Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
817
818 * mips.igen (delayslot32): Handle sequence like
819 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
820 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
821 (MULT): Actually pass the third register...
822
8231999-09-03 Mark Salter <msalter@cygnus.com>
824
825 * interp.c (sim_open): Added more memory aliases for additional
826 hardware being touched by cygmon on jmr3904 board.
827
828Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
829
830 * configure: Regenerated to track ../common/aclocal.m4 changes.
831
a0b3c4fd
JM		 832Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
833
834 * interp.c (sim_store_register): Handle case where client - GDB -
835 specifies that a 4 byte register is 8 bytes in size.
836 (sim_fetch_register): Ditto.
837
adf40b2e
JM		 8381999-07-14 Frank Ch. Eigler <fche@cygnus.com>
839
840 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
841 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
842 (idt_monitor_base): Base address for IDT monitor traps.
843 (pmon_monitor_base): Ditto for PMON.
844 (lsipmon_monitor_base): Ditto for LSI PMON.
845 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
846 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
847 (sim_firmware_command): New function.
848 (mips_option_handler): Call it for OPTION_FIRMWARE.
849 (sim_open): Allocate memory for idt_monitor region. If "--board"
850 option was given, add no monitor by default. Add BREAK hooks only if
851 monitors are also there.
852
43e526b9
JM		 853Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
854
855 * interp.c (sim_monitor): Flush output before reading input.
856
857Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
858
859 * tconfig.in (SIM_HANDLES_LMA): Always define.
860
861Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
862
863 From Mark Salter <msalter@cygnus.com>:
864 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
865 (sim_open): Add setup for BSP board.
866
9846de1b
JM		 867Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
868
869 * mips.igen (MULT, MULTU): Add syntax for two operand version.
870 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
871 them as unimplemented.
872
cd0fc7c3
SS		 8731999-05-08 Felix Lee <flee@cygnus.com>
874
875 * configure: Regenerated to track ../common/aclocal.m4 changes.
876
7a292a7a
SS		 8771999-04-21 Frank Ch. Eigler <fche@cygnus.com>
878
879 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
880
881Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
882
883 * configure.in: Any mips64vr5*-*-* target should have
884 -DTARGET_ENABLE_FR=1.
885 (default_endian): Any mips64vr*el-*-* target should default to
886 LITTLE_ENDIAN.
887 * configure: Re-generate.
888
8891999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
890
891 * mips.igen (ldl): Extend from _16_, not 32.
892
893Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
894
895 * interp.c (sim_store_register): Force registers written to by GDB
896 into an un-interpreted state.
897
c906108c
SS		 8981999-02-05 Frank Ch. Eigler <fche@cygnus.com>
899
900 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
901 CPU, start periodic background I/O polls.
902 (tx3904sio_poll): New function: periodic I/O poller.
903
9041998-12-30 Frank Ch. Eigler <fche@cygnus.com>
905
906 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
907
908Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
909
910 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
911 case statement.
912
9131998-12-29 Frank Ch. Eigler <fche@cygnus.com>
914
915 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
916 (load_word): Call SIM_CORE_SIGNAL hook on error.
917 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
918 starting. For exception dispatching, pass PC instead of NULL_CIA.
919 (decode_coproc): Use COP0_BADVADDR to store faulting address.
920 * sim-main.h (COP0_BADVADDR): Define.
921 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
922 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
923 (_sim_cpu): Add exc_* fields to store register value snapshots.
924 * mips.igen (*): Replace memory-related SignalException* calls
925 with references to SIM_CORE_SIGNAL hook.
926
927 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
928 fix.
929 * sim-main.c (*): Minor warning cleanups.
930
9311998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
932
933 * m16.igen (DADDIU5): Correct type-o.
934
935Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
936
937 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
938 variables.
939
940Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
941
942 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
943 to include path.
944 (interp.o): Add dependency on itable.h
945 (oengine.c, gencode): Delete remaining references.
946 (BUILT_SRC_FROM_GEN): Clean up.
947
9481998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
949
950 * vr4run.c: New.
951 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
952 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
953 tmp-run-hack) : New.
954 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
955 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
956 Drop the "64" qualifier to get the HACK generator working.
957 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
958 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
959 qualifier to get the hack generator working.
960 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
961 (DSLL): Use do_dsll.
962 (DSLLV): Use do_dsllv.
963 (DSRA): Use do_dsra.
964 (DSRL): Use do_dsrl.
965 (DSRLV): Use do_dsrlv.
966 (BC1): Move *vr4100 to get the HACK generator working.
967 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
968 get the HACK generator working.
969 (MACC) Rename to get the HACK generator working.
970 (DMACC,MACCS,DMACCS): Add the 64.
971
9721998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
973
974 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
975 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
976
9771998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
978
979 * mips/interp.c (DEBUG): Cleanups.
980
9811998-12-10 Frank Ch. Eigler <fche@cygnus.com>
982
983 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
984 (tx3904sio_tickle): fflush after a stdout character output.
985
9861998-12-03 Frank Ch. Eigler <fche@cygnus.com>
987
988 * interp.c (sim_close): Uninstall modules.
989
990Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
991
992 * sim-main.h, interp.c (sim_monitor): Change to global
993 function.
994
995Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
996
997 * configure.in (vr4100): Only include vr4100 instructions in
998 simulator.
999 * configure: Re-generate.
1000 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1001
1002Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1003
1004 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1005 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1006 true alternative.
1007
1008 * configure.in (sim_default_gen, sim_use_gen): Replace with
1009 sim_gen.
1010 (--enable-sim-igen): Delete config option. Always using IGEN.
1011 * configure: Re-generate.
1012
1013 * Makefile.in (gencode): Kill, kill, kill.
1014 * gencode.c: Ditto.
1015
1016Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1017
1018 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1019 bit mips16 igen simulator.
1020 * configure: Re-generate.
1021
1022 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1023 as part of vr4100 ISA.
1024 * vr.igen: Mark all instructions as 64 bit only.
1025
1026Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1027
1028 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1029 Pacify GCC.
1030
1031Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1034 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1035 * configure: Re-generate.
1036
1037 * m16.igen (BREAK): Define breakpoint instruction.
1038 (JALX32): Mark instruction as mips16 and not r3900.
1039 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1040
1041 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1042
1043Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1044
1045 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1046 insn as a debug breakpoint.
1047
1048 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1049 pending.slot_size.
1050 (PENDING_SCHED): Clean up trace statement.
1051 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1052 (PENDING_FILL): Delay write by only one cycle.
1053 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1054
1055 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1056 of pending writes.
1057 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1058 32 & 64.
1059 (pending_tick): Move incrementing of index to FOR statement.
1060 (pending_tick): Only update PENDING_OUT after a write has occured.
1061
1062 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1063 build simulator.
1064 * configure: Re-generate.
1065
1066 * interp.c (sim_engine_run OLD): Delete explicit call to
1067 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1068
1069Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1070
1071 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1072 interrupt level number to match changed SignalExceptionInterrupt
1073 macro.
1074
1075Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1076
1077 * interp.c: #include "itable.h" if WITH_IGEN.
1078 (get_insn_name): New function.
1079 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1080 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1081
1082Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1083
1084 * configure: Rebuilt to inhale new common/aclocal.m4.
1085
1086Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1087
1088 * dv-tx3904sio.c: Include sim-assert.h.
1089
1090Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1091
1092 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1093 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1094 Reorganize target-specific sim-hardware checks.
1095 * configure: rebuilt.
1096 * interp.c (sim_open): For tx39 target boards, set
1097 OPERATING_ENVIRONMENT, add tx3904sio devices.
1098 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1099 ROM executables. Install dv-sockser into sim-modules list.
1100
1101 * dv-tx3904irc.c: Compiler warning clean-up.
1102 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1103 frequent hw-trace messages.
1104
1105Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1106
1107 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1108
1109Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1110
1111 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1112
1113 * vr.igen: New file.
1114 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1115 * mips.igen: Define vr4100 model. Include vr.igen.
1116Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1117
1118 * mips.igen (check_mf_hilo): Correct check.
1119
1120Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1121
1122 * sim-main.h (interrupt_event): Add prototype.
1123
1124 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1125 register_ptr, register_value.
1126 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1127
1128 * sim-main.h (tracefh): Make extern.
1129
1130Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1131
1132 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1133 Reduce unnecessarily high timer event frequency.
1134 * dv-tx3904cpu.c: Ditto for interrupt event.
1135
1136Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1137
1138 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1139 to allay warnings.
1140 (interrupt_event): Made non-static.
1141
1142 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1143 interchange of configuration values for external vs. internal
1144 clock dividers.
1145
1146Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1147
1148 * mips.igen (BREAK): Moved code to here for
1149 simulator-reserved break instructions.
1150 * gencode.c (build_instruction): Ditto.
1151 * interp.c (signal_exception): Code moved from here. Non-
1152 reserved instructions now use exception vector, rather
1153 than halting sim.
1154 * sim-main.h: Moved magic constants to here.
1155
1156Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1157
1158 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1159 register upon non-zero interrupt event level, clear upon zero
1160 event value.
1161 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1162 by passing zero event value.
1163 (*_io_{read,write}_buffer): Endianness fixes.
1164 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1165 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1166
1167 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1168 serial I/O and timer module at base address 0xFFFF0000.
1169
1170Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1171
1172 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1173 and BigEndianCPU.
1174
1175Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1176
1177 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1178 parts.
1179 * configure: Update.
1180
1181Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1182
1183 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1184 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1185 * configure.in: Include tx3904tmr in hw_device list.
1186 * configure: Rebuilt.
1187 * interp.c (sim_open): Instantiate three timer instances.
1188 Fix address typo of tx3904irc instance.
1189
1190Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1191
1192 * interp.c (signal_exception): SystemCall exception now uses
1193 the exception vector.
1194
1195Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1196
1197 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1198 to allay warnings.
1199
1200Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1201
1202 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1203
1204Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1207
1208 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1209 sim-main.h. Declare a struct hw_descriptor instead of struct
1210 hw_device_descriptor.
1211
1212Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1213
1214 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1215 right bits and then re-align left hand bytes to correct byte
1216 lanes. Fix incorrect computation in do_store_left when loading
1217 bytes from second word.
1218
1219Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1220
1221 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1222 * interp.c (sim_open): Only create a device tree when HW is
1223 enabled.
1224
1225 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1226 * interp.c (signal_exception): Ditto.
1227
1228Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1229
1230 * gencode.c: Mark BEGEZALL as LIKELY.
1231
1232Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1233
1234 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1235 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1236
1237Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1238
1239 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1240 modules. Recognize TX39 target with "mips*tx39" pattern.
1241 * configure: Rebuilt.
1242 * sim-main.h (*): Added many macros defining bits in
1243 TX39 control registers.
1244 (SignalInterrupt): Send actual PC instead of NULL.
1245 (SignalNMIReset): New exception type.
1246 * interp.c (board): New variable for future use to identify
1247 a particular board being simulated.
1248 (mips_option_handler,mips_options): Added "--board" option.
1249 (interrupt_event): Send actual PC.
1250 (sim_open): Make memory layout conditional on board setting.
1251 (signal_exception): Initial implementation of hardware interrupt
1252 handling. Accept another break instruction variant for simulator
1253 exit.
1254 (decode_coproc): Implement RFE instruction for TX39.
1255 (mips.igen): Decode RFE instruction as such.
1256 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1257 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1258 bbegin to implement memory map.
1259 * dv-tx3904cpu.c: New file.
1260 * dv-tx3904irc.c: New file.
1261
1262Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1263
1264 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1265
1266Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1267
1268 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1269 with calls to check_div_hilo.
1270
1271Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1272
1273 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1274 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1275 Add special r3900 version of do_mult_hilo.
1276 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1277 with calls to check_mult_hilo.
1278 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1279 with calls to check_div_hilo.
1280
1281Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1282
1283 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1284 Document a replacement.
1285
1286Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1287
1288 * interp.c (sim_monitor): Make mon_printf work.
1289
1290Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1291
1292 * sim-main.h (INSN_NAME): New arg `cpu'.
1293
1294Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1295
1296 * configure: Regenerated to track ../common/aclocal.m4 changes.
1297
1298Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1299
1300 * configure: Regenerated to track ../common/aclocal.m4 changes.
1301 * config.in: Ditto.
1302
1303Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1304
1305 * acconfig.h: New file.
1306 * configure.in: Reverted change of Apr 24; use sinclude again.
1307
1308Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1309
1310 * configure: Regenerated to track ../common/aclocal.m4 changes.
1311 * config.in: Ditto.
1312
1313Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1314
1315 * configure.in: Don't call sinclude.
1316
1317Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1318
1319 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1320
1321Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1322
1323 * mips.igen (ERET): Implement.
1324
1325 * interp.c (decode_coproc): Return sign-extended EPC.
1326
1327 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1328
1329 * interp.c (signal_exception): Do not ignore Trap.
1330 (signal_exception): On TRAP, restart at exception address.
1331 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1332 (signal_exception): Update.
1333 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1334 so that TRAP instructions are caught.
1335
1336Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1337
1338 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1339 contains HI/LO access history.
1340 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1341 (HIACCESS, LOACCESS): Delete, replace with
1342 (HIHISTORY, LOHISTORY): New macros.
1343 (CHECKHILO): Delete all, moved to mips.igen
1344
1345 * gencode.c (build_instruction): Do not generate checks for
1346 correct HI/LO register usage.
1347
1348 * interp.c (old_engine_run): Delete checks for correct HI/LO
1349 register usage.
1350
1351 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1352 check_mf_cycles): New functions.
1353 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1354 do_divu, domultx, do_mult, do_multu): Use.
1355
1356 * tx.igen ("madd", "maddu"): Use.
1357
1358Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1359
1360 * mips.igen (DSRAV): Use function do_dsrav.
1361 (SRAV): Use new function do_srav.
1362
1363 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1364 (B): Sign extend 11 bit immediate.
1365 (EXT-B*): Shift 16 bit immediate left by 1.
1366 (ADDIU*): Don't sign extend immediate value.
1367
1368Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1369
1370 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1371
1372 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1373 functions.
1374
1375 * mips.igen (delayslot32, nullify_next_insn): New functions.
1376 (m16.igen): Always include.
1377 (do_*): Add more tracing.
1378
1379 * m16.igen (delayslot16): Add NIA argument, could be called by a
1380 32 bit MIPS16 instruction.
1381
1382 * interp.c (ifetch16): Move function from here.
1383 * sim-main.c (ifetch16): To here.
1384
1385 * sim-main.c (ifetch16, ifetch32): Update to match current
1386 implementations of LH, LW.
1387 (signal_exception): Don't print out incorrect hex value of illegal
1388 instruction.
1389
1390Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1391
1392 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1393 instruction.
1394
1395 * m16.igen: Implement MIPS16 instructions.
1396
1397 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1398 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1399 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1400 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1401 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1402 bodies of corresponding code from 32 bit insn to these. Also used
1403 by MIPS16 versions of functions.
1404
1405 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1406 (IMEM16): Drop NR argument from macro.
1407
1408Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1409
1410 * Makefile.in (SIM_OBJS): Add sim-main.o.
1411
1412 * sim-main.h (address_translation, load_memory, store_memory,
1413 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1414 as INLINE_SIM_MAIN.
1415 (pr_addr, pr_uword64): Declare.
1416 (sim-main.c): Include when H_REVEALS_MODULE_P.
1417
1418 * interp.c (address_translation, load_memory, store_memory,
1419 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1420 from here.
1421 * sim-main.c: To here. Fix compilation problems.
1422
1423 * configure.in: Enable inlining.
1424 * configure: Re-config.
1425
1426Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1427
1428 * configure: Regenerated to track ../common/aclocal.m4 changes.
1429
1430Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1431
1432 * mips.igen: Include tx.igen.
1433 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1434 * tx.igen: New file, contains MADD and MADDU.
1435
1436 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1437 the hardwired constant `7'.
1438 (store_memory): Ditto.
1439 (LOADDRMASK): Move definition to sim-main.h.
1440
1441 mips.igen (MTC0): Enable for r3900.
1442 (ADDU): Add trace.
1443
1444 mips.igen (do_load_byte): Delete.
1445 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1446 do_store_right): New functions.
1447 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1448
1449 configure.in: Let the tx39 use igen again.
1450 configure: Update.
1451
1452Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1453
1454 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1455 not an address sized quantity. Return zero for cache sizes.
1456
1457Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * mips.igen (r3900): r3900 does not support 64 bit integer
1460 operations.
1461
1462Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1463
1464 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1465 than igen one.
1466 * configure : Rebuild.
1467
1468Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * configure: Regenerated to track ../common/aclocal.m4 changes.
1471
1472Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1473
1474 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1475
1476Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1477
1478 * configure: Regenerated to track ../common/aclocal.m4 changes.
1479 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1480
1481Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1482
1483 * configure: Regenerated to track ../common/aclocal.m4 changes.
1484
1485Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1486
1487 * interp.c (Max, Min): Comment out functions. Not yet used.
1488
1489Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 * configure: Regenerated to track ../common/aclocal.m4 changes.
1492
1493Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1494
1495 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1496 configurable settings for stand-alone simulator.
1497
1498 * configure.in: Added X11 search, just in case.
1499
1500 * configure: Regenerated.
1501
1502Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1503
1504 * interp.c (sim_write, sim_read, load_memory, store_memory):
1505 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1506
1507Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * sim-main.h (GETFCC): Return an unsigned value.
1510
1511Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1514 (DADD): Result destination is RD not RT.
1515
1516Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * sim-main.h (HIACCESS, LOACCESS): Always define.
1519
1520 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1521
1522 * interp.c (sim_info): Delete.
1523
1524Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1525
1526 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1527 (mips_option_handler): New argument `cpu'.
1528 (sim_open): Update call to sim_add_option_table.
1529
1530Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * mips.igen (CxC1): Add tracing.
1533
1534Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1535
1536 * sim-main.h (Max, Min): Declare.
1537
1538 * interp.c (Max, Min): New functions.
1539
1540 * mips.igen (BC1): Add tracing.
1541
1542Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1543
1544 * interp.c Added memory map for stack in vr4100
1545
1546Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1547
1548 * interp.c (load_memory): Add missing "break"'s.
1549
1550Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * interp.c (sim_store_register, sim_fetch_register): Pass in
1553 length parameter. Return -1.
1554
1555Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1556
1557 * interp.c: Added hardware init hook, fixed warnings.
1558
1559Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1560
1561 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1562
1563Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1564
1565 * interp.c (ifetch16): New function.
1566
1567 * sim-main.h (IMEM32): Rename IMEM.
1568 (IMEM16_IMMED): Define.
1569 (IMEM16): Define.
1570 (DELAY_SLOT): Update.
1571
1572 * m16run.c (sim_engine_run): New file.
1573
1574 * m16.igen: All instructions except LB.
1575 (LB): Call do_load_byte.
1576 * mips.igen (do_load_byte): New function.
1577 (LB): Call do_load_byte.
1578
1579 * mips.igen: Move spec for insn bit size and high bit from here.
1580 * Makefile.in (tmp-igen, tmp-m16): To here.
1581
1582 * m16.dc: New file, decode mips16 instructions.
1583
1584 * Makefile.in (SIM_NO_ALL): Define.
1585 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1586
1587Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1588
1589 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1590 point unit to 32 bit registers.
1591 * configure: Re-generate.
1592
1593Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1594
1595 * configure.in (sim_use_gen): Make IGEN the default simulator
1596 generator for generic 32 and 64 bit mips targets.
1597 * configure: Re-generate.
1598
1599Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1600
1601 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1602 bitsize.
1603
1604 * interp.c (sim_fetch_register, sim_store_register): Read/write
1605 FGR from correct location.
1606 (sim_open): Set size of FGR's according to
1607 WITH_TARGET_FLOATING_POINT_BITSIZE.
1608
1609 * sim-main.h (FGR): Store floating point registers in a separate
1610 array.
1611
1612Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1613
1614 * configure: Regenerated to track ../common/aclocal.m4 changes.
1615
1616Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1617
1618 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1619
1620 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1621
1622 * interp.c (pending_tick): New function. Deliver pending writes.
1623
1624 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1625 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1626 it can handle mixed sized quantites and single bits.
1627
1628Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * interp.c (oengine.h): Do not include when building with IGEN.
1631 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1632 (sim_info): Ditto for PROCESSOR_64BIT.
1633 (sim_monitor): Replace ut_reg with unsigned_word.
1634 (*): Ditto for t_reg.
1635 (LOADDRMASK): Define.
1636 (sim_open): Remove defunct check that host FP is IEEE compliant,
1637 using software to emulate floating point.
1638 (value_fpr, ...): Always compile, was conditional on HASFPU.
1639
1640Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1643 size.
1644
1645 * interp.c (SD, CPU): Define.
1646 (mips_option_handler): Set flags in each CPU.
1647 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1648 (sim_close): Do not clear STATE, deleted anyway.
1649 (sim_write, sim_read): Assume CPU zero's vm should be used for
1650 data transfers.
1651 (sim_create_inferior): Set the PC for all processors.
1652 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1653 argument.
1654 (mips16_entry): Pass correct nr of args to store_word, load_word.
1655 (ColdReset): Cold reset all cpu's.
1656 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1657 (sim_monitor, load_memory, store_memory, signal_exception): Use
1658 `CPU' instead of STATE_CPU.
1659
1660
1661 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1662 SD or CPU_.
1663
1664 * sim-main.h (signal_exception): Add sim_cpu arg.
1665 (SignalException*): Pass both SD and CPU to signal_exception.
1666 * interp.c (signal_exception): Update.
1667
1668 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1669 Ditto
1670 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1671 address_translation): Ditto
1672 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1673
1674Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * configure: Regenerated to track ../common/aclocal.m4 changes.
1677
1678Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1681
1682 * mips.igen (model): Map processor names onto BFD name.
1683
1684 * sim-main.h (CPU_CIA): Delete.
1685 (SET_CIA, GET_CIA): Define
1686
1687Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1688
1689 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1690 regiser.
1691
1692 * configure.in (default_endian): Configure a big-endian simulator
1693 by default.
1694 * configure: Re-generate.
1695
1696Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1697
1698 * configure: Regenerated to track ../common/aclocal.m4 changes.
1699
1700Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1701
1702 * interp.c (sim_monitor): Handle Densan monitor outbyte
1703 and inbyte functions.
1704
17051997-12-29 Felix Lee <flee@cygnus.com>
1706
1707 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1708
1709Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1710
1711 * Makefile.in (tmp-igen): Arrange for $zero to always be
1712 reset to zero after every instruction.
1713
1714Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1715
1716 * configure: Regenerated to track ../common/aclocal.m4 changes.
1717 * config.in: Ditto.
1718
1719Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1720
1721 * mips.igen (MSUB): Fix to work like MADD.
1722 * gencode.c (MSUB): Similarly.
1723
1724Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1725
1726 * configure: Regenerated to track ../common/aclocal.m4 changes.
1727
1728Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1729
1730 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1731
1732Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1733
1734 * sim-main.h (sim-fpu.h): Include.
1735
1736 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1737 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1738 using host independant sim_fpu module.
1739
1740Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1741
1742 * interp.c (signal_exception): Report internal errors with SIGABRT
1743 not SIGQUIT.
1744
1745 * sim-main.h (C0_CONFIG): New register.
1746 (signal.h): No longer include.
1747
1748 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1749
1750Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1751
1752 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1753
1754Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1755
1756 * mips.igen: Tag vr5000 instructions.
1757 (ANDI): Was missing mipsIV model, fix assembler syntax.
1758 (do_c_cond_fmt): New function.
1759 (C.cond.fmt): Handle mips I-III which do not support CC field
1760 separatly.
1761 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1762 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1763 in IV3.2 spec.
1764 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1765 vr5000 which saves LO in a GPR separatly.
1766
1767 * configure.in (enable-sim-igen): For vr5000, select vr5000
1768 specific instructions.
1769 * configure: Re-generate.
1770
1771Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1772
1773 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1774
1775 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1776 fmt_uninterpreted_64 bit cases to switch. Convert to
1777 fmt_formatted,
1778
1779 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1780
1781 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1782 as specified in IV3.2 spec.
1783 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1784
1785Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1788 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1789 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1790 PENDING_FILL versions of instructions. Simplify.
1791 (X): New function.
1792 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1793 instructions.
1794 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1795 a signed value.
1796 (MTHI, MFHI): Disable code checking HI-LO.
1797
1798 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1799 global.
1800 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1801
1802Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1803
1804 * gencode.c (build_mips16_operands): Replace IPC with cia.
1805
1806 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1807 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1808 IPC to `cia'.
1809 (UndefinedResult): Replace function with macro/function
1810 combination.
1811 (sim_engine_run): Don't save PC in IPC.
1812
1813 * sim-main.h (IPC): Delete.
1814
1815
1816 * interp.c (signal_exception, store_word, load_word,
1817 address_translation, load_memory, store_memory, cache_op,
1818 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1819 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1820 current instruction address - cia - argument.
1821 (sim_read, sim_write): Call address_translation directly.
1822 (sim_engine_run): Rename variable vaddr to cia.
1823 (signal_exception): Pass cia to sim_monitor
1824
1825 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1826 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1827 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1828
1829 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1830 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1831 SIM_ASSERT.
1832
1833 * interp.c (signal_exception): Pass restart address to
1834 sim_engine_restart.
1835
1836 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1837 idecode.o): Add dependency.
1838
1839 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1840 Delete definitions
1841 (DELAY_SLOT): Update NIA not PC with branch address.
1842 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1843
1844 * mips.igen: Use CIA not PC in branch calculations.
1845 (illegal): Call SignalException.
1846 (BEQ, ADDIU): Fix assembler.
1847
1848Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * m16.igen (JALX): Was missing.
1851
1852 * configure.in (enable-sim-igen): New configuration option.
1853 * configure: Re-generate.
1854
1855 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1856
1857 * interp.c (load_memory, store_memory): Delete parameter RAW.
1858 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1859 bypassing {load,store}_memory.
1860
1861 * sim-main.h (ByteSwapMem): Delete definition.
1862
1863 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1864
1865 * interp.c (sim_do_command, sim_commands): Delete mips specific
1866 commands. Handled by module sim-options.
1867
1868 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1869 (WITH_MODULO_MEMORY): Define.
1870
1871 * interp.c (sim_info): Delete code printing memory size.
1872
1873 * interp.c (mips_size): Nee sim_size, delete function.
1874 (power2): Delete.
1875 (monitor, monitor_base, monitor_size): Delete global variables.
1876 (sim_open, sim_close): Delete code creating monitor and other
1877 memory regions. Use sim-memopts module, via sim_do_commandf, to
1878 manage memory regions.
1879 (load_memory, store_memory): Use sim-core for memory model.
1880
1881 * interp.c (address_translation): Delete all memory map code
1882 except line forcing 32 bit addresses.
1883
1884Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1887 trace options.
1888
1889 * interp.c (logfh, logfile): Delete globals.
1890 (sim_open, sim_close): Delete code opening & closing log file.
1891 (mips_option_handler): Delete -l and -n options.
1892 (OPTION mips_options): Ditto.
1893
1894 * interp.c (OPTION mips_options): Rename option trace to dinero.
1895 (mips_option_handler): Update.
1896
1897Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1898
1899 * interp.c (fetch_str): New function.
1900 (sim_monitor): Rewrite using sim_read & sim_write.
1901 (sim_open): Check magic number.
1902 (sim_open): Write monitor vectors into memory using sim_write.
1903 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1904 (sim_read, sim_write): Simplify - transfer data one byte at a
1905 time.
1906 (load_memory, store_memory): Clarify meaning of parameter RAW.
1907
1908 * sim-main.h (isHOST): Defete definition.
1909 (isTARGET): Mark as depreciated.
1910 (address_translation): Delete parameter HOST.
1911
1912 * interp.c (address_translation): Delete parameter HOST.
1913
1914Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1915
1916 * mips.igen:
1917
1918 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1919 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1920
1921Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * mips.igen: Add model filter field to records.
1924
1925Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1926
1927 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1928
1929 interp.c (sim_engine_run): Do not compile function sim_engine_run
1930 when WITH_IGEN == 1.
1931
1932 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1933 target architecture.
1934
1935 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1936 igen. Replace with configuration variables sim_igen_flags /
1937 sim_m16_flags.
1938
1939 * m16.igen: New file. Copy mips16 insns here.
1940 * mips.igen: From here.
1941
1942Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1943
1944 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1945 to top.
1946 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1947
1948Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1949
1950 * gencode.c (build_instruction): Follow sim_write's lead in using
1951 BigEndianMem instead of !ByteSwapMem.
1952
1953Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1954
1955 * configure.in (sim_gen): Dependent on target, select type of
1956 generator. Always select old style generator.
1957
1958 configure: Re-generate.
1959
1960 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1961 targets.
1962 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1963 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1964 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1965 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1966 SIM_@sim_gen@_*, set by autoconf.
1967
1968Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1971
1972 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1973 CURRENT_FLOATING_POINT instead.
1974
1975 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1976 (address_translation): Raise exception InstructionFetch when
1977 translation fails and isINSTRUCTION.
1978
1979 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1980 sim_engine_run): Change type of of vaddr and paddr to
1981 address_word.
1982 (address_translation, prefetch, load_memory, store_memory,
1983 cache_op): Change type of vAddr and pAddr to address_word.
1984
1985 * gencode.c (build_instruction): Change type of vaddr and paddr to
1986 address_word.
1987
1988Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1991 macro to obtain result of ALU op.
1992
1993Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * interp.c (sim_info): Call profile_print.
1996
1997Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1998
1999 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2000
2001 * sim-main.h (WITH_PROFILE): Do not define, defined in
2002 common/sim-config.h. Use sim-profile module.
2003 (simPROFILE): Delete defintion.
2004
2005 * interp.c (PROFILE): Delete definition.
2006 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2007 (sim_close): Delete code writing profile histogram.
2008 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2009 Delete.
2010 (sim_engine_run): Delete code profiling the PC.
2011
2012Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2013
2014 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2015
2016 * interp.c (sim_monitor): Make register pointers of type
2017 unsigned_word*.
2018
2019 * sim-main.h: Make registers of type unsigned_word not
2020 signed_word.
2021
2022Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * interp.c (sync_operation): Rename from SyncOperation, make
2025 global, add SD argument.
2026 (prefetch): Rename from Prefetch, make global, add SD argument.
2027 (decode_coproc): Make global.
2028
2029 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2030
2031 * gencode.c (build_instruction): Generate DecodeCoproc not
2032 decode_coproc calls.
2033
2034 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2035 (SizeFGR): Move to sim-main.h
2036 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2037 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2038 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2039 sim-main.h.
2040 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2041 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2042 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2043 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2044 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2045 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2046
2047 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2048 exception.
2049 (sim-alu.h): Include.
2050 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2051 (sim_cia): Typedef to instruction_address.
2052
2053Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2054
2055 * Makefile.in (interp.o): Rename generated file engine.c to
2056 oengine.c.
2057
2058 * interp.c: Update.
2059
2060Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2061
2062 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2063
2064Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * gencode.c (build_instruction): For "FPSQRT", output correct
2067 number of arguments to Recip.
2068
2069Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2070
2071 * Makefile.in (interp.o): Depends on sim-main.h
2072
2073 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2074
2075 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2076 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2077 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2078 STATE, DSSTATE): Define
2079 (GPR, FGRIDX, ..): Define.
2080
2081 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2082 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2083 (GPR, FGRIDX, ...): Delete macros.
2084
2085 * interp.c: Update names to match defines from sim-main.h
2086
2087Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2088
2089 * interp.c (sim_monitor): Add SD argument.
2090 (sim_warning): Delete. Replace calls with calls to
2091 sim_io_eprintf.
2092 (sim_error): Delete. Replace calls with sim_io_error.
2093 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2094 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2095 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2096 argument.
2097 (mips_size): Rename from sim_size. Add SD argument.
2098
2099 * interp.c (simulator): Delete global variable.
2100 (callback): Delete global variable.
2101 (mips_option_handler, sim_open, sim_write, sim_read,
2102 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2103 sim_size,sim_monitor): Use sim_io_* not callback->*.
2104 (sim_open): ZALLOC simulator struct.
2105 (PROFILE): Do not define.
2106
2107Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2108
2109 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2110 support.h with corresponding code.
2111
2112 * sim-main.h (word64, uword64), support.h: Move definition to
2113 sim-main.h.
2114 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2115
2116 * support.h: Delete
2117 * Makefile.in: Update dependencies
2118 * interp.c: Do not include.
2119
2120Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2121
2122 * interp.c (address_translation, load_memory, store_memory,
2123 cache_op): Rename to from AddressTranslation et.al., make global,
2124 add SD argument
2125
2126 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2127 CacheOp): Define.
2128
2129 * interp.c (SignalException): Rename to signal_exception, make
2130 global.
2131
2132 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2133
2134 * sim-main.h (SignalException, SignalExceptionInterrupt,
2135 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2136 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2137 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2138 Define.
2139
2140 * interp.c, support.h: Use.
2141
2142Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143
2144 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2145 to value_fpr / store_fpr. Add SD argument.
2146 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2147 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2148
2149 * sim-main.h (ValueFPR, StoreFPR): Define.
2150
2151Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2152
2153 * interp.c (sim_engine_run): Check consistency between configure
2154 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2155 and HASFPU.
2156
2157 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2158 (mips_fpu): Configure WITH_FLOATING_POINT.
2159 (mips_endian): Configure WITH_TARGET_ENDIAN.
2160 * configure: Update.
2161
2162Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * configure: Regenerated to track ../common/aclocal.m4 changes.
2165
2166Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2167
2168 * configure: Regenerated.
2169
2170Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2171
2172 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2173
2174Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2175
2176 * gencode.c (print_igen_insn_models): Assume certain architectures
2177 include all mips* instructions.
2178 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2179 instruction.
2180
2181 * Makefile.in (tmp.igen): Add target. Generate igen input from
2182 gencode file.
2183
2184 * gencode.c (FEATURE_IGEN): Define.
2185 (main): Add --igen option. Generate output in igen format.
2186 (process_instructions): Format output according to igen option.
2187 (print_igen_insn_format): New function.
2188 (print_igen_insn_models): New function.
2189 (process_instructions): Only issue warnings and ignore
2190 instructions when no FEATURE_IGEN.
2191
2192Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2193
2194 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2195 MIPS targets.
2196
2197Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198
2199 * configure: Regenerated to track ../common/aclocal.m4 changes.
2200
2201Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2202
2203 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2204 SIM_RESERVED_BITS): Delete, moved to common.
2205 (SIM_EXTRA_CFLAGS): Update.
2206
2207Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2208
2209 * configure.in: Configure non-strict memory alignment.
2210 * configure: Regenerated to track ../common/aclocal.m4 changes.
2211
2212Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * configure: Regenerated to track ../common/aclocal.m4 changes.
2215
2216Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2217
2218 * gencode.c (SDBBP,DERET): Added (3900) insns.
2219 (RFE): Turn on for 3900.
2220 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2221 (dsstate): Made global.
2222 (SUBTARGET_R3900): Added.
2223 (CANCELDELAYSLOT): New.
2224 (SignalException): Ignore SystemCall rather than ignore and
2225 terminate. Add DebugBreakPoint handling.
2226 (decode_coproc): New insns RFE, DERET; and new registers Debug
2227 and DEPC protected by SUBTARGET_R3900.
2228 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2229 bits explicitly.
2230 * Makefile.in,configure.in: Add mips subtarget option.
2231 * configure: Update.
2232
2233Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2234
2235 * gencode.c: Add r3900 (tx39).
2236
2237
2238Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2239
2240 * gencode.c (build_instruction): Don't need to subtract 4 for
2241 JALR, just 2.
2242
2243Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2244
2245 * interp.c: Correct some HASFPU problems.
2246
2247Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2248
2249 * configure: Regenerated to track ../common/aclocal.m4 changes.
2250
2251Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2252
2253 * interp.c (mips_options): Fix samples option short form, should
2254 be `x'.
2255
2256Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * interp.c (sim_info): Enable info code. Was just returning.
2259
2260Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2261
2262 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2263 MFC0.
2264
2265Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266
2267 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2268 constants.
2269 (build_instruction): Ditto for LL.
2270
2271Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2272
2273 * configure: Regenerated to track ../common/aclocal.m4 changes.
2274
2275Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2276
2277 * configure: Regenerated to track ../common/aclocal.m4 changes.
2278 * config.in: Ditto.
2279
2280Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * interp.c (sim_open): Add call to sim_analyze_program, update
2283 call to sim_config.
2284
2285Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * interp.c (sim_kill): Delete.
2288 (sim_create_inferior): Add ABFD argument. Set PC from same.
2289 (sim_load): Move code initializing trap handlers from here.
2290 (sim_open): To here.
2291 (sim_load): Delete, use sim-hload.c.
2292
2293 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2294
2295Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * configure: Regenerated to track ../common/aclocal.m4 changes.
2298 * config.in: Ditto.
2299
2300Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * interp.c (sim_open): Add ABFD argument.
2303 (sim_load): Move call to sim_config from here.
2304 (sim_open): To here. Check return status.
2305
2306Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2307
2308 * gencode.c (build_instruction): Two arg MADD should
2309 not assign result to $0.
2310
2311Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2312
2313 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2314 * sim/mips/configure.in: Regenerate.
2315
2316Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2317
2318 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2319 signed8, unsigned8 et.al. types.
2320
2321 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2322 hosts when selecting subreg.
2323
2324Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2325
2326 * interp.c (sim_engine_run): Reset the ZERO register to zero
2327 regardless of FEATURE_WARN_ZERO.
2328 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2329
2330Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2333 (SignalException): For BreakPoints ignore any mode bits and just
2334 save the PC.
2335 (SignalException): Always set the CAUSE register.
2336
2337Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2338
2339 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2340 exception has been taken.
2341
2342 * interp.c: Implement the ERET and mt/f sr instructions.
2343
2344Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2345
2346 * interp.c (SignalException): Don't bother restarting an
2347 interrupt.
2348
2349Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * interp.c (SignalException): Really take an interrupt.
2352 (interrupt_event): Only deliver interrupts when enabled.
2353
2354Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2355
2356 * interp.c (sim_info): Only print info when verbose.
2357 (sim_info) Use sim_io_printf for output.
2358
2359Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2360
2361 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2362 mips architectures.
2363
2364Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365
2366 * interp.c (sim_do_command): Check for common commands if a
2367 simulator specific command fails.
2368
2369Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2370
2371 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2372 and simBE when DEBUG is defined.
2373
2374Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375
2376 * interp.c (interrupt_event): New function. Pass exception event
2377 onto exception handler.
2378
2379 * configure.in: Check for stdlib.h.
2380 * configure: Regenerate.
2381
2382 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2383 variable declaration.
2384 (build_instruction): Initialize memval1.
2385 (build_instruction): Add UNUSED attribute to byte, bigend,
2386 reverse.
2387 (build_operands): Ditto.
2388
2389 * interp.c: Fix GCC warnings.
2390 (sim_get_quit_code): Delete.
2391
2392 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2393 * Makefile.in: Ditto.
2394 * configure: Re-generate.
2395
2396 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2397
2398Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2399
2400 * interp.c (mips_option_handler): New function parse argumes using
2401 sim-options.
2402 (myname): Replace with STATE_MY_NAME.
2403 (sim_open): Delete check for host endianness - performed by
2404 sim_config.
2405 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2406 (sim_open): Move much of the initialization from here.
2407 (sim_load): To here. After the image has been loaded and
2408 endianness set.
2409 (sim_open): Move ColdReset from here.
2410 (sim_create_inferior): To here.
2411 (sim_open): Make FP check less dependant on host endianness.
2412
2413 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2414 run.
2415 * interp.c (sim_set_callbacks): Delete.
2416
2417 * interp.c (membank, membank_base, membank_size): Replace with
2418 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2419 (sim_open): Remove call to callback->init. gdb/run do this.
2420
2421 * interp.c: Update
2422
2423 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2424
2425 * interp.c (big_endian_p): Delete, replaced by
2426 current_target_byte_order.
2427
2428Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2429
2430 * interp.c (host_read_long, host_read_word, host_swap_word,
2431 host_swap_long): Delete. Using common sim-endian.
2432 (sim_fetch_register, sim_store_register): Use H2T.
2433 (pipeline_ticks): Delete. Handled by sim-events.
2434 (sim_info): Update.
2435 (sim_engine_run): Update.
2436
2437Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2438
2439 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2440 reason from here.
2441 (SignalException): To here. Signal using sim_engine_halt.
2442 (sim_stop_reason): Delete, moved to common.
2443
2444Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2445
2446 * interp.c (sim_open): Add callback argument.
2447 (sim_set_callbacks): Delete SIM_DESC argument.
2448 (sim_size): Ditto.
2449
2450Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2451
2452 * Makefile.in (SIM_OBJS): Add common modules.
2453
2454 * interp.c (sim_set_callbacks): Also set SD callback.
2455 (set_endianness, xfer_*, swap_*): Delete.
2456 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2457 Change to functions using sim-endian macros.
2458 (control_c, sim_stop): Delete, use common version.
2459 (simulate): Convert into.
2460 (sim_engine_run): This function.
2461 (sim_resume): Delete.
2462
2463 * interp.c (simulation): New variable - the simulator object.
2464 (sim_kind): Delete global - merged into simulation.
2465 (sim_load): Cleanup. Move PC assignment from here.
2466 (sim_create_inferior): To here.
2467
2468 * sim-main.h: New file.
2469 * interp.c (sim-main.h): Include.
2470
2471Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2472
2473 * configure: Regenerated to track ../common/aclocal.m4 changes.
2474
2475Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2476
2477 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2478
2479Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2480
2481 * gencode.c (build_instruction): DIV instructions: check
2482 for division by zero and integer overflow before using
2483 host's division operation.
2484
2485Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2486
2487 * Makefile.in (SIM_OBJS): Add sim-load.o.
2488 * interp.c: #include bfd.h.
2489 (target_byte_order): Delete.
2490 (sim_kind, myname, big_endian_p): New static locals.
2491 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2492 after argument parsing. Recognize -E arg, set endianness accordingly.
2493 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2494 load file into simulator. Set PC from bfd.
2495 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2496 (set_endianness): Use big_endian_p instead of target_byte_order.
2497
2498Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2499
2500 * interp.c (sim_size): Delete prototype - conflicts with
2501 definition in remote-sim.h. Correct definition.
2502
2503Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2504
2505 * configure: Regenerated to track ../common/aclocal.m4 changes.
2506 * config.in: Ditto.
2507
2508Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2509
2510 * interp.c (sim_open): New arg `kind'.
2511
2512 * configure: Regenerated to track ../common/aclocal.m4 changes.
2513
2514Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2515
2516 * configure: Regenerated to track ../common/aclocal.m4 changes.
2517
2518Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2519
2520 * interp.c (sim_open): Set optind to 0 before calling getopt.
2521
2522Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2523
2524 * configure: Regenerated to track ../common/aclocal.m4 changes.
2525
2526Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2527
2528 * interp.c : Replace uses of pr_addr with pr_uword64
2529 where the bit length is always 64 independent of SIM_ADDR.
2530 (pr_uword64) : added.
2531
2532Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2533
2534 * configure: Re-generate.
2535
2536Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2537
2538 * configure: Regenerate to track ../common/aclocal.m4 changes.
2539
2540Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2541
2542 * interp.c (sim_open): New SIM_DESC result. Argument is now
2543 in argv form.
2544 (other sim_*): New SIM_DESC argument.
2545
2546Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2547
2548 * interp.c: Fix printing of addresses for non-64-bit targets.
2549 (pr_addr): Add function to print address based on size.
2550
2551Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2552
2553 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2554
2555Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2556
2557 * gencode.c (build_mips16_operands): Correct computation of base
2558 address for extended PC relative instruction.
2559
2560Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2561
2562 * interp.c (mips16_entry): Add support for floating point cases.
2563 (SignalException): Pass floating point cases to mips16_entry.
2564 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2565 registers.
2566 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2567 or fmt_word.
2568 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2569 and then set the state to fmt_uninterpreted.
2570 (COP_SW): Temporarily set the state to fmt_word while calling
2571 ValueFPR.
2572
2573Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2574
2575 * gencode.c (build_instruction): The high order may be set in the
2576 comparison flags at any ISA level, not just ISA 4.
2577
2578Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2579
2580 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2581 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2582 * configure.in: sinclude ../common/aclocal.m4.
2583 * configure: Regenerated.
2584
2585Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2586
2587 * configure: Rebuild after change to aclocal.m4.
2588
2589Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2590
2591 * configure configure.in Makefile.in: Update to new configure
2592 scheme which is more compatible with WinGDB builds.
2593 * configure.in: Improve comment on how to run autoconf.
2594 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2595 * Makefile.in: Use autoconf substitution to install common
2596 makefile fragment.
2597
2598Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2599
2600 * gencode.c (build_instruction): Use BigEndianCPU instead of
2601 ByteSwapMem.
2602
2603Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2604
2605 * interp.c (sim_monitor): Make output to stdout visible in
2606 wingdb's I/O log window.
2607
2608Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2609
2610 * support.h: Undo previous change to SIGTRAP
2611 and SIGQUIT values.
2612
2613Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2614
2615 * interp.c (store_word, load_word): New static functions.
2616 (mips16_entry): New static function.
2617 (SignalException): Look for mips16 entry and exit instructions.
2618 (simulate): Use the correct index when setting fpr_state after
2619 doing a pending move.
2620
2621Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2622
2623 * interp.c: Fix byte-swapping code throughout to work on
2624 both little- and big-endian hosts.
2625
2626Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2627
2628 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2629 with gdb/config/i386/xm-windows.h.
2630
2631Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2632
2633 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2634 that messes up arithmetic shifts.
2635
2636Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2637
2638 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2639 SIGTRAP and SIGQUIT for _WIN32.
2640
2641Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2642
2643 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2644 force a 64 bit multiplication.
2645 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2646 destination register is 0, since that is the default mips16 nop
2647 instruction.
2648
2649Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2650
2651 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2652 (build_endian_shift): Don't check proc64.
2653 (build_instruction): Always set memval to uword64. Cast op2 to
2654 uword64 when shifting it left in memory instructions. Always use
2655 the same code for stores--don't special case proc64.
2656
2657 * gencode.c (build_mips16_operands): Fix base PC value for PC
2658 relative operands.
2659 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2660 jal instruction.
2661 * interp.c (simJALDELAYSLOT): Define.
2662 (JALDELAYSLOT): Define.
2663 (INDELAYSLOT, INJALDELAYSLOT): Define.
2664 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2665
2666Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2667
2668 * interp.c (sim_open): add flush_cache as a PMON routine
2669 (sim_monitor): handle flush_cache by ignoring it
2670
2671Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2672
2673 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2674 BigEndianMem.
2675 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2676 (BigEndianMem): Rename to ByteSwapMem and change sense.
2677 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2678 BigEndianMem references to !ByteSwapMem.
2679 (set_endianness): New function, with prototype.
2680 (sim_open): Call set_endianness.
2681 (sim_info): Use simBE instead of BigEndianMem.
2682 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2683 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2684 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2685 ifdefs, keeping the prototype declaration.
2686 (swap_word): Rewrite correctly.
2687 (ColdReset): Delete references to CONFIG. Delete endianness related
2688 code; moved to set_endianness.
2689
2690Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2691
2692 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2693 * interp.c (CHECKHILO): Define away.
2694 (simSIGINT): New macro.
2695 (membank_size): Increase from 1MB to 2MB.
2696 (control_c): New function.
2697 (sim_resume): Rename parameter signal to signal_number. Add local
2698 variable prev. Call signal before and after simulate.
2699 (sim_stop_reason): Add simSIGINT support.
2700 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2701 functions always.
2702 (sim_warning): Delete call to SignalException. Do call printf_filtered
2703 if logfh is NULL.
2704 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2705 a call to sim_warning.
2706
2707Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2708
2709 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2710 16 bit instructions.
2711
2712Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2713
2714 Add support for mips16 (16 bit MIPS implementation):
2715 * gencode.c (inst_type): Add mips16 instruction encoding types.
2716 (GETDATASIZEINSN): Define.
2717 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2718 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2719 mtlo.
2720 (MIPS16_DECODE): New table, for mips16 instructions.
2721 (bitmap_val): New static function.
2722 (struct mips16_op): Define.
2723 (mips16_op_table): New table, for mips16 operands.
2724 (build_mips16_operands): New static function.
2725 (process_instructions): If PC is odd, decode a mips16
2726 instruction. Break out instruction handling into new
2727 build_instruction function.
2728 (build_instruction): New static function, broken out of
2729 process_instructions. Check modifiers rather than flags for SHIFT
2730 bit count and m[ft]{hi,lo} direction.
2731 (usage): Pass program name to fprintf.
2732 (main): Remove unused variable this_option_optind. Change
2733 ``*loptarg++'' to ``loptarg++''.
2734 (my_strtoul): Parenthesize && within ||.
2735 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2736 (simulate): If PC is odd, fetch a 16 bit instruction, and
2737 increment PC by 2 rather than 4.
2738 * configure.in: Add case for mips16*-*-*.
2739 * configure: Rebuild.
2740
2741Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2742
2743 * interp.c: Allow -t to enable tracing in standalone simulator.
2744 Fix garbage output in trace file and error messages.
2745
2746Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2747
2748 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2749 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2750 * configure.in: Simplify using macros in ../common/aclocal.m4.
2751 * configure: Regenerated.
2752 * tconfig.in: New file.
2753
2754Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2755
2756 * interp.c: Fix bugs in 64-bit port.
2757 Use ansi function declarations for msvc compiler.
2758 Initialize and test file pointer in trace code.
2759 Prevent duplicate definition of LAST_EMED_REGNUM.
2760
2761Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2762
2763 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2764
2765Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2766
2767 * interp.c (SignalException): Check for explicit terminating
2768 breakpoint value.
2769 * gencode.c: Pass instruction value through SignalException()
2770 calls for Trap, Breakpoint and Syscall.
2771
2772Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2773
2774 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2775 only used on those hosts that provide it.
2776 * configure.in: Add sqrt() to list of functions to be checked for.
2777 * config.in: Re-generated.
2778 * configure: Re-generated.
2779
2780Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2781
2782 * gencode.c (process_instructions): Call build_endian_shift when
2783 expanding STORE RIGHT, to fix swr.
2784 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2785 clear the high bits.
2786 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2787 Fix float to int conversions to produce signed values.
2788
2789Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2790
2791 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2792 (process_instructions): Correct handling of nor instruction.
2793 Correct shift count for 32 bit shift instructions. Correct sign
2794 extension for arithmetic shifts to not shift the number of bits in
2795 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2796 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2797 Fix madd.
2798 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2799 It's OK to have a mult follow a mult. What's not OK is to have a
2800 mult follow an mfhi.
2801 (Convert): Comment out incorrect rounding code.
2802
2803Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2804
2805 * interp.c (sim_monitor): Improved monitor printf
2806 simulation. Tidied up simulator warnings, and added "--log" option
2807 for directing warning message output.
2808 * gencode.c: Use sim_warning() rather than WARNING macro.
2809
2810Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2811
2812 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2813 getopt1.o, rather than on gencode.c. Link objects together.
2814 Don't link against -liberty.
2815 (gencode.o, getopt.o, getopt1.o): New targets.
2816 * gencode.c: Include <ctype.h> and "ansidecl.h".
2817 (AND): Undefine after including "ansidecl.h".
2818 (ULONG_MAX): Define if not defined.
2819 (OP_*): Don't define macros; now defined in opcode/mips.h.
2820 (main): Call my_strtoul rather than strtoul.
2821 (my_strtoul): New static function.
2822
2823Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2824
2825 * gencode.c (process_instructions): Generate word64 and uword64
2826 instead of `long long' and `unsigned long long' data types.
2827 * interp.c: #include sysdep.h to get signals, and define default
2828 for SIGBUS.
2829 * (Convert): Work around for Visual-C++ compiler bug with type
2830 conversion.
2831 * support.h: Make things compile under Visual-C++ by using
2832 __int64 instead of `long long'. Change many refs to long long
2833 into word64/uword64 typedefs.
2834
2835Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2836
2837 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2838 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2839 (docdir): Removed.
2840 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2841 (AC_PROG_INSTALL): Added.
2842 (AC_PROG_CC): Moved to before configure.host call.
2843 * configure: Rebuilt.
2844
2845Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2846
2847 * configure.in: Define @SIMCONF@ depending on mips target.
2848 * configure: Rebuild.
2849 * Makefile.in (run): Add @SIMCONF@ to control simulator
2850 construction.
2851 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2852 * interp.c: Remove some debugging, provide more detailed error
2853 messages, update memory accesses to use LOADDRMASK.
2854
2855Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2856
2857 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2858 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2859 stamp-h.
2860 * configure: Rebuild.
2861 * config.in: New file, generated by autoheader.
2862 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2863 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2864 HAVE_ANINT and HAVE_AINT, as appropriate.
2865 * Makefile.in (run): Use @LIBS@ rather than -lm.
2866 (interp.o): Depend upon config.h.
2867 (Makefile): Just rebuild Makefile.
2868 (clean): Remove stamp-h.
2869 (mostlyclean): Make the same as clean, not as distclean.
2870 (config.h, stamp-h): New targets.
2871
2872Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2873
2874 * interp.c (ColdReset): Fix boolean test. Make all simulator
2875 globals static.
2876
2877Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2878
2879 * interp.c (xfer_direct_word, xfer_direct_long,
2880 swap_direct_word, swap_direct_long, xfer_big_word,
2881 xfer_big_long, xfer_little_word, xfer_little_long,
2882 swap_word,swap_long): Added.
2883 * interp.c (ColdReset): Provide function indirection to
2884 host<->simulated_target transfer routines.
2885 * interp.c (sim_store_register, sim_fetch_register): Updated to
2886 make use of indirected transfer routines.
2887
2888Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2889
2890 * gencode.c (process_instructions): Ensure FP ABS instruction
2891 recognised.
2892 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2893 system call support.
2894
2895Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2896
2897 * interp.c (sim_do_command): Complain if callback structure not
2898 initialised.
2899
2900Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2901
2902 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2903 support for Sun hosts.
2904 * Makefile.in (gencode): Ensure the host compiler and libraries
2905 used for cross-hosted build.
2906
2907Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2908
2909 * interp.c, gencode.c: Some more (TODO) tidying.
2910
2911Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2912
2913 * gencode.c, interp.c: Replaced explicit long long references with
2914 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2915 * support.h (SET64LO, SET64HI): Macros added.
2916
2917Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2918
2919 * configure: Regenerate with autoconf 2.7.
2920
2921Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2922
2923 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2924 * support.h: Remove superfluous "1" from #if.
2925 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2926
2927Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2928
2929 * interp.c (StoreFPR): Control UndefinedResult() call on
2930 WARN_RESULT manifest.
2931
2932Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2933
2934 * gencode.c: Tidied instruction decoding, and added FP instruction
2935 support.
2936
2937 * interp.c: Added dineroIII, and BSD profiling support. Also
2938 run-time FP handling.
2939
2940Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2941
2942 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2943 gencode.c, interp.c, support.h: created.
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