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2004-04-10 Chris Demetriou <cgd@broadcom.com>
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
14234056
CD		 12004-04-09 Chris Demetriou <cgd@broadcom.com>
2
3 * mips.igen (check_fmt): Remove.
4 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
5 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
6 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
7 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
8 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
9 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
10 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
11 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
12 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
13 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
14
c6f9085c
CD		 152004-04-09 Chris Demetriou <cgd@broadcom.com>
16
17 * sb1.igen (check_sbx): New function.
18 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
19
11d66e66 202004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 21 Richard Sandiford <rsandifo@redhat.com>
22
23 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
24 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
25 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
26 separate implementations for mipsIV and mipsV. Use new macros to
27 determine whether the restrictions apply.
28
b3208fb8
CD		 292004-01-19 Chris Demetriou <cgd@broadcom.com>
30
31 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
32 (check_mult_hilo): Improve comments.
33 (check_div_hilo): Likewise. Also, fork off a new version
34 to handle mips32/mips64 (since there are no hazards to check
35 in MIPS32/MIPS64).
36
9a1d84fb
CD		 372003-06-17 Richard Sandiford <rsandifo@redhat.com>
38
39 * mips.igen (do_dmultx): Fix check for negative operands.
40
ae451ac6
ILT		 412003-05-16 Ian Lance Taylor <ian@airs.com>
42
43 * Makefile.in (SHELL): Make sure this is defined.
44 (various): Use $(SHELL) whenever we invoke move-if-change.
45
dd69d292
CD		 462003-05-03 Chris Demetriou <cgd@broadcom.com>
47
48 * cp1.c: Tweak attribution slightly.
49 * cp1.h: Likewise.
50 * mdmx.c: Likewise.
51 * mdmx.igen: Likewise.
52 * mips3d.igen: Likewise.
53 * sb1.igen: Likewise.
54
bcd0068e
CD		 552003-04-15 Richard Sandiford <rsandifo@redhat.com>
56
57 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
58 unsigned operands.
59
6b4a8935
AC		 602003-02-27 Andrew Cagney <cagney@redhat.com>
61
601da316
AC		 62 * interp.c (sim_open): Rename _bfd to bfd.
63 (sim_create_inferior): Ditto.
6b4a8935 64
d29e330f
CD		 652003-01-14 Chris Demetriou <cgd@broadcom.com>
66
67 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
68
a2353a08
CD		 692003-01-14 Chris Demetriou <cgd@broadcom.com>
70
71 * mips.igen (EI, DI): Remove.
72
80551777
CD		 732003-01-05 Richard Sandiford <rsandifo@redhat.com>
74
75 * Makefile.in (tmp-run-multi): Fix mips16 filter.
76
4c54fc26
CD		 772003-01-04 Richard Sandiford <rsandifo@redhat.com>
78 Andrew Cagney <ac131313@redhat.com>
79 Gavin Romig-Koch <gavin@redhat.com>
80 Graydon Hoare <graydon@redhat.com>
81 Aldy Hernandez <aldyh@redhat.com>
82 Dave Brolley <brolley@redhat.com>
83 Chris Demetriou <cgd@broadcom.com>
84
85 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
86 (sim_mach_default): New variable.
87 (mips64vr-*-*, mips64vrel-*-*): New configurations.
88 Add a new simulator generator, MULTI.
89 * configure: Regenerate.
90 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
91 (multi-run.o): New dependency.
92 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
93 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
94 (tmp-multi): Combine them.
95 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
96 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
97 (distclean-extra): New rule.
98 * sim-main.h: Include bfd.h.
99 (MIPS_MACH): New macro.
100 * mips.igen (vr4120, vr5400, vr5500): New models.
101 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
102 * vr.igen: Replace with new version.
103
e6c674b8
CD		 1042003-01-04 Chris Demetriou <cgd@broadcom.com>
105
106 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
107 * configure: Regenerate.
108
28f50ac8
CD		 1092002-12-31 Chris Demetriou <cgd@broadcom.com>
110
111 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
112 * mips.igen: Remove all invocations of check_branch_bug and
113 mark_branch_bug.
114
5071ffe6
CD		 1152002-12-16 Chris Demetriou <cgd@broadcom.com>
116
117 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
118
06e7837e
CD		 1192002-07-30 Chris Demetriou <cgd@broadcom.com>
120
121 * mips.igen (do_load_double, do_store_double): New functions.
122 (LDC1, SDC1): Rename to...
123 (LDC1b, SDC1b): respectively.
124 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
125
2265c243
MS		 1262002-07-29 Michael Snyder <msnyder@redhat.com>
127
128 * cp1.c (fp_recip2): Modify initialization expression so that
129 GCC will recognize it as constant.
130
a2f8b4f3
CD		 1312002-06-18 Chris Demetriou <cgd@broadcom.com>
132
133 * mdmx.c (SD_): Delete.
134 (Unpredictable): Re-define, for now, to directly invoke
135 unpredictable_action().
136 (mdmx_acc_op): Fix error in .ob immediate handling.
137
b4b6c939
AC		 1382002-06-18 Andrew Cagney <cagney@redhat.com>
139
140 * interp.c (sim_firmware_command): Initialize `address'.
141
c8cca39f
AC		 1422002-06-16 Andrew Cagney <ac131313@redhat.com>
143
144 * configure: Regenerated to track ../common/aclocal.m4 changes.
145
e7e81181
CD		 1462002-06-14 Chris Demetriou <cgd@broadcom.com>
147 Ed Satterthwaite <ehs@broadcom.com>
148
149 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
150 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
151 * mips.igen: Include mips3d.igen.
152 (mips3d): New model name for MIPS-3D ASE instructions.
153 (CVT.W.fmt): Don't use this instruction for word (source) format
154 instructions.
155 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
156 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
157 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
158 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
159 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
160 (RSquareRoot1, RSquareRoot2): New macros.
161 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
162 (fp_rsqrt2): New functions.
163 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
164 * configure: Regenerate.
165
3a2b820e 1662002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 167 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 168
169 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
170 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
171 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
172 (convert): Note that this function is not used for paired-single
173 format conversions.
174 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
175 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
176 (check_fmt_p): Enable paired-single support.
177 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
178 (PUU.PS): New instructions.
179 (CVT.S.fmt): Don't use this instruction for paired-single format
180 destinations.
181 * sim-main.h (FP_formats): New value 'fmt_ps.'
182 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
183 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
184
d18ea9c2
CD		 1852002-06-12 Chris Demetriou <cgd@broadcom.com>
186
187 * mips.igen: Fix formatting of function calls in
188 many FP operations.
189
95fd5cee
CD		 1902002-06-12 Chris Demetriou <cgd@broadcom.com>
191
192 * mips.igen (MOVN, MOVZ): Trace result.
193 (TNEI): Print "tnei" as the opcode name in traces.
194 (CEIL.W): Add disassembly string for traces.
195 (RSQRT.fmt): Make location of disassembly string consistent
196 with other instructions.
197
4f0d55ae
CD		 1982002-06-12 Chris Demetriou <cgd@broadcom.com>
199
200 * mips.igen (X): Delete unused function.
201
3c25f8c7
AC		 2022002-06-08 Andrew Cagney <cagney@redhat.com>
203
204 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
205
f3c08b7e
CD		 2062002-06-07 Chris Demetriou <cgd@broadcom.com>
207 Ed Satterthwaite <ehs@broadcom.com>
208
209 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
210 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
211 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
212 (fp_nmsub): New prototypes.
213 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
214 (NegMultiplySub): New defines.
215 * mips.igen (RSQRT.fmt): Use RSquareRoot().
216 (MADD.D, MADD.S): Replace with...
217 (MADD.fmt): New instruction.
218 (MSUB.D, MSUB.S): Replace with...
219 (MSUB.fmt): New instruction.
220 (NMADD.D, NMADD.S): Replace with...
221 (NMADD.fmt): New instruction.
222 (NMSUB.D, MSUB.S): Replace with...
223 (NMSUB.fmt): New instruction.
224
52714ff9
CD		 2252002-06-07 Chris Demetriou <cgd@broadcom.com>
226 Ed Satterthwaite <ehs@broadcom.com>
227
228 * cp1.c: Fix more comment spelling and formatting.
229 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
230 (denorm_mode): New function.
231 (fpu_unary, fpu_binary): Round results after operation, collect
232 status from rounding operations, and update the FCSR.
233 (convert): Collect status from integer conversions and rounding
234 operations, and update the FCSR. Adjust NaN values that result
235 from conversions. Convert to use sim_io_eprintf rather than
236 fprintf, and remove some debugging code.
237 * cp1.h (fenr_FS): New define.
238
577d8c4b
CD		 2392002-06-07 Chris Demetriou <cgd@broadcom.com>
240
241 * cp1.c (convert): Remove unusable debugging code, and move MIPS
242 rounding mode to sim FP rounding mode flag conversion code into...
243 (rounding_mode): New function.
244
196496ed
CD		 2452002-06-07 Chris Demetriou <cgd@broadcom.com>
246
247 * cp1.c: Clean up formatting of a few comments.
248 (value_fpr): Reformat switch statement.
249
cfe9ea23
CD		 2502002-06-06 Chris Demetriou <cgd@broadcom.com>
251 Ed Satterthwaite <ehs@broadcom.com>
252
253 * cp1.h: New file.
254 * sim-main.h: Include cp1.h.
255 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
256 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
257 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
258 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
259 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
260 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
261 * cp1.c: Don't include sim-fpu.h; already included by
262 sim-main.h. Clean up formatting of some comments.
263 (NaN, Equal, Less): Remove.
264 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
265 (fp_cmp): New functions.
266 * mips.igen (do_c_cond_fmt): Remove.
267 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
268 Compare. Add result tracing.
269 (CxC1): Remove, replace with...
270 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
271 (DMxC1): Remove, replace with...
272 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
273 (MxC1): Remove, replace with...
274 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
275
ee7254b0
CD		 2762002-06-04 Chris Demetriou <cgd@broadcom.com>
277
278 * sim-main.h (FGRIDX): Remove, replace all uses with...
279 (FGR_BASE): New macro.
280 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
281 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
282 (NR_FGR, FGR): Likewise.
283 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
284 * mips.igen: Likewise.
285
d3eb724f
CD		 2862002-06-04 Chris Demetriou <cgd@broadcom.com>
287
288 * cp1.c: Add an FSF Copyright notice to this file.
289
ba46ddd0
CD		 2902002-06-04 Chris Demetriou <cgd@broadcom.com>
291 Ed Satterthwaite <ehs@broadcom.com>
292
293 * cp1.c (Infinity): Remove.
294 * sim-main.h (Infinity): Likewise.
295
296 * cp1.c (fp_unary, fp_binary): New functions.
297 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
298 (fp_sqrt): New functions, implemented in terms of the above.
299 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
300 (Recip, SquareRoot): Remove (replaced by functions above).
301 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
302 (fp_recip, fp_sqrt): New prototypes.
303 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
304 (Recip, SquareRoot): Replace prototypes with #defines which
305 invoke the functions above.
306
18d8a52d
CD		 3072002-06-03 Chris Demetriou <cgd@broadcom.com>
308
309 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
310 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
311 file, remove PARAMS from prototypes.
312 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
313 simulator state arguments.
314 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
315 pass simulator state arguments.
316 * cp1.c (SD): Redefine as CPU_STATE(cpu).
317 (store_fpr, convert): Remove 'sd' argument.
318 (value_fpr): Likewise. Convert to use 'SD' instead.
319
0f154cbd
CD		 3202002-06-03 Chris Demetriou <cgd@broadcom.com>
321
322 * cp1.c (Min, Max): Remove #if 0'd functions.
323 * sim-main.h (Min, Max): Remove.
324
e80fc152
CD		 3252002-06-03 Chris Demetriou <cgd@broadcom.com>
326
327 * cp1.c: fix formatting of switch case and default labels.
328 * interp.c: Likewise.
329 * sim-main.c: Likewise.
330
bad673a9
CD		 3312002-06-03 Chris Demetriou <cgd@broadcom.com>
332
333 * cp1.c: Clean up comments which describe FP formats.
334 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
335
7cbea089
CD		 3362002-06-03 Chris Demetriou <cgd@broadcom.com>
337 Ed Satterthwaite <ehs@broadcom.com>
338
339 * configure.in (mipsisa64sb1*-*-*): New target for supporting
340 Broadcom SiByte SB-1 processor configurations.
341 * configure: Regenerate.
342 * sb1.igen: New file.
343 * mips.igen: Include sb1.igen.
344 (sb1): New model.
345 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
346 * mdmx.igen: Add "sb1" model to all appropriate functions and
347 instructions.
348 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
349 (ob_func, ob_acc): Reference the above.
350 (qh_acc): Adjust to keep the same size as ob_acc.
351 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
352 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
353
909daa82
CD		 3542002-06-03 Chris Demetriou <cgd@broadcom.com>
355
356 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
357
f4f1b9f1
CD		 3582002-06-02 Chris Demetriou <cgd@broadcom.com>
359 Ed Satterthwaite <ehs@broadcom.com>
360
361 * mips.igen (mdmx): New (pseudo-)model.
362 * mdmx.c, mdmx.igen: New files.
363 * Makefile.in (SIM_OBJS): Add mdmx.o.
364 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
365 New typedefs.
366 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
367 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
368 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
369 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
370 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
371 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
372 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
373 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
374 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
375 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
376 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
377 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
378 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
379 (qh_fmtsel): New macros.
380 (_sim_cpu): New member "acc".
381 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
382 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
383
5accf1ff
CD		 3842002-05-01 Chris Demetriou <cgd@broadcom.com>
385
386 * interp.c: Use 'deprecated' rather than 'depreciated.'
387 * sim-main.h: Likewise.
388
402586aa
CD		 3892002-05-01 Chris Demetriou <cgd@broadcom.com>
390
391 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
392 which wouldn't compile anyway.
393 * sim-main.h (unpredictable_action): New function prototype.
394 (Unpredictable): Define to call igen function unpredictable().
395 (NotWordValue): New macro to call igen function not_word_value().
396 (UndefinedResult): Remove.
397 * interp.c (undefined_result): Remove.
398 (unpredictable_action): New function.
399 * mips.igen (not_word_value, unpredictable): New functions.
400 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
401 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
402 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
403 NotWordValue() to check for unpredictable inputs, then
404 Unpredictable() to handle them.
405
c9b9995a
CD		 4062002-02-24 Chris Demetriou <cgd@broadcom.com>
407
408 * mips.igen: Fix formatting of calls to Unpredictable().
409
e1015982
AC		 4102002-04-20 Andrew Cagney <ac131313@redhat.com>
411
412 * interp.c (sim_open): Revert previous change.
413
b882a66b
AO		 4142002-04-18 Alexandre Oliva <aoliva@redhat.com>
415
416 * interp.c (sim_open): Disable chunk of code that wrote code in
417 vector table entries.
418
c429b7dd
CD		 4192002-03-19 Chris Demetriou <cgd@broadcom.com>
420
421 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
422 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
423 unused definitions.
424
37d146fa
CD		 4252002-03-19 Chris Demetriou <cgd@broadcom.com>
426
427 * cp1.c: Fix many formatting issues.
428
07892c0b
CD		 4292002-03-19 Chris G. Demetriou <cgd@broadcom.com>
430
431 * cp1.c (fpu_format_name): New function to replace...
432 (DOFMT): This. Delete, and update all callers.
433 (fpu_rounding_mode_name): New function to replace...
434 (RMMODE): This. Delete, and update all callers.
435
487f79b7
CD		 4362002-03-19 Chris G. Demetriou <cgd@broadcom.com>
437
438 * interp.c: Move FPU support routines from here to...
439 * cp1.c: Here. New file.
440 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
441 (cp1.o): New target.
442
1e799e28
CD		 4432002-03-12 Chris Demetriou <cgd@broadcom.com>
444
445 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
446 * mips.igen (mips32, mips64): New models, add to all instructions
447 and functions as appropriate.
448 (loadstore_ea, check_u64): New variant for model mips64.
449 (check_fmt_p): New variant for models mipsV and mips64, remove
450 mipsV model marking fro other variant.
451 (SLL) Rename to...
452 (SLLa) this.
453 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
454 for mips32 and mips64.
455 (DCLO, DCLZ): New instructions for mips64.
456
82f728db
CD		 4572002-03-07 Chris Demetriou <cgd@broadcom.com>
458
459 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
460 immediate or code as a hex value with the "%#lx" format.
461 (ANDI): Likewise, and fix printed instruction name.
462
b96e7ef1
CD		 4632002-03-05 Chris Demetriou <cgd@broadcom.com>
464
465 * sim-main.h (UndefinedResult, Unpredictable): New macros
466 which currently do nothing.
467
d35d4f70
CD		 4682002-03-05 Chris Demetriou <cgd@broadcom.com>
469
470 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
471 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
472 (status_CU3): New definitions.
473
474 * sim-main.h (ExceptionCause): Add new values for MIPS32
475 and MIPS64: MDMX, MCheck, CacheErr. Update comments
476 for DebugBreakPoint and NMIReset to note their status in
477 MIPS32 and MIPS64.
478 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
479 (SignalExceptionCacheErr): New exception macros.
480
3ad6f714
CD		 4812002-03-05 Chris Demetriou <cgd@broadcom.com>
482
483 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
484 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
485 is always enabled.
486 (SignalExceptionCoProcessorUnusable): Take as argument the
487 unusable coprocessor number.
488
86b77b47
CD		 4892002-03-05 Chris Demetriou <cgd@broadcom.com>
490
491 * mips.igen: Fix formatting of all SignalException calls.
492
97a88e93 4932002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 494
495 * sim-main.h (SIGNEXTEND): Remove.
496
97a88e93 4972002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 498
499 * mips.igen: Remove gencode comment from top of file, fix
500 spelling in another comment.
501
97a88e93 5022002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 503
504 * mips.igen (check_fmt, check_fmt_p): New functions to check
505 whether specific floating point formats are usable.
506 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
507 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
508 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
509 Use the new functions.
510 (do_c_cond_fmt): Remove format checks...
511 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
512
97a88e93 5132002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 514
515 * mips.igen: Fix formatting of check_fpu calls.
516
41774c9d
CD		 5172002-03-03 Chris Demetriou <cgd@broadcom.com>
518
519 * mips.igen (FLOOR.L.fmt): Store correct destination register.
520
4a0bd876
CD		 5212002-03-03 Chris Demetriou <cgd@broadcom.com>
522
523 * mips.igen: Remove whitespace at end of lines.
524
09297648
CD		 5252002-03-02 Chris Demetriou <cgd@broadcom.com>
526
527 * mips.igen (loadstore_ea): New function to do effective
528 address calculations.
529 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
530 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
531 CACHE): Use loadstore_ea to do effective address computations.
532
043b7057
CD		 5332002-03-02 Chris Demetriou <cgd@broadcom.com>
534
535 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
536 * mips.igen (LL, CxC1, MxC1): Likewise.
537
c1e8ada4
CD		 5382002-03-02 Chris Demetriou <cgd@broadcom.com>
539
540 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
541 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
542 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
543 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
544 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
545 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
546 Don't split opcode fields by hand, use the opcode field values
547 provided by igen.
548
3e1dca16
CD		 5492002-03-01 Chris Demetriou <cgd@broadcom.com>
550
551 * mips.igen (do_divu): Fix spacing.
552
553 * mips.igen (do_dsllv): Move to be right before DSLLV,
554 to match the rest of the do_<shift> functions.
555
fff8d27d
CD		 5562002-03-01 Chris Demetriou <cgd@broadcom.com>
557
558 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
559 DSRL32, do_dsrlv): Trace inputs and results.
560
0d3e762b
CD		 5612002-03-01 Chris Demetriou <cgd@broadcom.com>
562
563 * mips.igen (CACHE): Provide instruction-printing string.
564
565 * interp.c (signal_exception): Comment tokens after #endif.
566
eb5fcf93
CD		 5672002-02-28 Chris Demetriou <cgd@broadcom.com>
568
569 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
570 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
571 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
572 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
573 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
574 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
575 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
576 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
577
bb22bd7d
CD		 5782002-02-28 Chris Demetriou <cgd@broadcom.com>
579
580 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
581 instruction-printing string.
582 (LWU): Use '64' as the filter flag.
583
91a177cf
CD		 5842002-02-28 Chris Demetriou <cgd@broadcom.com>
585
586 * mips.igen (SDXC1): Fix instruction-printing string.
587
387f484a
CD		 5882002-02-28 Chris Demetriou <cgd@broadcom.com>
589
590 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
591 filter flags "32,f".
592
3d81f391
CD		 5932002-02-27 Chris Demetriou <cgd@broadcom.com>
594
595 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
596 as the filter flag.
597
af5107af
CD		 5982002-02-27 Chris Demetriou <cgd@broadcom.com>
599
600 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
601 add a comma) so that it more closely match the MIPS ISA
602 documentation opcode partitioning.
603 (PREF): Put useful names on opcode fields, and include
604 instruction-printing string.
605
ca971540
CD		 6062002-02-27 Chris Demetriou <cgd@broadcom.com>
607
608 * mips.igen (check_u64): New function which in the future will
609 check whether 64-bit instructions are usable and signal an
610 exception if not. Currently a no-op.
611 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
612 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
613 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
614 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
615
616 * mips.igen (check_fpu): New function which in the future will
617 check whether FPU instructions are usable and signal an exception
618 if not. Currently a no-op.
619 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
620 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
621 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
622 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
623 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
624 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
625 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
626 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
627
1c47a468
CD		 6282002-02-27 Chris Demetriou <cgd@broadcom.com>
629
630 * mips.igen (do_load_left, do_load_right): Move to be immediately
631 following do_load.
632 (do_store_left, do_store_right): Move to be immediately following
633 do_store.
634
603a98e7
CD		 6352002-02-27 Chris Demetriou <cgd@broadcom.com>
636
637 * mips.igen (mipsV): New model name. Also, add it to
638 all instructions and functions where it is appropriate.
639
c5d00cc7
CD		 6402002-02-18 Chris Demetriou <cgd@broadcom.com>
641
642 * mips.igen: For all functions and instructions, list model
643 names that support that instruction one per line.
644
074e9cb8
CD		 6452002-02-11 Chris Demetriou <cgd@broadcom.com>
646
647 * mips.igen: Add some additional comments about supported
648 models, and about which instructions go where.
649 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
650 order as is used in the rest of the file.
651
9805e229
CD		 6522002-02-11 Chris Demetriou <cgd@broadcom.com>
653
654 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
655 indicating that ALU32_END or ALU64_END are there to check
656 for overflow.
657 (DADD): Likewise, but also remove previous comment about
658 overflow checking.
659
f701dad2
CD		 6602002-02-10 Chris Demetriou <cgd@broadcom.com>
661
662 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
663 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
664 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
665 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
666 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
667 fields (i.e., add and move commas) so that they more closely
668 match the MIPS ISA documentation opcode partitioning.
669
6702002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 671
672 * mips.igen (ADDI): Print immediate value.
673 (BREAK): Print code.
674 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
675 (SLL): Print "nop" specially, and don't run the code
676 that does the shift for the "nop" case.
677
9e52972e
FF		 6782001-11-17 Fred Fish <fnf@redhat.com>
679
680 * sim-main.h (float_operation): Move enum declaration outside
681 of _sim_cpu struct declaration.
682
c0efbca4
JB		 6832001-04-12 Jim Blandy <jimb@redhat.com>
684
685 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
686 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
687 set of the FCSR.
688 * sim-main.h (COCIDX): Remove definition; this isn't supported by
689 PENDING_FILL, and you can get the intended effect gracefully by
690 calling PENDING_SCHED directly.
691
fb891446
BE		 6922001-02-23 Ben Elliston <bje@redhat.com>
693
694 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
695 already defined elsewhere.
696
8030f857
BE		 6972001-02-19 Ben Elliston <bje@redhat.com>
698
699 * sim-main.h (sim_monitor): Return an int.
700 * interp.c (sim_monitor): Add return values.
701 (signal_exception): Handle error conditions from sim_monitor.
702
56b48a7a
CD		 7032001-02-08 Ben Elliston <bje@redhat.com>
704
705 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
706 (store_memory): Likewise, pass cia to sim_core_write*.
707
d3ee60d9
FCE		 7082000-10-19 Frank Ch. Eigler <fche@redhat.com>
709
710 On advice from Chris G. Demetriou <cgd@sibyte.com>:
711 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
712
071da002
AC		 713Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
714
715 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
716 * Makefile.in: Don't delete *.igen when cleaning directory.
717
a28c02cd
AC		 718Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
719
720 * m16.igen (break): Call SignalException not sim_engine_halt.
721
80ee11fa
AC		 722Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
723
724 From Jason Eckhardt:
725 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
726
673388c0
AC		 727Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
728
729 * mips.igen (MxC1, DMxC1): Fix printf formatting.
730
4c0deff4
NC		 7312000-05-24 Michael Hayes <mhayes@cygnus.com>
732
733 * mips.igen (do_dmultx): Fix typo.
734
eb2d80b4
AC		 735Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
736
737 * configure: Regenerated to track ../common/aclocal.m4 changes.
738
dd37a34b
AC		 739Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
740
741 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
742
4c0deff4
NC		 7432000-04-12 Frank Ch. Eigler <fche@redhat.com>
744
745 * sim-main.h (GPR_CLEAR): Define macro.
746
e30db738
AC		 747Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
748
749 * interp.c (decode_coproc): Output long using %lx and not %s.
750
cb7450ea
FCE		 7512000-03-21 Frank Ch. Eigler <fche@redhat.com>
752
753 * interp.c (sim_open): Sort & extend dummy memory regions for
754 --board=jmr3904 for eCos.
755
a3027dd7
FCE		 7562000-03-02 Frank Ch. Eigler <fche@redhat.com>
757
758 * configure: Regenerated.
759
760Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
761
762 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
763 calls, conditional on the simulator being in verbose mode.
764
dfcd3bfb
JM		 765Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
766
767 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
768 cache don't get ReservedInstruction traps.
769
c2d11a7d
JM		 7701999-11-29 Mark Salter <msalter@cygnus.com>
771
772 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
773 to clear status bits in sdisr register. This is how the hardware works.
774
775 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
776 being used by cygmon.
777
4ce44c66
JM		 7781999-11-11 Andrew Haley <aph@cygnus.com>
779
780 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
781 instructions.
782
cff3e48b
JM		 783Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
784
785 * mips.igen (MULT): Correct previous mis-applied patch.
786
d4f3574e
SS		 787Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
788
789 * mips.igen (delayslot32): Handle sequence like
790 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
791 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
792 (MULT): Actually pass the third register...
793
7941999-09-03 Mark Salter <msalter@cygnus.com>
795
796 * interp.c (sim_open): Added more memory aliases for additional
797 hardware being touched by cygmon on jmr3904 board.
798
799Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
800
801 * configure: Regenerated to track ../common/aclocal.m4 changes.
802
a0b3c4fd
JM		 803Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
804
805 * interp.c (sim_store_register): Handle case where client - GDB -
806 specifies that a 4 byte register is 8 bytes in size.
807 (sim_fetch_register): Ditto.
808
adf40b2e
JM		 8091999-07-14 Frank Ch. Eigler <fche@cygnus.com>
810
811 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
812 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
813 (idt_monitor_base): Base address for IDT monitor traps.
814 (pmon_monitor_base): Ditto for PMON.
815 (lsipmon_monitor_base): Ditto for LSI PMON.
816 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
817 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
818 (sim_firmware_command): New function.
819 (mips_option_handler): Call it for OPTION_FIRMWARE.
820 (sim_open): Allocate memory for idt_monitor region. If "--board"
821 option was given, add no monitor by default. Add BREAK hooks only if
822 monitors are also there.
823
43e526b9
JM		 824Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
825
826 * interp.c (sim_monitor): Flush output before reading input.
827
828Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
829
830 * tconfig.in (SIM_HANDLES_LMA): Always define.
831
832Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
833
834 From Mark Salter <msalter@cygnus.com>:
835 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
836 (sim_open): Add setup for BSP board.
837
9846de1b
JM		 838Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
839
840 * mips.igen (MULT, MULTU): Add syntax for two operand version.
841 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
842 them as unimplemented.
843
cd0fc7c3
SS		 8441999-05-08 Felix Lee <flee@cygnus.com>
845
846 * configure: Regenerated to track ../common/aclocal.m4 changes.
847
7a292a7a
SS		 8481999-04-21 Frank Ch. Eigler <fche@cygnus.com>
849
850 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
851
852Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
853
854 * configure.in: Any mips64vr5*-*-* target should have
855 -DTARGET_ENABLE_FR=1.
856 (default_endian): Any mips64vr*el-*-* target should default to
857 LITTLE_ENDIAN.
858 * configure: Re-generate.
859
8601999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
861
862 * mips.igen (ldl): Extend from _16_, not 32.
863
864Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
865
866 * interp.c (sim_store_register): Force registers written to by GDB
867 into an un-interpreted state.
868
c906108c
SS		 8691999-02-05 Frank Ch. Eigler <fche@cygnus.com>
870
871 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
872 CPU, start periodic background I/O polls.
873 (tx3904sio_poll): New function: periodic I/O poller.
874
8751998-12-30 Frank Ch. Eigler <fche@cygnus.com>
876
877 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
878
879Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
880
881 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
882 case statement.
883
8841998-12-29 Frank Ch. Eigler <fche@cygnus.com>
885
886 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
887 (load_word): Call SIM_CORE_SIGNAL hook on error.
888 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
889 starting. For exception dispatching, pass PC instead of NULL_CIA.
890 (decode_coproc): Use COP0_BADVADDR to store faulting address.
891 * sim-main.h (COP0_BADVADDR): Define.
892 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
893 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
894 (_sim_cpu): Add exc_* fields to store register value snapshots.
895 * mips.igen (*): Replace memory-related SignalException* calls
896 with references to SIM_CORE_SIGNAL hook.
897
898 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
899 fix.
900 * sim-main.c (*): Minor warning cleanups.
901
9021998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
903
904 * m16.igen (DADDIU5): Correct type-o.
905
906Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
907
908 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
909 variables.
910
911Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
912
913 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
914 to include path.
915 (interp.o): Add dependency on itable.h
916 (oengine.c, gencode): Delete remaining references.
917 (BUILT_SRC_FROM_GEN): Clean up.
918
9191998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
920
921 * vr4run.c: New.
922 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
923 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
924 tmp-run-hack) : New.
925 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
926 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
927 Drop the "64" qualifier to get the HACK generator working.
928 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
929 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
930 qualifier to get the hack generator working.
931 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
932 (DSLL): Use do_dsll.
933 (DSLLV): Use do_dsllv.
934 (DSRA): Use do_dsra.
935 (DSRL): Use do_dsrl.
936 (DSRLV): Use do_dsrlv.
937 (BC1): Move *vr4100 to get the HACK generator working.
938 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
939 get the HACK generator working.
940 (MACC) Rename to get the HACK generator working.
941 (DMACC,MACCS,DMACCS): Add the 64.
942
9431998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
944
945 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
946 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
947
9481998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
949
950 * mips/interp.c (DEBUG): Cleanups.
951
9521998-12-10 Frank Ch. Eigler <fche@cygnus.com>
953
954 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
955 (tx3904sio_tickle): fflush after a stdout character output.
956
9571998-12-03 Frank Ch. Eigler <fche@cygnus.com>
958
959 * interp.c (sim_close): Uninstall modules.
960
961Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
962
963 * sim-main.h, interp.c (sim_monitor): Change to global
964 function.
965
966Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
967
968 * configure.in (vr4100): Only include vr4100 instructions in
969 simulator.
970 * configure: Re-generate.
971 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
972
973Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
974
975 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
976 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
977 true alternative.
978
979 * configure.in (sim_default_gen, sim_use_gen): Replace with
980 sim_gen.
981 (--enable-sim-igen): Delete config option. Always using IGEN.
982 * configure: Re-generate.
983
984 * Makefile.in (gencode): Kill, kill, kill.
985 * gencode.c: Ditto.
986
987Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
988
989 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
990 bit mips16 igen simulator.
991 * configure: Re-generate.
992
993 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
994 as part of vr4100 ISA.
995 * vr.igen: Mark all instructions as 64 bit only.
996
997Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
998
999 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1000 Pacify GCC.
1001
1002Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1003
1004 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1005 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1006 * configure: Re-generate.
1007
1008 * m16.igen (BREAK): Define breakpoint instruction.
1009 (JALX32): Mark instruction as mips16 and not r3900.
1010 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1011
1012 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1013
1014Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1015
1016 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1017 insn as a debug breakpoint.
1018
1019 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1020 pending.slot_size.
1021 (PENDING_SCHED): Clean up trace statement.
1022 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1023 (PENDING_FILL): Delay write by only one cycle.
1024 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1025
1026 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1027 of pending writes.
1028 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1029 32 & 64.
1030 (pending_tick): Move incrementing of index to FOR statement.
1031 (pending_tick): Only update PENDING_OUT after a write has occured.
1032
1033 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1034 build simulator.
1035 * configure: Re-generate.
1036
1037 * interp.c (sim_engine_run OLD): Delete explicit call to
1038 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1039
1040Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1041
1042 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1043 interrupt level number to match changed SignalExceptionInterrupt
1044 macro.
1045
1046Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1047
1048 * interp.c: #include "itable.h" if WITH_IGEN.
1049 (get_insn_name): New function.
1050 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1051 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1052
1053Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1054
1055 * configure: Rebuilt to inhale new common/aclocal.m4.
1056
1057Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1058
1059 * dv-tx3904sio.c: Include sim-assert.h.
1060
1061Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1062
1063 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1064 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1065 Reorganize target-specific sim-hardware checks.
1066 * configure: rebuilt.
1067 * interp.c (sim_open): For tx39 target boards, set
1068 OPERATING_ENVIRONMENT, add tx3904sio devices.
1069 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1070 ROM executables. Install dv-sockser into sim-modules list.
1071
1072 * dv-tx3904irc.c: Compiler warning clean-up.
1073 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1074 frequent hw-trace messages.
1075
1076Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1077
1078 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1079
1080Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1081
1082 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1083
1084 * vr.igen: New file.
1085 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1086 * mips.igen: Define vr4100 model. Include vr.igen.
1087Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1088
1089 * mips.igen (check_mf_hilo): Correct check.
1090
1091Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1092
1093 * sim-main.h (interrupt_event): Add prototype.
1094
1095 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1096 register_ptr, register_value.
1097 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1098
1099 * sim-main.h (tracefh): Make extern.
1100
1101Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1102
1103 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1104 Reduce unnecessarily high timer event frequency.
1105 * dv-tx3904cpu.c: Ditto for interrupt event.
1106
1107Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1108
1109 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1110 to allay warnings.
1111 (interrupt_event): Made non-static.
1112
1113 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1114 interchange of configuration values for external vs. internal
1115 clock dividers.
1116
1117Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1118
1119 * mips.igen (BREAK): Moved code to here for
1120 simulator-reserved break instructions.
1121 * gencode.c (build_instruction): Ditto.
1122 * interp.c (signal_exception): Code moved from here. Non-
1123 reserved instructions now use exception vector, rather
1124 than halting sim.
1125 * sim-main.h: Moved magic constants to here.
1126
1127Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1128
1129 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1130 register upon non-zero interrupt event level, clear upon zero
1131 event value.
1132 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1133 by passing zero event value.
1134 (*_io_{read,write}_buffer): Endianness fixes.
1135 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1136 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1137
1138 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1139 serial I/O and timer module at base address 0xFFFF0000.
1140
1141Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1142
1143 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1144 and BigEndianCPU.
1145
1146Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1147
1148 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1149 parts.
1150 * configure: Update.
1151
1152Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1153
1154 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1155 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1156 * configure.in: Include tx3904tmr in hw_device list.
1157 * configure: Rebuilt.
1158 * interp.c (sim_open): Instantiate three timer instances.
1159 Fix address typo of tx3904irc instance.
1160
1161Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1162
1163 * interp.c (signal_exception): SystemCall exception now uses
1164 the exception vector.
1165
1166Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1167
1168 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1169 to allay warnings.
1170
1171Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1172
1173 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1174
1175Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1178
1179 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1180 sim-main.h. Declare a struct hw_descriptor instead of struct
1181 hw_device_descriptor.
1182
1183Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1184
1185 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1186 right bits and then re-align left hand bytes to correct byte
1187 lanes. Fix incorrect computation in do_store_left when loading
1188 bytes from second word.
1189
1190Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1191
1192 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1193 * interp.c (sim_open): Only create a device tree when HW is
1194 enabled.
1195
1196 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1197 * interp.c (signal_exception): Ditto.
1198
1199Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1200
1201 * gencode.c: Mark BEGEZALL as LIKELY.
1202
1203Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1204
1205 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1206 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1207
1208Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1209
1210 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1211 modules. Recognize TX39 target with "mips*tx39" pattern.
1212 * configure: Rebuilt.
1213 * sim-main.h (*): Added many macros defining bits in
1214 TX39 control registers.
1215 (SignalInterrupt): Send actual PC instead of NULL.
1216 (SignalNMIReset): New exception type.
1217 * interp.c (board): New variable for future use to identify
1218 a particular board being simulated.
1219 (mips_option_handler,mips_options): Added "--board" option.
1220 (interrupt_event): Send actual PC.
1221 (sim_open): Make memory layout conditional on board setting.
1222 (signal_exception): Initial implementation of hardware interrupt
1223 handling. Accept another break instruction variant for simulator
1224 exit.
1225 (decode_coproc): Implement RFE instruction for TX39.
1226 (mips.igen): Decode RFE instruction as such.
1227 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1228 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1229 bbegin to implement memory map.
1230 * dv-tx3904cpu.c: New file.
1231 * dv-tx3904irc.c: New file.
1232
1233Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1234
1235 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1236
1237Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1238
1239 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1240 with calls to check_div_hilo.
1241
1242Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1243
1244 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1245 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1246 Add special r3900 version of do_mult_hilo.
1247 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1248 with calls to check_mult_hilo.
1249 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1250 with calls to check_div_hilo.
1251
1252Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1253
1254 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1255 Document a replacement.
1256
1257Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1258
1259 * interp.c (sim_monitor): Make mon_printf work.
1260
1261Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1262
1263 * sim-main.h (INSN_NAME): New arg `cpu'.
1264
1265Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1266
1267 * configure: Regenerated to track ../common/aclocal.m4 changes.
1268
1269Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1270
1271 * configure: Regenerated to track ../common/aclocal.m4 changes.
1272 * config.in: Ditto.
1273
1274Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1275
1276 * acconfig.h: New file.
1277 * configure.in: Reverted change of Apr 24; use sinclude again.
1278
1279Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1280
1281 * configure: Regenerated to track ../common/aclocal.m4 changes.
1282 * config.in: Ditto.
1283
1284Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1285
1286 * configure.in: Don't call sinclude.
1287
1288Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1289
1290 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1291
1292Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1293
1294 * mips.igen (ERET): Implement.
1295
1296 * interp.c (decode_coproc): Return sign-extended EPC.
1297
1298 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1299
1300 * interp.c (signal_exception): Do not ignore Trap.
1301 (signal_exception): On TRAP, restart at exception address.
1302 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1303 (signal_exception): Update.
1304 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1305 so that TRAP instructions are caught.
1306
1307Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1308
1309 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1310 contains HI/LO access history.
1311 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1312 (HIACCESS, LOACCESS): Delete, replace with
1313 (HIHISTORY, LOHISTORY): New macros.
1314 (CHECKHILO): Delete all, moved to mips.igen
1315
1316 * gencode.c (build_instruction): Do not generate checks for
1317 correct HI/LO register usage.
1318
1319 * interp.c (old_engine_run): Delete checks for correct HI/LO
1320 register usage.
1321
1322 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1323 check_mf_cycles): New functions.
1324 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1325 do_divu, domultx, do_mult, do_multu): Use.
1326
1327 * tx.igen ("madd", "maddu"): Use.
1328
1329Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1330
1331 * mips.igen (DSRAV): Use function do_dsrav.
1332 (SRAV): Use new function do_srav.
1333
1334 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1335 (B): Sign extend 11 bit immediate.
1336 (EXT-B*): Shift 16 bit immediate left by 1.
1337 (ADDIU*): Don't sign extend immediate value.
1338
1339Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1340
1341 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1342
1343 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1344 functions.
1345
1346 * mips.igen (delayslot32, nullify_next_insn): New functions.
1347 (m16.igen): Always include.
1348 (do_*): Add more tracing.
1349
1350 * m16.igen (delayslot16): Add NIA argument, could be called by a
1351 32 bit MIPS16 instruction.
1352
1353 * interp.c (ifetch16): Move function from here.
1354 * sim-main.c (ifetch16): To here.
1355
1356 * sim-main.c (ifetch16, ifetch32): Update to match current
1357 implementations of LH, LW.
1358 (signal_exception): Don't print out incorrect hex value of illegal
1359 instruction.
1360
1361Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1362
1363 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1364 instruction.
1365
1366 * m16.igen: Implement MIPS16 instructions.
1367
1368 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1369 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1370 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1371 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1372 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1373 bodies of corresponding code from 32 bit insn to these. Also used
1374 by MIPS16 versions of functions.
1375
1376 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1377 (IMEM16): Drop NR argument from macro.
1378
1379Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1380
1381 * Makefile.in (SIM_OBJS): Add sim-main.o.
1382
1383 * sim-main.h (address_translation, load_memory, store_memory,
1384 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1385 as INLINE_SIM_MAIN.
1386 (pr_addr, pr_uword64): Declare.
1387 (sim-main.c): Include when H_REVEALS_MODULE_P.
1388
1389 * interp.c (address_translation, load_memory, store_memory,
1390 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1391 from here.
1392 * sim-main.c: To here. Fix compilation problems.
1393
1394 * configure.in: Enable inlining.
1395 * configure: Re-config.
1396
1397Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1398
1399 * configure: Regenerated to track ../common/aclocal.m4 changes.
1400
1401Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1402
1403 * mips.igen: Include tx.igen.
1404 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1405 * tx.igen: New file, contains MADD and MADDU.
1406
1407 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1408 the hardwired constant `7'.
1409 (store_memory): Ditto.
1410 (LOADDRMASK): Move definition to sim-main.h.
1411
1412 mips.igen (MTC0): Enable for r3900.
1413 (ADDU): Add trace.
1414
1415 mips.igen (do_load_byte): Delete.
1416 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1417 do_store_right): New functions.
1418 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1419
1420 configure.in: Let the tx39 use igen again.
1421 configure: Update.
1422
1423Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1426 not an address sized quantity. Return zero for cache sizes.
1427
1428Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1429
1430 * mips.igen (r3900): r3900 does not support 64 bit integer
1431 operations.
1432
1433Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1434
1435 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1436 than igen one.
1437 * configure : Rebuild.
1438
1439Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440
1441 * configure: Regenerated to track ../common/aclocal.m4 changes.
1442
1443Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1444
1445 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1446
1447Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1448
1449 * configure: Regenerated to track ../common/aclocal.m4 changes.
1450 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1451
1452Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1453
1454 * configure: Regenerated to track ../common/aclocal.m4 changes.
1455
1456Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1457
1458 * interp.c (Max, Min): Comment out functions. Not yet used.
1459
1460Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1461
1462 * configure: Regenerated to track ../common/aclocal.m4 changes.
1463
1464Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1465
1466 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1467 configurable settings for stand-alone simulator.
1468
1469 * configure.in: Added X11 search, just in case.
1470
1471 * configure: Regenerated.
1472
1473Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1474
1475 * interp.c (sim_write, sim_read, load_memory, store_memory):
1476 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1477
1478Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1479
1480 * sim-main.h (GETFCC): Return an unsigned value.
1481
1482Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483
1484 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1485 (DADD): Result destination is RD not RT.
1486
1487Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1488
1489 * sim-main.h (HIACCESS, LOACCESS): Always define.
1490
1491 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1492
1493 * interp.c (sim_info): Delete.
1494
1495Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1496
1497 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1498 (mips_option_handler): New argument `cpu'.
1499 (sim_open): Update call to sim_add_option_table.
1500
1501Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1502
1503 * mips.igen (CxC1): Add tracing.
1504
1505Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1506
1507 * sim-main.h (Max, Min): Declare.
1508
1509 * interp.c (Max, Min): New functions.
1510
1511 * mips.igen (BC1): Add tracing.
1512
1513Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1514
1515 * interp.c Added memory map for stack in vr4100
1516
1517Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1518
1519 * interp.c (load_memory): Add missing "break"'s.
1520
1521Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * interp.c (sim_store_register, sim_fetch_register): Pass in
1524 length parameter. Return -1.
1525
1526Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1527
1528 * interp.c: Added hardware init hook, fixed warnings.
1529
1530Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1531
1532 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1533
1534Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1535
1536 * interp.c (ifetch16): New function.
1537
1538 * sim-main.h (IMEM32): Rename IMEM.
1539 (IMEM16_IMMED): Define.
1540 (IMEM16): Define.
1541 (DELAY_SLOT): Update.
1542
1543 * m16run.c (sim_engine_run): New file.
1544
1545 * m16.igen: All instructions except LB.
1546 (LB): Call do_load_byte.
1547 * mips.igen (do_load_byte): New function.
1548 (LB): Call do_load_byte.
1549
1550 * mips.igen: Move spec for insn bit size and high bit from here.
1551 * Makefile.in (tmp-igen, tmp-m16): To here.
1552
1553 * m16.dc: New file, decode mips16 instructions.
1554
1555 * Makefile.in (SIM_NO_ALL): Define.
1556 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1557
1558Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1561 point unit to 32 bit registers.
1562 * configure: Re-generate.
1563
1564Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1565
1566 * configure.in (sim_use_gen): Make IGEN the default simulator
1567 generator for generic 32 and 64 bit mips targets.
1568 * configure: Re-generate.
1569
1570Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1571
1572 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1573 bitsize.
1574
1575 * interp.c (sim_fetch_register, sim_store_register): Read/write
1576 FGR from correct location.
1577 (sim_open): Set size of FGR's according to
1578 WITH_TARGET_FLOATING_POINT_BITSIZE.
1579
1580 * sim-main.h (FGR): Store floating point registers in a separate
1581 array.
1582
1583Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * configure: Regenerated to track ../common/aclocal.m4 changes.
1586
1587Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1588
1589 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1590
1591 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1592
1593 * interp.c (pending_tick): New function. Deliver pending writes.
1594
1595 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1596 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1597 it can handle mixed sized quantites and single bits.
1598
1599Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1600
1601 * interp.c (oengine.h): Do not include when building with IGEN.
1602 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1603 (sim_info): Ditto for PROCESSOR_64BIT.
1604 (sim_monitor): Replace ut_reg with unsigned_word.
1605 (*): Ditto for t_reg.
1606 (LOADDRMASK): Define.
1607 (sim_open): Remove defunct check that host FP is IEEE compliant,
1608 using software to emulate floating point.
1609 (value_fpr, ...): Always compile, was conditional on HASFPU.
1610
1611Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1612
1613 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1614 size.
1615
1616 * interp.c (SD, CPU): Define.
1617 (mips_option_handler): Set flags in each CPU.
1618 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1619 (sim_close): Do not clear STATE, deleted anyway.
1620 (sim_write, sim_read): Assume CPU zero's vm should be used for
1621 data transfers.
1622 (sim_create_inferior): Set the PC for all processors.
1623 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1624 argument.
1625 (mips16_entry): Pass correct nr of args to store_word, load_word.
1626 (ColdReset): Cold reset all cpu's.
1627 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1628 (sim_monitor, load_memory, store_memory, signal_exception): Use
1629 `CPU' instead of STATE_CPU.
1630
1631
1632 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1633 SD or CPU_.
1634
1635 * sim-main.h (signal_exception): Add sim_cpu arg.
1636 (SignalException*): Pass both SD and CPU to signal_exception.
1637 * interp.c (signal_exception): Update.
1638
1639 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1640 Ditto
1641 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1642 address_translation): Ditto
1643 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1644
1645Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1646
1647 * configure: Regenerated to track ../common/aclocal.m4 changes.
1648
1649Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1652
1653 * mips.igen (model): Map processor names onto BFD name.
1654
1655 * sim-main.h (CPU_CIA): Delete.
1656 (SET_CIA, GET_CIA): Define
1657
1658Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1659
1660 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1661 regiser.
1662
1663 * configure.in (default_endian): Configure a big-endian simulator
1664 by default.
1665 * configure: Re-generate.
1666
1667Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1668
1669 * configure: Regenerated to track ../common/aclocal.m4 changes.
1670
1671Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1672
1673 * interp.c (sim_monitor): Handle Densan monitor outbyte
1674 and inbyte functions.
1675
16761997-12-29 Felix Lee <flee@cygnus.com>
1677
1678 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1679
1680Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1681
1682 * Makefile.in (tmp-igen): Arrange for $zero to always be
1683 reset to zero after every instruction.
1684
1685Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1686
1687 * configure: Regenerated to track ../common/aclocal.m4 changes.
1688 * config.in: Ditto.
1689
1690Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1691
1692 * mips.igen (MSUB): Fix to work like MADD.
1693 * gencode.c (MSUB): Similarly.
1694
1695Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1696
1697 * configure: Regenerated to track ../common/aclocal.m4 changes.
1698
1699Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1700
1701 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1702
1703Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1704
1705 * sim-main.h (sim-fpu.h): Include.
1706
1707 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1708 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1709 using host independant sim_fpu module.
1710
1711Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1712
1713 * interp.c (signal_exception): Report internal errors with SIGABRT
1714 not SIGQUIT.
1715
1716 * sim-main.h (C0_CONFIG): New register.
1717 (signal.h): No longer include.
1718
1719 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1720
1721Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1722
1723 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1724
1725Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1726
1727 * mips.igen: Tag vr5000 instructions.
1728 (ANDI): Was missing mipsIV model, fix assembler syntax.
1729 (do_c_cond_fmt): New function.
1730 (C.cond.fmt): Handle mips I-III which do not support CC field
1731 separatly.
1732 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1733 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1734 in IV3.2 spec.
1735 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1736 vr5000 which saves LO in a GPR separatly.
1737
1738 * configure.in (enable-sim-igen): For vr5000, select vr5000
1739 specific instructions.
1740 * configure: Re-generate.
1741
1742Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1745
1746 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1747 fmt_uninterpreted_64 bit cases to switch. Convert to
1748 fmt_formatted,
1749
1750 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1751
1752 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1753 as specified in IV3.2 spec.
1754 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1755
1756Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1757
1758 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1759 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1760 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1761 PENDING_FILL versions of instructions. Simplify.
1762 (X): New function.
1763 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1764 instructions.
1765 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1766 a signed value.
1767 (MTHI, MFHI): Disable code checking HI-LO.
1768
1769 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1770 global.
1771 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1772
1773Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1774
1775 * gencode.c (build_mips16_operands): Replace IPC with cia.
1776
1777 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1778 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1779 IPC to `cia'.
1780 (UndefinedResult): Replace function with macro/function
1781 combination.
1782 (sim_engine_run): Don't save PC in IPC.
1783
1784 * sim-main.h (IPC): Delete.
1785
1786
1787 * interp.c (signal_exception, store_word, load_word,
1788 address_translation, load_memory, store_memory, cache_op,
1789 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1790 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1791 current instruction address - cia - argument.
1792 (sim_read, sim_write): Call address_translation directly.
1793 (sim_engine_run): Rename variable vaddr to cia.
1794 (signal_exception): Pass cia to sim_monitor
1795
1796 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1797 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1798 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1799
1800 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1801 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1802 SIM_ASSERT.
1803
1804 * interp.c (signal_exception): Pass restart address to
1805 sim_engine_restart.
1806
1807 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1808 idecode.o): Add dependency.
1809
1810 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1811 Delete definitions
1812 (DELAY_SLOT): Update NIA not PC with branch address.
1813 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1814
1815 * mips.igen: Use CIA not PC in branch calculations.
1816 (illegal): Call SignalException.
1817 (BEQ, ADDIU): Fix assembler.
1818
1819Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1820
1821 * m16.igen (JALX): Was missing.
1822
1823 * configure.in (enable-sim-igen): New configuration option.
1824 * configure: Re-generate.
1825
1826 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1827
1828 * interp.c (load_memory, store_memory): Delete parameter RAW.
1829 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1830 bypassing {load,store}_memory.
1831
1832 * sim-main.h (ByteSwapMem): Delete definition.
1833
1834 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1835
1836 * interp.c (sim_do_command, sim_commands): Delete mips specific
1837 commands. Handled by module sim-options.
1838
1839 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1840 (WITH_MODULO_MEMORY): Define.
1841
1842 * interp.c (sim_info): Delete code printing memory size.
1843
1844 * interp.c (mips_size): Nee sim_size, delete function.
1845 (power2): Delete.
1846 (monitor, monitor_base, monitor_size): Delete global variables.
1847 (sim_open, sim_close): Delete code creating monitor and other
1848 memory regions. Use sim-memopts module, via sim_do_commandf, to
1849 manage memory regions.
1850 (load_memory, store_memory): Use sim-core for memory model.
1851
1852 * interp.c (address_translation): Delete all memory map code
1853 except line forcing 32 bit addresses.
1854
1855Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1856
1857 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1858 trace options.
1859
1860 * interp.c (logfh, logfile): Delete globals.
1861 (sim_open, sim_close): Delete code opening & closing log file.
1862 (mips_option_handler): Delete -l and -n options.
1863 (OPTION mips_options): Ditto.
1864
1865 * interp.c (OPTION mips_options): Rename option trace to dinero.
1866 (mips_option_handler): Update.
1867
1868Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1869
1870 * interp.c (fetch_str): New function.
1871 (sim_monitor): Rewrite using sim_read & sim_write.
1872 (sim_open): Check magic number.
1873 (sim_open): Write monitor vectors into memory using sim_write.
1874 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1875 (sim_read, sim_write): Simplify - transfer data one byte at a
1876 time.
1877 (load_memory, store_memory): Clarify meaning of parameter RAW.
1878
1879 * sim-main.h (isHOST): Defete definition.
1880 (isTARGET): Mark as depreciated.
1881 (address_translation): Delete parameter HOST.
1882
1883 * interp.c (address_translation): Delete parameter HOST.
1884
1885Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1886
1887 * mips.igen:
1888
1889 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1890 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1891
1892Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1893
1894 * mips.igen: Add model filter field to records.
1895
1896Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1899
1900 interp.c (sim_engine_run): Do not compile function sim_engine_run
1901 when WITH_IGEN == 1.
1902
1903 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1904 target architecture.
1905
1906 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1907 igen. Replace with configuration variables sim_igen_flags /
1908 sim_m16_flags.
1909
1910 * m16.igen: New file. Copy mips16 insns here.
1911 * mips.igen: From here.
1912
1913Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1914
1915 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1916 to top.
1917 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1918
1919Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1920
1921 * gencode.c (build_instruction): Follow sim_write's lead in using
1922 BigEndianMem instead of !ByteSwapMem.
1923
1924Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1925
1926 * configure.in (sim_gen): Dependent on target, select type of
1927 generator. Always select old style generator.
1928
1929 configure: Re-generate.
1930
1931 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1932 targets.
1933 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1934 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1935 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1936 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1937 SIM_@sim_gen@_*, set by autoconf.
1938
1939Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1940
1941 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1942
1943 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1944 CURRENT_FLOATING_POINT instead.
1945
1946 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1947 (address_translation): Raise exception InstructionFetch when
1948 translation fails and isINSTRUCTION.
1949
1950 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1951 sim_engine_run): Change type of of vaddr and paddr to
1952 address_word.
1953 (address_translation, prefetch, load_memory, store_memory,
1954 cache_op): Change type of vAddr and pAddr to address_word.
1955
1956 * gencode.c (build_instruction): Change type of vaddr and paddr to
1957 address_word.
1958
1959Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1962 macro to obtain result of ALU op.
1963
1964Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1965
1966 * interp.c (sim_info): Call profile_print.
1967
1968Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1971
1972 * sim-main.h (WITH_PROFILE): Do not define, defined in
1973 common/sim-config.h. Use sim-profile module.
1974 (simPROFILE): Delete defintion.
1975
1976 * interp.c (PROFILE): Delete definition.
1977 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1978 (sim_close): Delete code writing profile histogram.
1979 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1980 Delete.
1981 (sim_engine_run): Delete code profiling the PC.
1982
1983Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1984
1985 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1986
1987 * interp.c (sim_monitor): Make register pointers of type
1988 unsigned_word*.
1989
1990 * sim-main.h: Make registers of type unsigned_word not
1991 signed_word.
1992
1993Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * interp.c (sync_operation): Rename from SyncOperation, make
1996 global, add SD argument.
1997 (prefetch): Rename from Prefetch, make global, add SD argument.
1998 (decode_coproc): Make global.
1999
2000 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2001
2002 * gencode.c (build_instruction): Generate DecodeCoproc not
2003 decode_coproc calls.
2004
2005 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2006 (SizeFGR): Move to sim-main.h
2007 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2008 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2009 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2010 sim-main.h.
2011 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2012 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2013 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2014 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2015 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2016 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2017
2018 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2019 exception.
2020 (sim-alu.h): Include.
2021 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2022 (sim_cia): Typedef to instruction_address.
2023
2024Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2025
2026 * Makefile.in (interp.o): Rename generated file engine.c to
2027 oengine.c.
2028
2029 * interp.c: Update.
2030
2031Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2034
2035Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2036
2037 * gencode.c (build_instruction): For "FPSQRT", output correct
2038 number of arguments to Recip.
2039
2040Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2041
2042 * Makefile.in (interp.o): Depends on sim-main.h
2043
2044 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2045
2046 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2047 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2048 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2049 STATE, DSSTATE): Define
2050 (GPR, FGRIDX, ..): Define.
2051
2052 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2053 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2054 (GPR, FGRIDX, ...): Delete macros.
2055
2056 * interp.c: Update names to match defines from sim-main.h
2057
2058Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2059
2060 * interp.c (sim_monitor): Add SD argument.
2061 (sim_warning): Delete. Replace calls with calls to
2062 sim_io_eprintf.
2063 (sim_error): Delete. Replace calls with sim_io_error.
2064 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2065 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2066 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2067 argument.
2068 (mips_size): Rename from sim_size. Add SD argument.
2069
2070 * interp.c (simulator): Delete global variable.
2071 (callback): Delete global variable.
2072 (mips_option_handler, sim_open, sim_write, sim_read,
2073 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2074 sim_size,sim_monitor): Use sim_io_* not callback->*.
2075 (sim_open): ZALLOC simulator struct.
2076 (PROFILE): Do not define.
2077
2078Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2079
2080 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2081 support.h with corresponding code.
2082
2083 * sim-main.h (word64, uword64), support.h: Move definition to
2084 sim-main.h.
2085 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2086
2087 * support.h: Delete
2088 * Makefile.in: Update dependencies
2089 * interp.c: Do not include.
2090
2091Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * interp.c (address_translation, load_memory, store_memory,
2094 cache_op): Rename to from AddressTranslation et.al., make global,
2095 add SD argument
2096
2097 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2098 CacheOp): Define.
2099
2100 * interp.c (SignalException): Rename to signal_exception, make
2101 global.
2102
2103 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2104
2105 * sim-main.h (SignalException, SignalExceptionInterrupt,
2106 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2107 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2108 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2109 Define.
2110
2111 * interp.c, support.h: Use.
2112
2113Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2114
2115 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2116 to value_fpr / store_fpr. Add SD argument.
2117 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2118 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2119
2120 * sim-main.h (ValueFPR, StoreFPR): Define.
2121
2122Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2123
2124 * interp.c (sim_engine_run): Check consistency between configure
2125 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2126 and HASFPU.
2127
2128 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2129 (mips_fpu): Configure WITH_FLOATING_POINT.
2130 (mips_endian): Configure WITH_TARGET_ENDIAN.
2131 * configure: Update.
2132
2133Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2134
2135 * configure: Regenerated to track ../common/aclocal.m4 changes.
2136
2137Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2138
2139 * configure: Regenerated.
2140
2141Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2142
2143 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2144
2145Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2146
2147 * gencode.c (print_igen_insn_models): Assume certain architectures
2148 include all mips* instructions.
2149 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2150 instruction.
2151
2152 * Makefile.in (tmp.igen): Add target. Generate igen input from
2153 gencode file.
2154
2155 * gencode.c (FEATURE_IGEN): Define.
2156 (main): Add --igen option. Generate output in igen format.
2157 (process_instructions): Format output according to igen option.
2158 (print_igen_insn_format): New function.
2159 (print_igen_insn_models): New function.
2160 (process_instructions): Only issue warnings and ignore
2161 instructions when no FEATURE_IGEN.
2162
2163Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2166 MIPS targets.
2167
2168Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169
2170 * configure: Regenerated to track ../common/aclocal.m4 changes.
2171
2172Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2175 SIM_RESERVED_BITS): Delete, moved to common.
2176 (SIM_EXTRA_CFLAGS): Update.
2177
2178Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2179
2180 * configure.in: Configure non-strict memory alignment.
2181 * configure: Regenerated to track ../common/aclocal.m4 changes.
2182
2183Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2184
2185 * configure: Regenerated to track ../common/aclocal.m4 changes.
2186
2187Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2188
2189 * gencode.c (SDBBP,DERET): Added (3900) insns.
2190 (RFE): Turn on for 3900.
2191 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2192 (dsstate): Made global.
2193 (SUBTARGET_R3900): Added.
2194 (CANCELDELAYSLOT): New.
2195 (SignalException): Ignore SystemCall rather than ignore and
2196 terminate. Add DebugBreakPoint handling.
2197 (decode_coproc): New insns RFE, DERET; and new registers Debug
2198 and DEPC protected by SUBTARGET_R3900.
2199 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2200 bits explicitly.
2201 * Makefile.in,configure.in: Add mips subtarget option.
2202 * configure: Update.
2203
2204Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2205
2206 * gencode.c: Add r3900 (tx39).
2207
2208
2209Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2210
2211 * gencode.c (build_instruction): Don't need to subtract 4 for
2212 JALR, just 2.
2213
2214Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2215
2216 * interp.c: Correct some HASFPU problems.
2217
2218Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2219
2220 * configure: Regenerated to track ../common/aclocal.m4 changes.
2221
2222Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2223
2224 * interp.c (mips_options): Fix samples option short form, should
2225 be `x'.
2226
2227Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2228
2229 * interp.c (sim_info): Enable info code. Was just returning.
2230
2231Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2232
2233 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2234 MFC0.
2235
2236Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2239 constants.
2240 (build_instruction): Ditto for LL.
2241
2242Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2243
2244 * configure: Regenerated to track ../common/aclocal.m4 changes.
2245
2246Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2247
2248 * configure: Regenerated to track ../common/aclocal.m4 changes.
2249 * config.in: Ditto.
2250
2251Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2252
2253 * interp.c (sim_open): Add call to sim_analyze_program, update
2254 call to sim_config.
2255
2256Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * interp.c (sim_kill): Delete.
2259 (sim_create_inferior): Add ABFD argument. Set PC from same.
2260 (sim_load): Move code initializing trap handlers from here.
2261 (sim_open): To here.
2262 (sim_load): Delete, use sim-hload.c.
2263
2264 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2265
2266Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2267
2268 * configure: Regenerated to track ../common/aclocal.m4 changes.
2269 * config.in: Ditto.
2270
2271Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * interp.c (sim_open): Add ABFD argument.
2274 (sim_load): Move call to sim_config from here.
2275 (sim_open): To here. Check return status.
2276
2277Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2278
2279 * gencode.c (build_instruction): Two arg MADD should
2280 not assign result to $0.
2281
2282Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2283
2284 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2285 * sim/mips/configure.in: Regenerate.
2286
2287Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2288
2289 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2290 signed8, unsigned8 et.al. types.
2291
2292 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2293 hosts when selecting subreg.
2294
2295Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2296
2297 * interp.c (sim_engine_run): Reset the ZERO register to zero
2298 regardless of FEATURE_WARN_ZERO.
2299 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2300
2301Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2302
2303 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2304 (SignalException): For BreakPoints ignore any mode bits and just
2305 save the PC.
2306 (SignalException): Always set the CAUSE register.
2307
2308Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2309
2310 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2311 exception has been taken.
2312
2313 * interp.c: Implement the ERET and mt/f sr instructions.
2314
2315Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2316
2317 * interp.c (SignalException): Don't bother restarting an
2318 interrupt.
2319
2320Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2321
2322 * interp.c (SignalException): Really take an interrupt.
2323 (interrupt_event): Only deliver interrupts when enabled.
2324
2325Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2326
2327 * interp.c (sim_info): Only print info when verbose.
2328 (sim_info) Use sim_io_printf for output.
2329
2330Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2333 mips architectures.
2334
2335Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2336
2337 * interp.c (sim_do_command): Check for common commands if a
2338 simulator specific command fails.
2339
2340Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2341
2342 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2343 and simBE when DEBUG is defined.
2344
2345Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346
2347 * interp.c (interrupt_event): New function. Pass exception event
2348 onto exception handler.
2349
2350 * configure.in: Check for stdlib.h.
2351 * configure: Regenerate.
2352
2353 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2354 variable declaration.
2355 (build_instruction): Initialize memval1.
2356 (build_instruction): Add UNUSED attribute to byte, bigend,
2357 reverse.
2358 (build_operands): Ditto.
2359
2360 * interp.c: Fix GCC warnings.
2361 (sim_get_quit_code): Delete.
2362
2363 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2364 * Makefile.in: Ditto.
2365 * configure: Re-generate.
2366
2367 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2368
2369Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370
2371 * interp.c (mips_option_handler): New function parse argumes using
2372 sim-options.
2373 (myname): Replace with STATE_MY_NAME.
2374 (sim_open): Delete check for host endianness - performed by
2375 sim_config.
2376 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2377 (sim_open): Move much of the initialization from here.
2378 (sim_load): To here. After the image has been loaded and
2379 endianness set.
2380 (sim_open): Move ColdReset from here.
2381 (sim_create_inferior): To here.
2382 (sim_open): Make FP check less dependant on host endianness.
2383
2384 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2385 run.
2386 * interp.c (sim_set_callbacks): Delete.
2387
2388 * interp.c (membank, membank_base, membank_size): Replace with
2389 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2390 (sim_open): Remove call to callback->init. gdb/run do this.
2391
2392 * interp.c: Update
2393
2394 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2395
2396 * interp.c (big_endian_p): Delete, replaced by
2397 current_target_byte_order.
2398
2399Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400
2401 * interp.c (host_read_long, host_read_word, host_swap_word,
2402 host_swap_long): Delete. Using common sim-endian.
2403 (sim_fetch_register, sim_store_register): Use H2T.
2404 (pipeline_ticks): Delete. Handled by sim-events.
2405 (sim_info): Update.
2406 (sim_engine_run): Update.
2407
2408Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2409
2410 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2411 reason from here.
2412 (SignalException): To here. Signal using sim_engine_halt.
2413 (sim_stop_reason): Delete, moved to common.
2414
2415Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2416
2417 * interp.c (sim_open): Add callback argument.
2418 (sim_set_callbacks): Delete SIM_DESC argument.
2419 (sim_size): Ditto.
2420
2421Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2422
2423 * Makefile.in (SIM_OBJS): Add common modules.
2424
2425 * interp.c (sim_set_callbacks): Also set SD callback.
2426 (set_endianness, xfer_*, swap_*): Delete.
2427 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2428 Change to functions using sim-endian macros.
2429 (control_c, sim_stop): Delete, use common version.
2430 (simulate): Convert into.
2431 (sim_engine_run): This function.
2432 (sim_resume): Delete.
2433
2434 * interp.c (simulation): New variable - the simulator object.
2435 (sim_kind): Delete global - merged into simulation.
2436 (sim_load): Cleanup. Move PC assignment from here.
2437 (sim_create_inferior): To here.
2438
2439 * sim-main.h: New file.
2440 * interp.c (sim-main.h): Include.
2441
2442Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2443
2444 * configure: Regenerated to track ../common/aclocal.m4 changes.
2445
2446Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2447
2448 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2449
2450Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2451
2452 * gencode.c (build_instruction): DIV instructions: check
2453 for division by zero and integer overflow before using
2454 host's division operation.
2455
2456Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2457
2458 * Makefile.in (SIM_OBJS): Add sim-load.o.
2459 * interp.c: #include bfd.h.
2460 (target_byte_order): Delete.
2461 (sim_kind, myname, big_endian_p): New static locals.
2462 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2463 after argument parsing. Recognize -E arg, set endianness accordingly.
2464 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2465 load file into simulator. Set PC from bfd.
2466 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2467 (set_endianness): Use big_endian_p instead of target_byte_order.
2468
2469Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2470
2471 * interp.c (sim_size): Delete prototype - conflicts with
2472 definition in remote-sim.h. Correct definition.
2473
2474Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2475
2476 * configure: Regenerated to track ../common/aclocal.m4 changes.
2477 * config.in: Ditto.
2478
2479Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2480
2481 * interp.c (sim_open): New arg `kind'.
2482
2483 * configure: Regenerated to track ../common/aclocal.m4 changes.
2484
2485Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2486
2487 * configure: Regenerated to track ../common/aclocal.m4 changes.
2488
2489Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2490
2491 * interp.c (sim_open): Set optind to 0 before calling getopt.
2492
2493Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2494
2495 * configure: Regenerated to track ../common/aclocal.m4 changes.
2496
2497Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2498
2499 * interp.c : Replace uses of pr_addr with pr_uword64
2500 where the bit length is always 64 independent of SIM_ADDR.
2501 (pr_uword64) : added.
2502
2503Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2504
2505 * configure: Re-generate.
2506
2507Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2508
2509 * configure: Regenerate to track ../common/aclocal.m4 changes.
2510
2511Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2512
2513 * interp.c (sim_open): New SIM_DESC result. Argument is now
2514 in argv form.
2515 (other sim_*): New SIM_DESC argument.
2516
2517Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2518
2519 * interp.c: Fix printing of addresses for non-64-bit targets.
2520 (pr_addr): Add function to print address based on size.
2521
2522Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2523
2524 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2525
2526Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2527
2528 * gencode.c (build_mips16_operands): Correct computation of base
2529 address for extended PC relative instruction.
2530
2531Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2532
2533 * interp.c (mips16_entry): Add support for floating point cases.
2534 (SignalException): Pass floating point cases to mips16_entry.
2535 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2536 registers.
2537 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2538 or fmt_word.
2539 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2540 and then set the state to fmt_uninterpreted.
2541 (COP_SW): Temporarily set the state to fmt_word while calling
2542 ValueFPR.
2543
2544Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2545
2546 * gencode.c (build_instruction): The high order may be set in the
2547 comparison flags at any ISA level, not just ISA 4.
2548
2549Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2550
2551 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2552 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2553 * configure.in: sinclude ../common/aclocal.m4.
2554 * configure: Regenerated.
2555
2556Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2557
2558 * configure: Rebuild after change to aclocal.m4.
2559
2560Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2561
2562 * configure configure.in Makefile.in: Update to new configure
2563 scheme which is more compatible with WinGDB builds.
2564 * configure.in: Improve comment on how to run autoconf.
2565 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2566 * Makefile.in: Use autoconf substitution to install common
2567 makefile fragment.
2568
2569Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2570
2571 * gencode.c (build_instruction): Use BigEndianCPU instead of
2572 ByteSwapMem.
2573
2574Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2575
2576 * interp.c (sim_monitor): Make output to stdout visible in
2577 wingdb's I/O log window.
2578
2579Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2580
2581 * support.h: Undo previous change to SIGTRAP
2582 and SIGQUIT values.
2583
2584Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2585
2586 * interp.c (store_word, load_word): New static functions.
2587 (mips16_entry): New static function.
2588 (SignalException): Look for mips16 entry and exit instructions.
2589 (simulate): Use the correct index when setting fpr_state after
2590 doing a pending move.
2591
2592Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2593
2594 * interp.c: Fix byte-swapping code throughout to work on
2595 both little- and big-endian hosts.
2596
2597Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2598
2599 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2600 with gdb/config/i386/xm-windows.h.
2601
2602Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2603
2604 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2605 that messes up arithmetic shifts.
2606
2607Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2608
2609 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2610 SIGTRAP and SIGQUIT for _WIN32.
2611
2612Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2613
2614 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2615 force a 64 bit multiplication.
2616 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2617 destination register is 0, since that is the default mips16 nop
2618 instruction.
2619
2620Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2621
2622 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2623 (build_endian_shift): Don't check proc64.
2624 (build_instruction): Always set memval to uword64. Cast op2 to
2625 uword64 when shifting it left in memory instructions. Always use
2626 the same code for stores--don't special case proc64.
2627
2628 * gencode.c (build_mips16_operands): Fix base PC value for PC
2629 relative operands.
2630 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2631 jal instruction.
2632 * interp.c (simJALDELAYSLOT): Define.
2633 (JALDELAYSLOT): Define.
2634 (INDELAYSLOT, INJALDELAYSLOT): Define.
2635 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2636
2637Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2638
2639 * interp.c (sim_open): add flush_cache as a PMON routine
2640 (sim_monitor): handle flush_cache by ignoring it
2641
2642Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2643
2644 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2645 BigEndianMem.
2646 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2647 (BigEndianMem): Rename to ByteSwapMem and change sense.
2648 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2649 BigEndianMem references to !ByteSwapMem.
2650 (set_endianness): New function, with prototype.
2651 (sim_open): Call set_endianness.
2652 (sim_info): Use simBE instead of BigEndianMem.
2653 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2654 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2655 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2656 ifdefs, keeping the prototype declaration.
2657 (swap_word): Rewrite correctly.
2658 (ColdReset): Delete references to CONFIG. Delete endianness related
2659 code; moved to set_endianness.
2660
2661Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2662
2663 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2664 * interp.c (CHECKHILO): Define away.
2665 (simSIGINT): New macro.
2666 (membank_size): Increase from 1MB to 2MB.
2667 (control_c): New function.
2668 (sim_resume): Rename parameter signal to signal_number. Add local
2669 variable prev. Call signal before and after simulate.
2670 (sim_stop_reason): Add simSIGINT support.
2671 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2672 functions always.
2673 (sim_warning): Delete call to SignalException. Do call printf_filtered
2674 if logfh is NULL.
2675 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2676 a call to sim_warning.
2677
2678Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2679
2680 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2681 16 bit instructions.
2682
2683Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2684
2685 Add support for mips16 (16 bit MIPS implementation):
2686 * gencode.c (inst_type): Add mips16 instruction encoding types.
2687 (GETDATASIZEINSN): Define.
2688 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2689 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2690 mtlo.
2691 (MIPS16_DECODE): New table, for mips16 instructions.
2692 (bitmap_val): New static function.
2693 (struct mips16_op): Define.
2694 (mips16_op_table): New table, for mips16 operands.
2695 (build_mips16_operands): New static function.
2696 (process_instructions): If PC is odd, decode a mips16
2697 instruction. Break out instruction handling into new
2698 build_instruction function.
2699 (build_instruction): New static function, broken out of
2700 process_instructions. Check modifiers rather than flags for SHIFT
2701 bit count and m[ft]{hi,lo} direction.
2702 (usage): Pass program name to fprintf.
2703 (main): Remove unused variable this_option_optind. Change
2704 ``*loptarg++'' to ``loptarg++''.
2705 (my_strtoul): Parenthesize && within ||.
2706 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2707 (simulate): If PC is odd, fetch a 16 bit instruction, and
2708 increment PC by 2 rather than 4.
2709 * configure.in: Add case for mips16*-*-*.
2710 * configure: Rebuild.
2711
2712Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2713
2714 * interp.c: Allow -t to enable tracing in standalone simulator.
2715 Fix garbage output in trace file and error messages.
2716
2717Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2718
2719 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2720 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2721 * configure.in: Simplify using macros in ../common/aclocal.m4.
2722 * configure: Regenerated.
2723 * tconfig.in: New file.
2724
2725Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2726
2727 * interp.c: Fix bugs in 64-bit port.
2728 Use ansi function declarations for msvc compiler.
2729 Initialize and test file pointer in trace code.
2730 Prevent duplicate definition of LAST_EMED_REGNUM.
2731
2732Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2733
2734 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2735
2736Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2737
2738 * interp.c (SignalException): Check for explicit terminating
2739 breakpoint value.
2740 * gencode.c: Pass instruction value through SignalException()
2741 calls for Trap, Breakpoint and Syscall.
2742
2743Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2744
2745 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2746 only used on those hosts that provide it.
2747 * configure.in: Add sqrt() to list of functions to be checked for.
2748 * config.in: Re-generated.
2749 * configure: Re-generated.
2750
2751Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2752
2753 * gencode.c (process_instructions): Call build_endian_shift when
2754 expanding STORE RIGHT, to fix swr.
2755 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2756 clear the high bits.
2757 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2758 Fix float to int conversions to produce signed values.
2759
2760Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2761
2762 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2763 (process_instructions): Correct handling of nor instruction.
2764 Correct shift count for 32 bit shift instructions. Correct sign
2765 extension for arithmetic shifts to not shift the number of bits in
2766 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2767 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2768 Fix madd.
2769 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2770 It's OK to have a mult follow a mult. What's not OK is to have a
2771 mult follow an mfhi.
2772 (Convert): Comment out incorrect rounding code.
2773
2774Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2775
2776 * interp.c (sim_monitor): Improved monitor printf
2777 simulation. Tidied up simulator warnings, and added "--log" option
2778 for directing warning message output.
2779 * gencode.c: Use sim_warning() rather than WARNING macro.
2780
2781Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2782
2783 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2784 getopt1.o, rather than on gencode.c. Link objects together.
2785 Don't link against -liberty.
2786 (gencode.o, getopt.o, getopt1.o): New targets.
2787 * gencode.c: Include <ctype.h> and "ansidecl.h".
2788 (AND): Undefine after including "ansidecl.h".
2789 (ULONG_MAX): Define if not defined.
2790 (OP_*): Don't define macros; now defined in opcode/mips.h.
2791 (main): Call my_strtoul rather than strtoul.
2792 (my_strtoul): New static function.
2793
2794Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2795
2796 * gencode.c (process_instructions): Generate word64 and uword64
2797 instead of `long long' and `unsigned long long' data types.
2798 * interp.c: #include sysdep.h to get signals, and define default
2799 for SIGBUS.
2800 * (Convert): Work around for Visual-C++ compiler bug with type
2801 conversion.
2802 * support.h: Make things compile under Visual-C++ by using
2803 __int64 instead of `long long'. Change many refs to long long
2804 into word64/uword64 typedefs.
2805
2806Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2807
2808 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2809 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2810 (docdir): Removed.
2811 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2812 (AC_PROG_INSTALL): Added.
2813 (AC_PROG_CC): Moved to before configure.host call.
2814 * configure: Rebuilt.
2815
2816Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2817
2818 * configure.in: Define @SIMCONF@ depending on mips target.
2819 * configure: Rebuild.
2820 * Makefile.in (run): Add @SIMCONF@ to control simulator
2821 construction.
2822 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2823 * interp.c: Remove some debugging, provide more detailed error
2824 messages, update memory accesses to use LOADDRMASK.
2825
2826Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2827
2828 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2829 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2830 stamp-h.
2831 * configure: Rebuild.
2832 * config.in: New file, generated by autoheader.
2833 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2834 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2835 HAVE_ANINT and HAVE_AINT, as appropriate.
2836 * Makefile.in (run): Use @LIBS@ rather than -lm.
2837 (interp.o): Depend upon config.h.
2838 (Makefile): Just rebuild Makefile.
2839 (clean): Remove stamp-h.
2840 (mostlyclean): Make the same as clean, not as distclean.
2841 (config.h, stamp-h): New targets.
2842
2843Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2844
2845 * interp.c (ColdReset): Fix boolean test. Make all simulator
2846 globals static.
2847
2848Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2849
2850 * interp.c (xfer_direct_word, xfer_direct_long,
2851 swap_direct_word, swap_direct_long, xfer_big_word,
2852 xfer_big_long, xfer_little_word, xfer_little_long,
2853 swap_word,swap_long): Added.
2854 * interp.c (ColdReset): Provide function indirection to
2855 host<->simulated_target transfer routines.
2856 * interp.c (sim_store_register, sim_fetch_register): Updated to
2857 make use of indirected transfer routines.
2858
2859Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2860
2861 * gencode.c (process_instructions): Ensure FP ABS instruction
2862 recognised.
2863 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2864 system call support.
2865
2866Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2867
2868 * interp.c (sim_do_command): Complain if callback structure not
2869 initialised.
2870
2871Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2872
2873 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2874 support for Sun hosts.
2875 * Makefile.in (gencode): Ensure the host compiler and libraries
2876 used for cross-hosted build.
2877
2878Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2879
2880 * interp.c, gencode.c: Some more (TODO) tidying.
2881
2882Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2883
2884 * gencode.c, interp.c: Replaced explicit long long references with
2885 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2886 * support.h (SET64LO, SET64HI): Macros added.
2887
2888Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2889
2890 * configure: Regenerate with autoconf 2.7.
2891
2892Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2893
2894 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2895 * support.h: Remove superfluous "1" from #if.
2896 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2897
2898Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2899
2900 * interp.c (StoreFPR): Control UndefinedResult() call on
2901 WARN_RESULT manifest.
2902
2903Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2904
2905 * gencode.c: Tidied instruction decoding, and added FP instruction
2906 support.
2907
2908 * interp.c: Added dineroIII, and BSD profiling support. Also
2909 run-time FP handling.
2910
2911Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2912
2913 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2914 gencode.c, interp.c, support.h: created.
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