projects / thirdparty / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 9c082ca8 MF |
1 | 2011-10-17 Mike Frysinger <vapier@gentoo.org> |
| 2 | ||
| 3 | * configure.ac: Change include to common/acinclude.m4. | |
| 4 | ||
| 6ffe910a MF |
5 | 2011-10-17 Mike Frysinger <vapier@gentoo.org> |
| 6 | ||
| 7 | * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER | |
| 8 | call. Replace common.m4 include with SIM_AC_COMMON. | |
| 9 | * configure: Regenerate. | |
| 10 | ||
| 31b28250 HPN |
11 | 2011-07-08 Hans-Peter Nilsson <hp@axis.com> |
| 12 | ||
| 3faa01e3 HPN |
13 | * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h |
| 14 | $(SIM_EXTRA_DEPS). | |
| 15 | (tmp-mach-multi): Exit early when igen fails. | |
| 31b28250 | 16 | |
| 2419798b MF |
17 | 2011-07-05 Mike Frysinger <vapier@gentoo.org> |
| 18 | ||
| 19 | * interp.c (sim_do_command): Delete. | |
| 20 | ||
| d79fe0d6 MF |
21 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
| 22 | ||
| 23 | * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free. | |
| 24 | (tx3904sio_fifo_reset): Likewise. | |
| 25 | * interp.c (sim_monitor): Likewise. | |
| 26 | ||
| 5558e7e6 MF |
27 | 2010-04-14 Mike Frysinger <vapier@gentoo.org> |
| 28 | ||
| 29 | * interp.c (sim_write): Add const to buffer arg. | |
| 30 | ||
| 35aafff4 JB |
31 | 2010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change) |
| 32 | ||
| 33 | * interp.c: Don't include sysdep.h | |
| 34 | ||
| 3725885a RW |
35 | 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
| 36 | ||
| 37 | * configure: Regenerate. | |
| 38 | ||
| d6416cdc RW |
39 | 2009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
| 40 | ||
| 81ecdfbb RW |
41 | * config.in: Regenerate. |
| 42 | * configure: Likewise. | |
| 43 | ||
| d6416cdc RW |
44 | * configure: Regenerate. |
| 45 | ||
| b5bd9624 HPN |
46 | 2008-07-11 Hans-Peter Nilsson <hp@axis.com> |
| 47 | ||
| 48 | * configure: Regenerate to track ../common/common.m4 changes. | |
| 49 | * config.in: Ditto. | |
| 50 | ||
| 6efef468 JM |
51 | 2008-06-06 Vladimir Prus <vladimir@codesourcery.com> |
| 52 | Daniel Jacobowitz <dan@codesourcery.com> | |
| 53 | Joseph Myers <joseph@codesourcery.com> | |
| 54 | ||
| 55 | * configure: Regenerate. | |
| 56 | ||
| 60dc88db RS |
57 | 2007-10-22 Richard Sandiford <rsandifo@nildram.co.uk> |
| 58 | ||
| 59 | * mips.igen (check_fmt_p): Provide a separate mips32r2 definition | |
| 60 | that unconditionally allows fmt_ps. | |
| 61 | (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) | |
| 62 | (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) | |
| 63 | (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change | |
| 64 | filter from 64,f to 32,f. | |
| 65 | (PREFX): Change filter from 64 to 32. | |
| 66 | (LDXC1, LUXC1): Provide separate mips32r2 implementations | |
| 67 | that use do_load_double instead of do_load. Make both LUXC1 | |
| 68 | versions unpredictable if SizeFGR () != 64. | |
| 69 | (SDXC1, SUXC1): Extend to mips32r2, using do_store_double | |
| 70 | instead of do_store. Remove unused variable. Make both SUXC1 | |
| 71 | versions unpredictable if SizeFGR () != 64. | |
| 72 | ||
| 599ca73e RS |
73 | 2007-10-07 Richard Sandiford <rsandifo@nildram.co.uk> |
| 74 | ||
| 75 | * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. | |
| 76 | (sc, swxc1): Likewise. Also fix big-endian and reverse-endian | |
| 77 | shifts for that case. | |
| 78 | ||
| 2525df03 NC |
79 | 2007-09-04 Nick Clifton <nickc@redhat.com> |
| 80 | ||
| 81 | * interp.c (options enum): Add OPTION_INFO_MEMORY. | |
| 82 | (display_mem_info): New static variable. | |
| 83 | (mips_option_handler): Handle OPTION_INFO_MEMORY. | |
| 84 | (mips_options): Add info-memory and memory-info. | |
| 85 | (sim_open): After processing the command line and board | |
| 86 | specification, check display_mem_info. If it is set then | |
| 87 | call the real handler for the --memory-info command line | |
| 88 | switch. | |
| 89 | ||
| 35ee6e1e JB |
90 | 2007-08-24 Joel Brobecker <brobecker@adacore.com> |
| 91 | ||
| 92 | * configure.ac: Change license of multi-run.c to GPL version 3. | |
| 93 | * configure: Regenerate. | |
| 94 | ||
| d5fb0879 RS |
95 | 2007-06-28 Richard Sandiford <richard@codesourcery.com> |
| 96 | ||
| 97 | * configure.ac, configure: Revert last patch. | |
| 98 | ||
| 2a2ce21b RS |
99 | 2007-06-26 Richard Sandiford <richard@codesourcery.com> |
| 100 | ||
| 101 | * configure.ac (sim_mipsisa3264_configs): New variable. | |
| 102 | (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make | |
| 103 | every configuration support all four targets, using the triplet to | |
| 104 | determine the default. | |
| 105 | * configure: Regenerate. | |
| 106 | ||
| efdcccc9 RS |
107 | 2007-06-25 Richard Sandiford <richard@codesourcery.com> |
| 108 | ||
| 0a7692b2 | 109 | * Makefile.in (m16run.o): New rule. |
| efdcccc9 | 110 | |
| f532a356 TS |
111 | 2007-05-15 Thiemo Seufer <ths@mips.com> |
| 112 | ||
| 113 | * mips3264r2.igen (DSHD): Fix compile warning. | |
| 114 | ||
| bfe9c90b TS |
115 | 2007-05-14 Thiemo Seufer <ths@mips.com> |
| 116 | ||
| 117 | * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, | |
| 118 | CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt, | |
| 119 | NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS, | |
| 120 | RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support | |
| 121 | for mips32r2. | |
| 122 | ||
| 53f4826b TS |
123 | 2007-03-01 Thiemo Seufer <ths@mips.com> |
| 124 | ||
| 125 | * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32 | |
| 126 | and mips64. | |
| 127 | ||
| 8bf3ddc8 TS |
128 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
| 129 | ||
| 130 | * dsp.igen: Update copyright notice. | |
| 131 | * dsp2.igen: Fix copyright notice. | |
| 132 | ||
| 8b082fb1 TS |
133 | 2007-02-20 Thiemo Seufer <ths@mips.com> |
| 134 | Chao-Ying Fu <fu@mips.com> | |
| 135 | ||
| 136 | * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. | |
| 137 | * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): | |
| 138 | Add dsp2 to sim_igen_machine. | |
| 139 | * configure: Regenerate. | |
| 140 | * dsp.igen (do_ph_op): Add MUL support when op = 2. | |
| 141 | (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. | |
| 142 | (mulq_rs.ph): Use do_ph_mulq. | |
| 143 | (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. | |
| 144 | * mips.igen: Add dsp2 model and include dsp2.igen. | |
| 145 | (MFHI, MFLO, MTHI, MTLO): Extend these instructions for | |
| 146 | for *mips32r2, *mips64r2, *dsp. | |
| 147 | (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions | |
| 148 | for *mips32r2, *mips64r2, *dsp2. | |
| 149 | * dsp2.igen: New file for MIPS DSP REV 2 ASE. | |
| 150 | ||
| b1004875 TS |
151 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
| 152 | Nigel Stephens <nigel@mips.com> | |
| 153 | ||
| 154 | * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 | |
| 155 | jumps with hazard barrier. | |
| 156 | ||
| f8df4c77 TS |
157 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
| 158 | Nigel Stephens <nigel@mips.com> | |
| 159 | ||
| 160 | * interp.c (sim_monitor): Flush stdout and stderr file descriptors | |
| 161 | after each call to sim_io_write. | |
| 162 | ||
| b1004875 | 163 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
| 07802d98 | 164 | Nigel Stephens <nigel@mips.com> |
| b1004875 TS |
165 | |
| 166 | * interp.c (ColdReset): Set CP0 Config0 to reflect the address size | |
| 167 | supported by this simulator. | |
| 07802d98 TS |
168 | (decode_coproc): Recognise additional CP0 Config registers |
| 169 | correctly. | |
| 170 | ||
| 14fb6c5a TS |
171 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
| 172 | Nigel Stephens <nigel@mips.com> | |
| 173 | David Ung <davidu@mips.com> | |
| 174 | ||
| 175 | * cp1.c (value_fpr): Don't inherit existing FPR_STATE for | |
| 176 | uninterpreted formats. If fmt is one of the uninterpreted types | |
| 177 | don't update the FPR_STATE. Handle fmt_uninterpreted_32 like | |
| 178 | fmt_word, and fmt_uninterpreted_64 like fmt_long. | |
| 179 | (store_fpr): When writing an invalid odd register, set the | |
| 180 | matching even register to fmt_unknown, not the following register. | |
| 181 | * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to | |
| 182 | the the memory window at offset 0 set by --memory-size command | |
| 183 | line option. | |
| 184 | (sim_store_register): Handle storing 4 bytes to an 8 byte floating | |
| 185 | point register. | |
| 186 | (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte | |
| 187 | register. | |
| 188 | (sim_monitor): When returning the memory size to the MIPS | |
| 189 | application, use the value in STATE_MEM_SIZE, not an arbitrary | |
| 190 | hardcoded value. | |
| 191 | (cop_lw): Don' mess around with FPR_STATE, just pass | |
| 192 | fmt_uninterpreted_32 to StoreFPR. | |
| 193 | (cop_sw): Similarly. | |
| 194 | (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. | |
| 195 | (cop_sd): Similarly. | |
| 196 | * mips.igen (not_word_value): Single version for mips32, mips64 | |
| 197 | and mips16. | |
| 198 | ||
| c8847145 TS |
199 | 2007-02-19 Thiemo Seufer <ths@mips.com> |
| 200 | Nigel Stephens <nigel@mips.com> | |
| 201 | ||
| 202 | * interp.c (MEM_SIZE): Increase default memory size from 2 to 8 | |
| 203 | MBytes. | |
| 204 | ||
| 4b5d35ee TS |
205 | 2007-02-17 Thiemo Seufer <ths@mips.com> |
| 206 | ||
| 207 | * configure.ac (mips*-sde-elf*): Move in front of generic machine | |
| 208 | configuration. | |
| 209 | * configure: Regenerate. | |
| 210 | ||
| 3669427c TS |
211 | 2007-02-17 Thiemo Seufer <ths@mips.com> |
| 212 | ||
| 213 | * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): | |
| 214 | Add mdmx to sim_igen_machine. | |
| 215 | (mipsisa64*-*-*): Likewise. Remove dsp. | |
| 216 | (mipsisa32*-*-*): Remove dsp. | |
| 217 | * configure: Regenerate. | |
| 218 | ||
| 109ad085 TS |
219 | 2007-02-13 Thiemo Seufer <ths@mips.com> |
| 220 | ||
| 221 | * configure.ac: Add mips*-sde-elf* target. | |
| 222 | * configure: Regenerate. | |
| 223 | ||
| 921d7ad3 HPN |
224 | 2006-12-21 Hans-Peter Nilsson <hp@axis.com> |
| 225 | ||
| 226 | * acconfig.h: Remove. | |
| 227 | * config.in, configure: Regenerate. | |
| 228 | ||
| 02f97da7 TS |
229 | 2006-11-07 Thiemo Seufer <ths@mips.com> |
| 230 | ||
| 231 | * dsp.igen (do_w_op): Fix compiler warning. | |
| 232 | ||
| 2d2733fc TS |
233 | 2006-08-29 Thiemo Seufer <ths@mips.com> |
| 234 | David Ung <davidu@mips.com> | |
| 235 | ||
| 236 | * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to | |
| 237 | sim_igen_machine. | |
| 238 | * configure: Regenerate. | |
| 239 | * mips.igen (model): Add smartmips. | |
| 240 | (MADDU): Increment ACX if carry. | |
| 241 | (do_mult): Clear ACX. | |
| 242 | (ROR,RORV): Add smartmips. | |
| 243 | (include): Include smartmips.igen. | |
| 244 | * sim-main.h (ACX): Set to REGISTERS[89]. | |
| 245 | * smartmips.igen: New file. | |
| 246 | ||
| d85c3a10 TS |
247 | 2006-08-29 Thiemo Seufer <ths@mips.com> |
| 248 | David Ung <davidu@mips.com> | |
| 249 | ||
| 250 | * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and | |
| 251 | mips3264r2.igen. Add missing dependency rules. | |
| 252 | * m16e.igen: Support for mips16e save/restore instructions. | |
| 253 | ||
| e85e3205 RE |
254 | 2006-06-13 Richard Earnshaw <rearnsha@arm.com> |
| 255 | ||
| 256 | * configure: Regenerated. | |
| 257 | ||
| 2f0122dc DJ |
258 | 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com> |
| 259 | ||
| 260 | * configure: Regenerated. | |
| 261 | ||
| 20e95c23 DJ |
262 | 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com> |
| 263 | ||
| 264 | * configure: Regenerated. | |
| 265 | ||
| 69088b17 CF |
266 | 2006-05-15 Chao-ying Fu <fu@mips.com> |
| 267 | ||
| 268 | * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions. | |
| 269 | ||
| 0275de4e NC |
270 | 2006-04-18 Nick Clifton <nickc@redhat.com> |
| 271 | ||
| 272 | * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break | |
| 273 | statement. | |
| 274 | ||
| b3a3ffef HPN |
275 | 2006-03-29 Hans-Peter Nilsson <hp@axis.com> |
| 276 | ||
| 277 | * configure: Regenerate. | |
| 278 | ||
| 40a5538e CF |
279 | 2005-12-14 Chao-ying Fu <fu@mips.com> |
| 280 | ||
| 281 | * Makefile.in (SIM_OBJS): Add dsp.o. | |
| 282 | (dsp.o): New dependency. | |
| 283 | (IGEN_INCLUDE): Add dsp.igen. | |
| 284 | * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, | |
| 285 | mipsisa64*-*-*): Add dsp to sim_igen_machine. | |
| 286 | * configure: Regenerate. | |
| 287 | * mips.igen: Add dsp model and include dsp.igen. | |
| 288 | (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, | |
| 289 | because these instructions are extended in DSP ASE. | |
| 290 | * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of | |
| 291 | adding 6 DSP accumulator registers and 1 DSP control register. | |
| 292 | (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, | |
| 293 | AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, | |
| 294 | DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, | |
| 295 | DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, | |
| 296 | DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, | |
| 297 | DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, | |
| 298 | DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, | |
| 299 | DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, | |
| 300 | DSPCR_CCOND_SMASK): New define. | |
| 301 | (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. | |
| 302 | * dsp.c, dsp.igen: New files for MIPS DSP ASE. | |
| 303 | ||
| 21d14896 ILT |
304 | 2005-07-08 Ian Lance Taylor <ian@airs.com> |
| 305 | ||
| 306 | * tconfig.in (SIM_QUIET_NAN_NEGATED): Define. | |
| 307 | ||
| b16d63da DU |
308 | 2005-06-16 David Ung <davidu@mips.com> |
| 309 | Nigel Stephens <nigel@mips.com> | |
| 310 | ||
| 311 | * mips.igen: New mips16e model and include m16e.igen. | |
| 312 | (check_u64): Add mips16e tag. | |
| 313 | * m16e.igen: New file for MIPS16e instructions. | |
| 314 | * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, | |
| 315 | mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e | |
| 316 | models. | |
| 317 | * configure: Regenerate. | |
| 318 | ||
| e70cb6cd CD |
319 | 2005-05-26 David Ung <davidu@mips.com> |
| 320 | ||
| 321 | * mips.igen (mips32r2, mips64r2): New ISA models. Add new model | |
| 322 | tags to all instructions which are applicable to the new ISAs. | |
| 323 | (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from | |
| 324 | vr.igen. | |
| 325 | * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific | |
| 326 | instructions. | |
| 327 | * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move | |
| 328 | to mips.igen. | |
| 329 | * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets. | |
| 330 | * configure: Regenerate. | |
| 331 | ||
| 2b193c4a MK |
332 | 2005-03-23 Mark Kettenis <kettenis@gnu.org> |
| 333 | ||
| 334 | * configure: Regenerate. | |
| 335 | ||
| 35695fd6 AC |
336 | 2005-01-14 Andrew Cagney <cagney@gnu.org> |
| 337 | ||
| 338 | * configure.ac: Sinclude aclocal.m4 before common.m4. Add | |
| 339 | explicit call to AC_CONFIG_HEADER. | |
| 340 | * configure: Regenerate. | |
| 341 | ||
| f0569246 AC |
342 | 2005-01-12 Andrew Cagney <cagney@gnu.org> |
| 343 | ||
| 344 | * configure.ac: Update to use ../common/common.m4. | |
| 345 | * configure: Re-generate. | |
| 346 | ||
| 38f48d72 AC |
347 | 2005-01-11 Andrew Cagney <cagney@localhost.localdomain> |
| 348 | ||
| 349 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 350 | ||
| b7026657 AC |
351 | 2005-01-07 Andrew Cagney <cagney@gnu.org> |
| 352 | ||
| 353 | * configure.ac: Rename configure.in, require autoconf 2.59. | |
| 354 | * configure: Re-generate. | |
| 355 | ||
| 379832de HPN |
356 | 2004-12-08 Hans-Peter Nilsson <hp@axis.com> |
| 357 | ||
| 358 | * configure: Regenerate for ../common/aclocal.m4 update. | |
| 359 | ||
| cd62154c AC |
360 | 2004-09-24 Monika Chaddha <monika@acmet.com> |
| 361 | ||
| 362 | Committed by Andrew Cagney. | |
| 363 | * m16.igen (CMP, CMPI): Fix assembler. | |
| 364 | ||
| e5da76ec CD |
365 | 2004-08-18 Chris Demetriou <cgd@broadcom.com> |
| 366 | ||
| 367 | * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine. | |
| 368 | * configure: Regenerate. | |
| 369 | ||
| 139181c8 CD |
370 | 2004-06-25 Chris Demetriou <cgd@broadcom.com> |
| 371 | ||
| 372 | * configure.in (sim_m16_machine): Include mipsIII. | |
| 373 | * configure: Regenerate. | |
| 374 | ||
| 1a27f959 CD |
375 | 2004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> |
| 376 | ||
| 377 | * mips/interp.c (decode_coproc): Sign-extend the address retrieved | |
| 378 | from COP0_BADVADDR. | |
| 379 | * mips/sim-main.h (COP0_BADVADDR): Remove a cast. | |
| 380 | ||
| 5dbb7b5a CD |
381 | 2004-04-10 Chris Demetriou <cgd@broadcom.com> |
| 382 | ||
| 383 | * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. | |
| 384 | ||
| 14234056 CD |
385 | 2004-04-09 Chris Demetriou <cgd@broadcom.com> |
| 386 | ||
| 387 | * mips.igen (check_fmt): Remove. | |
| 388 | (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W) | |
| 389 | (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt) | |
| 390 | (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt) | |
| 391 | (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt) | |
| 392 | (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt) | |
| 393 | (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats. | |
| 394 | (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) | |
| 395 | (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt) | |
| 396 | (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt. | |
| 397 | (C.cnd.fmta): Remove incorrect call to check_fmt_p. | |
| 398 | ||
| c6f9085c CD |
399 | 2004-04-09 Chris Demetriou <cgd@broadcom.com> |
| 400 | ||
| 401 | * sb1.igen (check_sbx): New function. | |
| 402 | (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx. | |
| 403 | ||
| 11d66e66 | 404 | 2004-03-29 Chris Demetriou <cgd@broadcom.com> |
| 0e1b7197 RS |
405 | Richard Sandiford <rsandifo@redhat.com> |
| 406 | ||
| 407 | * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD) | |
| 408 | (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. | |
| 409 | * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide | |
| 410 | separate implementations for mipsIV and mipsV. Use new macros to | |
| 411 | determine whether the restrictions apply. | |
| 412 | ||
| b3208fb8 CD |
413 | 2004-01-19 Chris Demetriou <cgd@broadcom.com> |
| 414 | ||
| 415 | * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo) | |
| 416 | (check_mult_hilo): Improve comments. | |
| 417 | (check_div_hilo): Likewise. Also, fork off a new version | |
| 418 | to handle mips32/mips64 (since there are no hazards to check | |
| 419 | in MIPS32/MIPS64). | |
| 420 | ||
| 9a1d84fb CD |
421 | 2003-06-17 Richard Sandiford <rsandifo@redhat.com> |
| 422 | ||
| 423 | * mips.igen (do_dmultx): Fix check for negative operands. | |
| 424 | ||
| ae451ac6 ILT |
425 | 2003-05-16 Ian Lance Taylor <ian@airs.com> |
| 426 | ||
| 427 | * Makefile.in (SHELL): Make sure this is defined. | |
| 428 | (various): Use $(SHELL) whenever we invoke move-if-change. | |
| 429 | ||
| dd69d292 CD |
430 | 2003-05-03 Chris Demetriou <cgd@broadcom.com> |
| 431 | ||
| 432 | * cp1.c: Tweak attribution slightly. | |
| 433 | * cp1.h: Likewise. | |
| 434 | * mdmx.c: Likewise. | |
| 435 | * mdmx.igen: Likewise. | |
| 436 | * mips3d.igen: Likewise. | |
| 437 | * sb1.igen: Likewise. | |
| 438 | ||
| bcd0068e CD |
439 | 2003-04-15 Richard Sandiford <rsandifo@redhat.com> |
| 440 | ||
| 441 | * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of | |
| 442 | unsigned operands. | |
| 443 | ||
| 6b4a8935 AC |
444 | 2003-02-27 Andrew Cagney <cagney@redhat.com> |
| 445 | ||
| 601da316 AC |
446 | * interp.c (sim_open): Rename _bfd to bfd. |
| 447 | (sim_create_inferior): Ditto. | |
| 6b4a8935 | 448 | |
| d29e330f CD |
449 | 2003-01-14 Chris Demetriou <cgd@broadcom.com> |
| 450 | ||
| 451 | * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64. | |
| 452 | ||
| a2353a08 CD |
453 | 2003-01-14 Chris Demetriou <cgd@broadcom.com> |
| 454 | ||
| 455 | * mips.igen (EI, DI): Remove. | |
| 456 | ||
| 80551777 CD |
457 | 2003-01-05 Richard Sandiford <rsandifo@redhat.com> |
| 458 | ||
| 459 | * Makefile.in (tmp-run-multi): Fix mips16 filter. | |
| 460 | ||
| 4c54fc26 CD |
461 | 2003-01-04 Richard Sandiford <rsandifo@redhat.com> |
| 462 | Andrew Cagney <ac131313@redhat.com> | |
| 463 | Gavin Romig-Koch <gavin@redhat.com> | |
| 464 | Graydon Hoare <graydon@redhat.com> | |
| 465 | Aldy Hernandez <aldyh@redhat.com> | |
| 466 | Dave Brolley <brolley@redhat.com> | |
| 467 | Chris Demetriou <cgd@broadcom.com> | |
| 468 | ||
| 469 | * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. | |
| 470 | (sim_mach_default): New variable. | |
| 471 | (mips64vr-*-*, mips64vrel-*-*): New configurations. | |
| 472 | Add a new simulator generator, MULTI. | |
| 473 | * configure: Regenerate. | |
| 474 | * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. | |
| 475 | (multi-run.o): New dependency. | |
| 476 | (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. | |
| 477 | (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. | |
| 478 | (tmp-multi): Combine them. | |
| 479 | (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. | |
| 480 | (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. | |
| 481 | (distclean-extra): New rule. | |
| 482 | * sim-main.h: Include bfd.h. | |
| 483 | (MIPS_MACH): New macro. | |
| 484 | * mips.igen (vr4120, vr5400, vr5500): New models. | |
| 485 | (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. | |
| 486 | * vr.igen: Replace with new version. | |
| 487 | ||
| e6c674b8 CD |
488 | 2003-01-04 Chris Demetriou <cgd@broadcom.com> |
| 489 | ||
| 490 | * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1). | |
| 491 | * configure: Regenerate. | |
| 492 | ||
| 28f50ac8 CD |
493 | 2002-12-31 Chris Demetriou <cgd@broadcom.com> |
| 494 | ||
| 495 | * sim-main.h (check_branch_bug, mark_branch_bug): Remove. | |
| 496 | * mips.igen: Remove all invocations of check_branch_bug and | |
| 497 | mark_branch_bug. | |
| 498 | ||
| 5071ffe6 CD |
499 | 2002-12-16 Chris Demetriou <cgd@broadcom.com> |
| 500 | ||
| 501 | * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h". | |
| 502 | ||
| 06e7837e CD |
503 | 2002-07-30 Chris Demetriou <cgd@broadcom.com> |
| 504 | ||
| 505 | * mips.igen (do_load_double, do_store_double): New functions. | |
| 506 | (LDC1, SDC1): Rename to... | |
| 507 | (LDC1b, SDC1b): respectively. | |
| 508 | (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support. | |
| 509 | ||
| 2265c243 MS |
510 | 2002-07-29 Michael Snyder <msnyder@redhat.com> |
| 511 | ||
| 512 | * cp1.c (fp_recip2): Modify initialization expression so that | |
| 513 | GCC will recognize it as constant. | |
| 514 | ||
| a2f8b4f3 CD |
515 | 2002-06-18 Chris Demetriou <cgd@broadcom.com> |
| 516 | ||
| 517 | * mdmx.c (SD_): Delete. | |
| 518 | (Unpredictable): Re-define, for now, to directly invoke | |
| 519 | unpredictable_action(). | |
| 520 | (mdmx_acc_op): Fix error in .ob immediate handling. | |
| 521 | ||
| b4b6c939 AC |
522 | 2002-06-18 Andrew Cagney <cagney@redhat.com> |
| 523 | ||
| 524 | * interp.c (sim_firmware_command): Initialize `address'. | |
| 525 | ||
| c8cca39f AC |
526 | 2002-06-16 Andrew Cagney <ac131313@redhat.com> |
| 527 | ||
| 528 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 529 | ||
| e7e81181 CD |
530 | 2002-06-14 Chris Demetriou <cgd@broadcom.com> |
| 531 | Ed Satterthwaite <ehs@broadcom.com> | |
| 532 | ||
| 533 | * mips3d.igen: New file which contains MIPS-3D ASE instructions. | |
| 534 | * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. | |
| 535 | * mips.igen: Include mips3d.igen. | |
| 536 | (mips3d): New model name for MIPS-3D ASE instructions. | |
| 537 | (CVT.W.fmt): Don't use this instruction for word (source) format | |
| 538 | instructions. | |
| 539 | * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) | |
| 540 | (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) | |
| 541 | (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. | |
| 542 | (NR_FRAC_GUARD, IMPLICIT_1): New macros. | |
| 543 | * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) | |
| 544 | (RSquareRoot1, RSquareRoot2): New macros. | |
| 545 | (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) | |
| 546 | (fp_rsqrt2): New functions. | |
| 547 | * configure.in: Add MIPS-3D support to mipsisa64 simulator. | |
| 548 | * configure: Regenerate. | |
| 549 | ||
| 3a2b820e | 550 | 2002-06-13 Chris Demetriou <cgd@broadcom.com> |
| eab54952 | 551 | Ed Satterthwaite <ehs@broadcom.com> |
| 3a2b820e CD |
552 | |
| 553 | * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. | |
| 554 | (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) | |
| 555 | (fp_inv_sqrt, fpu_format_name): Add paired-single support. | |
| 556 | (convert): Note that this function is not used for paired-single | |
| 557 | format conversions. | |
| 558 | (ps_lower, ps_upper, pack_ps, convert_ps): New functions. | |
| 559 | * mips.igen (FMT, MOVtf.fmt): Add paired-single support. | |
| 560 | (check_fmt_p): Enable paired-single support. | |
| 561 | (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) | |
| 562 | (PUU.PS): New instructions. | |
| 563 | (CVT.S.fmt): Don't use this instruction for paired-single format | |
| 564 | destinations. | |
| 565 | * sim-main.h (FP_formats): New value 'fmt_ps.' | |
| 566 | (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. | |
| 567 | (PSLower, PSUpper, PackPS, ConvertPS): New macros. | |
| 568 | ||
| d18ea9c2 CD |
569 | 2002-06-12 Chris Demetriou <cgd@broadcom.com> |
| 570 | ||
| 571 | * mips.igen: Fix formatting of function calls in | |
| 572 | many FP operations. | |
| 573 | ||
| 95fd5cee CD |
574 | 2002-06-12 Chris Demetriou <cgd@broadcom.com> |
| 575 | ||
| 576 | * mips.igen (MOVN, MOVZ): Trace result. | |
| 577 | (TNEI): Print "tnei" as the opcode name in traces. | |
| 578 | (CEIL.W): Add disassembly string for traces. | |
| 579 | (RSQRT.fmt): Make location of disassembly string consistent | |
| 580 | with other instructions. | |
| 581 | ||
| 4f0d55ae CD |
582 | 2002-06-12 Chris Demetriou <cgd@broadcom.com> |
| 583 | ||
| 584 | * mips.igen (X): Delete unused function. | |
| 585 | ||
| 3c25f8c7 AC |
586 | 2002-06-08 Andrew Cagney <cagney@redhat.com> |
| 587 | ||
| 588 | * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". | |
| 589 | ||
| f3c08b7e CD |
590 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
| 591 | Ed Satterthwaite <ehs@broadcom.com> | |
| 592 | ||
| 593 | * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) | |
| 594 | (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. | |
| 595 | * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) | |
| 596 | (fp_nmsub): New prototypes. | |
| 597 | (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) | |
| 598 | (NegMultiplySub): New defines. | |
| 599 | * mips.igen (RSQRT.fmt): Use RSquareRoot(). | |
| 600 | (MADD.D, MADD.S): Replace with... | |
| 601 | (MADD.fmt): New instruction. | |
| 602 | (MSUB.D, MSUB.S): Replace with... | |
| 603 | (MSUB.fmt): New instruction. | |
| 604 | (NMADD.D, NMADD.S): Replace with... | |
| 605 | (NMADD.fmt): New instruction. | |
| 606 | (NMSUB.D, MSUB.S): Replace with... | |
| 607 | (NMSUB.fmt): New instruction. | |
| 608 | ||
| 52714ff9 CD |
609 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
| 610 | Ed Satterthwaite <ehs@broadcom.com> | |
| 611 | ||
| 612 | * cp1.c: Fix more comment spelling and formatting. | |
| 613 | (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value. | |
| 614 | (denorm_mode): New function. | |
| 615 | (fpu_unary, fpu_binary): Round results after operation, collect | |
| 616 | status from rounding operations, and update the FCSR. | |
| 617 | (convert): Collect status from integer conversions and rounding | |
| 618 | operations, and update the FCSR. Adjust NaN values that result | |
| 619 | from conversions. Convert to use sim_io_eprintf rather than | |
| 620 | fprintf, and remove some debugging code. | |
| 621 | * cp1.h (fenr_FS): New define. | |
| 622 | ||
| 577d8c4b CD |
623 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
| 624 | ||
| 625 | * cp1.c (convert): Remove unusable debugging code, and move MIPS | |
| 626 | rounding mode to sim FP rounding mode flag conversion code into... | |
| 627 | (rounding_mode): New function. | |
| 628 | ||
| 196496ed CD |
629 | 2002-06-07 Chris Demetriou <cgd@broadcom.com> |
| 630 | ||
| 631 | * cp1.c: Clean up formatting of a few comments. | |
| 632 | (value_fpr): Reformat switch statement. | |
| 633 | ||
| cfe9ea23 CD |
634 | 2002-06-06 Chris Demetriou <cgd@broadcom.com> |
| 635 | Ed Satterthwaite <ehs@broadcom.com> | |
| 636 | ||
| 637 | * cp1.h: New file. | |
| 638 | * sim-main.h: Include cp1.h. | |
| 639 | (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) | |
| 640 | (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) | |
| 641 | (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. | |
| 642 | (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. | |
| 643 | (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. | |
| 644 | (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. | |
| 645 | * cp1.c: Don't include sim-fpu.h; already included by | |
| 646 | sim-main.h. Clean up formatting of some comments. | |
| 647 | (NaN, Equal, Less): Remove. | |
| 648 | (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) | |
| 649 | (fp_cmp): New functions. | |
| 650 | * mips.igen (do_c_cond_fmt): Remove. | |
| 651 | (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with | |
| 652 | Compare. Add result tracing. | |
| 653 | (CxC1): Remove, replace with... | |
| 654 | (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. | |
| 655 | (DMxC1): Remove, replace with... | |
| 656 | (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. | |
| 657 | (MxC1): Remove, replace with... | |
| 658 | (MFC1a, MFC1b, MTC1a, MTC1b): New instructions. | |
| 659 | ||
| ee7254b0 CD |
660 | 2002-06-04 Chris Demetriou <cgd@broadcom.com> |
| 661 | ||
| 662 | * sim-main.h (FGRIDX): Remove, replace all uses with... | |
| 663 | (FGR_BASE): New macro. | |
| 664 | (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. | |
| 665 | (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. | |
| 666 | (NR_FGR, FGR): Likewise. | |
| 667 | * interp.c: Replace all uses of FGRIDX with FGR_BASE. | |
| 668 | * mips.igen: Likewise. | |
| 669 | ||
| d3eb724f CD |
670 | 2002-06-04 Chris Demetriou <cgd@broadcom.com> |
| 671 | ||
| 672 | * cp1.c: Add an FSF Copyright notice to this file. | |
| 673 | ||
| ba46ddd0 CD |
674 | 2002-06-04 Chris Demetriou <cgd@broadcom.com> |
| 675 | Ed Satterthwaite <ehs@broadcom.com> | |
| 676 | ||
| 677 | * cp1.c (Infinity): Remove. | |
| 678 | * sim-main.h (Infinity): Likewise. | |
| 679 | ||
| 680 | * cp1.c (fp_unary, fp_binary): New functions. | |
| 681 | (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) | |
| 682 | (fp_sqrt): New functions, implemented in terms of the above. | |
| 683 | (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) | |
| 684 | (Recip, SquareRoot): Remove (replaced by functions above). | |
| 685 | * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) | |
| 686 | (fp_recip, fp_sqrt): New prototypes. | |
| 687 | (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) | |
| 688 | (Recip, SquareRoot): Replace prototypes with #defines which | |
| 689 | invoke the functions above. | |
| 690 | ||
| 18d8a52d CD |
691 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
| 692 | ||
| 693 | * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) | |
| 694 | (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in | |
| 695 | file, remove PARAMS from prototypes. | |
| 696 | (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide | |
| 697 | simulator state arguments. | |
| 698 | (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to | |
| 699 | pass simulator state arguments. | |
| 700 | * cp1.c (SD): Redefine as CPU_STATE(cpu). | |
| 701 | (store_fpr, convert): Remove 'sd' argument. | |
| 702 | (value_fpr): Likewise. Convert to use 'SD' instead. | |
| 703 | ||
| 0f154cbd CD |
704 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
| 705 | ||
| 706 | * cp1.c (Min, Max): Remove #if 0'd functions. | |
| 707 | * sim-main.h (Min, Max): Remove. | |
| 708 | ||
| e80fc152 CD |
709 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
| 710 | ||
| 711 | * cp1.c: fix formatting of switch case and default labels. | |
| 712 | * interp.c: Likewise. | |
| 713 | * sim-main.c: Likewise. | |
| 714 | ||
| bad673a9 CD |
715 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
| 716 | ||
| 717 | * cp1.c: Clean up comments which describe FP formats. | |
| 718 | (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64. | |
| 719 | ||
| 7cbea089 CD |
720 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
| 721 | Ed Satterthwaite <ehs@broadcom.com> | |
| 722 | ||
| 723 | * configure.in (mipsisa64sb1*-*-*): New target for supporting | |
| 724 | Broadcom SiByte SB-1 processor configurations. | |
| 725 | * configure: Regenerate. | |
| 726 | * sb1.igen: New file. | |
| 727 | * mips.igen: Include sb1.igen. | |
| 728 | (sb1): New model. | |
| 729 | * Makefile.in (IGEN_INCLUDE): Add sb1.igen. | |
| 730 | * mdmx.igen: Add "sb1" model to all appropriate functions and | |
| 731 | instructions. | |
| 732 | * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. | |
| 733 | (ob_func, ob_acc): Reference the above. | |
| 734 | (qh_acc): Adjust to keep the same size as ob_acc. | |
| 735 | * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) | |
| 736 | (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros. | |
| 737 | ||
| 909daa82 CD |
738 | 2002-06-03 Chris Demetriou <cgd@broadcom.com> |
| 739 | ||
| 740 | * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. | |
| 741 | ||
| f4f1b9f1 CD |
742 | 2002-06-02 Chris Demetriou <cgd@broadcom.com> |
| 743 | Ed Satterthwaite <ehs@broadcom.com> | |
| 744 | ||
| 745 | * mips.igen (mdmx): New (pseudo-)model. | |
| 746 | * mdmx.c, mdmx.igen: New files. | |
| 747 | * Makefile.in (SIM_OBJS): Add mdmx.o. | |
| 748 | * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): | |
| 749 | New typedefs. | |
| 750 | (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) | |
| 751 | (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) | |
| 752 | (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) | |
| 753 | (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) | |
| 754 | (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) | |
| 755 | (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) | |
| 756 | (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) | |
| 757 | (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) | |
| 758 | (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) | |
| 759 | (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) | |
| 760 | (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) | |
| 761 | (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) | |
| 762 | (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) | |
| 763 | (qh_fmtsel): New macros. | |
| 764 | (_sim_cpu): New member "acc". | |
| 765 | (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) | |
| 766 | (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions. | |
| 767 | ||
| 5accf1ff CD |
768 | 2002-05-01 Chris Demetriou <cgd@broadcom.com> |
| 769 | ||
| 770 | * interp.c: Use 'deprecated' rather than 'depreciated.' | |
| 771 | * sim-main.h: Likewise. | |
| 772 | ||
| 402586aa CD |
773 | 2002-05-01 Chris Demetriou <cgd@broadcom.com> |
| 774 | ||
| 775 | * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult | |
| 776 | which wouldn't compile anyway. | |
| 777 | * sim-main.h (unpredictable_action): New function prototype. | |
| 778 | (Unpredictable): Define to call igen function unpredictable(). | |
| 779 | (NotWordValue): New macro to call igen function not_word_value(). | |
| 780 | (UndefinedResult): Remove. | |
| 781 | * interp.c (undefined_result): Remove. | |
| 782 | (unpredictable_action): New function. | |
| 783 | * mips.igen (not_word_value, unpredictable): New functions. | |
| 784 | (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) | |
| 785 | (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) | |
| 786 | (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke | |
| 787 | NotWordValue() to check for unpredictable inputs, then | |
| 788 | Unpredictable() to handle them. | |
| 789 | ||
| c9b9995a CD |
790 | 2002-02-24 Chris Demetriou <cgd@broadcom.com> |
| 791 | ||
| 792 | * mips.igen: Fix formatting of calls to Unpredictable(). | |
| 793 | ||
| e1015982 AC |
794 | 2002-04-20 Andrew Cagney <ac131313@redhat.com> |
| 795 | ||
| 796 | * interp.c (sim_open): Revert previous change. | |
| 797 | ||
| b882a66b AO |
798 | 2002-04-18 Alexandre Oliva <aoliva@redhat.com> |
| 799 | ||
| 800 | * interp.c (sim_open): Disable chunk of code that wrote code in | |
| 801 | vector table entries. | |
| 802 | ||
| c429b7dd CD |
803 | 2002-03-19 Chris Demetriou <cgd@broadcom.com> |
| 804 | ||
| 805 | * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f) | |
| 806 | (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove | |
| 807 | unused definitions. | |
| 808 | ||
| 37d146fa CD |
809 | 2002-03-19 Chris Demetriou <cgd@broadcom.com> |
| 810 | ||
| 811 | * cp1.c: Fix many formatting issues. | |
| 812 | ||
| 07892c0b CD |
813 | 2002-03-19 Chris G. Demetriou <cgd@broadcom.com> |
| 814 | ||
| 815 | * cp1.c (fpu_format_name): New function to replace... | |
| 816 | (DOFMT): This. Delete, and update all callers. | |
| 817 | (fpu_rounding_mode_name): New function to replace... | |
| 818 | (RMMODE): This. Delete, and update all callers. | |
| 819 | ||
| 487f79b7 CD |
820 | 2002-03-19 Chris G. Demetriou <cgd@broadcom.com> |
| 821 | ||
| 822 | * interp.c: Move FPU support routines from here to... | |
| 823 | * cp1.c: Here. New file. | |
| 824 | * Makefile.in (SIM_OBJS): Add cp1.o to object list. | |
| 825 | (cp1.o): New target. | |
| 826 | ||
| 1e799e28 CD |
827 | 2002-03-12 Chris Demetriou <cgd@broadcom.com> |
| 828 | ||
| 829 | * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. | |
| 830 | * mips.igen (mips32, mips64): New models, add to all instructions | |
| 831 | and functions as appropriate. | |
| 832 | (loadstore_ea, check_u64): New variant for model mips64. | |
| 833 | (check_fmt_p): New variant for models mipsV and mips64, remove | |
| 834 | mipsV model marking fro other variant. | |
| 835 | (SLL) Rename to... | |
| 836 | (SLLa) this. | |
| 837 | (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions | |
| 838 | for mips32 and mips64. | |
| 839 | (DCLO, DCLZ): New instructions for mips64. | |
| 840 | ||
| 82f728db CD |
841 | 2002-03-07 Chris Demetriou <cgd@broadcom.com> |
| 842 | ||
| 843 | * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print | |
| 844 | immediate or code as a hex value with the "%#lx" format. | |
| 845 | (ANDI): Likewise, and fix printed instruction name. | |
| 846 | ||
| b96e7ef1 CD |
847 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
| 848 | ||
| 849 | * sim-main.h (UndefinedResult, Unpredictable): New macros | |
| 850 | which currently do nothing. | |
| 851 | ||
| d35d4f70 CD |
852 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
| 853 | ||
| 854 | * sim-main.h (status_UX, status_SX, status_KX, status_TS) | |
| 855 | (status_PX, status_MX, status_CU0, status_CU1, status_CU2) | |
| 856 | (status_CU3): New definitions. | |
| 857 | ||
| 858 | * sim-main.h (ExceptionCause): Add new values for MIPS32 | |
| 859 | and MIPS64: MDMX, MCheck, CacheErr. Update comments | |
| 860 | for DebugBreakPoint and NMIReset to note their status in | |
| 861 | MIPS32 and MIPS64. | |
| 862 | (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) | |
| 863 | (SignalExceptionCacheErr): New exception macros. | |
| 864 | ||
| 3ad6f714 CD |
865 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
| 866 | ||
| 867 | * mips.igen (check_fpu): Enable check for coprocessor 1 usability. | |
| 868 | * sim-main.h (COP_Usable): Define, but for now coprocessor 1 | |
| 869 | is always enabled. | |
| 870 | (SignalExceptionCoProcessorUnusable): Take as argument the | |
| 871 | unusable coprocessor number. | |
| 872 | ||
| 86b77b47 CD |
873 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
| 874 | ||
| 875 | * mips.igen: Fix formatting of all SignalException calls. | |
| 876 | ||
| 97a88e93 | 877 | 2002-03-05 Chris Demetriou <cgd@broadcom.com> |
| 3dea6720 CD |
878 | |
| 879 | * sim-main.h (SIGNEXTEND): Remove. | |
| 880 | ||
| 97a88e93 | 881 | 2002-03-04 Chris Demetriou <cgd@broadcom.com> |
| b5040d49 CD |
882 | |
| 883 | * mips.igen: Remove gencode comment from top of file, fix | |
| 884 | spelling in another comment. | |
| 885 | ||
| 97a88e93 | 886 | 2002-03-04 Chris Demetriou <cgd@broadcom.com> |
| 8612006b CD |
887 | |
| 888 | * mips.igen (check_fmt, check_fmt_p): New functions to check | |
| 889 | whether specific floating point formats are usable. | |
| 890 | (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) | |
| 891 | (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt) | |
| 892 | (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W): | |
| 893 | Use the new functions. | |
| 894 | (do_c_cond_fmt): Remove format checks... | |
| 895 | (C.cond.fmta, C.cond.fmtb): And move them into all callers. | |
| 896 | ||
| 97a88e93 | 897 | 2002-03-03 Chris Demetriou <cgd@broadcom.com> |
| 9b17d183 CD |
898 | |
| 899 | * mips.igen: Fix formatting of check_fpu calls. | |
| 900 | ||
| 41774c9d CD |
901 | 2002-03-03 Chris Demetriou <cgd@broadcom.com> |
| 902 | ||
| 903 | * mips.igen (FLOOR.L.fmt): Store correct destination register. | |
| 904 | ||
| 4a0bd876 CD |
905 | 2002-03-03 Chris Demetriou <cgd@broadcom.com> |
| 906 | ||
| 907 | * mips.igen: Remove whitespace at end of lines. | |
| 908 | ||
| 09297648 CD |
909 | 2002-03-02 Chris Demetriou <cgd@broadcom.com> |
| 910 | ||
| 911 | * mips.igen (loadstore_ea): New function to do effective | |
| 912 | address calculations. | |
| 913 | (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store, | |
| 914 | do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1, | |
| 915 | CACHE): Use loadstore_ea to do effective address computations. | |
| 916 | ||
| 043b7057 CD |
917 | 2002-03-02 Chris Demetriou <cgd@broadcom.com> |
| 918 | ||
| 919 | * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND. | |
| 920 | * mips.igen (LL, CxC1, MxC1): Likewise. | |
| 921 | ||
| c1e8ada4 CD |
922 | 2002-03-02 Chris Demetriou <cgd@broadcom.com> |
| 923 | ||
| 924 | * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, | |
| 925 | CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, | |
| 926 | FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt, | |
| 927 | MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, | |
| 928 | NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, | |
| 929 | SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE): | |
| 930 | Don't split opcode fields by hand, use the opcode field values | |
| 931 | provided by igen. | |
| 932 | ||
| 3e1dca16 CD |
933 | 2002-03-01 Chris Demetriou <cgd@broadcom.com> |
| 934 | ||
| 935 | * mips.igen (do_divu): Fix spacing. | |
| 936 | ||
| 937 | * mips.igen (do_dsllv): Move to be right before DSLLV, | |
| 938 | to match the rest of the do_<shift> functions. | |
| 939 | ||
| fff8d27d CD |
940 | 2002-03-01 Chris Demetriou <cgd@broadcom.com> |
| 941 | ||
| 942 | * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl, | |
| 943 | DSRL32, do_dsrlv): Trace inputs and results. | |
| 944 | ||
| 0d3e762b CD |
945 | 2002-03-01 Chris Demetriou <cgd@broadcom.com> |
| 946 | ||
| 947 | * mips.igen (CACHE): Provide instruction-printing string. | |
| 948 | ||
| 949 | * interp.c (signal_exception): Comment tokens after #endif. | |
| 950 | ||
| eb5fcf93 CD |
951 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
| 952 | ||
| 953 | * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32". | |
| 954 | (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, | |
| 955 | NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, | |
| 956 | ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, | |
| 957 | CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, | |
| 958 | C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, | |
| 959 | SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, | |
| 960 | LWC1, SWC1): Add "f" to filter, since these are FP instructions. | |
| 961 | ||
| bb22bd7d CD |
962 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
| 963 | ||
| 964 | * mips.igen (DSRA32, DSRAV): Fix order of arguments in | |
| 965 | instruction-printing string. | |
| 966 | (LWU): Use '64' as the filter flag. | |
| 967 | ||
| 91a177cf CD |
968 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
| 969 | ||
| 970 | * mips.igen (SDXC1): Fix instruction-printing string. | |
| 971 | ||
| 387f484a CD |
972 | 2002-02-28 Chris Demetriou <cgd@broadcom.com> |
| 973 | ||
| 974 | * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with | |
| 975 | filter flags "32,f". | |
| 976 | ||
| 3d81f391 CD |
977 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
| 978 | ||
| 979 | * mips.igen (PREFX): This is a 64-bit instruction, use '64' | |
| 980 | as the filter flag. | |
| 981 | ||
| af5107af CD |
982 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
| 983 | ||
| 984 | * mips.igen (PREFX): Tweak instruction opcode fields (i.e., | |
| 985 | add a comma) so that it more closely match the MIPS ISA | |
| 986 | documentation opcode partitioning. | |
| 987 | (PREF): Put useful names on opcode fields, and include | |
| 988 | instruction-printing string. | |
| 989 | ||
| ca971540 CD |
990 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
| 991 | ||
| 992 | * mips.igen (check_u64): New function which in the future will | |
| 993 | check whether 64-bit instructions are usable and signal an | |
| 994 | exception if not. Currently a no-op. | |
| 995 | (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL, | |
| 996 | DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, | |
| 997 | DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1, | |
| 998 | LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64. | |
| 999 | ||
| 1000 | * mips.igen (check_fpu): New function which in the future will | |
| 1001 | check whether FPU instructions are usable and signal an exception | |
| 1002 | if not. Currently a no-op. | |
| 1003 | (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb, | |
| 1004 | CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, | |
| 1005 | CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1, | |
| 1006 | LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf, | |
| 1007 | MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, | |
| 1008 | NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt, | |
| 1009 | ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1, | |
| 1010 | SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu. | |
| 1011 | ||
| 1c47a468 CD |
1012 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
| 1013 | ||
| 1014 | * mips.igen (do_load_left, do_load_right): Move to be immediately | |
| 1015 | following do_load. | |
| 1016 | (do_store_left, do_store_right): Move to be immediately following | |
| 1017 | do_store. | |
| 1018 | ||
| 603a98e7 CD |
1019 | 2002-02-27 Chris Demetriou <cgd@broadcom.com> |
| 1020 | ||
| 1021 | * mips.igen (mipsV): New model name. Also, add it to | |
| 1022 | all instructions and functions where it is appropriate. | |
| 1023 | ||
| c5d00cc7 CD |
1024 | 2002-02-18 Chris Demetriou <cgd@broadcom.com> |
| 1025 | ||
| 1026 | * mips.igen: For all functions and instructions, list model | |
| 1027 | names that support that instruction one per line. | |
| 1028 | ||
| 074e9cb8 CD |
1029 | 2002-02-11 Chris Demetriou <cgd@broadcom.com> |
| 1030 | ||
| 1031 | * mips.igen: Add some additional comments about supported | |
| 1032 | models, and about which instructions go where. | |
| 1033 | (BC1b, MFC0, MTC0, RFE): Sort supported models in the same | |
| 1034 | order as is used in the rest of the file. | |
| 1035 | ||
| 9805e229 CD |
1036 | 2002-02-11 Chris Demetriou <cgd@broadcom.com> |
| 1037 | ||
| 1038 | * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment | |
| 1039 | indicating that ALU32_END or ALU64_END are there to check | |
| 1040 | for overflow. | |
| 1041 | (DADD): Likewise, but also remove previous comment about | |
| 1042 | overflow checking. | |
| 1043 | ||
| f701dad2 CD |
1044 | 2002-02-10 Chris Demetriou <cgd@broadcom.com> |
| 1045 | ||
| 1046 | * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, | |
| 1047 | DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, | |
| 1048 | JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, | |
| 1049 | SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, | |
| 1050 | ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode | |
| 1051 | fields (i.e., add and move commas) so that they more closely | |
| 1052 | match the MIPS ISA documentation opcode partitioning. | |
| 1053 | ||
| 1054 | 2002-02-10 Chris Demetriou <cgd@broadcom.com> | |
| 20ae0098 CD |
1055 | |
| 1056 | * mips.igen (ADDI): Print immediate value. | |
| 1057 | (BREAK): Print code. | |
| 1058 | (DADDIU, DSRAV, DSRLV): Print correct instruction name. | |
| 1059 | (SLL): Print "nop" specially, and don't run the code | |
| 1060 | that does the shift for the "nop" case. | |
| 1061 | ||
| 9e52972e FF |
1062 | 2001-11-17 Fred Fish <fnf@redhat.com> |
| 1063 | ||
| 1064 | * sim-main.h (float_operation): Move enum declaration outside | |
| 1065 | of _sim_cpu struct declaration. | |
| 1066 | ||
| c0efbca4 JB |
1067 | 2001-04-12 Jim Blandy <jimb@redhat.com> |
| 1068 | ||
| 1069 | * mips.igen (CFC1, CTC1): Pass the correct register numbers to | |
| 1070 | PENDING_FILL. Use PENDING_SCHED directly to handle the pending | |
| 1071 | set of the FCSR. | |
| 1072 | * sim-main.h (COCIDX): Remove definition; this isn't supported by | |
| 1073 | PENDING_FILL, and you can get the intended effect gracefully by | |
| 1074 | calling PENDING_SCHED directly. | |
| 1075 | ||
| fb891446 BE |
1076 | 2001-02-23 Ben Elliston <bje@redhat.com> |
| 1077 | ||
| 1078 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not | |
| 1079 | already defined elsewhere. | |
| 1080 | ||
| 8030f857 BE |
1081 | 2001-02-19 Ben Elliston <bje@redhat.com> |
| 1082 | ||
| 1083 | * sim-main.h (sim_monitor): Return an int. | |
| 1084 | * interp.c (sim_monitor): Add return values. | |
| 1085 | (signal_exception): Handle error conditions from sim_monitor. | |
| 1086 | ||
| 56b48a7a CD |
1087 | 2001-02-08 Ben Elliston <bje@redhat.com> |
| 1088 | ||
| 1089 | * sim-main.c (load_memory): Pass cia to sim_core_read* functions. | |
| 1090 | (store_memory): Likewise, pass cia to sim_core_write*. | |
| 1091 | ||
| d3ee60d9 FCE |
1092 | 2000-10-19 Frank Ch. Eigler <fche@redhat.com> |
| 1093 | ||
| 1094 | On advice from Chris G. Demetriou <cgd@sibyte.com>: | |
| 1095 | * sim-main.h (GPR_CLEAR): Remove unused alternative macro. | |
| 1096 | ||
| 071da002 AC |
1097 | Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1098 | ||
| 1099 | From Maciej W. Rozycki <macro@ds2.pg.gda.pl>: | |
| 1100 | * Makefile.in: Don't delete *.igen when cleaning directory. | |
| 1101 | ||
| a28c02cd AC |
1102 | Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1103 | ||
| 1104 | * m16.igen (break): Call SignalException not sim_engine_halt. | |
| 1105 | ||
| 80ee11fa AC |
1106 | Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1107 | ||
| 1108 | From Jason Eckhardt: | |
| 1109 | * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT]. | |
| 1110 | ||
| 673388c0 AC |
1111 | Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1112 | ||
| 1113 | * mips.igen (MxC1, DMxC1): Fix printf formatting. | |
| 1114 | ||
| 4c0deff4 NC |
1115 | 2000-05-24 Michael Hayes <mhayes@cygnus.com> |
| 1116 | ||
| 1117 | * mips.igen (do_dmultx): Fix typo. | |
| 1118 | ||
| eb2d80b4 AC |
1119 | Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1120 | ||
| 1121 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1122 | ||
| dd37a34b AC |
1123 | Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1124 | ||
| 1125 | * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. | |
| 1126 | ||
| 4c0deff4 NC |
1127 | 2000-04-12 Frank Ch. Eigler <fche@redhat.com> |
| 1128 | ||
| 1129 | * sim-main.h (GPR_CLEAR): Define macro. | |
| 1130 | ||
| e30db738 AC |
1131 | Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com> |
| 1132 | ||
| 1133 | * interp.c (decode_coproc): Output long using %lx and not %s. | |
| 1134 | ||
| cb7450ea FCE |
1135 | 2000-03-21 Frank Ch. Eigler <fche@redhat.com> |
| 1136 | ||
| 1137 | * interp.c (sim_open): Sort & extend dummy memory regions for | |
| 1138 | --board=jmr3904 for eCos. | |
| 1139 | ||
| a3027dd7 FCE |
1140 | 2000-03-02 Frank Ch. Eigler <fche@redhat.com> |
| 1141 | ||
| 1142 | * configure: Regenerated. | |
| 1143 | ||
| 1144 | Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> | |
| 1145 | ||
| 1146 | * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf | |
| 1147 | calls, conditional on the simulator being in verbose mode. | |
| 1148 | ||
| dfcd3bfb JM |
1149 | Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com> |
| 1150 | ||
| 1151 | * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary | |
| 1152 | cache don't get ReservedInstruction traps. | |
| 1153 | ||
| c2d11a7d JM |
1154 | 1999-11-29 Mark Salter <msalter@cygnus.com> |
| 1155 | ||
| 1156 | * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask | |
| 1157 | to clear status bits in sdisr register. This is how the hardware works. | |
| 1158 | ||
| 1159 | * interp.c (sim_open): Added more memory aliases for jmr3904 hardware | |
| 1160 | being used by cygmon. | |
| 1161 | ||
| 4ce44c66 JM |
1162 | 1999-11-11 Andrew Haley <aph@cygnus.com> |
| 1163 | ||
| 1164 | * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 | |
| 1165 | instructions. | |
| 1166 | ||
| cff3e48b JM |
1167 | Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com> |
| 1168 | ||
| 1169 | * mips.igen (MULT): Correct previous mis-applied patch. | |
| 1170 | ||
| d4f3574e SS |
1171 | Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com> |
| 1172 | ||
| 1173 | * mips.igen (delayslot32): Handle sequence like | |
| 1174 | mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12 | |
| 1175 | correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue. | |
| 1176 | (MULT): Actually pass the third register... | |
| 1177 | ||
| 1178 | 1999-09-03 Mark Salter <msalter@cygnus.com> | |
| 1179 | ||
| 1180 | * interp.c (sim_open): Added more memory aliases for additional | |
| 1181 | hardware being touched by cygmon on jmr3904 board. | |
| 1182 | ||
| 1183 | Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1184 | ||
| 1185 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1186 | ||
| a0b3c4fd JM |
1187 | Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com> |
| 1188 | ||
| 1189 | * interp.c (sim_store_register): Handle case where client - GDB - | |
| 1190 | specifies that a 4 byte register is 8 bytes in size. | |
| 1191 | (sim_fetch_register): Ditto. | |
| 1192 | ||
| adf40b2e JM |
1193 | 1999-07-14 Frank Ch. Eigler <fche@cygnus.com> |
| 1194 | ||
| 1195 | Implement "sim firmware" option, inspired by jimb's version of 1998-01. | |
| 1196 | * interp.c (firmware_option_p): New global flag: "sim firmware" given. | |
| 1197 | (idt_monitor_base): Base address for IDT monitor traps. | |
| 1198 | (pmon_monitor_base): Ditto for PMON. | |
| 1199 | (lsipmon_monitor_base): Ditto for LSI PMON. | |
| 1200 | (MONITOR_BASE, MONITOR_SIZE): Removed macros. | |
| 1201 | (mips_option): Add "firmware" option with new OPTION_FIRMWARE key. | |
| 1202 | (sim_firmware_command): New function. | |
| 1203 | (mips_option_handler): Call it for OPTION_FIRMWARE. | |
| 1204 | (sim_open): Allocate memory for idt_monitor region. If "--board" | |
| 1205 | option was given, add no monitor by default. Add BREAK hooks only if | |
| 1206 | monitors are also there. | |
| 1207 | ||
| 43e526b9 JM |
1208 | Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com> |
| 1209 | ||
| 1210 | * interp.c (sim_monitor): Flush output before reading input. | |
| 1211 | ||
| 1212 | Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1213 | ||
| 1214 | * tconfig.in (SIM_HANDLES_LMA): Always define. | |
| 1215 | ||
| 1216 | Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1217 | ||
| 1218 | From Mark Salter <msalter@cygnus.com>: | |
| 1219 | * interp.c (BOARD_BSP): Define. Add to list of possible boards. | |
| 1220 | (sim_open): Add setup for BSP board. | |
| 1221 | ||
| 9846de1b JM |
1222 | Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com> |
| 1223 | ||
| 1224 | * mips.igen (MULT, MULTU): Add syntax for two operand version. | |
| 1225 | (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report | |
| 1226 | them as unimplemented. | |
| 1227 | ||
| cd0fc7c3 SS |
1228 | 1999-05-08 Felix Lee <flee@cygnus.com> |
| 1229 | ||
| 1230 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1231 | ||
| 7a292a7a SS |
1232 | 1999-04-21 Frank Ch. Eigler <fche@cygnus.com> |
| 1233 | ||
| 1234 | * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub. | |
| 1235 | ||
| 1236 | Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com> | |
| 1237 | ||
| 1238 | * configure.in: Any mips64vr5*-*-* target should have | |
| 1239 | -DTARGET_ENABLE_FR=1. | |
| 1240 | (default_endian): Any mips64vr*el-*-* target should default to | |
| 1241 | LITTLE_ENDIAN. | |
| 1242 | * configure: Re-generate. | |
| 1243 | ||
| 1244 | 1999-02-19 Gavin Romig-Koch <gavin@cygnus.com> | |
| 1245 | ||
| 1246 | * mips.igen (ldl): Extend from _16_, not 32. | |
| 1247 | ||
| 1248 | Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com> | |
| 1249 | ||
| 1250 | * interp.c (sim_store_register): Force registers written to by GDB | |
| 1251 | into an un-interpreted state. | |
| 1252 | ||
| c906108c SS |
1253 | 1999-02-05 Frank Ch. Eigler <fche@cygnus.com> |
| 1254 | ||
| 1255 | * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the | |
| 1256 | CPU, start periodic background I/O polls. | |
| 1257 | (tx3904sio_poll): New function: periodic I/O poller. | |
| 1258 | ||
| 1259 | 1998-12-30 Frank Ch. Eigler <fche@cygnus.com> | |
| 1260 | ||
| 1261 | * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. | |
| 1262 | ||
| 1263 | Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> | |
| 1264 | ||
| 1265 | * configure.in, configure (mips64vr5*-*-*): Added missing ;; in | |
| 1266 | case statement. | |
| 1267 | ||
| 1268 | 1998-12-29 Frank Ch. Eigler <fche@cygnus.com> | |
| 1269 | ||
| 1270 | * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. | |
| 1271 | (load_word): Call SIM_CORE_SIGNAL hook on error. | |
| 1272 | (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before | |
| 1273 | starting. For exception dispatching, pass PC instead of NULL_CIA. | |
| 1274 | (decode_coproc): Use COP0_BADVADDR to store faulting address. | |
| 1275 | * sim-main.h (COP0_BADVADDR): Define. | |
| 1276 | (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. | |
| 1277 | (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). | |
| 1278 | (_sim_cpu): Add exc_* fields to store register value snapshots. | |
| 1279 | * mips.igen (*): Replace memory-related SignalException* calls | |
| 1280 | with references to SIM_CORE_SIGNAL hook. | |
| 1281 | ||
| 1282 | * dv-tx3904irc.c (tx3904irc_port_event): printf format warning | |
| 1283 | fix. | |
| 1284 | * sim-main.c (*): Minor warning cleanups. | |
| 1285 | ||
| 1286 | 1998-12-24 Gavin Romig-Koch <gavin@cygnus.com> | |
| 1287 | ||
| 1288 | * m16.igen (DADDIU5): Correct type-o. | |
| 1289 | ||
| 1290 | Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook> | |
| 1291 | ||
| 1292 | * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp | |
| 1293 | variables. | |
| 1294 | ||
| 1295 | Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook> | |
| 1296 | ||
| 1297 | * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib | |
| 1298 | to include path. | |
| 1299 | (interp.o): Add dependency on itable.h | |
| 1300 | (oengine.c, gencode): Delete remaining references. | |
| 1301 | (BUILT_SRC_FROM_GEN): Clean up. | |
| 1302 | ||
| 1303 | 1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> | |
| 1304 | ||
| 1305 | * vr4run.c: New. | |
| 1306 | * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a, | |
| 1307 | tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack, | |
| 1308 | tmp-run-hack) : New. | |
| 1309 | * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU, | |
| 1310 | DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): | |
| 1311 | Drop the "64" qualifier to get the HACK generator working. | |
| 1312 | Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT. | |
| 1313 | * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only | |
| 1314 | qualifier to get the hack generator working. | |
| 1315 | (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New. | |
| 1316 | (DSLL): Use do_dsll. | |
| 1317 | (DSLLV): Use do_dsllv. | |
| 1318 | (DSRA): Use do_dsra. | |
| 1319 | (DSRL): Use do_dsrl. | |
| 1320 | (DSRLV): Use do_dsrlv. | |
| 1321 | (BC1): Move *vr4100 to get the HACK generator working. | |
| 1322 | (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to | |
| 1323 | get the HACK generator working. | |
| 1324 | (MACC) Rename to get the HACK generator working. | |
| 1325 | (DMACC,MACCS,DMACCS): Add the 64. | |
| 1326 | ||
| 1327 | 1998-12-12 Gavin Romig-Koch <gavin@cygnus.com> | |
| 1328 | ||
| 1329 | * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. | |
| 1330 | * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR. | |
| 1331 | ||
| 1332 | 1998-12-11 Gavin Romig-Koch <gavin@cygnus.com> | |
| 1333 | ||
| 1334 | * mips/interp.c (DEBUG): Cleanups. | |
| 1335 | ||
| 1336 | 1998-12-10 Frank Ch. Eigler <fche@cygnus.com> | |
| 1337 | ||
| 1338 | * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. | |
| 1339 | (tx3904sio_tickle): fflush after a stdout character output. | |
| 1340 | ||
| 1341 | 1998-12-03 Frank Ch. Eigler <fche@cygnus.com> | |
| 1342 | ||
| 1343 | * interp.c (sim_close): Uninstall modules. | |
| 1344 | ||
| 1345 | Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1346 | ||
| 1347 | * sim-main.h, interp.c (sim_monitor): Change to global | |
| 1348 | function. | |
| 1349 | ||
| 1350 | Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1351 | ||
| 1352 | * configure.in (vr4100): Only include vr4100 instructions in | |
| 1353 | simulator. | |
| 1354 | * configure: Re-generate. | |
| 1355 | * m16.igen (*): Tag all mips16 instructions as also being vr4100. | |
| 1356 | ||
| 1357 | Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1358 | ||
| 1359 | * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN. | |
| 1360 | * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping | |
| 1361 | true alternative. | |
| 1362 | ||
| 1363 | * configure.in (sim_default_gen, sim_use_gen): Replace with | |
| 1364 | sim_gen. | |
| 1365 | (--enable-sim-igen): Delete config option. Always using IGEN. | |
| 1366 | * configure: Re-generate. | |
| 1367 | ||
| 1368 | * Makefile.in (gencode): Kill, kill, kill. | |
| 1369 | * gencode.c: Ditto. | |
| 1370 | ||
| 1371 | Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1372 | ||
| 1373 | * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64 | |
| 1374 | bit mips16 igen simulator. | |
| 1375 | * configure: Re-generate. | |
| 1376 | ||
| 1377 | * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark | |
| 1378 | as part of vr4100 ISA. | |
| 1379 | * vr.igen: Mark all instructions as 64 bit only. | |
| 1380 | ||
| 1381 | Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1382 | ||
| 1383 | * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent): | |
| 1384 | Pacify GCC. | |
| 1385 | ||
| 1386 | Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1387 | ||
| 1388 | * configure.in: Configure mips-lsi-elf nee mips*lsi* as a | |
| 1389 | mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos. | |
| 1390 | * configure: Re-generate. | |
| 1391 | ||
| 1392 | * m16.igen (BREAK): Define breakpoint instruction. | |
| 1393 | (JALX32): Mark instruction as mips16 and not r3900. | |
| 1394 | * mips.igen (C.cond.fmt): Fix typo in instruction format. | |
| 1395 | ||
| 1396 | * sim-main.h (PENDING_FILL): Wrap C statements in do/while. | |
| 1397 | ||
| 1398 | Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1399 | ||
| 1400 | * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK | |
| 1401 | insn as a debug breakpoint. | |
| 1402 | ||
| 1403 | * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as | |
| 1404 | pending.slot_size. | |
| 1405 | (PENDING_SCHED): Clean up trace statement. | |
| 1406 | (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. | |
| 1407 | (PENDING_FILL): Delay write by only one cycle. | |
| 1408 | (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. | |
| 1409 | ||
| 1410 | * sim-main.c (pending_tick): Clean up trace statements. Add trace | |
| 1411 | of pending writes. | |
| 1412 | (pending_tick): Fix sizes in switch statements, 4 & 8 instead of | |
| 1413 | 32 & 64. | |
| 1414 | (pending_tick): Move incrementing of index to FOR statement. | |
| 1415 | (pending_tick): Only update PENDING_OUT after a write has occured. | |
| 1416 | ||
| 1417 | * configure.in: Add explicit mips-lsi-* target. Use gencode to | |
| 1418 | build simulator. | |
| 1419 | * configure: Re-generate. | |
| 1420 | ||
| 1421 | * interp.c (sim_engine_run OLD): Delete explicit call to | |
| 1422 | PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. | |
| 1423 | ||
| 1424 | Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1425 | ||
| 1426 | * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy | |
| 1427 | interrupt level number to match changed SignalExceptionInterrupt | |
| 1428 | macro. | |
| 1429 | ||
| 1430 | Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 1431 | ||
| 1432 | * interp.c: #include "itable.h" if WITH_IGEN. | |
| 1433 | (get_insn_name): New function. | |
| 1434 | (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. | |
| 1435 | * sim-main.h (MAX_INSNS,INSN_NAME): Delete. | |
| 1436 | ||
| 1437 | Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1438 | ||
| 1439 | * configure: Rebuilt to inhale new common/aclocal.m4. | |
| 1440 | ||
| 1441 | Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1442 | ||
| 1443 | * dv-tx3904sio.c: Include sim-assert.h. | |
| 1444 | ||
| 1445 | Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1446 | ||
| 1447 | * dv-tx3904sio.c: New file: tx3904 serial I/O module. | |
| 1448 | * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. | |
| 1449 | Reorganize target-specific sim-hardware checks. | |
| 1450 | * configure: rebuilt. | |
| 1451 | * interp.c (sim_open): For tx39 target boards, set | |
| 1452 | OPERATING_ENVIRONMENT, add tx3904sio devices. | |
| 1453 | * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading | |
| 1454 | ROM executables. Install dv-sockser into sim-modules list. | |
| 1455 | ||
| 1456 | * dv-tx3904irc.c: Compiler warning clean-up. | |
| 1457 | * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly | |
| 1458 | frequent hw-trace messages. | |
| 1459 | ||
| 1460 | Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1461 | ||
| 1462 | * vr.igen (MulAcc): Identify as a vr4100 specific function. | |
| 1463 | ||
| 1464 | Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1465 | ||
| 1466 | * Makefile.in (IGEN_INCLUDE): Add vr.igen. | |
| 1467 | ||
| 1468 | * vr.igen: New file. | |
| 1469 | (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. | |
| 1470 | * mips.igen: Define vr4100 model. Include vr.igen. | |
| 1471 | Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com> | |
| 1472 | ||
| 1473 | * mips.igen (check_mf_hilo): Correct check. | |
| 1474 | ||
| 1475 | Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1476 | ||
| 1477 | * sim-main.h (interrupt_event): Add prototype. | |
| 1478 | ||
| 1479 | * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused | |
| 1480 | register_ptr, register_value. | |
| 1481 | (deliver_tx3904tmr_tick): Fix types passed to printf fmt. | |
| 1482 | ||
| 1483 | * sim-main.h (tracefh): Make extern. | |
| 1484 | ||
| 1485 | Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1486 | ||
| 1487 | * dv-tx3904tmr.c: Deschedule timer event after dispatching. | |
| 1488 | Reduce unnecessarily high timer event frequency. | |
| 1489 | * dv-tx3904cpu.c: Ditto for interrupt event. | |
| 1490 | ||
| 1491 | Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1492 | ||
| 1493 | * interp.c (decode_coproc): For TX39, add stub COP0 register #7, | |
| 1494 | to allay warnings. | |
| 1495 | (interrupt_event): Made non-static. | |
| 1496 | ||
| 1497 | * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental | |
| 1498 | interchange of configuration values for external vs. internal | |
| 1499 | clock dividers. | |
| 1500 | ||
| 1501 | Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1502 | ||
| 1503 | * mips.igen (BREAK): Moved code to here for | |
| 1504 | simulator-reserved break instructions. | |
| 1505 | * gencode.c (build_instruction): Ditto. | |
| 1506 | * interp.c (signal_exception): Code moved from here. Non- | |
| 1507 | reserved instructions now use exception vector, rather | |
| 1508 | than halting sim. | |
| 1509 | * sim-main.h: Moved magic constants to here. | |
| 1510 | ||
| 1511 | Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1512 | ||
| 1513 | * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE | |
| 1514 | register upon non-zero interrupt event level, clear upon zero | |
| 1515 | event value. | |
| 1516 | * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal | |
| 1517 | by passing zero event value. | |
| 1518 | (*_io_{read,write}_buffer): Endianness fixes. | |
| 1519 | * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. | |
| 1520 | (deliver_*_tick): Reduce sim event interval to 75% of count interval. | |
| 1521 | ||
| 1522 | * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based | |
| 1523 | serial I/O and timer module at base address 0xFFFF0000. | |
| 1524 | ||
| 1525 | Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com> | |
| 1526 | ||
| 1527 | * mips.igen (SWC1) : Correct the handling of ReverseEndian | |
| 1528 | and BigEndianCPU. | |
| 1529 | ||
| 1530 | Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com> | |
| 1531 | ||
| 1532 | * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips | |
| 1533 | parts. | |
| 1534 | * configure: Update. | |
| 1535 | ||
| 1536 | Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1537 | ||
| 1538 | * dv-tx3904tmr.c: New file - implements tx3904 timer. | |
| 1539 | * dv-tx3904{irc,cpu}.c: Mild reformatting. | |
| 1540 | * configure.in: Include tx3904tmr in hw_device list. | |
| 1541 | * configure: Rebuilt. | |
| 1542 | * interp.c (sim_open): Instantiate three timer instances. | |
| 1543 | Fix address typo of tx3904irc instance. | |
| 1544 | ||
| 1545 | Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1546 | ||
| 1547 | * interp.c (signal_exception): SystemCall exception now uses | |
| 1548 | the exception vector. | |
| 1549 | ||
| 1550 | Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1551 | ||
| 1552 | * interp.c (decode_coproc): For TX39, add stub COP0 register #3, | |
| 1553 | to allay warnings. | |
| 1554 | ||
| 1555 | Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1556 | ||
| 1557 | * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. | |
| 1558 | ||
| 1559 | Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1560 | ||
| 1561 | * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. | |
| 1562 | ||
| 1563 | * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and | |
| 1564 | sim-main.h. Declare a struct hw_descriptor instead of struct | |
| 1565 | hw_device_descriptor. | |
| 1566 | ||
| 1567 | Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1568 | ||
| 1569 | * mips.igen (do_store_left, do_load_left): Compute nr of left and | |
| 1570 | right bits and then re-align left hand bytes to correct byte | |
| 1571 | lanes. Fix incorrect computation in do_store_left when loading | |
| 1572 | bytes from second word. | |
| 1573 | ||
| 1574 | Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1575 | ||
| 1576 | * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. | |
| 1577 | * interp.c (sim_open): Only create a device tree when HW is | |
| 1578 | enabled. | |
| 1579 | ||
| 1580 | * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. | |
| 1581 | * interp.c (signal_exception): Ditto. | |
| 1582 | ||
| 1583 | Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com> | |
| 1584 | ||
| 1585 | * gencode.c: Mark BEGEZALL as LIKELY. | |
| 1586 | ||
| 1587 | Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1588 | ||
| 1589 | * sim-main.h (ALU32_END): Sign extend 32 bit results. | |
| 1590 | * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. | |
| 1591 | ||
| 1592 | Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1593 | ||
| 1594 | * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware | |
| 1595 | modules. Recognize TX39 target with "mips*tx39" pattern. | |
| 1596 | * configure: Rebuilt. | |
| 1597 | * sim-main.h (*): Added many macros defining bits in | |
| 1598 | TX39 control registers. | |
| 1599 | (SignalInterrupt): Send actual PC instead of NULL. | |
| 1600 | (SignalNMIReset): New exception type. | |
| 1601 | * interp.c (board): New variable for future use to identify | |
| 1602 | a particular board being simulated. | |
| 1603 | (mips_option_handler,mips_options): Added "--board" option. | |
| 1604 | (interrupt_event): Send actual PC. | |
| 1605 | (sim_open): Make memory layout conditional on board setting. | |
| 1606 | (signal_exception): Initial implementation of hardware interrupt | |
| 1607 | handling. Accept another break instruction variant for simulator | |
| 1608 | exit. | |
| 1609 | (decode_coproc): Implement RFE instruction for TX39. | |
| 1610 | (mips.igen): Decode RFE instruction as such. | |
| 1611 | * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. | |
| 1612 | * interp.c: Define "jmr3904" and "jmr3904debug" board types and | |
| 1613 | bbegin to implement memory map. | |
| 1614 | * dv-tx3904cpu.c: New file. | |
| 1615 | * dv-tx3904irc.c: New file. | |
| 1616 | ||
| 1617 | Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com> | |
| 1618 | ||
| 1619 | * mips.igen (check_mt_hilo): Create a separate r3900 version. | |
| 1620 | ||
| 1621 | Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com> | |
| 1622 | ||
| 1623 | * tx.igen (madd,maddu): Replace calls to check_op_hilo | |
| 1624 | with calls to check_div_hilo. | |
| 1625 | ||
| 1626 | Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com> | |
| 1627 | ||
| 1628 | * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): | |
| 1629 | Replace check_op_hilo with check_mult_hilo and check_div_hilo. | |
| 1630 | Add special r3900 version of do_mult_hilo. | |
| 1631 | (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo | |
| 1632 | with calls to check_mult_hilo. | |
| 1633 | (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo | |
| 1634 | with calls to check_div_hilo. | |
| 1635 | ||
| 1636 | Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1637 | ||
| 1638 | * configure.in (SUBTARGET_R3900): Define for mipstx39 target. | |
| 1639 | Document a replacement. | |
| 1640 | ||
| 1641 | Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1642 | ||
| 1643 | * interp.c (sim_monitor): Make mon_printf work. | |
| 1644 | ||
| 1645 | Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 1646 | ||
| 1647 | * sim-main.h (INSN_NAME): New arg `cpu'. | |
| 1648 | ||
| 1649 | Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> | |
| 1650 | ||
| 1651 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1652 | ||
| 1653 | Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> | |
| 1654 | ||
| 1655 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1656 | * config.in: Ditto. | |
| 1657 | ||
| 1658 | Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com> | |
| 1659 | ||
| 1660 | * acconfig.h: New file. | |
| 1661 | * configure.in: Reverted change of Apr 24; use sinclude again. | |
| 1662 | ||
| 1663 | Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> | |
| 1664 | ||
| 1665 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1666 | * config.in: Ditto. | |
| 1667 | ||
| 1668 | Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com> | |
| 1669 | ||
| 1670 | * configure.in: Don't call sinclude. | |
| 1671 | ||
| 1672 | Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com> | |
| 1673 | ||
| 1674 | * mips.igen (do_store_left): Pass 0 not NULL to store_memory. | |
| 1675 | ||
| 1676 | Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1677 | ||
| 1678 | * mips.igen (ERET): Implement. | |
| 1679 | ||
| 1680 | * interp.c (decode_coproc): Return sign-extended EPC. | |
| 1681 | ||
| 1682 | * mips.igen (ANDI, LUI, MFC0): Add tracing code. | |
| 1683 | ||
| 1684 | * interp.c (signal_exception): Do not ignore Trap. | |
| 1685 | (signal_exception): On TRAP, restart at exception address. | |
| 1686 | (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. | |
| 1687 | (signal_exception): Update. | |
| 1688 | (sim_open): Patch V_COMMON interrupt vector with an abort sequence | |
| 1689 | so that TRAP instructions are caught. | |
| 1690 | ||
| 1691 | Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1692 | ||
| 1693 | * sim-main.h (struct hilo_access, struct hilo_history): Define, | |
| 1694 | contains HI/LO access history. | |
| 1695 | (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. | |
| 1696 | (HIACCESS, LOACCESS): Delete, replace with | |
| 1697 | (HIHISTORY, LOHISTORY): New macros. | |
| 1698 | (CHECKHILO): Delete all, moved to mips.igen | |
| 1699 | ||
| 1700 | * gencode.c (build_instruction): Do not generate checks for | |
| 1701 | correct HI/LO register usage. | |
| 1702 | ||
| 1703 | * interp.c (old_engine_run): Delete checks for correct HI/LO | |
| 1704 | register usage. | |
| 1705 | ||
| 1706 | * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, | |
| 1707 | check_mf_cycles): New functions. | |
| 1708 | (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, | |
| 1709 | do_divu, domultx, do_mult, do_multu): Use. | |
| 1710 | ||
| 1711 | * tx.igen ("madd", "maddu"): Use. | |
| 1712 | ||
| 1713 | Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1714 | ||
| 1715 | * mips.igen (DSRAV): Use function do_dsrav. | |
| 1716 | (SRAV): Use new function do_srav. | |
| 1717 | ||
| 1718 | * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. | |
| 1719 | (B): Sign extend 11 bit immediate. | |
| 1720 | (EXT-B*): Shift 16 bit immediate left by 1. | |
| 1721 | (ADDIU*): Don't sign extend immediate value. | |
| 1722 | ||
| 1723 | Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1724 | ||
| 1725 | * m16run.c (sim_engine_run): Restore CIA after handling an event. | |
| 1726 | ||
| 1727 | * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use | |
| 1728 | functions. | |
| 1729 | ||
| 1730 | * mips.igen (delayslot32, nullify_next_insn): New functions. | |
| 1731 | (m16.igen): Always include. | |
| 1732 | (do_*): Add more tracing. | |
| 1733 | ||
| 1734 | * m16.igen (delayslot16): Add NIA argument, could be called by a | |
| 1735 | 32 bit MIPS16 instruction. | |
| 1736 | ||
| 1737 | * interp.c (ifetch16): Move function from here. | |
| 1738 | * sim-main.c (ifetch16): To here. | |
| 1739 | ||
| 1740 | * sim-main.c (ifetch16, ifetch32): Update to match current | |
| 1741 | implementations of LH, LW. | |
| 1742 | (signal_exception): Don't print out incorrect hex value of illegal | |
| 1743 | instruction. | |
| 1744 | ||
| 1745 | Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1746 | ||
| 1747 | * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an | |
| 1748 | instruction. | |
| 1749 | ||
| 1750 | * m16.igen: Implement MIPS16 instructions. | |
| 1751 | ||
| 1752 | * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, | |
| 1753 | do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, | |
| 1754 | do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, | |
| 1755 | do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, | |
| 1756 | do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move | |
| 1757 | bodies of corresponding code from 32 bit insn to these. Also used | |
| 1758 | by MIPS16 versions of functions. | |
| 1759 | ||
| 1760 | * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. | |
| 1761 | (IMEM16): Drop NR argument from macro. | |
| 1762 | ||
| 1763 | Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1764 | ||
| 1765 | * Makefile.in (SIM_OBJS): Add sim-main.o. | |
| 1766 | ||
| 1767 | * sim-main.h (address_translation, load_memory, store_memory, | |
| 1768 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark | |
| 1769 | as INLINE_SIM_MAIN. | |
| 1770 | (pr_addr, pr_uword64): Declare. | |
| 1771 | (sim-main.c): Include when H_REVEALS_MODULE_P. | |
| 1772 | ||
| 1773 | * interp.c (address_translation, load_memory, store_memory, | |
| 1774 | cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move | |
| 1775 | from here. | |
| 1776 | * sim-main.c: To here. Fix compilation problems. | |
| 1777 | ||
| 1778 | * configure.in: Enable inlining. | |
| 1779 | * configure: Re-config. | |
| 1780 | ||
| 1781 | Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1782 | ||
| 1783 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1784 | ||
| 1785 | Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1786 | ||
| 1787 | * mips.igen: Include tx.igen. | |
| 1788 | * Makefile.in (IGEN_INCLUDE): Add tx.igen. | |
| 1789 | * tx.igen: New file, contains MADD and MADDU. | |
| 1790 | ||
| 1791 | * interp.c (load_memory): When shifting bytes, use LOADDRMASK not | |
| 1792 | the hardwired constant `7'. | |
| 1793 | (store_memory): Ditto. | |
| 1794 | (LOADDRMASK): Move definition to sim-main.h. | |
| 1795 | ||
| 1796 | mips.igen (MTC0): Enable for r3900. | |
| 1797 | (ADDU): Add trace. | |
| 1798 | ||
| 1799 | mips.igen (do_load_byte): Delete. | |
| 1800 | (do_load, do_store, do_load_left, do_load_write, do_store_left, | |
| 1801 | do_store_right): New functions. | |
| 1802 | (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. | |
| 1803 | ||
| 1804 | configure.in: Let the tx39 use igen again. | |
| 1805 | configure: Update. | |
| 1806 | ||
| 1807 | Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1808 | ||
| 1809 | * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, | |
| 1810 | not an address sized quantity. Return zero for cache sizes. | |
| 1811 | ||
| 1812 | Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1813 | ||
| 1814 | * mips.igen (r3900): r3900 does not support 64 bit integer | |
| 1815 | operations. | |
| 1816 | ||
| 1817 | Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> | |
| 1818 | ||
| 1819 | * configure.in (mipstx39*-*-*): Use gencode simulator rather | |
| 1820 | than igen one. | |
| 1821 | * configure : Rebuild. | |
| 1822 | ||
| 1823 | Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1824 | ||
| 1825 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1826 | ||
| 1827 | Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1828 | ||
| 1829 | * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. | |
| 1830 | ||
| 1831 | Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1832 | ||
| 1833 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1834 | * config.in: Regenerated to track ../common/aclocal.m4 changes. | |
| 1835 | ||
| 1836 | Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1837 | ||
| 1838 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1839 | ||
| 1840 | Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1841 | ||
| 1842 | * interp.c (Max, Min): Comment out functions. Not yet used. | |
| 1843 | ||
| 1844 | Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1845 | ||
| 1846 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1847 | ||
| 1848 | Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> | |
| 1849 | ||
| 1850 | * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added | |
| 1851 | configurable settings for stand-alone simulator. | |
| 1852 | ||
| 1853 | * configure.in: Added X11 search, just in case. | |
| 1854 | ||
| 1855 | * configure: Regenerated. | |
| 1856 | ||
| 1857 | Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1858 | ||
| 1859 | * interp.c (sim_write, sim_read, load_memory, store_memory): | |
| 1860 | Replace sim_core_*_map with read_map, write_map, exec_map resp. | |
| 1861 | ||
| 1862 | Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1863 | ||
| 1864 | * sim-main.h (GETFCC): Return an unsigned value. | |
| 1865 | ||
| 1866 | Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1867 | ||
| 1868 | * mips.igen (DIV): Fix check for -1 / MIN_INT. | |
| 1869 | (DADD): Result destination is RD not RT. | |
| 1870 | ||
| 1871 | Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1872 | ||
| 1873 | * sim-main.h (HIACCESS, LOACCESS): Always define. | |
| 1874 | ||
| 1875 | * mdmx.igen (Maxi, Mini): Rename Max, Min. | |
| 1876 | ||
| 1877 | * interp.c (sim_info): Delete. | |
| 1878 | ||
| 1879 | Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> | |
| 1880 | ||
| 1881 | * interp.c (DECLARE_OPTION_HANDLER): Use it. | |
| 1882 | (mips_option_handler): New argument `cpu'. | |
| 1883 | (sim_open): Update call to sim_add_option_table. | |
| 1884 | ||
| 1885 | Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1886 | ||
| 1887 | * mips.igen (CxC1): Add tracing. | |
| 1888 | ||
| 1889 | Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1890 | ||
| 1891 | * sim-main.h (Max, Min): Declare. | |
| 1892 | ||
| 1893 | * interp.c (Max, Min): New functions. | |
| 1894 | ||
| 1895 | * mips.igen (BC1): Add tracing. | |
| 1896 | ||
| 1897 | Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> | |
| 1898 | ||
| 1899 | * interp.c Added memory map for stack in vr4100 | |
| 1900 | ||
| 1901 | Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> | |
| 1902 | ||
| 1903 | * interp.c (load_memory): Add missing "break"'s. | |
| 1904 | ||
| 1905 | Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1906 | ||
| 1907 | * interp.c (sim_store_register, sim_fetch_register): Pass in | |
| 1908 | length parameter. Return -1. | |
| 1909 | ||
| 1910 | Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> | |
| 1911 | ||
| 1912 | * interp.c: Added hardware init hook, fixed warnings. | |
| 1913 | ||
| 1914 | Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1915 | ||
| 1916 | * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. | |
| 1917 | ||
| 1918 | Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1919 | ||
| 1920 | * interp.c (ifetch16): New function. | |
| 1921 | ||
| 1922 | * sim-main.h (IMEM32): Rename IMEM. | |
| 1923 | (IMEM16_IMMED): Define. | |
| 1924 | (IMEM16): Define. | |
| 1925 | (DELAY_SLOT): Update. | |
| 1926 | ||
| 1927 | * m16run.c (sim_engine_run): New file. | |
| 1928 | ||
| 1929 | * m16.igen: All instructions except LB. | |
| 1930 | (LB): Call do_load_byte. | |
| 1931 | * mips.igen (do_load_byte): New function. | |
| 1932 | (LB): Call do_load_byte. | |
| 1933 | ||
| 1934 | * mips.igen: Move spec for insn bit size and high bit from here. | |
| 1935 | * Makefile.in (tmp-igen, tmp-m16): To here. | |
| 1936 | ||
| 1937 | * m16.dc: New file, decode mips16 instructions. | |
| 1938 | ||
| 1939 | * Makefile.in (SIM_NO_ALL): Define. | |
| 1940 | (tmp-m16): Generate both 16 bit and 32 bit simulator engines. | |
| 1941 | ||
| 1942 | Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1943 | ||
| 1944 | * configure.in (mips_fpu_bitsize): For tx39, restrict floating | |
| 1945 | point unit to 32 bit registers. | |
| 1946 | * configure: Re-generate. | |
| 1947 | ||
| 1948 | Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1949 | ||
| 1950 | * configure.in (sim_use_gen): Make IGEN the default simulator | |
| 1951 | generator for generic 32 and 64 bit mips targets. | |
| 1952 | * configure: Re-generate. | |
| 1953 | ||
| 1954 | Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1955 | ||
| 1956 | * sim-main.h (SizeFGR): Determine from floating-point and not gpr | |
| 1957 | bitsize. | |
| 1958 | ||
| 1959 | * interp.c (sim_fetch_register, sim_store_register): Read/write | |
| 1960 | FGR from correct location. | |
| 1961 | (sim_open): Set size of FGR's according to | |
| 1962 | WITH_TARGET_FLOATING_POINT_BITSIZE. | |
| 1963 | ||
| 1964 | * sim-main.h (FGR): Store floating point registers in a separate | |
| 1965 | array. | |
| 1966 | ||
| 1967 | Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1968 | ||
| 1969 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 1970 | ||
| 1971 | Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1972 | ||
| 1973 | * interp.c (ColdReset): Call PENDING_INVALIDATE. | |
| 1974 | ||
| 1975 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. | |
| 1976 | ||
| 1977 | * interp.c (pending_tick): New function. Deliver pending writes. | |
| 1978 | ||
| 1979 | * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, | |
| 1980 | PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that | |
| 1981 | it can handle mixed sized quantites and single bits. | |
| 1982 | ||
| 1983 | Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1984 | ||
| 1985 | * interp.c (oengine.h): Do not include when building with IGEN. | |
| 1986 | (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. | |
| 1987 | (sim_info): Ditto for PROCESSOR_64BIT. | |
| 1988 | (sim_monitor): Replace ut_reg with unsigned_word. | |
| 1989 | (*): Ditto for t_reg. | |
| 1990 | (LOADDRMASK): Define. | |
| 1991 | (sim_open): Remove defunct check that host FP is IEEE compliant, | |
| 1992 | using software to emulate floating point. | |
| 1993 | (value_fpr, ...): Always compile, was conditional on HASFPU. | |
| 1994 | ||
| 1995 | Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 1996 | ||
| 1997 | * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in | |
| 1998 | size. | |
| 1999 | ||
| 2000 | * interp.c (SD, CPU): Define. | |
| 2001 | (mips_option_handler): Set flags in each CPU. | |
| 2002 | (interrupt_event): Assume CPU 0 is the one being iterrupted. | |
| 2003 | (sim_close): Do not clear STATE, deleted anyway. | |
| 2004 | (sim_write, sim_read): Assume CPU zero's vm should be used for | |
| 2005 | data transfers. | |
| 2006 | (sim_create_inferior): Set the PC for all processors. | |
| 2007 | (sim_monitor, store_word, load_word, mips16_entry): Add cpu | |
| 2008 | argument. | |
| 2009 | (mips16_entry): Pass correct nr of args to store_word, load_word. | |
| 2010 | (ColdReset): Cold reset all cpu's. | |
| 2011 | (signal_exception): Pass cpu to sim_monitor & mips16_entry. | |
| 2012 | (sim_monitor, load_memory, store_memory, signal_exception): Use | |
| 2013 | `CPU' instead of STATE_CPU. | |
| 2014 | ||
| 2015 | ||
| 2016 | * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with | |
| 2017 | SD or CPU_. | |
| 2018 | ||
| 2019 | * sim-main.h (signal_exception): Add sim_cpu arg. | |
| 2020 | (SignalException*): Pass both SD and CPU to signal_exception. | |
| 2021 | * interp.c (signal_exception): Update. | |
| 2022 | ||
| 2023 | * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: | |
| 2024 | Ditto | |
| 2025 | (sync_operation, prefetch, cache_op, store_memory, load_memory, | |
| 2026 | address_translation): Ditto | |
| 2027 | (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. | |
| 2028 | ||
| 2029 | Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2030 | ||
| 2031 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2032 | ||
| 2033 | Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2034 | ||
| 2035 | * interp.c (sim_engine_run): Add `nr_cpus' argument. | |
| 2036 | ||
| 2037 | * mips.igen (model): Map processor names onto BFD name. | |
| 2038 | ||
| 2039 | * sim-main.h (CPU_CIA): Delete. | |
| 2040 | (SET_CIA, GET_CIA): Define | |
| 2041 | ||
| 2042 | Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2043 | ||
| 2044 | * sim-main.h (GPR_SET): Define, used by igen when zeroing a | |
| 2045 | regiser. | |
| 2046 | ||
| 2047 | * configure.in (default_endian): Configure a big-endian simulator | |
| 2048 | by default. | |
| 2049 | * configure: Re-generate. | |
| 2050 | ||
| 2051 | Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> | |
| 2052 | ||
| 2053 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2054 | ||
| 2055 | Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> | |
| 2056 | ||
| 2057 | * interp.c (sim_monitor): Handle Densan monitor outbyte | |
| 2058 | and inbyte functions. | |
| 2059 | ||
| 2060 | 1997-12-29 Felix Lee <flee@cygnus.com> | |
| 2061 | ||
| 2062 | * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). | |
| 2063 | ||
| 2064 | Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) | |
| 2065 | ||
| 2066 | * Makefile.in (tmp-igen): Arrange for $zero to always be | |
| 2067 | reset to zero after every instruction. | |
| 2068 | ||
| 2069 | Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2070 | ||
| 2071 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2072 | * config.in: Ditto. | |
| 2073 | ||
| 2074 | Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) | |
| 2075 | ||
| 2076 | * mips.igen (MSUB): Fix to work like MADD. | |
| 2077 | * gencode.c (MSUB): Similarly. | |
| 2078 | ||
| 2079 | Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> | |
| 2080 | ||
| 2081 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2082 | ||
| 2083 | Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2084 | ||
| 2085 | * mips.igen (LWC1): Correct assembler - lwc1 not swc1. | |
| 2086 | ||
| 2087 | Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2088 | ||
| 2089 | * sim-main.h (sim-fpu.h): Include. | |
| 2090 | ||
| 2091 | * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, | |
| 2092 | Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite | |
| 2093 | using host independant sim_fpu module. | |
| 2094 | ||
| 2095 | Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2096 | ||
| 2097 | * interp.c (signal_exception): Report internal errors with SIGABRT | |
| 2098 | not SIGQUIT. | |
| 2099 | ||
| 2100 | * sim-main.h (C0_CONFIG): New register. | |
| 2101 | (signal.h): No longer include. | |
| 2102 | ||
| 2103 | * interp.c (decode_coproc): Allow access C0_CONFIG to register. | |
| 2104 | ||
| 2105 | Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> | |
| 2106 | ||
| 2107 | * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). | |
| 2108 | ||
| 2109 | Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2110 | ||
| 2111 | * mips.igen: Tag vr5000 instructions. | |
| 2112 | (ANDI): Was missing mipsIV model, fix assembler syntax. | |
| 2113 | (do_c_cond_fmt): New function. | |
| 2114 | (C.cond.fmt): Handle mips I-III which do not support CC field | |
| 2115 | separatly. | |
| 2116 | (bc1): Handle mips IV which do not have a delaed FCC separatly. | |
| 2117 | (SDR): Mask paddr when BigEndianMem, not the converse as specified | |
| 2118 | in IV3.2 spec. | |
| 2119 | (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle | |
| 2120 | vr5000 which saves LO in a GPR separatly. | |
| 2121 | ||
| 2122 | * configure.in (enable-sim-igen): For vr5000, select vr5000 | |
| 2123 | specific instructions. | |
| 2124 | * configure: Re-generate. | |
| 2125 | ||
| 2126 | Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2127 | ||
| 2128 | * Makefile.in (SIM_OBJS): Add sim-fpu module. | |
| 2129 | ||
| 2130 | * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and | |
| 2131 | fmt_uninterpreted_64 bit cases to switch. Convert to | |
| 2132 | fmt_formatted, | |
| 2133 | ||
| 2134 | * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, | |
| 2135 | ||
| 2136 | * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse | |
| 2137 | as specified in IV3.2 spec. | |
| 2138 | (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. | |
| 2139 | ||
| 2140 | Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2141 | ||
| 2142 | * mips.igen: Delay slot branches add OFFSET to NIA not CIA. | |
| 2143 | (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. | |
| 2144 | (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non | |
| 2145 | PENDING_FILL versions of instructions. Simplify. | |
| 2146 | (X): New function. | |
| 2147 | (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of | |
| 2148 | instructions. | |
| 2149 | (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to | |
| 2150 | a signed value. | |
| 2151 | (MTHI, MFHI): Disable code checking HI-LO. | |
| 2152 | ||
| 2153 | * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh | |
| 2154 | global. | |
| 2155 | (NULLIFY_NEXT_INSTRUCTION): Call dotrace. | |
| 2156 | ||
| 2157 | Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2158 | ||
| 2159 | * gencode.c (build_mips16_operands): Replace IPC with cia. | |
| 2160 | ||
| 2161 | * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, | |
| 2162 | value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace | |
| 2163 | IPC to `cia'. | |
| 2164 | (UndefinedResult): Replace function with macro/function | |
| 2165 | combination. | |
| 2166 | (sim_engine_run): Don't save PC in IPC. | |
| 2167 | ||
| 2168 | * sim-main.h (IPC): Delete. | |
| 2169 | ||
| 2170 | ||
| 2171 | * interp.c (signal_exception, store_word, load_word, | |
| 2172 | address_translation, load_memory, store_memory, cache_op, | |
| 2173 | prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, | |
| 2174 | cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add | |
| 2175 | current instruction address - cia - argument. | |
| 2176 | (sim_read, sim_write): Call address_translation directly. | |
| 2177 | (sim_engine_run): Rename variable vaddr to cia. | |
| 2178 | (signal_exception): Pass cia to sim_monitor | |
| 2179 | ||
| 2180 | * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, | |
| 2181 | Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, | |
| 2182 | COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. | |
| 2183 | ||
| 2184 | * sim-main.h (SignalExceptionSimulatorFault): Delete definition. | |
| 2185 | * interp.c (sim_open): Replace SignalExceptionSimulatorFault with | |
| 2186 | SIM_ASSERT. | |
| 2187 | ||
| 2188 | * interp.c (signal_exception): Pass restart address to | |
| 2189 | sim_engine_restart. | |
| 2190 | ||
| 2191 | * Makefile.in (semantics.o, engine.o, support.o, itable.o, | |
| 2192 | idecode.o): Add dependency. | |
| 2193 | ||
| 2194 | * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): | |
| 2195 | Delete definitions | |
| 2196 | (DELAY_SLOT): Update NIA not PC with branch address. | |
| 2197 | (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. | |
| 2198 | ||
| 2199 | * mips.igen: Use CIA not PC in branch calculations. | |
| 2200 | (illegal): Call SignalException. | |
| 2201 | (BEQ, ADDIU): Fix assembler. | |
| 2202 | ||
| 2203 | Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2204 | ||
| 2205 | * m16.igen (JALX): Was missing. | |
| 2206 | ||
| 2207 | * configure.in (enable-sim-igen): New configuration option. | |
| 2208 | * configure: Re-generate. | |
| 2209 | ||
| 2210 | * sim-main.h (MAX_INSNS, INSN_NAME): Define. | |
| 2211 | ||
| 2212 | * interp.c (load_memory, store_memory): Delete parameter RAW. | |
| 2213 | (sim_read, sim_write): Use sim_core_{read,write}_buffer directly | |
| 2214 | bypassing {load,store}_memory. | |
| 2215 | ||
| 2216 | * sim-main.h (ByteSwapMem): Delete definition. | |
| 2217 | ||
| 2218 | * Makefile.in (SIM_OBJS): Add sim-memopt module. | |
| 2219 | ||
| 2220 | * interp.c (sim_do_command, sim_commands): Delete mips specific | |
| 2221 | commands. Handled by module sim-options. | |
| 2222 | ||
| 2223 | * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. | |
| 2224 | (WITH_MODULO_MEMORY): Define. | |
| 2225 | ||
| 2226 | * interp.c (sim_info): Delete code printing memory size. | |
| 2227 | ||
| 2228 | * interp.c (mips_size): Nee sim_size, delete function. | |
| 2229 | (power2): Delete. | |
| 2230 | (monitor, monitor_base, monitor_size): Delete global variables. | |
| 2231 | (sim_open, sim_close): Delete code creating monitor and other | |
| 2232 | memory regions. Use sim-memopts module, via sim_do_commandf, to | |
| 2233 | manage memory regions. | |
| 2234 | (load_memory, store_memory): Use sim-core for memory model. | |
| 2235 | ||
| 2236 | * interp.c (address_translation): Delete all memory map code | |
| 2237 | except line forcing 32 bit addresses. | |
| 2238 | ||
| 2239 | Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2240 | ||
| 2241 | * sim-main.h (WITH_TRACE): Delete definition. Enables common | |
| 2242 | trace options. | |
| 2243 | ||
| 2244 | * interp.c (logfh, logfile): Delete globals. | |
| 2245 | (sim_open, sim_close): Delete code opening & closing log file. | |
| 2246 | (mips_option_handler): Delete -l and -n options. | |
| 2247 | (OPTION mips_options): Ditto. | |
| 2248 | ||
| 2249 | * interp.c (OPTION mips_options): Rename option trace to dinero. | |
| 2250 | (mips_option_handler): Update. | |
| 2251 | ||
| 2252 | Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2253 | ||
| 2254 | * interp.c (fetch_str): New function. | |
| 2255 | (sim_monitor): Rewrite using sim_read & sim_write. | |
| 2256 | (sim_open): Check magic number. | |
| 2257 | (sim_open): Write monitor vectors into memory using sim_write. | |
| 2258 | (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. | |
| 2259 | (sim_read, sim_write): Simplify - transfer data one byte at a | |
| 2260 | time. | |
| 2261 | (load_memory, store_memory): Clarify meaning of parameter RAW. | |
| 2262 | ||
| 2263 | * sim-main.h (isHOST): Defete definition. | |
| 2264 | (isTARGET): Mark as depreciated. | |
| 2265 | (address_translation): Delete parameter HOST. | |
| 2266 | ||
| 2267 | * interp.c (address_translation): Delete parameter HOST. | |
| 2268 | ||
| 2269 | Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2270 | ||
| 2271 | * mips.igen: | |
| 2272 | ||
| 2273 | * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. | |
| 2274 | (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. | |
| 2275 | ||
| 2276 | Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2277 | ||
| 2278 | * mips.igen: Add model filter field to records. | |
| 2279 | ||
| 2280 | Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2281 | ||
| 2282 | * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. | |
| 2283 | ||
| 2284 | interp.c (sim_engine_run): Do not compile function sim_engine_run | |
| 2285 | when WITH_IGEN == 1. | |
| 2286 | ||
| 2287 | * configure.in (sim_igen_flags, sim_m16_flags): Set according to | |
| 2288 | target architecture. | |
| 2289 | ||
| 2290 | Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to | |
| 2291 | igen. Replace with configuration variables sim_igen_flags / | |
| 2292 | sim_m16_flags. | |
| 2293 | ||
| 2294 | * m16.igen: New file. Copy mips16 insns here. | |
| 2295 | * mips.igen: From here. | |
| 2296 | ||
| 2297 | Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2298 | ||
| 2299 | * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ | |
| 2300 | to top. | |
| 2301 | (tmp-igen, tmp-m16): Pass -I srcdir to igen. | |
| 2302 | ||
| 2303 | Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> | |
| 2304 | ||
| 2305 | * gencode.c (build_instruction): Follow sim_write's lead in using | |
| 2306 | BigEndianMem instead of !ByteSwapMem. | |
| 2307 | ||
| 2308 | Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2309 | ||
| 2310 | * configure.in (sim_gen): Dependent on target, select type of | |
| 2311 | generator. Always select old style generator. | |
| 2312 | ||
| 2313 | configure: Re-generate. | |
| 2314 | ||
| 2315 | Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New | |
| 2316 | targets. | |
| 2317 | (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, | |
| 2318 | SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, | |
| 2319 | IGEN_TRACE, IGEN_INSN, IGEN_DC): Define | |
| 2320 | (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member | |
| 2321 | SIM_@sim_gen@_*, set by autoconf. | |
| 2322 | ||
| 2323 | Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2324 | ||
| 2325 | * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. | |
| 2326 | ||
| 2327 | * interp.c (ColdReset): Remove #ifdef HASFPU, check | |
| 2328 | CURRENT_FLOATING_POINT instead. | |
| 2329 | ||
| 2330 | * interp.c (ifetch32): New function. Fetch 32 bit instruction. | |
| 2331 | (address_translation): Raise exception InstructionFetch when | |
| 2332 | translation fails and isINSTRUCTION. | |
| 2333 | ||
| 2334 | * interp.c (sim_open, sim_write, sim_monitor, store_word, | |
| 2335 | sim_engine_run): Change type of of vaddr and paddr to | |
| 2336 | address_word. | |
| 2337 | (address_translation, prefetch, load_memory, store_memory, | |
| 2338 | cache_op): Change type of vAddr and pAddr to address_word. | |
| 2339 | ||
| 2340 | * gencode.c (build_instruction): Change type of vaddr and paddr to | |
| 2341 | address_word. | |
| 2342 | ||
| 2343 | Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2344 | ||
| 2345 | * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT | |
| 2346 | macro to obtain result of ALU op. | |
| 2347 | ||
| 2348 | Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2349 | ||
| 2350 | * interp.c (sim_info): Call profile_print. | |
| 2351 | ||
| 2352 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2353 | ||
| 2354 | * Makefile.in (SIM_OBJS): Add sim-profile.o module. | |
| 2355 | ||
| 2356 | * sim-main.h (WITH_PROFILE): Do not define, defined in | |
| 2357 | common/sim-config.h. Use sim-profile module. | |
| 2358 | (simPROFILE): Delete defintion. | |
| 2359 | ||
| 2360 | * interp.c (PROFILE): Delete definition. | |
| 2361 | (mips_option_handler): Delete 'p', 'y' and 'x' profile options. | |
| 2362 | (sim_close): Delete code writing profile histogram. | |
| 2363 | (mips_set_profile, mips_set_profile_size, writeout16, writeout32): | |
| 2364 | Delete. | |
| 2365 | (sim_engine_run): Delete code profiling the PC. | |
| 2366 | ||
| 2367 | Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2368 | ||
| 2369 | * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. | |
| 2370 | ||
| 2371 | * interp.c (sim_monitor): Make register pointers of type | |
| 2372 | unsigned_word*. | |
| 2373 | ||
| 2374 | * sim-main.h: Make registers of type unsigned_word not | |
| 2375 | signed_word. | |
| 2376 | ||
| 2377 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2378 | ||
| 2379 | * interp.c (sync_operation): Rename from SyncOperation, make | |
| 2380 | global, add SD argument. | |
| 2381 | (prefetch): Rename from Prefetch, make global, add SD argument. | |
| 2382 | (decode_coproc): Make global. | |
| 2383 | ||
| 2384 | * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. | |
| 2385 | ||
| 2386 | * gencode.c (build_instruction): Generate DecodeCoproc not | |
| 2387 | decode_coproc calls. | |
| 2388 | ||
| 2389 | * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h | |
| 2390 | (SizeFGR): Move to sim-main.h | |
| 2391 | (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, | |
| 2392 | simSIGINT, simJALDELAYSLOT): Move to sim-main.h | |
| 2393 | (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to | |
| 2394 | sim-main.h. | |
| 2395 | (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, | |
| 2396 | FP_RM_TOMINF, GETRM): Move to sim-main.h. | |
| 2397 | (Uncached, CachedNoncoherent, CachedCoherent, Cached, | |
| 2398 | isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. | |
| 2399 | (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, | |
| 2400 | BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h | |
| 2401 | ||
| 2402 | * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise | |
| 2403 | exception. | |
| 2404 | (sim-alu.h): Include. | |
| 2405 | (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. | |
| 2406 | (sim_cia): Typedef to instruction_address. | |
| 2407 | ||
| 2408 | Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2409 | ||
| 2410 | * Makefile.in (interp.o): Rename generated file engine.c to | |
| 2411 | oengine.c. | |
| 2412 | ||
| 2413 | * interp.c: Update. | |
| 2414 | ||
| 2415 | Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2416 | ||
| 2417 | * gencode.c (build_instruction): Use FPR_STATE not fpr_state. | |
| 2418 | ||
| 2419 | Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2420 | ||
| 2421 | * gencode.c (build_instruction): For "FPSQRT", output correct | |
| 2422 | number of arguments to Recip. | |
| 2423 | ||
| 2424 | Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2425 | ||
| 2426 | * Makefile.in (interp.o): Depends on sim-main.h | |
| 2427 | ||
| 2428 | * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. | |
| 2429 | ||
| 2430 | * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, | |
| 2431 | ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. | |
| 2432 | (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, | |
| 2433 | STATE, DSSTATE): Define | |
| 2434 | (GPR, FGRIDX, ..): Define. | |
| 2435 | ||
| 2436 | * interp.c (registers, register_widths, fpr_state, ipc, dspc, | |
| 2437 | pending_*, hiaccess, loaccess, state, dsstate): Delete globals. | |
| 2438 | (GPR, FGRIDX, ...): Delete macros. | |
| 2439 | ||
| 2440 | * interp.c: Update names to match defines from sim-main.h | |
| 2441 | ||
| 2442 | Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2443 | ||
| 2444 | * interp.c (sim_monitor): Add SD argument. | |
| 2445 | (sim_warning): Delete. Replace calls with calls to | |
| 2446 | sim_io_eprintf. | |
| 2447 | (sim_error): Delete. Replace calls with sim_io_error. | |
| 2448 | (open_trace, writeout32, writeout16, getnum): Add SD argument. | |
| 2449 | (mips_set_profile): Rename from sim_set_profile. Add SD argument. | |
| 2450 | (mips_set_profile_size): Rename from sim_set_profile_size. Add SD | |
| 2451 | argument. | |
| 2452 | (mips_size): Rename from sim_size. Add SD argument. | |
| 2453 | ||
| 2454 | * interp.c (simulator): Delete global variable. | |
| 2455 | (callback): Delete global variable. | |
| 2456 | (mips_option_handler, sim_open, sim_write, sim_read, | |
| 2457 | sim_store_register, sim_fetch_register, sim_info, sim_do_command, | |
| 2458 | sim_size,sim_monitor): Use sim_io_* not callback->*. | |
| 2459 | (sim_open): ZALLOC simulator struct. | |
| 2460 | (PROFILE): Do not define. | |
| 2461 | ||
| 2462 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2463 | ||
| 2464 | * interp.c (sim_open), support.h: Replace CHECKSIM macro found in | |
| 2465 | support.h with corresponding code. | |
| 2466 | ||
| 2467 | * sim-main.h (word64, uword64), support.h: Move definition to | |
| 2468 | sim-main.h. | |
| 2469 | (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. | |
| 2470 | ||
| 2471 | * support.h: Delete | |
| 2472 | * Makefile.in: Update dependencies | |
| 2473 | * interp.c: Do not include. | |
| 2474 | ||
| 2475 | Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2476 | ||
| 2477 | * interp.c (address_translation, load_memory, store_memory, | |
| 2478 | cache_op): Rename to from AddressTranslation et.al., make global, | |
| 2479 | add SD argument | |
| 2480 | ||
| 2481 | * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, | |
| 2482 | CacheOp): Define. | |
| 2483 | ||
| 2484 | * interp.c (SignalException): Rename to signal_exception, make | |
| 2485 | global. | |
| 2486 | ||
| 2487 | * interp.c (Interrupt, ...): Move definitions to sim-main.h. | |
| 2488 | ||
| 2489 | * sim-main.h (SignalException, SignalExceptionInterrupt, | |
| 2490 | SignalExceptionInstructionFetch, SignalExceptionAddressStore, | |
| 2491 | SignalExceptionAddressLoad, SignalExceptionSimulatorFault, | |
| 2492 | SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): | |
| 2493 | Define. | |
| 2494 | ||
| 2495 | * interp.c, support.h: Use. | |
| 2496 | ||
| 2497 | Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2498 | ||
| 2499 | * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename | |
| 2500 | to value_fpr / store_fpr. Add SD argument. | |
| 2501 | (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, | |
| 2502 | Multiply, Divide, Recip, SquareRoot, Convert): Make global. | |
| 2503 | ||
| 2504 | * sim-main.h (ValueFPR, StoreFPR): Define. | |
| 2505 | ||
| 2506 | Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2507 | ||
| 2508 | * interp.c (sim_engine_run): Check consistency between configure | |
| 2509 | WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN | |
| 2510 | and HASFPU. | |
| 2511 | ||
| 2512 | * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. | |
| 2513 | (mips_fpu): Configure WITH_FLOATING_POINT. | |
| 2514 | (mips_endian): Configure WITH_TARGET_ENDIAN. | |
| 2515 | * configure: Update. | |
| 2516 | ||
| 2517 | Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2518 | ||
| 2519 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2520 | ||
| 2521 | Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> | |
| 2522 | ||
| 2523 | * configure: Regenerated. | |
| 2524 | ||
| 2525 | Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> | |
| 2526 | ||
| 2527 | * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. | |
| 2528 | ||
| 2529 | Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2530 | ||
| 2531 | * gencode.c (print_igen_insn_models): Assume certain architectures | |
| 2532 | include all mips* instructions. | |
| 2533 | (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 | |
| 2534 | instruction. | |
| 2535 | ||
| 2536 | * Makefile.in (tmp.igen): Add target. Generate igen input from | |
| 2537 | gencode file. | |
| 2538 | ||
| 2539 | * gencode.c (FEATURE_IGEN): Define. | |
| 2540 | (main): Add --igen option. Generate output in igen format. | |
| 2541 | (process_instructions): Format output according to igen option. | |
| 2542 | (print_igen_insn_format): New function. | |
| 2543 | (print_igen_insn_models): New function. | |
| 2544 | (process_instructions): Only issue warnings and ignore | |
| 2545 | instructions when no FEATURE_IGEN. | |
| 2546 | ||
| 2547 | Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2548 | ||
| 2549 | * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some | |
| 2550 | MIPS targets. | |
| 2551 | ||
| 2552 | Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2553 | ||
| 2554 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2555 | ||
| 2556 | Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2557 | ||
| 2558 | * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, | |
| 2559 | SIM_RESERVED_BITS): Delete, moved to common. | |
| 2560 | (SIM_EXTRA_CFLAGS): Update. | |
| 2561 | ||
| 2562 | Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2563 | ||
| 2564 | * configure.in: Configure non-strict memory alignment. | |
| 2565 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2566 | ||
| 2567 | Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2568 | ||
| 2569 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2570 | ||
| 2571 | Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> | |
| 2572 | ||
| 2573 | * gencode.c (SDBBP,DERET): Added (3900) insns. | |
| 2574 | (RFE): Turn on for 3900. | |
| 2575 | * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. | |
| 2576 | (dsstate): Made global. | |
| 2577 | (SUBTARGET_R3900): Added. | |
| 2578 | (CANCELDELAYSLOT): New. | |
| 2579 | (SignalException): Ignore SystemCall rather than ignore and | |
| 2580 | terminate. Add DebugBreakPoint handling. | |
| 2581 | (decode_coproc): New insns RFE, DERET; and new registers Debug | |
| 2582 | and DEPC protected by SUBTARGET_R3900. | |
| 2583 | (sim_engine_run): Use CANCELDELAYSLOT rather than clearing | |
| 2584 | bits explicitly. | |
| 2585 | * Makefile.in,configure.in: Add mips subtarget option. | |
| 2586 | * configure: Update. | |
| 2587 | ||
| 2588 | Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> | |
| 2589 | ||
| 2590 | * gencode.c: Add r3900 (tx39). | |
| 2591 | ||
| 2592 | ||
| 2593 | Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> | |
| 2594 | ||
| 2595 | * gencode.c (build_instruction): Don't need to subtract 4 for | |
| 2596 | JALR, just 2. | |
| 2597 | ||
| 2598 | Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> | |
| 2599 | ||
| 2600 | * interp.c: Correct some HASFPU problems. | |
| 2601 | ||
| 2602 | Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2603 | ||
| 2604 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2605 | ||
| 2606 | Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2607 | ||
| 2608 | * interp.c (mips_options): Fix samples option short form, should | |
| 2609 | be `x'. | |
| 2610 | ||
| 2611 | Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2612 | ||
| 2613 | * interp.c (sim_info): Enable info code. Was just returning. | |
| 2614 | ||
| 2615 | Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2616 | ||
| 2617 | * interp.c (decode_coproc): Clarify warning about unsuported MTC0, | |
| 2618 | MFC0. | |
| 2619 | ||
| 2620 | Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2621 | ||
| 2622 | * gencode.c (build_instruction): Use SIGNED64 for 64 bit | |
| 2623 | constants. | |
| 2624 | (build_instruction): Ditto for LL. | |
| 2625 | ||
| 2626 | Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> | |
| 2627 | ||
| 2628 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2629 | ||
| 2630 | Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2631 | ||
| 2632 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2633 | * config.in: Ditto. | |
| 2634 | ||
| 2635 | Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2636 | ||
| 2637 | * interp.c (sim_open): Add call to sim_analyze_program, update | |
| 2638 | call to sim_config. | |
| 2639 | ||
| 2640 | Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2641 | ||
| 2642 | * interp.c (sim_kill): Delete. | |
| 2643 | (sim_create_inferior): Add ABFD argument. Set PC from same. | |
| 2644 | (sim_load): Move code initializing trap handlers from here. | |
| 2645 | (sim_open): To here. | |
| 2646 | (sim_load): Delete, use sim-hload.c. | |
| 2647 | ||
| 2648 | * Makefile.in (SIM_OBJS): Add sim-hload.o module. | |
| 2649 | ||
| 2650 | Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2651 | ||
| 2652 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2653 | * config.in: Ditto. | |
| 2654 | ||
| 2655 | Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2656 | ||
| 2657 | * interp.c (sim_open): Add ABFD argument. | |
| 2658 | (sim_load): Move call to sim_config from here. | |
| 2659 | (sim_open): To here. Check return status. | |
| 2660 | ||
| 2661 | Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> | |
| 2662 | ||
| 2663 | * gencode.c (build_instruction): Two arg MADD should | |
| 2664 | not assign result to $0. | |
| 2665 | ||
| 2666 | Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) | |
| 2667 | ||
| 2668 | * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) | |
| 2669 | * sim/mips/configure.in: Regenerate. | |
| 2670 | ||
| 2671 | Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> | |
| 2672 | ||
| 2673 | * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit | |
| 2674 | signed8, unsigned8 et.al. types. | |
| 2675 | ||
| 2676 | * interp.c (SUB_REG_FETCH): Handle both little and big endian | |
| 2677 | hosts when selecting subreg. | |
| 2678 | ||
| 2679 | Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) | |
| 2680 | ||
| 2681 | * interp.c (sim_engine_run): Reset the ZERO register to zero | |
| 2682 | regardless of FEATURE_WARN_ZERO. | |
| 2683 | * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. | |
| 2684 | ||
| 2685 | Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2686 | ||
| 2687 | * interp.c (decode_coproc): Implement MTC0 N, CAUSE. | |
| 2688 | (SignalException): For BreakPoints ignore any mode bits and just | |
| 2689 | save the PC. | |
| 2690 | (SignalException): Always set the CAUSE register. | |
| 2691 | ||
| 2692 | Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2693 | ||
| 2694 | * interp.c (SignalException): Clear the simDELAYSLOT flag when an | |
| 2695 | exception has been taken. | |
| 2696 | ||
| 2697 | * interp.c: Implement the ERET and mt/f sr instructions. | |
| 2698 | ||
| 2699 | Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2700 | ||
| 2701 | * interp.c (SignalException): Don't bother restarting an | |
| 2702 | interrupt. | |
| 2703 | ||
| 2704 | Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2705 | ||
| 2706 | * interp.c (SignalException): Really take an interrupt. | |
| 2707 | (interrupt_event): Only deliver interrupts when enabled. | |
| 2708 | ||
| 2709 | Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2710 | ||
| 2711 | * interp.c (sim_info): Only print info when verbose. | |
| 2712 | (sim_info) Use sim_io_printf for output. | |
| 2713 | ||
| 2714 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2715 | ||
| 2716 | * interp.c (CoProcPresent): Add UNUSED attribute - not used by all | |
| 2717 | mips architectures. | |
| 2718 | ||
| 2719 | Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2720 | ||
| 2721 | * interp.c (sim_do_command): Check for common commands if a | |
| 2722 | simulator specific command fails. | |
| 2723 | ||
| 2724 | Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> | |
| 2725 | ||
| 2726 | * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP | |
| 2727 | and simBE when DEBUG is defined. | |
| 2728 | ||
| 2729 | Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2730 | ||
| 2731 | * interp.c (interrupt_event): New function. Pass exception event | |
| 2732 | onto exception handler. | |
| 2733 | ||
| 2734 | * configure.in: Check for stdlib.h. | |
| 2735 | * configure: Regenerate. | |
| 2736 | ||
| 2737 | * gencode.c (build_instruction): Add UNUSED attribute to tempS | |
| 2738 | variable declaration. | |
| 2739 | (build_instruction): Initialize memval1. | |
| 2740 | (build_instruction): Add UNUSED attribute to byte, bigend, | |
| 2741 | reverse. | |
| 2742 | (build_operands): Ditto. | |
| 2743 | ||
| 2744 | * interp.c: Fix GCC warnings. | |
| 2745 | (sim_get_quit_code): Delete. | |
| 2746 | ||
| 2747 | * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. | |
| 2748 | * Makefile.in: Ditto. | |
| 2749 | * configure: Re-generate. | |
| 2750 | ||
| 2751 | * Makefile.in (SIM_OBJS): Add sim-watch.o module. | |
| 2752 | ||
| 2753 | Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2754 | ||
| 2755 | * interp.c (mips_option_handler): New function parse argumes using | |
| 2756 | sim-options. | |
| 2757 | (myname): Replace with STATE_MY_NAME. | |
| 2758 | (sim_open): Delete check for host endianness - performed by | |
| 2759 | sim_config. | |
| 2760 | (simHOSTBE, simBE): Delete, replaced by sim-endian flags. | |
| 2761 | (sim_open): Move much of the initialization from here. | |
| 2762 | (sim_load): To here. After the image has been loaded and | |
| 2763 | endianness set. | |
| 2764 | (sim_open): Move ColdReset from here. | |
| 2765 | (sim_create_inferior): To here. | |
| 2766 | (sim_open): Make FP check less dependant on host endianness. | |
| 2767 | ||
| 2768 | * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or | |
| 2769 | run. | |
| 2770 | * interp.c (sim_set_callbacks): Delete. | |
| 2771 | ||
| 2772 | * interp.c (membank, membank_base, membank_size): Replace with | |
| 2773 | STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. | |
| 2774 | (sim_open): Remove call to callback->init. gdb/run do this. | |
| 2775 | ||
| 2776 | * interp.c: Update | |
| 2777 | ||
| 2778 | * sim-main.h (SIM_HAVE_FLATMEM): Define. | |
| 2779 | ||
| 2780 | * interp.c (big_endian_p): Delete, replaced by | |
| 2781 | current_target_byte_order. | |
| 2782 | ||
| 2783 | Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2784 | ||
| 2785 | * interp.c (host_read_long, host_read_word, host_swap_word, | |
| 2786 | host_swap_long): Delete. Using common sim-endian. | |
| 2787 | (sim_fetch_register, sim_store_register): Use H2T. | |
| 2788 | (pipeline_ticks): Delete. Handled by sim-events. | |
| 2789 | (sim_info): Update. | |
| 2790 | (sim_engine_run): Update. | |
| 2791 | ||
| 2792 | Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2793 | ||
| 2794 | * interp.c (sim_stop_reason): Move code determining simEXCEPTION | |
| 2795 | reason from here. | |
| 2796 | (SignalException): To here. Signal using sim_engine_halt. | |
| 2797 | (sim_stop_reason): Delete, moved to common. | |
| 2798 | ||
| 2799 | Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> | |
| 2800 | ||
| 2801 | * interp.c (sim_open): Add callback argument. | |
| 2802 | (sim_set_callbacks): Delete SIM_DESC argument. | |
| 2803 | (sim_size): Ditto. | |
| 2804 | ||
| 2805 | Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2806 | ||
| 2807 | * Makefile.in (SIM_OBJS): Add common modules. | |
| 2808 | ||
| 2809 | * interp.c (sim_set_callbacks): Also set SD callback. | |
| 2810 | (set_endianness, xfer_*, swap_*): Delete. | |
| 2811 | (host_read_word, host_read_long, host_swap_word, host_swap_long): | |
| 2812 | Change to functions using sim-endian macros. | |
| 2813 | (control_c, sim_stop): Delete, use common version. | |
| 2814 | (simulate): Convert into. | |
| 2815 | (sim_engine_run): This function. | |
| 2816 | (sim_resume): Delete. | |
| 2817 | ||
| 2818 | * interp.c (simulation): New variable - the simulator object. | |
| 2819 | (sim_kind): Delete global - merged into simulation. | |
| 2820 | (sim_load): Cleanup. Move PC assignment from here. | |
| 2821 | (sim_create_inferior): To here. | |
| 2822 | ||
| 2823 | * sim-main.h: New file. | |
| 2824 | * interp.c (sim-main.h): Include. | |
| 2825 | ||
| 2826 | Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2827 | ||
| 2828 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2829 | ||
| 2830 | Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2831 | ||
| 2832 | * tconfig.in (SIM_HAVE_BIENDIAN): Define. | |
| 2833 | ||
| 2834 | Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> | |
| 2835 | ||
| 2836 | * gencode.c (build_instruction): DIV instructions: check | |
| 2837 | for division by zero and integer overflow before using | |
| 2838 | host's division operation. | |
| 2839 | ||
| 2840 | Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2841 | ||
| 2842 | * Makefile.in (SIM_OBJS): Add sim-load.o. | |
| 2843 | * interp.c: #include bfd.h. | |
| 2844 | (target_byte_order): Delete. | |
| 2845 | (sim_kind, myname, big_endian_p): New static locals. | |
| 2846 | (sim_open): Set sim_kind, myname. Move call to set_endianness to | |
| 2847 | after argument parsing. Recognize -E arg, set endianness accordingly. | |
| 2848 | (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to | |
| 2849 | load file into simulator. Set PC from bfd. | |
| 2850 | (sim_create_inferior): Return SIM_RC. Delete arg start_address. | |
| 2851 | (set_endianness): Use big_endian_p instead of target_byte_order. | |
| 2852 | ||
| 2853 | Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> | |
| 2854 | ||
| 2855 | * interp.c (sim_size): Delete prototype - conflicts with | |
| 2856 | definition in remote-sim.h. Correct definition. | |
| 2857 | ||
| 2858 | Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
| 2859 | ||
| 2860 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2861 | * config.in: Ditto. | |
| 2862 | ||
| 2863 | Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2864 | ||
| 2865 | * interp.c (sim_open): New arg `kind'. | |
| 2866 | ||
| 2867 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2868 | ||
| 2869 | Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
| 2870 | ||
| 2871 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2872 | ||
| 2873 | Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2874 | ||
| 2875 | * interp.c (sim_open): Set optind to 0 before calling getopt. | |
| 2876 | ||
| 2877 | Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
| 2878 | ||
| 2879 | * configure: Regenerated to track ../common/aclocal.m4 changes. | |
| 2880 | ||
| 2881 | Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> | |
| 2882 | ||
| 2883 | * interp.c : Replace uses of pr_addr with pr_uword64 | |
| 2884 | where the bit length is always 64 independent of SIM_ADDR. | |
| 2885 | (pr_uword64) : added. | |
| 2886 | ||
| 2887 | Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> | |
| 2888 | ||
| 2889 | * configure: Re-generate. | |
| 2890 | ||
| 2891 | Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> | |
| 2892 | ||
| 2893 | * configure: Regenerate to track ../common/aclocal.m4 changes. | |
| 2894 | ||
| 2895 | Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2896 | ||
| 2897 | * interp.c (sim_open): New SIM_DESC result. Argument is now | |
| 2898 | in argv form. | |
| 2899 | (other sim_*): New SIM_DESC argument. | |
| 2900 | ||
| 2901 | Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> | |
| 2902 | ||
| 2903 | * interp.c: Fix printing of addresses for non-64-bit targets. | |
| 2904 | (pr_addr): Add function to print address based on size. | |
| 2905 | ||
| 2906 | Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> | |
| 2907 | ||
| 2908 | * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. | |
| 2909 | ||
| 2910 | Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> | |
| 2911 | ||
| 2912 | * gencode.c (build_mips16_operands): Correct computation of base | |
| 2913 | address for extended PC relative instruction. | |
| 2914 | ||
| 2915 | Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> | |
| 2916 | ||
| 2917 | * interp.c (mips16_entry): Add support for floating point cases. | |
| 2918 | (SignalException): Pass floating point cases to mips16_entry. | |
| 2919 | (ValueFPR): Don't restrict fmt_single and fmt_word to even | |
| 2920 | registers. | |
| 2921 | (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single | |
| 2922 | or fmt_word. | |
| 2923 | (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, | |
| 2924 | and then set the state to fmt_uninterpreted. | |
| 2925 | (COP_SW): Temporarily set the state to fmt_word while calling | |
| 2926 | ValueFPR. | |
| 2927 | ||
| 2928 | Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> | |
| 2929 | ||
| 2930 | * gencode.c (build_instruction): The high order may be set in the | |
| 2931 | comparison flags at any ISA level, not just ISA 4. | |
| 2932 | ||
| 2933 | Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> | |
| 2934 | ||
| 2935 | * Makefile.in (@COMMON_MAKEFILE_FRAG): Use | |
| 2936 | COMMON_{PRE,POST}_CONFIG_FRAG instead. | |
| 2937 | * configure.in: sinclude ../common/aclocal.m4. | |
| 2938 | * configure: Regenerated. | |
| 2939 | ||
| 2940 | Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> | |
| 2941 | ||
| 2942 | * configure: Rebuild after change to aclocal.m4. | |
| 2943 | ||
| 2944 | Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) | |
| 2945 | ||
| 2946 | * configure configure.in Makefile.in: Update to new configure | |
| 2947 | scheme which is more compatible with WinGDB builds. | |
| 2948 | * configure.in: Improve comment on how to run autoconf. | |
| 2949 | * configure: Re-run autoconf to get new ../common/aclocal.m4. | |
| 2950 | * Makefile.in: Use autoconf substitution to install common | |
| 2951 | makefile fragment. | |
| 2952 | ||
| 2953 | Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> | |
| 2954 | ||
| 2955 | * gencode.c (build_instruction): Use BigEndianCPU instead of | |
| 2956 | ByteSwapMem. | |
| 2957 | ||
| 2958 | Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> | |
| 2959 | ||
| 2960 | * interp.c (sim_monitor): Make output to stdout visible in | |
| 2961 | wingdb's I/O log window. | |
| 2962 | ||
| 2963 | Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> | |
| 2964 | ||
| 2965 | * support.h: Undo previous change to SIGTRAP | |
| 2966 | and SIGQUIT values. | |
| 2967 | ||
| 2968 | Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 2969 | ||
| 2970 | * interp.c (store_word, load_word): New static functions. | |
| 2971 | (mips16_entry): New static function. | |
| 2972 | (SignalException): Look for mips16 entry and exit instructions. | |
| 2973 | (simulate): Use the correct index when setting fpr_state after | |
| 2974 | doing a pending move. | |
| 2975 | ||
| 2976 | Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> | |
| 2977 | ||
| 2978 | * interp.c: Fix byte-swapping code throughout to work on | |
| 2979 | both little- and big-endian hosts. | |
| 2980 | ||
| 2981 | Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> | |
| 2982 | ||
| 2983 | * support.h: Make definitions of SIGTRAP and SIGQUIT consistent | |
| 2984 | with gdb/config/i386/xm-windows.h. | |
| 2985 | ||
| 2986 | Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> | |
| 2987 | ||
| 2988 | * gencode.c (build_instruction): Work around MSVC++ code gen bug | |
| 2989 | that messes up arithmetic shifts. | |
| 2990 | ||
| 2991 | Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) | |
| 2992 | ||
| 2993 | * support.h: Use _WIN32 instead of __WIN32__. Also add defs for | |
| 2994 | SIGTRAP and SIGQUIT for _WIN32. | |
| 2995 | ||
| 2996 | Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 2997 | ||
| 2998 | * gencode.c (build_instruction) [MUL]: Cast operands to word64, to | |
| 2999 | force a 64 bit multiplication. | |
| 3000 | (build_instruction) [OR]: In mips16 mode, don't do anything if the | |
| 3001 | destination register is 0, since that is the default mips16 nop | |
| 3002 | instruction. | |
| 3003 | ||
| 3004 | Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3005 | ||
| 3006 | * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. | |
| 3007 | (build_endian_shift): Don't check proc64. | |
| 3008 | (build_instruction): Always set memval to uword64. Cast op2 to | |
| 3009 | uword64 when shifting it left in memory instructions. Always use | |
| 3010 | the same code for stores--don't special case proc64. | |
| 3011 | ||
| 3012 | * gencode.c (build_mips16_operands): Fix base PC value for PC | |
| 3013 | relative operands. | |
| 3014 | (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a | |
| 3015 | jal instruction. | |
| 3016 | * interp.c (simJALDELAYSLOT): Define. | |
| 3017 | (JALDELAYSLOT): Define. | |
| 3018 | (INDELAYSLOT, INJALDELAYSLOT): Define. | |
| 3019 | (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. | |
| 3020 | ||
| 3021 | Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) | |
| 3022 | ||
| 3023 | * interp.c (sim_open): add flush_cache as a PMON routine | |
| 3024 | (sim_monitor): handle flush_cache by ignoring it | |
| 3025 | ||
| 3026 | Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> | |
| 3027 | ||
| 3028 | * gencode.c (build_instruction): Use !ByteSwapMem instead of | |
| 3029 | BigEndianMem. | |
| 3030 | * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. | |
| 3031 | (BigEndianMem): Rename to ByteSwapMem and change sense. | |
| 3032 | (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change | |
| 3033 | BigEndianMem references to !ByteSwapMem. | |
| 3034 | (set_endianness): New function, with prototype. | |
| 3035 | (sim_open): Call set_endianness. | |
| 3036 | (sim_info): Use simBE instead of BigEndianMem. | |
| 3037 | (xfer_direct_word, xfer_direct_long, swap_direct_word, | |
| 3038 | swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, | |
| 3039 | xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER | |
| 3040 | ifdefs, keeping the prototype declaration. | |
| 3041 | (swap_word): Rewrite correctly. | |
| 3042 | (ColdReset): Delete references to CONFIG. Delete endianness related | |
| 3043 | code; moved to set_endianness. | |
| 3044 | ||
| 3045 | Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> | |
| 3046 | ||
| 3047 | * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. | |
| 3048 | * interp.c (CHECKHILO): Define away. | |
| 3049 | (simSIGINT): New macro. | |
| 3050 | (membank_size): Increase from 1MB to 2MB. | |
| 3051 | (control_c): New function. | |
| 3052 | (sim_resume): Rename parameter signal to signal_number. Add local | |
| 3053 | variable prev. Call signal before and after simulate. | |
| 3054 | (sim_stop_reason): Add simSIGINT support. | |
| 3055 | (sim_warning, sim_error, dotrace, SignalException): Define as stdarg | |
| 3056 | functions always. | |
| 3057 | (sim_warning): Delete call to SignalException. Do call printf_filtered | |
| 3058 | if logfh is NULL. | |
| 3059 | (AddressTranslation): Add #ifdef DEBUG around debugging message and | |
| 3060 | a call to sim_warning. | |
| 3061 | ||
| 3062 | Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3063 | ||
| 3064 | * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD | |
| 3065 | 16 bit instructions. | |
| 3066 | ||
| 3067 | Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3068 | ||
| 3069 | Add support for mips16 (16 bit MIPS implementation): | |
| 3070 | * gencode.c (inst_type): Add mips16 instruction encoding types. | |
| 3071 | (GETDATASIZEINSN): Define. | |
| 3072 | (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add | |
| 3073 | jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and | |
| 3074 | mtlo. | |
| 3075 | (MIPS16_DECODE): New table, for mips16 instructions. | |
| 3076 | (bitmap_val): New static function. | |
| 3077 | (struct mips16_op): Define. | |
| 3078 | (mips16_op_table): New table, for mips16 operands. | |
| 3079 | (build_mips16_operands): New static function. | |
| 3080 | (process_instructions): If PC is odd, decode a mips16 | |
| 3081 | instruction. Break out instruction handling into new | |
| 3082 | build_instruction function. | |
| 3083 | (build_instruction): New static function, broken out of | |
| 3084 | process_instructions. Check modifiers rather than flags for SHIFT | |
| 3085 | bit count and m[ft]{hi,lo} direction. | |
| 3086 | (usage): Pass program name to fprintf. | |
| 3087 | (main): Remove unused variable this_option_optind. Change | |
| 3088 | ``*loptarg++'' to ``loptarg++''. | |
| 3089 | (my_strtoul): Parenthesize && within ||. | |
| 3090 | * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. | |
| 3091 | (simulate): If PC is odd, fetch a 16 bit instruction, and | |
| 3092 | increment PC by 2 rather than 4. | |
| 3093 | * configure.in: Add case for mips16*-*-*. | |
| 3094 | * configure: Rebuild. | |
| 3095 | ||
| 3096 | Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> | |
| 3097 | ||
| 3098 | * interp.c: Allow -t to enable tracing in standalone simulator. | |
| 3099 | Fix garbage output in trace file and error messages. | |
| 3100 | ||
| 3101 | Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> | |
| 3102 | ||
| 3103 | * Makefile.in: Delete stuff moved to ../common/Make-common.in. | |
| 3104 | (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. | |
| 3105 | * configure.in: Simplify using macros in ../common/aclocal.m4. | |
| 3106 | * configure: Regenerated. | |
| 3107 | * tconfig.in: New file. | |
| 3108 | ||
| 3109 | Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> | |
| 3110 | ||
| 3111 | * interp.c: Fix bugs in 64-bit port. | |
| 3112 | Use ansi function declarations for msvc compiler. | |
| 3113 | Initialize and test file pointer in trace code. | |
| 3114 | Prevent duplicate definition of LAST_EMED_REGNUM. | |
| 3115 | ||
| 3116 | Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> | |
| 3117 | ||
| 3118 | * interp.c (xfer_big_long): Prevent unwanted sign extension. | |
| 3119 | ||
| 3120 | Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3121 | ||
| 3122 | * interp.c (SignalException): Check for explicit terminating | |
| 3123 | breakpoint value. | |
| 3124 | * gencode.c: Pass instruction value through SignalException() | |
| 3125 | calls for Trap, Breakpoint and Syscall. | |
| 3126 | ||
| 3127 | Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3128 | ||
| 3129 | * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is | |
| 3130 | only used on those hosts that provide it. | |
| 3131 | * configure.in: Add sqrt() to list of functions to be checked for. | |
| 3132 | * config.in: Re-generated. | |
| 3133 | * configure: Re-generated. | |
| 3134 | ||
| 3135 | Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3136 | ||
| 3137 | * gencode.c (process_instructions): Call build_endian_shift when | |
| 3138 | expanding STORE RIGHT, to fix swr. | |
| 3139 | * support.h (SIGNEXTEND): If the sign bit is not set, explicitly | |
| 3140 | clear the high bits. | |
| 3141 | * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. | |
| 3142 | Fix float to int conversions to produce signed values. | |
| 3143 | ||
| 3144 | Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3145 | ||
| 3146 | * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. | |
| 3147 | (process_instructions): Correct handling of nor instruction. | |
| 3148 | Correct shift count for 32 bit shift instructions. Correct sign | |
| 3149 | extension for arithmetic shifts to not shift the number of bits in | |
| 3150 | the type. Fix 64 bit multiply high word calculation. Fix 32 bit | |
| 3151 | unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. | |
| 3152 | Fix madd. | |
| 3153 | * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. | |
| 3154 | It's OK to have a mult follow a mult. What's not OK is to have a | |
| 3155 | mult follow an mfhi. | |
| 3156 | (Convert): Comment out incorrect rounding code. | |
| 3157 | ||
| 3158 | Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3159 | ||
| 3160 | * interp.c (sim_monitor): Improved monitor printf | |
| 3161 | simulation. Tidied up simulator warnings, and added "--log" option | |
| 3162 | for directing warning message output. | |
| 3163 | * gencode.c: Use sim_warning() rather than WARNING macro. | |
| 3164 | ||
| 3165 | Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3166 | ||
| 3167 | * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and | |
| 3168 | getopt1.o, rather than on gencode.c. Link objects together. | |
| 3169 | Don't link against -liberty. | |
| 3170 | (gencode.o, getopt.o, getopt1.o): New targets. | |
| 3171 | * gencode.c: Include <ctype.h> and "ansidecl.h". | |
| 3172 | (AND): Undefine after including "ansidecl.h". | |
| 3173 | (ULONG_MAX): Define if not defined. | |
| 3174 | (OP_*): Don't define macros; now defined in opcode/mips.h. | |
| 3175 | (main): Call my_strtoul rather than strtoul. | |
| 3176 | (my_strtoul): New static function. | |
| 3177 | ||
| 3178 | Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) | |
| 3179 | ||
| 3180 | * gencode.c (process_instructions): Generate word64 and uword64 | |
| 3181 | instead of `long long' and `unsigned long long' data types. | |
| 3182 | * interp.c: #include sysdep.h to get signals, and define default | |
| 3183 | for SIGBUS. | |
| 3184 | * (Convert): Work around for Visual-C++ compiler bug with type | |
| 3185 | conversion. | |
| 3186 | * support.h: Make things compile under Visual-C++ by using | |
| 3187 | __int64 instead of `long long'. Change many refs to long long | |
| 3188 | into word64/uword64 typedefs. | |
| 3189 | ||
| 3190 | Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) | |
| 3191 | ||
| 3192 | * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, | |
| 3193 | INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. | |
| 3194 | (docdir): Removed. | |
| 3195 | * configure.in (AC_PREREQ): autoconf 2.5 or higher. | |
| 3196 | (AC_PROG_INSTALL): Added. | |
| 3197 | (AC_PROG_CC): Moved to before configure.host call. | |
| 3198 | * configure: Rebuilt. | |
| 3199 | ||
| 3200 | Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3201 | ||
| 3202 | * configure.in: Define @SIMCONF@ depending on mips target. | |
| 3203 | * configure: Rebuild. | |
| 3204 | * Makefile.in (run): Add @SIMCONF@ to control simulator | |
| 3205 | construction. | |
| 3206 | * gencode.c: Change LOADDRMASK to 64bit memory model only. | |
| 3207 | * interp.c: Remove some debugging, provide more detailed error | |
| 3208 | messages, update memory accesses to use LOADDRMASK. | |
| 3209 | ||
| 3210 | Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3211 | ||
| 3212 | * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, | |
| 3213 | AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set | |
| 3214 | stamp-h. | |
| 3215 | * configure: Rebuild. | |
| 3216 | * config.in: New file, generated by autoheader. | |
| 3217 | * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, | |
| 3218 | and <strings.h> if they exist. Replace #ifdef sun with #ifdef | |
| 3219 | HAVE_ANINT and HAVE_AINT, as appropriate. | |
| 3220 | * Makefile.in (run): Use @LIBS@ rather than -lm. | |
| 3221 | (interp.o): Depend upon config.h. | |
| 3222 | (Makefile): Just rebuild Makefile. | |
| 3223 | (clean): Remove stamp-h. | |
| 3224 | (mostlyclean): Make the same as clean, not as distclean. | |
| 3225 | (config.h, stamp-h): New targets. | |
| 3226 | ||
| 3227 | Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3228 | ||
| 3229 | * interp.c (ColdReset): Fix boolean test. Make all simulator | |
| 3230 | globals static. | |
| 3231 | ||
| 3232 | Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3233 | ||
| 3234 | * interp.c (xfer_direct_word, xfer_direct_long, | |
| 3235 | swap_direct_word, swap_direct_long, xfer_big_word, | |
| 3236 | xfer_big_long, xfer_little_word, xfer_little_long, | |
| 3237 | swap_word,swap_long): Added. | |
| 3238 | * interp.c (ColdReset): Provide function indirection to | |
| 3239 | host<->simulated_target transfer routines. | |
| 3240 | * interp.c (sim_store_register, sim_fetch_register): Updated to | |
| 3241 | make use of indirected transfer routines. | |
| 3242 | ||
| 3243 | Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3244 | ||
| 3245 | * gencode.c (process_instructions): Ensure FP ABS instruction | |
| 3246 | recognised. | |
| 3247 | * interp.c (AbsoluteValue): Add routine. Also provide simple PMON | |
| 3248 | system call support. | |
| 3249 | ||
| 3250 | Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3251 | ||
| 3252 | * interp.c (sim_do_command): Complain if callback structure not | |
| 3253 | initialised. | |
| 3254 | ||
| 3255 | Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3256 | ||
| 3257 | * interp.c (Convert): Provide round-to-nearest and round-to-zero | |
| 3258 | support for Sun hosts. | |
| 3259 | * Makefile.in (gencode): Ensure the host compiler and libraries | |
| 3260 | used for cross-hosted build. | |
| 3261 | ||
| 3262 | Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3263 | ||
| 3264 | * interp.c, gencode.c: Some more (TODO) tidying. | |
| 3265 | ||
| 3266 | Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> | |
| 3267 | ||
| 3268 | * gencode.c, interp.c: Replaced explicit long long references with | |
| 3269 | WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. | |
| 3270 | * support.h (SET64LO, SET64HI): Macros added. | |
| 3271 | ||
| 3272 | Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> | |
| 3273 | ||
| 3274 | * configure: Regenerate with autoconf 2.7. | |
| 3275 | ||
| 3276 | Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> | |
| 3277 | ||
| 3278 | * interp.c (LoadMemory): Enclose text following #endif in /* */. | |
| 3279 | * support.h: Remove superfluous "1" from #if. | |
| 3280 | * support.h (CHECKSIM): Remove stray 'a' at end of line. | |
| 3281 | ||
| 3282 | Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> | |
| 3283 | ||
| 3284 | * interp.c (StoreFPR): Control UndefinedResult() call on | |
| 3285 | WARN_RESULT manifest. | |
| 3286 | ||
| 3287 | Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> | |
| 3288 | ||
| 3289 | * gencode.c: Tidied instruction decoding, and added FP instruction | |
| 3290 | support. | |
| 3291 | ||
| 3292 | * interp.c: Added dineroIII, and BSD profiling support. Also | |
| 3293 | run-time FP handling. | |
| 3294 | ||
| 3295 | Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> | |
| 3296 | ||
| 3297 | * Changelog, Makefile.in, README.Cygnus, configure, configure.in, | |
| 3298 | gencode.c, interp.c, support.h: created. |