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b7026657
AC		 12005-01-07 Andrew Cagney <cagney@gnu.org>
2
3 * configure.ac: Rename configure.in, require autoconf 2.59.
4 * configure: Re-generate.
5
379832de
HPN		 62004-12-08 Hans-Peter Nilsson <hp@axis.com>
7
8 * configure: Regenerate for ../common/aclocal.m4 update.
9
cd62154c
AC		 102004-09-24 Monika Chaddha <monika@acmet.com>
11
12 Committed by Andrew Cagney.
13 * m16.igen (CMP, CMPI): Fix assembler.
14
e5da76ec
CD		 152004-08-18 Chris Demetriou <cgd@broadcom.com>
16
17 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
18 * configure: Regenerate.
19
139181c8
CD		 202004-06-25 Chris Demetriou <cgd@broadcom.com>
21
22 * configure.in (sim_m16_machine): Include mipsIII.
23 * configure: Regenerate.
24
1a27f959
CD		 252004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
26
27 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
28 from COP0_BADVADDR.
29 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
30
5dbb7b5a
CD		 312004-04-10 Chris Demetriou <cgd@broadcom.com>
32
33 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
34
14234056
CD		 352004-04-09 Chris Demetriou <cgd@broadcom.com>
36
37 * mips.igen (check_fmt): Remove.
38 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
39 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
40 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
41 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
42 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
43 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
44 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
45 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
46 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
47 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
48
c6f9085c
CD		 492004-04-09 Chris Demetriou <cgd@broadcom.com>
50
51 * sb1.igen (check_sbx): New function.
52 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
53
11d66e66 542004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 55 Richard Sandiford <rsandifo@redhat.com>
56
57 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
58 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
59 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
60 separate implementations for mipsIV and mipsV. Use new macros to
61 determine whether the restrictions apply.
62
b3208fb8
CD		 632004-01-19 Chris Demetriou <cgd@broadcom.com>
64
65 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
66 (check_mult_hilo): Improve comments.
67 (check_div_hilo): Likewise. Also, fork off a new version
68 to handle mips32/mips64 (since there are no hazards to check
69 in MIPS32/MIPS64).
70
9a1d84fb
CD		 712003-06-17 Richard Sandiford <rsandifo@redhat.com>
72
73 * mips.igen (do_dmultx): Fix check for negative operands.
74
ae451ac6
ILT		 752003-05-16 Ian Lance Taylor <ian@airs.com>
76
77 * Makefile.in (SHELL): Make sure this is defined.
78 (various): Use $(SHELL) whenever we invoke move-if-change.
79
dd69d292
CD		 802003-05-03 Chris Demetriou <cgd@broadcom.com>
81
82 * cp1.c: Tweak attribution slightly.
83 * cp1.h: Likewise.
84 * mdmx.c: Likewise.
85 * mdmx.igen: Likewise.
86 * mips3d.igen: Likewise.
87 * sb1.igen: Likewise.
88
bcd0068e
CD		 892003-04-15 Richard Sandiford <rsandifo@redhat.com>
90
91 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
92 unsigned operands.
93
6b4a8935
AC		 942003-02-27 Andrew Cagney <cagney@redhat.com>
95
601da316
AC		 96 * interp.c (sim_open): Rename _bfd to bfd.
97 (sim_create_inferior): Ditto.
6b4a8935 98
d29e330f
CD		 992003-01-14 Chris Demetriou <cgd@broadcom.com>
100
101 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
102
a2353a08
CD		 1032003-01-14 Chris Demetriou <cgd@broadcom.com>
104
105 * mips.igen (EI, DI): Remove.
106
80551777
CD		 1072003-01-05 Richard Sandiford <rsandifo@redhat.com>
108
109 * Makefile.in (tmp-run-multi): Fix mips16 filter.
110
4c54fc26
CD		 1112003-01-04 Richard Sandiford <rsandifo@redhat.com>
112 Andrew Cagney <ac131313@redhat.com>
113 Gavin Romig-Koch <gavin@redhat.com>
114 Graydon Hoare <graydon@redhat.com>
115 Aldy Hernandez <aldyh@redhat.com>
116 Dave Brolley <brolley@redhat.com>
117 Chris Demetriou <cgd@broadcom.com>
118
119 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
120 (sim_mach_default): New variable.
121 (mips64vr-*-*, mips64vrel-*-*): New configurations.
122 Add a new simulator generator, MULTI.
123 * configure: Regenerate.
124 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
125 (multi-run.o): New dependency.
126 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
127 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
128 (tmp-multi): Combine them.
129 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
130 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
131 (distclean-extra): New rule.
132 * sim-main.h: Include bfd.h.
133 (MIPS_MACH): New macro.
134 * mips.igen (vr4120, vr5400, vr5500): New models.
135 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
136 * vr.igen: Replace with new version.
137
e6c674b8
CD		 1382003-01-04 Chris Demetriou <cgd@broadcom.com>
139
140 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
141 * configure: Regenerate.
142
28f50ac8
CD		 1432002-12-31 Chris Demetriou <cgd@broadcom.com>
144
145 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
146 * mips.igen: Remove all invocations of check_branch_bug and
147 mark_branch_bug.
148
5071ffe6
CD		 1492002-12-16 Chris Demetriou <cgd@broadcom.com>
150
151 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
152
06e7837e
CD		 1532002-07-30 Chris Demetriou <cgd@broadcom.com>
154
155 * mips.igen (do_load_double, do_store_double): New functions.
156 (LDC1, SDC1): Rename to...
157 (LDC1b, SDC1b): respectively.
158 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
159
2265c243
MS		 1602002-07-29 Michael Snyder <msnyder@redhat.com>
161
162 * cp1.c (fp_recip2): Modify initialization expression so that
163 GCC will recognize it as constant.
164
a2f8b4f3
CD		 1652002-06-18 Chris Demetriou <cgd@broadcom.com>
166
167 * mdmx.c (SD_): Delete.
168 (Unpredictable): Re-define, for now, to directly invoke
169 unpredictable_action().
170 (mdmx_acc_op): Fix error in .ob immediate handling.
171
b4b6c939
AC		 1722002-06-18 Andrew Cagney <cagney@redhat.com>
173
174 * interp.c (sim_firmware_command): Initialize `address'.
175
c8cca39f
AC		 1762002-06-16 Andrew Cagney <ac131313@redhat.com>
177
178 * configure: Regenerated to track ../common/aclocal.m4 changes.
179
e7e81181
CD		 1802002-06-14 Chris Demetriou <cgd@broadcom.com>
181 Ed Satterthwaite <ehs@broadcom.com>
182
183 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
184 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
185 * mips.igen: Include mips3d.igen.
186 (mips3d): New model name for MIPS-3D ASE instructions.
187 (CVT.W.fmt): Don't use this instruction for word (source) format
188 instructions.
189 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
190 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
191 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
192 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
193 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
194 (RSquareRoot1, RSquareRoot2): New macros.
195 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
196 (fp_rsqrt2): New functions.
197 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
198 * configure: Regenerate.
199
3a2b820e 2002002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 201 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 202
203 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
204 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
205 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
206 (convert): Note that this function is not used for paired-single
207 format conversions.
208 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
209 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
210 (check_fmt_p): Enable paired-single support.
211 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
212 (PUU.PS): New instructions.
213 (CVT.S.fmt): Don't use this instruction for paired-single format
214 destinations.
215 * sim-main.h (FP_formats): New value 'fmt_ps.'
216 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
217 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
218
d18ea9c2
CD		 2192002-06-12 Chris Demetriou <cgd@broadcom.com>
220
221 * mips.igen: Fix formatting of function calls in
222 many FP operations.
223
95fd5cee
CD		 2242002-06-12 Chris Demetriou <cgd@broadcom.com>
225
226 * mips.igen (MOVN, MOVZ): Trace result.
227 (TNEI): Print "tnei" as the opcode name in traces.
228 (CEIL.W): Add disassembly string for traces.
229 (RSQRT.fmt): Make location of disassembly string consistent
230 with other instructions.
231
4f0d55ae
CD		 2322002-06-12 Chris Demetriou <cgd@broadcom.com>
233
234 * mips.igen (X): Delete unused function.
235
3c25f8c7
AC		 2362002-06-08 Andrew Cagney <cagney@redhat.com>
237
238 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
239
f3c08b7e
CD		 2402002-06-07 Chris Demetriou <cgd@broadcom.com>
241 Ed Satterthwaite <ehs@broadcom.com>
242
243 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
244 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
245 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
246 (fp_nmsub): New prototypes.
247 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
248 (NegMultiplySub): New defines.
249 * mips.igen (RSQRT.fmt): Use RSquareRoot().
250 (MADD.D, MADD.S): Replace with...
251 (MADD.fmt): New instruction.
252 (MSUB.D, MSUB.S): Replace with...
253 (MSUB.fmt): New instruction.
254 (NMADD.D, NMADD.S): Replace with...
255 (NMADD.fmt): New instruction.
256 (NMSUB.D, MSUB.S): Replace with...
257 (NMSUB.fmt): New instruction.
258
52714ff9
CD		 2592002-06-07 Chris Demetriou <cgd@broadcom.com>
260 Ed Satterthwaite <ehs@broadcom.com>
261
262 * cp1.c: Fix more comment spelling and formatting.
263 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
264 (denorm_mode): New function.
265 (fpu_unary, fpu_binary): Round results after operation, collect
266 status from rounding operations, and update the FCSR.
267 (convert): Collect status from integer conversions and rounding
268 operations, and update the FCSR. Adjust NaN values that result
269 from conversions. Convert to use sim_io_eprintf rather than
270 fprintf, and remove some debugging code.
271 * cp1.h (fenr_FS): New define.
272
577d8c4b
CD		 2732002-06-07 Chris Demetriou <cgd@broadcom.com>
274
275 * cp1.c (convert): Remove unusable debugging code, and move MIPS
276 rounding mode to sim FP rounding mode flag conversion code into...
277 (rounding_mode): New function.
278
196496ed
CD		 2792002-06-07 Chris Demetriou <cgd@broadcom.com>
280
281 * cp1.c: Clean up formatting of a few comments.
282 (value_fpr): Reformat switch statement.
283
cfe9ea23
CD		 2842002-06-06 Chris Demetriou <cgd@broadcom.com>
285 Ed Satterthwaite <ehs@broadcom.com>
286
287 * cp1.h: New file.
288 * sim-main.h: Include cp1.h.
289 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
290 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
291 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
292 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
293 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
294 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
295 * cp1.c: Don't include sim-fpu.h; already included by
296 sim-main.h. Clean up formatting of some comments.
297 (NaN, Equal, Less): Remove.
298 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
299 (fp_cmp): New functions.
300 * mips.igen (do_c_cond_fmt): Remove.
301 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
302 Compare. Add result tracing.
303 (CxC1): Remove, replace with...
304 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
305 (DMxC1): Remove, replace with...
306 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
307 (MxC1): Remove, replace with...
308 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
309
ee7254b0
CD		 3102002-06-04 Chris Demetriou <cgd@broadcom.com>
311
312 * sim-main.h (FGRIDX): Remove, replace all uses with...
313 (FGR_BASE): New macro.
314 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
315 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
316 (NR_FGR, FGR): Likewise.
317 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
318 * mips.igen: Likewise.
319
d3eb724f
CD		 3202002-06-04 Chris Demetriou <cgd@broadcom.com>
321
322 * cp1.c: Add an FSF Copyright notice to this file.
323
ba46ddd0
CD		 3242002-06-04 Chris Demetriou <cgd@broadcom.com>
325 Ed Satterthwaite <ehs@broadcom.com>
326
327 * cp1.c (Infinity): Remove.
328 * sim-main.h (Infinity): Likewise.
329
330 * cp1.c (fp_unary, fp_binary): New functions.
331 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
332 (fp_sqrt): New functions, implemented in terms of the above.
333 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
334 (Recip, SquareRoot): Remove (replaced by functions above).
335 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
336 (fp_recip, fp_sqrt): New prototypes.
337 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
338 (Recip, SquareRoot): Replace prototypes with #defines which
339 invoke the functions above.
340
18d8a52d
CD		 3412002-06-03 Chris Demetriou <cgd@broadcom.com>
342
343 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
344 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
345 file, remove PARAMS from prototypes.
346 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
347 simulator state arguments.
348 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
349 pass simulator state arguments.
350 * cp1.c (SD): Redefine as CPU_STATE(cpu).
351 (store_fpr, convert): Remove 'sd' argument.
352 (value_fpr): Likewise. Convert to use 'SD' instead.
353
0f154cbd
CD		 3542002-06-03 Chris Demetriou <cgd@broadcom.com>
355
356 * cp1.c (Min, Max): Remove #if 0'd functions.
357 * sim-main.h (Min, Max): Remove.
358
e80fc152
CD		 3592002-06-03 Chris Demetriou <cgd@broadcom.com>
360
361 * cp1.c: fix formatting of switch case and default labels.
362 * interp.c: Likewise.
363 * sim-main.c: Likewise.
364
bad673a9
CD		 3652002-06-03 Chris Demetriou <cgd@broadcom.com>
366
367 * cp1.c: Clean up comments which describe FP formats.
368 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
369
7cbea089
CD		 3702002-06-03 Chris Demetriou <cgd@broadcom.com>
371 Ed Satterthwaite <ehs@broadcom.com>
372
373 * configure.in (mipsisa64sb1*-*-*): New target for supporting
374 Broadcom SiByte SB-1 processor configurations.
375 * configure: Regenerate.
376 * sb1.igen: New file.
377 * mips.igen: Include sb1.igen.
378 (sb1): New model.
379 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
380 * mdmx.igen: Add "sb1" model to all appropriate functions and
381 instructions.
382 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
383 (ob_func, ob_acc): Reference the above.
384 (qh_acc): Adjust to keep the same size as ob_acc.
385 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
386 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
387
909daa82
CD		 3882002-06-03 Chris Demetriou <cgd@broadcom.com>
389
390 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
391
f4f1b9f1
CD		 3922002-06-02 Chris Demetriou <cgd@broadcom.com>
393 Ed Satterthwaite <ehs@broadcom.com>
394
395 * mips.igen (mdmx): New (pseudo-)model.
396 * mdmx.c, mdmx.igen: New files.
397 * Makefile.in (SIM_OBJS): Add mdmx.o.
398 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
399 New typedefs.
400 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
401 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
402 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
403 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
404 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
405 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
406 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
407 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
408 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
409 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
410 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
411 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
412 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
413 (qh_fmtsel): New macros.
414 (_sim_cpu): New member "acc".
415 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
416 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
417
5accf1ff
CD		 4182002-05-01 Chris Demetriou <cgd@broadcom.com>
419
420 * interp.c: Use 'deprecated' rather than 'depreciated.'
421 * sim-main.h: Likewise.
422
402586aa
CD		 4232002-05-01 Chris Demetriou <cgd@broadcom.com>
424
425 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
426 which wouldn't compile anyway.
427 * sim-main.h (unpredictable_action): New function prototype.
428 (Unpredictable): Define to call igen function unpredictable().
429 (NotWordValue): New macro to call igen function not_word_value().
430 (UndefinedResult): Remove.
431 * interp.c (undefined_result): Remove.
432 (unpredictable_action): New function.
433 * mips.igen (not_word_value, unpredictable): New functions.
434 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
435 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
436 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
437 NotWordValue() to check for unpredictable inputs, then
438 Unpredictable() to handle them.
439
c9b9995a
CD		 4402002-02-24 Chris Demetriou <cgd@broadcom.com>
441
442 * mips.igen: Fix formatting of calls to Unpredictable().
443
e1015982
AC		 4442002-04-20 Andrew Cagney <ac131313@redhat.com>
445
446 * interp.c (sim_open): Revert previous change.
447
b882a66b
AO		 4482002-04-18 Alexandre Oliva <aoliva@redhat.com>
449
450 * interp.c (sim_open): Disable chunk of code that wrote code in
451 vector table entries.
452
c429b7dd
CD		 4532002-03-19 Chris Demetriou <cgd@broadcom.com>
454
455 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
456 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
457 unused definitions.
458
37d146fa
CD		 4592002-03-19 Chris Demetriou <cgd@broadcom.com>
460
461 * cp1.c: Fix many formatting issues.
462
07892c0b
CD		 4632002-03-19 Chris G. Demetriou <cgd@broadcom.com>
464
465 * cp1.c (fpu_format_name): New function to replace...
466 (DOFMT): This. Delete, and update all callers.
467 (fpu_rounding_mode_name): New function to replace...
468 (RMMODE): This. Delete, and update all callers.
469
487f79b7
CD		 4702002-03-19 Chris G. Demetriou <cgd@broadcom.com>
471
472 * interp.c: Move FPU support routines from here to...
473 * cp1.c: Here. New file.
474 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
475 (cp1.o): New target.
476
1e799e28
CD		 4772002-03-12 Chris Demetriou <cgd@broadcom.com>
478
479 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
480 * mips.igen (mips32, mips64): New models, add to all instructions
481 and functions as appropriate.
482 (loadstore_ea, check_u64): New variant for model mips64.
483 (check_fmt_p): New variant for models mipsV and mips64, remove
484 mipsV model marking fro other variant.
485 (SLL) Rename to...
486 (SLLa) this.
487 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
488 for mips32 and mips64.
489 (DCLO, DCLZ): New instructions for mips64.
490
82f728db
CD		 4912002-03-07 Chris Demetriou <cgd@broadcom.com>
492
493 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
494 immediate or code as a hex value with the "%#lx" format.
495 (ANDI): Likewise, and fix printed instruction name.
496
b96e7ef1
CD		 4972002-03-05 Chris Demetriou <cgd@broadcom.com>
498
499 * sim-main.h (UndefinedResult, Unpredictable): New macros
500 which currently do nothing.
501
d35d4f70
CD		 5022002-03-05 Chris Demetriou <cgd@broadcom.com>
503
504 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
505 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
506 (status_CU3): New definitions.
507
508 * sim-main.h (ExceptionCause): Add new values for MIPS32
509 and MIPS64: MDMX, MCheck, CacheErr. Update comments
510 for DebugBreakPoint and NMIReset to note their status in
511 MIPS32 and MIPS64.
512 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
513 (SignalExceptionCacheErr): New exception macros.
514
3ad6f714
CD		 5152002-03-05 Chris Demetriou <cgd@broadcom.com>
516
517 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
518 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
519 is always enabled.
520 (SignalExceptionCoProcessorUnusable): Take as argument the
521 unusable coprocessor number.
522
86b77b47
CD		 5232002-03-05 Chris Demetriou <cgd@broadcom.com>
524
525 * mips.igen: Fix formatting of all SignalException calls.
526
97a88e93 5272002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 528
529 * sim-main.h (SIGNEXTEND): Remove.
530
97a88e93 5312002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 532
533 * mips.igen: Remove gencode comment from top of file, fix
534 spelling in another comment.
535
97a88e93 5362002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 537
538 * mips.igen (check_fmt, check_fmt_p): New functions to check
539 whether specific floating point formats are usable.
540 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
541 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
542 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
543 Use the new functions.
544 (do_c_cond_fmt): Remove format checks...
545 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
546
97a88e93 5472002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 548
549 * mips.igen: Fix formatting of check_fpu calls.
550
41774c9d
CD		 5512002-03-03 Chris Demetriou <cgd@broadcom.com>
552
553 * mips.igen (FLOOR.L.fmt): Store correct destination register.
554
4a0bd876
CD		 5552002-03-03 Chris Demetriou <cgd@broadcom.com>
556
557 * mips.igen: Remove whitespace at end of lines.
558
09297648
CD		 5592002-03-02 Chris Demetriou <cgd@broadcom.com>
560
561 * mips.igen (loadstore_ea): New function to do effective
562 address calculations.
563 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
564 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
565 CACHE): Use loadstore_ea to do effective address computations.
566
043b7057
CD		 5672002-03-02 Chris Demetriou <cgd@broadcom.com>
568
569 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
570 * mips.igen (LL, CxC1, MxC1): Likewise.
571
c1e8ada4
CD		 5722002-03-02 Chris Demetriou <cgd@broadcom.com>
573
574 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
575 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
576 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
577 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
578 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
579 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
580 Don't split opcode fields by hand, use the opcode field values
581 provided by igen.
582
3e1dca16
CD		 5832002-03-01 Chris Demetriou <cgd@broadcom.com>
584
585 * mips.igen (do_divu): Fix spacing.
586
587 * mips.igen (do_dsllv): Move to be right before DSLLV,
588 to match the rest of the do_<shift> functions.
589
fff8d27d
CD		 5902002-03-01 Chris Demetriou <cgd@broadcom.com>
591
592 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
593 DSRL32, do_dsrlv): Trace inputs and results.
594
0d3e762b
CD		 5952002-03-01 Chris Demetriou <cgd@broadcom.com>
596
597 * mips.igen (CACHE): Provide instruction-printing string.
598
599 * interp.c (signal_exception): Comment tokens after #endif.
600
eb5fcf93
CD		 6012002-02-28 Chris Demetriou <cgd@broadcom.com>
602
603 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
604 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
605 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
606 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
607 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
608 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
609 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
610 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
611
bb22bd7d
CD		 6122002-02-28 Chris Demetriou <cgd@broadcom.com>
613
614 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
615 instruction-printing string.
616 (LWU): Use '64' as the filter flag.
617
91a177cf
CD		 6182002-02-28 Chris Demetriou <cgd@broadcom.com>
619
620 * mips.igen (SDXC1): Fix instruction-printing string.
621
387f484a
CD		 6222002-02-28 Chris Demetriou <cgd@broadcom.com>
623
624 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
625 filter flags "32,f".
626
3d81f391
CD		 6272002-02-27 Chris Demetriou <cgd@broadcom.com>
628
629 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
630 as the filter flag.
631
af5107af
CD		 6322002-02-27 Chris Demetriou <cgd@broadcom.com>
633
634 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
635 add a comma) so that it more closely match the MIPS ISA
636 documentation opcode partitioning.
637 (PREF): Put useful names on opcode fields, and include
638 instruction-printing string.
639
ca971540
CD		 6402002-02-27 Chris Demetriou <cgd@broadcom.com>
641
642 * mips.igen (check_u64): New function which in the future will
643 check whether 64-bit instructions are usable and signal an
644 exception if not. Currently a no-op.
645 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
646 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
647 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
648 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
649
650 * mips.igen (check_fpu): New function which in the future will
651 check whether FPU instructions are usable and signal an exception
652 if not. Currently a no-op.
653 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
654 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
655 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
656 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
657 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
658 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
659 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
660 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
661
1c47a468
CD		 6622002-02-27 Chris Demetriou <cgd@broadcom.com>
663
664 * mips.igen (do_load_left, do_load_right): Move to be immediately
665 following do_load.
666 (do_store_left, do_store_right): Move to be immediately following
667 do_store.
668
603a98e7
CD		 6692002-02-27 Chris Demetriou <cgd@broadcom.com>
670
671 * mips.igen (mipsV): New model name. Also, add it to
672 all instructions and functions where it is appropriate.
673
c5d00cc7
CD		 6742002-02-18 Chris Demetriou <cgd@broadcom.com>
675
676 * mips.igen: For all functions and instructions, list model
677 names that support that instruction one per line.
678
074e9cb8
CD		 6792002-02-11 Chris Demetriou <cgd@broadcom.com>
680
681 * mips.igen: Add some additional comments about supported
682 models, and about which instructions go where.
683 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
684 order as is used in the rest of the file.
685
9805e229
CD		 6862002-02-11 Chris Demetriou <cgd@broadcom.com>
687
688 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
689 indicating that ALU32_END or ALU64_END are there to check
690 for overflow.
691 (DADD): Likewise, but also remove previous comment about
692 overflow checking.
693
f701dad2
CD		 6942002-02-10 Chris Demetriou <cgd@broadcom.com>
695
696 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
697 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
698 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
699 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
700 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
701 fields (i.e., add and move commas) so that they more closely
702 match the MIPS ISA documentation opcode partitioning.
703
7042002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 705
706 * mips.igen (ADDI): Print immediate value.
707 (BREAK): Print code.
708 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
709 (SLL): Print "nop" specially, and don't run the code
710 that does the shift for the "nop" case.
711
9e52972e
FF		 7122001-11-17 Fred Fish <fnf@redhat.com>
713
714 * sim-main.h (float_operation): Move enum declaration outside
715 of _sim_cpu struct declaration.
716
c0efbca4
JB		 7172001-04-12 Jim Blandy <jimb@redhat.com>
718
719 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
720 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
721 set of the FCSR.
722 * sim-main.h (COCIDX): Remove definition; this isn't supported by
723 PENDING_FILL, and you can get the intended effect gracefully by
724 calling PENDING_SCHED directly.
725
fb891446
BE		 7262001-02-23 Ben Elliston <bje@redhat.com>
727
728 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
729 already defined elsewhere.
730
8030f857
BE		 7312001-02-19 Ben Elliston <bje@redhat.com>
732
733 * sim-main.h (sim_monitor): Return an int.
734 * interp.c (sim_monitor): Add return values.
735 (signal_exception): Handle error conditions from sim_monitor.
736
56b48a7a
CD		 7372001-02-08 Ben Elliston <bje@redhat.com>
738
739 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
740 (store_memory): Likewise, pass cia to sim_core_write*.
741
d3ee60d9
FCE		 7422000-10-19 Frank Ch. Eigler <fche@redhat.com>
743
744 On advice from Chris G. Demetriou <cgd@sibyte.com>:
745 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
746
071da002
AC		 747Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
748
749 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
750 * Makefile.in: Don't delete *.igen when cleaning directory.
751
a28c02cd
AC		 752Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
753
754 * m16.igen (break): Call SignalException not sim_engine_halt.
755
80ee11fa
AC		 756Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
757
758 From Jason Eckhardt:
759 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
760
673388c0
AC		 761Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
762
763 * mips.igen (MxC1, DMxC1): Fix printf formatting.
764
4c0deff4
NC		 7652000-05-24 Michael Hayes <mhayes@cygnus.com>
766
767 * mips.igen (do_dmultx): Fix typo.
768
eb2d80b4
AC		 769Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
770
771 * configure: Regenerated to track ../common/aclocal.m4 changes.
772
dd37a34b
AC		 773Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
774
775 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
776
4c0deff4
NC		 7772000-04-12 Frank Ch. Eigler <fche@redhat.com>
778
779 * sim-main.h (GPR_CLEAR): Define macro.
780
e30db738
AC		 781Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
782
783 * interp.c (decode_coproc): Output long using %lx and not %s.
784
cb7450ea
FCE		 7852000-03-21 Frank Ch. Eigler <fche@redhat.com>
786
787 * interp.c (sim_open): Sort & extend dummy memory regions for
788 --board=jmr3904 for eCos.
789
a3027dd7
FCE		 7902000-03-02 Frank Ch. Eigler <fche@redhat.com>
791
792 * configure: Regenerated.
793
794Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
795
796 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
797 calls, conditional on the simulator being in verbose mode.
798
dfcd3bfb
JM		 799Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
800
801 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
802 cache don't get ReservedInstruction traps.
803
c2d11a7d
JM		 8041999-11-29 Mark Salter <msalter@cygnus.com>
805
806 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
807 to clear status bits in sdisr register. This is how the hardware works.
808
809 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
810 being used by cygmon.
811
4ce44c66
JM		 8121999-11-11 Andrew Haley <aph@cygnus.com>
813
814 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
815 instructions.
816
cff3e48b
JM		 817Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
818
819 * mips.igen (MULT): Correct previous mis-applied patch.
820
d4f3574e
SS		 821Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
822
823 * mips.igen (delayslot32): Handle sequence like
824 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
825 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
826 (MULT): Actually pass the third register...
827
8281999-09-03 Mark Salter <msalter@cygnus.com>
829
830 * interp.c (sim_open): Added more memory aliases for additional
831 hardware being touched by cygmon on jmr3904 board.
832
833Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
834
835 * configure: Regenerated to track ../common/aclocal.m4 changes.
836
a0b3c4fd
JM		 837Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
838
839 * interp.c (sim_store_register): Handle case where client - GDB -
840 specifies that a 4 byte register is 8 bytes in size.
841 (sim_fetch_register): Ditto.
842
adf40b2e
JM		 8431999-07-14 Frank Ch. Eigler <fche@cygnus.com>
844
845 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
846 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
847 (idt_monitor_base): Base address for IDT monitor traps.
848 (pmon_monitor_base): Ditto for PMON.
849 (lsipmon_monitor_base): Ditto for LSI PMON.
850 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
851 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
852 (sim_firmware_command): New function.
853 (mips_option_handler): Call it for OPTION_FIRMWARE.
854 (sim_open): Allocate memory for idt_monitor region. If "--board"
855 option was given, add no monitor by default. Add BREAK hooks only if
856 monitors are also there.
857
43e526b9
JM		 858Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
859
860 * interp.c (sim_monitor): Flush output before reading input.
861
862Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
863
864 * tconfig.in (SIM_HANDLES_LMA): Always define.
865
866Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
867
868 From Mark Salter <msalter@cygnus.com>:
869 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
870 (sim_open): Add setup for BSP board.
871
9846de1b
JM		 872Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
873
874 * mips.igen (MULT, MULTU): Add syntax for two operand version.
875 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
876 them as unimplemented.
877
cd0fc7c3
SS		 8781999-05-08 Felix Lee <flee@cygnus.com>
879
880 * configure: Regenerated to track ../common/aclocal.m4 changes.
881
7a292a7a
SS		 8821999-04-21 Frank Ch. Eigler <fche@cygnus.com>
883
884 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
885
886Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
887
888 * configure.in: Any mips64vr5*-*-* target should have
889 -DTARGET_ENABLE_FR=1.
890 (default_endian): Any mips64vr*el-*-* target should default to
891 LITTLE_ENDIAN.
892 * configure: Re-generate.
893
8941999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
895
896 * mips.igen (ldl): Extend from _16_, not 32.
897
898Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
899
900 * interp.c (sim_store_register): Force registers written to by GDB
901 into an un-interpreted state.
902
c906108c
SS		 9031999-02-05 Frank Ch. Eigler <fche@cygnus.com>
904
905 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
906 CPU, start periodic background I/O polls.
907 (tx3904sio_poll): New function: periodic I/O poller.
908
9091998-12-30 Frank Ch. Eigler <fche@cygnus.com>
910
911 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
912
913Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
914
915 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
916 case statement.
917
9181998-12-29 Frank Ch. Eigler <fche@cygnus.com>
919
920 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
921 (load_word): Call SIM_CORE_SIGNAL hook on error.
922 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
923 starting. For exception dispatching, pass PC instead of NULL_CIA.
924 (decode_coproc): Use COP0_BADVADDR to store faulting address.
925 * sim-main.h (COP0_BADVADDR): Define.
926 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
927 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
928 (_sim_cpu): Add exc_* fields to store register value snapshots.
929 * mips.igen (*): Replace memory-related SignalException* calls
930 with references to SIM_CORE_SIGNAL hook.
931
932 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
933 fix.
934 * sim-main.c (*): Minor warning cleanups.
935
9361998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
937
938 * m16.igen (DADDIU5): Correct type-o.
939
940Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
941
942 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
943 variables.
944
945Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
946
947 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
948 to include path.
949 (interp.o): Add dependency on itable.h
950 (oengine.c, gencode): Delete remaining references.
951 (BUILT_SRC_FROM_GEN): Clean up.
952
9531998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
954
955 * vr4run.c: New.
956 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
957 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
958 tmp-run-hack) : New.
959 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
960 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
961 Drop the "64" qualifier to get the HACK generator working.
962 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
963 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
964 qualifier to get the hack generator working.
965 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
966 (DSLL): Use do_dsll.
967 (DSLLV): Use do_dsllv.
968 (DSRA): Use do_dsra.
969 (DSRL): Use do_dsrl.
970 (DSRLV): Use do_dsrlv.
971 (BC1): Move *vr4100 to get the HACK generator working.
972 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
973 get the HACK generator working.
974 (MACC) Rename to get the HACK generator working.
975 (DMACC,MACCS,DMACCS): Add the 64.
976
9771998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
978
979 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
980 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
981
9821998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
983
984 * mips/interp.c (DEBUG): Cleanups.
985
9861998-12-10 Frank Ch. Eigler <fche@cygnus.com>
987
988 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
989 (tx3904sio_tickle): fflush after a stdout character output.
990
9911998-12-03 Frank Ch. Eigler <fche@cygnus.com>
992
993 * interp.c (sim_close): Uninstall modules.
994
995Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
996
997 * sim-main.h, interp.c (sim_monitor): Change to global
998 function.
999
1000Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1001
1002 * configure.in (vr4100): Only include vr4100 instructions in
1003 simulator.
1004 * configure: Re-generate.
1005 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1006
1007Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1008
1009 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1010 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1011 true alternative.
1012
1013 * configure.in (sim_default_gen, sim_use_gen): Replace with
1014 sim_gen.
1015 (--enable-sim-igen): Delete config option. Always using IGEN.
1016 * configure: Re-generate.
1017
1018 * Makefile.in (gencode): Kill, kill, kill.
1019 * gencode.c: Ditto.
1020
1021Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1022
1023 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1024 bit mips16 igen simulator.
1025 * configure: Re-generate.
1026
1027 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1028 as part of vr4100 ISA.
1029 * vr.igen: Mark all instructions as 64 bit only.
1030
1031Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1032
1033 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1034 Pacify GCC.
1035
1036Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1037
1038 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1039 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1040 * configure: Re-generate.
1041
1042 * m16.igen (BREAK): Define breakpoint instruction.
1043 (JALX32): Mark instruction as mips16 and not r3900.
1044 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1045
1046 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1047
1048Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1049
1050 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1051 insn as a debug breakpoint.
1052
1053 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1054 pending.slot_size.
1055 (PENDING_SCHED): Clean up trace statement.
1056 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1057 (PENDING_FILL): Delay write by only one cycle.
1058 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1059
1060 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1061 of pending writes.
1062 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1063 32 & 64.
1064 (pending_tick): Move incrementing of index to FOR statement.
1065 (pending_tick): Only update PENDING_OUT after a write has occured.
1066
1067 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1068 build simulator.
1069 * configure: Re-generate.
1070
1071 * interp.c (sim_engine_run OLD): Delete explicit call to
1072 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1073
1074Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1075
1076 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1077 interrupt level number to match changed SignalExceptionInterrupt
1078 macro.
1079
1080Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1081
1082 * interp.c: #include "itable.h" if WITH_IGEN.
1083 (get_insn_name): New function.
1084 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1085 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1086
1087Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1088
1089 * configure: Rebuilt to inhale new common/aclocal.m4.
1090
1091Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1092
1093 * dv-tx3904sio.c: Include sim-assert.h.
1094
1095Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1096
1097 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1098 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1099 Reorganize target-specific sim-hardware checks.
1100 * configure: rebuilt.
1101 * interp.c (sim_open): For tx39 target boards, set
1102 OPERATING_ENVIRONMENT, add tx3904sio devices.
1103 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1104 ROM executables. Install dv-sockser into sim-modules list.
1105
1106 * dv-tx3904irc.c: Compiler warning clean-up.
1107 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1108 frequent hw-trace messages.
1109
1110Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1111
1112 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1113
1114Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1115
1116 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1117
1118 * vr.igen: New file.
1119 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1120 * mips.igen: Define vr4100 model. Include vr.igen.
1121Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1122
1123 * mips.igen (check_mf_hilo): Correct check.
1124
1125Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1126
1127 * sim-main.h (interrupt_event): Add prototype.
1128
1129 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1130 register_ptr, register_value.
1131 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1132
1133 * sim-main.h (tracefh): Make extern.
1134
1135Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1136
1137 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1138 Reduce unnecessarily high timer event frequency.
1139 * dv-tx3904cpu.c: Ditto for interrupt event.
1140
1141Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1142
1143 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1144 to allay warnings.
1145 (interrupt_event): Made non-static.
1146
1147 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1148 interchange of configuration values for external vs. internal
1149 clock dividers.
1150
1151Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1152
1153 * mips.igen (BREAK): Moved code to here for
1154 simulator-reserved break instructions.
1155 * gencode.c (build_instruction): Ditto.
1156 * interp.c (signal_exception): Code moved from here. Non-
1157 reserved instructions now use exception vector, rather
1158 than halting sim.
1159 * sim-main.h: Moved magic constants to here.
1160
1161Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1162
1163 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1164 register upon non-zero interrupt event level, clear upon zero
1165 event value.
1166 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1167 by passing zero event value.
1168 (*_io_{read,write}_buffer): Endianness fixes.
1169 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1170 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1171
1172 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1173 serial I/O and timer module at base address 0xFFFF0000.
1174
1175Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1176
1177 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1178 and BigEndianCPU.
1179
1180Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1181
1182 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1183 parts.
1184 * configure: Update.
1185
1186Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1187
1188 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1189 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1190 * configure.in: Include tx3904tmr in hw_device list.
1191 * configure: Rebuilt.
1192 * interp.c (sim_open): Instantiate three timer instances.
1193 Fix address typo of tx3904irc instance.
1194
1195Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1196
1197 * interp.c (signal_exception): SystemCall exception now uses
1198 the exception vector.
1199
1200Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1201
1202 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1203 to allay warnings.
1204
1205Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1206
1207 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1208
1209Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1210
1211 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1212
1213 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1214 sim-main.h. Declare a struct hw_descriptor instead of struct
1215 hw_device_descriptor.
1216
1217Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1218
1219 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1220 right bits and then re-align left hand bytes to correct byte
1221 lanes. Fix incorrect computation in do_store_left when loading
1222 bytes from second word.
1223
1224Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1225
1226 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1227 * interp.c (sim_open): Only create a device tree when HW is
1228 enabled.
1229
1230 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1231 * interp.c (signal_exception): Ditto.
1232
1233Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1234
1235 * gencode.c: Mark BEGEZALL as LIKELY.
1236
1237Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1238
1239 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1240 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1241
1242Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1243
1244 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1245 modules. Recognize TX39 target with "mips*tx39" pattern.
1246 * configure: Rebuilt.
1247 * sim-main.h (*): Added many macros defining bits in
1248 TX39 control registers.
1249 (SignalInterrupt): Send actual PC instead of NULL.
1250 (SignalNMIReset): New exception type.
1251 * interp.c (board): New variable for future use to identify
1252 a particular board being simulated.
1253 (mips_option_handler,mips_options): Added "--board" option.
1254 (interrupt_event): Send actual PC.
1255 (sim_open): Make memory layout conditional on board setting.
1256 (signal_exception): Initial implementation of hardware interrupt
1257 handling. Accept another break instruction variant for simulator
1258 exit.
1259 (decode_coproc): Implement RFE instruction for TX39.
1260 (mips.igen): Decode RFE instruction as such.
1261 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1262 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1263 bbegin to implement memory map.
1264 * dv-tx3904cpu.c: New file.
1265 * dv-tx3904irc.c: New file.
1266
1267Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1268
1269 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1270
1271Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1272
1273 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1274 with calls to check_div_hilo.
1275
1276Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1277
1278 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1279 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1280 Add special r3900 version of do_mult_hilo.
1281 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1282 with calls to check_mult_hilo.
1283 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1284 with calls to check_div_hilo.
1285
1286Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1287
1288 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1289 Document a replacement.
1290
1291Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1292
1293 * interp.c (sim_monitor): Make mon_printf work.
1294
1295Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1296
1297 * sim-main.h (INSN_NAME): New arg `cpu'.
1298
1299Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1300
1301 * configure: Regenerated to track ../common/aclocal.m4 changes.
1302
1303Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1304
1305 * configure: Regenerated to track ../common/aclocal.m4 changes.
1306 * config.in: Ditto.
1307
1308Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1309
1310 * acconfig.h: New file.
1311 * configure.in: Reverted change of Apr 24; use sinclude again.
1312
1313Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1314
1315 * configure: Regenerated to track ../common/aclocal.m4 changes.
1316 * config.in: Ditto.
1317
1318Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1319
1320 * configure.in: Don't call sinclude.
1321
1322Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1323
1324 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1325
1326Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1327
1328 * mips.igen (ERET): Implement.
1329
1330 * interp.c (decode_coproc): Return sign-extended EPC.
1331
1332 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1333
1334 * interp.c (signal_exception): Do not ignore Trap.
1335 (signal_exception): On TRAP, restart at exception address.
1336 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1337 (signal_exception): Update.
1338 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1339 so that TRAP instructions are caught.
1340
1341Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1342
1343 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1344 contains HI/LO access history.
1345 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1346 (HIACCESS, LOACCESS): Delete, replace with
1347 (HIHISTORY, LOHISTORY): New macros.
1348 (CHECKHILO): Delete all, moved to mips.igen
1349
1350 * gencode.c (build_instruction): Do not generate checks for
1351 correct HI/LO register usage.
1352
1353 * interp.c (old_engine_run): Delete checks for correct HI/LO
1354 register usage.
1355
1356 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1357 check_mf_cycles): New functions.
1358 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1359 do_divu, domultx, do_mult, do_multu): Use.
1360
1361 * tx.igen ("madd", "maddu"): Use.
1362
1363Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1364
1365 * mips.igen (DSRAV): Use function do_dsrav.
1366 (SRAV): Use new function do_srav.
1367
1368 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1369 (B): Sign extend 11 bit immediate.
1370 (EXT-B*): Shift 16 bit immediate left by 1.
1371 (ADDIU*): Don't sign extend immediate value.
1372
1373Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1374
1375 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1376
1377 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1378 functions.
1379
1380 * mips.igen (delayslot32, nullify_next_insn): New functions.
1381 (m16.igen): Always include.
1382 (do_*): Add more tracing.
1383
1384 * m16.igen (delayslot16): Add NIA argument, could be called by a
1385 32 bit MIPS16 instruction.
1386
1387 * interp.c (ifetch16): Move function from here.
1388 * sim-main.c (ifetch16): To here.
1389
1390 * sim-main.c (ifetch16, ifetch32): Update to match current
1391 implementations of LH, LW.
1392 (signal_exception): Don't print out incorrect hex value of illegal
1393 instruction.
1394
1395Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1396
1397 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1398 instruction.
1399
1400 * m16.igen: Implement MIPS16 instructions.
1401
1402 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1403 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1404 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1405 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1406 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1407 bodies of corresponding code from 32 bit insn to these. Also used
1408 by MIPS16 versions of functions.
1409
1410 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1411 (IMEM16): Drop NR argument from macro.
1412
1413Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1414
1415 * Makefile.in (SIM_OBJS): Add sim-main.o.
1416
1417 * sim-main.h (address_translation, load_memory, store_memory,
1418 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1419 as INLINE_SIM_MAIN.
1420 (pr_addr, pr_uword64): Declare.
1421 (sim-main.c): Include when H_REVEALS_MODULE_P.
1422
1423 * interp.c (address_translation, load_memory, store_memory,
1424 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1425 from here.
1426 * sim-main.c: To here. Fix compilation problems.
1427
1428 * configure.in: Enable inlining.
1429 * configure: Re-config.
1430
1431Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1432
1433 * configure: Regenerated to track ../common/aclocal.m4 changes.
1434
1435Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1436
1437 * mips.igen: Include tx.igen.
1438 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1439 * tx.igen: New file, contains MADD and MADDU.
1440
1441 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1442 the hardwired constant `7'.
1443 (store_memory): Ditto.
1444 (LOADDRMASK): Move definition to sim-main.h.
1445
1446 mips.igen (MTC0): Enable for r3900.
1447 (ADDU): Add trace.
1448
1449 mips.igen (do_load_byte): Delete.
1450 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1451 do_store_right): New functions.
1452 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1453
1454 configure.in: Let the tx39 use igen again.
1455 configure: Update.
1456
1457Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1460 not an address sized quantity. Return zero for cache sizes.
1461
1462Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1463
1464 * mips.igen (r3900): r3900 does not support 64 bit integer
1465 operations.
1466
1467Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1468
1469 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1470 than igen one.
1471 * configure : Rebuild.
1472
1473Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1474
1475 * configure: Regenerated to track ../common/aclocal.m4 changes.
1476
1477Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1478
1479 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1480
1481Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1482
1483 * configure: Regenerated to track ../common/aclocal.m4 changes.
1484 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1485
1486Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * configure: Regenerated to track ../common/aclocal.m4 changes.
1489
1490Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1491
1492 * interp.c (Max, Min): Comment out functions. Not yet used.
1493
1494Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * configure: Regenerated to track ../common/aclocal.m4 changes.
1497
1498Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1499
1500 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1501 configurable settings for stand-alone simulator.
1502
1503 * configure.in: Added X11 search, just in case.
1504
1505 * configure: Regenerated.
1506
1507Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 * interp.c (sim_write, sim_read, load_memory, store_memory):
1510 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1511
1512Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1513
1514 * sim-main.h (GETFCC): Return an unsigned value.
1515
1516Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1517
1518 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1519 (DADD): Result destination is RD not RT.
1520
1521Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1522
1523 * sim-main.h (HIACCESS, LOACCESS): Always define.
1524
1525 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1526
1527 * interp.c (sim_info): Delete.
1528
1529Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1530
1531 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1532 (mips_option_handler): New argument `cpu'.
1533 (sim_open): Update call to sim_add_option_table.
1534
1535Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1536
1537 * mips.igen (CxC1): Add tracing.
1538
1539Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1540
1541 * sim-main.h (Max, Min): Declare.
1542
1543 * interp.c (Max, Min): New functions.
1544
1545 * mips.igen (BC1): Add tracing.
1546
1547Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1548
1549 * interp.c Added memory map for stack in vr4100
1550
1551Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1552
1553 * interp.c (load_memory): Add missing "break"'s.
1554
1555Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1556
1557 * interp.c (sim_store_register, sim_fetch_register): Pass in
1558 length parameter. Return -1.
1559
1560Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1561
1562 * interp.c: Added hardware init hook, fixed warnings.
1563
1564Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1565
1566 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1567
1568Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1569
1570 * interp.c (ifetch16): New function.
1571
1572 * sim-main.h (IMEM32): Rename IMEM.
1573 (IMEM16_IMMED): Define.
1574 (IMEM16): Define.
1575 (DELAY_SLOT): Update.
1576
1577 * m16run.c (sim_engine_run): New file.
1578
1579 * m16.igen: All instructions except LB.
1580 (LB): Call do_load_byte.
1581 * mips.igen (do_load_byte): New function.
1582 (LB): Call do_load_byte.
1583
1584 * mips.igen: Move spec for insn bit size and high bit from here.
1585 * Makefile.in (tmp-igen, tmp-m16): To here.
1586
1587 * m16.dc: New file, decode mips16 instructions.
1588
1589 * Makefile.in (SIM_NO_ALL): Define.
1590 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1591
1592Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1593
1594 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1595 point unit to 32 bit registers.
1596 * configure: Re-generate.
1597
1598Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1599
1600 * configure.in (sim_use_gen): Make IGEN the default simulator
1601 generator for generic 32 and 64 bit mips targets.
1602 * configure: Re-generate.
1603
1604Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1607 bitsize.
1608
1609 * interp.c (sim_fetch_register, sim_store_register): Read/write
1610 FGR from correct location.
1611 (sim_open): Set size of FGR's according to
1612 WITH_TARGET_FLOATING_POINT_BITSIZE.
1613
1614 * sim-main.h (FGR): Store floating point registers in a separate
1615 array.
1616
1617Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 * configure: Regenerated to track ../common/aclocal.m4 changes.
1620
1621Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1622
1623 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1624
1625 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1626
1627 * interp.c (pending_tick): New function. Deliver pending writes.
1628
1629 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1630 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1631 it can handle mixed sized quantites and single bits.
1632
1633Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1634
1635 * interp.c (oengine.h): Do not include when building with IGEN.
1636 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1637 (sim_info): Ditto for PROCESSOR_64BIT.
1638 (sim_monitor): Replace ut_reg with unsigned_word.
1639 (*): Ditto for t_reg.
1640 (LOADDRMASK): Define.
1641 (sim_open): Remove defunct check that host FP is IEEE compliant,
1642 using software to emulate floating point.
1643 (value_fpr, ...): Always compile, was conditional on HASFPU.
1644
1645Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1646
1647 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1648 size.
1649
1650 * interp.c (SD, CPU): Define.
1651 (mips_option_handler): Set flags in each CPU.
1652 (interrupt_event): Assume CPU 0 is the one being iterrupted.
1653 (sim_close): Do not clear STATE, deleted anyway.
1654 (sim_write, sim_read): Assume CPU zero's vm should be used for
1655 data transfers.
1656 (sim_create_inferior): Set the PC for all processors.
1657 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1658 argument.
1659 (mips16_entry): Pass correct nr of args to store_word, load_word.
1660 (ColdReset): Cold reset all cpu's.
1661 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1662 (sim_monitor, load_memory, store_memory, signal_exception): Use
1663 `CPU' instead of STATE_CPU.
1664
1665
1666 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1667 SD or CPU_.
1668
1669 * sim-main.h (signal_exception): Add sim_cpu arg.
1670 (SignalException*): Pass both SD and CPU to signal_exception.
1671 * interp.c (signal_exception): Update.
1672
1673 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1674 Ditto
1675 (sync_operation, prefetch, cache_op, store_memory, load_memory,
1676 address_translation): Ditto
1677 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1678
1679Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
1680
1681 * configure: Regenerated to track ../common/aclocal.m4 changes.
1682
1683Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1684
1685 * interp.c (sim_engine_run): Add `nr_cpus' argument.
1686
1687 * mips.igen (model): Map processor names onto BFD name.
1688
1689 * sim-main.h (CPU_CIA): Delete.
1690 (SET_CIA, GET_CIA): Define
1691
1692Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
1693
1694 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1695 regiser.
1696
1697 * configure.in (default_endian): Configure a big-endian simulator
1698 by default.
1699 * configure: Re-generate.
1700
1701Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
1702
1703 * configure: Regenerated to track ../common/aclocal.m4 changes.
1704
1705Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
1706
1707 * interp.c (sim_monitor): Handle Densan monitor outbyte
1708 and inbyte functions.
1709
17101997-12-29 Felix Lee <flee@cygnus.com>
1711
1712 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1713
1714Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
1715
1716 * Makefile.in (tmp-igen): Arrange for $zero to always be
1717 reset to zero after every instruction.
1718
1719Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1720
1721 * configure: Regenerated to track ../common/aclocal.m4 changes.
1722 * config.in: Ditto.
1723
1724Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
1725
1726 * mips.igen (MSUB): Fix to work like MADD.
1727 * gencode.c (MSUB): Similarly.
1728
1729Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
1730
1731 * configure: Regenerated to track ../common/aclocal.m4 changes.
1732
1733Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1734
1735 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1736
1737Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1738
1739 * sim-main.h (sim-fpu.h): Include.
1740
1741 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1742 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1743 using host independant sim_fpu module.
1744
1745Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1746
1747 * interp.c (signal_exception): Report internal errors with SIGABRT
1748 not SIGQUIT.
1749
1750 * sim-main.h (C0_CONFIG): New register.
1751 (signal.h): No longer include.
1752
1753 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1754
1755Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1756
1757 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1758
1759Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1760
1761 * mips.igen: Tag vr5000 instructions.
1762 (ANDI): Was missing mipsIV model, fix assembler syntax.
1763 (do_c_cond_fmt): New function.
1764 (C.cond.fmt): Handle mips I-III which do not support CC field
1765 separatly.
1766 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1767 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1768 in IV3.2 spec.
1769 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1770 vr5000 which saves LO in a GPR separatly.
1771
1772 * configure.in (enable-sim-igen): For vr5000, select vr5000
1773 specific instructions.
1774 * configure: Re-generate.
1775
1776Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1777
1778 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1779
1780 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1781 fmt_uninterpreted_64 bit cases to switch. Convert to
1782 fmt_formatted,
1783
1784 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1785
1786 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1787 as specified in IV3.2 spec.
1788 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1789
1790Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1793 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1794 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1795 PENDING_FILL versions of instructions. Simplify.
1796 (X): New function.
1797 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1798 instructions.
1799 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1800 a signed value.
1801 (MTHI, MFHI): Disable code checking HI-LO.
1802
1803 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1804 global.
1805 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1806
1807Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1808
1809 * gencode.c (build_mips16_operands): Replace IPC with cia.
1810
1811 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1812 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1813 IPC to `cia'.
1814 (UndefinedResult): Replace function with macro/function
1815 combination.
1816 (sim_engine_run): Don't save PC in IPC.
1817
1818 * sim-main.h (IPC): Delete.
1819
1820
1821 * interp.c (signal_exception, store_word, load_word,
1822 address_translation, load_memory, store_memory, cache_op,
1823 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1824 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1825 current instruction address - cia - argument.
1826 (sim_read, sim_write): Call address_translation directly.
1827 (sim_engine_run): Rename variable vaddr to cia.
1828 (signal_exception): Pass cia to sim_monitor
1829
1830 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1831 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1832 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1833
1834 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1835 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1836 SIM_ASSERT.
1837
1838 * interp.c (signal_exception): Pass restart address to
1839 sim_engine_restart.
1840
1841 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1842 idecode.o): Add dependency.
1843
1844 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1845 Delete definitions
1846 (DELAY_SLOT): Update NIA not PC with branch address.
1847 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1848
1849 * mips.igen: Use CIA not PC in branch calculations.
1850 (illegal): Call SignalException.
1851 (BEQ, ADDIU): Fix assembler.
1852
1853Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * m16.igen (JALX): Was missing.
1856
1857 * configure.in (enable-sim-igen): New configuration option.
1858 * configure: Re-generate.
1859
1860 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1861
1862 * interp.c (load_memory, store_memory): Delete parameter RAW.
1863 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1864 bypassing {load,store}_memory.
1865
1866 * sim-main.h (ByteSwapMem): Delete definition.
1867
1868 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1869
1870 * interp.c (sim_do_command, sim_commands): Delete mips specific
1871 commands. Handled by module sim-options.
1872
1873 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1874 (WITH_MODULO_MEMORY): Define.
1875
1876 * interp.c (sim_info): Delete code printing memory size.
1877
1878 * interp.c (mips_size): Nee sim_size, delete function.
1879 (power2): Delete.
1880 (monitor, monitor_base, monitor_size): Delete global variables.
1881 (sim_open, sim_close): Delete code creating monitor and other
1882 memory regions. Use sim-memopts module, via sim_do_commandf, to
1883 manage memory regions.
1884 (load_memory, store_memory): Use sim-core for memory model.
1885
1886 * interp.c (address_translation): Delete all memory map code
1887 except line forcing 32 bit addresses.
1888
1889Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1892 trace options.
1893
1894 * interp.c (logfh, logfile): Delete globals.
1895 (sim_open, sim_close): Delete code opening & closing log file.
1896 (mips_option_handler): Delete -l and -n options.
1897 (OPTION mips_options): Ditto.
1898
1899 * interp.c (OPTION mips_options): Rename option trace to dinero.
1900 (mips_option_handler): Update.
1901
1902Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 * interp.c (fetch_str): New function.
1905 (sim_monitor): Rewrite using sim_read & sim_write.
1906 (sim_open): Check magic number.
1907 (sim_open): Write monitor vectors into memory using sim_write.
1908 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1909 (sim_read, sim_write): Simplify - transfer data one byte at a
1910 time.
1911 (load_memory, store_memory): Clarify meaning of parameter RAW.
1912
1913 * sim-main.h (isHOST): Defete definition.
1914 (isTARGET): Mark as depreciated.
1915 (address_translation): Delete parameter HOST.
1916
1917 * interp.c (address_translation): Delete parameter HOST.
1918
1919Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1920
1921 * mips.igen:
1922
1923 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1924 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1925
1926Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1927
1928 * mips.igen: Add model filter field to records.
1929
1930Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1931
1932 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1933
1934 interp.c (sim_engine_run): Do not compile function sim_engine_run
1935 when WITH_IGEN == 1.
1936
1937 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1938 target architecture.
1939
1940 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1941 igen. Replace with configuration variables sim_igen_flags /
1942 sim_m16_flags.
1943
1944 * m16.igen: New file. Copy mips16 insns here.
1945 * mips.igen: From here.
1946
1947Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1950 to top.
1951 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1952
1953Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1954
1955 * gencode.c (build_instruction): Follow sim_write's lead in using
1956 BigEndianMem instead of !ByteSwapMem.
1957
1958Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * configure.in (sim_gen): Dependent on target, select type of
1961 generator. Always select old style generator.
1962
1963 configure: Re-generate.
1964
1965 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1966 targets.
1967 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1968 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1969 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1970 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1971 SIM_@sim_gen@_*, set by autoconf.
1972
1973Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1976
1977 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1978 CURRENT_FLOATING_POINT instead.
1979
1980 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1981 (address_translation): Raise exception InstructionFetch when
1982 translation fails and isINSTRUCTION.
1983
1984 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1985 sim_engine_run): Change type of of vaddr and paddr to
1986 address_word.
1987 (address_translation, prefetch, load_memory, store_memory,
1988 cache_op): Change type of vAddr and pAddr to address_word.
1989
1990 * gencode.c (build_instruction): Change type of vaddr and paddr to
1991 address_word.
1992
1993Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1996 macro to obtain result of ALU op.
1997
1998Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1999
2000 * interp.c (sim_info): Call profile_print.
2001
2002Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2005
2006 * sim-main.h (WITH_PROFILE): Do not define, defined in
2007 common/sim-config.h. Use sim-profile module.
2008 (simPROFILE): Delete defintion.
2009
2010 * interp.c (PROFILE): Delete definition.
2011 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2012 (sim_close): Delete code writing profile histogram.
2013 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2014 Delete.
2015 (sim_engine_run): Delete code profiling the PC.
2016
2017Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2020
2021 * interp.c (sim_monitor): Make register pointers of type
2022 unsigned_word*.
2023
2024 * sim-main.h: Make registers of type unsigned_word not
2025 signed_word.
2026
2027Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * interp.c (sync_operation): Rename from SyncOperation, make
2030 global, add SD argument.
2031 (prefetch): Rename from Prefetch, make global, add SD argument.
2032 (decode_coproc): Make global.
2033
2034 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2035
2036 * gencode.c (build_instruction): Generate DecodeCoproc not
2037 decode_coproc calls.
2038
2039 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2040 (SizeFGR): Move to sim-main.h
2041 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2042 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2043 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2044 sim-main.h.
2045 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2046 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2047 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2048 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2049 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2050 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2051
2052 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2053 exception.
2054 (sim-alu.h): Include.
2055 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2056 (sim_cia): Typedef to instruction_address.
2057
2058Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2059
2060 * Makefile.in (interp.o): Rename generated file engine.c to
2061 oengine.c.
2062
2063 * interp.c: Update.
2064
2065Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2066
2067 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2068
2069Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2070
2071 * gencode.c (build_instruction): For "FPSQRT", output correct
2072 number of arguments to Recip.
2073
2074Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2075
2076 * Makefile.in (interp.o): Depends on sim-main.h
2077
2078 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2079
2080 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2081 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2082 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2083 STATE, DSSTATE): Define
2084 (GPR, FGRIDX, ..): Define.
2085
2086 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2087 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2088 (GPR, FGRIDX, ...): Delete macros.
2089
2090 * interp.c: Update names to match defines from sim-main.h
2091
2092Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2093
2094 * interp.c (sim_monitor): Add SD argument.
2095 (sim_warning): Delete. Replace calls with calls to
2096 sim_io_eprintf.
2097 (sim_error): Delete. Replace calls with sim_io_error.
2098 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2099 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2100 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2101 argument.
2102 (mips_size): Rename from sim_size. Add SD argument.
2103
2104 * interp.c (simulator): Delete global variable.
2105 (callback): Delete global variable.
2106 (mips_option_handler, sim_open, sim_write, sim_read,
2107 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2108 sim_size,sim_monitor): Use sim_io_* not callback->*.
2109 (sim_open): ZALLOC simulator struct.
2110 (PROFILE): Do not define.
2111
2112Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2113
2114 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2115 support.h with corresponding code.
2116
2117 * sim-main.h (word64, uword64), support.h: Move definition to
2118 sim-main.h.
2119 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2120
2121 * support.h: Delete
2122 * Makefile.in: Update dependencies
2123 * interp.c: Do not include.
2124
2125Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2126
2127 * interp.c (address_translation, load_memory, store_memory,
2128 cache_op): Rename to from AddressTranslation et.al., make global,
2129 add SD argument
2130
2131 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2132 CacheOp): Define.
2133
2134 * interp.c (SignalException): Rename to signal_exception, make
2135 global.
2136
2137 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2138
2139 * sim-main.h (SignalException, SignalExceptionInterrupt,
2140 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2141 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2142 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2143 Define.
2144
2145 * interp.c, support.h: Use.
2146
2147Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2148
2149 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2150 to value_fpr / store_fpr. Add SD argument.
2151 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2152 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2153
2154 * sim-main.h (ValueFPR, StoreFPR): Define.
2155
2156Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2157
2158 * interp.c (sim_engine_run): Check consistency between configure
2159 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2160 and HASFPU.
2161
2162 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2163 (mips_fpu): Configure WITH_FLOATING_POINT.
2164 (mips_endian): Configure WITH_TARGET_ENDIAN.
2165 * configure: Update.
2166
2167Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2168
2169 * configure: Regenerated to track ../common/aclocal.m4 changes.
2170
2171Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2172
2173 * configure: Regenerated.
2174
2175Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2176
2177 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2178
2179Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * gencode.c (print_igen_insn_models): Assume certain architectures
2182 include all mips* instructions.
2183 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2184 instruction.
2185
2186 * Makefile.in (tmp.igen): Add target. Generate igen input from
2187 gencode file.
2188
2189 * gencode.c (FEATURE_IGEN): Define.
2190 (main): Add --igen option. Generate output in igen format.
2191 (process_instructions): Format output according to igen option.
2192 (print_igen_insn_format): New function.
2193 (print_igen_insn_models): New function.
2194 (process_instructions): Only issue warnings and ignore
2195 instructions when no FEATURE_IGEN.
2196
2197Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2198
2199 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2200 MIPS targets.
2201
2202Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2203
2204 * configure: Regenerated to track ../common/aclocal.m4 changes.
2205
2206Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2207
2208 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2209 SIM_RESERVED_BITS): Delete, moved to common.
2210 (SIM_EXTRA_CFLAGS): Update.
2211
2212Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * configure.in: Configure non-strict memory alignment.
2215 * configure: Regenerated to track ../common/aclocal.m4 changes.
2216
2217Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * configure: Regenerated to track ../common/aclocal.m4 changes.
2220
2221Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2222
2223 * gencode.c (SDBBP,DERET): Added (3900) insns.
2224 (RFE): Turn on for 3900.
2225 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2226 (dsstate): Made global.
2227 (SUBTARGET_R3900): Added.
2228 (CANCELDELAYSLOT): New.
2229 (SignalException): Ignore SystemCall rather than ignore and
2230 terminate. Add DebugBreakPoint handling.
2231 (decode_coproc): New insns RFE, DERET; and new registers Debug
2232 and DEPC protected by SUBTARGET_R3900.
2233 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2234 bits explicitly.
2235 * Makefile.in,configure.in: Add mips subtarget option.
2236 * configure: Update.
2237
2238Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2239
2240 * gencode.c: Add r3900 (tx39).
2241
2242
2243Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2244
2245 * gencode.c (build_instruction): Don't need to subtract 4 for
2246 JALR, just 2.
2247
2248Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2249
2250 * interp.c: Correct some HASFPU problems.
2251
2252Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2253
2254 * configure: Regenerated to track ../common/aclocal.m4 changes.
2255
2256Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2257
2258 * interp.c (mips_options): Fix samples option short form, should
2259 be `x'.
2260
2261Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2262
2263 * interp.c (sim_info): Enable info code. Was just returning.
2264
2265Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2266
2267 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2268 MFC0.
2269
2270Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2271
2272 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2273 constants.
2274 (build_instruction): Ditto for LL.
2275
2276Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2277
2278 * configure: Regenerated to track ../common/aclocal.m4 changes.
2279
2280Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * configure: Regenerated to track ../common/aclocal.m4 changes.
2283 * config.in: Ditto.
2284
2285Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * interp.c (sim_open): Add call to sim_analyze_program, update
2288 call to sim_config.
2289
2290Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2291
2292 * interp.c (sim_kill): Delete.
2293 (sim_create_inferior): Add ABFD argument. Set PC from same.
2294 (sim_load): Move code initializing trap handlers from here.
2295 (sim_open): To here.
2296 (sim_load): Delete, use sim-hload.c.
2297
2298 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2299
2300Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2301
2302 * configure: Regenerated to track ../common/aclocal.m4 changes.
2303 * config.in: Ditto.
2304
2305Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2306
2307 * interp.c (sim_open): Add ABFD argument.
2308 (sim_load): Move call to sim_config from here.
2309 (sim_open): To here. Check return status.
2310
2311Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2312
2313 * gencode.c (build_instruction): Two arg MADD should
2314 not assign result to $0.
2315
2316Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2317
2318 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2319 * sim/mips/configure.in: Regenerate.
2320
2321Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2322
2323 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2324 signed8, unsigned8 et.al. types.
2325
2326 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2327 hosts when selecting subreg.
2328
2329Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2330
2331 * interp.c (sim_engine_run): Reset the ZERO register to zero
2332 regardless of FEATURE_WARN_ZERO.
2333 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2334
2335Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2336
2337 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2338 (SignalException): For BreakPoints ignore any mode bits and just
2339 save the PC.
2340 (SignalException): Always set the CAUSE register.
2341
2342Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2343
2344 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2345 exception has been taken.
2346
2347 * interp.c: Implement the ERET and mt/f sr instructions.
2348
2349Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * interp.c (SignalException): Don't bother restarting an
2352 interrupt.
2353
2354Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2355
2356 * interp.c (SignalException): Really take an interrupt.
2357 (interrupt_event): Only deliver interrupts when enabled.
2358
2359Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2360
2361 * interp.c (sim_info): Only print info when verbose.
2362 (sim_info) Use sim_io_printf for output.
2363
2364Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2365
2366 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2367 mips architectures.
2368
2369Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2370
2371 * interp.c (sim_do_command): Check for common commands if a
2372 simulator specific command fails.
2373
2374Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2375
2376 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2377 and simBE when DEBUG is defined.
2378
2379Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2380
2381 * interp.c (interrupt_event): New function. Pass exception event
2382 onto exception handler.
2383
2384 * configure.in: Check for stdlib.h.
2385 * configure: Regenerate.
2386
2387 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2388 variable declaration.
2389 (build_instruction): Initialize memval1.
2390 (build_instruction): Add UNUSED attribute to byte, bigend,
2391 reverse.
2392 (build_operands): Ditto.
2393
2394 * interp.c: Fix GCC warnings.
2395 (sim_get_quit_code): Delete.
2396
2397 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2398 * Makefile.in: Ditto.
2399 * configure: Re-generate.
2400
2401 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2402
2403Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2404
2405 * interp.c (mips_option_handler): New function parse argumes using
2406 sim-options.
2407 (myname): Replace with STATE_MY_NAME.
2408 (sim_open): Delete check for host endianness - performed by
2409 sim_config.
2410 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2411 (sim_open): Move much of the initialization from here.
2412 (sim_load): To here. After the image has been loaded and
2413 endianness set.
2414 (sim_open): Move ColdReset from here.
2415 (sim_create_inferior): To here.
2416 (sim_open): Make FP check less dependant on host endianness.
2417
2418 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2419 run.
2420 * interp.c (sim_set_callbacks): Delete.
2421
2422 * interp.c (membank, membank_base, membank_size): Replace with
2423 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2424 (sim_open): Remove call to callback->init. gdb/run do this.
2425
2426 * interp.c: Update
2427
2428 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2429
2430 * interp.c (big_endian_p): Delete, replaced by
2431 current_target_byte_order.
2432
2433Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2434
2435 * interp.c (host_read_long, host_read_word, host_swap_word,
2436 host_swap_long): Delete. Using common sim-endian.
2437 (sim_fetch_register, sim_store_register): Use H2T.
2438 (pipeline_ticks): Delete. Handled by sim-events.
2439 (sim_info): Update.
2440 (sim_engine_run): Update.
2441
2442Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2443
2444 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2445 reason from here.
2446 (SignalException): To here. Signal using sim_engine_halt.
2447 (sim_stop_reason): Delete, moved to common.
2448
2449Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2450
2451 * interp.c (sim_open): Add callback argument.
2452 (sim_set_callbacks): Delete SIM_DESC argument.
2453 (sim_size): Ditto.
2454
2455Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2456
2457 * Makefile.in (SIM_OBJS): Add common modules.
2458
2459 * interp.c (sim_set_callbacks): Also set SD callback.
2460 (set_endianness, xfer_*, swap_*): Delete.
2461 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2462 Change to functions using sim-endian macros.
2463 (control_c, sim_stop): Delete, use common version.
2464 (simulate): Convert into.
2465 (sim_engine_run): This function.
2466 (sim_resume): Delete.
2467
2468 * interp.c (simulation): New variable - the simulator object.
2469 (sim_kind): Delete global - merged into simulation.
2470 (sim_load): Cleanup. Move PC assignment from here.
2471 (sim_create_inferior): To here.
2472
2473 * sim-main.h: New file.
2474 * interp.c (sim-main.h): Include.
2475
2476Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2477
2478 * configure: Regenerated to track ../common/aclocal.m4 changes.
2479
2480Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2481
2482 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2483
2484Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2485
2486 * gencode.c (build_instruction): DIV instructions: check
2487 for division by zero and integer overflow before using
2488 host's division operation.
2489
2490Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2491
2492 * Makefile.in (SIM_OBJS): Add sim-load.o.
2493 * interp.c: #include bfd.h.
2494 (target_byte_order): Delete.
2495 (sim_kind, myname, big_endian_p): New static locals.
2496 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2497 after argument parsing. Recognize -E arg, set endianness accordingly.
2498 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2499 load file into simulator. Set PC from bfd.
2500 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2501 (set_endianness): Use big_endian_p instead of target_byte_order.
2502
2503Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2504
2505 * interp.c (sim_size): Delete prototype - conflicts with
2506 definition in remote-sim.h. Correct definition.
2507
2508Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2509
2510 * configure: Regenerated to track ../common/aclocal.m4 changes.
2511 * config.in: Ditto.
2512
2513Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2514
2515 * interp.c (sim_open): New arg `kind'.
2516
2517 * configure: Regenerated to track ../common/aclocal.m4 changes.
2518
2519Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2520
2521 * configure: Regenerated to track ../common/aclocal.m4 changes.
2522
2523Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2524
2525 * interp.c (sim_open): Set optind to 0 before calling getopt.
2526
2527Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2528
2529 * configure: Regenerated to track ../common/aclocal.m4 changes.
2530
2531Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2532
2533 * interp.c : Replace uses of pr_addr with pr_uword64
2534 where the bit length is always 64 independent of SIM_ADDR.
2535 (pr_uword64) : added.
2536
2537Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2538
2539 * configure: Re-generate.
2540
2541Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2542
2543 * configure: Regenerate to track ../common/aclocal.m4 changes.
2544
2545Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2546
2547 * interp.c (sim_open): New SIM_DESC result. Argument is now
2548 in argv form.
2549 (other sim_*): New SIM_DESC argument.
2550
2551Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2552
2553 * interp.c: Fix printing of addresses for non-64-bit targets.
2554 (pr_addr): Add function to print address based on size.
2555
2556Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2557
2558 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2559
2560Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2561
2562 * gencode.c (build_mips16_operands): Correct computation of base
2563 address for extended PC relative instruction.
2564
2565Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2566
2567 * interp.c (mips16_entry): Add support for floating point cases.
2568 (SignalException): Pass floating point cases to mips16_entry.
2569 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2570 registers.
2571 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2572 or fmt_word.
2573 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2574 and then set the state to fmt_uninterpreted.
2575 (COP_SW): Temporarily set the state to fmt_word while calling
2576 ValueFPR.
2577
2578Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2579
2580 * gencode.c (build_instruction): The high order may be set in the
2581 comparison flags at any ISA level, not just ISA 4.
2582
2583Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2584
2585 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2586 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2587 * configure.in: sinclude ../common/aclocal.m4.
2588 * configure: Regenerated.
2589
2590Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2591
2592 * configure: Rebuild after change to aclocal.m4.
2593
2594Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2595
2596 * configure configure.in Makefile.in: Update to new configure
2597 scheme which is more compatible with WinGDB builds.
2598 * configure.in: Improve comment on how to run autoconf.
2599 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2600 * Makefile.in: Use autoconf substitution to install common
2601 makefile fragment.
2602
2603Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2604
2605 * gencode.c (build_instruction): Use BigEndianCPU instead of
2606 ByteSwapMem.
2607
2608Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2609
2610 * interp.c (sim_monitor): Make output to stdout visible in
2611 wingdb's I/O log window.
2612
2613Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2614
2615 * support.h: Undo previous change to SIGTRAP
2616 and SIGQUIT values.
2617
2618Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2619
2620 * interp.c (store_word, load_word): New static functions.
2621 (mips16_entry): New static function.
2622 (SignalException): Look for mips16 entry and exit instructions.
2623 (simulate): Use the correct index when setting fpr_state after
2624 doing a pending move.
2625
2626Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2627
2628 * interp.c: Fix byte-swapping code throughout to work on
2629 both little- and big-endian hosts.
2630
2631Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2632
2633 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2634 with gdb/config/i386/xm-windows.h.
2635
2636Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2637
2638 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2639 that messes up arithmetic shifts.
2640
2641Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2642
2643 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2644 SIGTRAP and SIGQUIT for _WIN32.
2645
2646Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2647
2648 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2649 force a 64 bit multiplication.
2650 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2651 destination register is 0, since that is the default mips16 nop
2652 instruction.
2653
2654Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2655
2656 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2657 (build_endian_shift): Don't check proc64.
2658 (build_instruction): Always set memval to uword64. Cast op2 to
2659 uword64 when shifting it left in memory instructions. Always use
2660 the same code for stores--don't special case proc64.
2661
2662 * gencode.c (build_mips16_operands): Fix base PC value for PC
2663 relative operands.
2664 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2665 jal instruction.
2666 * interp.c (simJALDELAYSLOT): Define.
2667 (JALDELAYSLOT): Define.
2668 (INDELAYSLOT, INJALDELAYSLOT): Define.
2669 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2670
2671Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2672
2673 * interp.c (sim_open): add flush_cache as a PMON routine
2674 (sim_monitor): handle flush_cache by ignoring it
2675
2676Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2677
2678 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2679 BigEndianMem.
2680 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2681 (BigEndianMem): Rename to ByteSwapMem and change sense.
2682 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2683 BigEndianMem references to !ByteSwapMem.
2684 (set_endianness): New function, with prototype.
2685 (sim_open): Call set_endianness.
2686 (sim_info): Use simBE instead of BigEndianMem.
2687 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2688 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2689 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2690 ifdefs, keeping the prototype declaration.
2691 (swap_word): Rewrite correctly.
2692 (ColdReset): Delete references to CONFIG. Delete endianness related
2693 code; moved to set_endianness.
2694
2695Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2696
2697 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2698 * interp.c (CHECKHILO): Define away.
2699 (simSIGINT): New macro.
2700 (membank_size): Increase from 1MB to 2MB.
2701 (control_c): New function.
2702 (sim_resume): Rename parameter signal to signal_number. Add local
2703 variable prev. Call signal before and after simulate.
2704 (sim_stop_reason): Add simSIGINT support.
2705 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2706 functions always.
2707 (sim_warning): Delete call to SignalException. Do call printf_filtered
2708 if logfh is NULL.
2709 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2710 a call to sim_warning.
2711
2712Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2713
2714 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2715 16 bit instructions.
2716
2717Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2718
2719 Add support for mips16 (16 bit MIPS implementation):
2720 * gencode.c (inst_type): Add mips16 instruction encoding types.
2721 (GETDATASIZEINSN): Define.
2722 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2723 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2724 mtlo.
2725 (MIPS16_DECODE): New table, for mips16 instructions.
2726 (bitmap_val): New static function.
2727 (struct mips16_op): Define.
2728 (mips16_op_table): New table, for mips16 operands.
2729 (build_mips16_operands): New static function.
2730 (process_instructions): If PC is odd, decode a mips16
2731 instruction. Break out instruction handling into new
2732 build_instruction function.
2733 (build_instruction): New static function, broken out of
2734 process_instructions. Check modifiers rather than flags for SHIFT
2735 bit count and m[ft]{hi,lo} direction.
2736 (usage): Pass program name to fprintf.
2737 (main): Remove unused variable this_option_optind. Change
2738 ``*loptarg++'' to ``loptarg++''.
2739 (my_strtoul): Parenthesize && within ||.
2740 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2741 (simulate): If PC is odd, fetch a 16 bit instruction, and
2742 increment PC by 2 rather than 4.
2743 * configure.in: Add case for mips16*-*-*.
2744 * configure: Rebuild.
2745
2746Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2747
2748 * interp.c: Allow -t to enable tracing in standalone simulator.
2749 Fix garbage output in trace file and error messages.
2750
2751Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2752
2753 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2754 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2755 * configure.in: Simplify using macros in ../common/aclocal.m4.
2756 * configure: Regenerated.
2757 * tconfig.in: New file.
2758
2759Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2760
2761 * interp.c: Fix bugs in 64-bit port.
2762 Use ansi function declarations for msvc compiler.
2763 Initialize and test file pointer in trace code.
2764 Prevent duplicate definition of LAST_EMED_REGNUM.
2765
2766Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2767
2768 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2769
2770Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2771
2772 * interp.c (SignalException): Check for explicit terminating
2773 breakpoint value.
2774 * gencode.c: Pass instruction value through SignalException()
2775 calls for Trap, Breakpoint and Syscall.
2776
2777Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2778
2779 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2780 only used on those hosts that provide it.
2781 * configure.in: Add sqrt() to list of functions to be checked for.
2782 * config.in: Re-generated.
2783 * configure: Re-generated.
2784
2785Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2786
2787 * gencode.c (process_instructions): Call build_endian_shift when
2788 expanding STORE RIGHT, to fix swr.
2789 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2790 clear the high bits.
2791 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2792 Fix float to int conversions to produce signed values.
2793
2794Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2795
2796 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2797 (process_instructions): Correct handling of nor instruction.
2798 Correct shift count for 32 bit shift instructions. Correct sign
2799 extension for arithmetic shifts to not shift the number of bits in
2800 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2801 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2802 Fix madd.
2803 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2804 It's OK to have a mult follow a mult. What's not OK is to have a
2805 mult follow an mfhi.
2806 (Convert): Comment out incorrect rounding code.
2807
2808Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2809
2810 * interp.c (sim_monitor): Improved monitor printf
2811 simulation. Tidied up simulator warnings, and added "--log" option
2812 for directing warning message output.
2813 * gencode.c: Use sim_warning() rather than WARNING macro.
2814
2815Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2816
2817 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2818 getopt1.o, rather than on gencode.c. Link objects together.
2819 Don't link against -liberty.
2820 (gencode.o, getopt.o, getopt1.o): New targets.
2821 * gencode.c: Include <ctype.h> and "ansidecl.h".
2822 (AND): Undefine after including "ansidecl.h".
2823 (ULONG_MAX): Define if not defined.
2824 (OP_*): Don't define macros; now defined in opcode/mips.h.
2825 (main): Call my_strtoul rather than strtoul.
2826 (my_strtoul): New static function.
2827
2828Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2829
2830 * gencode.c (process_instructions): Generate word64 and uword64
2831 instead of `long long' and `unsigned long long' data types.
2832 * interp.c: #include sysdep.h to get signals, and define default
2833 for SIGBUS.
2834 * (Convert): Work around for Visual-C++ compiler bug with type
2835 conversion.
2836 * support.h: Make things compile under Visual-C++ by using
2837 __int64 instead of `long long'. Change many refs to long long
2838 into word64/uword64 typedefs.
2839
2840Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2841
2842 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2843 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2844 (docdir): Removed.
2845 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2846 (AC_PROG_INSTALL): Added.
2847 (AC_PROG_CC): Moved to before configure.host call.
2848 * configure: Rebuilt.
2849
2850Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2851
2852 * configure.in: Define @SIMCONF@ depending on mips target.
2853 * configure: Rebuild.
2854 * Makefile.in (run): Add @SIMCONF@ to control simulator
2855 construction.
2856 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2857 * interp.c: Remove some debugging, provide more detailed error
2858 messages, update memory accesses to use LOADDRMASK.
2859
2860Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2861
2862 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2863 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2864 stamp-h.
2865 * configure: Rebuild.
2866 * config.in: New file, generated by autoheader.
2867 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2868 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2869 HAVE_ANINT and HAVE_AINT, as appropriate.
2870 * Makefile.in (run): Use @LIBS@ rather than -lm.
2871 (interp.o): Depend upon config.h.
2872 (Makefile): Just rebuild Makefile.
2873 (clean): Remove stamp-h.
2874 (mostlyclean): Make the same as clean, not as distclean.
2875 (config.h, stamp-h): New targets.
2876
2877Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2878
2879 * interp.c (ColdReset): Fix boolean test. Make all simulator
2880 globals static.
2881
2882Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2883
2884 * interp.c (xfer_direct_word, xfer_direct_long,
2885 swap_direct_word, swap_direct_long, xfer_big_word,
2886 xfer_big_long, xfer_little_word, xfer_little_long,
2887 swap_word,swap_long): Added.
2888 * interp.c (ColdReset): Provide function indirection to
2889 host<->simulated_target transfer routines.
2890 * interp.c (sim_store_register, sim_fetch_register): Updated to
2891 make use of indirected transfer routines.
2892
2893Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2894
2895 * gencode.c (process_instructions): Ensure FP ABS instruction
2896 recognised.
2897 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2898 system call support.
2899
2900Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2901
2902 * interp.c (sim_do_command): Complain if callback structure not
2903 initialised.
2904
2905Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2906
2907 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2908 support for Sun hosts.
2909 * Makefile.in (gencode): Ensure the host compiler and libraries
2910 used for cross-hosted build.
2911
2912Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2913
2914 * interp.c, gencode.c: Some more (TODO) tidying.
2915
2916Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2917
2918 * gencode.c, interp.c: Replaced explicit long long references with
2919 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2920 * support.h (SET64LO, SET64HI): Macros added.
2921
2922Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2923
2924 * configure: Regenerate with autoconf 2.7.
2925
2926Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2927
2928 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2929 * support.h: Remove superfluous "1" from #if.
2930 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2931
2932Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2933
2934 * interp.c (StoreFPR): Control UndefinedResult() call on
2935 WARN_RESULT manifest.
2936
2937Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2938
2939 * gencode.c: Tidied instruction decoding, and added FP instruction
2940 support.
2941
2942 * interp.c: Added dineroIII, and BSD profiling support. Also
2943 run-time FP handling.
2944
2945Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2946
2947 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2948 gencode.c, interp.c, support.h: created.
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