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Add Intel Itanium Series 9500 support
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
5f3ef9d0
JB		 12012-06-15 Joel Brobecker <brobecker@adacore.com>
2
3 * config.in, configure: Regenerate.
4
a6ff997c
NC		 52012-05-18 Nick Clifton <nickc@redhat.com>
6
7 PR 14072
8 * interp.c: Include config.h before system header files.
9
2232061b
MF		 102012-03-24 Mike Frysinger <vapier@gentoo.org>
11
12 * aclocal.m4, config.in, configure: Regenerate.
13
db2e4d67
MF		 142011-12-03 Mike Frysinger <vapier@gentoo.org>
15
16 * aclocal.m4: New file.
17 * configure: Regenerate.
18
4399a56b
MF		 192011-10-19 Mike Frysinger <vapier@gentoo.org>
20
21 * configure: Regenerate after common/acinclude.m4 update.
22
9c082ca8
MF		 232011-10-17 Mike Frysinger <vapier@gentoo.org>
24
25 * configure.ac: Change include to common/acinclude.m4.
26
6ffe910a
MF		 272011-10-17 Mike Frysinger <vapier@gentoo.org>
28
29 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
30 call. Replace common.m4 include with SIM_AC_COMMON.
31 * configure: Regenerate.
32
31b28250
HPN		 332011-07-08 Hans-Peter Nilsson <hp@axis.com>
34
3faa01e3
HPN		 35 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
36 $(SIM_EXTRA_DEPS).
37 (tmp-mach-multi): Exit early when igen fails.
31b28250 38
2419798b
MF		 392011-07-05 Mike Frysinger <vapier@gentoo.org>
40
41 * interp.c (sim_do_command): Delete.
42
d79fe0d6
MF		 432011-02-14 Mike Frysinger <vapier@gentoo.org>
44
45 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
46 (tx3904sio_fifo_reset): Likewise.
47 * interp.c (sim_monitor): Likewise.
48
5558e7e6
MF		 492010-04-14 Mike Frysinger <vapier@gentoo.org>
50
51 * interp.c (sim_write): Add const to buffer arg.
52
35aafff4
JB		 532010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
54
55 * interp.c: Don't include sysdep.h
56
3725885a
RW		 572010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
58
59 * configure: Regenerate.
60
d6416cdc
RW		 612009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
62
81ecdfbb
RW		 63 * config.in: Regenerate.
64 * configure: Likewise.
65
d6416cdc
RW		 66 * configure: Regenerate.
67
b5bd9624
HPN		 682008-07-11 Hans-Peter Nilsson <hp@axis.com>
69
70 * configure: Regenerate to track ../common/common.m4 changes.
71 * config.in: Ditto.
72
6efef468
JM		 732008-06-06 Vladimir Prus <vladimir@codesourcery.com>
74 Daniel Jacobowitz <dan@codesourcery.com>
75 Joseph Myers <joseph@codesourcery.com>
76
77 * configure: Regenerate.
78
60dc88db
RS		 792007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
80
81 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
82 that unconditionally allows fmt_ps.
83 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
84 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
85 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
86 filter from 64,f to 32,f.
87 (PREFX): Change filter from 64 to 32.
88 (LDXC1, LUXC1): Provide separate mips32r2 implementations
89 that use do_load_double instead of do_load. Make both LUXC1
90 versions unpredictable if SizeFGR () != 64.
91 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
92 instead of do_store. Remove unused variable. Make both SUXC1
93 versions unpredictable if SizeFGR () != 64.
94
599ca73e
RS		 952007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
96
97 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
98 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
99 shifts for that case.
100
2525df03
NC		 1012007-09-04 Nick Clifton <nickc@redhat.com>
102
103 * interp.c (options enum): Add OPTION_INFO_MEMORY.
104 (display_mem_info): New static variable.
105 (mips_option_handler): Handle OPTION_INFO_MEMORY.
106 (mips_options): Add info-memory and memory-info.
107 (sim_open): After processing the command line and board
108 specification, check display_mem_info. If it is set then
109 call the real handler for the --memory-info command line
110 switch.
111
35ee6e1e
JB		 1122007-08-24 Joel Brobecker <brobecker@adacore.com>
113
114 * configure.ac: Change license of multi-run.c to GPL version 3.
115 * configure: Regenerate.
116
d5fb0879
RS		 1172007-06-28 Richard Sandiford <richard@codesourcery.com>
118
119 * configure.ac, configure: Revert last patch.
120
2a2ce21b
RS		 1212007-06-26 Richard Sandiford <richard@codesourcery.com>
122
123 * configure.ac (sim_mipsisa3264_configs): New variable.
124 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
125 every configuration support all four targets, using the triplet to
126 determine the default.
127 * configure: Regenerate.
128
efdcccc9
RS		 1292007-06-25 Richard Sandiford <richard@codesourcery.com>
130
0a7692b2 131 * Makefile.in (m16run.o): New rule.
efdcccc9 132
f532a356
TS		 1332007-05-15 Thiemo Seufer <ths@mips.com>
134
135 * mips3264r2.igen (DSHD): Fix compile warning.
136
bfe9c90b
TS		 1372007-05-14 Thiemo Seufer <ths@mips.com>
138
139 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
140 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
141 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
142 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
143 for mips32r2.
144
53f4826b
TS		 1452007-03-01 Thiemo Seufer <ths@mips.com>
146
147 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
148 and mips64.
149
8bf3ddc8
TS		 1502007-02-20 Thiemo Seufer <ths@mips.com>
151
152 * dsp.igen: Update copyright notice.
153 * dsp2.igen: Fix copyright notice.
154
8b082fb1
TS		 1552007-02-20 Thiemo Seufer <ths@mips.com>
156 Chao-Ying Fu <fu@mips.com>
157
158 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
159 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
160 Add dsp2 to sim_igen_machine.
161 * configure: Regenerate.
162 * dsp.igen (do_ph_op): Add MUL support when op = 2.
163 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
164 (mulq_rs.ph): Use do_ph_mulq.
165 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
166 * mips.igen: Add dsp2 model and include dsp2.igen.
167 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
168 for *mips32r2, *mips64r2, *dsp.
169 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
170 for *mips32r2, *mips64r2, *dsp2.
171 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
172
b1004875
TS		 1732007-02-19 Thiemo Seufer <ths@mips.com>
174 Nigel Stephens <nigel@mips.com>
175
176 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
177 jumps with hazard barrier.
178
f8df4c77
TS		 1792007-02-19 Thiemo Seufer <ths@mips.com>
180 Nigel Stephens <nigel@mips.com>
181
182 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
183 after each call to sim_io_write.
184
b1004875 1852007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 186 Nigel Stephens <nigel@mips.com>
b1004875
TS		 187
188 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
189 supported by this simulator.
07802d98
TS		 190 (decode_coproc): Recognise additional CP0 Config registers
191 correctly.
192
14fb6c5a
TS		 1932007-02-19 Thiemo Seufer <ths@mips.com>
194 Nigel Stephens <nigel@mips.com>
195 David Ung <davidu@mips.com>
196
197 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
198 uninterpreted formats. If fmt is one of the uninterpreted types
199 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
200 fmt_word, and fmt_uninterpreted_64 like fmt_long.
201 (store_fpr): When writing an invalid odd register, set the
202 matching even register to fmt_unknown, not the following register.
203 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
204 the the memory window at offset 0 set by --memory-size command
205 line option.
206 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
207 point register.
208 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
209 register.
210 (sim_monitor): When returning the memory size to the MIPS
211 application, use the value in STATE_MEM_SIZE, not an arbitrary
212 hardcoded value.
213 (cop_lw): Don' mess around with FPR_STATE, just pass
214 fmt_uninterpreted_32 to StoreFPR.
215 (cop_sw): Similarly.
216 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
217 (cop_sd): Similarly.
218 * mips.igen (not_word_value): Single version for mips32, mips64
219 and mips16.
220
c8847145
TS		 2212007-02-19 Thiemo Seufer <ths@mips.com>
222 Nigel Stephens <nigel@mips.com>
223
224 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
225 MBytes.
226
4b5d35ee
TS		 2272007-02-17 Thiemo Seufer <ths@mips.com>
228
229 * configure.ac (mips*-sde-elf*): Move in front of generic machine
230 configuration.
231 * configure: Regenerate.
232
3669427c
TS		 2332007-02-17 Thiemo Seufer <ths@mips.com>
234
235 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
236 Add mdmx to sim_igen_machine.
237 (mipsisa64*-*-*): Likewise. Remove dsp.
238 (mipsisa32*-*-*): Remove dsp.
239 * configure: Regenerate.
240
109ad085
TS		 2412007-02-13 Thiemo Seufer <ths@mips.com>
242
243 * configure.ac: Add mips*-sde-elf* target.
244 * configure: Regenerate.
245
921d7ad3
HPN		 2462006-12-21 Hans-Peter Nilsson <hp@axis.com>
247
248 * acconfig.h: Remove.
249 * config.in, configure: Regenerate.
250
02f97da7
TS		 2512006-11-07 Thiemo Seufer <ths@mips.com>
252
253 * dsp.igen (do_w_op): Fix compiler warning.
254
2d2733fc
TS		 2552006-08-29 Thiemo Seufer <ths@mips.com>
256 David Ung <davidu@mips.com>
257
258 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
259 sim_igen_machine.
260 * configure: Regenerate.
261 * mips.igen (model): Add smartmips.
262 (MADDU): Increment ACX if carry.
263 (do_mult): Clear ACX.
264 (ROR,RORV): Add smartmips.
265 (include): Include smartmips.igen.
266 * sim-main.h (ACX): Set to REGISTERS[89].
267 * smartmips.igen: New file.
268
d85c3a10
TS		 2692006-08-29 Thiemo Seufer <ths@mips.com>
270 David Ung <davidu@mips.com>
271
272 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
273 mips3264r2.igen. Add missing dependency rules.
274 * m16e.igen: Support for mips16e save/restore instructions.
275
e85e3205
RE		 2762006-06-13 Richard Earnshaw <rearnsha@arm.com>
277
278 * configure: Regenerated.
279
2f0122dc
DJ		 2802006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
281
282 * configure: Regenerated.
283
20e95c23
DJ		 2842006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
285
286 * configure: Regenerated.
287
69088b17
CF		 2882006-05-15 Chao-ying Fu <fu@mips.com>
289
290 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
291
0275de4e
NC		 2922006-04-18 Nick Clifton <nickc@redhat.com>
293
294 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
295 statement.
296
b3a3ffef
HPN		 2972006-03-29 Hans-Peter Nilsson <hp@axis.com>
298
299 * configure: Regenerate.
300
40a5538e
CF		 3012005-12-14 Chao-ying Fu <fu@mips.com>
302
303 * Makefile.in (SIM_OBJS): Add dsp.o.
304 (dsp.o): New dependency.
305 (IGEN_INCLUDE): Add dsp.igen.
306 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
307 mipsisa64*-*-*): Add dsp to sim_igen_machine.
308 * configure: Regenerate.
309 * mips.igen: Add dsp model and include dsp.igen.
310 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
311 because these instructions are extended in DSP ASE.
312 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
313 adding 6 DSP accumulator registers and 1 DSP control register.
314 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
315 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
316 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
317 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
318 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
319 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
320 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
321 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
322 DSPCR_CCOND_SMASK): New define.
323 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
324 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
325
21d14896
ILT		 3262005-07-08 Ian Lance Taylor <ian@airs.com>
327
328 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
329
b16d63da
DU		 3302005-06-16 David Ung <davidu@mips.com>
331 Nigel Stephens <nigel@mips.com>
332
333 * mips.igen: New mips16e model and include m16e.igen.
334 (check_u64): Add mips16e tag.
335 * m16e.igen: New file for MIPS16e instructions.
336 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
337 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
338 models.
339 * configure: Regenerate.
340
e70cb6cd
CD		 3412005-05-26 David Ung <davidu@mips.com>
342
343 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
344 tags to all instructions which are applicable to the new ISAs.
345 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
346 vr.igen.
347 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
348 instructions.
349 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
350 to mips.igen.
351 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
352 * configure: Regenerate.
353
2b193c4a
MK		 3542005-03-23 Mark Kettenis <kettenis@gnu.org>
355
356 * configure: Regenerate.
357
35695fd6
AC		 3582005-01-14 Andrew Cagney <cagney@gnu.org>
359
360 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
361 explicit call to AC_CONFIG_HEADER.
362 * configure: Regenerate.
363
f0569246
AC		 3642005-01-12 Andrew Cagney <cagney@gnu.org>
365
366 * configure.ac: Update to use ../common/common.m4.
367 * configure: Re-generate.
368
38f48d72
AC		 3692005-01-11 Andrew Cagney <cagney@localhost.localdomain>
370
371 * configure: Regenerated to track ../common/aclocal.m4 changes.
372
b7026657
AC		 3732005-01-07 Andrew Cagney <cagney@gnu.org>
374
375 * configure.ac: Rename configure.in, require autoconf 2.59.
376 * configure: Re-generate.
377
379832de
HPN		 3782004-12-08 Hans-Peter Nilsson <hp@axis.com>
379
380 * configure: Regenerate for ../common/aclocal.m4 update.
381
cd62154c
AC		 3822004-09-24 Monika Chaddha <monika@acmet.com>
383
384 Committed by Andrew Cagney.
385 * m16.igen (CMP, CMPI): Fix assembler.
386
e5da76ec
CD		 3872004-08-18 Chris Demetriou <cgd@broadcom.com>
388
389 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
390 * configure: Regenerate.
391
139181c8
CD		 3922004-06-25 Chris Demetriou <cgd@broadcom.com>
393
394 * configure.in (sim_m16_machine): Include mipsIII.
395 * configure: Regenerate.
396
1a27f959
CD		 3972004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
398
399 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
400 from COP0_BADVADDR.
401 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
402
5dbb7b5a
CD		 4032004-04-10 Chris Demetriou <cgd@broadcom.com>
404
405 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
406
14234056
CD		 4072004-04-09 Chris Demetriou <cgd@broadcom.com>
408
409 * mips.igen (check_fmt): Remove.
410 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
411 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
412 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
413 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
414 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
415 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
416 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
417 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
418 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
419 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
420
c6f9085c
CD		 4212004-04-09 Chris Demetriou <cgd@broadcom.com>
422
423 * sb1.igen (check_sbx): New function.
424 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
425
11d66e66 4262004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 427 Richard Sandiford <rsandifo@redhat.com>
428
429 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
430 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
431 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
432 separate implementations for mipsIV and mipsV. Use new macros to
433 determine whether the restrictions apply.
434
b3208fb8
CD		 4352004-01-19 Chris Demetriou <cgd@broadcom.com>
436
437 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
438 (check_mult_hilo): Improve comments.
439 (check_div_hilo): Likewise. Also, fork off a new version
440 to handle mips32/mips64 (since there are no hazards to check
441 in MIPS32/MIPS64).
442
9a1d84fb
CD		 4432003-06-17 Richard Sandiford <rsandifo@redhat.com>
444
445 * mips.igen (do_dmultx): Fix check for negative operands.
446
ae451ac6
ILT		 4472003-05-16 Ian Lance Taylor <ian@airs.com>
448
449 * Makefile.in (SHELL): Make sure this is defined.
450 (various): Use $(SHELL) whenever we invoke move-if-change.
451
dd69d292
CD		 4522003-05-03 Chris Demetriou <cgd@broadcom.com>
453
454 * cp1.c: Tweak attribution slightly.
455 * cp1.h: Likewise.
456 * mdmx.c: Likewise.
457 * mdmx.igen: Likewise.
458 * mips3d.igen: Likewise.
459 * sb1.igen: Likewise.
460
bcd0068e
CD		 4612003-04-15 Richard Sandiford <rsandifo@redhat.com>
462
463 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
464 unsigned operands.
465
6b4a8935
AC		 4662003-02-27 Andrew Cagney <cagney@redhat.com>
467
601da316
AC		 468 * interp.c (sim_open): Rename _bfd to bfd.
469 (sim_create_inferior): Ditto.
6b4a8935 470
d29e330f
CD		 4712003-01-14 Chris Demetriou <cgd@broadcom.com>
472
473 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
474
a2353a08
CD		 4752003-01-14 Chris Demetriou <cgd@broadcom.com>
476
477 * mips.igen (EI, DI): Remove.
478
80551777
CD		 4792003-01-05 Richard Sandiford <rsandifo@redhat.com>
480
481 * Makefile.in (tmp-run-multi): Fix mips16 filter.
482
4c54fc26
CD		 4832003-01-04 Richard Sandiford <rsandifo@redhat.com>
484 Andrew Cagney <ac131313@redhat.com>
485 Gavin Romig-Koch <gavin@redhat.com>
486 Graydon Hoare <graydon@redhat.com>
487 Aldy Hernandez <aldyh@redhat.com>
488 Dave Brolley <brolley@redhat.com>
489 Chris Demetriou <cgd@broadcom.com>
490
491 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
492 (sim_mach_default): New variable.
493 (mips64vr-*-*, mips64vrel-*-*): New configurations.
494 Add a new simulator generator, MULTI.
495 * configure: Regenerate.
496 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
497 (multi-run.o): New dependency.
498 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
499 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
500 (tmp-multi): Combine them.
501 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
502 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
503 (distclean-extra): New rule.
504 * sim-main.h: Include bfd.h.
505 (MIPS_MACH): New macro.
506 * mips.igen (vr4120, vr5400, vr5500): New models.
507 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
508 * vr.igen: Replace with new version.
509
e6c674b8
CD		 5102003-01-04 Chris Demetriou <cgd@broadcom.com>
511
512 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
513 * configure: Regenerate.
514
28f50ac8
CD		 5152002-12-31 Chris Demetriou <cgd@broadcom.com>
516
517 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
518 * mips.igen: Remove all invocations of check_branch_bug and
519 mark_branch_bug.
520
5071ffe6
CD		 5212002-12-16 Chris Demetriou <cgd@broadcom.com>
522
523 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
524
06e7837e
CD		 5252002-07-30 Chris Demetriou <cgd@broadcom.com>
526
527 * mips.igen (do_load_double, do_store_double): New functions.
528 (LDC1, SDC1): Rename to...
529 (LDC1b, SDC1b): respectively.
530 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
531
2265c243
MS		 5322002-07-29 Michael Snyder <msnyder@redhat.com>
533
534 * cp1.c (fp_recip2): Modify initialization expression so that
535 GCC will recognize it as constant.
536
a2f8b4f3
CD		 5372002-06-18 Chris Demetriou <cgd@broadcom.com>
538
539 * mdmx.c (SD_): Delete.
540 (Unpredictable): Re-define, for now, to directly invoke
541 unpredictable_action().
542 (mdmx_acc_op): Fix error in .ob immediate handling.
543
b4b6c939
AC		 5442002-06-18 Andrew Cagney <cagney@redhat.com>
545
546 * interp.c (sim_firmware_command): Initialize `address'.
547
c8cca39f
AC		 5482002-06-16 Andrew Cagney <ac131313@redhat.com>
549
550 * configure: Regenerated to track ../common/aclocal.m4 changes.
551
e7e81181
CD		 5522002-06-14 Chris Demetriou <cgd@broadcom.com>
553 Ed Satterthwaite <ehs@broadcom.com>
554
555 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
556 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
557 * mips.igen: Include mips3d.igen.
558 (mips3d): New model name for MIPS-3D ASE instructions.
559 (CVT.W.fmt): Don't use this instruction for word (source) format
560 instructions.
561 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
562 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
563 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
564 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
565 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
566 (RSquareRoot1, RSquareRoot2): New macros.
567 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
568 (fp_rsqrt2): New functions.
569 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
570 * configure: Regenerate.
571
3a2b820e 5722002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 573 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 574
575 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
576 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
577 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
578 (convert): Note that this function is not used for paired-single
579 format conversions.
580 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
581 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
582 (check_fmt_p): Enable paired-single support.
583 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
584 (PUU.PS): New instructions.
585 (CVT.S.fmt): Don't use this instruction for paired-single format
586 destinations.
587 * sim-main.h (FP_formats): New value 'fmt_ps.'
588 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
589 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
590
d18ea9c2
CD		 5912002-06-12 Chris Demetriou <cgd@broadcom.com>
592
593 * mips.igen: Fix formatting of function calls in
594 many FP operations.
595
95fd5cee
CD		 5962002-06-12 Chris Demetriou <cgd@broadcom.com>
597
598 * mips.igen (MOVN, MOVZ): Trace result.
599 (TNEI): Print "tnei" as the opcode name in traces.
600 (CEIL.W): Add disassembly string for traces.
601 (RSQRT.fmt): Make location of disassembly string consistent
602 with other instructions.
603
4f0d55ae
CD		 6042002-06-12 Chris Demetriou <cgd@broadcom.com>
605
606 * mips.igen (X): Delete unused function.
607
3c25f8c7
AC		 6082002-06-08 Andrew Cagney <cagney@redhat.com>
609
610 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
611
f3c08b7e
CD		 6122002-06-07 Chris Demetriou <cgd@broadcom.com>
613 Ed Satterthwaite <ehs@broadcom.com>
614
615 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
616 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
617 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
618 (fp_nmsub): New prototypes.
619 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
620 (NegMultiplySub): New defines.
621 * mips.igen (RSQRT.fmt): Use RSquareRoot().
622 (MADD.D, MADD.S): Replace with...
623 (MADD.fmt): New instruction.
624 (MSUB.D, MSUB.S): Replace with...
625 (MSUB.fmt): New instruction.
626 (NMADD.D, NMADD.S): Replace with...
627 (NMADD.fmt): New instruction.
628 (NMSUB.D, MSUB.S): Replace with...
629 (NMSUB.fmt): New instruction.
630
52714ff9
CD		 6312002-06-07 Chris Demetriou <cgd@broadcom.com>
632 Ed Satterthwaite <ehs@broadcom.com>
633
634 * cp1.c: Fix more comment spelling and formatting.
635 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
636 (denorm_mode): New function.
637 (fpu_unary, fpu_binary): Round results after operation, collect
638 status from rounding operations, and update the FCSR.
639 (convert): Collect status from integer conversions and rounding
640 operations, and update the FCSR. Adjust NaN values that result
641 from conversions. Convert to use sim_io_eprintf rather than
642 fprintf, and remove some debugging code.
643 * cp1.h (fenr_FS): New define.
644
577d8c4b
CD		 6452002-06-07 Chris Demetriou <cgd@broadcom.com>
646
647 * cp1.c (convert): Remove unusable debugging code, and move MIPS
648 rounding mode to sim FP rounding mode flag conversion code into...
649 (rounding_mode): New function.
650
196496ed
CD		 6512002-06-07 Chris Demetriou <cgd@broadcom.com>
652
653 * cp1.c: Clean up formatting of a few comments.
654 (value_fpr): Reformat switch statement.
655
cfe9ea23
CD		 6562002-06-06 Chris Demetriou <cgd@broadcom.com>
657 Ed Satterthwaite <ehs@broadcom.com>
658
659 * cp1.h: New file.
660 * sim-main.h: Include cp1.h.
661 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
662 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
663 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
664 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
665 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
666 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
667 * cp1.c: Don't include sim-fpu.h; already included by
668 sim-main.h. Clean up formatting of some comments.
669 (NaN, Equal, Less): Remove.
670 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
671 (fp_cmp): New functions.
672 * mips.igen (do_c_cond_fmt): Remove.
673 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
674 Compare. Add result tracing.
675 (CxC1): Remove, replace with...
676 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
677 (DMxC1): Remove, replace with...
678 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
679 (MxC1): Remove, replace with...
680 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
681
ee7254b0
CD		 6822002-06-04 Chris Demetriou <cgd@broadcom.com>
683
684 * sim-main.h (FGRIDX): Remove, replace all uses with...
685 (FGR_BASE): New macro.
686 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
687 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
688 (NR_FGR, FGR): Likewise.
689 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
690 * mips.igen: Likewise.
691
d3eb724f
CD		 6922002-06-04 Chris Demetriou <cgd@broadcom.com>
693
694 * cp1.c: Add an FSF Copyright notice to this file.
695
ba46ddd0
CD		 6962002-06-04 Chris Demetriou <cgd@broadcom.com>
697 Ed Satterthwaite <ehs@broadcom.com>
698
699 * cp1.c (Infinity): Remove.
700 * sim-main.h (Infinity): Likewise.
701
702 * cp1.c (fp_unary, fp_binary): New functions.
703 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
704 (fp_sqrt): New functions, implemented in terms of the above.
705 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
706 (Recip, SquareRoot): Remove (replaced by functions above).
707 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
708 (fp_recip, fp_sqrt): New prototypes.
709 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
710 (Recip, SquareRoot): Replace prototypes with #defines which
711 invoke the functions above.
712
18d8a52d
CD		 7132002-06-03 Chris Demetriou <cgd@broadcom.com>
714
715 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
716 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
717 file, remove PARAMS from prototypes.
718 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
719 simulator state arguments.
720 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
721 pass simulator state arguments.
722 * cp1.c (SD): Redefine as CPU_STATE(cpu).
723 (store_fpr, convert): Remove 'sd' argument.
724 (value_fpr): Likewise. Convert to use 'SD' instead.
725
0f154cbd
CD		 7262002-06-03 Chris Demetriou <cgd@broadcom.com>
727
728 * cp1.c (Min, Max): Remove #if 0'd functions.
729 * sim-main.h (Min, Max): Remove.
730
e80fc152
CD		 7312002-06-03 Chris Demetriou <cgd@broadcom.com>
732
733 * cp1.c: fix formatting of switch case and default labels.
734 * interp.c: Likewise.
735 * sim-main.c: Likewise.
736
bad673a9
CD		 7372002-06-03 Chris Demetriou <cgd@broadcom.com>
738
739 * cp1.c: Clean up comments which describe FP formats.
740 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
741
7cbea089
CD		 7422002-06-03 Chris Demetriou <cgd@broadcom.com>
743 Ed Satterthwaite <ehs@broadcom.com>
744
745 * configure.in (mipsisa64sb1*-*-*): New target for supporting
746 Broadcom SiByte SB-1 processor configurations.
747 * configure: Regenerate.
748 * sb1.igen: New file.
749 * mips.igen: Include sb1.igen.
750 (sb1): New model.
751 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
752 * mdmx.igen: Add "sb1" model to all appropriate functions and
753 instructions.
754 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
755 (ob_func, ob_acc): Reference the above.
756 (qh_acc): Adjust to keep the same size as ob_acc.
757 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
758 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
759
909daa82
CD		 7602002-06-03 Chris Demetriou <cgd@broadcom.com>
761
762 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
763
f4f1b9f1
CD		 7642002-06-02 Chris Demetriou <cgd@broadcom.com>
765 Ed Satterthwaite <ehs@broadcom.com>
766
767 * mips.igen (mdmx): New (pseudo-)model.
768 * mdmx.c, mdmx.igen: New files.
769 * Makefile.in (SIM_OBJS): Add mdmx.o.
770 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
771 New typedefs.
772 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
773 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
774 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
775 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
776 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
777 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
778 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
779 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
780 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
781 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
782 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
783 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
784 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
785 (qh_fmtsel): New macros.
786 (_sim_cpu): New member "acc".
787 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
788 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
789
5accf1ff
CD		 7902002-05-01 Chris Demetriou <cgd@broadcom.com>
791
792 * interp.c: Use 'deprecated' rather than 'depreciated.'
793 * sim-main.h: Likewise.
794
402586aa
CD		 7952002-05-01 Chris Demetriou <cgd@broadcom.com>
796
797 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
798 which wouldn't compile anyway.
799 * sim-main.h (unpredictable_action): New function prototype.
800 (Unpredictable): Define to call igen function unpredictable().
801 (NotWordValue): New macro to call igen function not_word_value().
802 (UndefinedResult): Remove.
803 * interp.c (undefined_result): Remove.
804 (unpredictable_action): New function.
805 * mips.igen (not_word_value, unpredictable): New functions.
806 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
807 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
808 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
809 NotWordValue() to check for unpredictable inputs, then
810 Unpredictable() to handle them.
811
c9b9995a
CD		 8122002-02-24 Chris Demetriou <cgd@broadcom.com>
813
814 * mips.igen: Fix formatting of calls to Unpredictable().
815
e1015982
AC		 8162002-04-20 Andrew Cagney <ac131313@redhat.com>
817
818 * interp.c (sim_open): Revert previous change.
819
b882a66b
AO		 8202002-04-18 Alexandre Oliva <aoliva@redhat.com>
821
822 * interp.c (sim_open): Disable chunk of code that wrote code in
823 vector table entries.
824
c429b7dd
CD		 8252002-03-19 Chris Demetriou <cgd@broadcom.com>
826
827 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
828 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
829 unused definitions.
830
37d146fa
CD		 8312002-03-19 Chris Demetriou <cgd@broadcom.com>
832
833 * cp1.c: Fix many formatting issues.
834
07892c0b
CD		 8352002-03-19 Chris G. Demetriou <cgd@broadcom.com>
836
837 * cp1.c (fpu_format_name): New function to replace...
838 (DOFMT): This. Delete, and update all callers.
839 (fpu_rounding_mode_name): New function to replace...
840 (RMMODE): This. Delete, and update all callers.
841
487f79b7
CD		 8422002-03-19 Chris G. Demetriou <cgd@broadcom.com>
843
844 * interp.c: Move FPU support routines from here to...
845 * cp1.c: Here. New file.
846 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
847 (cp1.o): New target.
848
1e799e28
CD		 8492002-03-12 Chris Demetriou <cgd@broadcom.com>
850
851 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
852 * mips.igen (mips32, mips64): New models, add to all instructions
853 and functions as appropriate.
854 (loadstore_ea, check_u64): New variant for model mips64.
855 (check_fmt_p): New variant for models mipsV and mips64, remove
856 mipsV model marking fro other variant.
857 (SLL) Rename to...
858 (SLLa) this.
859 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
860 for mips32 and mips64.
861 (DCLO, DCLZ): New instructions for mips64.
862
82f728db
CD		 8632002-03-07 Chris Demetriou <cgd@broadcom.com>
864
865 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
866 immediate or code as a hex value with the "%#lx" format.
867 (ANDI): Likewise, and fix printed instruction name.
868
b96e7ef1
CD		 8692002-03-05 Chris Demetriou <cgd@broadcom.com>
870
871 * sim-main.h (UndefinedResult, Unpredictable): New macros
872 which currently do nothing.
873
d35d4f70
CD		 8742002-03-05 Chris Demetriou <cgd@broadcom.com>
875
876 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
877 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
878 (status_CU3): New definitions.
879
880 * sim-main.h (ExceptionCause): Add new values for MIPS32
881 and MIPS64: MDMX, MCheck, CacheErr. Update comments
882 for DebugBreakPoint and NMIReset to note their status in
883 MIPS32 and MIPS64.
884 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
885 (SignalExceptionCacheErr): New exception macros.
886
3ad6f714
CD		 8872002-03-05 Chris Demetriou <cgd@broadcom.com>
888
889 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
890 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
891 is always enabled.
892 (SignalExceptionCoProcessorUnusable): Take as argument the
893 unusable coprocessor number.
894
86b77b47
CD		 8952002-03-05 Chris Demetriou <cgd@broadcom.com>
896
897 * mips.igen: Fix formatting of all SignalException calls.
898
97a88e93 8992002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 900
901 * sim-main.h (SIGNEXTEND): Remove.
902
97a88e93 9032002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 904
905 * mips.igen: Remove gencode comment from top of file, fix
906 spelling in another comment.
907
97a88e93 9082002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 909
910 * mips.igen (check_fmt, check_fmt_p): New functions to check
911 whether specific floating point formats are usable.
912 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
913 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
914 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
915 Use the new functions.
916 (do_c_cond_fmt): Remove format checks...
917 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
918
97a88e93 9192002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 920
921 * mips.igen: Fix formatting of check_fpu calls.
922
41774c9d
CD		 9232002-03-03 Chris Demetriou <cgd@broadcom.com>
924
925 * mips.igen (FLOOR.L.fmt): Store correct destination register.
926
4a0bd876
CD		 9272002-03-03 Chris Demetriou <cgd@broadcom.com>
928
929 * mips.igen: Remove whitespace at end of lines.
930
09297648
CD		 9312002-03-02 Chris Demetriou <cgd@broadcom.com>
932
933 * mips.igen (loadstore_ea): New function to do effective
934 address calculations.
935 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
936 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
937 CACHE): Use loadstore_ea to do effective address computations.
938
043b7057
CD		 9392002-03-02 Chris Demetriou <cgd@broadcom.com>
940
941 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
942 * mips.igen (LL, CxC1, MxC1): Likewise.
943
c1e8ada4
CD		 9442002-03-02 Chris Demetriou <cgd@broadcom.com>
945
946 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
947 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
948 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
949 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
950 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
951 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
952 Don't split opcode fields by hand, use the opcode field values
953 provided by igen.
954
3e1dca16
CD		 9552002-03-01 Chris Demetriou <cgd@broadcom.com>
956
957 * mips.igen (do_divu): Fix spacing.
958
959 * mips.igen (do_dsllv): Move to be right before DSLLV,
960 to match the rest of the do_<shift> functions.
961
fff8d27d
CD		 9622002-03-01 Chris Demetriou <cgd@broadcom.com>
963
964 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
965 DSRL32, do_dsrlv): Trace inputs and results.
966
0d3e762b
CD		 9672002-03-01 Chris Demetriou <cgd@broadcom.com>
968
969 * mips.igen (CACHE): Provide instruction-printing string.
970
971 * interp.c (signal_exception): Comment tokens after #endif.
972
eb5fcf93
CD		 9732002-02-28 Chris Demetriou <cgd@broadcom.com>
974
975 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
976 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
977 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
978 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
979 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
980 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
981 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
982 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
983
bb22bd7d
CD		 9842002-02-28 Chris Demetriou <cgd@broadcom.com>
985
986 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
987 instruction-printing string.
988 (LWU): Use '64' as the filter flag.
989
91a177cf
CD		 9902002-02-28 Chris Demetriou <cgd@broadcom.com>
991
992 * mips.igen (SDXC1): Fix instruction-printing string.
993
387f484a
CD		 9942002-02-28 Chris Demetriou <cgd@broadcom.com>
995
996 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
997 filter flags "32,f".
998
3d81f391
CD		 9992002-02-27 Chris Demetriou <cgd@broadcom.com>
1000
1001 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1002 as the filter flag.
1003
af5107af
CD		 10042002-02-27 Chris Demetriou <cgd@broadcom.com>
1005
1006 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1007 add a comma) so that it more closely match the MIPS ISA
1008 documentation opcode partitioning.
1009 (PREF): Put useful names on opcode fields, and include
1010 instruction-printing string.
1011
ca971540
CD		 10122002-02-27 Chris Demetriou <cgd@broadcom.com>
1013
1014 * mips.igen (check_u64): New function which in the future will
1015 check whether 64-bit instructions are usable and signal an
1016 exception if not. Currently a no-op.
1017 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1018 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1019 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1020 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1021
1022 * mips.igen (check_fpu): New function which in the future will
1023 check whether FPU instructions are usable and signal an exception
1024 if not. Currently a no-op.
1025 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1026 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1027 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1028 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1029 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1030 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1031 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1032 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1033
1c47a468
CD		 10342002-02-27 Chris Demetriou <cgd@broadcom.com>
1035
1036 * mips.igen (do_load_left, do_load_right): Move to be immediately
1037 following do_load.
1038 (do_store_left, do_store_right): Move to be immediately following
1039 do_store.
1040
603a98e7
CD		 10412002-02-27 Chris Demetriou <cgd@broadcom.com>
1042
1043 * mips.igen (mipsV): New model name. Also, add it to
1044 all instructions and functions where it is appropriate.
1045
c5d00cc7
CD		 10462002-02-18 Chris Demetriou <cgd@broadcom.com>
1047
1048 * mips.igen: For all functions and instructions, list model
1049 names that support that instruction one per line.
1050
074e9cb8
CD		 10512002-02-11 Chris Demetriou <cgd@broadcom.com>
1052
1053 * mips.igen: Add some additional comments about supported
1054 models, and about which instructions go where.
1055 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1056 order as is used in the rest of the file.
1057
9805e229
CD		 10582002-02-11 Chris Demetriou <cgd@broadcom.com>
1059
1060 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1061 indicating that ALU32_END or ALU64_END are there to check
1062 for overflow.
1063 (DADD): Likewise, but also remove previous comment about
1064 overflow checking.
1065
f701dad2
CD		 10662002-02-10 Chris Demetriou <cgd@broadcom.com>
1067
1068 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1069 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1070 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1071 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1072 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1073 fields (i.e., add and move commas) so that they more closely
1074 match the MIPS ISA documentation opcode partitioning.
1075
10762002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1077
1078 * mips.igen (ADDI): Print immediate value.
1079 (BREAK): Print code.
1080 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1081 (SLL): Print "nop" specially, and don't run the code
1082 that does the shift for the "nop" case.
1083
9e52972e
FF		 10842001-11-17 Fred Fish <fnf@redhat.com>
1085
1086 * sim-main.h (float_operation): Move enum declaration outside
1087 of _sim_cpu struct declaration.
1088
c0efbca4
JB		 10892001-04-12 Jim Blandy <jimb@redhat.com>
1090
1091 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1092 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1093 set of the FCSR.
1094 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1095 PENDING_FILL, and you can get the intended effect gracefully by
1096 calling PENDING_SCHED directly.
1097
fb891446
BE		 10982001-02-23 Ben Elliston <bje@redhat.com>
1099
1100 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1101 already defined elsewhere.
1102
8030f857
BE		 11032001-02-19 Ben Elliston <bje@redhat.com>
1104
1105 * sim-main.h (sim_monitor): Return an int.
1106 * interp.c (sim_monitor): Add return values.
1107 (signal_exception): Handle error conditions from sim_monitor.
1108
56b48a7a
CD		 11092001-02-08 Ben Elliston <bje@redhat.com>
1110
1111 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1112 (store_memory): Likewise, pass cia to sim_core_write*.
1113
d3ee60d9
FCE		 11142000-10-19 Frank Ch. Eigler <fche@redhat.com>
1115
1116 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1117 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1118
071da002
AC		 1119Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1120
1121 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1122 * Makefile.in: Don't delete *.igen when cleaning directory.
1123
a28c02cd
AC		 1124Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1125
1126 * m16.igen (break): Call SignalException not sim_engine_halt.
1127
80ee11fa
AC		 1128Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1129
1130 From Jason Eckhardt:
1131 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1132
673388c0
AC		 1133Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1134
1135 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1136
4c0deff4
NC		 11372000-05-24 Michael Hayes <mhayes@cygnus.com>
1138
1139 * mips.igen (do_dmultx): Fix typo.
1140
eb2d80b4
AC		 1141Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1142
1143 * configure: Regenerated to track ../common/aclocal.m4 changes.
1144
dd37a34b
AC		 1145Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1146
1147 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1148
4c0deff4
NC		 11492000-04-12 Frank Ch. Eigler <fche@redhat.com>
1150
1151 * sim-main.h (GPR_CLEAR): Define macro.
1152
e30db738
AC		 1153Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1154
1155 * interp.c (decode_coproc): Output long using %lx and not %s.
1156
cb7450ea
FCE		 11572000-03-21 Frank Ch. Eigler <fche@redhat.com>
1158
1159 * interp.c (sim_open): Sort & extend dummy memory regions for
1160 --board=jmr3904 for eCos.
1161
a3027dd7
FCE		 11622000-03-02 Frank Ch. Eigler <fche@redhat.com>
1163
1164 * configure: Regenerated.
1165
1166Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1167
1168 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1169 calls, conditional on the simulator being in verbose mode.
1170
dfcd3bfb
JM		 1171Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1172
1173 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1174 cache don't get ReservedInstruction traps.
1175
c2d11a7d
JM		 11761999-11-29 Mark Salter <msalter@cygnus.com>
1177
1178 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1179 to clear status bits in sdisr register. This is how the hardware works.
1180
1181 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1182 being used by cygmon.
1183
4ce44c66
JM		 11841999-11-11 Andrew Haley <aph@cygnus.com>
1185
1186 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1187 instructions.
1188
cff3e48b
JM		 1189Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1190
1191 * mips.igen (MULT): Correct previous mis-applied patch.
1192
d4f3574e
SS		 1193Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1194
1195 * mips.igen (delayslot32): Handle sequence like
1196 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1197 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1198 (MULT): Actually pass the third register...
1199
12001999-09-03 Mark Salter <msalter@cygnus.com>
1201
1202 * interp.c (sim_open): Added more memory aliases for additional
1203 hardware being touched by cygmon on jmr3904 board.
1204
1205Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1206
1207 * configure: Regenerated to track ../common/aclocal.m4 changes.
1208
a0b3c4fd
JM		 1209Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1210
1211 * interp.c (sim_store_register): Handle case where client - GDB -
1212 specifies that a 4 byte register is 8 bytes in size.
1213 (sim_fetch_register): Ditto.
1214
adf40b2e
JM		 12151999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1216
1217 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1218 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1219 (idt_monitor_base): Base address for IDT monitor traps.
1220 (pmon_monitor_base): Ditto for PMON.
1221 (lsipmon_monitor_base): Ditto for LSI PMON.
1222 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1223 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1224 (sim_firmware_command): New function.
1225 (mips_option_handler): Call it for OPTION_FIRMWARE.
1226 (sim_open): Allocate memory for idt_monitor region. If "--board"
1227 option was given, add no monitor by default. Add BREAK hooks only if
1228 monitors are also there.
1229
43e526b9
JM		 1230Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1231
1232 * interp.c (sim_monitor): Flush output before reading input.
1233
1234Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1235
1236 * tconfig.in (SIM_HANDLES_LMA): Always define.
1237
1238Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1239
1240 From Mark Salter <msalter@cygnus.com>:
1241 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1242 (sim_open): Add setup for BSP board.
1243
9846de1b
JM		 1244Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1245
1246 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1247 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1248 them as unimplemented.
1249
cd0fc7c3
SS		 12501999-05-08 Felix Lee <flee@cygnus.com>
1251
1252 * configure: Regenerated to track ../common/aclocal.m4 changes.
1253
7a292a7a
SS		 12541999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1255
1256 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1257
1258Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1259
1260 * configure.in: Any mips64vr5*-*-* target should have
1261 -DTARGET_ENABLE_FR=1.
1262 (default_endian): Any mips64vr*el-*-* target should default to
1263 LITTLE_ENDIAN.
1264 * configure: Re-generate.
1265
12661999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1267
1268 * mips.igen (ldl): Extend from _16_, not 32.
1269
1270Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1271
1272 * interp.c (sim_store_register): Force registers written to by GDB
1273 into an un-interpreted state.
1274
c906108c
SS		 12751999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1276
1277 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1278 CPU, start periodic background I/O polls.
1279 (tx3904sio_poll): New function: periodic I/O poller.
1280
12811998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1282
1283 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1284
1285Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1286
1287 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1288 case statement.
1289
12901998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1291
1292 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1293 (load_word): Call SIM_CORE_SIGNAL hook on error.
1294 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1295 starting. For exception dispatching, pass PC instead of NULL_CIA.
1296 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1297 * sim-main.h (COP0_BADVADDR): Define.
1298 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1299 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1300 (_sim_cpu): Add exc_* fields to store register value snapshots.
1301 * mips.igen (*): Replace memory-related SignalException* calls
1302 with references to SIM_CORE_SIGNAL hook.
1303
1304 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1305 fix.
1306 * sim-main.c (*): Minor warning cleanups.
1307
13081998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1309
1310 * m16.igen (DADDIU5): Correct type-o.
1311
1312Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1313
1314 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1315 variables.
1316
1317Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1318
1319 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1320 to include path.
1321 (interp.o): Add dependency on itable.h
1322 (oengine.c, gencode): Delete remaining references.
1323 (BUILT_SRC_FROM_GEN): Clean up.
1324
13251998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1326
1327 * vr4run.c: New.
1328 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1329 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1330 tmp-run-hack) : New.
1331 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1332 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1333 Drop the "64" qualifier to get the HACK generator working.
1334 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1335 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1336 qualifier to get the hack generator working.
1337 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1338 (DSLL): Use do_dsll.
1339 (DSLLV): Use do_dsllv.
1340 (DSRA): Use do_dsra.
1341 (DSRL): Use do_dsrl.
1342 (DSRLV): Use do_dsrlv.
1343 (BC1): Move *vr4100 to get the HACK generator working.
1344 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1345 get the HACK generator working.
1346 (MACC) Rename to get the HACK generator working.
1347 (DMACC,MACCS,DMACCS): Add the 64.
1348
13491998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1350
1351 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1352 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1353
13541998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1355
1356 * mips/interp.c (DEBUG): Cleanups.
1357
13581998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1359
1360 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1361 (tx3904sio_tickle): fflush after a stdout character output.
1362
13631998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1364
1365 * interp.c (sim_close): Uninstall modules.
1366
1367Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1368
1369 * sim-main.h, interp.c (sim_monitor): Change to global
1370 function.
1371
1372Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1373
1374 * configure.in (vr4100): Only include vr4100 instructions in
1375 simulator.
1376 * configure: Re-generate.
1377 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1378
1379Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1380
1381 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1382 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1383 true alternative.
1384
1385 * configure.in (sim_default_gen, sim_use_gen): Replace with
1386 sim_gen.
1387 (--enable-sim-igen): Delete config option. Always using IGEN.
1388 * configure: Re-generate.
1389
1390 * Makefile.in (gencode): Kill, kill, kill.
1391 * gencode.c: Ditto.
1392
1393Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1394
1395 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1396 bit mips16 igen simulator.
1397 * configure: Re-generate.
1398
1399 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1400 as part of vr4100 ISA.
1401 * vr.igen: Mark all instructions as 64 bit only.
1402
1403Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1404
1405 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1406 Pacify GCC.
1407
1408Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1409
1410 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1411 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1412 * configure: Re-generate.
1413
1414 * m16.igen (BREAK): Define breakpoint instruction.
1415 (JALX32): Mark instruction as mips16 and not r3900.
1416 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1417
1418 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1419
1420Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1421
1422 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1423 insn as a debug breakpoint.
1424
1425 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1426 pending.slot_size.
1427 (PENDING_SCHED): Clean up trace statement.
1428 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1429 (PENDING_FILL): Delay write by only one cycle.
1430 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1431
1432 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1433 of pending writes.
1434 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1435 32 & 64.
1436 (pending_tick): Move incrementing of index to FOR statement.
1437 (pending_tick): Only update PENDING_OUT after a write has occured.
1438
1439 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1440 build simulator.
1441 * configure: Re-generate.
1442
1443 * interp.c (sim_engine_run OLD): Delete explicit call to
1444 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1445
1446Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1447
1448 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1449 interrupt level number to match changed SignalExceptionInterrupt
1450 macro.
1451
1452Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1453
1454 * interp.c: #include "itable.h" if WITH_IGEN.
1455 (get_insn_name): New function.
1456 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1457 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1458
1459Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1460
1461 * configure: Rebuilt to inhale new common/aclocal.m4.
1462
1463Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1464
1465 * dv-tx3904sio.c: Include sim-assert.h.
1466
1467Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1468
1469 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1470 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1471 Reorganize target-specific sim-hardware checks.
1472 * configure: rebuilt.
1473 * interp.c (sim_open): For tx39 target boards, set
1474 OPERATING_ENVIRONMENT, add tx3904sio devices.
1475 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1476 ROM executables. Install dv-sockser into sim-modules list.
1477
1478 * dv-tx3904irc.c: Compiler warning clean-up.
1479 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1480 frequent hw-trace messages.
1481
1482Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1483
1484 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1485
1486Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1487
1488 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1489
1490 * vr.igen: New file.
1491 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1492 * mips.igen: Define vr4100 model. Include vr.igen.
1493Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1494
1495 * mips.igen (check_mf_hilo): Correct check.
1496
1497Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1498
1499 * sim-main.h (interrupt_event): Add prototype.
1500
1501 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1502 register_ptr, register_value.
1503 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1504
1505 * sim-main.h (tracefh): Make extern.
1506
1507Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1508
1509 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1510 Reduce unnecessarily high timer event frequency.
1511 * dv-tx3904cpu.c: Ditto for interrupt event.
1512
1513Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1514
1515 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1516 to allay warnings.
1517 (interrupt_event): Made non-static.
1518
1519 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1520 interchange of configuration values for external vs. internal
1521 clock dividers.
1522
1523Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1524
1525 * mips.igen (BREAK): Moved code to here for
1526 simulator-reserved break instructions.
1527 * gencode.c (build_instruction): Ditto.
1528 * interp.c (signal_exception): Code moved from here. Non-
1529 reserved instructions now use exception vector, rather
1530 than halting sim.
1531 * sim-main.h: Moved magic constants to here.
1532
1533Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1534
1535 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1536 register upon non-zero interrupt event level, clear upon zero
1537 event value.
1538 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1539 by passing zero event value.
1540 (*_io_{read,write}_buffer): Endianness fixes.
1541 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1542 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1543
1544 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1545 serial I/O and timer module at base address 0xFFFF0000.
1546
1547Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1548
1549 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1550 and BigEndianCPU.
1551
1552Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1553
1554 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1555 parts.
1556 * configure: Update.
1557
1558Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1559
1560 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1561 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1562 * configure.in: Include tx3904tmr in hw_device list.
1563 * configure: Rebuilt.
1564 * interp.c (sim_open): Instantiate three timer instances.
1565 Fix address typo of tx3904irc instance.
1566
1567Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1568
1569 * interp.c (signal_exception): SystemCall exception now uses
1570 the exception vector.
1571
1572Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1573
1574 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1575 to allay warnings.
1576
1577Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1580
1581Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1582
1583 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1584
1585 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1586 sim-main.h. Declare a struct hw_descriptor instead of struct
1587 hw_device_descriptor.
1588
1589Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1590
1591 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1592 right bits and then re-align left hand bytes to correct byte
1593 lanes. Fix incorrect computation in do_store_left when loading
1594 bytes from second word.
1595
1596Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1597
1598 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1599 * interp.c (sim_open): Only create a device tree when HW is
1600 enabled.
1601
1602 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1603 * interp.c (signal_exception): Ditto.
1604
1605Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1606
1607 * gencode.c: Mark BEGEZALL as LIKELY.
1608
1609Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1610
1611 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1612 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1613
1614Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1615
1616 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1617 modules. Recognize TX39 target with "mips*tx39" pattern.
1618 * configure: Rebuilt.
1619 * sim-main.h (*): Added many macros defining bits in
1620 TX39 control registers.
1621 (SignalInterrupt): Send actual PC instead of NULL.
1622 (SignalNMIReset): New exception type.
1623 * interp.c (board): New variable for future use to identify
1624 a particular board being simulated.
1625 (mips_option_handler,mips_options): Added "--board" option.
1626 (interrupt_event): Send actual PC.
1627 (sim_open): Make memory layout conditional on board setting.
1628 (signal_exception): Initial implementation of hardware interrupt
1629 handling. Accept another break instruction variant for simulator
1630 exit.
1631 (decode_coproc): Implement RFE instruction for TX39.
1632 (mips.igen): Decode RFE instruction as such.
1633 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1634 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1635 bbegin to implement memory map.
1636 * dv-tx3904cpu.c: New file.
1637 * dv-tx3904irc.c: New file.
1638
1639Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1640
1641 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1642
1643Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1644
1645 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1646 with calls to check_div_hilo.
1647
1648Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1649
1650 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1651 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1652 Add special r3900 version of do_mult_hilo.
1653 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1654 with calls to check_mult_hilo.
1655 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1656 with calls to check_div_hilo.
1657
1658Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1659
1660 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1661 Document a replacement.
1662
1663Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1664
1665 * interp.c (sim_monitor): Make mon_printf work.
1666
1667Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1668
1669 * sim-main.h (INSN_NAME): New arg `cpu'.
1670
1671Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1672
1673 * configure: Regenerated to track ../common/aclocal.m4 changes.
1674
1675Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1676
1677 * configure: Regenerated to track ../common/aclocal.m4 changes.
1678 * config.in: Ditto.
1679
1680Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1681
1682 * acconfig.h: New file.
1683 * configure.in: Reverted change of Apr 24; use sinclude again.
1684
1685Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1686
1687 * configure: Regenerated to track ../common/aclocal.m4 changes.
1688 * config.in: Ditto.
1689
1690Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1691
1692 * configure.in: Don't call sinclude.
1693
1694Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1695
1696 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1697
1698Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1699
1700 * mips.igen (ERET): Implement.
1701
1702 * interp.c (decode_coproc): Return sign-extended EPC.
1703
1704 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1705
1706 * interp.c (signal_exception): Do not ignore Trap.
1707 (signal_exception): On TRAP, restart at exception address.
1708 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1709 (signal_exception): Update.
1710 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1711 so that TRAP instructions are caught.
1712
1713Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1716 contains HI/LO access history.
1717 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1718 (HIACCESS, LOACCESS): Delete, replace with
1719 (HIHISTORY, LOHISTORY): New macros.
1720 (CHECKHILO): Delete all, moved to mips.igen
1721
1722 * gencode.c (build_instruction): Do not generate checks for
1723 correct HI/LO register usage.
1724
1725 * interp.c (old_engine_run): Delete checks for correct HI/LO
1726 register usage.
1727
1728 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1729 check_mf_cycles): New functions.
1730 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1731 do_divu, domultx, do_mult, do_multu): Use.
1732
1733 * tx.igen ("madd", "maddu"): Use.
1734
1735Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1736
1737 * mips.igen (DSRAV): Use function do_dsrav.
1738 (SRAV): Use new function do_srav.
1739
1740 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1741 (B): Sign extend 11 bit immediate.
1742 (EXT-B*): Shift 16 bit immediate left by 1.
1743 (ADDIU*): Don't sign extend immediate value.
1744
1745Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1746
1747 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1748
1749 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1750 functions.
1751
1752 * mips.igen (delayslot32, nullify_next_insn): New functions.
1753 (m16.igen): Always include.
1754 (do_*): Add more tracing.
1755
1756 * m16.igen (delayslot16): Add NIA argument, could be called by a
1757 32 bit MIPS16 instruction.
1758
1759 * interp.c (ifetch16): Move function from here.
1760 * sim-main.c (ifetch16): To here.
1761
1762 * sim-main.c (ifetch16, ifetch32): Update to match current
1763 implementations of LH, LW.
1764 (signal_exception): Don't print out incorrect hex value of illegal
1765 instruction.
1766
1767Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1768
1769 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1770 instruction.
1771
1772 * m16.igen: Implement MIPS16 instructions.
1773
1774 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1775 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1776 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1777 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1778 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1779 bodies of corresponding code from 32 bit insn to these. Also used
1780 by MIPS16 versions of functions.
1781
1782 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1783 (IMEM16): Drop NR argument from macro.
1784
1785Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * Makefile.in (SIM_OBJS): Add sim-main.o.
1788
1789 * sim-main.h (address_translation, load_memory, store_memory,
1790 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1791 as INLINE_SIM_MAIN.
1792 (pr_addr, pr_uword64): Declare.
1793 (sim-main.c): Include when H_REVEALS_MODULE_P.
1794
1795 * interp.c (address_translation, load_memory, store_memory,
1796 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1797 from here.
1798 * sim-main.c: To here. Fix compilation problems.
1799
1800 * configure.in: Enable inlining.
1801 * configure: Re-config.
1802
1803Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1804
1805 * configure: Regenerated to track ../common/aclocal.m4 changes.
1806
1807Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1808
1809 * mips.igen: Include tx.igen.
1810 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1811 * tx.igen: New file, contains MADD and MADDU.
1812
1813 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1814 the hardwired constant `7'.
1815 (store_memory): Ditto.
1816 (LOADDRMASK): Move definition to sim-main.h.
1817
1818 mips.igen (MTC0): Enable for r3900.
1819 (ADDU): Add trace.
1820
1821 mips.igen (do_load_byte): Delete.
1822 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1823 do_store_right): New functions.
1824 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1825
1826 configure.in: Let the tx39 use igen again.
1827 configure: Update.
1828
1829Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1830
1831 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1832 not an address sized quantity. Return zero for cache sizes.
1833
1834Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1835
1836 * mips.igen (r3900): r3900 does not support 64 bit integer
1837 operations.
1838
1839Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1840
1841 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1842 than igen one.
1843 * configure : Rebuild.
1844
1845Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1846
1847 * configure: Regenerated to track ../common/aclocal.m4 changes.
1848
1849Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1850
1851 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1852
1853Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1854
1855 * configure: Regenerated to track ../common/aclocal.m4 changes.
1856 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1857
1858Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * configure: Regenerated to track ../common/aclocal.m4 changes.
1861
1862Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * interp.c (Max, Min): Comment out functions. Not yet used.
1865
1866Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1867
1868 * configure: Regenerated to track ../common/aclocal.m4 changes.
1869
1870Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1871
1872 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1873 configurable settings for stand-alone simulator.
1874
1875 * configure.in: Added X11 search, just in case.
1876
1877 * configure: Regenerated.
1878
1879Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1880
1881 * interp.c (sim_write, sim_read, load_memory, store_memory):
1882 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1883
1884Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1885
1886 * sim-main.h (GETFCC): Return an unsigned value.
1887
1888Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1889
1890 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1891 (DADD): Result destination is RD not RT.
1892
1893Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * sim-main.h (HIACCESS, LOACCESS): Always define.
1896
1897 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1898
1899 * interp.c (sim_info): Delete.
1900
1901Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1902
1903 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1904 (mips_option_handler): New argument `cpu'.
1905 (sim_open): Update call to sim_add_option_table.
1906
1907Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1908
1909 * mips.igen (CxC1): Add tracing.
1910
1911Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1912
1913 * sim-main.h (Max, Min): Declare.
1914
1915 * interp.c (Max, Min): New functions.
1916
1917 * mips.igen (BC1): Add tracing.
1918
1919Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1920
1921 * interp.c Added memory map for stack in vr4100
1922
1923Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1924
1925 * interp.c (load_memory): Add missing "break"'s.
1926
1927Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1928
1929 * interp.c (sim_store_register, sim_fetch_register): Pass in
1930 length parameter. Return -1.
1931
1932Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1933
1934 * interp.c: Added hardware init hook, fixed warnings.
1935
1936Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1937
1938 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1939
1940Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1941
1942 * interp.c (ifetch16): New function.
1943
1944 * sim-main.h (IMEM32): Rename IMEM.
1945 (IMEM16_IMMED): Define.
1946 (IMEM16): Define.
1947 (DELAY_SLOT): Update.
1948
1949 * m16run.c (sim_engine_run): New file.
1950
1951 * m16.igen: All instructions except LB.
1952 (LB): Call do_load_byte.
1953 * mips.igen (do_load_byte): New function.
1954 (LB): Call do_load_byte.
1955
1956 * mips.igen: Move spec for insn bit size and high bit from here.
1957 * Makefile.in (tmp-igen, tmp-m16): To here.
1958
1959 * m16.dc: New file, decode mips16 instructions.
1960
1961 * Makefile.in (SIM_NO_ALL): Define.
1962 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1963
1964Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
1965
1966 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1967 point unit to 32 bit registers.
1968 * configure: Re-generate.
1969
1970Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1971
1972 * configure.in (sim_use_gen): Make IGEN the default simulator
1973 generator for generic 32 and 64 bit mips targets.
1974 * configure: Re-generate.
1975
1976Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1977
1978 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1979 bitsize.
1980
1981 * interp.c (sim_fetch_register, sim_store_register): Read/write
1982 FGR from correct location.
1983 (sim_open): Set size of FGR's according to
1984 WITH_TARGET_FLOATING_POINT_BITSIZE.
1985
1986 * sim-main.h (FGR): Store floating point registers in a separate
1987 array.
1988
1989Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
1990
1991 * configure: Regenerated to track ../common/aclocal.m4 changes.
1992
1993Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1994
1995 * interp.c (ColdReset): Call PENDING_INVALIDATE.
1996
1997 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1998
1999 * interp.c (pending_tick): New function. Deliver pending writes.
2000
2001 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2002 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2003 it can handle mixed sized quantites and single bits.
2004
2005Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2006
2007 * interp.c (oengine.h): Do not include when building with IGEN.
2008 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2009 (sim_info): Ditto for PROCESSOR_64BIT.
2010 (sim_monitor): Replace ut_reg with unsigned_word.
2011 (*): Ditto for t_reg.
2012 (LOADDRMASK): Define.
2013 (sim_open): Remove defunct check that host FP is IEEE compliant,
2014 using software to emulate floating point.
2015 (value_fpr, ...): Always compile, was conditional on HASFPU.
2016
2017Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2018
2019 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2020 size.
2021
2022 * interp.c (SD, CPU): Define.
2023 (mips_option_handler): Set flags in each CPU.
2024 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2025 (sim_close): Do not clear STATE, deleted anyway.
2026 (sim_write, sim_read): Assume CPU zero's vm should be used for
2027 data transfers.
2028 (sim_create_inferior): Set the PC for all processors.
2029 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2030 argument.
2031 (mips16_entry): Pass correct nr of args to store_word, load_word.
2032 (ColdReset): Cold reset all cpu's.
2033 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2034 (sim_monitor, load_memory, store_memory, signal_exception): Use
2035 `CPU' instead of STATE_CPU.
2036
2037
2038 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2039 SD or CPU_.
2040
2041 * sim-main.h (signal_exception): Add sim_cpu arg.
2042 (SignalException*): Pass both SD and CPU to signal_exception.
2043 * interp.c (signal_exception): Update.
2044
2045 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2046 Ditto
2047 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2048 address_translation): Ditto
2049 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2050
2051Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2052
2053 * configure: Regenerated to track ../common/aclocal.m4 changes.
2054
2055Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2056
2057 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2058
2059 * mips.igen (model): Map processor names onto BFD name.
2060
2061 * sim-main.h (CPU_CIA): Delete.
2062 (SET_CIA, GET_CIA): Define
2063
2064Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2065
2066 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2067 regiser.
2068
2069 * configure.in (default_endian): Configure a big-endian simulator
2070 by default.
2071 * configure: Re-generate.
2072
2073Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2074
2075 * configure: Regenerated to track ../common/aclocal.m4 changes.
2076
2077Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2078
2079 * interp.c (sim_monitor): Handle Densan monitor outbyte
2080 and inbyte functions.
2081
20821997-12-29 Felix Lee <flee@cygnus.com>
2083
2084 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2085
2086Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2087
2088 * Makefile.in (tmp-igen): Arrange for $zero to always be
2089 reset to zero after every instruction.
2090
2091Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2092
2093 * configure: Regenerated to track ../common/aclocal.m4 changes.
2094 * config.in: Ditto.
2095
2096Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2097
2098 * mips.igen (MSUB): Fix to work like MADD.
2099 * gencode.c (MSUB): Similarly.
2100
2101Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2102
2103 * configure: Regenerated to track ../common/aclocal.m4 changes.
2104
2105Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2108
2109Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2110
2111 * sim-main.h (sim-fpu.h): Include.
2112
2113 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2114 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2115 using host independant sim_fpu module.
2116
2117Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2118
2119 * interp.c (signal_exception): Report internal errors with SIGABRT
2120 not SIGQUIT.
2121
2122 * sim-main.h (C0_CONFIG): New register.
2123 (signal.h): No longer include.
2124
2125 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2126
2127Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2128
2129 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2130
2131Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * mips.igen: Tag vr5000 instructions.
2134 (ANDI): Was missing mipsIV model, fix assembler syntax.
2135 (do_c_cond_fmt): New function.
2136 (C.cond.fmt): Handle mips I-III which do not support CC field
2137 separatly.
2138 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2139 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2140 in IV3.2 spec.
2141 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2142 vr5000 which saves LO in a GPR separatly.
2143
2144 * configure.in (enable-sim-igen): For vr5000, select vr5000
2145 specific instructions.
2146 * configure: Re-generate.
2147
2148Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2149
2150 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2151
2152 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2153 fmt_uninterpreted_64 bit cases to switch. Convert to
2154 fmt_formatted,
2155
2156 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2157
2158 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2159 as specified in IV3.2 spec.
2160 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2161
2162Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2163
2164 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2165 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2166 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2167 PENDING_FILL versions of instructions. Simplify.
2168 (X): New function.
2169 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2170 instructions.
2171 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2172 a signed value.
2173 (MTHI, MFHI): Disable code checking HI-LO.
2174
2175 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2176 global.
2177 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2178
2179Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * gencode.c (build_mips16_operands): Replace IPC with cia.
2182
2183 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2184 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2185 IPC to `cia'.
2186 (UndefinedResult): Replace function with macro/function
2187 combination.
2188 (sim_engine_run): Don't save PC in IPC.
2189
2190 * sim-main.h (IPC): Delete.
2191
2192
2193 * interp.c (signal_exception, store_word, load_word,
2194 address_translation, load_memory, store_memory, cache_op,
2195 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2196 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2197 current instruction address - cia - argument.
2198 (sim_read, sim_write): Call address_translation directly.
2199 (sim_engine_run): Rename variable vaddr to cia.
2200 (signal_exception): Pass cia to sim_monitor
2201
2202 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2203 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2204 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2205
2206 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2207 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2208 SIM_ASSERT.
2209
2210 * interp.c (signal_exception): Pass restart address to
2211 sim_engine_restart.
2212
2213 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2214 idecode.o): Add dependency.
2215
2216 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2217 Delete definitions
2218 (DELAY_SLOT): Update NIA not PC with branch address.
2219 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2220
2221 * mips.igen: Use CIA not PC in branch calculations.
2222 (illegal): Call SignalException.
2223 (BEQ, ADDIU): Fix assembler.
2224
2225Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2226
2227 * m16.igen (JALX): Was missing.
2228
2229 * configure.in (enable-sim-igen): New configuration option.
2230 * configure: Re-generate.
2231
2232 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2233
2234 * interp.c (load_memory, store_memory): Delete parameter RAW.
2235 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2236 bypassing {load,store}_memory.
2237
2238 * sim-main.h (ByteSwapMem): Delete definition.
2239
2240 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2241
2242 * interp.c (sim_do_command, sim_commands): Delete mips specific
2243 commands. Handled by module sim-options.
2244
2245 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2246 (WITH_MODULO_MEMORY): Define.
2247
2248 * interp.c (sim_info): Delete code printing memory size.
2249
2250 * interp.c (mips_size): Nee sim_size, delete function.
2251 (power2): Delete.
2252 (monitor, monitor_base, monitor_size): Delete global variables.
2253 (sim_open, sim_close): Delete code creating monitor and other
2254 memory regions. Use sim-memopts module, via sim_do_commandf, to
2255 manage memory regions.
2256 (load_memory, store_memory): Use sim-core for memory model.
2257
2258 * interp.c (address_translation): Delete all memory map code
2259 except line forcing 32 bit addresses.
2260
2261Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2262
2263 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2264 trace options.
2265
2266 * interp.c (logfh, logfile): Delete globals.
2267 (sim_open, sim_close): Delete code opening & closing log file.
2268 (mips_option_handler): Delete -l and -n options.
2269 (OPTION mips_options): Ditto.
2270
2271 * interp.c (OPTION mips_options): Rename option trace to dinero.
2272 (mips_option_handler): Update.
2273
2274Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2275
2276 * interp.c (fetch_str): New function.
2277 (sim_monitor): Rewrite using sim_read & sim_write.
2278 (sim_open): Check magic number.
2279 (sim_open): Write monitor vectors into memory using sim_write.
2280 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2281 (sim_read, sim_write): Simplify - transfer data one byte at a
2282 time.
2283 (load_memory, store_memory): Clarify meaning of parameter RAW.
2284
2285 * sim-main.h (isHOST): Defete definition.
2286 (isTARGET): Mark as depreciated.
2287 (address_translation): Delete parameter HOST.
2288
2289 * interp.c (address_translation): Delete parameter HOST.
2290
2291Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2292
2293 * mips.igen:
2294
2295 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2296 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2297
2298Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2299
2300 * mips.igen: Add model filter field to records.
2301
2302Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2303
2304 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2305
2306 interp.c (sim_engine_run): Do not compile function sim_engine_run
2307 when WITH_IGEN == 1.
2308
2309 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2310 target architecture.
2311
2312 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2313 igen. Replace with configuration variables sim_igen_flags /
2314 sim_m16_flags.
2315
2316 * m16.igen: New file. Copy mips16 insns here.
2317 * mips.igen: From here.
2318
2319Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2320
2321 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2322 to top.
2323 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2324
2325Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2326
2327 * gencode.c (build_instruction): Follow sim_write's lead in using
2328 BigEndianMem instead of !ByteSwapMem.
2329
2330Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2331
2332 * configure.in (sim_gen): Dependent on target, select type of
2333 generator. Always select old style generator.
2334
2335 configure: Re-generate.
2336
2337 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2338 targets.
2339 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2340 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2341 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2342 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2343 SIM_@sim_gen@_*, set by autoconf.
2344
2345Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2346
2347 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2348
2349 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2350 CURRENT_FLOATING_POINT instead.
2351
2352 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2353 (address_translation): Raise exception InstructionFetch when
2354 translation fails and isINSTRUCTION.
2355
2356 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2357 sim_engine_run): Change type of of vaddr and paddr to
2358 address_word.
2359 (address_translation, prefetch, load_memory, store_memory,
2360 cache_op): Change type of vAddr and pAddr to address_word.
2361
2362 * gencode.c (build_instruction): Change type of vaddr and paddr to
2363 address_word.
2364
2365Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2366
2367 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2368 macro to obtain result of ALU op.
2369
2370Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2371
2372 * interp.c (sim_info): Call profile_print.
2373
2374Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2375
2376 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2377
2378 * sim-main.h (WITH_PROFILE): Do not define, defined in
2379 common/sim-config.h. Use sim-profile module.
2380 (simPROFILE): Delete defintion.
2381
2382 * interp.c (PROFILE): Delete definition.
2383 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2384 (sim_close): Delete code writing profile histogram.
2385 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2386 Delete.
2387 (sim_engine_run): Delete code profiling the PC.
2388
2389Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2390
2391 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2392
2393 * interp.c (sim_monitor): Make register pointers of type
2394 unsigned_word*.
2395
2396 * sim-main.h: Make registers of type unsigned_word not
2397 signed_word.
2398
2399Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2400
2401 * interp.c (sync_operation): Rename from SyncOperation, make
2402 global, add SD argument.
2403 (prefetch): Rename from Prefetch, make global, add SD argument.
2404 (decode_coproc): Make global.
2405
2406 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2407
2408 * gencode.c (build_instruction): Generate DecodeCoproc not
2409 decode_coproc calls.
2410
2411 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2412 (SizeFGR): Move to sim-main.h
2413 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2414 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2415 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2416 sim-main.h.
2417 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2418 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2419 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2420 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2421 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2422 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2423
2424 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2425 exception.
2426 (sim-alu.h): Include.
2427 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2428 (sim_cia): Typedef to instruction_address.
2429
2430Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2431
2432 * Makefile.in (interp.o): Rename generated file engine.c to
2433 oengine.c.
2434
2435 * interp.c: Update.
2436
2437Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2438
2439 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2440
2441Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2442
2443 * gencode.c (build_instruction): For "FPSQRT", output correct
2444 number of arguments to Recip.
2445
2446Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2447
2448 * Makefile.in (interp.o): Depends on sim-main.h
2449
2450 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2451
2452 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2453 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2454 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2455 STATE, DSSTATE): Define
2456 (GPR, FGRIDX, ..): Define.
2457
2458 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2459 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2460 (GPR, FGRIDX, ...): Delete macros.
2461
2462 * interp.c: Update names to match defines from sim-main.h
2463
2464Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2465
2466 * interp.c (sim_monitor): Add SD argument.
2467 (sim_warning): Delete. Replace calls with calls to
2468 sim_io_eprintf.
2469 (sim_error): Delete. Replace calls with sim_io_error.
2470 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2471 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2472 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2473 argument.
2474 (mips_size): Rename from sim_size. Add SD argument.
2475
2476 * interp.c (simulator): Delete global variable.
2477 (callback): Delete global variable.
2478 (mips_option_handler, sim_open, sim_write, sim_read,
2479 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2480 sim_size,sim_monitor): Use sim_io_* not callback->*.
2481 (sim_open): ZALLOC simulator struct.
2482 (PROFILE): Do not define.
2483
2484Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2485
2486 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2487 support.h with corresponding code.
2488
2489 * sim-main.h (word64, uword64), support.h: Move definition to
2490 sim-main.h.
2491 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2492
2493 * support.h: Delete
2494 * Makefile.in: Update dependencies
2495 * interp.c: Do not include.
2496
2497Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * interp.c (address_translation, load_memory, store_memory,
2500 cache_op): Rename to from AddressTranslation et.al., make global,
2501 add SD argument
2502
2503 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2504 CacheOp): Define.
2505
2506 * interp.c (SignalException): Rename to signal_exception, make
2507 global.
2508
2509 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2510
2511 * sim-main.h (SignalException, SignalExceptionInterrupt,
2512 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2513 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2514 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2515 Define.
2516
2517 * interp.c, support.h: Use.
2518
2519Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2520
2521 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2522 to value_fpr / store_fpr. Add SD argument.
2523 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2524 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2525
2526 * sim-main.h (ValueFPR, StoreFPR): Define.
2527
2528Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2529
2530 * interp.c (sim_engine_run): Check consistency between configure
2531 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2532 and HASFPU.
2533
2534 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2535 (mips_fpu): Configure WITH_FLOATING_POINT.
2536 (mips_endian): Configure WITH_TARGET_ENDIAN.
2537 * configure: Update.
2538
2539Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2540
2541 * configure: Regenerated to track ../common/aclocal.m4 changes.
2542
2543Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2544
2545 * configure: Regenerated.
2546
2547Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2548
2549 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2550
2551Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2552
2553 * gencode.c (print_igen_insn_models): Assume certain architectures
2554 include all mips* instructions.
2555 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2556 instruction.
2557
2558 * Makefile.in (tmp.igen): Add target. Generate igen input from
2559 gencode file.
2560
2561 * gencode.c (FEATURE_IGEN): Define.
2562 (main): Add --igen option. Generate output in igen format.
2563 (process_instructions): Format output according to igen option.
2564 (print_igen_insn_format): New function.
2565 (print_igen_insn_models): New function.
2566 (process_instructions): Only issue warnings and ignore
2567 instructions when no FEATURE_IGEN.
2568
2569Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2570
2571 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2572 MIPS targets.
2573
2574Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2575
2576 * configure: Regenerated to track ../common/aclocal.m4 changes.
2577
2578Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2579
2580 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2581 SIM_RESERVED_BITS): Delete, moved to common.
2582 (SIM_EXTRA_CFLAGS): Update.
2583
2584Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2585
2586 * configure.in: Configure non-strict memory alignment.
2587 * configure: Regenerated to track ../common/aclocal.m4 changes.
2588
2589Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2590
2591 * configure: Regenerated to track ../common/aclocal.m4 changes.
2592
2593Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2594
2595 * gencode.c (SDBBP,DERET): Added (3900) insns.
2596 (RFE): Turn on for 3900.
2597 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2598 (dsstate): Made global.
2599 (SUBTARGET_R3900): Added.
2600 (CANCELDELAYSLOT): New.
2601 (SignalException): Ignore SystemCall rather than ignore and
2602 terminate. Add DebugBreakPoint handling.
2603 (decode_coproc): New insns RFE, DERET; and new registers Debug
2604 and DEPC protected by SUBTARGET_R3900.
2605 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2606 bits explicitly.
2607 * Makefile.in,configure.in: Add mips subtarget option.
2608 * configure: Update.
2609
2610Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2611
2612 * gencode.c: Add r3900 (tx39).
2613
2614
2615Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2616
2617 * gencode.c (build_instruction): Don't need to subtract 4 for
2618 JALR, just 2.
2619
2620Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2621
2622 * interp.c: Correct some HASFPU problems.
2623
2624Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2625
2626 * configure: Regenerated to track ../common/aclocal.m4 changes.
2627
2628Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2629
2630 * interp.c (mips_options): Fix samples option short form, should
2631 be `x'.
2632
2633Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2634
2635 * interp.c (sim_info): Enable info code. Was just returning.
2636
2637Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2638
2639 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2640 MFC0.
2641
2642Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2643
2644 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2645 constants.
2646 (build_instruction): Ditto for LL.
2647
2648Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2649
2650 * configure: Regenerated to track ../common/aclocal.m4 changes.
2651
2652Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2653
2654 * configure: Regenerated to track ../common/aclocal.m4 changes.
2655 * config.in: Ditto.
2656
2657Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * interp.c (sim_open): Add call to sim_analyze_program, update
2660 call to sim_config.
2661
2662Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2663
2664 * interp.c (sim_kill): Delete.
2665 (sim_create_inferior): Add ABFD argument. Set PC from same.
2666 (sim_load): Move code initializing trap handlers from here.
2667 (sim_open): To here.
2668 (sim_load): Delete, use sim-hload.c.
2669
2670 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2671
2672Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2673
2674 * configure: Regenerated to track ../common/aclocal.m4 changes.
2675 * config.in: Ditto.
2676
2677Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2678
2679 * interp.c (sim_open): Add ABFD argument.
2680 (sim_load): Move call to sim_config from here.
2681 (sim_open): To here. Check return status.
2682
2683Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2684
2685 * gencode.c (build_instruction): Two arg MADD should
2686 not assign result to $0.
2687
2688Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2689
2690 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2691 * sim/mips/configure.in: Regenerate.
2692
2693Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2694
2695 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2696 signed8, unsigned8 et.al. types.
2697
2698 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2699 hosts when selecting subreg.
2700
2701Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2702
2703 * interp.c (sim_engine_run): Reset the ZERO register to zero
2704 regardless of FEATURE_WARN_ZERO.
2705 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2706
2707Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2708
2709 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2710 (SignalException): For BreakPoints ignore any mode bits and just
2711 save the PC.
2712 (SignalException): Always set the CAUSE register.
2713
2714Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2715
2716 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2717 exception has been taken.
2718
2719 * interp.c: Implement the ERET and mt/f sr instructions.
2720
2721Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2722
2723 * interp.c (SignalException): Don't bother restarting an
2724 interrupt.
2725
2726Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2727
2728 * interp.c (SignalException): Really take an interrupt.
2729 (interrupt_event): Only deliver interrupts when enabled.
2730
2731Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2732
2733 * interp.c (sim_info): Only print info when verbose.
2734 (sim_info) Use sim_io_printf for output.
2735
2736Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2737
2738 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2739 mips architectures.
2740
2741Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2742
2743 * interp.c (sim_do_command): Check for common commands if a
2744 simulator specific command fails.
2745
2746Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2747
2748 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2749 and simBE when DEBUG is defined.
2750
2751Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2752
2753 * interp.c (interrupt_event): New function. Pass exception event
2754 onto exception handler.
2755
2756 * configure.in: Check for stdlib.h.
2757 * configure: Regenerate.
2758
2759 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2760 variable declaration.
2761 (build_instruction): Initialize memval1.
2762 (build_instruction): Add UNUSED attribute to byte, bigend,
2763 reverse.
2764 (build_operands): Ditto.
2765
2766 * interp.c: Fix GCC warnings.
2767 (sim_get_quit_code): Delete.
2768
2769 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2770 * Makefile.in: Ditto.
2771 * configure: Re-generate.
2772
2773 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2774
2775Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2776
2777 * interp.c (mips_option_handler): New function parse argumes using
2778 sim-options.
2779 (myname): Replace with STATE_MY_NAME.
2780 (sim_open): Delete check for host endianness - performed by
2781 sim_config.
2782 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2783 (sim_open): Move much of the initialization from here.
2784 (sim_load): To here. After the image has been loaded and
2785 endianness set.
2786 (sim_open): Move ColdReset from here.
2787 (sim_create_inferior): To here.
2788 (sim_open): Make FP check less dependant on host endianness.
2789
2790 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2791 run.
2792 * interp.c (sim_set_callbacks): Delete.
2793
2794 * interp.c (membank, membank_base, membank_size): Replace with
2795 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2796 (sim_open): Remove call to callback->init. gdb/run do this.
2797
2798 * interp.c: Update
2799
2800 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2801
2802 * interp.c (big_endian_p): Delete, replaced by
2803 current_target_byte_order.
2804
2805Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2806
2807 * interp.c (host_read_long, host_read_word, host_swap_word,
2808 host_swap_long): Delete. Using common sim-endian.
2809 (sim_fetch_register, sim_store_register): Use H2T.
2810 (pipeline_ticks): Delete. Handled by sim-events.
2811 (sim_info): Update.
2812 (sim_engine_run): Update.
2813
2814Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2815
2816 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2817 reason from here.
2818 (SignalException): To here. Signal using sim_engine_halt.
2819 (sim_stop_reason): Delete, moved to common.
2820
2821Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2822
2823 * interp.c (sim_open): Add callback argument.
2824 (sim_set_callbacks): Delete SIM_DESC argument.
2825 (sim_size): Ditto.
2826
2827Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2828
2829 * Makefile.in (SIM_OBJS): Add common modules.
2830
2831 * interp.c (sim_set_callbacks): Also set SD callback.
2832 (set_endianness, xfer_*, swap_*): Delete.
2833 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2834 Change to functions using sim-endian macros.
2835 (control_c, sim_stop): Delete, use common version.
2836 (simulate): Convert into.
2837 (sim_engine_run): This function.
2838 (sim_resume): Delete.
2839
2840 * interp.c (simulation): New variable - the simulator object.
2841 (sim_kind): Delete global - merged into simulation.
2842 (sim_load): Cleanup. Move PC assignment from here.
2843 (sim_create_inferior): To here.
2844
2845 * sim-main.h: New file.
2846 * interp.c (sim-main.h): Include.
2847
2848Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2849
2850 * configure: Regenerated to track ../common/aclocal.m4 changes.
2851
2852Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2853
2854 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2855
2856Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2857
2858 * gencode.c (build_instruction): DIV instructions: check
2859 for division by zero and integer overflow before using
2860 host's division operation.
2861
2862Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2863
2864 * Makefile.in (SIM_OBJS): Add sim-load.o.
2865 * interp.c: #include bfd.h.
2866 (target_byte_order): Delete.
2867 (sim_kind, myname, big_endian_p): New static locals.
2868 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2869 after argument parsing. Recognize -E arg, set endianness accordingly.
2870 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2871 load file into simulator. Set PC from bfd.
2872 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2873 (set_endianness): Use big_endian_p instead of target_byte_order.
2874
2875Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2876
2877 * interp.c (sim_size): Delete prototype - conflicts with
2878 definition in remote-sim.h. Correct definition.
2879
2880Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2881
2882 * configure: Regenerated to track ../common/aclocal.m4 changes.
2883 * config.in: Ditto.
2884
2885Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2886
2887 * interp.c (sim_open): New arg `kind'.
2888
2889 * configure: Regenerated to track ../common/aclocal.m4 changes.
2890
2891Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2892
2893 * configure: Regenerated to track ../common/aclocal.m4 changes.
2894
2895Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2896
2897 * interp.c (sim_open): Set optind to 0 before calling getopt.
2898
2899Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2900
2901 * configure: Regenerated to track ../common/aclocal.m4 changes.
2902
2903Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2904
2905 * interp.c : Replace uses of pr_addr with pr_uword64
2906 where the bit length is always 64 independent of SIM_ADDR.
2907 (pr_uword64) : added.
2908
2909Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2910
2911 * configure: Re-generate.
2912
2913Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2914
2915 * configure: Regenerate to track ../common/aclocal.m4 changes.
2916
2917Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2918
2919 * interp.c (sim_open): New SIM_DESC result. Argument is now
2920 in argv form.
2921 (other sim_*): New SIM_DESC argument.
2922
2923Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2924
2925 * interp.c: Fix printing of addresses for non-64-bit targets.
2926 (pr_addr): Add function to print address based on size.
2927
2928Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2929
2930 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2931
2932Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2933
2934 * gencode.c (build_mips16_operands): Correct computation of base
2935 address for extended PC relative instruction.
2936
2937Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2938
2939 * interp.c (mips16_entry): Add support for floating point cases.
2940 (SignalException): Pass floating point cases to mips16_entry.
2941 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2942 registers.
2943 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2944 or fmt_word.
2945 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2946 and then set the state to fmt_uninterpreted.
2947 (COP_SW): Temporarily set the state to fmt_word while calling
2948 ValueFPR.
2949
2950Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2951
2952 * gencode.c (build_instruction): The high order may be set in the
2953 comparison flags at any ISA level, not just ISA 4.
2954
2955Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2956
2957 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2958 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2959 * configure.in: sinclude ../common/aclocal.m4.
2960 * configure: Regenerated.
2961
2962Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2963
2964 * configure: Rebuild after change to aclocal.m4.
2965
2966Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2967
2968 * configure configure.in Makefile.in: Update to new configure
2969 scheme which is more compatible with WinGDB builds.
2970 * configure.in: Improve comment on how to run autoconf.
2971 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2972 * Makefile.in: Use autoconf substitution to install common
2973 makefile fragment.
2974
2975Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2976
2977 * gencode.c (build_instruction): Use BigEndianCPU instead of
2978 ByteSwapMem.
2979
2980Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2981
2982 * interp.c (sim_monitor): Make output to stdout visible in
2983 wingdb's I/O log window.
2984
2985Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2986
2987 * support.h: Undo previous change to SIGTRAP
2988 and SIGQUIT values.
2989
2990Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2991
2992 * interp.c (store_word, load_word): New static functions.
2993 (mips16_entry): New static function.
2994 (SignalException): Look for mips16 entry and exit instructions.
2995 (simulate): Use the correct index when setting fpr_state after
2996 doing a pending move.
2997
2998Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2999
3000 * interp.c: Fix byte-swapping code throughout to work on
3001 both little- and big-endian hosts.
3002
3003Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3004
3005 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3006 with gdb/config/i386/xm-windows.h.
3007
3008Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3009
3010 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3011 that messes up arithmetic shifts.
3012
3013Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3014
3015 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3016 SIGTRAP and SIGQUIT for _WIN32.
3017
3018Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3019
3020 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3021 force a 64 bit multiplication.
3022 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3023 destination register is 0, since that is the default mips16 nop
3024 instruction.
3025
3026Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3027
3028 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3029 (build_endian_shift): Don't check proc64.
3030 (build_instruction): Always set memval to uword64. Cast op2 to
3031 uword64 when shifting it left in memory instructions. Always use
3032 the same code for stores--don't special case proc64.
3033
3034 * gencode.c (build_mips16_operands): Fix base PC value for PC
3035 relative operands.
3036 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3037 jal instruction.
3038 * interp.c (simJALDELAYSLOT): Define.
3039 (JALDELAYSLOT): Define.
3040 (INDELAYSLOT, INJALDELAYSLOT): Define.
3041 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3042
3043Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3044
3045 * interp.c (sim_open): add flush_cache as a PMON routine
3046 (sim_monitor): handle flush_cache by ignoring it
3047
3048Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3049
3050 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3051 BigEndianMem.
3052 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3053 (BigEndianMem): Rename to ByteSwapMem and change sense.
3054 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3055 BigEndianMem references to !ByteSwapMem.
3056 (set_endianness): New function, with prototype.
3057 (sim_open): Call set_endianness.
3058 (sim_info): Use simBE instead of BigEndianMem.
3059 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3060 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3061 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3062 ifdefs, keeping the prototype declaration.
3063 (swap_word): Rewrite correctly.
3064 (ColdReset): Delete references to CONFIG. Delete endianness related
3065 code; moved to set_endianness.
3066
3067Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3068
3069 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3070 * interp.c (CHECKHILO): Define away.
3071 (simSIGINT): New macro.
3072 (membank_size): Increase from 1MB to 2MB.
3073 (control_c): New function.
3074 (sim_resume): Rename parameter signal to signal_number. Add local
3075 variable prev. Call signal before and after simulate.
3076 (sim_stop_reason): Add simSIGINT support.
3077 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3078 functions always.
3079 (sim_warning): Delete call to SignalException. Do call printf_filtered
3080 if logfh is NULL.
3081 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3082 a call to sim_warning.
3083
3084Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3085
3086 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3087 16 bit instructions.
3088
3089Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3090
3091 Add support for mips16 (16 bit MIPS implementation):
3092 * gencode.c (inst_type): Add mips16 instruction encoding types.
3093 (GETDATASIZEINSN): Define.
3094 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3095 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3096 mtlo.
3097 (MIPS16_DECODE): New table, for mips16 instructions.
3098 (bitmap_val): New static function.
3099 (struct mips16_op): Define.
3100 (mips16_op_table): New table, for mips16 operands.
3101 (build_mips16_operands): New static function.
3102 (process_instructions): If PC is odd, decode a mips16
3103 instruction. Break out instruction handling into new
3104 build_instruction function.
3105 (build_instruction): New static function, broken out of
3106 process_instructions. Check modifiers rather than flags for SHIFT
3107 bit count and m[ft]{hi,lo} direction.
3108 (usage): Pass program name to fprintf.
3109 (main): Remove unused variable this_option_optind. Change
3110 ``*loptarg++'' to ``loptarg++''.
3111 (my_strtoul): Parenthesize && within ||.
3112 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3113 (simulate): If PC is odd, fetch a 16 bit instruction, and
3114 increment PC by 2 rather than 4.
3115 * configure.in: Add case for mips16*-*-*.
3116 * configure: Rebuild.
3117
3118Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3119
3120 * interp.c: Allow -t to enable tracing in standalone simulator.
3121 Fix garbage output in trace file and error messages.
3122
3123Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3124
3125 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3126 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3127 * configure.in: Simplify using macros in ../common/aclocal.m4.
3128 * configure: Regenerated.
3129 * tconfig.in: New file.
3130
3131Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3132
3133 * interp.c: Fix bugs in 64-bit port.
3134 Use ansi function declarations for msvc compiler.
3135 Initialize and test file pointer in trace code.
3136 Prevent duplicate definition of LAST_EMED_REGNUM.
3137
3138Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3139
3140 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3141
3142Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3143
3144 * interp.c (SignalException): Check for explicit terminating
3145 breakpoint value.
3146 * gencode.c: Pass instruction value through SignalException()
3147 calls for Trap, Breakpoint and Syscall.
3148
3149Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3150
3151 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3152 only used on those hosts that provide it.
3153 * configure.in: Add sqrt() to list of functions to be checked for.
3154 * config.in: Re-generated.
3155 * configure: Re-generated.
3156
3157Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3158
3159 * gencode.c (process_instructions): Call build_endian_shift when
3160 expanding STORE RIGHT, to fix swr.
3161 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3162 clear the high bits.
3163 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3164 Fix float to int conversions to produce signed values.
3165
3166Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3167
3168 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3169 (process_instructions): Correct handling of nor instruction.
3170 Correct shift count for 32 bit shift instructions. Correct sign
3171 extension for arithmetic shifts to not shift the number of bits in
3172 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3173 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3174 Fix madd.
3175 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3176 It's OK to have a mult follow a mult. What's not OK is to have a
3177 mult follow an mfhi.
3178 (Convert): Comment out incorrect rounding code.
3179
3180Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3181
3182 * interp.c (sim_monitor): Improved monitor printf
3183 simulation. Tidied up simulator warnings, and added "--log" option
3184 for directing warning message output.
3185 * gencode.c: Use sim_warning() rather than WARNING macro.
3186
3187Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3188
3189 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3190 getopt1.o, rather than on gencode.c. Link objects together.
3191 Don't link against -liberty.
3192 (gencode.o, getopt.o, getopt1.o): New targets.
3193 * gencode.c: Include <ctype.h> and "ansidecl.h".
3194 (AND): Undefine after including "ansidecl.h".
3195 (ULONG_MAX): Define if not defined.
3196 (OP_*): Don't define macros; now defined in opcode/mips.h.
3197 (main): Call my_strtoul rather than strtoul.
3198 (my_strtoul): New static function.
3199
3200Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3201
3202 * gencode.c (process_instructions): Generate word64 and uword64
3203 instead of `long long' and `unsigned long long' data types.
3204 * interp.c: #include sysdep.h to get signals, and define default
3205 for SIGBUS.
3206 * (Convert): Work around for Visual-C++ compiler bug with type
3207 conversion.
3208 * support.h: Make things compile under Visual-C++ by using
3209 __int64 instead of `long long'. Change many refs to long long
3210 into word64/uword64 typedefs.
3211
3212Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3213
3214 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3215 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3216 (docdir): Removed.
3217 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3218 (AC_PROG_INSTALL): Added.
3219 (AC_PROG_CC): Moved to before configure.host call.
3220 * configure: Rebuilt.
3221
3222Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3223
3224 * configure.in: Define @SIMCONF@ depending on mips target.
3225 * configure: Rebuild.
3226 * Makefile.in (run): Add @SIMCONF@ to control simulator
3227 construction.
3228 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3229 * interp.c: Remove some debugging, provide more detailed error
3230 messages, update memory accesses to use LOADDRMASK.
3231
3232Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3233
3234 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3235 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3236 stamp-h.
3237 * configure: Rebuild.
3238 * config.in: New file, generated by autoheader.
3239 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3240 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3241 HAVE_ANINT and HAVE_AINT, as appropriate.
3242 * Makefile.in (run): Use @LIBS@ rather than -lm.
3243 (interp.o): Depend upon config.h.
3244 (Makefile): Just rebuild Makefile.
3245 (clean): Remove stamp-h.
3246 (mostlyclean): Make the same as clean, not as distclean.
3247 (config.h, stamp-h): New targets.
3248
3249Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3250
3251 * interp.c (ColdReset): Fix boolean test. Make all simulator
3252 globals static.
3253
3254Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3255
3256 * interp.c (xfer_direct_word, xfer_direct_long,
3257 swap_direct_word, swap_direct_long, xfer_big_word,
3258 xfer_big_long, xfer_little_word, xfer_little_long,
3259 swap_word,swap_long): Added.
3260 * interp.c (ColdReset): Provide function indirection to
3261 host<->simulated_target transfer routines.
3262 * interp.c (sim_store_register, sim_fetch_register): Updated to
3263 make use of indirected transfer routines.
3264
3265Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3266
3267 * gencode.c (process_instructions): Ensure FP ABS instruction
3268 recognised.
3269 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3270 system call support.
3271
3272Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3273
3274 * interp.c (sim_do_command): Complain if callback structure not
3275 initialised.
3276
3277Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3278
3279 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3280 support for Sun hosts.
3281 * Makefile.in (gencode): Ensure the host compiler and libraries
3282 used for cross-hosted build.
3283
3284Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3285
3286 * interp.c, gencode.c: Some more (TODO) tidying.
3287
3288Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3289
3290 * gencode.c, interp.c: Replaced explicit long long references with
3291 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3292 * support.h (SET64LO, SET64HI): Macros added.
3293
3294Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3295
3296 * configure: Regenerate with autoconf 2.7.
3297
3298Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3299
3300 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3301 * support.h: Remove superfluous "1" from #if.
3302 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3303
3304Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3305
3306 * interp.c (StoreFPR): Control UndefinedResult() call on
3307 WARN_RESULT manifest.
3308
3309Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3310
3311 * gencode.c: Tidied instruction decoding, and added FP instruction
3312 support.
3313
3314 * interp.c: Added dineroIII, and BSD profiling support. Also
3315 run-time FP handling.
3316
3317Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3318
3319 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3320 gencode.c, interp.c, support.h: created.
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