]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/mmc.c
mmc: incomplete test to switch to high-capacity group size definitions
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF
8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF
14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF
20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK
25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK
38 else
39 wp = 0;
40 }
d23d8d7e
NK
41
42 return wp;
43}
44
cee9ab7c
JH
45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB
47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR
55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR
61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR
88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF
106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR
109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR
112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR
120
121 do {
122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK
123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK
130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK
133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9
RR
137
138 udelay(1000);
139
5d4fc8d9
RR
140 } while (timeout--);
141
5db2fe3a
RR
142#ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
145#endif
5b0c942f 146 if (timeout <= 0) {
56196826 147#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 148 printf("Timeout waiting card ready\n");
56196826 149#endif
5d4fc8d9
RR
150 return TIMEOUT;
151 }
6b2221b0
AG
152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
153 return SWITCH_ERR;
5d4fc8d9
RR
154
155 return 0;
156}
157
da61fa5f 158int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF
159{
160 struct mmc_cmd cmd;
161
786e8f81 162 if (mmc->ddr_mode)
d22e3d46
JC
163 return 0;
164
272cc70b
AF
165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
167 cmd.cmdarg = len;
272cc70b
AF
168
169 return mmc_send_cmd(mmc, &cmd, NULL);
170}
171
172struct mmc *find_mmc_device(int dev_num)
173{
174 struct mmc *m;
175 struct list_head *entry;
176
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
179
180 if (m->block_dev.dev == dev_num)
181 return m;
182 }
183
56196826 184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 185 printf("MMC Device %d not found\n", dev_num);
56196826 186#endif
272cc70b
AF
187
188 return NULL;
189}
190
ff8fef56 191static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 192 lbaint_t blkcnt)
272cc70b
AF
193{
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
4a1a06bc
AS
197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF
201
202 if (mmc->high_capacity)
4a1a06bc 203 cmd.cmdarg = start;
272cc70b 204 else
4a1a06bc 205 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF
206
207 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF
208
209 data.dest = dst;
4a1a06bc 210 data.blocks = blkcnt;
272cc70b
AF
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
4a1a06bc
AS
214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
272cc70b 216
4a1a06bc
AS
217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 222#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 223 printf("mmc fail to send stop cmd\n");
56196826 224#endif
4a1a06bc
AS
225 return 0;
226 }
272cc70b
AF
227 }
228
4a1a06bc 229 return blkcnt;
272cc70b
AF
230}
231
ff8fef56 232static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 233{
4a1a06bc
AS
234 lbaint_t cur, blocks_todo = blkcnt;
235
236 if (blkcnt == 0)
237 return 0;
272cc70b 238
4a1a06bc 239 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF
240 if (!mmc)
241 return 0;
242
d2bf29e3 243 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 244#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 246 start + blkcnt, mmc->block_dev.lba);
56196826 247#endif
d2bf29e3
LW
248 return 0;
249 }
272cc70b 250
4a1a06bc 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 252 return 0;
272cc70b 253
4a1a06bc 254 do {
93bfd616
PA
255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF
263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF
268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF
277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF
289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF
298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB
306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 315 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF
316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC
338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF
346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC
353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF
357 int err;
358
e9550449
CLC
359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
93bfd616 364 (mmc->cfg->voltages &
e9550449
CLC
365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
93bfd616 368 if (mmc->cfg->host_caps & MMC_MODE_HC)
e9550449
CLC
369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
750121c3 378static int mmc_send_op_cond(struct mmc *mmc)
e9550449
CLC
379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF
383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC
387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC
401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC
407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF
411 if (err)
412 return err;
e9550449
CLC
413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC
422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF
431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF
434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF
440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF
453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF
462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR
464 int timeout = 1000;
465 int ret;
272cc70b
AF
466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR
470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR
473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK
476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR
478
479 return ret;
480
272cc70b
AF
481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF
486 char cardtype;
487 int err;
488
786e8f81 489 mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 490
d52ebf10
TC
491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF
494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
272cc70b
AF
498 err = mmc_send_ext_csd(mmc, ext_csd);
499
500 if (err)
501 return err;
502
0560db18 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF
504
505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
506
507 if (err)
6b2221b0 508 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF
509
510 /* Now check to see that it worked */
511 err = mmc_send_ext_csd(mmc, ext_csd);
512
513 if (err)
514 return err;
515
516 /* No high-speed support */
0560db18 517 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF
518 return 0;
519
520 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 521 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 522 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 523 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 524 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 525 } else {
272cc70b 526 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 527 }
272cc70b
AF
528
529 return 0;
530}
531
f866a46d
SW
532static int mmc_set_capacity(struct mmc *mmc, int part_num)
533{
534 switch (part_num) {
535 case 0:
536 mmc->capacity = mmc->capacity_user;
537 break;
538 case 1:
539 case 2:
540 mmc->capacity = mmc->capacity_boot;
541 break;
542 case 3:
543 mmc->capacity = mmc->capacity_rpmb;
544 break;
545 case 4:
546 case 5:
547 case 6:
548 case 7:
549 mmc->capacity = mmc->capacity_gp[part_num - 4];
550 break;
551 default:
552 return -1;
553 }
554
555 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
556
557 return 0;
558}
559
d2356284
SW
560int mmc_select_hwpart(int dev_num, int hwpart)
561{
562 struct mmc *mmc = find_mmc_device(dev_num);
563 int ret;
564
565 if (!mmc)
d4622df3 566 return -ENODEV;
d2356284
SW
567
568 if (mmc->part_num == hwpart)
569 return 0;
570
571 if (mmc->part_config == MMCPART_NOAVAILABLE) {
572 printf("Card doesn't support part_switch\n");
d4622df3 573 return -EMEDIUMTYPE;
d2356284
SW
574 }
575
576 ret = mmc_switch_part(dev_num, hwpart);
577 if (ret)
d4622df3 578 return ret;
d2356284
SW
579
580 mmc->part_num = hwpart;
581
582 return 0;
583}
584
585
bc897b1d
LW
586int mmc_switch_part(int dev_num, unsigned int part_num)
587{
588 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 589 int ret;
bc897b1d
LW
590
591 if (!mmc)
592 return -1;
593
f866a46d
SW
594 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
595 (mmc->part_config & ~PART_ACCESS_MASK)
596 | (part_num & PART_ACCESS_MASK));
f866a46d 597
6dc93e70
PB
598 /*
599 * Set the capacity if the switch succeeded or was intended
600 * to return to representing the raw device.
601 */
602 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
603 ret = mmc_set_capacity(mmc, part_num);
604
605 return ret;
bc897b1d
LW
606}
607
48972d90
TR
608int mmc_getcd(struct mmc *mmc)
609{
610 int cd;
611
612 cd = board_mmc_getcd(mmc);
613
d4e1da4e 614 if (cd < 0) {
93bfd616
PA
615 if (mmc->cfg->ops->getcd)
616 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK
617 else
618 cd = 1;
619 }
48972d90
TR
620
621 return cd;
622}
623
fdbb873e 624static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF
625{
626 struct mmc_cmd cmd;
627 struct mmc_data data;
628
629 /* Switch the frequency */
630 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
631 cmd.resp_type = MMC_RSP_R1;
632 cmd.cmdarg = (mode << 31) | 0xffffff;
633 cmd.cmdarg &= ~(0xf << (group * 4));
634 cmd.cmdarg |= value << (group * 4);
272cc70b
AF
635
636 data.dest = (char *)resp;
637 data.blocksize = 64;
638 data.blocks = 1;
639 data.flags = MMC_DATA_READ;
640
641 return mmc_send_cmd(mmc, &cmd, &data);
642}
643
644
fdbb873e 645static int sd_change_freq(struct mmc *mmc)
272cc70b
AF
646{
647 int err;
648 struct mmc_cmd cmd;
f781dd38
A
649 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
650 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF
651 struct mmc_data data;
652 int timeout;
653
654 mmc->card_caps = 0;
655
d52ebf10
TC
656 if (mmc_host_is_spi(mmc))
657 return 0;
658
272cc70b
AF
659 /* Read the SCR to find out if this card supports higher speeds */
660 cmd.cmdidx = MMC_CMD_APP_CMD;
661 cmd.resp_type = MMC_RSP_R1;
662 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
663
664 err = mmc_send_cmd(mmc, &cmd, NULL);
665
666 if (err)
667 return err;
668
669 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
670 cmd.resp_type = MMC_RSP_R1;
671 cmd.cmdarg = 0;
272cc70b
AF
672
673 timeout = 3;
674
675retry_scr:
f781dd38 676 data.dest = (char *)scr;
272cc70b
AF
677 data.blocksize = 8;
678 data.blocks = 1;
679 data.flags = MMC_DATA_READ;
680
681 err = mmc_send_cmd(mmc, &cmd, &data);
682
683 if (err) {
684 if (timeout--)
685 goto retry_scr;
686
687 return err;
688 }
689
4e3d89ba
YK
690 mmc->scr[0] = __be32_to_cpu(scr[0]);
691 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF
692
693 switch ((mmc->scr[0] >> 24) & 0xf) {
694 case 0:
695 mmc->version = SD_VERSION_1_0;
696 break;
697 case 1:
698 mmc->version = SD_VERSION_1_10;
699 break;
700 case 2:
701 mmc->version = SD_VERSION_2;
1741c64d
JC
702 if ((mmc->scr[0] >> 15) & 0x1)
703 mmc->version = SD_VERSION_3;
272cc70b
AF
704 break;
705 default:
706 mmc->version = SD_VERSION_1_0;
707 break;
708 }
709
b44c7083
AS
710 if (mmc->scr[0] & SD_DATA_4BIT)
711 mmc->card_caps |= MMC_MODE_4BIT;
712
272cc70b
AF
713 /* Version 1.0 doesn't support switching */
714 if (mmc->version == SD_VERSION_1_0)
715 return 0;
716
717 timeout = 4;
718 while (timeout--) {
719 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 720 (u8 *)switch_status);
272cc70b
AF
721
722 if (err)
723 return err;
724
725 /* The high-speed function is busy. Try again */
4e3d89ba 726 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF
727 break;
728 }
729
272cc70b 730 /* If high-speed isn't supported, we return */
4e3d89ba 731 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF
732 return 0;
733
2c3fbf4c
ML
734 /*
735 * If the host doesn't support SD_HIGHSPEED, do not switch card to
736 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
737 * This can avoid furthur problem when the card runs in different
738 * mode between the host.
739 */
93bfd616
PA
740 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
741 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML
742 return 0;
743
f781dd38 744 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF
745
746 if (err)
747 return err;
748
4e3d89ba 749 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF
750 mmc->card_caps |= MMC_MODE_HS;
751
752 return 0;
753}
754
755/* frequency bases */
756/* divided by 10 to be nice to platforms without floating point */
5f837c2c 757static const int fbase[] = {
272cc70b
AF
758 10000,
759 100000,
760 1000000,
761 10000000,
762};
763
764/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
765 * to platforms without floating point.
766 */
5f837c2c 767static const int multipliers[] = {
272cc70b
AF
768 0, /* reserved */
769 10,
770 12,
771 13,
772 15,
773 20,
774 25,
775 30,
776 35,
777 40,
778 45,
779 50,
780 55,
781 60,
782 70,
783 80,
784};
785
fdbb873e 786static void mmc_set_ios(struct mmc *mmc)
272cc70b 787{
93bfd616
PA
788 if (mmc->cfg->ops->set_ios)
789 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF
790}
791
792void mmc_set_clock(struct mmc *mmc, uint clock)
793{
93bfd616
PA
794 if (clock > mmc->cfg->f_max)
795 clock = mmc->cfg->f_max;
272cc70b 796
93bfd616
PA
797 if (clock < mmc->cfg->f_min)
798 clock = mmc->cfg->f_min;
272cc70b
AF
799
800 mmc->clock = clock;
801
802 mmc_set_ios(mmc);
803}
804
fdbb873e 805static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF
806{
807 mmc->bus_width = width;
808
809 mmc_set_ios(mmc);
810}
811
fdbb873e 812static int mmc_startup(struct mmc *mmc)
272cc70b 813{
f866a46d 814 int err, i;
272cc70b 815 uint mult, freq;
639b7827 816 u64 cmult, csize, capacity;
272cc70b 817 struct mmc_cmd cmd;
8bfa195e
SG
818 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
819 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 820 int timeout = 1000;
0c453bb7 821 bool has_parts = false;
272cc70b 822
d52ebf10
TC
823#ifdef CONFIG_MMC_SPI_CRC_ON
824 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
825 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
826 cmd.resp_type = MMC_RSP_R1;
827 cmd.cmdarg = 1;
d52ebf10
TC
828 err = mmc_send_cmd(mmc, &cmd, NULL);
829
830 if (err)
831 return err;
832 }
833#endif
834
272cc70b 835 /* Put the Card in Identify Mode */
d52ebf10
TC
836 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
837 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF
838 cmd.resp_type = MMC_RSP_R2;
839 cmd.cmdarg = 0;
272cc70b
AF
840
841 err = mmc_send_cmd(mmc, &cmd, NULL);
842
843 if (err)
844 return err;
845
846 memcpy(mmc->cid, cmd.response, 16);
847
848 /*
849 * For MMC cards, set the Relative Address.
850 * For SD cards, get the Relatvie Address.
851 * This also puts the cards into Standby State
852 */
d52ebf10
TC
853 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
854 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
855 cmd.cmdarg = mmc->rca << 16;
856 cmd.resp_type = MMC_RSP_R6;
272cc70b 857
d52ebf10 858 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 859
d52ebf10
TC
860 if (err)
861 return err;
272cc70b 862
d52ebf10
TC
863 if (IS_SD(mmc))
864 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
865 }
272cc70b
AF
866
867 /* Get the Card-Specific Data */
868 cmd.cmdidx = MMC_CMD_SEND_CSD;
869 cmd.resp_type = MMC_RSP_R2;
870 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
871
872 err = mmc_send_cmd(mmc, &cmd, NULL);
873
5d4fc8d9
RR
874 /* Waiting for the ready status */
875 mmc_send_status(mmc, timeout);
876
272cc70b
AF
877 if (err)
878 return err;
879
998be3dd
RV
880 mmc->csd[0] = cmd.response[0];
881 mmc->csd[1] = cmd.response[1];
882 mmc->csd[2] = cmd.response[2];
883 mmc->csd[3] = cmd.response[3];
272cc70b
AF
884
885 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 886 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF
887
888 switch (version) {
889 case 0:
890 mmc->version = MMC_VERSION_1_2;
891 break;
892 case 1:
893 mmc->version = MMC_VERSION_1_4;
894 break;
895 case 2:
896 mmc->version = MMC_VERSION_2_2;
897 break;
898 case 3:
899 mmc->version = MMC_VERSION_3;
900 break;
901 case 4:
902 mmc->version = MMC_VERSION_4;
903 break;
904 default:
905 mmc->version = MMC_VERSION_1_2;
906 break;
907 }
908 }
909
910 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV
911 freq = fbase[(cmd.response[0] & 0x7)];
912 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF
913
914 mmc->tran_speed = freq * mult;
915
ab71188c 916 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 917 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF
918
919 if (IS_SD(mmc))
920 mmc->write_bl_len = mmc->read_bl_len;
921 else
998be3dd 922 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF
923
924 if (mmc->high_capacity) {
925 csize = (mmc->csd[1] & 0x3f) << 16
926 | (mmc->csd[2] & 0xffff0000) >> 16;
927 cmult = 8;
928 } else {
929 csize = (mmc->csd[1] & 0x3ff) << 2
930 | (mmc->csd[2] & 0xc0000000) >> 30;
931 cmult = (mmc->csd[2] & 0x00038000) >> 15;
932 }
933
f866a46d
SW
934 mmc->capacity_user = (csize + 1) << (cmult + 2);
935 mmc->capacity_user *= mmc->read_bl_len;
936 mmc->capacity_boot = 0;
937 mmc->capacity_rpmb = 0;
938 for (i = 0; i < 4; i++)
939 mmc->capacity_gp[i] = 0;
272cc70b 940
8bfa195e
SG
941 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
942 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 943
8bfa195e
SG
944 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
945 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 946
ab71188c
MN
947 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
948 cmd.cmdidx = MMC_CMD_SET_DSR;
949 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
950 cmd.resp_type = MMC_RSP_NONE;
951 if (mmc_send_cmd(mmc, &cmd, NULL))
952 printf("MMC: SET_DSR failed\n");
953 }
954
272cc70b 955 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC
956 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
957 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 958 cmd.resp_type = MMC_RSP_R1;
d52ebf10 959 cmd.cmdarg = mmc->rca << 16;
d52ebf10 960 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 961
d52ebf10
TC
962 if (err)
963 return err;
964 }
272cc70b 965
e6f99a56
LW
966 /*
967 * For SD, its erase group is always one sector
968 */
969 mmc->erase_grp_size = 1;
bc897b1d 970 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG
971 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
972 /* check ext_csd version and capacity */
973 err = mmc_send_ext_csd(mmc, ext_csd);
fdbb873e 974 if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
639b7827
YS
975 /*
976 * According to the JEDEC Standard, the value of
977 * ext_csd's capacity is valid if the value is more
978 * than 2GB
979 */
0560db18
LW
980 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
981 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
982 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
983 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 984 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 985 if ((capacity >> 20) > 2 * 1024)
f866a46d 986 mmc->capacity_user = capacity;
d23e2c09 987 }
bc897b1d 988
64f4a619
JC
989 switch (ext_csd[EXT_CSD_REV]) {
990 case 1:
991 mmc->version = MMC_VERSION_4_1;
992 break;
993 case 2:
994 mmc->version = MMC_VERSION_4_2;
995 break;
996 case 3:
997 mmc->version = MMC_VERSION_4_3;
998 break;
999 case 5:
1000 mmc->version = MMC_VERSION_4_41;
1001 break;
1002 case 6:
1003 mmc->version = MMC_VERSION_4_5;
1004 break;
edab723b
MN
1005 case 7:
1006 mmc->version = MMC_VERSION_5_0;
1007 break;
64f4a619
JC
1008 }
1009
0c453bb7
DSC
1010 /* store the partition info of emmc */
1011 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1012 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1013 ext_csd[EXT_CSD_BOOT_MULT])
1014 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1015 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)
1016 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1017
1018 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1019
1020 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1021
1022 for (i = 0; i < 4; i++) {
1023 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1024 mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
1025 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1026 mmc->capacity_gp[i] *=
1027 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1028 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1029 if (mmc->capacity_gp[i])
1030 has_parts = true;
1031 }
1032
e6f99a56 1033 /*
1937e5aa
OM
1034 * Host needs to enable ERASE_GRP_DEF bit if device is
1035 * partitioned. This bit will be lost every time after a reset
1036 * or power off. This will affect erase size.
e6f99a56 1037 */
0c453bb7
DSC
1038 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1039 EXT_CSD_PARTITION_SETTING_COMPLETED)
1040 has_parts = true;
1937e5aa 1041 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC
1042 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1043 has_parts = true;
1044 if (has_parts) {
1937e5aa
OM
1045 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1046 EXT_CSD_ERASE_GROUP_DEF, 1);
1047
1048 if (err)
1049 return err;
021a8055
HP
1050 else
1051 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1937e5aa
OM
1052
1053 /* Read out group size from ext_csd */
0560db18 1054 mmc->erase_grp_size =
8bfa195e
SG
1055 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
1056 MMC_MAX_BLOCK_LEN * 1024;
d7b29129
MN
1057 /*
1058 * if high capacity and partition setting completed
1059 * SEC_COUNT is valid even if it is smaller than 2 GiB
1060 * JEDEC Standard JESD84-B45, 6.2.4
1061 */
1062 if (mmc->high_capacity &&
1063 (ext_csd[EXT_CSD_PARTITION_SETTING] &
1064 EXT_CSD_PARTITION_SETTING_COMPLETED)) {
1065 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1066 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1067 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1068 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1069 capacity *= MMC_MAX_BLOCK_LEN;
1070 mmc->capacity_user = capacity;
1071 }
8bfa195e 1072 } else {
1937e5aa 1073 /* Calculate the group size from the csd value. */
e6f99a56
LW
1074 int erase_gsz, erase_gmul;
1075 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1076 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1077 mmc->erase_grp_size = (erase_gsz + 1)
1078 * (erase_gmul + 1);
1079 }
d23e2c09
SG
1080 }
1081
f866a46d
SW
1082 err = mmc_set_capacity(mmc, mmc->part_num);
1083 if (err)
1084 return err;
1085
272cc70b
AF
1086 if (IS_SD(mmc))
1087 err = sd_change_freq(mmc);
1088 else
1089 err = mmc_change_freq(mmc);
1090
1091 if (err)
1092 return err;
1093
1094 /* Restrict card's capabilities by what the host can do */
93bfd616 1095 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF
1096
1097 if (IS_SD(mmc)) {
1098 if (mmc->card_caps & MMC_MODE_4BIT) {
1099 cmd.cmdidx = MMC_CMD_APP_CMD;
1100 cmd.resp_type = MMC_RSP_R1;
1101 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1102
1103 err = mmc_send_cmd(mmc, &cmd, NULL);
1104 if (err)
1105 return err;
1106
1107 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1108 cmd.resp_type = MMC_RSP_R1;
1109 cmd.cmdarg = 2;
272cc70b
AF
1110 err = mmc_send_cmd(mmc, &cmd, NULL);
1111 if (err)
1112 return err;
1113
1114 mmc_set_bus_width(mmc, 4);
1115 }
1116
1117 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1118 mmc->tran_speed = 50000000;
272cc70b 1119 else
ad5fd922 1120 mmc->tran_speed = 25000000;
272cc70b 1121 } else {
7798f6db
AF
1122 int idx;
1123
1124 /* An array of possible bus widths in order of preference */
1125 static unsigned ext_csd_bits[] = {
d22e3d46
JC
1126 EXT_CSD_DDR_BUS_WIDTH_8,
1127 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF
1128 EXT_CSD_BUS_WIDTH_8,
1129 EXT_CSD_BUS_WIDTH_4,
1130 EXT_CSD_BUS_WIDTH_1,
1131 };
1132
1133 /* An array to map CSD bus widths to host cap bits */
1134 static unsigned ext_to_hostcaps[] = {
786e8f81
AG
1135 [EXT_CSD_DDR_BUS_WIDTH_4] =
1136 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1137 [EXT_CSD_DDR_BUS_WIDTH_8] =
1138 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF
1139 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1140 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1141 };
1142
1143 /* An array to map chosen bus width to an integer */
1144 static unsigned widths[] = {
d22e3d46 1145 8, 4, 8, 4, 1,
7798f6db
AF
1146 };
1147
1148 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1149 unsigned int extw = ext_csd_bits[idx];
786e8f81 1150 unsigned int caps = ext_to_hostcaps[extw];
7798f6db
AF
1151
1152 /*
786e8f81
AG
1153 * Check to make sure the card and controller support
1154 * these capabilities
7798f6db 1155 */
786e8f81 1156 if ((mmc->card_caps & caps) != caps)
7798f6db
AF
1157 continue;
1158
272cc70b 1159 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1160 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF
1161
1162 if (err)
4137894e 1163 continue;
272cc70b 1164
786e8f81 1165 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1166 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW
1167
1168 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG
1169
1170 if (err)
1171 continue;
1172
786a27b7 1173 /* Only compare read only fields */
786e8f81
AG
1174 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1175 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1176 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1177 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1178 ext_csd[EXT_CSD_REV]
1179 == test_csd[EXT_CSD_REV] &&
1180 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1181 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1182 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1183 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1184 break;
786e8f81
AG
1185 else
1186 err = SWITCH_ERR;
272cc70b
AF
1187 }
1188
786e8f81
AG
1189 if (err)
1190 return err;
1191
272cc70b
AF
1192 if (mmc->card_caps & MMC_MODE_HS) {
1193 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1194 mmc->tran_speed = 52000000;
272cc70b 1195 else
ad5fd922
JC
1196 mmc->tran_speed = 26000000;
1197 }
272cc70b
AF
1198 }
1199
ad5fd922
JC
1200 mmc_set_clock(mmc, mmc->tran_speed);
1201
5af8f45c
AG
1202 /* Fix the block length for DDR mode */
1203 if (mmc->ddr_mode) {
1204 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1205 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1206 }
1207
272cc70b
AF
1208 /* fill in device description */
1209 mmc->block_dev.lun = 0;
1210 mmc->block_dev.type = 0;
1211 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1212 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1213 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1214#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH
1215 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1216 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1217 (mmc->cid[3] >> 16) & 0xffff);
1218 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1219 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1220 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1221 (mmc->cid[2] >> 24) & 0xff);
1222 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1223 (mmc->cid[2] >> 16) & 0xf);
56196826
PB
1224#else
1225 mmc->block_dev.vendor[0] = 0;
1226 mmc->block_dev.product[0] = 0;
1227 mmc->block_dev.revision[0] = 0;
1228#endif
122efd43 1229#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1230 init_part(&mmc->block_dev);
122efd43 1231#endif
272cc70b
AF
1232
1233 return 0;
1234}
1235
fdbb873e 1236static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF
1237{
1238 struct mmc_cmd cmd;
1239 int err;
1240
1241 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1242 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1243 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1244 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF
1245
1246 err = mmc_send_cmd(mmc, &cmd, NULL);
1247
1248 if (err)
1249 return err;
1250
998be3dd 1251 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF
1252 return UNUSABLE_ERR;
1253 else
1254 mmc->version = SD_VERSION_2;
1255
1256 return 0;
1257}
1258
93bfd616
PA
1259/* not used any more */
1260int __deprecated mmc_register(struct mmc *mmc)
1261{
1262#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1263 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1264#endif
1265 return -1;
1266}
1267
1268struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1269{
93bfd616
PA
1270 struct mmc *mmc;
1271
1272 /* quick validation */
1273 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1274 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1275 return NULL;
1276
1277 mmc = calloc(1, sizeof(*mmc));
1278 if (mmc == NULL)
1279 return NULL;
1280
1281 mmc->cfg = cfg;
1282 mmc->priv = priv;
1283
1284 /* the following chunk was mmc_register() */
1285
ab71188c
MN
1286 /* Setup dsr related values */
1287 mmc->dsr_imp = 0;
1288 mmc->dsr = 0xffffffff;
272cc70b
AF
1289 /* Setup the universal parts of the block interface just once */
1290 mmc->block_dev.if_type = IF_TYPE_MMC;
1291 mmc->block_dev.dev = cur_dev_num++;
1292 mmc->block_dev.removable = 1;
1293 mmc->block_dev.block_read = mmc_bread;
1294 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1295 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1296
93bfd616
PA
1297 /* setup initial part type */
1298 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1299
93bfd616 1300 INIT_LIST_HEAD(&mmc->link);
272cc70b 1301
93bfd616
PA
1302 list_add_tail(&mmc->link, &mmc_devices);
1303
1304 return mmc;
1305}
1306
1307void mmc_destroy(struct mmc *mmc)
1308{
1309 /* only freeing memory for now */
1310 free(mmc);
272cc70b
AF
1311}
1312
df3fc526 1313#ifdef CONFIG_PARTITIONS
272cc70b
AF
1314block_dev_desc_t *mmc_get_dev(int dev)
1315{
1316 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1317 if (!mmc || mmc_init(mmc))
40242bc3 1318 return NULL;
272cc70b 1319
40242bc3 1320 return &mmc->block_dev;
272cc70b 1321}
df3fc526 1322#endif
272cc70b 1323
95de9ab2
PK
1324/* board-specific MMC power initializations. */
1325__weak void board_mmc_power_init(void)
1326{
1327}
1328
e9550449 1329int mmc_start_init(struct mmc *mmc)
272cc70b 1330{
afd5932b 1331 int err;
272cc70b 1332
ab769f22 1333 /* we pretend there's no card when init is NULL */
93bfd616 1334 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1335 mmc->has_init = 0;
56196826 1336#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1337 printf("MMC: no card present\n");
56196826 1338#endif
48972d90
TR
1339 return NO_CARD_ERR;
1340 }
1341
bc897b1d
LW
1342 if (mmc->has_init)
1343 return 0;
1344
95de9ab2
PK
1345 board_mmc_power_init();
1346
ab769f22 1347 /* made sure it's not NULL earlier */
93bfd616 1348 err = mmc->cfg->ops->init(mmc);
272cc70b
AF
1349
1350 if (err)
1351 return err;
1352
786e8f81 1353 mmc->ddr_mode = 0;
b86b85e2
IY
1354 mmc_set_bus_width(mmc, 1);
1355 mmc_set_clock(mmc, 1);
1356
272cc70b
AF
1357 /* Reset the Card */
1358 err = mmc_go_idle(mmc);
1359
1360 if (err)
1361 return err;
1362
bc897b1d
LW
1363 /* The internal partition reset to user partition(0) at every CMD0*/
1364 mmc->part_num = 0;
1365
272cc70b 1366 /* Test for SD version 2 */
afd5932b 1367 err = mmc_send_if_cond(mmc);
272cc70b 1368
272cc70b
AF
1369 /* Now try to get the SD card's operating condition */
1370 err = sd_send_op_cond(mmc);
1371
1372 /* If the command timed out, we check for an MMC card */
1373 if (err == TIMEOUT) {
1374 err = mmc_send_op_cond(mmc);
1375
e9550449 1376 if (err && err != IN_PROGRESS) {
56196826 1377#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1378 printf("Card did not respond to voltage select!\n");
56196826 1379#endif
272cc70b
AF
1380 return UNUSABLE_ERR;
1381 }
1382 }
1383
e9550449
CLC
1384 if (err == IN_PROGRESS)
1385 mmc->init_in_progress = 1;
1386
1387 return err;
1388}
1389
1390static int mmc_complete_init(struct mmc *mmc)
1391{
1392 int err = 0;
1393
1394 if (mmc->op_cond_pending)
1395 err = mmc_complete_op_cond(mmc);
1396
1397 if (!err)
1398 err = mmc_startup(mmc);
bc897b1d
LW
1399 if (err)
1400 mmc->has_init = 0;
1401 else
1402 mmc->has_init = 1;
e9550449
CLC
1403 mmc->init_in_progress = 0;
1404 return err;
1405}
1406
1407int mmc_init(struct mmc *mmc)
1408{
1409 int err = IN_PROGRESS;
d803fea5 1410 unsigned start;
e9550449
CLC
1411
1412 if (mmc->has_init)
1413 return 0;
d803fea5
MZ
1414
1415 start = get_timer(0);
1416
e9550449
CLC
1417 if (!mmc->init_in_progress)
1418 err = mmc_start_init(mmc);
1419
1420 if (!err || err == IN_PROGRESS)
1421 err = mmc_complete_init(mmc);
1422 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1423 return err;
272cc70b
AF
1424}
1425
ab71188c
MN
1426int mmc_set_dsr(struct mmc *mmc, u16 val)
1427{
1428 mmc->dsr = val;
1429 return 0;
1430}
1431
cee9ab7c
JH
1432/* CPU-specific MMC initializations */
1433__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF
1434{
1435 return -1;
1436}
1437
cee9ab7c
JH
1438/* board-specific MMC initializations. */
1439__weak int board_mmc_init(bd_t *bis)
1440{
1441 return -1;
1442}
272cc70b 1443
56196826
PB
1444#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1445
272cc70b
AF
1446void print_mmc_devices(char separator)
1447{
1448 struct mmc *m;
1449 struct list_head *entry;
1450
1451 list_for_each(entry, &mmc_devices) {
1452 m = list_entry(entry, struct mmc, link);
1453
93bfd616 1454 printf("%s: %d", m->cfg->name, m->block_dev.dev);
272cc70b 1455
e75eaf10
LP
1456 if (entry->next != &mmc_devices) {
1457 printf("%c", separator);
1458 if (separator != '\n')
1459 puts (" ");
1460 }
272cc70b
AF
1461 }
1462
1463 printf("\n");
1464}
1465
56196826
PB
1466#else
1467void print_mmc_devices(char separator) { }
1468#endif
1469
ea6ebe21
LW
1470int get_mmc_num(void)
1471{
1472 return cur_dev_num;
1473}
1474
e9550449
CLC
1475void mmc_set_preinit(struct mmc *mmc, int preinit)
1476{
1477 mmc->preinit = preinit;
1478}
1479
1480static void do_preinit(void)
1481{
1482 struct mmc *m;
1483 struct list_head *entry;
1484
1485 list_for_each(entry, &mmc_devices) {
1486 m = list_entry(entry, struct mmc, link);
1487
1488 if (m->preinit)
1489 mmc_start_init(m);
1490 }
1491}
1492
1493
272cc70b
AF
1494int mmc_initialize(bd_t *bis)
1495{
1496 INIT_LIST_HEAD (&mmc_devices);
1497 cur_dev_num = 0;
1498
1499 if (board_mmc_init(bis) < 0)
1500 cpu_mmc_init(bis);
1501
bb0dc108 1502#ifndef CONFIG_SPL_BUILD
272cc70b 1503 print_mmc_devices(',');
bb0dc108 1504#endif
272cc70b 1505
e9550449 1506 do_preinit();
272cc70b
AF
1507 return 0;
1508}
3690d6d6
A
1509
1510#ifdef CONFIG_SUPPORT_EMMC_BOOT
1511/*
1512 * This function changes the size of boot partition and the size of rpmb
1513 * partition present on EMMC devices.
1514 *
1515 * Input Parameters:
1516 * struct *mmc: pointer for the mmc device strcuture
1517 * bootsize: size of boot partition
1518 * rpmbsize: size of rpmb partition
1519 *
1520 * Returns 0 on success.
1521 */
1522
1523int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1524 unsigned long rpmbsize)
1525{
1526 int err;
1527 struct mmc_cmd cmd;
1528
1529 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1530 cmd.cmdidx = MMC_CMD_RES_MAN;
1531 cmd.resp_type = MMC_RSP_R1b;
1532 cmd.cmdarg = MMC_CMD62_ARG1;
1533
1534 err = mmc_send_cmd(mmc, &cmd, NULL);
1535 if (err) {
1536 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1537 return err;
1538 }
1539
1540 /* Boot partition changing mode */
1541 cmd.cmdidx = MMC_CMD_RES_MAN;
1542 cmd.resp_type = MMC_RSP_R1b;
1543 cmd.cmdarg = MMC_CMD62_ARG2;
1544
1545 err = mmc_send_cmd(mmc, &cmd, NULL);
1546 if (err) {
1547 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1548 return err;
1549 }
1550 /* boot partition size is multiple of 128KB */
1551 bootsize = (bootsize * 1024) / 128;
1552
1553 /* Arg: boot partition size */
1554 cmd.cmdidx = MMC_CMD_RES_MAN;
1555 cmd.resp_type = MMC_RSP_R1b;
1556 cmd.cmdarg = bootsize;
1557
1558 err = mmc_send_cmd(mmc, &cmd, NULL);
1559 if (err) {
1560 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1561 return err;
1562 }
1563 /* RPMB partition size is multiple of 128KB */
1564 rpmbsize = (rpmbsize * 1024) / 128;
1565 /* Arg: RPMB partition size */
1566 cmd.cmdidx = MMC_CMD_RES_MAN;
1567 cmd.resp_type = MMC_RSP_R1b;
1568 cmd.cmdarg = rpmbsize;
1569
1570 err = mmc_send_cmd(mmc, &cmd, NULL);
1571 if (err) {
1572 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1573 return err;
1574 }
1575 return 0;
1576}
1577
5a99b9de
TR
1578/*
1579 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1580 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1581 * and BOOT_MODE.
1582 *
1583 * Returns 0 on success.
1584 */
1585int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1586{
1587 int err;
1588
1589 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1590 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1591 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1592 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1593
1594 if (err)
1595 return err;
1596 return 0;
1597}
1598
792970b0
TR
1599/*
1600 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1601 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1602 * PARTITION_ACCESS.
1603 *
1604 * Returns 0 on success.
1605 */
1606int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1607{
1608 int err;
1609
1610 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1611 EXT_CSD_BOOT_ACK(ack) |
1612 EXT_CSD_BOOT_PART_NUM(part_num) |
1613 EXT_CSD_PARTITION_ACCESS(access));
1614
1615 if (err)
1616 return err;
1617 return 0;
1618}
33ace362
TR
1619
1620/*
1621 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1622 * for enable. Note that this is a write-once field for non-zero values.
1623 *
1624 * Returns 0 on success.
1625 */
1626int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1627{
1628 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1629 enable);
1630}
3690d6d6 1631#endif