]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mips/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim/erc32: use SIM_AC_OPTION_HOSTENDIAN to probe for host endianess
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
8406bb59
MF		 12015-03-15 Mike Frysinger <vapier@gentoo.org>
2
3 * tconfig.in: Delete includes.
4 [HAVE_DV_SOCKSER]: Delete.
5
465fb143
MF		 62015-03-14 Mike Frysinger <vapier@gentoo.org>
7
8 * Makefile.in (SIM_RUN_OBJS): Delete.
9
5cddc23a
MF		 102015-03-14 Mike Frysinger <vapier@gentoo.org>
11
12 * configure.ac (AC_CHECK_HEADERS): Delete.
13 * aclocal.m4, configure: Regenerate.
14
2974be62
AM		 152014-08-19 Alan Modra <amodra@gmail.com>
16
17 * configure: Regenerate.
18
faa743bb
RM		 192014-08-15 Roland McGrath <mcgrathr@google.com>
20
21 * configure: Regenerate.
22 * config.in: Regenerate.
23
1a8a700e
MF		 242014-03-04 Mike Frysinger <vapier@gentoo.org>
25
26 * configure: Regenerate.
27
bf3d9781
AM		 282013-09-23 Alan Modra <amodra@gmail.com>
29
30 * configure: Regenerate.
31
31e6ad7d
MF		 322013-06-03 Mike Frysinger <vapier@gentoo.org>
33
34 * aclocal.m4, configure: Regenerate.
35
d3685d60
TT		 362013-05-10 Freddie Chopin <freddie_chopin@op.pl>
37
38 * configure: Rebuild.
39
1517bd27
MF		 402013-03-26 Mike Frysinger <vapier@gentoo.org>
41
42 * configure: Regenerate.
43
3be31516
JS		 442013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
45
46 * configure.ac: Address use of dv-sockser.o.
47 * tconfig.in: Conditionalize use of dv_sockser_install.
48 * configure: Regenerated.
49 * config.in: Regenerated.
50
37cb8f8e
SE		 512012-10-04 Chao-ying Fu <fu@mips.com>
52 Steve Ellcey <sellcey@mips.com>
53
54 * mips/mips3264r2.igen (rdhwr): New.
55
87c8644f
JS		 562012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
57
58 * configure.ac: Always link against dv-sockser.o.
59 * configure: Regenerate.
60
5f3ef9d0
JB		 612012-06-15 Joel Brobecker <brobecker@adacore.com>
62
63 * config.in, configure: Regenerate.
64
a6ff997c
NC		 652012-05-18 Nick Clifton <nickc@redhat.com>
66
67 PR 14072
68 * interp.c: Include config.h before system header files.
69
2232061b
MF		 702012-03-24 Mike Frysinger <vapier@gentoo.org>
71
72 * aclocal.m4, config.in, configure: Regenerate.
73
db2e4d67
MF		 742011-12-03 Mike Frysinger <vapier@gentoo.org>
75
76 * aclocal.m4: New file.
77 * configure: Regenerate.
78
4399a56b
MF		 792011-10-19 Mike Frysinger <vapier@gentoo.org>
80
81 * configure: Regenerate after common/acinclude.m4 update.
82
9c082ca8
MF		 832011-10-17 Mike Frysinger <vapier@gentoo.org>
84
85 * configure.ac: Change include to common/acinclude.m4.
86
6ffe910a
MF		 872011-10-17 Mike Frysinger <vapier@gentoo.org>
88
89 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
90 call. Replace common.m4 include with SIM_AC_COMMON.
91 * configure: Regenerate.
92
31b28250
HPN		 932011-07-08 Hans-Peter Nilsson <hp@axis.com>
94
3faa01e3
HPN		 95 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
96 $(SIM_EXTRA_DEPS).
97 (tmp-mach-multi): Exit early when igen fails.
31b28250 98
2419798b
MF		 992011-07-05 Mike Frysinger <vapier@gentoo.org>
100
101 * interp.c (sim_do_command): Delete.
102
d79fe0d6
MF		 1032011-02-14 Mike Frysinger <vapier@gentoo.org>
104
105 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
106 (tx3904sio_fifo_reset): Likewise.
107 * interp.c (sim_monitor): Likewise.
108
5558e7e6
MF		 1092010-04-14 Mike Frysinger <vapier@gentoo.org>
110
111 * interp.c (sim_write): Add const to buffer arg.
112
35aafff4
JB		 1132010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
114
115 * interp.c: Don't include sysdep.h
116
3725885a
RW		 1172010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
118
119 * configure: Regenerate.
120
d6416cdc
RW		 1212009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
122
81ecdfbb
RW		 123 * config.in: Regenerate.
124 * configure: Likewise.
125
d6416cdc
RW		 126 * configure: Regenerate.
127
b5bd9624
HPN		 1282008-07-11 Hans-Peter Nilsson <hp@axis.com>
129
130 * configure: Regenerate to track ../common/common.m4 changes.
131 * config.in: Ditto.
132
6efef468
JM		 1332008-06-06 Vladimir Prus <vladimir@codesourcery.com>
134 Daniel Jacobowitz <dan@codesourcery.com>
135 Joseph Myers <joseph@codesourcery.com>
136
137 * configure: Regenerate.
138
60dc88db
RS		 1392007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
140
141 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
142 that unconditionally allows fmt_ps.
143 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
144 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
145 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
146 filter from 64,f to 32,f.
147 (PREFX): Change filter from 64 to 32.
148 (LDXC1, LUXC1): Provide separate mips32r2 implementations
149 that use do_load_double instead of do_load. Make both LUXC1
150 versions unpredictable if SizeFGR () != 64.
151 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
152 instead of do_store. Remove unused variable. Make both SUXC1
153 versions unpredictable if SizeFGR () != 64.
154
599ca73e
RS		 1552007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
156
157 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
158 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
159 shifts for that case.
160
2525df03
NC		 1612007-09-04 Nick Clifton <nickc@redhat.com>
162
163 * interp.c (options enum): Add OPTION_INFO_MEMORY.
164 (display_mem_info): New static variable.
165 (mips_option_handler): Handle OPTION_INFO_MEMORY.
166 (mips_options): Add info-memory and memory-info.
167 (sim_open): After processing the command line and board
168 specification, check display_mem_info. If it is set then
169 call the real handler for the --memory-info command line
170 switch.
171
35ee6e1e
JB		 1722007-08-24 Joel Brobecker <brobecker@adacore.com>
173
174 * configure.ac: Change license of multi-run.c to GPL version 3.
175 * configure: Regenerate.
176
d5fb0879
RS		 1772007-06-28 Richard Sandiford <richard@codesourcery.com>
178
179 * configure.ac, configure: Revert last patch.
180
2a2ce21b
RS		 1812007-06-26 Richard Sandiford <richard@codesourcery.com>
182
183 * configure.ac (sim_mipsisa3264_configs): New variable.
184 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
185 every configuration support all four targets, using the triplet to
186 determine the default.
187 * configure: Regenerate.
188
efdcccc9
RS		 1892007-06-25 Richard Sandiford <richard@codesourcery.com>
190
0a7692b2 191 * Makefile.in (m16run.o): New rule.
efdcccc9 192
f532a356
TS		 1932007-05-15 Thiemo Seufer <ths@mips.com>
194
195 * mips3264r2.igen (DSHD): Fix compile warning.
196
bfe9c90b
TS		 1972007-05-14 Thiemo Seufer <ths@mips.com>
198
199 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
200 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
201 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
202 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
203 for mips32r2.
204
53f4826b
TS		 2052007-03-01 Thiemo Seufer <ths@mips.com>
206
207 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
208 and mips64.
209
8bf3ddc8
TS		 2102007-02-20 Thiemo Seufer <ths@mips.com>
211
212 * dsp.igen: Update copyright notice.
213 * dsp2.igen: Fix copyright notice.
214
8b082fb1
TS		 2152007-02-20 Thiemo Seufer <ths@mips.com>
216 Chao-Ying Fu <fu@mips.com>
217
218 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
219 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
220 Add dsp2 to sim_igen_machine.
221 * configure: Regenerate.
222 * dsp.igen (do_ph_op): Add MUL support when op = 2.
223 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
224 (mulq_rs.ph): Use do_ph_mulq.
225 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
226 * mips.igen: Add dsp2 model and include dsp2.igen.
227 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
228 for *mips32r2, *mips64r2, *dsp.
229 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
230 for *mips32r2, *mips64r2, *dsp2.
231 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
232
b1004875
TS		 2332007-02-19 Thiemo Seufer <ths@mips.com>
234 Nigel Stephens <nigel@mips.com>
235
236 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
237 jumps with hazard barrier.
238
f8df4c77
TS		 2392007-02-19 Thiemo Seufer <ths@mips.com>
240 Nigel Stephens <nigel@mips.com>
241
242 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
243 after each call to sim_io_write.
244
b1004875 2452007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 246 Nigel Stephens <nigel@mips.com>
b1004875
TS		 247
248 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
249 supported by this simulator.
07802d98
TS		 250 (decode_coproc): Recognise additional CP0 Config registers
251 correctly.
252
14fb6c5a
TS		 2532007-02-19 Thiemo Seufer <ths@mips.com>
254 Nigel Stephens <nigel@mips.com>
255 David Ung <davidu@mips.com>
256
257 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
258 uninterpreted formats. If fmt is one of the uninterpreted types
259 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
260 fmt_word, and fmt_uninterpreted_64 like fmt_long.
261 (store_fpr): When writing an invalid odd register, set the
262 matching even register to fmt_unknown, not the following register.
263 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
264 the the memory window at offset 0 set by --memory-size command
265 line option.
266 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
267 point register.
268 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
269 register.
270 (sim_monitor): When returning the memory size to the MIPS
271 application, use the value in STATE_MEM_SIZE, not an arbitrary
272 hardcoded value.
273 (cop_lw): Don' mess around with FPR_STATE, just pass
274 fmt_uninterpreted_32 to StoreFPR.
275 (cop_sw): Similarly.
276 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
277 (cop_sd): Similarly.
278 * mips.igen (not_word_value): Single version for mips32, mips64
279 and mips16.
280
c8847145
TS		 2812007-02-19 Thiemo Seufer <ths@mips.com>
282 Nigel Stephens <nigel@mips.com>
283
284 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
285 MBytes.
286
4b5d35ee
TS		 2872007-02-17 Thiemo Seufer <ths@mips.com>
288
289 * configure.ac (mips*-sde-elf*): Move in front of generic machine
290 configuration.
291 * configure: Regenerate.
292
3669427c
TS		 2932007-02-17 Thiemo Seufer <ths@mips.com>
294
295 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
296 Add mdmx to sim_igen_machine.
297 (mipsisa64*-*-*): Likewise. Remove dsp.
298 (mipsisa32*-*-*): Remove dsp.
299 * configure: Regenerate.
300
109ad085
TS		 3012007-02-13 Thiemo Seufer <ths@mips.com>
302
303 * configure.ac: Add mips*-sde-elf* target.
304 * configure: Regenerate.
305
921d7ad3
HPN		 3062006-12-21 Hans-Peter Nilsson <hp@axis.com>
307
308 * acconfig.h: Remove.
309 * config.in, configure: Regenerate.
310
02f97da7
TS		 3112006-11-07 Thiemo Seufer <ths@mips.com>
312
313 * dsp.igen (do_w_op): Fix compiler warning.
314
2d2733fc
TS		 3152006-08-29 Thiemo Seufer <ths@mips.com>
316 David Ung <davidu@mips.com>
317
318 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
319 sim_igen_machine.
320 * configure: Regenerate.
321 * mips.igen (model): Add smartmips.
322 (MADDU): Increment ACX if carry.
323 (do_mult): Clear ACX.
324 (ROR,RORV): Add smartmips.
325 (include): Include smartmips.igen.
326 * sim-main.h (ACX): Set to REGISTERS[89].
327 * smartmips.igen: New file.
328
d85c3a10
TS		 3292006-08-29 Thiemo Seufer <ths@mips.com>
330 David Ung <davidu@mips.com>
331
332 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
333 mips3264r2.igen. Add missing dependency rules.
334 * m16e.igen: Support for mips16e save/restore instructions.
335
e85e3205
RE		 3362006-06-13 Richard Earnshaw <rearnsha@arm.com>
337
338 * configure: Regenerated.
339
2f0122dc
DJ		 3402006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
341
342 * configure: Regenerated.
343
20e95c23
DJ		 3442006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
345
346 * configure: Regenerated.
347
69088b17
CF		 3482006-05-15 Chao-ying Fu <fu@mips.com>
349
350 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
351
0275de4e
NC		 3522006-04-18 Nick Clifton <nickc@redhat.com>
353
354 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
355 statement.
356
b3a3ffef
HPN		 3572006-03-29 Hans-Peter Nilsson <hp@axis.com>
358
359 * configure: Regenerate.
360
40a5538e
CF		 3612005-12-14 Chao-ying Fu <fu@mips.com>
362
363 * Makefile.in (SIM_OBJS): Add dsp.o.
364 (dsp.o): New dependency.
365 (IGEN_INCLUDE): Add dsp.igen.
366 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
367 mipsisa64*-*-*): Add dsp to sim_igen_machine.
368 * configure: Regenerate.
369 * mips.igen: Add dsp model and include dsp.igen.
370 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
371 because these instructions are extended in DSP ASE.
372 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
373 adding 6 DSP accumulator registers and 1 DSP control register.
374 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
375 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
376 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
377 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
378 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
379 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
380 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
381 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
382 DSPCR_CCOND_SMASK): New define.
383 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
384 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
385
21d14896
ILT		 3862005-07-08 Ian Lance Taylor <ian@airs.com>
387
388 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
389
b16d63da
DU		 3902005-06-16 David Ung <davidu@mips.com>
391 Nigel Stephens <nigel@mips.com>
392
393 * mips.igen: New mips16e model and include m16e.igen.
394 (check_u64): Add mips16e tag.
395 * m16e.igen: New file for MIPS16e instructions.
396 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
397 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
398 models.
399 * configure: Regenerate.
400
e70cb6cd
CD		 4012005-05-26 David Ung <davidu@mips.com>
402
403 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
404 tags to all instructions which are applicable to the new ISAs.
405 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
406 vr.igen.
407 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
408 instructions.
409 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
410 to mips.igen.
411 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
412 * configure: Regenerate.
413
2b193c4a
MK		 4142005-03-23 Mark Kettenis <kettenis@gnu.org>
415
416 * configure: Regenerate.
417
35695fd6
AC		 4182005-01-14 Andrew Cagney <cagney@gnu.org>
419
420 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
421 explicit call to AC_CONFIG_HEADER.
422 * configure: Regenerate.
423
f0569246
AC		 4242005-01-12 Andrew Cagney <cagney@gnu.org>
425
426 * configure.ac: Update to use ../common/common.m4.
427 * configure: Re-generate.
428
38f48d72
AC		 4292005-01-11 Andrew Cagney <cagney@localhost.localdomain>
430
431 * configure: Regenerated to track ../common/aclocal.m4 changes.
432
b7026657
AC		 4332005-01-07 Andrew Cagney <cagney@gnu.org>
434
435 * configure.ac: Rename configure.in, require autoconf 2.59.
436 * configure: Re-generate.
437
379832de
HPN		 4382004-12-08 Hans-Peter Nilsson <hp@axis.com>
439
440 * configure: Regenerate for ../common/aclocal.m4 update.
441
cd62154c
AC		 4422004-09-24 Monika Chaddha <monika@acmet.com>
443
444 Committed by Andrew Cagney.
445 * m16.igen (CMP, CMPI): Fix assembler.
446
e5da76ec
CD		 4472004-08-18 Chris Demetriou <cgd@broadcom.com>
448
449 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
450 * configure: Regenerate.
451
139181c8
CD		 4522004-06-25 Chris Demetriou <cgd@broadcom.com>
453
454 * configure.in (sim_m16_machine): Include mipsIII.
455 * configure: Regenerate.
456
1a27f959
CD		 4572004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
458
459 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
460 from COP0_BADVADDR.
461 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
462
5dbb7b5a
CD		 4632004-04-10 Chris Demetriou <cgd@broadcom.com>
464
465 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
466
14234056
CD		 4672004-04-09 Chris Demetriou <cgd@broadcom.com>
468
469 * mips.igen (check_fmt): Remove.
470 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
471 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
472 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
473 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
474 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
475 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
476 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
477 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
478 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
479 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
480
c6f9085c
CD		 4812004-04-09 Chris Demetriou <cgd@broadcom.com>
482
483 * sb1.igen (check_sbx): New function.
484 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
485
11d66e66 4862004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 487 Richard Sandiford <rsandifo@redhat.com>
488
489 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
490 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
491 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
492 separate implementations for mipsIV and mipsV. Use new macros to
493 determine whether the restrictions apply.
494
b3208fb8
CD		 4952004-01-19 Chris Demetriou <cgd@broadcom.com>
496
497 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
498 (check_mult_hilo): Improve comments.
499 (check_div_hilo): Likewise. Also, fork off a new version
500 to handle mips32/mips64 (since there are no hazards to check
501 in MIPS32/MIPS64).
502
9a1d84fb
CD		 5032003-06-17 Richard Sandiford <rsandifo@redhat.com>
504
505 * mips.igen (do_dmultx): Fix check for negative operands.
506
ae451ac6
ILT		 5072003-05-16 Ian Lance Taylor <ian@airs.com>
508
509 * Makefile.in (SHELL): Make sure this is defined.
510 (various): Use $(SHELL) whenever we invoke move-if-change.
511
dd69d292
CD		 5122003-05-03 Chris Demetriou <cgd@broadcom.com>
513
514 * cp1.c: Tweak attribution slightly.
515 * cp1.h: Likewise.
516 * mdmx.c: Likewise.
517 * mdmx.igen: Likewise.
518 * mips3d.igen: Likewise.
519 * sb1.igen: Likewise.
520
bcd0068e
CD		 5212003-04-15 Richard Sandiford <rsandifo@redhat.com>
522
523 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
524 unsigned operands.
525
6b4a8935
AC		 5262003-02-27 Andrew Cagney <cagney@redhat.com>
527
601da316
AC		 528 * interp.c (sim_open): Rename _bfd to bfd.
529 (sim_create_inferior): Ditto.
6b4a8935 530
d29e330f
CD		 5312003-01-14 Chris Demetriou <cgd@broadcom.com>
532
533 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
534
a2353a08
CD		 5352003-01-14 Chris Demetriou <cgd@broadcom.com>
536
537 * mips.igen (EI, DI): Remove.
538
80551777
CD		 5392003-01-05 Richard Sandiford <rsandifo@redhat.com>
540
541 * Makefile.in (tmp-run-multi): Fix mips16 filter.
542
4c54fc26
CD		 5432003-01-04 Richard Sandiford <rsandifo@redhat.com>
544 Andrew Cagney <ac131313@redhat.com>
545 Gavin Romig-Koch <gavin@redhat.com>
546 Graydon Hoare <graydon@redhat.com>
547 Aldy Hernandez <aldyh@redhat.com>
548 Dave Brolley <brolley@redhat.com>
549 Chris Demetriou <cgd@broadcom.com>
550
551 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
552 (sim_mach_default): New variable.
553 (mips64vr-*-*, mips64vrel-*-*): New configurations.
554 Add a new simulator generator, MULTI.
555 * configure: Regenerate.
556 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
557 (multi-run.o): New dependency.
558 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
559 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
560 (tmp-multi): Combine them.
561 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
562 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
563 (distclean-extra): New rule.
564 * sim-main.h: Include bfd.h.
565 (MIPS_MACH): New macro.
566 * mips.igen (vr4120, vr5400, vr5500): New models.
567 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
568 * vr.igen: Replace with new version.
569
e6c674b8
CD		 5702003-01-04 Chris Demetriou <cgd@broadcom.com>
571
572 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
573 * configure: Regenerate.
574
28f50ac8
CD		 5752002-12-31 Chris Demetriou <cgd@broadcom.com>
576
577 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
578 * mips.igen: Remove all invocations of check_branch_bug and
579 mark_branch_bug.
580
5071ffe6
CD		 5812002-12-16 Chris Demetriou <cgd@broadcom.com>
582
583 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
584
06e7837e
CD		 5852002-07-30 Chris Demetriou <cgd@broadcom.com>
586
587 * mips.igen (do_load_double, do_store_double): New functions.
588 (LDC1, SDC1): Rename to...
589 (LDC1b, SDC1b): respectively.
590 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
591
2265c243
MS		 5922002-07-29 Michael Snyder <msnyder@redhat.com>
593
594 * cp1.c (fp_recip2): Modify initialization expression so that
595 GCC will recognize it as constant.
596
a2f8b4f3
CD		 5972002-06-18 Chris Demetriou <cgd@broadcom.com>
598
599 * mdmx.c (SD_): Delete.
600 (Unpredictable): Re-define, for now, to directly invoke
601 unpredictable_action().
602 (mdmx_acc_op): Fix error in .ob immediate handling.
603
b4b6c939
AC		 6042002-06-18 Andrew Cagney <cagney@redhat.com>
605
606 * interp.c (sim_firmware_command): Initialize `address'.
607
c8cca39f
AC		 6082002-06-16 Andrew Cagney <ac131313@redhat.com>
609
610 * configure: Regenerated to track ../common/aclocal.m4 changes.
611
e7e81181
CD		 6122002-06-14 Chris Demetriou <cgd@broadcom.com>
613 Ed Satterthwaite <ehs@broadcom.com>
614
615 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
616 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
617 * mips.igen: Include mips3d.igen.
618 (mips3d): New model name for MIPS-3D ASE instructions.
619 (CVT.W.fmt): Don't use this instruction for word (source) format
620 instructions.
621 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
622 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
623 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
624 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
625 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
626 (RSquareRoot1, RSquareRoot2): New macros.
627 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
628 (fp_rsqrt2): New functions.
629 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
630 * configure: Regenerate.
631
3a2b820e 6322002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 633 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 634
635 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
636 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
637 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
638 (convert): Note that this function is not used for paired-single
639 format conversions.
640 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
641 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
642 (check_fmt_p): Enable paired-single support.
643 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
644 (PUU.PS): New instructions.
645 (CVT.S.fmt): Don't use this instruction for paired-single format
646 destinations.
647 * sim-main.h (FP_formats): New value 'fmt_ps.'
648 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
649 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
650
d18ea9c2
CD		 6512002-06-12 Chris Demetriou <cgd@broadcom.com>
652
653 * mips.igen: Fix formatting of function calls in
654 many FP operations.
655
95fd5cee
CD		 6562002-06-12 Chris Demetriou <cgd@broadcom.com>
657
658 * mips.igen (MOVN, MOVZ): Trace result.
659 (TNEI): Print "tnei" as the opcode name in traces.
660 (CEIL.W): Add disassembly string for traces.
661 (RSQRT.fmt): Make location of disassembly string consistent
662 with other instructions.
663
4f0d55ae
CD		 6642002-06-12 Chris Demetriou <cgd@broadcom.com>
665
666 * mips.igen (X): Delete unused function.
667
3c25f8c7
AC		 6682002-06-08 Andrew Cagney <cagney@redhat.com>
669
670 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
671
f3c08b7e
CD		 6722002-06-07 Chris Demetriou <cgd@broadcom.com>
673 Ed Satterthwaite <ehs@broadcom.com>
674
675 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
676 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
677 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
678 (fp_nmsub): New prototypes.
679 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
680 (NegMultiplySub): New defines.
681 * mips.igen (RSQRT.fmt): Use RSquareRoot().
682 (MADD.D, MADD.S): Replace with...
683 (MADD.fmt): New instruction.
684 (MSUB.D, MSUB.S): Replace with...
685 (MSUB.fmt): New instruction.
686 (NMADD.D, NMADD.S): Replace with...
687 (NMADD.fmt): New instruction.
688 (NMSUB.D, MSUB.S): Replace with...
689 (NMSUB.fmt): New instruction.
690
52714ff9
CD		 6912002-06-07 Chris Demetriou <cgd@broadcom.com>
692 Ed Satterthwaite <ehs@broadcom.com>
693
694 * cp1.c: Fix more comment spelling and formatting.
695 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
696 (denorm_mode): New function.
697 (fpu_unary, fpu_binary): Round results after operation, collect
698 status from rounding operations, and update the FCSR.
699 (convert): Collect status from integer conversions and rounding
700 operations, and update the FCSR. Adjust NaN values that result
701 from conversions. Convert to use sim_io_eprintf rather than
702 fprintf, and remove some debugging code.
703 * cp1.h (fenr_FS): New define.
704
577d8c4b
CD		 7052002-06-07 Chris Demetriou <cgd@broadcom.com>
706
707 * cp1.c (convert): Remove unusable debugging code, and move MIPS
708 rounding mode to sim FP rounding mode flag conversion code into...
709 (rounding_mode): New function.
710
196496ed
CD		 7112002-06-07 Chris Demetriou <cgd@broadcom.com>
712
713 * cp1.c: Clean up formatting of a few comments.
714 (value_fpr): Reformat switch statement.
715
cfe9ea23
CD		 7162002-06-06 Chris Demetriou <cgd@broadcom.com>
717 Ed Satterthwaite <ehs@broadcom.com>
718
719 * cp1.h: New file.
720 * sim-main.h: Include cp1.h.
721 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
722 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
723 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
724 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
725 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
726 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
727 * cp1.c: Don't include sim-fpu.h; already included by
728 sim-main.h. Clean up formatting of some comments.
729 (NaN, Equal, Less): Remove.
730 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
731 (fp_cmp): New functions.
732 * mips.igen (do_c_cond_fmt): Remove.
733 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
734 Compare. Add result tracing.
735 (CxC1): Remove, replace with...
736 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
737 (DMxC1): Remove, replace with...
738 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
739 (MxC1): Remove, replace with...
740 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
741
ee7254b0
CD		 7422002-06-04 Chris Demetriou <cgd@broadcom.com>
743
744 * sim-main.h (FGRIDX): Remove, replace all uses with...
745 (FGR_BASE): New macro.
746 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
747 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
748 (NR_FGR, FGR): Likewise.
749 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
750 * mips.igen: Likewise.
751
d3eb724f
CD		 7522002-06-04 Chris Demetriou <cgd@broadcom.com>
753
754 * cp1.c: Add an FSF Copyright notice to this file.
755
ba46ddd0
CD		 7562002-06-04 Chris Demetriou <cgd@broadcom.com>
757 Ed Satterthwaite <ehs@broadcom.com>
758
759 * cp1.c (Infinity): Remove.
760 * sim-main.h (Infinity): Likewise.
761
762 * cp1.c (fp_unary, fp_binary): New functions.
763 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
764 (fp_sqrt): New functions, implemented in terms of the above.
765 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
766 (Recip, SquareRoot): Remove (replaced by functions above).
767 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
768 (fp_recip, fp_sqrt): New prototypes.
769 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
770 (Recip, SquareRoot): Replace prototypes with #defines which
771 invoke the functions above.
772
18d8a52d
CD		 7732002-06-03 Chris Demetriou <cgd@broadcom.com>
774
775 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
776 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
777 file, remove PARAMS from prototypes.
778 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
779 simulator state arguments.
780 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
781 pass simulator state arguments.
782 * cp1.c (SD): Redefine as CPU_STATE(cpu).
783 (store_fpr, convert): Remove 'sd' argument.
784 (value_fpr): Likewise. Convert to use 'SD' instead.
785
0f154cbd
CD		 7862002-06-03 Chris Demetriou <cgd@broadcom.com>
787
788 * cp1.c (Min, Max): Remove #if 0'd functions.
789 * sim-main.h (Min, Max): Remove.
790
e80fc152
CD		 7912002-06-03 Chris Demetriou <cgd@broadcom.com>
792
793 * cp1.c: fix formatting of switch case and default labels.
794 * interp.c: Likewise.
795 * sim-main.c: Likewise.
796
bad673a9
CD		 7972002-06-03 Chris Demetriou <cgd@broadcom.com>
798
799 * cp1.c: Clean up comments which describe FP formats.
800 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
801
7cbea089
CD		 8022002-06-03 Chris Demetriou <cgd@broadcom.com>
803 Ed Satterthwaite <ehs@broadcom.com>
804
805 * configure.in (mipsisa64sb1*-*-*): New target for supporting
806 Broadcom SiByte SB-1 processor configurations.
807 * configure: Regenerate.
808 * sb1.igen: New file.
809 * mips.igen: Include sb1.igen.
810 (sb1): New model.
811 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
812 * mdmx.igen: Add "sb1" model to all appropriate functions and
813 instructions.
814 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
815 (ob_func, ob_acc): Reference the above.
816 (qh_acc): Adjust to keep the same size as ob_acc.
817 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
818 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
819
909daa82
CD		 8202002-06-03 Chris Demetriou <cgd@broadcom.com>
821
822 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
823
f4f1b9f1
CD		 8242002-06-02 Chris Demetriou <cgd@broadcom.com>
825 Ed Satterthwaite <ehs@broadcom.com>
826
827 * mips.igen (mdmx): New (pseudo-)model.
828 * mdmx.c, mdmx.igen: New files.
829 * Makefile.in (SIM_OBJS): Add mdmx.o.
830 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
831 New typedefs.
832 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
833 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
834 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
835 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
836 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
837 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
838 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
839 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
840 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
841 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
842 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
843 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
844 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
845 (qh_fmtsel): New macros.
846 (_sim_cpu): New member "acc".
847 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
848 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
849
5accf1ff
CD		 8502002-05-01 Chris Demetriou <cgd@broadcom.com>
851
852 * interp.c: Use 'deprecated' rather than 'depreciated.'
853 * sim-main.h: Likewise.
854
402586aa
CD		 8552002-05-01 Chris Demetriou <cgd@broadcom.com>
856
857 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
858 which wouldn't compile anyway.
859 * sim-main.h (unpredictable_action): New function prototype.
860 (Unpredictable): Define to call igen function unpredictable().
861 (NotWordValue): New macro to call igen function not_word_value().
862 (UndefinedResult): Remove.
863 * interp.c (undefined_result): Remove.
864 (unpredictable_action): New function.
865 * mips.igen (not_word_value, unpredictable): New functions.
866 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
867 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
868 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
869 NotWordValue() to check for unpredictable inputs, then
870 Unpredictable() to handle them.
871
c9b9995a
CD		 8722002-02-24 Chris Demetriou <cgd@broadcom.com>
873
874 * mips.igen: Fix formatting of calls to Unpredictable().
875
e1015982
AC		 8762002-04-20 Andrew Cagney <ac131313@redhat.com>
877
878 * interp.c (sim_open): Revert previous change.
879
b882a66b
AO		 8802002-04-18 Alexandre Oliva <aoliva@redhat.com>
881
882 * interp.c (sim_open): Disable chunk of code that wrote code in
883 vector table entries.
884
c429b7dd
CD		 8852002-03-19 Chris Demetriou <cgd@broadcom.com>
886
887 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
888 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
889 unused definitions.
890
37d146fa
CD		 8912002-03-19 Chris Demetriou <cgd@broadcom.com>
892
893 * cp1.c: Fix many formatting issues.
894
07892c0b
CD		 8952002-03-19 Chris G. Demetriou <cgd@broadcom.com>
896
897 * cp1.c (fpu_format_name): New function to replace...
898 (DOFMT): This. Delete, and update all callers.
899 (fpu_rounding_mode_name): New function to replace...
900 (RMMODE): This. Delete, and update all callers.
901
487f79b7
CD		 9022002-03-19 Chris G. Demetriou <cgd@broadcom.com>
903
904 * interp.c: Move FPU support routines from here to...
905 * cp1.c: Here. New file.
906 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
907 (cp1.o): New target.
908
1e799e28
CD		 9092002-03-12 Chris Demetriou <cgd@broadcom.com>
910
911 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
912 * mips.igen (mips32, mips64): New models, add to all instructions
913 and functions as appropriate.
914 (loadstore_ea, check_u64): New variant for model mips64.
915 (check_fmt_p): New variant for models mipsV and mips64, remove
916 mipsV model marking fro other variant.
917 (SLL) Rename to...
918 (SLLa) this.
919 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
920 for mips32 and mips64.
921 (DCLO, DCLZ): New instructions for mips64.
922
82f728db
CD		 9232002-03-07 Chris Demetriou <cgd@broadcom.com>
924
925 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
926 immediate or code as a hex value with the "%#lx" format.
927 (ANDI): Likewise, and fix printed instruction name.
928
b96e7ef1
CD		 9292002-03-05 Chris Demetriou <cgd@broadcom.com>
930
931 * sim-main.h (UndefinedResult, Unpredictable): New macros
932 which currently do nothing.
933
d35d4f70
CD		 9342002-03-05 Chris Demetriou <cgd@broadcom.com>
935
936 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
937 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
938 (status_CU3): New definitions.
939
940 * sim-main.h (ExceptionCause): Add new values for MIPS32
941 and MIPS64: MDMX, MCheck, CacheErr. Update comments
942 for DebugBreakPoint and NMIReset to note their status in
943 MIPS32 and MIPS64.
944 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
945 (SignalExceptionCacheErr): New exception macros.
946
3ad6f714
CD		 9472002-03-05 Chris Demetriou <cgd@broadcom.com>
948
949 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
950 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
951 is always enabled.
952 (SignalExceptionCoProcessorUnusable): Take as argument the
953 unusable coprocessor number.
954
86b77b47
CD		 9552002-03-05 Chris Demetriou <cgd@broadcom.com>
956
957 * mips.igen: Fix formatting of all SignalException calls.
958
97a88e93 9592002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 960
961 * sim-main.h (SIGNEXTEND): Remove.
962
97a88e93 9632002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 964
965 * mips.igen: Remove gencode comment from top of file, fix
966 spelling in another comment.
967
97a88e93 9682002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 969
970 * mips.igen (check_fmt, check_fmt_p): New functions to check
971 whether specific floating point formats are usable.
972 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
973 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
974 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
975 Use the new functions.
976 (do_c_cond_fmt): Remove format checks...
977 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
978
97a88e93 9792002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 980
981 * mips.igen: Fix formatting of check_fpu calls.
982
41774c9d
CD		 9832002-03-03 Chris Demetriou <cgd@broadcom.com>
984
985 * mips.igen (FLOOR.L.fmt): Store correct destination register.
986
4a0bd876
CD		 9872002-03-03 Chris Demetriou <cgd@broadcom.com>
988
989 * mips.igen: Remove whitespace at end of lines.
990
09297648
CD		 9912002-03-02 Chris Demetriou <cgd@broadcom.com>
992
993 * mips.igen (loadstore_ea): New function to do effective
994 address calculations.
995 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
996 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
997 CACHE): Use loadstore_ea to do effective address computations.
998
043b7057
CD		 9992002-03-02 Chris Demetriou <cgd@broadcom.com>
1000
1001 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1002 * mips.igen (LL, CxC1, MxC1): Likewise.
1003
c1e8ada4
CD		 10042002-03-02 Chris Demetriou <cgd@broadcom.com>
1005
1006 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1007 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1008 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1009 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1010 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1011 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1012 Don't split opcode fields by hand, use the opcode field values
1013 provided by igen.
1014
3e1dca16
CD		 10152002-03-01 Chris Demetriou <cgd@broadcom.com>
1016
1017 * mips.igen (do_divu): Fix spacing.
1018
1019 * mips.igen (do_dsllv): Move to be right before DSLLV,
1020 to match the rest of the do_<shift> functions.
1021
fff8d27d
CD		 10222002-03-01 Chris Demetriou <cgd@broadcom.com>
1023
1024 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1025 DSRL32, do_dsrlv): Trace inputs and results.
1026
0d3e762b
CD		 10272002-03-01 Chris Demetriou <cgd@broadcom.com>
1028
1029 * mips.igen (CACHE): Provide instruction-printing string.
1030
1031 * interp.c (signal_exception): Comment tokens after #endif.
1032
eb5fcf93
CD		 10332002-02-28 Chris Demetriou <cgd@broadcom.com>
1034
1035 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1036 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1037 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1038 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1039 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1040 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1041 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1042 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1043
bb22bd7d
CD		 10442002-02-28 Chris Demetriou <cgd@broadcom.com>
1045
1046 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1047 instruction-printing string.
1048 (LWU): Use '64' as the filter flag.
1049
91a177cf
CD		 10502002-02-28 Chris Demetriou <cgd@broadcom.com>
1051
1052 * mips.igen (SDXC1): Fix instruction-printing string.
1053
387f484a
CD		 10542002-02-28 Chris Demetriou <cgd@broadcom.com>
1055
1056 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1057 filter flags "32,f".
1058
3d81f391
CD		 10592002-02-27 Chris Demetriou <cgd@broadcom.com>
1060
1061 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1062 as the filter flag.
1063
af5107af
CD		 10642002-02-27 Chris Demetriou <cgd@broadcom.com>
1065
1066 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1067 add a comma) so that it more closely match the MIPS ISA
1068 documentation opcode partitioning.
1069 (PREF): Put useful names on opcode fields, and include
1070 instruction-printing string.
1071
ca971540
CD		 10722002-02-27 Chris Demetriou <cgd@broadcom.com>
1073
1074 * mips.igen (check_u64): New function which in the future will
1075 check whether 64-bit instructions are usable and signal an
1076 exception if not. Currently a no-op.
1077 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1078 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1079 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1080 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1081
1082 * mips.igen (check_fpu): New function which in the future will
1083 check whether FPU instructions are usable and signal an exception
1084 if not. Currently a no-op.
1085 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1086 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1087 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1088 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1089 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1090 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1091 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1092 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1093
1c47a468
CD		 10942002-02-27 Chris Demetriou <cgd@broadcom.com>
1095
1096 * mips.igen (do_load_left, do_load_right): Move to be immediately
1097 following do_load.
1098 (do_store_left, do_store_right): Move to be immediately following
1099 do_store.
1100
603a98e7
CD		 11012002-02-27 Chris Demetriou <cgd@broadcom.com>
1102
1103 * mips.igen (mipsV): New model name. Also, add it to
1104 all instructions and functions where it is appropriate.
1105
c5d00cc7
CD		 11062002-02-18 Chris Demetriou <cgd@broadcom.com>
1107
1108 * mips.igen: For all functions and instructions, list model
1109 names that support that instruction one per line.
1110
074e9cb8
CD		 11112002-02-11 Chris Demetriou <cgd@broadcom.com>
1112
1113 * mips.igen: Add some additional comments about supported
1114 models, and about which instructions go where.
1115 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1116 order as is used in the rest of the file.
1117
9805e229
CD		 11182002-02-11 Chris Demetriou <cgd@broadcom.com>
1119
1120 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1121 indicating that ALU32_END or ALU64_END are there to check
1122 for overflow.
1123 (DADD): Likewise, but also remove previous comment about
1124 overflow checking.
1125
f701dad2
CD		 11262002-02-10 Chris Demetriou <cgd@broadcom.com>
1127
1128 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1129 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1130 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1131 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1132 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1133 fields (i.e., add and move commas) so that they more closely
1134 match the MIPS ISA documentation opcode partitioning.
1135
11362002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1137
1138 * mips.igen (ADDI): Print immediate value.
1139 (BREAK): Print code.
1140 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1141 (SLL): Print "nop" specially, and don't run the code
1142 that does the shift for the "nop" case.
1143
9e52972e
FF		 11442001-11-17 Fred Fish <fnf@redhat.com>
1145
1146 * sim-main.h (float_operation): Move enum declaration outside
1147 of _sim_cpu struct declaration.
1148
c0efbca4
JB		 11492001-04-12 Jim Blandy <jimb@redhat.com>
1150
1151 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1152 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1153 set of the FCSR.
1154 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1155 PENDING_FILL, and you can get the intended effect gracefully by
1156 calling PENDING_SCHED directly.
1157
fb891446
BE		 11582001-02-23 Ben Elliston <bje@redhat.com>
1159
1160 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1161 already defined elsewhere.
1162
8030f857
BE		 11632001-02-19 Ben Elliston <bje@redhat.com>
1164
1165 * sim-main.h (sim_monitor): Return an int.
1166 * interp.c (sim_monitor): Add return values.
1167 (signal_exception): Handle error conditions from sim_monitor.
1168
56b48a7a
CD		 11692001-02-08 Ben Elliston <bje@redhat.com>
1170
1171 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1172 (store_memory): Likewise, pass cia to sim_core_write*.
1173
d3ee60d9
FCE		 11742000-10-19 Frank Ch. Eigler <fche@redhat.com>
1175
1176 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1177 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1178
071da002
AC		 1179Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1180
1181 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1182 * Makefile.in: Don't delete *.igen when cleaning directory.
1183
a28c02cd
AC		 1184Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * m16.igen (break): Call SignalException not sim_engine_halt.
1187
80ee11fa
AC		 1188Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1189
1190 From Jason Eckhardt:
1191 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1192
673388c0
AC		 1193Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1194
1195 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1196
4c0deff4
NC		 11972000-05-24 Michael Hayes <mhayes@cygnus.com>
1198
1199 * mips.igen (do_dmultx): Fix typo.
1200
eb2d80b4
AC		 1201Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1202
1203 * configure: Regenerated to track ../common/aclocal.m4 changes.
1204
dd37a34b
AC		 1205Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1206
1207 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1208
4c0deff4
NC		 12092000-04-12 Frank Ch. Eigler <fche@redhat.com>
1210
1211 * sim-main.h (GPR_CLEAR): Define macro.
1212
e30db738
AC		 1213Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1214
1215 * interp.c (decode_coproc): Output long using %lx and not %s.
1216
cb7450ea
FCE		 12172000-03-21 Frank Ch. Eigler <fche@redhat.com>
1218
1219 * interp.c (sim_open): Sort & extend dummy memory regions for
1220 --board=jmr3904 for eCos.
1221
a3027dd7
FCE		 12222000-03-02 Frank Ch. Eigler <fche@redhat.com>
1223
1224 * configure: Regenerated.
1225
1226Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1227
1228 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1229 calls, conditional on the simulator being in verbose mode.
1230
dfcd3bfb
JM		 1231Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1232
1233 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1234 cache don't get ReservedInstruction traps.
1235
c2d11a7d
JM		 12361999-11-29 Mark Salter <msalter@cygnus.com>
1237
1238 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1239 to clear status bits in sdisr register. This is how the hardware works.
1240
1241 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1242 being used by cygmon.
1243
4ce44c66
JM		 12441999-11-11 Andrew Haley <aph@cygnus.com>
1245
1246 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1247 instructions.
1248
cff3e48b
JM		 1249Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1250
1251 * mips.igen (MULT): Correct previous mis-applied patch.
1252
d4f3574e
SS		 1253Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1254
1255 * mips.igen (delayslot32): Handle sequence like
1256 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1257 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1258 (MULT): Actually pass the third register...
1259
12601999-09-03 Mark Salter <msalter@cygnus.com>
1261
1262 * interp.c (sim_open): Added more memory aliases for additional
1263 hardware being touched by cygmon on jmr3904 board.
1264
1265Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1266
1267 * configure: Regenerated to track ../common/aclocal.m4 changes.
1268
a0b3c4fd
JM		 1269Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1270
1271 * interp.c (sim_store_register): Handle case where client - GDB -
1272 specifies that a 4 byte register is 8 bytes in size.
1273 (sim_fetch_register): Ditto.
1274
adf40b2e
JM		 12751999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1276
1277 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1278 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1279 (idt_monitor_base): Base address for IDT monitor traps.
1280 (pmon_monitor_base): Ditto for PMON.
1281 (lsipmon_monitor_base): Ditto for LSI PMON.
1282 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1283 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1284 (sim_firmware_command): New function.
1285 (mips_option_handler): Call it for OPTION_FIRMWARE.
1286 (sim_open): Allocate memory for idt_monitor region. If "--board"
1287 option was given, add no monitor by default. Add BREAK hooks only if
1288 monitors are also there.
1289
43e526b9
JM		 1290Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1291
1292 * interp.c (sim_monitor): Flush output before reading input.
1293
1294Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1295
1296 * tconfig.in (SIM_HANDLES_LMA): Always define.
1297
1298Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1299
1300 From Mark Salter <msalter@cygnus.com>:
1301 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1302 (sim_open): Add setup for BSP board.
1303
9846de1b
JM		 1304Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1305
1306 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1307 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1308 them as unimplemented.
1309
cd0fc7c3
SS		 13101999-05-08 Felix Lee <flee@cygnus.com>
1311
1312 * configure: Regenerated to track ../common/aclocal.m4 changes.
1313
7a292a7a
SS		 13141999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1315
1316 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1317
1318Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1319
1320 * configure.in: Any mips64vr5*-*-* target should have
1321 -DTARGET_ENABLE_FR=1.
1322 (default_endian): Any mips64vr*el-*-* target should default to
1323 LITTLE_ENDIAN.
1324 * configure: Re-generate.
1325
13261999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1327
1328 * mips.igen (ldl): Extend from _16_, not 32.
1329
1330Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1331
1332 * interp.c (sim_store_register): Force registers written to by GDB
1333 into an un-interpreted state.
1334
c906108c
SS		 13351999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1336
1337 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1338 CPU, start periodic background I/O polls.
1339 (tx3904sio_poll): New function: periodic I/O poller.
1340
13411998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1342
1343 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1344
1345Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1346
1347 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1348 case statement.
1349
13501998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1351
1352 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1353 (load_word): Call SIM_CORE_SIGNAL hook on error.
1354 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1355 starting. For exception dispatching, pass PC instead of NULL_CIA.
1356 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1357 * sim-main.h (COP0_BADVADDR): Define.
1358 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1359 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1360 (_sim_cpu): Add exc_* fields to store register value snapshots.
1361 * mips.igen (*): Replace memory-related SignalException* calls
1362 with references to SIM_CORE_SIGNAL hook.
1363
1364 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1365 fix.
1366 * sim-main.c (*): Minor warning cleanups.
1367
13681998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1369
1370 * m16.igen (DADDIU5): Correct type-o.
1371
1372Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1373
1374 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1375 variables.
1376
1377Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1378
1379 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1380 to include path.
1381 (interp.o): Add dependency on itable.h
1382 (oengine.c, gencode): Delete remaining references.
1383 (BUILT_SRC_FROM_GEN): Clean up.
1384
13851998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1386
1387 * vr4run.c: New.
1388 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1389 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1390 tmp-run-hack) : New.
1391 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1392 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1393 Drop the "64" qualifier to get the HACK generator working.
1394 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1395 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1396 qualifier to get the hack generator working.
1397 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1398 (DSLL): Use do_dsll.
1399 (DSLLV): Use do_dsllv.
1400 (DSRA): Use do_dsra.
1401 (DSRL): Use do_dsrl.
1402 (DSRLV): Use do_dsrlv.
1403 (BC1): Move *vr4100 to get the HACK generator working.
1404 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1405 get the HACK generator working.
1406 (MACC) Rename to get the HACK generator working.
1407 (DMACC,MACCS,DMACCS): Add the 64.
1408
14091998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1410
1411 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1412 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1413
14141998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1415
1416 * mips/interp.c (DEBUG): Cleanups.
1417
14181998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1419
1420 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1421 (tx3904sio_tickle): fflush after a stdout character output.
1422
14231998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1424
1425 * interp.c (sim_close): Uninstall modules.
1426
1427Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1428
1429 * sim-main.h, interp.c (sim_monitor): Change to global
1430 function.
1431
1432Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1433
1434 * configure.in (vr4100): Only include vr4100 instructions in
1435 simulator.
1436 * configure: Re-generate.
1437 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1438
1439Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1440
1441 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1442 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1443 true alternative.
1444
1445 * configure.in (sim_default_gen, sim_use_gen): Replace with
1446 sim_gen.
1447 (--enable-sim-igen): Delete config option. Always using IGEN.
1448 * configure: Re-generate.
1449
1450 * Makefile.in (gencode): Kill, kill, kill.
1451 * gencode.c: Ditto.
1452
1453Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1456 bit mips16 igen simulator.
1457 * configure: Re-generate.
1458
1459 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1460 as part of vr4100 ISA.
1461 * vr.igen: Mark all instructions as 64 bit only.
1462
1463Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1464
1465 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1466 Pacify GCC.
1467
1468Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1469
1470 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1471 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1472 * configure: Re-generate.
1473
1474 * m16.igen (BREAK): Define breakpoint instruction.
1475 (JALX32): Mark instruction as mips16 and not r3900.
1476 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1477
1478 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1479
1480Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1481
1482 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1483 insn as a debug breakpoint.
1484
1485 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1486 pending.slot_size.
1487 (PENDING_SCHED): Clean up trace statement.
1488 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1489 (PENDING_FILL): Delay write by only one cycle.
1490 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1491
1492 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1493 of pending writes.
1494 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1495 32 & 64.
1496 (pending_tick): Move incrementing of index to FOR statement.
1497 (pending_tick): Only update PENDING_OUT after a write has occured.
1498
1499 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1500 build simulator.
1501 * configure: Re-generate.
1502
1503 * interp.c (sim_engine_run OLD): Delete explicit call to
1504 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1505
1506Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1507
1508 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1509 interrupt level number to match changed SignalExceptionInterrupt
1510 macro.
1511
1512Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1513
1514 * interp.c: #include "itable.h" if WITH_IGEN.
1515 (get_insn_name): New function.
1516 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1517 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1518
1519Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1520
1521 * configure: Rebuilt to inhale new common/aclocal.m4.
1522
1523Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1524
1525 * dv-tx3904sio.c: Include sim-assert.h.
1526
1527Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1528
1529 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1530 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1531 Reorganize target-specific sim-hardware checks.
1532 * configure: rebuilt.
1533 * interp.c (sim_open): For tx39 target boards, set
1534 OPERATING_ENVIRONMENT, add tx3904sio devices.
1535 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1536 ROM executables. Install dv-sockser into sim-modules list.
1537
1538 * dv-tx3904irc.c: Compiler warning clean-up.
1539 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1540 frequent hw-trace messages.
1541
1542Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1543
1544 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1545
1546Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1549
1550 * vr.igen: New file.
1551 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1552 * mips.igen: Define vr4100 model. Include vr.igen.
1553Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1554
1555 * mips.igen (check_mf_hilo): Correct check.
1556
1557Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1558
1559 * sim-main.h (interrupt_event): Add prototype.
1560
1561 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1562 register_ptr, register_value.
1563 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1564
1565 * sim-main.h (tracefh): Make extern.
1566
1567Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1568
1569 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1570 Reduce unnecessarily high timer event frequency.
1571 * dv-tx3904cpu.c: Ditto for interrupt event.
1572
1573Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1574
1575 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1576 to allay warnings.
1577 (interrupt_event): Made non-static.
1578
1579 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1580 interchange of configuration values for external vs. internal
1581 clock dividers.
1582
1583Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1584
1585 * mips.igen (BREAK): Moved code to here for
1586 simulator-reserved break instructions.
1587 * gencode.c (build_instruction): Ditto.
1588 * interp.c (signal_exception): Code moved from here. Non-
1589 reserved instructions now use exception vector, rather
1590 than halting sim.
1591 * sim-main.h: Moved magic constants to here.
1592
1593Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1594
1595 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1596 register upon non-zero interrupt event level, clear upon zero
1597 event value.
1598 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1599 by passing zero event value.
1600 (*_io_{read,write}_buffer): Endianness fixes.
1601 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1602 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1603
1604 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1605 serial I/O and timer module at base address 0xFFFF0000.
1606
1607Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1608
1609 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1610 and BigEndianCPU.
1611
1612Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1613
1614 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1615 parts.
1616 * configure: Update.
1617
1618Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1619
1620 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1621 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1622 * configure.in: Include tx3904tmr in hw_device list.
1623 * configure: Rebuilt.
1624 * interp.c (sim_open): Instantiate three timer instances.
1625 Fix address typo of tx3904irc instance.
1626
1627Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1628
1629 * interp.c (signal_exception): SystemCall exception now uses
1630 the exception vector.
1631
1632Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1633
1634 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1635 to allay warnings.
1636
1637Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1638
1639 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1640
1641Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1642
1643 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1644
1645 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1646 sim-main.h. Declare a struct hw_descriptor instead of struct
1647 hw_device_descriptor.
1648
1649Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1652 right bits and then re-align left hand bytes to correct byte
1653 lanes. Fix incorrect computation in do_store_left when loading
1654 bytes from second word.
1655
1656Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1657
1658 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1659 * interp.c (sim_open): Only create a device tree when HW is
1660 enabled.
1661
1662 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1663 * interp.c (signal_exception): Ditto.
1664
1665Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1666
1667 * gencode.c: Mark BEGEZALL as LIKELY.
1668
1669Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1670
1671 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1672 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1673
1674Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1675
1676 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1677 modules. Recognize TX39 target with "mips*tx39" pattern.
1678 * configure: Rebuilt.
1679 * sim-main.h (*): Added many macros defining bits in
1680 TX39 control registers.
1681 (SignalInterrupt): Send actual PC instead of NULL.
1682 (SignalNMIReset): New exception type.
1683 * interp.c (board): New variable for future use to identify
1684 a particular board being simulated.
1685 (mips_option_handler,mips_options): Added "--board" option.
1686 (interrupt_event): Send actual PC.
1687 (sim_open): Make memory layout conditional on board setting.
1688 (signal_exception): Initial implementation of hardware interrupt
1689 handling. Accept another break instruction variant for simulator
1690 exit.
1691 (decode_coproc): Implement RFE instruction for TX39.
1692 (mips.igen): Decode RFE instruction as such.
1693 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1694 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1695 bbegin to implement memory map.
1696 * dv-tx3904cpu.c: New file.
1697 * dv-tx3904irc.c: New file.
1698
1699Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1700
1701 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1702
1703Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1704
1705 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1706 with calls to check_div_hilo.
1707
1708Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1709
1710 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1711 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1712 Add special r3900 version of do_mult_hilo.
1713 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1714 with calls to check_mult_hilo.
1715 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1716 with calls to check_div_hilo.
1717
1718Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1719
1720 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1721 Document a replacement.
1722
1723Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1724
1725 * interp.c (sim_monitor): Make mon_printf work.
1726
1727Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1728
1729 * sim-main.h (INSN_NAME): New arg `cpu'.
1730
1731Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1732
1733 * configure: Regenerated to track ../common/aclocal.m4 changes.
1734
1735Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1736
1737 * configure: Regenerated to track ../common/aclocal.m4 changes.
1738 * config.in: Ditto.
1739
1740Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1741
1742 * acconfig.h: New file.
1743 * configure.in: Reverted change of Apr 24; use sinclude again.
1744
1745Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1746
1747 * configure: Regenerated to track ../common/aclocal.m4 changes.
1748 * config.in: Ditto.
1749
1750Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1751
1752 * configure.in: Don't call sinclude.
1753
1754Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1755
1756 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1757
1758Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1759
1760 * mips.igen (ERET): Implement.
1761
1762 * interp.c (decode_coproc): Return sign-extended EPC.
1763
1764 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1765
1766 * interp.c (signal_exception): Do not ignore Trap.
1767 (signal_exception): On TRAP, restart at exception address.
1768 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1769 (signal_exception): Update.
1770 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1771 so that TRAP instructions are caught.
1772
1773Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774
1775 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1776 contains HI/LO access history.
1777 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1778 (HIACCESS, LOACCESS): Delete, replace with
1779 (HIHISTORY, LOHISTORY): New macros.
1780 (CHECKHILO): Delete all, moved to mips.igen
1781
1782 * gencode.c (build_instruction): Do not generate checks for
1783 correct HI/LO register usage.
1784
1785 * interp.c (old_engine_run): Delete checks for correct HI/LO
1786 register usage.
1787
1788 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1789 check_mf_cycles): New functions.
1790 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1791 do_divu, domultx, do_mult, do_multu): Use.
1792
1793 * tx.igen ("madd", "maddu"): Use.
1794
1795Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1796
1797 * mips.igen (DSRAV): Use function do_dsrav.
1798 (SRAV): Use new function do_srav.
1799
1800 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1801 (B): Sign extend 11 bit immediate.
1802 (EXT-B*): Shift 16 bit immediate left by 1.
1803 (ADDIU*): Don't sign extend immediate value.
1804
1805Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1806
1807 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1808
1809 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1810 functions.
1811
1812 * mips.igen (delayslot32, nullify_next_insn): New functions.
1813 (m16.igen): Always include.
1814 (do_*): Add more tracing.
1815
1816 * m16.igen (delayslot16): Add NIA argument, could be called by a
1817 32 bit MIPS16 instruction.
1818
1819 * interp.c (ifetch16): Move function from here.
1820 * sim-main.c (ifetch16): To here.
1821
1822 * sim-main.c (ifetch16, ifetch32): Update to match current
1823 implementations of LH, LW.
1824 (signal_exception): Don't print out incorrect hex value of illegal
1825 instruction.
1826
1827Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1828
1829 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1830 instruction.
1831
1832 * m16.igen: Implement MIPS16 instructions.
1833
1834 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1835 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1836 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1837 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1838 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1839 bodies of corresponding code from 32 bit insn to these. Also used
1840 by MIPS16 versions of functions.
1841
1842 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1843 (IMEM16): Drop NR argument from macro.
1844
1845Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1846
1847 * Makefile.in (SIM_OBJS): Add sim-main.o.
1848
1849 * sim-main.h (address_translation, load_memory, store_memory,
1850 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1851 as INLINE_SIM_MAIN.
1852 (pr_addr, pr_uword64): Declare.
1853 (sim-main.c): Include when H_REVEALS_MODULE_P.
1854
1855 * interp.c (address_translation, load_memory, store_memory,
1856 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1857 from here.
1858 * sim-main.c: To here. Fix compilation problems.
1859
1860 * configure.in: Enable inlining.
1861 * configure: Re-config.
1862
1863Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1864
1865 * configure: Regenerated to track ../common/aclocal.m4 changes.
1866
1867Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * mips.igen: Include tx.igen.
1870 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1871 * tx.igen: New file, contains MADD and MADDU.
1872
1873 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1874 the hardwired constant `7'.
1875 (store_memory): Ditto.
1876 (LOADDRMASK): Move definition to sim-main.h.
1877
1878 mips.igen (MTC0): Enable for r3900.
1879 (ADDU): Add trace.
1880
1881 mips.igen (do_load_byte): Delete.
1882 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1883 do_store_right): New functions.
1884 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1885
1886 configure.in: Let the tx39 use igen again.
1887 configure: Update.
1888
1889Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1892 not an address sized quantity. Return zero for cache sizes.
1893
1894Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1895
1896 * mips.igen (r3900): r3900 does not support 64 bit integer
1897 operations.
1898
1899Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1900
1901 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1902 than igen one.
1903 * configure : Rebuild.
1904
1905Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1906
1907 * configure: Regenerated to track ../common/aclocal.m4 changes.
1908
1909Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1910
1911 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1912
1913Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1914
1915 * configure: Regenerated to track ../common/aclocal.m4 changes.
1916 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1917
1918Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1919
1920 * configure: Regenerated to track ../common/aclocal.m4 changes.
1921
1922Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1923
1924 * interp.c (Max, Min): Comment out functions. Not yet used.
1925
1926Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1927
1928 * configure: Regenerated to track ../common/aclocal.m4 changes.
1929
1930Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1931
1932 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1933 configurable settings for stand-alone simulator.
1934
1935 * configure.in: Added X11 search, just in case.
1936
1937 * configure: Regenerated.
1938
1939Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1940
1941 * interp.c (sim_write, sim_read, load_memory, store_memory):
1942 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1943
1944Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1945
1946 * sim-main.h (GETFCC): Return an unsigned value.
1947
1948Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1949
1950 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1951 (DADD): Result destination is RD not RT.
1952
1953Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1954
1955 * sim-main.h (HIACCESS, LOACCESS): Always define.
1956
1957 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1958
1959 * interp.c (sim_info): Delete.
1960
1961Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1962
1963 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1964 (mips_option_handler): New argument `cpu'.
1965 (sim_open): Update call to sim_add_option_table.
1966
1967Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1968
1969 * mips.igen (CxC1): Add tracing.
1970
1971Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1972
1973 * sim-main.h (Max, Min): Declare.
1974
1975 * interp.c (Max, Min): New functions.
1976
1977 * mips.igen (BC1): Add tracing.
1978
1979Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1980
1981 * interp.c Added memory map for stack in vr4100
1982
1983Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1984
1985 * interp.c (load_memory): Add missing "break"'s.
1986
1987Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * interp.c (sim_store_register, sim_fetch_register): Pass in
1990 length parameter. Return -1.
1991
1992Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1993
1994 * interp.c: Added hardware init hook, fixed warnings.
1995
1996Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1997
1998 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1999
2000Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2001
2002 * interp.c (ifetch16): New function.
2003
2004 * sim-main.h (IMEM32): Rename IMEM.
2005 (IMEM16_IMMED): Define.
2006 (IMEM16): Define.
2007 (DELAY_SLOT): Update.
2008
2009 * m16run.c (sim_engine_run): New file.
2010
2011 * m16.igen: All instructions except LB.
2012 (LB): Call do_load_byte.
2013 * mips.igen (do_load_byte): New function.
2014 (LB): Call do_load_byte.
2015
2016 * mips.igen: Move spec for insn bit size and high bit from here.
2017 * Makefile.in (tmp-igen, tmp-m16): To here.
2018
2019 * m16.dc: New file, decode mips16 instructions.
2020
2021 * Makefile.in (SIM_NO_ALL): Define.
2022 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2023
2024Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2025
2026 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2027 point unit to 32 bit registers.
2028 * configure: Re-generate.
2029
2030Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2031
2032 * configure.in (sim_use_gen): Make IGEN the default simulator
2033 generator for generic 32 and 64 bit mips targets.
2034 * configure: Re-generate.
2035
2036Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2037
2038 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2039 bitsize.
2040
2041 * interp.c (sim_fetch_register, sim_store_register): Read/write
2042 FGR from correct location.
2043 (sim_open): Set size of FGR's according to
2044 WITH_TARGET_FLOATING_POINT_BITSIZE.
2045
2046 * sim-main.h (FGR): Store floating point registers in a separate
2047 array.
2048
2049Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2050
2051 * configure: Regenerated to track ../common/aclocal.m4 changes.
2052
2053Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2054
2055 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2056
2057 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2058
2059 * interp.c (pending_tick): New function. Deliver pending writes.
2060
2061 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2062 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2063 it can handle mixed sized quantites and single bits.
2064
2065Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2066
2067 * interp.c (oengine.h): Do not include when building with IGEN.
2068 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2069 (sim_info): Ditto for PROCESSOR_64BIT.
2070 (sim_monitor): Replace ut_reg with unsigned_word.
2071 (*): Ditto for t_reg.
2072 (LOADDRMASK): Define.
2073 (sim_open): Remove defunct check that host FP is IEEE compliant,
2074 using software to emulate floating point.
2075 (value_fpr, ...): Always compile, was conditional on HASFPU.
2076
2077Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2080 size.
2081
2082 * interp.c (SD, CPU): Define.
2083 (mips_option_handler): Set flags in each CPU.
2084 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2085 (sim_close): Do not clear STATE, deleted anyway.
2086 (sim_write, sim_read): Assume CPU zero's vm should be used for
2087 data transfers.
2088 (sim_create_inferior): Set the PC for all processors.
2089 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2090 argument.
2091 (mips16_entry): Pass correct nr of args to store_word, load_word.
2092 (ColdReset): Cold reset all cpu's.
2093 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2094 (sim_monitor, load_memory, store_memory, signal_exception): Use
2095 `CPU' instead of STATE_CPU.
2096
2097
2098 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2099 SD or CPU_.
2100
2101 * sim-main.h (signal_exception): Add sim_cpu arg.
2102 (SignalException*): Pass both SD and CPU to signal_exception.
2103 * interp.c (signal_exception): Update.
2104
2105 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2106 Ditto
2107 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2108 address_translation): Ditto
2109 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2110
2111Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2112
2113 * configure: Regenerated to track ../common/aclocal.m4 changes.
2114
2115Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2118
2119 * mips.igen (model): Map processor names onto BFD name.
2120
2121 * sim-main.h (CPU_CIA): Delete.
2122 (SET_CIA, GET_CIA): Define
2123
2124Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2127 regiser.
2128
2129 * configure.in (default_endian): Configure a big-endian simulator
2130 by default.
2131 * configure: Re-generate.
2132
2133Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2134
2135 * configure: Regenerated to track ../common/aclocal.m4 changes.
2136
2137Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2138
2139 * interp.c (sim_monitor): Handle Densan monitor outbyte
2140 and inbyte functions.
2141
21421997-12-29 Felix Lee <flee@cygnus.com>
2143
2144 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2145
2146Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2147
2148 * Makefile.in (tmp-igen): Arrange for $zero to always be
2149 reset to zero after every instruction.
2150
2151Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2152
2153 * configure: Regenerated to track ../common/aclocal.m4 changes.
2154 * config.in: Ditto.
2155
2156Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2157
2158 * mips.igen (MSUB): Fix to work like MADD.
2159 * gencode.c (MSUB): Similarly.
2160
2161Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2162
2163 * configure: Regenerated to track ../common/aclocal.m4 changes.
2164
2165Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2166
2167 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2168
2169Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2170
2171 * sim-main.h (sim-fpu.h): Include.
2172
2173 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2174 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2175 using host independant sim_fpu module.
2176
2177Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * interp.c (signal_exception): Report internal errors with SIGABRT
2180 not SIGQUIT.
2181
2182 * sim-main.h (C0_CONFIG): New register.
2183 (signal.h): No longer include.
2184
2185 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2186
2187Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2188
2189 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2190
2191Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2192
2193 * mips.igen: Tag vr5000 instructions.
2194 (ANDI): Was missing mipsIV model, fix assembler syntax.
2195 (do_c_cond_fmt): New function.
2196 (C.cond.fmt): Handle mips I-III which do not support CC field
2197 separatly.
2198 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2199 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2200 in IV3.2 spec.
2201 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2202 vr5000 which saves LO in a GPR separatly.
2203
2204 * configure.in (enable-sim-igen): For vr5000, select vr5000
2205 specific instructions.
2206 * configure: Re-generate.
2207
2208Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2211
2212 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2213 fmt_uninterpreted_64 bit cases to switch. Convert to
2214 fmt_formatted,
2215
2216 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2217
2218 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2219 as specified in IV3.2 spec.
2220 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2221
2222Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2223
2224 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2225 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2226 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2227 PENDING_FILL versions of instructions. Simplify.
2228 (X): New function.
2229 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2230 instructions.
2231 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2232 a signed value.
2233 (MTHI, MFHI): Disable code checking HI-LO.
2234
2235 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2236 global.
2237 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2238
2239Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2240
2241 * gencode.c (build_mips16_operands): Replace IPC with cia.
2242
2243 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2244 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2245 IPC to `cia'.
2246 (UndefinedResult): Replace function with macro/function
2247 combination.
2248 (sim_engine_run): Don't save PC in IPC.
2249
2250 * sim-main.h (IPC): Delete.
2251
2252
2253 * interp.c (signal_exception, store_word, load_word,
2254 address_translation, load_memory, store_memory, cache_op,
2255 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2256 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2257 current instruction address - cia - argument.
2258 (sim_read, sim_write): Call address_translation directly.
2259 (sim_engine_run): Rename variable vaddr to cia.
2260 (signal_exception): Pass cia to sim_monitor
2261
2262 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2263 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2264 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2265
2266 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2267 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2268 SIM_ASSERT.
2269
2270 * interp.c (signal_exception): Pass restart address to
2271 sim_engine_restart.
2272
2273 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2274 idecode.o): Add dependency.
2275
2276 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2277 Delete definitions
2278 (DELAY_SLOT): Update NIA not PC with branch address.
2279 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2280
2281 * mips.igen: Use CIA not PC in branch calculations.
2282 (illegal): Call SignalException.
2283 (BEQ, ADDIU): Fix assembler.
2284
2285Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2286
2287 * m16.igen (JALX): Was missing.
2288
2289 * configure.in (enable-sim-igen): New configuration option.
2290 * configure: Re-generate.
2291
2292 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2293
2294 * interp.c (load_memory, store_memory): Delete parameter RAW.
2295 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2296 bypassing {load,store}_memory.
2297
2298 * sim-main.h (ByteSwapMem): Delete definition.
2299
2300 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2301
2302 * interp.c (sim_do_command, sim_commands): Delete mips specific
2303 commands. Handled by module sim-options.
2304
2305 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2306 (WITH_MODULO_MEMORY): Define.
2307
2308 * interp.c (sim_info): Delete code printing memory size.
2309
2310 * interp.c (mips_size): Nee sim_size, delete function.
2311 (power2): Delete.
2312 (monitor, monitor_base, monitor_size): Delete global variables.
2313 (sim_open, sim_close): Delete code creating monitor and other
2314 memory regions. Use sim-memopts module, via sim_do_commandf, to
2315 manage memory regions.
2316 (load_memory, store_memory): Use sim-core for memory model.
2317
2318 * interp.c (address_translation): Delete all memory map code
2319 except line forcing 32 bit addresses.
2320
2321Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2322
2323 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2324 trace options.
2325
2326 * interp.c (logfh, logfile): Delete globals.
2327 (sim_open, sim_close): Delete code opening & closing log file.
2328 (mips_option_handler): Delete -l and -n options.
2329 (OPTION mips_options): Ditto.
2330
2331 * interp.c (OPTION mips_options): Rename option trace to dinero.
2332 (mips_option_handler): Update.
2333
2334Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2335
2336 * interp.c (fetch_str): New function.
2337 (sim_monitor): Rewrite using sim_read & sim_write.
2338 (sim_open): Check magic number.
2339 (sim_open): Write monitor vectors into memory using sim_write.
2340 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2341 (sim_read, sim_write): Simplify - transfer data one byte at a
2342 time.
2343 (load_memory, store_memory): Clarify meaning of parameter RAW.
2344
2345 * sim-main.h (isHOST): Defete definition.
2346 (isTARGET): Mark as depreciated.
2347 (address_translation): Delete parameter HOST.
2348
2349 * interp.c (address_translation): Delete parameter HOST.
2350
2351Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2352
2353 * mips.igen:
2354
2355 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2356 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2357
2358Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2359
2360 * mips.igen: Add model filter field to records.
2361
2362Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2365
2366 interp.c (sim_engine_run): Do not compile function sim_engine_run
2367 when WITH_IGEN == 1.
2368
2369 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2370 target architecture.
2371
2372 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2373 igen. Replace with configuration variables sim_igen_flags /
2374 sim_m16_flags.
2375
2376 * m16.igen: New file. Copy mips16 insns here.
2377 * mips.igen: From here.
2378
2379Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2380
2381 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2382 to top.
2383 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2384
2385Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2386
2387 * gencode.c (build_instruction): Follow sim_write's lead in using
2388 BigEndianMem instead of !ByteSwapMem.
2389
2390Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2391
2392 * configure.in (sim_gen): Dependent on target, select type of
2393 generator. Always select old style generator.
2394
2395 configure: Re-generate.
2396
2397 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2398 targets.
2399 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2400 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2401 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2402 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2403 SIM_@sim_gen@_*, set by autoconf.
2404
2405Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2406
2407 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2408
2409 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2410 CURRENT_FLOATING_POINT instead.
2411
2412 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2413 (address_translation): Raise exception InstructionFetch when
2414 translation fails and isINSTRUCTION.
2415
2416 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2417 sim_engine_run): Change type of of vaddr and paddr to
2418 address_word.
2419 (address_translation, prefetch, load_memory, store_memory,
2420 cache_op): Change type of vAddr and pAddr to address_word.
2421
2422 * gencode.c (build_instruction): Change type of vaddr and paddr to
2423 address_word.
2424
2425Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2426
2427 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2428 macro to obtain result of ALU op.
2429
2430Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2431
2432 * interp.c (sim_info): Call profile_print.
2433
2434Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2437
2438 * sim-main.h (WITH_PROFILE): Do not define, defined in
2439 common/sim-config.h. Use sim-profile module.
2440 (simPROFILE): Delete defintion.
2441
2442 * interp.c (PROFILE): Delete definition.
2443 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2444 (sim_close): Delete code writing profile histogram.
2445 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2446 Delete.
2447 (sim_engine_run): Delete code profiling the PC.
2448
2449Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2450
2451 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2452
2453 * interp.c (sim_monitor): Make register pointers of type
2454 unsigned_word*.
2455
2456 * sim-main.h: Make registers of type unsigned_word not
2457 signed_word.
2458
2459Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2460
2461 * interp.c (sync_operation): Rename from SyncOperation, make
2462 global, add SD argument.
2463 (prefetch): Rename from Prefetch, make global, add SD argument.
2464 (decode_coproc): Make global.
2465
2466 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2467
2468 * gencode.c (build_instruction): Generate DecodeCoproc not
2469 decode_coproc calls.
2470
2471 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2472 (SizeFGR): Move to sim-main.h
2473 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2474 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2475 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2476 sim-main.h.
2477 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2478 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2479 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2480 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2481 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2482 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2483
2484 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2485 exception.
2486 (sim-alu.h): Include.
2487 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2488 (sim_cia): Typedef to instruction_address.
2489
2490Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2491
2492 * Makefile.in (interp.o): Rename generated file engine.c to
2493 oengine.c.
2494
2495 * interp.c: Update.
2496
2497Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2500
2501Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * gencode.c (build_instruction): For "FPSQRT", output correct
2504 number of arguments to Recip.
2505
2506Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2507
2508 * Makefile.in (interp.o): Depends on sim-main.h
2509
2510 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2511
2512 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2513 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2514 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2515 STATE, DSSTATE): Define
2516 (GPR, FGRIDX, ..): Define.
2517
2518 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2519 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2520 (GPR, FGRIDX, ...): Delete macros.
2521
2522 * interp.c: Update names to match defines from sim-main.h
2523
2524Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2525
2526 * interp.c (sim_monitor): Add SD argument.
2527 (sim_warning): Delete. Replace calls with calls to
2528 sim_io_eprintf.
2529 (sim_error): Delete. Replace calls with sim_io_error.
2530 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2531 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2532 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2533 argument.
2534 (mips_size): Rename from sim_size. Add SD argument.
2535
2536 * interp.c (simulator): Delete global variable.
2537 (callback): Delete global variable.
2538 (mips_option_handler, sim_open, sim_write, sim_read,
2539 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2540 sim_size,sim_monitor): Use sim_io_* not callback->*.
2541 (sim_open): ZALLOC simulator struct.
2542 (PROFILE): Do not define.
2543
2544Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2545
2546 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2547 support.h with corresponding code.
2548
2549 * sim-main.h (word64, uword64), support.h: Move definition to
2550 sim-main.h.
2551 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2552
2553 * support.h: Delete
2554 * Makefile.in: Update dependencies
2555 * interp.c: Do not include.
2556
2557Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2558
2559 * interp.c (address_translation, load_memory, store_memory,
2560 cache_op): Rename to from AddressTranslation et.al., make global,
2561 add SD argument
2562
2563 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2564 CacheOp): Define.
2565
2566 * interp.c (SignalException): Rename to signal_exception, make
2567 global.
2568
2569 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2570
2571 * sim-main.h (SignalException, SignalExceptionInterrupt,
2572 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2573 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2574 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2575 Define.
2576
2577 * interp.c, support.h: Use.
2578
2579Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2582 to value_fpr / store_fpr. Add SD argument.
2583 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2584 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2585
2586 * sim-main.h (ValueFPR, StoreFPR): Define.
2587
2588Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2589
2590 * interp.c (sim_engine_run): Check consistency between configure
2591 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2592 and HASFPU.
2593
2594 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2595 (mips_fpu): Configure WITH_FLOATING_POINT.
2596 (mips_endian): Configure WITH_TARGET_ENDIAN.
2597 * configure: Update.
2598
2599Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2600
2601 * configure: Regenerated to track ../common/aclocal.m4 changes.
2602
2603Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2604
2605 * configure: Regenerated.
2606
2607Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2608
2609 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2610
2611Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2612
2613 * gencode.c (print_igen_insn_models): Assume certain architectures
2614 include all mips* instructions.
2615 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2616 instruction.
2617
2618 * Makefile.in (tmp.igen): Add target. Generate igen input from
2619 gencode file.
2620
2621 * gencode.c (FEATURE_IGEN): Define.
2622 (main): Add --igen option. Generate output in igen format.
2623 (process_instructions): Format output according to igen option.
2624 (print_igen_insn_format): New function.
2625 (print_igen_insn_models): New function.
2626 (process_instructions): Only issue warnings and ignore
2627 instructions when no FEATURE_IGEN.
2628
2629Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630
2631 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2632 MIPS targets.
2633
2634Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2635
2636 * configure: Regenerated to track ../common/aclocal.m4 changes.
2637
2638Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2639
2640 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2641 SIM_RESERVED_BITS): Delete, moved to common.
2642 (SIM_EXTRA_CFLAGS): Update.
2643
2644Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * configure.in: Configure non-strict memory alignment.
2647 * configure: Regenerated to track ../common/aclocal.m4 changes.
2648
2649Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2650
2651 * configure: Regenerated to track ../common/aclocal.m4 changes.
2652
2653Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2654
2655 * gencode.c (SDBBP,DERET): Added (3900) insns.
2656 (RFE): Turn on for 3900.
2657 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2658 (dsstate): Made global.
2659 (SUBTARGET_R3900): Added.
2660 (CANCELDELAYSLOT): New.
2661 (SignalException): Ignore SystemCall rather than ignore and
2662 terminate. Add DebugBreakPoint handling.
2663 (decode_coproc): New insns RFE, DERET; and new registers Debug
2664 and DEPC protected by SUBTARGET_R3900.
2665 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2666 bits explicitly.
2667 * Makefile.in,configure.in: Add mips subtarget option.
2668 * configure: Update.
2669
2670Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2671
2672 * gencode.c: Add r3900 (tx39).
2673
2674
2675Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2676
2677 * gencode.c (build_instruction): Don't need to subtract 4 for
2678 JALR, just 2.
2679
2680Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2681
2682 * interp.c: Correct some HASFPU problems.
2683
2684Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2685
2686 * configure: Regenerated to track ../common/aclocal.m4 changes.
2687
2688Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2689
2690 * interp.c (mips_options): Fix samples option short form, should
2691 be `x'.
2692
2693Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2694
2695 * interp.c (sim_info): Enable info code. Was just returning.
2696
2697Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2698
2699 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2700 MFC0.
2701
2702Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2703
2704 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2705 constants.
2706 (build_instruction): Ditto for LL.
2707
2708Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2709
2710 * configure: Regenerated to track ../common/aclocal.m4 changes.
2711
2712Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2713
2714 * configure: Regenerated to track ../common/aclocal.m4 changes.
2715 * config.in: Ditto.
2716
2717Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2718
2719 * interp.c (sim_open): Add call to sim_analyze_program, update
2720 call to sim_config.
2721
2722Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2723
2724 * interp.c (sim_kill): Delete.
2725 (sim_create_inferior): Add ABFD argument. Set PC from same.
2726 (sim_load): Move code initializing trap handlers from here.
2727 (sim_open): To here.
2728 (sim_load): Delete, use sim-hload.c.
2729
2730 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2731
2732Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733
2734 * configure: Regenerated to track ../common/aclocal.m4 changes.
2735 * config.in: Ditto.
2736
2737Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2738
2739 * interp.c (sim_open): Add ABFD argument.
2740 (sim_load): Move call to sim_config from here.
2741 (sim_open): To here. Check return status.
2742
2743Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2744
2745 * gencode.c (build_instruction): Two arg MADD should
2746 not assign result to $0.
2747
2748Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2749
2750 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2751 * sim/mips/configure.in: Regenerate.
2752
2753Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2754
2755 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2756 signed8, unsigned8 et.al. types.
2757
2758 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2759 hosts when selecting subreg.
2760
2761Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2762
2763 * interp.c (sim_engine_run): Reset the ZERO register to zero
2764 regardless of FEATURE_WARN_ZERO.
2765 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2766
2767Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768
2769 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2770 (SignalException): For BreakPoints ignore any mode bits and just
2771 save the PC.
2772 (SignalException): Always set the CAUSE register.
2773
2774Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775
2776 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2777 exception has been taken.
2778
2779 * interp.c: Implement the ERET and mt/f sr instructions.
2780
2781Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2782
2783 * interp.c (SignalException): Don't bother restarting an
2784 interrupt.
2785
2786Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2787
2788 * interp.c (SignalException): Really take an interrupt.
2789 (interrupt_event): Only deliver interrupts when enabled.
2790
2791Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2792
2793 * interp.c (sim_info): Only print info when verbose.
2794 (sim_info) Use sim_io_printf for output.
2795
2796Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2797
2798 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2799 mips architectures.
2800
2801Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2802
2803 * interp.c (sim_do_command): Check for common commands if a
2804 simulator specific command fails.
2805
2806Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2807
2808 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2809 and simBE when DEBUG is defined.
2810
2811Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2812
2813 * interp.c (interrupt_event): New function. Pass exception event
2814 onto exception handler.
2815
2816 * configure.in: Check for stdlib.h.
2817 * configure: Regenerate.
2818
2819 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2820 variable declaration.
2821 (build_instruction): Initialize memval1.
2822 (build_instruction): Add UNUSED attribute to byte, bigend,
2823 reverse.
2824 (build_operands): Ditto.
2825
2826 * interp.c: Fix GCC warnings.
2827 (sim_get_quit_code): Delete.
2828
2829 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2830 * Makefile.in: Ditto.
2831 * configure: Re-generate.
2832
2833 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2834
2835Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2836
2837 * interp.c (mips_option_handler): New function parse argumes using
2838 sim-options.
2839 (myname): Replace with STATE_MY_NAME.
2840 (sim_open): Delete check for host endianness - performed by
2841 sim_config.
2842 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2843 (sim_open): Move much of the initialization from here.
2844 (sim_load): To here. After the image has been loaded and
2845 endianness set.
2846 (sim_open): Move ColdReset from here.
2847 (sim_create_inferior): To here.
2848 (sim_open): Make FP check less dependant on host endianness.
2849
2850 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2851 run.
2852 * interp.c (sim_set_callbacks): Delete.
2853
2854 * interp.c (membank, membank_base, membank_size): Replace with
2855 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2856 (sim_open): Remove call to callback->init. gdb/run do this.
2857
2858 * interp.c: Update
2859
2860 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2861
2862 * interp.c (big_endian_p): Delete, replaced by
2863 current_target_byte_order.
2864
2865Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2866
2867 * interp.c (host_read_long, host_read_word, host_swap_word,
2868 host_swap_long): Delete. Using common sim-endian.
2869 (sim_fetch_register, sim_store_register): Use H2T.
2870 (pipeline_ticks): Delete. Handled by sim-events.
2871 (sim_info): Update.
2872 (sim_engine_run): Update.
2873
2874Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875
2876 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2877 reason from here.
2878 (SignalException): To here. Signal using sim_engine_halt.
2879 (sim_stop_reason): Delete, moved to common.
2880
2881Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2882
2883 * interp.c (sim_open): Add callback argument.
2884 (sim_set_callbacks): Delete SIM_DESC argument.
2885 (sim_size): Ditto.
2886
2887Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2888
2889 * Makefile.in (SIM_OBJS): Add common modules.
2890
2891 * interp.c (sim_set_callbacks): Also set SD callback.
2892 (set_endianness, xfer_*, swap_*): Delete.
2893 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2894 Change to functions using sim-endian macros.
2895 (control_c, sim_stop): Delete, use common version.
2896 (simulate): Convert into.
2897 (sim_engine_run): This function.
2898 (sim_resume): Delete.
2899
2900 * interp.c (simulation): New variable - the simulator object.
2901 (sim_kind): Delete global - merged into simulation.
2902 (sim_load): Cleanup. Move PC assignment from here.
2903 (sim_create_inferior): To here.
2904
2905 * sim-main.h: New file.
2906 * interp.c (sim-main.h): Include.
2907
2908Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2909
2910 * configure: Regenerated to track ../common/aclocal.m4 changes.
2911
2912Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2913
2914 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2915
2916Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2917
2918 * gencode.c (build_instruction): DIV instructions: check
2919 for division by zero and integer overflow before using
2920 host's division operation.
2921
2922Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2923
2924 * Makefile.in (SIM_OBJS): Add sim-load.o.
2925 * interp.c: #include bfd.h.
2926 (target_byte_order): Delete.
2927 (sim_kind, myname, big_endian_p): New static locals.
2928 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2929 after argument parsing. Recognize -E arg, set endianness accordingly.
2930 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2931 load file into simulator. Set PC from bfd.
2932 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2933 (set_endianness): Use big_endian_p instead of target_byte_order.
2934
2935Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2936
2937 * interp.c (sim_size): Delete prototype - conflicts with
2938 definition in remote-sim.h. Correct definition.
2939
2940Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2941
2942 * configure: Regenerated to track ../common/aclocal.m4 changes.
2943 * config.in: Ditto.
2944
2945Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2946
2947 * interp.c (sim_open): New arg `kind'.
2948
2949 * configure: Regenerated to track ../common/aclocal.m4 changes.
2950
2951Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2952
2953 * configure: Regenerated to track ../common/aclocal.m4 changes.
2954
2955Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2956
2957 * interp.c (sim_open): Set optind to 0 before calling getopt.
2958
2959Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2960
2961 * configure: Regenerated to track ../common/aclocal.m4 changes.
2962
2963Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2964
2965 * interp.c : Replace uses of pr_addr with pr_uword64
2966 where the bit length is always 64 independent of SIM_ADDR.
2967 (pr_uword64) : added.
2968
2969Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2970
2971 * configure: Re-generate.
2972
2973Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2974
2975 * configure: Regenerate to track ../common/aclocal.m4 changes.
2976
2977Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2978
2979 * interp.c (sim_open): New SIM_DESC result. Argument is now
2980 in argv form.
2981 (other sim_*): New SIM_DESC argument.
2982
2983Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2984
2985 * interp.c: Fix printing of addresses for non-64-bit targets.
2986 (pr_addr): Add function to print address based on size.
2987
2988Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2989
2990 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2991
2992Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2993
2994 * gencode.c (build_mips16_operands): Correct computation of base
2995 address for extended PC relative instruction.
2996
2997Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2998
2999 * interp.c (mips16_entry): Add support for floating point cases.
3000 (SignalException): Pass floating point cases to mips16_entry.
3001 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3002 registers.
3003 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3004 or fmt_word.
3005 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3006 and then set the state to fmt_uninterpreted.
3007 (COP_SW): Temporarily set the state to fmt_word while calling
3008 ValueFPR.
3009
3010Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3011
3012 * gencode.c (build_instruction): The high order may be set in the
3013 comparison flags at any ISA level, not just ISA 4.
3014
3015Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3016
3017 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3018 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3019 * configure.in: sinclude ../common/aclocal.m4.
3020 * configure: Regenerated.
3021
3022Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3023
3024 * configure: Rebuild after change to aclocal.m4.
3025
3026Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3027
3028 * configure configure.in Makefile.in: Update to new configure
3029 scheme which is more compatible with WinGDB builds.
3030 * configure.in: Improve comment on how to run autoconf.
3031 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3032 * Makefile.in: Use autoconf substitution to install common
3033 makefile fragment.
3034
3035Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3036
3037 * gencode.c (build_instruction): Use BigEndianCPU instead of
3038 ByteSwapMem.
3039
3040Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3041
3042 * interp.c (sim_monitor): Make output to stdout visible in
3043 wingdb's I/O log window.
3044
3045Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3046
3047 * support.h: Undo previous change to SIGTRAP
3048 and SIGQUIT values.
3049
3050Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3051
3052 * interp.c (store_word, load_word): New static functions.
3053 (mips16_entry): New static function.
3054 (SignalException): Look for mips16 entry and exit instructions.
3055 (simulate): Use the correct index when setting fpr_state after
3056 doing a pending move.
3057
3058Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3059
3060 * interp.c: Fix byte-swapping code throughout to work on
3061 both little- and big-endian hosts.
3062
3063Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3064
3065 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3066 with gdb/config/i386/xm-windows.h.
3067
3068Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3069
3070 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3071 that messes up arithmetic shifts.
3072
3073Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3074
3075 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3076 SIGTRAP and SIGQUIT for _WIN32.
3077
3078Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3079
3080 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3081 force a 64 bit multiplication.
3082 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3083 destination register is 0, since that is the default mips16 nop
3084 instruction.
3085
3086Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3087
3088 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3089 (build_endian_shift): Don't check proc64.
3090 (build_instruction): Always set memval to uword64. Cast op2 to
3091 uword64 when shifting it left in memory instructions. Always use
3092 the same code for stores--don't special case proc64.
3093
3094 * gencode.c (build_mips16_operands): Fix base PC value for PC
3095 relative operands.
3096 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3097 jal instruction.
3098 * interp.c (simJALDELAYSLOT): Define.
3099 (JALDELAYSLOT): Define.
3100 (INDELAYSLOT, INJALDELAYSLOT): Define.
3101 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3102
3103Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3104
3105 * interp.c (sim_open): add flush_cache as a PMON routine
3106 (sim_monitor): handle flush_cache by ignoring it
3107
3108Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3109
3110 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3111 BigEndianMem.
3112 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3113 (BigEndianMem): Rename to ByteSwapMem and change sense.
3114 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3115 BigEndianMem references to !ByteSwapMem.
3116 (set_endianness): New function, with prototype.
3117 (sim_open): Call set_endianness.
3118 (sim_info): Use simBE instead of BigEndianMem.
3119 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3120 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3121 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3122 ifdefs, keeping the prototype declaration.
3123 (swap_word): Rewrite correctly.
3124 (ColdReset): Delete references to CONFIG. Delete endianness related
3125 code; moved to set_endianness.
3126
3127Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3128
3129 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3130 * interp.c (CHECKHILO): Define away.
3131 (simSIGINT): New macro.
3132 (membank_size): Increase from 1MB to 2MB.
3133 (control_c): New function.
3134 (sim_resume): Rename parameter signal to signal_number. Add local
3135 variable prev. Call signal before and after simulate.
3136 (sim_stop_reason): Add simSIGINT support.
3137 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3138 functions always.
3139 (sim_warning): Delete call to SignalException. Do call printf_filtered
3140 if logfh is NULL.
3141 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3142 a call to sim_warning.
3143
3144Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3145
3146 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3147 16 bit instructions.
3148
3149Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3150
3151 Add support for mips16 (16 bit MIPS implementation):
3152 * gencode.c (inst_type): Add mips16 instruction encoding types.
3153 (GETDATASIZEINSN): Define.
3154 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3155 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3156 mtlo.
3157 (MIPS16_DECODE): New table, for mips16 instructions.
3158 (bitmap_val): New static function.
3159 (struct mips16_op): Define.
3160 (mips16_op_table): New table, for mips16 operands.
3161 (build_mips16_operands): New static function.
3162 (process_instructions): If PC is odd, decode a mips16
3163 instruction. Break out instruction handling into new
3164 build_instruction function.
3165 (build_instruction): New static function, broken out of
3166 process_instructions. Check modifiers rather than flags for SHIFT
3167 bit count and m[ft]{hi,lo} direction.
3168 (usage): Pass program name to fprintf.
3169 (main): Remove unused variable this_option_optind. Change
3170 ``*loptarg++'' to ``loptarg++''.
3171 (my_strtoul): Parenthesize && within ||.
3172 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3173 (simulate): If PC is odd, fetch a 16 bit instruction, and
3174 increment PC by 2 rather than 4.
3175 * configure.in: Add case for mips16*-*-*.
3176 * configure: Rebuild.
3177
3178Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3179
3180 * interp.c: Allow -t to enable tracing in standalone simulator.
3181 Fix garbage output in trace file and error messages.
3182
3183Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3184
3185 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3186 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3187 * configure.in: Simplify using macros in ../common/aclocal.m4.
3188 * configure: Regenerated.
3189 * tconfig.in: New file.
3190
3191Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3192
3193 * interp.c: Fix bugs in 64-bit port.
3194 Use ansi function declarations for msvc compiler.
3195 Initialize and test file pointer in trace code.
3196 Prevent duplicate definition of LAST_EMED_REGNUM.
3197
3198Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3199
3200 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3201
3202Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3203
3204 * interp.c (SignalException): Check for explicit terminating
3205 breakpoint value.
3206 * gencode.c: Pass instruction value through SignalException()
3207 calls for Trap, Breakpoint and Syscall.
3208
3209Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3210
3211 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3212 only used on those hosts that provide it.
3213 * configure.in: Add sqrt() to list of functions to be checked for.
3214 * config.in: Re-generated.
3215 * configure: Re-generated.
3216
3217Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3218
3219 * gencode.c (process_instructions): Call build_endian_shift when
3220 expanding STORE RIGHT, to fix swr.
3221 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3222 clear the high bits.
3223 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3224 Fix float to int conversions to produce signed values.
3225
3226Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3227
3228 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3229 (process_instructions): Correct handling of nor instruction.
3230 Correct shift count for 32 bit shift instructions. Correct sign
3231 extension for arithmetic shifts to not shift the number of bits in
3232 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3233 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3234 Fix madd.
3235 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3236 It's OK to have a mult follow a mult. What's not OK is to have a
3237 mult follow an mfhi.
3238 (Convert): Comment out incorrect rounding code.
3239
3240Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3241
3242 * interp.c (sim_monitor): Improved monitor printf
3243 simulation. Tidied up simulator warnings, and added "--log" option
3244 for directing warning message output.
3245 * gencode.c: Use sim_warning() rather than WARNING macro.
3246
3247Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3248
3249 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3250 getopt1.o, rather than on gencode.c. Link objects together.
3251 Don't link against -liberty.
3252 (gencode.o, getopt.o, getopt1.o): New targets.
3253 * gencode.c: Include <ctype.h> and "ansidecl.h".
3254 (AND): Undefine after including "ansidecl.h".
3255 (ULONG_MAX): Define if not defined.
3256 (OP_*): Don't define macros; now defined in opcode/mips.h.
3257 (main): Call my_strtoul rather than strtoul.
3258 (my_strtoul): New static function.
3259
3260Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3261
3262 * gencode.c (process_instructions): Generate word64 and uword64
3263 instead of `long long' and `unsigned long long' data types.
3264 * interp.c: #include sysdep.h to get signals, and define default
3265 for SIGBUS.
3266 * (Convert): Work around for Visual-C++ compiler bug with type
3267 conversion.
3268 * support.h: Make things compile under Visual-C++ by using
3269 __int64 instead of `long long'. Change many refs to long long
3270 into word64/uword64 typedefs.
3271
3272Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3273
3274 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3275 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3276 (docdir): Removed.
3277 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3278 (AC_PROG_INSTALL): Added.
3279 (AC_PROG_CC): Moved to before configure.host call.
3280 * configure: Rebuilt.
3281
3282Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3283
3284 * configure.in: Define @SIMCONF@ depending on mips target.
3285 * configure: Rebuild.
3286 * Makefile.in (run): Add @SIMCONF@ to control simulator
3287 construction.
3288 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3289 * interp.c: Remove some debugging, provide more detailed error
3290 messages, update memory accesses to use LOADDRMASK.
3291
3292Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3293
3294 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3295 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3296 stamp-h.
3297 * configure: Rebuild.
3298 * config.in: New file, generated by autoheader.
3299 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3300 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3301 HAVE_ANINT and HAVE_AINT, as appropriate.
3302 * Makefile.in (run): Use @LIBS@ rather than -lm.
3303 (interp.o): Depend upon config.h.
3304 (Makefile): Just rebuild Makefile.
3305 (clean): Remove stamp-h.
3306 (mostlyclean): Make the same as clean, not as distclean.
3307 (config.h, stamp-h): New targets.
3308
3309Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3310
3311 * interp.c (ColdReset): Fix boolean test. Make all simulator
3312 globals static.
3313
3314Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3315
3316 * interp.c (xfer_direct_word, xfer_direct_long,
3317 swap_direct_word, swap_direct_long, xfer_big_word,
3318 xfer_big_long, xfer_little_word, xfer_little_long,
3319 swap_word,swap_long): Added.
3320 * interp.c (ColdReset): Provide function indirection to
3321 host<->simulated_target transfer routines.
3322 * interp.c (sim_store_register, sim_fetch_register): Updated to
3323 make use of indirected transfer routines.
3324
3325Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3326
3327 * gencode.c (process_instructions): Ensure FP ABS instruction
3328 recognised.
3329 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3330 system call support.
3331
3332Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3333
3334 * interp.c (sim_do_command): Complain if callback structure not
3335 initialised.
3336
3337Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3338
3339 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3340 support for Sun hosts.
3341 * Makefile.in (gencode): Ensure the host compiler and libraries
3342 used for cross-hosted build.
3343
3344Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3345
3346 * interp.c, gencode.c: Some more (TODO) tidying.
3347
3348Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3349
3350 * gencode.c, interp.c: Replaced explicit long long references with
3351 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3352 * support.h (SET64LO, SET64HI): Macros added.
3353
3354Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3355
3356 * configure: Regenerate with autoconf 2.7.
3357
3358Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3359
3360 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3361 * support.h: Remove superfluous "1" from #if.
3362 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3363
3364Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3365
3366 * interp.c (StoreFPR): Control UndefinedResult() call on
3367 WARN_RESULT manifest.
3368
3369Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3370
3371 * gencode.c: Tidied instruction decoding, and added FP instruction
3372 support.
3373
3374 * interp.c: Added dineroIII, and BSD profiling support. Also
3375 run-time FP handling.
3376
3377Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3378
3379 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3380 gencode.c, interp.c, support.h: created.
A mirror of the official binutils-gdb repository