]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mips/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: drop duplicate header checks
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
5cddc23a
MF		 12015-03-14 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac (AC_CHECK_HEADERS): Delete.
4 * aclocal.m4, configure: Regenerate.
5
2974be62
AM		 62014-08-19 Alan Modra <amodra@gmail.com>
7
8 * configure: Regenerate.
9
faa743bb
RM		 102014-08-15 Roland McGrath <mcgrathr@google.com>
11
12 * configure: Regenerate.
13 * config.in: Regenerate.
14
1a8a700e
MF		 152014-03-04 Mike Frysinger <vapier@gentoo.org>
16
17 * configure: Regenerate.
18
bf3d9781
AM		 192013-09-23 Alan Modra <amodra@gmail.com>
20
21 * configure: Regenerate.
22
31e6ad7d
MF		 232013-06-03 Mike Frysinger <vapier@gentoo.org>
24
25 * aclocal.m4, configure: Regenerate.
26
d3685d60
TT		 272013-05-10 Freddie Chopin <freddie_chopin@op.pl>
28
29 * configure: Rebuild.
30
1517bd27
MF		 312013-03-26 Mike Frysinger <vapier@gentoo.org>
32
33 * configure: Regenerate.
34
3be31516
JS		 352013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
36
37 * configure.ac: Address use of dv-sockser.o.
38 * tconfig.in: Conditionalize use of dv_sockser_install.
39 * configure: Regenerated.
40 * config.in: Regenerated.
41
37cb8f8e
SE		 422012-10-04 Chao-ying Fu <fu@mips.com>
43 Steve Ellcey <sellcey@mips.com>
44
45 * mips/mips3264r2.igen (rdhwr): New.
46
87c8644f
JS		 472012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
48
49 * configure.ac: Always link against dv-sockser.o.
50 * configure: Regenerate.
51
5f3ef9d0
JB		 522012-06-15 Joel Brobecker <brobecker@adacore.com>
53
54 * config.in, configure: Regenerate.
55
a6ff997c
NC		 562012-05-18 Nick Clifton <nickc@redhat.com>
57
58 PR 14072
59 * interp.c: Include config.h before system header files.
60
2232061b
MF		 612012-03-24 Mike Frysinger <vapier@gentoo.org>
62
63 * aclocal.m4, config.in, configure: Regenerate.
64
db2e4d67
MF		 652011-12-03 Mike Frysinger <vapier@gentoo.org>
66
67 * aclocal.m4: New file.
68 * configure: Regenerate.
69
4399a56b
MF		 702011-10-19 Mike Frysinger <vapier@gentoo.org>
71
72 * configure: Regenerate after common/acinclude.m4 update.
73
9c082ca8
MF		 742011-10-17 Mike Frysinger <vapier@gentoo.org>
75
76 * configure.ac: Change include to common/acinclude.m4.
77
6ffe910a
MF		 782011-10-17 Mike Frysinger <vapier@gentoo.org>
79
80 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
81 call. Replace common.m4 include with SIM_AC_COMMON.
82 * configure: Regenerate.
83
31b28250
HPN		 842011-07-08 Hans-Peter Nilsson <hp@axis.com>
85
3faa01e3
HPN		 86 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
87 $(SIM_EXTRA_DEPS).
88 (tmp-mach-multi): Exit early when igen fails.
31b28250 89
2419798b
MF		 902011-07-05 Mike Frysinger <vapier@gentoo.org>
91
92 * interp.c (sim_do_command): Delete.
93
d79fe0d6
MF		 942011-02-14 Mike Frysinger <vapier@gentoo.org>
95
96 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
97 (tx3904sio_fifo_reset): Likewise.
98 * interp.c (sim_monitor): Likewise.
99
5558e7e6
MF		 1002010-04-14 Mike Frysinger <vapier@gentoo.org>
101
102 * interp.c (sim_write): Add const to buffer arg.
103
35aafff4
JB		 1042010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
105
106 * interp.c: Don't include sysdep.h
107
3725885a
RW		 1082010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
109
110 * configure: Regenerate.
111
d6416cdc
RW		 1122009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
113
81ecdfbb
RW		 114 * config.in: Regenerate.
115 * configure: Likewise.
116
d6416cdc
RW		 117 * configure: Regenerate.
118
b5bd9624
HPN		 1192008-07-11 Hans-Peter Nilsson <hp@axis.com>
120
121 * configure: Regenerate to track ../common/common.m4 changes.
122 * config.in: Ditto.
123
6efef468
JM		 1242008-06-06 Vladimir Prus <vladimir@codesourcery.com>
125 Daniel Jacobowitz <dan@codesourcery.com>
126 Joseph Myers <joseph@codesourcery.com>
127
128 * configure: Regenerate.
129
60dc88db
RS		 1302007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
131
132 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
133 that unconditionally allows fmt_ps.
134 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
135 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
136 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
137 filter from 64,f to 32,f.
138 (PREFX): Change filter from 64 to 32.
139 (LDXC1, LUXC1): Provide separate mips32r2 implementations
140 that use do_load_double instead of do_load. Make both LUXC1
141 versions unpredictable if SizeFGR () != 64.
142 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
143 instead of do_store. Remove unused variable. Make both SUXC1
144 versions unpredictable if SizeFGR () != 64.
145
599ca73e
RS		 1462007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
147
148 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
149 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
150 shifts for that case.
151
2525df03
NC		 1522007-09-04 Nick Clifton <nickc@redhat.com>
153
154 * interp.c (options enum): Add OPTION_INFO_MEMORY.
155 (display_mem_info): New static variable.
156 (mips_option_handler): Handle OPTION_INFO_MEMORY.
157 (mips_options): Add info-memory and memory-info.
158 (sim_open): After processing the command line and board
159 specification, check display_mem_info. If it is set then
160 call the real handler for the --memory-info command line
161 switch.
162
35ee6e1e
JB		 1632007-08-24 Joel Brobecker <brobecker@adacore.com>
164
165 * configure.ac: Change license of multi-run.c to GPL version 3.
166 * configure: Regenerate.
167
d5fb0879
RS		 1682007-06-28 Richard Sandiford <richard@codesourcery.com>
169
170 * configure.ac, configure: Revert last patch.
171
2a2ce21b
RS		 1722007-06-26 Richard Sandiford <richard@codesourcery.com>
173
174 * configure.ac (sim_mipsisa3264_configs): New variable.
175 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
176 every configuration support all four targets, using the triplet to
177 determine the default.
178 * configure: Regenerate.
179
efdcccc9
RS		 1802007-06-25 Richard Sandiford <richard@codesourcery.com>
181
0a7692b2 182 * Makefile.in (m16run.o): New rule.
efdcccc9 183
f532a356
TS		 1842007-05-15 Thiemo Seufer <ths@mips.com>
185
186 * mips3264r2.igen (DSHD): Fix compile warning.
187
bfe9c90b
TS		 1882007-05-14 Thiemo Seufer <ths@mips.com>
189
190 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
191 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
192 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
193 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
194 for mips32r2.
195
53f4826b
TS		 1962007-03-01 Thiemo Seufer <ths@mips.com>
197
198 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
199 and mips64.
200
8bf3ddc8
TS		 2012007-02-20 Thiemo Seufer <ths@mips.com>
202
203 * dsp.igen: Update copyright notice.
204 * dsp2.igen: Fix copyright notice.
205
8b082fb1
TS		 2062007-02-20 Thiemo Seufer <ths@mips.com>
207 Chao-Ying Fu <fu@mips.com>
208
209 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
210 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
211 Add dsp2 to sim_igen_machine.
212 * configure: Regenerate.
213 * dsp.igen (do_ph_op): Add MUL support when op = 2.
214 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
215 (mulq_rs.ph): Use do_ph_mulq.
216 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
217 * mips.igen: Add dsp2 model and include dsp2.igen.
218 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
219 for *mips32r2, *mips64r2, *dsp.
220 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
221 for *mips32r2, *mips64r2, *dsp2.
222 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
223
b1004875
TS		 2242007-02-19 Thiemo Seufer <ths@mips.com>
225 Nigel Stephens <nigel@mips.com>
226
227 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
228 jumps with hazard barrier.
229
f8df4c77
TS		 2302007-02-19 Thiemo Seufer <ths@mips.com>
231 Nigel Stephens <nigel@mips.com>
232
233 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
234 after each call to sim_io_write.
235
b1004875 2362007-02-19 Thiemo Seufer <ths@mips.com>
07802d98 237 Nigel Stephens <nigel@mips.com>
b1004875
TS		 238
239 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
240 supported by this simulator.
07802d98
TS		 241 (decode_coproc): Recognise additional CP0 Config registers
242 correctly.
243
14fb6c5a
TS		 2442007-02-19 Thiemo Seufer <ths@mips.com>
245 Nigel Stephens <nigel@mips.com>
246 David Ung <davidu@mips.com>
247
248 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
249 uninterpreted formats. If fmt is one of the uninterpreted types
250 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
251 fmt_word, and fmt_uninterpreted_64 like fmt_long.
252 (store_fpr): When writing an invalid odd register, set the
253 matching even register to fmt_unknown, not the following register.
254 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
255 the the memory window at offset 0 set by --memory-size command
256 line option.
257 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
258 point register.
259 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
260 register.
261 (sim_monitor): When returning the memory size to the MIPS
262 application, use the value in STATE_MEM_SIZE, not an arbitrary
263 hardcoded value.
264 (cop_lw): Don' mess around with FPR_STATE, just pass
265 fmt_uninterpreted_32 to StoreFPR.
266 (cop_sw): Similarly.
267 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
268 (cop_sd): Similarly.
269 * mips.igen (not_word_value): Single version for mips32, mips64
270 and mips16.
271
c8847145
TS		 2722007-02-19 Thiemo Seufer <ths@mips.com>
273 Nigel Stephens <nigel@mips.com>
274
275 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
276 MBytes.
277
4b5d35ee
TS		 2782007-02-17 Thiemo Seufer <ths@mips.com>
279
280 * configure.ac (mips*-sde-elf*): Move in front of generic machine
281 configuration.
282 * configure: Regenerate.
283
3669427c
TS		 2842007-02-17 Thiemo Seufer <ths@mips.com>
285
286 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
287 Add mdmx to sim_igen_machine.
288 (mipsisa64*-*-*): Likewise. Remove dsp.
289 (mipsisa32*-*-*): Remove dsp.
290 * configure: Regenerate.
291
109ad085
TS		 2922007-02-13 Thiemo Seufer <ths@mips.com>
293
294 * configure.ac: Add mips*-sde-elf* target.
295 * configure: Regenerate.
296
921d7ad3
HPN		 2972006-12-21 Hans-Peter Nilsson <hp@axis.com>
298
299 * acconfig.h: Remove.
300 * config.in, configure: Regenerate.
301
02f97da7
TS		 3022006-11-07 Thiemo Seufer <ths@mips.com>
303
304 * dsp.igen (do_w_op): Fix compiler warning.
305
2d2733fc
TS		 3062006-08-29 Thiemo Seufer <ths@mips.com>
307 David Ung <davidu@mips.com>
308
309 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
310 sim_igen_machine.
311 * configure: Regenerate.
312 * mips.igen (model): Add smartmips.
313 (MADDU): Increment ACX if carry.
314 (do_mult): Clear ACX.
315 (ROR,RORV): Add smartmips.
316 (include): Include smartmips.igen.
317 * sim-main.h (ACX): Set to REGISTERS[89].
318 * smartmips.igen: New file.
319
d85c3a10
TS		 3202006-08-29 Thiemo Seufer <ths@mips.com>
321 David Ung <davidu@mips.com>
322
323 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
324 mips3264r2.igen. Add missing dependency rules.
325 * m16e.igen: Support for mips16e save/restore instructions.
326
e85e3205
RE		 3272006-06-13 Richard Earnshaw <rearnsha@arm.com>
328
329 * configure: Regenerated.
330
2f0122dc
DJ		 3312006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
332
333 * configure: Regenerated.
334
20e95c23
DJ		 3352006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
336
337 * configure: Regenerated.
338
69088b17
CF		 3392006-05-15 Chao-ying Fu <fu@mips.com>
340
341 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
342
0275de4e
NC		 3432006-04-18 Nick Clifton <nickc@redhat.com>
344
345 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
346 statement.
347
b3a3ffef
HPN		 3482006-03-29 Hans-Peter Nilsson <hp@axis.com>
349
350 * configure: Regenerate.
351
40a5538e
CF		 3522005-12-14 Chao-ying Fu <fu@mips.com>
353
354 * Makefile.in (SIM_OBJS): Add dsp.o.
355 (dsp.o): New dependency.
356 (IGEN_INCLUDE): Add dsp.igen.
357 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
358 mipsisa64*-*-*): Add dsp to sim_igen_machine.
359 * configure: Regenerate.
360 * mips.igen: Add dsp model and include dsp.igen.
361 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
362 because these instructions are extended in DSP ASE.
363 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
364 adding 6 DSP accumulator registers and 1 DSP control register.
365 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
366 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
367 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
368 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
369 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
370 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
371 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
372 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
373 DSPCR_CCOND_SMASK): New define.
374 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
375 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
376
21d14896
ILT		 3772005-07-08 Ian Lance Taylor <ian@airs.com>
378
379 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
380
b16d63da
DU		 3812005-06-16 David Ung <davidu@mips.com>
382 Nigel Stephens <nigel@mips.com>
383
384 * mips.igen: New mips16e model and include m16e.igen.
385 (check_u64): Add mips16e tag.
386 * m16e.igen: New file for MIPS16e instructions.
387 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
388 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
389 models.
390 * configure: Regenerate.
391
e70cb6cd
CD		 3922005-05-26 David Ung <davidu@mips.com>
393
394 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
395 tags to all instructions which are applicable to the new ISAs.
396 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
397 vr.igen.
398 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
399 instructions.
400 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
401 to mips.igen.
402 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
403 * configure: Regenerate.
404
2b193c4a
MK		 4052005-03-23 Mark Kettenis <kettenis@gnu.org>
406
407 * configure: Regenerate.
408
35695fd6
AC		 4092005-01-14 Andrew Cagney <cagney@gnu.org>
410
411 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
412 explicit call to AC_CONFIG_HEADER.
413 * configure: Regenerate.
414
f0569246
AC		 4152005-01-12 Andrew Cagney <cagney@gnu.org>
416
417 * configure.ac: Update to use ../common/common.m4.
418 * configure: Re-generate.
419
38f48d72
AC		 4202005-01-11 Andrew Cagney <cagney@localhost.localdomain>
421
422 * configure: Regenerated to track ../common/aclocal.m4 changes.
423
b7026657
AC		 4242005-01-07 Andrew Cagney <cagney@gnu.org>
425
426 * configure.ac: Rename configure.in, require autoconf 2.59.
427 * configure: Re-generate.
428
379832de
HPN		 4292004-12-08 Hans-Peter Nilsson <hp@axis.com>
430
431 * configure: Regenerate for ../common/aclocal.m4 update.
432
cd62154c
AC		 4332004-09-24 Monika Chaddha <monika@acmet.com>
434
435 Committed by Andrew Cagney.
436 * m16.igen (CMP, CMPI): Fix assembler.
437
e5da76ec
CD		 4382004-08-18 Chris Demetriou <cgd@broadcom.com>
439
440 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
441 * configure: Regenerate.
442
139181c8
CD		 4432004-06-25 Chris Demetriou <cgd@broadcom.com>
444
445 * configure.in (sim_m16_machine): Include mipsIII.
446 * configure: Regenerate.
447
1a27f959
CD		 4482004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
449
450 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
451 from COP0_BADVADDR.
452 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
453
5dbb7b5a
CD		 4542004-04-10 Chris Demetriou <cgd@broadcom.com>
455
456 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
457
14234056
CD		 4582004-04-09 Chris Demetriou <cgd@broadcom.com>
459
460 * mips.igen (check_fmt): Remove.
461 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
462 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
463 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
464 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
465 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
466 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
467 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
468 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
469 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
470 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
471
c6f9085c
CD		 4722004-04-09 Chris Demetriou <cgd@broadcom.com>
473
474 * sb1.igen (check_sbx): New function.
475 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
476
11d66e66 4772004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 478 Richard Sandiford <rsandifo@redhat.com>
479
480 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
481 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
482 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
483 separate implementations for mipsIV and mipsV. Use new macros to
484 determine whether the restrictions apply.
485
b3208fb8
CD		 4862004-01-19 Chris Demetriou <cgd@broadcom.com>
487
488 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
489 (check_mult_hilo): Improve comments.
490 (check_div_hilo): Likewise. Also, fork off a new version
491 to handle mips32/mips64 (since there are no hazards to check
492 in MIPS32/MIPS64).
493
9a1d84fb
CD		 4942003-06-17 Richard Sandiford <rsandifo@redhat.com>
495
496 * mips.igen (do_dmultx): Fix check for negative operands.
497
ae451ac6
ILT		 4982003-05-16 Ian Lance Taylor <ian@airs.com>
499
500 * Makefile.in (SHELL): Make sure this is defined.
501 (various): Use $(SHELL) whenever we invoke move-if-change.
502
dd69d292
CD		 5032003-05-03 Chris Demetriou <cgd@broadcom.com>
504
505 * cp1.c: Tweak attribution slightly.
506 * cp1.h: Likewise.
507 * mdmx.c: Likewise.
508 * mdmx.igen: Likewise.
509 * mips3d.igen: Likewise.
510 * sb1.igen: Likewise.
511
bcd0068e
CD		 5122003-04-15 Richard Sandiford <rsandifo@redhat.com>
513
514 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
515 unsigned operands.
516
6b4a8935
AC		 5172003-02-27 Andrew Cagney <cagney@redhat.com>
518
601da316
AC		 519 * interp.c (sim_open): Rename _bfd to bfd.
520 (sim_create_inferior): Ditto.
6b4a8935 521
d29e330f
CD		 5222003-01-14 Chris Demetriou <cgd@broadcom.com>
523
524 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
525
a2353a08
CD		 5262003-01-14 Chris Demetriou <cgd@broadcom.com>
527
528 * mips.igen (EI, DI): Remove.
529
80551777
CD		 5302003-01-05 Richard Sandiford <rsandifo@redhat.com>
531
532 * Makefile.in (tmp-run-multi): Fix mips16 filter.
533
4c54fc26
CD		 5342003-01-04 Richard Sandiford <rsandifo@redhat.com>
535 Andrew Cagney <ac131313@redhat.com>
536 Gavin Romig-Koch <gavin@redhat.com>
537 Graydon Hoare <graydon@redhat.com>
538 Aldy Hernandez <aldyh@redhat.com>
539 Dave Brolley <brolley@redhat.com>
540 Chris Demetriou <cgd@broadcom.com>
541
542 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
543 (sim_mach_default): New variable.
544 (mips64vr-*-*, mips64vrel-*-*): New configurations.
545 Add a new simulator generator, MULTI.
546 * configure: Regenerate.
547 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
548 (multi-run.o): New dependency.
549 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
550 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
551 (tmp-multi): Combine them.
552 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
553 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
554 (distclean-extra): New rule.
555 * sim-main.h: Include bfd.h.
556 (MIPS_MACH): New macro.
557 * mips.igen (vr4120, vr5400, vr5500): New models.
558 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
559 * vr.igen: Replace with new version.
560
e6c674b8
CD		 5612003-01-04 Chris Demetriou <cgd@broadcom.com>
562
563 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
564 * configure: Regenerate.
565
28f50ac8
CD		 5662002-12-31 Chris Demetriou <cgd@broadcom.com>
567
568 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
569 * mips.igen: Remove all invocations of check_branch_bug and
570 mark_branch_bug.
571
5071ffe6
CD		 5722002-12-16 Chris Demetriou <cgd@broadcom.com>
573
574 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
575
06e7837e
CD		 5762002-07-30 Chris Demetriou <cgd@broadcom.com>
577
578 * mips.igen (do_load_double, do_store_double): New functions.
579 (LDC1, SDC1): Rename to...
580 (LDC1b, SDC1b): respectively.
581 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
582
2265c243
MS		 5832002-07-29 Michael Snyder <msnyder@redhat.com>
584
585 * cp1.c (fp_recip2): Modify initialization expression so that
586 GCC will recognize it as constant.
587
a2f8b4f3
CD		 5882002-06-18 Chris Demetriou <cgd@broadcom.com>
589
590 * mdmx.c (SD_): Delete.
591 (Unpredictable): Re-define, for now, to directly invoke
592 unpredictable_action().
593 (mdmx_acc_op): Fix error in .ob immediate handling.
594
b4b6c939
AC		 5952002-06-18 Andrew Cagney <cagney@redhat.com>
596
597 * interp.c (sim_firmware_command): Initialize `address'.
598
c8cca39f
AC		 5992002-06-16 Andrew Cagney <ac131313@redhat.com>
600
601 * configure: Regenerated to track ../common/aclocal.m4 changes.
602
e7e81181
CD		 6032002-06-14 Chris Demetriou <cgd@broadcom.com>
604 Ed Satterthwaite <ehs@broadcom.com>
605
606 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
607 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
608 * mips.igen: Include mips3d.igen.
609 (mips3d): New model name for MIPS-3D ASE instructions.
610 (CVT.W.fmt): Don't use this instruction for word (source) format
611 instructions.
612 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
613 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
614 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
615 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
616 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
617 (RSquareRoot1, RSquareRoot2): New macros.
618 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
619 (fp_rsqrt2): New functions.
620 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
621 * configure: Regenerate.
622
3a2b820e 6232002-06-13 Chris Demetriou <cgd@broadcom.com>
eab54952 624 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 625
626 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
627 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
628 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
629 (convert): Note that this function is not used for paired-single
630 format conversions.
631 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
632 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
633 (check_fmt_p): Enable paired-single support.
634 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
635 (PUU.PS): New instructions.
636 (CVT.S.fmt): Don't use this instruction for paired-single format
637 destinations.
638 * sim-main.h (FP_formats): New value 'fmt_ps.'
639 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
640 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
641
d18ea9c2
CD		 6422002-06-12 Chris Demetriou <cgd@broadcom.com>
643
644 * mips.igen: Fix formatting of function calls in
645 many FP operations.
646
95fd5cee
CD		 6472002-06-12 Chris Demetriou <cgd@broadcom.com>
648
649 * mips.igen (MOVN, MOVZ): Trace result.
650 (TNEI): Print "tnei" as the opcode name in traces.
651 (CEIL.W): Add disassembly string for traces.
652 (RSQRT.fmt): Make location of disassembly string consistent
653 with other instructions.
654
4f0d55ae
CD		 6552002-06-12 Chris Demetriou <cgd@broadcom.com>
656
657 * mips.igen (X): Delete unused function.
658
3c25f8c7
AC		 6592002-06-08 Andrew Cagney <cagney@redhat.com>
660
661 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
662
f3c08b7e
CD		 6632002-06-07 Chris Demetriou <cgd@broadcom.com>
664 Ed Satterthwaite <ehs@broadcom.com>
665
666 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
667 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
668 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
669 (fp_nmsub): New prototypes.
670 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
671 (NegMultiplySub): New defines.
672 * mips.igen (RSQRT.fmt): Use RSquareRoot().
673 (MADD.D, MADD.S): Replace with...
674 (MADD.fmt): New instruction.
675 (MSUB.D, MSUB.S): Replace with...
676 (MSUB.fmt): New instruction.
677 (NMADD.D, NMADD.S): Replace with...
678 (NMADD.fmt): New instruction.
679 (NMSUB.D, MSUB.S): Replace with...
680 (NMSUB.fmt): New instruction.
681
52714ff9
CD		 6822002-06-07 Chris Demetriou <cgd@broadcom.com>
683 Ed Satterthwaite <ehs@broadcom.com>
684
685 * cp1.c: Fix more comment spelling and formatting.
686 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
687 (denorm_mode): New function.
688 (fpu_unary, fpu_binary): Round results after operation, collect
689 status from rounding operations, and update the FCSR.
690 (convert): Collect status from integer conversions and rounding
691 operations, and update the FCSR. Adjust NaN values that result
692 from conversions. Convert to use sim_io_eprintf rather than
693 fprintf, and remove some debugging code.
694 * cp1.h (fenr_FS): New define.
695
577d8c4b
CD		 6962002-06-07 Chris Demetriou <cgd@broadcom.com>
697
698 * cp1.c (convert): Remove unusable debugging code, and move MIPS
699 rounding mode to sim FP rounding mode flag conversion code into...
700 (rounding_mode): New function.
701
196496ed
CD		 7022002-06-07 Chris Demetriou <cgd@broadcom.com>
703
704 * cp1.c: Clean up formatting of a few comments.
705 (value_fpr): Reformat switch statement.
706
cfe9ea23
CD		 7072002-06-06 Chris Demetriou <cgd@broadcom.com>
708 Ed Satterthwaite <ehs@broadcom.com>
709
710 * cp1.h: New file.
711 * sim-main.h: Include cp1.h.
712 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
713 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
714 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
715 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
716 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
717 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
718 * cp1.c: Don't include sim-fpu.h; already included by
719 sim-main.h. Clean up formatting of some comments.
720 (NaN, Equal, Less): Remove.
721 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
722 (fp_cmp): New functions.
723 * mips.igen (do_c_cond_fmt): Remove.
724 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
725 Compare. Add result tracing.
726 (CxC1): Remove, replace with...
727 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
728 (DMxC1): Remove, replace with...
729 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
730 (MxC1): Remove, replace with...
731 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
732
ee7254b0
CD		 7332002-06-04 Chris Demetriou <cgd@broadcom.com>
734
735 * sim-main.h (FGRIDX): Remove, replace all uses with...
736 (FGR_BASE): New macro.
737 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
738 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
739 (NR_FGR, FGR): Likewise.
740 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
741 * mips.igen: Likewise.
742
d3eb724f
CD		 7432002-06-04 Chris Demetriou <cgd@broadcom.com>
744
745 * cp1.c: Add an FSF Copyright notice to this file.
746
ba46ddd0
CD		 7472002-06-04 Chris Demetriou <cgd@broadcom.com>
748 Ed Satterthwaite <ehs@broadcom.com>
749
750 * cp1.c (Infinity): Remove.
751 * sim-main.h (Infinity): Likewise.
752
753 * cp1.c (fp_unary, fp_binary): New functions.
754 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
755 (fp_sqrt): New functions, implemented in terms of the above.
756 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
757 (Recip, SquareRoot): Remove (replaced by functions above).
758 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
759 (fp_recip, fp_sqrt): New prototypes.
760 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
761 (Recip, SquareRoot): Replace prototypes with #defines which
762 invoke the functions above.
763
18d8a52d
CD		 7642002-06-03 Chris Demetriou <cgd@broadcom.com>
765
766 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
767 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
768 file, remove PARAMS from prototypes.
769 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
770 simulator state arguments.
771 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
772 pass simulator state arguments.
773 * cp1.c (SD): Redefine as CPU_STATE(cpu).
774 (store_fpr, convert): Remove 'sd' argument.
775 (value_fpr): Likewise. Convert to use 'SD' instead.
776
0f154cbd
CD		 7772002-06-03 Chris Demetriou <cgd@broadcom.com>
778
779 * cp1.c (Min, Max): Remove #if 0'd functions.
780 * sim-main.h (Min, Max): Remove.
781
e80fc152
CD		 7822002-06-03 Chris Demetriou <cgd@broadcom.com>
783
784 * cp1.c: fix formatting of switch case and default labels.
785 * interp.c: Likewise.
786 * sim-main.c: Likewise.
787
bad673a9
CD		 7882002-06-03 Chris Demetriou <cgd@broadcom.com>
789
790 * cp1.c: Clean up comments which describe FP formats.
791 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
792
7cbea089
CD		 7932002-06-03 Chris Demetriou <cgd@broadcom.com>
794 Ed Satterthwaite <ehs@broadcom.com>
795
796 * configure.in (mipsisa64sb1*-*-*): New target for supporting
797 Broadcom SiByte SB-1 processor configurations.
798 * configure: Regenerate.
799 * sb1.igen: New file.
800 * mips.igen: Include sb1.igen.
801 (sb1): New model.
802 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
803 * mdmx.igen: Add "sb1" model to all appropriate functions and
804 instructions.
805 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
806 (ob_func, ob_acc): Reference the above.
807 (qh_acc): Adjust to keep the same size as ob_acc.
808 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
809 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
810
909daa82
CD		 8112002-06-03 Chris Demetriou <cgd@broadcom.com>
812
813 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
814
f4f1b9f1
CD		 8152002-06-02 Chris Demetriou <cgd@broadcom.com>
816 Ed Satterthwaite <ehs@broadcom.com>
817
818 * mips.igen (mdmx): New (pseudo-)model.
819 * mdmx.c, mdmx.igen: New files.
820 * Makefile.in (SIM_OBJS): Add mdmx.o.
821 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
822 New typedefs.
823 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
824 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
825 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
826 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
827 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
828 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
829 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
830 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
831 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
832 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
833 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
834 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
835 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
836 (qh_fmtsel): New macros.
837 (_sim_cpu): New member "acc".
838 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
839 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
840
5accf1ff
CD		 8412002-05-01 Chris Demetriou <cgd@broadcom.com>
842
843 * interp.c: Use 'deprecated' rather than 'depreciated.'
844 * sim-main.h: Likewise.
845
402586aa
CD		 8462002-05-01 Chris Demetriou <cgd@broadcom.com>
847
848 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
849 which wouldn't compile anyway.
850 * sim-main.h (unpredictable_action): New function prototype.
851 (Unpredictable): Define to call igen function unpredictable().
852 (NotWordValue): New macro to call igen function not_word_value().
853 (UndefinedResult): Remove.
854 * interp.c (undefined_result): Remove.
855 (unpredictable_action): New function.
856 * mips.igen (not_word_value, unpredictable): New functions.
857 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
858 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
859 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
860 NotWordValue() to check for unpredictable inputs, then
861 Unpredictable() to handle them.
862
c9b9995a
CD		 8632002-02-24 Chris Demetriou <cgd@broadcom.com>
864
865 * mips.igen: Fix formatting of calls to Unpredictable().
866
e1015982
AC		 8672002-04-20 Andrew Cagney <ac131313@redhat.com>
868
869 * interp.c (sim_open): Revert previous change.
870
b882a66b
AO		 8712002-04-18 Alexandre Oliva <aoliva@redhat.com>
872
873 * interp.c (sim_open): Disable chunk of code that wrote code in
874 vector table entries.
875
c429b7dd
CD		 8762002-03-19 Chris Demetriou <cgd@broadcom.com>
877
878 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
879 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
880 unused definitions.
881
37d146fa
CD		 8822002-03-19 Chris Demetriou <cgd@broadcom.com>
883
884 * cp1.c: Fix many formatting issues.
885
07892c0b
CD		 8862002-03-19 Chris G. Demetriou <cgd@broadcom.com>
887
888 * cp1.c (fpu_format_name): New function to replace...
889 (DOFMT): This. Delete, and update all callers.
890 (fpu_rounding_mode_name): New function to replace...
891 (RMMODE): This. Delete, and update all callers.
892
487f79b7
CD		 8932002-03-19 Chris G. Demetriou <cgd@broadcom.com>
894
895 * interp.c: Move FPU support routines from here to...
896 * cp1.c: Here. New file.
897 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
898 (cp1.o): New target.
899
1e799e28
CD		 9002002-03-12 Chris Demetriou <cgd@broadcom.com>
901
902 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
903 * mips.igen (mips32, mips64): New models, add to all instructions
904 and functions as appropriate.
905 (loadstore_ea, check_u64): New variant for model mips64.
906 (check_fmt_p): New variant for models mipsV and mips64, remove
907 mipsV model marking fro other variant.
908 (SLL) Rename to...
909 (SLLa) this.
910 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
911 for mips32 and mips64.
912 (DCLO, DCLZ): New instructions for mips64.
913
82f728db
CD		 9142002-03-07 Chris Demetriou <cgd@broadcom.com>
915
916 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
917 immediate or code as a hex value with the "%#lx" format.
918 (ANDI): Likewise, and fix printed instruction name.
919
b96e7ef1
CD		 9202002-03-05 Chris Demetriou <cgd@broadcom.com>
921
922 * sim-main.h (UndefinedResult, Unpredictable): New macros
923 which currently do nothing.
924
d35d4f70
CD		 9252002-03-05 Chris Demetriou <cgd@broadcom.com>
926
927 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
928 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
929 (status_CU3): New definitions.
930
931 * sim-main.h (ExceptionCause): Add new values for MIPS32
932 and MIPS64: MDMX, MCheck, CacheErr. Update comments
933 for DebugBreakPoint and NMIReset to note their status in
934 MIPS32 and MIPS64.
935 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
936 (SignalExceptionCacheErr): New exception macros.
937
3ad6f714
CD		 9382002-03-05 Chris Demetriou <cgd@broadcom.com>
939
940 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
941 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
942 is always enabled.
943 (SignalExceptionCoProcessorUnusable): Take as argument the
944 unusable coprocessor number.
945
86b77b47
CD		 9462002-03-05 Chris Demetriou <cgd@broadcom.com>
947
948 * mips.igen: Fix formatting of all SignalException calls.
949
97a88e93 9502002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 951
952 * sim-main.h (SIGNEXTEND): Remove.
953
97a88e93 9542002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 955
956 * mips.igen: Remove gencode comment from top of file, fix
957 spelling in another comment.
958
97a88e93 9592002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 960
961 * mips.igen (check_fmt, check_fmt_p): New functions to check
962 whether specific floating point formats are usable.
963 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
964 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
965 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
966 Use the new functions.
967 (do_c_cond_fmt): Remove format checks...
968 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
969
97a88e93 9702002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 971
972 * mips.igen: Fix formatting of check_fpu calls.
973
41774c9d
CD		 9742002-03-03 Chris Demetriou <cgd@broadcom.com>
975
976 * mips.igen (FLOOR.L.fmt): Store correct destination register.
977
4a0bd876
CD		 9782002-03-03 Chris Demetriou <cgd@broadcom.com>
979
980 * mips.igen: Remove whitespace at end of lines.
981
09297648
CD		 9822002-03-02 Chris Demetriou <cgd@broadcom.com>
983
984 * mips.igen (loadstore_ea): New function to do effective
985 address calculations.
986 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
987 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
988 CACHE): Use loadstore_ea to do effective address computations.
989
043b7057
CD		 9902002-03-02 Chris Demetriou <cgd@broadcom.com>
991
992 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
993 * mips.igen (LL, CxC1, MxC1): Likewise.
994
c1e8ada4
CD		 9952002-03-02 Chris Demetriou <cgd@broadcom.com>
996
997 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
998 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
999 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1000 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1001 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1002 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1003 Don't split opcode fields by hand, use the opcode field values
1004 provided by igen.
1005
3e1dca16
CD		 10062002-03-01 Chris Demetriou <cgd@broadcom.com>
1007
1008 * mips.igen (do_divu): Fix spacing.
1009
1010 * mips.igen (do_dsllv): Move to be right before DSLLV,
1011 to match the rest of the do_<shift> functions.
1012
fff8d27d
CD		 10132002-03-01 Chris Demetriou <cgd@broadcom.com>
1014
1015 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1016 DSRL32, do_dsrlv): Trace inputs and results.
1017
0d3e762b
CD		 10182002-03-01 Chris Demetriou <cgd@broadcom.com>
1019
1020 * mips.igen (CACHE): Provide instruction-printing string.
1021
1022 * interp.c (signal_exception): Comment tokens after #endif.
1023
eb5fcf93
CD		 10242002-02-28 Chris Demetriou <cgd@broadcom.com>
1025
1026 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
1027 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1028 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1029 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1030 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1031 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1032 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
1033 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1034
bb22bd7d
CD		 10352002-02-28 Chris Demetriou <cgd@broadcom.com>
1036
1037 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1038 instruction-printing string.
1039 (LWU): Use '64' as the filter flag.
1040
91a177cf
CD		 10412002-02-28 Chris Demetriou <cgd@broadcom.com>
1042
1043 * mips.igen (SDXC1): Fix instruction-printing string.
1044
387f484a
CD		 10452002-02-28 Chris Demetriou <cgd@broadcom.com>
1046
1047 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1048 filter flags "32,f".
1049
3d81f391
CD		 10502002-02-27 Chris Demetriou <cgd@broadcom.com>
1051
1052 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1053 as the filter flag.
1054
af5107af
CD		 10552002-02-27 Chris Demetriou <cgd@broadcom.com>
1056
1057 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1058 add a comma) so that it more closely match the MIPS ISA
1059 documentation opcode partitioning.
1060 (PREF): Put useful names on opcode fields, and include
1061 instruction-printing string.
1062
ca971540
CD		 10632002-02-27 Chris Demetriou <cgd@broadcom.com>
1064
1065 * mips.igen (check_u64): New function which in the future will
1066 check whether 64-bit instructions are usable and signal an
1067 exception if not. Currently a no-op.
1068 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1069 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1070 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1071 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1072
1073 * mips.igen (check_fpu): New function which in the future will
1074 check whether FPU instructions are usable and signal an exception
1075 if not. Currently a no-op.
1076 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1077 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1078 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1079 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1080 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1081 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1082 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1083 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1084
1c47a468
CD		 10852002-02-27 Chris Demetriou <cgd@broadcom.com>
1086
1087 * mips.igen (do_load_left, do_load_right): Move to be immediately
1088 following do_load.
1089 (do_store_left, do_store_right): Move to be immediately following
1090 do_store.
1091
603a98e7
CD		 10922002-02-27 Chris Demetriou <cgd@broadcom.com>
1093
1094 * mips.igen (mipsV): New model name. Also, add it to
1095 all instructions and functions where it is appropriate.
1096
c5d00cc7
CD		 10972002-02-18 Chris Demetriou <cgd@broadcom.com>
1098
1099 * mips.igen: For all functions and instructions, list model
1100 names that support that instruction one per line.
1101
074e9cb8
CD		 11022002-02-11 Chris Demetriou <cgd@broadcom.com>
1103
1104 * mips.igen: Add some additional comments about supported
1105 models, and about which instructions go where.
1106 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1107 order as is used in the rest of the file.
1108
9805e229
CD		 11092002-02-11 Chris Demetriou <cgd@broadcom.com>
1110
1111 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1112 indicating that ALU32_END or ALU64_END are there to check
1113 for overflow.
1114 (DADD): Likewise, but also remove previous comment about
1115 overflow checking.
1116
f701dad2
CD		 11172002-02-10 Chris Demetriou <cgd@broadcom.com>
1118
1119 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1120 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1121 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1122 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1123 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1124 fields (i.e., add and move commas) so that they more closely
1125 match the MIPS ISA documentation opcode partitioning.
1126
11272002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098
CD		 1128
1129 * mips.igen (ADDI): Print immediate value.
1130 (BREAK): Print code.
1131 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1132 (SLL): Print "nop" specially, and don't run the code
1133 that does the shift for the "nop" case.
1134
9e52972e
FF		 11352001-11-17 Fred Fish <fnf@redhat.com>
1136
1137 * sim-main.h (float_operation): Move enum declaration outside
1138 of _sim_cpu struct declaration.
1139
c0efbca4
JB		 11402001-04-12 Jim Blandy <jimb@redhat.com>
1141
1142 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1143 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1144 set of the FCSR.
1145 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1146 PENDING_FILL, and you can get the intended effect gracefully by
1147 calling PENDING_SCHED directly.
1148
fb891446
BE		 11492001-02-23 Ben Elliston <bje@redhat.com>
1150
1151 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1152 already defined elsewhere.
1153
8030f857
BE		 11542001-02-19 Ben Elliston <bje@redhat.com>
1155
1156 * sim-main.h (sim_monitor): Return an int.
1157 * interp.c (sim_monitor): Add return values.
1158 (signal_exception): Handle error conditions from sim_monitor.
1159
56b48a7a
CD		 11602001-02-08 Ben Elliston <bje@redhat.com>
1161
1162 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1163 (store_memory): Likewise, pass cia to sim_core_write*.
1164
d3ee60d9
FCE		 11652000-10-19 Frank Ch. Eigler <fche@redhat.com>
1166
1167 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1168 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1169
071da002
AC		 1170Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1171
1172 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1173 * Makefile.in: Don't delete *.igen when cleaning directory.
1174
a28c02cd
AC		 1175Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1176
1177 * m16.igen (break): Call SignalException not sim_engine_halt.
1178
80ee11fa
AC		 1179Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1180
1181 From Jason Eckhardt:
1182 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1183
673388c0
AC		 1184Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1185
1186 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1187
4c0deff4
NC		 11882000-05-24 Michael Hayes <mhayes@cygnus.com>
1189
1190 * mips.igen (do_dmultx): Fix typo.
1191
eb2d80b4
AC		 1192Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1193
1194 * configure: Regenerated to track ../common/aclocal.m4 changes.
1195
dd37a34b
AC		 1196Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1197
1198 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1199
4c0deff4
NC		 12002000-04-12 Frank Ch. Eigler <fche@redhat.com>
1201
1202 * sim-main.h (GPR_CLEAR): Define macro.
1203
e30db738
AC		 1204Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1205
1206 * interp.c (decode_coproc): Output long using %lx and not %s.
1207
cb7450ea
FCE		 12082000-03-21 Frank Ch. Eigler <fche@redhat.com>
1209
1210 * interp.c (sim_open): Sort & extend dummy memory regions for
1211 --board=jmr3904 for eCos.
1212
a3027dd7
FCE		 12132000-03-02 Frank Ch. Eigler <fche@redhat.com>
1214
1215 * configure: Regenerated.
1216
1217Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1218
1219 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1220 calls, conditional on the simulator being in verbose mode.
1221
dfcd3bfb
JM		 1222Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1223
1224 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1225 cache don't get ReservedInstruction traps.
1226
c2d11a7d
JM		 12271999-11-29 Mark Salter <msalter@cygnus.com>
1228
1229 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1230 to clear status bits in sdisr register. This is how the hardware works.
1231
1232 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1233 being used by cygmon.
1234
4ce44c66
JM		 12351999-11-11 Andrew Haley <aph@cygnus.com>
1236
1237 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1238 instructions.
1239
cff3e48b
JM		 1240Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1241
1242 * mips.igen (MULT): Correct previous mis-applied patch.
1243
d4f3574e
SS		 1244Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1245
1246 * mips.igen (delayslot32): Handle sequence like
1247 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1248 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1249 (MULT): Actually pass the third register...
1250
12511999-09-03 Mark Salter <msalter@cygnus.com>
1252
1253 * interp.c (sim_open): Added more memory aliases for additional
1254 hardware being touched by cygmon on jmr3904 board.
1255
1256Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1257
1258 * configure: Regenerated to track ../common/aclocal.m4 changes.
1259
a0b3c4fd
JM		 1260Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1261
1262 * interp.c (sim_store_register): Handle case where client - GDB -
1263 specifies that a 4 byte register is 8 bytes in size.
1264 (sim_fetch_register): Ditto.
1265
adf40b2e
JM		 12661999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1267
1268 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1269 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1270 (idt_monitor_base): Base address for IDT monitor traps.
1271 (pmon_monitor_base): Ditto for PMON.
1272 (lsipmon_monitor_base): Ditto for LSI PMON.
1273 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1274 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1275 (sim_firmware_command): New function.
1276 (mips_option_handler): Call it for OPTION_FIRMWARE.
1277 (sim_open): Allocate memory for idt_monitor region. If "--board"
1278 option was given, add no monitor by default. Add BREAK hooks only if
1279 monitors are also there.
1280
43e526b9
JM		 1281Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1282
1283 * interp.c (sim_monitor): Flush output before reading input.
1284
1285Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1286
1287 * tconfig.in (SIM_HANDLES_LMA): Always define.
1288
1289Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1290
1291 From Mark Salter <msalter@cygnus.com>:
1292 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1293 (sim_open): Add setup for BSP board.
1294
9846de1b
JM		 1295Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1296
1297 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1298 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1299 them as unimplemented.
1300
cd0fc7c3
SS		 13011999-05-08 Felix Lee <flee@cygnus.com>
1302
1303 * configure: Regenerated to track ../common/aclocal.m4 changes.
1304
7a292a7a
SS		 13051999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1306
1307 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1308
1309Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1310
1311 * configure.in: Any mips64vr5*-*-* target should have
1312 -DTARGET_ENABLE_FR=1.
1313 (default_endian): Any mips64vr*el-*-* target should default to
1314 LITTLE_ENDIAN.
1315 * configure: Re-generate.
1316
13171999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1318
1319 * mips.igen (ldl): Extend from _16_, not 32.
1320
1321Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1322
1323 * interp.c (sim_store_register): Force registers written to by GDB
1324 into an un-interpreted state.
1325
c906108c
SS		 13261999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1327
1328 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1329 CPU, start periodic background I/O polls.
1330 (tx3904sio_poll): New function: periodic I/O poller.
1331
13321998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1333
1334 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1335
1336Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1337
1338 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1339 case statement.
1340
13411998-12-29 Frank Ch. Eigler <fche@cygnus.com>
1342
1343 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1344 (load_word): Call SIM_CORE_SIGNAL hook on error.
1345 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1346 starting. For exception dispatching, pass PC instead of NULL_CIA.
1347 (decode_coproc): Use COP0_BADVADDR to store faulting address.
1348 * sim-main.h (COP0_BADVADDR): Define.
1349 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1350 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1351 (_sim_cpu): Add exc_* fields to store register value snapshots.
1352 * mips.igen (*): Replace memory-related SignalException* calls
1353 with references to SIM_CORE_SIGNAL hook.
1354
1355 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1356 fix.
1357 * sim-main.c (*): Minor warning cleanups.
1358
13591998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1360
1361 * m16.igen (DADDIU5): Correct type-o.
1362
1363Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1364
1365 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1366 variables.
1367
1368Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1369
1370 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1371 to include path.
1372 (interp.o): Add dependency on itable.h
1373 (oengine.c, gencode): Delete remaining references.
1374 (BUILT_SRC_FROM_GEN): Clean up.
1375
13761998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
1377
1378 * vr4run.c: New.
1379 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1380 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1381 tmp-run-hack) : New.
1382 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1383 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1384 Drop the "64" qualifier to get the HACK generator working.
1385 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1386 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1387 qualifier to get the hack generator working.
1388 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1389 (DSLL): Use do_dsll.
1390 (DSLLV): Use do_dsllv.
1391 (DSRA): Use do_dsra.
1392 (DSRL): Use do_dsrl.
1393 (DSRLV): Use do_dsrlv.
1394 (BC1): Move *vr4100 to get the HACK generator working.
1395 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1396 get the HACK generator working.
1397 (MACC) Rename to get the HACK generator working.
1398 (DMACC,MACCS,DMACCS): Add the 64.
1399
14001998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1401
1402 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1403 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1404
14051998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1406
1407 * mips/interp.c (DEBUG): Cleanups.
1408
14091998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1410
1411 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1412 (tx3904sio_tickle): fflush after a stdout character output.
1413
14141998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1415
1416 * interp.c (sim_close): Uninstall modules.
1417
1418Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1419
1420 * sim-main.h, interp.c (sim_monitor): Change to global
1421 function.
1422
1423Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1424
1425 * configure.in (vr4100): Only include vr4100 instructions in
1426 simulator.
1427 * configure: Re-generate.
1428 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1429
1430Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1431
1432 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1433 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1434 true alternative.
1435
1436 * configure.in (sim_default_gen, sim_use_gen): Replace with
1437 sim_gen.
1438 (--enable-sim-igen): Delete config option. Always using IGEN.
1439 * configure: Re-generate.
1440
1441 * Makefile.in (gencode): Kill, kill, kill.
1442 * gencode.c: Ditto.
1443
1444Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1445
1446 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1447 bit mips16 igen simulator.
1448 * configure: Re-generate.
1449
1450 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1451 as part of vr4100 ISA.
1452 * vr.igen: Mark all instructions as 64 bit only.
1453
1454Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1455
1456 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1457 Pacify GCC.
1458
1459Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1460
1461 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1462 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1463 * configure: Re-generate.
1464
1465 * m16.igen (BREAK): Define breakpoint instruction.
1466 (JALX32): Mark instruction as mips16 and not r3900.
1467 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1468
1469 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1470
1471Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1472
1473 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1474 insn as a debug breakpoint.
1475
1476 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1477 pending.slot_size.
1478 (PENDING_SCHED): Clean up trace statement.
1479 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1480 (PENDING_FILL): Delay write by only one cycle.
1481 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1482
1483 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1484 of pending writes.
1485 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1486 32 & 64.
1487 (pending_tick): Move incrementing of index to FOR statement.
1488 (pending_tick): Only update PENDING_OUT after a write has occured.
1489
1490 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1491 build simulator.
1492 * configure: Re-generate.
1493
1494 * interp.c (sim_engine_run OLD): Delete explicit call to
1495 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1496
1497Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1498
1499 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1500 interrupt level number to match changed SignalExceptionInterrupt
1501 macro.
1502
1503Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1504
1505 * interp.c: #include "itable.h" if WITH_IGEN.
1506 (get_insn_name): New function.
1507 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1508 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1509
1510Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1511
1512 * configure: Rebuilt to inhale new common/aclocal.m4.
1513
1514Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1515
1516 * dv-tx3904sio.c: Include sim-assert.h.
1517
1518Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1519
1520 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1521 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1522 Reorganize target-specific sim-hardware checks.
1523 * configure: rebuilt.
1524 * interp.c (sim_open): For tx39 target boards, set
1525 OPERATING_ENVIRONMENT, add tx3904sio devices.
1526 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1527 ROM executables. Install dv-sockser into sim-modules list.
1528
1529 * dv-tx3904irc.c: Compiler warning clean-up.
1530 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1531 frequent hw-trace messages.
1532
1533Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1536
1537Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1540
1541 * vr.igen: New file.
1542 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1543 * mips.igen: Define vr4100 model. Include vr.igen.
1544Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1545
1546 * mips.igen (check_mf_hilo): Correct check.
1547
1548Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1549
1550 * sim-main.h (interrupt_event): Add prototype.
1551
1552 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1553 register_ptr, register_value.
1554 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1555
1556 * sim-main.h (tracefh): Make extern.
1557
1558Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1559
1560 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1561 Reduce unnecessarily high timer event frequency.
1562 * dv-tx3904cpu.c: Ditto for interrupt event.
1563
1564Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1565
1566 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1567 to allay warnings.
1568 (interrupt_event): Made non-static.
1569
1570 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1571 interchange of configuration values for external vs. internal
1572 clock dividers.
1573
1574Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1575
1576 * mips.igen (BREAK): Moved code to here for
1577 simulator-reserved break instructions.
1578 * gencode.c (build_instruction): Ditto.
1579 * interp.c (signal_exception): Code moved from here. Non-
1580 reserved instructions now use exception vector, rather
1581 than halting sim.
1582 * sim-main.h: Moved magic constants to here.
1583
1584Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1585
1586 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1587 register upon non-zero interrupt event level, clear upon zero
1588 event value.
1589 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1590 by passing zero event value.
1591 (*_io_{read,write}_buffer): Endianness fixes.
1592 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1593 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1594
1595 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1596 serial I/O and timer module at base address 0xFFFF0000.
1597
1598Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1599
1600 * mips.igen (SWC1) : Correct the handling of ReverseEndian
1601 and BigEndianCPU.
1602
1603Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1604
1605 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1606 parts.
1607 * configure: Update.
1608
1609Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1610
1611 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1612 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1613 * configure.in: Include tx3904tmr in hw_device list.
1614 * configure: Rebuilt.
1615 * interp.c (sim_open): Instantiate three timer instances.
1616 Fix address typo of tx3904irc instance.
1617
1618Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1619
1620 * interp.c (signal_exception): SystemCall exception now uses
1621 the exception vector.
1622
1623Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1624
1625 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1626 to allay warnings.
1627
1628Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1629
1630 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1631
1632Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1633
1634 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1635
1636 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1637 sim-main.h. Declare a struct hw_descriptor instead of struct
1638 hw_device_descriptor.
1639
1640Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1643 right bits and then re-align left hand bytes to correct byte
1644 lanes. Fix incorrect computation in do_store_left when loading
1645 bytes from second word.
1646
1647Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1648
1649 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1650 * interp.c (sim_open): Only create a device tree when HW is
1651 enabled.
1652
1653 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1654 * interp.c (signal_exception): Ditto.
1655
1656Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1657
1658 * gencode.c: Mark BEGEZALL as LIKELY.
1659
1660Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1661
1662 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1663 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1664
1665Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1666
1667 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1668 modules. Recognize TX39 target with "mips*tx39" pattern.
1669 * configure: Rebuilt.
1670 * sim-main.h (*): Added many macros defining bits in
1671 TX39 control registers.
1672 (SignalInterrupt): Send actual PC instead of NULL.
1673 (SignalNMIReset): New exception type.
1674 * interp.c (board): New variable for future use to identify
1675 a particular board being simulated.
1676 (mips_option_handler,mips_options): Added "--board" option.
1677 (interrupt_event): Send actual PC.
1678 (sim_open): Make memory layout conditional on board setting.
1679 (signal_exception): Initial implementation of hardware interrupt
1680 handling. Accept another break instruction variant for simulator
1681 exit.
1682 (decode_coproc): Implement RFE instruction for TX39.
1683 (mips.igen): Decode RFE instruction as such.
1684 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1685 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1686 bbegin to implement memory map.
1687 * dv-tx3904cpu.c: New file.
1688 * dv-tx3904irc.c: New file.
1689
1690Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1691
1692 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1693
1694Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1695
1696 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1697 with calls to check_div_hilo.
1698
1699Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1700
1701 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1702 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1703 Add special r3900 version of do_mult_hilo.
1704 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1705 with calls to check_mult_hilo.
1706 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1707 with calls to check_div_hilo.
1708
1709Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1710
1711 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1712 Document a replacement.
1713
1714Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1715
1716 * interp.c (sim_monitor): Make mon_printf work.
1717
1718Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1719
1720 * sim-main.h (INSN_NAME): New arg `cpu'.
1721
1722Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1723
1724 * configure: Regenerated to track ../common/aclocal.m4 changes.
1725
1726Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1727
1728 * configure: Regenerated to track ../common/aclocal.m4 changes.
1729 * config.in: Ditto.
1730
1731Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1732
1733 * acconfig.h: New file.
1734 * configure.in: Reverted change of Apr 24; use sinclude again.
1735
1736Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1737
1738 * configure: Regenerated to track ../common/aclocal.m4 changes.
1739 * config.in: Ditto.
1740
1741Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
1742
1743 * configure.in: Don't call sinclude.
1744
1745Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
1746
1747 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1748
1749Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1750
1751 * mips.igen (ERET): Implement.
1752
1753 * interp.c (decode_coproc): Return sign-extended EPC.
1754
1755 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1756
1757 * interp.c (signal_exception): Do not ignore Trap.
1758 (signal_exception): On TRAP, restart at exception address.
1759 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1760 (signal_exception): Update.
1761 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1762 so that TRAP instructions are caught.
1763
1764Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
1765
1766 * sim-main.h (struct hilo_access, struct hilo_history): Define,
1767 contains HI/LO access history.
1768 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1769 (HIACCESS, LOACCESS): Delete, replace with
1770 (HIHISTORY, LOHISTORY): New macros.
1771 (CHECKHILO): Delete all, moved to mips.igen
1772
1773 * gencode.c (build_instruction): Do not generate checks for
1774 correct HI/LO register usage.
1775
1776 * interp.c (old_engine_run): Delete checks for correct HI/LO
1777 register usage.
1778
1779 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1780 check_mf_cycles): New functions.
1781 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1782 do_divu, domultx, do_mult, do_multu): Use.
1783
1784 * tx.igen ("madd", "maddu"): Use.
1785
1786Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
1787
1788 * mips.igen (DSRAV): Use function do_dsrav.
1789 (SRAV): Use new function do_srav.
1790
1791 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1792 (B): Sign extend 11 bit immediate.
1793 (EXT-B*): Shift 16 bit immediate left by 1.
1794 (ADDIU*): Don't sign extend immediate value.
1795
1796Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
1797
1798 * m16run.c (sim_engine_run): Restore CIA after handling an event.
1799
1800 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1801 functions.
1802
1803 * mips.igen (delayslot32, nullify_next_insn): New functions.
1804 (m16.igen): Always include.
1805 (do_*): Add more tracing.
1806
1807 * m16.igen (delayslot16): Add NIA argument, could be called by a
1808 32 bit MIPS16 instruction.
1809
1810 * interp.c (ifetch16): Move function from here.
1811 * sim-main.c (ifetch16): To here.
1812
1813 * sim-main.c (ifetch16, ifetch32): Update to match current
1814 implementations of LH, LW.
1815 (signal_exception): Don't print out incorrect hex value of illegal
1816 instruction.
1817
1818Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1819
1820 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1821 instruction.
1822
1823 * m16.igen: Implement MIPS16 instructions.
1824
1825 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1826 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1827 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1828 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1829 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
1830 bodies of corresponding code from 32 bit insn to these. Also used
1831 by MIPS16 versions of functions.
1832
1833 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1834 (IMEM16): Drop NR argument from macro.
1835
1836Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1837
1838 * Makefile.in (SIM_OBJS): Add sim-main.o.
1839
1840 * sim-main.h (address_translation, load_memory, store_memory,
1841 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1842 as INLINE_SIM_MAIN.
1843 (pr_addr, pr_uword64): Declare.
1844 (sim-main.c): Include when H_REVEALS_MODULE_P.
1845
1846 * interp.c (address_translation, load_memory, store_memory,
1847 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1848 from here.
1849 * sim-main.c: To here. Fix compilation problems.
1850
1851 * configure.in: Enable inlining.
1852 * configure: Re-config.
1853
1854Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
1855
1856 * configure: Regenerated to track ../common/aclocal.m4 changes.
1857
1858Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * mips.igen: Include tx.igen.
1861 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1862 * tx.igen: New file, contains MADD and MADDU.
1863
1864 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1865 the hardwired constant `7'.
1866 (store_memory): Ditto.
1867 (LOADDRMASK): Move definition to sim-main.h.
1868
1869 mips.igen (MTC0): Enable for r3900.
1870 (ADDU): Add trace.
1871
1872 mips.igen (do_load_byte): Delete.
1873 (do_load, do_store, do_load_left, do_load_write, do_store_left,
1874 do_store_right): New functions.
1875 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1876
1877 configure.in: Let the tx39 use igen again.
1878 configure: Update.
1879
1880Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1881
1882 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1883 not an address sized quantity. Return zero for cache sizes.
1884
1885Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
1886
1887 * mips.igen (r3900): r3900 does not support 64 bit integer
1888 operations.
1889
1890Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
1891
1892 * configure.in (mipstx39*-*-*): Use gencode simulator rather
1893 than igen one.
1894 * configure : Rebuild.
1895
1896Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
1897
1898 * configure: Regenerated to track ../common/aclocal.m4 changes.
1899
1900Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
1901
1902 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1903
1904Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
1905
1906 * configure: Regenerated to track ../common/aclocal.m4 changes.
1907 * config.in: Regenerated to track ../common/aclocal.m4 changes.
1908
1909Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
1910
1911 * configure: Regenerated to track ../common/aclocal.m4 changes.
1912
1913Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
1914
1915 * interp.c (Max, Min): Comment out functions. Not yet used.
1916
1917Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
1918
1919 * configure: Regenerated to track ../common/aclocal.m4 changes.
1920
1921Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
1922
1923 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1924 configurable settings for stand-alone simulator.
1925
1926 * configure.in: Added X11 search, just in case.
1927
1928 * configure: Regenerated.
1929
1930Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
1931
1932 * interp.c (sim_write, sim_read, load_memory, store_memory):
1933 Replace sim_core_*_map with read_map, write_map, exec_map resp.
1934
1935Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
1936
1937 * sim-main.h (GETFCC): Return an unsigned value.
1938
1939Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1940
1941 * mips.igen (DIV): Fix check for -1 / MIN_INT.
1942 (DADD): Result destination is RD not RT.
1943
1944Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1945
1946 * sim-main.h (HIACCESS, LOACCESS): Always define.
1947
1948 * mdmx.igen (Maxi, Mini): Rename Max, Min.
1949
1950 * interp.c (sim_info): Delete.
1951
1952Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
1953
1954 * interp.c (DECLARE_OPTION_HANDLER): Use it.
1955 (mips_option_handler): New argument `cpu'.
1956 (sim_open): Update call to sim_add_option_table.
1957
1958Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
1959
1960 * mips.igen (CxC1): Add tracing.
1961
1962Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
1963
1964 * sim-main.h (Max, Min): Declare.
1965
1966 * interp.c (Max, Min): New functions.
1967
1968 * mips.igen (BC1): Add tracing.
1969
1970Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
1971
1972 * interp.c Added memory map for stack in vr4100
1973
1974Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
1975
1976 * interp.c (load_memory): Add missing "break"'s.
1977
1978Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
1979
1980 * interp.c (sim_store_register, sim_fetch_register): Pass in
1981 length parameter. Return -1.
1982
1983Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
1984
1985 * interp.c: Added hardware init hook, fixed warnings.
1986
1987Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1988
1989 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1990
1991Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
1992
1993 * interp.c (ifetch16): New function.
1994
1995 * sim-main.h (IMEM32): Rename IMEM.
1996 (IMEM16_IMMED): Define.
1997 (IMEM16): Define.
1998 (DELAY_SLOT): Update.
1999
2000 * m16run.c (sim_engine_run): New file.
2001
2002 * m16.igen: All instructions except LB.
2003 (LB): Call do_load_byte.
2004 * mips.igen (do_load_byte): New function.
2005 (LB): Call do_load_byte.
2006
2007 * mips.igen: Move spec for insn bit size and high bit from here.
2008 * Makefile.in (tmp-igen, tmp-m16): To here.
2009
2010 * m16.dc: New file, decode mips16 instructions.
2011
2012 * Makefile.in (SIM_NO_ALL): Define.
2013 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2014
2015Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2016
2017 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2018 point unit to 32 bit registers.
2019 * configure: Re-generate.
2020
2021Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2022
2023 * configure.in (sim_use_gen): Make IGEN the default simulator
2024 generator for generic 32 and 64 bit mips targets.
2025 * configure: Re-generate.
2026
2027Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2030 bitsize.
2031
2032 * interp.c (sim_fetch_register, sim_store_register): Read/write
2033 FGR from correct location.
2034 (sim_open): Set size of FGR's according to
2035 WITH_TARGET_FLOATING_POINT_BITSIZE.
2036
2037 * sim-main.h (FGR): Store floating point registers in a separate
2038 array.
2039
2040Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2041
2042 * configure: Regenerated to track ../common/aclocal.m4 changes.
2043
2044Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2045
2046 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2047
2048 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2049
2050 * interp.c (pending_tick): New function. Deliver pending writes.
2051
2052 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2053 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2054 it can handle mixed sized quantites and single bits.
2055
2056Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2057
2058 * interp.c (oengine.h): Do not include when building with IGEN.
2059 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2060 (sim_info): Ditto for PROCESSOR_64BIT.
2061 (sim_monitor): Replace ut_reg with unsigned_word.
2062 (*): Ditto for t_reg.
2063 (LOADDRMASK): Define.
2064 (sim_open): Remove defunct check that host FP is IEEE compliant,
2065 using software to emulate floating point.
2066 (value_fpr, ...): Always compile, was conditional on HASFPU.
2067
2068Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2071 size.
2072
2073 * interp.c (SD, CPU): Define.
2074 (mips_option_handler): Set flags in each CPU.
2075 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2076 (sim_close): Do not clear STATE, deleted anyway.
2077 (sim_write, sim_read): Assume CPU zero's vm should be used for
2078 data transfers.
2079 (sim_create_inferior): Set the PC for all processors.
2080 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2081 argument.
2082 (mips16_entry): Pass correct nr of args to store_word, load_word.
2083 (ColdReset): Cold reset all cpu's.
2084 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2085 (sim_monitor, load_memory, store_memory, signal_exception): Use
2086 `CPU' instead of STATE_CPU.
2087
2088
2089 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2090 SD or CPU_.
2091
2092 * sim-main.h (signal_exception): Add sim_cpu arg.
2093 (SignalException*): Pass both SD and CPU to signal_exception.
2094 * interp.c (signal_exception): Update.
2095
2096 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2097 Ditto
2098 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2099 address_translation): Ditto
2100 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
2101
2102Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * configure: Regenerated to track ../common/aclocal.m4 changes.
2105
2106Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2107
2108 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2109
2110 * mips.igen (model): Map processor names onto BFD name.
2111
2112 * sim-main.h (CPU_CIA): Delete.
2113 (SET_CIA, GET_CIA): Define
2114
2115Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2118 regiser.
2119
2120 * configure.in (default_endian): Configure a big-endian simulator
2121 by default.
2122 * configure: Re-generate.
2123
2124Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2125
2126 * configure: Regenerated to track ../common/aclocal.m4 changes.
2127
2128Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2129
2130 * interp.c (sim_monitor): Handle Densan monitor outbyte
2131 and inbyte functions.
2132
21331997-12-29 Felix Lee <flee@cygnus.com>
2134
2135 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2136
2137Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2138
2139 * Makefile.in (tmp-igen): Arrange for $zero to always be
2140 reset to zero after every instruction.
2141
2142Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2143
2144 * configure: Regenerated to track ../common/aclocal.m4 changes.
2145 * config.in: Ditto.
2146
2147Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2148
2149 * mips.igen (MSUB): Fix to work like MADD.
2150 * gencode.c (MSUB): Similarly.
2151
2152Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2153
2154 * configure: Regenerated to track ../common/aclocal.m4 changes.
2155
2156Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2157
2158 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2159
2160Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2161
2162 * sim-main.h (sim-fpu.h): Include.
2163
2164 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2165 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2166 using host independant sim_fpu module.
2167
2168Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2169
2170 * interp.c (signal_exception): Report internal errors with SIGABRT
2171 not SIGQUIT.
2172
2173 * sim-main.h (C0_CONFIG): New register.
2174 (signal.h): No longer include.
2175
2176 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2177
2178Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2179
2180 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2181
2182Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * mips.igen: Tag vr5000 instructions.
2185 (ANDI): Was missing mipsIV model, fix assembler syntax.
2186 (do_c_cond_fmt): New function.
2187 (C.cond.fmt): Handle mips I-III which do not support CC field
2188 separatly.
2189 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2190 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2191 in IV3.2 spec.
2192 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2193 vr5000 which saves LO in a GPR separatly.
2194
2195 * configure.in (enable-sim-igen): For vr5000, select vr5000
2196 specific instructions.
2197 * configure: Re-generate.
2198
2199Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2202
2203 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2204 fmt_uninterpreted_64 bit cases to switch. Convert to
2205 fmt_formatted,
2206
2207 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2208
2209 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2210 as specified in IV3.2 spec.
2211 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2212
2213Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2214
2215 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2216 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2217 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2218 PENDING_FILL versions of instructions. Simplify.
2219 (X): New function.
2220 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2221 instructions.
2222 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2223 a signed value.
2224 (MTHI, MFHI): Disable code checking HI-LO.
2225
2226 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2227 global.
2228 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2229
2230Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2231
2232 * gencode.c (build_mips16_operands): Replace IPC with cia.
2233
2234 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2235 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2236 IPC to `cia'.
2237 (UndefinedResult): Replace function with macro/function
2238 combination.
2239 (sim_engine_run): Don't save PC in IPC.
2240
2241 * sim-main.h (IPC): Delete.
2242
2243
2244 * interp.c (signal_exception, store_word, load_word,
2245 address_translation, load_memory, store_memory, cache_op,
2246 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2247 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2248 current instruction address - cia - argument.
2249 (sim_read, sim_write): Call address_translation directly.
2250 (sim_engine_run): Rename variable vaddr to cia.
2251 (signal_exception): Pass cia to sim_monitor
2252
2253 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2254 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2255 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2256
2257 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2258 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2259 SIM_ASSERT.
2260
2261 * interp.c (signal_exception): Pass restart address to
2262 sim_engine_restart.
2263
2264 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2265 idecode.o): Add dependency.
2266
2267 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2268 Delete definitions
2269 (DELAY_SLOT): Update NIA not PC with branch address.
2270 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2271
2272 * mips.igen: Use CIA not PC in branch calculations.
2273 (illegal): Call SignalException.
2274 (BEQ, ADDIU): Fix assembler.
2275
2276Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * m16.igen (JALX): Was missing.
2279
2280 * configure.in (enable-sim-igen): New configuration option.
2281 * configure: Re-generate.
2282
2283 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2284
2285 * interp.c (load_memory, store_memory): Delete parameter RAW.
2286 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2287 bypassing {load,store}_memory.
2288
2289 * sim-main.h (ByteSwapMem): Delete definition.
2290
2291 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2292
2293 * interp.c (sim_do_command, sim_commands): Delete mips specific
2294 commands. Handled by module sim-options.
2295
2296 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2297 (WITH_MODULO_MEMORY): Define.
2298
2299 * interp.c (sim_info): Delete code printing memory size.
2300
2301 * interp.c (mips_size): Nee sim_size, delete function.
2302 (power2): Delete.
2303 (monitor, monitor_base, monitor_size): Delete global variables.
2304 (sim_open, sim_close): Delete code creating monitor and other
2305 memory regions. Use sim-memopts module, via sim_do_commandf, to
2306 manage memory regions.
2307 (load_memory, store_memory): Use sim-core for memory model.
2308
2309 * interp.c (address_translation): Delete all memory map code
2310 except line forcing 32 bit addresses.
2311
2312Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2313
2314 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2315 trace options.
2316
2317 * interp.c (logfh, logfile): Delete globals.
2318 (sim_open, sim_close): Delete code opening & closing log file.
2319 (mips_option_handler): Delete -l and -n options.
2320 (OPTION mips_options): Ditto.
2321
2322 * interp.c (OPTION mips_options): Rename option trace to dinero.
2323 (mips_option_handler): Update.
2324
2325Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2326
2327 * interp.c (fetch_str): New function.
2328 (sim_monitor): Rewrite using sim_read & sim_write.
2329 (sim_open): Check magic number.
2330 (sim_open): Write monitor vectors into memory using sim_write.
2331 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2332 (sim_read, sim_write): Simplify - transfer data one byte at a
2333 time.
2334 (load_memory, store_memory): Clarify meaning of parameter RAW.
2335
2336 * sim-main.h (isHOST): Defete definition.
2337 (isTARGET): Mark as depreciated.
2338 (address_translation): Delete parameter HOST.
2339
2340 * interp.c (address_translation): Delete parameter HOST.
2341
2342Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2343
2344 * mips.igen:
2345
2346 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2347 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2348
2349Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * mips.igen: Add model filter field to records.
2352
2353Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
2356
2357 interp.c (sim_engine_run): Do not compile function sim_engine_run
2358 when WITH_IGEN == 1.
2359
2360 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2361 target architecture.
2362
2363 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2364 igen. Replace with configuration variables sim_igen_flags /
2365 sim_m16_flags.
2366
2367 * m16.igen: New file. Copy mips16 insns here.
2368 * mips.igen: From here.
2369
2370Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2371
2372 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2373 to top.
2374 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2375
2376Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2377
2378 * gencode.c (build_instruction): Follow sim_write's lead in using
2379 BigEndianMem instead of !ByteSwapMem.
2380
2381Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2382
2383 * configure.in (sim_gen): Dependent on target, select type of
2384 generator. Always select old style generator.
2385
2386 configure: Re-generate.
2387
2388 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2389 targets.
2390 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2391 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2392 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2393 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2394 SIM_@sim_gen@_*, set by autoconf.
2395
2396Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2397
2398 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2399
2400 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2401 CURRENT_FLOATING_POINT instead.
2402
2403 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2404 (address_translation): Raise exception InstructionFetch when
2405 translation fails and isINSTRUCTION.
2406
2407 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2408 sim_engine_run): Change type of of vaddr and paddr to
2409 address_word.
2410 (address_translation, prefetch, load_memory, store_memory,
2411 cache_op): Change type of vAddr and pAddr to address_word.
2412
2413 * gencode.c (build_instruction): Change type of vaddr and paddr to
2414 address_word.
2415
2416Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2417
2418 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2419 macro to obtain result of ALU op.
2420
2421Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2422
2423 * interp.c (sim_info): Call profile_print.
2424
2425Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2426
2427 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2428
2429 * sim-main.h (WITH_PROFILE): Do not define, defined in
2430 common/sim-config.h. Use sim-profile module.
2431 (simPROFILE): Delete defintion.
2432
2433 * interp.c (PROFILE): Delete definition.
2434 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2435 (sim_close): Delete code writing profile histogram.
2436 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2437 Delete.
2438 (sim_engine_run): Delete code profiling the PC.
2439
2440Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2441
2442 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2443
2444 * interp.c (sim_monitor): Make register pointers of type
2445 unsigned_word*.
2446
2447 * sim-main.h: Make registers of type unsigned_word not
2448 signed_word.
2449
2450Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2451
2452 * interp.c (sync_operation): Rename from SyncOperation, make
2453 global, add SD argument.
2454 (prefetch): Rename from Prefetch, make global, add SD argument.
2455 (decode_coproc): Make global.
2456
2457 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2458
2459 * gencode.c (build_instruction): Generate DecodeCoproc not
2460 decode_coproc calls.
2461
2462 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2463 (SizeFGR): Move to sim-main.h
2464 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2465 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2466 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2467 sim-main.h.
2468 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2469 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2470 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2471 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2472 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2473 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2474
2475 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2476 exception.
2477 (sim-alu.h): Include.
2478 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2479 (sim_cia): Typedef to instruction_address.
2480
2481Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2482
2483 * Makefile.in (interp.o): Rename generated file engine.c to
2484 oengine.c.
2485
2486 * interp.c: Update.
2487
2488Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2491
2492Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2493
2494 * gencode.c (build_instruction): For "FPSQRT", output correct
2495 number of arguments to Recip.
2496
2497Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2498
2499 * Makefile.in (interp.o): Depends on sim-main.h
2500
2501 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2502
2503 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2504 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2505 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2506 STATE, DSSTATE): Define
2507 (GPR, FGRIDX, ..): Define.
2508
2509 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2510 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2511 (GPR, FGRIDX, ...): Delete macros.
2512
2513 * interp.c: Update names to match defines from sim-main.h
2514
2515Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2516
2517 * interp.c (sim_monitor): Add SD argument.
2518 (sim_warning): Delete. Replace calls with calls to
2519 sim_io_eprintf.
2520 (sim_error): Delete. Replace calls with sim_io_error.
2521 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2522 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2523 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2524 argument.
2525 (mips_size): Rename from sim_size. Add SD argument.
2526
2527 * interp.c (simulator): Delete global variable.
2528 (callback): Delete global variable.
2529 (mips_option_handler, sim_open, sim_write, sim_read,
2530 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2531 sim_size,sim_monitor): Use sim_io_* not callback->*.
2532 (sim_open): ZALLOC simulator struct.
2533 (PROFILE): Do not define.
2534
2535Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2538 support.h with corresponding code.
2539
2540 * sim-main.h (word64, uword64), support.h: Move definition to
2541 sim-main.h.
2542 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2543
2544 * support.h: Delete
2545 * Makefile.in: Update dependencies
2546 * interp.c: Do not include.
2547
2548Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2549
2550 * interp.c (address_translation, load_memory, store_memory,
2551 cache_op): Rename to from AddressTranslation et.al., make global,
2552 add SD argument
2553
2554 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2555 CacheOp): Define.
2556
2557 * interp.c (SignalException): Rename to signal_exception, make
2558 global.
2559
2560 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2561
2562 * sim-main.h (SignalException, SignalExceptionInterrupt,
2563 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2564 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2565 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2566 Define.
2567
2568 * interp.c, support.h: Use.
2569
2570Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2571
2572 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2573 to value_fpr / store_fpr. Add SD argument.
2574 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2575 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2576
2577 * sim-main.h (ValueFPR, StoreFPR): Define.
2578
2579Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2580
2581 * interp.c (sim_engine_run): Check consistency between configure
2582 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2583 and HASFPU.
2584
2585 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2586 (mips_fpu): Configure WITH_FLOATING_POINT.
2587 (mips_endian): Configure WITH_TARGET_ENDIAN.
2588 * configure: Update.
2589
2590Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2591
2592 * configure: Regenerated to track ../common/aclocal.m4 changes.
2593
2594Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2595
2596 * configure: Regenerated.
2597
2598Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2599
2600 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2601
2602Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2603
2604 * gencode.c (print_igen_insn_models): Assume certain architectures
2605 include all mips* instructions.
2606 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2607 instruction.
2608
2609 * Makefile.in (tmp.igen): Add target. Generate igen input from
2610 gencode file.
2611
2612 * gencode.c (FEATURE_IGEN): Define.
2613 (main): Add --igen option. Generate output in igen format.
2614 (process_instructions): Format output according to igen option.
2615 (print_igen_insn_format): New function.
2616 (print_igen_insn_models): New function.
2617 (process_instructions): Only issue warnings and ignore
2618 instructions when no FEATURE_IGEN.
2619
2620Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2621
2622 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2623 MIPS targets.
2624
2625Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2626
2627 * configure: Regenerated to track ../common/aclocal.m4 changes.
2628
2629Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630
2631 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2632 SIM_RESERVED_BITS): Delete, moved to common.
2633 (SIM_EXTRA_CFLAGS): Update.
2634
2635Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2636
2637 * configure.in: Configure non-strict memory alignment.
2638 * configure: Regenerated to track ../common/aclocal.m4 changes.
2639
2640Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * configure: Regenerated to track ../common/aclocal.m4 changes.
2643
2644Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2645
2646 * gencode.c (SDBBP,DERET): Added (3900) insns.
2647 (RFE): Turn on for 3900.
2648 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2649 (dsstate): Made global.
2650 (SUBTARGET_R3900): Added.
2651 (CANCELDELAYSLOT): New.
2652 (SignalException): Ignore SystemCall rather than ignore and
2653 terminate. Add DebugBreakPoint handling.
2654 (decode_coproc): New insns RFE, DERET; and new registers Debug
2655 and DEPC protected by SUBTARGET_R3900.
2656 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2657 bits explicitly.
2658 * Makefile.in,configure.in: Add mips subtarget option.
2659 * configure: Update.
2660
2661Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2662
2663 * gencode.c: Add r3900 (tx39).
2664
2665
2666Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2667
2668 * gencode.c (build_instruction): Don't need to subtract 4 for
2669 JALR, just 2.
2670
2671Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2672
2673 * interp.c: Correct some HASFPU problems.
2674
2675Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2676
2677 * configure: Regenerated to track ../common/aclocal.m4 changes.
2678
2679Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2680
2681 * interp.c (mips_options): Fix samples option short form, should
2682 be `x'.
2683
2684Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2685
2686 * interp.c (sim_info): Enable info code. Was just returning.
2687
2688Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2689
2690 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2691 MFC0.
2692
2693Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2694
2695 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2696 constants.
2697 (build_instruction): Ditto for LL.
2698
2699Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2700
2701 * configure: Regenerated to track ../common/aclocal.m4 changes.
2702
2703Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * configure: Regenerated to track ../common/aclocal.m4 changes.
2706 * config.in: Ditto.
2707
2708Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2709
2710 * interp.c (sim_open): Add call to sim_analyze_program, update
2711 call to sim_config.
2712
2713Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2714
2715 * interp.c (sim_kill): Delete.
2716 (sim_create_inferior): Add ABFD argument. Set PC from same.
2717 (sim_load): Move code initializing trap handlers from here.
2718 (sim_open): To here.
2719 (sim_load): Delete, use sim-hload.c.
2720
2721 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2722
2723Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2724
2725 * configure: Regenerated to track ../common/aclocal.m4 changes.
2726 * config.in: Ditto.
2727
2728Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2729
2730 * interp.c (sim_open): Add ABFD argument.
2731 (sim_load): Move call to sim_config from here.
2732 (sim_open): To here. Check return status.
2733
2734Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
2735
2736 * gencode.c (build_instruction): Two arg MADD should
2737 not assign result to $0.
2738
2739Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
2740
2741 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2742 * sim/mips/configure.in: Regenerate.
2743
2744Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
2745
2746 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2747 signed8, unsigned8 et.al. types.
2748
2749 * interp.c (SUB_REG_FETCH): Handle both little and big endian
2750 hosts when selecting subreg.
2751
2752Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
2753
2754 * interp.c (sim_engine_run): Reset the ZERO register to zero
2755 regardless of FEATURE_WARN_ZERO.
2756 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2757
2758Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2761 (SignalException): For BreakPoints ignore any mode bits and just
2762 save the PC.
2763 (SignalException): Always set the CAUSE register.
2764
2765Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
2766
2767 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2768 exception has been taken.
2769
2770 * interp.c: Implement the ERET and mt/f sr instructions.
2771
2772Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
2773
2774 * interp.c (SignalException): Don't bother restarting an
2775 interrupt.
2776
2777Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2778
2779 * interp.c (SignalException): Really take an interrupt.
2780 (interrupt_event): Only deliver interrupts when enabled.
2781
2782Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2783
2784 * interp.c (sim_info): Only print info when verbose.
2785 (sim_info) Use sim_io_printf for output.
2786
2787Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2788
2789 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2790 mips architectures.
2791
2792Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2793
2794 * interp.c (sim_do_command): Check for common commands if a
2795 simulator specific command fails.
2796
2797Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
2798
2799 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2800 and simBE when DEBUG is defined.
2801
2802Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * interp.c (interrupt_event): New function. Pass exception event
2805 onto exception handler.
2806
2807 * configure.in: Check for stdlib.h.
2808 * configure: Regenerate.
2809
2810 * gencode.c (build_instruction): Add UNUSED attribute to tempS
2811 variable declaration.
2812 (build_instruction): Initialize memval1.
2813 (build_instruction): Add UNUSED attribute to byte, bigend,
2814 reverse.
2815 (build_operands): Ditto.
2816
2817 * interp.c: Fix GCC warnings.
2818 (sim_get_quit_code): Delete.
2819
2820 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2821 * Makefile.in: Ditto.
2822 * configure: Re-generate.
2823
2824 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2825
2826Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2827
2828 * interp.c (mips_option_handler): New function parse argumes using
2829 sim-options.
2830 (myname): Replace with STATE_MY_NAME.
2831 (sim_open): Delete check for host endianness - performed by
2832 sim_config.
2833 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2834 (sim_open): Move much of the initialization from here.
2835 (sim_load): To here. After the image has been loaded and
2836 endianness set.
2837 (sim_open): Move ColdReset from here.
2838 (sim_create_inferior): To here.
2839 (sim_open): Make FP check less dependant on host endianness.
2840
2841 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2842 run.
2843 * interp.c (sim_set_callbacks): Delete.
2844
2845 * interp.c (membank, membank_base, membank_size): Replace with
2846 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2847 (sim_open): Remove call to callback->init. gdb/run do this.
2848
2849 * interp.c: Update
2850
2851 * sim-main.h (SIM_HAVE_FLATMEM): Define.
2852
2853 * interp.c (big_endian_p): Delete, replaced by
2854 current_target_byte_order.
2855
2856Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2857
2858 * interp.c (host_read_long, host_read_word, host_swap_word,
2859 host_swap_long): Delete. Using common sim-endian.
2860 (sim_fetch_register, sim_store_register): Use H2T.
2861 (pipeline_ticks): Delete. Handled by sim-events.
2862 (sim_info): Update.
2863 (sim_engine_run): Update.
2864
2865Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
2866
2867 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2868 reason from here.
2869 (SignalException): To here. Signal using sim_engine_halt.
2870 (sim_stop_reason): Delete, moved to common.
2871
2872Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
2873
2874 * interp.c (sim_open): Add callback argument.
2875 (sim_set_callbacks): Delete SIM_DESC argument.
2876 (sim_size): Ditto.
2877
2878Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2879
2880 * Makefile.in (SIM_OBJS): Add common modules.
2881
2882 * interp.c (sim_set_callbacks): Also set SD callback.
2883 (set_endianness, xfer_*, swap_*): Delete.
2884 (host_read_word, host_read_long, host_swap_word, host_swap_long):
2885 Change to functions using sim-endian macros.
2886 (control_c, sim_stop): Delete, use common version.
2887 (simulate): Convert into.
2888 (sim_engine_run): This function.
2889 (sim_resume): Delete.
2890
2891 * interp.c (simulation): New variable - the simulator object.
2892 (sim_kind): Delete global - merged into simulation.
2893 (sim_load): Cleanup. Move PC assignment from here.
2894 (sim_create_inferior): To here.
2895
2896 * sim-main.h: New file.
2897 * interp.c (sim-main.h): Include.
2898
2899Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
2900
2901 * configure: Regenerated to track ../common/aclocal.m4 changes.
2902
2903Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
2904
2905 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2906
2907Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
2908
2909 * gencode.c (build_instruction): DIV instructions: check
2910 for division by zero and integer overflow before using
2911 host's division operation.
2912
2913Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
2914
2915 * Makefile.in (SIM_OBJS): Add sim-load.o.
2916 * interp.c: #include bfd.h.
2917 (target_byte_order): Delete.
2918 (sim_kind, myname, big_endian_p): New static locals.
2919 (sim_open): Set sim_kind, myname. Move call to set_endianness to
2920 after argument parsing. Recognize -E arg, set endianness accordingly.
2921 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
2922 load file into simulator. Set PC from bfd.
2923 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
2924 (set_endianness): Use big_endian_p instead of target_byte_order.
2925
2926Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
2927
2928 * interp.c (sim_size): Delete prototype - conflicts with
2929 definition in remote-sim.h. Correct definition.
2930
2931Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2932
2933 * configure: Regenerated to track ../common/aclocal.m4 changes.
2934 * config.in: Ditto.
2935
2936Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
2937
2938 * interp.c (sim_open): New arg `kind'.
2939
2940 * configure: Regenerated to track ../common/aclocal.m4 changes.
2941
2942Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2943
2944 * configure: Regenerated to track ../common/aclocal.m4 changes.
2945
2946Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
2947
2948 * interp.c (sim_open): Set optind to 0 before calling getopt.
2949
2950Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2951
2952 * configure: Regenerated to track ../common/aclocal.m4 changes.
2953
2954Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
2955
2956 * interp.c : Replace uses of pr_addr with pr_uword64
2957 where the bit length is always 64 independent of SIM_ADDR.
2958 (pr_uword64) : added.
2959
2960Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2961
2962 * configure: Re-generate.
2963
2964Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
2965
2966 * configure: Regenerate to track ../common/aclocal.m4 changes.
2967
2968Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
2969
2970 * interp.c (sim_open): New SIM_DESC result. Argument is now
2971 in argv form.
2972 (other sim_*): New SIM_DESC argument.
2973
2974Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
2975
2976 * interp.c: Fix printing of addresses for non-64-bit targets.
2977 (pr_addr): Add function to print address based on size.
2978
2979Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
2980
2981 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2982
2983Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
2984
2985 * gencode.c (build_mips16_operands): Correct computation of base
2986 address for extended PC relative instruction.
2987
2988Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
2989
2990 * interp.c (mips16_entry): Add support for floating point cases.
2991 (SignalException): Pass floating point cases to mips16_entry.
2992 (ValueFPR): Don't restrict fmt_single and fmt_word to even
2993 registers.
2994 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
2995 or fmt_word.
2996 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2997 and then set the state to fmt_uninterpreted.
2998 (COP_SW): Temporarily set the state to fmt_word while calling
2999 ValueFPR.
3000
3001Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3002
3003 * gencode.c (build_instruction): The high order may be set in the
3004 comparison flags at any ISA level, not just ISA 4.
3005
3006Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3007
3008 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3009 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3010 * configure.in: sinclude ../common/aclocal.m4.
3011 * configure: Regenerated.
3012
3013Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3014
3015 * configure: Rebuild after change to aclocal.m4.
3016
3017Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3018
3019 * configure configure.in Makefile.in: Update to new configure
3020 scheme which is more compatible with WinGDB builds.
3021 * configure.in: Improve comment on how to run autoconf.
3022 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3023 * Makefile.in: Use autoconf substitution to install common
3024 makefile fragment.
3025
3026Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3027
3028 * gencode.c (build_instruction): Use BigEndianCPU instead of
3029 ByteSwapMem.
3030
3031Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3032
3033 * interp.c (sim_monitor): Make output to stdout visible in
3034 wingdb's I/O log window.
3035
3036Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3037
3038 * support.h: Undo previous change to SIGTRAP
3039 and SIGQUIT values.
3040
3041Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3042
3043 * interp.c (store_word, load_word): New static functions.
3044 (mips16_entry): New static function.
3045 (SignalException): Look for mips16 entry and exit instructions.
3046 (simulate): Use the correct index when setting fpr_state after
3047 doing a pending move.
3048
3049Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3050
3051 * interp.c: Fix byte-swapping code throughout to work on
3052 both little- and big-endian hosts.
3053
3054Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3055
3056 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3057 with gdb/config/i386/xm-windows.h.
3058
3059Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3060
3061 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3062 that messes up arithmetic shifts.
3063
3064Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3065
3066 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3067 SIGTRAP and SIGQUIT for _WIN32.
3068
3069Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3070
3071 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3072 force a 64 bit multiplication.
3073 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3074 destination register is 0, since that is the default mips16 nop
3075 instruction.
3076
3077Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3078
3079 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3080 (build_endian_shift): Don't check proc64.
3081 (build_instruction): Always set memval to uword64. Cast op2 to
3082 uword64 when shifting it left in memory instructions. Always use
3083 the same code for stores--don't special case proc64.
3084
3085 * gencode.c (build_mips16_operands): Fix base PC value for PC
3086 relative operands.
3087 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3088 jal instruction.
3089 * interp.c (simJALDELAYSLOT): Define.
3090 (JALDELAYSLOT): Define.
3091 (INDELAYSLOT, INJALDELAYSLOT): Define.
3092 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3093
3094Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3095
3096 * interp.c (sim_open): add flush_cache as a PMON routine
3097 (sim_monitor): handle flush_cache by ignoring it
3098
3099Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3100
3101 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3102 BigEndianMem.
3103 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3104 (BigEndianMem): Rename to ByteSwapMem and change sense.
3105 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3106 BigEndianMem references to !ByteSwapMem.
3107 (set_endianness): New function, with prototype.
3108 (sim_open): Call set_endianness.
3109 (sim_info): Use simBE instead of BigEndianMem.
3110 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3111 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3112 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3113 ifdefs, keeping the prototype declaration.
3114 (swap_word): Rewrite correctly.
3115 (ColdReset): Delete references to CONFIG. Delete endianness related
3116 code; moved to set_endianness.
3117
3118Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3119
3120 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3121 * interp.c (CHECKHILO): Define away.
3122 (simSIGINT): New macro.
3123 (membank_size): Increase from 1MB to 2MB.
3124 (control_c): New function.
3125 (sim_resume): Rename parameter signal to signal_number. Add local
3126 variable prev. Call signal before and after simulate.
3127 (sim_stop_reason): Add simSIGINT support.
3128 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3129 functions always.
3130 (sim_warning): Delete call to SignalException. Do call printf_filtered
3131 if logfh is NULL.
3132 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3133 a call to sim_warning.
3134
3135Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3136
3137 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3138 16 bit instructions.
3139
3140Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3141
3142 Add support for mips16 (16 bit MIPS implementation):
3143 * gencode.c (inst_type): Add mips16 instruction encoding types.
3144 (GETDATASIZEINSN): Define.
3145 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3146 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3147 mtlo.
3148 (MIPS16_DECODE): New table, for mips16 instructions.
3149 (bitmap_val): New static function.
3150 (struct mips16_op): Define.
3151 (mips16_op_table): New table, for mips16 operands.
3152 (build_mips16_operands): New static function.
3153 (process_instructions): If PC is odd, decode a mips16
3154 instruction. Break out instruction handling into new
3155 build_instruction function.
3156 (build_instruction): New static function, broken out of
3157 process_instructions. Check modifiers rather than flags for SHIFT
3158 bit count and m[ft]{hi,lo} direction.
3159 (usage): Pass program name to fprintf.
3160 (main): Remove unused variable this_option_optind. Change
3161 ``*loptarg++'' to ``loptarg++''.
3162 (my_strtoul): Parenthesize && within ||.
3163 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3164 (simulate): If PC is odd, fetch a 16 bit instruction, and
3165 increment PC by 2 rather than 4.
3166 * configure.in: Add case for mips16*-*-*.
3167 * configure: Rebuild.
3168
3169Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3170
3171 * interp.c: Allow -t to enable tracing in standalone simulator.
3172 Fix garbage output in trace file and error messages.
3173
3174Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3175
3176 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3177 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3178 * configure.in: Simplify using macros in ../common/aclocal.m4.
3179 * configure: Regenerated.
3180 * tconfig.in: New file.
3181
3182Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3183
3184 * interp.c: Fix bugs in 64-bit port.
3185 Use ansi function declarations for msvc compiler.
3186 Initialize and test file pointer in trace code.
3187 Prevent duplicate definition of LAST_EMED_REGNUM.
3188
3189Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3190
3191 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3192
3193Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3194
3195 * interp.c (SignalException): Check for explicit terminating
3196 breakpoint value.
3197 * gencode.c: Pass instruction value through SignalException()
3198 calls for Trap, Breakpoint and Syscall.
3199
3200Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3201
3202 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3203 only used on those hosts that provide it.
3204 * configure.in: Add sqrt() to list of functions to be checked for.
3205 * config.in: Re-generated.
3206 * configure: Re-generated.
3207
3208Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3209
3210 * gencode.c (process_instructions): Call build_endian_shift when
3211 expanding STORE RIGHT, to fix swr.
3212 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3213 clear the high bits.
3214 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3215 Fix float to int conversions to produce signed values.
3216
3217Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3218
3219 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3220 (process_instructions): Correct handling of nor instruction.
3221 Correct shift count for 32 bit shift instructions. Correct sign
3222 extension for arithmetic shifts to not shift the number of bits in
3223 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3224 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3225 Fix madd.
3226 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3227 It's OK to have a mult follow a mult. What's not OK is to have a
3228 mult follow an mfhi.
3229 (Convert): Comment out incorrect rounding code.
3230
3231Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3232
3233 * interp.c (sim_monitor): Improved monitor printf
3234 simulation. Tidied up simulator warnings, and added "--log" option
3235 for directing warning message output.
3236 * gencode.c: Use sim_warning() rather than WARNING macro.
3237
3238Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3239
3240 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3241 getopt1.o, rather than on gencode.c. Link objects together.
3242 Don't link against -liberty.
3243 (gencode.o, getopt.o, getopt1.o): New targets.
3244 * gencode.c: Include <ctype.h> and "ansidecl.h".
3245 (AND): Undefine after including "ansidecl.h".
3246 (ULONG_MAX): Define if not defined.
3247 (OP_*): Don't define macros; now defined in opcode/mips.h.
3248 (main): Call my_strtoul rather than strtoul.
3249 (my_strtoul): New static function.
3250
3251Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3252
3253 * gencode.c (process_instructions): Generate word64 and uword64
3254 instead of `long long' and `unsigned long long' data types.
3255 * interp.c: #include sysdep.h to get signals, and define default
3256 for SIGBUS.
3257 * (Convert): Work around for Visual-C++ compiler bug with type
3258 conversion.
3259 * support.h: Make things compile under Visual-C++ by using
3260 __int64 instead of `long long'. Change many refs to long long
3261 into word64/uword64 typedefs.
3262
3263Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3264
3265 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3266 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3267 (docdir): Removed.
3268 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3269 (AC_PROG_INSTALL): Added.
3270 (AC_PROG_CC): Moved to before configure.host call.
3271 * configure: Rebuilt.
3272
3273Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3274
3275 * configure.in: Define @SIMCONF@ depending on mips target.
3276 * configure: Rebuild.
3277 * Makefile.in (run): Add @SIMCONF@ to control simulator
3278 construction.
3279 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3280 * interp.c: Remove some debugging, provide more detailed error
3281 messages, update memory accesses to use LOADDRMASK.
3282
3283Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3284
3285 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3286 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3287 stamp-h.
3288 * configure: Rebuild.
3289 * config.in: New file, generated by autoheader.
3290 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3291 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3292 HAVE_ANINT and HAVE_AINT, as appropriate.
3293 * Makefile.in (run): Use @LIBS@ rather than -lm.
3294 (interp.o): Depend upon config.h.
3295 (Makefile): Just rebuild Makefile.
3296 (clean): Remove stamp-h.
3297 (mostlyclean): Make the same as clean, not as distclean.
3298 (config.h, stamp-h): New targets.
3299
3300Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3301
3302 * interp.c (ColdReset): Fix boolean test. Make all simulator
3303 globals static.
3304
3305Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3306
3307 * interp.c (xfer_direct_word, xfer_direct_long,
3308 swap_direct_word, swap_direct_long, xfer_big_word,
3309 xfer_big_long, xfer_little_word, xfer_little_long,
3310 swap_word,swap_long): Added.
3311 * interp.c (ColdReset): Provide function indirection to
3312 host<->simulated_target transfer routines.
3313 * interp.c (sim_store_register, sim_fetch_register): Updated to
3314 make use of indirected transfer routines.
3315
3316Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3317
3318 * gencode.c (process_instructions): Ensure FP ABS instruction
3319 recognised.
3320 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3321 system call support.
3322
3323Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3324
3325 * interp.c (sim_do_command): Complain if callback structure not
3326 initialised.
3327
3328Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3329
3330 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3331 support for Sun hosts.
3332 * Makefile.in (gencode): Ensure the host compiler and libraries
3333 used for cross-hosted build.
3334
3335Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3336
3337 * interp.c, gencode.c: Some more (TODO) tidying.
3338
3339Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3340
3341 * gencode.c, interp.c: Replaced explicit long long references with
3342 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3343 * support.h (SET64LO, SET64HI): Macros added.
3344
3345Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3346
3347 * configure: Regenerate with autoconf 2.7.
3348
3349Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3350
3351 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3352 * support.h: Remove superfluous "1" from #if.
3353 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3354
3355Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3356
3357 * interp.c (StoreFPR): Control UndefinedResult() call on
3358 WARN_RESULT manifest.
3359
3360Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3361
3362 * gencode.c: Tidied instruction decoding, and added FP instruction
3363 support.
3364
3365 * interp.c: Added dineroIII, and BSD profiling support. Also
3366 run-time FP handling.
3367
3368Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3369
3370 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3371 gencode.c, interp.c, support.h: created.
A mirror of the official binutils-gdb repository