]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - sim/mips/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sim: cris: do not pass cpu when writing memory during init
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
ef04e371
MF		 12015-12-24 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
4 * configure: Regenerated.
5
cb379ede
MF		 62015-12-24 Mike Frysinger <vapier@gentoo.org>
7
8 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
9 * tconfig.h: Delete.
10
26936211
MF		 112015-12-24 Mike Frysinger <vapier@gentoo.org>
12
13 * tconfig.h (SIM_HANDLES_LMA): Delete.
14
84e8e361
MF		 152015-12-24 Mike Frysinger <vapier@gentoo.org>
16
17 * sim-main.h (WITH_WATCHPOINTS): Delete.
18
3cabaf66
MF		 192015-12-24 Mike Frysinger <vapier@gentoo.org>
20
21 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
22
8abe6c66
MF		 232015-12-24 Mike Frysinger <vapier@gentoo.org>
24
25 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
26
1d19cae7
DV		 272015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
28
29 * micromips.igen (process_isa_mode): Fix left shift of negative
30 value.
31
cdf850e9
MF		 322015-11-17 Mike Frysinger <vapier@gentoo.org>
33
34 * sim-main.h (WITH_MODULO_MEMORY): Delete.
35
797eee42
MF		 362015-11-15 Mike Frysinger <vapier@gentoo.org>
37
38 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
39
6e4f085c
MF		 402015-11-14 Mike Frysinger <vapier@gentoo.org>
41
42 * interp.c (sim_close): Rename to ...
43 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
44 sim_io_shutdown.
45 * sim-main.h (mips_sim_close): Declare.
46 (SIM_CLOSE_HOOK): Define.
47
8e394ffc
AB		 482015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
49 Ali Lown <ali.lown@imgtec.com>
50
51 * Makefile.in (tmp-micromips): New rule.
52 (tmp-mach-multi): Add support for micromips.
53 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
54 that works for both mips64 and micromips64.
55 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
56 micromips32.
57 Add build support for micromips.
58 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
59 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
60 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
61 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
62 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
63 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
64 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
65 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
66 Refactored instruction code to use these functions.
67 * dsp2.igen: Refactored instruction code to use the new functions.
68 * interp.c (decode_coproc): Refactored to work with any instruction
69 encoding.
70 (isa_mode): New variable
71 (RSVD_INSTRUCTION): Changed to 0x00000039.
72 * m16.igen (BREAK16): Refactored instruction to use do_break16.
73 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
74 * micromips.dc: New file.
75 * micromips.igen: New file.
76 * micromips16.dc: New file.
77 * micromipsdsp.igen: New file.
78 * micromipsrun.c: New file.
79 * mips.igen (do_swc1): Changed to work with any instruction encoding.
80 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
81 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
82 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
83 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
84 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
85 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
86 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
87 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
88 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
89 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
90 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
91 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
92 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
93 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
94 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
95 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
96 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
97 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
98 instructions.
99 Refactored instruction code to use these functions.
100 (RSVD): Changed to use new reserved instruction.
101 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
102 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
103 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
104 do_store_double): Added micromips32 and micromips64 models.
105 Added include for micromips.igen and micromipsdsp.igen
106 Add micromips32 and micromips64 models.
107 (DecodeCoproc): Updated to use new macro definition.
108 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
109 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
110 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
111 Refactored instruction code to use these functions.
112 * sim-main.h (CP0_operation): New enum.
113 (DecodeCoproc): Updated macro.
114 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
115 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
116 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
117 ISA_MODE_MICROMIPS): New defines.
118 (sim_state): Add isa_mode field.
119
8d0978fb
MF		 1202015-06-23 Mike Frysinger <vapier@gentoo.org>
121
122 * configure: Regenerate.
123
306f4178
MF		 1242015-06-12 Mike Frysinger <vapier@gentoo.org>
125
126 * configure.ac: Change configure.in to configure.ac.
127 * configure: Regenerate.
128
a3487082
MF		 1292015-06-12 Mike Frysinger <vapier@gentoo.org>
130
131 * configure: Regenerate.
132
29bc024d
MF		 1332015-06-12 Mike Frysinger <vapier@gentoo.org>
134
135 * interp.c [TRACE]: Delete.
136 (TRACE): Change to WITH_TRACE_ANY_P.
137 [!WITH_TRACE_ANY_P] (open_trace): Define.
138 (mips_option_handler, open_trace, sim_close, dotrace):
139 Change defined(TRACE) to WITH_TRACE_ANY_P.
140 (sim_open): Delete TRACE ifdef check.
141 * sim-main.c (load_memory): Delete TRACE ifdef check.
142 (store_memory): Likewise.
143 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
144 [!WITH_TRACE_ANY_P] (dotrace): Define.
145
3ebe2863
MF		 1462015-04-18 Mike Frysinger <vapier@gentoo.org>
147
148 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
149 comments.
150
20bca71d
MF		 1512015-04-18 Mike Frysinger <vapier@gentoo.org>
152
153 * sim-main.h (SIM_CPU): Delete.
154
7e83aa92
MF		 1552015-04-18 Mike Frysinger <vapier@gentoo.org>
156
157 * sim-main.h (sim_cia): Delete.
158
034685f9
MF		 1592015-04-17 Mike Frysinger <vapier@gentoo.org>
160
161 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
162 PU_PC_GET.
163 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
164 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
165 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
166 CIA_SET to CPU_PC_SET.
167 * sim-main.h (CIA_GET, CIA_SET): Delete.
168
78e9aa70
MF		 1692015-04-15 Mike Frysinger <vapier@gentoo.org>
170
171 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
172 * sim-main.h (STATE_CPU): Delete.
173
bf12d44e
MF		 1742015-04-13 Mike Frysinger <vapier@gentoo.org>
175
176 * configure: Regenerate.
177
7bebb329
MF		 1782015-04-13 Mike Frysinger <vapier@gentoo.org>
179
180 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
181 * interp.c (mips_pc_get, mips_pc_set): New functions.
182 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
183 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
184 (sim_pc_get): Delete.
185 * sim-main.h (SIM_CPU): Define.
186 (struct sim_state): Change cpu to an array of pointers.
187 (STATE_CPU): Drop &.
188
8ac57fbd
MF		 1892015-04-13 Mike Frysinger <vapier@gentoo.org>
190
191 * interp.c (mips_option_handler, open_trace, sim_close,
192 sim_write, sim_read, sim_store_register, sim_fetch_register,
193 sim_create_inferior, pr_addr, pr_uword64): Convert old style
194 prototypes.
195 (sim_open): Convert old style prototype. Change casts with
196 sim_write to unsigned char *.
197 (fetch_str): Change null to unsigned char, and change cast to
198 unsigned char *.
199 (sim_monitor): Change c & ch to unsigned char. Change cast to
200 unsigned char *.
201
e787f858
MF		 2022015-04-12 Mike Frysinger <vapier@gentoo.org>
203
204 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
205
122bbfb5
MF		 2062015-04-06 Mike Frysinger <vapier@gentoo.org>
207
208 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
209
0fe84f3f
MF		 2102015-04-01 Mike Frysinger <vapier@gentoo.org>
211
212 * tconfig.h (SIM_HAVE_PROFILE): Delete.
213
aadc9410
MF		 2142015-03-31 Mike Frysinger <vapier@gentoo.org>
215
216 * config.in, configure: Regenerate.
217
05f53ed6
MF		 2182015-03-24 Mike Frysinger <vapier@gentoo.org>
219
220 * interp.c (sim_pc_get): New function.
221
c0931f26
MF		 2222015-03-24 Mike Frysinger <vapier@gentoo.org>
223
224 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
225 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
226
30452bbe
MF		 2272015-03-24 Mike Frysinger <vapier@gentoo.org>
228
229 * configure: Regenerate.
230
64dd13df
MF		 2312015-03-23 Mike Frysinger <vapier@gentoo.org>
232
233 * configure: Regenerate.
234
49cd1634
MF		 2352015-03-23 Mike Frysinger <vapier@gentoo.org>
236
237 * configure: Regenerate.
238 * configure.ac (mips_extra_objs): Delete.
239 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
240 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
241
3649cb06
MF		 2422015-03-23 Mike Frysinger <vapier@gentoo.org>
243
244 * configure: Regenerate.
245 * configure.ac: Delete sim_hw checks for dv-sockser.
246
ae7d0cac
MF		 2472015-03-16 Mike Frysinger <vapier@gentoo.org>
248
249 * config.in, configure: Regenerate.
250 * tconfig.in: Rename file ...
251 * tconfig.h: ... here.
252
8406bb59
MF		 2532015-03-15 Mike Frysinger <vapier@gentoo.org>
254
255 * tconfig.in: Delete includes.
256 [HAVE_DV_SOCKSER]: Delete.
257
465fb143
MF		 2582015-03-14 Mike Frysinger <vapier@gentoo.org>
259
260 * Makefile.in (SIM_RUN_OBJS): Delete.
261
5cddc23a
MF		 2622015-03-14 Mike Frysinger <vapier@gentoo.org>
263
264 * configure.ac (AC_CHECK_HEADERS): Delete.
265 * aclocal.m4, configure: Regenerate.
266
2974be62
AM		 2672014-08-19 Alan Modra <amodra@gmail.com>
268
269 * configure: Regenerate.
270
faa743bb
RM		 2712014-08-15 Roland McGrath <mcgrathr@google.com>
272
273 * configure: Regenerate.
274 * config.in: Regenerate.
275
1a8a700e
MF		 2762014-03-04 Mike Frysinger <vapier@gentoo.org>
277
278 * configure: Regenerate.
279
bf3d9781
AM		 2802013-09-23 Alan Modra <amodra@gmail.com>
281
282 * configure: Regenerate.
283
31e6ad7d
MF		 2842013-06-03 Mike Frysinger <vapier@gentoo.org>
285
286 * aclocal.m4, configure: Regenerate.
287
d3685d60
TT		 2882013-05-10 Freddie Chopin <freddie_chopin@op.pl>
289
290 * configure: Rebuild.
291
1517bd27
MF		 2922013-03-26 Mike Frysinger <vapier@gentoo.org>
293
294 * configure: Regenerate.
295
3be31516
JS		 2962013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
297
298 * configure.ac: Address use of dv-sockser.o.
299 * tconfig.in: Conditionalize use of dv_sockser_install.
300 * configure: Regenerated.
301 * config.in: Regenerated.
302
37cb8f8e
SE		 3032012-10-04 Chao-ying Fu <fu@mips.com>
304 Steve Ellcey <sellcey@mips.com>
305
306 * mips/mips3264r2.igen (rdhwr): New.
307
87c8644f
JS		 3082012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
309
310 * configure.ac: Always link against dv-sockser.o.
311 * configure: Regenerate.
312
5f3ef9d0
JB		 3132012-06-15 Joel Brobecker <brobecker@adacore.com>
314
315 * config.in, configure: Regenerate.
316
a6ff997c
NC		 3172012-05-18 Nick Clifton <nickc@redhat.com>
318
319 PR 14072
320 * interp.c: Include config.h before system header files.
321
2232061b
MF		 3222012-03-24 Mike Frysinger <vapier@gentoo.org>
323
324 * aclocal.m4, config.in, configure: Regenerate.
325
db2e4d67
MF		 3262011-12-03 Mike Frysinger <vapier@gentoo.org>
327
328 * aclocal.m4: New file.
329 * configure: Regenerate.
330
4399a56b
MF		 3312011-10-19 Mike Frysinger <vapier@gentoo.org>
332
333 * configure: Regenerate after common/acinclude.m4 update.
334
9c082ca8
MF		 3352011-10-17 Mike Frysinger <vapier@gentoo.org>
336
337 * configure.ac: Change include to common/acinclude.m4.
338
6ffe910a
MF		 3392011-10-17 Mike Frysinger <vapier@gentoo.org>
340
341 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
342 call. Replace common.m4 include with SIM_AC_COMMON.
343 * configure: Regenerate.
344
31b28250
HPN		 3452011-07-08 Hans-Peter Nilsson <hp@axis.com>
346
3faa01e3
HPN		 347 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
348 $(SIM_EXTRA_DEPS).
349 (tmp-mach-multi): Exit early when igen fails.
31b28250 350
2419798b
MF		 3512011-07-05 Mike Frysinger <vapier@gentoo.org>
352
353 * interp.c (sim_do_command): Delete.
354
d79fe0d6
MF		 3552011-02-14 Mike Frysinger <vapier@gentoo.org>
356
357 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
358 (tx3904sio_fifo_reset): Likewise.
359 * interp.c (sim_monitor): Likewise.
360
5558e7e6
MF		 3612010-04-14 Mike Frysinger <vapier@gentoo.org>
362
363 * interp.c (sim_write): Add const to buffer arg.
364
35aafff4
JB		 3652010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
366
367 * interp.c: Don't include sysdep.h
368
3725885a
RW		 3692010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
370
371 * configure: Regenerate.
372
d6416cdc
RW		 3732009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
374
81ecdfbb
RW		 375 * config.in: Regenerate.
376 * configure: Likewise.
377
d6416cdc
RW		 378 * configure: Regenerate.
379
b5bd9624
HPN		 3802008-07-11 Hans-Peter Nilsson <hp@axis.com>
381
382 * configure: Regenerate to track ../common/common.m4 changes.
383 * config.in: Ditto.
384
6efef468 3852008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 386 Daniel Jacobowitz <dan@codesourcery.com>
387 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 388
389 * configure: Regenerate.
390
60dc88db
RS		 3912007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
392
393 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
394 that unconditionally allows fmt_ps.
395 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
396 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
397 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
398 filter from 64,f to 32,f.
399 (PREFX): Change filter from 64 to 32.
400 (LDXC1, LUXC1): Provide separate mips32r2 implementations
401 that use do_load_double instead of do_load. Make both LUXC1
402 versions unpredictable if SizeFGR () != 64.
403 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
404 instead of do_store. Remove unused variable. Make both SUXC1
405 versions unpredictable if SizeFGR () != 64.
406
599ca73e
RS		 4072007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
408
409 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
410 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
411 shifts for that case.
412
2525df03
NC		 4132007-09-04 Nick Clifton <nickc@redhat.com>
414
415 * interp.c (options enum): Add OPTION_INFO_MEMORY.
416 (display_mem_info): New static variable.
417 (mips_option_handler): Handle OPTION_INFO_MEMORY.
418 (mips_options): Add info-memory and memory-info.
419 (sim_open): After processing the command line and board
420 specification, check display_mem_info. If it is set then
421 call the real handler for the --memory-info command line
422 switch.
423
35ee6e1e
JB		 4242007-08-24 Joel Brobecker <brobecker@adacore.com>
425
426 * configure.ac: Change license of multi-run.c to GPL version 3.
427 * configure: Regenerate.
428
d5fb0879
RS		 4292007-06-28 Richard Sandiford <richard@codesourcery.com>
430
431 * configure.ac, configure: Revert last patch.
432
2a2ce21b
RS		 4332007-06-26 Richard Sandiford <richard@codesourcery.com>
434
435 * configure.ac (sim_mipsisa3264_configs): New variable.
436 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
437 every configuration support all four targets, using the triplet to
438 determine the default.
439 * configure: Regenerate.
440
efdcccc9
RS		 4412007-06-25 Richard Sandiford <richard@codesourcery.com>
442
0a7692b2 443 * Makefile.in (m16run.o): New rule.
efdcccc9 444
f532a356
TS		 4452007-05-15 Thiemo Seufer <ths@mips.com>
446
447 * mips3264r2.igen (DSHD): Fix compile warning.
448
bfe9c90b
TS		 4492007-05-14 Thiemo Seufer <ths@mips.com>
450
451 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
452 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
453 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
454 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
455 for mips32r2.
456
53f4826b
TS		 4572007-03-01 Thiemo Seufer <ths@mips.com>
458
459 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
460 and mips64.
461
8bf3ddc8
TS		 4622007-02-20 Thiemo Seufer <ths@mips.com>
463
464 * dsp.igen: Update copyright notice.
465 * dsp2.igen: Fix copyright notice.
466
8b082fb1 4672007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 468 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 469
470 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
471 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
472 Add dsp2 to sim_igen_machine.
473 * configure: Regenerate.
474 * dsp.igen (do_ph_op): Add MUL support when op = 2.
475 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
476 (mulq_rs.ph): Use do_ph_mulq.
477 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
478 * mips.igen: Add dsp2 model and include dsp2.igen.
479 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
480 for *mips32r2, *mips64r2, *dsp.
481 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
482 for *mips32r2, *mips64r2, *dsp2.
483 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
484
b1004875 4852007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 486 Nigel Stephens <nigel@mips.com>
b1004875
TS		 487
488 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
489 jumps with hazard barrier.
490
f8df4c77 4912007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 492 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 493
494 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
495 after each call to sim_io_write.
496
b1004875 4972007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 498 Nigel Stephens <nigel@mips.com>
b1004875
TS		 499
500 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
501 supported by this simulator.
07802d98
TS		 502 (decode_coproc): Recognise additional CP0 Config registers
503 correctly.
504
14fb6c5a 5052007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 506 Nigel Stephens <nigel@mips.com>
507 David Ung <davidu@mips.com>
14fb6c5a
TS		 508
509 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
510 uninterpreted formats. If fmt is one of the uninterpreted types
511 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
512 fmt_word, and fmt_uninterpreted_64 like fmt_long.
513 (store_fpr): When writing an invalid odd register, set the
514 matching even register to fmt_unknown, not the following register.
515 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
516 the the memory window at offset 0 set by --memory-size command
517 line option.
518 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
519 point register.
520 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
521 register.
522 (sim_monitor): When returning the memory size to the MIPS
523 application, use the value in STATE_MEM_SIZE, not an arbitrary
524 hardcoded value.
525 (cop_lw): Don' mess around with FPR_STATE, just pass
526 fmt_uninterpreted_32 to StoreFPR.
527 (cop_sw): Similarly.
528 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
529 (cop_sd): Similarly.
530 * mips.igen (not_word_value): Single version for mips32, mips64
531 and mips16.
532
c8847145 5332007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 534 Nigel Stephens <nigel@mips.com>
c8847145
TS		 535
536 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
537 MBytes.
538
4b5d35ee
TS		 5392007-02-17 Thiemo Seufer <ths@mips.com>
540
541 * configure.ac (mips*-sde-elf*): Move in front of generic machine
542 configuration.
543 * configure: Regenerate.
544
3669427c
TS		 5452007-02-17 Thiemo Seufer <ths@mips.com>
546
547 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
548 Add mdmx to sim_igen_machine.
549 (mipsisa64*-*-*): Likewise. Remove dsp.
550 (mipsisa32*-*-*): Remove dsp.
551 * configure: Regenerate.
552
109ad085
TS		 5532007-02-13 Thiemo Seufer <ths@mips.com>
554
555 * configure.ac: Add mips*-sde-elf* target.
556 * configure: Regenerate.
557
921d7ad3
HPN		 5582006-12-21 Hans-Peter Nilsson <hp@axis.com>
559
560 * acconfig.h: Remove.
561 * config.in, configure: Regenerate.
562
02f97da7
TS		 5632006-11-07 Thiemo Seufer <ths@mips.com>
564
565 * dsp.igen (do_w_op): Fix compiler warning.
566
2d2733fc 5672006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 568 David Ung <davidu@mips.com>
2d2733fc
TS		 569
570 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
571 sim_igen_machine.
572 * configure: Regenerate.
573 * mips.igen (model): Add smartmips.
574 (MADDU): Increment ACX if carry.
575 (do_mult): Clear ACX.
576 (ROR,RORV): Add smartmips.
72f4393d 577 (include): Include smartmips.igen.
2d2733fc
TS		 578 * sim-main.h (ACX): Set to REGISTERS[89].
579 * smartmips.igen: New file.
580
d85c3a10 5812006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 582 David Ung <davidu@mips.com>
d85c3a10
TS		 583
584 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
585 mips3264r2.igen. Add missing dependency rules.
586 * m16e.igen: Support for mips16e save/restore instructions.
587
e85e3205
RE		 5882006-06-13 Richard Earnshaw <rearnsha@arm.com>
589
590 * configure: Regenerated.
591
2f0122dc
DJ		 5922006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
593
594 * configure: Regenerated.
595
20e95c23
DJ		 5962006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
597
598 * configure: Regenerated.
599
69088b17
CF		 6002006-05-15 Chao-ying Fu <fu@mips.com>
601
602 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
603
0275de4e
NC		 6042006-04-18 Nick Clifton <nickc@redhat.com>
605
606 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
607 statement.
608
b3a3ffef
HPN		 6092006-03-29 Hans-Peter Nilsson <hp@axis.com>
610
611 * configure: Regenerate.
612
40a5538e
CF		 6132005-12-14 Chao-ying Fu <fu@mips.com>
614
615 * Makefile.in (SIM_OBJS): Add dsp.o.
616 (dsp.o): New dependency.
617 (IGEN_INCLUDE): Add dsp.igen.
618 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
619 mipsisa64*-*-*): Add dsp to sim_igen_machine.
620 * configure: Regenerate.
621 * mips.igen: Add dsp model and include dsp.igen.
622 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
623 because these instructions are extended in DSP ASE.
624 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
625 adding 6 DSP accumulator registers and 1 DSP control register.
626 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
627 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
628 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
629 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
630 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
631 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
632 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
633 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
634 DSPCR_CCOND_SMASK): New define.
635 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
636 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
637
21d14896
ILT		 6382005-07-08 Ian Lance Taylor <ian@airs.com>
639
640 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
641
b16d63da 6422005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 643 Nigel Stephens <nigel@mips.com>
644
645 * mips.igen: New mips16e model and include m16e.igen.
646 (check_u64): Add mips16e tag.
647 * m16e.igen: New file for MIPS16e instructions.
648 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
649 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
650 models.
651 * configure: Regenerate.
b16d63da 652
e70cb6cd 6532005-05-26 David Ung <davidu@mips.com>
72f4393d 654
e70cb6cd
CD		 655 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
656 tags to all instructions which are applicable to the new ISAs.
657 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
658 vr.igen.
659 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 660 instructions.
e70cb6cd
CD		 661 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
662 to mips.igen.
663 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
664 * configure: Regenerate.
72f4393d 665
2b193c4a
MK		 6662005-03-23 Mark Kettenis <kettenis@gnu.org>
667
668 * configure: Regenerate.
669
35695fd6
AC		 6702005-01-14 Andrew Cagney <cagney@gnu.org>
671
672 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
673 explicit call to AC_CONFIG_HEADER.
674 * configure: Regenerate.
675
f0569246
AC		 6762005-01-12 Andrew Cagney <cagney@gnu.org>
677
678 * configure.ac: Update to use ../common/common.m4.
679 * configure: Re-generate.
680
38f48d72
AC		 6812005-01-11 Andrew Cagney <cagney@localhost.localdomain>
682
683 * configure: Regenerated to track ../common/aclocal.m4 changes.
684
b7026657
AC		 6852005-01-07 Andrew Cagney <cagney@gnu.org>
686
687 * configure.ac: Rename configure.in, require autoconf 2.59.
688 * configure: Re-generate.
689
379832de
HPN		 6902004-12-08 Hans-Peter Nilsson <hp@axis.com>
691
692 * configure: Regenerate for ../common/aclocal.m4 update.
693
cd62154c 6942004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 695
cd62154c
AC		 696 Committed by Andrew Cagney.
697 * m16.igen (CMP, CMPI): Fix assembler.
698
e5da76ec
CD		 6992004-08-18 Chris Demetriou <cgd@broadcom.com>
700
701 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
702 * configure: Regenerate.
703
139181c8
CD		 7042004-06-25 Chris Demetriou <cgd@broadcom.com>
705
706 * configure.in (sim_m16_machine): Include mipsIII.
707 * configure: Regenerate.
708
1a27f959
CD		 7092004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
710
72f4393d 711 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 712 from COP0_BADVADDR.
713 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
714
5dbb7b5a
CD		 7152004-04-10 Chris Demetriou <cgd@broadcom.com>
716
717 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
718
14234056
CD		 7192004-04-09 Chris Demetriou <cgd@broadcom.com>
720
721 * mips.igen (check_fmt): Remove.
722 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
723 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
724 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
725 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
726 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
727 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
728 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
729 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
730 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
731 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
732
c6f9085c
CD		 7332004-04-09 Chris Demetriou <cgd@broadcom.com>
734
735 * sb1.igen (check_sbx): New function.
736 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
737
11d66e66 7382004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 739 Richard Sandiford <rsandifo@redhat.com>
740
741 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
742 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
743 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
744 separate implementations for mipsIV and mipsV. Use new macros to
745 determine whether the restrictions apply.
746
b3208fb8
CD		 7472004-01-19 Chris Demetriou <cgd@broadcom.com>
748
749 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
750 (check_mult_hilo): Improve comments.
751 (check_div_hilo): Likewise. Also, fork off a new version
752 to handle mips32/mips64 (since there are no hazards to check
753 in MIPS32/MIPS64).
754
9a1d84fb
CD		 7552003-06-17 Richard Sandiford <rsandifo@redhat.com>
756
757 * mips.igen (do_dmultx): Fix check for negative operands.
758
ae451ac6
ILT		 7592003-05-16 Ian Lance Taylor <ian@airs.com>
760
761 * Makefile.in (SHELL): Make sure this is defined.
762 (various): Use $(SHELL) whenever we invoke move-if-change.
763
dd69d292
CD		 7642003-05-03 Chris Demetriou <cgd@broadcom.com>
765
766 * cp1.c: Tweak attribution slightly.
767 * cp1.h: Likewise.
768 * mdmx.c: Likewise.
769 * mdmx.igen: Likewise.
770 * mips3d.igen: Likewise.
771 * sb1.igen: Likewise.
772
bcd0068e
CD		 7732003-04-15 Richard Sandiford <rsandifo@redhat.com>
774
775 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
776 unsigned operands.
777
6b4a8935
AC		 7782003-02-27 Andrew Cagney <cagney@redhat.com>
779
601da316
AC		 780 * interp.c (sim_open): Rename _bfd to bfd.
781 (sim_create_inferior): Ditto.
6b4a8935 782
d29e330f
CD		 7832003-01-14 Chris Demetriou <cgd@broadcom.com>
784
785 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
786
a2353a08
CD		 7872003-01-14 Chris Demetriou <cgd@broadcom.com>
788
789 * mips.igen (EI, DI): Remove.
790
80551777
CD		 7912003-01-05 Richard Sandiford <rsandifo@redhat.com>
792
793 * Makefile.in (tmp-run-multi): Fix mips16 filter.
794
4c54fc26
CD		 7952003-01-04 Richard Sandiford <rsandifo@redhat.com>
796 Andrew Cagney <ac131313@redhat.com>
797 Gavin Romig-Koch <gavin@redhat.com>
798 Graydon Hoare <graydon@redhat.com>
799 Aldy Hernandez <aldyh@redhat.com>
800 Dave Brolley <brolley@redhat.com>
801 Chris Demetriou <cgd@broadcom.com>
802
803 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
804 (sim_mach_default): New variable.
805 (mips64vr-*-*, mips64vrel-*-*): New configurations.
806 Add a new simulator generator, MULTI.
807 * configure: Regenerate.
808 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
809 (multi-run.o): New dependency.
810 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
811 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
812 (tmp-multi): Combine them.
813 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
814 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
815 (distclean-extra): New rule.
816 * sim-main.h: Include bfd.h.
817 (MIPS_MACH): New macro.
818 * mips.igen (vr4120, vr5400, vr5500): New models.
819 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
820 * vr.igen: Replace with new version.
821
e6c674b8
CD		 8222003-01-04 Chris Demetriou <cgd@broadcom.com>
823
824 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
825 * configure: Regenerate.
826
28f50ac8
CD		 8272002-12-31 Chris Demetriou <cgd@broadcom.com>
828
829 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
830 * mips.igen: Remove all invocations of check_branch_bug and
831 mark_branch_bug.
832
5071ffe6
CD		 8332002-12-16 Chris Demetriou <cgd@broadcom.com>
834
72f4393d 835 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 836
06e7837e
CD		 8372002-07-30 Chris Demetriou <cgd@broadcom.com>
838
839 * mips.igen (do_load_double, do_store_double): New functions.
840 (LDC1, SDC1): Rename to...
841 (LDC1b, SDC1b): respectively.
842 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
843
2265c243
MS		 8442002-07-29 Michael Snyder <msnyder@redhat.com>
845
846 * cp1.c (fp_recip2): Modify initialization expression so that
847 GCC will recognize it as constant.
848
a2f8b4f3
CD		 8492002-06-18 Chris Demetriou <cgd@broadcom.com>
850
851 * mdmx.c (SD_): Delete.
852 (Unpredictable): Re-define, for now, to directly invoke
853 unpredictable_action().
854 (mdmx_acc_op): Fix error in .ob immediate handling.
855
b4b6c939
AC		 8562002-06-18 Andrew Cagney <cagney@redhat.com>
857
858 * interp.c (sim_firmware_command): Initialize `address'.
859
c8cca39f
AC		 8602002-06-16 Andrew Cagney <ac131313@redhat.com>
861
862 * configure: Regenerated to track ../common/aclocal.m4 changes.
863
e7e81181 8642002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 865 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 866
867 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
868 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
869 * mips.igen: Include mips3d.igen.
870 (mips3d): New model name for MIPS-3D ASE instructions.
871 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 872 instructions.
e7e81181
CD		 873 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
874 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
875 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
876 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
877 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
878 (RSquareRoot1, RSquareRoot2): New macros.
879 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
880 (fp_rsqrt2): New functions.
881 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
882 * configure: Regenerate.
883
3a2b820e 8842002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 885 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 886
887 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
888 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
889 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
890 (convert): Note that this function is not used for paired-single
891 format conversions.
892 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
893 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
894 (check_fmt_p): Enable paired-single support.
895 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
896 (PUU.PS): New instructions.
897 (CVT.S.fmt): Don't use this instruction for paired-single format
898 destinations.
899 * sim-main.h (FP_formats): New value 'fmt_ps.'
900 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
901 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
902
d18ea9c2
CD		 9032002-06-12 Chris Demetriou <cgd@broadcom.com>
904
905 * mips.igen: Fix formatting of function calls in
906 many FP operations.
907
95fd5cee
CD		 9082002-06-12 Chris Demetriou <cgd@broadcom.com>
909
910 * mips.igen (MOVN, MOVZ): Trace result.
911 (TNEI): Print "tnei" as the opcode name in traces.
912 (CEIL.W): Add disassembly string for traces.
913 (RSQRT.fmt): Make location of disassembly string consistent
914 with other instructions.
915
4f0d55ae
CD		 9162002-06-12 Chris Demetriou <cgd@broadcom.com>
917
918 * mips.igen (X): Delete unused function.
919
3c25f8c7
AC		 9202002-06-08 Andrew Cagney <cagney@redhat.com>
921
922 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
923
f3c08b7e 9242002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 925 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 926
927 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
928 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
929 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
930 (fp_nmsub): New prototypes.
931 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
932 (NegMultiplySub): New defines.
933 * mips.igen (RSQRT.fmt): Use RSquareRoot().
934 (MADD.D, MADD.S): Replace with...
935 (MADD.fmt): New instruction.
936 (MSUB.D, MSUB.S): Replace with...
937 (MSUB.fmt): New instruction.
938 (NMADD.D, NMADD.S): Replace with...
939 (NMADD.fmt): New instruction.
940 (NMSUB.D, MSUB.S): Replace with...
941 (NMSUB.fmt): New instruction.
942
52714ff9 9432002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 944 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 945
946 * cp1.c: Fix more comment spelling and formatting.
947 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
948 (denorm_mode): New function.
949 (fpu_unary, fpu_binary): Round results after operation, collect
950 status from rounding operations, and update the FCSR.
951 (convert): Collect status from integer conversions and rounding
952 operations, and update the FCSR. Adjust NaN values that result
953 from conversions. Convert to use sim_io_eprintf rather than
954 fprintf, and remove some debugging code.
955 * cp1.h (fenr_FS): New define.
956
577d8c4b
CD		 9572002-06-07 Chris Demetriou <cgd@broadcom.com>
958
959 * cp1.c (convert): Remove unusable debugging code, and move MIPS
960 rounding mode to sim FP rounding mode flag conversion code into...
961 (rounding_mode): New function.
962
196496ed
CD		 9632002-06-07 Chris Demetriou <cgd@broadcom.com>
964
965 * cp1.c: Clean up formatting of a few comments.
966 (value_fpr): Reformat switch statement.
967
cfe9ea23 9682002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 969 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 970
971 * cp1.h: New file.
972 * sim-main.h: Include cp1.h.
973 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
974 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
975 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
976 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
977 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
978 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
979 * cp1.c: Don't include sim-fpu.h; already included by
980 sim-main.h. Clean up formatting of some comments.
981 (NaN, Equal, Less): Remove.
982 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
983 (fp_cmp): New functions.
984 * mips.igen (do_c_cond_fmt): Remove.
985 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
986 Compare. Add result tracing.
987 (CxC1): Remove, replace with...
988 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
989 (DMxC1): Remove, replace with...
990 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 991 (MxC1): Remove, replace with...
992 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 993
ee7254b0
CD		 9942002-06-04 Chris Demetriou <cgd@broadcom.com>
995
996 * sim-main.h (FGRIDX): Remove, replace all uses with...
997 (FGR_BASE): New macro.
998 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
999 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1000 (NR_FGR, FGR): Likewise.
1001 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1002 * mips.igen: Likewise.
1003
d3eb724f
CD		 10042002-06-04 Chris Demetriou <cgd@broadcom.com>
1005
1006 * cp1.c: Add an FSF Copyright notice to this file.
1007
ba46ddd0 10082002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1009 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1010
1011 * cp1.c (Infinity): Remove.
1012 * sim-main.h (Infinity): Likewise.
1013
1014 * cp1.c (fp_unary, fp_binary): New functions.
1015 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1016 (fp_sqrt): New functions, implemented in terms of the above.
1017 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1018 (Recip, SquareRoot): Remove (replaced by functions above).
1019 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1020 (fp_recip, fp_sqrt): New prototypes.
1021 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1022 (Recip, SquareRoot): Replace prototypes with #defines which
1023 invoke the functions above.
72f4393d 1024
18d8a52d
CD		 10252002-06-03 Chris Demetriou <cgd@broadcom.com>
1026
1027 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1028 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1029 file, remove PARAMS from prototypes.
1030 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1031 simulator state arguments.
1032 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1033 pass simulator state arguments.
1034 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1035 (store_fpr, convert): Remove 'sd' argument.
1036 (value_fpr): Likewise. Convert to use 'SD' instead.
1037
0f154cbd
CD		 10382002-06-03 Chris Demetriou <cgd@broadcom.com>
1039
1040 * cp1.c (Min, Max): Remove #if 0'd functions.
1041 * sim-main.h (Min, Max): Remove.
1042
e80fc152
CD		 10432002-06-03 Chris Demetriou <cgd@broadcom.com>
1044
1045 * cp1.c: fix formatting of switch case and default labels.
1046 * interp.c: Likewise.
1047 * sim-main.c: Likewise.
1048
bad673a9
CD		 10492002-06-03 Chris Demetriou <cgd@broadcom.com>
1050
1051 * cp1.c: Clean up comments which describe FP formats.
1052 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1053
7cbea089 10542002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1055 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1056
1057 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1058 Broadcom SiByte SB-1 processor configurations.
1059 * configure: Regenerate.
1060 * sb1.igen: New file.
1061 * mips.igen: Include sb1.igen.
1062 (sb1): New model.
1063 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1064 * mdmx.igen: Add "sb1" model to all appropriate functions and
1065 instructions.
1066 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1067 (ob_func, ob_acc): Reference the above.
1068 (qh_acc): Adjust to keep the same size as ob_acc.
1069 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1070 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1071
909daa82
CD		 10722002-06-03 Chris Demetriou <cgd@broadcom.com>
1073
1074 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1075
f4f1b9f1 10762002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1077 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1078
1079 * mips.igen (mdmx): New (pseudo-)model.
1080 * mdmx.c, mdmx.igen: New files.
1081 * Makefile.in (SIM_OBJS): Add mdmx.o.
1082 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1083 New typedefs.
1084 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1085 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1086 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1087 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1088 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1089 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1090 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1091 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1092 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1093 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1094 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1095 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1096 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1097 (qh_fmtsel): New macros.
1098 (_sim_cpu): New member "acc".
1099 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1100 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1101
5accf1ff
CD		 11022002-05-01 Chris Demetriou <cgd@broadcom.com>
1103
1104 * interp.c: Use 'deprecated' rather than 'depreciated.'
1105 * sim-main.h: Likewise.
1106
402586aa
CD		 11072002-05-01 Chris Demetriou <cgd@broadcom.com>
1108
1109 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1110 which wouldn't compile anyway.
1111 * sim-main.h (unpredictable_action): New function prototype.
1112 (Unpredictable): Define to call igen function unpredictable().
1113 (NotWordValue): New macro to call igen function not_word_value().
1114 (UndefinedResult): Remove.
1115 * interp.c (undefined_result): Remove.
1116 (unpredictable_action): New function.
1117 * mips.igen (not_word_value, unpredictable): New functions.
1118 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1119 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1120 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1121 NotWordValue() to check for unpredictable inputs, then
1122 Unpredictable() to handle them.
1123
c9b9995a
CD		 11242002-02-24 Chris Demetriou <cgd@broadcom.com>
1125
1126 * mips.igen: Fix formatting of calls to Unpredictable().
1127
e1015982
AC		 11282002-04-20 Andrew Cagney <ac131313@redhat.com>
1129
1130 * interp.c (sim_open): Revert previous change.
1131
b882a66b
AO		 11322002-04-18 Alexandre Oliva <aoliva@redhat.com>
1133
1134 * interp.c (sim_open): Disable chunk of code that wrote code in
1135 vector table entries.
1136
c429b7dd
CD		 11372002-03-19 Chris Demetriou <cgd@broadcom.com>
1138
1139 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1140 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1141 unused definitions.
1142
37d146fa
CD		 11432002-03-19 Chris Demetriou <cgd@broadcom.com>
1144
1145 * cp1.c: Fix many formatting issues.
1146
07892c0b
CD		 11472002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1148
1149 * cp1.c (fpu_format_name): New function to replace...
1150 (DOFMT): This. Delete, and update all callers.
1151 (fpu_rounding_mode_name): New function to replace...
1152 (RMMODE): This. Delete, and update all callers.
1153
487f79b7
CD		 11542002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1155
1156 * interp.c: Move FPU support routines from here to...
1157 * cp1.c: Here. New file.
1158 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1159 (cp1.o): New target.
1160
1e799e28
CD		 11612002-03-12 Chris Demetriou <cgd@broadcom.com>
1162
1163 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1164 * mips.igen (mips32, mips64): New models, add to all instructions
1165 and functions as appropriate.
1166 (loadstore_ea, check_u64): New variant for model mips64.
1167 (check_fmt_p): New variant for models mipsV and mips64, remove
1168 mipsV model marking fro other variant.
1169 (SLL) Rename to...
1170 (SLLa) this.
1171 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1172 for mips32 and mips64.
1173 (DCLO, DCLZ): New instructions for mips64.
1174
82f728db
CD		 11752002-03-07 Chris Demetriou <cgd@broadcom.com>
1176
1177 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1178 immediate or code as a hex value with the "%#lx" format.
1179 (ANDI): Likewise, and fix printed instruction name.
1180
b96e7ef1
CD		 11812002-03-05 Chris Demetriou <cgd@broadcom.com>
1182
1183 * sim-main.h (UndefinedResult, Unpredictable): New macros
1184 which currently do nothing.
1185
d35d4f70
CD		 11862002-03-05 Chris Demetriou <cgd@broadcom.com>
1187
1188 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1189 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1190 (status_CU3): New definitions.
1191
1192 * sim-main.h (ExceptionCause): Add new values for MIPS32
1193 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1194 for DebugBreakPoint and NMIReset to note their status in
1195 MIPS32 and MIPS64.
1196 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1197 (SignalExceptionCacheErr): New exception macros.
1198
3ad6f714
CD		 11992002-03-05 Chris Demetriou <cgd@broadcom.com>
1200
1201 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1202 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1203 is always enabled.
1204 (SignalExceptionCoProcessorUnusable): Take as argument the
1205 unusable coprocessor number.
1206
86b77b47
CD		 12072002-03-05 Chris Demetriou <cgd@broadcom.com>
1208
1209 * mips.igen: Fix formatting of all SignalException calls.
1210
97a88e93 12112002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1212
1213 * sim-main.h (SIGNEXTEND): Remove.
1214
97a88e93 12152002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1216
1217 * mips.igen: Remove gencode comment from top of file, fix
1218 spelling in another comment.
1219
97a88e93 12202002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1221
1222 * mips.igen (check_fmt, check_fmt_p): New functions to check
1223 whether specific floating point formats are usable.
1224 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1225 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1226 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1227 Use the new functions.
1228 (do_c_cond_fmt): Remove format checks...
1229 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1230
97a88e93 12312002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1232
1233 * mips.igen: Fix formatting of check_fpu calls.
1234
41774c9d
CD		 12352002-03-03 Chris Demetriou <cgd@broadcom.com>
1236
1237 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1238
4a0bd876
CD		 12392002-03-03 Chris Demetriou <cgd@broadcom.com>
1240
1241 * mips.igen: Remove whitespace at end of lines.
1242
09297648
CD		 12432002-03-02 Chris Demetriou <cgd@broadcom.com>
1244
1245 * mips.igen (loadstore_ea): New function to do effective
1246 address calculations.
1247 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1248 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1249 CACHE): Use loadstore_ea to do effective address computations.
1250
043b7057
CD		 12512002-03-02 Chris Demetriou <cgd@broadcom.com>
1252
1253 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1254 * mips.igen (LL, CxC1, MxC1): Likewise.
1255
c1e8ada4
CD		 12562002-03-02 Chris Demetriou <cgd@broadcom.com>
1257
1258 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1259 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1260 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1261 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1262 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1263 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1264 Don't split opcode fields by hand, use the opcode field values
1265 provided by igen.
1266
3e1dca16
CD		 12672002-03-01 Chris Demetriou <cgd@broadcom.com>
1268
1269 * mips.igen (do_divu): Fix spacing.
1270
1271 * mips.igen (do_dsllv): Move to be right before DSLLV,
1272 to match the rest of the do_<shift> functions.
1273
fff8d27d
CD		 12742002-03-01 Chris Demetriou <cgd@broadcom.com>
1275
1276 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1277 DSRL32, do_dsrlv): Trace inputs and results.
1278
0d3e762b
CD		 12792002-03-01 Chris Demetriou <cgd@broadcom.com>
1280
1281 * mips.igen (CACHE): Provide instruction-printing string.
1282
1283 * interp.c (signal_exception): Comment tokens after #endif.
1284
eb5fcf93
CD		 12852002-02-28 Chris Demetriou <cgd@broadcom.com>
1286
1287 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1288 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1289 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1290 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1291 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1292 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1293 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1294 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1295
bb22bd7d
CD		 12962002-02-28 Chris Demetriou <cgd@broadcom.com>
1297
1298 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1299 instruction-printing string.
1300 (LWU): Use '64' as the filter flag.
1301
91a177cf
CD		 13022002-02-28 Chris Demetriou <cgd@broadcom.com>
1303
1304 * mips.igen (SDXC1): Fix instruction-printing string.
1305
387f484a
CD		 13062002-02-28 Chris Demetriou <cgd@broadcom.com>
1307
1308 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1309 filter flags "32,f".
1310
3d81f391
CD		 13112002-02-27 Chris Demetriou <cgd@broadcom.com>
1312
1313 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1314 as the filter flag.
1315
af5107af
CD		 13162002-02-27 Chris Demetriou <cgd@broadcom.com>
1317
1318 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1319 add a comma) so that it more closely match the MIPS ISA
1320 documentation opcode partitioning.
1321 (PREF): Put useful names on opcode fields, and include
1322 instruction-printing string.
1323
ca971540
CD		 13242002-02-27 Chris Demetriou <cgd@broadcom.com>
1325
1326 * mips.igen (check_u64): New function which in the future will
1327 check whether 64-bit instructions are usable and signal an
1328 exception if not. Currently a no-op.
1329 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1330 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1331 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1332 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1333
1334 * mips.igen (check_fpu): New function which in the future will
1335 check whether FPU instructions are usable and signal an exception
1336 if not. Currently a no-op.
1337 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1338 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1339 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1340 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1341 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1342 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1343 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1344 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1345
1c47a468
CD		 13462002-02-27 Chris Demetriou <cgd@broadcom.com>
1347
1348 * mips.igen (do_load_left, do_load_right): Move to be immediately
1349 following do_load.
1350 (do_store_left, do_store_right): Move to be immediately following
1351 do_store.
1352
603a98e7
CD		 13532002-02-27 Chris Demetriou <cgd@broadcom.com>
1354
1355 * mips.igen (mipsV): New model name. Also, add it to
1356 all instructions and functions where it is appropriate.
1357
c5d00cc7
CD		 13582002-02-18 Chris Demetriou <cgd@broadcom.com>
1359
1360 * mips.igen: For all functions and instructions, list model
1361 names that support that instruction one per line.
1362
074e9cb8
CD		 13632002-02-11 Chris Demetriou <cgd@broadcom.com>
1364
1365 * mips.igen: Add some additional comments about supported
1366 models, and about which instructions go where.
1367 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1368 order as is used in the rest of the file.
1369
9805e229
CD		 13702002-02-11 Chris Demetriou <cgd@broadcom.com>
1371
1372 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1373 indicating that ALU32_END or ALU64_END are there to check
1374 for overflow.
1375 (DADD): Likewise, but also remove previous comment about
1376 overflow checking.
1377
f701dad2
CD		 13782002-02-10 Chris Demetriou <cgd@broadcom.com>
1379
1380 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1381 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1382 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1383 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1384 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1385 fields (i.e., add and move commas) so that they more closely
1386 match the MIPS ISA documentation opcode partitioning.
1387
13882002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1389
72f4393d
L		 1390 * mips.igen (ADDI): Print immediate value.
1391 (BREAK): Print code.
1392 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1393 (SLL): Print "nop" specially, and don't run the code
1394 that does the shift for the "nop" case.
20ae0098 1395
9e52972e
FF		 13962001-11-17 Fred Fish <fnf@redhat.com>
1397
1398 * sim-main.h (float_operation): Move enum declaration outside
1399 of _sim_cpu struct declaration.
1400
c0efbca4
JB		 14012001-04-12 Jim Blandy <jimb@redhat.com>
1402
1403 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1404 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1405 set of the FCSR.
1406 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1407 PENDING_FILL, and you can get the intended effect gracefully by
1408 calling PENDING_SCHED directly.
1409
fb891446
BE		 14102001-02-23 Ben Elliston <bje@redhat.com>
1411
1412 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1413 already defined elsewhere.
1414
8030f857
BE		 14152001-02-19 Ben Elliston <bje@redhat.com>
1416
1417 * sim-main.h (sim_monitor): Return an int.
1418 * interp.c (sim_monitor): Add return values.
1419 (signal_exception): Handle error conditions from sim_monitor.
1420
56b48a7a
CD		 14212001-02-08 Ben Elliston <bje@redhat.com>
1422
1423 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1424 (store_memory): Likewise, pass cia to sim_core_write*.
1425
d3ee60d9
FCE		 14262000-10-19 Frank Ch. Eigler <fche@redhat.com>
1427
1428 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1429 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1430
071da002
AC		 1431Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1432
1433 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1434 * Makefile.in: Don't delete *.igen when cleaning directory.
1435
a28c02cd
AC		 1436Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1437
1438 * m16.igen (break): Call SignalException not sim_engine_halt.
1439
80ee11fa
AC		 1440Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1441
1442 From Jason Eckhardt:
1443 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1444
673388c0
AC		 1445Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1446
1447 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1448
4c0deff4
NC		 14492000-05-24 Michael Hayes <mhayes@cygnus.com>
1450
1451 * mips.igen (do_dmultx): Fix typo.
1452
eb2d80b4
AC		 1453Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1454
1455 * configure: Regenerated to track ../common/aclocal.m4 changes.
1456
dd37a34b
AC		 1457Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1458
1459 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1460
4c0deff4
NC		 14612000-04-12 Frank Ch. Eigler <fche@redhat.com>
1462
1463 * sim-main.h (GPR_CLEAR): Define macro.
1464
e30db738
AC		 1465Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1466
1467 * interp.c (decode_coproc): Output long using %lx and not %s.
1468
cb7450ea
FCE		 14692000-03-21 Frank Ch. Eigler <fche@redhat.com>
1470
1471 * interp.c (sim_open): Sort & extend dummy memory regions for
1472 --board=jmr3904 for eCos.
1473
a3027dd7
FCE		 14742000-03-02 Frank Ch. Eigler <fche@redhat.com>
1475
1476 * configure: Regenerated.
1477
1478Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1479
1480 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1481 calls, conditional on the simulator being in verbose mode.
1482
dfcd3bfb
JM		 1483Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1484
1485 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1486 cache don't get ReservedInstruction traps.
1487
c2d11a7d
JM		 14881999-11-29 Mark Salter <msalter@cygnus.com>
1489
1490 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1491 to clear status bits in sdisr register. This is how the hardware works.
1492
1493 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1494 being used by cygmon.
1495
4ce44c66
JM		 14961999-11-11 Andrew Haley <aph@cygnus.com>
1497
1498 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1499 instructions.
1500
cff3e48b
JM		 1501Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1502
1503 * mips.igen (MULT): Correct previous mis-applied patch.
1504
d4f3574e
SS		 1505Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1506
1507 * mips.igen (delayslot32): Handle sequence like
1508 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1509 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1510 (MULT): Actually pass the third register...
1511
15121999-09-03 Mark Salter <msalter@cygnus.com>
1513
1514 * interp.c (sim_open): Added more memory aliases for additional
1515 hardware being touched by cygmon on jmr3904 board.
1516
1517Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1518
1519 * configure: Regenerated to track ../common/aclocal.m4 changes.
1520
a0b3c4fd
JM		 1521Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1522
1523 * interp.c (sim_store_register): Handle case where client - GDB -
1524 specifies that a 4 byte register is 8 bytes in size.
1525 (sim_fetch_register): Ditto.
72f4393d 1526
adf40b2e
JM		 15271999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1528
1529 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1530 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1531 (idt_monitor_base): Base address for IDT monitor traps.
1532 (pmon_monitor_base): Ditto for PMON.
1533 (lsipmon_monitor_base): Ditto for LSI PMON.
1534 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1535 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1536 (sim_firmware_command): New function.
1537 (mips_option_handler): Call it for OPTION_FIRMWARE.
1538 (sim_open): Allocate memory for idt_monitor region. If "--board"
1539 option was given, add no monitor by default. Add BREAK hooks only if
1540 monitors are also there.
72f4393d 1541
43e526b9
JM		 1542Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1543
1544 * interp.c (sim_monitor): Flush output before reading input.
1545
1546Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * tconfig.in (SIM_HANDLES_LMA): Always define.
1549
1550Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 From Mark Salter <msalter@cygnus.com>:
1553 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1554 (sim_open): Add setup for BSP board.
1555
9846de1b
JM		 1556Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1557
1558 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1559 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1560 them as unimplemented.
1561
cd0fc7c3
SS		 15621999-05-08 Felix Lee <flee@cygnus.com>
1563
1564 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1565
7a292a7a
SS		 15661999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1567
1568 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1569
1570Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1571
1572 * configure.in: Any mips64vr5*-*-* target should have
1573 -DTARGET_ENABLE_FR=1.
1574 (default_endian): Any mips64vr*el-*-* target should default to
1575 LITTLE_ENDIAN.
1576 * configure: Re-generate.
1577
15781999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1579
1580 * mips.igen (ldl): Extend from _16_, not 32.
1581
1582Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1583
1584 * interp.c (sim_store_register): Force registers written to by GDB
1585 into an un-interpreted state.
1586
c906108c
SS		 15871999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1588
1589 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1590 CPU, start periodic background I/O polls.
72f4393d 1591 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1592
15931998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1594
1595 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1596
c906108c
SS		 1597Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1598
1599 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1600 case statement.
1601
16021998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1603
1604 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1605 (load_word): Call SIM_CORE_SIGNAL hook on error.
1606 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1607 starting. For exception dispatching, pass PC instead of NULL_CIA.
1608 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1609 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1610 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1611 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1612 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1613 * mips.igen (*): Replace memory-related SignalException* calls
1614 with references to SIM_CORE_SIGNAL hook.
72f4393d 1615
c906108c
SS		 1616 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1617 fix.
1618 * sim-main.c (*): Minor warning cleanups.
72f4393d 1619
c906108c
SS		 16201998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1621
1622 * m16.igen (DADDIU5): Correct type-o.
1623
1624Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1625
1626 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1627 variables.
1628
1629Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1630
1631 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1632 to include path.
1633 (interp.o): Add dependency on itable.h
1634 (oengine.c, gencode): Delete remaining references.
1635 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1636
c906108c 16371998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1638
c906108c
SS		 1639 * vr4run.c: New.
1640 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1641 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1642 tmp-run-hack) : New.
1643 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1644 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1645 Drop the "64" qualifier to get the HACK generator working.
1646 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1647 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1648 qualifier to get the hack generator working.
1649 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1650 (DSLL): Use do_dsll.
1651 (DSLLV): Use do_dsllv.
1652 (DSRA): Use do_dsra.
1653 (DSRL): Use do_dsrl.
1654 (DSRLV): Use do_dsrlv.
1655 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1656 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1657 get the HACK generator working.
1658 (MACC) Rename to get the HACK generator working.
1659 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1660
c906108c
SS		 16611998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1662
1663 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1664 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1665
c906108c
SS		 16661998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1667
1668 * mips/interp.c (DEBUG): Cleanups.
1669
16701998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1671
1672 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1673 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1674
c906108c
SS		 16751998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1676
1677 * interp.c (sim_close): Uninstall modules.
1678
1679Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1680
1681 * sim-main.h, interp.c (sim_monitor): Change to global
1682 function.
1683
1684Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1685
1686 * configure.in (vr4100): Only include vr4100 instructions in
1687 simulator.
1688 * configure: Re-generate.
1689 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1690
1691Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1692
1693 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1694 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1695 true alternative.
1696
1697 * configure.in (sim_default_gen, sim_use_gen): Replace with
1698 sim_gen.
1699 (--enable-sim-igen): Delete config option. Always using IGEN.
1700 * configure: Re-generate.
72f4393d 1701
c906108c
SS		 1702 * Makefile.in (gencode): Kill, kill, kill.
1703 * gencode.c: Ditto.
72f4393d 1704
c906108c
SS		 1705Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1706
1707 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1708 bit mips16 igen simulator.
1709 * configure: Re-generate.
1710
1711 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1712 as part of vr4100 ISA.
1713 * vr.igen: Mark all instructions as 64 bit only.
1714
1715Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1716
1717 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1718 Pacify GCC.
1719
1720Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1721
1722 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1723 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1724 * configure: Re-generate.
1725
1726 * m16.igen (BREAK): Define breakpoint instruction.
1727 (JALX32): Mark instruction as mips16 and not r3900.
1728 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1729
1730 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1731
1732Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1733
1734 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1735 insn as a debug breakpoint.
1736
1737 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1738 pending.slot_size.
1739 (PENDING_SCHED): Clean up trace statement.
1740 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1741 (PENDING_FILL): Delay write by only one cycle.
1742 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1743
1744 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1745 of pending writes.
1746 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1747 32 & 64.
1748 (pending_tick): Move incrementing of index to FOR statement.
1749 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1750
c906108c
SS		 1751 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1752 build simulator.
1753 * configure: Re-generate.
72f4393d 1754
c906108c
SS		 1755 * interp.c (sim_engine_run OLD): Delete explicit call to
1756 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1757
c906108c
SS		 1758Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1759
1760 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1761 interrupt level number to match changed SignalExceptionInterrupt
1762 macro.
1763
1764Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1765
1766 * interp.c: #include "itable.h" if WITH_IGEN.
1767 (get_insn_name): New function.
1768 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1769 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1770
1771Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1772
1773 * configure: Rebuilt to inhale new common/aclocal.m4.
1774
1775Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1776
1777 * dv-tx3904sio.c: Include sim-assert.h.
1778
1779Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1780
1781 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1782 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1783 Reorganize target-specific sim-hardware checks.
1784 * configure: rebuilt.
1785 * interp.c (sim_open): For tx39 target boards, set
1786 OPERATING_ENVIRONMENT, add tx3904sio devices.
1787 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1788 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1789
c906108c
SS		 1790 * dv-tx3904irc.c: Compiler warning clean-up.
1791 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1792 frequent hw-trace messages.
1793
1794Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1795
1796 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1797
1798Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799
1800 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1801
1802 * vr.igen: New file.
1803 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1804 * mips.igen: Define vr4100 model. Include vr.igen.
1805Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1806
1807 * mips.igen (check_mf_hilo): Correct check.
1808
1809Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1810
1811 * sim-main.h (interrupt_event): Add prototype.
1812
1813 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1814 register_ptr, register_value.
1815 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1816
1817 * sim-main.h (tracefh): Make extern.
1818
1819Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1820
1821 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1822 Reduce unnecessarily high timer event frequency.
c906108c 1823 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1824
c906108c
SS		 1825Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1826
1827 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1828 to allay warnings.
1829 (interrupt_event): Made non-static.
72f4393d 1830
c906108c
SS		 1831 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1832 interchange of configuration values for external vs. internal
1833 clock dividers.
72f4393d 1834
c906108c
SS		 1835Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1836
72f4393d 1837 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1838 simulator-reserved break instructions.
1839 * gencode.c (build_instruction): Ditto.
1840 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1841 reserved instructions now use exception vector, rather
c906108c
SS		 1842 than halting sim.
1843 * sim-main.h: Moved magic constants to here.
1844
1845Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1846
1847 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1848 register upon non-zero interrupt event level, clear upon zero
1849 event value.
1850 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1851 by passing zero event value.
1852 (*_io_{read,write}_buffer): Endianness fixes.
1853 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1854 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1855
1856 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1857 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1858
c906108c
SS		 1859Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1860
72f4393d 1861 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1862 and BigEndianCPU.
1863
1864Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1865
1866 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1867 parts.
1868 * configure: Update.
1869
1870Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1871
1872 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1873 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1874 * configure.in: Include tx3904tmr in hw_device list.
1875 * configure: Rebuilt.
1876 * interp.c (sim_open): Instantiate three timer instances.
1877 Fix address typo of tx3904irc instance.
1878
1879Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1880
1881 * interp.c (signal_exception): SystemCall exception now uses
1882 the exception vector.
1883
1884Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1885
1886 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1887 to allay warnings.
1888
1889Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1892
1893Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1896
1897 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1898 sim-main.h. Declare a struct hw_descriptor instead of struct
1899 hw_device_descriptor.
1900
1901Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1902
1903 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1904 right bits and then re-align left hand bytes to correct byte
1905 lanes. Fix incorrect computation in do_store_left when loading
1906 bytes from second word.
1907
1908Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1909
1910 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1911 * interp.c (sim_open): Only create a device tree when HW is
1912 enabled.
1913
1914 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1915 * interp.c (signal_exception): Ditto.
1916
1917Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1918
1919 * gencode.c: Mark BEGEZALL as LIKELY.
1920
1921Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1922
1923 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1924 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1925
c906108c
SS		 1926Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1927
1928 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1929 modules. Recognize TX39 target with "mips*tx39" pattern.
1930 * configure: Rebuilt.
1931 * sim-main.h (*): Added many macros defining bits in
1932 TX39 control registers.
1933 (SignalInterrupt): Send actual PC instead of NULL.
1934 (SignalNMIReset): New exception type.
1935 * interp.c (board): New variable for future use to identify
1936 a particular board being simulated.
1937 (mips_option_handler,mips_options): Added "--board" option.
1938 (interrupt_event): Send actual PC.
1939 (sim_open): Make memory layout conditional on board setting.
1940 (signal_exception): Initial implementation of hardware interrupt
1941 handling. Accept another break instruction variant for simulator
1942 exit.
1943 (decode_coproc): Implement RFE instruction for TX39.
1944 (mips.igen): Decode RFE instruction as such.
1945 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1946 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1947 bbegin to implement memory map.
1948 * dv-tx3904cpu.c: New file.
1949 * dv-tx3904irc.c: New file.
1950
1951Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
1952
1953 * mips.igen (check_mt_hilo): Create a separate r3900 version.
1954
1955Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
1956
1957 * tx.igen (madd,maddu): Replace calls to check_op_hilo
1958 with calls to check_div_hilo.
1959
1960Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
1961
1962 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1963 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 1964 Add special r3900 version of do_mult_hilo.
c906108c
SS		 1965 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1966 with calls to check_mult_hilo.
1967 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1968 with calls to check_div_hilo.
1969
1970Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
1971
1972 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1973 Document a replacement.
1974
1975Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
1976
1977 * interp.c (sim_monitor): Make mon_printf work.
1978
1979Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
1980
1981 * sim-main.h (INSN_NAME): New arg `cpu'.
1982
1983Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
1984
72f4393d 1985 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 1986
1987Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
1988
1989 * configure: Regenerated to track ../common/aclocal.m4 changes.
1990 * config.in: Ditto.
1991
1992Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
1993
1994 * acconfig.h: New file.
1995 * configure.in: Reverted change of Apr 24; use sinclude again.
1996
1997Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
1998
1999 * configure: Regenerated to track ../common/aclocal.m4 changes.
2000 * config.in: Ditto.
2001
2002Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2003
2004 * configure.in: Don't call sinclude.
2005
2006Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2007
2008 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2009
2010Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2011
2012 * mips.igen (ERET): Implement.
2013
2014 * interp.c (decode_coproc): Return sign-extended EPC.
2015
2016 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2017
2018 * interp.c (signal_exception): Do not ignore Trap.
2019 (signal_exception): On TRAP, restart at exception address.
2020 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2021 (signal_exception): Update.
2022 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2023 so that TRAP instructions are caught.
2024
2025Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2028 contains HI/LO access history.
2029 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2030 (HIACCESS, LOACCESS): Delete, replace with
2031 (HIHISTORY, LOHISTORY): New macros.
2032 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2033
c906108c
SS		 2034 * gencode.c (build_instruction): Do not generate checks for
2035 correct HI/LO register usage.
2036
2037 * interp.c (old_engine_run): Delete checks for correct HI/LO
2038 register usage.
2039
2040 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2041 check_mf_cycles): New functions.
2042 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2043 do_divu, domultx, do_mult, do_multu): Use.
2044
2045 * tx.igen ("madd", "maddu"): Use.
72f4393d 2046
c906108c
SS		 2047Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2048
2049 * mips.igen (DSRAV): Use function do_dsrav.
2050 (SRAV): Use new function do_srav.
2051
2052 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2053 (B): Sign extend 11 bit immediate.
2054 (EXT-B*): Shift 16 bit immediate left by 1.
2055 (ADDIU*): Don't sign extend immediate value.
2056
2057Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2058
2059 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2060
2061 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2062 functions.
2063
2064 * mips.igen (delayslot32, nullify_next_insn): New functions.
2065 (m16.igen): Always include.
2066 (do_*): Add more tracing.
2067
2068 * m16.igen (delayslot16): Add NIA argument, could be called by a
2069 32 bit MIPS16 instruction.
72f4393d 2070
c906108c
SS		 2071 * interp.c (ifetch16): Move function from here.
2072 * sim-main.c (ifetch16): To here.
72f4393d 2073
c906108c
SS		 2074 * sim-main.c (ifetch16, ifetch32): Update to match current
2075 implementations of LH, LW.
2076 (signal_exception): Don't print out incorrect hex value of illegal
2077 instruction.
2078
2079Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2080
2081 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2082 instruction.
2083
2084 * m16.igen: Implement MIPS16 instructions.
72f4393d 2085
c906108c
SS		 2086 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2087 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2088 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2089 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2090 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2091 bodies of corresponding code from 32 bit insn to these. Also used
2092 by MIPS16 versions of functions.
72f4393d 2093
c906108c
SS		 2094 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2095 (IMEM16): Drop NR argument from macro.
2096
2097Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2098
2099 * Makefile.in (SIM_OBJS): Add sim-main.o.
2100
2101 * sim-main.h (address_translation, load_memory, store_memory,
2102 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2103 as INLINE_SIM_MAIN.
2104 (pr_addr, pr_uword64): Declare.
2105 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2106
c906108c
SS		 2107 * interp.c (address_translation, load_memory, store_memory,
2108 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2109 from here.
2110 * sim-main.c: To here. Fix compilation problems.
72f4393d 2111
c906108c
SS		 2112 * configure.in: Enable inlining.
2113 * configure: Re-config.
2114
2115Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * configure: Regenerated to track ../common/aclocal.m4 changes.
2118
2119Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2120
2121 * mips.igen: Include tx.igen.
2122 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2123 * tx.igen: New file, contains MADD and MADDU.
2124
2125 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2126 the hardwired constant `7'.
2127 (store_memory): Ditto.
2128 (LOADDRMASK): Move definition to sim-main.h.
2129
2130 mips.igen (MTC0): Enable for r3900.
2131 (ADDU): Add trace.
2132
2133 mips.igen (do_load_byte): Delete.
2134 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2135 do_store_right): New functions.
2136 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2137
2138 configure.in: Let the tx39 use igen again.
2139 configure: Update.
72f4393d 2140
c906108c
SS		 2141Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2142
2143 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2144 not an address sized quantity. Return zero for cache sizes.
2145
2146Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * mips.igen (r3900): r3900 does not support 64 bit integer
2149 operations.
2150
2151Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2152
2153 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2154 than igen one.
2155 * configure : Rebuild.
72f4393d 2156
c906108c
SS		 2157Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2158
2159 * configure: Regenerated to track ../common/aclocal.m4 changes.
2160
2161Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2162
2163 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2164
2165Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2166
2167 * configure: Regenerated to track ../common/aclocal.m4 changes.
2168 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2169
2170Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2171
2172 * configure: Regenerated to track ../common/aclocal.m4 changes.
2173
2174Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2175
2176 * interp.c (Max, Min): Comment out functions. Not yet used.
2177
2178Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2179
2180 * configure: Regenerated to track ../common/aclocal.m4 changes.
2181
2182Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2183
2184 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2185 configurable settings for stand-alone simulator.
72f4393d 2186
c906108c 2187 * configure.in: Added X11 search, just in case.
72f4393d 2188
c906108c
SS		 2189 * configure: Regenerated.
2190
2191Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2192
2193 * interp.c (sim_write, sim_read, load_memory, store_memory):
2194 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2195
2196Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2197
2198 * sim-main.h (GETFCC): Return an unsigned value.
2199
2200Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2201
2202 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2203 (DADD): Result destination is RD not RT.
2204
2205Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2206
2207 * sim-main.h (HIACCESS, LOACCESS): Always define.
2208
2209 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2210
2211 * interp.c (sim_info): Delete.
2212
2213Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2214
2215 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2216 (mips_option_handler): New argument `cpu'.
2217 (sim_open): Update call to sim_add_option_table.
2218
2219Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2220
2221 * mips.igen (CxC1): Add tracing.
2222
2223Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2224
2225 * sim-main.h (Max, Min): Declare.
2226
2227 * interp.c (Max, Min): New functions.
2228
2229 * mips.igen (BC1): Add tracing.
72f4393d 2230
c906108c 2231Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2232
c906108c 2233 * interp.c Added memory map for stack in vr4100
72f4393d 2234
c906108c
SS		 2235Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2236
2237 * interp.c (load_memory): Add missing "break"'s.
2238
2239Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2240
2241 * interp.c (sim_store_register, sim_fetch_register): Pass in
2242 length parameter. Return -1.
2243
2244Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2245
2246 * interp.c: Added hardware init hook, fixed warnings.
2247
2248Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2249
2250 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2251
2252Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2253
2254 * interp.c (ifetch16): New function.
2255
2256 * sim-main.h (IMEM32): Rename IMEM.
2257 (IMEM16_IMMED): Define.
2258 (IMEM16): Define.
2259 (DELAY_SLOT): Update.
72f4393d 2260
c906108c 2261 * m16run.c (sim_engine_run): New file.
72f4393d 2262
c906108c
SS		 2263 * m16.igen: All instructions except LB.
2264 (LB): Call do_load_byte.
2265 * mips.igen (do_load_byte): New function.
2266 (LB): Call do_load_byte.
2267
2268 * mips.igen: Move spec for insn bit size and high bit from here.
2269 * Makefile.in (tmp-igen, tmp-m16): To here.
2270
2271 * m16.dc: New file, decode mips16 instructions.
2272
2273 * Makefile.in (SIM_NO_ALL): Define.
2274 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2275
2276Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2279 point unit to 32 bit registers.
2280 * configure: Re-generate.
2281
2282Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2283
2284 * configure.in (sim_use_gen): Make IGEN the default simulator
2285 generator for generic 32 and 64 bit mips targets.
2286 * configure: Re-generate.
2287
2288Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2289
2290 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2291 bitsize.
2292
2293 * interp.c (sim_fetch_register, sim_store_register): Read/write
2294 FGR from correct location.
2295 (sim_open): Set size of FGR's according to
2296 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2297
c906108c
SS		 2298 * sim-main.h (FGR): Store floating point registers in a separate
2299 array.
2300
2301Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2302
2303 * configure: Regenerated to track ../common/aclocal.m4 changes.
2304
2305Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2306
2307 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2308
2309 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2310
2311 * interp.c (pending_tick): New function. Deliver pending writes.
2312
2313 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2314 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2315 it can handle mixed sized quantites and single bits.
72f4393d 2316
c906108c
SS		 2317Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2318
2319 * interp.c (oengine.h): Do not include when building with IGEN.
2320 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2321 (sim_info): Ditto for PROCESSOR_64BIT.
2322 (sim_monitor): Replace ut_reg with unsigned_word.
2323 (*): Ditto for t_reg.
2324 (LOADDRMASK): Define.
2325 (sim_open): Remove defunct check that host FP is IEEE compliant,
2326 using software to emulate floating point.
2327 (value_fpr, ...): Always compile, was conditional on HASFPU.
2328
2329Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2330
2331 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2332 size.
2333
2334 * interp.c (SD, CPU): Define.
2335 (mips_option_handler): Set flags in each CPU.
2336 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2337 (sim_close): Do not clear STATE, deleted anyway.
2338 (sim_write, sim_read): Assume CPU zero's vm should be used for
2339 data transfers.
2340 (sim_create_inferior): Set the PC for all processors.
2341 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2342 argument.
2343 (mips16_entry): Pass correct nr of args to store_word, load_word.
2344 (ColdReset): Cold reset all cpu's.
2345 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2346 (sim_monitor, load_memory, store_memory, signal_exception): Use
2347 `CPU' instead of STATE_CPU.
2348
2349
2350 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2351 SD or CPU_.
72f4393d 2352
c906108c
SS		 2353 * sim-main.h (signal_exception): Add sim_cpu arg.
2354 (SignalException*): Pass both SD and CPU to signal_exception.
2355 * interp.c (signal_exception): Update.
72f4393d 2356
c906108c
SS		 2357 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2358 Ditto
2359 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2360 address_translation): Ditto
2361 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2362
c906108c
SS		 2363Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * configure: Regenerated to track ../common/aclocal.m4 changes.
2366
2367Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2368
2369 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2370
72f4393d 2371 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2372
2373 * sim-main.h (CPU_CIA): Delete.
2374 (SET_CIA, GET_CIA): Define
2375
2376Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2377
2378 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2379 regiser.
2380
2381 * configure.in (default_endian): Configure a big-endian simulator
2382 by default.
2383 * configure: Re-generate.
72f4393d 2384
c906108c
SS		 2385Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2386
2387 * configure: Regenerated to track ../common/aclocal.m4 changes.
2388
2389Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2390
2391 * interp.c (sim_monitor): Handle Densan monitor outbyte
2392 and inbyte functions.
2393
23941997-12-29 Felix Lee <flee@cygnus.com>
2395
2396 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2397
2398Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2399
2400 * Makefile.in (tmp-igen): Arrange for $zero to always be
2401 reset to zero after every instruction.
2402
2403Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2404
2405 * configure: Regenerated to track ../common/aclocal.m4 changes.
2406 * config.in: Ditto.
2407
2408Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2409
2410 * mips.igen (MSUB): Fix to work like MADD.
2411 * gencode.c (MSUB): Similarly.
2412
2413Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2414
2415 * configure: Regenerated to track ../common/aclocal.m4 changes.
2416
2417Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2418
2419 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2420
2421Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2422
2423 * sim-main.h (sim-fpu.h): Include.
2424
2425 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2426 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2427 using host independant sim_fpu module.
2428
2429Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2430
2431 * interp.c (signal_exception): Report internal errors with SIGABRT
2432 not SIGQUIT.
2433
2434 * sim-main.h (C0_CONFIG): New register.
2435 (signal.h): No longer include.
2436
2437 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2438
2439Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2440
2441 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2442
2443Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2444
2445 * mips.igen: Tag vr5000 instructions.
2446 (ANDI): Was missing mipsIV model, fix assembler syntax.
2447 (do_c_cond_fmt): New function.
2448 (C.cond.fmt): Handle mips I-III which do not support CC field
2449 separatly.
2450 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2451 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2452 in IV3.2 spec.
2453 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2454 vr5000 which saves LO in a GPR separatly.
72f4393d 2455
c906108c
SS		 2456 * configure.in (enable-sim-igen): For vr5000, select vr5000
2457 specific instructions.
2458 * configure: Re-generate.
72f4393d 2459
c906108c
SS		 2460Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2461
2462 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2463
2464 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2465 fmt_uninterpreted_64 bit cases to switch. Convert to
2466 fmt_formatted,
2467
2468 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2469
2470 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2471 as specified in IV3.2 spec.
2472 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2473
2474Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2475
2476 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2477 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2478 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2479 PENDING_FILL versions of instructions. Simplify.
2480 (X): New function.
2481 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2482 instructions.
2483 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2484 a signed value.
2485 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2486
c906108c
SS		 2487 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2488 global.
2489 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2490
2491Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2492
2493 * gencode.c (build_mips16_operands): Replace IPC with cia.
2494
2495 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2496 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2497 IPC to `cia'.
2498 (UndefinedResult): Replace function with macro/function
2499 combination.
2500 (sim_engine_run): Don't save PC in IPC.
2501
2502 * sim-main.h (IPC): Delete.
2503
2504
2505 * interp.c (signal_exception, store_word, load_word,
2506 address_translation, load_memory, store_memory, cache_op,
2507 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2508 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2509 current instruction address - cia - argument.
2510 (sim_read, sim_write): Call address_translation directly.
2511 (sim_engine_run): Rename variable vaddr to cia.
2512 (signal_exception): Pass cia to sim_monitor
72f4393d 2513
c906108c
SS		 2514 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2515 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2516 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2517
2518 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2519 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2520 SIM_ASSERT.
72f4393d 2521
c906108c
SS		 2522 * interp.c (signal_exception): Pass restart address to
2523 sim_engine_restart.
2524
2525 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2526 idecode.o): Add dependency.
2527
2528 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2529 Delete definitions
2530 (DELAY_SLOT): Update NIA not PC with branch address.
2531 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2532
2533 * mips.igen: Use CIA not PC in branch calculations.
2534 (illegal): Call SignalException.
2535 (BEQ, ADDIU): Fix assembler.
2536
2537Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2538
2539 * m16.igen (JALX): Was missing.
2540
2541 * configure.in (enable-sim-igen): New configuration option.
2542 * configure: Re-generate.
72f4393d 2543
c906108c
SS		 2544 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2545
2546 * interp.c (load_memory, store_memory): Delete parameter RAW.
2547 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2548 bypassing {load,store}_memory.
2549
2550 * sim-main.h (ByteSwapMem): Delete definition.
2551
2552 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2553
2554 * interp.c (sim_do_command, sim_commands): Delete mips specific
2555 commands. Handled by module sim-options.
72f4393d 2556
c906108c
SS		 2557 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2558 (WITH_MODULO_MEMORY): Define.
2559
2560 * interp.c (sim_info): Delete code printing memory size.
2561
2562 * interp.c (mips_size): Nee sim_size, delete function.
2563 (power2): Delete.
2564 (monitor, monitor_base, monitor_size): Delete global variables.
2565 (sim_open, sim_close): Delete code creating monitor and other
2566 memory regions. Use sim-memopts module, via sim_do_commandf, to
2567 manage memory regions.
2568 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2569
c906108c
SS		 2570 * interp.c (address_translation): Delete all memory map code
2571 except line forcing 32 bit addresses.
2572
2573Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2574
2575 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2576 trace options.
2577
2578 * interp.c (logfh, logfile): Delete globals.
2579 (sim_open, sim_close): Delete code opening & closing log file.
2580 (mips_option_handler): Delete -l and -n options.
2581 (OPTION mips_options): Ditto.
2582
2583 * interp.c (OPTION mips_options): Rename option trace to dinero.
2584 (mips_option_handler): Update.
2585
2586Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2587
2588 * interp.c (fetch_str): New function.
2589 (sim_monitor): Rewrite using sim_read & sim_write.
2590 (sim_open): Check magic number.
2591 (sim_open): Write monitor vectors into memory using sim_write.
2592 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2593 (sim_read, sim_write): Simplify - transfer data one byte at a
2594 time.
2595 (load_memory, store_memory): Clarify meaning of parameter RAW.
2596
2597 * sim-main.h (isHOST): Defete definition.
2598 (isTARGET): Mark as depreciated.
2599 (address_translation): Delete parameter HOST.
2600
2601 * interp.c (address_translation): Delete parameter HOST.
2602
2603Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2604
72f4393d 2605 * mips.igen:
c906108c
SS		 2606
2607 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2608 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2609
2610Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2611
2612 * mips.igen: Add model filter field to records.
2613
2614Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2615
2616 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2617
c906108c
SS		 2618 interp.c (sim_engine_run): Do not compile function sim_engine_run
2619 when WITH_IGEN == 1.
2620
2621 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2622 target architecture.
2623
2624 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2625 igen. Replace with configuration variables sim_igen_flags /
2626 sim_m16_flags.
2627
2628 * m16.igen: New file. Copy mips16 insns here.
2629 * mips.igen: From here.
2630
2631Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2634 to top.
2635 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2636
2637Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2638
2639 * gencode.c (build_instruction): Follow sim_write's lead in using
2640 BigEndianMem instead of !ByteSwapMem.
2641
2642Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2643
2644 * configure.in (sim_gen): Dependent on target, select type of
2645 generator. Always select old style generator.
2646
2647 configure: Re-generate.
2648
2649 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2650 targets.
2651 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2652 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2653 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2654 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2655 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2656
c906108c
SS		 2657Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2660
2661 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2662 CURRENT_FLOATING_POINT instead.
2663
2664 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2665 (address_translation): Raise exception InstructionFetch when
2666 translation fails and isINSTRUCTION.
72f4393d 2667
c906108c
SS		 2668 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2669 sim_engine_run): Change type of of vaddr and paddr to
2670 address_word.
2671 (address_translation, prefetch, load_memory, store_memory,
2672 cache_op): Change type of vAddr and pAddr to address_word.
2673
2674 * gencode.c (build_instruction): Change type of vaddr and paddr to
2675 address_word.
2676
2677Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2678
2679 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2680 macro to obtain result of ALU op.
2681
2682Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2683
2684 * interp.c (sim_info): Call profile_print.
2685
2686Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2687
2688 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2689
2690 * sim-main.h (WITH_PROFILE): Do not define, defined in
2691 common/sim-config.h. Use sim-profile module.
2692 (simPROFILE): Delete defintion.
2693
2694 * interp.c (PROFILE): Delete definition.
2695 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2696 (sim_close): Delete code writing profile histogram.
2697 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2698 Delete.
2699 (sim_engine_run): Delete code profiling the PC.
2700
2701Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2702
2703 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2704
2705 * interp.c (sim_monitor): Make register pointers of type
2706 unsigned_word*.
2707
2708 * sim-main.h: Make registers of type unsigned_word not
2709 signed_word.
2710
2711Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712
2713 * interp.c (sync_operation): Rename from SyncOperation, make
2714 global, add SD argument.
2715 (prefetch): Rename from Prefetch, make global, add SD argument.
2716 (decode_coproc): Make global.
2717
2718 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2719
2720 * gencode.c (build_instruction): Generate DecodeCoproc not
2721 decode_coproc calls.
2722
2723 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2724 (SizeFGR): Move to sim-main.h
2725 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2726 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2727 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2728 sim-main.h.
2729 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2730 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2731 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2732 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2733 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2734 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2735
c906108c
SS		 2736 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2737 exception.
2738 (sim-alu.h): Include.
2739 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2740 (sim_cia): Typedef to instruction_address.
72f4393d 2741
c906108c
SS		 2742Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2743
2744 * Makefile.in (interp.o): Rename generated file engine.c to
2745 oengine.c.
72f4393d 2746
c906108c 2747 * interp.c: Update.
72f4393d 2748
c906108c
SS		 2749Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2750
2751 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2752
c906108c
SS		 2753Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2754
2755 * gencode.c (build_instruction): For "FPSQRT", output correct
2756 number of arguments to Recip.
72f4393d 2757
c906108c
SS		 2758Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * Makefile.in (interp.o): Depends on sim-main.h
2761
2762 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2763
2764 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2765 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2766 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2767 STATE, DSSTATE): Define
2768 (GPR, FGRIDX, ..): Define.
2769
2770 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2771 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2772 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2773
c906108c 2774 * interp.c: Update names to match defines from sim-main.h
72f4393d 2775
c906108c
SS		 2776Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2777
2778 * interp.c (sim_monitor): Add SD argument.
2779 (sim_warning): Delete. Replace calls with calls to
2780 sim_io_eprintf.
2781 (sim_error): Delete. Replace calls with sim_io_error.
2782 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2783 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2784 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2785 argument.
2786 (mips_size): Rename from sim_size. Add SD argument.
2787
2788 * interp.c (simulator): Delete global variable.
2789 (callback): Delete global variable.
2790 (mips_option_handler, sim_open, sim_write, sim_read,
2791 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2792 sim_size,sim_monitor): Use sim_io_* not callback->*.
2793 (sim_open): ZALLOC simulator struct.
2794 (PROFILE): Do not define.
2795
2796Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2797
2798 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2799 support.h with corresponding code.
2800
2801 * sim-main.h (word64, uword64), support.h: Move definition to
2802 sim-main.h.
2803 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2804
2805 * support.h: Delete
2806 * Makefile.in: Update dependencies
2807 * interp.c: Do not include.
72f4393d 2808
c906108c
SS		 2809Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2810
2811 * interp.c (address_translation, load_memory, store_memory,
2812 cache_op): Rename to from AddressTranslation et.al., make global,
2813 add SD argument
72f4393d 2814
c906108c
SS		 2815 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2816 CacheOp): Define.
72f4393d 2817
c906108c
SS		 2818 * interp.c (SignalException): Rename to signal_exception, make
2819 global.
2820
2821 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2822
c906108c
SS		 2823 * sim-main.h (SignalException, SignalExceptionInterrupt,
2824 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2825 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2826 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2827 Define.
72f4393d 2828
c906108c 2829 * interp.c, support.h: Use.
72f4393d 2830
c906108c
SS		 2831Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2832
2833 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2834 to value_fpr / store_fpr. Add SD argument.
2835 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2836 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2837
2838 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2839
c906108c
SS		 2840Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2841
2842 * interp.c (sim_engine_run): Check consistency between configure
2843 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2844 and HASFPU.
2845
2846 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2847 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2848 (mips_endian): Configure WITH_TARGET_ENDIAN.
2849 * configure: Update.
2850
2851Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852
2853 * configure: Regenerated to track ../common/aclocal.m4 changes.
2854
2855Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2856
2857 * configure: Regenerated.
2858
2859Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2860
2861 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2862
2863Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2864
2865 * gencode.c (print_igen_insn_models): Assume certain architectures
2866 include all mips* instructions.
2867 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2868 instruction.
2869
2870 * Makefile.in (tmp.igen): Add target. Generate igen input from
2871 gencode file.
2872
2873 * gencode.c (FEATURE_IGEN): Define.
2874 (main): Add --igen option. Generate output in igen format.
2875 (process_instructions): Format output according to igen option.
2876 (print_igen_insn_format): New function.
2877 (print_igen_insn_models): New function.
2878 (process_instructions): Only issue warnings and ignore
2879 instructions when no FEATURE_IGEN.
2880
2881Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2882
2883 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2884 MIPS targets.
2885
2886Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2887
2888 * configure: Regenerated to track ../common/aclocal.m4 changes.
2889
2890Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2891
2892 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2893 SIM_RESERVED_BITS): Delete, moved to common.
2894 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2895
c906108c
SS		 2896Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2897
2898 * configure.in: Configure non-strict memory alignment.
2899 * configure: Regenerated to track ../common/aclocal.m4 changes.
2900
2901Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2902
2903 * configure: Regenerated to track ../common/aclocal.m4 changes.
2904
2905Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2906
2907 * gencode.c (SDBBP,DERET): Added (3900) insns.
2908 (RFE): Turn on for 3900.
2909 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2910 (dsstate): Made global.
2911 (SUBTARGET_R3900): Added.
2912 (CANCELDELAYSLOT): New.
2913 (SignalException): Ignore SystemCall rather than ignore and
2914 terminate. Add DebugBreakPoint handling.
2915 (decode_coproc): New insns RFE, DERET; and new registers Debug
2916 and DEPC protected by SUBTARGET_R3900.
2917 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2918 bits explicitly.
2919 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2920 * configure: Update.
c906108c
SS		 2921
2922Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2923
2924 * gencode.c: Add r3900 (tx39).
72f4393d 2925
c906108c
SS		 2926
2927Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2928
2929 * gencode.c (build_instruction): Don't need to subtract 4 for
2930 JALR, just 2.
2931
2932Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2933
2934 * interp.c: Correct some HASFPU problems.
2935
2936Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2937
2938 * configure: Regenerated to track ../common/aclocal.m4 changes.
2939
2940Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2941
2942 * interp.c (mips_options): Fix samples option short form, should
2943 be `x'.
2944
2945Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
2946
2947 * interp.c (sim_info): Enable info code. Was just returning.
2948
2949Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2950
2951 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2952 MFC0.
2953
2954Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
2955
2956 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2957 constants.
2958 (build_instruction): Ditto for LL.
2959
2960Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
2961
2962 * configure: Regenerated to track ../common/aclocal.m4 changes.
2963
2964Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965
2966 * configure: Regenerated to track ../common/aclocal.m4 changes.
2967 * config.in: Ditto.
2968
2969Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
2970
2971 * interp.c (sim_open): Add call to sim_analyze_program, update
2972 call to sim_config.
2973
2974Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
2975
2976 * interp.c (sim_kill): Delete.
2977 (sim_create_inferior): Add ABFD argument. Set PC from same.
2978 (sim_load): Move code initializing trap handlers from here.
2979 (sim_open): To here.
2980 (sim_load): Delete, use sim-hload.c.
2981
2982 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2983
2984Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2985
2986 * configure: Regenerated to track ../common/aclocal.m4 changes.
2987 * config.in: Ditto.
2988
2989Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990
2991 * interp.c (sim_open): Add ABFD argument.
2992 (sim_load): Move call to sim_config from here.
2993 (sim_open): To here. Check return status.
2994
2995Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 2996
c906108c
SS		 2997 * gencode.c (build_instruction): Two arg MADD should
2998 not assign result to $0.
72f4393d 2999
c906108c
SS		 3000Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3001
3002 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3003 * sim/mips/configure.in: Regenerate.
3004
3005Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3006
3007 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3008 signed8, unsigned8 et.al. types.
3009
3010 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3011 hosts when selecting subreg.
3012
3013Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3014
3015 * interp.c (sim_engine_run): Reset the ZERO register to zero
3016 regardless of FEATURE_WARN_ZERO.
3017 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3018
3019Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3020
3021 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3022 (SignalException): For BreakPoints ignore any mode bits and just
3023 save the PC.
3024 (SignalException): Always set the CAUSE register.
3025
3026Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3027
3028 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3029 exception has been taken.
3030
3031 * interp.c: Implement the ERET and mt/f sr instructions.
3032
3033Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3034
3035 * interp.c (SignalException): Don't bother restarting an
3036 interrupt.
3037
3038Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039
3040 * interp.c (SignalException): Really take an interrupt.
3041 (interrupt_event): Only deliver interrupts when enabled.
3042
3043Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * interp.c (sim_info): Only print info when verbose.
3046 (sim_info) Use sim_io_printf for output.
72f4393d 3047
c906108c
SS		 3048Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3049
3050 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3051 mips architectures.
3052
3053Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3054
3055 * interp.c (sim_do_command): Check for common commands if a
3056 simulator specific command fails.
3057
3058Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3059
3060 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3061 and simBE when DEBUG is defined.
3062
3063Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3064
3065 * interp.c (interrupt_event): New function. Pass exception event
3066 onto exception handler.
3067
3068 * configure.in: Check for stdlib.h.
3069 * configure: Regenerate.
3070
3071 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3072 variable declaration.
3073 (build_instruction): Initialize memval1.
3074 (build_instruction): Add UNUSED attribute to byte, bigend,
3075 reverse.
3076 (build_operands): Ditto.
3077
3078 * interp.c: Fix GCC warnings.
3079 (sim_get_quit_code): Delete.
3080
3081 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3082 * Makefile.in: Ditto.
3083 * configure: Re-generate.
72f4393d 3084
c906108c
SS		 3085 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3086
3087Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3088
3089 * interp.c (mips_option_handler): New function parse argumes using
3090 sim-options.
3091 (myname): Replace with STATE_MY_NAME.
3092 (sim_open): Delete check for host endianness - performed by
3093 sim_config.
3094 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3095 (sim_open): Move much of the initialization from here.
3096 (sim_load): To here. After the image has been loaded and
3097 endianness set.
3098 (sim_open): Move ColdReset from here.
3099 (sim_create_inferior): To here.
3100 (sim_open): Make FP check less dependant on host endianness.
3101
3102 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3103 run.
3104 * interp.c (sim_set_callbacks): Delete.
3105
3106 * interp.c (membank, membank_base, membank_size): Replace with
3107 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3108 (sim_open): Remove call to callback->init. gdb/run do this.
3109
3110 * interp.c: Update
3111
3112 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3113
3114 * interp.c (big_endian_p): Delete, replaced by
3115 current_target_byte_order.
3116
3117Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3118
3119 * interp.c (host_read_long, host_read_word, host_swap_word,
3120 host_swap_long): Delete. Using common sim-endian.
3121 (sim_fetch_register, sim_store_register): Use H2T.
3122 (pipeline_ticks): Delete. Handled by sim-events.
3123 (sim_info): Update.
3124 (sim_engine_run): Update.
3125
3126Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3127
3128 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3129 reason from here.
3130 (SignalException): To here. Signal using sim_engine_halt.
3131 (sim_stop_reason): Delete, moved to common.
72f4393d 3132
c906108c
SS		 3133Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3134
3135 * interp.c (sim_open): Add callback argument.
3136 (sim_set_callbacks): Delete SIM_DESC argument.
3137 (sim_size): Ditto.
3138
3139Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3140
3141 * Makefile.in (SIM_OBJS): Add common modules.
3142
3143 * interp.c (sim_set_callbacks): Also set SD callback.
3144 (set_endianness, xfer_*, swap_*): Delete.
3145 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3146 Change to functions using sim-endian macros.
3147 (control_c, sim_stop): Delete, use common version.
3148 (simulate): Convert into.
3149 (sim_engine_run): This function.
3150 (sim_resume): Delete.
72f4393d 3151
c906108c
SS		 3152 * interp.c (simulation): New variable - the simulator object.
3153 (sim_kind): Delete global - merged into simulation.
3154 (sim_load): Cleanup. Move PC assignment from here.
3155 (sim_create_inferior): To here.
3156
3157 * sim-main.h: New file.
3158 * interp.c (sim-main.h): Include.
72f4393d 3159
c906108c
SS		 3160Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3161
3162 * configure: Regenerated to track ../common/aclocal.m4 changes.
3163
3164Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3165
3166 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3167
3168Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3169
72f4393d
L		 3170 * gencode.c (build_instruction): DIV instructions: check
3171 for division by zero and integer overflow before using
c906108c
SS		 3172 host's division operation.
3173
3174Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3175
3176 * Makefile.in (SIM_OBJS): Add sim-load.o.
3177 * interp.c: #include bfd.h.
3178 (target_byte_order): Delete.
3179 (sim_kind, myname, big_endian_p): New static locals.
3180 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3181 after argument parsing. Recognize -E arg, set endianness accordingly.
3182 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3183 load file into simulator. Set PC from bfd.
3184 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3185 (set_endianness): Use big_endian_p instead of target_byte_order.
3186
3187Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3188
3189 * interp.c (sim_size): Delete prototype - conflicts with
3190 definition in remote-sim.h. Correct definition.
3191
3192Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3193
3194 * configure: Regenerated to track ../common/aclocal.m4 changes.
3195 * config.in: Ditto.
3196
3197Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3198
3199 * interp.c (sim_open): New arg `kind'.
3200
3201 * configure: Regenerated to track ../common/aclocal.m4 changes.
3202
3203Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3204
3205 * configure: Regenerated to track ../common/aclocal.m4 changes.
3206
3207Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3208
3209 * interp.c (sim_open): Set optind to 0 before calling getopt.
3210
3211Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3212
3213 * configure: Regenerated to track ../common/aclocal.m4 changes.
3214
3215Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3216
3217 * interp.c : Replace uses of pr_addr with pr_uword64
3218 where the bit length is always 64 independent of SIM_ADDR.
3219 (pr_uword64) : added.
3220
3221Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3222
3223 * configure: Re-generate.
3224
3225Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3226
3227 * configure: Regenerate to track ../common/aclocal.m4 changes.
3228
3229Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3230
3231 * interp.c (sim_open): New SIM_DESC result. Argument is now
3232 in argv form.
3233 (other sim_*): New SIM_DESC argument.
3234
3235Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3236
3237 * interp.c: Fix printing of addresses for non-64-bit targets.
3238 (pr_addr): Add function to print address based on size.
3239
3240Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3241
3242 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3243
3244Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3245
3246 * gencode.c (build_mips16_operands): Correct computation of base
3247 address for extended PC relative instruction.
3248
3249Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3250
3251 * interp.c (mips16_entry): Add support for floating point cases.
3252 (SignalException): Pass floating point cases to mips16_entry.
3253 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3254 registers.
3255 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3256 or fmt_word.
3257 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3258 and then set the state to fmt_uninterpreted.
3259 (COP_SW): Temporarily set the state to fmt_word while calling
3260 ValueFPR.
3261
3262Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3263
3264 * gencode.c (build_instruction): The high order may be set in the
3265 comparison flags at any ISA level, not just ISA 4.
3266
3267Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3268
3269 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3270 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3271 * configure.in: sinclude ../common/aclocal.m4.
3272 * configure: Regenerated.
3273
3274Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3275
3276 * configure: Rebuild after change to aclocal.m4.
3277
3278Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3279
3280 * configure configure.in Makefile.in: Update to new configure
3281 scheme which is more compatible with WinGDB builds.
3282 * configure.in: Improve comment on how to run autoconf.
3283 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3284 * Makefile.in: Use autoconf substitution to install common
3285 makefile fragment.
3286
3287Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3288
3289 * gencode.c (build_instruction): Use BigEndianCPU instead of
3290 ByteSwapMem.
3291
3292Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3293
3294 * interp.c (sim_monitor): Make output to stdout visible in
3295 wingdb's I/O log window.
3296
3297Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3298
3299 * support.h: Undo previous change to SIGTRAP
3300 and SIGQUIT values.
3301
3302Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3303
3304 * interp.c (store_word, load_word): New static functions.
3305 (mips16_entry): New static function.
3306 (SignalException): Look for mips16 entry and exit instructions.
3307 (simulate): Use the correct index when setting fpr_state after
3308 doing a pending move.
3309
3310Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3311
3312 * interp.c: Fix byte-swapping code throughout to work on
3313 both little- and big-endian hosts.
3314
3315Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3316
3317 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3318 with gdb/config/i386/xm-windows.h.
3319
3320Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3321
3322 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3323 that messes up arithmetic shifts.
3324
3325Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3326
3327 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3328 SIGTRAP and SIGQUIT for _WIN32.
3329
3330Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3331
3332 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3333 force a 64 bit multiplication.
3334 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3335 destination register is 0, since that is the default mips16 nop
3336 instruction.
3337
3338Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3339
3340 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3341 (build_endian_shift): Don't check proc64.
3342 (build_instruction): Always set memval to uword64. Cast op2 to
3343 uword64 when shifting it left in memory instructions. Always use
3344 the same code for stores--don't special case proc64.
3345
3346 * gencode.c (build_mips16_operands): Fix base PC value for PC
3347 relative operands.
3348 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3349 jal instruction.
3350 * interp.c (simJALDELAYSLOT): Define.
3351 (JALDELAYSLOT): Define.
3352 (INDELAYSLOT, INJALDELAYSLOT): Define.
3353 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3354
3355Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3356
3357 * interp.c (sim_open): add flush_cache as a PMON routine
3358 (sim_monitor): handle flush_cache by ignoring it
3359
3360Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3361
3362 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3363 BigEndianMem.
3364 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3365 (BigEndianMem): Rename to ByteSwapMem and change sense.
3366 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3367 BigEndianMem references to !ByteSwapMem.
3368 (set_endianness): New function, with prototype.
3369 (sim_open): Call set_endianness.
3370 (sim_info): Use simBE instead of BigEndianMem.
3371 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3372 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3373 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3374 ifdefs, keeping the prototype declaration.
3375 (swap_word): Rewrite correctly.
3376 (ColdReset): Delete references to CONFIG. Delete endianness related
3377 code; moved to set_endianness.
72f4393d 3378
c906108c
SS		 3379Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3380
3381 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3382 * interp.c (CHECKHILO): Define away.
3383 (simSIGINT): New macro.
3384 (membank_size): Increase from 1MB to 2MB.
3385 (control_c): New function.
3386 (sim_resume): Rename parameter signal to signal_number. Add local
3387 variable prev. Call signal before and after simulate.
3388 (sim_stop_reason): Add simSIGINT support.
3389 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3390 functions always.
3391 (sim_warning): Delete call to SignalException. Do call printf_filtered
3392 if logfh is NULL.
3393 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3394 a call to sim_warning.
3395
3396Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3397
3398 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3399 16 bit instructions.
3400
3401Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3402
3403 Add support for mips16 (16 bit MIPS implementation):
3404 * gencode.c (inst_type): Add mips16 instruction encoding types.
3405 (GETDATASIZEINSN): Define.
3406 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3407 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3408 mtlo.
3409 (MIPS16_DECODE): New table, for mips16 instructions.
3410 (bitmap_val): New static function.
3411 (struct mips16_op): Define.
3412 (mips16_op_table): New table, for mips16 operands.
3413 (build_mips16_operands): New static function.
3414 (process_instructions): If PC is odd, decode a mips16
3415 instruction. Break out instruction handling into new
3416 build_instruction function.
3417 (build_instruction): New static function, broken out of
3418 process_instructions. Check modifiers rather than flags for SHIFT
3419 bit count and m[ft]{hi,lo} direction.
3420 (usage): Pass program name to fprintf.
3421 (main): Remove unused variable this_option_optind. Change
3422 ``*loptarg++'' to ``loptarg++''.
3423 (my_strtoul): Parenthesize && within ||.
3424 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3425 (simulate): If PC is odd, fetch a 16 bit instruction, and
3426 increment PC by 2 rather than 4.
3427 * configure.in: Add case for mips16*-*-*.
3428 * configure: Rebuild.
3429
3430Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3431
3432 * interp.c: Allow -t to enable tracing in standalone simulator.
3433 Fix garbage output in trace file and error messages.
3434
3435Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3436
3437 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3438 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3439 * configure.in: Simplify using macros in ../common/aclocal.m4.
3440 * configure: Regenerated.
3441 * tconfig.in: New file.
3442
3443Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3444
3445 * interp.c: Fix bugs in 64-bit port.
3446 Use ansi function declarations for msvc compiler.
3447 Initialize and test file pointer in trace code.
3448 Prevent duplicate definition of LAST_EMED_REGNUM.
3449
3450Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3451
3452 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3453
3454Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3455
3456 * interp.c (SignalException): Check for explicit terminating
3457 breakpoint value.
3458 * gencode.c: Pass instruction value through SignalException()
3459 calls for Trap, Breakpoint and Syscall.
3460
3461Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3462
3463 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3464 only used on those hosts that provide it.
3465 * configure.in: Add sqrt() to list of functions to be checked for.
3466 * config.in: Re-generated.
3467 * configure: Re-generated.
3468
3469Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3470
3471 * gencode.c (process_instructions): Call build_endian_shift when
3472 expanding STORE RIGHT, to fix swr.
3473 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3474 clear the high bits.
3475 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3476 Fix float to int conversions to produce signed values.
3477
3478Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3479
3480 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3481 (process_instructions): Correct handling of nor instruction.
3482 Correct shift count for 32 bit shift instructions. Correct sign
3483 extension for arithmetic shifts to not shift the number of bits in
3484 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3485 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3486 Fix madd.
3487 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3488 It's OK to have a mult follow a mult. What's not OK is to have a
3489 mult follow an mfhi.
3490 (Convert): Comment out incorrect rounding code.
3491
3492Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3493
3494 * interp.c (sim_monitor): Improved monitor printf
3495 simulation. Tidied up simulator warnings, and added "--log" option
3496 for directing warning message output.
3497 * gencode.c: Use sim_warning() rather than WARNING macro.
3498
3499Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3500
3501 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3502 getopt1.o, rather than on gencode.c. Link objects together.
3503 Don't link against -liberty.
3504 (gencode.o, getopt.o, getopt1.o): New targets.
3505 * gencode.c: Include <ctype.h> and "ansidecl.h".
3506 (AND): Undefine after including "ansidecl.h".
3507 (ULONG_MAX): Define if not defined.
3508 (OP_*): Don't define macros; now defined in opcode/mips.h.
3509 (main): Call my_strtoul rather than strtoul.
3510 (my_strtoul): New static function.
3511
3512Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3513
3514 * gencode.c (process_instructions): Generate word64 and uword64
3515 instead of `long long' and `unsigned long long' data types.
3516 * interp.c: #include sysdep.h to get signals, and define default
3517 for SIGBUS.
3518 * (Convert): Work around for Visual-C++ compiler bug with type
3519 conversion.
3520 * support.h: Make things compile under Visual-C++ by using
3521 __int64 instead of `long long'. Change many refs to long long
3522 into word64/uword64 typedefs.
3523
3524Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3525
72f4393d
L		 3526 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3527 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3528 (docdir): Removed.
3529 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3530 (AC_PROG_INSTALL): Added.
c906108c 3531 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3532 * configure: Rebuilt.
3533
c906108c
SS		 3534Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3535
3536 * configure.in: Define @SIMCONF@ depending on mips target.
3537 * configure: Rebuild.
3538 * Makefile.in (run): Add @SIMCONF@ to control simulator
3539 construction.
3540 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3541 * interp.c: Remove some debugging, provide more detailed error
3542 messages, update memory accesses to use LOADDRMASK.
72f4393d 3543
c906108c
SS		 3544Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3545
3546 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3547 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3548 stamp-h.
3549 * configure: Rebuild.
3550 * config.in: New file, generated by autoheader.
3551 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3552 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3553 HAVE_ANINT and HAVE_AINT, as appropriate.
3554 * Makefile.in (run): Use @LIBS@ rather than -lm.
3555 (interp.o): Depend upon config.h.
3556 (Makefile): Just rebuild Makefile.
3557 (clean): Remove stamp-h.
3558 (mostlyclean): Make the same as clean, not as distclean.
3559 (config.h, stamp-h): New targets.
3560
3561Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3562
3563 * interp.c (ColdReset): Fix boolean test. Make all simulator
3564 globals static.
3565
3566Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3567
3568 * interp.c (xfer_direct_word, xfer_direct_long,
3569 swap_direct_word, swap_direct_long, xfer_big_word,
3570 xfer_big_long, xfer_little_word, xfer_little_long,
3571 swap_word,swap_long): Added.
3572 * interp.c (ColdReset): Provide function indirection to
3573 host<->simulated_target transfer routines.
3574 * interp.c (sim_store_register, sim_fetch_register): Updated to
3575 make use of indirected transfer routines.
3576
3577Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3578
3579 * gencode.c (process_instructions): Ensure FP ABS instruction
3580 recognised.
3581 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3582 system call support.
3583
3584Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3585
3586 * interp.c (sim_do_command): Complain if callback structure not
3587 initialised.
3588
3589Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3590
3591 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3592 support for Sun hosts.
3593 * Makefile.in (gencode): Ensure the host compiler and libraries
3594 used for cross-hosted build.
3595
3596Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3597
3598 * interp.c, gencode.c: Some more (TODO) tidying.
3599
3600Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3601
3602 * gencode.c, interp.c: Replaced explicit long long references with
3603 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3604 * support.h (SET64LO, SET64HI): Macros added.
3605
3606Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3607
3608 * configure: Regenerate with autoconf 2.7.
3609
3610Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3611
3612 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3613 * support.h: Remove superfluous "1" from #if.
3614 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3615
3616Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3617
3618 * interp.c (StoreFPR): Control UndefinedResult() call on
3619 WARN_RESULT manifest.
3620
3621Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3622
3623 * gencode.c: Tidied instruction decoding, and added FP instruction
3624 support.
3625
3626 * interp.c: Added dineroIII, and BSD profiling support. Also
3627 run-time FP handling.
3628
3629Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3630
3631 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3632 gencode.c, interp.c, support.h: created.
A mirror of the official binutils-gdb repository