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mmc: Add a function to dump the mmc capabilities
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
b5b838f1
MV		 33#if CONFIG_IS_ENABLED(MMC_TINY)
34static struct mmc mmc_static;
35struct mmc *find_mmc_device(int dev_num)
36{
37 return &mmc_static;
38}
39
40void mmc_do_preinit(void)
41{
42 struct mmc *m = &mmc_static;
43#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
44 mmc_set_preinit(m, 1);
45#endif
46 if (m->preinit)
47 mmc_start_init(m);
48}
49
50struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
51{
52 return &mmc->block_dev;
53}
54#endif
55
e7881d85 56#if !CONFIG_IS_ENABLED(DM_MMC)
750121c3 57__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 58{
59 return -1;
60}
61
62int mmc_getwp(struct mmc *mmc)
63{
64 int wp;
65
66 wp = board_mmc_getwp(mmc);
67
d4e1da4e 68 if (wp < 0) {
93bfd616
PA		 69 if (mmc->cfg->ops->getwp)
70 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 71 else
72 wp = 0;
73 }
d23d8d7e
NK		 74
75 return wp;
76}
77
cee9ab7c
JH		 78__weak int board_mmc_getcd(struct mmc *mmc)
79{
11fdade2
SB		 80 return -1;
81}
8ca51e51 82#endif
11fdade2 83
c0c76eba
SG		 84#ifdef CONFIG_MMC_TRACE
85void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 86{
c0c76eba
SG		 87 printf("CMD_SEND:%d\n", cmd->cmdidx);
88 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
89}
8635ff9e 90
c0c76eba
SG		 91void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
92{
5db2fe3a
RR		 93 int i;
94 u8 *ptr;
95
7863ce58
BM		 96 if (ret) {
97 printf("\t\tRET\t\t\t %d\n", ret);
98 } else {
99 switch (cmd->resp_type) {
100 case MMC_RSP_NONE:
101 printf("\t\tMMC_RSP_NONE\n");
102 break;
103 case MMC_RSP_R1:
104 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
105 cmd->response[0]);
106 break;
107 case MMC_RSP_R1b:
108 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
109 cmd->response[0]);
110 break;
111 case MMC_RSP_R2:
112 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
113 cmd->response[0]);
114 printf("\t\t \t\t 0x%08X \n",
115 cmd->response[1]);
116 printf("\t\t \t\t 0x%08X \n",
117 cmd->response[2]);
118 printf("\t\t \t\t 0x%08X \n",
119 cmd->response[3]);
5db2fe3a 120 printf("\n");
7863ce58
BM		 121 printf("\t\t\t\t\tDUMPING DATA\n");
122 for (i = 0; i < 4; i++) {
123 int j;
124 printf("\t\t\t\t\t%03d - ", i*4);
125 ptr = (u8 *)&cmd->response[i];
126 ptr += 3;
127 for (j = 0; j < 4; j++)
128 printf("%02X ", *ptr--);
129 printf("\n");
130 }
131 break;
132 case MMC_RSP_R3:
133 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
134 cmd->response[0]);
135 break;
136 default:
137 printf("\t\tERROR MMC rsp not supported\n");
138 break;
53e8e40b 139 }
5db2fe3a 140 }
c0c76eba
SG		 141}
142
143void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
144{
145 int status;
146
147 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
148 printf("CURR STATE:%d\n", status);
149}
5db2fe3a 150#endif
c0c76eba 151
35f9e196
JJH		 152#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
153const char *mmc_mode_name(enum bus_mode mode)
154{
155 static const char *const names[] = {
156 [MMC_LEGACY] = "MMC legacy",
157 [SD_LEGACY] = "SD Legacy",
158 [MMC_HS] = "MMC High Speed (26MHz)",
159 [SD_HS] = "SD High Speed (50MHz)",
160 [UHS_SDR12] = "UHS SDR12 (25MHz)",
161 [UHS_SDR25] = "UHS SDR25 (50MHz)",
162 [UHS_SDR50] = "UHS SDR50 (100MHz)",
163 [UHS_SDR104] = "UHS SDR104 (208MHz)",
164 [UHS_DDR50] = "UHS DDR50 (50MHz)",
165 [MMC_HS_52] = "MMC High Speed (52MHz)",
166 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
167 [MMC_HS_200] = "HS200 (200MHz)",
168 };
169
170 if (mode >= MMC_MODES_END)
171 return "Unknown mode";
172 else
173 return names[mode];
174}
175#endif
176
177static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
178{
179 mmc->selected_mode = mode;
180 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
181 mmc->tran_speed / 1000000);
182 return 0;
183}
184
e7881d85 185#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 186int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
187{
188 int ret;
189
190 mmmc_trace_before_send(mmc, cmd);
191 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
192 mmmc_trace_after_send(mmc, cmd, ret);
193
8635ff9e 194 return ret;
272cc70b 195}
8ca51e51 196#endif
272cc70b 197
da61fa5f 198int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 199{
200 struct mmc_cmd cmd;
d617c426 201 int err, retries = 5;
5d4fc8d9
RR		 202
203 cmd.cmdidx = MMC_CMD_SEND_STATUS;
204 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 205 if (!mmc_host_is_spi(mmc))
206 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 207
1677eef4 208 while (1) {
5d4fc8d9 209 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 210 if (!err) {
211 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
212 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
213 MMC_STATE_PRG)
214 break;
215 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 216#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 217 printf("Status Error: 0x%08X\n",
218 cmd.response[0]);
56196826 219#endif
915ffa52 220 return -ECOMM;
d617c426
JK		 221 }
222 } else if (--retries < 0)
5d4fc8d9 223 return err;
5d4fc8d9 224
1677eef4
AG		 225 if (timeout-- <= 0)
226 break;
5d4fc8d9 227
1677eef4
AG		 228 udelay(1000);
229 }
5d4fc8d9 230
c0c76eba 231 mmc_trace_state(mmc, &cmd);
5b0c942f 232 if (timeout <= 0) {
56196826 233#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 234 printf("Timeout waiting card ready\n");
56196826 235#endif
915ffa52 236 return -ETIMEDOUT;
5d4fc8d9
RR		 237 }
238
239 return 0;
240}
241
da61fa5f 242int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 243{
244 struct mmc_cmd cmd;
245
786e8f81 246 if (mmc->ddr_mode)
d22e3d46
JC		 247 return 0;
248
272cc70b
AF		 249 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
250 cmd.resp_type = MMC_RSP_R1;
251 cmd.cmdarg = len;
272cc70b
AF		 252
253 return mmc_send_cmd(mmc, &cmd, NULL);
254}
255
ff8fef56 256static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 257 lbaint_t blkcnt)
272cc70b
AF		 258{
259 struct mmc_cmd cmd;
260 struct mmc_data data;
261
4a1a06bc
AS		 262 if (blkcnt > 1)
263 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
264 else
265 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 266
267 if (mmc->high_capacity)
4a1a06bc 268 cmd.cmdarg = start;
272cc70b 269 else
4a1a06bc 270 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 271
272 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 273
274 data.dest = dst;
4a1a06bc 275 data.blocks = blkcnt;
272cc70b
AF		 276 data.blocksize = mmc->read_bl_len;
277 data.flags = MMC_DATA_READ;
278
4a1a06bc
AS		 279 if (mmc_send_cmd(mmc, &cmd, &data))
280 return 0;
272cc70b 281
4a1a06bc
AS		 282 if (blkcnt > 1) {
283 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
284 cmd.cmdarg = 0;
285 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 286 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 287#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 288 printf("mmc fail to send stop cmd\n");
56196826 289#endif
4a1a06bc
AS		 290 return 0;
291 }
272cc70b
AF		 292 }
293
4a1a06bc 294 return blkcnt;
272cc70b
AF		 295}
296
c4d660d4 297#if CONFIG_IS_ENABLED(BLK)
7dba0b93 298ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 299#else
7dba0b93
SG		 300ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
301 void *dst)
33fb211d 302#endif
272cc70b 303{
c4d660d4 304#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 305 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
306#endif
bcce53d0 307 int dev_num = block_dev->devnum;
873cc1d7 308 int err;
4a1a06bc
AS		 309 lbaint_t cur, blocks_todo = blkcnt;
310
311 if (blkcnt == 0)
312 return 0;
272cc70b 313
4a1a06bc 314 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 315 if (!mmc)
316 return 0;
317
b5b838f1
MV		 318 if (CONFIG_IS_ENABLED(MMC_TINY))
319 err = mmc_switch_part(mmc, block_dev->hwpart);
320 else
321 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
322
873cc1d7
SW		 323 if (err < 0)
324 return 0;
325
c40fdca6 326 if ((start + blkcnt) > block_dev->lba) {
56196826 327#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 328 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
c40fdca6 329 start + blkcnt, block_dev->lba);
56196826 330#endif
d2bf29e3
LW		 331 return 0;
332 }
272cc70b 333
11692991
SG		 334 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
335 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 336 return 0;
11692991 337 }
272cc70b 338
4a1a06bc 339 do {
93bfd616
PA		 340 cur = (blocks_todo > mmc->cfg->b_max) ?
341 mmc->cfg->b_max : blocks_todo;
11692991
SG		 342 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
343 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 344 return 0;
11692991 345 }
4a1a06bc
AS		 346 blocks_todo -= cur;
347 start += cur;
348 dst += cur * mmc->read_bl_len;
349 } while (blocks_todo > 0);
272cc70b
AF		 350
351 return blkcnt;
352}
353
fdbb873e 354static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 355{
356 struct mmc_cmd cmd;
357 int err;
358
359 udelay(1000);
360
361 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
362 cmd.cmdarg = 0;
363 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 364
365 err = mmc_send_cmd(mmc, &cmd, NULL);
366
367 if (err)
368 return err;
369
370 udelay(2000);
371
372 return 0;
373}
374
fdbb873e 375static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF		 376{
377 int timeout = 1000;
378 int err;
379 struct mmc_cmd cmd;
380
1677eef4 381 while (1) {
272cc70b
AF		 382 cmd.cmdidx = MMC_CMD_APP_CMD;
383 cmd.resp_type = MMC_RSP_R1;
384 cmd.cmdarg = 0;
272cc70b
AF		 385
386 err = mmc_send_cmd(mmc, &cmd, NULL);
387
388 if (err)
389 return err;
390
391 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
392 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 393
394 /*
395 * Most cards do not answer if some reserved bits
396 * in the ocr are set. However, Some controller
397 * can set bit 7 (reserved for low voltages), but
398 * how to manage low voltages SD card is not yet
399 * specified.
400 */
d52ebf10 401 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 402 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 403
404 if (mmc->version == SD_VERSION_2)
405 cmd.cmdarg |= OCR_HCS;
406
407 err = mmc_send_cmd(mmc, &cmd, NULL);
408
409 if (err)
410 return err;
411
1677eef4
AG		 412 if (cmd.response[0] & OCR_BUSY)
413 break;
414
415 if (timeout-- <= 0)
915ffa52 416 return -EOPNOTSUPP;
272cc70b 417
1677eef4
AG		 418 udelay(1000);
419 }
272cc70b
AF		 420
421 if (mmc->version != SD_VERSION_2)
422 mmc->version = SD_VERSION_1_0;
423
d52ebf10
TC		 424 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
425 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
426 cmd.resp_type = MMC_RSP_R3;
427 cmd.cmdarg = 0;
d52ebf10
TC		 428
429 err = mmc_send_cmd(mmc, &cmd, NULL);
430
431 if (err)
432 return err;
433 }
434
998be3dd 435 mmc->ocr = cmd.response[0];
272cc70b
AF		 436
437 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
438 mmc->rca = 0;
439
440 return 0;
441}
442
5289b535 443static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 444{
5289b535 445 struct mmc_cmd cmd;
272cc70b
AF		 446 int err;
447
5289b535
AG		 448 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
449 cmd.resp_type = MMC_RSP_R3;
450 cmd.cmdarg = 0;
5a20397b
RH		 451 if (use_arg && !mmc_host_is_spi(mmc))
452 cmd.cmdarg = OCR_HCS |
93bfd616 453 (mmc->cfg->voltages &
a626c8d4
AG		 454 (mmc->ocr & OCR_VOLTAGE_MASK)) |
455 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 456
5289b535 457 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 458 if (err)
459 return err;
5289b535 460 mmc->ocr = cmd.response[0];
e9550449
CLC		 461 return 0;
462}
463
750121c3 464static int mmc_send_op_cond(struct mmc *mmc)
e9550449 465{
e9550449
CLC		 466 int err, i;
467
272cc70b
AF		 468 /* Some cards seem to need this */
469 mmc_go_idle(mmc);
470
31cacbab 471 /* Asking to the card its capabilities */
e9550449 472 for (i = 0; i < 2; i++) {
5289b535 473 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 474 if (err)
475 return err;
cd6881b5 476
e9550449 477 /* exit if not busy (flag seems to be inverted) */
a626c8d4 478 if (mmc->ocr & OCR_BUSY)
bd47c135 479 break;
e9550449 480 }
bd47c135
AG		 481 mmc->op_cond_pending = 1;
482 return 0;
e9550449 483}
cd6881b5 484
750121c3 485static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 486{
487 struct mmc_cmd cmd;
488 int timeout = 1000;
489 uint start;
490 int err;
cd6881b5 491
e9550449 492 mmc->op_cond_pending = 0;
cc17c01f 493 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 494 /* Some cards seem to need this */
495 mmc_go_idle(mmc);
496
cc17c01f 497 start = get_timer(0);
1677eef4 498 while (1) {
cc17c01f
AG		 499 err = mmc_send_op_cond_iter(mmc, 1);
500 if (err)
501 return err;
1677eef4
AG		 502 if (mmc->ocr & OCR_BUSY)
503 break;
cc17c01f 504 if (get_timer(start) > timeout)
915ffa52 505 return -EOPNOTSUPP;
cc17c01f 506 udelay(100);
1677eef4 507 }
cc17c01f 508 }
272cc70b 509
d52ebf10
TC		 510 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
511 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
512 cmd.resp_type = MMC_RSP_R3;
513 cmd.cmdarg = 0;
d52ebf10
TC		 514
515 err = mmc_send_cmd(mmc, &cmd, NULL);
516
517 if (err)
518 return err;
a626c8d4
AG		 519
520 mmc->ocr = cmd.response[0];
d52ebf10
TC		 521 }
522
272cc70b 523 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 524
525 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 526 mmc->rca = 1;
272cc70b
AF		 527
528 return 0;
529}
530
531
fdbb873e 532static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 533{
534 struct mmc_cmd cmd;
535 struct mmc_data data;
536 int err;
537
538 /* Get the Card Status Register */
539 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
540 cmd.resp_type = MMC_RSP_R1;
541 cmd.cmdarg = 0;
272cc70b 542
cdfd1ac6 543 data.dest = (char *)ext_csd;
272cc70b 544 data.blocks = 1;
8bfa195e 545 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 546 data.flags = MMC_DATA_READ;
547
548 err = mmc_send_cmd(mmc, &cmd, &data);
549
550 return err;
551}
552
c40704f4 553int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 554{
555 struct mmc_cmd cmd;
5d4fc8d9 556 int timeout = 1000;
a9003dc6 557 int retries = 3;
5d4fc8d9 558 int ret;
272cc70b
AF		 559
560 cmd.cmdidx = MMC_CMD_SWITCH;
561 cmd.resp_type = MMC_RSP_R1b;
562 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 563 (index << 16) |
564 (value << 8);
272cc70b 565
a9003dc6
MR		 566 while (retries > 0) {
567 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 568
a9003dc6
MR		 569 /* Waiting for the ready status */
570 if (!ret) {
571 ret = mmc_send_status(mmc, timeout);
572 return ret;
573 }
574
575 retries--;
576 }
5d4fc8d9
RR		 577
578 return ret;
579
272cc70b
AF		 580}
581
fdbb873e 582static int mmc_change_freq(struct mmc *mmc)
272cc70b 583{
8bfa195e 584 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF		 585 char cardtype;
586 int err;
587
fc5b32fb 588 mmc->card_caps = 0;
272cc70b 589
d52ebf10
TC		 590 if (mmc_host_is_spi(mmc))
591 return 0;
592
272cc70b
AF		 593 /* Only version 4 supports high-speed */
594 if (mmc->version < MMC_VERSION_4)
595 return 0;
596
fc5b32fb
AG		 597 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
598
272cc70b
AF		 599 err = mmc_send_ext_csd(mmc, ext_csd);
600
601 if (err)
602 return err;
603
0560db18 604 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF		 605
606 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
607
608 if (err)
a5e27b41 609 return err;
272cc70b
AF		 610
611 /* Now check to see that it worked */
612 err = mmc_send_ext_csd(mmc, ext_csd);
613
614 if (err)
615 return err;
616
617 /* No high-speed support */
0560db18 618 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF		 619 return 0;
620
621 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 622 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 623 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 624 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 625 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 626 } else {
272cc70b 627 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 628 }
272cc70b
AF		 629
630 return 0;
631}
632
f866a46d
SW		 633static int mmc_set_capacity(struct mmc *mmc, int part_num)
634{
635 switch (part_num) {
636 case 0:
637 mmc->capacity = mmc->capacity_user;
638 break;
639 case 1:
640 case 2:
641 mmc->capacity = mmc->capacity_boot;
642 break;
643 case 3:
644 mmc->capacity = mmc->capacity_rpmb;
645 break;
646 case 4:
647 case 5:
648 case 6:
649 case 7:
650 mmc->capacity = mmc->capacity_gp[part_num - 4];
651 break;
652 default:
653 return -1;
654 }
655
c40fdca6 656 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 657
658 return 0;
659}
660
7dba0b93 661int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 662{
f866a46d 663 int ret;
bc897b1d 664
f866a46d
SW		 665 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
666 (mmc->part_config & ~PART_ACCESS_MASK)
667 | (part_num & PART_ACCESS_MASK));
f866a46d 668
6dc93e70
PB		 669 /*
670 * Set the capacity if the switch succeeded or was intended
671 * to return to representing the raw device.
672 */
873cc1d7 673 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 674 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 675 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 676 }
6dc93e70
PB		 677
678 return ret;
bc897b1d
LW		 679}
680
ac9da0e0
DSC		 681int mmc_hwpart_config(struct mmc *mmc,
682 const struct mmc_hwpart_conf *conf,
683 enum mmc_hwpart_conf_mode mode)
684{
685 u8 part_attrs = 0;
686 u32 enh_size_mult;
687 u32 enh_start_addr;
688 u32 gp_size_mult[4];
689 u32 max_enh_size_mult;
690 u32 tot_enh_size_mult = 0;
8dda5b0e 691 u8 wr_rel_set;
ac9da0e0
DSC		 692 int i, pidx, err;
693 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
694
695 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
696 return -EINVAL;
697
698 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
699 printf("eMMC >= 4.4 required for enhanced user data area\n");
700 return -EMEDIUMTYPE;
701 }
702
703 if (!(mmc->part_support & PART_SUPPORT)) {
704 printf("Card does not support partitioning\n");
705 return -EMEDIUMTYPE;
706 }
707
708 if (!mmc->hc_wp_grp_size) {
709 printf("Card does not define HC WP group size\n");
710 return -EMEDIUMTYPE;
711 }
712
713 /* check partition alignment and total enhanced size */
714 if (conf->user.enh_size) {
715 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
716 conf->user.enh_start % mmc->hc_wp_grp_size) {
717 printf("User data enhanced area not HC WP group "
718 "size aligned\n");
719 return -EINVAL;
720 }
721 part_attrs |= EXT_CSD_ENH_USR;
722 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
723 if (mmc->high_capacity) {
724 enh_start_addr = conf->user.enh_start;
725 } else {
726 enh_start_addr = (conf->user.enh_start << 9);
727 }
728 } else {
729 enh_size_mult = 0;
730 enh_start_addr = 0;
731 }
732 tot_enh_size_mult += enh_size_mult;
733
734 for (pidx = 0; pidx < 4; pidx++) {
735 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
736 printf("GP%i partition not HC WP group size "
737 "aligned\n", pidx+1);
738 return -EINVAL;
739 }
740 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
741 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
742 part_attrs |= EXT_CSD_ENH_GP(pidx);
743 tot_enh_size_mult += gp_size_mult[pidx];
744 }
745 }
746
747 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
748 printf("Card does not support enhanced attribute\n");
749 return -EMEDIUMTYPE;
750 }
751
752 err = mmc_send_ext_csd(mmc, ext_csd);
753 if (err)
754 return err;
755
756 max_enh_size_mult =
757 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
758 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
759 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
760 if (tot_enh_size_mult > max_enh_size_mult) {
761 printf("Total enhanced size exceeds maximum (%u > %u)\n",
762 tot_enh_size_mult, max_enh_size_mult);
763 return -EMEDIUMTYPE;
764 }
765
8dda5b0e
DSC		 766 /* The default value of EXT_CSD_WR_REL_SET is device
767 * dependent, the values can only be changed if the
768 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
769 * changed only once and before partitioning is completed. */
770 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
771 if (conf->user.wr_rel_change) {
772 if (conf->user.wr_rel_set)
773 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
774 else
775 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
776 }
777 for (pidx = 0; pidx < 4; pidx++) {
778 if (conf->gp_part[pidx].wr_rel_change) {
779 if (conf->gp_part[pidx].wr_rel_set)
780 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
781 else
782 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
783 }
784 }
785
786 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
787 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
788 puts("Card does not support host controlled partition write "
789 "reliability settings\n");
790 return -EMEDIUMTYPE;
791 }
792
ac9da0e0
DSC		 793 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
794 EXT_CSD_PARTITION_SETTING_COMPLETED) {
795 printf("Card already partitioned\n");
796 return -EPERM;
797 }
798
799 if (mode == MMC_HWPART_CONF_CHECK)
800 return 0;
801
802 /* Partitioning requires high-capacity size definitions */
803 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
804 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
805 EXT_CSD_ERASE_GROUP_DEF, 1);
806
807 if (err)
808 return err;
809
810 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
811
812 /* update erase group size to be high-capacity */
813 mmc->erase_grp_size =
814 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
815
816 }
817
818 /* all OK, write the configuration */
819 for (i = 0; i < 4; i++) {
820 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
821 EXT_CSD_ENH_START_ADDR+i,
822 (enh_start_addr >> (i*8)) & 0xFF);
823 if (err)
824 return err;
825 }
826 for (i = 0; i < 3; i++) {
827 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
828 EXT_CSD_ENH_SIZE_MULT+i,
829 (enh_size_mult >> (i*8)) & 0xFF);
830 if (err)
831 return err;
832 }
833 for (pidx = 0; pidx < 4; pidx++) {
834 for (i = 0; i < 3; i++) {
835 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
836 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
837 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
838 if (err)
839 return err;
840 }
841 }
842 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
843 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
844 if (err)
845 return err;
846
847 if (mode == MMC_HWPART_CONF_SET)
848 return 0;
849
8dda5b0e
DSC		 850 /* The WR_REL_SET is a write-once register but shall be
851 * written before setting PART_SETTING_COMPLETED. As it is
852 * write-once we can only write it when completing the
853 * partitioning. */
854 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
855 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
856 EXT_CSD_WR_REL_SET, wr_rel_set);
857 if (err)
858 return err;
859 }
860
ac9da0e0
DSC		 861 /* Setting PART_SETTING_COMPLETED confirms the partition
862 * configuration but it only becomes effective after power
863 * cycle, so we do not adjust the partition related settings
864 * in the mmc struct. */
865
866 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
867 EXT_CSD_PARTITION_SETTING,
868 EXT_CSD_PARTITION_SETTING_COMPLETED);
869 if (err)
870 return err;
871
872 return 0;
873}
874
e7881d85 875#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 876int mmc_getcd(struct mmc *mmc)
877{
878 int cd;
879
880 cd = board_mmc_getcd(mmc);
881
d4e1da4e 882 if (cd < 0) {
93bfd616
PA		 883 if (mmc->cfg->ops->getcd)
884 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 885 else
886 cd = 1;
887 }
48972d90
TR		 888
889 return cd;
890}
8ca51e51 891#endif
48972d90 892
fdbb873e 893static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 894{
895 struct mmc_cmd cmd;
896 struct mmc_data data;
897
898 /* Switch the frequency */
899 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
900 cmd.resp_type = MMC_RSP_R1;
901 cmd.cmdarg = (mode << 31) | 0xffffff;
902 cmd.cmdarg &= ~(0xf << (group * 4));
903 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 904
905 data.dest = (char *)resp;
906 data.blocksize = 64;
907 data.blocks = 1;
908 data.flags = MMC_DATA_READ;
909
910 return mmc_send_cmd(mmc, &cmd, &data);
911}
912
913
fdbb873e 914static int sd_change_freq(struct mmc *mmc)
272cc70b
AF		 915{
916 int err;
917 struct mmc_cmd cmd;
18e7c8f6
SM		 918 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
919 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 920 struct mmc_data data;
921 int timeout;
922
923 mmc->card_caps = 0;
924
d52ebf10
TC		 925 if (mmc_host_is_spi(mmc))
926 return 0;
927
272cc70b
AF		 928 /* Read the SCR to find out if this card supports higher speeds */
929 cmd.cmdidx = MMC_CMD_APP_CMD;
930 cmd.resp_type = MMC_RSP_R1;
931 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 932
933 err = mmc_send_cmd(mmc, &cmd, NULL);
934
935 if (err)
936 return err;
937
938 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
939 cmd.resp_type = MMC_RSP_R1;
940 cmd.cmdarg = 0;
272cc70b
AF		 941
942 timeout = 3;
943
944retry_scr:
f781dd38 945 data.dest = (char *)scr;
272cc70b
AF		 946 data.blocksize = 8;
947 data.blocks = 1;
948 data.flags = MMC_DATA_READ;
949
950 err = mmc_send_cmd(mmc, &cmd, &data);
951
952 if (err) {
953 if (timeout--)
954 goto retry_scr;
955
956 return err;
957 }
958
4e3d89ba
YK		 959 mmc->scr[0] = __be32_to_cpu(scr[0]);
960 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 961
962 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 963 case 0:
964 mmc->version = SD_VERSION_1_0;
965 break;
966 case 1:
967 mmc->version = SD_VERSION_1_10;
968 break;
969 case 2:
970 mmc->version = SD_VERSION_2;
971 if ((mmc->scr[0] >> 15) & 0x1)
972 mmc->version = SD_VERSION_3;
973 break;
974 default:
975 mmc->version = SD_VERSION_1_0;
976 break;
272cc70b
AF		 977 }
978
b44c7083
AS		 979 if (mmc->scr[0] & SD_DATA_4BIT)
980 mmc->card_caps |= MMC_MODE_4BIT;
981
272cc70b
AF		 982 /* Version 1.0 doesn't support switching */
983 if (mmc->version == SD_VERSION_1_0)
984 return 0;
985
986 timeout = 4;
987 while (timeout--) {
988 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 989 (u8 *)switch_status);
272cc70b
AF		 990
991 if (err)
992 return err;
993
994 /* The high-speed function is busy. Try again */
4e3d89ba 995 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 996 break;
997 }
998
272cc70b 999 /* If high-speed isn't supported, we return */
4e3d89ba 1000 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF		 1001 return 0;
1002
2c3fbf4c
ML		 1003 /*
1004 * If the host doesn't support SD_HIGHSPEED, do not switch card to
1005 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
1006 * This can avoid furthur problem when the card runs in different
1007 * mode between the host.
1008 */
93bfd616
PA		 1009 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
1010 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML		 1011 return 0;
1012
f781dd38 1013 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF		 1014
1015 if (err)
1016 return err;
1017
4e3d89ba 1018 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF		 1019 mmc->card_caps |= MMC_MODE_HS;
1020
1021 return 0;
1022}
1023
3697e599
PF		 1024static int sd_read_ssr(struct mmc *mmc)
1025{
1026 int err, i;
1027 struct mmc_cmd cmd;
1028 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1029 struct mmc_data data;
1030 int timeout = 3;
1031 unsigned int au, eo, et, es;
1032
1033 cmd.cmdidx = MMC_CMD_APP_CMD;
1034 cmd.resp_type = MMC_RSP_R1;
1035 cmd.cmdarg = mmc->rca << 16;
1036
1037 err = mmc_send_cmd(mmc, &cmd, NULL);
1038 if (err)
1039 return err;
1040
1041 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1042 cmd.resp_type = MMC_RSP_R1;
1043 cmd.cmdarg = 0;
1044
1045retry_ssr:
1046 data.dest = (char *)ssr;
1047 data.blocksize = 64;
1048 data.blocks = 1;
1049 data.flags = MMC_DATA_READ;
1050
1051 err = mmc_send_cmd(mmc, &cmd, &data);
1052 if (err) {
1053 if (timeout--)
1054 goto retry_ssr;
1055
1056 return err;
1057 }
1058
1059 for (i = 0; i < 16; i++)
1060 ssr[i] = be32_to_cpu(ssr[i]);
1061
1062 au = (ssr[2] >> 12) & 0xF;
1063 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1064 mmc->ssr.au = sd_au_size[au];
1065 es = (ssr[3] >> 24) & 0xFF;
1066 es |= (ssr[2] & 0xFF) << 8;
1067 et = (ssr[3] >> 18) & 0x3F;
1068 if (es && et) {
1069 eo = (ssr[3] >> 16) & 0x3;
1070 mmc->ssr.erase_timeout = (et * 1000) / es;
1071 mmc->ssr.erase_offset = eo * 1000;
1072 }
1073 } else {
1074 debug("Invalid Allocation Unit Size.\n");
1075 }
1076
1077 return 0;
1078}
1079
272cc70b
AF		 1080/* frequency bases */
1081/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1082static const int fbase[] = {
272cc70b
AF		 1083 10000,
1084 100000,
1085 1000000,
1086 10000000,
1087};
1088
1089/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1090 * to platforms without floating point.
1091 */
61fe076f 1092static const u8 multipliers[] = {
272cc70b
AF		 1093 0, /* reserved */
1094 10,
1095 12,
1096 13,
1097 15,
1098 20,
1099 25,
1100 30,
1101 35,
1102 40,
1103 45,
1104 50,
1105 55,
1106 60,
1107 70,
1108 80,
1109};
1110
e7881d85 1111#if !CONFIG_IS_ENABLED(DM_MMC)
fdbb873e 1112static void mmc_set_ios(struct mmc *mmc)
272cc70b 1113{
93bfd616
PA		 1114 if (mmc->cfg->ops->set_ios)
1115 mmc->cfg->ops->set_ios(mmc);
272cc70b 1116}
8ca51e51 1117#endif
272cc70b
AF		 1118
1119void mmc_set_clock(struct mmc *mmc, uint clock)
1120{
93bfd616
PA		 1121 if (clock > mmc->cfg->f_max)
1122 clock = mmc->cfg->f_max;
272cc70b 1123
93bfd616
PA		 1124 if (clock < mmc->cfg->f_min)
1125 clock = mmc->cfg->f_min;
272cc70b
AF		 1126
1127 mmc->clock = clock;
1128
1129 mmc_set_ios(mmc);
1130}
1131
fdbb873e 1132static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1133{
1134 mmc->bus_width = width;
1135
1136 mmc_set_ios(mmc);
1137}
1138
4c9d2aaa
JJH		 1139#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1140/*
1141 * helper function to display the capabilities in a human
1142 * friendly manner. The capabilities include bus width and
1143 * supported modes.
1144 */
1145void mmc_dump_capabilities(const char *text, uint caps)
1146{
1147 enum bus_mode mode;
1148
1149 printf("%s: widths [", text);
1150 if (caps & MMC_MODE_8BIT)
1151 printf("8, ");
1152 if (caps & MMC_MODE_4BIT)
1153 printf("4, ");
1154 printf("1] modes [");
1155
1156 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1157 if (MMC_CAP(mode) & caps)
1158 printf("%s, ", mmc_mode_name(mode));
1159 printf("\b\b]\n");
1160}
1161#endif
1162
8ac8a263
JJH		 1163static int sd_select_bus_freq_width(struct mmc *mmc)
1164{
1165 int err;
1166 struct mmc_cmd cmd;
1167
1168 err = sd_change_freq(mmc);
1169 if (err)
1170 return err;
1171
1172 /* Restrict card's capabilities by what the host can do */
1173 mmc->card_caps &= mmc->cfg->host_caps;
1174
1175 if (mmc->card_caps & MMC_MODE_4BIT) {
1176 cmd.cmdidx = MMC_CMD_APP_CMD;
1177 cmd.resp_type = MMC_RSP_R1;
1178 cmd.cmdarg = mmc->rca << 16;
1179
1180 err = mmc_send_cmd(mmc, &cmd, NULL);
1181 if (err)
1182 return err;
1183
1184 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1185 cmd.resp_type = MMC_RSP_R1;
1186 cmd.cmdarg = 2;
1187 err = mmc_send_cmd(mmc, &cmd, NULL);
1188 if (err)
1189 return err;
1190
1191 mmc_set_bus_width(mmc, 4);
1192 }
1193
1194 err = sd_read_ssr(mmc);
1195 if (err)
1196 return err;
1197
35f9e196
JJH		 1198 if (mmc->card_caps & MMC_MODE_HS) {
1199 mmc_select_mode(mmc, SD_HS);
8ac8a263 1200 mmc->tran_speed = 50000000;
35f9e196
JJH		 1201 } else {
1202 mmc_select_mode(mmc, SD_LEGACY);
8ac8a263 1203 mmc->tran_speed = 25000000;
35f9e196 1204 }
8ac8a263
JJH		 1205
1206 return 0;
1207}
1208
7382e691
JJH		 1209/*
1210 * read the compare the part of ext csd that is constant.
1211 * This can be used to check that the transfer is working
1212 * as expected.
1213 */
1214static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1215{
7382e691 1216 int err;
dfda9d88 1217 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1218 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1219
1220 err = mmc_send_ext_csd(mmc, test_csd);
1221 if (err)
1222 return err;
1223
1224 /* Only compare read only fields */
1225 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1226 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1227 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1228 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1229 ext_csd[EXT_CSD_REV]
1230 == test_csd[EXT_CSD_REV] &&
1231 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1232 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1233 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1234 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1235 return 0;
1236
1237 return -EBADMSG;
1238}
1239
1240static int mmc_select_bus_freq_width(struct mmc *mmc)
1241{
8ac8a263
JJH		 1242 /* An array of possible bus widths in order of preference */
1243 static const unsigned int ext_csd_bits[] = {
1244 EXT_CSD_DDR_BUS_WIDTH_8,
1245 EXT_CSD_DDR_BUS_WIDTH_4,
1246 EXT_CSD_BUS_WIDTH_8,
1247 EXT_CSD_BUS_WIDTH_4,
1248 EXT_CSD_BUS_WIDTH_1,
1249 };
1250 /* An array to map CSD bus widths to host cap bits */
1251 static const unsigned int ext_to_hostcaps[] = {
1252 [EXT_CSD_DDR_BUS_WIDTH_4] =
1253 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1254 [EXT_CSD_DDR_BUS_WIDTH_8] =
1255 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
1256 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1257 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1258 };
1259 /* An array to map chosen bus width to an integer */
1260 static const unsigned int widths[] = {
1261 8, 4, 8, 4, 1,
1262 };
1263 int err;
1264 int idx;
1265
1266 err = mmc_change_freq(mmc);
1267 if (err)
1268 return err;
1269
1270 /* Restrict card's capabilities by what the host can do */
1271 mmc->card_caps &= mmc->cfg->host_caps;
1272
1273 /* Only version 4 of MMC supports wider bus widths */
1274 if (mmc->version < MMC_VERSION_4)
1275 return 0;
1276
dfda9d88
JJH		 1277 if (!mmc->ext_csd) {
1278 debug("No ext_csd found!\n"); /* this should enver happen */
1279 return -ENOTSUPP;
1280 }
1281
8ac8a263
JJH		 1282 for (idx = 0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1283 unsigned int extw = ext_csd_bits[idx];
1284 unsigned int caps = ext_to_hostcaps[extw];
1285 /*
1286 * If the bus width is still not changed,
1287 * don't try to set the default again.
1288 * Otherwise, recover from switch attempts
1289 * by switching to 1-bit bus width.
1290 */
1291 if (extw == EXT_CSD_BUS_WIDTH_1 &&
1292 mmc->bus_width == 1) {
1293 err = 0;
1294 break;
1295 }
1296
1297 /*
1298 * Check to make sure the card and controller support
1299 * these capabilities
1300 */
1301 if ((mmc->card_caps & caps) != caps)
1302 continue;
1303
1304 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1305 EXT_CSD_BUS_WIDTH, extw);
1306
1307 if (err)
1308 continue;
1309
1310 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
1311 mmc_set_bus_width(mmc, widths[idx]);
1312
7382e691
JJH		 1313 err = mmc_read_and_compare_ext_csd(mmc);
1314 if (!err)
8ac8a263 1315 break;
8ac8a263
JJH		 1316 }
1317
1318 if (err)
1319 return err;
1320
35f9e196
JJH		 1321 if (mmc->card_caps & MMC_MODE_HS_52MHz) {
1322 if (mmc->ddr_mode)
1323 mmc_select_mode(mmc, MMC_DDR_52);
8ac8a263 1324 else
35f9e196
JJH		 1325 mmc_select_mode(mmc, MMC_HS_52);
1326 mmc->tran_speed = 52000000;
1327 } else if (mmc->card_caps & MMC_MODE_HS) {
1328 mmc_select_mode(mmc, MMC_HS);
1329 mmc->tran_speed = 26000000;
8ac8a263
JJH		 1330 }
1331
1332 return err;
1333}
1334
dfda9d88 1335static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 1336{
1337 int err, i;
1338 u64 capacity;
1339 bool has_parts = false;
1340 bool part_completed;
dfda9d88 1341 u8 *ext_csd;
c744b6f6
JJH		 1342
1343 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1344 return 0;
1345
dfda9d88
JJH		 1346 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1347 if (!ext_csd)
1348 return -ENOMEM;
1349
1350 mmc->ext_csd = ext_csd;
1351
c744b6f6
JJH		 1352 /* check ext_csd version and capacity */
1353 err = mmc_send_ext_csd(mmc, ext_csd);
1354 if (err)
1355 return err;
1356 if (ext_csd[EXT_CSD_REV] >= 2) {
1357 /*
1358 * According to the JEDEC Standard, the value of
1359 * ext_csd's capacity is valid if the value is more
1360 * than 2GB
1361 */
1362 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1363 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1364 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1365 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1366 capacity *= MMC_MAX_BLOCK_LEN;
1367 if ((capacity >> 20) > 2 * 1024)
1368 mmc->capacity_user = capacity;
1369 }
1370
1371 switch (ext_csd[EXT_CSD_REV]) {
1372 case 1:
1373 mmc->version = MMC_VERSION_4_1;
1374 break;
1375 case 2:
1376 mmc->version = MMC_VERSION_4_2;
1377 break;
1378 case 3:
1379 mmc->version = MMC_VERSION_4_3;
1380 break;
1381 case 5:
1382 mmc->version = MMC_VERSION_4_41;
1383 break;
1384 case 6:
1385 mmc->version = MMC_VERSION_4_5;
1386 break;
1387 case 7:
1388 mmc->version = MMC_VERSION_5_0;
1389 break;
1390 case 8:
1391 mmc->version = MMC_VERSION_5_1;
1392 break;
1393 }
1394
1395 /* The partition data may be non-zero but it is only
1396 * effective if PARTITION_SETTING_COMPLETED is set in
1397 * EXT_CSD, so ignore any data if this bit is not set,
1398 * except for enabling the high-capacity group size
1399 * definition (see below).
1400 */
1401 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1402 EXT_CSD_PARTITION_SETTING_COMPLETED);
1403
1404 /* store the partition info of emmc */
1405 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1406 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1407 ext_csd[EXT_CSD_BOOT_MULT])
1408 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1409 if (part_completed &&
1410 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1411 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1412
1413 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1414
1415 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1416
1417 for (i = 0; i < 4; i++) {
1418 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1419 uint mult = (ext_csd[idx + 2] << 16) +
1420 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1421 if (mult)
1422 has_parts = true;
1423 if (!part_completed)
1424 continue;
1425 mmc->capacity_gp[i] = mult;
1426 mmc->capacity_gp[i] *=
1427 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1428 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1429 mmc->capacity_gp[i] <<= 19;
1430 }
1431
1432 if (part_completed) {
1433 mmc->enh_user_size =
1434 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1435 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1436 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1437 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1438 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1439 mmc->enh_user_size <<= 19;
1440 mmc->enh_user_start =
1441 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1442 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1443 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1444 ext_csd[EXT_CSD_ENH_START_ADDR];
1445 if (mmc->high_capacity)
1446 mmc->enh_user_start <<= 9;
1447 }
1448
1449 /*
1450 * Host needs to enable ERASE_GRP_DEF bit if device is
1451 * partitioned. This bit will be lost every time after a reset
1452 * or power off. This will affect erase size.
1453 */
1454 if (part_completed)
1455 has_parts = true;
1456 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1457 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1458 has_parts = true;
1459 if (has_parts) {
1460 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1461 EXT_CSD_ERASE_GROUP_DEF, 1);
1462
1463 if (err)
1464 return err;
1465
1466 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1467 }
1468
1469 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1470 /* Read out group size from ext_csd */
1471 mmc->erase_grp_size =
1472 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1473 /*
1474 * if high capacity and partition setting completed
1475 * SEC_COUNT is valid even if it is smaller than 2 GiB
1476 * JEDEC Standard JESD84-B45, 6.2.4
1477 */
1478 if (mmc->high_capacity && part_completed) {
1479 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1480 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1481 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1482 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1483 capacity *= MMC_MAX_BLOCK_LEN;
1484 mmc->capacity_user = capacity;
1485 }
1486 } else {
1487 /* Calculate the group size from the csd value. */
1488 int erase_gsz, erase_gmul;
1489
1490 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1491 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1492 mmc->erase_grp_size = (erase_gsz + 1)
1493 * (erase_gmul + 1);
1494 }
1495
1496 mmc->hc_wp_grp_size = 1024
1497 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1498 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1499
1500 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1501
1502 return 0;
1503}
1504
fdbb873e 1505static int mmc_startup(struct mmc *mmc)
272cc70b 1506{
f866a46d 1507 int err, i;
272cc70b 1508 uint mult, freq;
c744b6f6 1509 u64 cmult, csize;
272cc70b 1510 struct mmc_cmd cmd;
c40fdca6 1511 struct blk_desc *bdesc;
272cc70b 1512
d52ebf10
TC		 1513#ifdef CONFIG_MMC_SPI_CRC_ON
1514 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1515 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1516 cmd.resp_type = MMC_RSP_R1;
1517 cmd.cmdarg = 1;
d52ebf10
TC		 1518 err = mmc_send_cmd(mmc, &cmd, NULL);
1519
1520 if (err)
1521 return err;
1522 }
1523#endif
1524
272cc70b 1525 /* Put the Card in Identify Mode */
d52ebf10
TC		 1526 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1527 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1528 cmd.resp_type = MMC_RSP_R2;
1529 cmd.cmdarg = 0;
272cc70b
AF		 1530
1531 err = mmc_send_cmd(mmc, &cmd, NULL);
1532
1533 if (err)
1534 return err;
1535
1536 memcpy(mmc->cid, cmd.response, 16);
1537
1538 /*
1539 * For MMC cards, set the Relative Address.
1540 * For SD cards, get the Relatvie Address.
1541 * This also puts the cards into Standby State
1542 */
d52ebf10
TC		 1543 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1544 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1545 cmd.cmdarg = mmc->rca << 16;
1546 cmd.resp_type = MMC_RSP_R6;
272cc70b 1547
d52ebf10 1548 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1549
d52ebf10
TC		 1550 if (err)
1551 return err;
272cc70b 1552
d52ebf10
TC		 1553 if (IS_SD(mmc))
1554 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1555 }
272cc70b
AF		 1556
1557 /* Get the Card-Specific Data */
1558 cmd.cmdidx = MMC_CMD_SEND_CSD;
1559 cmd.resp_type = MMC_RSP_R2;
1560 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1561
1562 err = mmc_send_cmd(mmc, &cmd, NULL);
1563
1564 if (err)
1565 return err;
1566
998be3dd
RV		 1567 mmc->csd[0] = cmd.response[0];
1568 mmc->csd[1] = cmd.response[1];
1569 mmc->csd[2] = cmd.response[2];
1570 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1571
1572 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1573 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1574
1575 switch (version) {
53e8e40b
BM		 1576 case 0:
1577 mmc->version = MMC_VERSION_1_2;
1578 break;
1579 case 1:
1580 mmc->version = MMC_VERSION_1_4;
1581 break;
1582 case 2:
1583 mmc->version = MMC_VERSION_2_2;
1584 break;
1585 case 3:
1586 mmc->version = MMC_VERSION_3;
1587 break;
1588 case 4:
1589 mmc->version = MMC_VERSION_4;
1590 break;
1591 default:
1592 mmc->version = MMC_VERSION_1_2;
1593 break;
272cc70b
AF		 1594 }
1595 }
1596
1597 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1598 freq = fbase[(cmd.response[0] & 0x7)];
1599 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 1600
35f9e196
JJH		 1601 mmc->legacy_speed = freq * mult;
1602 mmc->tran_speed = mmc->legacy_speed;
1603 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 1604
ab71188c 1605 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1606 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1607
1608 if (IS_SD(mmc))
1609 mmc->write_bl_len = mmc->read_bl_len;
1610 else
998be3dd 1611 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1612
1613 if (mmc->high_capacity) {
1614 csize = (mmc->csd[1] & 0x3f) << 16
1615 | (mmc->csd[2] & 0xffff0000) >> 16;
1616 cmult = 8;
1617 } else {
1618 csize = (mmc->csd[1] & 0x3ff) << 2
1619 | (mmc->csd[2] & 0xc0000000) >> 30;
1620 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1621 }
1622
f866a46d
SW		 1623 mmc->capacity_user = (csize + 1) << (cmult + 2);
1624 mmc->capacity_user *= mmc->read_bl_len;
1625 mmc->capacity_boot = 0;
1626 mmc->capacity_rpmb = 0;
1627 for (i = 0; i < 4; i++)
1628 mmc->capacity_gp[i] = 0;
272cc70b 1629
8bfa195e
SG		 1630 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1631 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1632
8bfa195e
SG		 1633 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1634 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1635
ab71188c
MN		 1636 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1637 cmd.cmdidx = MMC_CMD_SET_DSR;
1638 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1639 cmd.resp_type = MMC_RSP_NONE;
1640 if (mmc_send_cmd(mmc, &cmd, NULL))
1641 printf("MMC: SET_DSR failed\n");
1642 }
1643
272cc70b 1644 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1645 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1646 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1647 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1648 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1649 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1650
d52ebf10
TC		 1651 if (err)
1652 return err;
1653 }
272cc70b 1654
e6f99a56
LW		 1655 /*
1656 * For SD, its erase group is always one sector
1657 */
1658 mmc->erase_grp_size = 1;
bc897b1d 1659 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 1660
dfda9d88 1661 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 1662 if (err)
1663 return err;
d23e2c09 1664
c40fdca6 1665 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 1666 if (err)
1667 return err;
1668
272cc70b 1669 if (IS_SD(mmc))
8ac8a263 1670 err = sd_select_bus_freq_width(mmc);
272cc70b 1671 else
dfda9d88 1672 err = mmc_select_bus_freq_width(mmc);
272cc70b
AF		 1673
1674 if (err)
1675 return err;
1676
ad5fd922
JC		 1677 mmc_set_clock(mmc, mmc->tran_speed);
1678
5af8f45c
AG		 1679 /* Fix the block length for DDR mode */
1680 if (mmc->ddr_mode) {
1681 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1682 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1683 }
1684
272cc70b 1685 /* fill in device description */
c40fdca6
SG		 1686 bdesc = mmc_get_blk_desc(mmc);
1687 bdesc->lun = 0;
1688 bdesc->hwpart = 0;
1689 bdesc->type = 0;
1690 bdesc->blksz = mmc->read_bl_len;
1691 bdesc->log2blksz = LOG2(bdesc->blksz);
1692 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 1693#if !defined(CONFIG_SPL_BUILD) || \
1694 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
1695 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 1696 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 1697 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1698 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 1699 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 1700 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1701 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1702 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 1703 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 1704 (mmc->cid[2] >> 16) & 0xf);
56196826 1705#else
c40fdca6
SG		 1706 bdesc->vendor[0] = 0;
1707 bdesc->product[0] = 0;
1708 bdesc->revision[0] = 0;
56196826 1709#endif
122efd43 1710#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 1711 part_init(bdesc);
122efd43 1712#endif
272cc70b
AF		 1713
1714 return 0;
1715}
1716
fdbb873e 1717static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 1718{
1719 struct mmc_cmd cmd;
1720 int err;
1721
1722 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1723 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1724 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1725 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 1726
1727 err = mmc_send_cmd(mmc, &cmd, NULL);
1728
1729 if (err)
1730 return err;
1731
998be3dd 1732 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 1733 return -EOPNOTSUPP;
272cc70b
AF		 1734 else
1735 mmc->version = SD_VERSION_2;
1736
1737 return 0;
1738}
1739
c4d660d4 1740#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 1741/* board-specific MMC power initializations. */
1742__weak void board_mmc_power_init(void)
1743{
1744}
05cbeb7c 1745#endif
95de9ab2 1746
2051aefe
PF		 1747static int mmc_power_init(struct mmc *mmc)
1748{
c4d660d4 1749#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 1750#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 1751 int ret;
1752
1753 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 1754 &mmc->vmmc_supply);
1755 if (ret)
288db7c7 1756 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 1757
06ec045f
JJH		 1758 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
1759 &mmc->vqmmc_supply);
1760 if (ret)
1761 debug("%s: No vqmmc supply\n", mmc->dev->name);
1762
1763 if (mmc->vmmc_supply) {
1764 ret = regulator_set_enable(mmc->vmmc_supply, true);
1765 if (ret) {
1766 puts("Error enabling VMMC supply\n");
1767 return ret;
1768 }
2051aefe 1769 }
05cbeb7c
SG		 1770#endif
1771#else /* !CONFIG_DM_MMC */
1772 /*
1773 * Driver model should use a regulator, as above, rather than calling
1774 * out to board code.
1775 */
1776 board_mmc_power_init();
2051aefe
PF		 1777#endif
1778 return 0;
1779}
1780
e9550449 1781int mmc_start_init(struct mmc *mmc)
272cc70b 1782{
8ca51e51 1783 bool no_card;
afd5932b 1784 int err;
272cc70b 1785
ab769f22 1786 /* we pretend there's no card when init is NULL */
8ca51e51 1787 no_card = mmc_getcd(mmc) == 0;
e7881d85 1788#if !CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 1789 no_card = no_card || (mmc->cfg->ops->init == NULL);
1790#endif
1791 if (no_card) {
48972d90 1792 mmc->has_init = 0;
56196826 1793#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1794 printf("MMC: no card present\n");
56196826 1795#endif
915ffa52 1796 return -ENOMEDIUM;
48972d90
TR		 1797 }
1798
bc897b1d
LW		 1799 if (mmc->has_init)
1800 return 0;
1801
5a8dbdc6
YL		 1802#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
1803 mmc_adapter_card_type_ident();
1804#endif
2051aefe
PF		 1805 err = mmc_power_init(mmc);
1806 if (err)
1807 return err;
95de9ab2 1808
e7881d85 1809#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 1810 /* The device has already been probed ready for use */
1811#else
ab769f22 1812 /* made sure it's not NULL earlier */
93bfd616 1813 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 1814 if (err)
1815 return err;
8ca51e51 1816#endif
786e8f81 1817 mmc->ddr_mode = 0;
b86b85e2
IY		 1818 mmc_set_bus_width(mmc, 1);
1819 mmc_set_clock(mmc, 1);
1820
272cc70b
AF		 1821 /* Reset the Card */
1822 err = mmc_go_idle(mmc);
1823
1824 if (err)
1825 return err;
1826
bc897b1d 1827 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 1828 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 1829
272cc70b 1830 /* Test for SD version 2 */
afd5932b 1831 err = mmc_send_if_cond(mmc);
272cc70b 1832
272cc70b
AF		 1833 /* Now try to get the SD card's operating condition */
1834 err = sd_send_op_cond(mmc);
1835
1836 /* If the command timed out, we check for an MMC card */
915ffa52 1837 if (err == -ETIMEDOUT) {
272cc70b
AF		 1838 err = mmc_send_op_cond(mmc);
1839
bd47c135 1840 if (err) {
56196826 1841#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1842 printf("Card did not respond to voltage select!\n");
56196826 1843#endif
915ffa52 1844 return -EOPNOTSUPP;
272cc70b
AF		 1845 }
1846 }
1847
bd47c135 1848 if (!err)
e9550449
CLC		 1849 mmc->init_in_progress = 1;
1850
1851 return err;
1852}
1853
1854static int mmc_complete_init(struct mmc *mmc)
1855{
1856 int err = 0;
1857
bd47c135 1858 mmc->init_in_progress = 0;
e9550449
CLC		 1859 if (mmc->op_cond_pending)
1860 err = mmc_complete_op_cond(mmc);
1861
1862 if (!err)
1863 err = mmc_startup(mmc);
bc897b1d
LW		 1864 if (err)
1865 mmc->has_init = 0;
1866 else
1867 mmc->has_init = 1;
e9550449
CLC		 1868 return err;
1869}
1870
1871int mmc_init(struct mmc *mmc)
1872{
bd47c135 1873 int err = 0;
ce9eca94 1874 __maybe_unused unsigned start;
c4d660d4 1875#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 1876 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 1877
33fb211d
SG		 1878 upriv->mmc = mmc;
1879#endif
e9550449
CLC		 1880 if (mmc->has_init)
1881 return 0;
d803fea5
MZ		 1882
1883 start = get_timer(0);
1884
e9550449
CLC		 1885 if (!mmc->init_in_progress)
1886 err = mmc_start_init(mmc);
1887
bd47c135 1888 if (!err)
e9550449 1889 err = mmc_complete_init(mmc);
919b4858
JT		 1890 if (err)
1891 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
1892
bc897b1d 1893 return err;
272cc70b
AF		 1894}
1895
ab71188c
MN		 1896int mmc_set_dsr(struct mmc *mmc, u16 val)
1897{
1898 mmc->dsr = val;
1899 return 0;
1900}
1901
cee9ab7c
JH		 1902/* CPU-specific MMC initializations */
1903__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 1904{
1905 return -1;
1906}
1907
cee9ab7c
JH		 1908/* board-specific MMC initializations. */
1909__weak int board_mmc_init(bd_t *bis)
1910{
1911 return -1;
1912}
272cc70b 1913
e9550449
CLC		 1914void mmc_set_preinit(struct mmc *mmc, int preinit)
1915{
1916 mmc->preinit = preinit;
1917}
1918
c4d660d4 1919#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
8e3332e2
SS		 1920static int mmc_probe(bd_t *bis)
1921{
1922 return 0;
1923}
c4d660d4 1924#elif CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 1925static int mmc_probe(bd_t *bis)
1926{
4a1db6d8 1927 int ret, i;
8e3332e2 1928 struct uclass *uc;
4a1db6d8 1929 struct udevice *dev;
8e3332e2
SS		 1930
1931 ret = uclass_get(UCLASS_MMC, &uc);
1932 if (ret)
1933 return ret;
1934
4a1db6d8
SG		 1935 /*
1936 * Try to add them in sequence order. Really with driver model we
1937 * should allow holes, but the current MMC list does not allow that.
1938 * So if we request 0, 1, 3 we will get 0, 1, 2.
1939 */
1940 for (i = 0; ; i++) {
1941 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
1942 if (ret == -ENODEV)
1943 break;
1944 }
1945 uclass_foreach_dev(dev, uc) {
1946 ret = device_probe(dev);
8e3332e2 1947 if (ret)
4a1db6d8 1948 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 1949 }
1950
1951 return 0;
1952}
1953#else
1954static int mmc_probe(bd_t *bis)
1955{
1956 if (board_mmc_init(bis) < 0)
1957 cpu_mmc_init(bis);
1958
1959 return 0;
1960}
1961#endif
e9550449 1962
272cc70b
AF		 1963int mmc_initialize(bd_t *bis)
1964{
1b26bab1 1965 static int initialized = 0;
8e3332e2 1966 int ret;
1b26bab1
DK		 1967 if (initialized) /* Avoid initializing mmc multiple times */
1968 return 0;
1969 initialized = 1;
1970
c4d660d4 1971#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 1972#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 1973 mmc_list_init();
b5b838f1 1974#endif
c40fdca6 1975#endif
8e3332e2
SS		 1976 ret = mmc_probe(bis);
1977 if (ret)
1978 return ret;
272cc70b 1979
bb0dc108 1980#ifndef CONFIG_SPL_BUILD
272cc70b 1981 print_mmc_devices(',');
bb0dc108 1982#endif
272cc70b 1983
c40fdca6 1984 mmc_do_preinit();
272cc70b
AF		 1985 return 0;
1986}
cd3d4880
TM		 1987
1988#ifdef CONFIG_CMD_BKOPS_ENABLE
1989int mmc_set_bkops_enable(struct mmc *mmc)
1990{
1991 int err;
1992 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
1993
1994 err = mmc_send_ext_csd(mmc, ext_csd);
1995 if (err) {
1996 puts("Could not get ext_csd register values\n");
1997 return err;
1998 }
1999
2000 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2001 puts("Background operations not supported on device\n");
2002 return -EMEDIUMTYPE;
2003 }
2004
2005 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2006 puts("Background operations already enabled\n");
2007 return 0;
2008 }
2009
2010 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2011 if (err) {
2012 puts("Failed to enable manual background operations\n");
2013 return err;
2014 }
2015
2016 puts("Enabled manual background operations\n");
2017
2018 return 0;
2019}
2020#endif
"Das U-Boot" Source Tree