]> git.ipfire.org Git - people/ms/u-boot.git/blame - drivers/mmc/mmc.c
mmc: display size and start of eMMC enhanced user data area in mmcinfo
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF
1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF
8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
d4622df3 13#include <errno.h>
272cc70b
AF
14#include <mmc.h>
15#include <part.h>
16#include <malloc.h>
17#include <linux/list.h>
9b1f942c 18#include <div64.h>
da61fa5f 19#include "mmc_private.h"
272cc70b
AF
20
21static struct list_head mmc_devices;
22static int cur_dev_num = -1;
23
750121c3 24__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK
25{
26 return -1;
27}
28
29int mmc_getwp(struct mmc *mmc)
30{
31 int wp;
32
33 wp = board_mmc_getwp(mmc);
34
d4e1da4e 35 if (wp < 0) {
93bfd616
PA
36 if (mmc->cfg->ops->getwp)
37 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK
38 else
39 wp = 0;
40 }
d23d8d7e
NK
41
42 return wp;
43}
44
cee9ab7c
JH
45__weak int board_mmc_getcd(struct mmc *mmc)
46{
11fdade2
SB
47 return -1;
48}
49
da61fa5f 50int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
272cc70b 51{
5db2fe3a 52 int ret;
8635ff9e 53
8635ff9e 54#ifdef CONFIG_MMC_TRACE
5db2fe3a
RR
55 int i;
56 u8 *ptr;
57
58 printf("CMD_SEND:%d\n", cmd->cmdidx);
59 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
93bfd616 60 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a
RR
61 switch (cmd->resp_type) {
62 case MMC_RSP_NONE:
63 printf("\t\tMMC_RSP_NONE\n");
64 break;
65 case MMC_RSP_R1:
66 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
67 cmd->response[0]);
68 break;
69 case MMC_RSP_R1b:
70 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
71 cmd->response[0]);
72 break;
73 case MMC_RSP_R2:
74 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
75 cmd->response[0]);
76 printf("\t\t \t\t 0x%08X \n",
77 cmd->response[1]);
78 printf("\t\t \t\t 0x%08X \n",
79 cmd->response[2]);
80 printf("\t\t \t\t 0x%08X \n",
81 cmd->response[3]);
82 printf("\n");
83 printf("\t\t\t\t\tDUMPING DATA\n");
84 for (i = 0; i < 4; i++) {
85 int j;
86 printf("\t\t\t\t\t%03d - ", i*4);
146bec79 87 ptr = (u8 *)&cmd->response[i];
5db2fe3a
RR
88 ptr += 3;
89 for (j = 0; j < 4; j++)
90 printf("%02X ", *ptr--);
91 printf("\n");
92 }
93 break;
94 case MMC_RSP_R3:
95 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
96 cmd->response[0]);
97 break;
98 default:
99 printf("\t\tERROR MMC rsp not supported\n");
100 break;
101 }
5db2fe3a 102#else
93bfd616 103 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
5db2fe3a 104#endif
8635ff9e 105 return ret;
272cc70b
AF
106}
107
da61fa5f 108int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR
109{
110 struct mmc_cmd cmd;
d617c426 111 int err, retries = 5;
5d4fc8d9
RR
112#ifdef CONFIG_MMC_TRACE
113 int status;
114#endif
115
116 cmd.cmdidx = MMC_CMD_SEND_STATUS;
117 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV
118 if (!mmc_host_is_spi(mmc))
119 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9
RR
120
121 do {
122 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK
123 if (!err) {
124 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
125 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
126 MMC_STATE_PRG)
127 break;
128 else if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 129#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK
130 printf("Status Error: 0x%08X\n",
131 cmd.response[0]);
56196826 132#endif
d617c426
JK
133 return COMM_ERR;
134 }
135 } else if (--retries < 0)
5d4fc8d9 136 return err;
5d4fc8d9
RR
137
138 udelay(1000);
139
5d4fc8d9
RR
140 } while (timeout--);
141
5db2fe3a
RR
142#ifdef CONFIG_MMC_TRACE
143 status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9;
144 printf("CURR STATE:%d\n", status);
145#endif
5b0c942f 146 if (timeout <= 0) {
56196826 147#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 148 printf("Timeout waiting card ready\n");
56196826 149#endif
5d4fc8d9
RR
150 return TIMEOUT;
151 }
6b2221b0
AG
152 if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR)
153 return SWITCH_ERR;
5d4fc8d9
RR
154
155 return 0;
156}
157
da61fa5f 158int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF
159{
160 struct mmc_cmd cmd;
161
786e8f81 162 if (mmc->ddr_mode)
d22e3d46
JC
163 return 0;
164
272cc70b
AF
165 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
166 cmd.resp_type = MMC_RSP_R1;
167 cmd.cmdarg = len;
272cc70b
AF
168
169 return mmc_send_cmd(mmc, &cmd, NULL);
170}
171
172struct mmc *find_mmc_device(int dev_num)
173{
174 struct mmc *m;
175 struct list_head *entry;
176
177 list_for_each(entry, &mmc_devices) {
178 m = list_entry(entry, struct mmc, link);
179
180 if (m->block_dev.dev == dev_num)
181 return m;
182 }
183
56196826 184#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 185 printf("MMC Device %d not found\n", dev_num);
56196826 186#endif
272cc70b
AF
187
188 return NULL;
189}
190
ff8fef56 191static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 192 lbaint_t blkcnt)
272cc70b
AF
193{
194 struct mmc_cmd cmd;
195 struct mmc_data data;
196
4a1a06bc
AS
197 if (blkcnt > 1)
198 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
199 else
200 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF
201
202 if (mmc->high_capacity)
4a1a06bc 203 cmd.cmdarg = start;
272cc70b 204 else
4a1a06bc 205 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF
206
207 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF
208
209 data.dest = dst;
4a1a06bc 210 data.blocks = blkcnt;
272cc70b
AF
211 data.blocksize = mmc->read_bl_len;
212 data.flags = MMC_DATA_READ;
213
4a1a06bc
AS
214 if (mmc_send_cmd(mmc, &cmd, &data))
215 return 0;
272cc70b 216
4a1a06bc
AS
217 if (blkcnt > 1) {
218 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
219 cmd.cmdarg = 0;
220 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 221 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 222#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 223 printf("mmc fail to send stop cmd\n");
56196826 224#endif
4a1a06bc
AS
225 return 0;
226 }
272cc70b
AF
227 }
228
4a1a06bc 229 return blkcnt;
272cc70b
AF
230}
231
ff8fef56 232static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst)
272cc70b 233{
4a1a06bc
AS
234 lbaint_t cur, blocks_todo = blkcnt;
235
236 if (blkcnt == 0)
237 return 0;
272cc70b 238
4a1a06bc 239 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF
240 if (!mmc)
241 return 0;
242
d2bf29e3 243 if ((start + blkcnt) > mmc->block_dev.lba) {
56196826 244#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 245 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
d2bf29e3 246 start + blkcnt, mmc->block_dev.lba);
56196826 247#endif
d2bf29e3
LW
248 return 0;
249 }
272cc70b 250
4a1a06bc 251 if (mmc_set_blocklen(mmc, mmc->read_bl_len))
272cc70b 252 return 0;
272cc70b 253
4a1a06bc 254 do {
93bfd616
PA
255 cur = (blocks_todo > mmc->cfg->b_max) ?
256 mmc->cfg->b_max : blocks_todo;
4a1a06bc
AS
257 if(mmc_read_blocks(mmc, dst, start, cur) != cur)
258 return 0;
259 blocks_todo -= cur;
260 start += cur;
261 dst += cur * mmc->read_bl_len;
262 } while (blocks_todo > 0);
272cc70b
AF
263
264 return blkcnt;
265}
266
fdbb873e 267static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF
268{
269 struct mmc_cmd cmd;
270 int err;
271
272 udelay(1000);
273
274 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
275 cmd.cmdarg = 0;
276 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF
277
278 err = mmc_send_cmd(mmc, &cmd, NULL);
279
280 if (err)
281 return err;
282
283 udelay(2000);
284
285 return 0;
286}
287
fdbb873e 288static int sd_send_op_cond(struct mmc *mmc)
272cc70b
AF
289{
290 int timeout = 1000;
291 int err;
292 struct mmc_cmd cmd;
293
294 do {
295 cmd.cmdidx = MMC_CMD_APP_CMD;
296 cmd.resp_type = MMC_RSP_R1;
297 cmd.cmdarg = 0;
272cc70b
AF
298
299 err = mmc_send_cmd(mmc, &cmd, NULL);
300
301 if (err)
302 return err;
303
304 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
305 cmd.resp_type = MMC_RSP_R3;
250de12b
SB
306
307 /*
308 * Most cards do not answer if some reserved bits
309 * in the ocr are set. However, Some controller
310 * can set bit 7 (reserved for low voltages), but
311 * how to manage low voltages SD card is not yet
312 * specified.
313 */
d52ebf10 314 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 315 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF
316
317 if (mmc->version == SD_VERSION_2)
318 cmd.cmdarg |= OCR_HCS;
319
320 err = mmc_send_cmd(mmc, &cmd, NULL);
321
322 if (err)
323 return err;
324
325 udelay(1000);
326 } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--);
327
328 if (timeout <= 0)
329 return UNUSABLE_ERR;
330
331 if (mmc->version != SD_VERSION_2)
332 mmc->version = SD_VERSION_1_0;
333
d52ebf10
TC
334 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
335 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
336 cmd.resp_type = MMC_RSP_R3;
337 cmd.cmdarg = 0;
d52ebf10
TC
338
339 err = mmc_send_cmd(mmc, &cmd, NULL);
340
341 if (err)
342 return err;
343 }
344
998be3dd 345 mmc->ocr = cmd.response[0];
272cc70b
AF
346
347 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
348 mmc->rca = 0;
349
350 return 0;
351}
352
e9550449
CLC
353/* We pass in the cmd since otherwise the init seems to fail */
354static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd,
355 int use_arg)
272cc70b 356{
272cc70b
AF
357 int err;
358
e9550449
CLC
359 cmd->cmdidx = MMC_CMD_SEND_OP_COND;
360 cmd->resp_type = MMC_RSP_R3;
361 cmd->cmdarg = 0;
362 if (use_arg && !mmc_host_is_spi(mmc)) {
363 cmd->cmdarg =
93bfd616 364 (mmc->cfg->voltages &
e9550449
CLC
365 (mmc->op_cond_response & OCR_VOLTAGE_MASK)) |
366 (mmc->op_cond_response & OCR_ACCESS_MODE);
367
93bfd616 368 if (mmc->cfg->host_caps & MMC_MODE_HC)
e9550449
CLC
369 cmd->cmdarg |= OCR_HCS;
370 }
371 err = mmc_send_cmd(mmc, cmd, NULL);
372 if (err)
373 return err;
374 mmc->op_cond_response = cmd->response[0];
375 return 0;
376}
377
750121c3 378static int mmc_send_op_cond(struct mmc *mmc)
e9550449
CLC
379{
380 struct mmc_cmd cmd;
381 int err, i;
382
272cc70b
AF
383 /* Some cards seem to need this */
384 mmc_go_idle(mmc);
385
31cacbab 386 /* Asking to the card its capabilities */
e9550449
CLC
387 mmc->op_cond_pending = 1;
388 for (i = 0; i < 2; i++) {
389 err = mmc_send_op_cond_iter(mmc, &cmd, i != 0);
390 if (err)
391 return err;
cd6881b5 392
e9550449
CLC
393 /* exit if not busy (flag seems to be inverted) */
394 if (mmc->op_cond_response & OCR_BUSY)
395 return 0;
396 }
397 return IN_PROGRESS;
398}
cd6881b5 399
750121c3 400static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC
401{
402 struct mmc_cmd cmd;
403 int timeout = 1000;
404 uint start;
405 int err;
cd6881b5 406
e9550449
CLC
407 mmc->op_cond_pending = 0;
408 start = get_timer(0);
272cc70b 409 do {
e9550449 410 err = mmc_send_op_cond_iter(mmc, &cmd, 1);
272cc70b
AF
411 if (err)
412 return err;
e9550449
CLC
413 if (get_timer(start) > timeout)
414 return UNUSABLE_ERR;
415 udelay(100);
416 } while (!(mmc->op_cond_response & OCR_BUSY));
272cc70b 417
d52ebf10
TC
418 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
419 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
420 cmd.resp_type = MMC_RSP_R3;
421 cmd.cmdarg = 0;
d52ebf10
TC
422
423 err = mmc_send_cmd(mmc, &cmd, NULL);
424
425 if (err)
426 return err;
427 }
428
272cc70b 429 mmc->version = MMC_VERSION_UNKNOWN;
998be3dd 430 mmc->ocr = cmd.response[0];
272cc70b
AF
431
432 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 433 mmc->rca = 1;
272cc70b
AF
434
435 return 0;
436}
437
438
fdbb873e 439static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF
440{
441 struct mmc_cmd cmd;
442 struct mmc_data data;
443 int err;
444
445 /* Get the Card Status Register */
446 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
447 cmd.resp_type = MMC_RSP_R1;
448 cmd.cmdarg = 0;
272cc70b 449
cdfd1ac6 450 data.dest = (char *)ext_csd;
272cc70b 451 data.blocks = 1;
8bfa195e 452 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF
453 data.flags = MMC_DATA_READ;
454
455 err = mmc_send_cmd(mmc, &cmd, &data);
456
457 return err;
458}
459
460
fdbb873e 461static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF
462{
463 struct mmc_cmd cmd;
5d4fc8d9
RR
464 int timeout = 1000;
465 int ret;
272cc70b
AF
466
467 cmd.cmdidx = MMC_CMD_SWITCH;
468 cmd.resp_type = MMC_RSP_R1b;
469 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR
470 (index << 16) |
471 (value << 8);
272cc70b 472
5d4fc8d9
RR
473 ret = mmc_send_cmd(mmc, &cmd, NULL);
474
475 /* Waiting for the ready status */
93ad0d18
JK
476 if (!ret)
477 ret = mmc_send_status(mmc, timeout);
5d4fc8d9
RR
478
479 return ret;
480
272cc70b
AF
481}
482
fdbb873e 483static int mmc_change_freq(struct mmc *mmc)
272cc70b 484{
8bfa195e 485 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
272cc70b
AF
486 char cardtype;
487 int err;
488
786e8f81 489 mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 490
d52ebf10
TC
491 if (mmc_host_is_spi(mmc))
492 return 0;
493
272cc70b
AF
494 /* Only version 4 supports high-speed */
495 if (mmc->version < MMC_VERSION_4)
496 return 0;
497
272cc70b
AF
498 err = mmc_send_ext_csd(mmc, ext_csd);
499
500 if (err)
501 return err;
502
0560db18 503 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf;
272cc70b
AF
504
505 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
506
507 if (err)
6b2221b0 508 return err == SWITCH_ERR ? 0 : err;
272cc70b
AF
509
510 /* Now check to see that it worked */
511 err = mmc_send_ext_csd(mmc, ext_csd);
512
513 if (err)
514 return err;
515
516 /* No high-speed support */
0560db18 517 if (!ext_csd[EXT_CSD_HS_TIMING])
272cc70b
AF
518 return 0;
519
520 /* High Speed is set, there are two types: 52MHz and 26MHz */
d22e3d46 521 if (cardtype & EXT_CSD_CARD_TYPE_52) {
201d5ac4 522 if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
d22e3d46 523 mmc->card_caps |= MMC_MODE_DDR_52MHz;
272cc70b 524 mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
d22e3d46 525 } else {
272cc70b 526 mmc->card_caps |= MMC_MODE_HS;
d22e3d46 527 }
272cc70b
AF
528
529 return 0;
530}
531
f866a46d
SW
532static int mmc_set_capacity(struct mmc *mmc, int part_num)
533{
534 switch (part_num) {
535 case 0:
536 mmc->capacity = mmc->capacity_user;
537 break;
538 case 1:
539 case 2:
540 mmc->capacity = mmc->capacity_boot;
541 break;
542 case 3:
543 mmc->capacity = mmc->capacity_rpmb;
544 break;
545 case 4:
546 case 5:
547 case 6:
548 case 7:
549 mmc->capacity = mmc->capacity_gp[part_num - 4];
550 break;
551 default:
552 return -1;
553 }
554
555 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
556
557 return 0;
558}
559
d2356284
SW
560int mmc_select_hwpart(int dev_num, int hwpart)
561{
562 struct mmc *mmc = find_mmc_device(dev_num);
563 int ret;
564
565 if (!mmc)
d4622df3 566 return -ENODEV;
d2356284
SW
567
568 if (mmc->part_num == hwpart)
569 return 0;
570
571 if (mmc->part_config == MMCPART_NOAVAILABLE) {
572 printf("Card doesn't support part_switch\n");
d4622df3 573 return -EMEDIUMTYPE;
d2356284
SW
574 }
575
576 ret = mmc_switch_part(dev_num, hwpart);
577 if (ret)
d4622df3 578 return ret;
d2356284
SW
579
580 mmc->part_num = hwpart;
581
582 return 0;
583}
584
585
bc897b1d
LW
586int mmc_switch_part(int dev_num, unsigned int part_num)
587{
588 struct mmc *mmc = find_mmc_device(dev_num);
f866a46d 589 int ret;
bc897b1d
LW
590
591 if (!mmc)
592 return -1;
593
f866a46d
SW
594 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
595 (mmc->part_config & ~PART_ACCESS_MASK)
596 | (part_num & PART_ACCESS_MASK));
f866a46d 597
6dc93e70
PB
598 /*
599 * Set the capacity if the switch succeeded or was intended
600 * to return to representing the raw device.
601 */
602 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0)))
603 ret = mmc_set_capacity(mmc, part_num);
604
605 return ret;
bc897b1d
LW
606}
607
48972d90
TR
608int mmc_getcd(struct mmc *mmc)
609{
610 int cd;
611
612 cd = board_mmc_getcd(mmc);
613
d4e1da4e 614 if (cd < 0) {
93bfd616
PA
615 if (mmc->cfg->ops->getcd)
616 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK
617 else
618 cd = 1;
619 }
48972d90
TR
620
621 return cd;
622}
623
fdbb873e 624static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF
625{
626 struct mmc_cmd cmd;
627 struct mmc_data data;
628
629 /* Switch the frequency */
630 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
631 cmd.resp_type = MMC_RSP_R1;
632 cmd.cmdarg = (mode << 31) | 0xffffff;
633 cmd.cmdarg &= ~(0xf << (group * 4));
634 cmd.cmdarg |= value << (group * 4);
272cc70b
AF
635
636 data.dest = (char *)resp;
637 data.blocksize = 64;
638 data.blocks = 1;
639 data.flags = MMC_DATA_READ;
640
641 return mmc_send_cmd(mmc, &cmd, &data);
642}
643
644
fdbb873e 645static int sd_change_freq(struct mmc *mmc)
272cc70b
AF
646{
647 int err;
648 struct mmc_cmd cmd;
f781dd38
A
649 ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2);
650 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
272cc70b
AF
651 struct mmc_data data;
652 int timeout;
653
654 mmc->card_caps = 0;
655
d52ebf10
TC
656 if (mmc_host_is_spi(mmc))
657 return 0;
658
272cc70b
AF
659 /* Read the SCR to find out if this card supports higher speeds */
660 cmd.cmdidx = MMC_CMD_APP_CMD;
661 cmd.resp_type = MMC_RSP_R1;
662 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
663
664 err = mmc_send_cmd(mmc, &cmd, NULL);
665
666 if (err)
667 return err;
668
669 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
670 cmd.resp_type = MMC_RSP_R1;
671 cmd.cmdarg = 0;
272cc70b
AF
672
673 timeout = 3;
674
675retry_scr:
f781dd38 676 data.dest = (char *)scr;
272cc70b
AF
677 data.blocksize = 8;
678 data.blocks = 1;
679 data.flags = MMC_DATA_READ;
680
681 err = mmc_send_cmd(mmc, &cmd, &data);
682
683 if (err) {
684 if (timeout--)
685 goto retry_scr;
686
687 return err;
688 }
689
4e3d89ba
YK
690 mmc->scr[0] = __be32_to_cpu(scr[0]);
691 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF
692
693 switch ((mmc->scr[0] >> 24) & 0xf) {
694 case 0:
695 mmc->version = SD_VERSION_1_0;
696 break;
697 case 1:
698 mmc->version = SD_VERSION_1_10;
699 break;
700 case 2:
701 mmc->version = SD_VERSION_2;
1741c64d
JC
702 if ((mmc->scr[0] >> 15) & 0x1)
703 mmc->version = SD_VERSION_3;
272cc70b
AF
704 break;
705 default:
706 mmc->version = SD_VERSION_1_0;
707 break;
708 }
709
b44c7083
AS
710 if (mmc->scr[0] & SD_DATA_4BIT)
711 mmc->card_caps |= MMC_MODE_4BIT;
712
272cc70b
AF
713 /* Version 1.0 doesn't support switching */
714 if (mmc->version == SD_VERSION_1_0)
715 return 0;
716
717 timeout = 4;
718 while (timeout--) {
719 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 720 (u8 *)switch_status);
272cc70b
AF
721
722 if (err)
723 return err;
724
725 /* The high-speed function is busy. Try again */
4e3d89ba 726 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF
727 break;
728 }
729
272cc70b 730 /* If high-speed isn't supported, we return */
4e3d89ba 731 if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED))
272cc70b
AF
732 return 0;
733
2c3fbf4c
ML
734 /*
735 * If the host doesn't support SD_HIGHSPEED, do not switch card to
736 * HIGHSPEED mode even if the card support SD_HIGHSPPED.
737 * This can avoid furthur problem when the card runs in different
738 * mode between the host.
739 */
93bfd616
PA
740 if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) &&
741 (mmc->cfg->host_caps & MMC_MODE_HS)))
2c3fbf4c
ML
742 return 0;
743
f781dd38 744 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status);
272cc70b
AF
745
746 if (err)
747 return err;
748
4e3d89ba 749 if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000)
272cc70b
AF
750 mmc->card_caps |= MMC_MODE_HS;
751
752 return 0;
753}
754
755/* frequency bases */
756/* divided by 10 to be nice to platforms without floating point */
5f837c2c 757static const int fbase[] = {
272cc70b
AF
758 10000,
759 100000,
760 1000000,
761 10000000,
762};
763
764/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
765 * to platforms without floating point.
766 */
5f837c2c 767static const int multipliers[] = {
272cc70b
AF
768 0, /* reserved */
769 10,
770 12,
771 13,
772 15,
773 20,
774 25,
775 30,
776 35,
777 40,
778 45,
779 50,
780 55,
781 60,
782 70,
783 80,
784};
785
fdbb873e 786static void mmc_set_ios(struct mmc *mmc)
272cc70b 787{
93bfd616
PA
788 if (mmc->cfg->ops->set_ios)
789 mmc->cfg->ops->set_ios(mmc);
272cc70b
AF
790}
791
792void mmc_set_clock(struct mmc *mmc, uint clock)
793{
93bfd616
PA
794 if (clock > mmc->cfg->f_max)
795 clock = mmc->cfg->f_max;
272cc70b 796
93bfd616
PA
797 if (clock < mmc->cfg->f_min)
798 clock = mmc->cfg->f_min;
272cc70b
AF
799
800 mmc->clock = clock;
801
802 mmc_set_ios(mmc);
803}
804
fdbb873e 805static void mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF
806{
807 mmc->bus_width = width;
808
809 mmc_set_ios(mmc);
810}
811
fdbb873e 812static int mmc_startup(struct mmc *mmc)
272cc70b 813{
f866a46d 814 int err, i;
272cc70b 815 uint mult, freq;
639b7827 816 u64 cmult, csize, capacity;
272cc70b 817 struct mmc_cmd cmd;
8bfa195e
SG
818 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
819 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
5d4fc8d9 820 int timeout = 1000;
0c453bb7 821 bool has_parts = false;
272cc70b 822
d52ebf10
TC
823#ifdef CONFIG_MMC_SPI_CRC_ON
824 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
825 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
826 cmd.resp_type = MMC_RSP_R1;
827 cmd.cmdarg = 1;
d52ebf10
TC
828 err = mmc_send_cmd(mmc, &cmd, NULL);
829
830 if (err)
831 return err;
832 }
833#endif
834
272cc70b 835 /* Put the Card in Identify Mode */
d52ebf10
TC
836 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
837 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF
838 cmd.resp_type = MMC_RSP_R2;
839 cmd.cmdarg = 0;
272cc70b
AF
840
841 err = mmc_send_cmd(mmc, &cmd, NULL);
842
843 if (err)
844 return err;
845
846 memcpy(mmc->cid, cmd.response, 16);
847
848 /*
849 * For MMC cards, set the Relative Address.
850 * For SD cards, get the Relatvie Address.
851 * This also puts the cards into Standby State
852 */
d52ebf10
TC
853 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
854 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
855 cmd.cmdarg = mmc->rca << 16;
856 cmd.resp_type = MMC_RSP_R6;
272cc70b 857
d52ebf10 858 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 859
d52ebf10
TC
860 if (err)
861 return err;
272cc70b 862
d52ebf10
TC
863 if (IS_SD(mmc))
864 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
865 }
272cc70b
AF
866
867 /* Get the Card-Specific Data */
868 cmd.cmdidx = MMC_CMD_SEND_CSD;
869 cmd.resp_type = MMC_RSP_R2;
870 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
871
872 err = mmc_send_cmd(mmc, &cmd, NULL);
873
5d4fc8d9
RR
874 /* Waiting for the ready status */
875 mmc_send_status(mmc, timeout);
876
272cc70b
AF
877 if (err)
878 return err;
879
998be3dd
RV
880 mmc->csd[0] = cmd.response[0];
881 mmc->csd[1] = cmd.response[1];
882 mmc->csd[2] = cmd.response[2];
883 mmc->csd[3] = cmd.response[3];
272cc70b
AF
884
885 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 886 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF
887
888 switch (version) {
889 case 0:
890 mmc->version = MMC_VERSION_1_2;
891 break;
892 case 1:
893 mmc->version = MMC_VERSION_1_4;
894 break;
895 case 2:
896 mmc->version = MMC_VERSION_2_2;
897 break;
898 case 3:
899 mmc->version = MMC_VERSION_3;
900 break;
901 case 4:
902 mmc->version = MMC_VERSION_4;
903 break;
904 default:
905 mmc->version = MMC_VERSION_1_2;
906 break;
907 }
908 }
909
910 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV
911 freq = fbase[(cmd.response[0] & 0x7)];
912 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b
AF
913
914 mmc->tran_speed = freq * mult;
915
ab71188c 916 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 917 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF
918
919 if (IS_SD(mmc))
920 mmc->write_bl_len = mmc->read_bl_len;
921 else
998be3dd 922 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF
923
924 if (mmc->high_capacity) {
925 csize = (mmc->csd[1] & 0x3f) << 16
926 | (mmc->csd[2] & 0xffff0000) >> 16;
927 cmult = 8;
928 } else {
929 csize = (mmc->csd[1] & 0x3ff) << 2
930 | (mmc->csd[2] & 0xc0000000) >> 30;
931 cmult = (mmc->csd[2] & 0x00038000) >> 15;
932 }
933
f866a46d
SW
934 mmc->capacity_user = (csize + 1) << (cmult + 2);
935 mmc->capacity_user *= mmc->read_bl_len;
936 mmc->capacity_boot = 0;
937 mmc->capacity_rpmb = 0;
938 for (i = 0; i < 4; i++)
939 mmc->capacity_gp[i] = 0;
272cc70b 940
8bfa195e
SG
941 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
942 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 943
8bfa195e
SG
944 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
945 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 946
ab71188c
MN
947 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
948 cmd.cmdidx = MMC_CMD_SET_DSR;
949 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
950 cmd.resp_type = MMC_RSP_NONE;
951 if (mmc_send_cmd(mmc, &cmd, NULL))
952 printf("MMC: SET_DSR failed\n");
953 }
954
272cc70b 955 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC
956 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
957 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 958 cmd.resp_type = MMC_RSP_R1;
d52ebf10 959 cmd.cmdarg = mmc->rca << 16;
d52ebf10 960 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 961
d52ebf10
TC
962 if (err)
963 return err;
964 }
272cc70b 965
e6f99a56
LW
966 /*
967 * For SD, its erase group is always one sector
968 */
969 mmc->erase_grp_size = 1;
bc897b1d 970 mmc->part_config = MMCPART_NOAVAILABLE;
d23e2c09
SG
971 if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
972 /* check ext_csd version and capacity */
973 err = mmc_send_ext_csd(mmc, ext_csd);
fdbb873e 974 if (!err && (ext_csd[EXT_CSD_REV] >= 2)) {
639b7827
YS
975 /*
976 * According to the JEDEC Standard, the value of
977 * ext_csd's capacity is valid if the value is more
978 * than 2GB
979 */
0560db18
LW
980 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
981 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
982 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
983 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
8bfa195e 984 capacity *= MMC_MAX_BLOCK_LEN;
b1f1e821 985 if ((capacity >> 20) > 2 * 1024)
f866a46d 986 mmc->capacity_user = capacity;
d23e2c09 987 }
bc897b1d 988
64f4a619
JC
989 switch (ext_csd[EXT_CSD_REV]) {
990 case 1:
991 mmc->version = MMC_VERSION_4_1;
992 break;
993 case 2:
994 mmc->version = MMC_VERSION_4_2;
995 break;
996 case 3:
997 mmc->version = MMC_VERSION_4_3;
998 break;
999 case 5:
1000 mmc->version = MMC_VERSION_4_41;
1001 break;
1002 case 6:
1003 mmc->version = MMC_VERSION_4_5;
1004 break;
edab723b
MN
1005 case 7:
1006 mmc->version = MMC_VERSION_5_0;
1007 break;
64f4a619
JC
1008 }
1009
0c453bb7
DSC
1010 /* store the partition info of emmc */
1011 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1012 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1013 ext_csd[EXT_CSD_BOOT_MULT])
1014 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1015 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)
1016 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1017
1018 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1019
1020 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1021
1022 for (i = 0; i < 4; i++) {
1023 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1024 mmc->capacity_gp[i] = (ext_csd[idx + 2] << 16) +
1025 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1026 mmc->capacity_gp[i] *=
1027 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1028 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
f8e89d67 1029 mmc->capacity_gp[i] <<= 19;
0c453bb7
DSC
1030 if (mmc->capacity_gp[i])
1031 has_parts = true;
1032 }
1033
a7f852b6
DSC
1034 mmc->enh_user_size =
1035 (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) +
1036 (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) +
1037 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1038 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1039 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1040 mmc->enh_user_size <<= 19;
1041 mmc->enh_user_start =
1042 (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) +
1043 (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) +
1044 (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) +
1045 ext_csd[EXT_CSD_ENH_START_ADDR];
1046 if (mmc->high_capacity)
1047 mmc->enh_user_start <<= 9;
1048
e6f99a56 1049 /*
1937e5aa
OM
1050 * Host needs to enable ERASE_GRP_DEF bit if device is
1051 * partitioned. This bit will be lost every time after a reset
1052 * or power off. This will affect erase size.
e6f99a56 1053 */
0c453bb7
DSC
1054 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
1055 EXT_CSD_PARTITION_SETTING_COMPLETED)
1056 has_parts = true;
1937e5aa 1057 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
0c453bb7
DSC
1058 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1059 has_parts = true;
1060 if (has_parts) {
1937e5aa
OM
1061 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1062 EXT_CSD_ERASE_GROUP_DEF, 1);
1063
1064 if (err)
1065 return err;
021a8055
HP
1066 else
1067 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1937e5aa
OM
1068
1069 /* Read out group size from ext_csd */
0560db18 1070 mmc->erase_grp_size =
8bfa195e
SG
1071 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] *
1072 MMC_MAX_BLOCK_LEN * 1024;
d7b29129
MN
1073 /*
1074 * if high capacity and partition setting completed
1075 * SEC_COUNT is valid even if it is smaller than 2 GiB
1076 * JEDEC Standard JESD84-B45, 6.2.4
1077 */
1078 if (mmc->high_capacity &&
1079 (ext_csd[EXT_CSD_PARTITION_SETTING] &
1080 EXT_CSD_PARTITION_SETTING_COMPLETED)) {
1081 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1082 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1083 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1084 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1085 capacity *= MMC_MAX_BLOCK_LEN;
1086 mmc->capacity_user = capacity;
1087 }
8bfa195e 1088 } else {
1937e5aa 1089 /* Calculate the group size from the csd value. */
e6f99a56
LW
1090 int erase_gsz, erase_gmul;
1091 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1092 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1093 mmc->erase_grp_size = (erase_gsz + 1)
1094 * (erase_gmul + 1);
1095 }
d23e2c09
SG
1096 }
1097
f866a46d
SW
1098 err = mmc_set_capacity(mmc, mmc->part_num);
1099 if (err)
1100 return err;
1101
272cc70b
AF
1102 if (IS_SD(mmc))
1103 err = sd_change_freq(mmc);
1104 else
1105 err = mmc_change_freq(mmc);
1106
1107 if (err)
1108 return err;
1109
1110 /* Restrict card's capabilities by what the host can do */
93bfd616 1111 mmc->card_caps &= mmc->cfg->host_caps;
272cc70b
AF
1112
1113 if (IS_SD(mmc)) {
1114 if (mmc->card_caps & MMC_MODE_4BIT) {
1115 cmd.cmdidx = MMC_CMD_APP_CMD;
1116 cmd.resp_type = MMC_RSP_R1;
1117 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF
1118
1119 err = mmc_send_cmd(mmc, &cmd, NULL);
1120 if (err)
1121 return err;
1122
1123 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1124 cmd.resp_type = MMC_RSP_R1;
1125 cmd.cmdarg = 2;
272cc70b
AF
1126 err = mmc_send_cmd(mmc, &cmd, NULL);
1127 if (err)
1128 return err;
1129
1130 mmc_set_bus_width(mmc, 4);
1131 }
1132
1133 if (mmc->card_caps & MMC_MODE_HS)
ad5fd922 1134 mmc->tran_speed = 50000000;
272cc70b 1135 else
ad5fd922 1136 mmc->tran_speed = 25000000;
272cc70b 1137 } else {
7798f6db
AF
1138 int idx;
1139
1140 /* An array of possible bus widths in order of preference */
1141 static unsigned ext_csd_bits[] = {
d22e3d46
JC
1142 EXT_CSD_DDR_BUS_WIDTH_8,
1143 EXT_CSD_DDR_BUS_WIDTH_4,
7798f6db
AF
1144 EXT_CSD_BUS_WIDTH_8,
1145 EXT_CSD_BUS_WIDTH_4,
1146 EXT_CSD_BUS_WIDTH_1,
1147 };
1148
1149 /* An array to map CSD bus widths to host cap bits */
1150 static unsigned ext_to_hostcaps[] = {
786e8f81
AG
1151 [EXT_CSD_DDR_BUS_WIDTH_4] =
1152 MMC_MODE_DDR_52MHz | MMC_MODE_4BIT,
1153 [EXT_CSD_DDR_BUS_WIDTH_8] =
1154 MMC_MODE_DDR_52MHz | MMC_MODE_8BIT,
7798f6db
AF
1155 [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT,
1156 [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT,
1157 };
1158
1159 /* An array to map chosen bus width to an integer */
1160 static unsigned widths[] = {
d22e3d46 1161 8, 4, 8, 4, 1,
7798f6db
AF
1162 };
1163
1164 for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) {
1165 unsigned int extw = ext_csd_bits[idx];
786e8f81 1166 unsigned int caps = ext_to_hostcaps[extw];
7798f6db
AF
1167
1168 /*
786e8f81
AG
1169 * Check to make sure the card and controller support
1170 * these capabilities
7798f6db 1171 */
786e8f81 1172 if ((mmc->card_caps & caps) != caps)
7798f6db
AF
1173 continue;
1174
272cc70b 1175 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
7798f6db 1176 EXT_CSD_BUS_WIDTH, extw);
272cc70b
AF
1177
1178 if (err)
4137894e 1179 continue;
272cc70b 1180
786e8f81 1181 mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0;
7798f6db 1182 mmc_set_bus_width(mmc, widths[idx]);
4137894e
LW
1183
1184 err = mmc_send_ext_csd(mmc, test_csd);
786e8f81
AG
1185
1186 if (err)
1187 continue;
1188
786a27b7 1189 /* Only compare read only fields */
786e8f81
AG
1190 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1191 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1192 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1193 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1194 ext_csd[EXT_CSD_REV]
1195 == test_csd[EXT_CSD_REV] &&
1196 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1197 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1198 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1199 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
4137894e 1200 break;
786e8f81
AG
1201 else
1202 err = SWITCH_ERR;
272cc70b
AF
1203 }
1204
786e8f81
AG
1205 if (err)
1206 return err;
1207
272cc70b
AF
1208 if (mmc->card_caps & MMC_MODE_HS) {
1209 if (mmc->card_caps & MMC_MODE_HS_52MHz)
ad5fd922 1210 mmc->tran_speed = 52000000;
272cc70b 1211 else
ad5fd922
JC
1212 mmc->tran_speed = 26000000;
1213 }
272cc70b
AF
1214 }
1215
ad5fd922
JC
1216 mmc_set_clock(mmc, mmc->tran_speed);
1217
5af8f45c
AG
1218 /* Fix the block length for DDR mode */
1219 if (mmc->ddr_mode) {
1220 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
1221 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
1222 }
1223
272cc70b
AF
1224 /* fill in device description */
1225 mmc->block_dev.lun = 0;
1226 mmc->block_dev.type = 0;
1227 mmc->block_dev.blksz = mmc->read_bl_len;
0472fbfd 1228 mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz);
9b1f942c 1229 mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len);
56196826 1230#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
babce5f6
TH
1231 sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x",
1232 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
1233 (mmc->cid[3] >> 16) & 0xffff);
1234 sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
1235 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
1236 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
1237 (mmc->cid[2] >> 24) & 0xff);
1238 sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
1239 (mmc->cid[2] >> 16) & 0xf);
56196826
PB
1240#else
1241 mmc->block_dev.vendor[0] = 0;
1242 mmc->block_dev.product[0] = 0;
1243 mmc->block_dev.revision[0] = 0;
1244#endif
122efd43 1245#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
272cc70b 1246 init_part(&mmc->block_dev);
122efd43 1247#endif
272cc70b
AF
1248
1249 return 0;
1250}
1251
fdbb873e 1252static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF
1253{
1254 struct mmc_cmd cmd;
1255 int err;
1256
1257 cmd.cmdidx = SD_CMD_SEND_IF_COND;
1258 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 1259 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 1260 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF
1261
1262 err = mmc_send_cmd(mmc, &cmd, NULL);
1263
1264 if (err)
1265 return err;
1266
998be3dd 1267 if ((cmd.response[0] & 0xff) != 0xaa)
272cc70b
AF
1268 return UNUSABLE_ERR;
1269 else
1270 mmc->version = SD_VERSION_2;
1271
1272 return 0;
1273}
1274
93bfd616
PA
1275/* not used any more */
1276int __deprecated mmc_register(struct mmc *mmc)
1277{
1278#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1279 printf("%s is deprecated! use mmc_create() instead.\n", __func__);
1280#endif
1281 return -1;
1282}
1283
1284struct mmc *mmc_create(const struct mmc_config *cfg, void *priv)
272cc70b 1285{
93bfd616
PA
1286 struct mmc *mmc;
1287
1288 /* quick validation */
1289 if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL ||
1290 cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0)
1291 return NULL;
1292
1293 mmc = calloc(1, sizeof(*mmc));
1294 if (mmc == NULL)
1295 return NULL;
1296
1297 mmc->cfg = cfg;
1298 mmc->priv = priv;
1299
1300 /* the following chunk was mmc_register() */
1301
ab71188c
MN
1302 /* Setup dsr related values */
1303 mmc->dsr_imp = 0;
1304 mmc->dsr = 0xffffffff;
272cc70b
AF
1305 /* Setup the universal parts of the block interface just once */
1306 mmc->block_dev.if_type = IF_TYPE_MMC;
1307 mmc->block_dev.dev = cur_dev_num++;
1308 mmc->block_dev.removable = 1;
1309 mmc->block_dev.block_read = mmc_bread;
1310 mmc->block_dev.block_write = mmc_bwrite;
e6f99a56 1311 mmc->block_dev.block_erase = mmc_berase;
272cc70b 1312
93bfd616
PA
1313 /* setup initial part type */
1314 mmc->block_dev.part_type = mmc->cfg->part_type;
272cc70b 1315
93bfd616 1316 INIT_LIST_HEAD(&mmc->link);
272cc70b 1317
93bfd616
PA
1318 list_add_tail(&mmc->link, &mmc_devices);
1319
1320 return mmc;
1321}
1322
1323void mmc_destroy(struct mmc *mmc)
1324{
1325 /* only freeing memory for now */
1326 free(mmc);
272cc70b
AF
1327}
1328
df3fc526 1329#ifdef CONFIG_PARTITIONS
272cc70b
AF
1330block_dev_desc_t *mmc_get_dev(int dev)
1331{
1332 struct mmc *mmc = find_mmc_device(dev);
6bb4b4bc 1333 if (!mmc || mmc_init(mmc))
40242bc3 1334 return NULL;
272cc70b 1335
40242bc3 1336 return &mmc->block_dev;
272cc70b 1337}
df3fc526 1338#endif
272cc70b 1339
95de9ab2
PK
1340/* board-specific MMC power initializations. */
1341__weak void board_mmc_power_init(void)
1342{
1343}
1344
e9550449 1345int mmc_start_init(struct mmc *mmc)
272cc70b 1346{
afd5932b 1347 int err;
272cc70b 1348
ab769f22 1349 /* we pretend there's no card when init is NULL */
93bfd616 1350 if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) {
48972d90 1351 mmc->has_init = 0;
56196826 1352#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 1353 printf("MMC: no card present\n");
56196826 1354#endif
48972d90
TR
1355 return NO_CARD_ERR;
1356 }
1357
bc897b1d
LW
1358 if (mmc->has_init)
1359 return 0;
1360
95de9ab2
PK
1361 board_mmc_power_init();
1362
ab769f22 1363 /* made sure it's not NULL earlier */
93bfd616 1364 err = mmc->cfg->ops->init(mmc);
272cc70b
AF
1365
1366 if (err)
1367 return err;
1368
786e8f81 1369 mmc->ddr_mode = 0;
b86b85e2
IY
1370 mmc_set_bus_width(mmc, 1);
1371 mmc_set_clock(mmc, 1);
1372
272cc70b
AF
1373 /* Reset the Card */
1374 err = mmc_go_idle(mmc);
1375
1376 if (err)
1377 return err;
1378
bc897b1d
LW
1379 /* The internal partition reset to user partition(0) at every CMD0*/
1380 mmc->part_num = 0;
1381
272cc70b 1382 /* Test for SD version 2 */
afd5932b 1383 err = mmc_send_if_cond(mmc);
272cc70b 1384
272cc70b
AF
1385 /* Now try to get the SD card's operating condition */
1386 err = sd_send_op_cond(mmc);
1387
1388 /* If the command timed out, we check for an MMC card */
1389 if (err == TIMEOUT) {
1390 err = mmc_send_op_cond(mmc);
1391
e9550449 1392 if (err && err != IN_PROGRESS) {
56196826 1393#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 1394 printf("Card did not respond to voltage select!\n");
56196826 1395#endif
272cc70b
AF
1396 return UNUSABLE_ERR;
1397 }
1398 }
1399
e9550449
CLC
1400 if (err == IN_PROGRESS)
1401 mmc->init_in_progress = 1;
1402
1403 return err;
1404}
1405
1406static int mmc_complete_init(struct mmc *mmc)
1407{
1408 int err = 0;
1409
1410 if (mmc->op_cond_pending)
1411 err = mmc_complete_op_cond(mmc);
1412
1413 if (!err)
1414 err = mmc_startup(mmc);
bc897b1d
LW
1415 if (err)
1416 mmc->has_init = 0;
1417 else
1418 mmc->has_init = 1;
e9550449
CLC
1419 mmc->init_in_progress = 0;
1420 return err;
1421}
1422
1423int mmc_init(struct mmc *mmc)
1424{
1425 int err = IN_PROGRESS;
d803fea5 1426 unsigned start;
e9550449
CLC
1427
1428 if (mmc->has_init)
1429 return 0;
d803fea5
MZ
1430
1431 start = get_timer(0);
1432
e9550449
CLC
1433 if (!mmc->init_in_progress)
1434 err = mmc_start_init(mmc);
1435
1436 if (!err || err == IN_PROGRESS)
1437 err = mmc_complete_init(mmc);
1438 debug("%s: %d, time %lu\n", __func__, err, get_timer(start));
bc897b1d 1439 return err;
272cc70b
AF
1440}
1441
ab71188c
MN
1442int mmc_set_dsr(struct mmc *mmc, u16 val)
1443{
1444 mmc->dsr = val;
1445 return 0;
1446}
1447
cee9ab7c
JH
1448/* CPU-specific MMC initializations */
1449__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF
1450{
1451 return -1;
1452}
1453
cee9ab7c
JH
1454/* board-specific MMC initializations. */
1455__weak int board_mmc_init(bd_t *bis)
1456{
1457 return -1;
1458}
272cc70b 1459
56196826
PB
1460#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
1461
272cc70b
AF
1462void print_mmc_devices(char separator)
1463{
1464 struct mmc *m;
1465 struct list_head *entry;
1466
1467 list_for_each(entry, &mmc_devices) {
1468 m = list_entry(entry, struct mmc, link);
1469
93bfd616 1470 printf("%s: %d", m->cfg->name, m->block_dev.dev);
272cc70b 1471
e75eaf10
LP
1472 if (entry->next != &mmc_devices) {
1473 printf("%c", separator);
1474 if (separator != '\n')
1475 puts (" ");
1476 }
272cc70b
AF
1477 }
1478
1479 printf("\n");
1480}
1481
56196826
PB
1482#else
1483void print_mmc_devices(char separator) { }
1484#endif
1485
ea6ebe21
LW
1486int get_mmc_num(void)
1487{
1488 return cur_dev_num;
1489}
1490
e9550449
CLC
1491void mmc_set_preinit(struct mmc *mmc, int preinit)
1492{
1493 mmc->preinit = preinit;
1494}
1495
1496static void do_preinit(void)
1497{
1498 struct mmc *m;
1499 struct list_head *entry;
1500
1501 list_for_each(entry, &mmc_devices) {
1502 m = list_entry(entry, struct mmc, link);
1503
1504 if (m->preinit)
1505 mmc_start_init(m);
1506 }
1507}
1508
1509
272cc70b
AF
1510int mmc_initialize(bd_t *bis)
1511{
1512 INIT_LIST_HEAD (&mmc_devices);
1513 cur_dev_num = 0;
1514
1515 if (board_mmc_init(bis) < 0)
1516 cpu_mmc_init(bis);
1517
bb0dc108 1518#ifndef CONFIG_SPL_BUILD
272cc70b 1519 print_mmc_devices(',');
bb0dc108 1520#endif
272cc70b 1521
e9550449 1522 do_preinit();
272cc70b
AF
1523 return 0;
1524}
3690d6d6
A
1525
1526#ifdef CONFIG_SUPPORT_EMMC_BOOT
1527/*
1528 * This function changes the size of boot partition and the size of rpmb
1529 * partition present on EMMC devices.
1530 *
1531 * Input Parameters:
1532 * struct *mmc: pointer for the mmc device strcuture
1533 * bootsize: size of boot partition
1534 * rpmbsize: size of rpmb partition
1535 *
1536 * Returns 0 on success.
1537 */
1538
1539int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
1540 unsigned long rpmbsize)
1541{
1542 int err;
1543 struct mmc_cmd cmd;
1544
1545 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */
1546 cmd.cmdidx = MMC_CMD_RES_MAN;
1547 cmd.resp_type = MMC_RSP_R1b;
1548 cmd.cmdarg = MMC_CMD62_ARG1;
1549
1550 err = mmc_send_cmd(mmc, &cmd, NULL);
1551 if (err) {
1552 debug("mmc_boot_partition_size_change: Error1 = %d\n", err);
1553 return err;
1554 }
1555
1556 /* Boot partition changing mode */
1557 cmd.cmdidx = MMC_CMD_RES_MAN;
1558 cmd.resp_type = MMC_RSP_R1b;
1559 cmd.cmdarg = MMC_CMD62_ARG2;
1560
1561 err = mmc_send_cmd(mmc, &cmd, NULL);
1562 if (err) {
1563 debug("mmc_boot_partition_size_change: Error2 = %d\n", err);
1564 return err;
1565 }
1566 /* boot partition size is multiple of 128KB */
1567 bootsize = (bootsize * 1024) / 128;
1568
1569 /* Arg: boot partition size */
1570 cmd.cmdidx = MMC_CMD_RES_MAN;
1571 cmd.resp_type = MMC_RSP_R1b;
1572 cmd.cmdarg = bootsize;
1573
1574 err = mmc_send_cmd(mmc, &cmd, NULL);
1575 if (err) {
1576 debug("mmc_boot_partition_size_change: Error3 = %d\n", err);
1577 return err;
1578 }
1579 /* RPMB partition size is multiple of 128KB */
1580 rpmbsize = (rpmbsize * 1024) / 128;
1581 /* Arg: RPMB partition size */
1582 cmd.cmdidx = MMC_CMD_RES_MAN;
1583 cmd.resp_type = MMC_RSP_R1b;
1584 cmd.cmdarg = rpmbsize;
1585
1586 err = mmc_send_cmd(mmc, &cmd, NULL);
1587 if (err) {
1588 debug("mmc_boot_partition_size_change: Error4 = %d\n", err);
1589 return err;
1590 }
1591 return 0;
1592}
1593
5a99b9de
TR
1594/*
1595 * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH
1596 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
1597 * and BOOT_MODE.
1598 *
1599 * Returns 0 on success.
1600 */
1601int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode)
1602{
1603 int err;
1604
1605 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH,
1606 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) |
1607 EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) |
1608 EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width));
1609
1610 if (err)
1611 return err;
1612 return 0;
1613}
1614
792970b0
TR
1615/*
1616 * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG)
1617 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
1618 * PARTITION_ACCESS.
1619 *
1620 * Returns 0 on success.
1621 */
1622int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access)
1623{
1624 int err;
1625
1626 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
1627 EXT_CSD_BOOT_ACK(ack) |
1628 EXT_CSD_BOOT_PART_NUM(part_num) |
1629 EXT_CSD_PARTITION_ACCESS(access));
1630
1631 if (err)
1632 return err;
1633 return 0;
1634}
33ace362
TR
1635
1636/*
1637 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
1638 * for enable. Note that this is a write-once field for non-zero values.
1639 *
1640 * Returns 0 on success.
1641 */
1642int mmc_set_rst_n_function(struct mmc *mmc, u8 enable)
1643{
1644 return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION,
1645 enable);
1646}
3690d6d6 1647#endif