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sim: d10v: gut endian logic
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
77cf2ef5
MF		 12016-01-03 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c (sim_open): Update sim_parse_args comment.
4
0cb8d851
MF		 52016-01-03 Mike Frysinger <vapier@gentoo.org>
6
7 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
8 * configure: Regenerate.
9
1ac72f06
MF		 102016-01-02 Mike Frysinger <vapier@gentoo.org>
11
12 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
13 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
14 * configure: Regenerate.
15 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
16
d47f5b30
MF		 172016-01-02 Mike Frysinger <vapier@gentoo.org>
18
19 * dv-tx3904cpu.c (CPU, SD): Delete.
20
e1211e55
MF		 212015-12-30 Mike Frysinger <vapier@gentoo.org>
22
23 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
24 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
25 (sim_store_register): Rename to ...
26 (mips_reg_store): ... this. Delete local cpu var.
27 Update sim_io_eprintf calls.
28 (sim_fetch_register): Rename to ...
29 (mips_reg_fetch): ... this. Delete local cpu var.
30 Update sim_io_eprintf calls.
31
5e744ef8
MF		 322015-12-27 Mike Frysinger <vapier@gentoo.org>
33
34 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
35
1b393626
MF		 362015-12-26 Mike Frysinger <vapier@gentoo.org>
37
38 * config.in, configure: Regenerate.
39
26f8bf63
MF		 402015-12-26 Mike Frysinger <vapier@gentoo.org>
41
42 * interp.c (sim_write, sim_read): Delete.
43 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
44 (load_word): Likewise.
45 * micromips.igen (cache): Likewise.
46 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
47 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
48 do_store_left, do_store_right, do_load_double, do_store_double):
49 Likewise.
50 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
51 (do_prefx): Likewise.
52 * sim-main.c (address_translation, prefetch): Delete.
53 (ifetch32, ifetch16): Delete call to AddressTranslation and set
54 paddr=vaddr.
55 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
56 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
57 (LoadMemory, StoreMemory): Delete CCA arg.
58
ef04e371
MF		 592015-12-24 Mike Frysinger <vapier@gentoo.org>
60
61 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
62 * configure: Regenerated.
63
cb379ede
MF		 642015-12-24 Mike Frysinger <vapier@gentoo.org>
65
66 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
67 * tconfig.h: Delete.
68
26936211
MF		 692015-12-24 Mike Frysinger <vapier@gentoo.org>
70
71 * tconfig.h (SIM_HANDLES_LMA): Delete.
72
84e8e361
MF		 732015-12-24 Mike Frysinger <vapier@gentoo.org>
74
75 * sim-main.h (WITH_WATCHPOINTS): Delete.
76
3cabaf66
MF		 772015-12-24 Mike Frysinger <vapier@gentoo.org>
78
79 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
80
8abe6c66
MF		 812015-12-24 Mike Frysinger <vapier@gentoo.org>
82
83 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
84
1d19cae7
DV		 852015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
86
87 * micromips.igen (process_isa_mode): Fix left shift of negative
88 value.
89
cdf850e9
MF		 902015-11-17 Mike Frysinger <vapier@gentoo.org>
91
92 * sim-main.h (WITH_MODULO_MEMORY): Delete.
93
797eee42
MF		 942015-11-15 Mike Frysinger <vapier@gentoo.org>
95
96 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
97
6e4f085c
MF		 982015-11-14 Mike Frysinger <vapier@gentoo.org>
99
100 * interp.c (sim_close): Rename to ...
101 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
102 sim_io_shutdown.
103 * sim-main.h (mips_sim_close): Declare.
104 (SIM_CLOSE_HOOK): Define.
105
8e394ffc
AB		 1062015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
107 Ali Lown <ali.lown@imgtec.com>
108
109 * Makefile.in (tmp-micromips): New rule.
110 (tmp-mach-multi): Add support for micromips.
111 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
112 that works for both mips64 and micromips64.
113 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
114 micromips32.
115 Add build support for micromips.
116 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
117 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
118 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
119 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
120 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
121 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
122 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
123 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
124 Refactored instruction code to use these functions.
125 * dsp2.igen: Refactored instruction code to use the new functions.
126 * interp.c (decode_coproc): Refactored to work with any instruction
127 encoding.
128 (isa_mode): New variable
129 (RSVD_INSTRUCTION): Changed to 0x00000039.
130 * m16.igen (BREAK16): Refactored instruction to use do_break16.
131 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
132 * micromips.dc: New file.
133 * micromips.igen: New file.
134 * micromips16.dc: New file.
135 * micromipsdsp.igen: New file.
136 * micromipsrun.c: New file.
137 * mips.igen (do_swc1): Changed to work with any instruction encoding.
138 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
139 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
140 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
141 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
142 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
143 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
144 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
145 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
146 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
147 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
148 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
149 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
150 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
151 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
152 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
153 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
154 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
155 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
156 instructions.
157 Refactored instruction code to use these functions.
158 (RSVD): Changed to use new reserved instruction.
159 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
160 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
161 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
162 do_store_double): Added micromips32 and micromips64 models.
163 Added include for micromips.igen and micromipsdsp.igen
164 Add micromips32 and micromips64 models.
165 (DecodeCoproc): Updated to use new macro definition.
166 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
167 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
168 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
169 Refactored instruction code to use these functions.
170 * sim-main.h (CP0_operation): New enum.
171 (DecodeCoproc): Updated macro.
172 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
173 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
174 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
175 ISA_MODE_MICROMIPS): New defines.
176 (sim_state): Add isa_mode field.
177
8d0978fb
MF		 1782015-06-23 Mike Frysinger <vapier@gentoo.org>
179
180 * configure: Regenerate.
181
306f4178
MF		 1822015-06-12 Mike Frysinger <vapier@gentoo.org>
183
184 * configure.ac: Change configure.in to configure.ac.
185 * configure: Regenerate.
186
a3487082
MF		 1872015-06-12 Mike Frysinger <vapier@gentoo.org>
188
189 * configure: Regenerate.
190
29bc024d
MF		 1912015-06-12 Mike Frysinger <vapier@gentoo.org>
192
193 * interp.c [TRACE]: Delete.
194 (TRACE): Change to WITH_TRACE_ANY_P.
195 [!WITH_TRACE_ANY_P] (open_trace): Define.
196 (mips_option_handler, open_trace, sim_close, dotrace):
197 Change defined(TRACE) to WITH_TRACE_ANY_P.
198 (sim_open): Delete TRACE ifdef check.
199 * sim-main.c (load_memory): Delete TRACE ifdef check.
200 (store_memory): Likewise.
201 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
202 [!WITH_TRACE_ANY_P] (dotrace): Define.
203
3ebe2863
MF		 2042015-04-18 Mike Frysinger <vapier@gentoo.org>
205
206 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
207 comments.
208
20bca71d
MF		 2092015-04-18 Mike Frysinger <vapier@gentoo.org>
210
211 * sim-main.h (SIM_CPU): Delete.
212
7e83aa92
MF		 2132015-04-18 Mike Frysinger <vapier@gentoo.org>
214
215 * sim-main.h (sim_cia): Delete.
216
034685f9
MF		 2172015-04-17 Mike Frysinger <vapier@gentoo.org>
218
219 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
220 PU_PC_GET.
221 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
222 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
223 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
224 CIA_SET to CPU_PC_SET.
225 * sim-main.h (CIA_GET, CIA_SET): Delete.
226
78e9aa70
MF		 2272015-04-15 Mike Frysinger <vapier@gentoo.org>
228
229 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
230 * sim-main.h (STATE_CPU): Delete.
231
bf12d44e
MF		 2322015-04-13 Mike Frysinger <vapier@gentoo.org>
233
234 * configure: Regenerate.
235
7bebb329
MF		 2362015-04-13 Mike Frysinger <vapier@gentoo.org>
237
238 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
239 * interp.c (mips_pc_get, mips_pc_set): New functions.
240 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
241 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
242 (sim_pc_get): Delete.
243 * sim-main.h (SIM_CPU): Define.
244 (struct sim_state): Change cpu to an array of pointers.
245 (STATE_CPU): Drop &.
246
8ac57fbd
MF		 2472015-04-13 Mike Frysinger <vapier@gentoo.org>
248
249 * interp.c (mips_option_handler, open_trace, sim_close,
250 sim_write, sim_read, sim_store_register, sim_fetch_register,
251 sim_create_inferior, pr_addr, pr_uword64): Convert old style
252 prototypes.
253 (sim_open): Convert old style prototype. Change casts with
254 sim_write to unsigned char *.
255 (fetch_str): Change null to unsigned char, and change cast to
256 unsigned char *.
257 (sim_monitor): Change c & ch to unsigned char. Change cast to
258 unsigned char *.
259
e787f858
MF		 2602015-04-12 Mike Frysinger <vapier@gentoo.org>
261
262 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
263
122bbfb5
MF		 2642015-04-06 Mike Frysinger <vapier@gentoo.org>
265
266 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
267
0fe84f3f
MF		 2682015-04-01 Mike Frysinger <vapier@gentoo.org>
269
270 * tconfig.h (SIM_HAVE_PROFILE): Delete.
271
aadc9410
MF		 2722015-03-31 Mike Frysinger <vapier@gentoo.org>
273
274 * config.in, configure: Regenerate.
275
05f53ed6
MF		 2762015-03-24 Mike Frysinger <vapier@gentoo.org>
277
278 * interp.c (sim_pc_get): New function.
279
c0931f26
MF		 2802015-03-24 Mike Frysinger <vapier@gentoo.org>
281
282 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
283 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
284
30452bbe
MF		 2852015-03-24 Mike Frysinger <vapier@gentoo.org>
286
287 * configure: Regenerate.
288
64dd13df
MF		 2892015-03-23 Mike Frysinger <vapier@gentoo.org>
290
291 * configure: Regenerate.
292
49cd1634
MF		 2932015-03-23 Mike Frysinger <vapier@gentoo.org>
294
295 * configure: Regenerate.
296 * configure.ac (mips_extra_objs): Delete.
297 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
298 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
299
3649cb06
MF		 3002015-03-23 Mike Frysinger <vapier@gentoo.org>
301
302 * configure: Regenerate.
303 * configure.ac: Delete sim_hw checks for dv-sockser.
304
ae7d0cac
MF		 3052015-03-16 Mike Frysinger <vapier@gentoo.org>
306
307 * config.in, configure: Regenerate.
308 * tconfig.in: Rename file ...
309 * tconfig.h: ... here.
310
8406bb59
MF		 3112015-03-15 Mike Frysinger <vapier@gentoo.org>
312
313 * tconfig.in: Delete includes.
314 [HAVE_DV_SOCKSER]: Delete.
315
465fb143
MF		 3162015-03-14 Mike Frysinger <vapier@gentoo.org>
317
318 * Makefile.in (SIM_RUN_OBJS): Delete.
319
5cddc23a
MF		 3202015-03-14 Mike Frysinger <vapier@gentoo.org>
321
322 * configure.ac (AC_CHECK_HEADERS): Delete.
323 * aclocal.m4, configure: Regenerate.
324
2974be62
AM		 3252014-08-19 Alan Modra <amodra@gmail.com>
326
327 * configure: Regenerate.
328
faa743bb
RM		 3292014-08-15 Roland McGrath <mcgrathr@google.com>
330
331 * configure: Regenerate.
332 * config.in: Regenerate.
333
1a8a700e
MF		 3342014-03-04 Mike Frysinger <vapier@gentoo.org>
335
336 * configure: Regenerate.
337
bf3d9781
AM		 3382013-09-23 Alan Modra <amodra@gmail.com>
339
340 * configure: Regenerate.
341
31e6ad7d
MF		 3422013-06-03 Mike Frysinger <vapier@gentoo.org>
343
344 * aclocal.m4, configure: Regenerate.
345
d3685d60
TT		 3462013-05-10 Freddie Chopin <freddie_chopin@op.pl>
347
348 * configure: Rebuild.
349
1517bd27
MF		 3502013-03-26 Mike Frysinger <vapier@gentoo.org>
351
352 * configure: Regenerate.
353
3be31516
JS		 3542013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
355
356 * configure.ac: Address use of dv-sockser.o.
357 * tconfig.in: Conditionalize use of dv_sockser_install.
358 * configure: Regenerated.
359 * config.in: Regenerated.
360
37cb8f8e
SE		 3612012-10-04 Chao-ying Fu <fu@mips.com>
362 Steve Ellcey <sellcey@mips.com>
363
364 * mips/mips3264r2.igen (rdhwr): New.
365
87c8644f
JS		 3662012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
367
368 * configure.ac: Always link against dv-sockser.o.
369 * configure: Regenerate.
370
5f3ef9d0
JB		 3712012-06-15 Joel Brobecker <brobecker@adacore.com>
372
373 * config.in, configure: Regenerate.
374
a6ff997c
NC		 3752012-05-18 Nick Clifton <nickc@redhat.com>
376
377 PR 14072
378 * interp.c: Include config.h before system header files.
379
2232061b
MF		 3802012-03-24 Mike Frysinger <vapier@gentoo.org>
381
382 * aclocal.m4, config.in, configure: Regenerate.
383
db2e4d67
MF		 3842011-12-03 Mike Frysinger <vapier@gentoo.org>
385
386 * aclocal.m4: New file.
387 * configure: Regenerate.
388
4399a56b
MF		 3892011-10-19 Mike Frysinger <vapier@gentoo.org>
390
391 * configure: Regenerate after common/acinclude.m4 update.
392
9c082ca8
MF		 3932011-10-17 Mike Frysinger <vapier@gentoo.org>
394
395 * configure.ac: Change include to common/acinclude.m4.
396
6ffe910a
MF		 3972011-10-17 Mike Frysinger <vapier@gentoo.org>
398
399 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
400 call. Replace common.m4 include with SIM_AC_COMMON.
401 * configure: Regenerate.
402
31b28250
HPN		 4032011-07-08 Hans-Peter Nilsson <hp@axis.com>
404
3faa01e3
HPN		 405 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
406 $(SIM_EXTRA_DEPS).
407 (tmp-mach-multi): Exit early when igen fails.
31b28250 408
2419798b
MF		 4092011-07-05 Mike Frysinger <vapier@gentoo.org>
410
411 * interp.c (sim_do_command): Delete.
412
d79fe0d6
MF		 4132011-02-14 Mike Frysinger <vapier@gentoo.org>
414
415 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
416 (tx3904sio_fifo_reset): Likewise.
417 * interp.c (sim_monitor): Likewise.
418
5558e7e6
MF		 4192010-04-14 Mike Frysinger <vapier@gentoo.org>
420
421 * interp.c (sim_write): Add const to buffer arg.
422
35aafff4
JB		 4232010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
424
425 * interp.c: Don't include sysdep.h
426
3725885a
RW		 4272010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
428
429 * configure: Regenerate.
430
d6416cdc
RW		 4312009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
432
81ecdfbb
RW		 433 * config.in: Regenerate.
434 * configure: Likewise.
435
d6416cdc
RW		 436 * configure: Regenerate.
437
b5bd9624
HPN		 4382008-07-11 Hans-Peter Nilsson <hp@axis.com>
439
440 * configure: Regenerate to track ../common/common.m4 changes.
441 * config.in: Ditto.
442
6efef468 4432008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 444 Daniel Jacobowitz <dan@codesourcery.com>
445 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 446
447 * configure: Regenerate.
448
60dc88db
RS		 4492007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
450
451 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
452 that unconditionally allows fmt_ps.
453 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
454 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
455 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
456 filter from 64,f to 32,f.
457 (PREFX): Change filter from 64 to 32.
458 (LDXC1, LUXC1): Provide separate mips32r2 implementations
459 that use do_load_double instead of do_load. Make both LUXC1
460 versions unpredictable if SizeFGR () != 64.
461 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
462 instead of do_store. Remove unused variable. Make both SUXC1
463 versions unpredictable if SizeFGR () != 64.
464
599ca73e
RS		 4652007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
466
467 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
468 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
469 shifts for that case.
470
2525df03
NC		 4712007-09-04 Nick Clifton <nickc@redhat.com>
472
473 * interp.c (options enum): Add OPTION_INFO_MEMORY.
474 (display_mem_info): New static variable.
475 (mips_option_handler): Handle OPTION_INFO_MEMORY.
476 (mips_options): Add info-memory and memory-info.
477 (sim_open): After processing the command line and board
478 specification, check display_mem_info. If it is set then
479 call the real handler for the --memory-info command line
480 switch.
481
35ee6e1e
JB		 4822007-08-24 Joel Brobecker <brobecker@adacore.com>
483
484 * configure.ac: Change license of multi-run.c to GPL version 3.
485 * configure: Regenerate.
486
d5fb0879
RS		 4872007-06-28 Richard Sandiford <richard@codesourcery.com>
488
489 * configure.ac, configure: Revert last patch.
490
2a2ce21b
RS		 4912007-06-26 Richard Sandiford <richard@codesourcery.com>
492
493 * configure.ac (sim_mipsisa3264_configs): New variable.
494 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
495 every configuration support all four targets, using the triplet to
496 determine the default.
497 * configure: Regenerate.
498
efdcccc9
RS		 4992007-06-25 Richard Sandiford <richard@codesourcery.com>
500
0a7692b2 501 * Makefile.in (m16run.o): New rule.
efdcccc9 502
f532a356
TS		 5032007-05-15 Thiemo Seufer <ths@mips.com>
504
505 * mips3264r2.igen (DSHD): Fix compile warning.
506
bfe9c90b
TS		 5072007-05-14 Thiemo Seufer <ths@mips.com>
508
509 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
510 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
511 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
512 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
513 for mips32r2.
514
53f4826b
TS		 5152007-03-01 Thiemo Seufer <ths@mips.com>
516
517 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
518 and mips64.
519
8bf3ddc8
TS		 5202007-02-20 Thiemo Seufer <ths@mips.com>
521
522 * dsp.igen: Update copyright notice.
523 * dsp2.igen: Fix copyright notice.
524
8b082fb1 5252007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 526 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 527
528 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
529 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
530 Add dsp2 to sim_igen_machine.
531 * configure: Regenerate.
532 * dsp.igen (do_ph_op): Add MUL support when op = 2.
533 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
534 (mulq_rs.ph): Use do_ph_mulq.
535 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
536 * mips.igen: Add dsp2 model and include dsp2.igen.
537 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
538 for *mips32r2, *mips64r2, *dsp.
539 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
540 for *mips32r2, *mips64r2, *dsp2.
541 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
542
b1004875 5432007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 544 Nigel Stephens <nigel@mips.com>
b1004875
TS		 545
546 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
547 jumps with hazard barrier.
548
f8df4c77 5492007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 550 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 551
552 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
553 after each call to sim_io_write.
554
b1004875 5552007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 556 Nigel Stephens <nigel@mips.com>
b1004875
TS		 557
558 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
559 supported by this simulator.
07802d98
TS		 560 (decode_coproc): Recognise additional CP0 Config registers
561 correctly.
562
14fb6c5a 5632007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 564 Nigel Stephens <nigel@mips.com>
565 David Ung <davidu@mips.com>
14fb6c5a
TS		 566
567 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
568 uninterpreted formats. If fmt is one of the uninterpreted types
569 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
570 fmt_word, and fmt_uninterpreted_64 like fmt_long.
571 (store_fpr): When writing an invalid odd register, set the
572 matching even register to fmt_unknown, not the following register.
573 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
574 the the memory window at offset 0 set by --memory-size command
575 line option.
576 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
577 point register.
578 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
579 register.
580 (sim_monitor): When returning the memory size to the MIPS
581 application, use the value in STATE_MEM_SIZE, not an arbitrary
582 hardcoded value.
583 (cop_lw): Don' mess around with FPR_STATE, just pass
584 fmt_uninterpreted_32 to StoreFPR.
585 (cop_sw): Similarly.
586 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
587 (cop_sd): Similarly.
588 * mips.igen (not_word_value): Single version for mips32, mips64
589 and mips16.
590
c8847145 5912007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 592 Nigel Stephens <nigel@mips.com>
c8847145
TS		 593
594 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
595 MBytes.
596
4b5d35ee
TS		 5972007-02-17 Thiemo Seufer <ths@mips.com>
598
599 * configure.ac (mips*-sde-elf*): Move in front of generic machine
600 configuration.
601 * configure: Regenerate.
602
3669427c
TS		 6032007-02-17 Thiemo Seufer <ths@mips.com>
604
605 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
606 Add mdmx to sim_igen_machine.
607 (mipsisa64*-*-*): Likewise. Remove dsp.
608 (mipsisa32*-*-*): Remove dsp.
609 * configure: Regenerate.
610
109ad085
TS		 6112007-02-13 Thiemo Seufer <ths@mips.com>
612
613 * configure.ac: Add mips*-sde-elf* target.
614 * configure: Regenerate.
615
921d7ad3
HPN		 6162006-12-21 Hans-Peter Nilsson <hp@axis.com>
617
618 * acconfig.h: Remove.
619 * config.in, configure: Regenerate.
620
02f97da7
TS		 6212006-11-07 Thiemo Seufer <ths@mips.com>
622
623 * dsp.igen (do_w_op): Fix compiler warning.
624
2d2733fc 6252006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 626 David Ung <davidu@mips.com>
2d2733fc
TS		 627
628 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
629 sim_igen_machine.
630 * configure: Regenerate.
631 * mips.igen (model): Add smartmips.
632 (MADDU): Increment ACX if carry.
633 (do_mult): Clear ACX.
634 (ROR,RORV): Add smartmips.
72f4393d 635 (include): Include smartmips.igen.
2d2733fc
TS		 636 * sim-main.h (ACX): Set to REGISTERS[89].
637 * smartmips.igen: New file.
638
d85c3a10 6392006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 640 David Ung <davidu@mips.com>
d85c3a10
TS		 641
642 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
643 mips3264r2.igen. Add missing dependency rules.
644 * m16e.igen: Support for mips16e save/restore instructions.
645
e85e3205
RE		 6462006-06-13 Richard Earnshaw <rearnsha@arm.com>
647
648 * configure: Regenerated.
649
2f0122dc
DJ		 6502006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
651
652 * configure: Regenerated.
653
20e95c23
DJ		 6542006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
655
656 * configure: Regenerated.
657
69088b17
CF		 6582006-05-15 Chao-ying Fu <fu@mips.com>
659
660 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
661
0275de4e
NC		 6622006-04-18 Nick Clifton <nickc@redhat.com>
663
664 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
665 statement.
666
b3a3ffef
HPN		 6672006-03-29 Hans-Peter Nilsson <hp@axis.com>
668
669 * configure: Regenerate.
670
40a5538e
CF		 6712005-12-14 Chao-ying Fu <fu@mips.com>
672
673 * Makefile.in (SIM_OBJS): Add dsp.o.
674 (dsp.o): New dependency.
675 (IGEN_INCLUDE): Add dsp.igen.
676 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
677 mipsisa64*-*-*): Add dsp to sim_igen_machine.
678 * configure: Regenerate.
679 * mips.igen: Add dsp model and include dsp.igen.
680 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
681 because these instructions are extended in DSP ASE.
682 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
683 adding 6 DSP accumulator registers and 1 DSP control register.
684 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
685 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
686 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
687 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
688 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
689 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
690 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
691 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
692 DSPCR_CCOND_SMASK): New define.
693 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
694 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
695
21d14896
ILT		 6962005-07-08 Ian Lance Taylor <ian@airs.com>
697
698 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
699
b16d63da 7002005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 701 Nigel Stephens <nigel@mips.com>
702
703 * mips.igen: New mips16e model and include m16e.igen.
704 (check_u64): Add mips16e tag.
705 * m16e.igen: New file for MIPS16e instructions.
706 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
707 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
708 models.
709 * configure: Regenerate.
b16d63da 710
e70cb6cd 7112005-05-26 David Ung <davidu@mips.com>
72f4393d 712
e70cb6cd
CD		 713 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
714 tags to all instructions which are applicable to the new ISAs.
715 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
716 vr.igen.
717 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 718 instructions.
e70cb6cd
CD		 719 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
720 to mips.igen.
721 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
722 * configure: Regenerate.
72f4393d 723
2b193c4a
MK		 7242005-03-23 Mark Kettenis <kettenis@gnu.org>
725
726 * configure: Regenerate.
727
35695fd6
AC		 7282005-01-14 Andrew Cagney <cagney@gnu.org>
729
730 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
731 explicit call to AC_CONFIG_HEADER.
732 * configure: Regenerate.
733
f0569246
AC		 7342005-01-12 Andrew Cagney <cagney@gnu.org>
735
736 * configure.ac: Update to use ../common/common.m4.
737 * configure: Re-generate.
738
38f48d72
AC		 7392005-01-11 Andrew Cagney <cagney@localhost.localdomain>
740
741 * configure: Regenerated to track ../common/aclocal.m4 changes.
742
b7026657
AC		 7432005-01-07 Andrew Cagney <cagney@gnu.org>
744
745 * configure.ac: Rename configure.in, require autoconf 2.59.
746 * configure: Re-generate.
747
379832de
HPN		 7482004-12-08 Hans-Peter Nilsson <hp@axis.com>
749
750 * configure: Regenerate for ../common/aclocal.m4 update.
751
cd62154c 7522004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 753
cd62154c
AC		 754 Committed by Andrew Cagney.
755 * m16.igen (CMP, CMPI): Fix assembler.
756
e5da76ec
CD		 7572004-08-18 Chris Demetriou <cgd@broadcom.com>
758
759 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
760 * configure: Regenerate.
761
139181c8
CD		 7622004-06-25 Chris Demetriou <cgd@broadcom.com>
763
764 * configure.in (sim_m16_machine): Include mipsIII.
765 * configure: Regenerate.
766
1a27f959
CD		 7672004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
768
72f4393d 769 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 770 from COP0_BADVADDR.
771 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
772
5dbb7b5a
CD		 7732004-04-10 Chris Demetriou <cgd@broadcom.com>
774
775 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
776
14234056
CD		 7772004-04-09 Chris Demetriou <cgd@broadcom.com>
778
779 * mips.igen (check_fmt): Remove.
780 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
781 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
782 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
783 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
784 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
785 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
786 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
787 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
788 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
789 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
790
c6f9085c
CD		 7912004-04-09 Chris Demetriou <cgd@broadcom.com>
792
793 * sb1.igen (check_sbx): New function.
794 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
795
11d66e66 7962004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 797 Richard Sandiford <rsandifo@redhat.com>
798
799 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
800 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
801 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
802 separate implementations for mipsIV and mipsV. Use new macros to
803 determine whether the restrictions apply.
804
b3208fb8
CD		 8052004-01-19 Chris Demetriou <cgd@broadcom.com>
806
807 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
808 (check_mult_hilo): Improve comments.
809 (check_div_hilo): Likewise. Also, fork off a new version
810 to handle mips32/mips64 (since there are no hazards to check
811 in MIPS32/MIPS64).
812
9a1d84fb
CD		 8132003-06-17 Richard Sandiford <rsandifo@redhat.com>
814
815 * mips.igen (do_dmultx): Fix check for negative operands.
816
ae451ac6
ILT		 8172003-05-16 Ian Lance Taylor <ian@airs.com>
818
819 * Makefile.in (SHELL): Make sure this is defined.
820 (various): Use $(SHELL) whenever we invoke move-if-change.
821
dd69d292
CD		 8222003-05-03 Chris Demetriou <cgd@broadcom.com>
823
824 * cp1.c: Tweak attribution slightly.
825 * cp1.h: Likewise.
826 * mdmx.c: Likewise.
827 * mdmx.igen: Likewise.
828 * mips3d.igen: Likewise.
829 * sb1.igen: Likewise.
830
bcd0068e
CD		 8312003-04-15 Richard Sandiford <rsandifo@redhat.com>
832
833 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
834 unsigned operands.
835
6b4a8935
AC		 8362003-02-27 Andrew Cagney <cagney@redhat.com>
837
601da316
AC		 838 * interp.c (sim_open): Rename _bfd to bfd.
839 (sim_create_inferior): Ditto.
6b4a8935 840
d29e330f
CD		 8412003-01-14 Chris Demetriou <cgd@broadcom.com>
842
843 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
844
a2353a08
CD		 8452003-01-14 Chris Demetriou <cgd@broadcom.com>
846
847 * mips.igen (EI, DI): Remove.
848
80551777
CD		 8492003-01-05 Richard Sandiford <rsandifo@redhat.com>
850
851 * Makefile.in (tmp-run-multi): Fix mips16 filter.
852
4c54fc26
CD		 8532003-01-04 Richard Sandiford <rsandifo@redhat.com>
854 Andrew Cagney <ac131313@redhat.com>
855 Gavin Romig-Koch <gavin@redhat.com>
856 Graydon Hoare <graydon@redhat.com>
857 Aldy Hernandez <aldyh@redhat.com>
858 Dave Brolley <brolley@redhat.com>
859 Chris Demetriou <cgd@broadcom.com>
860
861 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
862 (sim_mach_default): New variable.
863 (mips64vr-*-*, mips64vrel-*-*): New configurations.
864 Add a new simulator generator, MULTI.
865 * configure: Regenerate.
866 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
867 (multi-run.o): New dependency.
868 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
869 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
870 (tmp-multi): Combine them.
871 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
872 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
873 (distclean-extra): New rule.
874 * sim-main.h: Include bfd.h.
875 (MIPS_MACH): New macro.
876 * mips.igen (vr4120, vr5400, vr5500): New models.
877 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
878 * vr.igen: Replace with new version.
879
e6c674b8
CD		 8802003-01-04 Chris Demetriou <cgd@broadcom.com>
881
882 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
883 * configure: Regenerate.
884
28f50ac8
CD		 8852002-12-31 Chris Demetriou <cgd@broadcom.com>
886
887 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
888 * mips.igen: Remove all invocations of check_branch_bug and
889 mark_branch_bug.
890
5071ffe6
CD		 8912002-12-16 Chris Demetriou <cgd@broadcom.com>
892
72f4393d 893 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 894
06e7837e
CD		 8952002-07-30 Chris Demetriou <cgd@broadcom.com>
896
897 * mips.igen (do_load_double, do_store_double): New functions.
898 (LDC1, SDC1): Rename to...
899 (LDC1b, SDC1b): respectively.
900 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
901
2265c243
MS		 9022002-07-29 Michael Snyder <msnyder@redhat.com>
903
904 * cp1.c (fp_recip2): Modify initialization expression so that
905 GCC will recognize it as constant.
906
a2f8b4f3
CD		 9072002-06-18 Chris Demetriou <cgd@broadcom.com>
908
909 * mdmx.c (SD_): Delete.
910 (Unpredictable): Re-define, for now, to directly invoke
911 unpredictable_action().
912 (mdmx_acc_op): Fix error in .ob immediate handling.
913
b4b6c939
AC		 9142002-06-18 Andrew Cagney <cagney@redhat.com>
915
916 * interp.c (sim_firmware_command): Initialize `address'.
917
c8cca39f
AC		 9182002-06-16 Andrew Cagney <ac131313@redhat.com>
919
920 * configure: Regenerated to track ../common/aclocal.m4 changes.
921
e7e81181 9222002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 923 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 924
925 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
926 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
927 * mips.igen: Include mips3d.igen.
928 (mips3d): New model name for MIPS-3D ASE instructions.
929 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 930 instructions.
e7e81181
CD		 931 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
932 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
933 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
934 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
935 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
936 (RSquareRoot1, RSquareRoot2): New macros.
937 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
938 (fp_rsqrt2): New functions.
939 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
940 * configure: Regenerate.
941
3a2b820e 9422002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 943 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 944
945 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
946 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
947 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
948 (convert): Note that this function is not used for paired-single
949 format conversions.
950 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
951 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
952 (check_fmt_p): Enable paired-single support.
953 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
954 (PUU.PS): New instructions.
955 (CVT.S.fmt): Don't use this instruction for paired-single format
956 destinations.
957 * sim-main.h (FP_formats): New value 'fmt_ps.'
958 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
959 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
960
d18ea9c2
CD		 9612002-06-12 Chris Demetriou <cgd@broadcom.com>
962
963 * mips.igen: Fix formatting of function calls in
964 many FP operations.
965
95fd5cee
CD		 9662002-06-12 Chris Demetriou <cgd@broadcom.com>
967
968 * mips.igen (MOVN, MOVZ): Trace result.
969 (TNEI): Print "tnei" as the opcode name in traces.
970 (CEIL.W): Add disassembly string for traces.
971 (RSQRT.fmt): Make location of disassembly string consistent
972 with other instructions.
973
4f0d55ae
CD		 9742002-06-12 Chris Demetriou <cgd@broadcom.com>
975
976 * mips.igen (X): Delete unused function.
977
3c25f8c7
AC		 9782002-06-08 Andrew Cagney <cagney@redhat.com>
979
980 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
981
f3c08b7e 9822002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 983 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 984
985 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
986 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
987 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
988 (fp_nmsub): New prototypes.
989 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
990 (NegMultiplySub): New defines.
991 * mips.igen (RSQRT.fmt): Use RSquareRoot().
992 (MADD.D, MADD.S): Replace with...
993 (MADD.fmt): New instruction.
994 (MSUB.D, MSUB.S): Replace with...
995 (MSUB.fmt): New instruction.
996 (NMADD.D, NMADD.S): Replace with...
997 (NMADD.fmt): New instruction.
998 (NMSUB.D, MSUB.S): Replace with...
999 (NMSUB.fmt): New instruction.
1000
52714ff9 10012002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1002 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1003
1004 * cp1.c: Fix more comment spelling and formatting.
1005 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1006 (denorm_mode): New function.
1007 (fpu_unary, fpu_binary): Round results after operation, collect
1008 status from rounding operations, and update the FCSR.
1009 (convert): Collect status from integer conversions and rounding
1010 operations, and update the FCSR. Adjust NaN values that result
1011 from conversions. Convert to use sim_io_eprintf rather than
1012 fprintf, and remove some debugging code.
1013 * cp1.h (fenr_FS): New define.
1014
577d8c4b
CD		 10152002-06-07 Chris Demetriou <cgd@broadcom.com>
1016
1017 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1018 rounding mode to sim FP rounding mode flag conversion code into...
1019 (rounding_mode): New function.
1020
196496ed
CD		 10212002-06-07 Chris Demetriou <cgd@broadcom.com>
1022
1023 * cp1.c: Clean up formatting of a few comments.
1024 (value_fpr): Reformat switch statement.
1025
cfe9ea23 10262002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1027 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1028
1029 * cp1.h: New file.
1030 * sim-main.h: Include cp1.h.
1031 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1032 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1033 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1034 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1035 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1036 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1037 * cp1.c: Don't include sim-fpu.h; already included by
1038 sim-main.h. Clean up formatting of some comments.
1039 (NaN, Equal, Less): Remove.
1040 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1041 (fp_cmp): New functions.
1042 * mips.igen (do_c_cond_fmt): Remove.
1043 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1044 Compare. Add result tracing.
1045 (CxC1): Remove, replace with...
1046 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1047 (DMxC1): Remove, replace with...
1048 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1049 (MxC1): Remove, replace with...
1050 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1051
ee7254b0
CD		 10522002-06-04 Chris Demetriou <cgd@broadcom.com>
1053
1054 * sim-main.h (FGRIDX): Remove, replace all uses with...
1055 (FGR_BASE): New macro.
1056 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1057 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1058 (NR_FGR, FGR): Likewise.
1059 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1060 * mips.igen: Likewise.
1061
d3eb724f
CD		 10622002-06-04 Chris Demetriou <cgd@broadcom.com>
1063
1064 * cp1.c: Add an FSF Copyright notice to this file.
1065
ba46ddd0 10662002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1067 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1068
1069 * cp1.c (Infinity): Remove.
1070 * sim-main.h (Infinity): Likewise.
1071
1072 * cp1.c (fp_unary, fp_binary): New functions.
1073 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1074 (fp_sqrt): New functions, implemented in terms of the above.
1075 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1076 (Recip, SquareRoot): Remove (replaced by functions above).
1077 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1078 (fp_recip, fp_sqrt): New prototypes.
1079 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1080 (Recip, SquareRoot): Replace prototypes with #defines which
1081 invoke the functions above.
72f4393d 1082
18d8a52d
CD		 10832002-06-03 Chris Demetriou <cgd@broadcom.com>
1084
1085 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1086 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1087 file, remove PARAMS from prototypes.
1088 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1089 simulator state arguments.
1090 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1091 pass simulator state arguments.
1092 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1093 (store_fpr, convert): Remove 'sd' argument.
1094 (value_fpr): Likewise. Convert to use 'SD' instead.
1095
0f154cbd
CD		 10962002-06-03 Chris Demetriou <cgd@broadcom.com>
1097
1098 * cp1.c (Min, Max): Remove #if 0'd functions.
1099 * sim-main.h (Min, Max): Remove.
1100
e80fc152
CD		 11012002-06-03 Chris Demetriou <cgd@broadcom.com>
1102
1103 * cp1.c: fix formatting of switch case and default labels.
1104 * interp.c: Likewise.
1105 * sim-main.c: Likewise.
1106
bad673a9
CD		 11072002-06-03 Chris Demetriou <cgd@broadcom.com>
1108
1109 * cp1.c: Clean up comments which describe FP formats.
1110 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1111
7cbea089 11122002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1113 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1114
1115 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1116 Broadcom SiByte SB-1 processor configurations.
1117 * configure: Regenerate.
1118 * sb1.igen: New file.
1119 * mips.igen: Include sb1.igen.
1120 (sb1): New model.
1121 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1122 * mdmx.igen: Add "sb1" model to all appropriate functions and
1123 instructions.
1124 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1125 (ob_func, ob_acc): Reference the above.
1126 (qh_acc): Adjust to keep the same size as ob_acc.
1127 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1128 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1129
909daa82
CD		 11302002-06-03 Chris Demetriou <cgd@broadcom.com>
1131
1132 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1133
f4f1b9f1 11342002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1135 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1136
1137 * mips.igen (mdmx): New (pseudo-)model.
1138 * mdmx.c, mdmx.igen: New files.
1139 * Makefile.in (SIM_OBJS): Add mdmx.o.
1140 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1141 New typedefs.
1142 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1143 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1144 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1145 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1146 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1147 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1148 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1149 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1150 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1151 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1152 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1153 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1154 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1155 (qh_fmtsel): New macros.
1156 (_sim_cpu): New member "acc".
1157 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1158 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1159
5accf1ff
CD		 11602002-05-01 Chris Demetriou <cgd@broadcom.com>
1161
1162 * interp.c: Use 'deprecated' rather than 'depreciated.'
1163 * sim-main.h: Likewise.
1164
402586aa
CD		 11652002-05-01 Chris Demetriou <cgd@broadcom.com>
1166
1167 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1168 which wouldn't compile anyway.
1169 * sim-main.h (unpredictable_action): New function prototype.
1170 (Unpredictable): Define to call igen function unpredictable().
1171 (NotWordValue): New macro to call igen function not_word_value().
1172 (UndefinedResult): Remove.
1173 * interp.c (undefined_result): Remove.
1174 (unpredictable_action): New function.
1175 * mips.igen (not_word_value, unpredictable): New functions.
1176 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1177 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1178 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1179 NotWordValue() to check for unpredictable inputs, then
1180 Unpredictable() to handle them.
1181
c9b9995a
CD		 11822002-02-24 Chris Demetriou <cgd@broadcom.com>
1183
1184 * mips.igen: Fix formatting of calls to Unpredictable().
1185
e1015982
AC		 11862002-04-20 Andrew Cagney <ac131313@redhat.com>
1187
1188 * interp.c (sim_open): Revert previous change.
1189
b882a66b
AO		 11902002-04-18 Alexandre Oliva <aoliva@redhat.com>
1191
1192 * interp.c (sim_open): Disable chunk of code that wrote code in
1193 vector table entries.
1194
c429b7dd
CD		 11952002-03-19 Chris Demetriou <cgd@broadcom.com>
1196
1197 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1198 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1199 unused definitions.
1200
37d146fa
CD		 12012002-03-19 Chris Demetriou <cgd@broadcom.com>
1202
1203 * cp1.c: Fix many formatting issues.
1204
07892c0b
CD		 12052002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1206
1207 * cp1.c (fpu_format_name): New function to replace...
1208 (DOFMT): This. Delete, and update all callers.
1209 (fpu_rounding_mode_name): New function to replace...
1210 (RMMODE): This. Delete, and update all callers.
1211
487f79b7
CD		 12122002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1213
1214 * interp.c: Move FPU support routines from here to...
1215 * cp1.c: Here. New file.
1216 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1217 (cp1.o): New target.
1218
1e799e28
CD		 12192002-03-12 Chris Demetriou <cgd@broadcom.com>
1220
1221 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1222 * mips.igen (mips32, mips64): New models, add to all instructions
1223 and functions as appropriate.
1224 (loadstore_ea, check_u64): New variant for model mips64.
1225 (check_fmt_p): New variant for models mipsV and mips64, remove
1226 mipsV model marking fro other variant.
1227 (SLL) Rename to...
1228 (SLLa) this.
1229 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1230 for mips32 and mips64.
1231 (DCLO, DCLZ): New instructions for mips64.
1232
82f728db
CD		 12332002-03-07 Chris Demetriou <cgd@broadcom.com>
1234
1235 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1236 immediate or code as a hex value with the "%#lx" format.
1237 (ANDI): Likewise, and fix printed instruction name.
1238
b96e7ef1
CD		 12392002-03-05 Chris Demetriou <cgd@broadcom.com>
1240
1241 * sim-main.h (UndefinedResult, Unpredictable): New macros
1242 which currently do nothing.
1243
d35d4f70
CD		 12442002-03-05 Chris Demetriou <cgd@broadcom.com>
1245
1246 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1247 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1248 (status_CU3): New definitions.
1249
1250 * sim-main.h (ExceptionCause): Add new values for MIPS32
1251 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1252 for DebugBreakPoint and NMIReset to note their status in
1253 MIPS32 and MIPS64.
1254 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1255 (SignalExceptionCacheErr): New exception macros.
1256
3ad6f714
CD		 12572002-03-05 Chris Demetriou <cgd@broadcom.com>
1258
1259 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1260 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1261 is always enabled.
1262 (SignalExceptionCoProcessorUnusable): Take as argument the
1263 unusable coprocessor number.
1264
86b77b47
CD		 12652002-03-05 Chris Demetriou <cgd@broadcom.com>
1266
1267 * mips.igen: Fix formatting of all SignalException calls.
1268
97a88e93 12692002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1270
1271 * sim-main.h (SIGNEXTEND): Remove.
1272
97a88e93 12732002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1274
1275 * mips.igen: Remove gencode comment from top of file, fix
1276 spelling in another comment.
1277
97a88e93 12782002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1279
1280 * mips.igen (check_fmt, check_fmt_p): New functions to check
1281 whether specific floating point formats are usable.
1282 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1283 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1284 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1285 Use the new functions.
1286 (do_c_cond_fmt): Remove format checks...
1287 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1288
97a88e93 12892002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1290
1291 * mips.igen: Fix formatting of check_fpu calls.
1292
41774c9d
CD		 12932002-03-03 Chris Demetriou <cgd@broadcom.com>
1294
1295 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1296
4a0bd876
CD		 12972002-03-03 Chris Demetriou <cgd@broadcom.com>
1298
1299 * mips.igen: Remove whitespace at end of lines.
1300
09297648
CD		 13012002-03-02 Chris Demetriou <cgd@broadcom.com>
1302
1303 * mips.igen (loadstore_ea): New function to do effective
1304 address calculations.
1305 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1306 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1307 CACHE): Use loadstore_ea to do effective address computations.
1308
043b7057
CD		 13092002-03-02 Chris Demetriou <cgd@broadcom.com>
1310
1311 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1312 * mips.igen (LL, CxC1, MxC1): Likewise.
1313
c1e8ada4
CD		 13142002-03-02 Chris Demetriou <cgd@broadcom.com>
1315
1316 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1317 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1318 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1319 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1320 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1321 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1322 Don't split opcode fields by hand, use the opcode field values
1323 provided by igen.
1324
3e1dca16
CD		 13252002-03-01 Chris Demetriou <cgd@broadcom.com>
1326
1327 * mips.igen (do_divu): Fix spacing.
1328
1329 * mips.igen (do_dsllv): Move to be right before DSLLV,
1330 to match the rest of the do_<shift> functions.
1331
fff8d27d
CD		 13322002-03-01 Chris Demetriou <cgd@broadcom.com>
1333
1334 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1335 DSRL32, do_dsrlv): Trace inputs and results.
1336
0d3e762b
CD		 13372002-03-01 Chris Demetriou <cgd@broadcom.com>
1338
1339 * mips.igen (CACHE): Provide instruction-printing string.
1340
1341 * interp.c (signal_exception): Comment tokens after #endif.
1342
eb5fcf93
CD		 13432002-02-28 Chris Demetriou <cgd@broadcom.com>
1344
1345 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1346 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1347 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1348 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1349 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1350 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1351 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1352 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1353
bb22bd7d
CD		 13542002-02-28 Chris Demetriou <cgd@broadcom.com>
1355
1356 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1357 instruction-printing string.
1358 (LWU): Use '64' as the filter flag.
1359
91a177cf
CD		 13602002-02-28 Chris Demetriou <cgd@broadcom.com>
1361
1362 * mips.igen (SDXC1): Fix instruction-printing string.
1363
387f484a
CD		 13642002-02-28 Chris Demetriou <cgd@broadcom.com>
1365
1366 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1367 filter flags "32,f".
1368
3d81f391
CD		 13692002-02-27 Chris Demetriou <cgd@broadcom.com>
1370
1371 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1372 as the filter flag.
1373
af5107af
CD		 13742002-02-27 Chris Demetriou <cgd@broadcom.com>
1375
1376 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1377 add a comma) so that it more closely match the MIPS ISA
1378 documentation opcode partitioning.
1379 (PREF): Put useful names on opcode fields, and include
1380 instruction-printing string.
1381
ca971540
CD		 13822002-02-27 Chris Demetriou <cgd@broadcom.com>
1383
1384 * mips.igen (check_u64): New function which in the future will
1385 check whether 64-bit instructions are usable and signal an
1386 exception if not. Currently a no-op.
1387 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1388 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1389 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1390 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1391
1392 * mips.igen (check_fpu): New function which in the future will
1393 check whether FPU instructions are usable and signal an exception
1394 if not. Currently a no-op.
1395 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1396 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1397 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1398 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1399 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1400 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1401 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1402 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1403
1c47a468
CD		 14042002-02-27 Chris Demetriou <cgd@broadcom.com>
1405
1406 * mips.igen (do_load_left, do_load_right): Move to be immediately
1407 following do_load.
1408 (do_store_left, do_store_right): Move to be immediately following
1409 do_store.
1410
603a98e7
CD		 14112002-02-27 Chris Demetriou <cgd@broadcom.com>
1412
1413 * mips.igen (mipsV): New model name. Also, add it to
1414 all instructions and functions where it is appropriate.
1415
c5d00cc7
CD		 14162002-02-18 Chris Demetriou <cgd@broadcom.com>
1417
1418 * mips.igen: For all functions and instructions, list model
1419 names that support that instruction one per line.
1420
074e9cb8
CD		 14212002-02-11 Chris Demetriou <cgd@broadcom.com>
1422
1423 * mips.igen: Add some additional comments about supported
1424 models, and about which instructions go where.
1425 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1426 order as is used in the rest of the file.
1427
9805e229
CD		 14282002-02-11 Chris Demetriou <cgd@broadcom.com>
1429
1430 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1431 indicating that ALU32_END or ALU64_END are there to check
1432 for overflow.
1433 (DADD): Likewise, but also remove previous comment about
1434 overflow checking.
1435
f701dad2
CD		 14362002-02-10 Chris Demetriou <cgd@broadcom.com>
1437
1438 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1439 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1440 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1441 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1442 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1443 fields (i.e., add and move commas) so that they more closely
1444 match the MIPS ISA documentation opcode partitioning.
1445
14462002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1447
72f4393d
L		 1448 * mips.igen (ADDI): Print immediate value.
1449 (BREAK): Print code.
1450 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1451 (SLL): Print "nop" specially, and don't run the code
1452 that does the shift for the "nop" case.
20ae0098 1453
9e52972e
FF		 14542001-11-17 Fred Fish <fnf@redhat.com>
1455
1456 * sim-main.h (float_operation): Move enum declaration outside
1457 of _sim_cpu struct declaration.
1458
c0efbca4
JB		 14592001-04-12 Jim Blandy <jimb@redhat.com>
1460
1461 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1462 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1463 set of the FCSR.
1464 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1465 PENDING_FILL, and you can get the intended effect gracefully by
1466 calling PENDING_SCHED directly.
1467
fb891446
BE		 14682001-02-23 Ben Elliston <bje@redhat.com>
1469
1470 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1471 already defined elsewhere.
1472
8030f857
BE		 14732001-02-19 Ben Elliston <bje@redhat.com>
1474
1475 * sim-main.h (sim_monitor): Return an int.
1476 * interp.c (sim_monitor): Add return values.
1477 (signal_exception): Handle error conditions from sim_monitor.
1478
56b48a7a
CD		 14792001-02-08 Ben Elliston <bje@redhat.com>
1480
1481 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1482 (store_memory): Likewise, pass cia to sim_core_write*.
1483
d3ee60d9
FCE		 14842000-10-19 Frank Ch. Eigler <fche@redhat.com>
1485
1486 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1487 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1488
071da002
AC		 1489Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1490
1491 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1492 * Makefile.in: Don't delete *.igen when cleaning directory.
1493
a28c02cd
AC		 1494Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1495
1496 * m16.igen (break): Call SignalException not sim_engine_halt.
1497
80ee11fa
AC		 1498Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 From Jason Eckhardt:
1501 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1502
673388c0
AC		 1503Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1504
1505 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1506
4c0deff4
NC		 15072000-05-24 Michael Hayes <mhayes@cygnus.com>
1508
1509 * mips.igen (do_dmultx): Fix typo.
1510
eb2d80b4
AC		 1511Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1512
1513 * configure: Regenerated to track ../common/aclocal.m4 changes.
1514
dd37a34b
AC		 1515Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1518
4c0deff4
NC		 15192000-04-12 Frank Ch. Eigler <fche@redhat.com>
1520
1521 * sim-main.h (GPR_CLEAR): Define macro.
1522
e30db738
AC		 1523Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1524
1525 * interp.c (decode_coproc): Output long using %lx and not %s.
1526
cb7450ea
FCE		 15272000-03-21 Frank Ch. Eigler <fche@redhat.com>
1528
1529 * interp.c (sim_open): Sort & extend dummy memory regions for
1530 --board=jmr3904 for eCos.
1531
a3027dd7
FCE		 15322000-03-02 Frank Ch. Eigler <fche@redhat.com>
1533
1534 * configure: Regenerated.
1535
1536Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1537
1538 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1539 calls, conditional on the simulator being in verbose mode.
1540
dfcd3bfb
JM		 1541Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1542
1543 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1544 cache don't get ReservedInstruction traps.
1545
c2d11a7d
JM		 15461999-11-29 Mark Salter <msalter@cygnus.com>
1547
1548 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1549 to clear status bits in sdisr register. This is how the hardware works.
1550
1551 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1552 being used by cygmon.
1553
4ce44c66
JM		 15541999-11-11 Andrew Haley <aph@cygnus.com>
1555
1556 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1557 instructions.
1558
cff3e48b
JM		 1559Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1560
1561 * mips.igen (MULT): Correct previous mis-applied patch.
1562
d4f3574e
SS		 1563Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1564
1565 * mips.igen (delayslot32): Handle sequence like
1566 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1567 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1568 (MULT): Actually pass the third register...
1569
15701999-09-03 Mark Salter <msalter@cygnus.com>
1571
1572 * interp.c (sim_open): Added more memory aliases for additional
1573 hardware being touched by cygmon on jmr3904 board.
1574
1575Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1576
1577 * configure: Regenerated to track ../common/aclocal.m4 changes.
1578
a0b3c4fd
JM		 1579Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1580
1581 * interp.c (sim_store_register): Handle case where client - GDB -
1582 specifies that a 4 byte register is 8 bytes in size.
1583 (sim_fetch_register): Ditto.
72f4393d 1584
adf40b2e
JM		 15851999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1586
1587 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1588 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1589 (idt_monitor_base): Base address for IDT monitor traps.
1590 (pmon_monitor_base): Ditto for PMON.
1591 (lsipmon_monitor_base): Ditto for LSI PMON.
1592 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1593 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1594 (sim_firmware_command): New function.
1595 (mips_option_handler): Call it for OPTION_FIRMWARE.
1596 (sim_open): Allocate memory for idt_monitor region. If "--board"
1597 option was given, add no monitor by default. Add BREAK hooks only if
1598 monitors are also there.
72f4393d 1599
43e526b9
JM		 1600Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1601
1602 * interp.c (sim_monitor): Flush output before reading input.
1603
1604Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1605
1606 * tconfig.in (SIM_HANDLES_LMA): Always define.
1607
1608Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1609
1610 From Mark Salter <msalter@cygnus.com>:
1611 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1612 (sim_open): Add setup for BSP board.
1613
9846de1b
JM		 1614Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1615
1616 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1617 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1618 them as unimplemented.
1619
cd0fc7c3
SS		 16201999-05-08 Felix Lee <flee@cygnus.com>
1621
1622 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1623
7a292a7a
SS		 16241999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1625
1626 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1627
1628Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1629
1630 * configure.in: Any mips64vr5*-*-* target should have
1631 -DTARGET_ENABLE_FR=1.
1632 (default_endian): Any mips64vr*el-*-* target should default to
1633 LITTLE_ENDIAN.
1634 * configure: Re-generate.
1635
16361999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1637
1638 * mips.igen (ldl): Extend from _16_, not 32.
1639
1640Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1641
1642 * interp.c (sim_store_register): Force registers written to by GDB
1643 into an un-interpreted state.
1644
c906108c
SS		 16451999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1646
1647 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1648 CPU, start periodic background I/O polls.
72f4393d 1649 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1650
16511998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1652
1653 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1654
c906108c
SS		 1655Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1656
1657 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1658 case statement.
1659
16601998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1661
1662 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1663 (load_word): Call SIM_CORE_SIGNAL hook on error.
1664 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1665 starting. For exception dispatching, pass PC instead of NULL_CIA.
1666 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1667 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1668 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1669 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1670 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1671 * mips.igen (*): Replace memory-related SignalException* calls
1672 with references to SIM_CORE_SIGNAL hook.
72f4393d 1673
c906108c
SS		 1674 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1675 fix.
1676 * sim-main.c (*): Minor warning cleanups.
72f4393d 1677
c906108c
SS		 16781998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1679
1680 * m16.igen (DADDIU5): Correct type-o.
1681
1682Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1683
1684 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1685 variables.
1686
1687Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1688
1689 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1690 to include path.
1691 (interp.o): Add dependency on itable.h
1692 (oengine.c, gencode): Delete remaining references.
1693 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1694
c906108c 16951998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1696
c906108c
SS		 1697 * vr4run.c: New.
1698 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1699 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1700 tmp-run-hack) : New.
1701 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1702 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1703 Drop the "64" qualifier to get the HACK generator working.
1704 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1705 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1706 qualifier to get the hack generator working.
1707 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1708 (DSLL): Use do_dsll.
1709 (DSLLV): Use do_dsllv.
1710 (DSRA): Use do_dsra.
1711 (DSRL): Use do_dsrl.
1712 (DSRLV): Use do_dsrlv.
1713 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1714 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1715 get the HACK generator working.
1716 (MACC) Rename to get the HACK generator working.
1717 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1718
c906108c
SS		 17191998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1720
1721 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1722 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1723
c906108c
SS		 17241998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1725
1726 * mips/interp.c (DEBUG): Cleanups.
1727
17281998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1729
1730 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1731 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1732
c906108c
SS		 17331998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1734
1735 * interp.c (sim_close): Uninstall modules.
1736
1737Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1738
1739 * sim-main.h, interp.c (sim_monitor): Change to global
1740 function.
1741
1742Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1743
1744 * configure.in (vr4100): Only include vr4100 instructions in
1745 simulator.
1746 * configure: Re-generate.
1747 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1748
1749Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1750
1751 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1752 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1753 true alternative.
1754
1755 * configure.in (sim_default_gen, sim_use_gen): Replace with
1756 sim_gen.
1757 (--enable-sim-igen): Delete config option. Always using IGEN.
1758 * configure: Re-generate.
72f4393d 1759
c906108c
SS		 1760 * Makefile.in (gencode): Kill, kill, kill.
1761 * gencode.c: Ditto.
72f4393d 1762
c906108c
SS		 1763Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1764
1765 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1766 bit mips16 igen simulator.
1767 * configure: Re-generate.
1768
1769 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1770 as part of vr4100 ISA.
1771 * vr.igen: Mark all instructions as 64 bit only.
1772
1773Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1774
1775 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1776 Pacify GCC.
1777
1778Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1779
1780 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1781 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1782 * configure: Re-generate.
1783
1784 * m16.igen (BREAK): Define breakpoint instruction.
1785 (JALX32): Mark instruction as mips16 and not r3900.
1786 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1787
1788 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1789
1790Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1791
1792 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1793 insn as a debug breakpoint.
1794
1795 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1796 pending.slot_size.
1797 (PENDING_SCHED): Clean up trace statement.
1798 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1799 (PENDING_FILL): Delay write by only one cycle.
1800 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1801
1802 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1803 of pending writes.
1804 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1805 32 & 64.
1806 (pending_tick): Move incrementing of index to FOR statement.
1807 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1808
c906108c
SS		 1809 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1810 build simulator.
1811 * configure: Re-generate.
72f4393d 1812
c906108c
SS		 1813 * interp.c (sim_engine_run OLD): Delete explicit call to
1814 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1815
c906108c
SS		 1816Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1817
1818 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1819 interrupt level number to match changed SignalExceptionInterrupt
1820 macro.
1821
1822Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1823
1824 * interp.c: #include "itable.h" if WITH_IGEN.
1825 (get_insn_name): New function.
1826 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1827 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1828
1829Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1830
1831 * configure: Rebuilt to inhale new common/aclocal.m4.
1832
1833Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1834
1835 * dv-tx3904sio.c: Include sim-assert.h.
1836
1837Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1838
1839 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1840 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1841 Reorganize target-specific sim-hardware checks.
1842 * configure: rebuilt.
1843 * interp.c (sim_open): For tx39 target boards, set
1844 OPERATING_ENVIRONMENT, add tx3904sio devices.
1845 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1846 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1847
c906108c
SS		 1848 * dv-tx3904irc.c: Compiler warning clean-up.
1849 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1850 frequent hw-trace messages.
1851
1852Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1855
1856Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1857
1858 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1859
1860 * vr.igen: New file.
1861 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1862 * mips.igen: Define vr4100 model. Include vr.igen.
1863Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1864
1865 * mips.igen (check_mf_hilo): Correct check.
1866
1867Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1868
1869 * sim-main.h (interrupt_event): Add prototype.
1870
1871 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1872 register_ptr, register_value.
1873 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1874
1875 * sim-main.h (tracefh): Make extern.
1876
1877Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1878
1879 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1880 Reduce unnecessarily high timer event frequency.
c906108c 1881 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1882
c906108c
SS		 1883Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1884
1885 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1886 to allay warnings.
1887 (interrupt_event): Made non-static.
72f4393d 1888
c906108c
SS		 1889 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1890 interchange of configuration values for external vs. internal
1891 clock dividers.
72f4393d 1892
c906108c
SS		 1893Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1894
72f4393d 1895 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1896 simulator-reserved break instructions.
1897 * gencode.c (build_instruction): Ditto.
1898 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1899 reserved instructions now use exception vector, rather
c906108c
SS		 1900 than halting sim.
1901 * sim-main.h: Moved magic constants to here.
1902
1903Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1904
1905 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1906 register upon non-zero interrupt event level, clear upon zero
1907 event value.
1908 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1909 by passing zero event value.
1910 (*_io_{read,write}_buffer): Endianness fixes.
1911 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1912 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1913
1914 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1915 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1916
c906108c
SS		 1917Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1918
72f4393d 1919 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1920 and BigEndianCPU.
1921
1922Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1923
1924 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1925 parts.
1926 * configure: Update.
1927
1928Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1929
1930 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1931 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1932 * configure.in: Include tx3904tmr in hw_device list.
1933 * configure: Rebuilt.
1934 * interp.c (sim_open): Instantiate three timer instances.
1935 Fix address typo of tx3904irc instance.
1936
1937Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1938
1939 * interp.c (signal_exception): SystemCall exception now uses
1940 the exception vector.
1941
1942Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1943
1944 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1945 to allay warnings.
1946
1947Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1950
1951Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1954
1955 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1956 sim-main.h. Declare a struct hw_descriptor instead of struct
1957 hw_device_descriptor.
1958
1959Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1960
1961 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1962 right bits and then re-align left hand bytes to correct byte
1963 lanes. Fix incorrect computation in do_store_left when loading
1964 bytes from second word.
1965
1966Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1969 * interp.c (sim_open): Only create a device tree when HW is
1970 enabled.
1971
1972 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1973 * interp.c (signal_exception): Ditto.
1974
1975Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1976
1977 * gencode.c: Mark BEGEZALL as LIKELY.
1978
1979Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1980
1981 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1982 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1983
c906108c
SS		 1984Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1985
1986 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1987 modules. Recognize TX39 target with "mips*tx39" pattern.
1988 * configure: Rebuilt.
1989 * sim-main.h (*): Added many macros defining bits in
1990 TX39 control registers.
1991 (SignalInterrupt): Send actual PC instead of NULL.
1992 (SignalNMIReset): New exception type.
1993 * interp.c (board): New variable for future use to identify
1994 a particular board being simulated.
1995 (mips_option_handler,mips_options): Added "--board" option.
1996 (interrupt_event): Send actual PC.
1997 (sim_open): Make memory layout conditional on board setting.
1998 (signal_exception): Initial implementation of hardware interrupt
1999 handling. Accept another break instruction variant for simulator
2000 exit.
2001 (decode_coproc): Implement RFE instruction for TX39.
2002 (mips.igen): Decode RFE instruction as such.
2003 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2004 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2005 bbegin to implement memory map.
2006 * dv-tx3904cpu.c: New file.
2007 * dv-tx3904irc.c: New file.
2008
2009Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2010
2011 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2012
2013Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2014
2015 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2016 with calls to check_div_hilo.
2017
2018Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2019
2020 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2021 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2022 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2023 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2024 with calls to check_mult_hilo.
2025 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2026 with calls to check_div_hilo.
2027
2028Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2029
2030 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2031 Document a replacement.
2032
2033Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2034
2035 * interp.c (sim_monitor): Make mon_printf work.
2036
2037Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2038
2039 * sim-main.h (INSN_NAME): New arg `cpu'.
2040
2041Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2042
72f4393d 2043 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2044
2045Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2046
2047 * configure: Regenerated to track ../common/aclocal.m4 changes.
2048 * config.in: Ditto.
2049
2050Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2051
2052 * acconfig.h: New file.
2053 * configure.in: Reverted change of Apr 24; use sinclude again.
2054
2055Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2056
2057 * configure: Regenerated to track ../common/aclocal.m4 changes.
2058 * config.in: Ditto.
2059
2060Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2061
2062 * configure.in: Don't call sinclude.
2063
2064Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2065
2066 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2067
2068Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2069
2070 * mips.igen (ERET): Implement.
2071
2072 * interp.c (decode_coproc): Return sign-extended EPC.
2073
2074 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2075
2076 * interp.c (signal_exception): Do not ignore Trap.
2077 (signal_exception): On TRAP, restart at exception address.
2078 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2079 (signal_exception): Update.
2080 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2081 so that TRAP instructions are caught.
2082
2083Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2084
2085 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2086 contains HI/LO access history.
2087 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2088 (HIACCESS, LOACCESS): Delete, replace with
2089 (HIHISTORY, LOHISTORY): New macros.
2090 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2091
c906108c
SS		 2092 * gencode.c (build_instruction): Do not generate checks for
2093 correct HI/LO register usage.
2094
2095 * interp.c (old_engine_run): Delete checks for correct HI/LO
2096 register usage.
2097
2098 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2099 check_mf_cycles): New functions.
2100 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2101 do_divu, domultx, do_mult, do_multu): Use.
2102
2103 * tx.igen ("madd", "maddu"): Use.
72f4393d 2104
c906108c
SS		 2105Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2106
2107 * mips.igen (DSRAV): Use function do_dsrav.
2108 (SRAV): Use new function do_srav.
2109
2110 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2111 (B): Sign extend 11 bit immediate.
2112 (EXT-B*): Shift 16 bit immediate left by 1.
2113 (ADDIU*): Don't sign extend immediate value.
2114
2115Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2116
2117 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2118
2119 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2120 functions.
2121
2122 * mips.igen (delayslot32, nullify_next_insn): New functions.
2123 (m16.igen): Always include.
2124 (do_*): Add more tracing.
2125
2126 * m16.igen (delayslot16): Add NIA argument, could be called by a
2127 32 bit MIPS16 instruction.
72f4393d 2128
c906108c
SS		 2129 * interp.c (ifetch16): Move function from here.
2130 * sim-main.c (ifetch16): To here.
72f4393d 2131
c906108c
SS		 2132 * sim-main.c (ifetch16, ifetch32): Update to match current
2133 implementations of LH, LW.
2134 (signal_exception): Don't print out incorrect hex value of illegal
2135 instruction.
2136
2137Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2138
2139 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2140 instruction.
2141
2142 * m16.igen: Implement MIPS16 instructions.
72f4393d 2143
c906108c
SS		 2144 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2145 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2146 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2147 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2148 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2149 bodies of corresponding code from 32 bit insn to these. Also used
2150 by MIPS16 versions of functions.
72f4393d 2151
c906108c
SS		 2152 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2153 (IMEM16): Drop NR argument from macro.
2154
2155Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2156
2157 * Makefile.in (SIM_OBJS): Add sim-main.o.
2158
2159 * sim-main.h (address_translation, load_memory, store_memory,
2160 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2161 as INLINE_SIM_MAIN.
2162 (pr_addr, pr_uword64): Declare.
2163 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2164
c906108c
SS		 2165 * interp.c (address_translation, load_memory, store_memory,
2166 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2167 from here.
2168 * sim-main.c: To here. Fix compilation problems.
72f4393d 2169
c906108c
SS		 2170 * configure.in: Enable inlining.
2171 * configure: Re-config.
2172
2173Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2174
2175 * configure: Regenerated to track ../common/aclocal.m4 changes.
2176
2177Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2178
2179 * mips.igen: Include tx.igen.
2180 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2181 * tx.igen: New file, contains MADD and MADDU.
2182
2183 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2184 the hardwired constant `7'.
2185 (store_memory): Ditto.
2186 (LOADDRMASK): Move definition to sim-main.h.
2187
2188 mips.igen (MTC0): Enable for r3900.
2189 (ADDU): Add trace.
2190
2191 mips.igen (do_load_byte): Delete.
2192 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2193 do_store_right): New functions.
2194 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2195
2196 configure.in: Let the tx39 use igen again.
2197 configure: Update.
72f4393d 2198
c906108c
SS		 2199Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2202 not an address sized quantity. Return zero for cache sizes.
2203
2204Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2205
2206 * mips.igen (r3900): r3900 does not support 64 bit integer
2207 operations.
2208
2209Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2210
2211 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2212 than igen one.
2213 * configure : Rebuild.
72f4393d 2214
c906108c
SS		 2215Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2216
2217 * configure: Regenerated to track ../common/aclocal.m4 changes.
2218
2219Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2220
2221 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2222
2223Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2224
2225 * configure: Regenerated to track ../common/aclocal.m4 changes.
2226 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2227
2228Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * configure: Regenerated to track ../common/aclocal.m4 changes.
2231
2232Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2233
2234 * interp.c (Max, Min): Comment out functions. Not yet used.
2235
2236Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * configure: Regenerated to track ../common/aclocal.m4 changes.
2239
2240Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2241
2242 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2243 configurable settings for stand-alone simulator.
72f4393d 2244
c906108c 2245 * configure.in: Added X11 search, just in case.
72f4393d 2246
c906108c
SS		 2247 * configure: Regenerated.
2248
2249Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2250
2251 * interp.c (sim_write, sim_read, load_memory, store_memory):
2252 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2253
2254Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2255
2256 * sim-main.h (GETFCC): Return an unsigned value.
2257
2258Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2261 (DADD): Result destination is RD not RT.
2262
2263Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2264
2265 * sim-main.h (HIACCESS, LOACCESS): Always define.
2266
2267 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2268
2269 * interp.c (sim_info): Delete.
2270
2271Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2272
2273 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2274 (mips_option_handler): New argument `cpu'.
2275 (sim_open): Update call to sim_add_option_table.
2276
2277Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2278
2279 * mips.igen (CxC1): Add tracing.
2280
2281Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2282
2283 * sim-main.h (Max, Min): Declare.
2284
2285 * interp.c (Max, Min): New functions.
2286
2287 * mips.igen (BC1): Add tracing.
72f4393d 2288
c906108c 2289Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2290
c906108c 2291 * interp.c Added memory map for stack in vr4100
72f4393d 2292
c906108c
SS		 2293Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2294
2295 * interp.c (load_memory): Add missing "break"'s.
2296
2297Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2298
2299 * interp.c (sim_store_register, sim_fetch_register): Pass in
2300 length parameter. Return -1.
2301
2302Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2303
2304 * interp.c: Added hardware init hook, fixed warnings.
2305
2306Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2307
2308 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2309
2310Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2311
2312 * interp.c (ifetch16): New function.
2313
2314 * sim-main.h (IMEM32): Rename IMEM.
2315 (IMEM16_IMMED): Define.
2316 (IMEM16): Define.
2317 (DELAY_SLOT): Update.
72f4393d 2318
c906108c 2319 * m16run.c (sim_engine_run): New file.
72f4393d 2320
c906108c
SS		 2321 * m16.igen: All instructions except LB.
2322 (LB): Call do_load_byte.
2323 * mips.igen (do_load_byte): New function.
2324 (LB): Call do_load_byte.
2325
2326 * mips.igen: Move spec for insn bit size and high bit from here.
2327 * Makefile.in (tmp-igen, tmp-m16): To here.
2328
2329 * m16.dc: New file, decode mips16 instructions.
2330
2331 * Makefile.in (SIM_NO_ALL): Define.
2332 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2333
2334Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2335
2336 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2337 point unit to 32 bit registers.
2338 * configure: Re-generate.
2339
2340Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * configure.in (sim_use_gen): Make IGEN the default simulator
2343 generator for generic 32 and 64 bit mips targets.
2344 * configure: Re-generate.
2345
2346Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2347
2348 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2349 bitsize.
2350
2351 * interp.c (sim_fetch_register, sim_store_register): Read/write
2352 FGR from correct location.
2353 (sim_open): Set size of FGR's according to
2354 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2355
c906108c
SS		 2356 * sim-main.h (FGR): Store floating point registers in a separate
2357 array.
2358
2359Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2360
2361 * configure: Regenerated to track ../common/aclocal.m4 changes.
2362
2363Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2364
2365 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2366
2367 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2368
2369 * interp.c (pending_tick): New function. Deliver pending writes.
2370
2371 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2372 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2373 it can handle mixed sized quantites and single bits.
72f4393d 2374
c906108c
SS		 2375Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2376
2377 * interp.c (oengine.h): Do not include when building with IGEN.
2378 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2379 (sim_info): Ditto for PROCESSOR_64BIT.
2380 (sim_monitor): Replace ut_reg with unsigned_word.
2381 (*): Ditto for t_reg.
2382 (LOADDRMASK): Define.
2383 (sim_open): Remove defunct check that host FP is IEEE compliant,
2384 using software to emulate floating point.
2385 (value_fpr, ...): Always compile, was conditional on HASFPU.
2386
2387Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2388
2389 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2390 size.
2391
2392 * interp.c (SD, CPU): Define.
2393 (mips_option_handler): Set flags in each CPU.
2394 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2395 (sim_close): Do not clear STATE, deleted anyway.
2396 (sim_write, sim_read): Assume CPU zero's vm should be used for
2397 data transfers.
2398 (sim_create_inferior): Set the PC for all processors.
2399 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2400 argument.
2401 (mips16_entry): Pass correct nr of args to store_word, load_word.
2402 (ColdReset): Cold reset all cpu's.
2403 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2404 (sim_monitor, load_memory, store_memory, signal_exception): Use
2405 `CPU' instead of STATE_CPU.
2406
2407
2408 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2409 SD or CPU_.
72f4393d 2410
c906108c
SS		 2411 * sim-main.h (signal_exception): Add sim_cpu arg.
2412 (SignalException*): Pass both SD and CPU to signal_exception.
2413 * interp.c (signal_exception): Update.
72f4393d 2414
c906108c
SS		 2415 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2416 Ditto
2417 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2418 address_translation): Ditto
2419 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2420
c906108c
SS		 2421Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2422
2423 * configure: Regenerated to track ../common/aclocal.m4 changes.
2424
2425Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2426
2427 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2428
72f4393d 2429 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2430
2431 * sim-main.h (CPU_CIA): Delete.
2432 (SET_CIA, GET_CIA): Define
2433
2434Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2437 regiser.
2438
2439 * configure.in (default_endian): Configure a big-endian simulator
2440 by default.
2441 * configure: Re-generate.
72f4393d 2442
c906108c
SS		 2443Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2444
2445 * configure: Regenerated to track ../common/aclocal.m4 changes.
2446
2447Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2448
2449 * interp.c (sim_monitor): Handle Densan monitor outbyte
2450 and inbyte functions.
2451
24521997-12-29 Felix Lee <flee@cygnus.com>
2453
2454 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2455
2456Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2457
2458 * Makefile.in (tmp-igen): Arrange for $zero to always be
2459 reset to zero after every instruction.
2460
2461Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2462
2463 * configure: Regenerated to track ../common/aclocal.m4 changes.
2464 * config.in: Ditto.
2465
2466Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2467
2468 * mips.igen (MSUB): Fix to work like MADD.
2469 * gencode.c (MSUB): Similarly.
2470
2471Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2472
2473 * configure: Regenerated to track ../common/aclocal.m4 changes.
2474
2475Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2476
2477 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2478
2479Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2480
2481 * sim-main.h (sim-fpu.h): Include.
2482
2483 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2484 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2485 using host independant sim_fpu module.
2486
2487Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2488
2489 * interp.c (signal_exception): Report internal errors with SIGABRT
2490 not SIGQUIT.
2491
2492 * sim-main.h (C0_CONFIG): New register.
2493 (signal.h): No longer include.
2494
2495 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2496
2497Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2498
2499 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2500
2501Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * mips.igen: Tag vr5000 instructions.
2504 (ANDI): Was missing mipsIV model, fix assembler syntax.
2505 (do_c_cond_fmt): New function.
2506 (C.cond.fmt): Handle mips I-III which do not support CC field
2507 separatly.
2508 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2509 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2510 in IV3.2 spec.
2511 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2512 vr5000 which saves LO in a GPR separatly.
72f4393d 2513
c906108c
SS		 2514 * configure.in (enable-sim-igen): For vr5000, select vr5000
2515 specific instructions.
2516 * configure: Re-generate.
72f4393d 2517
c906108c
SS		 2518Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2519
2520 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2521
2522 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2523 fmt_uninterpreted_64 bit cases to switch. Convert to
2524 fmt_formatted,
2525
2526 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2527
2528 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2529 as specified in IV3.2 spec.
2530 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2531
2532Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2533
2534 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2535 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2536 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2537 PENDING_FILL versions of instructions. Simplify.
2538 (X): New function.
2539 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2540 instructions.
2541 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2542 a signed value.
2543 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2544
c906108c
SS		 2545 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2546 global.
2547 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2548
2549Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * gencode.c (build_mips16_operands): Replace IPC with cia.
2552
2553 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2554 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2555 IPC to `cia'.
2556 (UndefinedResult): Replace function with macro/function
2557 combination.
2558 (sim_engine_run): Don't save PC in IPC.
2559
2560 * sim-main.h (IPC): Delete.
2561
2562
2563 * interp.c (signal_exception, store_word, load_word,
2564 address_translation, load_memory, store_memory, cache_op,
2565 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2566 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2567 current instruction address - cia - argument.
2568 (sim_read, sim_write): Call address_translation directly.
2569 (sim_engine_run): Rename variable vaddr to cia.
2570 (signal_exception): Pass cia to sim_monitor
72f4393d 2571
c906108c
SS		 2572 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2573 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2574 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2575
2576 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2577 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2578 SIM_ASSERT.
72f4393d 2579
c906108c
SS		 2580 * interp.c (signal_exception): Pass restart address to
2581 sim_engine_restart.
2582
2583 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2584 idecode.o): Add dependency.
2585
2586 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2587 Delete definitions
2588 (DELAY_SLOT): Update NIA not PC with branch address.
2589 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2590
2591 * mips.igen: Use CIA not PC in branch calculations.
2592 (illegal): Call SignalException.
2593 (BEQ, ADDIU): Fix assembler.
2594
2595Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2596
2597 * m16.igen (JALX): Was missing.
2598
2599 * configure.in (enable-sim-igen): New configuration option.
2600 * configure: Re-generate.
72f4393d 2601
c906108c
SS		 2602 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2603
2604 * interp.c (load_memory, store_memory): Delete parameter RAW.
2605 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2606 bypassing {load,store}_memory.
2607
2608 * sim-main.h (ByteSwapMem): Delete definition.
2609
2610 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2611
2612 * interp.c (sim_do_command, sim_commands): Delete mips specific
2613 commands. Handled by module sim-options.
72f4393d 2614
c906108c
SS		 2615 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2616 (WITH_MODULO_MEMORY): Define.
2617
2618 * interp.c (sim_info): Delete code printing memory size.
2619
2620 * interp.c (mips_size): Nee sim_size, delete function.
2621 (power2): Delete.
2622 (monitor, monitor_base, monitor_size): Delete global variables.
2623 (sim_open, sim_close): Delete code creating monitor and other
2624 memory regions. Use sim-memopts module, via sim_do_commandf, to
2625 manage memory regions.
2626 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2627
c906108c
SS		 2628 * interp.c (address_translation): Delete all memory map code
2629 except line forcing 32 bit addresses.
2630
2631Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2634 trace options.
2635
2636 * interp.c (logfh, logfile): Delete globals.
2637 (sim_open, sim_close): Delete code opening & closing log file.
2638 (mips_option_handler): Delete -l and -n options.
2639 (OPTION mips_options): Ditto.
2640
2641 * interp.c (OPTION mips_options): Rename option trace to dinero.
2642 (mips_option_handler): Update.
2643
2644Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2645
2646 * interp.c (fetch_str): New function.
2647 (sim_monitor): Rewrite using sim_read & sim_write.
2648 (sim_open): Check magic number.
2649 (sim_open): Write monitor vectors into memory using sim_write.
2650 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2651 (sim_read, sim_write): Simplify - transfer data one byte at a
2652 time.
2653 (load_memory, store_memory): Clarify meaning of parameter RAW.
2654
2655 * sim-main.h (isHOST): Defete definition.
2656 (isTARGET): Mark as depreciated.
2657 (address_translation): Delete parameter HOST.
2658
2659 * interp.c (address_translation): Delete parameter HOST.
2660
2661Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2662
72f4393d 2663 * mips.igen:
c906108c
SS		 2664
2665 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2666 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2667
2668Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2669
2670 * mips.igen: Add model filter field to records.
2671
2672Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2673
2674 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2675
c906108c
SS		 2676 interp.c (sim_engine_run): Do not compile function sim_engine_run
2677 when WITH_IGEN == 1.
2678
2679 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2680 target architecture.
2681
2682 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2683 igen. Replace with configuration variables sim_igen_flags /
2684 sim_m16_flags.
2685
2686 * m16.igen: New file. Copy mips16 insns here.
2687 * mips.igen: From here.
2688
2689Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2690
2691 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2692 to top.
2693 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2694
2695Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2696
2697 * gencode.c (build_instruction): Follow sim_write's lead in using
2698 BigEndianMem instead of !ByteSwapMem.
2699
2700Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2701
2702 * configure.in (sim_gen): Dependent on target, select type of
2703 generator. Always select old style generator.
2704
2705 configure: Re-generate.
2706
2707 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2708 targets.
2709 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2710 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2711 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2712 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2713 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2714
c906108c
SS		 2715Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716
2717 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2718
2719 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2720 CURRENT_FLOATING_POINT instead.
2721
2722 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2723 (address_translation): Raise exception InstructionFetch when
2724 translation fails and isINSTRUCTION.
72f4393d 2725
c906108c
SS		 2726 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2727 sim_engine_run): Change type of of vaddr and paddr to
2728 address_word.
2729 (address_translation, prefetch, load_memory, store_memory,
2730 cache_op): Change type of vAddr and pAddr to address_word.
2731
2732 * gencode.c (build_instruction): Change type of vaddr and paddr to
2733 address_word.
2734
2735Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2736
2737 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2738 macro to obtain result of ALU op.
2739
2740Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2741
2742 * interp.c (sim_info): Call profile_print.
2743
2744Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2745
2746 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2747
2748 * sim-main.h (WITH_PROFILE): Do not define, defined in
2749 common/sim-config.h. Use sim-profile module.
2750 (simPROFILE): Delete defintion.
2751
2752 * interp.c (PROFILE): Delete definition.
2753 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2754 (sim_close): Delete code writing profile histogram.
2755 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2756 Delete.
2757 (sim_engine_run): Delete code profiling the PC.
2758
2759Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2760
2761 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2762
2763 * interp.c (sim_monitor): Make register pointers of type
2764 unsigned_word*.
2765
2766 * sim-main.h: Make registers of type unsigned_word not
2767 signed_word.
2768
2769Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2770
2771 * interp.c (sync_operation): Rename from SyncOperation, make
2772 global, add SD argument.
2773 (prefetch): Rename from Prefetch, make global, add SD argument.
2774 (decode_coproc): Make global.
2775
2776 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2777
2778 * gencode.c (build_instruction): Generate DecodeCoproc not
2779 decode_coproc calls.
2780
2781 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2782 (SizeFGR): Move to sim-main.h
2783 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2784 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2785 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2786 sim-main.h.
2787 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2788 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2789 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2790 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2791 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2792 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2793
c906108c
SS		 2794 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2795 exception.
2796 (sim-alu.h): Include.
2797 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2798 (sim_cia): Typedef to instruction_address.
72f4393d 2799
c906108c
SS		 2800Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2801
2802 * Makefile.in (interp.o): Rename generated file engine.c to
2803 oengine.c.
72f4393d 2804
c906108c 2805 * interp.c: Update.
72f4393d 2806
c906108c
SS		 2807Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2808
2809 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2810
c906108c
SS		 2811Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2812
2813 * gencode.c (build_instruction): For "FPSQRT", output correct
2814 number of arguments to Recip.
72f4393d 2815
c906108c
SS		 2816Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2817
2818 * Makefile.in (interp.o): Depends on sim-main.h
2819
2820 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2821
2822 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2823 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2824 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2825 STATE, DSSTATE): Define
2826 (GPR, FGRIDX, ..): Define.
2827
2828 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2829 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2830 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2831
c906108c 2832 * interp.c: Update names to match defines from sim-main.h
72f4393d 2833
c906108c
SS		 2834Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2835
2836 * interp.c (sim_monitor): Add SD argument.
2837 (sim_warning): Delete. Replace calls with calls to
2838 sim_io_eprintf.
2839 (sim_error): Delete. Replace calls with sim_io_error.
2840 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2841 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2842 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2843 argument.
2844 (mips_size): Rename from sim_size. Add SD argument.
2845
2846 * interp.c (simulator): Delete global variable.
2847 (callback): Delete global variable.
2848 (mips_option_handler, sim_open, sim_write, sim_read,
2849 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2850 sim_size,sim_monitor): Use sim_io_* not callback->*.
2851 (sim_open): ZALLOC simulator struct.
2852 (PROFILE): Do not define.
2853
2854Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2855
2856 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2857 support.h with corresponding code.
2858
2859 * sim-main.h (word64, uword64), support.h: Move definition to
2860 sim-main.h.
2861 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2862
2863 * support.h: Delete
2864 * Makefile.in: Update dependencies
2865 * interp.c: Do not include.
72f4393d 2866
c906108c
SS		 2867Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2868
2869 * interp.c (address_translation, load_memory, store_memory,
2870 cache_op): Rename to from AddressTranslation et.al., make global,
2871 add SD argument
72f4393d 2872
c906108c
SS		 2873 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2874 CacheOp): Define.
72f4393d 2875
c906108c
SS		 2876 * interp.c (SignalException): Rename to signal_exception, make
2877 global.
2878
2879 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2880
c906108c
SS		 2881 * sim-main.h (SignalException, SignalExceptionInterrupt,
2882 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2883 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2884 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2885 Define.
72f4393d 2886
c906108c 2887 * interp.c, support.h: Use.
72f4393d 2888
c906108c
SS		 2889Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2890
2891 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2892 to value_fpr / store_fpr. Add SD argument.
2893 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2894 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2895
2896 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2897
c906108c
SS		 2898Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2899
2900 * interp.c (sim_engine_run): Check consistency between configure
2901 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2902 and HASFPU.
2903
2904 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2905 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2906 (mips_endian): Configure WITH_TARGET_ENDIAN.
2907 * configure: Update.
2908
2909Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2910
2911 * configure: Regenerated to track ../common/aclocal.m4 changes.
2912
2913Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2914
2915 * configure: Regenerated.
2916
2917Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2918
2919 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2920
2921Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2922
2923 * gencode.c (print_igen_insn_models): Assume certain architectures
2924 include all mips* instructions.
2925 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2926 instruction.
2927
2928 * Makefile.in (tmp.igen): Add target. Generate igen input from
2929 gencode file.
2930
2931 * gencode.c (FEATURE_IGEN): Define.
2932 (main): Add --igen option. Generate output in igen format.
2933 (process_instructions): Format output according to igen option.
2934 (print_igen_insn_format): New function.
2935 (print_igen_insn_models): New function.
2936 (process_instructions): Only issue warnings and ignore
2937 instructions when no FEATURE_IGEN.
2938
2939Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2940
2941 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2942 MIPS targets.
2943
2944Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2945
2946 * configure: Regenerated to track ../common/aclocal.m4 changes.
2947
2948Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2949
2950 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2951 SIM_RESERVED_BITS): Delete, moved to common.
2952 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2953
c906108c
SS		 2954Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2955
2956 * configure.in: Configure non-strict memory alignment.
2957 * configure: Regenerated to track ../common/aclocal.m4 changes.
2958
2959Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2960
2961 * configure: Regenerated to track ../common/aclocal.m4 changes.
2962
2963Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2964
2965 * gencode.c (SDBBP,DERET): Added (3900) insns.
2966 (RFE): Turn on for 3900.
2967 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2968 (dsstate): Made global.
2969 (SUBTARGET_R3900): Added.
2970 (CANCELDELAYSLOT): New.
2971 (SignalException): Ignore SystemCall rather than ignore and
2972 terminate. Add DebugBreakPoint handling.
2973 (decode_coproc): New insns RFE, DERET; and new registers Debug
2974 and DEPC protected by SUBTARGET_R3900.
2975 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2976 bits explicitly.
2977 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2978 * configure: Update.
c906108c
SS		 2979
2980Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2981
2982 * gencode.c: Add r3900 (tx39).
72f4393d 2983
c906108c
SS		 2984
2985Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2986
2987 * gencode.c (build_instruction): Don't need to subtract 4 for
2988 JALR, just 2.
2989
2990Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
2991
2992 * interp.c: Correct some HASFPU problems.
2993
2994Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
2995
2996 * configure: Regenerated to track ../common/aclocal.m4 changes.
2997
2998Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2999
3000 * interp.c (mips_options): Fix samples option short form, should
3001 be `x'.
3002
3003Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3004
3005 * interp.c (sim_info): Enable info code. Was just returning.
3006
3007Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3008
3009 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3010 MFC0.
3011
3012Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3013
3014 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3015 constants.
3016 (build_instruction): Ditto for LL.
3017
3018Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3019
3020 * configure: Regenerated to track ../common/aclocal.m4 changes.
3021
3022Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3023
3024 * configure: Regenerated to track ../common/aclocal.m4 changes.
3025 * config.in: Ditto.
3026
3027Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3028
3029 * interp.c (sim_open): Add call to sim_analyze_program, update
3030 call to sim_config.
3031
3032Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3033
3034 * interp.c (sim_kill): Delete.
3035 (sim_create_inferior): Add ABFD argument. Set PC from same.
3036 (sim_load): Move code initializing trap handlers from here.
3037 (sim_open): To here.
3038 (sim_load): Delete, use sim-hload.c.
3039
3040 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3041
3042Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3043
3044 * configure: Regenerated to track ../common/aclocal.m4 changes.
3045 * config.in: Ditto.
3046
3047Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3048
3049 * interp.c (sim_open): Add ABFD argument.
3050 (sim_load): Move call to sim_config from here.
3051 (sim_open): To here. Check return status.
3052
3053Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3054
c906108c
SS		 3055 * gencode.c (build_instruction): Two arg MADD should
3056 not assign result to $0.
72f4393d 3057
c906108c
SS		 3058Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3059
3060 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3061 * sim/mips/configure.in: Regenerate.
3062
3063Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3064
3065 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3066 signed8, unsigned8 et.al. types.
3067
3068 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3069 hosts when selecting subreg.
3070
3071Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3072
3073 * interp.c (sim_engine_run): Reset the ZERO register to zero
3074 regardless of FEATURE_WARN_ZERO.
3075 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3076
3077Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3078
3079 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3080 (SignalException): For BreakPoints ignore any mode bits and just
3081 save the PC.
3082 (SignalException): Always set the CAUSE register.
3083
3084Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3085
3086 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3087 exception has been taken.
3088
3089 * interp.c: Implement the ERET and mt/f sr instructions.
3090
3091Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3092
3093 * interp.c (SignalException): Don't bother restarting an
3094 interrupt.
3095
3096Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3097
3098 * interp.c (SignalException): Really take an interrupt.
3099 (interrupt_event): Only deliver interrupts when enabled.
3100
3101Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102
3103 * interp.c (sim_info): Only print info when verbose.
3104 (sim_info) Use sim_io_printf for output.
72f4393d 3105
c906108c
SS		 3106Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3109 mips architectures.
3110
3111Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3112
3113 * interp.c (sim_do_command): Check for common commands if a
3114 simulator specific command fails.
3115
3116Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3117
3118 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3119 and simBE when DEBUG is defined.
3120
3121Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3122
3123 * interp.c (interrupt_event): New function. Pass exception event
3124 onto exception handler.
3125
3126 * configure.in: Check for stdlib.h.
3127 * configure: Regenerate.
3128
3129 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3130 variable declaration.
3131 (build_instruction): Initialize memval1.
3132 (build_instruction): Add UNUSED attribute to byte, bigend,
3133 reverse.
3134 (build_operands): Ditto.
3135
3136 * interp.c: Fix GCC warnings.
3137 (sim_get_quit_code): Delete.
3138
3139 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3140 * Makefile.in: Ditto.
3141 * configure: Re-generate.
72f4393d 3142
c906108c
SS		 3143 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3144
3145Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3146
3147 * interp.c (mips_option_handler): New function parse argumes using
3148 sim-options.
3149 (myname): Replace with STATE_MY_NAME.
3150 (sim_open): Delete check for host endianness - performed by
3151 sim_config.
3152 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3153 (sim_open): Move much of the initialization from here.
3154 (sim_load): To here. After the image has been loaded and
3155 endianness set.
3156 (sim_open): Move ColdReset from here.
3157 (sim_create_inferior): To here.
3158 (sim_open): Make FP check less dependant on host endianness.
3159
3160 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3161 run.
3162 * interp.c (sim_set_callbacks): Delete.
3163
3164 * interp.c (membank, membank_base, membank_size): Replace with
3165 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3166 (sim_open): Remove call to callback->init. gdb/run do this.
3167
3168 * interp.c: Update
3169
3170 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3171
3172 * interp.c (big_endian_p): Delete, replaced by
3173 current_target_byte_order.
3174
3175Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3176
3177 * interp.c (host_read_long, host_read_word, host_swap_word,
3178 host_swap_long): Delete. Using common sim-endian.
3179 (sim_fetch_register, sim_store_register): Use H2T.
3180 (pipeline_ticks): Delete. Handled by sim-events.
3181 (sim_info): Update.
3182 (sim_engine_run): Update.
3183
3184Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3185
3186 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3187 reason from here.
3188 (SignalException): To here. Signal using sim_engine_halt.
3189 (sim_stop_reason): Delete, moved to common.
72f4393d 3190
c906108c
SS		 3191Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3192
3193 * interp.c (sim_open): Add callback argument.
3194 (sim_set_callbacks): Delete SIM_DESC argument.
3195 (sim_size): Ditto.
3196
3197Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3198
3199 * Makefile.in (SIM_OBJS): Add common modules.
3200
3201 * interp.c (sim_set_callbacks): Also set SD callback.
3202 (set_endianness, xfer_*, swap_*): Delete.
3203 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3204 Change to functions using sim-endian macros.
3205 (control_c, sim_stop): Delete, use common version.
3206 (simulate): Convert into.
3207 (sim_engine_run): This function.
3208 (sim_resume): Delete.
72f4393d 3209
c906108c
SS		 3210 * interp.c (simulation): New variable - the simulator object.
3211 (sim_kind): Delete global - merged into simulation.
3212 (sim_load): Cleanup. Move PC assignment from here.
3213 (sim_create_inferior): To here.
3214
3215 * sim-main.h: New file.
3216 * interp.c (sim-main.h): Include.
72f4393d 3217
c906108c
SS		 3218Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3219
3220 * configure: Regenerated to track ../common/aclocal.m4 changes.
3221
3222Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3223
3224 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3225
3226Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3227
72f4393d
L		 3228 * gencode.c (build_instruction): DIV instructions: check
3229 for division by zero and integer overflow before using
c906108c
SS		 3230 host's division operation.
3231
3232Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3233
3234 * Makefile.in (SIM_OBJS): Add sim-load.o.
3235 * interp.c: #include bfd.h.
3236 (target_byte_order): Delete.
3237 (sim_kind, myname, big_endian_p): New static locals.
3238 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3239 after argument parsing. Recognize -E arg, set endianness accordingly.
3240 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3241 load file into simulator. Set PC from bfd.
3242 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3243 (set_endianness): Use big_endian_p instead of target_byte_order.
3244
3245Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3246
3247 * interp.c (sim_size): Delete prototype - conflicts with
3248 definition in remote-sim.h. Correct definition.
3249
3250Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3251
3252 * configure: Regenerated to track ../common/aclocal.m4 changes.
3253 * config.in: Ditto.
3254
3255Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3256
3257 * interp.c (sim_open): New arg `kind'.
3258
3259 * configure: Regenerated to track ../common/aclocal.m4 changes.
3260
3261Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3262
3263 * configure: Regenerated to track ../common/aclocal.m4 changes.
3264
3265Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3266
3267 * interp.c (sim_open): Set optind to 0 before calling getopt.
3268
3269Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3270
3271 * configure: Regenerated to track ../common/aclocal.m4 changes.
3272
3273Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3274
3275 * interp.c : Replace uses of pr_addr with pr_uword64
3276 where the bit length is always 64 independent of SIM_ADDR.
3277 (pr_uword64) : added.
3278
3279Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3280
3281 * configure: Re-generate.
3282
3283Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3284
3285 * configure: Regenerate to track ../common/aclocal.m4 changes.
3286
3287Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3288
3289 * interp.c (sim_open): New SIM_DESC result. Argument is now
3290 in argv form.
3291 (other sim_*): New SIM_DESC argument.
3292
3293Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3294
3295 * interp.c: Fix printing of addresses for non-64-bit targets.
3296 (pr_addr): Add function to print address based on size.
3297
3298Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3299
3300 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3301
3302Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3303
3304 * gencode.c (build_mips16_operands): Correct computation of base
3305 address for extended PC relative instruction.
3306
3307Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3308
3309 * interp.c (mips16_entry): Add support for floating point cases.
3310 (SignalException): Pass floating point cases to mips16_entry.
3311 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3312 registers.
3313 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3314 or fmt_word.
3315 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3316 and then set the state to fmt_uninterpreted.
3317 (COP_SW): Temporarily set the state to fmt_word while calling
3318 ValueFPR.
3319
3320Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3321
3322 * gencode.c (build_instruction): The high order may be set in the
3323 comparison flags at any ISA level, not just ISA 4.
3324
3325Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3326
3327 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3328 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3329 * configure.in: sinclude ../common/aclocal.m4.
3330 * configure: Regenerated.
3331
3332Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3333
3334 * configure: Rebuild after change to aclocal.m4.
3335
3336Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3337
3338 * configure configure.in Makefile.in: Update to new configure
3339 scheme which is more compatible with WinGDB builds.
3340 * configure.in: Improve comment on how to run autoconf.
3341 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3342 * Makefile.in: Use autoconf substitution to install common
3343 makefile fragment.
3344
3345Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3346
3347 * gencode.c (build_instruction): Use BigEndianCPU instead of
3348 ByteSwapMem.
3349
3350Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3351
3352 * interp.c (sim_monitor): Make output to stdout visible in
3353 wingdb's I/O log window.
3354
3355Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3356
3357 * support.h: Undo previous change to SIGTRAP
3358 and SIGQUIT values.
3359
3360Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3361
3362 * interp.c (store_word, load_word): New static functions.
3363 (mips16_entry): New static function.
3364 (SignalException): Look for mips16 entry and exit instructions.
3365 (simulate): Use the correct index when setting fpr_state after
3366 doing a pending move.
3367
3368Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3369
3370 * interp.c: Fix byte-swapping code throughout to work on
3371 both little- and big-endian hosts.
3372
3373Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3374
3375 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3376 with gdb/config/i386/xm-windows.h.
3377
3378Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3379
3380 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3381 that messes up arithmetic shifts.
3382
3383Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3384
3385 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3386 SIGTRAP and SIGQUIT for _WIN32.
3387
3388Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3389
3390 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3391 force a 64 bit multiplication.
3392 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3393 destination register is 0, since that is the default mips16 nop
3394 instruction.
3395
3396Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3397
3398 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3399 (build_endian_shift): Don't check proc64.
3400 (build_instruction): Always set memval to uword64. Cast op2 to
3401 uword64 when shifting it left in memory instructions. Always use
3402 the same code for stores--don't special case proc64.
3403
3404 * gencode.c (build_mips16_operands): Fix base PC value for PC
3405 relative operands.
3406 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3407 jal instruction.
3408 * interp.c (simJALDELAYSLOT): Define.
3409 (JALDELAYSLOT): Define.
3410 (INDELAYSLOT, INJALDELAYSLOT): Define.
3411 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3412
3413Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3414
3415 * interp.c (sim_open): add flush_cache as a PMON routine
3416 (sim_monitor): handle flush_cache by ignoring it
3417
3418Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3419
3420 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3421 BigEndianMem.
3422 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3423 (BigEndianMem): Rename to ByteSwapMem and change sense.
3424 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3425 BigEndianMem references to !ByteSwapMem.
3426 (set_endianness): New function, with prototype.
3427 (sim_open): Call set_endianness.
3428 (sim_info): Use simBE instead of BigEndianMem.
3429 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3430 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3431 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3432 ifdefs, keeping the prototype declaration.
3433 (swap_word): Rewrite correctly.
3434 (ColdReset): Delete references to CONFIG. Delete endianness related
3435 code; moved to set_endianness.
72f4393d 3436
c906108c
SS		 3437Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3438
3439 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3440 * interp.c (CHECKHILO): Define away.
3441 (simSIGINT): New macro.
3442 (membank_size): Increase from 1MB to 2MB.
3443 (control_c): New function.
3444 (sim_resume): Rename parameter signal to signal_number. Add local
3445 variable prev. Call signal before and after simulate.
3446 (sim_stop_reason): Add simSIGINT support.
3447 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3448 functions always.
3449 (sim_warning): Delete call to SignalException. Do call printf_filtered
3450 if logfh is NULL.
3451 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3452 a call to sim_warning.
3453
3454Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3455
3456 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3457 16 bit instructions.
3458
3459Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3460
3461 Add support for mips16 (16 bit MIPS implementation):
3462 * gencode.c (inst_type): Add mips16 instruction encoding types.
3463 (GETDATASIZEINSN): Define.
3464 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3465 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3466 mtlo.
3467 (MIPS16_DECODE): New table, for mips16 instructions.
3468 (bitmap_val): New static function.
3469 (struct mips16_op): Define.
3470 (mips16_op_table): New table, for mips16 operands.
3471 (build_mips16_operands): New static function.
3472 (process_instructions): If PC is odd, decode a mips16
3473 instruction. Break out instruction handling into new
3474 build_instruction function.
3475 (build_instruction): New static function, broken out of
3476 process_instructions. Check modifiers rather than flags for SHIFT
3477 bit count and m[ft]{hi,lo} direction.
3478 (usage): Pass program name to fprintf.
3479 (main): Remove unused variable this_option_optind. Change
3480 ``*loptarg++'' to ``loptarg++''.
3481 (my_strtoul): Parenthesize && within ||.
3482 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3483 (simulate): If PC is odd, fetch a 16 bit instruction, and
3484 increment PC by 2 rather than 4.
3485 * configure.in: Add case for mips16*-*-*.
3486 * configure: Rebuild.
3487
3488Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3489
3490 * interp.c: Allow -t to enable tracing in standalone simulator.
3491 Fix garbage output in trace file and error messages.
3492
3493Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3494
3495 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3496 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3497 * configure.in: Simplify using macros in ../common/aclocal.m4.
3498 * configure: Regenerated.
3499 * tconfig.in: New file.
3500
3501Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3502
3503 * interp.c: Fix bugs in 64-bit port.
3504 Use ansi function declarations for msvc compiler.
3505 Initialize and test file pointer in trace code.
3506 Prevent duplicate definition of LAST_EMED_REGNUM.
3507
3508Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3509
3510 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3511
3512Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3513
3514 * interp.c (SignalException): Check for explicit terminating
3515 breakpoint value.
3516 * gencode.c: Pass instruction value through SignalException()
3517 calls for Trap, Breakpoint and Syscall.
3518
3519Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3520
3521 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3522 only used on those hosts that provide it.
3523 * configure.in: Add sqrt() to list of functions to be checked for.
3524 * config.in: Re-generated.
3525 * configure: Re-generated.
3526
3527Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3528
3529 * gencode.c (process_instructions): Call build_endian_shift when
3530 expanding STORE RIGHT, to fix swr.
3531 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3532 clear the high bits.
3533 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3534 Fix float to int conversions to produce signed values.
3535
3536Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3537
3538 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3539 (process_instructions): Correct handling of nor instruction.
3540 Correct shift count for 32 bit shift instructions. Correct sign
3541 extension for arithmetic shifts to not shift the number of bits in
3542 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3543 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3544 Fix madd.
3545 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3546 It's OK to have a mult follow a mult. What's not OK is to have a
3547 mult follow an mfhi.
3548 (Convert): Comment out incorrect rounding code.
3549
3550Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3551
3552 * interp.c (sim_monitor): Improved monitor printf
3553 simulation. Tidied up simulator warnings, and added "--log" option
3554 for directing warning message output.
3555 * gencode.c: Use sim_warning() rather than WARNING macro.
3556
3557Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3558
3559 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3560 getopt1.o, rather than on gencode.c. Link objects together.
3561 Don't link against -liberty.
3562 (gencode.o, getopt.o, getopt1.o): New targets.
3563 * gencode.c: Include <ctype.h> and "ansidecl.h".
3564 (AND): Undefine after including "ansidecl.h".
3565 (ULONG_MAX): Define if not defined.
3566 (OP_*): Don't define macros; now defined in opcode/mips.h.
3567 (main): Call my_strtoul rather than strtoul.
3568 (my_strtoul): New static function.
3569
3570Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3571
3572 * gencode.c (process_instructions): Generate word64 and uword64
3573 instead of `long long' and `unsigned long long' data types.
3574 * interp.c: #include sysdep.h to get signals, and define default
3575 for SIGBUS.
3576 * (Convert): Work around for Visual-C++ compiler bug with type
3577 conversion.
3578 * support.h: Make things compile under Visual-C++ by using
3579 __int64 instead of `long long'. Change many refs to long long
3580 into word64/uword64 typedefs.
3581
3582Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3583
72f4393d
L		 3584 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3585 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3586 (docdir): Removed.
3587 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3588 (AC_PROG_INSTALL): Added.
c906108c 3589 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3590 * configure: Rebuilt.
3591
c906108c
SS		 3592Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3593
3594 * configure.in: Define @SIMCONF@ depending on mips target.
3595 * configure: Rebuild.
3596 * Makefile.in (run): Add @SIMCONF@ to control simulator
3597 construction.
3598 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3599 * interp.c: Remove some debugging, provide more detailed error
3600 messages, update memory accesses to use LOADDRMASK.
72f4393d 3601
c906108c
SS		 3602Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3603
3604 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3605 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3606 stamp-h.
3607 * configure: Rebuild.
3608 * config.in: New file, generated by autoheader.
3609 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3610 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3611 HAVE_ANINT and HAVE_AINT, as appropriate.
3612 * Makefile.in (run): Use @LIBS@ rather than -lm.
3613 (interp.o): Depend upon config.h.
3614 (Makefile): Just rebuild Makefile.
3615 (clean): Remove stamp-h.
3616 (mostlyclean): Make the same as clean, not as distclean.
3617 (config.h, stamp-h): New targets.
3618
3619Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3620
3621 * interp.c (ColdReset): Fix boolean test. Make all simulator
3622 globals static.
3623
3624Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3625
3626 * interp.c (xfer_direct_word, xfer_direct_long,
3627 swap_direct_word, swap_direct_long, xfer_big_word,
3628 xfer_big_long, xfer_little_word, xfer_little_long,
3629 swap_word,swap_long): Added.
3630 * interp.c (ColdReset): Provide function indirection to
3631 host<->simulated_target transfer routines.
3632 * interp.c (sim_store_register, sim_fetch_register): Updated to
3633 make use of indirected transfer routines.
3634
3635Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3636
3637 * gencode.c (process_instructions): Ensure FP ABS instruction
3638 recognised.
3639 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3640 system call support.
3641
3642Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3643
3644 * interp.c (sim_do_command): Complain if callback structure not
3645 initialised.
3646
3647Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3648
3649 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3650 support for Sun hosts.
3651 * Makefile.in (gencode): Ensure the host compiler and libraries
3652 used for cross-hosted build.
3653
3654Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3655
3656 * interp.c, gencode.c: Some more (TODO) tidying.
3657
3658Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3659
3660 * gencode.c, interp.c: Replaced explicit long long references with
3661 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3662 * support.h (SET64LO, SET64HI): Macros added.
3663
3664Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3665
3666 * configure: Regenerate with autoconf 2.7.
3667
3668Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3669
3670 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3671 * support.h: Remove superfluous "1" from #if.
3672 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3673
3674Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3675
3676 * interp.c (StoreFPR): Control UndefinedResult() call on
3677 WARN_RESULT manifest.
3678
3679Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3680
3681 * gencode.c: Tidied instruction decoding, and added FP instruction
3682 support.
3683
3684 * interp.c: Added dineroIII, and BSD profiling support. Also
3685 run-time FP handling.
3686
3687Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3688
3689 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3690 gencode.c, interp.c, support.h: created.
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