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mmc: disable UHS modes if Vcc cannot be switched on and off
[people/ms/u-boot.git] / drivers / mmc / mmc.c
CommitLineData
272cc70b
AF		 1/*
2 * Copyright 2008, Freescale Semiconductor, Inc
3 * Andy Fleming
4 *
5 * Based vaguely on the Linux code
6 *
1a459660 7 * SPDX-License-Identifier: GPL-2.0+
272cc70b
AF		 8 */
9
10#include <config.h>
11#include <common.h>
12#include <command.h>
8e3332e2
SS		 13#include <dm.h>
14#include <dm/device-internal.h>
d4622df3 15#include <errno.h>
272cc70b
AF		 16#include <mmc.h>
17#include <part.h>
2051aefe 18#include <power/regulator.h>
272cc70b 19#include <malloc.h>
cf92e05c 20#include <memalign.h>
272cc70b 21#include <linux/list.h>
9b1f942c 22#include <div64.h>
da61fa5f 23#include "mmc_private.h"
272cc70b 24
3697e599
PF		 25static const unsigned int sd_au_size[] = {
26 0, SZ_16K / 512, SZ_32K / 512,
27 SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
28 SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
29 SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
30 SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512, SZ_64M / 512,
31};
32
aff5d3c8 33static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
fb7c3beb 34static int mmc_power_cycle(struct mmc *mmc);
aff5d3c8 35
b5b838f1
MV		 36#if CONFIG_IS_ENABLED(MMC_TINY)
37static struct mmc mmc_static;
38struct mmc *find_mmc_device(int dev_num)
39{
40 return &mmc_static;
41}
42
43void mmc_do_preinit(void)
44{
45 struct mmc *m = &mmc_static;
46#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
47 mmc_set_preinit(m, 1);
48#endif
49 if (m->preinit)
50 mmc_start_init(m);
51}
52
53struct blk_desc *mmc_get_blk_desc(struct mmc *mmc)
54{
55 return &mmc->block_dev;
56}
57#endif
58
e7881d85 59#if !CONFIG_IS_ENABLED(DM_MMC)
c10b85d6
JJH		 60
61static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout)
62{
63 return -ENOSYS;
64}
65
750121c3 66__weak int board_mmc_getwp(struct mmc *mmc)
d23d8d7e
NK		 67{
68 return -1;
69}
70
71int mmc_getwp(struct mmc *mmc)
72{
73 int wp;
74
75 wp = board_mmc_getwp(mmc);
76
d4e1da4e 77 if (wp < 0) {
93bfd616
PA		 78 if (mmc->cfg->ops->getwp)
79 wp = mmc->cfg->ops->getwp(mmc);
d4e1da4e
PK		 80 else
81 wp = 0;
82 }
d23d8d7e
NK		 83
84 return wp;
85}
86
cee9ab7c
JH		 87__weak int board_mmc_getcd(struct mmc *mmc)
88{
11fdade2
SB		 89 return -1;
90}
8ca51e51 91#endif
11fdade2 92
c0c76eba
SG		 93#ifdef CONFIG_MMC_TRACE
94void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
272cc70b 95{
c0c76eba
SG		 96 printf("CMD_SEND:%d\n", cmd->cmdidx);
97 printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg);
98}
8635ff9e 99
c0c76eba
SG		 100void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
101{
5db2fe3a
RR		 102 int i;
103 u8 *ptr;
104
7863ce58
BM		 105 if (ret) {
106 printf("\t\tRET\t\t\t %d\n", ret);
107 } else {
108 switch (cmd->resp_type) {
109 case MMC_RSP_NONE:
110 printf("\t\tMMC_RSP_NONE\n");
111 break;
112 case MMC_RSP_R1:
113 printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n",
114 cmd->response[0]);
115 break;
116 case MMC_RSP_R1b:
117 printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n",
118 cmd->response[0]);
119 break;
120 case MMC_RSP_R2:
121 printf("\t\tMMC_RSP_R2\t\t 0x%08X \n",
122 cmd->response[0]);
123 printf("\t\t \t\t 0x%08X \n",
124 cmd->response[1]);
125 printf("\t\t \t\t 0x%08X \n",
126 cmd->response[2]);
127 printf("\t\t \t\t 0x%08X \n",
128 cmd->response[3]);
5db2fe3a 129 printf("\n");
7863ce58
BM		 130 printf("\t\t\t\t\tDUMPING DATA\n");
131 for (i = 0; i < 4; i++) {
132 int j;
133 printf("\t\t\t\t\t%03d - ", i*4);
134 ptr = (u8 *)&cmd->response[i];
135 ptr += 3;
136 for (j = 0; j < 4; j++)
137 printf("%02X ", *ptr--);
138 printf("\n");
139 }
140 break;
141 case MMC_RSP_R3:
142 printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n",
143 cmd->response[0]);
144 break;
145 default:
146 printf("\t\tERROR MMC rsp not supported\n");
147 break;
53e8e40b 148 }
5db2fe3a 149 }
c0c76eba
SG		 150}
151
152void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
153{
154 int status;
155
156 status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
157 printf("CURR STATE:%d\n", status);
158}
5db2fe3a 159#endif
c0c76eba 160
35f9e196
JJH		 161#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
162const char *mmc_mode_name(enum bus_mode mode)
163{
164 static const char *const names[] = {
165 [MMC_LEGACY] = "MMC legacy",
166 [SD_LEGACY] = "SD Legacy",
167 [MMC_HS] = "MMC High Speed (26MHz)",
168 [SD_HS] = "SD High Speed (50MHz)",
169 [UHS_SDR12] = "UHS SDR12 (25MHz)",
170 [UHS_SDR25] = "UHS SDR25 (50MHz)",
171 [UHS_SDR50] = "UHS SDR50 (100MHz)",
172 [UHS_SDR104] = "UHS SDR104 (208MHz)",
173 [UHS_DDR50] = "UHS DDR50 (50MHz)",
174 [MMC_HS_52] = "MMC High Speed (52MHz)",
175 [MMC_DDR_52] = "MMC DDR52 (52MHz)",
176 [MMC_HS_200] = "HS200 (200MHz)",
177 };
178
179 if (mode >= MMC_MODES_END)
180 return "Unknown mode";
181 else
182 return names[mode];
183}
184#endif
185
05038576
JJH		 186static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
187{
188 static const int freqs[] = {
189 [SD_LEGACY] = 25000000,
190 [MMC_HS] = 26000000,
191 [SD_HS] = 50000000,
192 [UHS_SDR12] = 25000000,
193 [UHS_SDR25] = 50000000,
194 [UHS_SDR50] = 100000000,
195 [UHS_SDR104] = 208000000,
196 [UHS_DDR50] = 50000000,
197 [MMC_HS_52] = 52000000,
198 [MMC_DDR_52] = 52000000,
199 [MMC_HS_200] = 200000000,
200 };
201
202 if (mode == MMC_LEGACY)
203 return mmc->legacy_speed;
204 else if (mode >= MMC_MODES_END)
205 return 0;
206 else
207 return freqs[mode];
208}
209
35f9e196
JJH		 210static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
211{
212 mmc->selected_mode = mode;
05038576 213 mmc->tran_speed = mmc_mode2freq(mmc, mode);
3862b854 214 mmc->ddr_mode = mmc_is_mode_ddr(mode);
35f9e196
JJH		 215 debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
216 mmc->tran_speed / 1000000);
217 return 0;
218}
219
e7881d85 220#if !CONFIG_IS_ENABLED(DM_MMC)
c0c76eba
SG		 221int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
222{
223 int ret;
224
225 mmmc_trace_before_send(mmc, cmd);
226 ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
227 mmmc_trace_after_send(mmc, cmd, ret);
228
8635ff9e 229 return ret;
272cc70b 230}
8ca51e51 231#endif
272cc70b 232
da61fa5f 233int mmc_send_status(struct mmc *mmc, int timeout)
5d4fc8d9
RR		 234{
235 struct mmc_cmd cmd;
d617c426 236 int err, retries = 5;
5d4fc8d9
RR		 237
238 cmd.cmdidx = MMC_CMD_SEND_STATUS;
239 cmd.resp_type = MMC_RSP_R1;
aaf3d41a
MV		 240 if (!mmc_host_is_spi(mmc))
241 cmd.cmdarg = mmc->rca << 16;
5d4fc8d9 242
1677eef4 243 while (1) {
5d4fc8d9 244 err = mmc_send_cmd(mmc, &cmd, NULL);
d617c426
JK		 245 if (!err) {
246 if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) &&
247 (cmd.response[0] & MMC_STATUS_CURR_STATE) !=
248 MMC_STATE_PRG)
249 break;
d0c221fe
JJH		 250
251 if (cmd.response[0] & MMC_STATUS_MASK) {
56196826 252#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
d617c426
JK		 253 printf("Status Error: 0x%08X\n",
254 cmd.response[0]);
56196826 255#endif
915ffa52 256 return -ECOMM;
d617c426
JK		 257 }
258 } else if (--retries < 0)
5d4fc8d9 259 return err;
5d4fc8d9 260
1677eef4
AG		 261 if (timeout-- <= 0)
262 break;
5d4fc8d9 263
1677eef4
AG		 264 udelay(1000);
265 }
5d4fc8d9 266
c0c76eba 267 mmc_trace_state(mmc, &cmd);
5b0c942f 268 if (timeout <= 0) {
56196826 269#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
5d4fc8d9 270 printf("Timeout waiting card ready\n");
56196826 271#endif
915ffa52 272 return -ETIMEDOUT;
5d4fc8d9
RR		 273 }
274
275 return 0;
276}
277
da61fa5f 278int mmc_set_blocklen(struct mmc *mmc, int len)
272cc70b
AF		 279{
280 struct mmc_cmd cmd;
281
786e8f81 282 if (mmc->ddr_mode)
d22e3d46
JC		 283 return 0;
284
272cc70b
AF		 285 cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
286 cmd.resp_type = MMC_RSP_R1;
287 cmd.cmdarg = len;
272cc70b
AF		 288
289 return mmc_send_cmd(mmc, &cmd, NULL);
290}
291
ff8fef56 292static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
fdbb873e 293 lbaint_t blkcnt)
272cc70b
AF		 294{
295 struct mmc_cmd cmd;
296 struct mmc_data data;
297
4a1a06bc
AS		 298 if (blkcnt > 1)
299 cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
300 else
301 cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
272cc70b
AF		 302
303 if (mmc->high_capacity)
4a1a06bc 304 cmd.cmdarg = start;
272cc70b 305 else
4a1a06bc 306 cmd.cmdarg = start * mmc->read_bl_len;
272cc70b
AF		 307
308 cmd.resp_type = MMC_RSP_R1;
272cc70b
AF		 309
310 data.dest = dst;
4a1a06bc 311 data.blocks = blkcnt;
272cc70b
AF		 312 data.blocksize = mmc->read_bl_len;
313 data.flags = MMC_DATA_READ;
314
4a1a06bc
AS		 315 if (mmc_send_cmd(mmc, &cmd, &data))
316 return 0;
272cc70b 317
4a1a06bc
AS		 318 if (blkcnt > 1) {
319 cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
320 cmd.cmdarg = 0;
321 cmd.resp_type = MMC_RSP_R1b;
4a1a06bc 322 if (mmc_send_cmd(mmc, &cmd, NULL)) {
56196826 323#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
4a1a06bc 324 printf("mmc fail to send stop cmd\n");
56196826 325#endif
4a1a06bc
AS		 326 return 0;
327 }
272cc70b
AF		 328 }
329
4a1a06bc 330 return blkcnt;
272cc70b
AF		 331}
332
c4d660d4 333#if CONFIG_IS_ENABLED(BLK)
7dba0b93 334ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
33fb211d 335#else
7dba0b93
SG		 336ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
337 void *dst)
33fb211d 338#endif
272cc70b 339{
c4d660d4 340#if CONFIG_IS_ENABLED(BLK)
33fb211d
SG		 341 struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
342#endif
bcce53d0 343 int dev_num = block_dev->devnum;
873cc1d7 344 int err;
4a1a06bc
AS		 345 lbaint_t cur, blocks_todo = blkcnt;
346
347 if (blkcnt == 0)
348 return 0;
272cc70b 349
4a1a06bc 350 struct mmc *mmc = find_mmc_device(dev_num);
272cc70b
AF		 351 if (!mmc)
352 return 0;
353
b5b838f1
MV		 354 if (CONFIG_IS_ENABLED(MMC_TINY))
355 err = mmc_switch_part(mmc, block_dev->hwpart);
356 else
357 err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
358
873cc1d7
SW		 359 if (err < 0)
360 return 0;
361
c40fdca6 362 if ((start + blkcnt) > block_dev->lba) {
56196826 363#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
ff8fef56 364 printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
c40fdca6 365 start + blkcnt, block_dev->lba);
56196826 366#endif
d2bf29e3
LW		 367 return 0;
368 }
272cc70b 369
11692991
SG		 370 if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
371 debug("%s: Failed to set blocklen\n", __func__);
272cc70b 372 return 0;
11692991 373 }
272cc70b 374
4a1a06bc 375 do {
93bfd616
PA		 376 cur = (blocks_todo > mmc->cfg->b_max) ?
377 mmc->cfg->b_max : blocks_todo;
11692991
SG		 378 if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
379 debug("%s: Failed to read blocks\n", __func__);
4a1a06bc 380 return 0;
11692991 381 }
4a1a06bc
AS		 382 blocks_todo -= cur;
383 start += cur;
384 dst += cur * mmc->read_bl_len;
385 } while (blocks_todo > 0);
272cc70b
AF		 386
387 return blkcnt;
388}
389
fdbb873e 390static int mmc_go_idle(struct mmc *mmc)
272cc70b
AF		 391{
392 struct mmc_cmd cmd;
393 int err;
394
395 udelay(1000);
396
397 cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
398 cmd.cmdarg = 0;
399 cmd.resp_type = MMC_RSP_NONE;
272cc70b
AF		 400
401 err = mmc_send_cmd(mmc, &cmd, NULL);
402
403 if (err)
404 return err;
405
406 udelay(2000);
407
408 return 0;
409}
410
c10b85d6
JJH		 411static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
412{
413 struct mmc_cmd cmd;
414 int err = 0;
415
416 /*
417 * Send CMD11 only if the request is to switch the card to
418 * 1.8V signalling.
419 */
420 if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
421 return mmc_set_signal_voltage(mmc, signal_voltage);
422
423 cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
424 cmd.cmdarg = 0;
425 cmd.resp_type = MMC_RSP_R1;
426
427 err = mmc_send_cmd(mmc, &cmd, NULL);
428 if (err)
429 return err;
430
431 if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
432 return -EIO;
433
434 /*
435 * The card should drive cmd and dat[0:3] low immediately
436 * after the response of cmd11, but wait 100 us to be sure
437 */
438 err = mmc_wait_dat0(mmc, 0, 100);
439 if (err == -ENOSYS)
440 udelay(100);
441 else if (err)
442 return -ETIMEDOUT;
443
444 /*
445 * During a signal voltage level switch, the clock must be gated
446 * for 5 ms according to the SD spec
447 */
448 mmc_set_clock(mmc, mmc->clock, true);
449
450 err = mmc_set_signal_voltage(mmc, signal_voltage);
451 if (err)
452 return err;
453
454 /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
455 mdelay(10);
456 mmc_set_clock(mmc, mmc->clock, false);
457
458 /*
459 * Failure to switch is indicated by the card holding
460 * dat[0:3] low. Wait for at least 1 ms according to spec
461 */
462 err = mmc_wait_dat0(mmc, 1, 1000);
463 if (err == -ENOSYS)
464 udelay(1000);
465 else if (err)
466 return -ETIMEDOUT;
467
468 return 0;
469}
470
471static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
272cc70b
AF		 472{
473 int timeout = 1000;
474 int err;
475 struct mmc_cmd cmd;
476
1677eef4 477 while (1) {
272cc70b
AF		 478 cmd.cmdidx = MMC_CMD_APP_CMD;
479 cmd.resp_type = MMC_RSP_R1;
480 cmd.cmdarg = 0;
272cc70b
AF		 481
482 err = mmc_send_cmd(mmc, &cmd, NULL);
483
484 if (err)
485 return err;
486
487 cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
488 cmd.resp_type = MMC_RSP_R3;
250de12b
SB		 489
490 /*
491 * Most cards do not answer if some reserved bits
492 * in the ocr are set. However, Some controller
493 * can set bit 7 (reserved for low voltages), but
494 * how to manage low voltages SD card is not yet
495 * specified.
496 */
d52ebf10 497 cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
93bfd616 498 (mmc->cfg->voltages & 0xff8000);
272cc70b
AF		 499
500 if (mmc->version == SD_VERSION_2)
501 cmd.cmdarg |= OCR_HCS;
502
c10b85d6
JJH		 503 if (uhs_en)
504 cmd.cmdarg |= OCR_S18R;
505
272cc70b
AF		 506 err = mmc_send_cmd(mmc, &cmd, NULL);
507
508 if (err)
509 return err;
510
1677eef4
AG		 511 if (cmd.response[0] & OCR_BUSY)
512 break;
513
514 if (timeout-- <= 0)
915ffa52 515 return -EOPNOTSUPP;
272cc70b 516
1677eef4
AG		 517 udelay(1000);
518 }
272cc70b
AF		 519
520 if (mmc->version != SD_VERSION_2)
521 mmc->version = SD_VERSION_1_0;
522
d52ebf10
TC		 523 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
524 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
525 cmd.resp_type = MMC_RSP_R3;
526 cmd.cmdarg = 0;
d52ebf10
TC		 527
528 err = mmc_send_cmd(mmc, &cmd, NULL);
529
530 if (err)
531 return err;
532 }
533
998be3dd 534 mmc->ocr = cmd.response[0];
272cc70b 535
c10b85d6
JJH		 536 if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
537 == 0x41000000) {
538 err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
539 if (err)
540 return err;
541 }
542
272cc70b
AF		 543 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
544 mmc->rca = 0;
545
546 return 0;
547}
548
5289b535 549static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
272cc70b 550{
5289b535 551 struct mmc_cmd cmd;
272cc70b
AF		 552 int err;
553
5289b535
AG		 554 cmd.cmdidx = MMC_CMD_SEND_OP_COND;
555 cmd.resp_type = MMC_RSP_R3;
556 cmd.cmdarg = 0;
5a20397b
RH		 557 if (use_arg && !mmc_host_is_spi(mmc))
558 cmd.cmdarg = OCR_HCS |
93bfd616 559 (mmc->cfg->voltages &
a626c8d4
AG		 560 (mmc->ocr & OCR_VOLTAGE_MASK)) |
561 (mmc->ocr & OCR_ACCESS_MODE);
e9550449 562
5289b535 563 err = mmc_send_cmd(mmc, &cmd, NULL);
e9550449
CLC		 564 if (err)
565 return err;
5289b535 566 mmc->ocr = cmd.response[0];
e9550449
CLC		 567 return 0;
568}
569
750121c3 570static int mmc_send_op_cond(struct mmc *mmc)
e9550449 571{
e9550449
CLC		 572 int err, i;
573
272cc70b
AF		 574 /* Some cards seem to need this */
575 mmc_go_idle(mmc);
576
31cacbab 577 /* Asking to the card its capabilities */
e9550449 578 for (i = 0; i < 2; i++) {
5289b535 579 err = mmc_send_op_cond_iter(mmc, i != 0);
e9550449
CLC		 580 if (err)
581 return err;
cd6881b5 582
e9550449 583 /* exit if not busy (flag seems to be inverted) */
a626c8d4 584 if (mmc->ocr & OCR_BUSY)
bd47c135 585 break;
e9550449 586 }
bd47c135
AG		 587 mmc->op_cond_pending = 1;
588 return 0;
e9550449 589}
cd6881b5 590
750121c3 591static int mmc_complete_op_cond(struct mmc *mmc)
e9550449
CLC		 592{
593 struct mmc_cmd cmd;
594 int timeout = 1000;
595 uint start;
596 int err;
cd6881b5 597
e9550449 598 mmc->op_cond_pending = 0;
cc17c01f 599 if (!(mmc->ocr & OCR_BUSY)) {
d188b113
YL		 600 /* Some cards seem to need this */
601 mmc_go_idle(mmc);
602
cc17c01f 603 start = get_timer(0);
1677eef4 604 while (1) {
cc17c01f
AG		 605 err = mmc_send_op_cond_iter(mmc, 1);
606 if (err)
607 return err;
1677eef4
AG		 608 if (mmc->ocr & OCR_BUSY)
609 break;
cc17c01f 610 if (get_timer(start) > timeout)
915ffa52 611 return -EOPNOTSUPP;
cc17c01f 612 udelay(100);
1677eef4 613 }
cc17c01f 614 }
272cc70b 615
d52ebf10
TC		 616 if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
617 cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
618 cmd.resp_type = MMC_RSP_R3;
619 cmd.cmdarg = 0;
d52ebf10
TC		 620
621 err = mmc_send_cmd(mmc, &cmd, NULL);
622
623 if (err)
624 return err;
a626c8d4
AG		 625
626 mmc->ocr = cmd.response[0];
d52ebf10
TC		 627 }
628
272cc70b 629 mmc->version = MMC_VERSION_UNKNOWN;
272cc70b
AF		 630
631 mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
def816a2 632 mmc->rca = 1;
272cc70b
AF		 633
634 return 0;
635}
636
637
fdbb873e 638static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
272cc70b
AF		 639{
640 struct mmc_cmd cmd;
641 struct mmc_data data;
642 int err;
643
644 /* Get the Card Status Register */
645 cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
646 cmd.resp_type = MMC_RSP_R1;
647 cmd.cmdarg = 0;
272cc70b 648
cdfd1ac6 649 data.dest = (char *)ext_csd;
272cc70b 650 data.blocks = 1;
8bfa195e 651 data.blocksize = MMC_MAX_BLOCK_LEN;
272cc70b
AF		 652 data.flags = MMC_DATA_READ;
653
654 err = mmc_send_cmd(mmc, &cmd, &data);
655
656 return err;
657}
658
c40704f4 659int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
272cc70b
AF		 660{
661 struct mmc_cmd cmd;
5d4fc8d9 662 int timeout = 1000;
a9003dc6 663 int retries = 3;
5d4fc8d9 664 int ret;
272cc70b
AF		 665
666 cmd.cmdidx = MMC_CMD_SWITCH;
667 cmd.resp_type = MMC_RSP_R1b;
668 cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
5d4fc8d9
RR		 669 (index << 16) |
670 (value << 8);
272cc70b 671
a9003dc6
MR		 672 while (retries > 0) {
673 ret = mmc_send_cmd(mmc, &cmd, NULL);
5d4fc8d9 674
a9003dc6
MR		 675 /* Waiting for the ready status */
676 if (!ret) {
677 ret = mmc_send_status(mmc, timeout);
678 return ret;
679 }
680
681 retries--;
682 }
5d4fc8d9
RR		 683
684 return ret;
685
272cc70b
AF		 686}
687
3862b854 688static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode)
272cc70b 689{
272cc70b 690 int err;
3862b854
JJH		 691 int speed_bits;
692
693 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
694
695 switch (mode) {
696 case MMC_HS:
697 case MMC_HS_52:
698 case MMC_DDR_52:
699 speed_bits = EXT_CSD_TIMING_HS;
634d4849
KVA		 700 break;
701 case MMC_HS_200:
702 speed_bits = EXT_CSD_TIMING_HS200;
703 break;
3862b854
JJH		 704 case MMC_LEGACY:
705 speed_bits = EXT_CSD_TIMING_LEGACY;
706 break;
707 default:
708 return -EINVAL;
709 }
710 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
711 speed_bits);
712 if (err)
713 return err;
714
715 if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
716 /* Now check to see that it worked */
717 err = mmc_send_ext_csd(mmc, test_csd);
718 if (err)
719 return err;
720
721 /* No high-speed support */
722 if (!test_csd[EXT_CSD_HS_TIMING])
723 return -ENOTSUPP;
724 }
725
726 return 0;
727}
728
729static int mmc_get_capabilities(struct mmc *mmc)
730{
731 u8 *ext_csd = mmc->ext_csd;
732 char cardtype;
272cc70b 733
d0c221fe 734 mmc->card_caps = MMC_MODE_1BIT;
272cc70b 735
d52ebf10
TC		 736 if (mmc_host_is_spi(mmc))
737 return 0;
738
272cc70b
AF		 739 /* Only version 4 supports high-speed */
740 if (mmc->version < MMC_VERSION_4)
741 return 0;
742
3862b854
JJH		 743 if (!ext_csd) {
744 printf("No ext_csd found!\n"); /* this should enver happen */
745 return -ENOTSUPP;
746 }
272cc70b 747
3862b854 748 mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
272cc70b 749
634d4849 750 cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0x3f;
272cc70b 751
634d4849
KVA		 752 if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
753 EXT_CSD_CARD_TYPE_HS200_1_8V)) {
754 mmc->card_caps |= MMC_MODE_HS200;
755 }
d22e3d46 756 if (cardtype & EXT_CSD_CARD_TYPE_52) {
3862b854 757 if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
d22e3d46 758 mmc->card_caps |= MMC_MODE_DDR_52MHz;
3862b854 759 mmc->card_caps |= MMC_MODE_HS_52MHz;
d22e3d46 760 }
3862b854
JJH		 761 if (cardtype & EXT_CSD_CARD_TYPE_26)
762 mmc->card_caps |= MMC_MODE_HS;
272cc70b
AF		 763
764 return 0;
765}
766
f866a46d
SW		 767static int mmc_set_capacity(struct mmc *mmc, int part_num)
768{
769 switch (part_num) {
770 case 0:
771 mmc->capacity = mmc->capacity_user;
772 break;
773 case 1:
774 case 2:
775 mmc->capacity = mmc->capacity_boot;
776 break;
777 case 3:
778 mmc->capacity = mmc->capacity_rpmb;
779 break;
780 case 4:
781 case 5:
782 case 6:
783 case 7:
784 mmc->capacity = mmc->capacity_gp[part_num - 4];
785 break;
786 default:
787 return -1;
788 }
789
c40fdca6 790 mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
f866a46d
SW		 791
792 return 0;
793}
794
7dba0b93 795int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
bc897b1d 796{
f866a46d 797 int ret;
bc897b1d 798
f866a46d
SW		 799 ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
800 (mmc->part_config & ~PART_ACCESS_MASK)
801 | (part_num & PART_ACCESS_MASK));
f866a46d 802
6dc93e70
PB		 803 /*
804 * Set the capacity if the switch succeeded or was intended
805 * to return to representing the raw device.
806 */
873cc1d7 807 if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
6dc93e70 808 ret = mmc_set_capacity(mmc, part_num);
fdbb139f 809 mmc_get_blk_desc(mmc)->hwpart = part_num;
873cc1d7 810 }
6dc93e70
PB		 811
812 return ret;
bc897b1d
LW		 813}
814
ac9da0e0
DSC		 815int mmc_hwpart_config(struct mmc *mmc,
816 const struct mmc_hwpart_conf *conf,
817 enum mmc_hwpart_conf_mode mode)
818{
819 u8 part_attrs = 0;
820 u32 enh_size_mult;
821 u32 enh_start_addr;
822 u32 gp_size_mult[4];
823 u32 max_enh_size_mult;
824 u32 tot_enh_size_mult = 0;
8dda5b0e 825 u8 wr_rel_set;
ac9da0e0
DSC		 826 int i, pidx, err;
827 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
828
829 if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
830 return -EINVAL;
831
832 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
833 printf("eMMC >= 4.4 required for enhanced user data area\n");
834 return -EMEDIUMTYPE;
835 }
836
837 if (!(mmc->part_support & PART_SUPPORT)) {
838 printf("Card does not support partitioning\n");
839 return -EMEDIUMTYPE;
840 }
841
842 if (!mmc->hc_wp_grp_size) {
843 printf("Card does not define HC WP group size\n");
844 return -EMEDIUMTYPE;
845 }
846
847 /* check partition alignment and total enhanced size */
848 if (conf->user.enh_size) {
849 if (conf->user.enh_size % mmc->hc_wp_grp_size ||
850 conf->user.enh_start % mmc->hc_wp_grp_size) {
851 printf("User data enhanced area not HC WP group "
852 "size aligned\n");
853 return -EINVAL;
854 }
855 part_attrs |= EXT_CSD_ENH_USR;
856 enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
857 if (mmc->high_capacity) {
858 enh_start_addr = conf->user.enh_start;
859 } else {
860 enh_start_addr = (conf->user.enh_start << 9);
861 }
862 } else {
863 enh_size_mult = 0;
864 enh_start_addr = 0;
865 }
866 tot_enh_size_mult += enh_size_mult;
867
868 for (pidx = 0; pidx < 4; pidx++) {
869 if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
870 printf("GP%i partition not HC WP group size "
871 "aligned\n", pidx+1);
872 return -EINVAL;
873 }
874 gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
875 if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
876 part_attrs |= EXT_CSD_ENH_GP(pidx);
877 tot_enh_size_mult += gp_size_mult[pidx];
878 }
879 }
880
881 if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
882 printf("Card does not support enhanced attribute\n");
883 return -EMEDIUMTYPE;
884 }
885
886 err = mmc_send_ext_csd(mmc, ext_csd);
887 if (err)
888 return err;
889
890 max_enh_size_mult =
891 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
892 (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
893 ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
894 if (tot_enh_size_mult > max_enh_size_mult) {
895 printf("Total enhanced size exceeds maximum (%u > %u)\n",
896 tot_enh_size_mult, max_enh_size_mult);
897 return -EMEDIUMTYPE;
898 }
899
8dda5b0e
DSC		 900 /* The default value of EXT_CSD_WR_REL_SET is device
901 * dependent, the values can only be changed if the
902 * EXT_CSD_HS_CTRL_REL bit is set. The values can be
903 * changed only once and before partitioning is completed. */
904 wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
905 if (conf->user.wr_rel_change) {
906 if (conf->user.wr_rel_set)
907 wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
908 else
909 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
910 }
911 for (pidx = 0; pidx < 4; pidx++) {
912 if (conf->gp_part[pidx].wr_rel_change) {
913 if (conf->gp_part[pidx].wr_rel_set)
914 wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
915 else
916 wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
917 }
918 }
919
920 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
921 !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
922 puts("Card does not support host controlled partition write "
923 "reliability settings\n");
924 return -EMEDIUMTYPE;
925 }
926
ac9da0e0
DSC		 927 if (ext_csd[EXT_CSD_PARTITION_SETTING] &
928 EXT_CSD_PARTITION_SETTING_COMPLETED) {
929 printf("Card already partitioned\n");
930 return -EPERM;
931 }
932
933 if (mode == MMC_HWPART_CONF_CHECK)
934 return 0;
935
936 /* Partitioning requires high-capacity size definitions */
937 if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
938 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
939 EXT_CSD_ERASE_GROUP_DEF, 1);
940
941 if (err)
942 return err;
943
944 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
945
946 /* update erase group size to be high-capacity */
947 mmc->erase_grp_size =
948 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
949
950 }
951
952 /* all OK, write the configuration */
953 for (i = 0; i < 4; i++) {
954 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
955 EXT_CSD_ENH_START_ADDR+i,
956 (enh_start_addr >> (i*8)) & 0xFF);
957 if (err)
958 return err;
959 }
960 for (i = 0; i < 3; i++) {
961 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
962 EXT_CSD_ENH_SIZE_MULT+i,
963 (enh_size_mult >> (i*8)) & 0xFF);
964 if (err)
965 return err;
966 }
967 for (pidx = 0; pidx < 4; pidx++) {
968 for (i = 0; i < 3; i++) {
969 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
970 EXT_CSD_GP_SIZE_MULT+pidx*3+i,
971 (gp_size_mult[pidx] >> (i*8)) & 0xFF);
972 if (err)
973 return err;
974 }
975 }
976 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
977 EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
978 if (err)
979 return err;
980
981 if (mode == MMC_HWPART_CONF_SET)
982 return 0;
983
8dda5b0e
DSC		 984 /* The WR_REL_SET is a write-once register but shall be
985 * written before setting PART_SETTING_COMPLETED. As it is
986 * write-once we can only write it when completing the
987 * partitioning. */
988 if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
989 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
990 EXT_CSD_WR_REL_SET, wr_rel_set);
991 if (err)
992 return err;
993 }
994
ac9da0e0
DSC		 995 /* Setting PART_SETTING_COMPLETED confirms the partition
996 * configuration but it only becomes effective after power
997 * cycle, so we do not adjust the partition related settings
998 * in the mmc struct. */
999
1000 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1001 EXT_CSD_PARTITION_SETTING,
1002 EXT_CSD_PARTITION_SETTING_COMPLETED);
1003 if (err)
1004 return err;
1005
1006 return 0;
1007}
1008
e7881d85 1009#if !CONFIG_IS_ENABLED(DM_MMC)
48972d90
TR		 1010int mmc_getcd(struct mmc *mmc)
1011{
1012 int cd;
1013
1014 cd = board_mmc_getcd(mmc);
1015
d4e1da4e 1016 if (cd < 0) {
93bfd616
PA		 1017 if (mmc->cfg->ops->getcd)
1018 cd = mmc->cfg->ops->getcd(mmc);
d4e1da4e
PK		 1019 else
1020 cd = 1;
1021 }
48972d90
TR		 1022
1023 return cd;
1024}
8ca51e51 1025#endif
48972d90 1026
fdbb873e 1027static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
272cc70b
AF		 1028{
1029 struct mmc_cmd cmd;
1030 struct mmc_data data;
1031
1032 /* Switch the frequency */
1033 cmd.cmdidx = SD_CMD_SWITCH_FUNC;
1034 cmd.resp_type = MMC_RSP_R1;
1035 cmd.cmdarg = (mode << 31) | 0xffffff;
1036 cmd.cmdarg &= ~(0xf << (group * 4));
1037 cmd.cmdarg |= value << (group * 4);
272cc70b
AF		 1038
1039 data.dest = (char *)resp;
1040 data.blocksize = 64;
1041 data.blocks = 1;
1042 data.flags = MMC_DATA_READ;
1043
1044 return mmc_send_cmd(mmc, &cmd, &data);
1045}
1046
1047
d0c221fe 1048static int sd_get_capabilities(struct mmc *mmc)
272cc70b
AF		 1049{
1050 int err;
1051 struct mmc_cmd cmd;
18e7c8f6
SM		 1052 ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
1053 ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
272cc70b
AF		 1054 struct mmc_data data;
1055 int timeout;
c10b85d6 1056 u32 sd3_bus_mode;
272cc70b 1057
d0c221fe 1058 mmc->card_caps = MMC_MODE_1BIT;
272cc70b 1059
d52ebf10
TC		 1060 if (mmc_host_is_spi(mmc))
1061 return 0;
1062
272cc70b
AF		 1063 /* Read the SCR to find out if this card supports higher speeds */
1064 cmd.cmdidx = MMC_CMD_APP_CMD;
1065 cmd.resp_type = MMC_RSP_R1;
1066 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1067
1068 err = mmc_send_cmd(mmc, &cmd, NULL);
1069
1070 if (err)
1071 return err;
1072
1073 cmd.cmdidx = SD_CMD_APP_SEND_SCR;
1074 cmd.resp_type = MMC_RSP_R1;
1075 cmd.cmdarg = 0;
272cc70b
AF		 1076
1077 timeout = 3;
1078
1079retry_scr:
f781dd38 1080 data.dest = (char *)scr;
272cc70b
AF		 1081 data.blocksize = 8;
1082 data.blocks = 1;
1083 data.flags = MMC_DATA_READ;
1084
1085 err = mmc_send_cmd(mmc, &cmd, &data);
1086
1087 if (err) {
1088 if (timeout--)
1089 goto retry_scr;
1090
1091 return err;
1092 }
1093
4e3d89ba
YK		 1094 mmc->scr[0] = __be32_to_cpu(scr[0]);
1095 mmc->scr[1] = __be32_to_cpu(scr[1]);
272cc70b
AF		 1096
1097 switch ((mmc->scr[0] >> 24) & 0xf) {
53e8e40b
BM		 1098 case 0:
1099 mmc->version = SD_VERSION_1_0;
1100 break;
1101 case 1:
1102 mmc->version = SD_VERSION_1_10;
1103 break;
1104 case 2:
1105 mmc->version = SD_VERSION_2;
1106 if ((mmc->scr[0] >> 15) & 0x1)
1107 mmc->version = SD_VERSION_3;
1108 break;
1109 default:
1110 mmc->version = SD_VERSION_1_0;
1111 break;
272cc70b
AF		 1112 }
1113
b44c7083
AS		 1114 if (mmc->scr[0] & SD_DATA_4BIT)
1115 mmc->card_caps |= MMC_MODE_4BIT;
1116
272cc70b
AF		 1117 /* Version 1.0 doesn't support switching */
1118 if (mmc->version == SD_VERSION_1_0)
1119 return 0;
1120
1121 timeout = 4;
1122 while (timeout--) {
1123 err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
f781dd38 1124 (u8 *)switch_status);
272cc70b
AF		 1125
1126 if (err)
1127 return err;
1128
1129 /* The high-speed function is busy. Try again */
4e3d89ba 1130 if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
272cc70b
AF		 1131 break;
1132 }
1133
272cc70b 1134 /* If high-speed isn't supported, we return */
d0c221fe
JJH		 1135 if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
1136 mmc->card_caps |= MMC_CAP(SD_HS);
272cc70b 1137
c10b85d6
JJH		 1138 /* Version before 3.0 don't support UHS modes */
1139 if (mmc->version < SD_VERSION_3)
1140 return 0;
1141
1142 sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
1143 if (sd3_bus_mode & SD_MODE_UHS_SDR104)
1144 mmc->card_caps |= MMC_CAP(UHS_SDR104);
1145 if (sd3_bus_mode & SD_MODE_UHS_SDR50)
1146 mmc->card_caps |= MMC_CAP(UHS_SDR50);
1147 if (sd3_bus_mode & SD_MODE_UHS_SDR25)
1148 mmc->card_caps |= MMC_CAP(UHS_SDR25);
1149 if (sd3_bus_mode & SD_MODE_UHS_SDR12)
1150 mmc->card_caps |= MMC_CAP(UHS_SDR12);
1151 if (sd3_bus_mode & SD_MODE_UHS_DDR50)
1152 mmc->card_caps |= MMC_CAP(UHS_DDR50);
1153
d0c221fe
JJH		 1154 return 0;
1155}
1156
1157static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
1158{
1159 int err;
1160
1161 ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
c10b85d6 1162 int speed;
2c3fbf4c 1163
c10b85d6
JJH		 1164 switch (mode) {
1165 case SD_LEGACY:
1166 case UHS_SDR12:
1167 speed = UHS_SDR12_BUS_SPEED;
1168 break;
1169 case SD_HS:
1170 case UHS_SDR25:
1171 speed = UHS_SDR25_BUS_SPEED;
1172 break;
1173 case UHS_SDR50:
1174 speed = UHS_SDR50_BUS_SPEED;
1175 break;
1176 case UHS_DDR50:
1177 speed = UHS_DDR50_BUS_SPEED;
1178 break;
1179 case UHS_SDR104:
1180 speed = UHS_SDR104_BUS_SPEED;
1181 break;
1182 default:
1183 return -EINVAL;
1184 }
1185
1186 err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
d0c221fe
JJH		 1187 if (err)
1188 return err;
1189
c10b85d6 1190 if ((__be32_to_cpu(switch_status[4]) >> 24) != speed)
d0c221fe 1191 return -ENOTSUPP;
272cc70b 1192
d0c221fe
JJH		 1193 return 0;
1194}
1195
1196int sd_select_bus_width(struct mmc *mmc, int w)
1197{
1198 int err;
1199 struct mmc_cmd cmd;
1200
1201 if ((w != 4) && (w != 1))
1202 return -EINVAL;
1203
1204 cmd.cmdidx = MMC_CMD_APP_CMD;
1205 cmd.resp_type = MMC_RSP_R1;
1206 cmd.cmdarg = mmc->rca << 16;
1207
1208 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b
AF		 1209 if (err)
1210 return err;
1211
d0c221fe
JJH		 1212 cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
1213 cmd.resp_type = MMC_RSP_R1;
1214 if (w == 4)
1215 cmd.cmdarg = 2;
1216 else if (w == 1)
1217 cmd.cmdarg = 0;
1218 err = mmc_send_cmd(mmc, &cmd, NULL);
1219 if (err)
1220 return err;
272cc70b
AF		 1221
1222 return 0;
1223}
1224
3697e599
PF		 1225static int sd_read_ssr(struct mmc *mmc)
1226{
1227 int err, i;
1228 struct mmc_cmd cmd;
1229 ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
1230 struct mmc_data data;
1231 int timeout = 3;
1232 unsigned int au, eo, et, es;
1233
1234 cmd.cmdidx = MMC_CMD_APP_CMD;
1235 cmd.resp_type = MMC_RSP_R1;
1236 cmd.cmdarg = mmc->rca << 16;
1237
1238 err = mmc_send_cmd(mmc, &cmd, NULL);
1239 if (err)
1240 return err;
1241
1242 cmd.cmdidx = SD_CMD_APP_SD_STATUS;
1243 cmd.resp_type = MMC_RSP_R1;
1244 cmd.cmdarg = 0;
1245
1246retry_ssr:
1247 data.dest = (char *)ssr;
1248 data.blocksize = 64;
1249 data.blocks = 1;
1250 data.flags = MMC_DATA_READ;
1251
1252 err = mmc_send_cmd(mmc, &cmd, &data);
1253 if (err) {
1254 if (timeout--)
1255 goto retry_ssr;
1256
1257 return err;
1258 }
1259
1260 for (i = 0; i < 16; i++)
1261 ssr[i] = be32_to_cpu(ssr[i]);
1262
1263 au = (ssr[2] >> 12) & 0xF;
1264 if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
1265 mmc->ssr.au = sd_au_size[au];
1266 es = (ssr[3] >> 24) & 0xFF;
1267 es |= (ssr[2] & 0xFF) << 8;
1268 et = (ssr[3] >> 18) & 0x3F;
1269 if (es && et) {
1270 eo = (ssr[3] >> 16) & 0x3;
1271 mmc->ssr.erase_timeout = (et * 1000) / es;
1272 mmc->ssr.erase_offset = eo * 1000;
1273 }
1274 } else {
1275 debug("Invalid Allocation Unit Size.\n");
1276 }
1277
1278 return 0;
1279}
1280
272cc70b
AF		 1281/* frequency bases */
1282/* divided by 10 to be nice to platforms without floating point */
5f837c2c 1283static const int fbase[] = {
272cc70b
AF		 1284 10000,
1285 100000,
1286 1000000,
1287 10000000,
1288};
1289
1290/* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
1291 * to platforms without floating point.
1292 */
61fe076f 1293static const u8 multipliers[] = {
272cc70b
AF		 1294 0, /* reserved */
1295 10,
1296 12,
1297 13,
1298 15,
1299 20,
1300 25,
1301 30,
1302 35,
1303 40,
1304 45,
1305 50,
1306 55,
1307 60,
1308 70,
1309 80,
1310};
1311
d0c221fe
JJH		 1312static inline int bus_width(uint cap)
1313{
1314 if (cap == MMC_MODE_8BIT)
1315 return 8;
1316 if (cap == MMC_MODE_4BIT)
1317 return 4;
1318 if (cap == MMC_MODE_1BIT)
1319 return 1;
1320 printf("invalid bus witdh capability 0x%x\n", cap);
1321 return 0;
1322}
1323
e7881d85 1324#if !CONFIG_IS_ENABLED(DM_MMC)
ec841209
KVA		 1325static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
1326{
1327 return -ENOTSUPP;
1328}
1329
318a7a57
JJH		 1330static void mmc_send_init_stream(struct mmc *mmc)
1331{
1332}
1333
2a4d212f 1334static int mmc_set_ios(struct mmc *mmc)
272cc70b 1335{
2a4d212f
KVA		 1336 int ret = 0;
1337
93bfd616 1338 if (mmc->cfg->ops->set_ios)
2a4d212f
KVA		 1339 ret = mmc->cfg->ops->set_ios(mmc);
1340
1341 return ret;
272cc70b 1342}
8ca51e51 1343#endif
272cc70b 1344
35f67820 1345int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
272cc70b 1346{
93bfd616
PA		 1347 if (clock > mmc->cfg->f_max)
1348 clock = mmc->cfg->f_max;
272cc70b 1349
93bfd616
PA		 1350 if (clock < mmc->cfg->f_min)
1351 clock = mmc->cfg->f_min;
272cc70b
AF		 1352
1353 mmc->clock = clock;
35f67820 1354 mmc->clk_disable = disable;
272cc70b 1355
2a4d212f 1356 return mmc_set_ios(mmc);
272cc70b
AF		 1357}
1358
2a4d212f 1359static int mmc_set_bus_width(struct mmc *mmc, uint width)
272cc70b
AF		 1360{
1361 mmc->bus_width = width;
1362
2a4d212f 1363 return mmc_set_ios(mmc);
272cc70b
AF		 1364}
1365
4c9d2aaa
JJH		 1366#if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
1367/*
1368 * helper function to display the capabilities in a human
1369 * friendly manner. The capabilities include bus width and
1370 * supported modes.
1371 */
1372void mmc_dump_capabilities(const char *text, uint caps)
1373{
1374 enum bus_mode mode;
1375
1376 printf("%s: widths [", text);
1377 if (caps & MMC_MODE_8BIT)
1378 printf("8, ");
1379 if (caps & MMC_MODE_4BIT)
1380 printf("4, ");
d0c221fe
JJH		 1381 if (caps & MMC_MODE_1BIT)
1382 printf("1, ");
1383 printf("\b\b] modes [");
4c9d2aaa
JJH		 1384 for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
1385 if (MMC_CAP(mode) & caps)
1386 printf("%s, ", mmc_mode_name(mode));
1387 printf("\b\b]\n");
1388}
1389#endif
1390
d0c221fe
JJH		 1391struct mode_width_tuning {
1392 enum bus_mode mode;
1393 uint widths;
634d4849 1394 uint tuning;
d0c221fe
JJH		 1395};
1396
aff5d3c8
KVA		 1397static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
1398{
1399 mmc->signal_voltage = signal_voltage;
1400 return mmc_set_ios(mmc);
1401}
1402
d0c221fe 1403static const struct mode_width_tuning sd_modes_by_pref[] = {
c10b85d6
JJH		 1404 {
1405 .mode = UHS_SDR104,
1406 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1407 .tuning = MMC_CMD_SEND_TUNING_BLOCK
1408 },
1409 {
1410 .mode = UHS_SDR50,
1411 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1412 },
1413 {
1414 .mode = UHS_DDR50,
1415 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1416 },
1417 {
1418 .mode = UHS_SDR25,
1419 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1420 },
d0c221fe
JJH		 1421 {
1422 .mode = SD_HS,
1423 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1424 },
c10b85d6
JJH		 1425 {
1426 .mode = UHS_SDR12,
1427 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1428 },
d0c221fe
JJH		 1429 {
1430 .mode = SD_LEGACY,
1431 .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
1432 }
1433};
1434
1435#define for_each_sd_mode_by_pref(caps, mwt) \
1436 for (mwt = sd_modes_by_pref;\
1437 mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
1438 mwt++) \
1439 if (caps & MMC_CAP(mwt->mode))
1440
1441static int sd_select_mode_and_width(struct mmc *mmc)
8ac8a263
JJH		 1442{
1443 int err;
d0c221fe
JJH		 1444 uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
1445 const struct mode_width_tuning *mwt;
c10b85d6
JJH		 1446 bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
1447 uint caps;
1448
8ac8a263 1449
d0c221fe 1450 err = sd_get_capabilities(mmc);
8ac8a263
JJH		 1451 if (err)
1452 return err;
8ac8a263 1453 /* Restrict card's capabilities by what the host can do */
04a2ea24 1454 caps = mmc->card_caps & (mmc->host_caps | MMC_MODE_1BIT);
d0c221fe 1455
c10b85d6
JJH		 1456 if (!uhs_en)
1457 caps &= ~UHS_CAPS;
1458
1459 for_each_sd_mode_by_pref(caps, mwt) {
d0c221fe
JJH		 1460 uint *w;
1461
1462 for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
c10b85d6 1463 if (*w & caps & mwt->widths) {
d0c221fe
JJH		 1464 debug("trying mode %s width %d (at %d MHz)\n",
1465 mmc_mode_name(mwt->mode),
1466 bus_width(*w),
1467 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1468
1469 /* configure the bus width (card + host) */
1470 err = sd_select_bus_width(mmc, bus_width(*w));
1471 if (err)
1472 goto error;
1473 mmc_set_bus_width(mmc, bus_width(*w));
1474
1475 /* configure the bus mode (card) */
1476 err = sd_set_card_speed(mmc, mwt->mode);
1477 if (err)
1478 goto error;
1479
1480 /* configure the bus mode (host) */
1481 mmc_select_mode(mmc, mwt->mode);
35f67820 1482 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe 1483
c10b85d6
JJH		 1484 /* execute tuning if needed */
1485 if (mwt->tuning && !mmc_host_is_spi(mmc)) {
1486 err = mmc_execute_tuning(mmc,
1487 mwt->tuning);
1488 if (err) {
1489 debug("tuning failed\n");
1490 goto error;
1491 }
1492 }
1493
d0c221fe
JJH		 1494 err = sd_read_ssr(mmc);
1495 if (!err)
1496 return 0;
1497
1498 printf("bad ssr\n");
1499
1500error:
1501 /* revert to a safer bus speed */
1502 mmc_select_mode(mmc, SD_LEGACY);
35f67820 1503 mmc_set_clock(mmc, mmc->tran_speed, false);
d0c221fe
JJH		 1504 }
1505 }
8ac8a263
JJH		 1506 }
1507
d0c221fe
JJH		 1508 printf("unable to select a mode\n");
1509 return -ENOTSUPP;
8ac8a263
JJH		 1510}
1511
7382e691
JJH		 1512/*
1513 * read the compare the part of ext csd that is constant.
1514 * This can be used to check that the transfer is working
1515 * as expected.
1516 */
1517static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
8ac8a263 1518{
7382e691 1519 int err;
dfda9d88 1520 const u8 *ext_csd = mmc->ext_csd;
7382e691
JJH		 1521 ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
1522
1523 err = mmc_send_ext_csd(mmc, test_csd);
1524 if (err)
1525 return err;
1526
1527 /* Only compare read only fields */
1528 if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
1529 == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
1530 ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
1531 == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
1532 ext_csd[EXT_CSD_REV]
1533 == test_csd[EXT_CSD_REV] &&
1534 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1535 == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
1536 memcmp(&ext_csd[EXT_CSD_SEC_CNT],
1537 &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
1538 return 0;
1539
1540 return -EBADMSG;
1541}
1542
3862b854
JJH		 1543static const struct mode_width_tuning mmc_modes_by_pref[] = {
1544 {
1545 .mode = MMC_HS_200,
1546 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
634d4849 1547 .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
3862b854
JJH		 1548 },
1549 {
1550 .mode = MMC_DDR_52,
1551 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
1552 },
1553 {
1554 .mode = MMC_HS_52,
1555 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1556 },
1557 {
1558 .mode = MMC_HS,
1559 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1560 },
1561 {
1562 .mode = MMC_LEGACY,
1563 .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
1564 }
1565};
1566
1567#define for_each_mmc_mode_by_pref(caps, mwt) \
1568 for (mwt = mmc_modes_by_pref;\
1569 mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
1570 mwt++) \
1571 if (caps & MMC_CAP(mwt->mode))
1572
1573static const struct ext_csd_bus_width {
1574 uint cap;
1575 bool is_ddr;
1576 uint ext_csd_bits;
1577} ext_csd_bus_width[] = {
1578 {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
1579 {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
1580 {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
1581 {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
1582 {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
1583};
1584
1585#define for_each_supported_width(caps, ddr, ecbv) \
1586 for (ecbv = ext_csd_bus_width;\
1587 ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
1588 ecbv++) \
1589 if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
1590
1591static int mmc_select_mode_and_width(struct mmc *mmc)
7382e691 1592{
8ac8a263 1593 int err;
3862b854
JJH		 1594 const struct mode_width_tuning *mwt;
1595 const struct ext_csd_bus_width *ecbw;
8ac8a263 1596
3862b854 1597 err = mmc_get_capabilities(mmc);
8ac8a263
JJH		 1598 if (err)
1599 return err;
1600
1601 /* Restrict card's capabilities by what the host can do */
04a2ea24 1602 mmc->card_caps &= (mmc->host_caps | MMC_MODE_1BIT);
8ac8a263
JJH		 1603
1604 /* Only version 4 of MMC supports wider bus widths */
1605 if (mmc->version < MMC_VERSION_4)
1606 return 0;
1607
dfda9d88
JJH		 1608 if (!mmc->ext_csd) {
1609 debug("No ext_csd found!\n"); /* this should enver happen */
1610 return -ENOTSUPP;
1611 }
1612
3862b854
JJH		 1613 for_each_mmc_mode_by_pref(mmc->card_caps, mwt) {
1614 for_each_supported_width(mmc->card_caps & mwt->widths,
1615 mmc_is_mode_ddr(mwt->mode), ecbw) {
1616 debug("trying mode %s width %d (at %d MHz)\n",
1617 mmc_mode_name(mwt->mode),
1618 bus_width(ecbw->cap),
1619 mmc_mode2freq(mmc, mwt->mode) / 1000000);
1620 /* configure the bus width (card + host) */
1621 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1622 EXT_CSD_BUS_WIDTH,
1623 ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
1624 if (err)
1625 goto error;
1626 mmc_set_bus_width(mmc, bus_width(ecbw->cap));
8ac8a263 1627
3862b854
JJH		 1628 /* configure the bus speed (card) */
1629 err = mmc_set_card_speed(mmc, mwt->mode);
1630 if (err)
1631 goto error;
1632
1633 /*
1634 * configure the bus width AND the ddr mode (card)
1635 * The host side will be taken care of in the next step
1636 */
1637 if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
1638 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1639 EXT_CSD_BUS_WIDTH,
1640 ecbw->ext_csd_bits);
1641 if (err)
1642 goto error;
1643 }
8ac8a263 1644
3862b854
JJH		 1645 /* configure the bus mode (host) */
1646 mmc_select_mode(mmc, mwt->mode);
35f67820 1647 mmc_set_clock(mmc, mmc->tran_speed, false);
8ac8a263 1648
634d4849
KVA		 1649 /* execute tuning if needed */
1650 if (mwt->tuning) {
1651 err = mmc_execute_tuning(mmc, mwt->tuning);
1652 if (err) {
1653 debug("tuning failed\n");
1654 goto error;
1655 }
1656 }
1657
3862b854
JJH		 1658 /* do a transfer to check the configuration */
1659 err = mmc_read_and_compare_ext_csd(mmc);
1660 if (!err)
1661 return 0;
1662error:
1663 /* if an error occured, revert to a safer bus mode */
1664 mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1665 EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
1666 mmc_select_mode(mmc, MMC_LEGACY);
1667 mmc_set_bus_width(mmc, 1);
1668 }
8ac8a263
JJH		 1669 }
1670
3862b854 1671 printf("unable to select a mode\n");
8ac8a263 1672
3862b854 1673 return -ENOTSUPP;
8ac8a263
JJH		 1674}
1675
dfda9d88 1676static int mmc_startup_v4(struct mmc *mmc)
c744b6f6
JJH		 1677{
1678 int err, i;
1679 u64 capacity;
1680 bool has_parts = false;
1681 bool part_completed;
dfda9d88 1682 u8 *ext_csd;
c744b6f6
JJH		 1683
1684 if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
1685 return 0;
1686
dfda9d88
JJH		 1687 ext_csd = malloc_cache_aligned(MMC_MAX_BLOCK_LEN);
1688 if (!ext_csd)
1689 return -ENOMEM;
1690
1691 mmc->ext_csd = ext_csd;
1692
c744b6f6
JJH		 1693 /* check ext_csd version and capacity */
1694 err = mmc_send_ext_csd(mmc, ext_csd);
1695 if (err)
1696 return err;
1697 if (ext_csd[EXT_CSD_REV] >= 2) {
1698 /*
1699 * According to the JEDEC Standard, the value of
1700 * ext_csd's capacity is valid if the value is more
1701 * than 2GB
1702 */
1703 capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
1704 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
1705 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
1706 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
1707 capacity *= MMC_MAX_BLOCK_LEN;
1708 if ((capacity >> 20) > 2 * 1024)
1709 mmc->capacity_user = capacity;
1710 }
1711
1712 switch (ext_csd[EXT_CSD_REV]) {
1713 case 1:
1714 mmc->version = MMC_VERSION_4_1;
1715 break;
1716 case 2:
1717 mmc->version = MMC_VERSION_4_2;
1718 break;
1719 case 3:
1720 mmc->version = MMC_VERSION_4_3;
1721 break;
1722 case 5:
1723 mmc->version = MMC_VERSION_4_41;
1724 break;
1725 case 6:
1726 mmc->version = MMC_VERSION_4_5;
1727 break;
1728 case 7:
1729 mmc->version = MMC_VERSION_5_0;
1730 break;
1731 case 8:
1732 mmc->version = MMC_VERSION_5_1;
1733 break;
1734 }
1735
1736 /* The partition data may be non-zero but it is only
1737 * effective if PARTITION_SETTING_COMPLETED is set in
1738 * EXT_CSD, so ignore any data if this bit is not set,
1739 * except for enabling the high-capacity group size
1740 * definition (see below).
1741 */
1742 part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
1743 EXT_CSD_PARTITION_SETTING_COMPLETED);
1744
1745 /* store the partition info of emmc */
1746 mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
1747 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
1748 ext_csd[EXT_CSD_BOOT_MULT])
1749 mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
1750 if (part_completed &&
1751 (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
1752 mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
1753
1754 mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
1755
1756 mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
1757
1758 for (i = 0; i < 4; i++) {
1759 int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
1760 uint mult = (ext_csd[idx + 2] << 16) +
1761 (ext_csd[idx + 1] << 8) + ext_csd[idx];
1762 if (mult)
1763 has_parts = true;
1764 if (!part_completed)
1765 continue;
1766 mmc->capacity_gp[i] = mult;
1767 mmc->capacity_gp[i] *=
1768 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1769 mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1770 mmc->capacity_gp[i] <<= 19;
1771 }
1772
1773 if (part_completed) {
1774 mmc->enh_user_size =
1775 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
1776 (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
1777 ext_csd[EXT_CSD_ENH_SIZE_MULT];
1778 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
1779 mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1780 mmc->enh_user_size <<= 19;
1781 mmc->enh_user_start =
1782 (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
1783 (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
1784 (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
1785 ext_csd[EXT_CSD_ENH_START_ADDR];
1786 if (mmc->high_capacity)
1787 mmc->enh_user_start <<= 9;
1788 }
1789
1790 /*
1791 * Host needs to enable ERASE_GRP_DEF bit if device is
1792 * partitioned. This bit will be lost every time after a reset
1793 * or power off. This will affect erase size.
1794 */
1795 if (part_completed)
1796 has_parts = true;
1797 if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
1798 (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
1799 has_parts = true;
1800 if (has_parts) {
1801 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
1802 EXT_CSD_ERASE_GROUP_DEF, 1);
1803
1804 if (err)
1805 return err;
1806
1807 ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
1808 }
1809
1810 if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
1811 /* Read out group size from ext_csd */
1812 mmc->erase_grp_size =
1813 ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
1814 /*
1815 * if high capacity and partition setting completed
1816 * SEC_COUNT is valid even if it is smaller than 2 GiB
1817 * JEDEC Standard JESD84-B45, 6.2.4
1818 */
1819 if (mmc->high_capacity && part_completed) {
1820 capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
1821 (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
1822 (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
1823 (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
1824 capacity *= MMC_MAX_BLOCK_LEN;
1825 mmc->capacity_user = capacity;
1826 }
1827 } else {
1828 /* Calculate the group size from the csd value. */
1829 int erase_gsz, erase_gmul;
1830
1831 erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
1832 erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
1833 mmc->erase_grp_size = (erase_gsz + 1)
1834 * (erase_gmul + 1);
1835 }
1836
1837 mmc->hc_wp_grp_size = 1024
1838 * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
1839 * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
1840
1841 mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
1842
1843 return 0;
1844}
1845
fdbb873e 1846static int mmc_startup(struct mmc *mmc)
272cc70b 1847{
f866a46d 1848 int err, i;
272cc70b 1849 uint mult, freq;
c744b6f6 1850 u64 cmult, csize;
272cc70b 1851 struct mmc_cmd cmd;
c40fdca6 1852 struct blk_desc *bdesc;
272cc70b 1853
d52ebf10
TC		 1854#ifdef CONFIG_MMC_SPI_CRC_ON
1855 if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
1856 cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
1857 cmd.resp_type = MMC_RSP_R1;
1858 cmd.cmdarg = 1;
d52ebf10
TC		 1859 err = mmc_send_cmd(mmc, &cmd, NULL);
1860
1861 if (err)
1862 return err;
1863 }
1864#endif
1865
272cc70b 1866 /* Put the Card in Identify Mode */
d52ebf10
TC		 1867 cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
1868 MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
272cc70b
AF		 1869 cmd.resp_type = MMC_RSP_R2;
1870 cmd.cmdarg = 0;
272cc70b
AF		 1871
1872 err = mmc_send_cmd(mmc, &cmd, NULL);
1873
1874 if (err)
1875 return err;
1876
1877 memcpy(mmc->cid, cmd.response, 16);
1878
1879 /*
1880 * For MMC cards, set the Relative Address.
1881 * For SD cards, get the Relatvie Address.
1882 * This also puts the cards into Standby State
1883 */
d52ebf10
TC		 1884 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1885 cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
1886 cmd.cmdarg = mmc->rca << 16;
1887 cmd.resp_type = MMC_RSP_R6;
272cc70b 1888
d52ebf10 1889 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1890
d52ebf10
TC		 1891 if (err)
1892 return err;
272cc70b 1893
d52ebf10
TC		 1894 if (IS_SD(mmc))
1895 mmc->rca = (cmd.response[0] >> 16) & 0xffff;
1896 }
272cc70b
AF		 1897
1898 /* Get the Card-Specific Data */
1899 cmd.cmdidx = MMC_CMD_SEND_CSD;
1900 cmd.resp_type = MMC_RSP_R2;
1901 cmd.cmdarg = mmc->rca << 16;
272cc70b
AF		 1902
1903 err = mmc_send_cmd(mmc, &cmd, NULL);
1904
1905 if (err)
1906 return err;
1907
998be3dd
RV		 1908 mmc->csd[0] = cmd.response[0];
1909 mmc->csd[1] = cmd.response[1];
1910 mmc->csd[2] = cmd.response[2];
1911 mmc->csd[3] = cmd.response[3];
272cc70b
AF		 1912
1913 if (mmc->version == MMC_VERSION_UNKNOWN) {
0b453ffe 1914 int version = (cmd.response[0] >> 26) & 0xf;
272cc70b
AF		 1915
1916 switch (version) {
53e8e40b
BM		 1917 case 0:
1918 mmc->version = MMC_VERSION_1_2;
1919 break;
1920 case 1:
1921 mmc->version = MMC_VERSION_1_4;
1922 break;
1923 case 2:
1924 mmc->version = MMC_VERSION_2_2;
1925 break;
1926 case 3:
1927 mmc->version = MMC_VERSION_3;
1928 break;
1929 case 4:
1930 mmc->version = MMC_VERSION_4;
1931 break;
1932 default:
1933 mmc->version = MMC_VERSION_1_2;
1934 break;
272cc70b
AF		 1935 }
1936 }
1937
1938 /* divide frequency by 10, since the mults are 10x bigger */
0b453ffe
RV		 1939 freq = fbase[(cmd.response[0] & 0x7)];
1940 mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
272cc70b 1941
35f9e196 1942 mmc->legacy_speed = freq * mult;
35f9e196 1943 mmc_select_mode(mmc, MMC_LEGACY);
272cc70b 1944
ab71188c 1945 mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
998be3dd 1946 mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
272cc70b
AF		 1947
1948 if (IS_SD(mmc))
1949 mmc->write_bl_len = mmc->read_bl_len;
1950 else
998be3dd 1951 mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
272cc70b
AF		 1952
1953 if (mmc->high_capacity) {
1954 csize = (mmc->csd[1] & 0x3f) << 16
1955 | (mmc->csd[2] & 0xffff0000) >> 16;
1956 cmult = 8;
1957 } else {
1958 csize = (mmc->csd[1] & 0x3ff) << 2
1959 | (mmc->csd[2] & 0xc0000000) >> 30;
1960 cmult = (mmc->csd[2] & 0x00038000) >> 15;
1961 }
1962
f866a46d
SW		 1963 mmc->capacity_user = (csize + 1) << (cmult + 2);
1964 mmc->capacity_user *= mmc->read_bl_len;
1965 mmc->capacity_boot = 0;
1966 mmc->capacity_rpmb = 0;
1967 for (i = 0; i < 4; i++)
1968 mmc->capacity_gp[i] = 0;
272cc70b 1969
8bfa195e
SG		 1970 if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
1971 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1972
8bfa195e
SG		 1973 if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
1974 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
272cc70b 1975
ab71188c
MN		 1976 if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
1977 cmd.cmdidx = MMC_CMD_SET_DSR;
1978 cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
1979 cmd.resp_type = MMC_RSP_NONE;
1980 if (mmc_send_cmd(mmc, &cmd, NULL))
1981 printf("MMC: SET_DSR failed\n");
1982 }
1983
272cc70b 1984 /* Select the card, and put it into Transfer Mode */
d52ebf10
TC		 1985 if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
1986 cmd.cmdidx = MMC_CMD_SELECT_CARD;
fe8f7066 1987 cmd.resp_type = MMC_RSP_R1;
d52ebf10 1988 cmd.cmdarg = mmc->rca << 16;
d52ebf10 1989 err = mmc_send_cmd(mmc, &cmd, NULL);
272cc70b 1990
d52ebf10
TC		 1991 if (err)
1992 return err;
1993 }
272cc70b 1994
e6f99a56
LW		 1995 /*
1996 * For SD, its erase group is always one sector
1997 */
1998 mmc->erase_grp_size = 1;
bc897b1d 1999 mmc->part_config = MMCPART_NOAVAILABLE;
1937e5aa 2000
dfda9d88 2001 err = mmc_startup_v4(mmc);
c744b6f6
JJH		 2002 if (err)
2003 return err;
d23e2c09 2004
c40fdca6 2005 err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
f866a46d
SW		 2006 if (err)
2007 return err;
2008
272cc70b 2009 if (IS_SD(mmc))
d0c221fe 2010 err = sd_select_mode_and_width(mmc);
272cc70b 2011 else
3862b854 2012 err = mmc_select_mode_and_width(mmc);
272cc70b
AF		 2013
2014 if (err)
2015 return err;
2016
ad5fd922 2017
5af8f45c
AG		 2018 /* Fix the block length for DDR mode */
2019 if (mmc->ddr_mode) {
2020 mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
2021 mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
2022 }
2023
272cc70b 2024 /* fill in device description */
c40fdca6
SG		 2025 bdesc = mmc_get_blk_desc(mmc);
2026 bdesc->lun = 0;
2027 bdesc->hwpart = 0;
2028 bdesc->type = 0;
2029 bdesc->blksz = mmc->read_bl_len;
2030 bdesc->log2blksz = LOG2(bdesc->blksz);
2031 bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
fc011f64
SS		 2032#if !defined(CONFIG_SPL_BUILD) || \
2033 (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
2034 !defined(CONFIG_USE_TINY_PRINTF))
c40fdca6 2035 sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
babce5f6
TH		 2036 mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
2037 (mmc->cid[3] >> 16) & 0xffff);
c40fdca6 2038 sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
babce5f6
TH		 2039 (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
2040 (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
2041 (mmc->cid[2] >> 24) & 0xff);
c40fdca6 2042 sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
babce5f6 2043 (mmc->cid[2] >> 16) & 0xf);
56196826 2044#else
c40fdca6
SG		 2045 bdesc->vendor[0] = 0;
2046 bdesc->product[0] = 0;
2047 bdesc->revision[0] = 0;
56196826 2048#endif
122efd43 2049#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT)
c40fdca6 2050 part_init(bdesc);
122efd43 2051#endif
272cc70b
AF		 2052
2053 return 0;
2054}
2055
fdbb873e 2056static int mmc_send_if_cond(struct mmc *mmc)
272cc70b
AF		 2057{
2058 struct mmc_cmd cmd;
2059 int err;
2060
2061 cmd.cmdidx = SD_CMD_SEND_IF_COND;
2062 /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
93bfd616 2063 cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
272cc70b 2064 cmd.resp_type = MMC_RSP_R7;
272cc70b
AF		 2065
2066 err = mmc_send_cmd(mmc, &cmd, NULL);
2067
2068 if (err)
2069 return err;
2070
998be3dd 2071 if ((cmd.response[0] & 0xff) != 0xaa)
915ffa52 2072 return -EOPNOTSUPP;
272cc70b
AF		 2073 else
2074 mmc->version = SD_VERSION_2;
2075
2076 return 0;
2077}
2078
c4d660d4 2079#if !CONFIG_IS_ENABLED(DM_MMC)
95de9ab2
PK		 2080/* board-specific MMC power initializations. */
2081__weak void board_mmc_power_init(void)
2082{
2083}
05cbeb7c 2084#endif
95de9ab2 2085
2051aefe
PF		 2086static int mmc_power_init(struct mmc *mmc)
2087{
c4d660d4 2088#if CONFIG_IS_ENABLED(DM_MMC)
06ec045f 2089#if CONFIG_IS_ENABLED(DM_REGULATOR)
2051aefe
PF		 2090 int ret;
2091
2092 ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
06ec045f
JJH		 2093 &mmc->vmmc_supply);
2094 if (ret)
288db7c7 2095 debug("%s: No vmmc supply\n", mmc->dev->name);
2051aefe 2096
06ec045f
JJH		 2097 ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
2098 &mmc->vqmmc_supply);
2099 if (ret)
2100 debug("%s: No vqmmc supply\n", mmc->dev->name);
fb7c3beb
KVA		 2101#endif
2102#else /* !CONFIG_DM_MMC */
2103 /*
2104 * Driver model should use a regulator, as above, rather than calling
2105 * out to board code.
2106 */
2107 board_mmc_power_init();
2108#endif
2109 return 0;
2110}
2111
2112/*
2113 * put the host in the initial state:
2114 * - turn on Vdd (card power supply)
2115 * - configure the bus width and clock to minimal values
2116 */
2117static void mmc_set_initial_state(struct mmc *mmc)
2118{
2119 int err;
2120
2121 /* First try to set 3.3V. If it fails set to 1.8V */
2122 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
2123 if (err != 0)
2124 err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
2125 if (err != 0)
2126 printf("mmc: failed to set signal voltage\n");
2127
2128 mmc_select_mode(mmc, MMC_LEGACY);
2129 mmc_set_bus_width(mmc, 1);
35f67820 2130 mmc_set_clock(mmc, 0, false);
fb7c3beb 2131}
06ec045f 2132
fb7c3beb
KVA		 2133static int mmc_power_on(struct mmc *mmc)
2134{
2135#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
06ec045f 2136 if (mmc->vmmc_supply) {
fb7c3beb
KVA		 2137 int ret = regulator_set_enable(mmc->vmmc_supply, true);
2138
06ec045f
JJH		 2139 if (ret) {
2140 puts("Error enabling VMMC supply\n");
2141 return ret;
2142 }
2051aefe 2143 }
05cbeb7c 2144#endif
fb7c3beb
KVA		 2145 return 0;
2146}
2147
2148static int mmc_power_off(struct mmc *mmc)
2149{
2e7410d7 2150 mmc_set_clock(mmc, 1, true);
fb7c3beb
KVA		 2151#if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
2152 if (mmc->vmmc_supply) {
2153 int ret = regulator_set_enable(mmc->vmmc_supply, false);
2154
2155 if (ret) {
c10b85d6 2156 debug("Error disabling VMMC supply\n");
fb7c3beb
KVA		 2157 return ret;
2158 }
2159 }
2051aefe
PF		 2160#endif
2161 return 0;
2162}
2163
fb7c3beb
KVA		 2164static int mmc_power_cycle(struct mmc *mmc)
2165{
2166 int ret;
2167
2168 ret = mmc_power_off(mmc);
2169 if (ret)
2170 return ret;
2171 /*
2172 * SD spec recommends at least 1ms of delay. Let's wait for 2ms
2173 * to be on the safer side.
2174 */
2175 udelay(2000);
2176 return mmc_power_on(mmc);
2177}
2178
e9550449 2179int mmc_start_init(struct mmc *mmc)
272cc70b 2180{
8ca51e51 2181 bool no_card;
c10b85d6 2182 bool uhs_en = supports_uhs(mmc->cfg->host_caps);
afd5932b 2183 int err;
272cc70b 2184
04a2ea24
JJH		 2185 mmc->host_caps = mmc->cfg->host_caps;
2186
ab769f22 2187 /* we pretend there's no card when init is NULL */
8ca51e51 2188 no_card = mmc_getcd(mmc) == 0;
e7881d85 2189#if !CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2190 no_card = no_card || (mmc->cfg->ops->init == NULL);
2191#endif
2192 if (no_card) {
48972d90 2193 mmc->has_init = 0;
56196826 2194#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
48972d90 2195 printf("MMC: no card present\n");
56196826 2196#endif
915ffa52 2197 return -ENOMEDIUM;
48972d90
TR		 2198 }
2199
bc897b1d
LW		 2200 if (mmc->has_init)
2201 return 0;
2202
5a8dbdc6
YL		 2203#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
2204 mmc_adapter_card_type_ident();
2205#endif
2051aefe
PF		 2206 err = mmc_power_init(mmc);
2207 if (err)
2208 return err;
95de9ab2 2209
04a2ea24
JJH		 2210 err = mmc_power_cycle(mmc);
2211 if (err) {
2212 /*
2213 * if power cycling is not supported, we should not try
2214 * to use the UHS modes, because we wouldn't be able to
2215 * recover from an error during the UHS initialization.
2216 */
2217 debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
2218 uhs_en = false;
2219 mmc->host_caps &= ~UHS_CAPS;
2220 err = mmc_power_on(mmc);
2221 }
fb7c3beb
KVA		 2222 if (err)
2223 return err;
2224
e7881d85 2225#if CONFIG_IS_ENABLED(DM_MMC)
8ca51e51
SG		 2226 /* The device has already been probed ready for use */
2227#else
ab769f22 2228 /* made sure it's not NULL earlier */
93bfd616 2229 err = mmc->cfg->ops->init(mmc);
272cc70b
AF		 2230 if (err)
2231 return err;
8ca51e51 2232#endif
786e8f81 2233 mmc->ddr_mode = 0;
aff5d3c8 2234
c10b85d6 2235retry:
fb7c3beb 2236 mmc_set_initial_state(mmc);
318a7a57
JJH		 2237 mmc_send_init_stream(mmc);
2238
272cc70b
AF		 2239 /* Reset the Card */
2240 err = mmc_go_idle(mmc);
2241
2242 if (err)
2243 return err;
2244
bc897b1d 2245 /* The internal partition reset to user partition(0) at every CMD0*/
c40fdca6 2246 mmc_get_blk_desc(mmc)->hwpart = 0;
bc897b1d 2247
272cc70b 2248 /* Test for SD version 2 */
afd5932b 2249 err = mmc_send_if_cond(mmc);
272cc70b 2250
272cc70b 2251 /* Now try to get the SD card's operating condition */
c10b85d6
JJH		 2252 err = sd_send_op_cond(mmc, uhs_en);
2253 if (err && uhs_en) {
2254 uhs_en = false;
2255 mmc_power_cycle(mmc);
2256 goto retry;
2257 }
272cc70b
AF		 2258
2259 /* If the command timed out, we check for an MMC card */
915ffa52 2260 if (err == -ETIMEDOUT) {
272cc70b
AF		 2261 err = mmc_send_op_cond(mmc);
2262
bd47c135 2263 if (err) {
56196826 2264#if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
272cc70b 2265 printf("Card did not respond to voltage select!\n");
56196826 2266#endif
915ffa52 2267 return -EOPNOTSUPP;
272cc70b
AF		 2268 }
2269 }
2270
bd47c135 2271 if (!err)
e9550449
CLC		 2272 mmc->init_in_progress = 1;
2273
2274 return err;
2275}
2276
2277static int mmc_complete_init(struct mmc *mmc)
2278{
2279 int err = 0;
2280
bd47c135 2281 mmc->init_in_progress = 0;
e9550449
CLC		 2282 if (mmc->op_cond_pending)
2283 err = mmc_complete_op_cond(mmc);
2284
2285 if (!err)
2286 err = mmc_startup(mmc);
bc897b1d
LW		 2287 if (err)
2288 mmc->has_init = 0;
2289 else
2290 mmc->has_init = 1;
e9550449
CLC		 2291 return err;
2292}
2293
2294int mmc_init(struct mmc *mmc)
2295{
bd47c135 2296 int err = 0;
ce9eca94 2297 __maybe_unused unsigned start;
c4d660d4 2298#if CONFIG_IS_ENABLED(DM_MMC)
33fb211d 2299 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
e9550449 2300
33fb211d
SG		 2301 upriv->mmc = mmc;
2302#endif
e9550449
CLC		 2303 if (mmc->has_init)
2304 return 0;
d803fea5
MZ		 2305
2306 start = get_timer(0);
2307
e9550449
CLC		 2308 if (!mmc->init_in_progress)
2309 err = mmc_start_init(mmc);
2310
bd47c135 2311 if (!err)
e9550449 2312 err = mmc_complete_init(mmc);
919b4858
JT		 2313 if (err)
2314 printf("%s: %d, time %lu\n", __func__, err, get_timer(start));
2315
bc897b1d 2316 return err;
272cc70b
AF		 2317}
2318
ab71188c
MN		 2319int mmc_set_dsr(struct mmc *mmc, u16 val)
2320{
2321 mmc->dsr = val;
2322 return 0;
2323}
2324
cee9ab7c
JH		 2325/* CPU-specific MMC initializations */
2326__weak int cpu_mmc_init(bd_t *bis)
272cc70b
AF		 2327{
2328 return -1;
2329}
2330
cee9ab7c
JH		 2331/* board-specific MMC initializations. */
2332__weak int board_mmc_init(bd_t *bis)
2333{
2334 return -1;
2335}
272cc70b 2336
e9550449
CLC		 2337void mmc_set_preinit(struct mmc *mmc, int preinit)
2338{
2339 mmc->preinit = preinit;
2340}
2341
c4d660d4 2342#if CONFIG_IS_ENABLED(DM_MMC) && defined(CONFIG_SPL_BUILD)
8e3332e2
SS		 2343static int mmc_probe(bd_t *bis)
2344{
2345 return 0;
2346}
c4d660d4 2347#elif CONFIG_IS_ENABLED(DM_MMC)
8e3332e2
SS		 2348static int mmc_probe(bd_t *bis)
2349{
4a1db6d8 2350 int ret, i;
8e3332e2 2351 struct uclass *uc;
4a1db6d8 2352 struct udevice *dev;
8e3332e2
SS		 2353
2354 ret = uclass_get(UCLASS_MMC, &uc);
2355 if (ret)
2356 return ret;
2357
4a1db6d8
SG		 2358 /*
2359 * Try to add them in sequence order. Really with driver model we
2360 * should allow holes, but the current MMC list does not allow that.
2361 * So if we request 0, 1, 3 we will get 0, 1, 2.
2362 */
2363 for (i = 0; ; i++) {
2364 ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
2365 if (ret == -ENODEV)
2366 break;
2367 }
2368 uclass_foreach_dev(dev, uc) {
2369 ret = device_probe(dev);
8e3332e2 2370 if (ret)
4a1db6d8 2371 printf("%s - probe failed: %d\n", dev->name, ret);
8e3332e2
SS		 2372 }
2373
2374 return 0;
2375}
2376#else
2377static int mmc_probe(bd_t *bis)
2378{
2379 if (board_mmc_init(bis) < 0)
2380 cpu_mmc_init(bis);
2381
2382 return 0;
2383}
2384#endif
e9550449 2385
272cc70b
AF		 2386int mmc_initialize(bd_t *bis)
2387{
1b26bab1 2388 static int initialized = 0;
8e3332e2 2389 int ret;
1b26bab1
DK		 2390 if (initialized) /* Avoid initializing mmc multiple times */
2391 return 0;
2392 initialized = 1;
2393
c4d660d4 2394#if !CONFIG_IS_ENABLED(BLK)
b5b838f1 2395#if !CONFIG_IS_ENABLED(MMC_TINY)
c40fdca6 2396 mmc_list_init();
b5b838f1 2397#endif
c40fdca6 2398#endif
8e3332e2
SS		 2399 ret = mmc_probe(bis);
2400 if (ret)
2401 return ret;
272cc70b 2402
bb0dc108 2403#ifndef CONFIG_SPL_BUILD
272cc70b 2404 print_mmc_devices(',');
bb0dc108 2405#endif
272cc70b 2406
c40fdca6 2407 mmc_do_preinit();
272cc70b
AF		 2408 return 0;
2409}
cd3d4880
TM		 2410
2411#ifdef CONFIG_CMD_BKOPS_ENABLE
2412int mmc_set_bkops_enable(struct mmc *mmc)
2413{
2414 int err;
2415 ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
2416
2417 err = mmc_send_ext_csd(mmc, ext_csd);
2418 if (err) {
2419 puts("Could not get ext_csd register values\n");
2420 return err;
2421 }
2422
2423 if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
2424 puts("Background operations not supported on device\n");
2425 return -EMEDIUMTYPE;
2426 }
2427
2428 if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
2429 puts("Background operations already enabled\n");
2430 return 0;
2431 }
2432
2433 err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
2434 if (err) {
2435 puts("Failed to enable manual background operations\n");
2436 return err;
2437 }
2438
2439 puts("Enabled manual background operations\n");
2440
2441 return 0;
2442}
2443#endif
"Das U-Boot" Source Tree