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2e3d4f4d
MF		 12016-01-06 Mike Frysinger <vapier@gentoo.org>
2
3 * interp.c (sim_open): Mark argv const.
4 (sim_create_inferior): Mark argv and env const.
5
9bbf6f91
MF		 62016-01-04 Mike Frysinger <vapier@gentoo.org>
7
8 * configure: Regenerate.
9
77cf2ef5
MF		 102016-01-03 Mike Frysinger <vapier@gentoo.org>
11
12 * interp.c (sim_open): Update sim_parse_args comment.
13
0cb8d851
MF		 142016-01-03 Mike Frysinger <vapier@gentoo.org>
15
16 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
17 * configure: Regenerate.
18
1ac72f06
MF		 192016-01-02 Mike Frysinger <vapier@gentoo.org>
20
21 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
22 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
23 * configure: Regenerate.
24 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
25
d47f5b30
MF		 262016-01-02 Mike Frysinger <vapier@gentoo.org>
27
28 * dv-tx3904cpu.c (CPU, SD): Delete.
29
e1211e55
MF		 302015-12-30 Mike Frysinger <vapier@gentoo.org>
31
32 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
33 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
34 (sim_store_register): Rename to ...
35 (mips_reg_store): ... this. Delete local cpu var.
36 Update sim_io_eprintf calls.
37 (sim_fetch_register): Rename to ...
38 (mips_reg_fetch): ... this. Delete local cpu var.
39 Update sim_io_eprintf calls.
40
5e744ef8
MF		 412015-12-27 Mike Frysinger <vapier@gentoo.org>
42
43 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
44
1b393626
MF		 452015-12-26 Mike Frysinger <vapier@gentoo.org>
46
47 * config.in, configure: Regenerate.
48
26f8bf63
MF		 492015-12-26 Mike Frysinger <vapier@gentoo.org>
50
51 * interp.c (sim_write, sim_read): Delete.
52 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
53 (load_word): Likewise.
54 * micromips.igen (cache): Likewise.
55 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
56 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
57 do_store_left, do_store_right, do_load_double, do_store_double):
58 Likewise.
59 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
60 (do_prefx): Likewise.
61 * sim-main.c (address_translation, prefetch): Delete.
62 (ifetch32, ifetch16): Delete call to AddressTranslation and set
63 paddr=vaddr.
64 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
65 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
66 (LoadMemory, StoreMemory): Delete CCA arg.
67
ef04e371
MF		 682015-12-24 Mike Frysinger <vapier@gentoo.org>
69
70 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
71 * configure: Regenerated.
72
cb379ede
MF		 732015-12-24 Mike Frysinger <vapier@gentoo.org>
74
75 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
76 * tconfig.h: Delete.
77
26936211
MF		 782015-12-24 Mike Frysinger <vapier@gentoo.org>
79
80 * tconfig.h (SIM_HANDLES_LMA): Delete.
81
84e8e361
MF		 822015-12-24 Mike Frysinger <vapier@gentoo.org>
83
84 * sim-main.h (WITH_WATCHPOINTS): Delete.
85
3cabaf66
MF		 862015-12-24 Mike Frysinger <vapier@gentoo.org>
87
88 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
89
8abe6c66
MF		 902015-12-24 Mike Frysinger <vapier@gentoo.org>
91
92 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
93
1d19cae7
DV		 942015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
95
96 * micromips.igen (process_isa_mode): Fix left shift of negative
97 value.
98
cdf850e9
MF		 992015-11-17 Mike Frysinger <vapier@gentoo.org>
100
101 * sim-main.h (WITH_MODULO_MEMORY): Delete.
102
797eee42
MF		 1032015-11-15 Mike Frysinger <vapier@gentoo.org>
104
105 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
106
6e4f085c
MF		 1072015-11-14 Mike Frysinger <vapier@gentoo.org>
108
109 * interp.c (sim_close): Rename to ...
110 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
111 sim_io_shutdown.
112 * sim-main.h (mips_sim_close): Declare.
113 (SIM_CLOSE_HOOK): Define.
114
8e394ffc
AB		 1152015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
116 Ali Lown <ali.lown@imgtec.com>
117
118 * Makefile.in (tmp-micromips): New rule.
119 (tmp-mach-multi): Add support for micromips.
120 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
121 that works for both mips64 and micromips64.
122 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
123 micromips32.
124 Add build support for micromips.
125 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
126 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
127 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
128 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
129 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
130 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
131 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
132 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
133 Refactored instruction code to use these functions.
134 * dsp2.igen: Refactored instruction code to use the new functions.
135 * interp.c (decode_coproc): Refactored to work with any instruction
136 encoding.
137 (isa_mode): New variable
138 (RSVD_INSTRUCTION): Changed to 0x00000039.
139 * m16.igen (BREAK16): Refactored instruction to use do_break16.
140 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
141 * micromips.dc: New file.
142 * micromips.igen: New file.
143 * micromips16.dc: New file.
144 * micromipsdsp.igen: New file.
145 * micromipsrun.c: New file.
146 * mips.igen (do_swc1): Changed to work with any instruction encoding.
147 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
148 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
149 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
150 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
151 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
152 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
153 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
154 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
155 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
156 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
157 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
158 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
159 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
160 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
161 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
162 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
163 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
164 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
165 instructions.
166 Refactored instruction code to use these functions.
167 (RSVD): Changed to use new reserved instruction.
168 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
169 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
170 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
171 do_store_double): Added micromips32 and micromips64 models.
172 Added include for micromips.igen and micromipsdsp.igen
173 Add micromips32 and micromips64 models.
174 (DecodeCoproc): Updated to use new macro definition.
175 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
176 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
177 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
178 Refactored instruction code to use these functions.
179 * sim-main.h (CP0_operation): New enum.
180 (DecodeCoproc): Updated macro.
181 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
182 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
183 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
184 ISA_MODE_MICROMIPS): New defines.
185 (sim_state): Add isa_mode field.
186
8d0978fb
MF		 1872015-06-23 Mike Frysinger <vapier@gentoo.org>
188
189 * configure: Regenerate.
190
306f4178
MF		 1912015-06-12 Mike Frysinger <vapier@gentoo.org>
192
193 * configure.ac: Change configure.in to configure.ac.
194 * configure: Regenerate.
195
a3487082
MF		 1962015-06-12 Mike Frysinger <vapier@gentoo.org>
197
198 * configure: Regenerate.
199
29bc024d
MF		 2002015-06-12 Mike Frysinger <vapier@gentoo.org>
201
202 * interp.c [TRACE]: Delete.
203 (TRACE): Change to WITH_TRACE_ANY_P.
204 [!WITH_TRACE_ANY_P] (open_trace): Define.
205 (mips_option_handler, open_trace, sim_close, dotrace):
206 Change defined(TRACE) to WITH_TRACE_ANY_P.
207 (sim_open): Delete TRACE ifdef check.
208 * sim-main.c (load_memory): Delete TRACE ifdef check.
209 (store_memory): Likewise.
210 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
211 [!WITH_TRACE_ANY_P] (dotrace): Define.
212
3ebe2863
MF		 2132015-04-18 Mike Frysinger <vapier@gentoo.org>
214
215 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
216 comments.
217
20bca71d
MF		 2182015-04-18 Mike Frysinger <vapier@gentoo.org>
219
220 * sim-main.h (SIM_CPU): Delete.
221
7e83aa92
MF		 2222015-04-18 Mike Frysinger <vapier@gentoo.org>
223
224 * sim-main.h (sim_cia): Delete.
225
034685f9
MF		 2262015-04-17 Mike Frysinger <vapier@gentoo.org>
227
228 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
229 PU_PC_GET.
230 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
231 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
232 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
233 CIA_SET to CPU_PC_SET.
234 * sim-main.h (CIA_GET, CIA_SET): Delete.
235
78e9aa70
MF		 2362015-04-15 Mike Frysinger <vapier@gentoo.org>
237
238 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
239 * sim-main.h (STATE_CPU): Delete.
240
bf12d44e
MF		 2412015-04-13 Mike Frysinger <vapier@gentoo.org>
242
243 * configure: Regenerate.
244
7bebb329
MF		 2452015-04-13 Mike Frysinger <vapier@gentoo.org>
246
247 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
248 * interp.c (mips_pc_get, mips_pc_set): New functions.
249 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
250 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
251 (sim_pc_get): Delete.
252 * sim-main.h (SIM_CPU): Define.
253 (struct sim_state): Change cpu to an array of pointers.
254 (STATE_CPU): Drop &.
255
8ac57fbd
MF		 2562015-04-13 Mike Frysinger <vapier@gentoo.org>
257
258 * interp.c (mips_option_handler, open_trace, sim_close,
259 sim_write, sim_read, sim_store_register, sim_fetch_register,
260 sim_create_inferior, pr_addr, pr_uword64): Convert old style
261 prototypes.
262 (sim_open): Convert old style prototype. Change casts with
263 sim_write to unsigned char *.
264 (fetch_str): Change null to unsigned char, and change cast to
265 unsigned char *.
266 (sim_monitor): Change c & ch to unsigned char. Change cast to
267 unsigned char *.
268
e787f858
MF		 2692015-04-12 Mike Frysinger <vapier@gentoo.org>
270
271 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
272
122bbfb5
MF		 2732015-04-06 Mike Frysinger <vapier@gentoo.org>
274
275 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
276
0fe84f3f
MF		 2772015-04-01 Mike Frysinger <vapier@gentoo.org>
278
279 * tconfig.h (SIM_HAVE_PROFILE): Delete.
280
aadc9410
MF		 2812015-03-31 Mike Frysinger <vapier@gentoo.org>
282
283 * config.in, configure: Regenerate.
284
05f53ed6
MF		 2852015-03-24 Mike Frysinger <vapier@gentoo.org>
286
287 * interp.c (sim_pc_get): New function.
288
c0931f26
MF		 2892015-03-24 Mike Frysinger <vapier@gentoo.org>
290
291 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
292 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
293
30452bbe
MF		 2942015-03-24 Mike Frysinger <vapier@gentoo.org>
295
296 * configure: Regenerate.
297
64dd13df
MF		 2982015-03-23 Mike Frysinger <vapier@gentoo.org>
299
300 * configure: Regenerate.
301
49cd1634
MF		 3022015-03-23 Mike Frysinger <vapier@gentoo.org>
303
304 * configure: Regenerate.
305 * configure.ac (mips_extra_objs): Delete.
306 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
307 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
308
3649cb06
MF		 3092015-03-23 Mike Frysinger <vapier@gentoo.org>
310
311 * configure: Regenerate.
312 * configure.ac: Delete sim_hw checks for dv-sockser.
313
ae7d0cac
MF		 3142015-03-16 Mike Frysinger <vapier@gentoo.org>
315
316 * config.in, configure: Regenerate.
317 * tconfig.in: Rename file ...
318 * tconfig.h: ... here.
319
8406bb59
MF		 3202015-03-15 Mike Frysinger <vapier@gentoo.org>
321
322 * tconfig.in: Delete includes.
323 [HAVE_DV_SOCKSER]: Delete.
324
465fb143
MF		 3252015-03-14 Mike Frysinger <vapier@gentoo.org>
326
327 * Makefile.in (SIM_RUN_OBJS): Delete.
328
5cddc23a
MF		 3292015-03-14 Mike Frysinger <vapier@gentoo.org>
330
331 * configure.ac (AC_CHECK_HEADERS): Delete.
332 * aclocal.m4, configure: Regenerate.
333
2974be62
AM		 3342014-08-19 Alan Modra <amodra@gmail.com>
335
336 * configure: Regenerate.
337
faa743bb
RM		 3382014-08-15 Roland McGrath <mcgrathr@google.com>
339
340 * configure: Regenerate.
341 * config.in: Regenerate.
342
1a8a700e
MF		 3432014-03-04 Mike Frysinger <vapier@gentoo.org>
344
345 * configure: Regenerate.
346
bf3d9781
AM		 3472013-09-23 Alan Modra <amodra@gmail.com>
348
349 * configure: Regenerate.
350
31e6ad7d
MF		 3512013-06-03 Mike Frysinger <vapier@gentoo.org>
352
353 * aclocal.m4, configure: Regenerate.
354
d3685d60
TT		 3552013-05-10 Freddie Chopin <freddie_chopin@op.pl>
356
357 * configure: Rebuild.
358
1517bd27
MF		 3592013-03-26 Mike Frysinger <vapier@gentoo.org>
360
361 * configure: Regenerate.
362
3be31516
JS		 3632013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
364
365 * configure.ac: Address use of dv-sockser.o.
366 * tconfig.in: Conditionalize use of dv_sockser_install.
367 * configure: Regenerated.
368 * config.in: Regenerated.
369
37cb8f8e
SE		 3702012-10-04 Chao-ying Fu <fu@mips.com>
371 Steve Ellcey <sellcey@mips.com>
372
373 * mips/mips3264r2.igen (rdhwr): New.
374
87c8644f
JS		 3752012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
376
377 * configure.ac: Always link against dv-sockser.o.
378 * configure: Regenerate.
379
5f3ef9d0
JB		 3802012-06-15 Joel Brobecker <brobecker@adacore.com>
381
382 * config.in, configure: Regenerate.
383
a6ff997c
NC		 3842012-05-18 Nick Clifton <nickc@redhat.com>
385
386 PR 14072
387 * interp.c: Include config.h before system header files.
388
2232061b
MF		 3892012-03-24 Mike Frysinger <vapier@gentoo.org>
390
391 * aclocal.m4, config.in, configure: Regenerate.
392
db2e4d67
MF		 3932011-12-03 Mike Frysinger <vapier@gentoo.org>
394
395 * aclocal.m4: New file.
396 * configure: Regenerate.
397
4399a56b
MF		 3982011-10-19 Mike Frysinger <vapier@gentoo.org>
399
400 * configure: Regenerate after common/acinclude.m4 update.
401
9c082ca8
MF		 4022011-10-17 Mike Frysinger <vapier@gentoo.org>
403
404 * configure.ac: Change include to common/acinclude.m4.
405
6ffe910a
MF		 4062011-10-17 Mike Frysinger <vapier@gentoo.org>
407
408 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
409 call. Replace common.m4 include with SIM_AC_COMMON.
410 * configure: Regenerate.
411
31b28250
HPN		 4122011-07-08 Hans-Peter Nilsson <hp@axis.com>
413
3faa01e3
HPN		 414 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
415 $(SIM_EXTRA_DEPS).
416 (tmp-mach-multi): Exit early when igen fails.
31b28250 417
2419798b
MF		 4182011-07-05 Mike Frysinger <vapier@gentoo.org>
419
420 * interp.c (sim_do_command): Delete.
421
d79fe0d6
MF		 4222011-02-14 Mike Frysinger <vapier@gentoo.org>
423
424 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
425 (tx3904sio_fifo_reset): Likewise.
426 * interp.c (sim_monitor): Likewise.
427
5558e7e6
MF		 4282010-04-14 Mike Frysinger <vapier@gentoo.org>
429
430 * interp.c (sim_write): Add const to buffer arg.
431
35aafff4
JB		 4322010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
433
434 * interp.c: Don't include sysdep.h
435
3725885a
RW		 4362010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
437
438 * configure: Regenerate.
439
d6416cdc
RW		 4402009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
441
81ecdfbb
RW		 442 * config.in: Regenerate.
443 * configure: Likewise.
444
d6416cdc
RW		 445 * configure: Regenerate.
446
b5bd9624
HPN		 4472008-07-11 Hans-Peter Nilsson <hp@axis.com>
448
449 * configure: Regenerate to track ../common/common.m4 changes.
450 * config.in: Ditto.
451
6efef468 4522008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 453 Daniel Jacobowitz <dan@codesourcery.com>
454 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 455
456 * configure: Regenerate.
457
60dc88db
RS		 4582007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
459
460 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
461 that unconditionally allows fmt_ps.
462 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
463 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
464 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
465 filter from 64,f to 32,f.
466 (PREFX): Change filter from 64 to 32.
467 (LDXC1, LUXC1): Provide separate mips32r2 implementations
468 that use do_load_double instead of do_load. Make both LUXC1
469 versions unpredictable if SizeFGR () != 64.
470 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
471 instead of do_store. Remove unused variable. Make both SUXC1
472 versions unpredictable if SizeFGR () != 64.
473
599ca73e
RS		 4742007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
475
476 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
477 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
478 shifts for that case.
479
2525df03
NC		 4802007-09-04 Nick Clifton <nickc@redhat.com>
481
482 * interp.c (options enum): Add OPTION_INFO_MEMORY.
483 (display_mem_info): New static variable.
484 (mips_option_handler): Handle OPTION_INFO_MEMORY.
485 (mips_options): Add info-memory and memory-info.
486 (sim_open): After processing the command line and board
487 specification, check display_mem_info. If it is set then
488 call the real handler for the --memory-info command line
489 switch.
490
35ee6e1e
JB		 4912007-08-24 Joel Brobecker <brobecker@adacore.com>
492
493 * configure.ac: Change license of multi-run.c to GPL version 3.
494 * configure: Regenerate.
495
d5fb0879
RS		 4962007-06-28 Richard Sandiford <richard@codesourcery.com>
497
498 * configure.ac, configure: Revert last patch.
499
2a2ce21b
RS		 5002007-06-26 Richard Sandiford <richard@codesourcery.com>
501
502 * configure.ac (sim_mipsisa3264_configs): New variable.
503 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
504 every configuration support all four targets, using the triplet to
505 determine the default.
506 * configure: Regenerate.
507
efdcccc9
RS		 5082007-06-25 Richard Sandiford <richard@codesourcery.com>
509
0a7692b2 510 * Makefile.in (m16run.o): New rule.
efdcccc9 511
f532a356
TS		 5122007-05-15 Thiemo Seufer <ths@mips.com>
513
514 * mips3264r2.igen (DSHD): Fix compile warning.
515
bfe9c90b
TS		 5162007-05-14 Thiemo Seufer <ths@mips.com>
517
518 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
519 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
520 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
521 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
522 for mips32r2.
523
53f4826b
TS		 5242007-03-01 Thiemo Seufer <ths@mips.com>
525
526 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
527 and mips64.
528
8bf3ddc8
TS		 5292007-02-20 Thiemo Seufer <ths@mips.com>
530
531 * dsp.igen: Update copyright notice.
532 * dsp2.igen: Fix copyright notice.
533
8b082fb1 5342007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 535 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 536
537 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
538 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
539 Add dsp2 to sim_igen_machine.
540 * configure: Regenerate.
541 * dsp.igen (do_ph_op): Add MUL support when op = 2.
542 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
543 (mulq_rs.ph): Use do_ph_mulq.
544 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
545 * mips.igen: Add dsp2 model and include dsp2.igen.
546 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
547 for *mips32r2, *mips64r2, *dsp.
548 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
549 for *mips32r2, *mips64r2, *dsp2.
550 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
551
b1004875 5522007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 553 Nigel Stephens <nigel@mips.com>
b1004875
TS		 554
555 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
556 jumps with hazard barrier.
557
f8df4c77 5582007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 559 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 560
561 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
562 after each call to sim_io_write.
563
b1004875 5642007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 565 Nigel Stephens <nigel@mips.com>
b1004875
TS		 566
567 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
568 supported by this simulator.
07802d98
TS		 569 (decode_coproc): Recognise additional CP0 Config registers
570 correctly.
571
14fb6c5a 5722007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 573 Nigel Stephens <nigel@mips.com>
574 David Ung <davidu@mips.com>
14fb6c5a
TS		 575
576 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
577 uninterpreted formats. If fmt is one of the uninterpreted types
578 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
579 fmt_word, and fmt_uninterpreted_64 like fmt_long.
580 (store_fpr): When writing an invalid odd register, set the
581 matching even register to fmt_unknown, not the following register.
582 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
583 the the memory window at offset 0 set by --memory-size command
584 line option.
585 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
586 point register.
587 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
588 register.
589 (sim_monitor): When returning the memory size to the MIPS
590 application, use the value in STATE_MEM_SIZE, not an arbitrary
591 hardcoded value.
592 (cop_lw): Don' mess around with FPR_STATE, just pass
593 fmt_uninterpreted_32 to StoreFPR.
594 (cop_sw): Similarly.
595 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
596 (cop_sd): Similarly.
597 * mips.igen (not_word_value): Single version for mips32, mips64
598 and mips16.
599
c8847145 6002007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 601 Nigel Stephens <nigel@mips.com>
c8847145
TS		 602
603 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
604 MBytes.
605
4b5d35ee
TS		 6062007-02-17 Thiemo Seufer <ths@mips.com>
607
608 * configure.ac (mips*-sde-elf*): Move in front of generic machine
609 configuration.
610 * configure: Regenerate.
611
3669427c
TS		 6122007-02-17 Thiemo Seufer <ths@mips.com>
613
614 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
615 Add mdmx to sim_igen_machine.
616 (mipsisa64*-*-*): Likewise. Remove dsp.
617 (mipsisa32*-*-*): Remove dsp.
618 * configure: Regenerate.
619
109ad085
TS		 6202007-02-13 Thiemo Seufer <ths@mips.com>
621
622 * configure.ac: Add mips*-sde-elf* target.
623 * configure: Regenerate.
624
921d7ad3
HPN		 6252006-12-21 Hans-Peter Nilsson <hp@axis.com>
626
627 * acconfig.h: Remove.
628 * config.in, configure: Regenerate.
629
02f97da7
TS		 6302006-11-07 Thiemo Seufer <ths@mips.com>
631
632 * dsp.igen (do_w_op): Fix compiler warning.
633
2d2733fc 6342006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 635 David Ung <davidu@mips.com>
2d2733fc
TS		 636
637 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
638 sim_igen_machine.
639 * configure: Regenerate.
640 * mips.igen (model): Add smartmips.
641 (MADDU): Increment ACX if carry.
642 (do_mult): Clear ACX.
643 (ROR,RORV): Add smartmips.
72f4393d 644 (include): Include smartmips.igen.
2d2733fc
TS		 645 * sim-main.h (ACX): Set to REGISTERS[89].
646 * smartmips.igen: New file.
647
d85c3a10 6482006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 649 David Ung <davidu@mips.com>
d85c3a10
TS		 650
651 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
652 mips3264r2.igen. Add missing dependency rules.
653 * m16e.igen: Support for mips16e save/restore instructions.
654
e85e3205
RE		 6552006-06-13 Richard Earnshaw <rearnsha@arm.com>
656
657 * configure: Regenerated.
658
2f0122dc
DJ		 6592006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
660
661 * configure: Regenerated.
662
20e95c23
DJ		 6632006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
664
665 * configure: Regenerated.
666
69088b17
CF		 6672006-05-15 Chao-ying Fu <fu@mips.com>
668
669 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
670
0275de4e
NC		 6712006-04-18 Nick Clifton <nickc@redhat.com>
672
673 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
674 statement.
675
b3a3ffef
HPN		 6762006-03-29 Hans-Peter Nilsson <hp@axis.com>
677
678 * configure: Regenerate.
679
40a5538e
CF		 6802005-12-14 Chao-ying Fu <fu@mips.com>
681
682 * Makefile.in (SIM_OBJS): Add dsp.o.
683 (dsp.o): New dependency.
684 (IGEN_INCLUDE): Add dsp.igen.
685 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
686 mipsisa64*-*-*): Add dsp to sim_igen_machine.
687 * configure: Regenerate.
688 * mips.igen: Add dsp model and include dsp.igen.
689 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
690 because these instructions are extended in DSP ASE.
691 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
692 adding 6 DSP accumulator registers and 1 DSP control register.
693 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
694 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
695 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
696 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
697 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
698 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
699 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
700 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
701 DSPCR_CCOND_SMASK): New define.
702 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
703 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
704
21d14896
ILT		 7052005-07-08 Ian Lance Taylor <ian@airs.com>
706
707 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
708
b16d63da 7092005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 710 Nigel Stephens <nigel@mips.com>
711
712 * mips.igen: New mips16e model and include m16e.igen.
713 (check_u64): Add mips16e tag.
714 * m16e.igen: New file for MIPS16e instructions.
715 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
716 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
717 models.
718 * configure: Regenerate.
b16d63da 719
e70cb6cd 7202005-05-26 David Ung <davidu@mips.com>
72f4393d 721
e70cb6cd
CD		 722 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
723 tags to all instructions which are applicable to the new ISAs.
724 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
725 vr.igen.
726 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 727 instructions.
e70cb6cd
CD		 728 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
729 to mips.igen.
730 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
731 * configure: Regenerate.
72f4393d 732
2b193c4a
MK		 7332005-03-23 Mark Kettenis <kettenis@gnu.org>
734
735 * configure: Regenerate.
736
35695fd6
AC		 7372005-01-14 Andrew Cagney <cagney@gnu.org>
738
739 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
740 explicit call to AC_CONFIG_HEADER.
741 * configure: Regenerate.
742
f0569246
AC		 7432005-01-12 Andrew Cagney <cagney@gnu.org>
744
745 * configure.ac: Update to use ../common/common.m4.
746 * configure: Re-generate.
747
38f48d72
AC		 7482005-01-11 Andrew Cagney <cagney@localhost.localdomain>
749
750 * configure: Regenerated to track ../common/aclocal.m4 changes.
751
b7026657
AC		 7522005-01-07 Andrew Cagney <cagney@gnu.org>
753
754 * configure.ac: Rename configure.in, require autoconf 2.59.
755 * configure: Re-generate.
756
379832de
HPN		 7572004-12-08 Hans-Peter Nilsson <hp@axis.com>
758
759 * configure: Regenerate for ../common/aclocal.m4 update.
760
cd62154c 7612004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 762
cd62154c
AC		 763 Committed by Andrew Cagney.
764 * m16.igen (CMP, CMPI): Fix assembler.
765
e5da76ec
CD		 7662004-08-18 Chris Demetriou <cgd@broadcom.com>
767
768 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
769 * configure: Regenerate.
770
139181c8
CD		 7712004-06-25 Chris Demetriou <cgd@broadcom.com>
772
773 * configure.in (sim_m16_machine): Include mipsIII.
774 * configure: Regenerate.
775
1a27f959
CD		 7762004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
777
72f4393d 778 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 779 from COP0_BADVADDR.
780 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
781
5dbb7b5a
CD		 7822004-04-10 Chris Demetriou <cgd@broadcom.com>
783
784 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
785
14234056
CD		 7862004-04-09 Chris Demetriou <cgd@broadcom.com>
787
788 * mips.igen (check_fmt): Remove.
789 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
790 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
791 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
792 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
793 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
794 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
795 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
796 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
797 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
798 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
799
c6f9085c
CD		 8002004-04-09 Chris Demetriou <cgd@broadcom.com>
801
802 * sb1.igen (check_sbx): New function.
803 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
804
11d66e66 8052004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 806 Richard Sandiford <rsandifo@redhat.com>
807
808 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
809 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
810 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
811 separate implementations for mipsIV and mipsV. Use new macros to
812 determine whether the restrictions apply.
813
b3208fb8
CD		 8142004-01-19 Chris Demetriou <cgd@broadcom.com>
815
816 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
817 (check_mult_hilo): Improve comments.
818 (check_div_hilo): Likewise. Also, fork off a new version
819 to handle mips32/mips64 (since there are no hazards to check
820 in MIPS32/MIPS64).
821
9a1d84fb
CD		 8222003-06-17 Richard Sandiford <rsandifo@redhat.com>
823
824 * mips.igen (do_dmultx): Fix check for negative operands.
825
ae451ac6
ILT		 8262003-05-16 Ian Lance Taylor <ian@airs.com>
827
828 * Makefile.in (SHELL): Make sure this is defined.
829 (various): Use $(SHELL) whenever we invoke move-if-change.
830
dd69d292
CD		 8312003-05-03 Chris Demetriou <cgd@broadcom.com>
832
833 * cp1.c: Tweak attribution slightly.
834 * cp1.h: Likewise.
835 * mdmx.c: Likewise.
836 * mdmx.igen: Likewise.
837 * mips3d.igen: Likewise.
838 * sb1.igen: Likewise.
839
bcd0068e
CD		 8402003-04-15 Richard Sandiford <rsandifo@redhat.com>
841
842 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
843 unsigned operands.
844
6b4a8935
AC		 8452003-02-27 Andrew Cagney <cagney@redhat.com>
846
601da316
AC		 847 * interp.c (sim_open): Rename _bfd to bfd.
848 (sim_create_inferior): Ditto.
6b4a8935 849
d29e330f
CD		 8502003-01-14 Chris Demetriou <cgd@broadcom.com>
851
852 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
853
a2353a08
CD		 8542003-01-14 Chris Demetriou <cgd@broadcom.com>
855
856 * mips.igen (EI, DI): Remove.
857
80551777
CD		 8582003-01-05 Richard Sandiford <rsandifo@redhat.com>
859
860 * Makefile.in (tmp-run-multi): Fix mips16 filter.
861
4c54fc26
CD		 8622003-01-04 Richard Sandiford <rsandifo@redhat.com>
863 Andrew Cagney <ac131313@redhat.com>
864 Gavin Romig-Koch <gavin@redhat.com>
865 Graydon Hoare <graydon@redhat.com>
866 Aldy Hernandez <aldyh@redhat.com>
867 Dave Brolley <brolley@redhat.com>
868 Chris Demetriou <cgd@broadcom.com>
869
870 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
871 (sim_mach_default): New variable.
872 (mips64vr-*-*, mips64vrel-*-*): New configurations.
873 Add a new simulator generator, MULTI.
874 * configure: Regenerate.
875 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
876 (multi-run.o): New dependency.
877 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
878 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
879 (tmp-multi): Combine them.
880 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
881 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
882 (distclean-extra): New rule.
883 * sim-main.h: Include bfd.h.
884 (MIPS_MACH): New macro.
885 * mips.igen (vr4120, vr5400, vr5500): New models.
886 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
887 * vr.igen: Replace with new version.
888
e6c674b8
CD		 8892003-01-04 Chris Demetriou <cgd@broadcom.com>
890
891 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
892 * configure: Regenerate.
893
28f50ac8
CD		 8942002-12-31 Chris Demetriou <cgd@broadcom.com>
895
896 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
897 * mips.igen: Remove all invocations of check_branch_bug and
898 mark_branch_bug.
899
5071ffe6
CD		 9002002-12-16 Chris Demetriou <cgd@broadcom.com>
901
72f4393d 902 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 903
06e7837e
CD		 9042002-07-30 Chris Demetriou <cgd@broadcom.com>
905
906 * mips.igen (do_load_double, do_store_double): New functions.
907 (LDC1, SDC1): Rename to...
908 (LDC1b, SDC1b): respectively.
909 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
910
2265c243
MS		 9112002-07-29 Michael Snyder <msnyder@redhat.com>
912
913 * cp1.c (fp_recip2): Modify initialization expression so that
914 GCC will recognize it as constant.
915
a2f8b4f3
CD		 9162002-06-18 Chris Demetriou <cgd@broadcom.com>
917
918 * mdmx.c (SD_): Delete.
919 (Unpredictable): Re-define, for now, to directly invoke
920 unpredictable_action().
921 (mdmx_acc_op): Fix error in .ob immediate handling.
922
b4b6c939
AC		 9232002-06-18 Andrew Cagney <cagney@redhat.com>
924
925 * interp.c (sim_firmware_command): Initialize `address'.
926
c8cca39f
AC		 9272002-06-16 Andrew Cagney <ac131313@redhat.com>
928
929 * configure: Regenerated to track ../common/aclocal.m4 changes.
930
e7e81181 9312002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 932 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 933
934 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
935 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
936 * mips.igen: Include mips3d.igen.
937 (mips3d): New model name for MIPS-3D ASE instructions.
938 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 939 instructions.
e7e81181
CD		 940 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
941 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
942 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
943 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
944 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
945 (RSquareRoot1, RSquareRoot2): New macros.
946 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
947 (fp_rsqrt2): New functions.
948 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
949 * configure: Regenerate.
950
3a2b820e 9512002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 952 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 953
954 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
955 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
956 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
957 (convert): Note that this function is not used for paired-single
958 format conversions.
959 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
960 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
961 (check_fmt_p): Enable paired-single support.
962 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
963 (PUU.PS): New instructions.
964 (CVT.S.fmt): Don't use this instruction for paired-single format
965 destinations.
966 * sim-main.h (FP_formats): New value 'fmt_ps.'
967 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
968 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
969
d18ea9c2
CD		 9702002-06-12 Chris Demetriou <cgd@broadcom.com>
971
972 * mips.igen: Fix formatting of function calls in
973 many FP operations.
974
95fd5cee
CD		 9752002-06-12 Chris Demetriou <cgd@broadcom.com>
976
977 * mips.igen (MOVN, MOVZ): Trace result.
978 (TNEI): Print "tnei" as the opcode name in traces.
979 (CEIL.W): Add disassembly string for traces.
980 (RSQRT.fmt): Make location of disassembly string consistent
981 with other instructions.
982
4f0d55ae
CD		 9832002-06-12 Chris Demetriou <cgd@broadcom.com>
984
985 * mips.igen (X): Delete unused function.
986
3c25f8c7
AC		 9872002-06-08 Andrew Cagney <cagney@redhat.com>
988
989 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
990
f3c08b7e 9912002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 992 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 993
994 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
995 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
996 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
997 (fp_nmsub): New prototypes.
998 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
999 (NegMultiplySub): New defines.
1000 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1001 (MADD.D, MADD.S): Replace with...
1002 (MADD.fmt): New instruction.
1003 (MSUB.D, MSUB.S): Replace with...
1004 (MSUB.fmt): New instruction.
1005 (NMADD.D, NMADD.S): Replace with...
1006 (NMADD.fmt): New instruction.
1007 (NMSUB.D, MSUB.S): Replace with...
1008 (NMSUB.fmt): New instruction.
1009
52714ff9 10102002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1011 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1012
1013 * cp1.c: Fix more comment spelling and formatting.
1014 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1015 (denorm_mode): New function.
1016 (fpu_unary, fpu_binary): Round results after operation, collect
1017 status from rounding operations, and update the FCSR.
1018 (convert): Collect status from integer conversions and rounding
1019 operations, and update the FCSR. Adjust NaN values that result
1020 from conversions. Convert to use sim_io_eprintf rather than
1021 fprintf, and remove some debugging code.
1022 * cp1.h (fenr_FS): New define.
1023
577d8c4b
CD		 10242002-06-07 Chris Demetriou <cgd@broadcom.com>
1025
1026 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1027 rounding mode to sim FP rounding mode flag conversion code into...
1028 (rounding_mode): New function.
1029
196496ed
CD		 10302002-06-07 Chris Demetriou <cgd@broadcom.com>
1031
1032 * cp1.c: Clean up formatting of a few comments.
1033 (value_fpr): Reformat switch statement.
1034
cfe9ea23 10352002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1036 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1037
1038 * cp1.h: New file.
1039 * sim-main.h: Include cp1.h.
1040 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1041 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1042 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1043 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1044 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1045 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1046 * cp1.c: Don't include sim-fpu.h; already included by
1047 sim-main.h. Clean up formatting of some comments.
1048 (NaN, Equal, Less): Remove.
1049 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1050 (fp_cmp): New functions.
1051 * mips.igen (do_c_cond_fmt): Remove.
1052 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1053 Compare. Add result tracing.
1054 (CxC1): Remove, replace with...
1055 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1056 (DMxC1): Remove, replace with...
1057 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1058 (MxC1): Remove, replace with...
1059 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1060
ee7254b0
CD		 10612002-06-04 Chris Demetriou <cgd@broadcom.com>
1062
1063 * sim-main.h (FGRIDX): Remove, replace all uses with...
1064 (FGR_BASE): New macro.
1065 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1066 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1067 (NR_FGR, FGR): Likewise.
1068 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1069 * mips.igen: Likewise.
1070
d3eb724f
CD		 10712002-06-04 Chris Demetriou <cgd@broadcom.com>
1072
1073 * cp1.c: Add an FSF Copyright notice to this file.
1074
ba46ddd0 10752002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1076 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1077
1078 * cp1.c (Infinity): Remove.
1079 * sim-main.h (Infinity): Likewise.
1080
1081 * cp1.c (fp_unary, fp_binary): New functions.
1082 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1083 (fp_sqrt): New functions, implemented in terms of the above.
1084 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1085 (Recip, SquareRoot): Remove (replaced by functions above).
1086 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1087 (fp_recip, fp_sqrt): New prototypes.
1088 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1089 (Recip, SquareRoot): Replace prototypes with #defines which
1090 invoke the functions above.
72f4393d 1091
18d8a52d
CD		 10922002-06-03 Chris Demetriou <cgd@broadcom.com>
1093
1094 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1095 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1096 file, remove PARAMS from prototypes.
1097 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1098 simulator state arguments.
1099 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1100 pass simulator state arguments.
1101 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1102 (store_fpr, convert): Remove 'sd' argument.
1103 (value_fpr): Likewise. Convert to use 'SD' instead.
1104
0f154cbd
CD		 11052002-06-03 Chris Demetriou <cgd@broadcom.com>
1106
1107 * cp1.c (Min, Max): Remove #if 0'd functions.
1108 * sim-main.h (Min, Max): Remove.
1109
e80fc152
CD		 11102002-06-03 Chris Demetriou <cgd@broadcom.com>
1111
1112 * cp1.c: fix formatting of switch case and default labels.
1113 * interp.c: Likewise.
1114 * sim-main.c: Likewise.
1115
bad673a9
CD		 11162002-06-03 Chris Demetriou <cgd@broadcom.com>
1117
1118 * cp1.c: Clean up comments which describe FP formats.
1119 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1120
7cbea089 11212002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1122 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1123
1124 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1125 Broadcom SiByte SB-1 processor configurations.
1126 * configure: Regenerate.
1127 * sb1.igen: New file.
1128 * mips.igen: Include sb1.igen.
1129 (sb1): New model.
1130 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1131 * mdmx.igen: Add "sb1" model to all appropriate functions and
1132 instructions.
1133 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1134 (ob_func, ob_acc): Reference the above.
1135 (qh_acc): Adjust to keep the same size as ob_acc.
1136 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1137 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1138
909daa82
CD		 11392002-06-03 Chris Demetriou <cgd@broadcom.com>
1140
1141 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1142
f4f1b9f1 11432002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1144 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1145
1146 * mips.igen (mdmx): New (pseudo-)model.
1147 * mdmx.c, mdmx.igen: New files.
1148 * Makefile.in (SIM_OBJS): Add mdmx.o.
1149 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1150 New typedefs.
1151 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1152 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1153 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1154 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1155 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1156 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1157 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1158 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1159 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1160 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1161 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1162 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1163 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1164 (qh_fmtsel): New macros.
1165 (_sim_cpu): New member "acc".
1166 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1167 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1168
5accf1ff
CD		 11692002-05-01 Chris Demetriou <cgd@broadcom.com>
1170
1171 * interp.c: Use 'deprecated' rather than 'depreciated.'
1172 * sim-main.h: Likewise.
1173
402586aa
CD		 11742002-05-01 Chris Demetriou <cgd@broadcom.com>
1175
1176 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1177 which wouldn't compile anyway.
1178 * sim-main.h (unpredictable_action): New function prototype.
1179 (Unpredictable): Define to call igen function unpredictable().
1180 (NotWordValue): New macro to call igen function not_word_value().
1181 (UndefinedResult): Remove.
1182 * interp.c (undefined_result): Remove.
1183 (unpredictable_action): New function.
1184 * mips.igen (not_word_value, unpredictable): New functions.
1185 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1186 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1187 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1188 NotWordValue() to check for unpredictable inputs, then
1189 Unpredictable() to handle them.
1190
c9b9995a
CD		 11912002-02-24 Chris Demetriou <cgd@broadcom.com>
1192
1193 * mips.igen: Fix formatting of calls to Unpredictable().
1194
e1015982
AC		 11952002-04-20 Andrew Cagney <ac131313@redhat.com>
1196
1197 * interp.c (sim_open): Revert previous change.
1198
b882a66b
AO		 11992002-04-18 Alexandre Oliva <aoliva@redhat.com>
1200
1201 * interp.c (sim_open): Disable chunk of code that wrote code in
1202 vector table entries.
1203
c429b7dd
CD		 12042002-03-19 Chris Demetriou <cgd@broadcom.com>
1205
1206 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1207 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1208 unused definitions.
1209
37d146fa
CD		 12102002-03-19 Chris Demetriou <cgd@broadcom.com>
1211
1212 * cp1.c: Fix many formatting issues.
1213
07892c0b
CD		 12142002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1215
1216 * cp1.c (fpu_format_name): New function to replace...
1217 (DOFMT): This. Delete, and update all callers.
1218 (fpu_rounding_mode_name): New function to replace...
1219 (RMMODE): This. Delete, and update all callers.
1220
487f79b7
CD		 12212002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1222
1223 * interp.c: Move FPU support routines from here to...
1224 * cp1.c: Here. New file.
1225 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1226 (cp1.o): New target.
1227
1e799e28
CD		 12282002-03-12 Chris Demetriou <cgd@broadcom.com>
1229
1230 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1231 * mips.igen (mips32, mips64): New models, add to all instructions
1232 and functions as appropriate.
1233 (loadstore_ea, check_u64): New variant for model mips64.
1234 (check_fmt_p): New variant for models mipsV and mips64, remove
1235 mipsV model marking fro other variant.
1236 (SLL) Rename to...
1237 (SLLa) this.
1238 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1239 for mips32 and mips64.
1240 (DCLO, DCLZ): New instructions for mips64.
1241
82f728db
CD		 12422002-03-07 Chris Demetriou <cgd@broadcom.com>
1243
1244 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1245 immediate or code as a hex value with the "%#lx" format.
1246 (ANDI): Likewise, and fix printed instruction name.
1247
b96e7ef1
CD		 12482002-03-05 Chris Demetriou <cgd@broadcom.com>
1249
1250 * sim-main.h (UndefinedResult, Unpredictable): New macros
1251 which currently do nothing.
1252
d35d4f70
CD		 12532002-03-05 Chris Demetriou <cgd@broadcom.com>
1254
1255 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1256 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1257 (status_CU3): New definitions.
1258
1259 * sim-main.h (ExceptionCause): Add new values for MIPS32
1260 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1261 for DebugBreakPoint and NMIReset to note their status in
1262 MIPS32 and MIPS64.
1263 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1264 (SignalExceptionCacheErr): New exception macros.
1265
3ad6f714
CD		 12662002-03-05 Chris Demetriou <cgd@broadcom.com>
1267
1268 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1269 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1270 is always enabled.
1271 (SignalExceptionCoProcessorUnusable): Take as argument the
1272 unusable coprocessor number.
1273
86b77b47
CD		 12742002-03-05 Chris Demetriou <cgd@broadcom.com>
1275
1276 * mips.igen: Fix formatting of all SignalException calls.
1277
97a88e93 12782002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1279
1280 * sim-main.h (SIGNEXTEND): Remove.
1281
97a88e93 12822002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1283
1284 * mips.igen: Remove gencode comment from top of file, fix
1285 spelling in another comment.
1286
97a88e93 12872002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1288
1289 * mips.igen (check_fmt, check_fmt_p): New functions to check
1290 whether specific floating point formats are usable.
1291 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1292 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1293 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1294 Use the new functions.
1295 (do_c_cond_fmt): Remove format checks...
1296 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1297
97a88e93 12982002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1299
1300 * mips.igen: Fix formatting of check_fpu calls.
1301
41774c9d
CD		 13022002-03-03 Chris Demetriou <cgd@broadcom.com>
1303
1304 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1305
4a0bd876
CD		 13062002-03-03 Chris Demetriou <cgd@broadcom.com>
1307
1308 * mips.igen: Remove whitespace at end of lines.
1309
09297648
CD		 13102002-03-02 Chris Demetriou <cgd@broadcom.com>
1311
1312 * mips.igen (loadstore_ea): New function to do effective
1313 address calculations.
1314 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1315 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1316 CACHE): Use loadstore_ea to do effective address computations.
1317
043b7057
CD		 13182002-03-02 Chris Demetriou <cgd@broadcom.com>
1319
1320 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1321 * mips.igen (LL, CxC1, MxC1): Likewise.
1322
c1e8ada4
CD		 13232002-03-02 Chris Demetriou <cgd@broadcom.com>
1324
1325 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1326 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1327 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1328 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1329 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1330 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1331 Don't split opcode fields by hand, use the opcode field values
1332 provided by igen.
1333
3e1dca16
CD		 13342002-03-01 Chris Demetriou <cgd@broadcom.com>
1335
1336 * mips.igen (do_divu): Fix spacing.
1337
1338 * mips.igen (do_dsllv): Move to be right before DSLLV,
1339 to match the rest of the do_<shift> functions.
1340
fff8d27d
CD		 13412002-03-01 Chris Demetriou <cgd@broadcom.com>
1342
1343 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1344 DSRL32, do_dsrlv): Trace inputs and results.
1345
0d3e762b
CD		 13462002-03-01 Chris Demetriou <cgd@broadcom.com>
1347
1348 * mips.igen (CACHE): Provide instruction-printing string.
1349
1350 * interp.c (signal_exception): Comment tokens after #endif.
1351
eb5fcf93
CD		 13522002-02-28 Chris Demetriou <cgd@broadcom.com>
1353
1354 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1355 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1356 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1357 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1358 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1359 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1360 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1361 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1362
bb22bd7d
CD		 13632002-02-28 Chris Demetriou <cgd@broadcom.com>
1364
1365 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1366 instruction-printing string.
1367 (LWU): Use '64' as the filter flag.
1368
91a177cf
CD		 13692002-02-28 Chris Demetriou <cgd@broadcom.com>
1370
1371 * mips.igen (SDXC1): Fix instruction-printing string.
1372
387f484a
CD		 13732002-02-28 Chris Demetriou <cgd@broadcom.com>
1374
1375 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1376 filter flags "32,f".
1377
3d81f391
CD		 13782002-02-27 Chris Demetriou <cgd@broadcom.com>
1379
1380 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1381 as the filter flag.
1382
af5107af
CD		 13832002-02-27 Chris Demetriou <cgd@broadcom.com>
1384
1385 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1386 add a comma) so that it more closely match the MIPS ISA
1387 documentation opcode partitioning.
1388 (PREF): Put useful names on opcode fields, and include
1389 instruction-printing string.
1390
ca971540
CD		 13912002-02-27 Chris Demetriou <cgd@broadcom.com>
1392
1393 * mips.igen (check_u64): New function which in the future will
1394 check whether 64-bit instructions are usable and signal an
1395 exception if not. Currently a no-op.
1396 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1397 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1398 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1399 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1400
1401 * mips.igen (check_fpu): New function which in the future will
1402 check whether FPU instructions are usable and signal an exception
1403 if not. Currently a no-op.
1404 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1405 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1406 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1407 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1408 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1409 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1410 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1411 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1412
1c47a468
CD		 14132002-02-27 Chris Demetriou <cgd@broadcom.com>
1414
1415 * mips.igen (do_load_left, do_load_right): Move to be immediately
1416 following do_load.
1417 (do_store_left, do_store_right): Move to be immediately following
1418 do_store.
1419
603a98e7
CD		 14202002-02-27 Chris Demetriou <cgd@broadcom.com>
1421
1422 * mips.igen (mipsV): New model name. Also, add it to
1423 all instructions and functions where it is appropriate.
1424
c5d00cc7
CD		 14252002-02-18 Chris Demetriou <cgd@broadcom.com>
1426
1427 * mips.igen: For all functions and instructions, list model
1428 names that support that instruction one per line.
1429
074e9cb8
CD		 14302002-02-11 Chris Demetriou <cgd@broadcom.com>
1431
1432 * mips.igen: Add some additional comments about supported
1433 models, and about which instructions go where.
1434 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1435 order as is used in the rest of the file.
1436
9805e229
CD		 14372002-02-11 Chris Demetriou <cgd@broadcom.com>
1438
1439 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1440 indicating that ALU32_END or ALU64_END are there to check
1441 for overflow.
1442 (DADD): Likewise, but also remove previous comment about
1443 overflow checking.
1444
f701dad2
CD		 14452002-02-10 Chris Demetriou <cgd@broadcom.com>
1446
1447 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1448 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1449 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1450 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1451 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1452 fields (i.e., add and move commas) so that they more closely
1453 match the MIPS ISA documentation opcode partitioning.
1454
14552002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1456
72f4393d
L		 1457 * mips.igen (ADDI): Print immediate value.
1458 (BREAK): Print code.
1459 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1460 (SLL): Print "nop" specially, and don't run the code
1461 that does the shift for the "nop" case.
20ae0098 1462
9e52972e
FF		 14632001-11-17 Fred Fish <fnf@redhat.com>
1464
1465 * sim-main.h (float_operation): Move enum declaration outside
1466 of _sim_cpu struct declaration.
1467
c0efbca4
JB		 14682001-04-12 Jim Blandy <jimb@redhat.com>
1469
1470 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1471 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1472 set of the FCSR.
1473 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1474 PENDING_FILL, and you can get the intended effect gracefully by
1475 calling PENDING_SCHED directly.
1476
fb891446
BE		 14772001-02-23 Ben Elliston <bje@redhat.com>
1478
1479 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1480 already defined elsewhere.
1481
8030f857
BE		 14822001-02-19 Ben Elliston <bje@redhat.com>
1483
1484 * sim-main.h (sim_monitor): Return an int.
1485 * interp.c (sim_monitor): Add return values.
1486 (signal_exception): Handle error conditions from sim_monitor.
1487
56b48a7a
CD		 14882001-02-08 Ben Elliston <bje@redhat.com>
1489
1490 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1491 (store_memory): Likewise, pass cia to sim_core_write*.
1492
d3ee60d9
FCE		 14932000-10-19 Frank Ch. Eigler <fche@redhat.com>
1494
1495 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1496 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1497
071da002
AC		 1498Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1499
1500 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1501 * Makefile.in: Don't delete *.igen when cleaning directory.
1502
a28c02cd
AC		 1503Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1504
1505 * m16.igen (break): Call SignalException not sim_engine_halt.
1506
80ee11fa
AC		 1507Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1508
1509 From Jason Eckhardt:
1510 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1511
673388c0
AC		 1512Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1513
1514 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1515
4c0deff4
NC		 15162000-05-24 Michael Hayes <mhayes@cygnus.com>
1517
1518 * mips.igen (do_dmultx): Fix typo.
1519
eb2d80b4
AC		 1520Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * configure: Regenerated to track ../common/aclocal.m4 changes.
1523
dd37a34b
AC		 1524Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1527
4c0deff4
NC		 15282000-04-12 Frank Ch. Eigler <fche@redhat.com>
1529
1530 * sim-main.h (GPR_CLEAR): Define macro.
1531
e30db738
AC		 1532Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1533
1534 * interp.c (decode_coproc): Output long using %lx and not %s.
1535
cb7450ea
FCE		 15362000-03-21 Frank Ch. Eigler <fche@redhat.com>
1537
1538 * interp.c (sim_open): Sort & extend dummy memory regions for
1539 --board=jmr3904 for eCos.
1540
a3027dd7
FCE		 15412000-03-02 Frank Ch. Eigler <fche@redhat.com>
1542
1543 * configure: Regenerated.
1544
1545Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1546
1547 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1548 calls, conditional on the simulator being in verbose mode.
1549
dfcd3bfb
JM		 1550Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1551
1552 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1553 cache don't get ReservedInstruction traps.
1554
c2d11a7d
JM		 15551999-11-29 Mark Salter <msalter@cygnus.com>
1556
1557 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1558 to clear status bits in sdisr register. This is how the hardware works.
1559
1560 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1561 being used by cygmon.
1562
4ce44c66
JM		 15631999-11-11 Andrew Haley <aph@cygnus.com>
1564
1565 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1566 instructions.
1567
cff3e48b
JM		 1568Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1569
1570 * mips.igen (MULT): Correct previous mis-applied patch.
1571
d4f3574e
SS		 1572Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1573
1574 * mips.igen (delayslot32): Handle sequence like
1575 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1576 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1577 (MULT): Actually pass the third register...
1578
15791999-09-03 Mark Salter <msalter@cygnus.com>
1580
1581 * interp.c (sim_open): Added more memory aliases for additional
1582 hardware being touched by cygmon on jmr3904 board.
1583
1584Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1585
1586 * configure: Regenerated to track ../common/aclocal.m4 changes.
1587
a0b3c4fd
JM		 1588Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1589
1590 * interp.c (sim_store_register): Handle case where client - GDB -
1591 specifies that a 4 byte register is 8 bytes in size.
1592 (sim_fetch_register): Ditto.
72f4393d 1593
adf40b2e
JM		 15941999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1595
1596 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1597 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1598 (idt_monitor_base): Base address for IDT monitor traps.
1599 (pmon_monitor_base): Ditto for PMON.
1600 (lsipmon_monitor_base): Ditto for LSI PMON.
1601 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1602 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1603 (sim_firmware_command): New function.
1604 (mips_option_handler): Call it for OPTION_FIRMWARE.
1605 (sim_open): Allocate memory for idt_monitor region. If "--board"
1606 option was given, add no monitor by default. Add BREAK hooks only if
1607 monitors are also there.
72f4393d 1608
43e526b9
JM		 1609Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1610
1611 * interp.c (sim_monitor): Flush output before reading input.
1612
1613Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1614
1615 * tconfig.in (SIM_HANDLES_LMA): Always define.
1616
1617Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1618
1619 From Mark Salter <msalter@cygnus.com>:
1620 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1621 (sim_open): Add setup for BSP board.
1622
9846de1b
JM		 1623Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1624
1625 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1626 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1627 them as unimplemented.
1628
cd0fc7c3
SS		 16291999-05-08 Felix Lee <flee@cygnus.com>
1630
1631 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1632
7a292a7a
SS		 16331999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1634
1635 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1636
1637Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1638
1639 * configure.in: Any mips64vr5*-*-* target should have
1640 -DTARGET_ENABLE_FR=1.
1641 (default_endian): Any mips64vr*el-*-* target should default to
1642 LITTLE_ENDIAN.
1643 * configure: Re-generate.
1644
16451999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1646
1647 * mips.igen (ldl): Extend from _16_, not 32.
1648
1649Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1650
1651 * interp.c (sim_store_register): Force registers written to by GDB
1652 into an un-interpreted state.
1653
c906108c
SS		 16541999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1655
1656 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1657 CPU, start periodic background I/O polls.
72f4393d 1658 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1659
16601998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1661
1662 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1663
c906108c
SS		 1664Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1665
1666 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1667 case statement.
1668
16691998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1670
1671 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1672 (load_word): Call SIM_CORE_SIGNAL hook on error.
1673 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1674 starting. For exception dispatching, pass PC instead of NULL_CIA.
1675 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1676 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1677 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1678 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1679 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1680 * mips.igen (*): Replace memory-related SignalException* calls
1681 with references to SIM_CORE_SIGNAL hook.
72f4393d 1682
c906108c
SS		 1683 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1684 fix.
1685 * sim-main.c (*): Minor warning cleanups.
72f4393d 1686
c906108c
SS		 16871998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1688
1689 * m16.igen (DADDIU5): Correct type-o.
1690
1691Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1692
1693 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1694 variables.
1695
1696Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1697
1698 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1699 to include path.
1700 (interp.o): Add dependency on itable.h
1701 (oengine.c, gencode): Delete remaining references.
1702 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1703
c906108c 17041998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1705
c906108c
SS		 1706 * vr4run.c: New.
1707 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1708 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1709 tmp-run-hack) : New.
1710 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1711 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1712 Drop the "64" qualifier to get the HACK generator working.
1713 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1714 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1715 qualifier to get the hack generator working.
1716 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1717 (DSLL): Use do_dsll.
1718 (DSLLV): Use do_dsllv.
1719 (DSRA): Use do_dsra.
1720 (DSRL): Use do_dsrl.
1721 (DSRLV): Use do_dsrlv.
1722 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1723 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1724 get the HACK generator working.
1725 (MACC) Rename to get the HACK generator working.
1726 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1727
c906108c
SS		 17281998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1729
1730 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1731 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1732
c906108c
SS		 17331998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1734
1735 * mips/interp.c (DEBUG): Cleanups.
1736
17371998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1738
1739 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1740 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1741
c906108c
SS		 17421998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1743
1744 * interp.c (sim_close): Uninstall modules.
1745
1746Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1747
1748 * sim-main.h, interp.c (sim_monitor): Change to global
1749 function.
1750
1751Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1752
1753 * configure.in (vr4100): Only include vr4100 instructions in
1754 simulator.
1755 * configure: Re-generate.
1756 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1757
1758Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1759
1760 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1761 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1762 true alternative.
1763
1764 * configure.in (sim_default_gen, sim_use_gen): Replace with
1765 sim_gen.
1766 (--enable-sim-igen): Delete config option. Always using IGEN.
1767 * configure: Re-generate.
72f4393d 1768
c906108c
SS		 1769 * Makefile.in (gencode): Kill, kill, kill.
1770 * gencode.c: Ditto.
72f4393d 1771
c906108c
SS		 1772Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1775 bit mips16 igen simulator.
1776 * configure: Re-generate.
1777
1778 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1779 as part of vr4100 ISA.
1780 * vr.igen: Mark all instructions as 64 bit only.
1781
1782Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1783
1784 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1785 Pacify GCC.
1786
1787Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1788
1789 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1790 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1791 * configure: Re-generate.
1792
1793 * m16.igen (BREAK): Define breakpoint instruction.
1794 (JALX32): Mark instruction as mips16 and not r3900.
1795 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1796
1797 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1798
1799Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1802 insn as a debug breakpoint.
1803
1804 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1805 pending.slot_size.
1806 (PENDING_SCHED): Clean up trace statement.
1807 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1808 (PENDING_FILL): Delay write by only one cycle.
1809 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1810
1811 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1812 of pending writes.
1813 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1814 32 & 64.
1815 (pending_tick): Move incrementing of index to FOR statement.
1816 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1817
c906108c
SS		 1818 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1819 build simulator.
1820 * configure: Re-generate.
72f4393d 1821
c906108c
SS		 1822 * interp.c (sim_engine_run OLD): Delete explicit call to
1823 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1824
c906108c
SS		 1825Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1826
1827 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1828 interrupt level number to match changed SignalExceptionInterrupt
1829 macro.
1830
1831Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1832
1833 * interp.c: #include "itable.h" if WITH_IGEN.
1834 (get_insn_name): New function.
1835 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1836 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1837
1838Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1839
1840 * configure: Rebuilt to inhale new common/aclocal.m4.
1841
1842Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1843
1844 * dv-tx3904sio.c: Include sim-assert.h.
1845
1846Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1847
1848 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1849 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1850 Reorganize target-specific sim-hardware checks.
1851 * configure: rebuilt.
1852 * interp.c (sim_open): For tx39 target boards, set
1853 OPERATING_ENVIRONMENT, add tx3904sio devices.
1854 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1855 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1856
c906108c
SS		 1857 * dv-tx3904irc.c: Compiler warning clean-up.
1858 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1859 frequent hw-trace messages.
1860
1861Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1862
1863 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1864
1865Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1866
1867 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1868
1869 * vr.igen: New file.
1870 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1871 * mips.igen: Define vr4100 model. Include vr.igen.
1872Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1873
1874 * mips.igen (check_mf_hilo): Correct check.
1875
1876Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1877
1878 * sim-main.h (interrupt_event): Add prototype.
1879
1880 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1881 register_ptr, register_value.
1882 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1883
1884 * sim-main.h (tracefh): Make extern.
1885
1886Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1887
1888 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1889 Reduce unnecessarily high timer event frequency.
c906108c 1890 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1891
c906108c
SS		 1892Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1893
1894 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1895 to allay warnings.
1896 (interrupt_event): Made non-static.
72f4393d 1897
c906108c
SS		 1898 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1899 interchange of configuration values for external vs. internal
1900 clock dividers.
72f4393d 1901
c906108c
SS		 1902Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1903
72f4393d 1904 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1905 simulator-reserved break instructions.
1906 * gencode.c (build_instruction): Ditto.
1907 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1908 reserved instructions now use exception vector, rather
c906108c
SS		 1909 than halting sim.
1910 * sim-main.h: Moved magic constants to here.
1911
1912Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1913
1914 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1915 register upon non-zero interrupt event level, clear upon zero
1916 event value.
1917 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1918 by passing zero event value.
1919 (*_io_{read,write}_buffer): Endianness fixes.
1920 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1921 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1922
1923 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1924 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1925
c906108c
SS		 1926Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1927
72f4393d 1928 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1929 and BigEndianCPU.
1930
1931Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1932
1933 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1934 parts.
1935 * configure: Update.
1936
1937Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1938
1939 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1940 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1941 * configure.in: Include tx3904tmr in hw_device list.
1942 * configure: Rebuilt.
1943 * interp.c (sim_open): Instantiate three timer instances.
1944 Fix address typo of tx3904irc instance.
1945
1946Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1947
1948 * interp.c (signal_exception): SystemCall exception now uses
1949 the exception vector.
1950
1951Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1952
1953 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1954 to allay warnings.
1955
1956Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1957
1958 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1959
1960Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1961
1962 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1963
1964 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1965 sim-main.h. Declare a struct hw_descriptor instead of struct
1966 hw_device_descriptor.
1967
1968Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1969
1970 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1971 right bits and then re-align left hand bytes to correct byte
1972 lanes. Fix incorrect computation in do_store_left when loading
1973 bytes from second word.
1974
1975Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1976
1977 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1978 * interp.c (sim_open): Only create a device tree when HW is
1979 enabled.
1980
1981 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1982 * interp.c (signal_exception): Ditto.
1983
1984Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
1985
1986 * gencode.c: Mark BEGEZALL as LIKELY.
1987
1988Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
1989
1990 * sim-main.h (ALU32_END): Sign extend 32 bit results.
1991 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 1992
c906108c
SS		 1993Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
1994
1995 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1996 modules. Recognize TX39 target with "mips*tx39" pattern.
1997 * configure: Rebuilt.
1998 * sim-main.h (*): Added many macros defining bits in
1999 TX39 control registers.
2000 (SignalInterrupt): Send actual PC instead of NULL.
2001 (SignalNMIReset): New exception type.
2002 * interp.c (board): New variable for future use to identify
2003 a particular board being simulated.
2004 (mips_option_handler,mips_options): Added "--board" option.
2005 (interrupt_event): Send actual PC.
2006 (sim_open): Make memory layout conditional on board setting.
2007 (signal_exception): Initial implementation of hardware interrupt
2008 handling. Accept another break instruction variant for simulator
2009 exit.
2010 (decode_coproc): Implement RFE instruction for TX39.
2011 (mips.igen): Decode RFE instruction as such.
2012 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2013 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2014 bbegin to implement memory map.
2015 * dv-tx3904cpu.c: New file.
2016 * dv-tx3904irc.c: New file.
2017
2018Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2019
2020 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2021
2022Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2023
2024 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2025 with calls to check_div_hilo.
2026
2027Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2028
2029 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2030 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2031 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2032 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2033 with calls to check_mult_hilo.
2034 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2035 with calls to check_div_hilo.
2036
2037Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2038
2039 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2040 Document a replacement.
2041
2042Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2043
2044 * interp.c (sim_monitor): Make mon_printf work.
2045
2046Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2047
2048 * sim-main.h (INSN_NAME): New arg `cpu'.
2049
2050Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2051
72f4393d 2052 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2053
2054Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2055
2056 * configure: Regenerated to track ../common/aclocal.m4 changes.
2057 * config.in: Ditto.
2058
2059Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2060
2061 * acconfig.h: New file.
2062 * configure.in: Reverted change of Apr 24; use sinclude again.
2063
2064Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2065
2066 * configure: Regenerated to track ../common/aclocal.m4 changes.
2067 * config.in: Ditto.
2068
2069Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2070
2071 * configure.in: Don't call sinclude.
2072
2073Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2074
2075 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2076
2077Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2078
2079 * mips.igen (ERET): Implement.
2080
2081 * interp.c (decode_coproc): Return sign-extended EPC.
2082
2083 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2084
2085 * interp.c (signal_exception): Do not ignore Trap.
2086 (signal_exception): On TRAP, restart at exception address.
2087 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2088 (signal_exception): Update.
2089 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2090 so that TRAP instructions are caught.
2091
2092Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2093
2094 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2095 contains HI/LO access history.
2096 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2097 (HIACCESS, LOACCESS): Delete, replace with
2098 (HIHISTORY, LOHISTORY): New macros.
2099 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2100
c906108c
SS		 2101 * gencode.c (build_instruction): Do not generate checks for
2102 correct HI/LO register usage.
2103
2104 * interp.c (old_engine_run): Delete checks for correct HI/LO
2105 register usage.
2106
2107 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2108 check_mf_cycles): New functions.
2109 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2110 do_divu, domultx, do_mult, do_multu): Use.
2111
2112 * tx.igen ("madd", "maddu"): Use.
72f4393d 2113
c906108c
SS		 2114Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2115
2116 * mips.igen (DSRAV): Use function do_dsrav.
2117 (SRAV): Use new function do_srav.
2118
2119 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2120 (B): Sign extend 11 bit immediate.
2121 (EXT-B*): Shift 16 bit immediate left by 1.
2122 (ADDIU*): Don't sign extend immediate value.
2123
2124Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2125
2126 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2127
2128 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2129 functions.
2130
2131 * mips.igen (delayslot32, nullify_next_insn): New functions.
2132 (m16.igen): Always include.
2133 (do_*): Add more tracing.
2134
2135 * m16.igen (delayslot16): Add NIA argument, could be called by a
2136 32 bit MIPS16 instruction.
72f4393d 2137
c906108c
SS		 2138 * interp.c (ifetch16): Move function from here.
2139 * sim-main.c (ifetch16): To here.
72f4393d 2140
c906108c
SS		 2141 * sim-main.c (ifetch16, ifetch32): Update to match current
2142 implementations of LH, LW.
2143 (signal_exception): Don't print out incorrect hex value of illegal
2144 instruction.
2145
2146Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2147
2148 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2149 instruction.
2150
2151 * m16.igen: Implement MIPS16 instructions.
72f4393d 2152
c906108c
SS		 2153 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2154 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2155 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2156 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2157 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2158 bodies of corresponding code from 32 bit insn to these. Also used
2159 by MIPS16 versions of functions.
72f4393d 2160
c906108c
SS		 2161 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2162 (IMEM16): Drop NR argument from macro.
2163
2164Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2165
2166 * Makefile.in (SIM_OBJS): Add sim-main.o.
2167
2168 * sim-main.h (address_translation, load_memory, store_memory,
2169 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2170 as INLINE_SIM_MAIN.
2171 (pr_addr, pr_uword64): Declare.
2172 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2173
c906108c
SS		 2174 * interp.c (address_translation, load_memory, store_memory,
2175 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2176 from here.
2177 * sim-main.c: To here. Fix compilation problems.
72f4393d 2178
c906108c
SS		 2179 * configure.in: Enable inlining.
2180 * configure: Re-config.
2181
2182Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * configure: Regenerated to track ../common/aclocal.m4 changes.
2185
2186Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2187
2188 * mips.igen: Include tx.igen.
2189 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2190 * tx.igen: New file, contains MADD and MADDU.
2191
2192 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2193 the hardwired constant `7'.
2194 (store_memory): Ditto.
2195 (LOADDRMASK): Move definition to sim-main.h.
2196
2197 mips.igen (MTC0): Enable for r3900.
2198 (ADDU): Add trace.
2199
2200 mips.igen (do_load_byte): Delete.
2201 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2202 do_store_right): New functions.
2203 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2204
2205 configure.in: Let the tx39 use igen again.
2206 configure: Update.
72f4393d 2207
c906108c
SS		 2208Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2211 not an address sized quantity. Return zero for cache sizes.
2212
2213Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2214
2215 * mips.igen (r3900): r3900 does not support 64 bit integer
2216 operations.
2217
2218Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2219
2220 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2221 than igen one.
2222 * configure : Rebuild.
72f4393d 2223
c906108c
SS		 2224Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2225
2226 * configure: Regenerated to track ../common/aclocal.m4 changes.
2227
2228Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2229
2230 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2231
2232Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2233
2234 * configure: Regenerated to track ../common/aclocal.m4 changes.
2235 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2236
2237Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2238
2239 * configure: Regenerated to track ../common/aclocal.m4 changes.
2240
2241Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2242
2243 * interp.c (Max, Min): Comment out functions. Not yet used.
2244
2245Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * configure: Regenerated to track ../common/aclocal.m4 changes.
2248
2249Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2250
2251 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2252 configurable settings for stand-alone simulator.
72f4393d 2253
c906108c 2254 * configure.in: Added X11 search, just in case.
72f4393d 2255
c906108c
SS		 2256 * configure: Regenerated.
2257
2258Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * interp.c (sim_write, sim_read, load_memory, store_memory):
2261 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2262
2263Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2264
2265 * sim-main.h (GETFCC): Return an unsigned value.
2266
2267Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2270 (DADD): Result destination is RD not RT.
2271
2272Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2273
2274 * sim-main.h (HIACCESS, LOACCESS): Always define.
2275
2276 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2277
2278 * interp.c (sim_info): Delete.
2279
2280Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2281
2282 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2283 (mips_option_handler): New argument `cpu'.
2284 (sim_open): Update call to sim_add_option_table.
2285
2286Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2287
2288 * mips.igen (CxC1): Add tracing.
2289
2290Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2291
2292 * sim-main.h (Max, Min): Declare.
2293
2294 * interp.c (Max, Min): New functions.
2295
2296 * mips.igen (BC1): Add tracing.
72f4393d 2297
c906108c 2298Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2299
c906108c 2300 * interp.c Added memory map for stack in vr4100
72f4393d 2301
c906108c
SS		 2302Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2303
2304 * interp.c (load_memory): Add missing "break"'s.
2305
2306Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2307
2308 * interp.c (sim_store_register, sim_fetch_register): Pass in
2309 length parameter. Return -1.
2310
2311Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2312
2313 * interp.c: Added hardware init hook, fixed warnings.
2314
2315Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2316
2317 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2318
2319Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2320
2321 * interp.c (ifetch16): New function.
2322
2323 * sim-main.h (IMEM32): Rename IMEM.
2324 (IMEM16_IMMED): Define.
2325 (IMEM16): Define.
2326 (DELAY_SLOT): Update.
72f4393d 2327
c906108c 2328 * m16run.c (sim_engine_run): New file.
72f4393d 2329
c906108c
SS		 2330 * m16.igen: All instructions except LB.
2331 (LB): Call do_load_byte.
2332 * mips.igen (do_load_byte): New function.
2333 (LB): Call do_load_byte.
2334
2335 * mips.igen: Move spec for insn bit size and high bit from here.
2336 * Makefile.in (tmp-igen, tmp-m16): To here.
2337
2338 * m16.dc: New file, decode mips16 instructions.
2339
2340 * Makefile.in (SIM_NO_ALL): Define.
2341 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2342
2343Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2344
2345 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2346 point unit to 32 bit registers.
2347 * configure: Re-generate.
2348
2349Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * configure.in (sim_use_gen): Make IGEN the default simulator
2352 generator for generic 32 and 64 bit mips targets.
2353 * configure: Re-generate.
2354
2355Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2356
2357 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2358 bitsize.
2359
2360 * interp.c (sim_fetch_register, sim_store_register): Read/write
2361 FGR from correct location.
2362 (sim_open): Set size of FGR's according to
2363 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2364
c906108c
SS		 2365 * sim-main.h (FGR): Store floating point registers in a separate
2366 array.
2367
2368Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2369
2370 * configure: Regenerated to track ../common/aclocal.m4 changes.
2371
2372Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2373
2374 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2375
2376 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2377
2378 * interp.c (pending_tick): New function. Deliver pending writes.
2379
2380 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2381 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2382 it can handle mixed sized quantites and single bits.
72f4393d 2383
c906108c
SS		 2384Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2385
2386 * interp.c (oengine.h): Do not include when building with IGEN.
2387 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2388 (sim_info): Ditto for PROCESSOR_64BIT.
2389 (sim_monitor): Replace ut_reg with unsigned_word.
2390 (*): Ditto for t_reg.
2391 (LOADDRMASK): Define.
2392 (sim_open): Remove defunct check that host FP is IEEE compliant,
2393 using software to emulate floating point.
2394 (value_fpr, ...): Always compile, was conditional on HASFPU.
2395
2396Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2397
2398 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2399 size.
2400
2401 * interp.c (SD, CPU): Define.
2402 (mips_option_handler): Set flags in each CPU.
2403 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2404 (sim_close): Do not clear STATE, deleted anyway.
2405 (sim_write, sim_read): Assume CPU zero's vm should be used for
2406 data transfers.
2407 (sim_create_inferior): Set the PC for all processors.
2408 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2409 argument.
2410 (mips16_entry): Pass correct nr of args to store_word, load_word.
2411 (ColdReset): Cold reset all cpu's.
2412 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2413 (sim_monitor, load_memory, store_memory, signal_exception): Use
2414 `CPU' instead of STATE_CPU.
2415
2416
2417 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2418 SD or CPU_.
72f4393d 2419
c906108c
SS		 2420 * sim-main.h (signal_exception): Add sim_cpu arg.
2421 (SignalException*): Pass both SD and CPU to signal_exception.
2422 * interp.c (signal_exception): Update.
72f4393d 2423
c906108c
SS		 2424 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2425 Ditto
2426 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2427 address_translation): Ditto
2428 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2429
c906108c
SS		 2430Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2431
2432 * configure: Regenerated to track ../common/aclocal.m4 changes.
2433
2434Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2435
2436 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2437
72f4393d 2438 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2439
2440 * sim-main.h (CPU_CIA): Delete.
2441 (SET_CIA, GET_CIA): Define
2442
2443Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2444
2445 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2446 regiser.
2447
2448 * configure.in (default_endian): Configure a big-endian simulator
2449 by default.
2450 * configure: Re-generate.
72f4393d 2451
c906108c
SS		 2452Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2453
2454 * configure: Regenerated to track ../common/aclocal.m4 changes.
2455
2456Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2457
2458 * interp.c (sim_monitor): Handle Densan monitor outbyte
2459 and inbyte functions.
2460
24611997-12-29 Felix Lee <flee@cygnus.com>
2462
2463 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2464
2465Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2466
2467 * Makefile.in (tmp-igen): Arrange for $zero to always be
2468 reset to zero after every instruction.
2469
2470Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2471
2472 * configure: Regenerated to track ../common/aclocal.m4 changes.
2473 * config.in: Ditto.
2474
2475Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2476
2477 * mips.igen (MSUB): Fix to work like MADD.
2478 * gencode.c (MSUB): Similarly.
2479
2480Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2481
2482 * configure: Regenerated to track ../common/aclocal.m4 changes.
2483
2484Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2485
2486 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2487
2488Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2489
2490 * sim-main.h (sim-fpu.h): Include.
2491
2492 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2493 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2494 using host independant sim_fpu module.
2495
2496Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2497
2498 * interp.c (signal_exception): Report internal errors with SIGABRT
2499 not SIGQUIT.
2500
2501 * sim-main.h (C0_CONFIG): New register.
2502 (signal.h): No longer include.
2503
2504 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2505
2506Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2507
2508 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2509
2510Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2511
2512 * mips.igen: Tag vr5000 instructions.
2513 (ANDI): Was missing mipsIV model, fix assembler syntax.
2514 (do_c_cond_fmt): New function.
2515 (C.cond.fmt): Handle mips I-III which do not support CC field
2516 separatly.
2517 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2518 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2519 in IV3.2 spec.
2520 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2521 vr5000 which saves LO in a GPR separatly.
72f4393d 2522
c906108c
SS		 2523 * configure.in (enable-sim-igen): For vr5000, select vr5000
2524 specific instructions.
2525 * configure: Re-generate.
72f4393d 2526
c906108c
SS		 2527Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528
2529 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2530
2531 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2532 fmt_uninterpreted_64 bit cases to switch. Convert to
2533 fmt_formatted,
2534
2535 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2536
2537 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2538 as specified in IV3.2 spec.
2539 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2540
2541Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2542
2543 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2544 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2545 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2546 PENDING_FILL versions of instructions. Simplify.
2547 (X): New function.
2548 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2549 instructions.
2550 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2551 a signed value.
2552 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2553
c906108c
SS		 2554 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2555 global.
2556 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2557
2558Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2559
2560 * gencode.c (build_mips16_operands): Replace IPC with cia.
2561
2562 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2563 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2564 IPC to `cia'.
2565 (UndefinedResult): Replace function with macro/function
2566 combination.
2567 (sim_engine_run): Don't save PC in IPC.
2568
2569 * sim-main.h (IPC): Delete.
2570
2571
2572 * interp.c (signal_exception, store_word, load_word,
2573 address_translation, load_memory, store_memory, cache_op,
2574 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2575 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2576 current instruction address - cia - argument.
2577 (sim_read, sim_write): Call address_translation directly.
2578 (sim_engine_run): Rename variable vaddr to cia.
2579 (signal_exception): Pass cia to sim_monitor
72f4393d 2580
c906108c
SS		 2581 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2582 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2583 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2584
2585 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2586 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2587 SIM_ASSERT.
72f4393d 2588
c906108c
SS		 2589 * interp.c (signal_exception): Pass restart address to
2590 sim_engine_restart.
2591
2592 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2593 idecode.o): Add dependency.
2594
2595 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2596 Delete definitions
2597 (DELAY_SLOT): Update NIA not PC with branch address.
2598 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2599
2600 * mips.igen: Use CIA not PC in branch calculations.
2601 (illegal): Call SignalException.
2602 (BEQ, ADDIU): Fix assembler.
2603
2604Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2605
2606 * m16.igen (JALX): Was missing.
2607
2608 * configure.in (enable-sim-igen): New configuration option.
2609 * configure: Re-generate.
72f4393d 2610
c906108c
SS		 2611 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2612
2613 * interp.c (load_memory, store_memory): Delete parameter RAW.
2614 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2615 bypassing {load,store}_memory.
2616
2617 * sim-main.h (ByteSwapMem): Delete definition.
2618
2619 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2620
2621 * interp.c (sim_do_command, sim_commands): Delete mips specific
2622 commands. Handled by module sim-options.
72f4393d 2623
c906108c
SS		 2624 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2625 (WITH_MODULO_MEMORY): Define.
2626
2627 * interp.c (sim_info): Delete code printing memory size.
2628
2629 * interp.c (mips_size): Nee sim_size, delete function.
2630 (power2): Delete.
2631 (monitor, monitor_base, monitor_size): Delete global variables.
2632 (sim_open, sim_close): Delete code creating monitor and other
2633 memory regions. Use sim-memopts module, via sim_do_commandf, to
2634 manage memory regions.
2635 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2636
c906108c
SS		 2637 * interp.c (address_translation): Delete all memory map code
2638 except line forcing 32 bit addresses.
2639
2640Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2641
2642 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2643 trace options.
2644
2645 * interp.c (logfh, logfile): Delete globals.
2646 (sim_open, sim_close): Delete code opening & closing log file.
2647 (mips_option_handler): Delete -l and -n options.
2648 (OPTION mips_options): Ditto.
2649
2650 * interp.c (OPTION mips_options): Rename option trace to dinero.
2651 (mips_option_handler): Update.
2652
2653Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2654
2655 * interp.c (fetch_str): New function.
2656 (sim_monitor): Rewrite using sim_read & sim_write.
2657 (sim_open): Check magic number.
2658 (sim_open): Write monitor vectors into memory using sim_write.
2659 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2660 (sim_read, sim_write): Simplify - transfer data one byte at a
2661 time.
2662 (load_memory, store_memory): Clarify meaning of parameter RAW.
2663
2664 * sim-main.h (isHOST): Defete definition.
2665 (isTARGET): Mark as depreciated.
2666 (address_translation): Delete parameter HOST.
2667
2668 * interp.c (address_translation): Delete parameter HOST.
2669
2670Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2671
72f4393d 2672 * mips.igen:
c906108c
SS		 2673
2674 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2675 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2676
2677Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2678
2679 * mips.igen: Add model filter field to records.
2680
2681Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2682
2683 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2684
c906108c
SS		 2685 interp.c (sim_engine_run): Do not compile function sim_engine_run
2686 when WITH_IGEN == 1.
2687
2688 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2689 target architecture.
2690
2691 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2692 igen. Replace with configuration variables sim_igen_flags /
2693 sim_m16_flags.
2694
2695 * m16.igen: New file. Copy mips16 insns here.
2696 * mips.igen: From here.
2697
2698Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2699
2700 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2701 to top.
2702 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2703
2704Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2705
2706 * gencode.c (build_instruction): Follow sim_write's lead in using
2707 BigEndianMem instead of !ByteSwapMem.
2708
2709Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2710
2711 * configure.in (sim_gen): Dependent on target, select type of
2712 generator. Always select old style generator.
2713
2714 configure: Re-generate.
2715
2716 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2717 targets.
2718 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2719 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2720 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2721 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2722 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2723
c906108c
SS		 2724Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725
2726 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2727
2728 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2729 CURRENT_FLOATING_POINT instead.
2730
2731 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2732 (address_translation): Raise exception InstructionFetch when
2733 translation fails and isINSTRUCTION.
72f4393d 2734
c906108c
SS		 2735 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2736 sim_engine_run): Change type of of vaddr and paddr to
2737 address_word.
2738 (address_translation, prefetch, load_memory, store_memory,
2739 cache_op): Change type of vAddr and pAddr to address_word.
2740
2741 * gencode.c (build_instruction): Change type of vaddr and paddr to
2742 address_word.
2743
2744Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2745
2746 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2747 macro to obtain result of ALU op.
2748
2749Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2750
2751 * interp.c (sim_info): Call profile_print.
2752
2753Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2754
2755 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2756
2757 * sim-main.h (WITH_PROFILE): Do not define, defined in
2758 common/sim-config.h. Use sim-profile module.
2759 (simPROFILE): Delete defintion.
2760
2761 * interp.c (PROFILE): Delete definition.
2762 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2763 (sim_close): Delete code writing profile histogram.
2764 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2765 Delete.
2766 (sim_engine_run): Delete code profiling the PC.
2767
2768Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2769
2770 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2771
2772 * interp.c (sim_monitor): Make register pointers of type
2773 unsigned_word*.
2774
2775 * sim-main.h: Make registers of type unsigned_word not
2776 signed_word.
2777
2778Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2779
2780 * interp.c (sync_operation): Rename from SyncOperation, make
2781 global, add SD argument.
2782 (prefetch): Rename from Prefetch, make global, add SD argument.
2783 (decode_coproc): Make global.
2784
2785 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2786
2787 * gencode.c (build_instruction): Generate DecodeCoproc not
2788 decode_coproc calls.
2789
2790 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2791 (SizeFGR): Move to sim-main.h
2792 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2793 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2794 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2795 sim-main.h.
2796 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2797 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2798 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2799 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2800 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2801 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2802
c906108c
SS		 2803 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2804 exception.
2805 (sim-alu.h): Include.
2806 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2807 (sim_cia): Typedef to instruction_address.
72f4393d 2808
c906108c
SS		 2809Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2810
2811 * Makefile.in (interp.o): Rename generated file engine.c to
2812 oengine.c.
72f4393d 2813
c906108c 2814 * interp.c: Update.
72f4393d 2815
c906108c
SS		 2816Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2817
2818 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2819
c906108c
SS		 2820Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2821
2822 * gencode.c (build_instruction): For "FPSQRT", output correct
2823 number of arguments to Recip.
72f4393d 2824
c906108c
SS		 2825Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2826
2827 * Makefile.in (interp.o): Depends on sim-main.h
2828
2829 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2830
2831 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2832 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2833 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2834 STATE, DSSTATE): Define
2835 (GPR, FGRIDX, ..): Define.
2836
2837 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2838 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2839 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2840
c906108c 2841 * interp.c: Update names to match defines from sim-main.h
72f4393d 2842
c906108c
SS		 2843Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * interp.c (sim_monitor): Add SD argument.
2846 (sim_warning): Delete. Replace calls with calls to
2847 sim_io_eprintf.
2848 (sim_error): Delete. Replace calls with sim_io_error.
2849 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2850 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2851 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2852 argument.
2853 (mips_size): Rename from sim_size. Add SD argument.
2854
2855 * interp.c (simulator): Delete global variable.
2856 (callback): Delete global variable.
2857 (mips_option_handler, sim_open, sim_write, sim_read,
2858 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2859 sim_size,sim_monitor): Use sim_io_* not callback->*.
2860 (sim_open): ZALLOC simulator struct.
2861 (PROFILE): Do not define.
2862
2863Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2864
2865 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2866 support.h with corresponding code.
2867
2868 * sim-main.h (word64, uword64), support.h: Move definition to
2869 sim-main.h.
2870 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2871
2872 * support.h: Delete
2873 * Makefile.in: Update dependencies
2874 * interp.c: Do not include.
72f4393d 2875
c906108c
SS		 2876Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2877
2878 * interp.c (address_translation, load_memory, store_memory,
2879 cache_op): Rename to from AddressTranslation et.al., make global,
2880 add SD argument
72f4393d 2881
c906108c
SS		 2882 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2883 CacheOp): Define.
72f4393d 2884
c906108c
SS		 2885 * interp.c (SignalException): Rename to signal_exception, make
2886 global.
2887
2888 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2889
c906108c
SS		 2890 * sim-main.h (SignalException, SignalExceptionInterrupt,
2891 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2892 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2893 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2894 Define.
72f4393d 2895
c906108c 2896 * interp.c, support.h: Use.
72f4393d 2897
c906108c
SS		 2898Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2899
2900 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2901 to value_fpr / store_fpr. Add SD argument.
2902 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2903 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2904
2905 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2906
c906108c
SS		 2907Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2908
2909 * interp.c (sim_engine_run): Check consistency between configure
2910 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2911 and HASFPU.
2912
2913 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2914 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2915 (mips_endian): Configure WITH_TARGET_ENDIAN.
2916 * configure: Update.
2917
2918Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2919
2920 * configure: Regenerated to track ../common/aclocal.m4 changes.
2921
2922Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2923
2924 * configure: Regenerated.
2925
2926Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2927
2928 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2929
2930Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2931
2932 * gencode.c (print_igen_insn_models): Assume certain architectures
2933 include all mips* instructions.
2934 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2935 instruction.
2936
2937 * Makefile.in (tmp.igen): Add target. Generate igen input from
2938 gencode file.
2939
2940 * gencode.c (FEATURE_IGEN): Define.
2941 (main): Add --igen option. Generate output in igen format.
2942 (process_instructions): Format output according to igen option.
2943 (print_igen_insn_format): New function.
2944 (print_igen_insn_models): New function.
2945 (process_instructions): Only issue warnings and ignore
2946 instructions when no FEATURE_IGEN.
2947
2948Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2949
2950 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2951 MIPS targets.
2952
2953Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2954
2955 * configure: Regenerated to track ../common/aclocal.m4 changes.
2956
2957Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2958
2959 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2960 SIM_RESERVED_BITS): Delete, moved to common.
2961 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2962
c906108c
SS		 2963Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2964
2965 * configure.in: Configure non-strict memory alignment.
2966 * configure: Regenerated to track ../common/aclocal.m4 changes.
2967
2968Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2969
2970 * configure: Regenerated to track ../common/aclocal.m4 changes.
2971
2972Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2973
2974 * gencode.c (SDBBP,DERET): Added (3900) insns.
2975 (RFE): Turn on for 3900.
2976 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2977 (dsstate): Made global.
2978 (SUBTARGET_R3900): Added.
2979 (CANCELDELAYSLOT): New.
2980 (SignalException): Ignore SystemCall rather than ignore and
2981 terminate. Add DebugBreakPoint handling.
2982 (decode_coproc): New insns RFE, DERET; and new registers Debug
2983 and DEPC protected by SUBTARGET_R3900.
2984 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2985 bits explicitly.
2986 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 2987 * configure: Update.
c906108c
SS		 2988
2989Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
2990
2991 * gencode.c: Add r3900 (tx39).
72f4393d 2992
c906108c
SS		 2993
2994Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
2995
2996 * gencode.c (build_instruction): Don't need to subtract 4 for
2997 JALR, just 2.
2998
2999Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3000
3001 * interp.c: Correct some HASFPU problems.
3002
3003Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3004
3005 * configure: Regenerated to track ../common/aclocal.m4 changes.
3006
3007Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3008
3009 * interp.c (mips_options): Fix samples option short form, should
3010 be `x'.
3011
3012Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3013
3014 * interp.c (sim_info): Enable info code. Was just returning.
3015
3016Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3017
3018 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3019 MFC0.
3020
3021Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3022
3023 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3024 constants.
3025 (build_instruction): Ditto for LL.
3026
3027Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3028
3029 * configure: Regenerated to track ../common/aclocal.m4 changes.
3030
3031Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3032
3033 * configure: Regenerated to track ../common/aclocal.m4 changes.
3034 * config.in: Ditto.
3035
3036Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3037
3038 * interp.c (sim_open): Add call to sim_analyze_program, update
3039 call to sim_config.
3040
3041Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3042
3043 * interp.c (sim_kill): Delete.
3044 (sim_create_inferior): Add ABFD argument. Set PC from same.
3045 (sim_load): Move code initializing trap handlers from here.
3046 (sim_open): To here.
3047 (sim_load): Delete, use sim-hload.c.
3048
3049 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3050
3051Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3052
3053 * configure: Regenerated to track ../common/aclocal.m4 changes.
3054 * config.in: Ditto.
3055
3056Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3057
3058 * interp.c (sim_open): Add ABFD argument.
3059 (sim_load): Move call to sim_config from here.
3060 (sim_open): To here. Check return status.
3061
3062Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3063
c906108c
SS		 3064 * gencode.c (build_instruction): Two arg MADD should
3065 not assign result to $0.
72f4393d 3066
c906108c
SS		 3067Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3068
3069 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3070 * sim/mips/configure.in: Regenerate.
3071
3072Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3073
3074 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3075 signed8, unsigned8 et.al. types.
3076
3077 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3078 hosts when selecting subreg.
3079
3080Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3081
3082 * interp.c (sim_engine_run): Reset the ZERO register to zero
3083 regardless of FEATURE_WARN_ZERO.
3084 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3085
3086Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3087
3088 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3089 (SignalException): For BreakPoints ignore any mode bits and just
3090 save the PC.
3091 (SignalException): Always set the CAUSE register.
3092
3093Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3094
3095 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3096 exception has been taken.
3097
3098 * interp.c: Implement the ERET and mt/f sr instructions.
3099
3100Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3101
3102 * interp.c (SignalException): Don't bother restarting an
3103 interrupt.
3104
3105Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3106
3107 * interp.c (SignalException): Really take an interrupt.
3108 (interrupt_event): Only deliver interrupts when enabled.
3109
3110Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3111
3112 * interp.c (sim_info): Only print info when verbose.
3113 (sim_info) Use sim_io_printf for output.
72f4393d 3114
c906108c
SS		 3115Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3116
3117 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3118 mips architectures.
3119
3120Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3121
3122 * interp.c (sim_do_command): Check for common commands if a
3123 simulator specific command fails.
3124
3125Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3126
3127 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3128 and simBE when DEBUG is defined.
3129
3130Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3131
3132 * interp.c (interrupt_event): New function. Pass exception event
3133 onto exception handler.
3134
3135 * configure.in: Check for stdlib.h.
3136 * configure: Regenerate.
3137
3138 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3139 variable declaration.
3140 (build_instruction): Initialize memval1.
3141 (build_instruction): Add UNUSED attribute to byte, bigend,
3142 reverse.
3143 (build_operands): Ditto.
3144
3145 * interp.c: Fix GCC warnings.
3146 (sim_get_quit_code): Delete.
3147
3148 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3149 * Makefile.in: Ditto.
3150 * configure: Re-generate.
72f4393d 3151
c906108c
SS		 3152 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3153
3154Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3155
3156 * interp.c (mips_option_handler): New function parse argumes using
3157 sim-options.
3158 (myname): Replace with STATE_MY_NAME.
3159 (sim_open): Delete check for host endianness - performed by
3160 sim_config.
3161 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3162 (sim_open): Move much of the initialization from here.
3163 (sim_load): To here. After the image has been loaded and
3164 endianness set.
3165 (sim_open): Move ColdReset from here.
3166 (sim_create_inferior): To here.
3167 (sim_open): Make FP check less dependant on host endianness.
3168
3169 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3170 run.
3171 * interp.c (sim_set_callbacks): Delete.
3172
3173 * interp.c (membank, membank_base, membank_size): Replace with
3174 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3175 (sim_open): Remove call to callback->init. gdb/run do this.
3176
3177 * interp.c: Update
3178
3179 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3180
3181 * interp.c (big_endian_p): Delete, replaced by
3182 current_target_byte_order.
3183
3184Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3185
3186 * interp.c (host_read_long, host_read_word, host_swap_word,
3187 host_swap_long): Delete. Using common sim-endian.
3188 (sim_fetch_register, sim_store_register): Use H2T.
3189 (pipeline_ticks): Delete. Handled by sim-events.
3190 (sim_info): Update.
3191 (sim_engine_run): Update.
3192
3193Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3194
3195 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3196 reason from here.
3197 (SignalException): To here. Signal using sim_engine_halt.
3198 (sim_stop_reason): Delete, moved to common.
72f4393d 3199
c906108c
SS		 3200Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3201
3202 * interp.c (sim_open): Add callback argument.
3203 (sim_set_callbacks): Delete SIM_DESC argument.
3204 (sim_size): Ditto.
3205
3206Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3207
3208 * Makefile.in (SIM_OBJS): Add common modules.
3209
3210 * interp.c (sim_set_callbacks): Also set SD callback.
3211 (set_endianness, xfer_*, swap_*): Delete.
3212 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3213 Change to functions using sim-endian macros.
3214 (control_c, sim_stop): Delete, use common version.
3215 (simulate): Convert into.
3216 (sim_engine_run): This function.
3217 (sim_resume): Delete.
72f4393d 3218
c906108c
SS		 3219 * interp.c (simulation): New variable - the simulator object.
3220 (sim_kind): Delete global - merged into simulation.
3221 (sim_load): Cleanup. Move PC assignment from here.
3222 (sim_create_inferior): To here.
3223
3224 * sim-main.h: New file.
3225 * interp.c (sim-main.h): Include.
72f4393d 3226
c906108c
SS		 3227Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3228
3229 * configure: Regenerated to track ../common/aclocal.m4 changes.
3230
3231Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3232
3233 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3234
3235Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3236
72f4393d
L		 3237 * gencode.c (build_instruction): DIV instructions: check
3238 for division by zero and integer overflow before using
c906108c
SS		 3239 host's division operation.
3240
3241Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3242
3243 * Makefile.in (SIM_OBJS): Add sim-load.o.
3244 * interp.c: #include bfd.h.
3245 (target_byte_order): Delete.
3246 (sim_kind, myname, big_endian_p): New static locals.
3247 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3248 after argument parsing. Recognize -E arg, set endianness accordingly.
3249 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3250 load file into simulator. Set PC from bfd.
3251 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3252 (set_endianness): Use big_endian_p instead of target_byte_order.
3253
3254Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3255
3256 * interp.c (sim_size): Delete prototype - conflicts with
3257 definition in remote-sim.h. Correct definition.
3258
3259Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3260
3261 * configure: Regenerated to track ../common/aclocal.m4 changes.
3262 * config.in: Ditto.
3263
3264Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3265
3266 * interp.c (sim_open): New arg `kind'.
3267
3268 * configure: Regenerated to track ../common/aclocal.m4 changes.
3269
3270Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3271
3272 * configure: Regenerated to track ../common/aclocal.m4 changes.
3273
3274Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3275
3276 * interp.c (sim_open): Set optind to 0 before calling getopt.
3277
3278Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3279
3280 * configure: Regenerated to track ../common/aclocal.m4 changes.
3281
3282Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3283
3284 * interp.c : Replace uses of pr_addr with pr_uword64
3285 where the bit length is always 64 independent of SIM_ADDR.
3286 (pr_uword64) : added.
3287
3288Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3289
3290 * configure: Re-generate.
3291
3292Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3293
3294 * configure: Regenerate to track ../common/aclocal.m4 changes.
3295
3296Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3297
3298 * interp.c (sim_open): New SIM_DESC result. Argument is now
3299 in argv form.
3300 (other sim_*): New SIM_DESC argument.
3301
3302Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3303
3304 * interp.c: Fix printing of addresses for non-64-bit targets.
3305 (pr_addr): Add function to print address based on size.
3306
3307Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3308
3309 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3310
3311Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3312
3313 * gencode.c (build_mips16_operands): Correct computation of base
3314 address for extended PC relative instruction.
3315
3316Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3317
3318 * interp.c (mips16_entry): Add support for floating point cases.
3319 (SignalException): Pass floating point cases to mips16_entry.
3320 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3321 registers.
3322 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3323 or fmt_word.
3324 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3325 and then set the state to fmt_uninterpreted.
3326 (COP_SW): Temporarily set the state to fmt_word while calling
3327 ValueFPR.
3328
3329Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3330
3331 * gencode.c (build_instruction): The high order may be set in the
3332 comparison flags at any ISA level, not just ISA 4.
3333
3334Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3335
3336 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3337 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3338 * configure.in: sinclude ../common/aclocal.m4.
3339 * configure: Regenerated.
3340
3341Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3342
3343 * configure: Rebuild after change to aclocal.m4.
3344
3345Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3346
3347 * configure configure.in Makefile.in: Update to new configure
3348 scheme which is more compatible with WinGDB builds.
3349 * configure.in: Improve comment on how to run autoconf.
3350 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3351 * Makefile.in: Use autoconf substitution to install common
3352 makefile fragment.
3353
3354Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3355
3356 * gencode.c (build_instruction): Use BigEndianCPU instead of
3357 ByteSwapMem.
3358
3359Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3360
3361 * interp.c (sim_monitor): Make output to stdout visible in
3362 wingdb's I/O log window.
3363
3364Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3365
3366 * support.h: Undo previous change to SIGTRAP
3367 and SIGQUIT values.
3368
3369Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3370
3371 * interp.c (store_word, load_word): New static functions.
3372 (mips16_entry): New static function.
3373 (SignalException): Look for mips16 entry and exit instructions.
3374 (simulate): Use the correct index when setting fpr_state after
3375 doing a pending move.
3376
3377Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3378
3379 * interp.c: Fix byte-swapping code throughout to work on
3380 both little- and big-endian hosts.
3381
3382Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3383
3384 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3385 with gdb/config/i386/xm-windows.h.
3386
3387Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3388
3389 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3390 that messes up arithmetic shifts.
3391
3392Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3393
3394 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3395 SIGTRAP and SIGQUIT for _WIN32.
3396
3397Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3398
3399 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3400 force a 64 bit multiplication.
3401 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3402 destination register is 0, since that is the default mips16 nop
3403 instruction.
3404
3405Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3406
3407 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3408 (build_endian_shift): Don't check proc64.
3409 (build_instruction): Always set memval to uword64. Cast op2 to
3410 uword64 when shifting it left in memory instructions. Always use
3411 the same code for stores--don't special case proc64.
3412
3413 * gencode.c (build_mips16_operands): Fix base PC value for PC
3414 relative operands.
3415 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3416 jal instruction.
3417 * interp.c (simJALDELAYSLOT): Define.
3418 (JALDELAYSLOT): Define.
3419 (INDELAYSLOT, INJALDELAYSLOT): Define.
3420 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3421
3422Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3423
3424 * interp.c (sim_open): add flush_cache as a PMON routine
3425 (sim_monitor): handle flush_cache by ignoring it
3426
3427Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3428
3429 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3430 BigEndianMem.
3431 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3432 (BigEndianMem): Rename to ByteSwapMem and change sense.
3433 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3434 BigEndianMem references to !ByteSwapMem.
3435 (set_endianness): New function, with prototype.
3436 (sim_open): Call set_endianness.
3437 (sim_info): Use simBE instead of BigEndianMem.
3438 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3439 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3440 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3441 ifdefs, keeping the prototype declaration.
3442 (swap_word): Rewrite correctly.
3443 (ColdReset): Delete references to CONFIG. Delete endianness related
3444 code; moved to set_endianness.
72f4393d 3445
c906108c
SS		 3446Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3447
3448 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3449 * interp.c (CHECKHILO): Define away.
3450 (simSIGINT): New macro.
3451 (membank_size): Increase from 1MB to 2MB.
3452 (control_c): New function.
3453 (sim_resume): Rename parameter signal to signal_number. Add local
3454 variable prev. Call signal before and after simulate.
3455 (sim_stop_reason): Add simSIGINT support.
3456 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3457 functions always.
3458 (sim_warning): Delete call to SignalException. Do call printf_filtered
3459 if logfh is NULL.
3460 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3461 a call to sim_warning.
3462
3463Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3464
3465 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3466 16 bit instructions.
3467
3468Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3469
3470 Add support for mips16 (16 bit MIPS implementation):
3471 * gencode.c (inst_type): Add mips16 instruction encoding types.
3472 (GETDATASIZEINSN): Define.
3473 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3474 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3475 mtlo.
3476 (MIPS16_DECODE): New table, for mips16 instructions.
3477 (bitmap_val): New static function.
3478 (struct mips16_op): Define.
3479 (mips16_op_table): New table, for mips16 operands.
3480 (build_mips16_operands): New static function.
3481 (process_instructions): If PC is odd, decode a mips16
3482 instruction. Break out instruction handling into new
3483 build_instruction function.
3484 (build_instruction): New static function, broken out of
3485 process_instructions. Check modifiers rather than flags for SHIFT
3486 bit count and m[ft]{hi,lo} direction.
3487 (usage): Pass program name to fprintf.
3488 (main): Remove unused variable this_option_optind. Change
3489 ``*loptarg++'' to ``loptarg++''.
3490 (my_strtoul): Parenthesize && within ||.
3491 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3492 (simulate): If PC is odd, fetch a 16 bit instruction, and
3493 increment PC by 2 rather than 4.
3494 * configure.in: Add case for mips16*-*-*.
3495 * configure: Rebuild.
3496
3497Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3498
3499 * interp.c: Allow -t to enable tracing in standalone simulator.
3500 Fix garbage output in trace file and error messages.
3501
3502Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3503
3504 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3505 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3506 * configure.in: Simplify using macros in ../common/aclocal.m4.
3507 * configure: Regenerated.
3508 * tconfig.in: New file.
3509
3510Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3511
3512 * interp.c: Fix bugs in 64-bit port.
3513 Use ansi function declarations for msvc compiler.
3514 Initialize and test file pointer in trace code.
3515 Prevent duplicate definition of LAST_EMED_REGNUM.
3516
3517Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3518
3519 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3520
3521Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3522
3523 * interp.c (SignalException): Check for explicit terminating
3524 breakpoint value.
3525 * gencode.c: Pass instruction value through SignalException()
3526 calls for Trap, Breakpoint and Syscall.
3527
3528Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3529
3530 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3531 only used on those hosts that provide it.
3532 * configure.in: Add sqrt() to list of functions to be checked for.
3533 * config.in: Re-generated.
3534 * configure: Re-generated.
3535
3536Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3537
3538 * gencode.c (process_instructions): Call build_endian_shift when
3539 expanding STORE RIGHT, to fix swr.
3540 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3541 clear the high bits.
3542 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3543 Fix float to int conversions to produce signed values.
3544
3545Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3546
3547 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3548 (process_instructions): Correct handling of nor instruction.
3549 Correct shift count for 32 bit shift instructions. Correct sign
3550 extension for arithmetic shifts to not shift the number of bits in
3551 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3552 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3553 Fix madd.
3554 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3555 It's OK to have a mult follow a mult. What's not OK is to have a
3556 mult follow an mfhi.
3557 (Convert): Comment out incorrect rounding code.
3558
3559Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3560
3561 * interp.c (sim_monitor): Improved monitor printf
3562 simulation. Tidied up simulator warnings, and added "--log" option
3563 for directing warning message output.
3564 * gencode.c: Use sim_warning() rather than WARNING macro.
3565
3566Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3567
3568 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3569 getopt1.o, rather than on gencode.c. Link objects together.
3570 Don't link against -liberty.
3571 (gencode.o, getopt.o, getopt1.o): New targets.
3572 * gencode.c: Include <ctype.h> and "ansidecl.h".
3573 (AND): Undefine after including "ansidecl.h".
3574 (ULONG_MAX): Define if not defined.
3575 (OP_*): Don't define macros; now defined in opcode/mips.h.
3576 (main): Call my_strtoul rather than strtoul.
3577 (my_strtoul): New static function.
3578
3579Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3580
3581 * gencode.c (process_instructions): Generate word64 and uword64
3582 instead of `long long' and `unsigned long long' data types.
3583 * interp.c: #include sysdep.h to get signals, and define default
3584 for SIGBUS.
3585 * (Convert): Work around for Visual-C++ compiler bug with type
3586 conversion.
3587 * support.h: Make things compile under Visual-C++ by using
3588 __int64 instead of `long long'. Change many refs to long long
3589 into word64/uword64 typedefs.
3590
3591Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3592
72f4393d
L		 3593 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3594 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3595 (docdir): Removed.
3596 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3597 (AC_PROG_INSTALL): Added.
c906108c 3598 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3599 * configure: Rebuilt.
3600
c906108c
SS		 3601Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3602
3603 * configure.in: Define @SIMCONF@ depending on mips target.
3604 * configure: Rebuild.
3605 * Makefile.in (run): Add @SIMCONF@ to control simulator
3606 construction.
3607 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3608 * interp.c: Remove some debugging, provide more detailed error
3609 messages, update memory accesses to use LOADDRMASK.
72f4393d 3610
c906108c
SS		 3611Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3612
3613 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3614 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3615 stamp-h.
3616 * configure: Rebuild.
3617 * config.in: New file, generated by autoheader.
3618 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3619 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3620 HAVE_ANINT and HAVE_AINT, as appropriate.
3621 * Makefile.in (run): Use @LIBS@ rather than -lm.
3622 (interp.o): Depend upon config.h.
3623 (Makefile): Just rebuild Makefile.
3624 (clean): Remove stamp-h.
3625 (mostlyclean): Make the same as clean, not as distclean.
3626 (config.h, stamp-h): New targets.
3627
3628Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3629
3630 * interp.c (ColdReset): Fix boolean test. Make all simulator
3631 globals static.
3632
3633Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3634
3635 * interp.c (xfer_direct_word, xfer_direct_long,
3636 swap_direct_word, swap_direct_long, xfer_big_word,
3637 xfer_big_long, xfer_little_word, xfer_little_long,
3638 swap_word,swap_long): Added.
3639 * interp.c (ColdReset): Provide function indirection to
3640 host<->simulated_target transfer routines.
3641 * interp.c (sim_store_register, sim_fetch_register): Updated to
3642 make use of indirected transfer routines.
3643
3644Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3645
3646 * gencode.c (process_instructions): Ensure FP ABS instruction
3647 recognised.
3648 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3649 system call support.
3650
3651Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3652
3653 * interp.c (sim_do_command): Complain if callback structure not
3654 initialised.
3655
3656Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3657
3658 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3659 support for Sun hosts.
3660 * Makefile.in (gencode): Ensure the host compiler and libraries
3661 used for cross-hosted build.
3662
3663Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3664
3665 * interp.c, gencode.c: Some more (TODO) tidying.
3666
3667Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3668
3669 * gencode.c, interp.c: Replaced explicit long long references with
3670 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3671 * support.h (SET64LO, SET64HI): Macros added.
3672
3673Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3674
3675 * configure: Regenerate with autoconf 2.7.
3676
3677Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3678
3679 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3680 * support.h: Remove superfluous "1" from #if.
3681 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3682
3683Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3684
3685 * interp.c (StoreFPR): Control UndefinedResult() call on
3686 WARN_RESULT manifest.
3687
3688Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3689
3690 * gencode.c: Tidied instruction decoding, and added FP instruction
3691 support.
3692
3693 * interp.c: Added dineroIII, and BSD profiling support. Also
3694 run-time FP handling.
3695
3696Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3697
3698 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3699 gencode.c, interp.c, support.h: created.
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