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Commit | Line | Data |
---|---|---|
272cc70b AF |
1 | /* |
2 | * Copyright 2008, Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based vaguely on the Linux code | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
272cc70b AF |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <common.h> | |
12 | #include <command.h> | |
d4622df3 | 13 | #include <errno.h> |
272cc70b AF |
14 | #include <mmc.h> |
15 | #include <part.h> | |
16 | #include <malloc.h> | |
17 | #include <linux/list.h> | |
9b1f942c | 18 | #include <div64.h> |
da61fa5f | 19 | #include "mmc_private.h" |
272cc70b AF |
20 | |
21 | static struct list_head mmc_devices; | |
22 | static int cur_dev_num = -1; | |
23 | ||
750121c3 | 24 | __weak int board_mmc_getwp(struct mmc *mmc) |
d23d8d7e NK |
25 | { |
26 | return -1; | |
27 | } | |
28 | ||
29 | int mmc_getwp(struct mmc *mmc) | |
30 | { | |
31 | int wp; | |
32 | ||
33 | wp = board_mmc_getwp(mmc); | |
34 | ||
d4e1da4e | 35 | if (wp < 0) { |
93bfd616 PA |
36 | if (mmc->cfg->ops->getwp) |
37 | wp = mmc->cfg->ops->getwp(mmc); | |
d4e1da4e PK |
38 | else |
39 | wp = 0; | |
40 | } | |
d23d8d7e NK |
41 | |
42 | return wp; | |
43 | } | |
44 | ||
cee9ab7c JH |
45 | __weak int board_mmc_getcd(struct mmc *mmc) |
46 | { | |
11fdade2 SB |
47 | return -1; |
48 | } | |
49 | ||
da61fa5f | 50 | int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
272cc70b | 51 | { |
5db2fe3a | 52 | int ret; |
8635ff9e | 53 | |
8635ff9e | 54 | #ifdef CONFIG_MMC_TRACE |
5db2fe3a RR |
55 | int i; |
56 | u8 *ptr; | |
57 | ||
58 | printf("CMD_SEND:%d\n", cmd->cmdidx); | |
59 | printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); | |
93bfd616 | 60 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a RR |
61 | switch (cmd->resp_type) { |
62 | case MMC_RSP_NONE: | |
63 | printf("\t\tMMC_RSP_NONE\n"); | |
64 | break; | |
65 | case MMC_RSP_R1: | |
66 | printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", | |
67 | cmd->response[0]); | |
68 | break; | |
69 | case MMC_RSP_R1b: | |
70 | printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", | |
71 | cmd->response[0]); | |
72 | break; | |
73 | case MMC_RSP_R2: | |
74 | printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", | |
75 | cmd->response[0]); | |
76 | printf("\t\t \t\t 0x%08X \n", | |
77 | cmd->response[1]); | |
78 | printf("\t\t \t\t 0x%08X \n", | |
79 | cmd->response[2]); | |
80 | printf("\t\t \t\t 0x%08X \n", | |
81 | cmd->response[3]); | |
82 | printf("\n"); | |
83 | printf("\t\t\t\t\tDUMPING DATA\n"); | |
84 | for (i = 0; i < 4; i++) { | |
85 | int j; | |
86 | printf("\t\t\t\t\t%03d - ", i*4); | |
146bec79 | 87 | ptr = (u8 *)&cmd->response[i]; |
5db2fe3a RR |
88 | ptr += 3; |
89 | for (j = 0; j < 4; j++) | |
90 | printf("%02X ", *ptr--); | |
91 | printf("\n"); | |
92 | } | |
93 | break; | |
94 | case MMC_RSP_R3: | |
95 | printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", | |
96 | cmd->response[0]); | |
97 | break; | |
98 | default: | |
99 | printf("\t\tERROR MMC rsp not supported\n"); | |
100 | break; | |
101 | } | |
5db2fe3a | 102 | #else |
93bfd616 | 103 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a | 104 | #endif |
8635ff9e | 105 | return ret; |
272cc70b AF |
106 | } |
107 | ||
da61fa5f | 108 | int mmc_send_status(struct mmc *mmc, int timeout) |
5d4fc8d9 RR |
109 | { |
110 | struct mmc_cmd cmd; | |
d617c426 | 111 | int err, retries = 5; |
5d4fc8d9 RR |
112 | #ifdef CONFIG_MMC_TRACE |
113 | int status; | |
114 | #endif | |
115 | ||
116 | cmd.cmdidx = MMC_CMD_SEND_STATUS; | |
117 | cmd.resp_type = MMC_RSP_R1; | |
aaf3d41a MV |
118 | if (!mmc_host_is_spi(mmc)) |
119 | cmd.cmdarg = mmc->rca << 16; | |
5d4fc8d9 RR |
120 | |
121 | do { | |
122 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
d617c426 JK |
123 | if (!err) { |
124 | if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && | |
125 | (cmd.response[0] & MMC_STATUS_CURR_STATE) != | |
126 | MMC_STATE_PRG) | |
127 | break; | |
128 | else if (cmd.response[0] & MMC_STATUS_MASK) { | |
56196826 | 129 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
d617c426 JK |
130 | printf("Status Error: 0x%08X\n", |
131 | cmd.response[0]); | |
56196826 | 132 | #endif |
d617c426 JK |
133 | return COMM_ERR; |
134 | } | |
135 | } else if (--retries < 0) | |
5d4fc8d9 | 136 | return err; |
5d4fc8d9 RR |
137 | |
138 | udelay(1000); | |
139 | ||
5d4fc8d9 RR |
140 | } while (timeout--); |
141 | ||
5db2fe3a RR |
142 | #ifdef CONFIG_MMC_TRACE |
143 | status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; | |
144 | printf("CURR STATE:%d\n", status); | |
145 | #endif | |
5b0c942f | 146 | if (timeout <= 0) { |
56196826 | 147 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
5d4fc8d9 | 148 | printf("Timeout waiting card ready\n"); |
56196826 | 149 | #endif |
5d4fc8d9 RR |
150 | return TIMEOUT; |
151 | } | |
6b2221b0 AG |
152 | if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) |
153 | return SWITCH_ERR; | |
5d4fc8d9 RR |
154 | |
155 | return 0; | |
156 | } | |
157 | ||
da61fa5f | 158 | int mmc_set_blocklen(struct mmc *mmc, int len) |
272cc70b AF |
159 | { |
160 | struct mmc_cmd cmd; | |
161 | ||
786e8f81 | 162 | if (mmc->ddr_mode) |
d22e3d46 JC |
163 | return 0; |
164 | ||
272cc70b AF |
165 | cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; |
166 | cmd.resp_type = MMC_RSP_R1; | |
167 | cmd.cmdarg = len; | |
272cc70b AF |
168 | |
169 | return mmc_send_cmd(mmc, &cmd, NULL); | |
170 | } | |
171 | ||
172 | struct mmc *find_mmc_device(int dev_num) | |
173 | { | |
174 | struct mmc *m; | |
175 | struct list_head *entry; | |
176 | ||
177 | list_for_each(entry, &mmc_devices) { | |
178 | m = list_entry(entry, struct mmc, link); | |
179 | ||
180 | if (m->block_dev.dev == dev_num) | |
181 | return m; | |
182 | } | |
183 | ||
56196826 | 184 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 185 | printf("MMC Device %d not found\n", dev_num); |
56196826 | 186 | #endif |
272cc70b AF |
187 | |
188 | return NULL; | |
189 | } | |
190 | ||
ff8fef56 | 191 | static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, |
fdbb873e | 192 | lbaint_t blkcnt) |
272cc70b AF |
193 | { |
194 | struct mmc_cmd cmd; | |
195 | struct mmc_data data; | |
196 | ||
4a1a06bc AS |
197 | if (blkcnt > 1) |
198 | cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; | |
199 | else | |
200 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; | |
272cc70b AF |
201 | |
202 | if (mmc->high_capacity) | |
4a1a06bc | 203 | cmd.cmdarg = start; |
272cc70b | 204 | else |
4a1a06bc | 205 | cmd.cmdarg = start * mmc->read_bl_len; |
272cc70b AF |
206 | |
207 | cmd.resp_type = MMC_RSP_R1; | |
272cc70b AF |
208 | |
209 | data.dest = dst; | |
4a1a06bc | 210 | data.blocks = blkcnt; |
272cc70b AF |
211 | data.blocksize = mmc->read_bl_len; |
212 | data.flags = MMC_DATA_READ; | |
213 | ||
4a1a06bc AS |
214 | if (mmc_send_cmd(mmc, &cmd, &data)) |
215 | return 0; | |
272cc70b | 216 | |
4a1a06bc AS |
217 | if (blkcnt > 1) { |
218 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
219 | cmd.cmdarg = 0; | |
220 | cmd.resp_type = MMC_RSP_R1b; | |
4a1a06bc | 221 | if (mmc_send_cmd(mmc, &cmd, NULL)) { |
56196826 | 222 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
4a1a06bc | 223 | printf("mmc fail to send stop cmd\n"); |
56196826 | 224 | #endif |
4a1a06bc AS |
225 | return 0; |
226 | } | |
272cc70b AF |
227 | } |
228 | ||
4a1a06bc | 229 | return blkcnt; |
272cc70b AF |
230 | } |
231 | ||
ff8fef56 | 232 | static ulong mmc_bread(int dev_num, lbaint_t start, lbaint_t blkcnt, void *dst) |
272cc70b | 233 | { |
4a1a06bc AS |
234 | lbaint_t cur, blocks_todo = blkcnt; |
235 | ||
236 | if (blkcnt == 0) | |
237 | return 0; | |
272cc70b | 238 | |
4a1a06bc | 239 | struct mmc *mmc = find_mmc_device(dev_num); |
272cc70b AF |
240 | if (!mmc) |
241 | return 0; | |
242 | ||
d2bf29e3 | 243 | if ((start + blkcnt) > mmc->block_dev.lba) { |
56196826 | 244 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
ff8fef56 | 245 | printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", |
d2bf29e3 | 246 | start + blkcnt, mmc->block_dev.lba); |
56196826 | 247 | #endif |
d2bf29e3 LW |
248 | return 0; |
249 | } | |
272cc70b | 250 | |
4a1a06bc | 251 | if (mmc_set_blocklen(mmc, mmc->read_bl_len)) |
272cc70b | 252 | return 0; |
272cc70b | 253 | |
4a1a06bc | 254 | do { |
93bfd616 PA |
255 | cur = (blocks_todo > mmc->cfg->b_max) ? |
256 | mmc->cfg->b_max : blocks_todo; | |
4a1a06bc AS |
257 | if(mmc_read_blocks(mmc, dst, start, cur) != cur) |
258 | return 0; | |
259 | blocks_todo -= cur; | |
260 | start += cur; | |
261 | dst += cur * mmc->read_bl_len; | |
262 | } while (blocks_todo > 0); | |
272cc70b AF |
263 | |
264 | return blkcnt; | |
265 | } | |
266 | ||
fdbb873e | 267 | static int mmc_go_idle(struct mmc *mmc) |
272cc70b AF |
268 | { |
269 | struct mmc_cmd cmd; | |
270 | int err; | |
271 | ||
272 | udelay(1000); | |
273 | ||
274 | cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; | |
275 | cmd.cmdarg = 0; | |
276 | cmd.resp_type = MMC_RSP_NONE; | |
272cc70b AF |
277 | |
278 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
279 | ||
280 | if (err) | |
281 | return err; | |
282 | ||
283 | udelay(2000); | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
fdbb873e | 288 | static int sd_send_op_cond(struct mmc *mmc) |
272cc70b AF |
289 | { |
290 | int timeout = 1000; | |
291 | int err; | |
292 | struct mmc_cmd cmd; | |
293 | ||
294 | do { | |
295 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
296 | cmd.resp_type = MMC_RSP_R1; | |
297 | cmd.cmdarg = 0; | |
272cc70b AF |
298 | |
299 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
300 | ||
301 | if (err) | |
302 | return err; | |
303 | ||
304 | cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; | |
305 | cmd.resp_type = MMC_RSP_R3; | |
250de12b SB |
306 | |
307 | /* | |
308 | * Most cards do not answer if some reserved bits | |
309 | * in the ocr are set. However, Some controller | |
310 | * can set bit 7 (reserved for low voltages), but | |
311 | * how to manage low voltages SD card is not yet | |
312 | * specified. | |
313 | */ | |
d52ebf10 | 314 | cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : |
93bfd616 | 315 | (mmc->cfg->voltages & 0xff8000); |
272cc70b AF |
316 | |
317 | if (mmc->version == SD_VERSION_2) | |
318 | cmd.cmdarg |= OCR_HCS; | |
319 | ||
320 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
321 | ||
322 | if (err) | |
323 | return err; | |
324 | ||
325 | udelay(1000); | |
326 | } while ((!(cmd.response[0] & OCR_BUSY)) && timeout--); | |
327 | ||
328 | if (timeout <= 0) | |
329 | return UNUSABLE_ERR; | |
330 | ||
331 | if (mmc->version != SD_VERSION_2) | |
332 | mmc->version = SD_VERSION_1_0; | |
333 | ||
d52ebf10 TC |
334 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
335 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
336 | cmd.resp_type = MMC_RSP_R3; | |
337 | cmd.cmdarg = 0; | |
d52ebf10 TC |
338 | |
339 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
340 | ||
341 | if (err) | |
342 | return err; | |
343 | } | |
344 | ||
998be3dd | 345 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
346 | |
347 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
348 | mmc->rca = 0; | |
349 | ||
350 | return 0; | |
351 | } | |
352 | ||
e9550449 CLC |
353 | /* We pass in the cmd since otherwise the init seems to fail */ |
354 | static int mmc_send_op_cond_iter(struct mmc *mmc, struct mmc_cmd *cmd, | |
355 | int use_arg) | |
272cc70b | 356 | { |
272cc70b AF |
357 | int err; |
358 | ||
e9550449 CLC |
359 | cmd->cmdidx = MMC_CMD_SEND_OP_COND; |
360 | cmd->resp_type = MMC_RSP_R3; | |
361 | cmd->cmdarg = 0; | |
362 | if (use_arg && !mmc_host_is_spi(mmc)) { | |
363 | cmd->cmdarg = | |
93bfd616 | 364 | (mmc->cfg->voltages & |
e9550449 CLC |
365 | (mmc->op_cond_response & OCR_VOLTAGE_MASK)) | |
366 | (mmc->op_cond_response & OCR_ACCESS_MODE); | |
367 | ||
93bfd616 | 368 | if (mmc->cfg->host_caps & MMC_MODE_HC) |
e9550449 CLC |
369 | cmd->cmdarg |= OCR_HCS; |
370 | } | |
371 | err = mmc_send_cmd(mmc, cmd, NULL); | |
372 | if (err) | |
373 | return err; | |
374 | mmc->op_cond_response = cmd->response[0]; | |
375 | return 0; | |
376 | } | |
377 | ||
750121c3 | 378 | static int mmc_send_op_cond(struct mmc *mmc) |
e9550449 CLC |
379 | { |
380 | struct mmc_cmd cmd; | |
381 | int err, i; | |
382 | ||
272cc70b AF |
383 | /* Some cards seem to need this */ |
384 | mmc_go_idle(mmc); | |
385 | ||
31cacbab | 386 | /* Asking to the card its capabilities */ |
e9550449 CLC |
387 | mmc->op_cond_pending = 1; |
388 | for (i = 0; i < 2; i++) { | |
389 | err = mmc_send_op_cond_iter(mmc, &cmd, i != 0); | |
390 | if (err) | |
391 | return err; | |
cd6881b5 | 392 | |
e9550449 CLC |
393 | /* exit if not busy (flag seems to be inverted) */ |
394 | if (mmc->op_cond_response & OCR_BUSY) | |
395 | return 0; | |
396 | } | |
397 | return IN_PROGRESS; | |
398 | } | |
cd6881b5 | 399 | |
750121c3 | 400 | static int mmc_complete_op_cond(struct mmc *mmc) |
e9550449 CLC |
401 | { |
402 | struct mmc_cmd cmd; | |
403 | int timeout = 1000; | |
404 | uint start; | |
405 | int err; | |
cd6881b5 | 406 | |
e9550449 CLC |
407 | mmc->op_cond_pending = 0; |
408 | start = get_timer(0); | |
272cc70b | 409 | do { |
e9550449 | 410 | err = mmc_send_op_cond_iter(mmc, &cmd, 1); |
272cc70b AF |
411 | if (err) |
412 | return err; | |
e9550449 CLC |
413 | if (get_timer(start) > timeout) |
414 | return UNUSABLE_ERR; | |
415 | udelay(100); | |
416 | } while (!(mmc->op_cond_response & OCR_BUSY)); | |
272cc70b | 417 | |
d52ebf10 TC |
418 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
419 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
420 | cmd.resp_type = MMC_RSP_R3; | |
421 | cmd.cmdarg = 0; | |
d52ebf10 TC |
422 | |
423 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
424 | ||
425 | if (err) | |
426 | return err; | |
427 | } | |
428 | ||
272cc70b | 429 | mmc->version = MMC_VERSION_UNKNOWN; |
998be3dd | 430 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
431 | |
432 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
def816a2 | 433 | mmc->rca = 1; |
272cc70b AF |
434 | |
435 | return 0; | |
436 | } | |
437 | ||
438 | ||
fdbb873e | 439 | static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) |
272cc70b AF |
440 | { |
441 | struct mmc_cmd cmd; | |
442 | struct mmc_data data; | |
443 | int err; | |
444 | ||
445 | /* Get the Card Status Register */ | |
446 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; | |
447 | cmd.resp_type = MMC_RSP_R1; | |
448 | cmd.cmdarg = 0; | |
272cc70b | 449 | |
cdfd1ac6 | 450 | data.dest = (char *)ext_csd; |
272cc70b | 451 | data.blocks = 1; |
8bfa195e | 452 | data.blocksize = MMC_MAX_BLOCK_LEN; |
272cc70b AF |
453 | data.flags = MMC_DATA_READ; |
454 | ||
455 | err = mmc_send_cmd(mmc, &cmd, &data); | |
456 | ||
457 | return err; | |
458 | } | |
459 | ||
460 | ||
fdbb873e | 461 | static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) |
272cc70b AF |
462 | { |
463 | struct mmc_cmd cmd; | |
5d4fc8d9 RR |
464 | int timeout = 1000; |
465 | int ret; | |
272cc70b AF |
466 | |
467 | cmd.cmdidx = MMC_CMD_SWITCH; | |
468 | cmd.resp_type = MMC_RSP_R1b; | |
469 | cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | | |
5d4fc8d9 RR |
470 | (index << 16) | |
471 | (value << 8); | |
272cc70b | 472 | |
5d4fc8d9 RR |
473 | ret = mmc_send_cmd(mmc, &cmd, NULL); |
474 | ||
475 | /* Waiting for the ready status */ | |
93ad0d18 JK |
476 | if (!ret) |
477 | ret = mmc_send_status(mmc, timeout); | |
5d4fc8d9 RR |
478 | |
479 | return ret; | |
480 | ||
272cc70b AF |
481 | } |
482 | ||
fdbb873e | 483 | static int mmc_change_freq(struct mmc *mmc) |
272cc70b | 484 | { |
8bfa195e | 485 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
272cc70b AF |
486 | char cardtype; |
487 | int err; | |
488 | ||
786e8f81 | 489 | mmc->card_caps = MMC_MODE_4BIT | MMC_MODE_8BIT; |
272cc70b | 490 | |
d52ebf10 TC |
491 | if (mmc_host_is_spi(mmc)) |
492 | return 0; | |
493 | ||
272cc70b AF |
494 | /* Only version 4 supports high-speed */ |
495 | if (mmc->version < MMC_VERSION_4) | |
496 | return 0; | |
497 | ||
272cc70b AF |
498 | err = mmc_send_ext_csd(mmc, ext_csd); |
499 | ||
500 | if (err) | |
501 | return err; | |
502 | ||
0560db18 | 503 | cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; |
272cc70b AF |
504 | |
505 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); | |
506 | ||
507 | if (err) | |
6b2221b0 | 508 | return err == SWITCH_ERR ? 0 : err; |
272cc70b AF |
509 | |
510 | /* Now check to see that it worked */ | |
511 | err = mmc_send_ext_csd(mmc, ext_csd); | |
512 | ||
513 | if (err) | |
514 | return err; | |
515 | ||
516 | /* No high-speed support */ | |
0560db18 | 517 | if (!ext_csd[EXT_CSD_HS_TIMING]) |
272cc70b AF |
518 | return 0; |
519 | ||
520 | /* High Speed is set, there are two types: 52MHz and 26MHz */ | |
d22e3d46 | 521 | if (cardtype & EXT_CSD_CARD_TYPE_52) { |
201d5ac4 | 522 | if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) |
d22e3d46 | 523 | mmc->card_caps |= MMC_MODE_DDR_52MHz; |
272cc70b | 524 | mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
d22e3d46 | 525 | } else { |
272cc70b | 526 | mmc->card_caps |= MMC_MODE_HS; |
d22e3d46 | 527 | } |
272cc70b AF |
528 | |
529 | return 0; | |
530 | } | |
531 | ||
f866a46d SW |
532 | static int mmc_set_capacity(struct mmc *mmc, int part_num) |
533 | { | |
534 | switch (part_num) { | |
535 | case 0: | |
536 | mmc->capacity = mmc->capacity_user; | |
537 | break; | |
538 | case 1: | |
539 | case 2: | |
540 | mmc->capacity = mmc->capacity_boot; | |
541 | break; | |
542 | case 3: | |
543 | mmc->capacity = mmc->capacity_rpmb; | |
544 | break; | |
545 | case 4: | |
546 | case 5: | |
547 | case 6: | |
548 | case 7: | |
549 | mmc->capacity = mmc->capacity_gp[part_num - 4]; | |
550 | break; | |
551 | default: | |
552 | return -1; | |
553 | } | |
554 | ||
555 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); | |
556 | ||
557 | return 0; | |
558 | } | |
559 | ||
d2356284 SW |
560 | int mmc_select_hwpart(int dev_num, int hwpart) |
561 | { | |
562 | struct mmc *mmc = find_mmc_device(dev_num); | |
563 | int ret; | |
564 | ||
565 | if (!mmc) | |
d4622df3 | 566 | return -ENODEV; |
d2356284 SW |
567 | |
568 | if (mmc->part_num == hwpart) | |
569 | return 0; | |
570 | ||
571 | if (mmc->part_config == MMCPART_NOAVAILABLE) { | |
572 | printf("Card doesn't support part_switch\n"); | |
d4622df3 | 573 | return -EMEDIUMTYPE; |
d2356284 SW |
574 | } |
575 | ||
576 | ret = mmc_switch_part(dev_num, hwpart); | |
577 | if (ret) | |
d4622df3 | 578 | return ret; |
d2356284 SW |
579 | |
580 | mmc->part_num = hwpart; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | ||
585 | ||
bc897b1d LW |
586 | int mmc_switch_part(int dev_num, unsigned int part_num) |
587 | { | |
588 | struct mmc *mmc = find_mmc_device(dev_num); | |
f866a46d | 589 | int ret; |
bc897b1d LW |
590 | |
591 | if (!mmc) | |
592 | return -1; | |
593 | ||
f866a46d SW |
594 | ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, |
595 | (mmc->part_config & ~PART_ACCESS_MASK) | |
596 | | (part_num & PART_ACCESS_MASK)); | |
f866a46d | 597 | |
6dc93e70 PB |
598 | /* |
599 | * Set the capacity if the switch succeeded or was intended | |
600 | * to return to representing the raw device. | |
601 | */ | |
602 | if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) | |
603 | ret = mmc_set_capacity(mmc, part_num); | |
604 | ||
605 | return ret; | |
bc897b1d LW |
606 | } |
607 | ||
ac9da0e0 DSC |
608 | int mmc_hwpart_config(struct mmc *mmc, |
609 | const struct mmc_hwpart_conf *conf, | |
610 | enum mmc_hwpart_conf_mode mode) | |
611 | { | |
612 | u8 part_attrs = 0; | |
613 | u32 enh_size_mult; | |
614 | u32 enh_start_addr; | |
615 | u32 gp_size_mult[4]; | |
616 | u32 max_enh_size_mult; | |
617 | u32 tot_enh_size_mult = 0; | |
8dda5b0e | 618 | u8 wr_rel_set; |
ac9da0e0 DSC |
619 | int i, pidx, err; |
620 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); | |
621 | ||
622 | if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) | |
623 | return -EINVAL; | |
624 | ||
625 | if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { | |
626 | printf("eMMC >= 4.4 required for enhanced user data area\n"); | |
627 | return -EMEDIUMTYPE; | |
628 | } | |
629 | ||
630 | if (!(mmc->part_support & PART_SUPPORT)) { | |
631 | printf("Card does not support partitioning\n"); | |
632 | return -EMEDIUMTYPE; | |
633 | } | |
634 | ||
635 | if (!mmc->hc_wp_grp_size) { | |
636 | printf("Card does not define HC WP group size\n"); | |
637 | return -EMEDIUMTYPE; | |
638 | } | |
639 | ||
640 | /* check partition alignment and total enhanced size */ | |
641 | if (conf->user.enh_size) { | |
642 | if (conf->user.enh_size % mmc->hc_wp_grp_size || | |
643 | conf->user.enh_start % mmc->hc_wp_grp_size) { | |
644 | printf("User data enhanced area not HC WP group " | |
645 | "size aligned\n"); | |
646 | return -EINVAL; | |
647 | } | |
648 | part_attrs |= EXT_CSD_ENH_USR; | |
649 | enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; | |
650 | if (mmc->high_capacity) { | |
651 | enh_start_addr = conf->user.enh_start; | |
652 | } else { | |
653 | enh_start_addr = (conf->user.enh_start << 9); | |
654 | } | |
655 | } else { | |
656 | enh_size_mult = 0; | |
657 | enh_start_addr = 0; | |
658 | } | |
659 | tot_enh_size_mult += enh_size_mult; | |
660 | ||
661 | for (pidx = 0; pidx < 4; pidx++) { | |
662 | if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { | |
663 | printf("GP%i partition not HC WP group size " | |
664 | "aligned\n", pidx+1); | |
665 | return -EINVAL; | |
666 | } | |
667 | gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; | |
668 | if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { | |
669 | part_attrs |= EXT_CSD_ENH_GP(pidx); | |
670 | tot_enh_size_mult += gp_size_mult[pidx]; | |
671 | } | |
672 | } | |
673 | ||
674 | if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { | |
675 | printf("Card does not support enhanced attribute\n"); | |
676 | return -EMEDIUMTYPE; | |
677 | } | |
678 | ||
679 | err = mmc_send_ext_csd(mmc, ext_csd); | |
680 | if (err) | |
681 | return err; | |
682 | ||
683 | max_enh_size_mult = | |
684 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + | |
685 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + | |
686 | ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; | |
687 | if (tot_enh_size_mult > max_enh_size_mult) { | |
688 | printf("Total enhanced size exceeds maximum (%u > %u)\n", | |
689 | tot_enh_size_mult, max_enh_size_mult); | |
690 | return -EMEDIUMTYPE; | |
691 | } | |
692 | ||
8dda5b0e DSC |
693 | /* The default value of EXT_CSD_WR_REL_SET is device |
694 | * dependent, the values can only be changed if the | |
695 | * EXT_CSD_HS_CTRL_REL bit is set. The values can be | |
696 | * changed only once and before partitioning is completed. */ | |
697 | wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
698 | if (conf->user.wr_rel_change) { | |
699 | if (conf->user.wr_rel_set) | |
700 | wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; | |
701 | else | |
702 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; | |
703 | } | |
704 | for (pidx = 0; pidx < 4; pidx++) { | |
705 | if (conf->gp_part[pidx].wr_rel_change) { | |
706 | if (conf->gp_part[pidx].wr_rel_set) | |
707 | wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); | |
708 | else | |
709 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); | |
710 | } | |
711 | } | |
712 | ||
713 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && | |
714 | !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { | |
715 | puts("Card does not support host controlled partition write " | |
716 | "reliability settings\n"); | |
717 | return -EMEDIUMTYPE; | |
718 | } | |
719 | ||
ac9da0e0 DSC |
720 | if (ext_csd[EXT_CSD_PARTITION_SETTING] & |
721 | EXT_CSD_PARTITION_SETTING_COMPLETED) { | |
722 | printf("Card already partitioned\n"); | |
723 | return -EPERM; | |
724 | } | |
725 | ||
726 | if (mode == MMC_HWPART_CONF_CHECK) | |
727 | return 0; | |
728 | ||
729 | /* Partitioning requires high-capacity size definitions */ | |
730 | if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { | |
731 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
732 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
733 | ||
734 | if (err) | |
735 | return err; | |
736 | ||
737 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
738 | ||
739 | /* update erase group size to be high-capacity */ | |
740 | mmc->erase_grp_size = | |
741 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; | |
742 | ||
743 | } | |
744 | ||
745 | /* all OK, write the configuration */ | |
746 | for (i = 0; i < 4; i++) { | |
747 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
748 | EXT_CSD_ENH_START_ADDR+i, | |
749 | (enh_start_addr >> (i*8)) & 0xFF); | |
750 | if (err) | |
751 | return err; | |
752 | } | |
753 | for (i = 0; i < 3; i++) { | |
754 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
755 | EXT_CSD_ENH_SIZE_MULT+i, | |
756 | (enh_size_mult >> (i*8)) & 0xFF); | |
757 | if (err) | |
758 | return err; | |
759 | } | |
760 | for (pidx = 0; pidx < 4; pidx++) { | |
761 | for (i = 0; i < 3; i++) { | |
762 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
763 | EXT_CSD_GP_SIZE_MULT+pidx*3+i, | |
764 | (gp_size_mult[pidx] >> (i*8)) & 0xFF); | |
765 | if (err) | |
766 | return err; | |
767 | } | |
768 | } | |
769 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
770 | EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); | |
771 | if (err) | |
772 | return err; | |
773 | ||
774 | if (mode == MMC_HWPART_CONF_SET) | |
775 | return 0; | |
776 | ||
8dda5b0e DSC |
777 | /* The WR_REL_SET is a write-once register but shall be |
778 | * written before setting PART_SETTING_COMPLETED. As it is | |
779 | * write-once we can only write it when completing the | |
780 | * partitioning. */ | |
781 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { | |
782 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
783 | EXT_CSD_WR_REL_SET, wr_rel_set); | |
784 | if (err) | |
785 | return err; | |
786 | } | |
787 | ||
ac9da0e0 DSC |
788 | /* Setting PART_SETTING_COMPLETED confirms the partition |
789 | * configuration but it only becomes effective after power | |
790 | * cycle, so we do not adjust the partition related settings | |
791 | * in the mmc struct. */ | |
792 | ||
793 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
794 | EXT_CSD_PARTITION_SETTING, | |
795 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
796 | if (err) | |
797 | return err; | |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
48972d90 TR |
802 | int mmc_getcd(struct mmc *mmc) |
803 | { | |
804 | int cd; | |
805 | ||
806 | cd = board_mmc_getcd(mmc); | |
807 | ||
d4e1da4e | 808 | if (cd < 0) { |
93bfd616 PA |
809 | if (mmc->cfg->ops->getcd) |
810 | cd = mmc->cfg->ops->getcd(mmc); | |
d4e1da4e PK |
811 | else |
812 | cd = 1; | |
813 | } | |
48972d90 TR |
814 | |
815 | return cd; | |
816 | } | |
817 | ||
fdbb873e | 818 | static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) |
272cc70b AF |
819 | { |
820 | struct mmc_cmd cmd; | |
821 | struct mmc_data data; | |
822 | ||
823 | /* Switch the frequency */ | |
824 | cmd.cmdidx = SD_CMD_SWITCH_FUNC; | |
825 | cmd.resp_type = MMC_RSP_R1; | |
826 | cmd.cmdarg = (mode << 31) | 0xffffff; | |
827 | cmd.cmdarg &= ~(0xf << (group * 4)); | |
828 | cmd.cmdarg |= value << (group * 4); | |
272cc70b AF |
829 | |
830 | data.dest = (char *)resp; | |
831 | data.blocksize = 64; | |
832 | data.blocks = 1; | |
833 | data.flags = MMC_DATA_READ; | |
834 | ||
835 | return mmc_send_cmd(mmc, &cmd, &data); | |
836 | } | |
837 | ||
838 | ||
fdbb873e | 839 | static int sd_change_freq(struct mmc *mmc) |
272cc70b AF |
840 | { |
841 | int err; | |
842 | struct mmc_cmd cmd; | |
f781dd38 A |
843 | ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); |
844 | ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); | |
272cc70b AF |
845 | struct mmc_data data; |
846 | int timeout; | |
847 | ||
848 | mmc->card_caps = 0; | |
849 | ||
d52ebf10 TC |
850 | if (mmc_host_is_spi(mmc)) |
851 | return 0; | |
852 | ||
272cc70b AF |
853 | /* Read the SCR to find out if this card supports higher speeds */ |
854 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
855 | cmd.resp_type = MMC_RSP_R1; | |
856 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
857 | |
858 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
859 | ||
860 | if (err) | |
861 | return err; | |
862 | ||
863 | cmd.cmdidx = SD_CMD_APP_SEND_SCR; | |
864 | cmd.resp_type = MMC_RSP_R1; | |
865 | cmd.cmdarg = 0; | |
272cc70b AF |
866 | |
867 | timeout = 3; | |
868 | ||
869 | retry_scr: | |
f781dd38 | 870 | data.dest = (char *)scr; |
272cc70b AF |
871 | data.blocksize = 8; |
872 | data.blocks = 1; | |
873 | data.flags = MMC_DATA_READ; | |
874 | ||
875 | err = mmc_send_cmd(mmc, &cmd, &data); | |
876 | ||
877 | if (err) { | |
878 | if (timeout--) | |
879 | goto retry_scr; | |
880 | ||
881 | return err; | |
882 | } | |
883 | ||
4e3d89ba YK |
884 | mmc->scr[0] = __be32_to_cpu(scr[0]); |
885 | mmc->scr[1] = __be32_to_cpu(scr[1]); | |
272cc70b AF |
886 | |
887 | switch ((mmc->scr[0] >> 24) & 0xf) { | |
888 | case 0: | |
889 | mmc->version = SD_VERSION_1_0; | |
890 | break; | |
891 | case 1: | |
892 | mmc->version = SD_VERSION_1_10; | |
893 | break; | |
894 | case 2: | |
895 | mmc->version = SD_VERSION_2; | |
1741c64d JC |
896 | if ((mmc->scr[0] >> 15) & 0x1) |
897 | mmc->version = SD_VERSION_3; | |
272cc70b AF |
898 | break; |
899 | default: | |
900 | mmc->version = SD_VERSION_1_0; | |
901 | break; | |
902 | } | |
903 | ||
b44c7083 AS |
904 | if (mmc->scr[0] & SD_DATA_4BIT) |
905 | mmc->card_caps |= MMC_MODE_4BIT; | |
906 | ||
272cc70b AF |
907 | /* Version 1.0 doesn't support switching */ |
908 | if (mmc->version == SD_VERSION_1_0) | |
909 | return 0; | |
910 | ||
911 | timeout = 4; | |
912 | while (timeout--) { | |
913 | err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, | |
f781dd38 | 914 | (u8 *)switch_status); |
272cc70b AF |
915 | |
916 | if (err) | |
917 | return err; | |
918 | ||
919 | /* The high-speed function is busy. Try again */ | |
4e3d89ba | 920 | if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) |
272cc70b AF |
921 | break; |
922 | } | |
923 | ||
272cc70b | 924 | /* If high-speed isn't supported, we return */ |
4e3d89ba | 925 | if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) |
272cc70b AF |
926 | return 0; |
927 | ||
2c3fbf4c ML |
928 | /* |
929 | * If the host doesn't support SD_HIGHSPEED, do not switch card to | |
930 | * HIGHSPEED mode even if the card support SD_HIGHSPPED. | |
931 | * This can avoid furthur problem when the card runs in different | |
932 | * mode between the host. | |
933 | */ | |
93bfd616 PA |
934 | if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && |
935 | (mmc->cfg->host_caps & MMC_MODE_HS))) | |
2c3fbf4c ML |
936 | return 0; |
937 | ||
f781dd38 | 938 | err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); |
272cc70b AF |
939 | |
940 | if (err) | |
941 | return err; | |
942 | ||
4e3d89ba | 943 | if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) |
272cc70b AF |
944 | mmc->card_caps |= MMC_MODE_HS; |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | /* frequency bases */ | |
950 | /* divided by 10 to be nice to platforms without floating point */ | |
5f837c2c | 951 | static const int fbase[] = { |
272cc70b AF |
952 | 10000, |
953 | 100000, | |
954 | 1000000, | |
955 | 10000000, | |
956 | }; | |
957 | ||
958 | /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice | |
959 | * to platforms without floating point. | |
960 | */ | |
5f837c2c | 961 | static const int multipliers[] = { |
272cc70b AF |
962 | 0, /* reserved */ |
963 | 10, | |
964 | 12, | |
965 | 13, | |
966 | 15, | |
967 | 20, | |
968 | 25, | |
969 | 30, | |
970 | 35, | |
971 | 40, | |
972 | 45, | |
973 | 50, | |
974 | 55, | |
975 | 60, | |
976 | 70, | |
977 | 80, | |
978 | }; | |
979 | ||
fdbb873e | 980 | static void mmc_set_ios(struct mmc *mmc) |
272cc70b | 981 | { |
93bfd616 PA |
982 | if (mmc->cfg->ops->set_ios) |
983 | mmc->cfg->ops->set_ios(mmc); | |
272cc70b AF |
984 | } |
985 | ||
986 | void mmc_set_clock(struct mmc *mmc, uint clock) | |
987 | { | |
93bfd616 PA |
988 | if (clock > mmc->cfg->f_max) |
989 | clock = mmc->cfg->f_max; | |
272cc70b | 990 | |
93bfd616 PA |
991 | if (clock < mmc->cfg->f_min) |
992 | clock = mmc->cfg->f_min; | |
272cc70b AF |
993 | |
994 | mmc->clock = clock; | |
995 | ||
996 | mmc_set_ios(mmc); | |
997 | } | |
998 | ||
fdbb873e | 999 | static void mmc_set_bus_width(struct mmc *mmc, uint width) |
272cc70b AF |
1000 | { |
1001 | mmc->bus_width = width; | |
1002 | ||
1003 | mmc_set_ios(mmc); | |
1004 | } | |
1005 | ||
fdbb873e | 1006 | static int mmc_startup(struct mmc *mmc) |
272cc70b | 1007 | { |
f866a46d | 1008 | int err, i; |
272cc70b | 1009 | uint mult, freq; |
639b7827 | 1010 | u64 cmult, csize, capacity; |
272cc70b | 1011 | struct mmc_cmd cmd; |
8bfa195e SG |
1012 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
1013 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); | |
5d4fc8d9 | 1014 | int timeout = 1000; |
0c453bb7 | 1015 | bool has_parts = false; |
8a0cf490 | 1016 | bool part_completed; |
272cc70b | 1017 | |
d52ebf10 TC |
1018 | #ifdef CONFIG_MMC_SPI_CRC_ON |
1019 | if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ | |
1020 | cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; | |
1021 | cmd.resp_type = MMC_RSP_R1; | |
1022 | cmd.cmdarg = 1; | |
d52ebf10 TC |
1023 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1024 | ||
1025 | if (err) | |
1026 | return err; | |
1027 | } | |
1028 | #endif | |
1029 | ||
272cc70b | 1030 | /* Put the Card in Identify Mode */ |
d52ebf10 TC |
1031 | cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : |
1032 | MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ | |
272cc70b AF |
1033 | cmd.resp_type = MMC_RSP_R2; |
1034 | cmd.cmdarg = 0; | |
272cc70b AF |
1035 | |
1036 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1037 | ||
1038 | if (err) | |
1039 | return err; | |
1040 | ||
1041 | memcpy(mmc->cid, cmd.response, 16); | |
1042 | ||
1043 | /* | |
1044 | * For MMC cards, set the Relative Address. | |
1045 | * For SD cards, get the Relatvie Address. | |
1046 | * This also puts the cards into Standby State | |
1047 | */ | |
d52ebf10 TC |
1048 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1049 | cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; | |
1050 | cmd.cmdarg = mmc->rca << 16; | |
1051 | cmd.resp_type = MMC_RSP_R6; | |
272cc70b | 1052 | |
d52ebf10 | 1053 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1054 | |
d52ebf10 TC |
1055 | if (err) |
1056 | return err; | |
272cc70b | 1057 | |
d52ebf10 TC |
1058 | if (IS_SD(mmc)) |
1059 | mmc->rca = (cmd.response[0] >> 16) & 0xffff; | |
1060 | } | |
272cc70b AF |
1061 | |
1062 | /* Get the Card-Specific Data */ | |
1063 | cmd.cmdidx = MMC_CMD_SEND_CSD; | |
1064 | cmd.resp_type = MMC_RSP_R2; | |
1065 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1066 | |
1067 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1068 | ||
5d4fc8d9 RR |
1069 | /* Waiting for the ready status */ |
1070 | mmc_send_status(mmc, timeout); | |
1071 | ||
272cc70b AF |
1072 | if (err) |
1073 | return err; | |
1074 | ||
998be3dd RV |
1075 | mmc->csd[0] = cmd.response[0]; |
1076 | mmc->csd[1] = cmd.response[1]; | |
1077 | mmc->csd[2] = cmd.response[2]; | |
1078 | mmc->csd[3] = cmd.response[3]; | |
272cc70b AF |
1079 | |
1080 | if (mmc->version == MMC_VERSION_UNKNOWN) { | |
0b453ffe | 1081 | int version = (cmd.response[0] >> 26) & 0xf; |
272cc70b AF |
1082 | |
1083 | switch (version) { | |
1084 | case 0: | |
1085 | mmc->version = MMC_VERSION_1_2; | |
1086 | break; | |
1087 | case 1: | |
1088 | mmc->version = MMC_VERSION_1_4; | |
1089 | break; | |
1090 | case 2: | |
1091 | mmc->version = MMC_VERSION_2_2; | |
1092 | break; | |
1093 | case 3: | |
1094 | mmc->version = MMC_VERSION_3; | |
1095 | break; | |
1096 | case 4: | |
1097 | mmc->version = MMC_VERSION_4; | |
1098 | break; | |
1099 | default: | |
1100 | mmc->version = MMC_VERSION_1_2; | |
1101 | break; | |
1102 | } | |
1103 | } | |
1104 | ||
1105 | /* divide frequency by 10, since the mults are 10x bigger */ | |
0b453ffe RV |
1106 | freq = fbase[(cmd.response[0] & 0x7)]; |
1107 | mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; | |
272cc70b AF |
1108 | |
1109 | mmc->tran_speed = freq * mult; | |
1110 | ||
ab71188c | 1111 | mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); |
998be3dd | 1112 | mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); |
272cc70b AF |
1113 | |
1114 | if (IS_SD(mmc)) | |
1115 | mmc->write_bl_len = mmc->read_bl_len; | |
1116 | else | |
998be3dd | 1117 | mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); |
272cc70b AF |
1118 | |
1119 | if (mmc->high_capacity) { | |
1120 | csize = (mmc->csd[1] & 0x3f) << 16 | |
1121 | | (mmc->csd[2] & 0xffff0000) >> 16; | |
1122 | cmult = 8; | |
1123 | } else { | |
1124 | csize = (mmc->csd[1] & 0x3ff) << 2 | |
1125 | | (mmc->csd[2] & 0xc0000000) >> 30; | |
1126 | cmult = (mmc->csd[2] & 0x00038000) >> 15; | |
1127 | } | |
1128 | ||
f866a46d SW |
1129 | mmc->capacity_user = (csize + 1) << (cmult + 2); |
1130 | mmc->capacity_user *= mmc->read_bl_len; | |
1131 | mmc->capacity_boot = 0; | |
1132 | mmc->capacity_rpmb = 0; | |
1133 | for (i = 0; i < 4; i++) | |
1134 | mmc->capacity_gp[i] = 0; | |
272cc70b | 1135 | |
8bfa195e SG |
1136 | if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) |
1137 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1138 | |
8bfa195e SG |
1139 | if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) |
1140 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1141 | |
ab71188c MN |
1142 | if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { |
1143 | cmd.cmdidx = MMC_CMD_SET_DSR; | |
1144 | cmd.cmdarg = (mmc->dsr & 0xffff) << 16; | |
1145 | cmd.resp_type = MMC_RSP_NONE; | |
1146 | if (mmc_send_cmd(mmc, &cmd, NULL)) | |
1147 | printf("MMC: SET_DSR failed\n"); | |
1148 | } | |
1149 | ||
272cc70b | 1150 | /* Select the card, and put it into Transfer Mode */ |
d52ebf10 TC |
1151 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1152 | cmd.cmdidx = MMC_CMD_SELECT_CARD; | |
fe8f7066 | 1153 | cmd.resp_type = MMC_RSP_R1; |
d52ebf10 | 1154 | cmd.cmdarg = mmc->rca << 16; |
d52ebf10 | 1155 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1156 | |
d52ebf10 TC |
1157 | if (err) |
1158 | return err; | |
1159 | } | |
272cc70b | 1160 | |
e6f99a56 LW |
1161 | /* |
1162 | * For SD, its erase group is always one sector | |
1163 | */ | |
1164 | mmc->erase_grp_size = 1; | |
bc897b1d | 1165 | mmc->part_config = MMCPART_NOAVAILABLE; |
d23e2c09 SG |
1166 | if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { |
1167 | /* check ext_csd version and capacity */ | |
1168 | err = mmc_send_ext_csd(mmc, ext_csd); | |
9cf199eb DSC |
1169 | if (err) |
1170 | return err; | |
1171 | if (ext_csd[EXT_CSD_REV] >= 2) { | |
639b7827 YS |
1172 | /* |
1173 | * According to the JEDEC Standard, the value of | |
1174 | * ext_csd's capacity is valid if the value is more | |
1175 | * than 2GB | |
1176 | */ | |
0560db18 LW |
1177 | capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 |
1178 | | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | |
1179 | | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | |
1180 | | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; | |
8bfa195e | 1181 | capacity *= MMC_MAX_BLOCK_LEN; |
b1f1e821 | 1182 | if ((capacity >> 20) > 2 * 1024) |
f866a46d | 1183 | mmc->capacity_user = capacity; |
d23e2c09 | 1184 | } |
bc897b1d | 1185 | |
64f4a619 JC |
1186 | switch (ext_csd[EXT_CSD_REV]) { |
1187 | case 1: | |
1188 | mmc->version = MMC_VERSION_4_1; | |
1189 | break; | |
1190 | case 2: | |
1191 | mmc->version = MMC_VERSION_4_2; | |
1192 | break; | |
1193 | case 3: | |
1194 | mmc->version = MMC_VERSION_4_3; | |
1195 | break; | |
1196 | case 5: | |
1197 | mmc->version = MMC_VERSION_4_41; | |
1198 | break; | |
1199 | case 6: | |
1200 | mmc->version = MMC_VERSION_4_5; | |
1201 | break; | |
edab723b MN |
1202 | case 7: |
1203 | mmc->version = MMC_VERSION_5_0; | |
1204 | break; | |
64f4a619 JC |
1205 | } |
1206 | ||
8a0cf490 DSC |
1207 | /* The partition data may be non-zero but it is only |
1208 | * effective if PARTITION_SETTING_COMPLETED is set in | |
1209 | * EXT_CSD, so ignore any data if this bit is not set, | |
1210 | * except for enabling the high-capacity group size | |
1211 | * definition (see below). */ | |
1212 | part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & | |
1213 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
1214 | ||
0c453bb7 DSC |
1215 | /* store the partition info of emmc */ |
1216 | mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; | |
1217 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || | |
1218 | ext_csd[EXT_CSD_BOOT_MULT]) | |
1219 | mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; | |
8a0cf490 DSC |
1220 | if (part_completed && |
1221 | (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) | |
0c453bb7 DSC |
1222 | mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; |
1223 | ||
1224 | mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; | |
1225 | ||
1226 | mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; | |
1227 | ||
1228 | for (i = 0; i < 4; i++) { | |
1229 | int idx = EXT_CSD_GP_SIZE_MULT + i * 3; | |
8a0cf490 | 1230 | uint mult = (ext_csd[idx + 2] << 16) + |
0c453bb7 | 1231 | (ext_csd[idx + 1] << 8) + ext_csd[idx]; |
8a0cf490 DSC |
1232 | if (mult) |
1233 | has_parts = true; | |
1234 | if (!part_completed) | |
1235 | continue; | |
1236 | mmc->capacity_gp[i] = mult; | |
0c453bb7 DSC |
1237 | mmc->capacity_gp[i] *= |
1238 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1239 | mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
f8e89d67 | 1240 | mmc->capacity_gp[i] <<= 19; |
0c453bb7 DSC |
1241 | } |
1242 | ||
8a0cf490 DSC |
1243 | if (part_completed) { |
1244 | mmc->enh_user_size = | |
1245 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + | |
1246 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + | |
1247 | ext_csd[EXT_CSD_ENH_SIZE_MULT]; | |
1248 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1249 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1250 | mmc->enh_user_size <<= 19; | |
1251 | mmc->enh_user_start = | |
1252 | (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + | |
1253 | (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + | |
1254 | (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + | |
1255 | ext_csd[EXT_CSD_ENH_START_ADDR]; | |
1256 | if (mmc->high_capacity) | |
1257 | mmc->enh_user_start <<= 9; | |
1258 | } | |
a7f852b6 | 1259 | |
e6f99a56 | 1260 | /* |
1937e5aa OM |
1261 | * Host needs to enable ERASE_GRP_DEF bit if device is |
1262 | * partitioned. This bit will be lost every time after a reset | |
1263 | * or power off. This will affect erase size. | |
e6f99a56 | 1264 | */ |
8a0cf490 | 1265 | if (part_completed) |
0c453bb7 | 1266 | has_parts = true; |
1937e5aa | 1267 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && |
0c453bb7 DSC |
1268 | (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) |
1269 | has_parts = true; | |
1270 | if (has_parts) { | |
1937e5aa OM |
1271 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
1272 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
1273 | ||
1274 | if (err) | |
1275 | return err; | |
021a8055 HP |
1276 | else |
1277 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
037dc0ab | 1278 | } |
1937e5aa | 1279 | |
037dc0ab | 1280 | if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { |
1937e5aa | 1281 | /* Read out group size from ext_csd */ |
0560db18 | 1282 | mmc->erase_grp_size = |
a4ff9f83 | 1283 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; |
d7b29129 MN |
1284 | /* |
1285 | * if high capacity and partition setting completed | |
1286 | * SEC_COUNT is valid even if it is smaller than 2 GiB | |
1287 | * JEDEC Standard JESD84-B45, 6.2.4 | |
1288 | */ | |
8a0cf490 | 1289 | if (mmc->high_capacity && part_completed) { |
d7b29129 MN |
1290 | capacity = (ext_csd[EXT_CSD_SEC_CNT]) | |
1291 | (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | | |
1292 | (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | | |
1293 | (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); | |
1294 | capacity *= MMC_MAX_BLOCK_LEN; | |
1295 | mmc->capacity_user = capacity; | |
1296 | } | |
8bfa195e | 1297 | } else { |
1937e5aa | 1298 | /* Calculate the group size from the csd value. */ |
e6f99a56 LW |
1299 | int erase_gsz, erase_gmul; |
1300 | erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; | |
1301 | erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; | |
1302 | mmc->erase_grp_size = (erase_gsz + 1) | |
1303 | * (erase_gmul + 1); | |
1304 | } | |
037dc0ab DSC |
1305 | |
1306 | mmc->hc_wp_grp_size = 1024 | |
1307 | * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1308 | * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
d23e2c09 SG |
1309 | } |
1310 | ||
f866a46d SW |
1311 | err = mmc_set_capacity(mmc, mmc->part_num); |
1312 | if (err) | |
1313 | return err; | |
1314 | ||
272cc70b AF |
1315 | if (IS_SD(mmc)) |
1316 | err = sd_change_freq(mmc); | |
1317 | else | |
1318 | err = mmc_change_freq(mmc); | |
1319 | ||
1320 | if (err) | |
1321 | return err; | |
1322 | ||
1323 | /* Restrict card's capabilities by what the host can do */ | |
93bfd616 | 1324 | mmc->card_caps &= mmc->cfg->host_caps; |
272cc70b AF |
1325 | |
1326 | if (IS_SD(mmc)) { | |
1327 | if (mmc->card_caps & MMC_MODE_4BIT) { | |
1328 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1329 | cmd.resp_type = MMC_RSP_R1; | |
1330 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1331 | |
1332 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1333 | if (err) | |
1334 | return err; | |
1335 | ||
1336 | cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; | |
1337 | cmd.resp_type = MMC_RSP_R1; | |
1338 | cmd.cmdarg = 2; | |
272cc70b AF |
1339 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1340 | if (err) | |
1341 | return err; | |
1342 | ||
1343 | mmc_set_bus_width(mmc, 4); | |
1344 | } | |
1345 | ||
1346 | if (mmc->card_caps & MMC_MODE_HS) | |
ad5fd922 | 1347 | mmc->tran_speed = 50000000; |
272cc70b | 1348 | else |
ad5fd922 | 1349 | mmc->tran_speed = 25000000; |
272cc70b | 1350 | } else { |
7798f6db AF |
1351 | int idx; |
1352 | ||
1353 | /* An array of possible bus widths in order of preference */ | |
1354 | static unsigned ext_csd_bits[] = { | |
d22e3d46 JC |
1355 | EXT_CSD_DDR_BUS_WIDTH_8, |
1356 | EXT_CSD_DDR_BUS_WIDTH_4, | |
7798f6db AF |
1357 | EXT_CSD_BUS_WIDTH_8, |
1358 | EXT_CSD_BUS_WIDTH_4, | |
1359 | EXT_CSD_BUS_WIDTH_1, | |
1360 | }; | |
1361 | ||
1362 | /* An array to map CSD bus widths to host cap bits */ | |
1363 | static unsigned ext_to_hostcaps[] = { | |
786e8f81 AG |
1364 | [EXT_CSD_DDR_BUS_WIDTH_4] = |
1365 | MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, | |
1366 | [EXT_CSD_DDR_BUS_WIDTH_8] = | |
1367 | MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, | |
7798f6db AF |
1368 | [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, |
1369 | [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, | |
1370 | }; | |
1371 | ||
1372 | /* An array to map chosen bus width to an integer */ | |
1373 | static unsigned widths[] = { | |
d22e3d46 | 1374 | 8, 4, 8, 4, 1, |
7798f6db AF |
1375 | }; |
1376 | ||
1377 | for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { | |
1378 | unsigned int extw = ext_csd_bits[idx]; | |
786e8f81 | 1379 | unsigned int caps = ext_to_hostcaps[extw]; |
7798f6db AF |
1380 | |
1381 | /* | |
786e8f81 AG |
1382 | * Check to make sure the card and controller support |
1383 | * these capabilities | |
7798f6db | 1384 | */ |
786e8f81 | 1385 | if ((mmc->card_caps & caps) != caps) |
7798f6db AF |
1386 | continue; |
1387 | ||
272cc70b | 1388 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
7798f6db | 1389 | EXT_CSD_BUS_WIDTH, extw); |
272cc70b AF |
1390 | |
1391 | if (err) | |
4137894e | 1392 | continue; |
272cc70b | 1393 | |
786e8f81 | 1394 | mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; |
7798f6db | 1395 | mmc_set_bus_width(mmc, widths[idx]); |
4137894e LW |
1396 | |
1397 | err = mmc_send_ext_csd(mmc, test_csd); | |
786e8f81 AG |
1398 | |
1399 | if (err) | |
1400 | continue; | |
1401 | ||
786a27b7 | 1402 | /* Only compare read only fields */ |
786e8f81 AG |
1403 | if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] |
1404 | == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && | |
1405 | ext_csd[EXT_CSD_HC_WP_GRP_SIZE] | |
1406 | == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && | |
1407 | ext_csd[EXT_CSD_REV] | |
1408 | == test_csd[EXT_CSD_REV] && | |
1409 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1410 | == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && | |
1411 | memcmp(&ext_csd[EXT_CSD_SEC_CNT], | |
1412 | &test_csd[EXT_CSD_SEC_CNT], 4) == 0) | |
4137894e | 1413 | break; |
786e8f81 AG |
1414 | else |
1415 | err = SWITCH_ERR; | |
272cc70b AF |
1416 | } |
1417 | ||
786e8f81 AG |
1418 | if (err) |
1419 | return err; | |
1420 | ||
272cc70b AF |
1421 | if (mmc->card_caps & MMC_MODE_HS) { |
1422 | if (mmc->card_caps & MMC_MODE_HS_52MHz) | |
ad5fd922 | 1423 | mmc->tran_speed = 52000000; |
272cc70b | 1424 | else |
ad5fd922 JC |
1425 | mmc->tran_speed = 26000000; |
1426 | } | |
272cc70b AF |
1427 | } |
1428 | ||
ad5fd922 JC |
1429 | mmc_set_clock(mmc, mmc->tran_speed); |
1430 | ||
5af8f45c AG |
1431 | /* Fix the block length for DDR mode */ |
1432 | if (mmc->ddr_mode) { | |
1433 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
1434 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
1435 | } | |
1436 | ||
272cc70b AF |
1437 | /* fill in device description */ |
1438 | mmc->block_dev.lun = 0; | |
1439 | mmc->block_dev.type = 0; | |
1440 | mmc->block_dev.blksz = mmc->read_bl_len; | |
0472fbfd | 1441 | mmc->block_dev.log2blksz = LOG2(mmc->block_dev.blksz); |
9b1f942c | 1442 | mmc->block_dev.lba = lldiv(mmc->capacity, mmc->read_bl_len); |
56196826 | 1443 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
babce5f6 TH |
1444 | sprintf(mmc->block_dev.vendor, "Man %06x Snr %04x%04x", |
1445 | mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), | |
1446 | (mmc->cid[3] >> 16) & 0xffff); | |
1447 | sprintf(mmc->block_dev.product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, | |
1448 | (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, | |
1449 | (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, | |
1450 | (mmc->cid[2] >> 24) & 0xff); | |
1451 | sprintf(mmc->block_dev.revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, | |
1452 | (mmc->cid[2] >> 16) & 0xf); | |
56196826 PB |
1453 | #else |
1454 | mmc->block_dev.vendor[0] = 0; | |
1455 | mmc->block_dev.product[0] = 0; | |
1456 | mmc->block_dev.revision[0] = 0; | |
1457 | #endif | |
122efd43 | 1458 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) |
272cc70b | 1459 | init_part(&mmc->block_dev); |
122efd43 | 1460 | #endif |
272cc70b AF |
1461 | |
1462 | return 0; | |
1463 | } | |
1464 | ||
fdbb873e | 1465 | static int mmc_send_if_cond(struct mmc *mmc) |
272cc70b AF |
1466 | { |
1467 | struct mmc_cmd cmd; | |
1468 | int err; | |
1469 | ||
1470 | cmd.cmdidx = SD_CMD_SEND_IF_COND; | |
1471 | /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ | |
93bfd616 | 1472 | cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; |
272cc70b | 1473 | cmd.resp_type = MMC_RSP_R7; |
272cc70b AF |
1474 | |
1475 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1476 | ||
1477 | if (err) | |
1478 | return err; | |
1479 | ||
998be3dd | 1480 | if ((cmd.response[0] & 0xff) != 0xaa) |
272cc70b AF |
1481 | return UNUSABLE_ERR; |
1482 | else | |
1483 | mmc->version = SD_VERSION_2; | |
1484 | ||
1485 | return 0; | |
1486 | } | |
1487 | ||
93bfd616 PA |
1488 | /* not used any more */ |
1489 | int __deprecated mmc_register(struct mmc *mmc) | |
1490 | { | |
1491 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) | |
1492 | printf("%s is deprecated! use mmc_create() instead.\n", __func__); | |
1493 | #endif | |
1494 | return -1; | |
1495 | } | |
1496 | ||
1497 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) | |
272cc70b | 1498 | { |
93bfd616 PA |
1499 | struct mmc *mmc; |
1500 | ||
1501 | /* quick validation */ | |
1502 | if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || | |
1503 | cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) | |
1504 | return NULL; | |
1505 | ||
1506 | mmc = calloc(1, sizeof(*mmc)); | |
1507 | if (mmc == NULL) | |
1508 | return NULL; | |
1509 | ||
1510 | mmc->cfg = cfg; | |
1511 | mmc->priv = priv; | |
1512 | ||
1513 | /* the following chunk was mmc_register() */ | |
1514 | ||
ab71188c MN |
1515 | /* Setup dsr related values */ |
1516 | mmc->dsr_imp = 0; | |
1517 | mmc->dsr = 0xffffffff; | |
272cc70b AF |
1518 | /* Setup the universal parts of the block interface just once */ |
1519 | mmc->block_dev.if_type = IF_TYPE_MMC; | |
1520 | mmc->block_dev.dev = cur_dev_num++; | |
1521 | mmc->block_dev.removable = 1; | |
1522 | mmc->block_dev.block_read = mmc_bread; | |
1523 | mmc->block_dev.block_write = mmc_bwrite; | |
e6f99a56 | 1524 | mmc->block_dev.block_erase = mmc_berase; |
272cc70b | 1525 | |
93bfd616 PA |
1526 | /* setup initial part type */ |
1527 | mmc->block_dev.part_type = mmc->cfg->part_type; | |
272cc70b | 1528 | |
93bfd616 | 1529 | INIT_LIST_HEAD(&mmc->link); |
272cc70b | 1530 | |
93bfd616 PA |
1531 | list_add_tail(&mmc->link, &mmc_devices); |
1532 | ||
1533 | return mmc; | |
1534 | } | |
1535 | ||
1536 | void mmc_destroy(struct mmc *mmc) | |
1537 | { | |
1538 | /* only freeing memory for now */ | |
1539 | free(mmc); | |
272cc70b AF |
1540 | } |
1541 | ||
df3fc526 | 1542 | #ifdef CONFIG_PARTITIONS |
272cc70b AF |
1543 | block_dev_desc_t *mmc_get_dev(int dev) |
1544 | { | |
1545 | struct mmc *mmc = find_mmc_device(dev); | |
6bb4b4bc | 1546 | if (!mmc || mmc_init(mmc)) |
40242bc3 | 1547 | return NULL; |
272cc70b | 1548 | |
40242bc3 | 1549 | return &mmc->block_dev; |
272cc70b | 1550 | } |
df3fc526 | 1551 | #endif |
272cc70b | 1552 | |
95de9ab2 PK |
1553 | /* board-specific MMC power initializations. */ |
1554 | __weak void board_mmc_power_init(void) | |
1555 | { | |
1556 | } | |
1557 | ||
e9550449 | 1558 | int mmc_start_init(struct mmc *mmc) |
272cc70b | 1559 | { |
afd5932b | 1560 | int err; |
272cc70b | 1561 | |
ab769f22 | 1562 | /* we pretend there's no card when init is NULL */ |
93bfd616 | 1563 | if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { |
48972d90 | 1564 | mmc->has_init = 0; |
56196826 | 1565 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
48972d90 | 1566 | printf("MMC: no card present\n"); |
56196826 | 1567 | #endif |
48972d90 TR |
1568 | return NO_CARD_ERR; |
1569 | } | |
1570 | ||
bc897b1d LW |
1571 | if (mmc->has_init) |
1572 | return 0; | |
1573 | ||
95de9ab2 PK |
1574 | board_mmc_power_init(); |
1575 | ||
ab769f22 | 1576 | /* made sure it's not NULL earlier */ |
93bfd616 | 1577 | err = mmc->cfg->ops->init(mmc); |
272cc70b AF |
1578 | |
1579 | if (err) | |
1580 | return err; | |
1581 | ||
786e8f81 | 1582 | mmc->ddr_mode = 0; |
b86b85e2 IY |
1583 | mmc_set_bus_width(mmc, 1); |
1584 | mmc_set_clock(mmc, 1); | |
1585 | ||
272cc70b AF |
1586 | /* Reset the Card */ |
1587 | err = mmc_go_idle(mmc); | |
1588 | ||
1589 | if (err) | |
1590 | return err; | |
1591 | ||
bc897b1d LW |
1592 | /* The internal partition reset to user partition(0) at every CMD0*/ |
1593 | mmc->part_num = 0; | |
1594 | ||
272cc70b | 1595 | /* Test for SD version 2 */ |
afd5932b | 1596 | err = mmc_send_if_cond(mmc); |
272cc70b | 1597 | |
272cc70b AF |
1598 | /* Now try to get the SD card's operating condition */ |
1599 | err = sd_send_op_cond(mmc); | |
1600 | ||
1601 | /* If the command timed out, we check for an MMC card */ | |
1602 | if (err == TIMEOUT) { | |
1603 | err = mmc_send_op_cond(mmc); | |
1604 | ||
e9550449 | 1605 | if (err && err != IN_PROGRESS) { |
56196826 | 1606 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 1607 | printf("Card did not respond to voltage select!\n"); |
56196826 | 1608 | #endif |
272cc70b AF |
1609 | return UNUSABLE_ERR; |
1610 | } | |
1611 | } | |
1612 | ||
e9550449 CLC |
1613 | if (err == IN_PROGRESS) |
1614 | mmc->init_in_progress = 1; | |
1615 | ||
1616 | return err; | |
1617 | } | |
1618 | ||
1619 | static int mmc_complete_init(struct mmc *mmc) | |
1620 | { | |
1621 | int err = 0; | |
1622 | ||
1623 | if (mmc->op_cond_pending) | |
1624 | err = mmc_complete_op_cond(mmc); | |
1625 | ||
1626 | if (!err) | |
1627 | err = mmc_startup(mmc); | |
bc897b1d LW |
1628 | if (err) |
1629 | mmc->has_init = 0; | |
1630 | else | |
1631 | mmc->has_init = 1; | |
e9550449 CLC |
1632 | mmc->init_in_progress = 0; |
1633 | return err; | |
1634 | } | |
1635 | ||
1636 | int mmc_init(struct mmc *mmc) | |
1637 | { | |
1638 | int err = IN_PROGRESS; | |
d803fea5 | 1639 | unsigned start; |
e9550449 CLC |
1640 | |
1641 | if (mmc->has_init) | |
1642 | return 0; | |
d803fea5 MZ |
1643 | |
1644 | start = get_timer(0); | |
1645 | ||
e9550449 CLC |
1646 | if (!mmc->init_in_progress) |
1647 | err = mmc_start_init(mmc); | |
1648 | ||
1649 | if (!err || err == IN_PROGRESS) | |
1650 | err = mmc_complete_init(mmc); | |
1651 | debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); | |
bc897b1d | 1652 | return err; |
272cc70b AF |
1653 | } |
1654 | ||
ab71188c MN |
1655 | int mmc_set_dsr(struct mmc *mmc, u16 val) |
1656 | { | |
1657 | mmc->dsr = val; | |
1658 | return 0; | |
1659 | } | |
1660 | ||
cee9ab7c JH |
1661 | /* CPU-specific MMC initializations */ |
1662 | __weak int cpu_mmc_init(bd_t *bis) | |
272cc70b AF |
1663 | { |
1664 | return -1; | |
1665 | } | |
1666 | ||
cee9ab7c JH |
1667 | /* board-specific MMC initializations. */ |
1668 | __weak int board_mmc_init(bd_t *bis) | |
1669 | { | |
1670 | return -1; | |
1671 | } | |
272cc70b | 1672 | |
56196826 PB |
1673 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
1674 | ||
272cc70b AF |
1675 | void print_mmc_devices(char separator) |
1676 | { | |
1677 | struct mmc *m; | |
1678 | struct list_head *entry; | |
1679 | ||
1680 | list_for_each(entry, &mmc_devices) { | |
1681 | m = list_entry(entry, struct mmc, link); | |
1682 | ||
93bfd616 | 1683 | printf("%s: %d", m->cfg->name, m->block_dev.dev); |
272cc70b | 1684 | |
e75eaf10 LP |
1685 | if (entry->next != &mmc_devices) { |
1686 | printf("%c", separator); | |
1687 | if (separator != '\n') | |
1688 | puts (" "); | |
1689 | } | |
272cc70b AF |
1690 | } |
1691 | ||
1692 | printf("\n"); | |
1693 | } | |
1694 | ||
56196826 PB |
1695 | #else |
1696 | void print_mmc_devices(char separator) { } | |
1697 | #endif | |
1698 | ||
ea6ebe21 LW |
1699 | int get_mmc_num(void) |
1700 | { | |
1701 | return cur_dev_num; | |
1702 | } | |
1703 | ||
e9550449 CLC |
1704 | void mmc_set_preinit(struct mmc *mmc, int preinit) |
1705 | { | |
1706 | mmc->preinit = preinit; | |
1707 | } | |
1708 | ||
1709 | static void do_preinit(void) | |
1710 | { | |
1711 | struct mmc *m; | |
1712 | struct list_head *entry; | |
1713 | ||
1714 | list_for_each(entry, &mmc_devices) { | |
1715 | m = list_entry(entry, struct mmc, link); | |
1716 | ||
1717 | if (m->preinit) | |
1718 | mmc_start_init(m); | |
1719 | } | |
1720 | } | |
1721 | ||
1722 | ||
272cc70b AF |
1723 | int mmc_initialize(bd_t *bis) |
1724 | { | |
1725 | INIT_LIST_HEAD (&mmc_devices); | |
1726 | cur_dev_num = 0; | |
1727 | ||
1728 | if (board_mmc_init(bis) < 0) | |
1729 | cpu_mmc_init(bis); | |
1730 | ||
bb0dc108 | 1731 | #ifndef CONFIG_SPL_BUILD |
272cc70b | 1732 | print_mmc_devices(','); |
bb0dc108 | 1733 | #endif |
272cc70b | 1734 | |
e9550449 | 1735 | do_preinit(); |
272cc70b AF |
1736 | return 0; |
1737 | } | |
3690d6d6 A |
1738 | |
1739 | #ifdef CONFIG_SUPPORT_EMMC_BOOT | |
1740 | /* | |
1741 | * This function changes the size of boot partition and the size of rpmb | |
1742 | * partition present on EMMC devices. | |
1743 | * | |
1744 | * Input Parameters: | |
1745 | * struct *mmc: pointer for the mmc device strcuture | |
1746 | * bootsize: size of boot partition | |
1747 | * rpmbsize: size of rpmb partition | |
1748 | * | |
1749 | * Returns 0 on success. | |
1750 | */ | |
1751 | ||
1752 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
1753 | unsigned long rpmbsize) | |
1754 | { | |
1755 | int err; | |
1756 | struct mmc_cmd cmd; | |
1757 | ||
1758 | /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ | |
1759 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1760 | cmd.resp_type = MMC_RSP_R1b; | |
1761 | cmd.cmdarg = MMC_CMD62_ARG1; | |
1762 | ||
1763 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1764 | if (err) { | |
1765 | debug("mmc_boot_partition_size_change: Error1 = %d\n", err); | |
1766 | return err; | |
1767 | } | |
1768 | ||
1769 | /* Boot partition changing mode */ | |
1770 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1771 | cmd.resp_type = MMC_RSP_R1b; | |
1772 | cmd.cmdarg = MMC_CMD62_ARG2; | |
1773 | ||
1774 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1775 | if (err) { | |
1776 | debug("mmc_boot_partition_size_change: Error2 = %d\n", err); | |
1777 | return err; | |
1778 | } | |
1779 | /* boot partition size is multiple of 128KB */ | |
1780 | bootsize = (bootsize * 1024) / 128; | |
1781 | ||
1782 | /* Arg: boot partition size */ | |
1783 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1784 | cmd.resp_type = MMC_RSP_R1b; | |
1785 | cmd.cmdarg = bootsize; | |
1786 | ||
1787 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1788 | if (err) { | |
1789 | debug("mmc_boot_partition_size_change: Error3 = %d\n", err); | |
1790 | return err; | |
1791 | } | |
1792 | /* RPMB partition size is multiple of 128KB */ | |
1793 | rpmbsize = (rpmbsize * 1024) / 128; | |
1794 | /* Arg: RPMB partition size */ | |
1795 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1796 | cmd.resp_type = MMC_RSP_R1b; | |
1797 | cmd.cmdarg = rpmbsize; | |
1798 | ||
1799 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1800 | if (err) { | |
1801 | debug("mmc_boot_partition_size_change: Error4 = %d\n", err); | |
1802 | return err; | |
1803 | } | |
1804 | return 0; | |
1805 | } | |
1806 | ||
5a99b9de TR |
1807 | /* |
1808 | * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH | |
1809 | * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH | |
1810 | * and BOOT_MODE. | |
1811 | * | |
1812 | * Returns 0 on success. | |
1813 | */ | |
1814 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) | |
1815 | { | |
1816 | int err; | |
1817 | ||
1818 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, | |
1819 | EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | | |
1820 | EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | | |
1821 | EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); | |
1822 | ||
1823 | if (err) | |
1824 | return err; | |
1825 | return 0; | |
1826 | } | |
1827 | ||
792970b0 TR |
1828 | /* |
1829 | * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) | |
1830 | * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and | |
1831 | * PARTITION_ACCESS. | |
1832 | * | |
1833 | * Returns 0 on success. | |
1834 | */ | |
1835 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) | |
1836 | { | |
1837 | int err; | |
1838 | ||
1839 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, | |
1840 | EXT_CSD_BOOT_ACK(ack) | | |
1841 | EXT_CSD_BOOT_PART_NUM(part_num) | | |
1842 | EXT_CSD_PARTITION_ACCESS(access)); | |
1843 | ||
1844 | if (err) | |
1845 | return err; | |
1846 | return 0; | |
1847 | } | |
33ace362 TR |
1848 | |
1849 | /* | |
1850 | * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value | |
1851 | * for enable. Note that this is a write-once field for non-zero values. | |
1852 | * | |
1853 | * Returns 0 on success. | |
1854 | */ | |
1855 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) | |
1856 | { | |
1857 | return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, | |
1858 | enable); | |
1859 | } | |
3690d6d6 | 1860 | #endif |