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sim: allow the inline configure option everywhere
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
347fe5bb
MF		 12016-01-10 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
4 * configure: Regenerate.
5
22be3fbe
MF		 62016-01-10 Mike Frysinger <vapier@gentoo.org>
7
8 * configure: Regenerate.
9
0dc73ef7
MF		 102016-01-10 Mike Frysinger <vapier@gentoo.org>
11
12 * configure: Regenerate.
13
936df756
MF		 142016-01-09 Mike Frysinger <vapier@gentoo.org>
15
16 * config.in, configure: Regenerate.
17
2e3d4f4d
MF		 182016-01-06 Mike Frysinger <vapier@gentoo.org>
19
20 * interp.c (sim_open): Mark argv const.
21 (sim_create_inferior): Mark argv and env const.
22
9bbf6f91
MF		 232016-01-04 Mike Frysinger <vapier@gentoo.org>
24
25 * configure: Regenerate.
26
77cf2ef5
MF		 272016-01-03 Mike Frysinger <vapier@gentoo.org>
28
29 * interp.c (sim_open): Update sim_parse_args comment.
30
0cb8d851
MF		 312016-01-03 Mike Frysinger <vapier@gentoo.org>
32
33 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
34 * configure: Regenerate.
35
1ac72f06
MF		 362016-01-02 Mike Frysinger <vapier@gentoo.org>
37
38 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
39 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
40 * configure: Regenerate.
41 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
42
d47f5b30
MF		 432016-01-02 Mike Frysinger <vapier@gentoo.org>
44
45 * dv-tx3904cpu.c (CPU, SD): Delete.
46
e1211e55
MF		 472015-12-30 Mike Frysinger <vapier@gentoo.org>
48
49 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
50 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
51 (sim_store_register): Rename to ...
52 (mips_reg_store): ... this. Delete local cpu var.
53 Update sim_io_eprintf calls.
54 (sim_fetch_register): Rename to ...
55 (mips_reg_fetch): ... this. Delete local cpu var.
56 Update sim_io_eprintf calls.
57
5e744ef8
MF		 582015-12-27 Mike Frysinger <vapier@gentoo.org>
59
60 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
61
1b393626
MF		 622015-12-26 Mike Frysinger <vapier@gentoo.org>
63
64 * config.in, configure: Regenerate.
65
26f8bf63
MF		 662015-12-26 Mike Frysinger <vapier@gentoo.org>
67
68 * interp.c (sim_write, sim_read): Delete.
69 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
70 (load_word): Likewise.
71 * micromips.igen (cache): Likewise.
72 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
73 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
74 do_store_left, do_store_right, do_load_double, do_store_double):
75 Likewise.
76 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
77 (do_prefx): Likewise.
78 * sim-main.c (address_translation, prefetch): Delete.
79 (ifetch32, ifetch16): Delete call to AddressTranslation and set
80 paddr=vaddr.
81 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
82 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
83 (LoadMemory, StoreMemory): Delete CCA arg.
84
ef04e371
MF		 852015-12-24 Mike Frysinger <vapier@gentoo.org>
86
87 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
88 * configure: Regenerated.
89
cb379ede
MF		 902015-12-24 Mike Frysinger <vapier@gentoo.org>
91
92 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
93 * tconfig.h: Delete.
94
26936211
MF		 952015-12-24 Mike Frysinger <vapier@gentoo.org>
96
97 * tconfig.h (SIM_HANDLES_LMA): Delete.
98
84e8e361
MF		 992015-12-24 Mike Frysinger <vapier@gentoo.org>
100
101 * sim-main.h (WITH_WATCHPOINTS): Delete.
102
3cabaf66
MF		 1032015-12-24 Mike Frysinger <vapier@gentoo.org>
104
105 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
106
8abe6c66
MF		 1072015-12-24 Mike Frysinger <vapier@gentoo.org>
108
109 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
110
1d19cae7
DV		 1112015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
112
113 * micromips.igen (process_isa_mode): Fix left shift of negative
114 value.
115
cdf850e9
MF		 1162015-11-17 Mike Frysinger <vapier@gentoo.org>
117
118 * sim-main.h (WITH_MODULO_MEMORY): Delete.
119
797eee42
MF		 1202015-11-15 Mike Frysinger <vapier@gentoo.org>
121
122 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
123
6e4f085c
MF		 1242015-11-14 Mike Frysinger <vapier@gentoo.org>
125
126 * interp.c (sim_close): Rename to ...
127 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
128 sim_io_shutdown.
129 * sim-main.h (mips_sim_close): Declare.
130 (SIM_CLOSE_HOOK): Define.
131
8e394ffc
AB		 1322015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
133 Ali Lown <ali.lown@imgtec.com>
134
135 * Makefile.in (tmp-micromips): New rule.
136 (tmp-mach-multi): Add support for micromips.
137 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
138 that works for both mips64 and micromips64.
139 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
140 micromips32.
141 Add build support for micromips.
142 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
143 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
144 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
145 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
146 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
147 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
148 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
149 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
150 Refactored instruction code to use these functions.
151 * dsp2.igen: Refactored instruction code to use the new functions.
152 * interp.c (decode_coproc): Refactored to work with any instruction
153 encoding.
154 (isa_mode): New variable
155 (RSVD_INSTRUCTION): Changed to 0x00000039.
156 * m16.igen (BREAK16): Refactored instruction to use do_break16.
157 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
158 * micromips.dc: New file.
159 * micromips.igen: New file.
160 * micromips16.dc: New file.
161 * micromipsdsp.igen: New file.
162 * micromipsrun.c: New file.
163 * mips.igen (do_swc1): Changed to work with any instruction encoding.
164 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
165 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
166 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
167 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
168 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
169 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
170 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
171 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
172 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
173 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
174 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
175 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
176 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
177 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
178 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
179 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
180 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
181 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
182 instructions.
183 Refactored instruction code to use these functions.
184 (RSVD): Changed to use new reserved instruction.
185 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
186 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
187 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
188 do_store_double): Added micromips32 and micromips64 models.
189 Added include for micromips.igen and micromipsdsp.igen
190 Add micromips32 and micromips64 models.
191 (DecodeCoproc): Updated to use new macro definition.
192 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
193 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
194 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
195 Refactored instruction code to use these functions.
196 * sim-main.h (CP0_operation): New enum.
197 (DecodeCoproc): Updated macro.
198 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
199 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
200 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
201 ISA_MODE_MICROMIPS): New defines.
202 (sim_state): Add isa_mode field.
203
8d0978fb
MF		 2042015-06-23 Mike Frysinger <vapier@gentoo.org>
205
206 * configure: Regenerate.
207
306f4178
MF		 2082015-06-12 Mike Frysinger <vapier@gentoo.org>
209
210 * configure.ac: Change configure.in to configure.ac.
211 * configure: Regenerate.
212
a3487082
MF		 2132015-06-12 Mike Frysinger <vapier@gentoo.org>
214
215 * configure: Regenerate.
216
29bc024d
MF		 2172015-06-12 Mike Frysinger <vapier@gentoo.org>
218
219 * interp.c [TRACE]: Delete.
220 (TRACE): Change to WITH_TRACE_ANY_P.
221 [!WITH_TRACE_ANY_P] (open_trace): Define.
222 (mips_option_handler, open_trace, sim_close, dotrace):
223 Change defined(TRACE) to WITH_TRACE_ANY_P.
224 (sim_open): Delete TRACE ifdef check.
225 * sim-main.c (load_memory): Delete TRACE ifdef check.
226 (store_memory): Likewise.
227 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
228 [!WITH_TRACE_ANY_P] (dotrace): Define.
229
3ebe2863
MF		 2302015-04-18 Mike Frysinger <vapier@gentoo.org>
231
232 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
233 comments.
234
20bca71d
MF		 2352015-04-18 Mike Frysinger <vapier@gentoo.org>
236
237 * sim-main.h (SIM_CPU): Delete.
238
7e83aa92
MF		 2392015-04-18 Mike Frysinger <vapier@gentoo.org>
240
241 * sim-main.h (sim_cia): Delete.
242
034685f9
MF		 2432015-04-17 Mike Frysinger <vapier@gentoo.org>
244
245 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
246 PU_PC_GET.
247 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
248 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
249 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
250 CIA_SET to CPU_PC_SET.
251 * sim-main.h (CIA_GET, CIA_SET): Delete.
252
78e9aa70
MF		 2532015-04-15 Mike Frysinger <vapier@gentoo.org>
254
255 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
256 * sim-main.h (STATE_CPU): Delete.
257
bf12d44e
MF		 2582015-04-13 Mike Frysinger <vapier@gentoo.org>
259
260 * configure: Regenerate.
261
7bebb329
MF		 2622015-04-13 Mike Frysinger <vapier@gentoo.org>
263
264 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
265 * interp.c (mips_pc_get, mips_pc_set): New functions.
266 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
267 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
268 (sim_pc_get): Delete.
269 * sim-main.h (SIM_CPU): Define.
270 (struct sim_state): Change cpu to an array of pointers.
271 (STATE_CPU): Drop &.
272
8ac57fbd
MF		 2732015-04-13 Mike Frysinger <vapier@gentoo.org>
274
275 * interp.c (mips_option_handler, open_trace, sim_close,
276 sim_write, sim_read, sim_store_register, sim_fetch_register,
277 sim_create_inferior, pr_addr, pr_uword64): Convert old style
278 prototypes.
279 (sim_open): Convert old style prototype. Change casts with
280 sim_write to unsigned char *.
281 (fetch_str): Change null to unsigned char, and change cast to
282 unsigned char *.
283 (sim_monitor): Change c & ch to unsigned char. Change cast to
284 unsigned char *.
285
e787f858
MF		 2862015-04-12 Mike Frysinger <vapier@gentoo.org>
287
288 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
289
122bbfb5
MF		 2902015-04-06 Mike Frysinger <vapier@gentoo.org>
291
292 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
293
0fe84f3f
MF		 2942015-04-01 Mike Frysinger <vapier@gentoo.org>
295
296 * tconfig.h (SIM_HAVE_PROFILE): Delete.
297
aadc9410
MF		 2982015-03-31 Mike Frysinger <vapier@gentoo.org>
299
300 * config.in, configure: Regenerate.
301
05f53ed6
MF		 3022015-03-24 Mike Frysinger <vapier@gentoo.org>
303
304 * interp.c (sim_pc_get): New function.
305
c0931f26
MF		 3062015-03-24 Mike Frysinger <vapier@gentoo.org>
307
308 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
309 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
310
30452bbe
MF		 3112015-03-24 Mike Frysinger <vapier@gentoo.org>
312
313 * configure: Regenerate.
314
64dd13df
MF		 3152015-03-23 Mike Frysinger <vapier@gentoo.org>
316
317 * configure: Regenerate.
318
49cd1634
MF		 3192015-03-23 Mike Frysinger <vapier@gentoo.org>
320
321 * configure: Regenerate.
322 * configure.ac (mips_extra_objs): Delete.
323 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
324 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
325
3649cb06
MF		 3262015-03-23 Mike Frysinger <vapier@gentoo.org>
327
328 * configure: Regenerate.
329 * configure.ac: Delete sim_hw checks for dv-sockser.
330
ae7d0cac
MF		 3312015-03-16 Mike Frysinger <vapier@gentoo.org>
332
333 * config.in, configure: Regenerate.
334 * tconfig.in: Rename file ...
335 * tconfig.h: ... here.
336
8406bb59
MF		 3372015-03-15 Mike Frysinger <vapier@gentoo.org>
338
339 * tconfig.in: Delete includes.
340 [HAVE_DV_SOCKSER]: Delete.
341
465fb143
MF		 3422015-03-14 Mike Frysinger <vapier@gentoo.org>
343
344 * Makefile.in (SIM_RUN_OBJS): Delete.
345
5cddc23a
MF		 3462015-03-14 Mike Frysinger <vapier@gentoo.org>
347
348 * configure.ac (AC_CHECK_HEADERS): Delete.
349 * aclocal.m4, configure: Regenerate.
350
2974be62
AM		 3512014-08-19 Alan Modra <amodra@gmail.com>
352
353 * configure: Regenerate.
354
faa743bb
RM		 3552014-08-15 Roland McGrath <mcgrathr@google.com>
356
357 * configure: Regenerate.
358 * config.in: Regenerate.
359
1a8a700e
MF		 3602014-03-04 Mike Frysinger <vapier@gentoo.org>
361
362 * configure: Regenerate.
363
bf3d9781
AM		 3642013-09-23 Alan Modra <amodra@gmail.com>
365
366 * configure: Regenerate.
367
31e6ad7d
MF		 3682013-06-03 Mike Frysinger <vapier@gentoo.org>
369
370 * aclocal.m4, configure: Regenerate.
371
d3685d60
TT		 3722013-05-10 Freddie Chopin <freddie_chopin@op.pl>
373
374 * configure: Rebuild.
375
1517bd27
MF		 3762013-03-26 Mike Frysinger <vapier@gentoo.org>
377
378 * configure: Regenerate.
379
3be31516
JS		 3802013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
381
382 * configure.ac: Address use of dv-sockser.o.
383 * tconfig.in: Conditionalize use of dv_sockser_install.
384 * configure: Regenerated.
385 * config.in: Regenerated.
386
37cb8f8e
SE		 3872012-10-04 Chao-ying Fu <fu@mips.com>
388 Steve Ellcey <sellcey@mips.com>
389
390 * mips/mips3264r2.igen (rdhwr): New.
391
87c8644f
JS		 3922012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
393
394 * configure.ac: Always link against dv-sockser.o.
395 * configure: Regenerate.
396
5f3ef9d0
JB		 3972012-06-15 Joel Brobecker <brobecker@adacore.com>
398
399 * config.in, configure: Regenerate.
400
a6ff997c
NC		 4012012-05-18 Nick Clifton <nickc@redhat.com>
402
403 PR 14072
404 * interp.c: Include config.h before system header files.
405
2232061b
MF		 4062012-03-24 Mike Frysinger <vapier@gentoo.org>
407
408 * aclocal.m4, config.in, configure: Regenerate.
409
db2e4d67
MF		 4102011-12-03 Mike Frysinger <vapier@gentoo.org>
411
412 * aclocal.m4: New file.
413 * configure: Regenerate.
414
4399a56b
MF		 4152011-10-19 Mike Frysinger <vapier@gentoo.org>
416
417 * configure: Regenerate after common/acinclude.m4 update.
418
9c082ca8
MF		 4192011-10-17 Mike Frysinger <vapier@gentoo.org>
420
421 * configure.ac: Change include to common/acinclude.m4.
422
6ffe910a
MF		 4232011-10-17 Mike Frysinger <vapier@gentoo.org>
424
425 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
426 call. Replace common.m4 include with SIM_AC_COMMON.
427 * configure: Regenerate.
428
31b28250
HPN		 4292011-07-08 Hans-Peter Nilsson <hp@axis.com>
430
3faa01e3
HPN		 431 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
432 $(SIM_EXTRA_DEPS).
433 (tmp-mach-multi): Exit early when igen fails.
31b28250 434
2419798b
MF		 4352011-07-05 Mike Frysinger <vapier@gentoo.org>
436
437 * interp.c (sim_do_command): Delete.
438
d79fe0d6
MF		 4392011-02-14 Mike Frysinger <vapier@gentoo.org>
440
441 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
442 (tx3904sio_fifo_reset): Likewise.
443 * interp.c (sim_monitor): Likewise.
444
5558e7e6
MF		 4452010-04-14 Mike Frysinger <vapier@gentoo.org>
446
447 * interp.c (sim_write): Add const to buffer arg.
448
35aafff4
JB		 4492010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
450
451 * interp.c: Don't include sysdep.h
452
3725885a
RW		 4532010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
454
455 * configure: Regenerate.
456
d6416cdc
RW		 4572009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
458
81ecdfbb
RW		 459 * config.in: Regenerate.
460 * configure: Likewise.
461
d6416cdc
RW		 462 * configure: Regenerate.
463
b5bd9624
HPN		 4642008-07-11 Hans-Peter Nilsson <hp@axis.com>
465
466 * configure: Regenerate to track ../common/common.m4 changes.
467 * config.in: Ditto.
468
6efef468 4692008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 470 Daniel Jacobowitz <dan@codesourcery.com>
471 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 472
473 * configure: Regenerate.
474
60dc88db
RS		 4752007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
476
477 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
478 that unconditionally allows fmt_ps.
479 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
480 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
481 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
482 filter from 64,f to 32,f.
483 (PREFX): Change filter from 64 to 32.
484 (LDXC1, LUXC1): Provide separate mips32r2 implementations
485 that use do_load_double instead of do_load. Make both LUXC1
486 versions unpredictable if SizeFGR () != 64.
487 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
488 instead of do_store. Remove unused variable. Make both SUXC1
489 versions unpredictable if SizeFGR () != 64.
490
599ca73e
RS		 4912007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
492
493 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
494 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
495 shifts for that case.
496
2525df03
NC		 4972007-09-04 Nick Clifton <nickc@redhat.com>
498
499 * interp.c (options enum): Add OPTION_INFO_MEMORY.
500 (display_mem_info): New static variable.
501 (mips_option_handler): Handle OPTION_INFO_MEMORY.
502 (mips_options): Add info-memory and memory-info.
503 (sim_open): After processing the command line and board
504 specification, check display_mem_info. If it is set then
505 call the real handler for the --memory-info command line
506 switch.
507
35ee6e1e
JB		 5082007-08-24 Joel Brobecker <brobecker@adacore.com>
509
510 * configure.ac: Change license of multi-run.c to GPL version 3.
511 * configure: Regenerate.
512
d5fb0879
RS		 5132007-06-28 Richard Sandiford <richard@codesourcery.com>
514
515 * configure.ac, configure: Revert last patch.
516
2a2ce21b
RS		 5172007-06-26 Richard Sandiford <richard@codesourcery.com>
518
519 * configure.ac (sim_mipsisa3264_configs): New variable.
520 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
521 every configuration support all four targets, using the triplet to
522 determine the default.
523 * configure: Regenerate.
524
efdcccc9
RS		 5252007-06-25 Richard Sandiford <richard@codesourcery.com>
526
0a7692b2 527 * Makefile.in (m16run.o): New rule.
efdcccc9 528
f532a356
TS		 5292007-05-15 Thiemo Seufer <ths@mips.com>
530
531 * mips3264r2.igen (DSHD): Fix compile warning.
532
bfe9c90b
TS		 5332007-05-14 Thiemo Seufer <ths@mips.com>
534
535 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
536 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
537 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
538 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
539 for mips32r2.
540
53f4826b
TS		 5412007-03-01 Thiemo Seufer <ths@mips.com>
542
543 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
544 and mips64.
545
8bf3ddc8
TS		 5462007-02-20 Thiemo Seufer <ths@mips.com>
547
548 * dsp.igen: Update copyright notice.
549 * dsp2.igen: Fix copyright notice.
550
8b082fb1 5512007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 552 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 553
554 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
555 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
556 Add dsp2 to sim_igen_machine.
557 * configure: Regenerate.
558 * dsp.igen (do_ph_op): Add MUL support when op = 2.
559 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
560 (mulq_rs.ph): Use do_ph_mulq.
561 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
562 * mips.igen: Add dsp2 model and include dsp2.igen.
563 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
564 for *mips32r2, *mips64r2, *dsp.
565 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
566 for *mips32r2, *mips64r2, *dsp2.
567 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
568
b1004875 5692007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 570 Nigel Stephens <nigel@mips.com>
b1004875
TS		 571
572 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
573 jumps with hazard barrier.
574
f8df4c77 5752007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 576 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 577
578 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
579 after each call to sim_io_write.
580
b1004875 5812007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 582 Nigel Stephens <nigel@mips.com>
b1004875
TS		 583
584 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
585 supported by this simulator.
07802d98
TS		 586 (decode_coproc): Recognise additional CP0 Config registers
587 correctly.
588
14fb6c5a 5892007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 590 Nigel Stephens <nigel@mips.com>
591 David Ung <davidu@mips.com>
14fb6c5a
TS		 592
593 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
594 uninterpreted formats. If fmt is one of the uninterpreted types
595 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
596 fmt_word, and fmt_uninterpreted_64 like fmt_long.
597 (store_fpr): When writing an invalid odd register, set the
598 matching even register to fmt_unknown, not the following register.
599 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
600 the the memory window at offset 0 set by --memory-size command
601 line option.
602 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
603 point register.
604 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
605 register.
606 (sim_monitor): When returning the memory size to the MIPS
607 application, use the value in STATE_MEM_SIZE, not an arbitrary
608 hardcoded value.
609 (cop_lw): Don' mess around with FPR_STATE, just pass
610 fmt_uninterpreted_32 to StoreFPR.
611 (cop_sw): Similarly.
612 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
613 (cop_sd): Similarly.
614 * mips.igen (not_word_value): Single version for mips32, mips64
615 and mips16.
616
c8847145 6172007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 618 Nigel Stephens <nigel@mips.com>
c8847145
TS		 619
620 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
621 MBytes.
622
4b5d35ee
TS		 6232007-02-17 Thiemo Seufer <ths@mips.com>
624
625 * configure.ac (mips*-sde-elf*): Move in front of generic machine
626 configuration.
627 * configure: Regenerate.
628
3669427c
TS		 6292007-02-17 Thiemo Seufer <ths@mips.com>
630
631 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
632 Add mdmx to sim_igen_machine.
633 (mipsisa64*-*-*): Likewise. Remove dsp.
634 (mipsisa32*-*-*): Remove dsp.
635 * configure: Regenerate.
636
109ad085
TS		 6372007-02-13 Thiemo Seufer <ths@mips.com>
638
639 * configure.ac: Add mips*-sde-elf* target.
640 * configure: Regenerate.
641
921d7ad3
HPN		 6422006-12-21 Hans-Peter Nilsson <hp@axis.com>
643
644 * acconfig.h: Remove.
645 * config.in, configure: Regenerate.
646
02f97da7
TS		 6472006-11-07 Thiemo Seufer <ths@mips.com>
648
649 * dsp.igen (do_w_op): Fix compiler warning.
650
2d2733fc 6512006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 652 David Ung <davidu@mips.com>
2d2733fc
TS		 653
654 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
655 sim_igen_machine.
656 * configure: Regenerate.
657 * mips.igen (model): Add smartmips.
658 (MADDU): Increment ACX if carry.
659 (do_mult): Clear ACX.
660 (ROR,RORV): Add smartmips.
72f4393d 661 (include): Include smartmips.igen.
2d2733fc
TS		 662 * sim-main.h (ACX): Set to REGISTERS[89].
663 * smartmips.igen: New file.
664
d85c3a10 6652006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 666 David Ung <davidu@mips.com>
d85c3a10
TS		 667
668 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
669 mips3264r2.igen. Add missing dependency rules.
670 * m16e.igen: Support for mips16e save/restore instructions.
671
e85e3205
RE		 6722006-06-13 Richard Earnshaw <rearnsha@arm.com>
673
674 * configure: Regenerated.
675
2f0122dc
DJ		 6762006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
677
678 * configure: Regenerated.
679
20e95c23
DJ		 6802006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
681
682 * configure: Regenerated.
683
69088b17
CF		 6842006-05-15 Chao-ying Fu <fu@mips.com>
685
686 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
687
0275de4e
NC		 6882006-04-18 Nick Clifton <nickc@redhat.com>
689
690 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
691 statement.
692
b3a3ffef
HPN		 6932006-03-29 Hans-Peter Nilsson <hp@axis.com>
694
695 * configure: Regenerate.
696
40a5538e
CF		 6972005-12-14 Chao-ying Fu <fu@mips.com>
698
699 * Makefile.in (SIM_OBJS): Add dsp.o.
700 (dsp.o): New dependency.
701 (IGEN_INCLUDE): Add dsp.igen.
702 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
703 mipsisa64*-*-*): Add dsp to sim_igen_machine.
704 * configure: Regenerate.
705 * mips.igen: Add dsp model and include dsp.igen.
706 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
707 because these instructions are extended in DSP ASE.
708 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
709 adding 6 DSP accumulator registers and 1 DSP control register.
710 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
711 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
712 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
713 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
714 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
715 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
716 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
717 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
718 DSPCR_CCOND_SMASK): New define.
719 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
720 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
721
21d14896
ILT		 7222005-07-08 Ian Lance Taylor <ian@airs.com>
723
724 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
725
b16d63da 7262005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 727 Nigel Stephens <nigel@mips.com>
728
729 * mips.igen: New mips16e model and include m16e.igen.
730 (check_u64): Add mips16e tag.
731 * m16e.igen: New file for MIPS16e instructions.
732 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
733 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
734 models.
735 * configure: Regenerate.
b16d63da 736
e70cb6cd 7372005-05-26 David Ung <davidu@mips.com>
72f4393d 738
e70cb6cd
CD		 739 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
740 tags to all instructions which are applicable to the new ISAs.
741 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
742 vr.igen.
743 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 744 instructions.
e70cb6cd
CD		 745 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
746 to mips.igen.
747 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
748 * configure: Regenerate.
72f4393d 749
2b193c4a
MK		 7502005-03-23 Mark Kettenis <kettenis@gnu.org>
751
752 * configure: Regenerate.
753
35695fd6
AC		 7542005-01-14 Andrew Cagney <cagney@gnu.org>
755
756 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
757 explicit call to AC_CONFIG_HEADER.
758 * configure: Regenerate.
759
f0569246
AC		 7602005-01-12 Andrew Cagney <cagney@gnu.org>
761
762 * configure.ac: Update to use ../common/common.m4.
763 * configure: Re-generate.
764
38f48d72
AC		 7652005-01-11 Andrew Cagney <cagney@localhost.localdomain>
766
767 * configure: Regenerated to track ../common/aclocal.m4 changes.
768
b7026657
AC		 7692005-01-07 Andrew Cagney <cagney@gnu.org>
770
771 * configure.ac: Rename configure.in, require autoconf 2.59.
772 * configure: Re-generate.
773
379832de
HPN		 7742004-12-08 Hans-Peter Nilsson <hp@axis.com>
775
776 * configure: Regenerate for ../common/aclocal.m4 update.
777
cd62154c 7782004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 779
cd62154c
AC		 780 Committed by Andrew Cagney.
781 * m16.igen (CMP, CMPI): Fix assembler.
782
e5da76ec
CD		 7832004-08-18 Chris Demetriou <cgd@broadcom.com>
784
785 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
786 * configure: Regenerate.
787
139181c8
CD		 7882004-06-25 Chris Demetriou <cgd@broadcom.com>
789
790 * configure.in (sim_m16_machine): Include mipsIII.
791 * configure: Regenerate.
792
1a27f959
CD		 7932004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
794
72f4393d 795 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 796 from COP0_BADVADDR.
797 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
798
5dbb7b5a
CD		 7992004-04-10 Chris Demetriou <cgd@broadcom.com>
800
801 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
802
14234056
CD		 8032004-04-09 Chris Demetriou <cgd@broadcom.com>
804
805 * mips.igen (check_fmt): Remove.
806 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
807 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
808 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
809 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
810 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
811 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
812 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
813 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
814 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
815 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
816
c6f9085c
CD		 8172004-04-09 Chris Demetriou <cgd@broadcom.com>
818
819 * sb1.igen (check_sbx): New function.
820 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
821
11d66e66 8222004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 823 Richard Sandiford <rsandifo@redhat.com>
824
825 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
826 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
827 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
828 separate implementations for mipsIV and mipsV. Use new macros to
829 determine whether the restrictions apply.
830
b3208fb8
CD		 8312004-01-19 Chris Demetriou <cgd@broadcom.com>
832
833 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
834 (check_mult_hilo): Improve comments.
835 (check_div_hilo): Likewise. Also, fork off a new version
836 to handle mips32/mips64 (since there are no hazards to check
837 in MIPS32/MIPS64).
838
9a1d84fb
CD		 8392003-06-17 Richard Sandiford <rsandifo@redhat.com>
840
841 * mips.igen (do_dmultx): Fix check for negative operands.
842
ae451ac6
ILT		 8432003-05-16 Ian Lance Taylor <ian@airs.com>
844
845 * Makefile.in (SHELL): Make sure this is defined.
846 (various): Use $(SHELL) whenever we invoke move-if-change.
847
dd69d292
CD		 8482003-05-03 Chris Demetriou <cgd@broadcom.com>
849
850 * cp1.c: Tweak attribution slightly.
851 * cp1.h: Likewise.
852 * mdmx.c: Likewise.
853 * mdmx.igen: Likewise.
854 * mips3d.igen: Likewise.
855 * sb1.igen: Likewise.
856
bcd0068e
CD		 8572003-04-15 Richard Sandiford <rsandifo@redhat.com>
858
859 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
860 unsigned operands.
861
6b4a8935
AC		 8622003-02-27 Andrew Cagney <cagney@redhat.com>
863
601da316
AC		 864 * interp.c (sim_open): Rename _bfd to bfd.
865 (sim_create_inferior): Ditto.
6b4a8935 866
d29e330f
CD		 8672003-01-14 Chris Demetriou <cgd@broadcom.com>
868
869 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
870
a2353a08
CD		 8712003-01-14 Chris Demetriou <cgd@broadcom.com>
872
873 * mips.igen (EI, DI): Remove.
874
80551777
CD		 8752003-01-05 Richard Sandiford <rsandifo@redhat.com>
876
877 * Makefile.in (tmp-run-multi): Fix mips16 filter.
878
4c54fc26
CD		 8792003-01-04 Richard Sandiford <rsandifo@redhat.com>
880 Andrew Cagney <ac131313@redhat.com>
881 Gavin Romig-Koch <gavin@redhat.com>
882 Graydon Hoare <graydon@redhat.com>
883 Aldy Hernandez <aldyh@redhat.com>
884 Dave Brolley <brolley@redhat.com>
885 Chris Demetriou <cgd@broadcom.com>
886
887 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
888 (sim_mach_default): New variable.
889 (mips64vr-*-*, mips64vrel-*-*): New configurations.
890 Add a new simulator generator, MULTI.
891 * configure: Regenerate.
892 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
893 (multi-run.o): New dependency.
894 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
895 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
896 (tmp-multi): Combine them.
897 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
898 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
899 (distclean-extra): New rule.
900 * sim-main.h: Include bfd.h.
901 (MIPS_MACH): New macro.
902 * mips.igen (vr4120, vr5400, vr5500): New models.
903 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
904 * vr.igen: Replace with new version.
905
e6c674b8
CD		 9062003-01-04 Chris Demetriou <cgd@broadcom.com>
907
908 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
909 * configure: Regenerate.
910
28f50ac8
CD		 9112002-12-31 Chris Demetriou <cgd@broadcom.com>
912
913 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
914 * mips.igen: Remove all invocations of check_branch_bug and
915 mark_branch_bug.
916
5071ffe6
CD		 9172002-12-16 Chris Demetriou <cgd@broadcom.com>
918
72f4393d 919 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 920
06e7837e
CD		 9212002-07-30 Chris Demetriou <cgd@broadcom.com>
922
923 * mips.igen (do_load_double, do_store_double): New functions.
924 (LDC1, SDC1): Rename to...
925 (LDC1b, SDC1b): respectively.
926 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
927
2265c243
MS		 9282002-07-29 Michael Snyder <msnyder@redhat.com>
929
930 * cp1.c (fp_recip2): Modify initialization expression so that
931 GCC will recognize it as constant.
932
a2f8b4f3
CD		 9332002-06-18 Chris Demetriou <cgd@broadcom.com>
934
935 * mdmx.c (SD_): Delete.
936 (Unpredictable): Re-define, for now, to directly invoke
937 unpredictable_action().
938 (mdmx_acc_op): Fix error in .ob immediate handling.
939
b4b6c939
AC		 9402002-06-18 Andrew Cagney <cagney@redhat.com>
941
942 * interp.c (sim_firmware_command): Initialize `address'.
943
c8cca39f
AC		 9442002-06-16 Andrew Cagney <ac131313@redhat.com>
945
946 * configure: Regenerated to track ../common/aclocal.m4 changes.
947
e7e81181 9482002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 949 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 950
951 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
952 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
953 * mips.igen: Include mips3d.igen.
954 (mips3d): New model name for MIPS-3D ASE instructions.
955 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 956 instructions.
e7e81181
CD		 957 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
958 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
959 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
960 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
961 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
962 (RSquareRoot1, RSquareRoot2): New macros.
963 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
964 (fp_rsqrt2): New functions.
965 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
966 * configure: Regenerate.
967
3a2b820e 9682002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 969 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 970
971 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
972 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
973 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
974 (convert): Note that this function is not used for paired-single
975 format conversions.
976 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
977 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
978 (check_fmt_p): Enable paired-single support.
979 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
980 (PUU.PS): New instructions.
981 (CVT.S.fmt): Don't use this instruction for paired-single format
982 destinations.
983 * sim-main.h (FP_formats): New value 'fmt_ps.'
984 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
985 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
986
d18ea9c2
CD		 9872002-06-12 Chris Demetriou <cgd@broadcom.com>
988
989 * mips.igen: Fix formatting of function calls in
990 many FP operations.
991
95fd5cee
CD		 9922002-06-12 Chris Demetriou <cgd@broadcom.com>
993
994 * mips.igen (MOVN, MOVZ): Trace result.
995 (TNEI): Print "tnei" as the opcode name in traces.
996 (CEIL.W): Add disassembly string for traces.
997 (RSQRT.fmt): Make location of disassembly string consistent
998 with other instructions.
999
4f0d55ae
CD		 10002002-06-12 Chris Demetriou <cgd@broadcom.com>
1001
1002 * mips.igen (X): Delete unused function.
1003
3c25f8c7
AC		 10042002-06-08 Andrew Cagney <cagney@redhat.com>
1005
1006 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1007
f3c08b7e 10082002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1009 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1010
1011 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1012 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1013 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1014 (fp_nmsub): New prototypes.
1015 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1016 (NegMultiplySub): New defines.
1017 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1018 (MADD.D, MADD.S): Replace with...
1019 (MADD.fmt): New instruction.
1020 (MSUB.D, MSUB.S): Replace with...
1021 (MSUB.fmt): New instruction.
1022 (NMADD.D, NMADD.S): Replace with...
1023 (NMADD.fmt): New instruction.
1024 (NMSUB.D, MSUB.S): Replace with...
1025 (NMSUB.fmt): New instruction.
1026
52714ff9 10272002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1028 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1029
1030 * cp1.c: Fix more comment spelling and formatting.
1031 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1032 (denorm_mode): New function.
1033 (fpu_unary, fpu_binary): Round results after operation, collect
1034 status from rounding operations, and update the FCSR.
1035 (convert): Collect status from integer conversions and rounding
1036 operations, and update the FCSR. Adjust NaN values that result
1037 from conversions. Convert to use sim_io_eprintf rather than
1038 fprintf, and remove some debugging code.
1039 * cp1.h (fenr_FS): New define.
1040
577d8c4b
CD		 10412002-06-07 Chris Demetriou <cgd@broadcom.com>
1042
1043 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1044 rounding mode to sim FP rounding mode flag conversion code into...
1045 (rounding_mode): New function.
1046
196496ed
CD		 10472002-06-07 Chris Demetriou <cgd@broadcom.com>
1048
1049 * cp1.c: Clean up formatting of a few comments.
1050 (value_fpr): Reformat switch statement.
1051
cfe9ea23 10522002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1053 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1054
1055 * cp1.h: New file.
1056 * sim-main.h: Include cp1.h.
1057 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1058 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1059 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1060 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1061 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1062 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1063 * cp1.c: Don't include sim-fpu.h; already included by
1064 sim-main.h. Clean up formatting of some comments.
1065 (NaN, Equal, Less): Remove.
1066 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1067 (fp_cmp): New functions.
1068 * mips.igen (do_c_cond_fmt): Remove.
1069 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1070 Compare. Add result tracing.
1071 (CxC1): Remove, replace with...
1072 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1073 (DMxC1): Remove, replace with...
1074 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1075 (MxC1): Remove, replace with...
1076 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1077
ee7254b0
CD		 10782002-06-04 Chris Demetriou <cgd@broadcom.com>
1079
1080 * sim-main.h (FGRIDX): Remove, replace all uses with...
1081 (FGR_BASE): New macro.
1082 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1083 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1084 (NR_FGR, FGR): Likewise.
1085 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1086 * mips.igen: Likewise.
1087
d3eb724f
CD		 10882002-06-04 Chris Demetriou <cgd@broadcom.com>
1089
1090 * cp1.c: Add an FSF Copyright notice to this file.
1091
ba46ddd0 10922002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1093 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1094
1095 * cp1.c (Infinity): Remove.
1096 * sim-main.h (Infinity): Likewise.
1097
1098 * cp1.c (fp_unary, fp_binary): New functions.
1099 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1100 (fp_sqrt): New functions, implemented in terms of the above.
1101 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1102 (Recip, SquareRoot): Remove (replaced by functions above).
1103 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1104 (fp_recip, fp_sqrt): New prototypes.
1105 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1106 (Recip, SquareRoot): Replace prototypes with #defines which
1107 invoke the functions above.
72f4393d 1108
18d8a52d
CD		 11092002-06-03 Chris Demetriou <cgd@broadcom.com>
1110
1111 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1112 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1113 file, remove PARAMS from prototypes.
1114 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1115 simulator state arguments.
1116 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1117 pass simulator state arguments.
1118 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1119 (store_fpr, convert): Remove 'sd' argument.
1120 (value_fpr): Likewise. Convert to use 'SD' instead.
1121
0f154cbd
CD		 11222002-06-03 Chris Demetriou <cgd@broadcom.com>
1123
1124 * cp1.c (Min, Max): Remove #if 0'd functions.
1125 * sim-main.h (Min, Max): Remove.
1126
e80fc152
CD		 11272002-06-03 Chris Demetriou <cgd@broadcom.com>
1128
1129 * cp1.c: fix formatting of switch case and default labels.
1130 * interp.c: Likewise.
1131 * sim-main.c: Likewise.
1132
bad673a9
CD		 11332002-06-03 Chris Demetriou <cgd@broadcom.com>
1134
1135 * cp1.c: Clean up comments which describe FP formats.
1136 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1137
7cbea089 11382002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1139 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1140
1141 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1142 Broadcom SiByte SB-1 processor configurations.
1143 * configure: Regenerate.
1144 * sb1.igen: New file.
1145 * mips.igen: Include sb1.igen.
1146 (sb1): New model.
1147 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1148 * mdmx.igen: Add "sb1" model to all appropriate functions and
1149 instructions.
1150 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1151 (ob_func, ob_acc): Reference the above.
1152 (qh_acc): Adjust to keep the same size as ob_acc.
1153 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1154 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1155
909daa82
CD		 11562002-06-03 Chris Demetriou <cgd@broadcom.com>
1157
1158 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1159
f4f1b9f1 11602002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1161 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1162
1163 * mips.igen (mdmx): New (pseudo-)model.
1164 * mdmx.c, mdmx.igen: New files.
1165 * Makefile.in (SIM_OBJS): Add mdmx.o.
1166 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1167 New typedefs.
1168 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1169 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1170 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1171 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1172 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1173 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1174 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1175 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1176 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1177 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1178 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1179 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1180 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1181 (qh_fmtsel): New macros.
1182 (_sim_cpu): New member "acc".
1183 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1184 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1185
5accf1ff
CD		 11862002-05-01 Chris Demetriou <cgd@broadcom.com>
1187
1188 * interp.c: Use 'deprecated' rather than 'depreciated.'
1189 * sim-main.h: Likewise.
1190
402586aa
CD		 11912002-05-01 Chris Demetriou <cgd@broadcom.com>
1192
1193 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1194 which wouldn't compile anyway.
1195 * sim-main.h (unpredictable_action): New function prototype.
1196 (Unpredictable): Define to call igen function unpredictable().
1197 (NotWordValue): New macro to call igen function not_word_value().
1198 (UndefinedResult): Remove.
1199 * interp.c (undefined_result): Remove.
1200 (unpredictable_action): New function.
1201 * mips.igen (not_word_value, unpredictable): New functions.
1202 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1203 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1204 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1205 NotWordValue() to check for unpredictable inputs, then
1206 Unpredictable() to handle them.
1207
c9b9995a
CD		 12082002-02-24 Chris Demetriou <cgd@broadcom.com>
1209
1210 * mips.igen: Fix formatting of calls to Unpredictable().
1211
e1015982
AC		 12122002-04-20 Andrew Cagney <ac131313@redhat.com>
1213
1214 * interp.c (sim_open): Revert previous change.
1215
b882a66b
AO		 12162002-04-18 Alexandre Oliva <aoliva@redhat.com>
1217
1218 * interp.c (sim_open): Disable chunk of code that wrote code in
1219 vector table entries.
1220
c429b7dd
CD		 12212002-03-19 Chris Demetriou <cgd@broadcom.com>
1222
1223 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1224 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1225 unused definitions.
1226
37d146fa
CD		 12272002-03-19 Chris Demetriou <cgd@broadcom.com>
1228
1229 * cp1.c: Fix many formatting issues.
1230
07892c0b
CD		 12312002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1232
1233 * cp1.c (fpu_format_name): New function to replace...
1234 (DOFMT): This. Delete, and update all callers.
1235 (fpu_rounding_mode_name): New function to replace...
1236 (RMMODE): This. Delete, and update all callers.
1237
487f79b7
CD		 12382002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1239
1240 * interp.c: Move FPU support routines from here to...
1241 * cp1.c: Here. New file.
1242 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1243 (cp1.o): New target.
1244
1e799e28
CD		 12452002-03-12 Chris Demetriou <cgd@broadcom.com>
1246
1247 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1248 * mips.igen (mips32, mips64): New models, add to all instructions
1249 and functions as appropriate.
1250 (loadstore_ea, check_u64): New variant for model mips64.
1251 (check_fmt_p): New variant for models mipsV and mips64, remove
1252 mipsV model marking fro other variant.
1253 (SLL) Rename to...
1254 (SLLa) this.
1255 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1256 for mips32 and mips64.
1257 (DCLO, DCLZ): New instructions for mips64.
1258
82f728db
CD		 12592002-03-07 Chris Demetriou <cgd@broadcom.com>
1260
1261 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1262 immediate or code as a hex value with the "%#lx" format.
1263 (ANDI): Likewise, and fix printed instruction name.
1264
b96e7ef1
CD		 12652002-03-05 Chris Demetriou <cgd@broadcom.com>
1266
1267 * sim-main.h (UndefinedResult, Unpredictable): New macros
1268 which currently do nothing.
1269
d35d4f70
CD		 12702002-03-05 Chris Demetriou <cgd@broadcom.com>
1271
1272 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1273 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1274 (status_CU3): New definitions.
1275
1276 * sim-main.h (ExceptionCause): Add new values for MIPS32
1277 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1278 for DebugBreakPoint and NMIReset to note their status in
1279 MIPS32 and MIPS64.
1280 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1281 (SignalExceptionCacheErr): New exception macros.
1282
3ad6f714
CD		 12832002-03-05 Chris Demetriou <cgd@broadcom.com>
1284
1285 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1286 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1287 is always enabled.
1288 (SignalExceptionCoProcessorUnusable): Take as argument the
1289 unusable coprocessor number.
1290
86b77b47
CD		 12912002-03-05 Chris Demetriou <cgd@broadcom.com>
1292
1293 * mips.igen: Fix formatting of all SignalException calls.
1294
97a88e93 12952002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1296
1297 * sim-main.h (SIGNEXTEND): Remove.
1298
97a88e93 12992002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1300
1301 * mips.igen: Remove gencode comment from top of file, fix
1302 spelling in another comment.
1303
97a88e93 13042002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1305
1306 * mips.igen (check_fmt, check_fmt_p): New functions to check
1307 whether specific floating point formats are usable.
1308 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1309 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1310 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1311 Use the new functions.
1312 (do_c_cond_fmt): Remove format checks...
1313 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1314
97a88e93 13152002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1316
1317 * mips.igen: Fix formatting of check_fpu calls.
1318
41774c9d
CD		 13192002-03-03 Chris Demetriou <cgd@broadcom.com>
1320
1321 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1322
4a0bd876
CD		 13232002-03-03 Chris Demetriou <cgd@broadcom.com>
1324
1325 * mips.igen: Remove whitespace at end of lines.
1326
09297648
CD		 13272002-03-02 Chris Demetriou <cgd@broadcom.com>
1328
1329 * mips.igen (loadstore_ea): New function to do effective
1330 address calculations.
1331 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1332 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1333 CACHE): Use loadstore_ea to do effective address computations.
1334
043b7057
CD		 13352002-03-02 Chris Demetriou <cgd@broadcom.com>
1336
1337 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1338 * mips.igen (LL, CxC1, MxC1): Likewise.
1339
c1e8ada4
CD		 13402002-03-02 Chris Demetriou <cgd@broadcom.com>
1341
1342 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1343 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1344 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1345 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1346 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1347 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1348 Don't split opcode fields by hand, use the opcode field values
1349 provided by igen.
1350
3e1dca16
CD		 13512002-03-01 Chris Demetriou <cgd@broadcom.com>
1352
1353 * mips.igen (do_divu): Fix spacing.
1354
1355 * mips.igen (do_dsllv): Move to be right before DSLLV,
1356 to match the rest of the do_<shift> functions.
1357
fff8d27d
CD		 13582002-03-01 Chris Demetriou <cgd@broadcom.com>
1359
1360 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1361 DSRL32, do_dsrlv): Trace inputs and results.
1362
0d3e762b
CD		 13632002-03-01 Chris Demetriou <cgd@broadcom.com>
1364
1365 * mips.igen (CACHE): Provide instruction-printing string.
1366
1367 * interp.c (signal_exception): Comment tokens after #endif.
1368
eb5fcf93
CD		 13692002-02-28 Chris Demetriou <cgd@broadcom.com>
1370
1371 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1372 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1373 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1374 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1375 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1376 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1377 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1378 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1379
bb22bd7d
CD		 13802002-02-28 Chris Demetriou <cgd@broadcom.com>
1381
1382 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1383 instruction-printing string.
1384 (LWU): Use '64' as the filter flag.
1385
91a177cf
CD		 13862002-02-28 Chris Demetriou <cgd@broadcom.com>
1387
1388 * mips.igen (SDXC1): Fix instruction-printing string.
1389
387f484a
CD		 13902002-02-28 Chris Demetriou <cgd@broadcom.com>
1391
1392 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1393 filter flags "32,f".
1394
3d81f391
CD		 13952002-02-27 Chris Demetriou <cgd@broadcom.com>
1396
1397 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1398 as the filter flag.
1399
af5107af
CD		 14002002-02-27 Chris Demetriou <cgd@broadcom.com>
1401
1402 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1403 add a comma) so that it more closely match the MIPS ISA
1404 documentation opcode partitioning.
1405 (PREF): Put useful names on opcode fields, and include
1406 instruction-printing string.
1407
ca971540
CD		 14082002-02-27 Chris Demetriou <cgd@broadcom.com>
1409
1410 * mips.igen (check_u64): New function which in the future will
1411 check whether 64-bit instructions are usable and signal an
1412 exception if not. Currently a no-op.
1413 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1414 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1415 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1416 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1417
1418 * mips.igen (check_fpu): New function which in the future will
1419 check whether FPU instructions are usable and signal an exception
1420 if not. Currently a no-op.
1421 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1422 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1423 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1424 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1425 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1426 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1427 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1428 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1429
1c47a468
CD		 14302002-02-27 Chris Demetriou <cgd@broadcom.com>
1431
1432 * mips.igen (do_load_left, do_load_right): Move to be immediately
1433 following do_load.
1434 (do_store_left, do_store_right): Move to be immediately following
1435 do_store.
1436
603a98e7
CD		 14372002-02-27 Chris Demetriou <cgd@broadcom.com>
1438
1439 * mips.igen (mipsV): New model name. Also, add it to
1440 all instructions and functions where it is appropriate.
1441
c5d00cc7
CD		 14422002-02-18 Chris Demetriou <cgd@broadcom.com>
1443
1444 * mips.igen: For all functions and instructions, list model
1445 names that support that instruction one per line.
1446
074e9cb8
CD		 14472002-02-11 Chris Demetriou <cgd@broadcom.com>
1448
1449 * mips.igen: Add some additional comments about supported
1450 models, and about which instructions go where.
1451 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1452 order as is used in the rest of the file.
1453
9805e229
CD		 14542002-02-11 Chris Demetriou <cgd@broadcom.com>
1455
1456 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1457 indicating that ALU32_END or ALU64_END are there to check
1458 for overflow.
1459 (DADD): Likewise, but also remove previous comment about
1460 overflow checking.
1461
f701dad2
CD		 14622002-02-10 Chris Demetriou <cgd@broadcom.com>
1463
1464 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1465 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1466 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1467 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1468 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1469 fields (i.e., add and move commas) so that they more closely
1470 match the MIPS ISA documentation opcode partitioning.
1471
14722002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1473
72f4393d
L		 1474 * mips.igen (ADDI): Print immediate value.
1475 (BREAK): Print code.
1476 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1477 (SLL): Print "nop" specially, and don't run the code
1478 that does the shift for the "nop" case.
20ae0098 1479
9e52972e
FF		 14802001-11-17 Fred Fish <fnf@redhat.com>
1481
1482 * sim-main.h (float_operation): Move enum declaration outside
1483 of _sim_cpu struct declaration.
1484
c0efbca4
JB		 14852001-04-12 Jim Blandy <jimb@redhat.com>
1486
1487 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1488 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1489 set of the FCSR.
1490 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1491 PENDING_FILL, and you can get the intended effect gracefully by
1492 calling PENDING_SCHED directly.
1493
fb891446
BE		 14942001-02-23 Ben Elliston <bje@redhat.com>
1495
1496 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1497 already defined elsewhere.
1498
8030f857
BE		 14992001-02-19 Ben Elliston <bje@redhat.com>
1500
1501 * sim-main.h (sim_monitor): Return an int.
1502 * interp.c (sim_monitor): Add return values.
1503 (signal_exception): Handle error conditions from sim_monitor.
1504
56b48a7a
CD		 15052001-02-08 Ben Elliston <bje@redhat.com>
1506
1507 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1508 (store_memory): Likewise, pass cia to sim_core_write*.
1509
d3ee60d9
FCE		 15102000-10-19 Frank Ch. Eigler <fche@redhat.com>
1511
1512 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1513 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1514
071da002
AC		 1515Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1516
1517 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1518 * Makefile.in: Don't delete *.igen when cleaning directory.
1519
a28c02cd
AC		 1520Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1521
1522 * m16.igen (break): Call SignalException not sim_engine_halt.
1523
80ee11fa
AC		 1524Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 From Jason Eckhardt:
1527 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1528
673388c0
AC		 1529Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1532
4c0deff4
NC		 15332000-05-24 Michael Hayes <mhayes@cygnus.com>
1534
1535 * mips.igen (do_dmultx): Fix typo.
1536
eb2d80b4
AC		 1537Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * configure: Regenerated to track ../common/aclocal.m4 changes.
1540
dd37a34b
AC		 1541Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1544
4c0deff4
NC		 15452000-04-12 Frank Ch. Eigler <fche@redhat.com>
1546
1547 * sim-main.h (GPR_CLEAR): Define macro.
1548
e30db738
AC		 1549Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1550
1551 * interp.c (decode_coproc): Output long using %lx and not %s.
1552
cb7450ea
FCE		 15532000-03-21 Frank Ch. Eigler <fche@redhat.com>
1554
1555 * interp.c (sim_open): Sort & extend dummy memory regions for
1556 --board=jmr3904 for eCos.
1557
a3027dd7
FCE		 15582000-03-02 Frank Ch. Eigler <fche@redhat.com>
1559
1560 * configure: Regenerated.
1561
1562Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1563
1564 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1565 calls, conditional on the simulator being in verbose mode.
1566
dfcd3bfb
JM		 1567Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1568
1569 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1570 cache don't get ReservedInstruction traps.
1571
c2d11a7d
JM		 15721999-11-29 Mark Salter <msalter@cygnus.com>
1573
1574 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1575 to clear status bits in sdisr register. This is how the hardware works.
1576
1577 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1578 being used by cygmon.
1579
4ce44c66
JM		 15801999-11-11 Andrew Haley <aph@cygnus.com>
1581
1582 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1583 instructions.
1584
cff3e48b
JM		 1585Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1586
1587 * mips.igen (MULT): Correct previous mis-applied patch.
1588
d4f3574e
SS		 1589Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1590
1591 * mips.igen (delayslot32): Handle sequence like
1592 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1593 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1594 (MULT): Actually pass the third register...
1595
15961999-09-03 Mark Salter <msalter@cygnus.com>
1597
1598 * interp.c (sim_open): Added more memory aliases for additional
1599 hardware being touched by cygmon on jmr3904 board.
1600
1601Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1602
1603 * configure: Regenerated to track ../common/aclocal.m4 changes.
1604
a0b3c4fd
JM		 1605Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1606
1607 * interp.c (sim_store_register): Handle case where client - GDB -
1608 specifies that a 4 byte register is 8 bytes in size.
1609 (sim_fetch_register): Ditto.
72f4393d 1610
adf40b2e
JM		 16111999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1612
1613 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1614 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1615 (idt_monitor_base): Base address for IDT monitor traps.
1616 (pmon_monitor_base): Ditto for PMON.
1617 (lsipmon_monitor_base): Ditto for LSI PMON.
1618 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1619 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1620 (sim_firmware_command): New function.
1621 (mips_option_handler): Call it for OPTION_FIRMWARE.
1622 (sim_open): Allocate memory for idt_monitor region. If "--board"
1623 option was given, add no monitor by default. Add BREAK hooks only if
1624 monitors are also there.
72f4393d 1625
43e526b9
JM		 1626Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1627
1628 * interp.c (sim_monitor): Flush output before reading input.
1629
1630Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1631
1632 * tconfig.in (SIM_HANDLES_LMA): Always define.
1633
1634Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1635
1636 From Mark Salter <msalter@cygnus.com>:
1637 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1638 (sim_open): Add setup for BSP board.
1639
9846de1b
JM		 1640Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1641
1642 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1643 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1644 them as unimplemented.
1645
cd0fc7c3
SS		 16461999-05-08 Felix Lee <flee@cygnus.com>
1647
1648 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1649
7a292a7a
SS		 16501999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1651
1652 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1653
1654Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1655
1656 * configure.in: Any mips64vr5*-*-* target should have
1657 -DTARGET_ENABLE_FR=1.
1658 (default_endian): Any mips64vr*el-*-* target should default to
1659 LITTLE_ENDIAN.
1660 * configure: Re-generate.
1661
16621999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1663
1664 * mips.igen (ldl): Extend from _16_, not 32.
1665
1666Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1667
1668 * interp.c (sim_store_register): Force registers written to by GDB
1669 into an un-interpreted state.
1670
c906108c
SS		 16711999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1672
1673 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1674 CPU, start periodic background I/O polls.
72f4393d 1675 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1676
16771998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1678
1679 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1680
c906108c
SS		 1681Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1682
1683 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1684 case statement.
1685
16861998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1687
1688 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1689 (load_word): Call SIM_CORE_SIGNAL hook on error.
1690 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1691 starting. For exception dispatching, pass PC instead of NULL_CIA.
1692 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1693 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1694 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1695 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1696 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1697 * mips.igen (*): Replace memory-related SignalException* calls
1698 with references to SIM_CORE_SIGNAL hook.
72f4393d 1699
c906108c
SS		 1700 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1701 fix.
1702 * sim-main.c (*): Minor warning cleanups.
72f4393d 1703
c906108c
SS		 17041998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1705
1706 * m16.igen (DADDIU5): Correct type-o.
1707
1708Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1709
1710 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1711 variables.
1712
1713Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1714
1715 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1716 to include path.
1717 (interp.o): Add dependency on itable.h
1718 (oengine.c, gencode): Delete remaining references.
1719 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1720
c906108c 17211998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1722
c906108c
SS		 1723 * vr4run.c: New.
1724 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1725 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1726 tmp-run-hack) : New.
1727 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1728 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1729 Drop the "64" qualifier to get the HACK generator working.
1730 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1731 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1732 qualifier to get the hack generator working.
1733 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1734 (DSLL): Use do_dsll.
1735 (DSLLV): Use do_dsllv.
1736 (DSRA): Use do_dsra.
1737 (DSRL): Use do_dsrl.
1738 (DSRLV): Use do_dsrlv.
1739 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1740 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1741 get the HACK generator working.
1742 (MACC) Rename to get the HACK generator working.
1743 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1744
c906108c
SS		 17451998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1746
1747 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1748 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1749
c906108c
SS		 17501998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1751
1752 * mips/interp.c (DEBUG): Cleanups.
1753
17541998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1755
1756 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1757 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1758
c906108c
SS		 17591998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1760
1761 * interp.c (sim_close): Uninstall modules.
1762
1763Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1764
1765 * sim-main.h, interp.c (sim_monitor): Change to global
1766 function.
1767
1768Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1769
1770 * configure.in (vr4100): Only include vr4100 instructions in
1771 simulator.
1772 * configure: Re-generate.
1773 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1774
1775Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1776
1777 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1778 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1779 true alternative.
1780
1781 * configure.in (sim_default_gen, sim_use_gen): Replace with
1782 sim_gen.
1783 (--enable-sim-igen): Delete config option. Always using IGEN.
1784 * configure: Re-generate.
72f4393d 1785
c906108c
SS		 1786 * Makefile.in (gencode): Kill, kill, kill.
1787 * gencode.c: Ditto.
72f4393d 1788
c906108c
SS		 1789Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1790
1791 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1792 bit mips16 igen simulator.
1793 * configure: Re-generate.
1794
1795 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1796 as part of vr4100 ISA.
1797 * vr.igen: Mark all instructions as 64 bit only.
1798
1799Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1800
1801 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1802 Pacify GCC.
1803
1804Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1805
1806 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1807 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1808 * configure: Re-generate.
1809
1810 * m16.igen (BREAK): Define breakpoint instruction.
1811 (JALX32): Mark instruction as mips16 and not r3900.
1812 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1813
1814 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1815
1816Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1819 insn as a debug breakpoint.
1820
1821 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1822 pending.slot_size.
1823 (PENDING_SCHED): Clean up trace statement.
1824 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1825 (PENDING_FILL): Delay write by only one cycle.
1826 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1827
1828 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1829 of pending writes.
1830 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1831 32 & 64.
1832 (pending_tick): Move incrementing of index to FOR statement.
1833 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1834
c906108c
SS		 1835 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1836 build simulator.
1837 * configure: Re-generate.
72f4393d 1838
c906108c
SS		 1839 * interp.c (sim_engine_run OLD): Delete explicit call to
1840 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1841
c906108c
SS		 1842Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1843
1844 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1845 interrupt level number to match changed SignalExceptionInterrupt
1846 macro.
1847
1848Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1849
1850 * interp.c: #include "itable.h" if WITH_IGEN.
1851 (get_insn_name): New function.
1852 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1853 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1854
1855Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1856
1857 * configure: Rebuilt to inhale new common/aclocal.m4.
1858
1859Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1860
1861 * dv-tx3904sio.c: Include sim-assert.h.
1862
1863Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1864
1865 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1866 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1867 Reorganize target-specific sim-hardware checks.
1868 * configure: rebuilt.
1869 * interp.c (sim_open): For tx39 target boards, set
1870 OPERATING_ENVIRONMENT, add tx3904sio devices.
1871 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1872 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1873
c906108c
SS		 1874 * dv-tx3904irc.c: Compiler warning clean-up.
1875 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1876 frequent hw-trace messages.
1877
1878Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1879
1880 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1881
1882Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1883
1884 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1885
1886 * vr.igen: New file.
1887 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1888 * mips.igen: Define vr4100 model. Include vr.igen.
1889Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1890
1891 * mips.igen (check_mf_hilo): Correct check.
1892
1893Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1894
1895 * sim-main.h (interrupt_event): Add prototype.
1896
1897 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1898 register_ptr, register_value.
1899 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1900
1901 * sim-main.h (tracefh): Make extern.
1902
1903Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1904
1905 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1906 Reduce unnecessarily high timer event frequency.
c906108c 1907 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1908
c906108c
SS		 1909Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1910
1911 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1912 to allay warnings.
1913 (interrupt_event): Made non-static.
72f4393d 1914
c906108c
SS		 1915 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1916 interchange of configuration values for external vs. internal
1917 clock dividers.
72f4393d 1918
c906108c
SS		 1919Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1920
72f4393d 1921 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1922 simulator-reserved break instructions.
1923 * gencode.c (build_instruction): Ditto.
1924 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1925 reserved instructions now use exception vector, rather
c906108c
SS		 1926 than halting sim.
1927 * sim-main.h: Moved magic constants to here.
1928
1929Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1930
1931 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1932 register upon non-zero interrupt event level, clear upon zero
1933 event value.
1934 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1935 by passing zero event value.
1936 (*_io_{read,write}_buffer): Endianness fixes.
1937 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1938 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1939
1940 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1941 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1942
c906108c
SS		 1943Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1944
72f4393d 1945 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1946 and BigEndianCPU.
1947
1948Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1949
1950 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1951 parts.
1952 * configure: Update.
1953
1954Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1955
1956 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1957 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1958 * configure.in: Include tx3904tmr in hw_device list.
1959 * configure: Rebuilt.
1960 * interp.c (sim_open): Instantiate three timer instances.
1961 Fix address typo of tx3904irc instance.
1962
1963Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1964
1965 * interp.c (signal_exception): SystemCall exception now uses
1966 the exception vector.
1967
1968Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1969
1970 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1971 to allay warnings.
1972
1973Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1974
1975 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1976
1977Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1978
1979 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1980
1981 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1982 sim-main.h. Declare a struct hw_descriptor instead of struct
1983 hw_device_descriptor.
1984
1985Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1986
1987 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1988 right bits and then re-align left hand bytes to correct byte
1989 lanes. Fix incorrect computation in do_store_left when loading
1990 bytes from second word.
1991
1992Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
1993
1994 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1995 * interp.c (sim_open): Only create a device tree when HW is
1996 enabled.
1997
1998 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1999 * interp.c (signal_exception): Ditto.
2000
2001Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2002
2003 * gencode.c: Mark BEGEZALL as LIKELY.
2004
2005Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2006
2007 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2008 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2009
c906108c
SS		 2010Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2011
2012 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2013 modules. Recognize TX39 target with "mips*tx39" pattern.
2014 * configure: Rebuilt.
2015 * sim-main.h (*): Added many macros defining bits in
2016 TX39 control registers.
2017 (SignalInterrupt): Send actual PC instead of NULL.
2018 (SignalNMIReset): New exception type.
2019 * interp.c (board): New variable for future use to identify
2020 a particular board being simulated.
2021 (mips_option_handler,mips_options): Added "--board" option.
2022 (interrupt_event): Send actual PC.
2023 (sim_open): Make memory layout conditional on board setting.
2024 (signal_exception): Initial implementation of hardware interrupt
2025 handling. Accept another break instruction variant for simulator
2026 exit.
2027 (decode_coproc): Implement RFE instruction for TX39.
2028 (mips.igen): Decode RFE instruction as such.
2029 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2030 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2031 bbegin to implement memory map.
2032 * dv-tx3904cpu.c: New file.
2033 * dv-tx3904irc.c: New file.
2034
2035Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2036
2037 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2038
2039Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2040
2041 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2042 with calls to check_div_hilo.
2043
2044Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2045
2046 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2047 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2048 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2049 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2050 with calls to check_mult_hilo.
2051 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2052 with calls to check_div_hilo.
2053
2054Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2055
2056 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2057 Document a replacement.
2058
2059Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2060
2061 * interp.c (sim_monitor): Make mon_printf work.
2062
2063Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2064
2065 * sim-main.h (INSN_NAME): New arg `cpu'.
2066
2067Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2068
72f4393d 2069 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2070
2071Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2072
2073 * configure: Regenerated to track ../common/aclocal.m4 changes.
2074 * config.in: Ditto.
2075
2076Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2077
2078 * acconfig.h: New file.
2079 * configure.in: Reverted change of Apr 24; use sinclude again.
2080
2081Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2082
2083 * configure: Regenerated to track ../common/aclocal.m4 changes.
2084 * config.in: Ditto.
2085
2086Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2087
2088 * configure.in: Don't call sinclude.
2089
2090Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2091
2092 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2093
2094Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2095
2096 * mips.igen (ERET): Implement.
2097
2098 * interp.c (decode_coproc): Return sign-extended EPC.
2099
2100 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2101
2102 * interp.c (signal_exception): Do not ignore Trap.
2103 (signal_exception): On TRAP, restart at exception address.
2104 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2105 (signal_exception): Update.
2106 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2107 so that TRAP instructions are caught.
2108
2109Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2110
2111 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2112 contains HI/LO access history.
2113 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2114 (HIACCESS, LOACCESS): Delete, replace with
2115 (HIHISTORY, LOHISTORY): New macros.
2116 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2117
c906108c
SS		 2118 * gencode.c (build_instruction): Do not generate checks for
2119 correct HI/LO register usage.
2120
2121 * interp.c (old_engine_run): Delete checks for correct HI/LO
2122 register usage.
2123
2124 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2125 check_mf_cycles): New functions.
2126 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2127 do_divu, domultx, do_mult, do_multu): Use.
2128
2129 * tx.igen ("madd", "maddu"): Use.
72f4393d 2130
c906108c
SS		 2131Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2132
2133 * mips.igen (DSRAV): Use function do_dsrav.
2134 (SRAV): Use new function do_srav.
2135
2136 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2137 (B): Sign extend 11 bit immediate.
2138 (EXT-B*): Shift 16 bit immediate left by 1.
2139 (ADDIU*): Don't sign extend immediate value.
2140
2141Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2142
2143 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2144
2145 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2146 functions.
2147
2148 * mips.igen (delayslot32, nullify_next_insn): New functions.
2149 (m16.igen): Always include.
2150 (do_*): Add more tracing.
2151
2152 * m16.igen (delayslot16): Add NIA argument, could be called by a
2153 32 bit MIPS16 instruction.
72f4393d 2154
c906108c
SS		 2155 * interp.c (ifetch16): Move function from here.
2156 * sim-main.c (ifetch16): To here.
72f4393d 2157
c906108c
SS		 2158 * sim-main.c (ifetch16, ifetch32): Update to match current
2159 implementations of LH, LW.
2160 (signal_exception): Don't print out incorrect hex value of illegal
2161 instruction.
2162
2163Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2166 instruction.
2167
2168 * m16.igen: Implement MIPS16 instructions.
72f4393d 2169
c906108c
SS		 2170 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2171 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2172 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2173 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2174 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2175 bodies of corresponding code from 32 bit insn to these. Also used
2176 by MIPS16 versions of functions.
72f4393d 2177
c906108c
SS		 2178 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2179 (IMEM16): Drop NR argument from macro.
2180
2181Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2182
2183 * Makefile.in (SIM_OBJS): Add sim-main.o.
2184
2185 * sim-main.h (address_translation, load_memory, store_memory,
2186 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2187 as INLINE_SIM_MAIN.
2188 (pr_addr, pr_uword64): Declare.
2189 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2190
c906108c
SS		 2191 * interp.c (address_translation, load_memory, store_memory,
2192 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2193 from here.
2194 * sim-main.c: To here. Fix compilation problems.
72f4393d 2195
c906108c
SS		 2196 * configure.in: Enable inlining.
2197 * configure: Re-config.
2198
2199Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2200
2201 * configure: Regenerated to track ../common/aclocal.m4 changes.
2202
2203Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2204
2205 * mips.igen: Include tx.igen.
2206 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2207 * tx.igen: New file, contains MADD and MADDU.
2208
2209 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2210 the hardwired constant `7'.
2211 (store_memory): Ditto.
2212 (LOADDRMASK): Move definition to sim-main.h.
2213
2214 mips.igen (MTC0): Enable for r3900.
2215 (ADDU): Add trace.
2216
2217 mips.igen (do_load_byte): Delete.
2218 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2219 do_store_right): New functions.
2220 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2221
2222 configure.in: Let the tx39 use igen again.
2223 configure: Update.
72f4393d 2224
c906108c
SS		 2225Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2226
2227 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2228 not an address sized quantity. Return zero for cache sizes.
2229
2230Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2231
2232 * mips.igen (r3900): r3900 does not support 64 bit integer
2233 operations.
2234
2235Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2236
2237 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2238 than igen one.
2239 * configure : Rebuild.
72f4393d 2240
c906108c
SS		 2241Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2242
2243 * configure: Regenerated to track ../common/aclocal.m4 changes.
2244
2245Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2246
2247 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2248
2249Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2250
2251 * configure: Regenerated to track ../common/aclocal.m4 changes.
2252 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2253
2254Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2255
2256 * configure: Regenerated to track ../common/aclocal.m4 changes.
2257
2258Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * interp.c (Max, Min): Comment out functions. Not yet used.
2261
2262Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2263
2264 * configure: Regenerated to track ../common/aclocal.m4 changes.
2265
2266Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2267
2268 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2269 configurable settings for stand-alone simulator.
72f4393d 2270
c906108c 2271 * configure.in: Added X11 search, just in case.
72f4393d 2272
c906108c
SS		 2273 * configure: Regenerated.
2274
2275Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2276
2277 * interp.c (sim_write, sim_read, load_memory, store_memory):
2278 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2279
2280Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2281
2282 * sim-main.h (GETFCC): Return an unsigned value.
2283
2284Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2285
2286 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2287 (DADD): Result destination is RD not RT.
2288
2289Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2290
2291 * sim-main.h (HIACCESS, LOACCESS): Always define.
2292
2293 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2294
2295 * interp.c (sim_info): Delete.
2296
2297Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2298
2299 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2300 (mips_option_handler): New argument `cpu'.
2301 (sim_open): Update call to sim_add_option_table.
2302
2303Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2304
2305 * mips.igen (CxC1): Add tracing.
2306
2307Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2308
2309 * sim-main.h (Max, Min): Declare.
2310
2311 * interp.c (Max, Min): New functions.
2312
2313 * mips.igen (BC1): Add tracing.
72f4393d 2314
c906108c 2315Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2316
c906108c 2317 * interp.c Added memory map for stack in vr4100
72f4393d 2318
c906108c
SS		 2319Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2320
2321 * interp.c (load_memory): Add missing "break"'s.
2322
2323Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * interp.c (sim_store_register, sim_fetch_register): Pass in
2326 length parameter. Return -1.
2327
2328Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2329
2330 * interp.c: Added hardware init hook, fixed warnings.
2331
2332Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2335
2336Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2337
2338 * interp.c (ifetch16): New function.
2339
2340 * sim-main.h (IMEM32): Rename IMEM.
2341 (IMEM16_IMMED): Define.
2342 (IMEM16): Define.
2343 (DELAY_SLOT): Update.
72f4393d 2344
c906108c 2345 * m16run.c (sim_engine_run): New file.
72f4393d 2346
c906108c
SS		 2347 * m16.igen: All instructions except LB.
2348 (LB): Call do_load_byte.
2349 * mips.igen (do_load_byte): New function.
2350 (LB): Call do_load_byte.
2351
2352 * mips.igen: Move spec for insn bit size and high bit from here.
2353 * Makefile.in (tmp-igen, tmp-m16): To here.
2354
2355 * m16.dc: New file, decode mips16 instructions.
2356
2357 * Makefile.in (SIM_NO_ALL): Define.
2358 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2359
2360Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2361
2362 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2363 point unit to 32 bit registers.
2364 * configure: Re-generate.
2365
2366Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2367
2368 * configure.in (sim_use_gen): Make IGEN the default simulator
2369 generator for generic 32 and 64 bit mips targets.
2370 * configure: Re-generate.
2371
2372Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2373
2374 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2375 bitsize.
2376
2377 * interp.c (sim_fetch_register, sim_store_register): Read/write
2378 FGR from correct location.
2379 (sim_open): Set size of FGR's according to
2380 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2381
c906108c
SS		 2382 * sim-main.h (FGR): Store floating point registers in a separate
2383 array.
2384
2385Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2386
2387 * configure: Regenerated to track ../common/aclocal.m4 changes.
2388
2389Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2390
2391 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2392
2393 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2394
2395 * interp.c (pending_tick): New function. Deliver pending writes.
2396
2397 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2398 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2399 it can handle mixed sized quantites and single bits.
72f4393d 2400
c906108c
SS		 2401Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2402
2403 * interp.c (oengine.h): Do not include when building with IGEN.
2404 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2405 (sim_info): Ditto for PROCESSOR_64BIT.
2406 (sim_monitor): Replace ut_reg with unsigned_word.
2407 (*): Ditto for t_reg.
2408 (LOADDRMASK): Define.
2409 (sim_open): Remove defunct check that host FP is IEEE compliant,
2410 using software to emulate floating point.
2411 (value_fpr, ...): Always compile, was conditional on HASFPU.
2412
2413Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2414
2415 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2416 size.
2417
2418 * interp.c (SD, CPU): Define.
2419 (mips_option_handler): Set flags in each CPU.
2420 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2421 (sim_close): Do not clear STATE, deleted anyway.
2422 (sim_write, sim_read): Assume CPU zero's vm should be used for
2423 data transfers.
2424 (sim_create_inferior): Set the PC for all processors.
2425 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2426 argument.
2427 (mips16_entry): Pass correct nr of args to store_word, load_word.
2428 (ColdReset): Cold reset all cpu's.
2429 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2430 (sim_monitor, load_memory, store_memory, signal_exception): Use
2431 `CPU' instead of STATE_CPU.
2432
2433
2434 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2435 SD or CPU_.
72f4393d 2436
c906108c
SS		 2437 * sim-main.h (signal_exception): Add sim_cpu arg.
2438 (SignalException*): Pass both SD and CPU to signal_exception.
2439 * interp.c (signal_exception): Update.
72f4393d 2440
c906108c
SS		 2441 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2442 Ditto
2443 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2444 address_translation): Ditto
2445 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2446
c906108c
SS		 2447Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2448
2449 * configure: Regenerated to track ../common/aclocal.m4 changes.
2450
2451Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2452
2453 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2454
72f4393d 2455 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2456
2457 * sim-main.h (CPU_CIA): Delete.
2458 (SET_CIA, GET_CIA): Define
2459
2460Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2461
2462 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2463 regiser.
2464
2465 * configure.in (default_endian): Configure a big-endian simulator
2466 by default.
2467 * configure: Re-generate.
72f4393d 2468
c906108c
SS		 2469Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2470
2471 * configure: Regenerated to track ../common/aclocal.m4 changes.
2472
2473Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2474
2475 * interp.c (sim_monitor): Handle Densan monitor outbyte
2476 and inbyte functions.
2477
24781997-12-29 Felix Lee <flee@cygnus.com>
2479
2480 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2481
2482Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2483
2484 * Makefile.in (tmp-igen): Arrange for $zero to always be
2485 reset to zero after every instruction.
2486
2487Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2488
2489 * configure: Regenerated to track ../common/aclocal.m4 changes.
2490 * config.in: Ditto.
2491
2492Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2493
2494 * mips.igen (MSUB): Fix to work like MADD.
2495 * gencode.c (MSUB): Similarly.
2496
2497Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2498
2499 * configure: Regenerated to track ../common/aclocal.m4 changes.
2500
2501Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2504
2505Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2506
2507 * sim-main.h (sim-fpu.h): Include.
2508
2509 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2510 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2511 using host independant sim_fpu module.
2512
2513Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2514
2515 * interp.c (signal_exception): Report internal errors with SIGABRT
2516 not SIGQUIT.
2517
2518 * sim-main.h (C0_CONFIG): New register.
2519 (signal.h): No longer include.
2520
2521 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2522
2523Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2524
2525 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2526
2527Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2528
2529 * mips.igen: Tag vr5000 instructions.
2530 (ANDI): Was missing mipsIV model, fix assembler syntax.
2531 (do_c_cond_fmt): New function.
2532 (C.cond.fmt): Handle mips I-III which do not support CC field
2533 separatly.
2534 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2535 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2536 in IV3.2 spec.
2537 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2538 vr5000 which saves LO in a GPR separatly.
72f4393d 2539
c906108c
SS		 2540 * configure.in (enable-sim-igen): For vr5000, select vr5000
2541 specific instructions.
2542 * configure: Re-generate.
72f4393d 2543
c906108c
SS		 2544Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2545
2546 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2547
2548 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2549 fmt_uninterpreted_64 bit cases to switch. Convert to
2550 fmt_formatted,
2551
2552 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2553
2554 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2555 as specified in IV3.2 spec.
2556 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2557
2558Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2559
2560 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2561 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2562 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2563 PENDING_FILL versions of instructions. Simplify.
2564 (X): New function.
2565 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2566 instructions.
2567 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2568 a signed value.
2569 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2570
c906108c
SS		 2571 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2572 global.
2573 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2574
2575Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * gencode.c (build_mips16_operands): Replace IPC with cia.
2578
2579 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2580 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2581 IPC to `cia'.
2582 (UndefinedResult): Replace function with macro/function
2583 combination.
2584 (sim_engine_run): Don't save PC in IPC.
2585
2586 * sim-main.h (IPC): Delete.
2587
2588
2589 * interp.c (signal_exception, store_word, load_word,
2590 address_translation, load_memory, store_memory, cache_op,
2591 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2592 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2593 current instruction address - cia - argument.
2594 (sim_read, sim_write): Call address_translation directly.
2595 (sim_engine_run): Rename variable vaddr to cia.
2596 (signal_exception): Pass cia to sim_monitor
72f4393d 2597
c906108c
SS		 2598 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2599 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2600 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2601
2602 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2603 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2604 SIM_ASSERT.
72f4393d 2605
c906108c
SS		 2606 * interp.c (signal_exception): Pass restart address to
2607 sim_engine_restart.
2608
2609 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2610 idecode.o): Add dependency.
2611
2612 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2613 Delete definitions
2614 (DELAY_SLOT): Update NIA not PC with branch address.
2615 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2616
2617 * mips.igen: Use CIA not PC in branch calculations.
2618 (illegal): Call SignalException.
2619 (BEQ, ADDIU): Fix assembler.
2620
2621Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2622
2623 * m16.igen (JALX): Was missing.
2624
2625 * configure.in (enable-sim-igen): New configuration option.
2626 * configure: Re-generate.
72f4393d 2627
c906108c
SS		 2628 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2629
2630 * interp.c (load_memory, store_memory): Delete parameter RAW.
2631 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2632 bypassing {load,store}_memory.
2633
2634 * sim-main.h (ByteSwapMem): Delete definition.
2635
2636 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2637
2638 * interp.c (sim_do_command, sim_commands): Delete mips specific
2639 commands. Handled by module sim-options.
72f4393d 2640
c906108c
SS		 2641 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2642 (WITH_MODULO_MEMORY): Define.
2643
2644 * interp.c (sim_info): Delete code printing memory size.
2645
2646 * interp.c (mips_size): Nee sim_size, delete function.
2647 (power2): Delete.
2648 (monitor, monitor_base, monitor_size): Delete global variables.
2649 (sim_open, sim_close): Delete code creating monitor and other
2650 memory regions. Use sim-memopts module, via sim_do_commandf, to
2651 manage memory regions.
2652 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2653
c906108c
SS		 2654 * interp.c (address_translation): Delete all memory map code
2655 except line forcing 32 bit addresses.
2656
2657Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2658
2659 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2660 trace options.
2661
2662 * interp.c (logfh, logfile): Delete globals.
2663 (sim_open, sim_close): Delete code opening & closing log file.
2664 (mips_option_handler): Delete -l and -n options.
2665 (OPTION mips_options): Ditto.
2666
2667 * interp.c (OPTION mips_options): Rename option trace to dinero.
2668 (mips_option_handler): Update.
2669
2670Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2671
2672 * interp.c (fetch_str): New function.
2673 (sim_monitor): Rewrite using sim_read & sim_write.
2674 (sim_open): Check magic number.
2675 (sim_open): Write monitor vectors into memory using sim_write.
2676 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2677 (sim_read, sim_write): Simplify - transfer data one byte at a
2678 time.
2679 (load_memory, store_memory): Clarify meaning of parameter RAW.
2680
2681 * sim-main.h (isHOST): Defete definition.
2682 (isTARGET): Mark as depreciated.
2683 (address_translation): Delete parameter HOST.
2684
2685 * interp.c (address_translation): Delete parameter HOST.
2686
2687Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2688
72f4393d 2689 * mips.igen:
c906108c
SS		 2690
2691 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2692 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2693
2694Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695
2696 * mips.igen: Add model filter field to records.
2697
2698Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2699
2700 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2701
c906108c
SS		 2702 interp.c (sim_engine_run): Do not compile function sim_engine_run
2703 when WITH_IGEN == 1.
2704
2705 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2706 target architecture.
2707
2708 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2709 igen. Replace with configuration variables sim_igen_flags /
2710 sim_m16_flags.
2711
2712 * m16.igen: New file. Copy mips16 insns here.
2713 * mips.igen: From here.
2714
2715Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716
2717 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2718 to top.
2719 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2720
2721Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2722
2723 * gencode.c (build_instruction): Follow sim_write's lead in using
2724 BigEndianMem instead of !ByteSwapMem.
2725
2726Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2727
2728 * configure.in (sim_gen): Dependent on target, select type of
2729 generator. Always select old style generator.
2730
2731 configure: Re-generate.
2732
2733 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2734 targets.
2735 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2736 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2737 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2738 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2739 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2740
c906108c
SS		 2741Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2742
2743 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2744
2745 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2746 CURRENT_FLOATING_POINT instead.
2747
2748 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2749 (address_translation): Raise exception InstructionFetch when
2750 translation fails and isINSTRUCTION.
72f4393d 2751
c906108c
SS		 2752 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2753 sim_engine_run): Change type of of vaddr and paddr to
2754 address_word.
2755 (address_translation, prefetch, load_memory, store_memory,
2756 cache_op): Change type of vAddr and pAddr to address_word.
2757
2758 * gencode.c (build_instruction): Change type of vaddr and paddr to
2759 address_word.
2760
2761Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2762
2763 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2764 macro to obtain result of ALU op.
2765
2766Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2767
2768 * interp.c (sim_info): Call profile_print.
2769
2770Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2771
2772 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2773
2774 * sim-main.h (WITH_PROFILE): Do not define, defined in
2775 common/sim-config.h. Use sim-profile module.
2776 (simPROFILE): Delete defintion.
2777
2778 * interp.c (PROFILE): Delete definition.
2779 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2780 (sim_close): Delete code writing profile histogram.
2781 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2782 Delete.
2783 (sim_engine_run): Delete code profiling the PC.
2784
2785Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2786
2787 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2788
2789 * interp.c (sim_monitor): Make register pointers of type
2790 unsigned_word*.
2791
2792 * sim-main.h: Make registers of type unsigned_word not
2793 signed_word.
2794
2795Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
2797 * interp.c (sync_operation): Rename from SyncOperation, make
2798 global, add SD argument.
2799 (prefetch): Rename from Prefetch, make global, add SD argument.
2800 (decode_coproc): Make global.
2801
2802 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2803
2804 * gencode.c (build_instruction): Generate DecodeCoproc not
2805 decode_coproc calls.
2806
2807 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2808 (SizeFGR): Move to sim-main.h
2809 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2810 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2811 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2812 sim-main.h.
2813 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2814 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2815 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2816 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2817 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2818 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2819
c906108c
SS		 2820 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2821 exception.
2822 (sim-alu.h): Include.
2823 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2824 (sim_cia): Typedef to instruction_address.
72f4393d 2825
c906108c
SS		 2826Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2827
2828 * Makefile.in (interp.o): Rename generated file engine.c to
2829 oengine.c.
72f4393d 2830
c906108c 2831 * interp.c: Update.
72f4393d 2832
c906108c
SS		 2833Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2836
c906108c
SS		 2837Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2838
2839 * gencode.c (build_instruction): For "FPSQRT", output correct
2840 number of arguments to Recip.
72f4393d 2841
c906108c
SS		 2842Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2843
2844 * Makefile.in (interp.o): Depends on sim-main.h
2845
2846 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2847
2848 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2849 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2850 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2851 STATE, DSSTATE): Define
2852 (GPR, FGRIDX, ..): Define.
2853
2854 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2855 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2856 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2857
c906108c 2858 * interp.c: Update names to match defines from sim-main.h
72f4393d 2859
c906108c
SS		 2860Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2861
2862 * interp.c (sim_monitor): Add SD argument.
2863 (sim_warning): Delete. Replace calls with calls to
2864 sim_io_eprintf.
2865 (sim_error): Delete. Replace calls with sim_io_error.
2866 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2867 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2868 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2869 argument.
2870 (mips_size): Rename from sim_size. Add SD argument.
2871
2872 * interp.c (simulator): Delete global variable.
2873 (callback): Delete global variable.
2874 (mips_option_handler, sim_open, sim_write, sim_read,
2875 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2876 sim_size,sim_monitor): Use sim_io_* not callback->*.
2877 (sim_open): ZALLOC simulator struct.
2878 (PROFILE): Do not define.
2879
2880Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2881
2882 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2883 support.h with corresponding code.
2884
2885 * sim-main.h (word64, uword64), support.h: Move definition to
2886 sim-main.h.
2887 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2888
2889 * support.h: Delete
2890 * Makefile.in: Update dependencies
2891 * interp.c: Do not include.
72f4393d 2892
c906108c
SS		 2893Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2894
2895 * interp.c (address_translation, load_memory, store_memory,
2896 cache_op): Rename to from AddressTranslation et.al., make global,
2897 add SD argument
72f4393d 2898
c906108c
SS		 2899 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2900 CacheOp): Define.
72f4393d 2901
c906108c
SS		 2902 * interp.c (SignalException): Rename to signal_exception, make
2903 global.
2904
2905 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2906
c906108c
SS		 2907 * sim-main.h (SignalException, SignalExceptionInterrupt,
2908 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2909 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2910 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2911 Define.
72f4393d 2912
c906108c 2913 * interp.c, support.h: Use.
72f4393d 2914
c906108c
SS		 2915Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916
2917 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2918 to value_fpr / store_fpr. Add SD argument.
2919 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2920 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2921
2922 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2923
c906108c
SS		 2924Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2925
2926 * interp.c (sim_engine_run): Check consistency between configure
2927 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2928 and HASFPU.
2929
2930 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2931 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2932 (mips_endian): Configure WITH_TARGET_ENDIAN.
2933 * configure: Update.
2934
2935Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2936
2937 * configure: Regenerated to track ../common/aclocal.m4 changes.
2938
2939Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2940
2941 * configure: Regenerated.
2942
2943Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2944
2945 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2946
2947Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2948
2949 * gencode.c (print_igen_insn_models): Assume certain architectures
2950 include all mips* instructions.
2951 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2952 instruction.
2953
2954 * Makefile.in (tmp.igen): Add target. Generate igen input from
2955 gencode file.
2956
2957 * gencode.c (FEATURE_IGEN): Define.
2958 (main): Add --igen option. Generate output in igen format.
2959 (process_instructions): Format output according to igen option.
2960 (print_igen_insn_format): New function.
2961 (print_igen_insn_models): New function.
2962 (process_instructions): Only issue warnings and ignore
2963 instructions when no FEATURE_IGEN.
2964
2965Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2966
2967 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2968 MIPS targets.
2969
2970Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2971
2972 * configure: Regenerated to track ../common/aclocal.m4 changes.
2973
2974Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2975
2976 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2977 SIM_RESERVED_BITS): Delete, moved to common.
2978 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2979
c906108c
SS		 2980Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2981
2982 * configure.in: Configure non-strict memory alignment.
2983 * configure: Regenerated to track ../common/aclocal.m4 changes.
2984
2985Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2986
2987 * configure: Regenerated to track ../common/aclocal.m4 changes.
2988
2989Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2990
2991 * gencode.c (SDBBP,DERET): Added (3900) insns.
2992 (RFE): Turn on for 3900.
2993 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2994 (dsstate): Made global.
2995 (SUBTARGET_R3900): Added.
2996 (CANCELDELAYSLOT): New.
2997 (SignalException): Ignore SystemCall rather than ignore and
2998 terminate. Add DebugBreakPoint handling.
2999 (decode_coproc): New insns RFE, DERET; and new registers Debug
3000 and DEPC protected by SUBTARGET_R3900.
3001 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3002 bits explicitly.
3003 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3004 * configure: Update.
c906108c
SS		 3005
3006Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3007
3008 * gencode.c: Add r3900 (tx39).
72f4393d 3009
c906108c
SS		 3010
3011Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3012
3013 * gencode.c (build_instruction): Don't need to subtract 4 for
3014 JALR, just 2.
3015
3016Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3017
3018 * interp.c: Correct some HASFPU problems.
3019
3020Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3021
3022 * configure: Regenerated to track ../common/aclocal.m4 changes.
3023
3024Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025
3026 * interp.c (mips_options): Fix samples option short form, should
3027 be `x'.
3028
3029Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030
3031 * interp.c (sim_info): Enable info code. Was just returning.
3032
3033Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3034
3035 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3036 MFC0.
3037
3038Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039
3040 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3041 constants.
3042 (build_instruction): Ditto for LL.
3043
3044Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3045
3046 * configure: Regenerated to track ../common/aclocal.m4 changes.
3047
3048Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3049
3050 * configure: Regenerated to track ../common/aclocal.m4 changes.
3051 * config.in: Ditto.
3052
3053Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3054
3055 * interp.c (sim_open): Add call to sim_analyze_program, update
3056 call to sim_config.
3057
3058Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3059
3060 * interp.c (sim_kill): Delete.
3061 (sim_create_inferior): Add ABFD argument. Set PC from same.
3062 (sim_load): Move code initializing trap handlers from here.
3063 (sim_open): To here.
3064 (sim_load): Delete, use sim-hload.c.
3065
3066 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3067
3068Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3069
3070 * configure: Regenerated to track ../common/aclocal.m4 changes.
3071 * config.in: Ditto.
3072
3073Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3074
3075 * interp.c (sim_open): Add ABFD argument.
3076 (sim_load): Move call to sim_config from here.
3077 (sim_open): To here. Check return status.
3078
3079Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3080
c906108c
SS		 3081 * gencode.c (build_instruction): Two arg MADD should
3082 not assign result to $0.
72f4393d 3083
c906108c
SS		 3084Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3085
3086 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3087 * sim/mips/configure.in: Regenerate.
3088
3089Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3090
3091 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3092 signed8, unsigned8 et.al. types.
3093
3094 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3095 hosts when selecting subreg.
3096
3097Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3098
3099 * interp.c (sim_engine_run): Reset the ZERO register to zero
3100 regardless of FEATURE_WARN_ZERO.
3101 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3102
3103Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3104
3105 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3106 (SignalException): For BreakPoints ignore any mode bits and just
3107 save the PC.
3108 (SignalException): Always set the CAUSE register.
3109
3110Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3111
3112 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3113 exception has been taken.
3114
3115 * interp.c: Implement the ERET and mt/f sr instructions.
3116
3117Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3118
3119 * interp.c (SignalException): Don't bother restarting an
3120 interrupt.
3121
3122Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3123
3124 * interp.c (SignalException): Really take an interrupt.
3125 (interrupt_event): Only deliver interrupts when enabled.
3126
3127Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * interp.c (sim_info): Only print info when verbose.
3130 (sim_info) Use sim_io_printf for output.
72f4393d 3131
c906108c
SS		 3132Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3133
3134 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3135 mips architectures.
3136
3137Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3138
3139 * interp.c (sim_do_command): Check for common commands if a
3140 simulator specific command fails.
3141
3142Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3143
3144 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3145 and simBE when DEBUG is defined.
3146
3147Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3148
3149 * interp.c (interrupt_event): New function. Pass exception event
3150 onto exception handler.
3151
3152 * configure.in: Check for stdlib.h.
3153 * configure: Regenerate.
3154
3155 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3156 variable declaration.
3157 (build_instruction): Initialize memval1.
3158 (build_instruction): Add UNUSED attribute to byte, bigend,
3159 reverse.
3160 (build_operands): Ditto.
3161
3162 * interp.c: Fix GCC warnings.
3163 (sim_get_quit_code): Delete.
3164
3165 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3166 * Makefile.in: Ditto.
3167 * configure: Re-generate.
72f4393d 3168
c906108c
SS		 3169 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3170
3171Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3172
3173 * interp.c (mips_option_handler): New function parse argumes using
3174 sim-options.
3175 (myname): Replace with STATE_MY_NAME.
3176 (sim_open): Delete check for host endianness - performed by
3177 sim_config.
3178 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3179 (sim_open): Move much of the initialization from here.
3180 (sim_load): To here. After the image has been loaded and
3181 endianness set.
3182 (sim_open): Move ColdReset from here.
3183 (sim_create_inferior): To here.
3184 (sim_open): Make FP check less dependant on host endianness.
3185
3186 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3187 run.
3188 * interp.c (sim_set_callbacks): Delete.
3189
3190 * interp.c (membank, membank_base, membank_size): Replace with
3191 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3192 (sim_open): Remove call to callback->init. gdb/run do this.
3193
3194 * interp.c: Update
3195
3196 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3197
3198 * interp.c (big_endian_p): Delete, replaced by
3199 current_target_byte_order.
3200
3201Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3202
3203 * interp.c (host_read_long, host_read_word, host_swap_word,
3204 host_swap_long): Delete. Using common sim-endian.
3205 (sim_fetch_register, sim_store_register): Use H2T.
3206 (pipeline_ticks): Delete. Handled by sim-events.
3207 (sim_info): Update.
3208 (sim_engine_run): Update.
3209
3210Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3213 reason from here.
3214 (SignalException): To here. Signal using sim_engine_halt.
3215 (sim_stop_reason): Delete, moved to common.
72f4393d 3216
c906108c
SS		 3217Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3218
3219 * interp.c (sim_open): Add callback argument.
3220 (sim_set_callbacks): Delete SIM_DESC argument.
3221 (sim_size): Ditto.
3222
3223Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3224
3225 * Makefile.in (SIM_OBJS): Add common modules.
3226
3227 * interp.c (sim_set_callbacks): Also set SD callback.
3228 (set_endianness, xfer_*, swap_*): Delete.
3229 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3230 Change to functions using sim-endian macros.
3231 (control_c, sim_stop): Delete, use common version.
3232 (simulate): Convert into.
3233 (sim_engine_run): This function.
3234 (sim_resume): Delete.
72f4393d 3235
c906108c
SS		 3236 * interp.c (simulation): New variable - the simulator object.
3237 (sim_kind): Delete global - merged into simulation.
3238 (sim_load): Cleanup. Move PC assignment from here.
3239 (sim_create_inferior): To here.
3240
3241 * sim-main.h: New file.
3242 * interp.c (sim-main.h): Include.
72f4393d 3243
c906108c
SS		 3244Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3245
3246 * configure: Regenerated to track ../common/aclocal.m4 changes.
3247
3248Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3249
3250 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3251
3252Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3253
72f4393d
L		 3254 * gencode.c (build_instruction): DIV instructions: check
3255 for division by zero and integer overflow before using
c906108c
SS		 3256 host's division operation.
3257
3258Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3259
3260 * Makefile.in (SIM_OBJS): Add sim-load.o.
3261 * interp.c: #include bfd.h.
3262 (target_byte_order): Delete.
3263 (sim_kind, myname, big_endian_p): New static locals.
3264 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3265 after argument parsing. Recognize -E arg, set endianness accordingly.
3266 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3267 load file into simulator. Set PC from bfd.
3268 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3269 (set_endianness): Use big_endian_p instead of target_byte_order.
3270
3271Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3272
3273 * interp.c (sim_size): Delete prototype - conflicts with
3274 definition in remote-sim.h. Correct definition.
3275
3276Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3277
3278 * configure: Regenerated to track ../common/aclocal.m4 changes.
3279 * config.in: Ditto.
3280
3281Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3282
3283 * interp.c (sim_open): New arg `kind'.
3284
3285 * configure: Regenerated to track ../common/aclocal.m4 changes.
3286
3287Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3288
3289 * configure: Regenerated to track ../common/aclocal.m4 changes.
3290
3291Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3292
3293 * interp.c (sim_open): Set optind to 0 before calling getopt.
3294
3295Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3296
3297 * configure: Regenerated to track ../common/aclocal.m4 changes.
3298
3299Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3300
3301 * interp.c : Replace uses of pr_addr with pr_uword64
3302 where the bit length is always 64 independent of SIM_ADDR.
3303 (pr_uword64) : added.
3304
3305Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3306
3307 * configure: Re-generate.
3308
3309Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3310
3311 * configure: Regenerate to track ../common/aclocal.m4 changes.
3312
3313Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3314
3315 * interp.c (sim_open): New SIM_DESC result. Argument is now
3316 in argv form.
3317 (other sim_*): New SIM_DESC argument.
3318
3319Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3320
3321 * interp.c: Fix printing of addresses for non-64-bit targets.
3322 (pr_addr): Add function to print address based on size.
3323
3324Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3325
3326 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3327
3328Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3329
3330 * gencode.c (build_mips16_operands): Correct computation of base
3331 address for extended PC relative instruction.
3332
3333Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3334
3335 * interp.c (mips16_entry): Add support for floating point cases.
3336 (SignalException): Pass floating point cases to mips16_entry.
3337 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3338 registers.
3339 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3340 or fmt_word.
3341 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3342 and then set the state to fmt_uninterpreted.
3343 (COP_SW): Temporarily set the state to fmt_word while calling
3344 ValueFPR.
3345
3346Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3347
3348 * gencode.c (build_instruction): The high order may be set in the
3349 comparison flags at any ISA level, not just ISA 4.
3350
3351Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3352
3353 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3354 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3355 * configure.in: sinclude ../common/aclocal.m4.
3356 * configure: Regenerated.
3357
3358Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3359
3360 * configure: Rebuild after change to aclocal.m4.
3361
3362Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3363
3364 * configure configure.in Makefile.in: Update to new configure
3365 scheme which is more compatible with WinGDB builds.
3366 * configure.in: Improve comment on how to run autoconf.
3367 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3368 * Makefile.in: Use autoconf substitution to install common
3369 makefile fragment.
3370
3371Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3372
3373 * gencode.c (build_instruction): Use BigEndianCPU instead of
3374 ByteSwapMem.
3375
3376Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3377
3378 * interp.c (sim_monitor): Make output to stdout visible in
3379 wingdb's I/O log window.
3380
3381Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3382
3383 * support.h: Undo previous change to SIGTRAP
3384 and SIGQUIT values.
3385
3386Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3387
3388 * interp.c (store_word, load_word): New static functions.
3389 (mips16_entry): New static function.
3390 (SignalException): Look for mips16 entry and exit instructions.
3391 (simulate): Use the correct index when setting fpr_state after
3392 doing a pending move.
3393
3394Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3395
3396 * interp.c: Fix byte-swapping code throughout to work on
3397 both little- and big-endian hosts.
3398
3399Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3400
3401 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3402 with gdb/config/i386/xm-windows.h.
3403
3404Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3405
3406 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3407 that messes up arithmetic shifts.
3408
3409Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3410
3411 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3412 SIGTRAP and SIGQUIT for _WIN32.
3413
3414Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3415
3416 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3417 force a 64 bit multiplication.
3418 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3419 destination register is 0, since that is the default mips16 nop
3420 instruction.
3421
3422Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3423
3424 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3425 (build_endian_shift): Don't check proc64.
3426 (build_instruction): Always set memval to uword64. Cast op2 to
3427 uword64 when shifting it left in memory instructions. Always use
3428 the same code for stores--don't special case proc64.
3429
3430 * gencode.c (build_mips16_operands): Fix base PC value for PC
3431 relative operands.
3432 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3433 jal instruction.
3434 * interp.c (simJALDELAYSLOT): Define.
3435 (JALDELAYSLOT): Define.
3436 (INDELAYSLOT, INJALDELAYSLOT): Define.
3437 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3438
3439Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3440
3441 * interp.c (sim_open): add flush_cache as a PMON routine
3442 (sim_monitor): handle flush_cache by ignoring it
3443
3444Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3445
3446 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3447 BigEndianMem.
3448 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3449 (BigEndianMem): Rename to ByteSwapMem and change sense.
3450 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3451 BigEndianMem references to !ByteSwapMem.
3452 (set_endianness): New function, with prototype.
3453 (sim_open): Call set_endianness.
3454 (sim_info): Use simBE instead of BigEndianMem.
3455 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3456 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3457 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3458 ifdefs, keeping the prototype declaration.
3459 (swap_word): Rewrite correctly.
3460 (ColdReset): Delete references to CONFIG. Delete endianness related
3461 code; moved to set_endianness.
72f4393d 3462
c906108c
SS		 3463Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3464
3465 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3466 * interp.c (CHECKHILO): Define away.
3467 (simSIGINT): New macro.
3468 (membank_size): Increase from 1MB to 2MB.
3469 (control_c): New function.
3470 (sim_resume): Rename parameter signal to signal_number. Add local
3471 variable prev. Call signal before and after simulate.
3472 (sim_stop_reason): Add simSIGINT support.
3473 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3474 functions always.
3475 (sim_warning): Delete call to SignalException. Do call printf_filtered
3476 if logfh is NULL.
3477 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3478 a call to sim_warning.
3479
3480Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3481
3482 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3483 16 bit instructions.
3484
3485Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3486
3487 Add support for mips16 (16 bit MIPS implementation):
3488 * gencode.c (inst_type): Add mips16 instruction encoding types.
3489 (GETDATASIZEINSN): Define.
3490 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3491 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3492 mtlo.
3493 (MIPS16_DECODE): New table, for mips16 instructions.
3494 (bitmap_val): New static function.
3495 (struct mips16_op): Define.
3496 (mips16_op_table): New table, for mips16 operands.
3497 (build_mips16_operands): New static function.
3498 (process_instructions): If PC is odd, decode a mips16
3499 instruction. Break out instruction handling into new
3500 build_instruction function.
3501 (build_instruction): New static function, broken out of
3502 process_instructions. Check modifiers rather than flags for SHIFT
3503 bit count and m[ft]{hi,lo} direction.
3504 (usage): Pass program name to fprintf.
3505 (main): Remove unused variable this_option_optind. Change
3506 ``*loptarg++'' to ``loptarg++''.
3507 (my_strtoul): Parenthesize && within ||.
3508 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3509 (simulate): If PC is odd, fetch a 16 bit instruction, and
3510 increment PC by 2 rather than 4.
3511 * configure.in: Add case for mips16*-*-*.
3512 * configure: Rebuild.
3513
3514Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3515
3516 * interp.c: Allow -t to enable tracing in standalone simulator.
3517 Fix garbage output in trace file and error messages.
3518
3519Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3520
3521 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3522 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3523 * configure.in: Simplify using macros in ../common/aclocal.m4.
3524 * configure: Regenerated.
3525 * tconfig.in: New file.
3526
3527Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3528
3529 * interp.c: Fix bugs in 64-bit port.
3530 Use ansi function declarations for msvc compiler.
3531 Initialize and test file pointer in trace code.
3532 Prevent duplicate definition of LAST_EMED_REGNUM.
3533
3534Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3535
3536 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3537
3538Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3539
3540 * interp.c (SignalException): Check for explicit terminating
3541 breakpoint value.
3542 * gencode.c: Pass instruction value through SignalException()
3543 calls for Trap, Breakpoint and Syscall.
3544
3545Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3546
3547 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3548 only used on those hosts that provide it.
3549 * configure.in: Add sqrt() to list of functions to be checked for.
3550 * config.in: Re-generated.
3551 * configure: Re-generated.
3552
3553Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3554
3555 * gencode.c (process_instructions): Call build_endian_shift when
3556 expanding STORE RIGHT, to fix swr.
3557 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3558 clear the high bits.
3559 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3560 Fix float to int conversions to produce signed values.
3561
3562Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3563
3564 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3565 (process_instructions): Correct handling of nor instruction.
3566 Correct shift count for 32 bit shift instructions. Correct sign
3567 extension for arithmetic shifts to not shift the number of bits in
3568 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3569 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3570 Fix madd.
3571 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3572 It's OK to have a mult follow a mult. What's not OK is to have a
3573 mult follow an mfhi.
3574 (Convert): Comment out incorrect rounding code.
3575
3576Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3577
3578 * interp.c (sim_monitor): Improved monitor printf
3579 simulation. Tidied up simulator warnings, and added "--log" option
3580 for directing warning message output.
3581 * gencode.c: Use sim_warning() rather than WARNING macro.
3582
3583Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3584
3585 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3586 getopt1.o, rather than on gencode.c. Link objects together.
3587 Don't link against -liberty.
3588 (gencode.o, getopt.o, getopt1.o): New targets.
3589 * gencode.c: Include <ctype.h> and "ansidecl.h".
3590 (AND): Undefine after including "ansidecl.h".
3591 (ULONG_MAX): Define if not defined.
3592 (OP_*): Don't define macros; now defined in opcode/mips.h.
3593 (main): Call my_strtoul rather than strtoul.
3594 (my_strtoul): New static function.
3595
3596Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3597
3598 * gencode.c (process_instructions): Generate word64 and uword64
3599 instead of `long long' and `unsigned long long' data types.
3600 * interp.c: #include sysdep.h to get signals, and define default
3601 for SIGBUS.
3602 * (Convert): Work around for Visual-C++ compiler bug with type
3603 conversion.
3604 * support.h: Make things compile under Visual-C++ by using
3605 __int64 instead of `long long'. Change many refs to long long
3606 into word64/uword64 typedefs.
3607
3608Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3609
72f4393d
L		 3610 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3611 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3612 (docdir): Removed.
3613 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3614 (AC_PROG_INSTALL): Added.
c906108c 3615 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3616 * configure: Rebuilt.
3617
c906108c
SS		 3618Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3619
3620 * configure.in: Define @SIMCONF@ depending on mips target.
3621 * configure: Rebuild.
3622 * Makefile.in (run): Add @SIMCONF@ to control simulator
3623 construction.
3624 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3625 * interp.c: Remove some debugging, provide more detailed error
3626 messages, update memory accesses to use LOADDRMASK.
72f4393d 3627
c906108c
SS		 3628Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3629
3630 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3631 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3632 stamp-h.
3633 * configure: Rebuild.
3634 * config.in: New file, generated by autoheader.
3635 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3636 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3637 HAVE_ANINT and HAVE_AINT, as appropriate.
3638 * Makefile.in (run): Use @LIBS@ rather than -lm.
3639 (interp.o): Depend upon config.h.
3640 (Makefile): Just rebuild Makefile.
3641 (clean): Remove stamp-h.
3642 (mostlyclean): Make the same as clean, not as distclean.
3643 (config.h, stamp-h): New targets.
3644
3645Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3646
3647 * interp.c (ColdReset): Fix boolean test. Make all simulator
3648 globals static.
3649
3650Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3651
3652 * interp.c (xfer_direct_word, xfer_direct_long,
3653 swap_direct_word, swap_direct_long, xfer_big_word,
3654 xfer_big_long, xfer_little_word, xfer_little_long,
3655 swap_word,swap_long): Added.
3656 * interp.c (ColdReset): Provide function indirection to
3657 host<->simulated_target transfer routines.
3658 * interp.c (sim_store_register, sim_fetch_register): Updated to
3659 make use of indirected transfer routines.
3660
3661Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3662
3663 * gencode.c (process_instructions): Ensure FP ABS instruction
3664 recognised.
3665 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3666 system call support.
3667
3668Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3669
3670 * interp.c (sim_do_command): Complain if callback structure not
3671 initialised.
3672
3673Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3674
3675 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3676 support for Sun hosts.
3677 * Makefile.in (gencode): Ensure the host compiler and libraries
3678 used for cross-hosted build.
3679
3680Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3681
3682 * interp.c, gencode.c: Some more (TODO) tidying.
3683
3684Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3685
3686 * gencode.c, interp.c: Replaced explicit long long references with
3687 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3688 * support.h (SET64LO, SET64HI): Macros added.
3689
3690Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3691
3692 * configure: Regenerate with autoconf 2.7.
3693
3694Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3695
3696 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3697 * support.h: Remove superfluous "1" from #if.
3698 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3699
3700Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3701
3702 * interp.c (StoreFPR): Control UndefinedResult() call on
3703 WARN_RESULT manifest.
3704
3705Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3706
3707 * gencode.c: Tidied instruction decoding, and added FP instruction
3708 support.
3709
3710 * interp.c: Added dineroIII, and BSD profiling support. Also
3711 run-time FP handling.
3712
3713Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3714
3715 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3716 gencode.c, interp.c, support.h: created.
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