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[ARC] [COMMITTED] Fix FASTMATH field.
[thirdparty/binutils-gdb.git] / gas / config / tc-arm.c
CommitLineData
b99bd4ef 1/* tc-arm.c -- Assemble for the ARM
82704155 2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
b99bd4ef
NC		 3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
22d9c8c5 5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
34920d91
NC		 6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
b99bd4ef
NC		 8
9 This file is part of GAS, the GNU Assembler.
10
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
ec2655a6 13 the Free Software Foundation; either version 3, or (at your option)
b99bd4ef
NC		 14 any later version.
15
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
c19d1205 18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
b99bd4ef
NC		 19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
699d2810
NC		 23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 02110-1301, USA. */
b99bd4ef 25
42a68e18 26#include "as.h"
5287ad62 27#include <limits.h>
037e8744 28#include <stdarg.h>
c19d1205 29#define NO_RELOC 0
3882b010 30#include "safe-ctype.h"
b99bd4ef
NC		 31#include "subsegs.h"
32#include "obstack.h"
3da1d841 33#include "libiberty.h"
f263249b
RE		 34#include "opcode/arm.h"
35
b99bd4ef
NC		 36#ifdef OBJ_ELF
37#include "elf/arm.h"
a394c00f 38#include "dw2gencfi.h"
b99bd4ef
NC		 39#endif
40
f0927246
NC		 41#include "dwarf2dbg.h"
42
7ed4c4c5
NC		 43#ifdef OBJ_ELF
44/* Must be at least the size of the largest unwind opcode (currently two). */
45#define ARM_OPCODE_CHUNK_SIZE 8
46
47/* This structure holds the unwinding state. */
48
49static struct
50{
c19d1205
ZW		 51 symbolS * proc_start;
52 symbolS * table_entry;
53 symbolS * personality_routine;
54 int personality_index;
7ed4c4c5 55 /* The segment containing the function. */
c19d1205
ZW		 56 segT saved_seg;
57 subsegT saved_subseg;
7ed4c4c5
NC		 58 /* Opcodes generated from this function. */
59 unsigned char * opcodes;
c19d1205
ZW		 60 int opcode_count;
61 int opcode_alloc;
7ed4c4c5 62 /* The number of bytes pushed to the stack. */
c19d1205 63 offsetT frame_size;
7ed4c4c5
NC		 64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
c19d1205 67 offsetT pending_offset;
7ed4c4c5 68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
c19d1205
ZW		 69 hold the reg+offset to use when restoring sp from a frame pointer. */
70 offsetT fp_offset;
71 int fp_reg;
7ed4c4c5 72 /* Nonzero if an unwind_setfp directive has been seen. */
c19d1205 73 unsigned fp_used:1;
7ed4c4c5 74 /* Nonzero if the last opcode restores sp from fp_reg. */
c19d1205 75 unsigned sp_restored:1;
7ed4c4c5
NC		 76} unwind;
77
18a20338
CL		 78/* Whether --fdpic was given. */
79static int arm_fdpic;
80
8b1ad454
NC		 81#endif /* OBJ_ELF */
82
4962c51a
MS		 83/* Results from operand parsing worker functions. */
84
85typedef enum
86{
87 PARSE_OPERAND_SUCCESS,
88 PARSE_OPERAND_FAIL,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90} parse_operand_result;
91
33a392fb
PB		 92enum arm_float_abi
93{
94 ARM_FLOAT_ABI_HARD,
95 ARM_FLOAT_ABI_SOFTFP,
96 ARM_FLOAT_ABI_SOFT
97};
98
c19d1205 99/* Types of processor to assemble for. */
b99bd4ef 100#ifndef CPU_DEFAULT
8a59fff3 101/* The code that was here used to select a default CPU depending on compiler
fa94de6b 102 pre-defines which were only present when doing native builds, thus
8a59fff3
MGD		 103 changing gas' default behaviour depending upon the build host.
104
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
b99bd4ef
NC		 107#endif
108
109#ifndef FPU_DEFAULT
c820d418
MM		 110# ifdef TE_LINUX
111# define FPU_DEFAULT FPU_ARCH_FPA
112# elif defined (TE_NetBSD)
113# ifdef OBJ_ELF
114# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115# else
116 /* Legacy a.out format. */
117# define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118# endif
4e7fd91e
PB		 119# elif defined (TE_VXWORKS)
120# define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
c820d418
MM		 121# else
122 /* For backwards compatibility, default to FPA. */
123# define FPU_DEFAULT FPU_ARCH_FPA
124# endif
125#endif /* ifndef FPU_DEFAULT */
b99bd4ef 126
c19d1205 127#define streq(a, b) (strcmp (a, b) == 0)
b99bd4ef 128
4d354d8b
TP		 129/* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
e74cfd16 132static arm_feature_set cpu_variant;
4d354d8b
TP		 133/* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
e74cfd16
PB		 135static arm_feature_set arm_arch_used;
136static arm_feature_set thumb_arch_used;
b99bd4ef 137
b99bd4ef 138/* Flags stored in private area of BFD structure. */
c19d1205
ZW		 139static int uses_apcs_26 = FALSE;
140static int atpcs = FALSE;
b34976b6
AM		 141static int support_interwork = FALSE;
142static int uses_apcs_float = FALSE;
c19d1205 143static int pic_code = FALSE;
845b51d6 144static int fix_v4bx = FALSE;
278df34e
NS		 145/* Warn on using deprecated features. */
146static int warn_on_deprecated = TRUE;
147
2e6976a8
DG		 148/* Understand CodeComposer Studio assembly syntax. */
149bfd_boolean codecomposer_syntax = FALSE;
03b1477f
RE		 150
151/* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
153 assembly flags. */
4d354d8b
TP		 154
155/* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157static const arm_feature_set *legacy_cpu = NULL;
158static const arm_feature_set *legacy_fpu = NULL;
159
160/* CPU, extension and FPU feature bits selected by -mcpu. */
161static const arm_feature_set *mcpu_cpu_opt = NULL;
162static arm_feature_set *mcpu_ext_opt = NULL;
163static const arm_feature_set *mcpu_fpu_opt = NULL;
164
165/* CPU, extension and FPU feature bits selected by -march. */
166static const arm_feature_set *march_cpu_opt = NULL;
167static arm_feature_set *march_ext_opt = NULL;
168static const arm_feature_set *march_fpu_opt = NULL;
169
170/* Feature bits selected by -mfpu. */
171static const arm_feature_set *mfpu_opt = NULL;
e74cfd16
PB		 172
173/* Constants for known architecture features. */
174static const arm_feature_set fpu_default = FPU_DEFAULT;
f85d59c3 175static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V1;
e74cfd16 176static const arm_feature_set fpu_arch_vfp_v2 = FPU_ARCH_VFP_V2;
f85d59c3
KT		 177static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED = FPU_ARCH_VFP_V3;
178static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED = FPU_ARCH_NEON_V1;
e74cfd16
PB		 179static const arm_feature_set fpu_arch_fpa = FPU_ARCH_FPA;
180static const arm_feature_set fpu_any_hard = FPU_ANY_HARD;
69c9e028 181#ifdef OBJ_ELF
e74cfd16 182static const arm_feature_set fpu_arch_maverick = FPU_ARCH_MAVERICK;
69c9e028 183#endif
e74cfd16
PB		 184static const arm_feature_set fpu_endian_pure = FPU_ARCH_ENDIAN_PURE;
185
186#ifdef CPU_DEFAULT
187static const arm_feature_set cpu_default = CPU_DEFAULT;
188#endif
189
823d2571 190static const arm_feature_set arm_ext_v1 = ARM_FEATURE_CORE_LOW (ARM_EXT_V1);
4070243b 191static const arm_feature_set arm_ext_v2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V2);
823d2571
TG		 192static const arm_feature_set arm_ext_v2s = ARM_FEATURE_CORE_LOW (ARM_EXT_V2S);
193static const arm_feature_set arm_ext_v3 = ARM_FEATURE_CORE_LOW (ARM_EXT_V3);
194static const arm_feature_set arm_ext_v3m = ARM_FEATURE_CORE_LOW (ARM_EXT_V3M);
195static const arm_feature_set arm_ext_v4 = ARM_FEATURE_CORE_LOW (ARM_EXT_V4);
196static const arm_feature_set arm_ext_v4t = ARM_FEATURE_CORE_LOW (ARM_EXT_V4T);
197static const arm_feature_set arm_ext_v5 = ARM_FEATURE_CORE_LOW (ARM_EXT_V5);
e74cfd16 198static const arm_feature_set arm_ext_v4t_5 =
823d2571
TG		 199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T | ARM_EXT_V5);
200static const arm_feature_set arm_ext_v5t = ARM_FEATURE_CORE_LOW (ARM_EXT_V5T);
201static const arm_feature_set arm_ext_v5e = ARM_FEATURE_CORE_LOW (ARM_EXT_V5E);
202static const arm_feature_set arm_ext_v5exp = ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP);
203static const arm_feature_set arm_ext_v5j = ARM_FEATURE_CORE_LOW (ARM_EXT_V5J);
204static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
205static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
206static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
55e8aae7
SP		 207/* Only for compatability of hint instructions. */
208static const arm_feature_set arm_ext_v6k_v6t2 =
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K | ARM_EXT_V6T2);
823d2571
TG		 210static const arm_feature_set arm_ext_v6_notm =
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
212static const arm_feature_set arm_ext_v6_dsp =
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP);
214static const arm_feature_set arm_ext_barrier =
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER);
216static const arm_feature_set arm_ext_msr =
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR);
218static const arm_feature_set arm_ext_div = ARM_FEATURE_CORE_LOW (ARM_EXT_DIV);
219static const arm_feature_set arm_ext_v7 = ARM_FEATURE_CORE_LOW (ARM_EXT_V7);
220static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
221static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
69c9e028 222#ifdef OBJ_ELF
e7d39ed3 223static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
69c9e028 224#endif
823d2571 225static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
7e806470 226static const arm_feature_set arm_ext_m =
173205ca 227 ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
16a1fa25 228 ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
823d2571
TG		 229static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
230static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
231static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
232static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
233static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
ddfded2f 234static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
4ed7ed8d 235static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
16a1fa25
TP		 236static const arm_feature_set arm_ext_v8m_main =
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
e12437dc
AV		 238static const arm_feature_set arm_ext_v8_1m_main =
239ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
16a1fa25
TP		 240/* Instructions in ARMv8-M only found in M profile architectures. */
241static const arm_feature_set arm_ext_v8m_m_only =
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
ff8646ee
TP		 243static const arm_feature_set arm_ext_v6t2_v8m =
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
4ed7ed8d
TP		 245/* Instructions shared between ARMv8-A and ARMv8-M. */
246static const arm_feature_set arm_ext_atomics =
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS);
69c9e028 248#ifdef OBJ_ELF
15afaa63
TP		 249/* DSP instructions Tag_DSP_extension refers to. */
250static const arm_feature_set arm_ext_dsp =
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E | ARM_EXT_V5ExP | ARM_EXT_V6_DSP);
69c9e028 252#endif
4d1464f2
MW		 253static const arm_feature_set arm_ext_ras =
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS);
b8ec4e87
JW		 255/* FP16 instructions. */
256static const arm_feature_set arm_ext_fp16 =
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
01f48020
TC		 258static const arm_feature_set arm_ext_fp16_fml =
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML);
dec41383
JW		 260static const arm_feature_set arm_ext_v8_2 =
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A);
49e8a725
SN		 262static const arm_feature_set arm_ext_v8_3 =
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
7fadb25d
SD		 264static const arm_feature_set arm_ext_sb =
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB);
dad0c3bf
SD		 266static const arm_feature_set arm_ext_predres =
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES);
e74cfd16
PB		 268
269static const arm_feature_set arm_arch_any = ARM_ANY;
49fa50ef 270#ifdef OBJ_ELF
2c6b98ea 271static const arm_feature_set fpu_any = FPU_ANY;
49fa50ef 272#endif
f85d59c3 273static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
e74cfd16
PB		 274static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
275static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
276
2d447fca 277static const arm_feature_set arm_cext_iwmmxt2 =
823d2571 278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
e74cfd16 279static const arm_feature_set arm_cext_iwmmxt =
823d2571 280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT);
e74cfd16 281static const arm_feature_set arm_cext_xscale =
823d2571 282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE);
e74cfd16 283static const arm_feature_set arm_cext_maverick =
823d2571
TG		 284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK);
285static const arm_feature_set fpu_fpa_ext_v1 =
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1);
287static const arm_feature_set fpu_fpa_ext_v2 =
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2);
e74cfd16 289static const arm_feature_set fpu_vfp_ext_v1xd =
823d2571
TG		 290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD);
291static const arm_feature_set fpu_vfp_ext_v1 =
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1);
293static const arm_feature_set fpu_vfp_ext_v2 =
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2);
295static const arm_feature_set fpu_vfp_ext_v3xd =
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD);
297static const arm_feature_set fpu_vfp_ext_v3 =
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3);
b1cc4aeb 299static const arm_feature_set fpu_vfp_ext_d32 =
823d2571
TG		 300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32);
301static const arm_feature_set fpu_neon_ext_v1 =
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1);
5287ad62 303static const arm_feature_set fpu_vfp_v3_or_neon_ext =
823d2571 304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_VFP_EXT_V3);
a7ad558c
AV		 305static const arm_feature_set mve_ext =
306 ARM_FEATURE_COPROC (FPU_MVE);
307static const arm_feature_set mve_fp_ext =
308 ARM_FEATURE_COPROC (FPU_MVE_FP);
69c9e028 309#ifdef OBJ_ELF
823d2571
TG		 310static const arm_feature_set fpu_vfp_fp16 =
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16);
312static const arm_feature_set fpu_neon_ext_fma =
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA);
69c9e028 314#endif
823d2571
TG		 315static const arm_feature_set fpu_vfp_ext_fma =
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA);
bca38921 317static const arm_feature_set fpu_vfp_ext_armv8 =
823d2571 318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8);
a715796b 319static const arm_feature_set fpu_vfp_ext_armv8xd =
823d2571 320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD);
bca38921 321static const arm_feature_set fpu_neon_ext_armv8 =
823d2571 322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8);
bca38921 323static const arm_feature_set fpu_crypto_ext_armv8 =
823d2571 324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8);
dd5181d5 325static const arm_feature_set crc_ext_armv8 =
823d2571 326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
d6b4b13e 327static const arm_feature_set fpu_neon_ext_v8_1 =
643afb90 328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
c604a79a
JW		 329static const arm_feature_set fpu_neon_ext_dotprod =
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
e74cfd16 331
33a392fb 332static int mfloat_abi_opt = -1;
4d354d8b
TP		 333/* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
334 directive. */
335static arm_feature_set selected_arch = ARM_ARCH_NONE;
336/* Extension feature bits selected by the last -mcpu/-march or .arch_extension
337 directive. */
338static arm_feature_set selected_ext = ARM_ARCH_NONE;
339/* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
341 directive. */
e74cfd16 342static arm_feature_set selected_cpu = ARM_ARCH_NONE;
4d354d8b
TP		 343/* FPU feature bits selected by the last -mfpu or .fpu directive. */
344static arm_feature_set selected_fpu = FPU_NONE;
345/* Feature bits selected by the last .object_arch directive. */
346static arm_feature_set selected_object_arch = ARM_ARCH_NONE;
ee065d83 347/* Must be long enough to hold any of the names in arm_cpus. */
ef8e6722 348static char selected_cpu_name[20];
8d67f500 349
aacf0b33
KT		 350extern FLONUM_TYPE generic_floating_point_number;
351
8d67f500
NC		 352/* Return if no cpu was selected on command-line. */
353static bfd_boolean
354no_cpu_selected (void)
355{
823d2571 356 return ARM_FEATURE_EQUAL (selected_cpu, arm_arch_none);
8d67f500
NC		 357}
358
7cc69913 359#ifdef OBJ_ELF
deeaaff8
DJ		 360# ifdef EABI_DEFAULT
361static int meabi_flags = EABI_DEFAULT;
362# else
d507cf36 363static int meabi_flags = EF_ARM_EABI_UNKNOWN;
deeaaff8 364# endif
e1da3f5b 365
ee3c0378
AS		 366static int attributes_set_explicitly[NUM_KNOWN_OBJ_ATTRIBUTES];
367
e1da3f5b 368bfd_boolean
5f4273c7 369arm_is_eabi (void)
e1da3f5b
PB		 370{
371 return (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4);
372}
7cc69913 373#endif
b99bd4ef 374
b99bd4ef 375#ifdef OBJ_ELF
c19d1205 376/* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
b99bd4ef
NC		 377symbolS * GOT_symbol;
378#endif
379
b99bd4ef
NC		 380/* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
383 instructions. */
384static int thumb_mode = 0;
8dc2430f
NC		 385/* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388#define MODE_RECORDED (1 << 4)
b99bd4ef 389
e07e6e58
NC		 390/* Specifies the intrinsic IT insn behavior mode. */
391enum implicit_it_mode
392{
393 IMPLICIT_IT_MODE_NEVER = 0x00,
394 IMPLICIT_IT_MODE_ARM = 0x01,
395 IMPLICIT_IT_MODE_THUMB = 0x02,
396 IMPLICIT_IT_MODE_ALWAYS = (IMPLICIT_IT_MODE_ARM | IMPLICIT_IT_MODE_THUMB)
397};
398static int implicit_it_mode = IMPLICIT_IT_MODE_ARM;
399
c19d1205
ZW		 400/* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
402
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
407 there.)
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
410 machine code.
411
412 Important differences from the old Thumb mode:
413
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
422
423static bfd_boolean unified_syntax = FALSE;
b99bd4ef 424
bacebabc
RM		 425/* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
477330fc
RM		 427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429const char arm_symbol_chars[] = "#[]{}";
bacebabc 430
5287ad62
JB		 431enum neon_el_type
432{
dcbf9037 433 NT_invtype,
5287ad62
JB		 434 NT_untyped,
435 NT_integer,
436 NT_float,
437 NT_poly,
438 NT_signed,
dcbf9037 439 NT_unsigned
5287ad62
JB		 440};
441
442struct neon_type_el
443{
444 enum neon_el_type type;
445 unsigned size;
446};
447
448#define NEON_MAX_TYPE_ELS 4
449
450struct neon_type
451{
452 struct neon_type_el el[NEON_MAX_TYPE_ELS];
453 unsigned elems;
454};
455
5ee91343 456enum pred_instruction_type
e07e6e58 457{
5ee91343
AV		 458 OUTSIDE_PRED_INSN,
459 INSIDE_VPT_INSN,
e07e6e58
NC		 460 INSIDE_IT_INSN,
461 INSIDE_IT_LAST_INSN,
462 IF_INSIDE_IT_LAST_INSN, /* Either outside or inside;
477330fc 463 if inside, should be the last one. */
e07e6e58 464 NEUTRAL_IT_INSN, /* This could be either inside or outside,
477330fc 465 i.e. BKPT and NOP. */
5ee91343
AV		 466 IT_INSN, /* The IT insn has been parsed. */
467 VPT_INSN, /* The VPT/VPST insn has been parsed. */
35c228db 468 MVE_OUTSIDE_PRED_INSN , /* Instruction to indicate a MVE instruction without
5ee91343 469 a predication code. */
35c228db 470 MVE_UNPREDICABLE_INSN /* MVE instruction that is non-predicable. */
e07e6e58
NC		 471};
472
ad6cec43
MGD		 473/* The maximum number of operands we need. */
474#define ARM_IT_MAX_OPERANDS 6
e2b0ab59 475#define ARM_IT_MAX_RELOCS 3
ad6cec43 476
b99bd4ef
NC		 477struct arm_it
478{
c19d1205 479 const char * error;
b99bd4ef 480 unsigned long instruction;
c19d1205
ZW		 481 int size;
482 int size_req;
483 int cond;
037e8744
JB		 484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
486 appropriate. */
487 int uncond_value;
5287ad62 488 struct neon_type vectype;
88714cb8
DG		 489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
491 int is_neon;
0110f2b8
PB		 492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
494 unsigned long relax;
b99bd4ef
NC		 495 struct
496 {
497 bfd_reloc_code_real_type type;
c19d1205
ZW		 498 expressionS exp;
499 int pc_rel;
e2b0ab59 500 } relocs[ARM_IT_MAX_RELOCS];
b99bd4ef 501
5ee91343 502 enum pred_instruction_type pred_insn_type;
e07e6e58 503
c19d1205
ZW		 504 struct
505 {
506 unsigned reg;
ca3f61f7 507 signed int imm;
dcbf9037 508 struct neon_type_el vectype;
ca3f61f7
NC		 509 unsigned present : 1; /* Operand present. */
510 unsigned isreg : 1; /* Operand was a register. */
f5f10c66
AV		 511 unsigned immisreg : 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
57785aa2
AV		 513 unsigned isscalar : 2; /* Operand is a (SIMD) scalar:
514 0) not scalar,
515 1) Neon scalar,
516 2) MVE scalar. */
5287ad62 517 unsigned immisalign : 1; /* Immediate is an alignment specifier. */
c96612cc 518 unsigned immisfloat : 1; /* Immediate was parsed as a float. */
5287ad62
JB		 519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm : 1; /* 64-bit immediate, reg forms high 32 bits. */
037e8744 522 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
5ee91343 523 unsigned isquad : 1; /* Operand is SIMD quad register. */
037e8744 524 unsigned issingle : 1; /* Operand is VFP single-precision register. */
1b883319 525 unsigned iszr : 1; /* Operand is ZR register. */
ca3f61f7
NC		 526 unsigned hasreloc : 1; /* Operand has relocation suffix. */
527 unsigned writeback : 1; /* Operand has trailing ! */
528 unsigned preind : 1; /* Preindexed address. */
529 unsigned postind : 1; /* Postindexed address. */
530 unsigned negative : 1; /* Index register was negated. */
531 unsigned shifted : 1; /* Shift applied to operation. */
532 unsigned shift_kind : 3; /* Shift operation (enum shift_kind). */
ad6cec43 533 } operands[ARM_IT_MAX_OPERANDS];
b99bd4ef
NC		 534};
535
c19d1205 536static struct arm_it inst;
b99bd4ef
NC		 537
538#define NUM_FLOAT_VALS 8
539
05d2d07e 540const char * fp_const[] =
b99bd4ef
NC		 541{
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
543};
544
b99bd4ef
NC		 545LITTLENUM_TYPE fp_values[NUM_FLOAT_VALS][MAX_LITTLENUMS];
546
547#define FAIL (-1)
548#define SUCCESS (0)
549
550#define SUFF_S 1
551#define SUFF_D 2
552#define SUFF_E 3
553#define SUFF_P 4
554
c19d1205
ZW		 555#define CP_T_X 0x00008000
556#define CP_T_Y 0x00400000
b99bd4ef 557
c19d1205
ZW		 558#define CONDS_BIT 0x00100000
559#define LOAD_BIT 0x00100000
b99bd4ef
NC		 560
561#define DOUBLE_LOAD_FLAG 0x00000001
562
563struct asm_cond
564{
d3ce72d0 565 const char * template_name;
c921be7d 566 unsigned long value;
b99bd4ef
NC		 567};
568
c19d1205 569#define COND_ALWAYS 0xE
b99bd4ef 570
b99bd4ef
NC		 571struct asm_psr
572{
d3ce72d0 573 const char * template_name;
c921be7d 574 unsigned long field;
b99bd4ef
NC		 575};
576
62b3e311
PB		 577struct asm_barrier_opt
578{
e797f7e0
MGD		 579 const char * template_name;
580 unsigned long value;
581 const arm_feature_set arch;
62b3e311
PB		 582};
583
2d2255b5 584/* The bit that distinguishes CPSR and SPSR. */
b99bd4ef
NC		 585#define SPSR_BIT (1 << 22)
586
c19d1205
ZW		 587/* The individual PSR flag bits. */
588#define PSR_c (1 << 16)
589#define PSR_x (1 << 17)
590#define PSR_s (1 << 18)
591#define PSR_f (1 << 19)
b99bd4ef 592
c19d1205 593struct reloc_entry
bfae80f2 594{
0198d5e6 595 const char * name;
c921be7d 596 bfd_reloc_code_real_type reloc;
bfae80f2
RE		 597};
598
5287ad62 599enum vfp_reg_pos
bfae80f2 600{
5287ad62
JB		 601 VFP_REG_Sd, VFP_REG_Sm, VFP_REG_Sn,
602 VFP_REG_Dd, VFP_REG_Dm, VFP_REG_Dn
bfae80f2
RE		 603};
604
605enum vfp_ldstm_type
606{
607 VFP_LDSTMIA, VFP_LDSTMDB, VFP_LDSTMIAX, VFP_LDSTMDBX
608};
609
dcbf9037
JB		 610/* Bits for DEFINED field in neon_typed_alias. */
611#define NTA_HASTYPE 1
612#define NTA_HASINDEX 2
613
614struct neon_typed_alias
615{
c921be7d
NC		 616 unsigned char defined;
617 unsigned char index;
618 struct neon_type_el eltype;
dcbf9037
JB		 619};
620
c19d1205 621/* ARM register categories. This includes coprocessor numbers and various
5aa75429
TP		 622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
c19d1205 624enum arm_reg_type
bfae80f2 625{
c19d1205
ZW		 626 REG_TYPE_RN,
627 REG_TYPE_CP,
628 REG_TYPE_CN,
629 REG_TYPE_FN,
630 REG_TYPE_VFS,
631 REG_TYPE_VFD,
5287ad62 632 REG_TYPE_NQ,
037e8744 633 REG_TYPE_VFSD,
5287ad62 634 REG_TYPE_NDQ,
dec41383 635 REG_TYPE_NSD,
037e8744 636 REG_TYPE_NSDQ,
c19d1205
ZW		 637 REG_TYPE_VFC,
638 REG_TYPE_MVF,
639 REG_TYPE_MVD,
640 REG_TYPE_MVFX,
641 REG_TYPE_MVDX,
642 REG_TYPE_MVAX,
5ee91343 643 REG_TYPE_MQ,
c19d1205
ZW		 644 REG_TYPE_DSPSC,
645 REG_TYPE_MMXWR,
646 REG_TYPE_MMXWC,
647 REG_TYPE_MMXWCG,
648 REG_TYPE_XSCALE,
5ee91343 649 REG_TYPE_RNB,
1b883319 650 REG_TYPE_ZR
bfae80f2
RE		 651};
652
dcbf9037
JB		 653/* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
6c43fab6
RE		 657struct reg_entry
658{
c921be7d 659 const char * name;
90ec0d68 660 unsigned int number;
c921be7d
NC		 661 unsigned char type;
662 unsigned char builtin;
663 struct neon_typed_alias * neon;
6c43fab6
RE		 664};
665
c19d1205 666/* Diagnostics used when we don't get a register of the expected type. */
c921be7d 667const char * const reg_expected_msgs[] =
c19d1205 668{
5aa75429
TP		 669 [REG_TYPE_RN] = N_("ARM register expected"),
670 [REG_TYPE_CP] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN] = N_("co-processor register expected"),
672 [REG_TYPE_FN] = N_("FPA register expected"),
673 [REG_TYPE_VFS] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ] = N_("VFP single, double or Neon quad precision register"
680 " expected"),
681 [REG_TYPE_VFC] = N_("VFP system register expected"),
682 [REG_TYPE_MVF] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE] = N_("XScale accumulator register expected"),
5ee91343 692 [REG_TYPE_MQ] = N_("MVE vector register expected"),
5aa75429 693 [REG_TYPE_RNB] = N_("")
6c43fab6
RE		 694};
695
c19d1205 696/* Some well known registers that we refer to directly elsewhere. */
bd340a04 697#define REG_R12 12
c19d1205
ZW		 698#define REG_SP 13
699#define REG_LR 14
700#define REG_PC 15
404ff6b5 701
b99bd4ef
NC		 702/* ARM instructions take 4bytes in the object file, Thumb instructions
703 take 2: */
c19d1205 704#define INSN_SIZE 4
b99bd4ef
NC		 705
706struct asm_opcode
707{
708 /* Basic string to match. */
d3ce72d0 709 const char * template_name;
c19d1205
ZW		 710
711 /* Parameters to instruction. */
5be8be5d 712 unsigned int operands[8];
c19d1205
ZW		 713
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag : 4;
b99bd4ef
NC		 716
717 /* Basic instruction code. */
a302e574 718 unsigned int avalue;
b99bd4ef 719
c19d1205
ZW		 720 /* Thumb-format instruction code. */
721 unsigned int tvalue;
b99bd4ef 722
90e4755a 723 /* Which architecture variant provides this instruction. */
c921be7d
NC		 724 const arm_feature_set * avariant;
725 const arm_feature_set * tvariant;
c19d1205
ZW		 726
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode) (void);
b99bd4ef 729
c19d1205
ZW		 730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode) (void);
5ee91343
AV		 732
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred : 1;
b99bd4ef
NC		 735};
736
a737bd4d
NC		 737/* Defines for various bits that we will want to toggle. */
738#define INST_IMMEDIATE 0x02000000
739#define OFFSET_REG 0x02000000
c19d1205 740#define HWOFFSET_IMM 0x00400000
a737bd4d
NC		 741#define SHIFT_BY_REG 0x00000010
742#define PRE_INDEX 0x01000000
743#define INDEX_UP 0x00800000
744#define WRITE_BACK 0x00200000
745#define LDM_TYPE_2_OR_3 0x00400000
a028a6f5 746#define CPSI_MMOD 0x00020000
90e4755a 747
a737bd4d
NC		 748#define LITERAL_MASK 0xf000f000
749#define OPCODE_MASK 0xfe1fffff
750#define V4_STR_BIT 0x00000020
8335d6aa 751#define VLDR_VMOV_SAME 0x0040f000
90e4755a 752
efd81785
PB		 753#define T2_SUBS_PC_LR 0xf3de8f00
754
a737bd4d 755#define DATA_OP_SHIFT 21
bada4342 756#define SBIT_SHIFT 20
90e4755a 757
ef8d22e6
PB		 758#define T2_OPCODE_MASK 0xfe1fffff
759#define T2_DATA_OP_SHIFT 21
bada4342 760#define T2_SBIT_SHIFT 20
ef8d22e6 761
6530b175
NC		 762#define A_COND_MASK 0xf0000000
763#define A_PUSH_POP_OP_MASK 0x0fff0000
764
765/* Opcodes for pushing/poping registers to/from the stack. */
766#define A1_OPCODE_PUSH 0x092d0000
767#define A2_OPCODE_PUSH 0x052d0004
768#define A2_OPCODE_POP 0x049d0004
769
a737bd4d
NC		 770/* Codes to distinguish the arithmetic instructions. */
771#define OPCODE_AND 0
772#define OPCODE_EOR 1
773#define OPCODE_SUB 2
774#define OPCODE_RSB 3
775#define OPCODE_ADD 4
776#define OPCODE_ADC 5
777#define OPCODE_SBC 6
778#define OPCODE_RSC 7
779#define OPCODE_TST 8
780#define OPCODE_TEQ 9
781#define OPCODE_CMP 10
782#define OPCODE_CMN 11
783#define OPCODE_ORR 12
784#define OPCODE_MOV 13
785#define OPCODE_BIC 14
786#define OPCODE_MVN 15
90e4755a 787
ef8d22e6
PB		 788#define T2_OPCODE_AND 0
789#define T2_OPCODE_BIC 1
790#define T2_OPCODE_ORR 2
791#define T2_OPCODE_ORN 3
792#define T2_OPCODE_EOR 4
793#define T2_OPCODE_ADD 8
794#define T2_OPCODE_ADC 10
795#define T2_OPCODE_SBC 11
796#define T2_OPCODE_SUB 13
797#define T2_OPCODE_RSB 14
798
a737bd4d
NC		 799#define T_OPCODE_MUL 0x4340
800#define T_OPCODE_TST 0x4200
801#define T_OPCODE_CMN 0x42c0
802#define T_OPCODE_NEG 0x4240
803#define T_OPCODE_MVN 0x43c0
90e4755a 804
a737bd4d
NC		 805#define T_OPCODE_ADD_R3 0x1800
806#define T_OPCODE_SUB_R3 0x1a00
807#define T_OPCODE_ADD_HI 0x4400
808#define T_OPCODE_ADD_ST 0xb000
809#define T_OPCODE_SUB_ST 0xb080
810#define T_OPCODE_ADD_SP 0xa800
811#define T_OPCODE_ADD_PC 0xa000
812#define T_OPCODE_ADD_I8 0x3000
813#define T_OPCODE_SUB_I8 0x3800
814#define T_OPCODE_ADD_I3 0x1c00
815#define T_OPCODE_SUB_I3 0x1e00
b99bd4ef 816
a737bd4d
NC		 817#define T_OPCODE_ASR_R 0x4100
818#define T_OPCODE_LSL_R 0x4080
c19d1205
ZW		 819#define T_OPCODE_LSR_R 0x40c0
820#define T_OPCODE_ROR_R 0x41c0
a737bd4d
NC		 821#define T_OPCODE_ASR_I 0x1000
822#define T_OPCODE_LSL_I 0x0000
823#define T_OPCODE_LSR_I 0x0800
b99bd4ef 824
a737bd4d
NC		 825#define T_OPCODE_MOV_I8 0x2000
826#define T_OPCODE_CMP_I8 0x2800
827#define T_OPCODE_CMP_LR 0x4280
828#define T_OPCODE_MOV_HR 0x4600
829#define T_OPCODE_CMP_HR 0x4500
b99bd4ef 830
a737bd4d
NC		 831#define T_OPCODE_LDR_PC 0x4800
832#define T_OPCODE_LDR_SP 0x9800
833#define T_OPCODE_STR_SP 0x9000
834#define T_OPCODE_LDR_IW 0x6800
835#define T_OPCODE_STR_IW 0x6000
836#define T_OPCODE_LDR_IH 0x8800
837#define T_OPCODE_STR_IH 0x8000
838#define T_OPCODE_LDR_IB 0x7800
839#define T_OPCODE_STR_IB 0x7000
840#define T_OPCODE_LDR_RW 0x5800
841#define T_OPCODE_STR_RW 0x5000
842#define T_OPCODE_LDR_RH 0x5a00
843#define T_OPCODE_STR_RH 0x5200
844#define T_OPCODE_LDR_RB 0x5c00
845#define T_OPCODE_STR_RB 0x5400
c9b604bd 846
a737bd4d
NC		 847#define T_OPCODE_PUSH 0xb400
848#define T_OPCODE_POP 0xbc00
b99bd4ef 849
2fc8bdac 850#define T_OPCODE_BRANCH 0xe000
b99bd4ef 851
a737bd4d 852#define THUMB_SIZE 2 /* Size of thumb instruction. */
a737bd4d 853#define THUMB_PP_PC_LR 0x0100
c19d1205 854#define THUMB_LOAD_BIT 0x0800
53365c0d 855#define THUMB2_LOAD_BIT 0x00100000
c19d1205 856
5ee91343 857#define BAD_SYNTAX _("syntax error")
c19d1205 858#define BAD_ARGS _("bad arguments to instruction")
fdfde340 859#define BAD_SP _("r13 not allowed here")
c19d1205 860#define BAD_PC _("r15 not allowed here")
a302e574
AV		 861#define BAD_ODD _("Odd register not allowed here")
862#define BAD_EVEN _("Even register not allowed here")
c19d1205
ZW		 863#define BAD_COND _("instruction cannot be conditional")
864#define BAD_OVERLAP _("registers may not be the same")
865#define BAD_HIREG _("lo register required")
866#define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
35c228db 867#define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
dfa9f0d5 868#define BAD_BRANCH _("branch must be last instruction in IT block")
e12437dc 869#define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
dfa9f0d5 870#define BAD_NOT_IT _("instruction not allowed in IT block")
5ee91343 871#define BAD_NOT_VPT _("instruction missing MVE vector predication code")
037e8744 872#define BAD_FPU _("selected FPU does not support instruction")
e07e6e58 873#define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
5ee91343
AV		 874#define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
e07e6e58 876#define BAD_IT_COND _("incorrect condition in IT block")
5ee91343 877#define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
e07e6e58 878#define BAD_IT_IT _("IT falling in the range of a previous IT block")
921e5f0a 879#define MISSING_FNSTART _("missing .fnstart before unwinding directive")
5be8be5d
DG		 880#define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882#define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
9db2f6b4
RL		 884#define BAD_RANGE _("branch out of range")
885#define BAD_FP16 _("selected processor does not support fp16 instruction")
dd5181d5 886#define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
a9f02af8 887#define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
5ee91343
AV		 888#define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
889 "block")
890#define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
891 "block")
892#define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
893 " operand")
894#define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
895 " operand")
a302e574 896#define BAD_SIMD_TYPE _("bad type in SIMD instruction")
886e1c73
AV		 897#define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900#define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
35c228db 902#define BAD_EL_TYPE _("bad element type for instruction")
1b883319 903#define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
c19d1205 904
c921be7d
NC		 905static struct hash_control * arm_ops_hsh;
906static struct hash_control * arm_cond_hsh;
5ee91343 907static struct hash_control * arm_vcond_hsh;
c921be7d
NC		 908static struct hash_control * arm_shift_hsh;
909static struct hash_control * arm_psr_hsh;
910static struct hash_control * arm_v7m_psr_hsh;
911static struct hash_control * arm_reg_hsh;
912static struct hash_control * arm_reloc_hsh;
913static struct hash_control * arm_barrier_opt_hsh;
b99bd4ef 914
b99bd4ef
NC		 915/* Stuff needed to resolve the label ambiguity
916 As:
917 ...
918 label: <insn>
919 may differ from:
920 ...
921 label:
5f4273c7 922 <insn> */
b99bd4ef
NC		 923
924symbolS * last_label_seen;
b34976b6 925static int label_is_thumb_function_name = FALSE;
e07e6e58 926
3d0c9500
NC		 927/* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
a737bd4d 929
c19d1205 930#define MAX_LITERAL_POOL_SIZE 1024
3d0c9500 931typedef struct literal_pool
b99bd4ef 932{
c921be7d
NC		 933 expressionS literals [MAX_LITERAL_POOL_SIZE];
934 unsigned int next_free_entry;
935 unsigned int id;
936 symbolS * symbol;
937 segT section;
938 subsegT sub_section;
a8040cf2
NC		 939#ifdef OBJ_ELF
940 struct dwarf2_line_info locs [MAX_LITERAL_POOL_SIZE];
941#endif
c921be7d 942 struct literal_pool * next;
8335d6aa 943 unsigned int alignment;
3d0c9500 944} literal_pool;
b99bd4ef 945
3d0c9500
NC		 946/* Pointer to a linked list of literal pools. */
947literal_pool * list_of_pools = NULL;
e27ec89e 948
2e6976a8
DG		 949typedef enum asmfunc_states
950{
951 OUTSIDE_ASMFUNC,
952 WAITING_ASMFUNC_NAME,
953 WAITING_ENDASMFUNC
954} asmfunc_states;
955
956static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC;
957
e07e6e58 958#ifdef OBJ_ELF
5ee91343 959# define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
e07e6e58 960#else
5ee91343 961static struct current_pred now_pred;
e07e6e58
NC		 962#endif
963
964static inline int
5ee91343 965now_pred_compatible (int cond)
e07e6e58 966{
5ee91343 967 return (cond & ~1) == (now_pred.cc & ~1);
e07e6e58
NC		 968}
969
970static inline int
971conditional_insn (void)
972{
973 return inst.cond != COND_ALWAYS;
974}
975
5ee91343 976static int in_pred_block (void);
e07e6e58 977
5ee91343 978static int handle_pred_state (void);
e07e6e58
NC		 979
980static void force_automatic_it_block_close (void);
981
c921be7d
NC		 982static void it_fsm_post_encode (void);
983
5ee91343 984#define set_pred_insn_type(type) \
e07e6e58
NC		 985 do \
986 { \
5ee91343
AV		 987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
477330fc 989 return; \
e07e6e58
NC		 990 } \
991 while (0)
992
5ee91343 993#define set_pred_insn_type_nonvoid(type, failret) \
c921be7d
NC		 994 do \
995 { \
5ee91343
AV		 996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
477330fc 998 return failret; \
c921be7d
NC		 999 } \
1000 while(0)
1001
5ee91343 1002#define set_pred_insn_type_last() \
e07e6e58
NC		 1003 do \
1004 { \
1005 if (inst.cond == COND_ALWAYS) \
5ee91343 1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
e07e6e58 1007 else \
5ee91343 1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
e07e6e58
NC		 1009 } \
1010 while (0)
1011
e39c1607
SD		 1012/* Toggle value[pos]. */
1013#define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1014
c19d1205 1015/* Pure syntax. */
b99bd4ef 1016
c19d1205
ZW		 1017/* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
2e6976a8 1019char arm_comment_chars[] = "@";
3d0c9500 1020
c19d1205
ZW		 1021/* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024/* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027/* Also note that comments like this one will always work. */
1028const char line_comment_chars[] = "#";
3d0c9500 1029
2e6976a8 1030char arm_line_separator_chars[] = ";";
b99bd4ef 1031
c19d1205
ZW		 1032/* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034const char EXP_CHARS[] = "eE";
3d0c9500 1035
c19d1205
ZW		 1036/* Chars that mean this number is a floating point constant. */
1037/* As in 0f12.456 */
1038/* or 0d1.2345e12 */
b99bd4ef 1039
5312fe52 1040const char FLT_CHARS[] = "rRsSfFdDxXeEpPHh";
3d0c9500 1041
c19d1205
ZW		 1042/* Prefix characters that indicate the start of an immediate
1043 value. */
1044#define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
3d0c9500 1045
c19d1205
ZW		 1046/* Separator character handling. */
1047
1048#define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1049
5312fe52
BW		 1050enum fp_16bit_format
1051{
1052 ARM_FP16_FORMAT_IEEE = 0x1,
1053 ARM_FP16_FORMAT_ALTERNATIVE = 0x2,
1054 ARM_FP16_FORMAT_DEFAULT = 0x3
1055};
1056
1057static enum fp_16bit_format fp16_format = ARM_FP16_FORMAT_DEFAULT;
1058
1059
c19d1205
ZW		 1060static inline int
1061skip_past_char (char ** str, char c)
1062{
8ab8155f
NC		 1063 /* PR gas/14987: Allow for whitespace before the expected character. */
1064 skip_whitespace (*str);
427d0db6 1065
c19d1205
ZW		 1066 if (**str == c)
1067 {
1068 (*str)++;
1069 return SUCCESS;
3d0c9500 1070 }
c19d1205
ZW		 1071 else
1072 return FAIL;
1073}
c921be7d 1074
c19d1205 1075#define skip_past_comma(str) skip_past_char (str, ',')
3d0c9500 1076
c19d1205
ZW		 1077/* Arithmetic expressions (possibly involving symbols). */
1078
1079/* Return TRUE if anything in the expression is a bignum. */
1080
0198d5e6 1081static bfd_boolean
c19d1205
ZW		 1082walk_no_bignums (symbolS * sp)
1083{
1084 if (symbol_get_value_expression (sp)->X_op == O_big)
0198d5e6 1085 return TRUE;
c19d1205
ZW		 1086
1087 if (symbol_get_value_expression (sp)->X_add_symbol)
3d0c9500 1088 {
c19d1205
ZW		 1089 return (walk_no_bignums (symbol_get_value_expression (sp)->X_add_symbol)
1090 || (symbol_get_value_expression (sp)->X_op_symbol
1091 && walk_no_bignums (symbol_get_value_expression (sp)->X_op_symbol)));
3d0c9500
NC		 1092 }
1093
0198d5e6 1094 return FALSE;
3d0c9500
NC		 1095}
1096
0198d5e6 1097static bfd_boolean in_my_get_expression = FALSE;
c19d1205
ZW		 1098
1099/* Third argument to my_get_expression. */
1100#define GE_NO_PREFIX 0
1101#define GE_IMM_PREFIX 1
1102#define GE_OPT_PREFIX 2
5287ad62
JB		 1103/* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1104 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1105#define GE_OPT_PREFIX_BIG 3
a737bd4d 1106
b99bd4ef 1107static int
c19d1205 1108my_get_expression (expressionS * ep, char ** str, int prefix_mode)
b99bd4ef 1109{
c19d1205 1110 char * save_in;
b99bd4ef 1111
c19d1205
ZW		 1112 /* In unified syntax, all prefixes are optional. */
1113 if (unified_syntax)
5287ad62 1114 prefix_mode = (prefix_mode == GE_OPT_PREFIX_BIG) ? prefix_mode
477330fc 1115 : GE_OPT_PREFIX;
b99bd4ef 1116
c19d1205 1117 switch (prefix_mode)
b99bd4ef 1118 {
c19d1205
ZW		 1119 case GE_NO_PREFIX: break;
1120 case GE_IMM_PREFIX:
1121 if (!is_immediate_prefix (**str))
1122 {
1123 inst.error = _("immediate expression requires a # prefix");
1124 return FAIL;
1125 }
1126 (*str)++;
1127 break;
1128 case GE_OPT_PREFIX:
5287ad62 1129 case GE_OPT_PREFIX_BIG:
c19d1205
ZW		 1130 if (is_immediate_prefix (**str))
1131 (*str)++;
1132 break;
0198d5e6
TC		 1133 default:
1134 abort ();
c19d1205 1135 }
b99bd4ef 1136
c19d1205 1137 memset (ep, 0, sizeof (expressionS));
b99bd4ef 1138
c19d1205
ZW		 1139 save_in = input_line_pointer;
1140 input_line_pointer = *str;
0198d5e6 1141 in_my_get_expression = TRUE;
2ac93be7 1142 expression (ep);
0198d5e6 1143 in_my_get_expression = FALSE;
c19d1205 1144
f86adc07 1145 if (ep->X_op == O_illegal || ep->X_op == O_absent)
b99bd4ef 1146 {
f86adc07 1147 /* We found a bad or missing expression in md_operand(). */
c19d1205
ZW		 1148 *str = input_line_pointer;
1149 input_line_pointer = save_in;
1150 if (inst.error == NULL)
f86adc07
NS		 1151 inst.error = (ep->X_op == O_absent
1152 ? _("missing expression") :_("bad expression"));
c19d1205
ZW		 1153 return 1;
1154 }
b99bd4ef 1155
c19d1205
ZW		 1156 /* Get rid of any bignums now, so that we don't generate an error for which
1157 we can't establish a line number later on. Big numbers are never valid
1158 in instructions, which is where this routine is always called. */
5287ad62
JB		 1159 if (prefix_mode != GE_OPT_PREFIX_BIG
1160 && (ep->X_op == O_big
477330fc 1161 || (ep->X_add_symbol
5287ad62 1162 && (walk_no_bignums (ep->X_add_symbol)
477330fc 1163 || (ep->X_op_symbol
5287ad62 1164 && walk_no_bignums (ep->X_op_symbol))))))
c19d1205
ZW		 1165 {
1166 inst.error = _("invalid constant");
1167 *str = input_line_pointer;
1168 input_line_pointer = save_in;
1169 return 1;
1170 }
b99bd4ef 1171
c19d1205
ZW		 1172 *str = input_line_pointer;
1173 input_line_pointer = save_in;
0198d5e6 1174 return SUCCESS;
b99bd4ef
NC		 1175}
1176
c19d1205
ZW		 1177/* Turn a string in input_line_pointer into a floating point constant
1178 of type TYPE, and store the appropriate bytes in *LITP. The number
1179 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1180 returned, or NULL on OK.
b99bd4ef 1181
c19d1205
ZW		 1182 Note that fp constants aren't represent in the normal way on the ARM.
1183 In big endian mode, things are as expected. However, in little endian
1184 mode fp constants are big-endian word-wise, and little-endian byte-wise
1185 within the words. For example, (double) 1.1 in big endian mode is
1186 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1187 the byte sequence 99 99 f1 3f 9a 99 99 99.
b99bd4ef 1188
c19d1205 1189 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
b99bd4ef 1190
6d4af3c2 1191const char *
c19d1205
ZW		 1192md_atof (int type, char * litP, int * sizeP)
1193{
1194 int prec;
1195 LITTLENUM_TYPE words[MAX_LITTLENUMS];
1196 char *t;
1197 int i;
b99bd4ef 1198
c19d1205
ZW		 1199 switch (type)
1200 {
5312fe52
BW		 1201 case 'H':
1202 case 'h':
1203 prec = 1;
1204 break;
1205
c19d1205
ZW		 1206 case 'f':
1207 case 'F':
1208 case 's':
1209 case 'S':
1210 prec = 2;
1211 break;
b99bd4ef 1212
c19d1205
ZW		 1213 case 'd':
1214 case 'D':
1215 case 'r':
1216 case 'R':
1217 prec = 4;
1218 break;
b99bd4ef 1219
c19d1205
ZW		 1220 case 'x':
1221 case 'X':
499ac353 1222 prec = 5;
c19d1205 1223 break;
b99bd4ef 1224
c19d1205
ZW		 1225 case 'p':
1226 case 'P':
499ac353 1227 prec = 5;
c19d1205 1228 break;
a737bd4d 1229
c19d1205
ZW		 1230 default:
1231 *sizeP = 0;
499ac353 1232 return _("Unrecognized or unsupported floating point constant");
c19d1205 1233 }
b99bd4ef 1234
c19d1205
ZW		 1235 t = atof_ieee (input_line_pointer, type, words);
1236 if (t)
1237 input_line_pointer = t;
499ac353 1238 *sizeP = prec * sizeof (LITTLENUM_TYPE);
b99bd4ef 1239
72c03e30
BW		 1240 if (target_big_endian || prec == 1)
1241 for (i = 0; i < prec; i++)
1242 {
1243 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1244 litP += sizeof (LITTLENUM_TYPE);
1245 }
1246 else if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
1247 for (i = prec - 1; i >= 0; i--)
1248 {
1249 md_number_to_chars (litP, (valueT) words[i], sizeof (LITTLENUM_TYPE));
1250 litP += sizeof (LITTLENUM_TYPE);
1251 }
c19d1205 1252 else
72c03e30
BW		 1253 /* For a 4 byte float the order of elements in `words' is 1 0.
1254 For an 8 byte float the order is 1 0 3 2. */
1255 for (i = 0; i < prec; i += 2)
1256 {
1257 md_number_to_chars (litP, (valueT) words[i + 1],
1258 sizeof (LITTLENUM_TYPE));
1259 md_number_to_chars (litP + sizeof (LITTLENUM_TYPE),
1260 (valueT) words[i], sizeof (LITTLENUM_TYPE));
1261 litP += 2 * sizeof (LITTLENUM_TYPE);
1262 }
b99bd4ef 1263
499ac353 1264 return NULL;
c19d1205 1265}
b99bd4ef 1266
c19d1205
ZW		 1267/* We handle all bad expressions here, so that we can report the faulty
1268 instruction in the error message. */
0198d5e6 1269
c19d1205 1270void
91d6fa6a 1271md_operand (expressionS * exp)
c19d1205
ZW		 1272{
1273 if (in_my_get_expression)
91d6fa6a 1274 exp->X_op = O_illegal;
b99bd4ef
NC		 1275}
1276
c19d1205 1277/* Immediate values. */
b99bd4ef 1278
0198d5e6 1279#ifdef OBJ_ELF
c19d1205
ZW		 1280/* Generic immediate-value read function for use in directives.
1281 Accepts anything that 'expression' can fold to a constant.
1282 *val receives the number. */
0198d5e6 1283
c19d1205
ZW		 1284static int
1285immediate_for_directive (int *val)
b99bd4ef 1286{
c19d1205
ZW		 1287 expressionS exp;
1288 exp.X_op = O_illegal;
b99bd4ef 1289
c19d1205
ZW		 1290 if (is_immediate_prefix (*input_line_pointer))
1291 {
1292 input_line_pointer++;
1293 expression (&exp);
1294 }
b99bd4ef 1295
c19d1205
ZW		 1296 if (exp.X_op != O_constant)
1297 {
1298 as_bad (_("expected #constant"));
1299 ignore_rest_of_line ();
1300 return FAIL;
1301 }
1302 *val = exp.X_add_number;
1303 return SUCCESS;
b99bd4ef 1304}
c19d1205 1305#endif
b99bd4ef 1306
c19d1205 1307/* Register parsing. */
b99bd4ef 1308
c19d1205
ZW		 1309/* Generic register parser. CCP points to what should be the
1310 beginning of a register name. If it is indeed a valid register
1311 name, advance CCP over it and return the reg_entry structure;
1312 otherwise return NULL. Does not issue diagnostics. */
1313
1314static struct reg_entry *
1315arm_reg_parse_multi (char **ccp)
b99bd4ef 1316{
c19d1205
ZW		 1317 char *start = *ccp;
1318 char *p;
1319 struct reg_entry *reg;
b99bd4ef 1320
477330fc
RM		 1321 skip_whitespace (start);
1322
c19d1205
ZW		 1323#ifdef REGISTER_PREFIX
1324 if (*start != REGISTER_PREFIX)
01cfc07f 1325 return NULL;
c19d1205
ZW		 1326 start++;
1327#endif
1328#ifdef OPTIONAL_REGISTER_PREFIX
1329 if (*start == OPTIONAL_REGISTER_PREFIX)
1330 start++;
1331#endif
b99bd4ef 1332
c19d1205
ZW		 1333 p = start;
1334 if (!ISALPHA (*p) || !is_name_beginner (*p))
1335 return NULL;
b99bd4ef 1336
c19d1205
ZW		 1337 do
1338 p++;
1339 while (ISALPHA (*p) || ISDIGIT (*p) || *p == '_');
1340
1341 reg = (struct reg_entry *) hash_find_n (arm_reg_hsh, start, p - start);
1342
1343 if (!reg)
1344 return NULL;
1345
1346 *ccp = p;
1347 return reg;
b99bd4ef
NC		 1348}
1349
1350static int
dcbf9037 1351arm_reg_alt_syntax (char **ccp, char *start, struct reg_entry *reg,
477330fc 1352 enum arm_reg_type type)
b99bd4ef 1353{
c19d1205
ZW		 1354 /* Alternative syntaxes are accepted for a few register classes. */
1355 switch (type)
1356 {
1357 case REG_TYPE_MVF:
1358 case REG_TYPE_MVD:
1359 case REG_TYPE_MVFX:
1360 case REG_TYPE_MVDX:
1361 /* Generic coprocessor register names are allowed for these. */
79134647 1362 if (reg && reg->type == REG_TYPE_CN)
c19d1205
ZW		 1363 return reg->number;
1364 break;
69b97547 1365
c19d1205
ZW		 1366 case REG_TYPE_CP:
1367 /* For backward compatibility, a bare number is valid here. */
1368 {
1369 unsigned long processor = strtoul (start, ccp, 10);
1370 if (*ccp != start && processor <= 15)
1371 return processor;
1372 }
1a0670f3 1373 /* Fall through. */
6057a28f 1374
c19d1205
ZW		 1375 case REG_TYPE_MMXWC:
1376 /* WC includes WCG. ??? I'm not sure this is true for all
1377 instructions that take WC registers. */
79134647 1378 if (reg && reg->type == REG_TYPE_MMXWCG)
c19d1205 1379 return reg->number;
6057a28f 1380 break;
c19d1205 1381
6057a28f 1382 default:
c19d1205 1383 break;
6057a28f
NC		 1384 }
1385
dcbf9037
JB		 1386 return FAIL;
1387}
1388
1389/* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1390 return value is the register number or FAIL. */
1391
1392static int
1393arm_reg_parse (char **ccp, enum arm_reg_type type)
1394{
1395 char *start = *ccp;
1396 struct reg_entry *reg = arm_reg_parse_multi (ccp);
1397 int ret;
1398
1399 /* Do not allow a scalar (reg+index) to parse as a register. */
1400 if (reg && reg->neon && (reg->neon->defined & NTA_HASINDEX))
1401 return FAIL;
1402
1403 if (reg && reg->type == type)
1404 return reg->number;
1405
1406 if ((ret = arm_reg_alt_syntax (ccp, start, reg, type)) != FAIL)
1407 return ret;
1408
c19d1205
ZW		 1409 *ccp = start;
1410 return FAIL;
1411}
69b97547 1412
dcbf9037
JB		 1413/* Parse a Neon type specifier. *STR should point at the leading '.'
1414 character. Does no verification at this stage that the type fits the opcode
1415 properly. E.g.,
1416
1417 .i32.i32.s16
1418 .s32.f32
1419 .u16
1420
1421 Can all be legally parsed by this function.
1422
1423 Fills in neon_type struct pointer with parsed information, and updates STR
1424 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1425 type, FAIL if not. */
1426
1427static int
1428parse_neon_type (struct neon_type *type, char **str)
1429{
1430 char *ptr = *str;
1431
1432 if (type)
1433 type->elems = 0;
1434
1435 while (type->elems < NEON_MAX_TYPE_ELS)
1436 {
1437 enum neon_el_type thistype = NT_untyped;
1438 unsigned thissize = -1u;
1439
1440 if (*ptr != '.')
1441 break;
1442
1443 ptr++;
1444
1445 /* Just a size without an explicit type. */
1446 if (ISDIGIT (*ptr))
1447 goto parsesize;
1448
1449 switch (TOLOWER (*ptr))
1450 {
1451 case 'i': thistype = NT_integer; break;
1452 case 'f': thistype = NT_float; break;
1453 case 'p': thistype = NT_poly; break;
1454 case 's': thistype = NT_signed; break;
1455 case 'u': thistype = NT_unsigned; break;
477330fc
RM		 1456 case 'd':
1457 thistype = NT_float;
1458 thissize = 64;
1459 ptr++;
1460 goto done;
dcbf9037
JB		 1461 default:
1462 as_bad (_("unexpected character `%c' in type specifier"), *ptr);
1463 return FAIL;
1464 }
1465
1466 ptr++;
1467
1468 /* .f is an abbreviation for .f32. */
1469 if (thistype == NT_float && !ISDIGIT (*ptr))
1470 thissize = 32;
1471 else
1472 {
1473 parsesize:
1474 thissize = strtoul (ptr, &ptr, 10);
1475
1476 if (thissize != 8 && thissize != 16 && thissize != 32
477330fc
RM		 1477 && thissize != 64)
1478 {
1479 as_bad (_("bad size %d in type specifier"), thissize);
dcbf9037
JB		 1480 return FAIL;
1481 }
1482 }
1483
037e8744 1484 done:
dcbf9037 1485 if (type)
477330fc
RM		 1486 {
1487 type->el[type->elems].type = thistype;
dcbf9037
JB		 1488 type->el[type->elems].size = thissize;
1489 type->elems++;
1490 }
1491 }
1492
1493 /* Empty/missing type is not a successful parse. */
1494 if (type->elems == 0)
1495 return FAIL;
1496
1497 *str = ptr;
1498
1499 return SUCCESS;
1500}
1501
1502/* Errors may be set multiple times during parsing or bit encoding
1503 (particularly in the Neon bits), but usually the earliest error which is set
1504 will be the most meaningful. Avoid overwriting it with later (cascading)
1505 errors by calling this function. */
1506
1507static void
1508first_error (const char *err)
1509{
1510 if (!inst.error)
1511 inst.error = err;
1512}
1513
1514/* Parse a single type, e.g. ".s32", leading period included. */
1515static int
1516parse_neon_operand_type (struct neon_type_el *vectype, char **ccp)
1517{
1518 char *str = *ccp;
1519 struct neon_type optype;
1520
1521 if (*str == '.')
1522 {
1523 if (parse_neon_type (&optype, &str) == SUCCESS)
477330fc
RM		 1524 {
1525 if (optype.elems == 1)
1526 *vectype = optype.el[0];
1527 else
1528 {
1529 first_error (_("only one type should be specified for operand"));
1530 return FAIL;
1531 }
1532 }
dcbf9037 1533 else
477330fc
RM		 1534 {
1535 first_error (_("vector type expected"));
1536 return FAIL;
1537 }
dcbf9037
JB		 1538 }
1539 else
1540 return FAIL;
5f4273c7 1541
dcbf9037 1542 *ccp = str;
5f4273c7 1543
dcbf9037
JB		 1544 return SUCCESS;
1545}
1546
1547/* Special meanings for indices (which have a range of 0-7), which will fit into
1548 a 4-bit integer. */
1549
1550#define NEON_ALL_LANES 15
1551#define NEON_INTERLEAVE_LANES 14
1552
5ee91343
AV		 1553/* Record a use of the given feature. */
1554static void
1555record_feature_use (const arm_feature_set *feature)
1556{
1557 if (thumb_mode)
1558 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, *feature);
1559 else
1560 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, *feature);
1561}
1562
1563/* If the given feature available in the selected CPU, mark it as used.
1564 Returns TRUE iff feature is available. */
1565static bfd_boolean
1566mark_feature_used (const arm_feature_set *feature)
1567{
886e1c73
AV		 1568
1569 /* Do not support the use of MVE only instructions when in auto-detection or
1570 -march=all. */
1571 if (((feature == &mve_ext) || (feature == &mve_fp_ext))
1572 && ARM_CPU_IS_ANY (cpu_variant))
1573 {
1574 first_error (BAD_MVE_AUTO);
1575 return FALSE;
1576 }
5ee91343
AV		 1577 /* Ensure the option is valid on the current architecture. */
1578 if (!ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
1579 return FALSE;
1580
1581 /* Add the appropriate architecture feature for the barrier option used.
1582 */
1583 record_feature_use (feature);
1584
1585 return TRUE;
1586}
1587
dcbf9037
JB		 1588/* Parse either a register or a scalar, with an optional type. Return the
1589 register number, and optionally fill in the actual type of the register
1590 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1591 type/index information in *TYPEINFO. */
1592
1593static int
1594parse_typed_reg_or_scalar (char **ccp, enum arm_reg_type type,
477330fc
RM		 1595 enum arm_reg_type *rtype,
1596 struct neon_typed_alias *typeinfo)
dcbf9037
JB		 1597{
1598 char *str = *ccp;
1599 struct reg_entry *reg = arm_reg_parse_multi (&str);
1600 struct neon_typed_alias atype;
1601 struct neon_type_el parsetype;
1602
1603 atype.defined = 0;
1604 atype.index = -1;
1605 atype.eltype.type = NT_invtype;
1606 atype.eltype.size = -1;
1607
1608 /* Try alternate syntax for some types of register. Note these are mutually
1609 exclusive with the Neon syntax extensions. */
1610 if (reg == NULL)
1611 {
1612 int altreg = arm_reg_alt_syntax (&str, *ccp, reg, type);
1613 if (altreg != FAIL)
477330fc 1614 *ccp = str;
dcbf9037 1615 if (typeinfo)
477330fc 1616 *typeinfo = atype;
dcbf9037
JB		 1617 return altreg;
1618 }
1619
037e8744
JB		 1620 /* Undo polymorphism when a set of register types may be accepted. */
1621 if ((type == REG_TYPE_NDQ
1622 && (reg->type == REG_TYPE_NQ || reg->type == REG_TYPE_VFD))
1623 || (type == REG_TYPE_VFSD
477330fc 1624 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
037e8744 1625 || (type == REG_TYPE_NSDQ
477330fc
RM		 1626 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD
1627 || reg->type == REG_TYPE_NQ))
dec41383
JW		 1628 || (type == REG_TYPE_NSD
1629 && (reg->type == REG_TYPE_VFS || reg->type == REG_TYPE_VFD))
f512f76f
NC		 1630 || (type == REG_TYPE_MMXWC
1631 && (reg->type == REG_TYPE_MMXWCG)))
21d799b5 1632 type = (enum arm_reg_type) reg->type;
dcbf9037 1633
5ee91343
AV		 1634 if (type == REG_TYPE_MQ)
1635 {
1636 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1637 return FAIL;
1638
1639 if (!reg || reg->type != REG_TYPE_NQ)
1640 return FAIL;
1641
1642 if (reg->number > 14 && !mark_feature_used (&fpu_vfp_ext_d32))
1643 {
1644 first_error (_("expected MVE register [q0..q7]"));
1645 return FAIL;
1646 }
1647 type = REG_TYPE_NQ;
1648 }
1649 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
1650 && (type == REG_TYPE_NQ))
1651 return FAIL;
1652
1653
dcbf9037
JB		 1654 if (type != reg->type)
1655 return FAIL;
1656
1657 if (reg->neon)
1658 atype = *reg->neon;
5f4273c7 1659
dcbf9037
JB		 1660 if (parse_neon_operand_type (&parsetype, &str) == SUCCESS)
1661 {
1662 if ((atype.defined & NTA_HASTYPE) != 0)
477330fc
RM		 1663 {
1664 first_error (_("can't redefine type for operand"));
1665 return FAIL;
1666 }
dcbf9037
JB		 1667 atype.defined |= NTA_HASTYPE;
1668 atype.eltype = parsetype;
1669 }
5f4273c7 1670
dcbf9037
JB		 1671 if (skip_past_char (&str, '[') == SUCCESS)
1672 {
dec41383
JW		 1673 if (type != REG_TYPE_VFD
1674 && !(type == REG_TYPE_VFS
57785aa2
AV		 1675 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_2))
1676 && !(type == REG_TYPE_NQ
1677 && ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)))
477330fc 1678 {
57785aa2
AV		 1679 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
1680 first_error (_("only D and Q registers may be indexed"));
1681 else
1682 first_error (_("only D registers may be indexed"));
477330fc
RM		 1683 return FAIL;
1684 }
5f4273c7 1685
dcbf9037 1686 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 1687 {
1688 first_error (_("can't change index for operand"));
1689 return FAIL;
1690 }
dcbf9037
JB		 1691
1692 atype.defined |= NTA_HASINDEX;
1693
1694 if (skip_past_char (&str, ']') == SUCCESS)
477330fc 1695 atype.index = NEON_ALL_LANES;
dcbf9037 1696 else
477330fc
RM		 1697 {
1698 expressionS exp;
dcbf9037 1699
477330fc 1700 my_get_expression (&exp, &str, GE_NO_PREFIX);
dcbf9037 1701
477330fc
RM		 1702 if (exp.X_op != O_constant)
1703 {
1704 first_error (_("constant expression required"));
1705 return FAIL;
1706 }
dcbf9037 1707
477330fc
RM		 1708 if (skip_past_char (&str, ']') == FAIL)
1709 return FAIL;
dcbf9037 1710
477330fc
RM		 1711 atype.index = exp.X_add_number;
1712 }
dcbf9037 1713 }
5f4273c7 1714
dcbf9037
JB		 1715 if (typeinfo)
1716 *typeinfo = atype;
5f4273c7 1717
dcbf9037
JB		 1718 if (rtype)
1719 *rtype = type;
5f4273c7 1720
dcbf9037 1721 *ccp = str;
5f4273c7 1722
dcbf9037
JB		 1723 return reg->number;
1724}
1725
efd6b359 1726/* Like arm_reg_parse, but also allow the following extra features:
dcbf9037
JB		 1727 - If RTYPE is non-zero, return the (possibly restricted) type of the
1728 register (e.g. Neon double or quad reg when either has been requested).
1729 - If this is a Neon vector type with additional type information, fill
1730 in the struct pointed to by VECTYPE (if non-NULL).
5f4273c7 1731 This function will fault on encountering a scalar. */
dcbf9037
JB		 1732
1733static int
1734arm_typed_reg_parse (char **ccp, enum arm_reg_type type,
477330fc 1735 enum arm_reg_type *rtype, struct neon_type_el *vectype)
dcbf9037
JB		 1736{
1737 struct neon_typed_alias atype;
1738 char *str = *ccp;
1739 int reg = parse_typed_reg_or_scalar (&str, type, rtype, &atype);
1740
1741 if (reg == FAIL)
1742 return FAIL;
1743
0855e32b
NS		 1744 /* Do not allow regname(... to parse as a register. */
1745 if (*str == '(')
1746 return FAIL;
1747
dcbf9037
JB		 1748 /* Do not allow a scalar (reg+index) to parse as a register. */
1749 if ((atype.defined & NTA_HASINDEX) != 0)
1750 {
1751 first_error (_("register operand expected, but got scalar"));
1752 return FAIL;
1753 }
1754
1755 if (vectype)
1756 *vectype = atype.eltype;
1757
1758 *ccp = str;
1759
1760 return reg;
1761}
1762
1763#define NEON_SCALAR_REG(X) ((X) >> 4)
1764#define NEON_SCALAR_INDEX(X) ((X) & 15)
1765
5287ad62
JB		 1766/* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1767 have enough information to be able to do a good job bounds-checking. So, we
1768 just do easy checks here, and do further checks later. */
1769
1770static int
57785aa2
AV		 1771parse_scalar (char **ccp, int elsize, struct neon_type_el *type, enum
1772 arm_reg_type reg_type)
5287ad62 1773{
dcbf9037 1774 int reg;
5287ad62 1775 char *str = *ccp;
dcbf9037 1776 struct neon_typed_alias atype;
57785aa2 1777 unsigned reg_size;
5f4273c7 1778
dec41383 1779 reg = parse_typed_reg_or_scalar (&str, reg_type, NULL, &atype);
5f4273c7 1780
57785aa2
AV		 1781 switch (reg_type)
1782 {
1783 case REG_TYPE_VFS:
1784 reg_size = 32;
1785 break;
1786 case REG_TYPE_VFD:
1787 reg_size = 64;
1788 break;
1789 case REG_TYPE_MQ:
1790 reg_size = 128;
1791 break;
1792 default:
1793 gas_assert (0);
1794 return FAIL;
1795 }
1796
dcbf9037 1797 if (reg == FAIL || (atype.defined & NTA_HASINDEX) == 0)
5287ad62 1798 return FAIL;
5f4273c7 1799
57785aa2 1800 if (reg_type != REG_TYPE_MQ && atype.index == NEON_ALL_LANES)
5287ad62 1801 {
dcbf9037 1802 first_error (_("scalar must have an index"));
5287ad62
JB		 1803 return FAIL;
1804 }
57785aa2 1805 else if (atype.index >= reg_size / elsize)
5287ad62 1806 {
dcbf9037 1807 first_error (_("scalar index out of range"));
5287ad62
JB		 1808 return FAIL;
1809 }
5f4273c7 1810
dcbf9037
JB		 1811 if (type)
1812 *type = atype.eltype;
5f4273c7 1813
5287ad62 1814 *ccp = str;
5f4273c7 1815
dcbf9037 1816 return reg * 16 + atype.index;
5287ad62
JB		 1817}
1818
4b5a202f
AV		 1819/* Types of registers in a list. */
1820
1821enum reg_list_els
1822{
1823 REGLIST_RN,
1824 REGLIST_CLRM,
1825 REGLIST_VFP_S,
efd6b359 1826 REGLIST_VFP_S_VPR,
4b5a202f 1827 REGLIST_VFP_D,
efd6b359 1828 REGLIST_VFP_D_VPR,
4b5a202f
AV		 1829 REGLIST_NEON_D
1830};
1831
c19d1205 1832/* Parse an ARM register list. Returns the bitmask, or FAIL. */
e07e6e58 1833
c19d1205 1834static long
4b5a202f 1835parse_reg_list (char ** strp, enum reg_list_els etype)
c19d1205 1836{
4b5a202f
AV		 1837 char *str = *strp;
1838 long range = 0;
1839 int another_range;
1840
1841 gas_assert (etype == REGLIST_RN || etype == REGLIST_CLRM);
a737bd4d 1842
c19d1205
ZW		 1843 /* We come back here if we get ranges concatenated by '+' or '|'. */
1844 do
6057a28f 1845 {
477330fc
RM		 1846 skip_whitespace (str);
1847
c19d1205 1848 another_range = 0;
a737bd4d 1849
c19d1205
ZW		 1850 if (*str == '{')
1851 {
1852 int in_range = 0;
1853 int cur_reg = -1;
a737bd4d 1854
c19d1205
ZW		 1855 str++;
1856 do
1857 {
1858 int reg;
4b5a202f
AV		 1859 const char apsr_str[] = "apsr";
1860 int apsr_str_len = strlen (apsr_str);
6057a28f 1861
4b5a202f
AV		 1862 reg = arm_reg_parse (&str, REGLIST_RN);
1863 if (etype == REGLIST_CLRM)
c19d1205 1864 {
4b5a202f
AV		 1865 if (reg == REG_SP || reg == REG_PC)
1866 reg = FAIL;
1867 else if (reg == FAIL
1868 && !strncasecmp (str, apsr_str, apsr_str_len)
1869 && !ISALPHA (*(str + apsr_str_len)))
1870 {
1871 reg = 15;
1872 str += apsr_str_len;
1873 }
1874
1875 if (reg == FAIL)
1876 {
1877 first_error (_("r0-r12, lr or APSR expected"));
1878 return FAIL;
1879 }
1880 }
1881 else /* etype == REGLIST_RN. */
1882 {
1883 if (reg == FAIL)
1884 {
1885 first_error (_(reg_expected_msgs[REGLIST_RN]));
1886 return FAIL;
1887 }
c19d1205 1888 }
a737bd4d 1889
c19d1205
ZW		 1890 if (in_range)
1891 {
1892 int i;
a737bd4d 1893
c19d1205
ZW		 1894 if (reg <= cur_reg)
1895 {
dcbf9037 1896 first_error (_("bad range in register list"));
c19d1205
ZW		 1897 return FAIL;
1898 }
40a18ebd 1899
c19d1205
ZW		 1900 for (i = cur_reg + 1; i < reg; i++)
1901 {
1902 if (range & (1 << i))
1903 as_tsktsk
1904 (_("Warning: duplicated register (r%d) in register list"),
1905 i);
1906 else
1907 range |= 1 << i;
1908 }
1909 in_range = 0;
1910 }
a737bd4d 1911
c19d1205
ZW		 1912 if (range & (1 << reg))
1913 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1914 reg);
1915 else if (reg <= cur_reg)
1916 as_tsktsk (_("Warning: register range not in ascending order"));
a737bd4d 1917
c19d1205
ZW		 1918 range |= 1 << reg;
1919 cur_reg = reg;
1920 }
1921 while (skip_past_comma (&str) != FAIL
1922 || (in_range = 1, *str++ == '-'));
1923 str--;
a737bd4d 1924
d996d970 1925 if (skip_past_char (&str, '}') == FAIL)
c19d1205 1926 {
dcbf9037 1927 first_error (_("missing `}'"));
c19d1205
ZW		 1928 return FAIL;
1929 }
1930 }
4b5a202f 1931 else if (etype == REGLIST_RN)
c19d1205 1932 {
91d6fa6a 1933 expressionS exp;
40a18ebd 1934
91d6fa6a 1935 if (my_get_expression (&exp, &str, GE_NO_PREFIX))
c19d1205 1936 return FAIL;
40a18ebd 1937
91d6fa6a 1938 if (exp.X_op == O_constant)
c19d1205 1939 {
91d6fa6a
NC		 1940 if (exp.X_add_number
1941 != (exp.X_add_number & 0x0000ffff))
c19d1205
ZW		 1942 {
1943 inst.error = _("invalid register mask");
1944 return FAIL;
1945 }
a737bd4d 1946
91d6fa6a 1947 if ((range & exp.X_add_number) != 0)
c19d1205 1948 {
91d6fa6a 1949 int regno = range & exp.X_add_number;
a737bd4d 1950
c19d1205
ZW		 1951 regno &= -regno;
1952 regno = (1 << regno) - 1;
1953 as_tsktsk
1954 (_("Warning: duplicated register (r%d) in register list"),
1955 regno);
1956 }
a737bd4d 1957
91d6fa6a 1958 range |= exp.X_add_number;
c19d1205
ZW		 1959 }
1960 else
1961 {
e2b0ab59 1962 if (inst.relocs[0].type != 0)
c19d1205
ZW		 1963 {
1964 inst.error = _("expression too complex");
1965 return FAIL;
1966 }
a737bd4d 1967
e2b0ab59
AV		 1968 memcpy (&inst.relocs[0].exp, &exp, sizeof (expressionS));
1969 inst.relocs[0].type = BFD_RELOC_ARM_MULTI;
1970 inst.relocs[0].pc_rel = 0;
c19d1205
ZW		 1971 }
1972 }
a737bd4d 1973
c19d1205
ZW		 1974 if (*str == '|' || *str == '+')
1975 {
1976 str++;
1977 another_range = 1;
1978 }
a737bd4d 1979 }
c19d1205 1980 while (another_range);
a737bd4d 1981
c19d1205
ZW		 1982 *strp = str;
1983 return range;
a737bd4d
NC		 1984}
1985
c19d1205
ZW		 1986/* Parse a VFP register list. If the string is invalid return FAIL.
1987 Otherwise return the number of registers, and set PBASE to the first
5287ad62
JB		 1988 register. Parses registers of type ETYPE.
1989 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1990 - Q registers can be used to specify pairs of D registers
1991 - { } can be omitted from around a singleton register list
477330fc
RM		 1992 FIXME: This is not implemented, as it would require backtracking in
1993 some cases, e.g.:
1994 vtbl.8 d3,d4,d5
1995 This could be done (the meaning isn't really ambiguous), but doesn't
1996 fit in well with the current parsing framework.
dcbf9037
JB		 1997 - 32 D registers may be used (also true for VFPv3).
1998 FIXME: Types are ignored in these register lists, which is probably a
1999 bug. */
6057a28f 2000
c19d1205 2001static int
efd6b359
AV		 2002parse_vfp_reg_list (char **ccp, unsigned int *pbase, enum reg_list_els etype,
2003 bfd_boolean *partial_match)
6057a28f 2004{
037e8744 2005 char *str = *ccp;
c19d1205
ZW		 2006 int base_reg;
2007 int new_base;
21d799b5 2008 enum arm_reg_type regtype = (enum arm_reg_type) 0;
5287ad62 2009 int max_regs = 0;
c19d1205
ZW		 2010 int count = 0;
2011 int warned = 0;
2012 unsigned long mask = 0;
a737bd4d 2013 int i;
efd6b359
AV		 2014 bfd_boolean vpr_seen = FALSE;
2015 bfd_boolean expect_vpr =
2016 (etype == REGLIST_VFP_S_VPR) || (etype == REGLIST_VFP_D_VPR);
6057a28f 2017
477330fc 2018 if (skip_past_char (&str, '{') == FAIL)
5287ad62
JB		 2019 {
2020 inst.error = _("expecting {");
2021 return FAIL;
2022 }
6057a28f 2023
5287ad62 2024 switch (etype)
c19d1205 2025 {
5287ad62 2026 case REGLIST_VFP_S:
efd6b359 2027 case REGLIST_VFP_S_VPR:
c19d1205
ZW		 2028 regtype = REG_TYPE_VFS;
2029 max_regs = 32;
5287ad62 2030 break;
5f4273c7 2031
5287ad62 2032 case REGLIST_VFP_D:
efd6b359 2033 case REGLIST_VFP_D_VPR:
5287ad62 2034 regtype = REG_TYPE_VFD;
b7fc2769 2035 break;
5f4273c7 2036
b7fc2769
JB		 2037 case REGLIST_NEON_D:
2038 regtype = REG_TYPE_NDQ;
2039 break;
4b5a202f
AV		 2040
2041 default:
2042 gas_assert (0);
b7fc2769
JB		 2043 }
2044
efd6b359 2045 if (etype != REGLIST_VFP_S && etype != REGLIST_VFP_S_VPR)
b7fc2769 2046 {
b1cc4aeb
PB		 2047 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2048 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 2049 {
2050 max_regs = 32;
2051 if (thumb_mode)
2052 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
2053 fpu_vfp_ext_d32);
2054 else
2055 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
2056 fpu_vfp_ext_d32);
2057 }
5287ad62 2058 else
477330fc 2059 max_regs = 16;
c19d1205 2060 }
6057a28f 2061
c19d1205 2062 base_reg = max_regs;
efd6b359 2063 *partial_match = FALSE;
a737bd4d 2064
c19d1205
ZW		 2065 do
2066 {
5287ad62 2067 int setmask = 1, addregs = 1;
efd6b359
AV		 2068 const char vpr_str[] = "vpr";
2069 int vpr_str_len = strlen (vpr_str);
dcbf9037 2070
037e8744 2071 new_base = arm_typed_reg_parse (&str, regtype, &regtype, NULL);
dcbf9037 2072
efd6b359
AV		 2073 if (expect_vpr)
2074 {
2075 if (new_base == FAIL
2076 && !strncasecmp (str, vpr_str, vpr_str_len)
2077 && !ISALPHA (*(str + vpr_str_len))
2078 && !vpr_seen)
2079 {
2080 vpr_seen = TRUE;
2081 str += vpr_str_len;
2082 if (count == 0)
2083 base_reg = 0; /* Canonicalize VPR only on d0 with 0 regs. */
2084 }
2085 else if (vpr_seen)
2086 {
2087 first_error (_("VPR expected last"));
2088 return FAIL;
2089 }
2090 else if (new_base == FAIL)
2091 {
2092 if (regtype == REG_TYPE_VFS)
2093 first_error (_("VFP single precision register or VPR "
2094 "expected"));
2095 else /* regtype == REG_TYPE_VFD. */
2096 first_error (_("VFP/Neon double precision register or VPR "
2097 "expected"));
2098 return FAIL;
2099 }
2100 }
2101 else if (new_base == FAIL)
a737bd4d 2102 {
dcbf9037 2103 first_error (_(reg_expected_msgs[regtype]));
c19d1205
ZW		 2104 return FAIL;
2105 }
5f4273c7 2106
efd6b359
AV		 2107 *partial_match = TRUE;
2108 if (vpr_seen)
2109 continue;
2110
b7fc2769 2111 if (new_base >= max_regs)
477330fc
RM		 2112 {
2113 first_error (_("register out of range in list"));
2114 return FAIL;
2115 }
5f4273c7 2116
5287ad62
JB		 2117 /* Note: a value of 2 * n is returned for the register Q<n>. */
2118 if (regtype == REG_TYPE_NQ)
477330fc
RM		 2119 {
2120 setmask = 3;
2121 addregs = 2;
2122 }
5287ad62 2123
c19d1205
ZW		 2124 if (new_base < base_reg)
2125 base_reg = new_base;
a737bd4d 2126
5287ad62 2127 if (mask & (setmask << new_base))
c19d1205 2128 {
dcbf9037 2129 first_error (_("invalid register list"));
c19d1205 2130 return FAIL;
a737bd4d 2131 }
a737bd4d 2132
efd6b359 2133 if ((mask >> new_base) != 0 && ! warned && !vpr_seen)
c19d1205
ZW		 2134 {
2135 as_tsktsk (_("register list not in ascending order"));
2136 warned = 1;
2137 }
0bbf2aa4 2138
5287ad62
JB		 2139 mask |= setmask << new_base;
2140 count += addregs;
0bbf2aa4 2141
037e8744 2142 if (*str == '-') /* We have the start of a range expression */
c19d1205
ZW		 2143 {
2144 int high_range;
0bbf2aa4 2145
037e8744 2146 str++;
0bbf2aa4 2147
037e8744 2148 if ((high_range = arm_typed_reg_parse (&str, regtype, NULL, NULL))
477330fc 2149 == FAIL)
c19d1205
ZW		 2150 {
2151 inst.error = gettext (reg_expected_msgs[regtype]);
2152 return FAIL;
2153 }
0bbf2aa4 2154
477330fc
RM		 2155 if (high_range >= max_regs)
2156 {
2157 first_error (_("register out of range in list"));
2158 return FAIL;
2159 }
b7fc2769 2160
477330fc
RM		 2161 if (regtype == REG_TYPE_NQ)
2162 high_range = high_range + 1;
5287ad62 2163
c19d1205
ZW		 2164 if (high_range <= new_base)
2165 {
2166 inst.error = _("register range not in ascending order");
2167 return FAIL;
2168 }
0bbf2aa4 2169
5287ad62 2170 for (new_base += addregs; new_base <= high_range; new_base += addregs)
0bbf2aa4 2171 {
5287ad62 2172 if (mask & (setmask << new_base))
0bbf2aa4 2173 {
c19d1205
ZW		 2174 inst.error = _("invalid register list");
2175 return FAIL;
0bbf2aa4 2176 }
c19d1205 2177
5287ad62
JB		 2178 mask |= setmask << new_base;
2179 count += addregs;
0bbf2aa4 2180 }
0bbf2aa4 2181 }
0bbf2aa4 2182 }
037e8744 2183 while (skip_past_comma (&str) != FAIL);
0bbf2aa4 2184
037e8744 2185 str++;
0bbf2aa4 2186
c19d1205 2187 /* Sanity check -- should have raised a parse error above. */
efd6b359 2188 if ((!vpr_seen && count == 0) || count > max_regs)
c19d1205
ZW		 2189 abort ();
2190
2191 *pbase = base_reg;
2192
efd6b359
AV		 2193 if (expect_vpr && !vpr_seen)
2194 {
2195 first_error (_("VPR expected last"));
2196 return FAIL;
2197 }
2198
c19d1205
ZW		 2199 /* Final test -- the registers must be consecutive. */
2200 mask >>= base_reg;
2201 for (i = 0; i < count; i++)
2202 {
2203 if ((mask & (1u << i)) == 0)
2204 {
2205 inst.error = _("non-contiguous register range");
2206 return FAIL;
2207 }
2208 }
2209
037e8744
JB		 2210 *ccp = str;
2211
c19d1205 2212 return count;
b99bd4ef
NC		 2213}
2214
dcbf9037
JB		 2215/* True if two alias types are the same. */
2216
c921be7d 2217static bfd_boolean
dcbf9037
JB		 2218neon_alias_types_same (struct neon_typed_alias *a, struct neon_typed_alias *b)
2219{
2220 if (!a && !b)
c921be7d 2221 return TRUE;
5f4273c7 2222
dcbf9037 2223 if (!a || !b)
c921be7d 2224 return FALSE;
dcbf9037
JB		 2225
2226 if (a->defined != b->defined)
c921be7d 2227 return FALSE;
5f4273c7 2228
dcbf9037
JB		 2229 if ((a->defined & NTA_HASTYPE) != 0
2230 && (a->eltype.type != b->eltype.type
477330fc 2231 || a->eltype.size != b->eltype.size))
c921be7d 2232 return FALSE;
dcbf9037
JB		 2233
2234 if ((a->defined & NTA_HASINDEX) != 0
2235 && (a->index != b->index))
c921be7d 2236 return FALSE;
5f4273c7 2237
c921be7d 2238 return TRUE;
dcbf9037
JB		 2239}
2240
5287ad62
JB		 2241/* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2242 The base register is put in *PBASE.
dcbf9037 2243 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
5287ad62
JB		 2244 the return value.
2245 The register stride (minus one) is put in bit 4 of the return value.
dcbf9037
JB		 2246 Bits [6:5] encode the list length (minus one).
2247 The type of the list elements is put in *ELTYPE, if non-NULL. */
5287ad62 2248
5287ad62 2249#define NEON_LANE(X) ((X) & 0xf)
dcbf9037 2250#define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
5287ad62
JB		 2251#define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2252
2253static int
dcbf9037 2254parse_neon_el_struct_list (char **str, unsigned *pbase,
35c228db 2255 int mve,
477330fc 2256 struct neon_type_el *eltype)
5287ad62
JB		 2257{
2258 char *ptr = *str;
2259 int base_reg = -1;
2260 int reg_incr = -1;
2261 int count = 0;
2262 int lane = -1;
2263 int leading_brace = 0;
2264 enum arm_reg_type rtype = REG_TYPE_NDQ;
35c228db
AV		 2265 const char *const incr_error = mve ? _("register stride must be 1") :
2266 _("register stride must be 1 or 2");
20203fb9 2267 const char *const type_error = _("mismatched element/structure types in list");
dcbf9037 2268 struct neon_typed_alias firsttype;
f85d59c3
KT		 2269 firsttype.defined = 0;
2270 firsttype.eltype.type = NT_invtype;
2271 firsttype.eltype.size = -1;
2272 firsttype.index = -1;
5f4273c7 2273
5287ad62
JB		 2274 if (skip_past_char (&ptr, '{') == SUCCESS)
2275 leading_brace = 1;
5f4273c7 2276
5287ad62
JB		 2277 do
2278 {
dcbf9037 2279 struct neon_typed_alias atype;
35c228db
AV		 2280 if (mve)
2281 rtype = REG_TYPE_MQ;
dcbf9037
JB		 2282 int getreg = parse_typed_reg_or_scalar (&ptr, rtype, &rtype, &atype);
2283
5287ad62 2284 if (getreg == FAIL)
477330fc
RM		 2285 {
2286 first_error (_(reg_expected_msgs[rtype]));
2287 return FAIL;
2288 }
5f4273c7 2289
5287ad62 2290 if (base_reg == -1)
477330fc
RM		 2291 {
2292 base_reg = getreg;
2293 if (rtype == REG_TYPE_NQ)
2294 {
2295 reg_incr = 1;
2296 }
2297 firsttype = atype;
2298 }
5287ad62 2299 else if (reg_incr == -1)
477330fc
RM		 2300 {
2301 reg_incr = getreg - base_reg;
2302 if (reg_incr < 1 || reg_incr > 2)
2303 {
2304 first_error (_(incr_error));
2305 return FAIL;
2306 }
2307 }
5287ad62 2308 else if (getreg != base_reg + reg_incr * count)
477330fc
RM		 2309 {
2310 first_error (_(incr_error));
2311 return FAIL;
2312 }
dcbf9037 2313
c921be7d 2314 if (! neon_alias_types_same (&atype, &firsttype))
477330fc
RM		 2315 {
2316 first_error (_(type_error));
2317 return FAIL;
2318 }
5f4273c7 2319
5287ad62 2320 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
477330fc 2321 modes. */
5287ad62 2322 if (ptr[0] == '-')
477330fc
RM		 2323 {
2324 struct neon_typed_alias htype;
2325 int hireg, dregs = (rtype == REG_TYPE_NQ) ? 2 : 1;
2326 if (lane == -1)
2327 lane = NEON_INTERLEAVE_LANES;
2328 else if (lane != NEON_INTERLEAVE_LANES)
2329 {
2330 first_error (_(type_error));
2331 return FAIL;
2332 }
2333 if (reg_incr == -1)
2334 reg_incr = 1;
2335 else if (reg_incr != 1)
2336 {
2337 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2338 return FAIL;
2339 }
2340 ptr++;
2341 hireg = parse_typed_reg_or_scalar (&ptr, rtype, NULL, &htype);
2342 if (hireg == FAIL)
2343 {
2344 first_error (_(reg_expected_msgs[rtype]));
2345 return FAIL;
2346 }
2347 if (! neon_alias_types_same (&htype, &firsttype))
2348 {
2349 first_error (_(type_error));
2350 return FAIL;
2351 }
2352 count += hireg + dregs - getreg;
2353 continue;
2354 }
5f4273c7 2355
5287ad62
JB		 2356 /* If we're using Q registers, we can't use [] or [n] syntax. */
2357 if (rtype == REG_TYPE_NQ)
477330fc
RM		 2358 {
2359 count += 2;
2360 continue;
2361 }
5f4273c7 2362
dcbf9037 2363 if ((atype.defined & NTA_HASINDEX) != 0)
477330fc
RM		 2364 {
2365 if (lane == -1)
2366 lane = atype.index;
2367 else if (lane != atype.index)
2368 {
2369 first_error (_(type_error));
2370 return FAIL;
2371 }
2372 }
5287ad62 2373 else if (lane == -1)
477330fc 2374 lane = NEON_INTERLEAVE_LANES;
5287ad62 2375 else if (lane != NEON_INTERLEAVE_LANES)
477330fc
RM		 2376 {
2377 first_error (_(type_error));
2378 return FAIL;
2379 }
5287ad62
JB		 2380 count++;
2381 }
2382 while ((count != 1 || leading_brace) && skip_past_comma (&ptr) != FAIL);
5f4273c7 2383
5287ad62
JB		 2384 /* No lane set by [x]. We must be interleaving structures. */
2385 if (lane == -1)
2386 lane = NEON_INTERLEAVE_LANES;
5f4273c7 2387
5287ad62 2388 /* Sanity check. */
35c228db 2389 if (lane == -1 || base_reg == -1 || count < 1 || (!mve && count > 4)
5287ad62
JB		 2390 || (count > 1 && reg_incr == -1))
2391 {
dcbf9037 2392 first_error (_("error parsing element/structure list"));
5287ad62
JB		 2393 return FAIL;
2394 }
2395
2396 if ((count > 1 || leading_brace) && skip_past_char (&ptr, '}') == FAIL)
2397 {
dcbf9037 2398 first_error (_("expected }"));
5287ad62
JB		 2399 return FAIL;
2400 }
5f4273c7 2401
5287ad62
JB		 2402 if (reg_incr == -1)
2403 reg_incr = 1;
2404
dcbf9037
JB		 2405 if (eltype)
2406 *eltype = firsttype.eltype;
2407
5287ad62
JB		 2408 *pbase = base_reg;
2409 *str = ptr;
5f4273c7 2410
5287ad62
JB		 2411 return lane | ((reg_incr - 1) << 4) | ((count - 1) << 5);
2412}
2413
c19d1205
ZW		 2414/* Parse an explicit relocation suffix on an expression. This is
2415 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2416 arm_reloc_hsh contains no entries, so this function can only
2417 succeed if there is no () after the word. Returns -1 on error,
2418 BFD_RELOC_UNUSED if there wasn't any suffix. */
3da1d841 2419
c19d1205
ZW		 2420static int
2421parse_reloc (char **str)
b99bd4ef 2422{
c19d1205
ZW		 2423 struct reloc_entry *r;
2424 char *p, *q;
b99bd4ef 2425
c19d1205
ZW		 2426 if (**str != '(')
2427 return BFD_RELOC_UNUSED;
b99bd4ef 2428
c19d1205
ZW		 2429 p = *str + 1;
2430 q = p;
2431
2432 while (*q && *q != ')' && *q != ',')
2433 q++;
2434 if (*q != ')')
2435 return -1;
2436
21d799b5
NC		 2437 if ((r = (struct reloc_entry *)
2438 hash_find_n (arm_reloc_hsh, p, q - p)) == NULL)
c19d1205
ZW		 2439 return -1;
2440
2441 *str = q + 1;
2442 return r->reloc;
b99bd4ef
NC		 2443}
2444
c19d1205
ZW		 2445/* Directives: register aliases. */
2446
dcbf9037 2447static struct reg_entry *
90ec0d68 2448insert_reg_alias (char *str, unsigned number, int type)
b99bd4ef 2449{
d3ce72d0 2450 struct reg_entry *new_reg;
c19d1205 2451 const char *name;
b99bd4ef 2452
d3ce72d0 2453 if ((new_reg = (struct reg_entry *) hash_find (arm_reg_hsh, str)) != 0)
c19d1205 2454 {
d3ce72d0 2455 if (new_reg->builtin)
c19d1205 2456 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str);
b99bd4ef 2457
c19d1205
ZW		 2458 /* Only warn about a redefinition if it's not defined as the
2459 same register. */
d3ce72d0 2460 else if (new_reg->number != number || new_reg->type != type)
c19d1205 2461 as_warn (_("ignoring redefinition of register alias '%s'"), str);
69b97547 2462
d929913e 2463 return NULL;
c19d1205 2464 }
b99bd4ef 2465
c19d1205 2466 name = xstrdup (str);
325801bd 2467 new_reg = XNEW (struct reg_entry);
b99bd4ef 2468
d3ce72d0
NC		 2469 new_reg->name = name;
2470 new_reg->number = number;
2471 new_reg->type = type;
2472 new_reg->builtin = FALSE;
2473 new_reg->neon = NULL;
b99bd4ef 2474
d3ce72d0 2475 if (hash_insert (arm_reg_hsh, name, (void *) new_reg))
c19d1205 2476 abort ();
5f4273c7 2477
d3ce72d0 2478 return new_reg;
dcbf9037
JB		 2479}
2480
2481static void
2482insert_neon_reg_alias (char *str, int number, int type,
477330fc 2483 struct neon_typed_alias *atype)
dcbf9037
JB		 2484{
2485 struct reg_entry *reg = insert_reg_alias (str, number, type);
5f4273c7 2486
dcbf9037
JB		 2487 if (!reg)
2488 {
2489 first_error (_("attempt to redefine typed alias"));
2490 return;
2491 }
5f4273c7 2492
dcbf9037
JB		 2493 if (atype)
2494 {
325801bd 2495 reg->neon = XNEW (struct neon_typed_alias);
dcbf9037
JB		 2496 *reg->neon = *atype;
2497 }
c19d1205 2498}
b99bd4ef 2499
c19d1205 2500/* Look for the .req directive. This is of the form:
b99bd4ef 2501
c19d1205 2502 new_register_name .req existing_register_name
b99bd4ef 2503
c19d1205 2504 If we find one, or if it looks sufficiently like one that we want to
d929913e 2505 handle any error here, return TRUE. Otherwise return FALSE. */
b99bd4ef 2506
d929913e 2507static bfd_boolean
c19d1205
ZW		 2508create_register_alias (char * newname, char *p)
2509{
2510 struct reg_entry *old;
2511 char *oldname, *nbuf;
2512 size_t nlen;
b99bd4ef 2513
c19d1205
ZW		 2514 /* The input scrubber ensures that whitespace after the mnemonic is
2515 collapsed to single spaces. */
2516 oldname = p;
2517 if (strncmp (oldname, " .req ", 6) != 0)
d929913e 2518 return FALSE;
b99bd4ef 2519
c19d1205
ZW		 2520 oldname += 6;
2521 if (*oldname == '\0')
d929913e 2522 return FALSE;
b99bd4ef 2523
21d799b5 2524 old = (struct reg_entry *) hash_find (arm_reg_hsh, oldname);
c19d1205 2525 if (!old)
b99bd4ef 2526 {
c19d1205 2527 as_warn (_("unknown register '%s' -- .req ignored"), oldname);
d929913e 2528 return TRUE;
b99bd4ef
NC		 2529 }
2530
c19d1205
ZW		 2531 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2532 the desired alias name, and p points to its end. If not, then
2533 the desired alias name is in the global original_case_string. */
2534#ifdef TC_CASE_SENSITIVE
2535 nlen = p - newname;
2536#else
2537 newname = original_case_string;
2538 nlen = strlen (newname);
2539#endif
b99bd4ef 2540
29a2809e 2541 nbuf = xmemdup0 (newname, nlen);
b99bd4ef 2542
c19d1205
ZW		 2543 /* Create aliases under the new name as stated; an all-lowercase
2544 version of the new name; and an all-uppercase version of the new
2545 name. */
d929913e
NC		 2546 if (insert_reg_alias (nbuf, old->number, old->type) != NULL)
2547 {
2548 for (p = nbuf; *p; p++)
2549 *p = TOUPPER (*p);
c19d1205 2550
d929913e
NC		 2551 if (strncmp (nbuf, newname, nlen))
2552 {
2553 /* If this attempt to create an additional alias fails, do not bother
2554 trying to create the all-lower case alias. We will fail and issue
2555 a second, duplicate error message. This situation arises when the
2556 programmer does something like:
2557 foo .req r0
2558 Foo .req r1
2559 The second .req creates the "Foo" alias but then fails to create
5f4273c7 2560 the artificial FOO alias because it has already been created by the
d929913e
NC		 2561 first .req. */
2562 if (insert_reg_alias (nbuf, old->number, old->type) == NULL)
e1fa0163
NC		 2563 {
2564 free (nbuf);
2565 return TRUE;
2566 }
d929913e 2567 }
c19d1205 2568
d929913e
NC		 2569 for (p = nbuf; *p; p++)
2570 *p = TOLOWER (*p);
c19d1205 2571
d929913e
NC		 2572 if (strncmp (nbuf, newname, nlen))
2573 insert_reg_alias (nbuf, old->number, old->type);
2574 }
c19d1205 2575
e1fa0163 2576 free (nbuf);
d929913e 2577 return TRUE;
b99bd4ef
NC		 2578}
2579
dcbf9037
JB		 2580/* Create a Neon typed/indexed register alias using directives, e.g.:
2581 X .dn d5.s32[1]
2582 Y .qn 6.s16
2583 Z .dn d7
2584 T .dn Z[0]
2585 These typed registers can be used instead of the types specified after the
2586 Neon mnemonic, so long as all operands given have types. Types can also be
2587 specified directly, e.g.:
5f4273c7 2588 vadd d0.s32, d1.s32, d2.s32 */
dcbf9037 2589
c921be7d 2590static bfd_boolean
dcbf9037
JB		 2591create_neon_reg_alias (char *newname, char *p)
2592{
2593 enum arm_reg_type basetype;
2594 struct reg_entry *basereg;
2595 struct reg_entry mybasereg;
2596 struct neon_type ntype;
2597 struct neon_typed_alias typeinfo;
12d6b0b7 2598 char *namebuf, *nameend ATTRIBUTE_UNUSED;
dcbf9037 2599 int namelen;
5f4273c7 2600
dcbf9037
JB		 2601 typeinfo.defined = 0;
2602 typeinfo.eltype.type = NT_invtype;
2603 typeinfo.eltype.size = -1;
2604 typeinfo.index = -1;
5f4273c7 2605
dcbf9037 2606 nameend = p;
5f4273c7 2607
dcbf9037
JB		 2608 if (strncmp (p, " .dn ", 5) == 0)
2609 basetype = REG_TYPE_VFD;
2610 else if (strncmp (p, " .qn ", 5) == 0)
2611 basetype = REG_TYPE_NQ;
2612 else
c921be7d 2613 return FALSE;
5f4273c7 2614
dcbf9037 2615 p += 5;
5f4273c7 2616
dcbf9037 2617 if (*p == '\0')
c921be7d 2618 return FALSE;
5f4273c7 2619
dcbf9037
JB		 2620 basereg = arm_reg_parse_multi (&p);
2621
2622 if (basereg && basereg->type != basetype)
2623 {
2624 as_bad (_("bad type for register"));
c921be7d 2625 return FALSE;
dcbf9037
JB		 2626 }
2627
2628 if (basereg == NULL)
2629 {
2630 expressionS exp;
2631 /* Try parsing as an integer. */
2632 my_get_expression (&exp, &p, GE_NO_PREFIX);
2633 if (exp.X_op != O_constant)
477330fc
RM		 2634 {
2635 as_bad (_("expression must be constant"));
2636 return FALSE;
2637 }
dcbf9037
JB		 2638 basereg = &mybasereg;
2639 basereg->number = (basetype == REG_TYPE_NQ) ? exp.X_add_number * 2
477330fc 2640 : exp.X_add_number;
dcbf9037
JB		 2641 basereg->neon = 0;
2642 }
2643
2644 if (basereg->neon)
2645 typeinfo = *basereg->neon;
2646
2647 if (parse_neon_type (&ntype, &p) == SUCCESS)
2648 {
2649 /* We got a type. */
2650 if (typeinfo.defined & NTA_HASTYPE)
477330fc
RM		 2651 {
2652 as_bad (_("can't redefine the type of a register alias"));
2653 return FALSE;
2654 }
5f4273c7 2655
dcbf9037
JB		 2656 typeinfo.defined |= NTA_HASTYPE;
2657 if (ntype.elems != 1)
477330fc
RM		 2658 {
2659 as_bad (_("you must specify a single type only"));
2660 return FALSE;
2661 }
dcbf9037
JB		 2662 typeinfo.eltype = ntype.el[0];
2663 }
5f4273c7 2664
dcbf9037
JB		 2665 if (skip_past_char (&p, '[') == SUCCESS)
2666 {
2667 expressionS exp;
2668 /* We got a scalar index. */
5f4273c7 2669
dcbf9037 2670 if (typeinfo.defined & NTA_HASINDEX)
477330fc
RM		 2671 {
2672 as_bad (_("can't redefine the index of a scalar alias"));
2673 return FALSE;
2674 }
5f4273c7 2675
dcbf9037 2676 my_get_expression (&exp, &p, GE_NO_PREFIX);
5f4273c7 2677
dcbf9037 2678 if (exp.X_op != O_constant)
477330fc
RM		 2679 {
2680 as_bad (_("scalar index must be constant"));
2681 return FALSE;
2682 }
5f4273c7 2683
dcbf9037
JB		 2684 typeinfo.defined |= NTA_HASINDEX;
2685 typeinfo.index = exp.X_add_number;
5f4273c7 2686
dcbf9037 2687 if (skip_past_char (&p, ']') == FAIL)
477330fc
RM		 2688 {
2689 as_bad (_("expecting ]"));
2690 return FALSE;
2691 }
dcbf9037
JB		 2692 }
2693
15735687
NS		 2694 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2695 the desired alias name, and p points to its end. If not, then
2696 the desired alias name is in the global original_case_string. */
2697#ifdef TC_CASE_SENSITIVE
dcbf9037 2698 namelen = nameend - newname;
15735687
NS		 2699#else
2700 newname = original_case_string;
2701 namelen = strlen (newname);
2702#endif
2703
29a2809e 2704 namebuf = xmemdup0 (newname, namelen);
5f4273c7 2705
dcbf9037 2706 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2707 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2708
dcbf9037
JB		 2709 /* Insert name in all uppercase. */
2710 for (p = namebuf; *p; p++)
2711 *p = TOUPPER (*p);
5f4273c7 2712
dcbf9037
JB		 2713 if (strncmp (namebuf, newname, namelen))
2714 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2715 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2716
dcbf9037
JB		 2717 /* Insert name in all lowercase. */
2718 for (p = namebuf; *p; p++)
2719 *p = TOLOWER (*p);
5f4273c7 2720
dcbf9037
JB		 2721 if (strncmp (namebuf, newname, namelen))
2722 insert_neon_reg_alias (namebuf, basereg->number, basetype,
477330fc 2723 typeinfo.defined != 0 ? &typeinfo : NULL);
5f4273c7 2724
e1fa0163 2725 free (namebuf);
c921be7d 2726 return TRUE;
dcbf9037
JB		 2727}
2728
c19d1205
ZW		 2729/* Should never be called, as .req goes between the alias and the
2730 register name, not at the beginning of the line. */
c921be7d 2731
b99bd4ef 2732static void
c19d1205 2733s_req (int a ATTRIBUTE_UNUSED)
b99bd4ef 2734{
c19d1205
ZW		 2735 as_bad (_("invalid syntax for .req directive"));
2736}
b99bd4ef 2737
dcbf9037
JB		 2738static void
2739s_dn (int a ATTRIBUTE_UNUSED)
2740{
2741 as_bad (_("invalid syntax for .dn directive"));
2742}
2743
2744static void
2745s_qn (int a ATTRIBUTE_UNUSED)
2746{
2747 as_bad (_("invalid syntax for .qn directive"));
2748}
2749
c19d1205
ZW		 2750/* The .unreq directive deletes an alias which was previously defined
2751 by .req. For example:
b99bd4ef 2752
c19d1205
ZW		 2753 my_alias .req r11
2754 .unreq my_alias */
b99bd4ef
NC		 2755
2756static void
c19d1205 2757s_unreq (int a ATTRIBUTE_UNUSED)
b99bd4ef 2758{
c19d1205
ZW		 2759 char * name;
2760 char saved_char;
b99bd4ef 2761
c19d1205
ZW		 2762 name = input_line_pointer;
2763
2764 while (*input_line_pointer != 0
2765 && *input_line_pointer != ' '
2766 && *input_line_pointer != '\n')
2767 ++input_line_pointer;
2768
2769 saved_char = *input_line_pointer;
2770 *input_line_pointer = 0;
2771
2772 if (!*name)
2773 as_bad (_("invalid syntax for .unreq directive"));
2774 else
2775 {
21d799b5 2776 struct reg_entry *reg = (struct reg_entry *) hash_find (arm_reg_hsh,
477330fc 2777 name);
c19d1205
ZW		 2778
2779 if (!reg)
2780 as_bad (_("unknown register alias '%s'"), name);
2781 else if (reg->builtin)
a1727c1a 2782 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
c19d1205
ZW		 2783 name);
2784 else
2785 {
d929913e
NC		 2786 char * p;
2787 char * nbuf;
2788
db0bc284 2789 hash_delete (arm_reg_hsh, name, FALSE);
c19d1205 2790 free ((char *) reg->name);
477330fc
RM		 2791 if (reg->neon)
2792 free (reg->neon);
c19d1205 2793 free (reg);
d929913e
NC		 2794
2795 /* Also locate the all upper case and all lower case versions.
2796 Do not complain if we cannot find one or the other as it
2797 was probably deleted above. */
5f4273c7 2798
d929913e
NC		 2799 nbuf = strdup (name);
2800 for (p = nbuf; *p; p++)
2801 *p = TOUPPER (*p);
21d799b5 2802 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2803 if (reg)
2804 {
db0bc284 2805 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2806 free ((char *) reg->name);
2807 if (reg->neon)
2808 free (reg->neon);
2809 free (reg);
2810 }
2811
2812 for (p = nbuf; *p; p++)
2813 *p = TOLOWER (*p);
21d799b5 2814 reg = (struct reg_entry *) hash_find (arm_reg_hsh, nbuf);
d929913e
NC		 2815 if (reg)
2816 {
db0bc284 2817 hash_delete (arm_reg_hsh, nbuf, FALSE);
d929913e
NC		 2818 free ((char *) reg->name);
2819 if (reg->neon)
2820 free (reg->neon);
2821 free (reg);
2822 }
2823
2824 free (nbuf);
c19d1205
ZW		 2825 }
2826 }
b99bd4ef 2827
c19d1205 2828 *input_line_pointer = saved_char;
b99bd4ef
NC		 2829 demand_empty_rest_of_line ();
2830}
2831
c19d1205
ZW		 2832/* Directives: Instruction set selection. */
2833
2834#ifdef OBJ_ELF
2835/* This code is to handle mapping symbols as defined in the ARM ELF spec.
2836 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2837 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2838 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2839
cd000bff
DJ		 2840/* Create a new mapping symbol for the transition to STATE. */
2841
2842static void
2843make_mapping_symbol (enum mstate state, valueT value, fragS *frag)
b99bd4ef 2844{
a737bd4d 2845 symbolS * symbolP;
c19d1205
ZW		 2846 const char * symname;
2847 int type;
b99bd4ef 2848
c19d1205 2849 switch (state)
b99bd4ef 2850 {
c19d1205
ZW		 2851 case MAP_DATA:
2852 symname = "$d";
2853 type = BSF_NO_FLAGS;
2854 break;
2855 case MAP_ARM:
2856 symname = "$a";
2857 type = BSF_NO_FLAGS;
2858 break;
2859 case MAP_THUMB:
2860 symname = "$t";
2861 type = BSF_NO_FLAGS;
2862 break;
c19d1205
ZW		 2863 default:
2864 abort ();
2865 }
2866
cd000bff 2867 symbolP = symbol_new (symname, now_seg, value, frag);
c19d1205
ZW		 2868 symbol_get_bfdsym (symbolP)->flags |= type | BSF_LOCAL;
2869
2870 switch (state)
2871 {
2872 case MAP_ARM:
2873 THUMB_SET_FUNC (symbolP, 0);
2874 ARM_SET_THUMB (symbolP, 0);
2875 ARM_SET_INTERWORK (symbolP, support_interwork);
2876 break;
2877
2878 case MAP_THUMB:
2879 THUMB_SET_FUNC (symbolP, 1);
2880 ARM_SET_THUMB (symbolP, 1);
2881 ARM_SET_INTERWORK (symbolP, support_interwork);
2882 break;
2883
2884 case MAP_DATA:
2885 default:
cd000bff
DJ		 2886 break;
2887 }
2888
2889 /* Save the mapping symbols for future reference. Also check that
2890 we do not place two mapping symbols at the same offset within a
2891 frag. We'll handle overlap between frags in
2de7820f
JZ		 2892 check_mapping_symbols.
2893
2894 If .fill or other data filling directive generates zero sized data,
2895 the mapping symbol for the following code will have the same value
2896 as the one generated for the data filling directive. In this case,
2897 we replace the old symbol with the new one at the same address. */
cd000bff
DJ		 2898 if (value == 0)
2899 {
2de7820f
JZ		 2900 if (frag->tc_frag_data.first_map != NULL)
2901 {
2902 know (S_GET_VALUE (frag->tc_frag_data.first_map) == 0);
2903 symbol_remove (frag->tc_frag_data.first_map, &symbol_rootP, &symbol_lastP);
2904 }
cd000bff
DJ		 2905 frag->tc_frag_data.first_map = symbolP;
2906 }
2907 if (frag->tc_frag_data.last_map != NULL)
0f020cef
JZ		 2908 {
2909 know (S_GET_VALUE (frag->tc_frag_data.last_map) <= S_GET_VALUE (symbolP));
0f020cef
JZ		 2910 if (S_GET_VALUE (frag->tc_frag_data.last_map) == S_GET_VALUE (symbolP))
2911 symbol_remove (frag->tc_frag_data.last_map, &symbol_rootP, &symbol_lastP);
2912 }
cd000bff
DJ		 2913 frag->tc_frag_data.last_map = symbolP;
2914}
2915
2916/* We must sometimes convert a region marked as code to data during
2917 code alignment, if an odd number of bytes have to be padded. The
2918 code mapping symbol is pushed to an aligned address. */
2919
2920static void
2921insert_data_mapping_symbol (enum mstate state,
2922 valueT value, fragS *frag, offsetT bytes)
2923{
2924 /* If there was already a mapping symbol, remove it. */
2925 if (frag->tc_frag_data.last_map != NULL
2926 && S_GET_VALUE (frag->tc_frag_data.last_map) == frag->fr_address + value)
2927 {
2928 symbolS *symp = frag->tc_frag_data.last_map;
2929
2930 if (value == 0)
2931 {
2932 know (frag->tc_frag_data.first_map == symp);
2933 frag->tc_frag_data.first_map = NULL;
2934 }
2935 frag->tc_frag_data.last_map = NULL;
2936 symbol_remove (symp, &symbol_rootP, &symbol_lastP);
c19d1205 2937 }
cd000bff
DJ		 2938
2939 make_mapping_symbol (MAP_DATA, value, frag);
2940 make_mapping_symbol (state, value + bytes, frag);
2941}
2942
2943static void mapping_state_2 (enum mstate state, int max_chars);
2944
2945/* Set the mapping state to STATE. Only call this when about to
2946 emit some STATE bytes to the file. */
2947
4e9aaefb 2948#define TRANSITION(from, to) (mapstate == (from) && state == (to))
cd000bff
DJ		 2949void
2950mapping_state (enum mstate state)
2951{
940b5ce0
DJ		 2952 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2953
cd000bff
DJ		 2954 if (mapstate == state)
2955 /* The mapping symbol has already been emitted.
2956 There is nothing else to do. */
2957 return;
49c62a33
NC		 2958
2959 if (state == MAP_ARM || state == MAP_THUMB)
2960 /* PR gas/12931
2961 All ARM instructions require 4-byte alignment.
2962 (Almost) all Thumb instructions require 2-byte alignment.
2963
2964 When emitting instructions into any section, mark the section
2965 appropriately.
2966
2967 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2968 but themselves require 2-byte alignment; this applies to some
33eaf5de 2969 PC- relative forms. However, these cases will involve implicit
49c62a33
NC		 2970 literal pool generation or an explicit .align >=2, both of
2971 which will cause the section to me marked with sufficient
2972 alignment. Thus, we don't handle those cases here. */
2973 record_alignment (now_seg, state == MAP_ARM ? 2 : 1);
2974
2975 if (TRANSITION (MAP_UNDEFINED, MAP_DATA))
4e9aaefb 2976 /* This case will be evaluated later. */
cd000bff 2977 return;
cd000bff
DJ		 2978
2979 mapping_state_2 (state, 0);
cd000bff
DJ		 2980}
2981
2982/* Same as mapping_state, but MAX_CHARS bytes have already been
2983 allocated. Put the mapping symbol that far back. */
2984
2985static void
2986mapping_state_2 (enum mstate state, int max_chars)
2987{
940b5ce0
DJ		 2988 enum mstate mapstate = seg_info (now_seg)->tc_segment_info_data.mapstate;
2989
2990 if (!SEG_NORMAL (now_seg))
2991 return;
2992
cd000bff
DJ		 2993 if (mapstate == state)
2994 /* The mapping symbol has already been emitted.
2995 There is nothing else to do. */
2996 return;
2997
4e9aaefb
SA		 2998 if (TRANSITION (MAP_UNDEFINED, MAP_ARM)
2999 || TRANSITION (MAP_UNDEFINED, MAP_THUMB))
3000 {
3001 struct frag * const frag_first = seg_info (now_seg)->frchainP->frch_root;
3002 const int add_symbol = (frag_now != frag_first) || (frag_now_fix () > 0);
3003
3004 if (add_symbol)
3005 make_mapping_symbol (MAP_DATA, (valueT) 0, frag_first);
3006 }
3007
cd000bff
DJ		 3008 seg_info (now_seg)->tc_segment_info_data.mapstate = state;
3009 make_mapping_symbol (state, (valueT) frag_now_fix () - max_chars, frag_now);
c19d1205 3010}
4e9aaefb 3011#undef TRANSITION
c19d1205 3012#else
d3106081
NS		 3013#define mapping_state(x) ((void)0)
3014#define mapping_state_2(x, y) ((void)0)
c19d1205
ZW		 3015#endif
3016
3017/* Find the real, Thumb encoded start of a Thumb function. */
3018
4343666d 3019#ifdef OBJ_COFF
c19d1205
ZW		 3020static symbolS *
3021find_real_start (symbolS * symbolP)
3022{
3023 char * real_start;
3024 const char * name = S_GET_NAME (symbolP);
3025 symbolS * new_target;
3026
3027 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3028#define STUB_NAME ".real_start_of"
3029
3030 if (name == NULL)
3031 abort ();
3032
37f6032b
ZW		 3033 /* The compiler may generate BL instructions to local labels because
3034 it needs to perform a branch to a far away location. These labels
3035 do not have a corresponding ".real_start_of" label. We check
3036 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3037 the ".real_start_of" convention for nonlocal branches. */
3038 if (S_IS_LOCAL (symbolP) || name[0] == '.')
c19d1205
ZW		 3039 return symbolP;
3040
e1fa0163 3041 real_start = concat (STUB_NAME, name, NULL);
c19d1205 3042 new_target = symbol_find (real_start);
e1fa0163 3043 free (real_start);
c19d1205
ZW		 3044
3045 if (new_target == NULL)
3046 {
bd3ba5d1 3047 as_warn (_("Failed to find real start of function: %s\n"), name);
c19d1205
ZW		 3048 new_target = symbolP;
3049 }
3050
c19d1205
ZW		 3051 return new_target;
3052}
4343666d 3053#endif
c19d1205
ZW		 3054
3055static void
3056opcode_select (int width)
3057{
3058 switch (width)
3059 {
3060 case 16:
3061 if (! thumb_mode)
3062 {
e74cfd16 3063 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
c19d1205
ZW		 3064 as_bad (_("selected processor does not support THUMB opcodes"));
3065
3066 thumb_mode = 1;
3067 /* No need to force the alignment, since we will have been
3068 coming from ARM mode, which is word-aligned. */
3069 record_alignment (now_seg, 1);
3070 }
c19d1205
ZW		 3071 break;
3072
3073 case 32:
3074 if (thumb_mode)
3075 {
e74cfd16 3076 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205
ZW		 3077 as_bad (_("selected processor does not support ARM opcodes"));
3078
3079 thumb_mode = 0;
3080
3081 if (!need_pass_2)
3082 frag_align (2, 0, 0);
3083
3084 record_alignment (now_seg, 1);
3085 }
c19d1205
ZW		 3086 break;
3087
3088 default:
3089 as_bad (_("invalid instruction size selected (%d)"), width);
3090 }
3091}
3092
3093static void
3094s_arm (int ignore ATTRIBUTE_UNUSED)
3095{
3096 opcode_select (32);
3097 demand_empty_rest_of_line ();
3098}
3099
3100static void
3101s_thumb (int ignore ATTRIBUTE_UNUSED)
3102{
3103 opcode_select (16);
3104 demand_empty_rest_of_line ();
3105}
3106
3107static void
3108s_code (int unused ATTRIBUTE_UNUSED)
3109{
3110 int temp;
3111
3112 temp = get_absolute_expression ();
3113 switch (temp)
3114 {
3115 case 16:
3116 case 32:
3117 opcode_select (temp);
3118 break;
3119
3120 default:
3121 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp);
3122 }
3123}
3124
3125static void
3126s_force_thumb (int ignore ATTRIBUTE_UNUSED)
3127{
3128 /* If we are not already in thumb mode go into it, EVEN if
3129 the target processor does not support thumb instructions.
3130 This is used by gcc/config/arm/lib1funcs.asm for example
3131 to compile interworking support functions even if the
3132 target processor should not support interworking. */
3133 if (! thumb_mode)
3134 {
3135 thumb_mode = 2;
3136 record_alignment (now_seg, 1);
3137 }
3138
3139 demand_empty_rest_of_line ();
3140}
3141
3142static void
3143s_thumb_func (int ignore ATTRIBUTE_UNUSED)
3144{
3145 s_thumb (0);
3146
3147 /* The following label is the name/address of the start of a Thumb function.
3148 We need to know this for the interworking support. */
3149 label_is_thumb_function_name = TRUE;
3150}
3151
3152/* Perform a .set directive, but also mark the alias as
3153 being a thumb function. */
3154
3155static void
3156s_thumb_set (int equiv)
3157{
3158 /* XXX the following is a duplicate of the code for s_set() in read.c
3159 We cannot just call that code as we need to get at the symbol that
3160 is created. */
3161 char * name;
3162 char delim;
3163 char * end_name;
3164 symbolS * symbolP;
3165
3166 /* Especial apologies for the random logic:
3167 This just grew, and could be parsed much more simply!
3168 Dean - in haste. */
d02603dc 3169 delim = get_symbol_name (& name);
c19d1205 3170 end_name = input_line_pointer;
d02603dc 3171 (void) restore_line_pointer (delim);
c19d1205
ZW		 3172
3173 if (*input_line_pointer != ',')
3174 {
3175 *end_name = 0;
3176 as_bad (_("expected comma after name \"%s\""), name);
b99bd4ef
NC		 3177 *end_name = delim;
3178 ignore_rest_of_line ();
3179 return;
3180 }
3181
3182 input_line_pointer++;
3183 *end_name = 0;
3184
3185 if (name[0] == '.' && name[1] == '\0')
3186 {
3187 /* XXX - this should not happen to .thumb_set. */
3188 abort ();
3189 }
3190
3191 if ((symbolP = symbol_find (name)) == NULL
3192 && (symbolP = md_undefined_symbol (name)) == NULL)
3193 {
3194#ifndef NO_LISTING
3195 /* When doing symbol listings, play games with dummy fragments living
3196 outside the normal fragment chain to record the file and line info
c19d1205 3197 for this symbol. */
b99bd4ef
NC		 3198 if (listing & LISTING_SYMBOLS)
3199 {
3200 extern struct list_info_struct * listing_tail;
21d799b5 3201 fragS * dummy_frag = (fragS * ) xmalloc (sizeof (fragS));
b99bd4ef
NC		 3202
3203 memset (dummy_frag, 0, sizeof (fragS));
3204 dummy_frag->fr_type = rs_fill;
3205 dummy_frag->line = listing_tail;
3206 symbolP = symbol_new (name, undefined_section, 0, dummy_frag);
3207 dummy_frag->fr_symbol = symbolP;
3208 }
3209 else
3210#endif
3211 symbolP = symbol_new (name, undefined_section, 0, &zero_address_frag);
3212
3213#ifdef OBJ_COFF
3214 /* "set" symbols are local unless otherwise specified. */
3215 SF_SET_LOCAL (symbolP);
3216#endif /* OBJ_COFF */
3217 } /* Make a new symbol. */
3218
3219 symbol_table_insert (symbolP);
3220
3221 * end_name = delim;
3222
3223 if (equiv
3224 && S_IS_DEFINED (symbolP)
3225 && S_GET_SEGMENT (symbolP) != reg_section)
3226 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP));
3227
3228 pseudo_set (symbolP);
3229
3230 demand_empty_rest_of_line ();
3231
c19d1205 3232 /* XXX Now we come to the Thumb specific bit of code. */
b99bd4ef
NC		 3233
3234 THUMB_SET_FUNC (symbolP, 1);
3235 ARM_SET_THUMB (symbolP, 1);
3236#if defined OBJ_ELF || defined OBJ_COFF
3237 ARM_SET_INTERWORK (symbolP, support_interwork);
3238#endif
3239}
3240
c19d1205 3241/* Directives: Mode selection. */
b99bd4ef 3242
c19d1205
ZW		 3243/* .syntax [unified|divided] - choose the new unified syntax
3244 (same for Arm and Thumb encoding, modulo slight differences in what
3245 can be represented) or the old divergent syntax for each mode. */
b99bd4ef 3246static void
c19d1205 3247s_syntax (int unused ATTRIBUTE_UNUSED)
b99bd4ef 3248{
c19d1205
ZW		 3249 char *name, delim;
3250
d02603dc 3251 delim = get_symbol_name (& name);
c19d1205
ZW		 3252
3253 if (!strcasecmp (name, "unified"))
3254 unified_syntax = TRUE;
3255 else if (!strcasecmp (name, "divided"))
3256 unified_syntax = FALSE;
3257 else
3258 {
3259 as_bad (_("unrecognized syntax mode \"%s\""), name);
3260 return;
3261 }
d02603dc 3262 (void) restore_line_pointer (delim);
b99bd4ef
NC		 3263 demand_empty_rest_of_line ();
3264}
3265
c19d1205
ZW		 3266/* Directives: sectioning and alignment. */
3267
c19d1205
ZW		 3268static void
3269s_bss (int ignore ATTRIBUTE_UNUSED)
b99bd4ef 3270{
c19d1205
ZW		 3271 /* We don't support putting frags in the BSS segment, we fake it by
3272 marking in_bss, then looking at s_skip for clues. */
3273 subseg_set (bss_section, 0);
3274 demand_empty_rest_of_line ();
cd000bff
DJ		 3275
3276#ifdef md_elf_section_change_hook
3277 md_elf_section_change_hook ();
3278#endif
c19d1205 3279}
b99bd4ef 3280
c19d1205
ZW		 3281static void
3282s_even (int ignore ATTRIBUTE_UNUSED)
3283{
3284 /* Never make frag if expect extra pass. */
3285 if (!need_pass_2)
3286 frag_align (1, 0, 0);
b99bd4ef 3287
c19d1205 3288 record_alignment (now_seg, 1);
b99bd4ef 3289
c19d1205 3290 demand_empty_rest_of_line ();
b99bd4ef
NC		 3291}
3292
2e6976a8
DG		 3293/* Directives: CodeComposer Studio. */
3294
3295/* .ref (for CodeComposer Studio syntax only). */
3296static void
3297s_ccs_ref (int unused ATTRIBUTE_UNUSED)
3298{
3299 if (codecomposer_syntax)
3300 ignore_rest_of_line ();
3301 else
3302 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3303}
3304
3305/* If name is not NULL, then it is used for marking the beginning of a
2b0f3761 3306 function, whereas if it is NULL then it means the function end. */
2e6976a8
DG		 3307static void
3308asmfunc_debug (const char * name)
3309{
3310 static const char * last_name = NULL;
3311
3312 if (name != NULL)
3313 {
3314 gas_assert (last_name == NULL);
3315 last_name = name;
3316
3317 if (debug_type == DEBUG_STABS)
3318 stabs_generate_asm_func (name, name);
3319 }
3320 else
3321 {
3322 gas_assert (last_name != NULL);
3323
3324 if (debug_type == DEBUG_STABS)
3325 stabs_generate_asm_endfunc (last_name, last_name);
3326
3327 last_name = NULL;
3328 }
3329}
3330
3331static void
3332s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED)
3333{
3334 if (codecomposer_syntax)
3335 {
3336 switch (asmfunc_state)
3337 {
3338 case OUTSIDE_ASMFUNC:
3339 asmfunc_state = WAITING_ASMFUNC_NAME;
3340 break;
3341
3342 case WAITING_ASMFUNC_NAME:
3343 as_bad (_(".asmfunc repeated."));
3344 break;
3345
3346 case WAITING_ENDASMFUNC:
3347 as_bad (_(".asmfunc without function."));
3348 break;
3349 }
3350 demand_empty_rest_of_line ();
3351 }
3352 else
3353 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3354}
3355
3356static void
3357s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED)
3358{
3359 if (codecomposer_syntax)
3360 {
3361 switch (asmfunc_state)
3362 {
3363 case OUTSIDE_ASMFUNC:
3364 as_bad (_(".endasmfunc without a .asmfunc."));
3365 break;
3366
3367 case WAITING_ASMFUNC_NAME:
3368 as_bad (_(".endasmfunc without function."));
3369 break;
3370
3371 case WAITING_ENDASMFUNC:
3372 asmfunc_state = OUTSIDE_ASMFUNC;
3373 asmfunc_debug (NULL);
3374 break;
3375 }
3376 demand_empty_rest_of_line ();
3377 }
3378 else
3379 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3380}
3381
3382static void
3383s_ccs_def (int name)
3384{
3385 if (codecomposer_syntax)
3386 s_globl (name);
3387 else
3388 as_bad (_(".def pseudo-op only available with -mccs flag."));
3389}
3390
c19d1205 3391/* Directives: Literal pools. */
a737bd4d 3392
c19d1205
ZW		 3393static literal_pool *
3394find_literal_pool (void)
a737bd4d 3395{
c19d1205 3396 literal_pool * pool;
a737bd4d 3397
c19d1205 3398 for (pool = list_of_pools; pool != NULL; pool = pool->next)
a737bd4d 3399 {
c19d1205
ZW		 3400 if (pool->section == now_seg
3401 && pool->sub_section == now_subseg)
3402 break;
a737bd4d
NC		 3403 }
3404
c19d1205 3405 return pool;
a737bd4d
NC		 3406}
3407
c19d1205
ZW		 3408static literal_pool *
3409find_or_make_literal_pool (void)
a737bd4d 3410{
c19d1205
ZW		 3411 /* Next literal pool ID number. */
3412 static unsigned int latest_pool_num = 1;
3413 literal_pool * pool;
a737bd4d 3414
c19d1205 3415 pool = find_literal_pool ();
a737bd4d 3416
c19d1205 3417 if (pool == NULL)
a737bd4d 3418 {
c19d1205 3419 /* Create a new pool. */
325801bd 3420 pool = XNEW (literal_pool);
c19d1205
ZW		 3421 if (! pool)
3422 return NULL;
a737bd4d 3423
c19d1205
ZW		 3424 pool->next_free_entry = 0;
3425 pool->section = now_seg;
3426 pool->sub_section = now_subseg;
3427 pool->next = list_of_pools;
3428 pool->symbol = NULL;
8335d6aa 3429 pool->alignment = 2;
c19d1205
ZW		 3430
3431 /* Add it to the list. */
3432 list_of_pools = pool;
a737bd4d 3433 }
a737bd4d 3434
c19d1205
ZW		 3435 /* New pools, and emptied pools, will have a NULL symbol. */
3436 if (pool->symbol == NULL)
a737bd4d 3437 {
c19d1205
ZW		 3438 pool->symbol = symbol_create (FAKE_LABEL_NAME, undefined_section,
3439 (valueT) 0, &zero_address_frag);
3440 pool->id = latest_pool_num ++;
a737bd4d
NC		 3441 }
3442
c19d1205
ZW		 3443 /* Done. */
3444 return pool;
a737bd4d
NC		 3445}
3446
c19d1205 3447/* Add the literal in the global 'inst'
5f4273c7 3448 structure to the relevant literal pool. */
b99bd4ef
NC		 3449
3450static int
8335d6aa 3451add_to_lit_pool (unsigned int nbytes)
b99bd4ef 3452{
8335d6aa
JW		 3453#define PADDING_SLOT 0x1
3454#define LIT_ENTRY_SIZE_MASK 0xFF
c19d1205 3455 literal_pool * pool;
8335d6aa
JW		 3456 unsigned int entry, pool_size = 0;
3457 bfd_boolean padding_slot_p = FALSE;
e56c722b 3458 unsigned imm1 = 0;
8335d6aa
JW		 3459 unsigned imm2 = 0;
3460
3461 if (nbytes == 8)
3462 {
3463 imm1 = inst.operands[1].imm;
3464 imm2 = (inst.operands[1].regisimm ? inst.operands[1].reg
e2b0ab59 3465 : inst.relocs[0].exp.X_unsigned ? 0
2569ceb0 3466 : ((bfd_int64_t) inst.operands[1].imm) >> 32);
8335d6aa
JW		 3467 if (target_big_endian)
3468 {
3469 imm1 = imm2;
3470 imm2 = inst.operands[1].imm;
3471 }
3472 }
b99bd4ef 3473
c19d1205
ZW		 3474 pool = find_or_make_literal_pool ();
3475
3476 /* Check if this literal value is already in the pool. */
3477 for (entry = 0; entry < pool->next_free_entry; entry ++)
b99bd4ef 3478 {
8335d6aa
JW		 3479 if (nbytes == 4)
3480 {
e2b0ab59
AV		 3481 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3482 && (inst.relocs[0].exp.X_op == O_constant)
8335d6aa 3483 && (pool->literals[entry].X_add_number
e2b0ab59 3484 == inst.relocs[0].exp.X_add_number)
8335d6aa
JW		 3485 && (pool->literals[entry].X_md == nbytes)
3486 && (pool->literals[entry].X_unsigned
e2b0ab59 3487 == inst.relocs[0].exp.X_unsigned))
8335d6aa
JW		 3488 break;
3489
e2b0ab59
AV		 3490 if ((pool->literals[entry].X_op == inst.relocs[0].exp.X_op)
3491 && (inst.relocs[0].exp.X_op == O_symbol)
8335d6aa 3492 && (pool->literals[entry].X_add_number
e2b0ab59 3493 == inst.relocs[0].exp.X_add_number)
8335d6aa 3494 && (pool->literals[entry].X_add_symbol
e2b0ab59 3495 == inst.relocs[0].exp.X_add_symbol)
8335d6aa 3496 && (pool->literals[entry].X_op_symbol
e2b0ab59 3497 == inst.relocs[0].exp.X_op_symbol)
8335d6aa
JW		 3498 && (pool->literals[entry].X_md == nbytes))
3499 break;
3500 }
3501 else if ((nbytes == 8)
3502 && !(pool_size & 0x7)
3503 && ((entry + 1) != pool->next_free_entry)
3504 && (pool->literals[entry].X_op == O_constant)
19f2f6a9 3505 && (pool->literals[entry].X_add_number == (offsetT) imm1)
8335d6aa 3506 && (pool->literals[entry].X_unsigned
e2b0ab59 3507 == inst.relocs[0].exp.X_unsigned)
8335d6aa 3508 && (pool->literals[entry + 1].X_op == O_constant)
19f2f6a9 3509 && (pool->literals[entry + 1].X_add_number == (offsetT) imm2)
8335d6aa 3510 && (pool->literals[entry + 1].X_unsigned
e2b0ab59 3511 == inst.relocs[0].exp.X_unsigned))
c19d1205
ZW		 3512 break;
3513
8335d6aa
JW		 3514 padding_slot_p = ((pool->literals[entry].X_md >> 8) == PADDING_SLOT);
3515 if (padding_slot_p && (nbytes == 4))
c19d1205 3516 break;
8335d6aa
JW		 3517
3518 pool_size += 4;
b99bd4ef
NC		 3519 }
3520
c19d1205
ZW		 3521 /* Do we need to create a new entry? */
3522 if (entry == pool->next_free_entry)
3523 {
3524 if (entry >= MAX_LITERAL_POOL_SIZE)
3525 {
3526 inst.error = _("literal pool overflow");
3527 return FAIL;
3528 }
3529
8335d6aa
JW		 3530 if (nbytes == 8)
3531 {
3532 /* For 8-byte entries, we align to an 8-byte boundary,
3533 and split it into two 4-byte entries, because on 32-bit
3534 host, 8-byte constants are treated as big num, thus
3535 saved in "generic_bignum" which will be overwritten
3536 by later assignments.
3537
3538 We also need to make sure there is enough space for
3539 the split.
3540
3541 We also check to make sure the literal operand is a
3542 constant number. */
e2b0ab59
AV		 3543 if (!(inst.relocs[0].exp.X_op == O_constant
3544 || inst.relocs[0].exp.X_op == O_big))
8335d6aa
JW		 3545 {
3546 inst.error = _("invalid type for literal pool");
3547 return FAIL;
3548 }
3549 else if (pool_size & 0x7)
3550 {
3551 if ((entry + 2) >= MAX_LITERAL_POOL_SIZE)
3552 {
3553 inst.error = _("literal pool overflow");
3554 return FAIL;
3555 }
3556
e2b0ab59 3557 pool->literals[entry] = inst.relocs[0].exp;
a6684f0d 3558 pool->literals[entry].X_op = O_constant;
8335d6aa
JW		 3559 pool->literals[entry].X_add_number = 0;
3560 pool->literals[entry++].X_md = (PADDING_SLOT << 8) | 4;
3561 pool->next_free_entry += 1;
3562 pool_size += 4;
3563 }
3564 else if ((entry + 1) >= MAX_LITERAL_POOL_SIZE)
3565 {
3566 inst.error = _("literal pool overflow");
3567 return FAIL;
3568 }
3569
e2b0ab59 3570 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3571 pool->literals[entry].X_op = O_constant;
3572 pool->literals[entry].X_add_number = imm1;
e2b0ab59 3573 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa 3574 pool->literals[entry++].X_md = 4;
e2b0ab59 3575 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3576 pool->literals[entry].X_op = O_constant;
3577 pool->literals[entry].X_add_number = imm2;
e2b0ab59 3578 pool->literals[entry].X_unsigned = inst.relocs[0].exp.X_unsigned;
8335d6aa
JW		 3579 pool->literals[entry].X_md = 4;
3580 pool->alignment = 3;
3581 pool->next_free_entry += 1;
3582 }
3583 else
3584 {
e2b0ab59 3585 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3586 pool->literals[entry].X_md = 4;
3587 }
3588
a8040cf2
NC		 3589#ifdef OBJ_ELF
3590 /* PR ld/12974: Record the location of the first source line to reference
3591 this entry in the literal pool. If it turns out during linking that the
3592 symbol does not exist we will be able to give an accurate line number for
3593 the (first use of the) missing reference. */
3594 if (debug_type == DEBUG_DWARF2)
3595 dwarf2_where (pool->locs + entry);
3596#endif
c19d1205
ZW		 3597 pool->next_free_entry += 1;
3598 }
8335d6aa
JW		 3599 else if (padding_slot_p)
3600 {
e2b0ab59 3601 pool->literals[entry] = inst.relocs[0].exp;
8335d6aa
JW		 3602 pool->literals[entry].X_md = nbytes;
3603 }
b99bd4ef 3604
e2b0ab59
AV		 3605 inst.relocs[0].exp.X_op = O_symbol;
3606 inst.relocs[0].exp.X_add_number = pool_size;
3607 inst.relocs[0].exp.X_add_symbol = pool->symbol;
b99bd4ef 3608
c19d1205 3609 return SUCCESS;
b99bd4ef
NC		 3610}
3611
2e6976a8 3612bfd_boolean
2e57ce7b 3613tc_start_label_without_colon (void)
2e6976a8
DG		 3614{
3615 bfd_boolean ret = TRUE;
3616
3617 if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME)
3618 {
2e57ce7b 3619 const char *label = input_line_pointer;
2e6976a8
DG		 3620
3621 while (!is_end_of_line[(int) label[-1]])
3622 --label;
3623
3624 if (*label == '.')
3625 {
3626 as_bad (_("Invalid label '%s'"), label);
3627 ret = FALSE;
3628 }
3629
3630 asmfunc_debug (label);
3631
3632 asmfunc_state = WAITING_ENDASMFUNC;
3633 }
3634
3635 return ret;
3636}
3637
c19d1205 3638/* Can't use symbol_new here, so have to create a symbol and then at
33eaf5de 3639 a later date assign it a value. That's what these functions do. */
e16bb312 3640
c19d1205
ZW		 3641static void
3642symbol_locate (symbolS * symbolP,
3643 const char * name, /* It is copied, the caller can modify. */
3644 segT segment, /* Segment identifier (SEG_<something>). */
3645 valueT valu, /* Symbol value. */
3646 fragS * frag) /* Associated fragment. */
3647{
e57e6ddc 3648 size_t name_length;
c19d1205 3649 char * preserved_copy_of_name;
e16bb312 3650
c19d1205
ZW		 3651 name_length = strlen (name) + 1; /* +1 for \0. */
3652 obstack_grow (&notes, name, name_length);
21d799b5 3653 preserved_copy_of_name = (char *) obstack_finish (&notes);
e16bb312 3654
c19d1205
ZW		 3655#ifdef tc_canonicalize_symbol_name
3656 preserved_copy_of_name =
3657 tc_canonicalize_symbol_name (preserved_copy_of_name);
3658#endif
b99bd4ef 3659
c19d1205 3660 S_SET_NAME (symbolP, preserved_copy_of_name);
b99bd4ef 3661
c19d1205
ZW		 3662 S_SET_SEGMENT (symbolP, segment);
3663 S_SET_VALUE (symbolP, valu);
3664 symbol_clear_list_pointers (symbolP);
b99bd4ef 3665
c19d1205 3666 symbol_set_frag (symbolP, frag);
b99bd4ef 3667
c19d1205
ZW		 3668 /* Link to end of symbol chain. */
3669 {
3670 extern int symbol_table_frozen;
b99bd4ef 3671
c19d1205
ZW		 3672 if (symbol_table_frozen)
3673 abort ();
3674 }
b99bd4ef 3675
c19d1205 3676 symbol_append (symbolP, symbol_lastP, & symbol_rootP, & symbol_lastP);
b99bd4ef 3677
c19d1205 3678 obj_symbol_new_hook (symbolP);
b99bd4ef 3679
c19d1205
ZW		 3680#ifdef tc_symbol_new_hook
3681 tc_symbol_new_hook (symbolP);
3682#endif
3683
3684#ifdef DEBUG_SYMS
3685 verify_symbol_chain (symbol_rootP, symbol_lastP);
3686#endif /* DEBUG_SYMS */
b99bd4ef
NC		 3687}
3688
c19d1205
ZW		 3689static void
3690s_ltorg (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 3691{
c19d1205
ZW		 3692 unsigned int entry;
3693 literal_pool * pool;
3694 char sym_name[20];
b99bd4ef 3695
c19d1205
ZW		 3696 pool = find_literal_pool ();
3697 if (pool == NULL
3698 || pool->symbol == NULL
3699 || pool->next_free_entry == 0)
3700 return;
b99bd4ef 3701
c19d1205
ZW		 3702 /* Align pool as you have word accesses.
3703 Only make a frag if we have to. */
3704 if (!need_pass_2)
8335d6aa 3705 frag_align (pool->alignment, 0, 0);
b99bd4ef 3706
c19d1205 3707 record_alignment (now_seg, 2);
b99bd4ef 3708
aaca88ef 3709#ifdef OBJ_ELF
47fc6e36
WN		 3710 seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA;
3711 make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now);
aaca88ef 3712#endif
c19d1205 3713 sprintf (sym_name, "$$lit_\002%x", pool->id);
b99bd4ef 3714
c19d1205
ZW		 3715 symbol_locate (pool->symbol, sym_name, now_seg,
3716 (valueT) frag_now_fix (), frag_now);
3717 symbol_table_insert (pool->symbol);
b99bd4ef 3718
c19d1205 3719 ARM_SET_THUMB (pool->symbol, thumb_mode);
b99bd4ef 3720
c19d1205
ZW		 3721#if defined OBJ_COFF || defined OBJ_ELF
3722 ARM_SET_INTERWORK (pool->symbol, support_interwork);
3723#endif
6c43fab6 3724
c19d1205 3725 for (entry = 0; entry < pool->next_free_entry; entry ++)
a8040cf2
NC		 3726 {
3727#ifdef OBJ_ELF
3728 if (debug_type == DEBUG_DWARF2)
3729 dwarf2_gen_line_info (frag_now_fix (), pool->locs + entry);
3730#endif
3731 /* First output the expression in the instruction to the pool. */
8335d6aa
JW		 3732 emit_expr (&(pool->literals[entry]),
3733 pool->literals[entry].X_md & LIT_ENTRY_SIZE_MASK);
a8040cf2 3734 }
b99bd4ef 3735
c19d1205
ZW		 3736 /* Mark the pool as empty. */
3737 pool->next_free_entry = 0;
3738 pool->symbol = NULL;
b99bd4ef
NC		 3739}
3740
c19d1205
ZW		 3741#ifdef OBJ_ELF
3742/* Forward declarations for functions below, in the MD interface
3743 section. */
3744static void fix_new_arm (fragS *, int, short, expressionS *, int, int);
3745static valueT create_unwind_entry (int);
3746static void start_unwind_section (const segT, int);
3747static void add_unwind_opcode (valueT, int);
3748static void flush_pending_unwind (void);
b99bd4ef 3749
c19d1205 3750/* Directives: Data. */
b99bd4ef 3751
c19d1205
ZW		 3752static void
3753s_arm_elf_cons (int nbytes)
3754{
3755 expressionS exp;
b99bd4ef 3756
c19d1205
ZW		 3757#ifdef md_flush_pending_output
3758 md_flush_pending_output ();
3759#endif
b99bd4ef 3760
c19d1205 3761 if (is_it_end_of_statement ())
b99bd4ef 3762 {
c19d1205
ZW		 3763 demand_empty_rest_of_line ();
3764 return;
b99bd4ef
NC		 3765 }
3766
c19d1205
ZW		 3767#ifdef md_cons_align
3768 md_cons_align (nbytes);
3769#endif
b99bd4ef 3770
c19d1205
ZW		 3771 mapping_state (MAP_DATA);
3772 do
b99bd4ef 3773 {
c19d1205
ZW		 3774 int reloc;
3775 char *base = input_line_pointer;
b99bd4ef 3776
c19d1205 3777 expression (& exp);
b99bd4ef 3778
c19d1205
ZW		 3779 if (exp.X_op != O_symbol)
3780 emit_expr (&exp, (unsigned int) nbytes);
3781 else
3782 {
3783 char *before_reloc = input_line_pointer;
3784 reloc = parse_reloc (&input_line_pointer);
3785 if (reloc == -1)
3786 {
3787 as_bad (_("unrecognized relocation suffix"));
3788 ignore_rest_of_line ();
3789 return;
3790 }
3791 else if (reloc == BFD_RELOC_UNUSED)
3792 emit_expr (&exp, (unsigned int) nbytes);
3793 else
3794 {
21d799b5 3795 reloc_howto_type *howto = (reloc_howto_type *)
477330fc
RM		 3796 bfd_reloc_type_lookup (stdoutput,
3797 (bfd_reloc_code_real_type) reloc);
c19d1205 3798 int size = bfd_get_reloc_size (howto);
b99bd4ef 3799
2fc8bdac
ZW		 3800 if (reloc == BFD_RELOC_ARM_PLT32)
3801 {
3802 as_bad (_("(plt) is only valid on branch targets"));
3803 reloc = BFD_RELOC_UNUSED;
3804 size = 0;
3805 }
3806
c19d1205 3807 if (size > nbytes)
992a06ee
AM		 3808 as_bad (ngettext ("%s relocations do not fit in %d byte",
3809 "%s relocations do not fit in %d bytes",
3810 nbytes),
c19d1205
ZW		 3811 howto->name, nbytes);
3812 else
3813 {
3814 /* We've parsed an expression stopping at O_symbol.
3815 But there may be more expression left now that we
3816 have parsed the relocation marker. Parse it again.
3817 XXX Surely there is a cleaner way to do this. */
3818 char *p = input_line_pointer;
3819 int offset;
325801bd 3820 char *save_buf = XNEWVEC (char, input_line_pointer - base);
e1fa0163 3821
c19d1205
ZW		 3822 memcpy (save_buf, base, input_line_pointer - base);
3823 memmove (base + (input_line_pointer - before_reloc),
3824 base, before_reloc - base);
3825
3826 input_line_pointer = base + (input_line_pointer-before_reloc);
3827 expression (&exp);
3828 memcpy (base, save_buf, p - base);
3829
3830 offset = nbytes - size;
4b1a927e
AM		 3831 p = frag_more (nbytes);
3832 memset (p, 0, nbytes);
c19d1205 3833 fix_new_exp (frag_now, p - frag_now->fr_literal + offset,
21d799b5 3834 size, &exp, 0, (enum bfd_reloc_code_real) reloc);
e1fa0163 3835 free (save_buf);
c19d1205
ZW		 3836 }
3837 }
3838 }
b99bd4ef 3839 }
c19d1205 3840 while (*input_line_pointer++ == ',');
b99bd4ef 3841
c19d1205
ZW		 3842 /* Put terminator back into stream. */
3843 input_line_pointer --;
3844 demand_empty_rest_of_line ();
b99bd4ef
NC		 3845}
3846
c921be7d
NC		 3847/* Emit an expression containing a 32-bit thumb instruction.
3848 Implementation based on put_thumb32_insn. */
3849
3850static void
3851emit_thumb32_expr (expressionS * exp)
3852{
3853 expressionS exp_high = *exp;
3854
3855 exp_high.X_add_number = (unsigned long)exp_high.X_add_number >> 16;
3856 emit_expr (& exp_high, (unsigned int) THUMB_SIZE);
3857 exp->X_add_number &= 0xffff;
3858 emit_expr (exp, (unsigned int) THUMB_SIZE);
3859}
3860
3861/* Guess the instruction size based on the opcode. */
3862
3863static int
3864thumb_insn_size (int opcode)
3865{
3866 if ((unsigned int) opcode < 0xe800u)
3867 return 2;
3868 else if ((unsigned int) opcode >= 0xe8000000u)
3869 return 4;
3870 else
3871 return 0;
3872}
3873
3874static bfd_boolean
3875emit_insn (expressionS *exp, int nbytes)
3876{
3877 int size = 0;
3878
3879 if (exp->X_op == O_constant)
3880 {
3881 size = nbytes;
3882
3883 if (size == 0)
3884 size = thumb_insn_size (exp->X_add_number);
3885
3886 if (size != 0)
3887 {
3888 if (size == 2 && (unsigned int)exp->X_add_number > 0xffffu)
3889 {
3890 as_bad (_(".inst.n operand too big. "\
3891 "Use .inst.w instead"));
3892 size = 0;
3893 }
3894 else
3895 {
5ee91343
AV		 3896 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
3897 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN, 0);
c921be7d 3898 else
5ee91343 3899 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN, 0);
c921be7d
NC		 3900
3901 if (thumb_mode && (size > THUMB_SIZE) && !target_big_endian)
3902 emit_thumb32_expr (exp);
3903 else
3904 emit_expr (exp, (unsigned int) size);
3905
3906 it_fsm_post_encode ();
3907 }
3908 }
3909 else
3910 as_bad (_("cannot determine Thumb instruction size. " \
3911 "Use .inst.n/.inst.w instead"));
3912 }
3913 else
3914 as_bad (_("constant expression required"));
3915
3916 return (size != 0);
3917}
3918
3919/* Like s_arm_elf_cons but do not use md_cons_align and
3920 set the mapping state to MAP_ARM/MAP_THUMB. */
3921
3922static void
3923s_arm_elf_inst (int nbytes)
3924{
3925 if (is_it_end_of_statement ())
3926 {
3927 demand_empty_rest_of_line ();
3928 return;
3929 }
3930
3931 /* Calling mapping_state () here will not change ARM/THUMB,
3932 but will ensure not to be in DATA state. */
3933
3934 if (thumb_mode)
3935 mapping_state (MAP_THUMB);
3936 else
3937 {
3938 if (nbytes != 0)
3939 {
3940 as_bad (_("width suffixes are invalid in ARM mode"));
3941 ignore_rest_of_line ();
3942 return;
3943 }
3944
3945 nbytes = 4;
3946
3947 mapping_state (MAP_ARM);
3948 }
3949
3950 do
3951 {
3952 expressionS exp;
3953
3954 expression (& exp);
3955
3956 if (! emit_insn (& exp, nbytes))
3957 {
3958 ignore_rest_of_line ();
3959 return;
3960 }
3961 }
3962 while (*input_line_pointer++ == ',');
3963
3964 /* Put terminator back into stream. */
3965 input_line_pointer --;
3966 demand_empty_rest_of_line ();
3967}
b99bd4ef 3968
c19d1205 3969/* Parse a .rel31 directive. */
b99bd4ef 3970
c19d1205
ZW		 3971static void
3972s_arm_rel31 (int ignored ATTRIBUTE_UNUSED)
3973{
3974 expressionS exp;
3975 char *p;
3976 valueT highbit;
b99bd4ef 3977
c19d1205
ZW		 3978 highbit = 0;
3979 if (*input_line_pointer == '1')
3980 highbit = 0x80000000;
3981 else if (*input_line_pointer != '0')
3982 as_bad (_("expected 0 or 1"));
b99bd4ef 3983
c19d1205
ZW		 3984 input_line_pointer++;
3985 if (*input_line_pointer != ',')
3986 as_bad (_("missing comma"));
3987 input_line_pointer++;
b99bd4ef 3988
c19d1205
ZW		 3989#ifdef md_flush_pending_output
3990 md_flush_pending_output ();
3991#endif
b99bd4ef 3992
c19d1205
ZW		 3993#ifdef md_cons_align
3994 md_cons_align (4);
3995#endif
b99bd4ef 3996
c19d1205 3997 mapping_state (MAP_DATA);
b99bd4ef 3998
c19d1205 3999 expression (&exp);
b99bd4ef 4000
c19d1205
ZW		 4001 p = frag_more (4);
4002 md_number_to_chars (p, highbit, 4);
4003 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 1,
4004 BFD_RELOC_ARM_PREL31);
b99bd4ef 4005
c19d1205 4006 demand_empty_rest_of_line ();
b99bd4ef
NC		 4007}
4008
c19d1205 4009/* Directives: AEABI stack-unwind tables. */
b99bd4ef 4010
c19d1205 4011/* Parse an unwind_fnstart directive. Simply records the current location. */
b99bd4ef 4012
c19d1205
ZW		 4013static void
4014s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
4015{
4016 demand_empty_rest_of_line ();
921e5f0a
PB		 4017 if (unwind.proc_start)
4018 {
c921be7d 4019 as_bad (_("duplicate .fnstart directive"));
921e5f0a
PB		 4020 return;
4021 }
4022
c19d1205
ZW		 4023 /* Mark the start of the function. */
4024 unwind.proc_start = expr_build_dot ();
b99bd4ef 4025
c19d1205
ZW		 4026 /* Reset the rest of the unwind info. */
4027 unwind.opcode_count = 0;
4028 unwind.table_entry = NULL;
4029 unwind.personality_routine = NULL;
4030 unwind.personality_index = -1;
4031 unwind.frame_size = 0;
4032 unwind.fp_offset = 0;
fdfde340 4033 unwind.fp_reg = REG_SP;
c19d1205
ZW		 4034 unwind.fp_used = 0;
4035 unwind.sp_restored = 0;
4036}
b99bd4ef 4037
b99bd4ef 4038
c19d1205
ZW		 4039/* Parse a handlerdata directive. Creates the exception handling table entry
4040 for the function. */
b99bd4ef 4041
c19d1205
ZW		 4042static void
4043s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED)
4044{
4045 demand_empty_rest_of_line ();
921e5f0a 4046 if (!unwind.proc_start)
c921be7d 4047 as_bad (MISSING_FNSTART);
921e5f0a 4048
c19d1205 4049 if (unwind.table_entry)
6decc662 4050 as_bad (_("duplicate .handlerdata directive"));
f02232aa 4051
c19d1205
ZW		 4052 create_unwind_entry (1);
4053}
a737bd4d 4054
c19d1205 4055/* Parse an unwind_fnend directive. Generates the index table entry. */
b99bd4ef 4056
c19d1205
ZW		 4057static void
4058s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED)
4059{
4060 long where;
4061 char *ptr;
4062 valueT val;
940b5ce0 4063 unsigned int marked_pr_dependency;
f02232aa 4064
c19d1205 4065 demand_empty_rest_of_line ();
f02232aa 4066
921e5f0a
PB		 4067 if (!unwind.proc_start)
4068 {
c921be7d 4069 as_bad (_(".fnend directive without .fnstart"));
921e5f0a
PB		 4070 return;
4071 }
4072
c19d1205
ZW		 4073 /* Add eh table entry. */
4074 if (unwind.table_entry == NULL)
4075 val = create_unwind_entry (0);
4076 else
4077 val = 0;
f02232aa 4078
c19d1205
ZW		 4079 /* Add index table entry. This is two words. */
4080 start_unwind_section (unwind.saved_seg, 1);
4081 frag_align (2, 0, 0);
4082 record_alignment (now_seg, 2);
b99bd4ef 4083
c19d1205 4084 ptr = frag_more (8);
5011093d 4085 memset (ptr, 0, 8);
c19d1205 4086 where = frag_now_fix () - 8;
f02232aa 4087
c19d1205
ZW		 4088 /* Self relative offset of the function start. */
4089 fix_new (frag_now, where, 4, unwind.proc_start, 0, 1,
4090 BFD_RELOC_ARM_PREL31);
f02232aa 4091
c19d1205
ZW		 4092 /* Indicate dependency on EHABI-defined personality routines to the
4093 linker, if it hasn't been done already. */
940b5ce0
DJ		 4094 marked_pr_dependency
4095 = seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency;
c19d1205
ZW		 4096 if (unwind.personality_index >= 0 && unwind.personality_index < 3
4097 && !(marked_pr_dependency & (1 << unwind.personality_index)))
4098 {
5f4273c7
NC		 4099 static const char *const name[] =
4100 {
4101 "__aeabi_unwind_cpp_pr0",
4102 "__aeabi_unwind_cpp_pr1",
4103 "__aeabi_unwind_cpp_pr2"
4104 };
c19d1205
ZW		 4105 symbolS *pr = symbol_find_or_make (name[unwind.personality_index]);
4106 fix_new (frag_now, where, 0, pr, 0, 1, BFD_RELOC_NONE);
c19d1205 4107 seg_info (now_seg)->tc_segment_info_data.marked_pr_dependency
940b5ce0 4108 |= 1 << unwind.personality_index;
c19d1205 4109 }
f02232aa 4110
c19d1205
ZW		 4111 if (val)
4112 /* Inline exception table entry. */
4113 md_number_to_chars (ptr + 4, val, 4);
4114 else
4115 /* Self relative offset of the table entry. */
4116 fix_new (frag_now, where + 4, 4, unwind.table_entry, 0, 1,
4117 BFD_RELOC_ARM_PREL31);
f02232aa 4118
c19d1205
ZW		 4119 /* Restore the original section. */
4120 subseg_set (unwind.saved_seg, unwind.saved_subseg);
921e5f0a
PB		 4121
4122 unwind.proc_start = NULL;
c19d1205 4123}
f02232aa 4124
f02232aa 4125
c19d1205 4126/* Parse an unwind_cantunwind directive. */
b99bd4ef 4127
c19d1205
ZW		 4128static void
4129s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED)
4130{
4131 demand_empty_rest_of_line ();
921e5f0a 4132 if (!unwind.proc_start)
c921be7d 4133 as_bad (MISSING_FNSTART);
921e5f0a 4134
c19d1205
ZW		 4135 if (unwind.personality_routine || unwind.personality_index != -1)
4136 as_bad (_("personality routine specified for cantunwind frame"));
b99bd4ef 4137
c19d1205
ZW		 4138 unwind.personality_index = -2;
4139}
b99bd4ef 4140
b99bd4ef 4141
c19d1205 4142/* Parse a personalityindex directive. */
b99bd4ef 4143
c19d1205
ZW		 4144static void
4145s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED)
4146{
4147 expressionS exp;
b99bd4ef 4148
921e5f0a 4149 if (!unwind.proc_start)
c921be7d 4150 as_bad (MISSING_FNSTART);
921e5f0a 4151
c19d1205
ZW		 4152 if (unwind.personality_routine || unwind.personality_index != -1)
4153 as_bad (_("duplicate .personalityindex directive"));
b99bd4ef 4154
c19d1205 4155 expression (&exp);
b99bd4ef 4156
c19d1205
ZW		 4157 if (exp.X_op != O_constant
4158 || exp.X_add_number < 0 || exp.X_add_number > 15)
b99bd4ef 4159 {
c19d1205
ZW		 4160 as_bad (_("bad personality routine number"));
4161 ignore_rest_of_line ();
4162 return;
b99bd4ef
NC		 4163 }
4164
c19d1205 4165 unwind.personality_index = exp.X_add_number;
b99bd4ef 4166
c19d1205
ZW		 4167 demand_empty_rest_of_line ();
4168}
e16bb312 4169
e16bb312 4170
c19d1205 4171/* Parse a personality directive. */
e16bb312 4172
c19d1205
ZW		 4173static void
4174s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
4175{
4176 char *name, *p, c;
a737bd4d 4177
921e5f0a 4178 if (!unwind.proc_start)
c921be7d 4179 as_bad (MISSING_FNSTART);
921e5f0a 4180
c19d1205
ZW		 4181 if (unwind.personality_routine || unwind.personality_index != -1)
4182 as_bad (_("duplicate .personality directive"));
a737bd4d 4183
d02603dc 4184 c = get_symbol_name (& name);
c19d1205 4185 p = input_line_pointer;
d02603dc
NC		 4186 if (c == '"')
4187 ++ input_line_pointer;
c19d1205
ZW		 4188 unwind.personality_routine = symbol_find_or_make (name);
4189 *p = c;
4190 demand_empty_rest_of_line ();
4191}
e16bb312 4192
e16bb312 4193
c19d1205 4194/* Parse a directive saving core registers. */
e16bb312 4195
c19d1205
ZW		 4196static void
4197s_arm_unwind_save_core (void)
e16bb312 4198{
c19d1205
ZW		 4199 valueT op;
4200 long range;
4201 int n;
e16bb312 4202
4b5a202f 4203 range = parse_reg_list (&input_line_pointer, REGLIST_RN);
c19d1205 4204 if (range == FAIL)
e16bb312 4205 {
c19d1205
ZW		 4206 as_bad (_("expected register list"));
4207 ignore_rest_of_line ();
4208 return;
4209 }
e16bb312 4210
c19d1205 4211 demand_empty_rest_of_line ();
e16bb312 4212
c19d1205
ZW		 4213 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4214 into .unwind_save {..., sp...}. We aren't bothered about the value of
4215 ip because it is clobbered by calls. */
4216 if (unwind.sp_restored && unwind.fp_reg == 12
4217 && (range & 0x3000) == 0x1000)
4218 {
4219 unwind.opcode_count--;
4220 unwind.sp_restored = 0;
4221 range = (range | 0x2000) & ~0x1000;
4222 unwind.pending_offset = 0;
4223 }
e16bb312 4224
01ae4198
DJ		 4225 /* Pop r4-r15. */
4226 if (range & 0xfff0)
c19d1205 4227 {
01ae4198
DJ		 4228 /* See if we can use the short opcodes. These pop a block of up to 8
4229 registers starting with r4, plus maybe r14. */
4230 for (n = 0; n < 8; n++)
4231 {
4232 /* Break at the first non-saved register. */
4233 if ((range & (1 << (n + 4))) == 0)
4234 break;
4235 }
4236 /* See if there are any other bits set. */
4237 if (n == 0 || (range & (0xfff0 << n) & 0xbff0) != 0)
4238 {
4239 /* Use the long form. */
4240 op = 0x8000 | ((range >> 4) & 0xfff);
4241 add_unwind_opcode (op, 2);
4242 }
0dd132b6 4243 else
01ae4198
DJ		 4244 {
4245 /* Use the short form. */
4246 if (range & 0x4000)
4247 op = 0xa8; /* Pop r14. */
4248 else
4249 op = 0xa0; /* Do not pop r14. */
4250 op |= (n - 1);
4251 add_unwind_opcode (op, 1);
4252 }
c19d1205 4253 }
0dd132b6 4254
c19d1205
ZW		 4255 /* Pop r0-r3. */
4256 if (range & 0xf)
4257 {
4258 op = 0xb100 | (range & 0xf);
4259 add_unwind_opcode (op, 2);
0dd132b6
NC		 4260 }
4261
c19d1205
ZW		 4262 /* Record the number of bytes pushed. */
4263 for (n = 0; n < 16; n++)
4264 {
4265 if (range & (1 << n))
4266 unwind.frame_size += 4;
4267 }
0dd132b6
NC		 4268}
4269
c19d1205
ZW		 4270
4271/* Parse a directive saving FPA registers. */
b99bd4ef
NC		 4272
4273static void
c19d1205 4274s_arm_unwind_save_fpa (int reg)
b99bd4ef 4275{
c19d1205
ZW		 4276 expressionS exp;
4277 int num_regs;
4278 valueT op;
b99bd4ef 4279
c19d1205
ZW		 4280 /* Get Number of registers to transfer. */
4281 if (skip_past_comma (&input_line_pointer) != FAIL)
4282 expression (&exp);
4283 else
4284 exp.X_op = O_illegal;
b99bd4ef 4285
c19d1205 4286 if (exp.X_op != O_constant)
b99bd4ef 4287 {
c19d1205
ZW		 4288 as_bad (_("expected , <constant>"));
4289 ignore_rest_of_line ();
b99bd4ef
NC		 4290 return;
4291 }
4292
c19d1205
ZW		 4293 num_regs = exp.X_add_number;
4294
4295 if (num_regs < 1 || num_regs > 4)
b99bd4ef 4296 {
c19d1205
ZW		 4297 as_bad (_("number of registers must be in the range [1:4]"));
4298 ignore_rest_of_line ();
b99bd4ef
NC		 4299 return;
4300 }
4301
c19d1205 4302 demand_empty_rest_of_line ();
b99bd4ef 4303
c19d1205
ZW		 4304 if (reg == 4)
4305 {
4306 /* Short form. */
4307 op = 0xb4 | (num_regs - 1);
4308 add_unwind_opcode (op, 1);
4309 }
b99bd4ef
NC		 4310 else
4311 {
c19d1205
ZW		 4312 /* Long form. */
4313 op = 0xc800 | (reg << 4) | (num_regs - 1);
4314 add_unwind_opcode (op, 2);
b99bd4ef 4315 }
c19d1205 4316 unwind.frame_size += num_regs * 12;
b99bd4ef
NC		 4317}
4318
c19d1205 4319
fa073d69
MS		 4320/* Parse a directive saving VFP registers for ARMv6 and above. */
4321
4322static void
4323s_arm_unwind_save_vfp_armv6 (void)
4324{
4325 int count;
4326 unsigned int start;
4327 valueT op;
4328 int num_vfpv3_regs = 0;
4329 int num_regs_below_16;
efd6b359 4330 bfd_boolean partial_match;
fa073d69 4331
efd6b359
AV		 4332 count = parse_vfp_reg_list (&input_line_pointer, &start, REGLIST_VFP_D,
4333 &partial_match);
fa073d69
MS		 4334 if (count == FAIL)
4335 {
4336 as_bad (_("expected register list"));
4337 ignore_rest_of_line ();
4338 return;
4339 }
4340
4341 demand_empty_rest_of_line ();
4342
4343 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4344 than FSTMX/FLDMX-style ones). */
4345
4346 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4347 if (start >= 16)
4348 num_vfpv3_regs = count;
4349 else if (start + count > 16)
4350 num_vfpv3_regs = start + count - 16;
4351
4352 if (num_vfpv3_regs > 0)
4353 {
4354 int start_offset = start > 16 ? start - 16 : 0;
4355 op = 0xc800 | (start_offset << 4) | (num_vfpv3_regs - 1);
4356 add_unwind_opcode (op, 2);
4357 }
4358
4359 /* Generate opcode for registers numbered in the range 0 .. 15. */
4360 num_regs_below_16 = num_vfpv3_regs > 0 ? 16 - (int) start : count;
9c2799c2 4361 gas_assert (num_regs_below_16 + num_vfpv3_regs == count);
fa073d69
MS		 4362 if (num_regs_below_16 > 0)
4363 {
4364 op = 0xc900 | (start << 4) | (num_regs_below_16 - 1);
4365 add_unwind_opcode (op, 2);
4366 }
4367
4368 unwind.frame_size += count * 8;
4369}
4370
4371
4372/* Parse a directive saving VFP registers for pre-ARMv6. */
b99bd4ef
NC		 4373
4374static void
c19d1205 4375s_arm_unwind_save_vfp (void)
b99bd4ef 4376{
c19d1205 4377 int count;
ca3f61f7 4378 unsigned int reg;
c19d1205 4379 valueT op;
efd6b359 4380 bfd_boolean partial_match;
b99bd4ef 4381
efd6b359
AV		 4382 count = parse_vfp_reg_list (&input_line_pointer, &reg, REGLIST_VFP_D,
4383 &partial_match);
c19d1205 4384 if (count == FAIL)
b99bd4ef 4385 {
c19d1205
ZW		 4386 as_bad (_("expected register list"));
4387 ignore_rest_of_line ();
b99bd4ef
NC		 4388 return;
4389 }
4390
c19d1205 4391 demand_empty_rest_of_line ();
b99bd4ef 4392
c19d1205 4393 if (reg == 8)
b99bd4ef 4394 {
c19d1205
ZW		 4395 /* Short form. */
4396 op = 0xb8 | (count - 1);
4397 add_unwind_opcode (op, 1);
b99bd4ef 4398 }
c19d1205 4399 else
b99bd4ef 4400 {
c19d1205
ZW		 4401 /* Long form. */
4402 op = 0xb300 | (reg << 4) | (count - 1);
4403 add_unwind_opcode (op, 2);
b99bd4ef 4404 }
c19d1205
ZW		 4405 unwind.frame_size += count * 8 + 4;
4406}
b99bd4ef 4407
b99bd4ef 4408
c19d1205
ZW		 4409/* Parse a directive saving iWMMXt data registers. */
4410
4411static void
4412s_arm_unwind_save_mmxwr (void)
4413{
4414 int reg;
4415 int hi_reg;
4416 int i;
4417 unsigned mask = 0;
4418 valueT op;
b99bd4ef 4419
c19d1205
ZW		 4420 if (*input_line_pointer == '{')
4421 input_line_pointer++;
b99bd4ef 4422
c19d1205 4423 do
b99bd4ef 4424 {
dcbf9037 4425 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
b99bd4ef 4426
c19d1205 4427 if (reg == FAIL)
b99bd4ef 4428 {
9b7132d3 4429 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205 4430 goto error;
b99bd4ef
NC		 4431 }
4432
c19d1205
ZW		 4433 if (mask >> reg)
4434 as_tsktsk (_("register list not in ascending order"));
4435 mask |= 1 << reg;
b99bd4ef 4436
c19d1205
ZW		 4437 if (*input_line_pointer == '-')
4438 {
4439 input_line_pointer++;
dcbf9037 4440 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWR);
c19d1205
ZW		 4441 if (hi_reg == FAIL)
4442 {
9b7132d3 4443 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWR]));
c19d1205
ZW		 4444 goto error;
4445 }
4446 else if (reg >= hi_reg)
4447 {
4448 as_bad (_("bad register range"));
4449 goto error;
4450 }
4451 for (; reg < hi_reg; reg++)
4452 mask |= 1 << reg;
4453 }
4454 }
4455 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4456
d996d970 4457 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4458
c19d1205 4459 demand_empty_rest_of_line ();
b99bd4ef 4460
708587a4 4461 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4462 the list. */
4463 flush_pending_unwind ();
b99bd4ef 4464
c19d1205 4465 for (i = 0; i < 16; i++)
b99bd4ef 4466 {
c19d1205
ZW		 4467 if (mask & (1 << i))
4468 unwind.frame_size += 8;
b99bd4ef
NC		 4469 }
4470
c19d1205
ZW		 4471 /* Attempt to combine with a previous opcode. We do this because gcc
4472 likes to output separate unwind directives for a single block of
4473 registers. */
4474 if (unwind.opcode_count > 0)
b99bd4ef 4475 {
c19d1205
ZW		 4476 i = unwind.opcodes[unwind.opcode_count - 1];
4477 if ((i & 0xf8) == 0xc0)
4478 {
4479 i &= 7;
4480 /* Only merge if the blocks are contiguous. */
4481 if (i < 6)
4482 {
4483 if ((mask & 0xfe00) == (1 << 9))
4484 {
4485 mask |= ((1 << (i + 11)) - 1) & 0xfc00;
4486 unwind.opcode_count--;
4487 }
4488 }
4489 else if (i == 6 && unwind.opcode_count >= 2)
4490 {
4491 i = unwind.opcodes[unwind.opcode_count - 2];
4492 reg = i >> 4;
4493 i &= 0xf;
b99bd4ef 4494
c19d1205
ZW		 4495 op = 0xffff << (reg - 1);
4496 if (reg > 0
87a1fd79 4497 && ((mask & op) == (1u << (reg - 1))))
c19d1205
ZW		 4498 {
4499 op = (1 << (reg + i + 1)) - 1;
4500 op &= ~((1 << reg) - 1);
4501 mask |= op;
4502 unwind.opcode_count -= 2;
4503 }
4504 }
4505 }
b99bd4ef
NC		 4506 }
4507
c19d1205
ZW		 4508 hi_reg = 15;
4509 /* We want to generate opcodes in the order the registers have been
4510 saved, ie. descending order. */
4511 for (reg = 15; reg >= -1; reg--)
b99bd4ef 4512 {
c19d1205
ZW		 4513 /* Save registers in blocks. */
4514 if (reg < 0
4515 || !(mask & (1 << reg)))
4516 {
4517 /* We found an unsaved reg. Generate opcodes to save the
5f4273c7 4518 preceding block. */
c19d1205
ZW		 4519 if (reg != hi_reg)
4520 {
4521 if (reg == 9)
4522 {
4523 /* Short form. */
4524 op = 0xc0 | (hi_reg - 10);
4525 add_unwind_opcode (op, 1);
4526 }
4527 else
4528 {
4529 /* Long form. */
4530 op = 0xc600 | ((reg + 1) << 4) | ((hi_reg - reg) - 1);
4531 add_unwind_opcode (op, 2);
4532 }
4533 }
4534 hi_reg = reg - 1;
4535 }
b99bd4ef
NC		 4536 }
4537
c19d1205
ZW		 4538 return;
4539error:
4540 ignore_rest_of_line ();
b99bd4ef
NC		 4541}
4542
4543static void
c19d1205 4544s_arm_unwind_save_mmxwcg (void)
b99bd4ef 4545{
c19d1205
ZW		 4546 int reg;
4547 int hi_reg;
4548 unsigned mask = 0;
4549 valueT op;
b99bd4ef 4550
c19d1205
ZW		 4551 if (*input_line_pointer == '{')
4552 input_line_pointer++;
b99bd4ef 4553
477330fc
RM		 4554 skip_whitespace (input_line_pointer);
4555
c19d1205 4556 do
b99bd4ef 4557 {
dcbf9037 4558 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
b99bd4ef 4559
c19d1205
ZW		 4560 if (reg == FAIL)
4561 {
9b7132d3 4562 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4563 goto error;
4564 }
b99bd4ef 4565
c19d1205
ZW		 4566 reg -= 8;
4567 if (mask >> reg)
4568 as_tsktsk (_("register list not in ascending order"));
4569 mask |= 1 << reg;
b99bd4ef 4570
c19d1205
ZW		 4571 if (*input_line_pointer == '-')
4572 {
4573 input_line_pointer++;
dcbf9037 4574 hi_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_MMXWCG);
c19d1205
ZW		 4575 if (hi_reg == FAIL)
4576 {
9b7132d3 4577 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_MMXWCG]));
c19d1205
ZW		 4578 goto error;
4579 }
4580 else if (reg >= hi_reg)
4581 {
4582 as_bad (_("bad register range"));
4583 goto error;
4584 }
4585 for (; reg < hi_reg; reg++)
4586 mask |= 1 << reg;
4587 }
b99bd4ef 4588 }
c19d1205 4589 while (skip_past_comma (&input_line_pointer) != FAIL);
b99bd4ef 4590
d996d970 4591 skip_past_char (&input_line_pointer, '}');
b99bd4ef 4592
c19d1205
ZW		 4593 demand_empty_rest_of_line ();
4594
708587a4 4595 /* Generate any deferred opcodes because we're going to be looking at
c19d1205
ZW		 4596 the list. */
4597 flush_pending_unwind ();
b99bd4ef 4598
c19d1205 4599 for (reg = 0; reg < 16; reg++)
b99bd4ef 4600 {
c19d1205
ZW		 4601 if (mask & (1 << reg))
4602 unwind.frame_size += 4;
b99bd4ef 4603 }
c19d1205
ZW		 4604 op = 0xc700 | mask;
4605 add_unwind_opcode (op, 2);
4606 return;
4607error:
4608 ignore_rest_of_line ();
b99bd4ef
NC		 4609}
4610
c19d1205 4611
fa073d69
MS		 4612/* Parse an unwind_save directive.
4613 If the argument is non-zero, this is a .vsave directive. */
c19d1205 4614
b99bd4ef 4615static void
fa073d69 4616s_arm_unwind_save (int arch_v6)
b99bd4ef 4617{
c19d1205
ZW		 4618 char *peek;
4619 struct reg_entry *reg;
4620 bfd_boolean had_brace = FALSE;
b99bd4ef 4621
921e5f0a 4622 if (!unwind.proc_start)
c921be7d 4623 as_bad (MISSING_FNSTART);
921e5f0a 4624
c19d1205
ZW		 4625 /* Figure out what sort of save we have. */
4626 peek = input_line_pointer;
b99bd4ef 4627
c19d1205 4628 if (*peek == '{')
b99bd4ef 4629 {
c19d1205
ZW		 4630 had_brace = TRUE;
4631 peek++;
b99bd4ef
NC		 4632 }
4633
c19d1205 4634 reg = arm_reg_parse_multi (&peek);
b99bd4ef 4635
c19d1205 4636 if (!reg)
b99bd4ef 4637 {
c19d1205
ZW		 4638 as_bad (_("register expected"));
4639 ignore_rest_of_line ();
b99bd4ef
NC		 4640 return;
4641 }
4642
c19d1205 4643 switch (reg->type)
b99bd4ef 4644 {
c19d1205
ZW		 4645 case REG_TYPE_FN:
4646 if (had_brace)
4647 {
4648 as_bad (_("FPA .unwind_save does not take a register list"));
4649 ignore_rest_of_line ();
4650 return;
4651 }
93ac2687 4652 input_line_pointer = peek;
c19d1205 4653 s_arm_unwind_save_fpa (reg->number);
b99bd4ef 4654 return;
c19d1205 4655
1f5afe1c
NC		 4656 case REG_TYPE_RN:
4657 s_arm_unwind_save_core ();
4658 return;
4659
fa073d69
MS		 4660 case REG_TYPE_VFD:
4661 if (arch_v6)
477330fc 4662 s_arm_unwind_save_vfp_armv6 ();
fa073d69 4663 else
477330fc 4664 s_arm_unwind_save_vfp ();
fa073d69 4665 return;
1f5afe1c
NC		 4666
4667 case REG_TYPE_MMXWR:
4668 s_arm_unwind_save_mmxwr ();
4669 return;
4670
4671 case REG_TYPE_MMXWCG:
4672 s_arm_unwind_save_mmxwcg ();
4673 return;
c19d1205
ZW		 4674
4675 default:
4676 as_bad (_(".unwind_save does not support this kind of register"));
4677 ignore_rest_of_line ();
b99bd4ef 4678 }
c19d1205 4679}
b99bd4ef 4680
b99bd4ef 4681
c19d1205
ZW		 4682/* Parse an unwind_movsp directive. */
4683
4684static void
4685s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED)
4686{
4687 int reg;
4688 valueT op;
4fa3602b 4689 int offset;
c19d1205 4690
921e5f0a 4691 if (!unwind.proc_start)
c921be7d 4692 as_bad (MISSING_FNSTART);
921e5f0a 4693
dcbf9037 4694 reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205 4695 if (reg == FAIL)
b99bd4ef 4696 {
9b7132d3 4697 as_bad ("%s", _(reg_expected_msgs[REG_TYPE_RN]));
c19d1205 4698 ignore_rest_of_line ();
b99bd4ef
NC		 4699 return;
4700 }
4fa3602b
PB		 4701
4702 /* Optional constant. */
4703 if (skip_past_comma (&input_line_pointer) != FAIL)
4704 {
4705 if (immediate_for_directive (&offset) == FAIL)
4706 return;
4707 }
4708 else
4709 offset = 0;
4710
c19d1205 4711 demand_empty_rest_of_line ();
b99bd4ef 4712
c19d1205 4713 if (reg == REG_SP || reg == REG_PC)
b99bd4ef 4714 {
c19d1205 4715 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
b99bd4ef
NC		 4716 return;
4717 }
4718
c19d1205
ZW		 4719 if (unwind.fp_reg != REG_SP)
4720 as_bad (_("unexpected .unwind_movsp directive"));
b99bd4ef 4721
c19d1205
ZW		 4722 /* Generate opcode to restore the value. */
4723 op = 0x90 | reg;
4724 add_unwind_opcode (op, 1);
4725
4726 /* Record the information for later. */
4727 unwind.fp_reg = reg;
4fa3602b 4728 unwind.fp_offset = unwind.frame_size - offset;
c19d1205 4729 unwind.sp_restored = 1;
b05fe5cf
ZW		 4730}
4731
c19d1205
ZW		 4732/* Parse an unwind_pad directive. */
4733
b05fe5cf 4734static void
c19d1205 4735s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED)
b05fe5cf 4736{
c19d1205 4737 int offset;
b05fe5cf 4738
921e5f0a 4739 if (!unwind.proc_start)
c921be7d 4740 as_bad (MISSING_FNSTART);
921e5f0a 4741
c19d1205
ZW		 4742 if (immediate_for_directive (&offset) == FAIL)
4743 return;
b99bd4ef 4744
c19d1205
ZW		 4745 if (offset & 3)
4746 {
4747 as_bad (_("stack increment must be multiple of 4"));
4748 ignore_rest_of_line ();
4749 return;
4750 }
b99bd4ef 4751
c19d1205
ZW		 4752 /* Don't generate any opcodes, just record the details for later. */
4753 unwind.frame_size += offset;
4754 unwind.pending_offset += offset;
4755
4756 demand_empty_rest_of_line ();
4757}
4758
4759/* Parse an unwind_setfp directive. */
4760
4761static void
4762s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED)
b99bd4ef 4763{
c19d1205
ZW		 4764 int sp_reg;
4765 int fp_reg;
4766 int offset;
4767
921e5f0a 4768 if (!unwind.proc_start)
c921be7d 4769 as_bad (MISSING_FNSTART);
921e5f0a 4770
dcbf9037 4771 fp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
c19d1205
ZW		 4772 if (skip_past_comma (&input_line_pointer) == FAIL)
4773 sp_reg = FAIL;
4774 else
dcbf9037 4775 sp_reg = arm_reg_parse (&input_line_pointer, REG_TYPE_RN);
b99bd4ef 4776
c19d1205
ZW		 4777 if (fp_reg == FAIL || sp_reg == FAIL)
4778 {
4779 as_bad (_("expected <reg>, <reg>"));
4780 ignore_rest_of_line ();
4781 return;
4782 }
b99bd4ef 4783
c19d1205
ZW		 4784 /* Optional constant. */
4785 if (skip_past_comma (&input_line_pointer) != FAIL)
4786 {
4787 if (immediate_for_directive (&offset) == FAIL)
4788 return;
4789 }
4790 else
4791 offset = 0;
a737bd4d 4792
c19d1205 4793 demand_empty_rest_of_line ();
a737bd4d 4794
fdfde340 4795 if (sp_reg != REG_SP && sp_reg != unwind.fp_reg)
a737bd4d 4796 {
c19d1205
ZW		 4797 as_bad (_("register must be either sp or set by a previous"
4798 "unwind_movsp directive"));
4799 return;
a737bd4d
NC		 4800 }
4801
c19d1205
ZW		 4802 /* Don't generate any opcodes, just record the information for later. */
4803 unwind.fp_reg = fp_reg;
4804 unwind.fp_used = 1;
fdfde340 4805 if (sp_reg == REG_SP)
c19d1205
ZW		 4806 unwind.fp_offset = unwind.frame_size - offset;
4807 else
4808 unwind.fp_offset -= offset;
a737bd4d
NC		 4809}
4810
c19d1205
ZW		 4811/* Parse an unwind_raw directive. */
4812
4813static void
4814s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED)
a737bd4d 4815{
c19d1205 4816 expressionS exp;
708587a4 4817 /* This is an arbitrary limit. */
c19d1205
ZW		 4818 unsigned char op[16];
4819 int count;
a737bd4d 4820
921e5f0a 4821 if (!unwind.proc_start)
c921be7d 4822 as_bad (MISSING_FNSTART);
921e5f0a 4823
c19d1205
ZW		 4824 expression (&exp);
4825 if (exp.X_op == O_constant
4826 && skip_past_comma (&input_line_pointer) != FAIL)
a737bd4d 4827 {
c19d1205
ZW		 4828 unwind.frame_size += exp.X_add_number;
4829 expression (&exp);
4830 }
4831 else
4832 exp.X_op = O_illegal;
a737bd4d 4833
c19d1205
ZW		 4834 if (exp.X_op != O_constant)
4835 {
4836 as_bad (_("expected <offset>, <opcode>"));
4837 ignore_rest_of_line ();
4838 return;
4839 }
a737bd4d 4840
c19d1205 4841 count = 0;
a737bd4d 4842
c19d1205
ZW		 4843 /* Parse the opcode. */
4844 for (;;)
4845 {
4846 if (count >= 16)
4847 {
4848 as_bad (_("unwind opcode too long"));
4849 ignore_rest_of_line ();
a737bd4d 4850 }
c19d1205 4851 if (exp.X_op != O_constant || exp.X_add_number & ~0xff)
a737bd4d 4852 {
c19d1205
ZW		 4853 as_bad (_("invalid unwind opcode"));
4854 ignore_rest_of_line ();
4855 return;
a737bd4d 4856 }
c19d1205 4857 op[count++] = exp.X_add_number;
a737bd4d 4858
c19d1205
ZW		 4859 /* Parse the next byte. */
4860 if (skip_past_comma (&input_line_pointer) == FAIL)
4861 break;
a737bd4d 4862
c19d1205
ZW		 4863 expression (&exp);
4864 }
b99bd4ef 4865
c19d1205
ZW		 4866 /* Add the opcode bytes in reverse order. */
4867 while (count--)
4868 add_unwind_opcode (op[count], 1);
b99bd4ef 4869
c19d1205 4870 demand_empty_rest_of_line ();
b99bd4ef 4871}
ee065d83
PB		 4872
4873
4874/* Parse a .eabi_attribute directive. */
4875
4876static void
4877s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED)
4878{
0420f52b 4879 int tag = obj_elf_vendor_attribute (OBJ_ATTR_PROC);
ee3c0378 4880
3076e594 4881 if (tag >= 0 && tag < NUM_KNOWN_OBJ_ATTRIBUTES)
ee3c0378 4882 attributes_set_explicitly[tag] = 1;
ee065d83
PB		 4883}
4884
0855e32b
NS		 4885/* Emit a tls fix for the symbol. */
4886
4887static void
4888s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED)
4889{
4890 char *p;
4891 expressionS exp;
4892#ifdef md_flush_pending_output
4893 md_flush_pending_output ();
4894#endif
4895
4896#ifdef md_cons_align
4897 md_cons_align (4);
4898#endif
4899
4900 /* Since we're just labelling the code, there's no need to define a
4901 mapping symbol. */
4902 expression (&exp);
4903 p = obstack_next_free (&frchain_now->frch_obstack);
4904 fix_new_arm (frag_now, p - frag_now->fr_literal, 4, &exp, 0,
4905 thumb_mode ? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4906 : BFD_RELOC_ARM_TLS_DESCSEQ);
4907}
cdf9ccec 4908#endif /* OBJ_ELF */
0855e32b 4909
ee065d83 4910static void s_arm_arch (int);
7a1d4c38 4911static void s_arm_object_arch (int);
ee065d83
PB		 4912static void s_arm_cpu (int);
4913static void s_arm_fpu (int);
69133863 4914static void s_arm_arch_extension (int);
b99bd4ef 4915
f0927246
NC		 4916#ifdef TE_PE
4917
4918static void
5f4273c7 4919pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
f0927246
NC		 4920{
4921 expressionS exp;
4922
4923 do
4924 {
4925 expression (&exp);
4926 if (exp.X_op == O_symbol)
4927 exp.X_op = O_secrel;
4928
4929 emit_expr (&exp, 4);
4930 }
4931 while (*input_line_pointer++ == ',');
4932
4933 input_line_pointer--;
4934 demand_empty_rest_of_line ();
4935}
4936#endif /* TE_PE */
4937
5312fe52
BW		 4938int
4939arm_is_largest_exponent_ok (int precision)
4940{
4941 /* precision == 1 ensures that this will only return
4942 true for 16 bit floats. */
4943 return (precision == 1) && (fp16_format == ARM_FP16_FORMAT_ALTERNATIVE);
4944}
4945
4946static void
4947set_fp16_format (int dummy ATTRIBUTE_UNUSED)
4948{
4949 char saved_char;
4950 char* name;
4951 enum fp_16bit_format new_format;
4952
4953 new_format = ARM_FP16_FORMAT_DEFAULT;
4954
4955 name = input_line_pointer;
4956 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
4957 input_line_pointer++;
4958
4959 saved_char = *input_line_pointer;
4960 *input_line_pointer = 0;
4961
4962 if (strcasecmp (name, "ieee") == 0)
4963 new_format = ARM_FP16_FORMAT_IEEE;
4964 else if (strcasecmp (name, "alternative") == 0)
4965 new_format = ARM_FP16_FORMAT_ALTERNATIVE;
4966 else
4967 {
4968 as_bad (_("unrecognised float16 format \"%s\""), name);
4969 goto cleanup;
4970 }
4971
4972 /* Only set fp16_format if it is still the default (aka not already
4973 been set yet). */
4974 if (fp16_format == ARM_FP16_FORMAT_DEFAULT)
4975 fp16_format = new_format;
4976 else
4977 {
4978 if (new_format != fp16_format)
4979 as_warn (_("float16 format cannot be set more than once, ignoring."));
4980 }
4981
4982cleanup:
4983 *input_line_pointer = saved_char;
4984 ignore_rest_of_line ();
4985}
4986
c19d1205
ZW		 4987/* This table describes all the machine specific pseudo-ops the assembler
4988 has to support. The fields are:
4989 pseudo-op name without dot
4990 function to call to execute this pseudo-op
4991 Integer arg to pass to the function. */
b99bd4ef 4992
c19d1205 4993const pseudo_typeS md_pseudo_table[] =
b99bd4ef 4994{
c19d1205
ZW		 4995 /* Never called because '.req' does not start a line. */
4996 { "req", s_req, 0 },
dcbf9037
JB		 4997 /* Following two are likewise never called. */
4998 { "dn", s_dn, 0 },
4999 { "qn", s_qn, 0 },
c19d1205
ZW		 5000 { "unreq", s_unreq, 0 },
5001 { "bss", s_bss, 0 },
db2ed2e0 5002 { "align", s_align_ptwo, 2 },
c19d1205
ZW		 5003 { "arm", s_arm, 0 },
5004 { "thumb", s_thumb, 0 },
5005 { "code", s_code, 0 },
5006 { "force_thumb", s_force_thumb, 0 },
5007 { "thumb_func", s_thumb_func, 0 },
5008 { "thumb_set", s_thumb_set, 0 },
5009 { "even", s_even, 0 },
5010 { "ltorg", s_ltorg, 0 },
5011 { "pool", s_ltorg, 0 },
5012 { "syntax", s_syntax, 0 },
8463be01
PB		 5013 { "cpu", s_arm_cpu, 0 },
5014 { "arch", s_arm_arch, 0 },
7a1d4c38 5015 { "object_arch", s_arm_object_arch, 0 },
8463be01 5016 { "fpu", s_arm_fpu, 0 },
69133863 5017 { "arch_extension", s_arm_arch_extension, 0 },
c19d1205 5018#ifdef OBJ_ELF
c921be7d
NC		 5019 { "word", s_arm_elf_cons, 4 },
5020 { "long", s_arm_elf_cons, 4 },
5021 { "inst.n", s_arm_elf_inst, 2 },
5022 { "inst.w", s_arm_elf_inst, 4 },
5023 { "inst", s_arm_elf_inst, 0 },
5024 { "rel31", s_arm_rel31, 0 },
c19d1205
ZW		 5025 { "fnstart", s_arm_unwind_fnstart, 0 },
5026 { "fnend", s_arm_unwind_fnend, 0 },
5027 { "cantunwind", s_arm_unwind_cantunwind, 0 },
5028 { "personality", s_arm_unwind_personality, 0 },
5029 { "personalityindex", s_arm_unwind_personalityindex, 0 },
5030 { "handlerdata", s_arm_unwind_handlerdata, 0 },
5031 { "save", s_arm_unwind_save, 0 },
fa073d69 5032 { "vsave", s_arm_unwind_save, 1 },
c19d1205
ZW		 5033 { "movsp", s_arm_unwind_movsp, 0 },
5034 { "pad", s_arm_unwind_pad, 0 },
5035 { "setfp", s_arm_unwind_setfp, 0 },
5036 { "unwind_raw", s_arm_unwind_raw, 0 },
ee065d83 5037 { "eabi_attribute", s_arm_eabi_attribute, 0 },
0855e32b 5038 { "tlsdescseq", s_arm_tls_descseq, 0 },
c19d1205
ZW		 5039#else
5040 { "word", cons, 4},
f0927246
NC		 5041
5042 /* These are used for dwarf. */
5043 {"2byte", cons, 2},
5044 {"4byte", cons, 4},
5045 {"8byte", cons, 8},
5046 /* These are used for dwarf2. */
68d20676 5047 { "file", dwarf2_directive_file, 0 },
f0927246
NC		 5048 { "loc", dwarf2_directive_loc, 0 },
5049 { "loc_mark_labels", dwarf2_directive_loc_mark_labels, 0 },
c19d1205
ZW		 5050#endif
5051 { "extend", float_cons, 'x' },
5052 { "ldouble", float_cons, 'x' },
5053 { "packed", float_cons, 'p' },
f0927246
NC		 5054#ifdef TE_PE
5055 {"secrel32", pe_directive_secrel, 0},
5056#endif
2e6976a8
DG		 5057
5058 /* These are for compatibility with CodeComposer Studio. */
5059 {"ref", s_ccs_ref, 0},
5060 {"def", s_ccs_def, 0},
5061 {"asmfunc", s_ccs_asmfunc, 0},
5062 {"endasmfunc", s_ccs_endasmfunc, 0},
5063
5312fe52
BW		 5064 {"float16", float_cons, 'h' },
5065 {"float16_format", set_fp16_format, 0 },
5066
c19d1205
ZW		 5067 { 0, 0, 0 }
5068};
5312fe52 5069
c19d1205 5070/* Parser functions used exclusively in instruction operands. */
b99bd4ef 5071
c19d1205
ZW		 5072/* Generic immediate-value read function for use in insn parsing.
5073 STR points to the beginning of the immediate (the leading #);
5074 VAL receives the value; if the value is outside [MIN, MAX]
5075 issue an error. PREFIX_OPT is true if the immediate prefix is
5076 optional. */
b99bd4ef 5077
c19d1205
ZW		 5078static int
5079parse_immediate (char **str, int *val, int min, int max,
5080 bfd_boolean prefix_opt)
5081{
5082 expressionS exp;
0198d5e6 5083
c19d1205
ZW		 5084 my_get_expression (&exp, str, prefix_opt ? GE_OPT_PREFIX : GE_IMM_PREFIX);
5085 if (exp.X_op != O_constant)
b99bd4ef 5086 {
c19d1205
ZW		 5087 inst.error = _("constant expression required");
5088 return FAIL;
5089 }
b99bd4ef 5090
c19d1205
ZW		 5091 if (exp.X_add_number < min || exp.X_add_number > max)
5092 {
5093 inst.error = _("immediate value out of range");
5094 return FAIL;
5095 }
b99bd4ef 5096
c19d1205
ZW		 5097 *val = exp.X_add_number;
5098 return SUCCESS;
5099}
b99bd4ef 5100
5287ad62 5101/* Less-generic immediate-value read function with the possibility of loading a
036dc3f7 5102 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5287ad62
JB		 5103 instructions. Puts the result directly in inst.operands[i]. */
5104
5105static int
8335d6aa
JW		 5106parse_big_immediate (char **str, int i, expressionS *in_exp,
5107 bfd_boolean allow_symbol_p)
5287ad62
JB		 5108{
5109 expressionS exp;
8335d6aa 5110 expressionS *exp_p = in_exp ? in_exp : &exp;
5287ad62
JB		 5111 char *ptr = *str;
5112
8335d6aa 5113 my_get_expression (exp_p, &ptr, GE_OPT_PREFIX_BIG);
5287ad62 5114
8335d6aa 5115 if (exp_p->X_op == O_constant)
036dc3f7 5116 {
8335d6aa 5117 inst.operands[i].imm = exp_p->X_add_number & 0xffffffff;
036dc3f7
PB		 5118 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5119 O_constant. We have to be careful not to break compilation for
5120 32-bit X_add_number, though. */
8335d6aa 5121 if ((exp_p->X_add_number & ~(offsetT)(0xffffffffU)) != 0)
036dc3f7 5122 {
8335d6aa
JW		 5123 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5124 inst.operands[i].reg = (((exp_p->X_add_number >> 16) >> 16)
5125 & 0xffffffff);
036dc3f7
PB		 5126 inst.operands[i].regisimm = 1;
5127 }
5128 }
8335d6aa
JW		 5129 else if (exp_p->X_op == O_big
5130 && LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 32)
5287ad62
JB		 5131 {
5132 unsigned parts = 32 / LITTLENUM_NUMBER_OF_BITS, j, idx = 0;
95b75c01 5133
5287ad62 5134 /* Bignums have their least significant bits in
477330fc
RM		 5135 generic_bignum[0]. Make sure we put 32 bits in imm and
5136 32 bits in reg, in a (hopefully) portable way. */
9c2799c2 5137 gas_assert (parts != 0);
95b75c01
NC		 5138
5139 /* Make sure that the number is not too big.
5140 PR 11972: Bignums can now be sign-extended to the
5141 size of a .octa so check that the out of range bits
5142 are all zero or all one. */
8335d6aa 5143 if (LITTLENUM_NUMBER_OF_BITS * exp_p->X_add_number > 64)
95b75c01
NC		 5144 {
5145 LITTLENUM_TYPE m = -1;
5146
5147 if (generic_bignum[parts * 2] != 0
5148 && generic_bignum[parts * 2] != m)
5149 return FAIL;
5150
8335d6aa 5151 for (j = parts * 2 + 1; j < (unsigned) exp_p->X_add_number; j++)
95b75c01
NC		 5152 if (generic_bignum[j] != generic_bignum[j-1])
5153 return FAIL;
5154 }
5155
5287ad62
JB		 5156 inst.operands[i].imm = 0;
5157 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 5158 inst.operands[i].imm |= generic_bignum[idx]
5159 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 5160 inst.operands[i].reg = 0;
5161 for (j = 0; j < parts; j++, idx++)
477330fc
RM		 5162 inst.operands[i].reg |= generic_bignum[idx]
5163 << (LITTLENUM_NUMBER_OF_BITS * j);
5287ad62
JB		 5164 inst.operands[i].regisimm = 1;
5165 }
8335d6aa 5166 else if (!(exp_p->X_op == O_symbol && allow_symbol_p))
5287ad62 5167 return FAIL;
5f4273c7 5168
5287ad62
JB		 5169 *str = ptr;
5170
5171 return SUCCESS;
5172}
5173
c19d1205
ZW		 5174/* Returns the pseudo-register number of an FPA immediate constant,
5175 or FAIL if there isn't a valid constant here. */
b99bd4ef 5176
c19d1205
ZW		 5177static int
5178parse_fpa_immediate (char ** str)
5179{
5180 LITTLENUM_TYPE words[MAX_LITTLENUMS];
5181 char * save_in;
5182 expressionS exp;
5183 int i;
5184 int j;
b99bd4ef 5185
c19d1205
ZW		 5186 /* First try and match exact strings, this is to guarantee
5187 that some formats will work even for cross assembly. */
b99bd4ef 5188
c19d1205
ZW		 5189 for (i = 0; fp_const[i]; i++)
5190 {
5191 if (strncmp (*str, fp_const[i], strlen (fp_const[i])) == 0)
b99bd4ef 5192 {
c19d1205 5193 char *start = *str;
b99bd4ef 5194
c19d1205
ZW		 5195 *str += strlen (fp_const[i]);
5196 if (is_end_of_line[(unsigned char) **str])
5197 return i + 8;
5198 *str = start;
5199 }
5200 }
b99bd4ef 5201
c19d1205
ZW		 5202 /* Just because we didn't get a match doesn't mean that the constant
5203 isn't valid, just that it is in a format that we don't
5204 automatically recognize. Try parsing it with the standard
5205 expression routines. */
b99bd4ef 5206
c19d1205 5207 memset (words, 0, MAX_LITTLENUMS * sizeof (LITTLENUM_TYPE));
b99bd4ef 5208
c19d1205
ZW		 5209 /* Look for a raw floating point number. */
5210 if ((save_in = atof_ieee (*str, 'x', words)) != NULL
5211 && is_end_of_line[(unsigned char) *save_in])
5212 {
5213 for (i = 0; i < NUM_FLOAT_VALS; i++)
5214 {
5215 for (j = 0; j < MAX_LITTLENUMS; j++)
b99bd4ef 5216 {
c19d1205
ZW		 5217 if (words[j] != fp_values[i][j])
5218 break;
b99bd4ef
NC		 5219 }
5220
c19d1205 5221 if (j == MAX_LITTLENUMS)
b99bd4ef 5222 {
c19d1205
ZW		 5223 *str = save_in;
5224 return i + 8;
b99bd4ef
NC		 5225 }
5226 }
5227 }
b99bd4ef 5228
c19d1205
ZW		 5229 /* Try and parse a more complex expression, this will probably fail
5230 unless the code uses a floating point prefix (eg "0f"). */
5231 save_in = input_line_pointer;
5232 input_line_pointer = *str;
5233 if (expression (&exp) == absolute_section
5234 && exp.X_op == O_big
5235 && exp.X_add_number < 0)
5236 {
5237 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5238 Ditto for 15. */
ba592044
AM		 5239#define X_PRECISION 5
5240#define E_PRECISION 15L
5241 if (gen_to_words (words, X_PRECISION, E_PRECISION) == 0)
c19d1205
ZW		 5242 {
5243 for (i = 0; i < NUM_FLOAT_VALS; i++)
5244 {
5245 for (j = 0; j < MAX_LITTLENUMS; j++)
5246 {
5247 if (words[j] != fp_values[i][j])
5248 break;
5249 }
b99bd4ef 5250
c19d1205
ZW		 5251 if (j == MAX_LITTLENUMS)
5252 {
5253 *str = input_line_pointer;
5254 input_line_pointer = save_in;
5255 return i + 8;
5256 }
5257 }
5258 }
b99bd4ef
NC		 5259 }
5260
c19d1205
ZW		 5261 *str = input_line_pointer;
5262 input_line_pointer = save_in;
5263 inst.error = _("invalid FPA immediate expression");
5264 return FAIL;
b99bd4ef
NC		 5265}
5266
136da414
JB		 5267/* Returns 1 if a number has "quarter-precision" float format
5268 0baBbbbbbc defgh000 00000000 00000000. */
5269
5270static int
5271is_quarter_float (unsigned imm)
5272{
5273 int bs = (imm & 0x20000000) ? 0x3e000000 : 0x40000000;
5274 return (imm & 0x7ffff) == 0 && ((imm & 0x7e000000) ^ bs) == 0;
5275}
5276
aacf0b33
KT		 5277
5278/* Detect the presence of a floating point or integer zero constant,
5279 i.e. #0.0 or #0. */
5280
5281static bfd_boolean
5282parse_ifimm_zero (char **in)
5283{
5284 int error_code;
5285
5286 if (!is_immediate_prefix (**in))
3c6452ae
TP		 5287 {
5288 /* In unified syntax, all prefixes are optional. */
5289 if (!unified_syntax)
5290 return FALSE;
5291 }
5292 else
5293 ++*in;
0900a05b
JW		 5294
5295 /* Accept #0x0 as a synonym for #0. */
5296 if (strncmp (*in, "0x", 2) == 0)
5297 {
5298 int val;
5299 if (parse_immediate (in, &val, 0, 0, TRUE) == FAIL)
5300 return FALSE;
5301 return TRUE;
5302 }
5303
aacf0b33
KT		 5304 error_code = atof_generic (in, ".", EXP_CHARS,
5305 &generic_floating_point_number);
5306
5307 if (!error_code
5308 && generic_floating_point_number.sign == '+'
5309 && (generic_floating_point_number.low
5310 > generic_floating_point_number.leader))
5311 return TRUE;
5312
5313 return FALSE;
5314}
5315
136da414
JB		 5316/* Parse an 8-bit "quarter-precision" floating point number of the form:
5317 0baBbbbbbc defgh000 00000000 00000000.
c96612cc
JB		 5318 The zero and minus-zero cases need special handling, since they can't be
5319 encoded in the "quarter-precision" float format, but can nonetheless be
5320 loaded as integer constants. */
136da414
JB		 5321
5322static unsigned
5323parse_qfloat_immediate (char **ccp, int *immed)
5324{
5325 char *str = *ccp;
c96612cc 5326 char *fpnum;
136da414 5327 LITTLENUM_TYPE words[MAX_LITTLENUMS];
c96612cc 5328 int found_fpchar = 0;
5f4273c7 5329
136da414 5330 skip_past_char (&str, '#');
5f4273c7 5331
c96612cc
JB		 5332 /* We must not accidentally parse an integer as a floating-point number. Make
5333 sure that the value we parse is not an integer by checking for special
5334 characters '.' or 'e'.
5335 FIXME: This is a horrible hack, but doing better is tricky because type
5336 information isn't in a very usable state at parse time. */
5337 fpnum = str;
5338 skip_whitespace (fpnum);
5339
5340 if (strncmp (fpnum, "0x", 2) == 0)
5341 return FAIL;
5342 else
5343 {
5344 for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
477330fc
RM		 5345 if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
5346 {
5347 found_fpchar = 1;
5348 break;
5349 }
c96612cc
JB		 5350
5351 if (!found_fpchar)
477330fc 5352 return FAIL;
c96612cc 5353 }
5f4273c7 5354
136da414
JB		 5355 if ((str = atof_ieee (str, 's', words)) != NULL)
5356 {
5357 unsigned fpword = 0;
5358 int i;
5f4273c7 5359
136da414
JB		 5360 /* Our FP word must be 32 bits (single-precision FP). */
5361 for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
477330fc
RM		 5362 {
5363 fpword <<= LITTLENUM_NUMBER_OF_BITS;
5364 fpword |= words[i];
5365 }
5f4273c7 5366
c96612cc 5367 if (is_quarter_float (fpword) || (fpword & 0x7fffffff) == 0)
477330fc 5368 *immed = fpword;
136da414 5369 else
477330fc 5370 return FAIL;
136da414
JB		 5371
5372 *ccp = str;
5f4273c7 5373
136da414
JB		 5374 return SUCCESS;
5375 }
5f4273c7 5376
136da414
JB		 5377 return FAIL;
5378}
5379
c19d1205
ZW		 5380/* Shift operands. */
5381enum shift_kind
b99bd4ef 5382{
f5f10c66 5383 SHIFT_LSL, SHIFT_LSR, SHIFT_ASR, SHIFT_ROR, SHIFT_RRX, SHIFT_UXTW
c19d1205 5384};
b99bd4ef 5385
c19d1205
ZW		 5386struct asm_shift_name
5387{
5388 const char *name;
5389 enum shift_kind kind;
5390};
b99bd4ef 5391
c19d1205
ZW		 5392/* Third argument to parse_shift. */
5393enum parse_shift_mode
5394{
5395 NO_SHIFT_RESTRICT, /* Any kind of shift is accepted. */
5396 SHIFT_IMMEDIATE, /* Shift operand must be an immediate. */
5397 SHIFT_LSL_OR_ASR_IMMEDIATE, /* Shift must be LSL or ASR immediate. */
5398 SHIFT_ASR_IMMEDIATE, /* Shift must be ASR immediate. */
5399 SHIFT_LSL_IMMEDIATE, /* Shift must be LSL immediate. */
f5f10c66 5400 SHIFT_UXTW_IMMEDIATE /* Shift must be UXTW immediate. */
c19d1205 5401};
b99bd4ef 5402
c19d1205
ZW		 5403/* Parse a <shift> specifier on an ARM data processing instruction.
5404 This has three forms:
b99bd4ef 5405
c19d1205
ZW		 5406 (LSL|LSR|ASL|ASR|ROR) Rs
5407 (LSL|LSR|ASL|ASR|ROR) #imm
5408 RRX
b99bd4ef 5409
c19d1205
ZW		 5410 Note that ASL is assimilated to LSL in the instruction encoding, and
5411 RRX to ROR #0 (which cannot be written as such). */
b99bd4ef 5412
c19d1205
ZW		 5413static int
5414parse_shift (char **str, int i, enum parse_shift_mode mode)
b99bd4ef 5415{
c19d1205
ZW		 5416 const struct asm_shift_name *shift_name;
5417 enum shift_kind shift;
5418 char *s = *str;
5419 char *p = s;
5420 int reg;
b99bd4ef 5421
c19d1205
ZW		 5422 for (p = *str; ISALPHA (*p); p++)
5423 ;
b99bd4ef 5424
c19d1205 5425 if (p == *str)
b99bd4ef 5426 {
c19d1205
ZW		 5427 inst.error = _("shift expression expected");
5428 return FAIL;
b99bd4ef
NC		 5429 }
5430
21d799b5 5431 shift_name = (const struct asm_shift_name *) hash_find_n (arm_shift_hsh, *str,
477330fc 5432 p - *str);
c19d1205
ZW		 5433
5434 if (shift_name == NULL)
b99bd4ef 5435 {
c19d1205
ZW		 5436 inst.error = _("shift expression expected");
5437 return FAIL;
b99bd4ef
NC		 5438 }
5439
c19d1205 5440 shift = shift_name->kind;
b99bd4ef 5441
c19d1205
ZW		 5442 switch (mode)
5443 {
5444 case NO_SHIFT_RESTRICT:
f5f10c66
AV		 5445 case SHIFT_IMMEDIATE:
5446 if (shift == SHIFT_UXTW)
5447 {
5448 inst.error = _("'UXTW' not allowed here");
5449 return FAIL;
5450 }
5451 break;
b99bd4ef 5452
c19d1205
ZW		 5453 case SHIFT_LSL_OR_ASR_IMMEDIATE:
5454 if (shift != SHIFT_LSL && shift != SHIFT_ASR)
5455 {
5456 inst.error = _("'LSL' or 'ASR' required");
5457 return FAIL;
5458 }
5459 break;
b99bd4ef 5460
c19d1205
ZW		 5461 case SHIFT_LSL_IMMEDIATE:
5462 if (shift != SHIFT_LSL)
5463 {
5464 inst.error = _("'LSL' required");
5465 return FAIL;
5466 }
5467 break;
b99bd4ef 5468
c19d1205
ZW		 5469 case SHIFT_ASR_IMMEDIATE:
5470 if (shift != SHIFT_ASR)
5471 {
5472 inst.error = _("'ASR' required");
5473 return FAIL;
5474 }
5475 break;
f5f10c66
AV		 5476 case SHIFT_UXTW_IMMEDIATE:
5477 if (shift != SHIFT_UXTW)
5478 {
5479 inst.error = _("'UXTW' required");
5480 return FAIL;
5481 }
5482 break;
b99bd4ef 5483
c19d1205
ZW		 5484 default: abort ();
5485 }
b99bd4ef 5486
c19d1205
ZW		 5487 if (shift != SHIFT_RRX)
5488 {
5489 /* Whitespace can appear here if the next thing is a bare digit. */
5490 skip_whitespace (p);
b99bd4ef 5491
c19d1205 5492 if (mode == NO_SHIFT_RESTRICT
dcbf9037 5493 && (reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5494 {
5495 inst.operands[i].imm = reg;
5496 inst.operands[i].immisreg = 1;
5497 }
e2b0ab59 5498 else if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
c19d1205
ZW		 5499 return FAIL;
5500 }
5501 inst.operands[i].shift_kind = shift;
5502 inst.operands[i].shifted = 1;
5503 *str = p;
5504 return SUCCESS;
b99bd4ef
NC		 5505}
5506
c19d1205 5507/* Parse a <shifter_operand> for an ARM data processing instruction:
b99bd4ef 5508
c19d1205
ZW		 5509 #<immediate>
5510 #<immediate>, <rotate>
5511 <Rm>
5512 <Rm>, <shift>
b99bd4ef 5513
c19d1205
ZW		 5514 where <shift> is defined by parse_shift above, and <rotate> is a
5515 multiple of 2 between 0 and 30. Validation of immediate operands
55cf6793 5516 is deferred to md_apply_fix. */
b99bd4ef 5517
c19d1205
ZW		 5518static int
5519parse_shifter_operand (char **str, int i)
5520{
5521 int value;
91d6fa6a 5522 expressionS exp;
b99bd4ef 5523
dcbf9037 5524 if ((value = arm_reg_parse (str, REG_TYPE_RN)) != FAIL)
c19d1205
ZW		 5525 {
5526 inst.operands[i].reg = value;
5527 inst.operands[i].isreg = 1;
b99bd4ef 5528
c19d1205 5529 /* parse_shift will override this if appropriate */
e2b0ab59
AV		 5530 inst.relocs[0].exp.X_op = O_constant;
5531 inst.relocs[0].exp.X_add_number = 0;
b99bd4ef 5532
c19d1205
ZW		 5533 if (skip_past_comma (str) == FAIL)
5534 return SUCCESS;
b99bd4ef 5535
c19d1205
ZW		 5536 /* Shift operation on register. */
5537 return parse_shift (str, i, NO_SHIFT_RESTRICT);
b99bd4ef
NC		 5538 }
5539
e2b0ab59 5540 if (my_get_expression (&inst.relocs[0].exp, str, GE_IMM_PREFIX))
c19d1205 5541 return FAIL;
b99bd4ef 5542
c19d1205 5543 if (skip_past_comma (str) == SUCCESS)
b99bd4ef 5544 {
c19d1205 5545 /* #x, y -- ie explicit rotation by Y. */
91d6fa6a 5546 if (my_get_expression (&exp, str, GE_NO_PREFIX))
c19d1205 5547 return FAIL;
b99bd4ef 5548
e2b0ab59 5549 if (exp.X_op != O_constant || inst.relocs[0].exp.X_op != O_constant)
c19d1205
ZW		 5550 {
5551 inst.error = _("constant expression expected");
5552 return FAIL;
5553 }
b99bd4ef 5554
91d6fa6a 5555 value = exp.X_add_number;
c19d1205
ZW		 5556 if (value < 0 || value > 30 || value % 2 != 0)
5557 {
5558 inst.error = _("invalid rotation");
5559 return FAIL;
5560 }
e2b0ab59
AV		 5561 if (inst.relocs[0].exp.X_add_number < 0
5562 || inst.relocs[0].exp.X_add_number > 255)
c19d1205
ZW		 5563 {
5564 inst.error = _("invalid constant");
5565 return FAIL;
5566 }
09d92015 5567
a415b1cd 5568 /* Encode as specified. */
e2b0ab59 5569 inst.operands[i].imm = inst.relocs[0].exp.X_add_number | value << 7;
a415b1cd 5570 return SUCCESS;
09d92015
MM		 5571 }
5572
e2b0ab59
AV		 5573 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
5574 inst.relocs[0].pc_rel = 0;
c19d1205 5575 return SUCCESS;
09d92015
MM		 5576}
5577
4962c51a
MS		 5578/* Group relocation information. Each entry in the table contains the
5579 textual name of the relocation as may appear in assembler source
5580 and must end with a colon.
5581 Along with this textual name are the relocation codes to be used if
5582 the corresponding instruction is an ALU instruction (ADD or SUB only),
5583 an LDR, an LDRS, or an LDC. */
5584
5585struct group_reloc_table_entry
5586{
5587 const char *name;
5588 int alu_code;
5589 int ldr_code;
5590 int ldrs_code;
5591 int ldc_code;
5592};
5593
5594typedef enum
5595{
5596 /* Varieties of non-ALU group relocation. */
5597
5598 GROUP_LDR,
5599 GROUP_LDRS,
35c228db
AV		 5600 GROUP_LDC,
5601 GROUP_MVE
4962c51a
MS		 5602} group_reloc_type;
5603
5604static struct group_reloc_table_entry group_reloc_table[] =
5605 { /* Program counter relative: */
5606 { "pc_g0_nc",
5607 BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
5608 0, /* LDR */
5609 0, /* LDRS */
5610 0 }, /* LDC */
5611 { "pc_g0",
5612 BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
5613 BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
5614 BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
5615 BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
5616 { "pc_g1_nc",
5617 BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
5618 0, /* LDR */
5619 0, /* LDRS */
5620 0 }, /* LDC */
5621 { "pc_g1",
5622 BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
5623 BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
5624 BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
5625 BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
5626 { "pc_g2",
5627 BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
5628 BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
5629 BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
5630 BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
5631 /* Section base relative */
5632 { "sb_g0_nc",
5633 BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
5634 0, /* LDR */
5635 0, /* LDRS */
5636 0 }, /* LDC */
5637 { "sb_g0",
5638 BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
5639 BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
5640 BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
5641 BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
5642 { "sb_g1_nc",
5643 BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
5644 0, /* LDR */
5645 0, /* LDRS */
5646 0 }, /* LDC */
5647 { "sb_g1",
5648 BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
5649 BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
5650 BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
5651 BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
5652 { "sb_g2",
5653 BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
5654 BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
5655 BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
72d98d16
MG		 5656 BFD_RELOC_ARM_LDC_SB_G2 }, /* LDC */
5657 /* Absolute thumb alu relocations. */
5658 { "lower0_7",
5659 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC,/* ALU. */
5660 0, /* LDR. */
5661 0, /* LDRS. */
5662 0 }, /* LDC. */
5663 { "lower8_15",
5664 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC,/* ALU. */
5665 0, /* LDR. */
5666 0, /* LDRS. */
5667 0 }, /* LDC. */
5668 { "upper0_7",
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC,/* ALU. */
5670 0, /* LDR. */
5671 0, /* LDRS. */
5672 0 }, /* LDC. */
5673 { "upper8_15",
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC,/* ALU. */
5675 0, /* LDR. */
5676 0, /* LDRS. */
5677 0 } }; /* LDC. */
4962c51a
MS		 5678
5679/* Given the address of a pointer pointing to the textual name of a group
5680 relocation as may appear in assembler source, attempt to find its details
5681 in group_reloc_table. The pointer will be updated to the character after
5682 the trailing colon. On failure, FAIL will be returned; SUCCESS
5683 otherwise. On success, *entry will be updated to point at the relevant
5684 group_reloc_table entry. */
5685
5686static int
5687find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
5688{
5689 unsigned int i;
5690 for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
5691 {
5692 int length = strlen (group_reloc_table[i].name);
5693
5f4273c7
NC		 5694 if (strncasecmp (group_reloc_table[i].name, *str, length) == 0
5695 && (*str)[length] == ':')
477330fc
RM		 5696 {
5697 *out = &group_reloc_table[i];
5698 *str += (length + 1);
5699 return SUCCESS;
5700 }
4962c51a
MS		 5701 }
5702
5703 return FAIL;
5704}
5705
5706/* Parse a <shifter_operand> for an ARM data processing instruction
5707 (as for parse_shifter_operand) where group relocations are allowed:
5708
5709 #<immediate>
5710 #<immediate>, <rotate>
5711 #:<group_reloc>:<expression>
5712 <Rm>
5713 <Rm>, <shift>
5714
5715 where <group_reloc> is one of the strings defined in group_reloc_table.
5716 The hashes are optional.
5717
5718 Everything else is as for parse_shifter_operand. */
5719
5720static parse_operand_result
5721parse_shifter_operand_group_reloc (char **str, int i)
5722{
5723 /* Determine if we have the sequence of characters #: or just :
5724 coming next. If we do, then we check for a group relocation.
5725 If we don't, punt the whole lot to parse_shifter_operand. */
5726
5727 if (((*str)[0] == '#' && (*str)[1] == ':')
5728 || (*str)[0] == ':')
5729 {
5730 struct group_reloc_table_entry *entry;
5731
5732 if ((*str)[0] == '#')
477330fc 5733 (*str) += 2;
4962c51a 5734 else
477330fc 5735 (*str)++;
4962c51a
MS		 5736
5737 /* Try to parse a group relocation. Anything else is an error. */
5738 if (find_group_reloc_table_entry (str, &entry) == FAIL)
477330fc
RM		 5739 {
5740 inst.error = _("unknown group relocation");
5741 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5742 }
4962c51a
MS		 5743
5744 /* We now have the group relocation table entry corresponding to
477330fc 5745 the name in the assembler source. Next, we parse the expression. */
e2b0ab59 5746 if (my_get_expression (&inst.relocs[0].exp, str, GE_NO_PREFIX))
477330fc 5747 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
4962c51a
MS		 5748
5749 /* Record the relocation type (always the ALU variant here). */
e2b0ab59
AV		 5750 inst.relocs[0].type = (bfd_reloc_code_real_type) entry->alu_code;
5751 gas_assert (inst.relocs[0].type != 0);
4962c51a
MS		 5752
5753 return PARSE_OPERAND_SUCCESS;
5754 }
5755 else
5756 return parse_shifter_operand (str, i) == SUCCESS
477330fc 5757 ? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
4962c51a
MS		 5758
5759 /* Never reached. */
5760}
5761
8e560766
MGD		 5762/* Parse a Neon alignment expression. Information is written to
5763 inst.operands[i]. We assume the initial ':' has been skipped.
fa94de6b 5764
8e560766
MGD		 5765 align .imm = align << 8, .immisalign=1, .preind=0 */
5766static parse_operand_result
5767parse_neon_alignment (char **str, int i)
5768{
5769 char *p = *str;
5770 expressionS exp;
5771
5772 my_get_expression (&exp, &p, GE_NO_PREFIX);
5773
5774 if (exp.X_op != O_constant)
5775 {
5776 inst.error = _("alignment must be constant");
5777 return PARSE_OPERAND_FAIL;
5778 }
5779
5780 inst.operands[i].imm = exp.X_add_number << 8;
5781 inst.operands[i].immisalign = 1;
5782 /* Alignments are not pre-indexes. */
5783 inst.operands[i].preind = 0;
5784
5785 *str = p;
5786 return PARSE_OPERAND_SUCCESS;
5787}
5788
c19d1205 5789/* Parse all forms of an ARM address expression. Information is written
e2b0ab59 5790 to inst.operands[i] and/or inst.relocs[0].
09d92015 5791
c19d1205 5792 Preindexed addressing (.preind=1):
09d92015 5793
e2b0ab59 5794 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
c19d1205
ZW		 5795 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5796 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5797 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5798
c19d1205 5799 These three may have a trailing ! which causes .writeback to be set also.
09d92015 5800
c19d1205 5801 Postindexed addressing (.postind=1, .writeback=1):
09d92015 5802
e2b0ab59 5803 [Rn], #offset .reg=Rn .relocs[0].exp=offset
c19d1205
ZW		 5804 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5805 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
e2b0ab59 5806 .shift_kind=shift .relocs[0].exp=shift_imm
09d92015 5807
c19d1205 5808 Unindexed addressing (.preind=0, .postind=0):
09d92015 5809
c19d1205 5810 [Rn], {option} .reg=Rn .imm=option .immisreg=0
09d92015 5811
c19d1205 5812 Other:
09d92015 5813
c19d1205 5814 [Rn]{!} shorthand for [Rn,#0]{!}
e2b0ab59
AV		 5815 =immediate .isreg=0 .relocs[0].exp=immediate
5816 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
09d92015 5817
c19d1205 5818 It is the caller's responsibility to check for addressing modes not
e2b0ab59 5819 supported by the instruction, and to set inst.relocs[0].type. */
c19d1205 5820
4962c51a
MS		 5821static parse_operand_result
5822parse_address_main (char **str, int i, int group_relocations,
477330fc 5823 group_reloc_type group_type)
09d92015 5824{
c19d1205
ZW		 5825 char *p = *str;
5826 int reg;
09d92015 5827
c19d1205 5828 if (skip_past_char (&p, '[') == FAIL)
09d92015 5829 {
c19d1205
ZW		 5830 if (skip_past_char (&p, '=') == FAIL)
5831 {
974da60d 5832 /* Bare address - translate to PC-relative offset. */
e2b0ab59 5833 inst.relocs[0].pc_rel = 1;
c19d1205
ZW		 5834 inst.operands[i].reg = REG_PC;
5835 inst.operands[i].isreg = 1;
5836 inst.operands[i].preind = 1;
09d92015 5837
e2b0ab59 5838 if (my_get_expression (&inst.relocs[0].exp, &p, GE_OPT_PREFIX_BIG))
8335d6aa
JW		 5839 return PARSE_OPERAND_FAIL;
5840 }
e2b0ab59 5841 else if (parse_big_immediate (&p, i, &inst.relocs[0].exp,
8335d6aa 5842 /*allow_symbol_p=*/TRUE))
4962c51a 5843 return PARSE_OPERAND_FAIL;
09d92015 5844
c19d1205 5845 *str = p;
4962c51a 5846 return PARSE_OPERAND_SUCCESS;
09d92015
MM		 5847 }
5848
8ab8155f
NC		 5849 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5850 skip_whitespace (p);
5851
f5f10c66
AV		 5852 if (group_type == GROUP_MVE)
5853 {
5854 enum arm_reg_type rtype = REG_TYPE_MQ;
5855 struct neon_type_el et;
5856 if ((reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5857 {
5858 inst.operands[i].isquad = 1;
5859 }
5860 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
5861 {
5862 inst.error = BAD_ADDR_MODE;
5863 return PARSE_OPERAND_FAIL;
5864 }
5865 }
5866 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
09d92015 5867 {
35c228db
AV		 5868 if (group_type == GROUP_MVE)
5869 inst.error = BAD_ADDR_MODE;
5870 else
5871 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
4962c51a 5872 return PARSE_OPERAND_FAIL;
09d92015 5873 }
c19d1205
ZW		 5874 inst.operands[i].reg = reg;
5875 inst.operands[i].isreg = 1;
09d92015 5876
c19d1205 5877 if (skip_past_comma (&p) == SUCCESS)
09d92015 5878 {
c19d1205 5879 inst.operands[i].preind = 1;
09d92015 5880
c19d1205
ZW		 5881 if (*p == '+') p++;
5882 else if (*p == '-') p++, inst.operands[i].negative = 1;
5883
f5f10c66
AV		 5884 enum arm_reg_type rtype = REG_TYPE_MQ;
5885 struct neon_type_el et;
5886 if (group_type == GROUP_MVE
5887 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
5888 {
5889 inst.operands[i].immisreg = 2;
5890 inst.operands[i].imm = reg;
5891
5892 if (skip_past_comma (&p) == SUCCESS)
5893 {
5894 if (parse_shift (&p, i, SHIFT_UXTW_IMMEDIATE) == SUCCESS)
5895 {
5896 inst.operands[i].imm |= inst.relocs[0].exp.X_add_number << 5;
5897 inst.relocs[0].exp.X_add_number = 0;
5898 }
5899 else
5900 return PARSE_OPERAND_FAIL;
5901 }
5902 }
5903 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
09d92015 5904 {
c19d1205
ZW		 5905 inst.operands[i].imm = reg;
5906 inst.operands[i].immisreg = 1;
5907
5908 if (skip_past_comma (&p) == SUCCESS)
5909 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 5910 return PARSE_OPERAND_FAIL;
c19d1205 5911 }
5287ad62 5912 else if (skip_past_char (&p, ':') == SUCCESS)
8e560766
MGD		 5913 {
5914 /* FIXME: '@' should be used here, but it's filtered out by generic
5915 code before we get to see it here. This may be subject to
5916 change. */
5917 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 5918
8e560766
MGD		 5919 if (result != PARSE_OPERAND_SUCCESS)
5920 return result;
5921 }
c19d1205
ZW		 5922 else
5923 {
5924 if (inst.operands[i].negative)
5925 {
5926 inst.operands[i].negative = 0;
5927 p--;
5928 }
4962c51a 5929
5f4273c7
NC		 5930 if (group_relocations
5931 && ((*p == '#' && *(p + 1) == ':') || *p == ':'))
4962c51a
MS		 5932 {
5933 struct group_reloc_table_entry *entry;
5934
477330fc
RM		 5935 /* Skip over the #: or : sequence. */
5936 if (*p == '#')
5937 p += 2;
5938 else
5939 p++;
4962c51a
MS		 5940
5941 /* Try to parse a group relocation. Anything else is an
477330fc 5942 error. */
4962c51a
MS		 5943 if (find_group_reloc_table_entry (&p, &entry) == FAIL)
5944 {
5945 inst.error = _("unknown group relocation");
5946 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5947 }
5948
5949 /* We now have the group relocation table entry corresponding to
5950 the name in the assembler source. Next, we parse the
477330fc 5951 expression. */
e2b0ab59 5952 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
4962c51a
MS		 5953 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5954
5955 /* Record the relocation type. */
477330fc
RM		 5956 switch (group_type)
5957 {
5958 case GROUP_LDR:
e2b0ab59
AV		 5959 inst.relocs[0].type
5960 = (bfd_reloc_code_real_type) entry->ldr_code;
477330fc 5961 break;
4962c51a 5962
477330fc 5963 case GROUP_LDRS:
e2b0ab59
AV		 5964 inst.relocs[0].type
5965 = (bfd_reloc_code_real_type) entry->ldrs_code;
477330fc 5966 break;
4962c51a 5967
477330fc 5968 case GROUP_LDC:
e2b0ab59
AV		 5969 inst.relocs[0].type
5970 = (bfd_reloc_code_real_type) entry->ldc_code;
477330fc 5971 break;
4962c51a 5972
477330fc
RM		 5973 default:
5974 gas_assert (0);
5975 }
4962c51a 5976
e2b0ab59 5977 if (inst.relocs[0].type == 0)
4962c51a
MS		 5978 {
5979 inst.error = _("this group relocation is not allowed on this instruction");
5980 return PARSE_OPERAND_FAIL_NO_BACKTRACK;
5981 }
477330fc
RM		 5982 }
5983 else
26d97720
NS		 5984 {
5985 char *q = p;
0198d5e6 5986
e2b0ab59 5987 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
26d97720
NS		 5988 return PARSE_OPERAND_FAIL;
5989 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV		 5990 if (inst.relocs[0].exp.X_op == O_constant
5991 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS		 5992 {
5993 skip_whitespace (q);
5994 if (*q == '#')
5995 {
5996 q++;
5997 skip_whitespace (q);
5998 }
5999 if (*q == '-')
6000 inst.operands[i].negative = 1;
6001 }
6002 }
09d92015
MM		 6003 }
6004 }
8e560766
MGD		 6005 else if (skip_past_char (&p, ':') == SUCCESS)
6006 {
6007 /* FIXME: '@' should be used here, but it's filtered out by generic code
6008 before we get to see it here. This may be subject to change. */
6009 parse_operand_result result = parse_neon_alignment (&p, i);
fa94de6b 6010
8e560766
MGD		 6011 if (result != PARSE_OPERAND_SUCCESS)
6012 return result;
6013 }
09d92015 6014
c19d1205 6015 if (skip_past_char (&p, ']') == FAIL)
09d92015 6016 {
c19d1205 6017 inst.error = _("']' expected");
4962c51a 6018 return PARSE_OPERAND_FAIL;
09d92015
MM		 6019 }
6020
c19d1205
ZW		 6021 if (skip_past_char (&p, '!') == SUCCESS)
6022 inst.operands[i].writeback = 1;
09d92015 6023
c19d1205 6024 else if (skip_past_comma (&p) == SUCCESS)
09d92015 6025 {
c19d1205
ZW		 6026 if (skip_past_char (&p, '{') == SUCCESS)
6027 {
6028 /* [Rn], {expr} - unindexed, with option */
6029 if (parse_immediate (&p, &inst.operands[i].imm,
ca3f61f7 6030 0, 255, TRUE) == FAIL)
4962c51a 6031 return PARSE_OPERAND_FAIL;
09d92015 6032
c19d1205
ZW		 6033 if (skip_past_char (&p, '}') == FAIL)
6034 {
6035 inst.error = _("'}' expected at end of 'option' field");
4962c51a 6036 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6037 }
6038 if (inst.operands[i].preind)
6039 {
6040 inst.error = _("cannot combine index with option");
4962c51a 6041 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6042 }
6043 *str = p;
4962c51a 6044 return PARSE_OPERAND_SUCCESS;
09d92015 6045 }
c19d1205
ZW		 6046 else
6047 {
6048 inst.operands[i].postind = 1;
6049 inst.operands[i].writeback = 1;
09d92015 6050
c19d1205
ZW		 6051 if (inst.operands[i].preind)
6052 {
6053 inst.error = _("cannot combine pre- and post-indexing");
4962c51a 6054 return PARSE_OPERAND_FAIL;
c19d1205 6055 }
09d92015 6056
c19d1205
ZW		 6057 if (*p == '+') p++;
6058 else if (*p == '-') p++, inst.operands[i].negative = 1;
a737bd4d 6059
f5f10c66
AV		 6060 enum arm_reg_type rtype = REG_TYPE_MQ;
6061 struct neon_type_el et;
6062 if (group_type == GROUP_MVE
6063 && (reg = arm_typed_reg_parse (&p, rtype, &rtype, &et)) != FAIL)
6064 {
6065 inst.operands[i].immisreg = 2;
6066 inst.operands[i].imm = reg;
6067 }
6068 else if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) != FAIL)
c19d1205 6069 {
477330fc
RM		 6070 /* We might be using the immediate for alignment already. If we
6071 are, OR the register number into the low-order bits. */
6072 if (inst.operands[i].immisalign)
6073 inst.operands[i].imm |= reg;
6074 else
6075 inst.operands[i].imm = reg;
c19d1205 6076 inst.operands[i].immisreg = 1;
a737bd4d 6077
c19d1205
ZW		 6078 if (skip_past_comma (&p) == SUCCESS)
6079 if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
4962c51a 6080 return PARSE_OPERAND_FAIL;
c19d1205
ZW		 6081 }
6082 else
6083 {
26d97720 6084 char *q = p;
0198d5e6 6085
c19d1205
ZW		 6086 if (inst.operands[i].negative)
6087 {
6088 inst.operands[i].negative = 0;
6089 p--;
6090 }
e2b0ab59 6091 if (my_get_expression (&inst.relocs[0].exp, &p, GE_IMM_PREFIX))
4962c51a 6092 return PARSE_OPERAND_FAIL;
26d97720 6093 /* If the offset is 0, find out if it's a +0 or -0. */
e2b0ab59
AV		 6094 if (inst.relocs[0].exp.X_op == O_constant
6095 && inst.relocs[0].exp.X_add_number == 0)
26d97720
NS		 6096 {
6097 skip_whitespace (q);
6098 if (*q == '#')
6099 {
6100 q++;
6101 skip_whitespace (q);
6102 }
6103 if (*q == '-')
6104 inst.operands[i].negative = 1;
6105 }
c19d1205
ZW		 6106 }
6107 }
a737bd4d
NC		 6108 }
6109
c19d1205
ZW		 6110 /* If at this point neither .preind nor .postind is set, we have a
6111 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6112 if (inst.operands[i].preind == 0 && inst.operands[i].postind == 0)
6113 {
6114 inst.operands[i].preind = 1;
e2b0ab59
AV		 6115 inst.relocs[0].exp.X_op = O_constant;
6116 inst.relocs[0].exp.X_add_number = 0;
c19d1205
ZW		 6117 }
6118 *str = p;
4962c51a
MS		 6119 return PARSE_OPERAND_SUCCESS;
6120}
6121
6122static int
6123parse_address (char **str, int i)
6124{
21d799b5 6125 return parse_address_main (str, i, 0, GROUP_LDR) == PARSE_OPERAND_SUCCESS
477330fc 6126 ? SUCCESS : FAIL;
4962c51a
MS		 6127}
6128
6129static parse_operand_result
6130parse_address_group_reloc (char **str, int i, group_reloc_type type)
6131{
6132 return parse_address_main (str, i, 1, type);
a737bd4d
NC		 6133}
6134
b6895b4f
PB		 6135/* Parse an operand for a MOVW or MOVT instruction. */
6136static int
6137parse_half (char **str)
6138{
6139 char * p;
5f4273c7 6140
b6895b4f
PB		 6141 p = *str;
6142 skip_past_char (&p, '#');
5f4273c7 6143 if (strncasecmp (p, ":lower16:", 9) == 0)
e2b0ab59 6144 inst.relocs[0].type = BFD_RELOC_ARM_MOVW;
b6895b4f 6145 else if (strncasecmp (p, ":upper16:", 9) == 0)
e2b0ab59 6146 inst.relocs[0].type = BFD_RELOC_ARM_MOVT;
b6895b4f 6147
e2b0ab59 6148 if (inst.relocs[0].type != BFD_RELOC_UNUSED)
b6895b4f
PB		 6149 {
6150 p += 9;
5f4273c7 6151 skip_whitespace (p);
b6895b4f
PB		 6152 }
6153
e2b0ab59 6154 if (my_get_expression (&inst.relocs[0].exp, &p, GE_NO_PREFIX))
b6895b4f
PB		 6155 return FAIL;
6156
e2b0ab59 6157 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 6158 {
e2b0ab59 6159 if (inst.relocs[0].exp.X_op != O_constant)
b6895b4f
PB		 6160 {
6161 inst.error = _("constant expression expected");
6162 return FAIL;
6163 }
e2b0ab59
AV		 6164 if (inst.relocs[0].exp.X_add_number < 0
6165 || inst.relocs[0].exp.X_add_number > 0xffff)
b6895b4f
PB		 6166 {
6167 inst.error = _("immediate value out of range");
6168 return FAIL;
6169 }
6170 }
6171 *str = p;
6172 return SUCCESS;
6173}
6174
c19d1205 6175/* Miscellaneous. */
a737bd4d 6176
c19d1205
ZW		 6177/* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6178 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6179static int
d2cd1205 6180parse_psr (char **str, bfd_boolean lhs)
09d92015 6181{
c19d1205
ZW		 6182 char *p;
6183 unsigned long psr_field;
62b3e311
PB		 6184 const struct asm_psr *psr;
6185 char *start;
d2cd1205 6186 bfd_boolean is_apsr = FALSE;
ac7f631b 6187 bfd_boolean m_profile = ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m);
09d92015 6188
a4482bb6
NC		 6189 /* PR gas/12698: If the user has specified -march=all then m_profile will
6190 be TRUE, but we want to ignore it in this case as we are building for any
6191 CPU type, including non-m variants. */
823d2571 6192 if (ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
a4482bb6
NC		 6193 m_profile = FALSE;
6194
c19d1205
ZW		 6195 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6196 feature for ease of use and backwards compatibility. */
6197 p = *str;
62b3e311 6198 if (strncasecmp (p, "SPSR", 4) == 0)
d2cd1205
JB		 6199 {
6200 if (m_profile)
6201 goto unsupported_psr;
fa94de6b 6202
d2cd1205
JB		 6203 psr_field = SPSR_BIT;
6204 }
6205 else if (strncasecmp (p, "CPSR", 4) == 0)
6206 {
6207 if (m_profile)
6208 goto unsupported_psr;
6209
6210 psr_field = 0;
6211 }
6212 else if (strncasecmp (p, "APSR", 4) == 0)
6213 {
6214 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6215 and ARMv7-R architecture CPUs. */
6216 is_apsr = TRUE;
6217 psr_field = 0;
6218 }
6219 else if (m_profile)
62b3e311
PB		 6220 {
6221 start = p;
6222 do
6223 p++;
6224 while (ISALNUM (*p) || *p == '_');
6225
d2cd1205
JB		 6226 if (strncasecmp (start, "iapsr", 5) == 0
6227 || strncasecmp (start, "eapsr", 5) == 0
6228 || strncasecmp (start, "xpsr", 4) == 0
6229 || strncasecmp (start, "psr", 3) == 0)
6230 p = start + strcspn (start, "rR") + 1;
6231
21d799b5 6232 psr = (const struct asm_psr *) hash_find_n (arm_v7m_psr_hsh, start,
477330fc 6233 p - start);
d2cd1205 6234
62b3e311
PB		 6235 if (!psr)
6236 return FAIL;
09d92015 6237
d2cd1205
JB		 6238 /* If APSR is being written, a bitfield may be specified. Note that
6239 APSR itself is handled above. */
6240 if (psr->field <= 3)
6241 {
6242 psr_field = psr->field;
6243 is_apsr = TRUE;
6244 goto check_suffix;
6245 }
6246
62b3e311 6247 *str = p;
d2cd1205
JB		 6248 /* M-profile MSR instructions have the mask field set to "10", except
6249 *PSR variants which modify APSR, which may use a different mask (and
6250 have been handled already). Do that by setting the PSR_f field
6251 here. */
6252 return psr->field | (lhs ? PSR_f : 0);
62b3e311 6253 }
d2cd1205
JB		 6254 else
6255 goto unsupported_psr;
09d92015 6256
62b3e311 6257 p += 4;
d2cd1205 6258check_suffix:
c19d1205
ZW		 6259 if (*p == '_')
6260 {
6261 /* A suffix follows. */
c19d1205
ZW		 6262 p++;
6263 start = p;
a737bd4d 6264
c19d1205
ZW		 6265 do
6266 p++;
6267 while (ISALNUM (*p) || *p == '_');
a737bd4d 6268
d2cd1205
JB		 6269 if (is_apsr)
6270 {
6271 /* APSR uses a notation for bits, rather than fields. */
6272 unsigned int nzcvq_bits = 0;
6273 unsigned int g_bit = 0;
6274 char *bit;
fa94de6b 6275
d2cd1205
JB		 6276 for (bit = start; bit != p; bit++)
6277 {
6278 switch (TOLOWER (*bit))
477330fc 6279 {
d2cd1205
JB		 6280 case 'n':
6281 nzcvq_bits |= (nzcvq_bits & 0x01) ? 0x20 : 0x01;
6282 break;
6283
6284 case 'z':
6285 nzcvq_bits |= (nzcvq_bits & 0x02) ? 0x20 : 0x02;
6286 break;
6287
6288 case 'c':
6289 nzcvq_bits |= (nzcvq_bits & 0x04) ? 0x20 : 0x04;
6290 break;
6291
6292 case 'v':
6293 nzcvq_bits |= (nzcvq_bits & 0x08) ? 0x20 : 0x08;
6294 break;
fa94de6b 6295
d2cd1205
JB		 6296 case 'q':
6297 nzcvq_bits |= (nzcvq_bits & 0x10) ? 0x20 : 0x10;
6298 break;
fa94de6b 6299
d2cd1205
JB		 6300 case 'g':
6301 g_bit |= (g_bit & 0x1) ? 0x2 : 0x1;
6302 break;
fa94de6b 6303
d2cd1205
JB		 6304 default:
6305 inst.error = _("unexpected bit specified after APSR");
6306 return FAIL;
6307 }
6308 }
fa94de6b 6309
d2cd1205
JB		 6310 if (nzcvq_bits == 0x1f)
6311 psr_field |= PSR_f;
fa94de6b 6312
d2cd1205
JB		 6313 if (g_bit == 0x1)
6314 {
6315 if (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp))
477330fc 6316 {
d2cd1205
JB		 6317 inst.error = _("selected processor does not "
6318 "support DSP extension");
6319 return FAIL;
6320 }
6321
6322 psr_field |= PSR_s;
6323 }
fa94de6b 6324
d2cd1205
JB		 6325 if ((nzcvq_bits & 0x20) != 0
6326 || (nzcvq_bits != 0x1f && nzcvq_bits != 0)
6327 || (g_bit & 0x2) != 0)
6328 {
6329 inst.error = _("bad bitmask specified after APSR");
6330 return FAIL;
6331 }
6332 }
6333 else
477330fc 6334 {
d2cd1205 6335 psr = (const struct asm_psr *) hash_find_n (arm_psr_hsh, start,
477330fc 6336 p - start);
d2cd1205 6337 if (!psr)
477330fc 6338 goto error;
a737bd4d 6339
d2cd1205
JB		 6340 psr_field |= psr->field;
6341 }
a737bd4d 6342 }
c19d1205 6343 else
a737bd4d 6344 {
c19d1205
ZW		 6345 if (ISALNUM (*p))
6346 goto error; /* Garbage after "[CS]PSR". */
6347
d2cd1205 6348 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
477330fc 6349 is deprecated, but allow it anyway. */
d2cd1205
JB		 6350 if (is_apsr && lhs)
6351 {
6352 psr_field |= PSR_f;
6353 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6354 "deprecated"));
6355 }
6356 else if (!m_profile)
6357 /* These bits are never right for M-profile devices: don't set them
6358 (only code paths which read/write APSR reach here). */
6359 psr_field |= (PSR_c | PSR_f);
a737bd4d 6360 }
c19d1205
ZW		 6361 *str = p;
6362 return psr_field;
a737bd4d 6363
d2cd1205
JB		 6364 unsupported_psr:
6365 inst.error = _("selected processor does not support requested special "
6366 "purpose register");
6367 return FAIL;
6368
c19d1205
ZW		 6369 error:
6370 inst.error = _("flag for {c}psr instruction expected");
6371 return FAIL;
a737bd4d
NC		 6372}
6373
32c36c3c
AV		 6374static int
6375parse_sys_vldr_vstr (char **str)
6376{
6377 unsigned i;
6378 int val = FAIL;
6379 struct {
6380 const char *name;
6381 int regl;
6382 int regh;
6383 } sysregs[] = {
6384 {"FPSCR", 0x1, 0x0},
6385 {"FPSCR_nzcvqc", 0x2, 0x0},
6386 {"VPR", 0x4, 0x1},
6387 {"P0", 0x5, 0x1},
6388 {"FPCXTNS", 0x6, 0x1},
6389 {"FPCXTS", 0x7, 0x1}
6390 };
6391 char *op_end = strchr (*str, ',');
6392 size_t op_strlen = op_end - *str;
6393
6394 for (i = 0; i < sizeof (sysregs) / sizeof (sysregs[0]); i++)
6395 {
6396 if (!strncmp (*str, sysregs[i].name, op_strlen))
6397 {
6398 val = sysregs[i].regl | (sysregs[i].regh << 3);
6399 *str = op_end;
6400 break;
6401 }
6402 }
6403
6404 return val;
6405}
6406
c19d1205
ZW		 6407/* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6408 value suitable for splatting into the AIF field of the instruction. */
a737bd4d 6409
c19d1205
ZW		 6410static int
6411parse_cps_flags (char **str)
a737bd4d 6412{
c19d1205
ZW		 6413 int val = 0;
6414 int saw_a_flag = 0;
6415 char *s = *str;
a737bd4d 6416
c19d1205
ZW		 6417 for (;;)
6418 switch (*s++)
6419 {
6420 case '\0': case ',':
6421 goto done;
a737bd4d 6422
c19d1205
ZW		 6423 case 'a': case 'A': saw_a_flag = 1; val |= 0x4; break;
6424 case 'i': case 'I': saw_a_flag = 1; val |= 0x2; break;
6425 case 'f': case 'F': saw_a_flag = 1; val |= 0x1; break;
a737bd4d 6426
c19d1205
ZW		 6427 default:
6428 inst.error = _("unrecognized CPS flag");
6429 return FAIL;
6430 }
a737bd4d 6431
c19d1205
ZW		 6432 done:
6433 if (saw_a_flag == 0)
a737bd4d 6434 {
c19d1205
ZW		 6435 inst.error = _("missing CPS flags");
6436 return FAIL;
a737bd4d 6437 }
a737bd4d 6438
c19d1205
ZW		 6439 *str = s - 1;
6440 return val;
a737bd4d
NC		 6441}
6442
c19d1205
ZW		 6443/* Parse an endian specifier ("BE" or "LE", case insensitive);
6444 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
a737bd4d
NC		 6445
6446static int
c19d1205 6447parse_endian_specifier (char **str)
a737bd4d 6448{
c19d1205
ZW		 6449 int little_endian;
6450 char *s = *str;
a737bd4d 6451
c19d1205
ZW		 6452 if (strncasecmp (s, "BE", 2))
6453 little_endian = 0;
6454 else if (strncasecmp (s, "LE", 2))
6455 little_endian = 1;
6456 else
a737bd4d 6457 {
c19d1205 6458 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6459 return FAIL;
6460 }
6461
c19d1205 6462 if (ISALNUM (s[2]) || s[2] == '_')
a737bd4d 6463 {
c19d1205 6464 inst.error = _("valid endian specifiers are be or le");
a737bd4d
NC		 6465 return FAIL;
6466 }
6467
c19d1205
ZW		 6468 *str = s + 2;
6469 return little_endian;
6470}
a737bd4d 6471
c19d1205
ZW		 6472/* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6473 value suitable for poking into the rotate field of an sxt or sxta
6474 instruction, or FAIL on error. */
6475
6476static int
6477parse_ror (char **str)
6478{
6479 int rot;
6480 char *s = *str;
6481
6482 if (strncasecmp (s, "ROR", 3) == 0)
6483 s += 3;
6484 else
a737bd4d 6485 {
c19d1205 6486 inst.error = _("missing rotation field after comma");
a737bd4d
NC		 6487 return FAIL;
6488 }
c19d1205
ZW		 6489
6490 if (parse_immediate (&s, &rot, 0, 24, FALSE) == FAIL)
6491 return FAIL;
6492
6493 switch (rot)
a737bd4d 6494 {
c19d1205
ZW		 6495 case 0: *str = s; return 0x0;
6496 case 8: *str = s; return 0x1;
6497 case 16: *str = s; return 0x2;
6498 case 24: *str = s; return 0x3;
6499
6500 default:
6501 inst.error = _("rotation can only be 0, 8, 16, or 24");
a737bd4d
NC		 6502 return FAIL;
6503 }
c19d1205 6504}
a737bd4d 6505
c19d1205
ZW		 6506/* Parse a conditional code (from conds[] below). The value returned is in the
6507 range 0 .. 14, or FAIL. */
6508static int
6509parse_cond (char **str)
6510{
c462b453 6511 char *q;
c19d1205 6512 const struct asm_cond *c;
c462b453
PB		 6513 int n;
6514 /* Condition codes are always 2 characters, so matching up to
6515 3 characters is sufficient. */
6516 char cond[3];
a737bd4d 6517
c462b453
PB		 6518 q = *str;
6519 n = 0;
6520 while (ISALPHA (*q) && n < 3)
6521 {
e07e6e58 6522 cond[n] = TOLOWER (*q);
c462b453
PB		 6523 q++;
6524 n++;
6525 }
a737bd4d 6526
21d799b5 6527 c = (const struct asm_cond *) hash_find_n (arm_cond_hsh, cond, n);
c19d1205 6528 if (!c)
a737bd4d 6529 {
c19d1205 6530 inst.error = _("condition required");
a737bd4d
NC		 6531 return FAIL;
6532 }
6533
c19d1205
ZW		 6534 *str = q;
6535 return c->value;
6536}
6537
62b3e311
PB		 6538/* Parse an option for a barrier instruction. Returns the encoding for the
6539 option, or FAIL. */
6540static int
6541parse_barrier (char **str)
6542{
6543 char *p, *q;
6544 const struct asm_barrier_opt *o;
6545
6546 p = q = *str;
6547 while (ISALPHA (*q))
6548 q++;
6549
21d799b5 6550 o = (const struct asm_barrier_opt *) hash_find_n (arm_barrier_opt_hsh, p,
477330fc 6551 q - p);
62b3e311
PB		 6552 if (!o)
6553 return FAIL;
6554
e797f7e0
MGD		 6555 if (!mark_feature_used (&o->arch))
6556 return FAIL;
6557
62b3e311
PB		 6558 *str = q;
6559 return o->value;
6560}
6561
92e90b6e
PB		 6562/* Parse the operands of a table branch instruction. Similar to a memory
6563 operand. */
6564static int
6565parse_tb (char **str)
6566{
6567 char * p = *str;
6568 int reg;
6569
6570 if (skip_past_char (&p, '[') == FAIL)
ab1eb5fe
PB		 6571 {
6572 inst.error = _("'[' expected");
6573 return FAIL;
6574 }
92e90b6e 6575
dcbf9037 6576 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6577 {
6578 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6579 return FAIL;
6580 }
6581 inst.operands[0].reg = reg;
6582
6583 if (skip_past_comma (&p) == FAIL)
ab1eb5fe
PB		 6584 {
6585 inst.error = _("',' expected");
6586 return FAIL;
6587 }
5f4273c7 6588
dcbf9037 6589 if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
92e90b6e
PB		 6590 {
6591 inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
6592 return FAIL;
6593 }
6594 inst.operands[0].imm = reg;
6595
6596 if (skip_past_comma (&p) == SUCCESS)
6597 {
6598 if (parse_shift (&p, 0, SHIFT_LSL_IMMEDIATE) == FAIL)
6599 return FAIL;
e2b0ab59 6600 if (inst.relocs[0].exp.X_add_number != 1)
92e90b6e
PB		 6601 {
6602 inst.error = _("invalid shift");
6603 return FAIL;
6604 }
6605 inst.operands[0].shifted = 1;
6606 }
6607
6608 if (skip_past_char (&p, ']') == FAIL)
6609 {
6610 inst.error = _("']' expected");
6611 return FAIL;
6612 }
6613 *str = p;
6614 return SUCCESS;
6615}
6616
5287ad62
JB		 6617/* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6618 information on the types the operands can take and how they are encoded.
037e8744
JB		 6619 Up to four operands may be read; this function handles setting the
6620 ".present" field for each read operand itself.
5287ad62
JB		 6621 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6622 else returns FAIL. */
6623
6624static int
6625parse_neon_mov (char **str, int *which_operand)
6626{
6627 int i = *which_operand, val;
6628 enum arm_reg_type rtype;
6629 char *ptr = *str;
dcbf9037 6630 struct neon_type_el optype;
5f4273c7 6631
57785aa2
AV		 6632 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6633 {
6634 /* Cases 17 or 19. */
6635 inst.operands[i].reg = val;
6636 inst.operands[i].isvec = 1;
6637 inst.operands[i].isscalar = 2;
6638 inst.operands[i].vectype = optype;
6639 inst.operands[i++].present = 1;
6640
6641 if (skip_past_comma (&ptr) == FAIL)
6642 goto wanted_comma;
6643
6644 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
6645 {
6646 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6647 inst.operands[i].reg = val;
6648 inst.operands[i].isreg = 1;
6649 inst.operands[i].present = 1;
6650 }
6651 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6652 {
6653 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6654 inst.operands[i].reg = val;
6655 inst.operands[i].isvec = 1;
6656 inst.operands[i].isscalar = 2;
6657 inst.operands[i].vectype = optype;
6658 inst.operands[i++].present = 1;
6659
6660 if (skip_past_comma (&ptr) == FAIL)
6661 goto wanted_comma;
6662
6663 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6664 goto wanted_arm;
6665
6666 inst.operands[i].reg = val;
6667 inst.operands[i].isreg = 1;
6668 inst.operands[i++].present = 1;
6669
6670 if (skip_past_comma (&ptr) == FAIL)
6671 goto wanted_comma;
6672
6673 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6674 goto wanted_arm;
6675
6676 inst.operands[i].reg = val;
6677 inst.operands[i].isreg = 1;
6678 inst.operands[i].present = 1;
6679 }
6680 else
6681 {
6682 first_error (_("expected ARM or MVE vector register"));
6683 return FAIL;
6684 }
6685 }
6686 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
5287ad62
JB		 6687 {
6688 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6689 inst.operands[i].reg = val;
6690 inst.operands[i].isscalar = 1;
dcbf9037 6691 inst.operands[i].vectype = optype;
5287ad62
JB		 6692 inst.operands[i++].present = 1;
6693
6694 if (skip_past_comma (&ptr) == FAIL)
477330fc 6695 goto wanted_comma;
5f4273c7 6696
dcbf9037 6697 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
477330fc 6698 goto wanted_arm;
5f4273c7 6699
5287ad62
JB		 6700 inst.operands[i].reg = val;
6701 inst.operands[i].isreg = 1;
6702 inst.operands[i].present = 1;
6703 }
57785aa2
AV		 6704 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype, &optype))
6705 != FAIL)
6706 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype, &optype))
6707 != FAIL))
5287ad62
JB		 6708 {
6709 /* Cases 0, 1, 2, 3, 5 (D only). */
6710 if (skip_past_comma (&ptr) == FAIL)
477330fc 6711 goto wanted_comma;
5f4273c7 6712
5287ad62
JB		 6713 inst.operands[i].reg = val;
6714 inst.operands[i].isreg = 1;
6715 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
037e8744
JB		 6716 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6717 inst.operands[i].isvec = 1;
dcbf9037 6718 inst.operands[i].vectype = optype;
5287ad62
JB		 6719 inst.operands[i++].present = 1;
6720
dcbf9037 6721 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc
RM		 6722 {
6723 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6724 Case 13: VMOV <Sd>, <Rm> */
6725 inst.operands[i].reg = val;
6726 inst.operands[i].isreg = 1;
6727 inst.operands[i].present = 1;
6728
6729 if (rtype == REG_TYPE_NQ)
6730 {
6731 first_error (_("can't use Neon quad register here"));
6732 return FAIL;
6733 }
6734 else if (rtype != REG_TYPE_VFS)
6735 {
6736 i++;
6737 if (skip_past_comma (&ptr) == FAIL)
6738 goto wanted_comma;
6739 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6740 goto wanted_arm;
6741 inst.operands[i].reg = val;
6742 inst.operands[i].isreg = 1;
6743 inst.operands[i].present = 1;
6744 }
6745 }
c4a23bf8
SP		 6746 else if (((val = arm_typed_reg_parse (&ptr, REG_TYPE_NSDQ, &rtype,
6747 &optype)) != FAIL)
6748 || ((val = arm_typed_reg_parse (&ptr, REG_TYPE_MQ, &rtype,
6749 &optype)) != FAIL))
477330fc
RM		 6750 {
6751 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6752 Case 1: VMOV<c><q> <Dd>, <Dm>
6753 Case 8: VMOV.F32 <Sd>, <Sm>
6754 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6755
6756 inst.operands[i].reg = val;
6757 inst.operands[i].isreg = 1;
6758 inst.operands[i].isquad = (rtype == REG_TYPE_NQ);
6759 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
6760 inst.operands[i].isvec = 1;
6761 inst.operands[i].vectype = optype;
6762 inst.operands[i].present = 1;
6763
6764 if (skip_past_comma (&ptr) == SUCCESS)
6765 {
6766 /* Case 15. */
6767 i++;
6768
6769 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6770 goto wanted_arm;
6771
6772 inst.operands[i].reg = val;
6773 inst.operands[i].isreg = 1;
6774 inst.operands[i++].present = 1;
6775
6776 if (skip_past_comma (&ptr) == FAIL)
6777 goto wanted_comma;
6778
6779 if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) == FAIL)
6780 goto wanted_arm;
6781
6782 inst.operands[i].reg = val;
6783 inst.operands[i].isreg = 1;
6784 inst.operands[i].present = 1;
6785 }
6786 }
4641781c 6787 else if (parse_qfloat_immediate (&ptr, &inst.operands[i].imm) == SUCCESS)
477330fc
RM		 6788 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6789 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6790 Case 10: VMOV.F32 <Sd>, #<imm>
6791 Case 11: VMOV.F64 <Dd>, #<imm> */
6792 inst.operands[i].immisfloat = 1;
8335d6aa
JW		 6793 else if (parse_big_immediate (&ptr, i, NULL, /*allow_symbol_p=*/FALSE)
6794 == SUCCESS)
477330fc
RM		 6795 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6796 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6797 ;
5287ad62 6798 else
477330fc
RM		 6799 {
6800 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6801 return FAIL;
6802 }
5287ad62 6803 }
dcbf9037 6804 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
5287ad62 6805 {
57785aa2 6806 /* Cases 6, 7, 16, 18. */
5287ad62
JB		 6807 inst.operands[i].reg = val;
6808 inst.operands[i].isreg = 1;
6809 inst.operands[i++].present = 1;
5f4273c7 6810
5287ad62 6811 if (skip_past_comma (&ptr) == FAIL)
477330fc 6812 goto wanted_comma;
5f4273c7 6813
57785aa2
AV		 6814 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ)) != FAIL)
6815 {
6816 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6817 inst.operands[i].reg = val;
6818 inst.operands[i].isscalar = 2;
6819 inst.operands[i].present = 1;
6820 inst.operands[i].vectype = optype;
6821 }
6822 else if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_VFD)) != FAIL)
477330fc
RM		 6823 {
6824 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6825 inst.operands[i].reg = val;
6826 inst.operands[i].isscalar = 1;
6827 inst.operands[i].present = 1;
6828 inst.operands[i].vectype = optype;
6829 }
dcbf9037 6830 else if ((val = arm_reg_parse (&ptr, REG_TYPE_RN)) != FAIL)
477330fc 6831 {
477330fc
RM		 6832 inst.operands[i].reg = val;
6833 inst.operands[i].isreg = 1;
6834 inst.operands[i++].present = 1;
6835
6836 if (skip_past_comma (&ptr) == FAIL)
6837 goto wanted_comma;
6838
6839 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFSD, &rtype, &optype))
57785aa2 6840 != FAIL)
477330fc 6841 {
57785aa2 6842 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
477330fc 6843
477330fc
RM		 6844 inst.operands[i].reg = val;
6845 inst.operands[i].isreg = 1;
6846 inst.operands[i].isvec = 1;
57785aa2 6847 inst.operands[i].issingle = (rtype == REG_TYPE_VFS);
477330fc
RM		 6848 inst.operands[i].vectype = optype;
6849 inst.operands[i].present = 1;
57785aa2
AV		 6850
6851 if (rtype == REG_TYPE_VFS)
6852 {
6853 /* Case 14. */
6854 i++;
6855 if (skip_past_comma (&ptr) == FAIL)
6856 goto wanted_comma;
6857 if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL,
6858 &optype)) == FAIL)
6859 {
6860 first_error (_(reg_expected_msgs[REG_TYPE_VFS]));
6861 return FAIL;
6862 }
6863 inst.operands[i].reg = val;
6864 inst.operands[i].isreg = 1;
6865 inst.operands[i].isvec = 1;
6866 inst.operands[i].issingle = 1;
6867 inst.operands[i].vectype = optype;
6868 inst.operands[i].present = 1;
6869 }
6870 }
6871 else
6872 {
6873 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6874 != FAIL)
6875 {
6876 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6877 inst.operands[i].reg = val;
6878 inst.operands[i].isvec = 1;
6879 inst.operands[i].isscalar = 2;
6880 inst.operands[i].vectype = optype;
6881 inst.operands[i++].present = 1;
6882
6883 if (skip_past_comma (&ptr) == FAIL)
6884 goto wanted_comma;
6885
6886 if ((val = parse_scalar (&ptr, 8, &optype, REG_TYPE_MQ))
6887 == FAIL)
6888 {
6889 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
6890 return FAIL;
6891 }
6892 inst.operands[i].reg = val;
6893 inst.operands[i].isvec = 1;
6894 inst.operands[i].isscalar = 2;
6895 inst.operands[i].vectype = optype;
6896 inst.operands[i].present = 1;
6897 }
6898 else
6899 {
6900 first_error (_("VFP single, double or MVE vector register"
6901 " expected"));
6902 return FAIL;
6903 }
477330fc
RM		 6904 }
6905 }
037e8744 6906 else if ((val = arm_typed_reg_parse (&ptr, REG_TYPE_VFS, NULL, &optype))
477330fc
RM		 6907 != FAIL)
6908 {
6909 /* Case 13. */
6910 inst.operands[i].reg = val;
6911 inst.operands[i].isreg = 1;
6912 inst.operands[i].isvec = 1;
6913 inst.operands[i].issingle = 1;
6914 inst.operands[i].vectype = optype;
6915 inst.operands[i].present = 1;
6916 }
5287ad62
JB		 6917 }
6918 else
6919 {
dcbf9037 6920 first_error (_("parse error"));
5287ad62
JB		 6921 return FAIL;
6922 }
6923
6924 /* Successfully parsed the operands. Update args. */
6925 *which_operand = i;
6926 *str = ptr;
6927 return SUCCESS;
6928
5f4273c7 6929 wanted_comma:
dcbf9037 6930 first_error (_("expected comma"));
5287ad62 6931 return FAIL;
5f4273c7
NC		 6932
6933 wanted_arm:
dcbf9037 6934 first_error (_(reg_expected_msgs[REG_TYPE_RN]));
5287ad62 6935 return FAIL;
5287ad62
JB		 6936}
6937
5be8be5d
DG		 6938/* Use this macro when the operand constraints are different
6939 for ARM and THUMB (e.g. ldrd). */
6940#define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6941 ((arm_operand) | ((thumb_operand) << 16))
6942
c19d1205
ZW		 6943/* Matcher codes for parse_operands. */
6944enum operand_parse_code
6945{
6946 OP_stop, /* end of line */
6947
6948 OP_RR, /* ARM register */
6949 OP_RRnpc, /* ARM register, not r15 */
5be8be5d 6950 OP_RRnpcsp, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
c19d1205 6951 OP_RRnpcb, /* ARM register, not r15, in square brackets */
fa94de6b 6952 OP_RRnpctw, /* ARM register, not r15 in Thumb-state or with writeback,
55881a11 6953 optional trailing ! */
c19d1205
ZW		 6954 OP_RRw, /* ARM register, not r15, optional trailing ! */
6955 OP_RCP, /* Coprocessor number */
6956 OP_RCN, /* Coprocessor register */
6957 OP_RF, /* FPA register */
6958 OP_RVS, /* VFP single precision register */
5287ad62
JB		 6959 OP_RVD, /* VFP double precision register (0..15) */
6960 OP_RND, /* Neon double precision register (0..31) */
5ee91343
AV		 6961 OP_RNDMQ, /* Neon double precision (0..31) or MVE vector register. */
6962 OP_RNDMQR, /* Neon double precision (0..31), MVE vector or ARM register.
6963 */
5287ad62 6964 OP_RNQ, /* Neon quad precision register */
5ee91343 6965 OP_RNQMQ, /* Neon quad or MVE vector register. */
037e8744 6966 OP_RVSD, /* VFP single or double precision register */
1b883319 6967 OP_RVSD_COND, /* VFP single, double precision register or condition code. */
dd9634d9 6968 OP_RVSDMQ, /* VFP single, double precision or MVE vector register. */
dec41383 6969 OP_RNSD, /* Neon single or double precision register */
5287ad62 6970 OP_RNDQ, /* Neon double or quad precision register */
5ee91343 6971 OP_RNDQMQ, /* Neon double, quad or MVE vector register. */
7df54120 6972 OP_RNDQMQR, /* Neon double, quad, MVE vector or ARM register. */
037e8744 6973 OP_RNSDQ, /* Neon single, double or quad precision register */
5287ad62 6974 OP_RNSC, /* Neon scalar D[X] */
c19d1205
ZW		 6975 OP_RVC, /* VFP control register */
6976 OP_RMF, /* Maverick F register */
6977 OP_RMD, /* Maverick D register */
6978 OP_RMFX, /* Maverick FX register */
6979 OP_RMDX, /* Maverick DX register */
6980 OP_RMAX, /* Maverick AX register */
6981 OP_RMDS, /* Maverick DSPSC register */
6982 OP_RIWR, /* iWMMXt wR register */
6983 OP_RIWC, /* iWMMXt wC register */
6984 OP_RIWG, /* iWMMXt wCG register */
6985 OP_RXA, /* XScale accumulator register */
6986
5ee91343
AV		 6987 OP_RNSDQMQ, /* Neon single, double or quad register or MVE vector register
6988 */
6989 OP_RNSDQMQR, /* Neon single, double or quad register, MVE vector register or
6990 GPR (no SP/SP) */
a302e574 6991 OP_RMQ, /* MVE vector register. */
1b883319 6992 OP_RMQRZ, /* MVE vector or ARM register including ZR. */
35d1cfc2 6993 OP_RMQRR, /* MVE vector or ARM register. */
a302e574 6994
60f993ce
AV		 6995 /* New operands for Armv8.1-M Mainline. */
6996 OP_LR, /* ARM LR register */
a302e574
AV		 6997 OP_RRe, /* ARM register, only even numbered. */
6998 OP_RRo, /* ARM register, only odd numbered, not r13 or r15. */
60f993ce 6999 OP_RRnpcsp_I32, /* ARM register (no BadReg) or literal 1 .. 32 */
e39c1607 7000 OP_RR_ZR, /* ARM register or ZR but no PC */
60f993ce 7001
c19d1205 7002 OP_REGLST, /* ARM register list */
4b5a202f 7003 OP_CLRMLST, /* CLRM register list */
c19d1205
ZW		 7004 OP_VRSLST, /* VFP single-precision register list */
7005 OP_VRDLST, /* VFP double-precision register list */
037e8744 7006 OP_VRSDLST, /* VFP single or double-precision register list (& quad) */
5287ad62
JB		 7007 OP_NRDLST, /* Neon double-precision register list (d0-d31, qN aliases) */
7008 OP_NSTRLST, /* Neon element/structure list */
efd6b359 7009 OP_VRSDVLST, /* VFP single or double-precision register list and VPR */
35c228db
AV		 7010 OP_MSTRLST2, /* MVE vector list with two elements. */
7011 OP_MSTRLST4, /* MVE vector list with four elements. */
5287ad62 7012
5287ad62 7013 OP_RNDQ_I0, /* Neon D or Q reg, or immediate zero. */
037e8744 7014 OP_RVSD_I0, /* VFP S or D reg, or immediate zero. */
aacf0b33 7015 OP_RSVD_FI0, /* VFP S or D reg, or floating point immediate zero. */
1b883319
AV		 7016 OP_RSVDMQ_FI0, /* VFP S, D, MVE vector register or floating point immediate
7017 zero. */
5287ad62 7018 OP_RR_RNSC, /* ARM reg or Neon scalar. */
dec41383 7019 OP_RNSD_RNSC, /* Neon S or D reg, or Neon scalar. */
037e8744 7020 OP_RNSDQ_RNSC, /* Vector S, D or Q reg, or Neon scalar. */
886e1c73
AV		 7021 OP_RNSDQ_RNSC_MQ, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7022 */
a8465a06
AV		 7023 OP_RNSDQ_RNSC_MQ_RR, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7024 scalar, or ARM register. */
5287ad62 7025 OP_RNDQ_RNSC, /* Neon D or Q reg, or Neon scalar. */
42b16635
AV		 7026 OP_RNDQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, or ARM register. */
7027 OP_RNDQMQ_RNSC_RR, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7028 register. */
5d281bf0 7029 OP_RNDQMQ_RNSC, /* Neon D, Q or MVE vector reg, or Neon scalar. */
5287ad62
JB		 7030 OP_RND_RNSC, /* Neon D reg, or Neon scalar. */
7031 OP_VMOV, /* Neon VMOV operands. */
4316f0d2 7032 OP_RNDQ_Ibig, /* Neon D or Q reg, or big immediate for logic and VMVN. */
f601a00c
AV		 7033 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7034 OP_RNDQMQ_Ibig,
5287ad62 7035 OP_RNDQ_I63b, /* Neon D or Q reg, or immediate for shift. */
5150f0d8
AV		 7036 OP_RNDQMQ_I63b_RR, /* Neon D or Q reg, immediate for shift, MVE vector or
7037 ARM register. */
2d447fca 7038 OP_RIWR_I32z, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
32c36c3c 7039 OP_VLDR, /* VLDR operand. */
5287ad62
JB		 7040
7041 OP_I0, /* immediate zero */
c19d1205
ZW		 7042 OP_I7, /* immediate value 0 .. 7 */
7043 OP_I15, /* 0 .. 15 */
7044 OP_I16, /* 1 .. 16 */
5287ad62 7045 OP_I16z, /* 0 .. 16 */
c19d1205
ZW		 7046 OP_I31, /* 0 .. 31 */
7047 OP_I31w, /* 0 .. 31, optional trailing ! */
7048 OP_I32, /* 1 .. 32 */
5287ad62 7049 OP_I32z, /* 0 .. 32 */
08132bdd 7050 OP_I48_I64, /* 48 or 64 */
5287ad62 7051 OP_I63, /* 0 .. 63 */
c19d1205 7052 OP_I63s, /* -64 .. 63 */
5287ad62
JB		 7053 OP_I64, /* 1 .. 64 */
7054 OP_I64z, /* 0 .. 64 */
c19d1205 7055 OP_I255, /* 0 .. 255 */
c19d1205
ZW		 7056
7057 OP_I4b, /* immediate, prefix optional, 1 .. 4 */
7058 OP_I7b, /* 0 .. 7 */
7059 OP_I15b, /* 0 .. 15 */
7060 OP_I31b, /* 0 .. 31 */
7061
7062 OP_SH, /* shifter operand */
4962c51a 7063 OP_SHG, /* shifter operand with possible group relocation */
c19d1205 7064 OP_ADDR, /* Memory address expression (any mode) */
35c228db 7065 OP_ADDRMVE, /* Memory address expression for MVE's VSTR/VLDR. */
4962c51a
MS		 7066 OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
7067 OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
7068 OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
c19d1205
ZW		 7069 OP_EXP, /* arbitrary expression */
7070 OP_EXPi, /* same, with optional immediate prefix */
7071 OP_EXPr, /* same, with optional relocation suffix */
e2b0ab59 7072 OP_EXPs, /* same, with optional non-first operand relocation suffix */
b6895b4f 7073 OP_HALF, /* 0 .. 65535 or low/high reloc. */
c28eeff2
SN		 7074 OP_IROT1, /* VCADD rotate immediate: 90, 270. */
7075 OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
c19d1205
ZW		 7076
7077 OP_CPSF, /* CPS flags */
7078 OP_ENDI, /* Endianness specifier */
d2cd1205
JB		 7079 OP_wPSR, /* CPSR/SPSR/APSR mask for msr (writing). */
7080 OP_rPSR, /* CPSR/SPSR/APSR mask for msr (reading). */
c19d1205 7081 OP_COND, /* conditional code */
92e90b6e 7082 OP_TB, /* Table branch. */
c19d1205 7083
037e8744
JB		 7084 OP_APSR_RR, /* ARM register or "APSR_nzcv". */
7085
c19d1205 7086 OP_RRnpc_I0, /* ARM register or literal 0 */
33eaf5de 7087 OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
c19d1205
ZW		 7088 OP_RR_EXi, /* ARM register or expression with imm prefix */
7089 OP_RF_IF, /* FPA register or immediate */
7090 OP_RIWR_RIWC, /* iWMMXt R or C reg */
41adaa5c 7091 OP_RIWC_RIWG, /* iWMMXt wC or wCG reg */
c19d1205
ZW		 7092
7093 /* Optional operands. */
7094 OP_oI7b, /* immediate, prefix optional, 0 .. 7 */
7095 OP_oI31b, /* 0 .. 31 */
5287ad62 7096 OP_oI32b, /* 1 .. 32 */
5f1af56b 7097 OP_oI32z, /* 0 .. 32 */
c19d1205
ZW		 7098 OP_oIffffb, /* 0 .. 65535 */
7099 OP_oI255c, /* curly-brace enclosed, 0 .. 255 */
7100
7101 OP_oRR, /* ARM register */
60f993ce 7102 OP_oLR, /* ARM LR register */
c19d1205 7103 OP_oRRnpc, /* ARM register, not the PC */
5be8be5d 7104 OP_oRRnpcsp, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
b6702015 7105 OP_oRRw, /* ARM register, not r15, optional trailing ! */
5287ad62
JB		 7106 OP_oRND, /* Optional Neon double precision register */
7107 OP_oRNQ, /* Optional Neon quad precision register */
5ee91343 7108 OP_oRNDQMQ, /* Optional Neon double, quad or MVE vector register. */
5287ad62 7109 OP_oRNDQ, /* Optional Neon double or quad precision register */
037e8744 7110 OP_oRNSDQ, /* Optional single, double or quad precision vector register */
5ee91343
AV		 7111 OP_oRNSDQMQ, /* Optional single, double or quad register or MVE vector
7112 register. */
c19d1205
ZW		 7113 OP_oSHll, /* LSL immediate */
7114 OP_oSHar, /* ASR immediate */
7115 OP_oSHllar, /* LSL or ASR immediate */
7116 OP_oROR, /* ROR 0/8/16/24 */
52e7f43d 7117 OP_oBARRIER_I15, /* Option argument for a barrier instruction. */
c19d1205 7118
1b883319
AV		 7119 OP_oRMQRZ, /* optional MVE vector or ARM register including ZR. */
7120
5be8be5d
DG		 7121 /* Some pre-defined mixed (ARM/THUMB) operands. */
7122 OP_RR_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RR, OP_RRnpcsp),
7123 OP_RRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_RRnpc, OP_RRnpcsp),
7124 OP_oRRnpc_npcsp = MIX_ARM_THUMB_OPERANDS (OP_oRRnpc, OP_oRRnpcsp),
7125
c19d1205
ZW		 7126 OP_FIRST_OPTIONAL = OP_oI7b
7127};
a737bd4d 7128
c19d1205
ZW		 7129/* Generic instruction operand parser. This does no encoding and no
7130 semantic validation; it merely squirrels values away in the inst
7131 structure. Returns SUCCESS or FAIL depending on whether the
7132 specified grammar matched. */
7133static int
5be8be5d 7134parse_operands (char *str, const unsigned int *pattern, bfd_boolean thumb)
c19d1205 7135{
5be8be5d 7136 unsigned const int *upat = pattern;
c19d1205
ZW		 7137 char *backtrack_pos = 0;
7138 const char *backtrack_error = 0;
99aad254 7139 int i, val = 0, backtrack_index = 0;
5287ad62 7140 enum arm_reg_type rtype;
4962c51a 7141 parse_operand_result result;
5be8be5d 7142 unsigned int op_parse_code;
efd6b359 7143 bfd_boolean partial_match;
c19d1205 7144
e07e6e58
NC		 7145#define po_char_or_fail(chr) \
7146 do \
7147 { \
7148 if (skip_past_char (&str, chr) == FAIL) \
477330fc 7149 goto bad_args; \
e07e6e58
NC		 7150 } \
7151 while (0)
c19d1205 7152
e07e6e58
NC		 7153#define po_reg_or_fail(regtype) \
7154 do \
dcbf9037 7155 { \
e07e6e58 7156 val = arm_typed_reg_parse (& str, regtype, & rtype, \
477330fc 7157 & inst.operands[i].vectype); \
e07e6e58 7158 if (val == FAIL) \
477330fc
RM		 7159 { \
7160 first_error (_(reg_expected_msgs[regtype])); \
7161 goto failure; \
7162 } \
e07e6e58
NC		 7163 inst.operands[i].reg = val; \
7164 inst.operands[i].isreg = 1; \
7165 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7166 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7167 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc
RM		 7168 || rtype == REG_TYPE_VFD \
7169 || rtype == REG_TYPE_NQ); \
1b883319 7170 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
dcbf9037 7171 } \
e07e6e58
NC		 7172 while (0)
7173
7174#define po_reg_or_goto(regtype, label) \
7175 do \
7176 { \
7177 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7178 & inst.operands[i].vectype); \
7179 if (val == FAIL) \
7180 goto label; \
dcbf9037 7181 \
e07e6e58
NC		 7182 inst.operands[i].reg = val; \
7183 inst.operands[i].isreg = 1; \
7184 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7185 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7186 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
477330fc 7187 || rtype == REG_TYPE_VFD \
e07e6e58 7188 || rtype == REG_TYPE_NQ); \
1b883319 7189 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
e07e6e58
NC		 7190 } \
7191 while (0)
7192
7193#define po_imm_or_fail(min, max, popt) \
7194 do \
7195 { \
7196 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7197 goto failure; \
7198 inst.operands[i].imm = val; \
7199 } \
7200 while (0)
7201
08132bdd
SP		 7202#define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7203 do \
7204 { \
7205 expressionS exp; \
7206 my_get_expression (&exp, &str, popt); \
7207 if (exp.X_op != O_constant) \
7208 { \
7209 inst.error = _("constant expression required"); \
7210 goto failure; \
7211 } \
7212 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7213 { \
7214 inst.error = _("immediate value 48 or 64 expected"); \
7215 goto failure; \
7216 } \
7217 inst.operands[i].imm = exp.X_add_number; \
7218 } \
7219 while (0)
7220
57785aa2 7221#define po_scalar_or_goto(elsz, label, reg_type) \
e07e6e58
NC		 7222 do \
7223 { \
57785aa2
AV		 7224 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7225 reg_type); \
e07e6e58
NC		 7226 if (val == FAIL) \
7227 goto label; \
7228 inst.operands[i].reg = val; \
7229 inst.operands[i].isscalar = 1; \
7230 } \
7231 while (0)
7232
7233#define po_misc_or_fail(expr) \
7234 do \
7235 { \
7236 if (expr) \
7237 goto failure; \
7238 } \
7239 while (0)
7240
7241#define po_misc_or_fail_no_backtrack(expr) \
7242 do \
7243 { \
7244 result = expr; \
7245 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7246 backtrack_pos = 0; \
7247 if (result != PARSE_OPERAND_SUCCESS) \
7248 goto failure; \
7249 } \
7250 while (0)
4962c51a 7251
52e7f43d
RE		 7252#define po_barrier_or_imm(str) \
7253 do \
7254 { \
7255 val = parse_barrier (&str); \
ccb84d65
JB		 7256 if (val == FAIL && ! ISALPHA (*str)) \
7257 goto immediate; \
7258 if (val == FAIL \
7259 /* ISB can only take SY as an option. */ \
7260 || ((inst.instruction & 0xf0) == 0x60 \
7261 && val != 0xf)) \
52e7f43d 7262 { \
ccb84d65
JB		 7263 inst.error = _("invalid barrier type"); \
7264 backtrack_pos = 0; \
7265 goto failure; \
52e7f43d
RE		 7266 } \
7267 } \
7268 while (0)
7269
c19d1205
ZW		 7270 skip_whitespace (str);
7271
7272 for (i = 0; upat[i] != OP_stop; i++)
7273 {
5be8be5d
DG		 7274 op_parse_code = upat[i];
7275 if (op_parse_code >= 1<<16)
7276 op_parse_code = thumb ? (op_parse_code >> 16)
7277 : (op_parse_code & ((1<<16)-1));
7278
7279 if (op_parse_code >= OP_FIRST_OPTIONAL)
c19d1205
ZW		 7280 {
7281 /* Remember where we are in case we need to backtrack. */
c19d1205
ZW		 7282 backtrack_pos = str;
7283 backtrack_error = inst.error;
7284 backtrack_index = i;
7285 }
7286
b6702015 7287 if (i > 0 && (i > 1 || inst.operands[0].present))
c19d1205
ZW		 7288 po_char_or_fail (',');
7289
5be8be5d 7290 switch (op_parse_code)
c19d1205
ZW		 7291 {
7292 /* Registers */
7293 case OP_oRRnpc:
5be8be5d 7294 case OP_oRRnpcsp:
c19d1205 7295 case OP_RRnpc:
5be8be5d 7296 case OP_RRnpcsp:
c19d1205 7297 case OP_oRR:
a302e574
AV		 7298 case OP_RRe:
7299 case OP_RRo:
60f993ce
AV		 7300 case OP_LR:
7301 case OP_oLR:
c19d1205
ZW		 7302 case OP_RR: po_reg_or_fail (REG_TYPE_RN); break;
7303 case OP_RCP: po_reg_or_fail (REG_TYPE_CP); break;
7304 case OP_RCN: po_reg_or_fail (REG_TYPE_CN); break;
7305 case OP_RF: po_reg_or_fail (REG_TYPE_FN); break;
7306 case OP_RVS: po_reg_or_fail (REG_TYPE_VFS); break;
7307 case OP_RVD: po_reg_or_fail (REG_TYPE_VFD); break;
477330fc 7308 case OP_oRND:
5ee91343
AV		 7309 case OP_RNDMQR:
7310 po_reg_or_goto (REG_TYPE_RN, try_rndmq);
7311 break;
7312 try_rndmq:
7313 case OP_RNDMQ:
7314 po_reg_or_goto (REG_TYPE_MQ, try_rnd);
7315 break;
7316 try_rnd:
5287ad62 7317 case OP_RND: po_reg_or_fail (REG_TYPE_VFD); break;
cd2cf30b
PB		 7318 case OP_RVC:
7319 po_reg_or_goto (REG_TYPE_VFC, coproc_reg);
7320 break;
7321 /* Also accept generic coprocessor regs for unknown registers. */
7322 coproc_reg:
ba6cd17f
SD		 7323 po_reg_or_goto (REG_TYPE_CN, vpr_po);
7324 break;
7325 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7326 existing register with a value of 0, this seems like the
7327 best way to parse P0. */
7328 vpr_po:
7329 if (strncasecmp (str, "P0", 2) == 0)
7330 {
7331 str += 2;
7332 inst.operands[i].isreg = 1;
7333 inst.operands[i].reg = 13;
7334 }
7335 else
7336 goto failure;
cd2cf30b 7337 break;
c19d1205
ZW		 7338 case OP_RMF: po_reg_or_fail (REG_TYPE_MVF); break;
7339 case OP_RMD: po_reg_or_fail (REG_TYPE_MVD); break;
7340 case OP_RMFX: po_reg_or_fail (REG_TYPE_MVFX); break;
7341 case OP_RMDX: po_reg_or_fail (REG_TYPE_MVDX); break;
7342 case OP_RMAX: po_reg_or_fail (REG_TYPE_MVAX); break;
7343 case OP_RMDS: po_reg_or_fail (REG_TYPE_DSPSC); break;
7344 case OP_RIWR: po_reg_or_fail (REG_TYPE_MMXWR); break;
7345 case OP_RIWC: po_reg_or_fail (REG_TYPE_MMXWC); break;
7346 case OP_RIWG: po_reg_or_fail (REG_TYPE_MMXWCG); break;
7347 case OP_RXA: po_reg_or_fail (REG_TYPE_XSCALE); break;
477330fc 7348 case OP_oRNQ:
5ee91343
AV		 7349 case OP_RNQMQ:
7350 po_reg_or_goto (REG_TYPE_MQ, try_nq);
7351 break;
7352 try_nq:
5287ad62 7353 case OP_RNQ: po_reg_or_fail (REG_TYPE_NQ); break;
dec41383 7354 case OP_RNSD: po_reg_or_fail (REG_TYPE_NSD); break;
7df54120
AV		 7355 case OP_RNDQMQR:
7356 po_reg_or_goto (REG_TYPE_RN, try_rndqmq);
7357 break;
7358 try_rndqmq:
5ee91343
AV		 7359 case OP_oRNDQMQ:
7360 case OP_RNDQMQ:
7361 po_reg_or_goto (REG_TYPE_MQ, try_rndq);
7362 break;
7363 try_rndq:
477330fc 7364 case OP_oRNDQ:
5287ad62 7365 case OP_RNDQ: po_reg_or_fail (REG_TYPE_NDQ); break;
dd9634d9
AV		 7366 case OP_RVSDMQ:
7367 po_reg_or_goto (REG_TYPE_MQ, try_rvsd);
7368 break;
7369 try_rvsd:
477330fc 7370 case OP_RVSD: po_reg_or_fail (REG_TYPE_VFSD); break;
1b883319
AV		 7371 case OP_RVSD_COND:
7372 po_reg_or_goto (REG_TYPE_VFSD, try_cond);
7373 break;
477330fc
RM		 7374 case OP_oRNSDQ:
7375 case OP_RNSDQ: po_reg_or_fail (REG_TYPE_NSDQ); break;
5ee91343
AV		 7376 case OP_RNSDQMQR:
7377 po_reg_or_goto (REG_TYPE_RN, try_mq);
7378 break;
7379 try_mq:
7380 case OP_oRNSDQMQ:
7381 case OP_RNSDQMQ:
7382 po_reg_or_goto (REG_TYPE_MQ, try_nsdq2);
7383 break;
7384 try_nsdq2:
7385 po_reg_or_fail (REG_TYPE_NSDQ);
7386 inst.error = 0;
7387 break;
35d1cfc2
AV		 7388 case OP_RMQRR:
7389 po_reg_or_goto (REG_TYPE_RN, try_rmq);
7390 break;
7391 try_rmq:
a302e574
AV		 7392 case OP_RMQ:
7393 po_reg_or_fail (REG_TYPE_MQ);
7394 break;
477330fc
RM		 7395 /* Neon scalar. Using an element size of 8 means that some invalid
7396 scalars are accepted here, so deal with those in later code. */
57785aa2 7397 case OP_RNSC: po_scalar_or_goto (8, failure, REG_TYPE_VFD); break;
477330fc
RM		 7398
7399 case OP_RNDQ_I0:
7400 {
7401 po_reg_or_goto (REG_TYPE_NDQ, try_imm0);
7402 break;
7403 try_imm0:
7404 po_imm_or_fail (0, 0, TRUE);
7405 }
7406 break;
7407
7408 case OP_RVSD_I0:
7409 po_reg_or_goto (REG_TYPE_VFSD, try_imm0);
7410 break;
7411
1b883319
AV		 7412 case OP_RSVDMQ_FI0:
7413 po_reg_or_goto (REG_TYPE_MQ, try_rsvd_fi0);
7414 break;
7415 try_rsvd_fi0:
aacf0b33
KT		 7416 case OP_RSVD_FI0:
7417 {
7418 po_reg_or_goto (REG_TYPE_VFSD, try_ifimm0);
7419 break;
7420 try_ifimm0:
7421 if (parse_ifimm_zero (&str))
7422 inst.operands[i].imm = 0;
7423 else
7424 {
7425 inst.error
7426 = _("only floating point zero is allowed as immediate value");
7427 goto failure;
7428 }
7429 }
7430 break;
7431
477330fc
RM		 7432 case OP_RR_RNSC:
7433 {
57785aa2 7434 po_scalar_or_goto (8, try_rr, REG_TYPE_VFD);
477330fc
RM		 7435 break;
7436 try_rr:
7437 po_reg_or_fail (REG_TYPE_RN);
7438 }
7439 break;
7440
a8465a06
AV		 7441 case OP_RNSDQ_RNSC_MQ_RR:
7442 po_reg_or_goto (REG_TYPE_RN, try_rnsdq_rnsc_mq);
7443 break;
7444 try_rnsdq_rnsc_mq:
886e1c73
AV		 7445 case OP_RNSDQ_RNSC_MQ:
7446 po_reg_or_goto (REG_TYPE_MQ, try_rnsdq_rnsc);
7447 break;
7448 try_rnsdq_rnsc:
477330fc
RM		 7449 case OP_RNSDQ_RNSC:
7450 {
57785aa2
AV		 7451 po_scalar_or_goto (8, try_nsdq, REG_TYPE_VFD);
7452 inst.error = 0;
477330fc
RM		 7453 break;
7454 try_nsdq:
7455 po_reg_or_fail (REG_TYPE_NSDQ);
57785aa2 7456 inst.error = 0;
477330fc
RM		 7457 }
7458 break;
7459
dec41383
JW		 7460 case OP_RNSD_RNSC:
7461 {
57785aa2 7462 po_scalar_or_goto (8, try_s_scalar, REG_TYPE_VFD);
dec41383
JW		 7463 break;
7464 try_s_scalar:
57785aa2 7465 po_scalar_or_goto (4, try_nsd, REG_TYPE_VFS);
dec41383
JW		 7466 break;
7467 try_nsd:
7468 po_reg_or_fail (REG_TYPE_NSD);
7469 }
7470 break;
7471
42b16635
AV		 7472 case OP_RNDQMQ_RNSC_RR:
7473 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc_rr);
7474 break;
7475 try_rndq_rnsc_rr:
7476 case OP_RNDQ_RNSC_RR:
7477 po_reg_or_goto (REG_TYPE_RN, try_rndq_rnsc);
7478 break;
5d281bf0
AV		 7479 case OP_RNDQMQ_RNSC:
7480 po_reg_or_goto (REG_TYPE_MQ, try_rndq_rnsc);
7481 break;
7482 try_rndq_rnsc:
477330fc
RM		 7483 case OP_RNDQ_RNSC:
7484 {
57785aa2 7485 po_scalar_or_goto (8, try_ndq, REG_TYPE_VFD);
477330fc
RM		 7486 break;
7487 try_ndq:
7488 po_reg_or_fail (REG_TYPE_NDQ);
7489 }
7490 break;
7491
7492 case OP_RND_RNSC:
7493 {
57785aa2 7494 po_scalar_or_goto (8, try_vfd, REG_TYPE_VFD);
477330fc
RM		 7495 break;
7496 try_vfd:
7497 po_reg_or_fail (REG_TYPE_VFD);
7498 }
7499 break;
7500
7501 case OP_VMOV:
7502 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7503 not careful then bad things might happen. */
7504 po_misc_or_fail (parse_neon_mov (&str, &i) == FAIL);
7505 break;
7506
f601a00c
AV		 7507 case OP_RNDQMQ_Ibig:
7508 po_reg_or_goto (REG_TYPE_MQ, try_rndq_ibig);
7509 break;
7510 try_rndq_ibig:
477330fc
RM		 7511 case OP_RNDQ_Ibig:
7512 {
7513 po_reg_or_goto (REG_TYPE_NDQ, try_immbig);
7514 break;
7515 try_immbig:
7516 /* There's a possibility of getting a 64-bit immediate here, so
7517 we need special handling. */
8335d6aa
JW		 7518 if (parse_big_immediate (&str, i, NULL, /*allow_symbol_p=*/FALSE)
7519 == FAIL)
477330fc
RM		 7520 {
7521 inst.error = _("immediate value is out of range");
7522 goto failure;
7523 }
7524 }
7525 break;
7526
5150f0d8
AV		 7527 case OP_RNDQMQ_I63b_RR:
7528 po_reg_or_goto (REG_TYPE_MQ, try_rndq_i63b_rr);
7529 break;
7530 try_rndq_i63b_rr:
7531 po_reg_or_goto (REG_TYPE_RN, try_rndq_i63b);
7532 break;
7533 try_rndq_i63b:
477330fc
RM		 7534 case OP_RNDQ_I63b:
7535 {
7536 po_reg_or_goto (REG_TYPE_NDQ, try_shimm);
7537 break;
7538 try_shimm:
7539 po_imm_or_fail (0, 63, TRUE);
7540 }
7541 break;
c19d1205
ZW		 7542
7543 case OP_RRnpcb:
7544 po_char_or_fail ('[');
7545 po_reg_or_fail (REG_TYPE_RN);
7546 po_char_or_fail (']');
7547 break;
a737bd4d 7548
55881a11 7549 case OP_RRnpctw:
c19d1205 7550 case OP_RRw:
b6702015 7551 case OP_oRRw:
c19d1205
ZW		 7552 po_reg_or_fail (REG_TYPE_RN);
7553 if (skip_past_char (&str, '!') == SUCCESS)
7554 inst.operands[i].writeback = 1;
7555 break;
7556
7557 /* Immediates */
7558 case OP_I7: po_imm_or_fail ( 0, 7, FALSE); break;
7559 case OP_I15: po_imm_or_fail ( 0, 15, FALSE); break;
7560 case OP_I16: po_imm_or_fail ( 1, 16, FALSE); break;
477330fc 7561 case OP_I16z: po_imm_or_fail ( 0, 16, FALSE); break;
c19d1205
ZW		 7562 case OP_I31: po_imm_or_fail ( 0, 31, FALSE); break;
7563 case OP_I32: po_imm_or_fail ( 1, 32, FALSE); break;
477330fc 7564 case OP_I32z: po_imm_or_fail ( 0, 32, FALSE); break;
08132bdd 7565 case OP_I48_I64: po_imm1_or_imm2_or_fail (48, 64, FALSE); break;
c19d1205 7566 case OP_I63s: po_imm_or_fail (-64, 63, FALSE); break;
477330fc
RM		 7567 case OP_I63: po_imm_or_fail ( 0, 63, FALSE); break;
7568 case OP_I64: po_imm_or_fail ( 1, 64, FALSE); break;
7569 case OP_I64z: po_imm_or_fail ( 0, 64, FALSE); break;
c19d1205 7570 case OP_I255: po_imm_or_fail ( 0, 255, FALSE); break;
c19d1205
ZW		 7571
7572 case OP_I4b: po_imm_or_fail ( 1, 4, TRUE); break;
7573 case OP_oI7b:
7574 case OP_I7b: po_imm_or_fail ( 0, 7, TRUE); break;
7575 case OP_I15b: po_imm_or_fail ( 0, 15, TRUE); break;
7576 case OP_oI31b:
7577 case OP_I31b: po_imm_or_fail ( 0, 31, TRUE); break;
477330fc
RM		 7578 case OP_oI32b: po_imm_or_fail ( 1, 32, TRUE); break;
7579 case OP_oI32z: po_imm_or_fail ( 0, 32, TRUE); break;
c19d1205
ZW		 7580 case OP_oIffffb: po_imm_or_fail ( 0, 0xffff, TRUE); break;
7581
7582 /* Immediate variants */
7583 case OP_oI255c:
7584 po_char_or_fail ('{');
7585 po_imm_or_fail (0, 255, TRUE);
7586 po_char_or_fail ('}');
7587 break;
7588
7589 case OP_I31w:
7590 /* The expression parser chokes on a trailing !, so we have
7591 to find it first and zap it. */
7592 {
7593 char *s = str;
7594 while (*s && *s != ',')
7595 s++;
7596 if (s[-1] == '!')
7597 {
7598 s[-1] = '\0';
7599 inst.operands[i].writeback = 1;
7600 }
7601 po_imm_or_fail (0, 31, TRUE);
7602 if (str == s - 1)
7603 str = s;
7604 }
7605 break;
7606
7607 /* Expressions */
7608 case OP_EXPi: EXPi:
e2b0ab59 7609 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW		 7610 GE_OPT_PREFIX));
7611 break;
7612
7613 case OP_EXP:
e2b0ab59 7614 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205
ZW		 7615 GE_NO_PREFIX));
7616 break;
7617
7618 case OP_EXPr: EXPr:
e2b0ab59 7619 po_misc_or_fail (my_get_expression (&inst.relocs[0].exp, &str,
c19d1205 7620 GE_NO_PREFIX));
e2b0ab59 7621 if (inst.relocs[0].exp.X_op == O_symbol)
a737bd4d 7622 {
c19d1205
ZW		 7623 val = parse_reloc (&str);
7624 if (val == -1)
7625 {
7626 inst.error = _("unrecognized relocation suffix");
7627 goto failure;
7628 }
7629 else if (val != BFD_RELOC_UNUSED)
7630 {
7631 inst.operands[i].imm = val;
7632 inst.operands[i].hasreloc = 1;
7633 }
a737bd4d 7634 }
c19d1205 7635 break;
a737bd4d 7636
e2b0ab59
AV		 7637 case OP_EXPs:
7638 po_misc_or_fail (my_get_expression (&inst.relocs[i].exp, &str,
7639 GE_NO_PREFIX));
7640 if (inst.relocs[i].exp.X_op == O_symbol)
7641 {
7642 inst.operands[i].hasreloc = 1;
7643 }
7644 else if (inst.relocs[i].exp.X_op == O_constant)
7645 {
7646 inst.operands[i].imm = inst.relocs[i].exp.X_add_number;
7647 inst.operands[i].hasreloc = 0;
7648 }
7649 break;
7650
b6895b4f
PB		 7651 /* Operand for MOVW or MOVT. */
7652 case OP_HALF:
7653 po_misc_or_fail (parse_half (&str));
7654 break;
7655
e07e6e58 7656 /* Register or expression. */
c19d1205
ZW		 7657 case OP_RR_EXr: po_reg_or_goto (REG_TYPE_RN, EXPr); break;
7658 case OP_RR_EXi: po_reg_or_goto (REG_TYPE_RN, EXPi); break;
a737bd4d 7659
e07e6e58 7660 /* Register or immediate. */
c19d1205
ZW		 7661 case OP_RRnpc_I0: po_reg_or_goto (REG_TYPE_RN, I0); break;
7662 I0: po_imm_or_fail (0, 0, FALSE); break;
a737bd4d 7663
23d00a41
SD		 7664 case OP_RRnpcsp_I32: po_reg_or_goto (REG_TYPE_RN, I32); break;
7665 I32: po_imm_or_fail (1, 32, FALSE); break;
7666
c19d1205
ZW		 7667 case OP_RF_IF: po_reg_or_goto (REG_TYPE_FN, IF); break;
7668 IF:
7669 if (!is_immediate_prefix (*str))
7670 goto bad_args;
7671 str++;
7672 val = parse_fpa_immediate (&str);
7673 if (val == FAIL)
7674 goto failure;
7675 /* FPA immediates are encoded as registers 8-15.
7676 parse_fpa_immediate has already applied the offset. */
7677 inst.operands[i].reg = val;
7678 inst.operands[i].isreg = 1;
7679 break;
09d92015 7680
2d447fca
JM		 7681 case OP_RIWR_I32z: po_reg_or_goto (REG_TYPE_MMXWR, I32z); break;
7682 I32z: po_imm_or_fail (0, 32, FALSE); break;
7683
e07e6e58 7684 /* Two kinds of register. */
c19d1205
ZW		 7685 case OP_RIWR_RIWC:
7686 {
7687 struct reg_entry *rege = arm_reg_parse_multi (&str);
97f87066
JM		 7688 if (!rege
7689 || (rege->type != REG_TYPE_MMXWR
7690 && rege->type != REG_TYPE_MMXWC
7691 && rege->type != REG_TYPE_MMXWCG))
c19d1205
ZW		 7692 {
7693 inst.error = _("iWMMXt data or control register expected");
7694 goto failure;
7695 }
7696 inst.operands[i].reg = rege->number;
7697 inst.operands[i].isreg = (rege->type == REG_TYPE_MMXWR);
7698 }
7699 break;
09d92015 7700
41adaa5c
JM		 7701 case OP_RIWC_RIWG:
7702 {
7703 struct reg_entry *rege = arm_reg_parse_multi (&str);
7704 if (!rege
7705 || (rege->type != REG_TYPE_MMXWC
7706 && rege->type != REG_TYPE_MMXWCG))
7707 {
7708 inst.error = _("iWMMXt control register expected");
7709 goto failure;
7710 }
7711 inst.operands[i].reg = rege->number;
7712 inst.operands[i].isreg = 1;
7713 }
7714 break;
7715
c19d1205
ZW		 7716 /* Misc */
7717 case OP_CPSF: val = parse_cps_flags (&str); break;
7718 case OP_ENDI: val = parse_endian_specifier (&str); break;
7719 case OP_oROR: val = parse_ror (&str); break;
1b883319 7720 try_cond:
c19d1205 7721 case OP_COND: val = parse_cond (&str); break;
52e7f43d
RE		 7722 case OP_oBARRIER_I15:
7723 po_barrier_or_imm (str); break;
7724 immediate:
7725 if (parse_immediate (&str, &val, 0, 15, TRUE) == FAIL)
477330fc 7726 goto failure;
52e7f43d 7727 break;
c19d1205 7728
fa94de6b 7729 case OP_wPSR:
d2cd1205 7730 case OP_rPSR:
90ec0d68
MGD		 7731 po_reg_or_goto (REG_TYPE_RNB, try_psr);
7732 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_virt))
7733 {
7734 inst.error = _("Banked registers are not available with this "
7735 "architecture.");
7736 goto failure;
7737 }
7738 break;
d2cd1205
JB		 7739 try_psr:
7740 val = parse_psr (&str, op_parse_code == OP_wPSR);
7741 break;
037e8744 7742
32c36c3c
AV		 7743 case OP_VLDR:
7744 po_reg_or_goto (REG_TYPE_VFSD, try_sysreg);
7745 break;
7746 try_sysreg:
7747 val = parse_sys_vldr_vstr (&str);
7748 break;
7749
477330fc
RM		 7750 case OP_APSR_RR:
7751 po_reg_or_goto (REG_TYPE_RN, try_apsr);
7752 break;
7753 try_apsr:
7754 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7755 instruction). */
7756 if (strncasecmp (str, "APSR_", 5) == 0)
7757 {
7758 unsigned found = 0;
7759 str += 5;
7760 while (found < 15)
7761 switch (*str++)
7762 {
7763 case 'c': found = (found & 1) ? 16 : found | 1; break;
7764 case 'n': found = (found & 2) ? 16 : found | 2; break;
7765 case 'z': found = (found & 4) ? 16 : found | 4; break;
7766 case 'v': found = (found & 8) ? 16 : found | 8; break;
7767 default: found = 16;
7768 }
7769 if (found != 15)
7770 goto failure;
7771 inst.operands[i].isvec = 1;
f7c21dc7
NC		 7772 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7773 inst.operands[i].reg = REG_PC;
477330fc
RM		 7774 }
7775 else
7776 goto failure;
7777 break;
037e8744 7778
92e90b6e
PB		 7779 case OP_TB:
7780 po_misc_or_fail (parse_tb (&str));
7781 break;
7782
e07e6e58 7783 /* Register lists. */
c19d1205 7784 case OP_REGLST:
4b5a202f 7785 val = parse_reg_list (&str, REGLIST_RN);
c19d1205
ZW		 7786 if (*str == '^')
7787 {
5e0d7f77 7788 inst.operands[i].writeback = 1;
c19d1205
ZW		 7789 str++;
7790 }
7791 break;
09d92015 7792
4b5a202f
AV		 7793 case OP_CLRMLST:
7794 val = parse_reg_list (&str, REGLIST_CLRM);
7795 break;
7796
c19d1205 7797 case OP_VRSLST:
efd6b359
AV		 7798 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_S,
7799 &partial_match);
c19d1205 7800 break;
09d92015 7801
c19d1205 7802 case OP_VRDLST:
efd6b359
AV		 7803 val = parse_vfp_reg_list (&str, &inst.operands[i].reg, REGLIST_VFP_D,
7804 &partial_match);
c19d1205 7805 break;
a737bd4d 7806
477330fc
RM		 7807 case OP_VRSDLST:
7808 /* Allow Q registers too. */
7809 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7810 REGLIST_NEON_D, &partial_match);
477330fc
RM		 7811 if (val == FAIL)
7812 {
7813 inst.error = NULL;
7814 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359
AV		 7815 REGLIST_VFP_S, &partial_match);
7816 inst.operands[i].issingle = 1;
7817 }
7818 break;
7819
7820 case OP_VRSDVLST:
7821 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7822 REGLIST_VFP_D_VPR, &partial_match);
7823 if (val == FAIL && !partial_match)
7824 {
7825 inst.error = NULL;
7826 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
7827 REGLIST_VFP_S_VPR, &partial_match);
477330fc
RM		 7828 inst.operands[i].issingle = 1;
7829 }
7830 break;
7831
7832 case OP_NRDLST:
7833 val = parse_vfp_reg_list (&str, &inst.operands[i].reg,
efd6b359 7834 REGLIST_NEON_D, &partial_match);
477330fc 7835 break;
5287ad62 7836
35c228db
AV		 7837 case OP_MSTRLST4:
7838 case OP_MSTRLST2:
7839 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
7840 1, &inst.operands[i].vectype);
7841 if (val != (((op_parse_code == OP_MSTRLST2) ? 3 : 7) << 5 | 0xe))
7842 goto failure;
7843 break;
5287ad62 7844 case OP_NSTRLST:
477330fc 7845 val = parse_neon_el_struct_list (&str, &inst.operands[i].reg,
35c228db 7846 0, &inst.operands[i].vectype);
477330fc 7847 break;
5287ad62 7848
c19d1205 7849 /* Addressing modes */
35c228db
AV		 7850 case OP_ADDRMVE:
7851 po_misc_or_fail (parse_address_group_reloc (&str, i, GROUP_MVE));
7852 break;
7853
c19d1205
ZW		 7854 case OP_ADDR:
7855 po_misc_or_fail (parse_address (&str, i));
7856 break;
09d92015 7857
4962c51a
MS		 7858 case OP_ADDRGLDR:
7859 po_misc_or_fail_no_backtrack (
477330fc 7860 parse_address_group_reloc (&str, i, GROUP_LDR));
4962c51a
MS		 7861 break;
7862
7863 case OP_ADDRGLDRS:
7864 po_misc_or_fail_no_backtrack (
477330fc 7865 parse_address_group_reloc (&str, i, GROUP_LDRS));
4962c51a
MS		 7866 break;
7867
7868 case OP_ADDRGLDC:
7869 po_misc_or_fail_no_backtrack (
477330fc 7870 parse_address_group_reloc (&str, i, GROUP_LDC));
4962c51a
MS		 7871 break;
7872
c19d1205
ZW		 7873 case OP_SH:
7874 po_misc_or_fail (parse_shifter_operand (&str, i));
7875 break;
09d92015 7876
4962c51a
MS		 7877 case OP_SHG:
7878 po_misc_or_fail_no_backtrack (
477330fc 7879 parse_shifter_operand_group_reloc (&str, i));
4962c51a
MS		 7880 break;
7881
c19d1205
ZW		 7882 case OP_oSHll:
7883 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
7884 break;
09d92015 7885
c19d1205
ZW		 7886 case OP_oSHar:
7887 po_misc_or_fail (parse_shift (&str, i, SHIFT_ASR_IMMEDIATE));
7888 break;
09d92015 7889
c19d1205
ZW		 7890 case OP_oSHllar:
7891 po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_OR_ASR_IMMEDIATE));
7892 break;
09d92015 7893
1b883319
AV		 7894 case OP_RMQRZ:
7895 case OP_oRMQRZ:
7896 po_reg_or_goto (REG_TYPE_MQ, try_rr_zr);
7897 break;
e39c1607
SD		 7898
7899 case OP_RR_ZR:
1b883319
AV		 7900 try_rr_zr:
7901 po_reg_or_goto (REG_TYPE_RN, ZR);
7902 break;
7903 ZR:
7904 po_reg_or_fail (REG_TYPE_ZR);
7905 break;
7906
c19d1205 7907 default:
5be8be5d 7908 as_fatal (_("unhandled operand code %d"), op_parse_code);
c19d1205 7909 }
09d92015 7910
c19d1205
ZW		 7911 /* Various value-based sanity checks and shared operations. We
7912 do not signal immediate failures for the register constraints;
7913 this allows a syntax error to take precedence. */
5be8be5d 7914 switch (op_parse_code)
c19d1205
ZW		 7915 {
7916 case OP_oRRnpc:
7917 case OP_RRnpc:
7918 case OP_RRnpcb:
7919 case OP_RRw:
b6702015 7920 case OP_oRRw:
c19d1205
ZW		 7921 case OP_RRnpc_I0:
7922 if (inst.operands[i].isreg && inst.operands[i].reg == REG_PC)
7923 inst.error = BAD_PC;
7924 break;
09d92015 7925
5be8be5d
DG		 7926 case OP_oRRnpcsp:
7927 case OP_RRnpcsp:
23d00a41 7928 case OP_RRnpcsp_I32:
5be8be5d
DG		 7929 if (inst.operands[i].isreg)
7930 {
7931 if (inst.operands[i].reg == REG_PC)
7932 inst.error = BAD_PC;
5c8ed6a4
JW		 7933 else if (inst.operands[i].reg == REG_SP
7934 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7935 relaxed since ARMv8-A. */
7936 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
7937 {
7938 gas_assert (thumb);
7939 inst.error = BAD_SP;
7940 }
5be8be5d
DG		 7941 }
7942 break;
7943
55881a11 7944 case OP_RRnpctw:
fa94de6b
RM		 7945 if (inst.operands[i].isreg
7946 && inst.operands[i].reg == REG_PC
55881a11
MGD		 7947 && (inst.operands[i].writeback || thumb))
7948 inst.error = BAD_PC;
7949 break;
7950
1b883319 7951 case OP_RVSD_COND:
32c36c3c
AV		 7952 case OP_VLDR:
7953 if (inst.operands[i].isreg)
7954 break;
7955 /* fall through. */
1b883319 7956
c19d1205
ZW		 7957 case OP_CPSF:
7958 case OP_ENDI:
7959 case OP_oROR:
d2cd1205
JB		 7960 case OP_wPSR:
7961 case OP_rPSR:
c19d1205 7962 case OP_COND:
52e7f43d 7963 case OP_oBARRIER_I15:
c19d1205 7964 case OP_REGLST:
4b5a202f 7965 case OP_CLRMLST:
c19d1205
ZW		 7966 case OP_VRSLST:
7967 case OP_VRDLST:
477330fc 7968 case OP_VRSDLST:
efd6b359 7969 case OP_VRSDVLST:
477330fc
RM		 7970 case OP_NRDLST:
7971 case OP_NSTRLST:
35c228db
AV		 7972 case OP_MSTRLST2:
7973 case OP_MSTRLST4:
c19d1205
ZW		 7974 if (val == FAIL)
7975 goto failure;
7976 inst.operands[i].imm = val;
7977 break;
a737bd4d 7978
60f993ce
AV		 7979 case OP_LR:
7980 case OP_oLR:
7981 if (inst.operands[i].reg != REG_LR)
7982 inst.error = _("operand must be LR register");
7983 break;
7984
1b883319
AV		 7985 case OP_RMQRZ:
7986 case OP_oRMQRZ:
e39c1607 7987 case OP_RR_ZR:
1b883319
AV		 7988 if (!inst.operands[i].iszr && inst.operands[i].reg == REG_PC)
7989 inst.error = BAD_PC;
7990 break;
7991
a302e574
AV		 7992 case OP_RRe:
7993 if (inst.operands[i].isreg
7994 && (inst.operands[i].reg & 0x00000001) != 0)
7995 inst.error = BAD_ODD;
7996 break;
7997
7998 case OP_RRo:
7999 if (inst.operands[i].isreg)
8000 {
8001 if ((inst.operands[i].reg & 0x00000001) != 1)
8002 inst.error = BAD_EVEN;
8003 else if (inst.operands[i].reg == REG_SP)
8004 as_tsktsk (MVE_BAD_SP);
8005 else if (inst.operands[i].reg == REG_PC)
8006 inst.error = BAD_PC;
8007 }
8008 break;
8009
c19d1205
ZW		 8010 default:
8011 break;
8012 }
09d92015 8013
c19d1205
ZW		 8014 /* If we get here, this operand was successfully parsed. */
8015 inst.operands[i].present = 1;
8016 continue;
09d92015 8017
c19d1205 8018 bad_args:
09d92015 8019 inst.error = BAD_ARGS;
c19d1205
ZW		 8020
8021 failure:
8022 if (!backtrack_pos)
d252fdde
PB		 8023 {
8024 /* The parse routine should already have set inst.error, but set a
5f4273c7 8025 default here just in case. */
d252fdde 8026 if (!inst.error)
5ee91343 8027 inst.error = BAD_SYNTAX;
d252fdde
PB		 8028 return FAIL;
8029 }
c19d1205
ZW		 8030
8031 /* Do not backtrack over a trailing optional argument that
8032 absorbed some text. We will only fail again, with the
8033 'garbage following instruction' error message, which is
8034 probably less helpful than the current one. */
8035 if (backtrack_index == i && backtrack_pos != str
8036 && upat[i+1] == OP_stop)
d252fdde
PB		 8037 {
8038 if (!inst.error)
5ee91343 8039 inst.error = BAD_SYNTAX;
d252fdde
PB		 8040 return FAIL;
8041 }
c19d1205
ZW		 8042
8043 /* Try again, skipping the optional argument at backtrack_pos. */
8044 str = backtrack_pos;
8045 inst.error = backtrack_error;
8046 inst.operands[backtrack_index].present = 0;
8047 i = backtrack_index;
8048 backtrack_pos = 0;
09d92015 8049 }
09d92015 8050
c19d1205
ZW		 8051 /* Check that we have parsed all the arguments. */
8052 if (*str != '\0' && !inst.error)
8053 inst.error = _("garbage following instruction");
09d92015 8054
c19d1205 8055 return inst.error ? FAIL : SUCCESS;
09d92015
MM		 8056}
8057
c19d1205
ZW		 8058#undef po_char_or_fail
8059#undef po_reg_or_fail
8060#undef po_reg_or_goto
8061#undef po_imm_or_fail
5287ad62 8062#undef po_scalar_or_fail
52e7f43d 8063#undef po_barrier_or_imm
e07e6e58 8064
c19d1205 8065/* Shorthand macro for instruction encoding functions issuing errors. */
e07e6e58
NC		 8066#define constraint(expr, err) \
8067 do \
c19d1205 8068 { \
e07e6e58
NC		 8069 if (expr) \
8070 { \
8071 inst.error = err; \
8072 return; \
8073 } \
c19d1205 8074 } \
e07e6e58 8075 while (0)
c19d1205 8076
fdfde340
JM		 8077/* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8078 instructions are unpredictable if these registers are used. This
5c8ed6a4
JW		 8079 is the BadReg predicate in ARM's Thumb-2 documentation.
8080
8081 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8082 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8083#define reject_bad_reg(reg) \
8084 do \
8085 if (reg == REG_PC) \
8086 { \
8087 inst.error = BAD_PC; \
8088 return; \
8089 } \
8090 else if (reg == REG_SP \
8091 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8092 { \
8093 inst.error = BAD_SP; \
8094 return; \
8095 } \
fdfde340
JM		 8096 while (0)
8097
94206790
MM		 8098/* If REG is R13 (the stack pointer), warn that its use is
8099 deprecated. */
8100#define warn_deprecated_sp(reg) \
8101 do \
8102 if (warn_on_deprecated && reg == REG_SP) \
5c3696f8 8103 as_tsktsk (_("use of r13 is deprecated")); \
94206790
MM		 8104 while (0)
8105
c19d1205
ZW		 8106/* Functions for operand encoding. ARM, then Thumb. */
8107
d840c081 8108#define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
c19d1205 8109
9db2f6b4
RL		 8110/* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8111
8112 The only binary encoding difference is the Coprocessor number. Coprocessor
8113 9 is used for half-precision calculations or conversions. The format of the
2b0f3761 8114 instruction is the same as the equivalent Coprocessor 10 instruction that
9db2f6b4
RL		 8115 exists for Single-Precision operation. */
8116
8117static void
8118do_scalar_fp16_v82_encode (void)
8119{
5ee91343 8120 if (inst.cond < COND_ALWAYS)
9db2f6b4
RL		 8121 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8122 " the behaviour is UNPREDICTABLE"));
8123 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
8124 _(BAD_FP16));
8125
8126 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900;
8127 mark_feature_used (&arm_ext_fp16);
8128}
8129
c19d1205
ZW		 8130/* If VAL can be encoded in the immediate field of an ARM instruction,
8131 return the encoded form. Otherwise, return FAIL. */
8132
8133static unsigned int
8134encode_arm_immediate (unsigned int val)
09d92015 8135{
c19d1205
ZW		 8136 unsigned int a, i;
8137
4f1d6205
L		 8138 if (val <= 0xff)
8139 return val;
8140
8141 for (i = 2; i < 32; i += 2)
c19d1205
ZW		 8142 if ((a = rotate_left (val, i)) <= 0xff)
8143 return a | (i << 7); /* 12-bit pack: [shift-cnt,const]. */
8144
8145 return FAIL;
09d92015
MM		 8146}
8147
c19d1205
ZW		 8148/* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8149 return the encoded form. Otherwise, return FAIL. */
8150static unsigned int
8151encode_thumb32_immediate (unsigned int val)
09d92015 8152{
c19d1205 8153 unsigned int a, i;
09d92015 8154
9c3c69f2 8155 if (val <= 0xff)
c19d1205 8156 return val;
a737bd4d 8157
9c3c69f2 8158 for (i = 1; i <= 24; i++)
09d92015 8159 {
9c3c69f2
PB		 8160 a = val >> i;
8161 if ((val & ~(0xff << i)) == 0)
8162 return ((val >> i) & 0x7f) | ((32 - i) << 7);
09d92015 8163 }
a737bd4d 8164
c19d1205
ZW		 8165 a = val & 0xff;
8166 if (val == ((a << 16) | a))
8167 return 0x100 | a;
8168 if (val == ((a << 24) | (a << 16) | (a << 8) | a))
8169 return 0x300 | a;
09d92015 8170
c19d1205
ZW		 8171 a = val & 0xff00;
8172 if (val == ((a << 16) | a))
8173 return 0x200 | (a >> 8);
a737bd4d 8174
c19d1205 8175 return FAIL;
09d92015 8176}
5287ad62 8177/* Encode a VFP SP or DP register number into inst.instruction. */
09d92015
MM		 8178
8179static void
5287ad62
JB		 8180encode_arm_vfp_reg (int reg, enum vfp_reg_pos pos)
8181{
8182 if ((pos == VFP_REG_Dd || pos == VFP_REG_Dn || pos == VFP_REG_Dm)
8183 && reg > 15)
8184 {
b1cc4aeb 8185 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_d32))
477330fc
RM		 8186 {
8187 if (thumb_mode)
8188 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
8189 fpu_vfp_ext_d32);
8190 else
8191 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
8192 fpu_vfp_ext_d32);
8193 }
5287ad62 8194 else
477330fc
RM		 8195 {
8196 first_error (_("D register out of range for selected VFP version"));
8197 return;
8198 }
5287ad62
JB		 8199 }
8200
c19d1205 8201 switch (pos)
09d92015 8202 {
c19d1205
ZW		 8203 case VFP_REG_Sd:
8204 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22);
8205 break;
8206
8207 case VFP_REG_Sn:
8208 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7);
8209 break;
8210
8211 case VFP_REG_Sm:
8212 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5);
8213 break;
8214
5287ad62
JB		 8215 case VFP_REG_Dd:
8216 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22);
8217 break;
5f4273c7 8218
5287ad62
JB		 8219 case VFP_REG_Dn:
8220 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7);
8221 break;
5f4273c7 8222
5287ad62
JB		 8223 case VFP_REG_Dm:
8224 inst.instruction |= (reg & 15) | ((reg >> 4) << 5);
8225 break;
8226
c19d1205
ZW		 8227 default:
8228 abort ();
09d92015 8229 }
09d92015
MM		 8230}
8231
c19d1205 8232/* Encode a <shift> in an ARM-format instruction. The immediate,
55cf6793 8233 if any, is handled by md_apply_fix. */
09d92015 8234static void
c19d1205 8235encode_arm_shift (int i)
09d92015 8236{
008a97ef
RL		 8237 /* register-shifted register. */
8238 if (inst.operands[i].immisreg)
8239 {
bf355b69
MR		 8240 int op_index;
8241 for (op_index = 0; op_index <= i; ++op_index)
008a97ef 8242 {
5689c942
RL		 8243 /* Check the operand only when it's presented. In pre-UAL syntax,
8244 if the destination register is the same as the first operand, two
8245 register form of the instruction can be used. */
bf355b69
MR		 8246 if (inst.operands[op_index].present && inst.operands[op_index].isreg
8247 && inst.operands[op_index].reg == REG_PC)
008a97ef
RL		 8248 as_warn (UNPRED_REG ("r15"));
8249 }
8250
8251 if (inst.operands[i].imm == REG_PC)
8252 as_warn (UNPRED_REG ("r15"));
8253 }
8254
c19d1205
ZW		 8255 if (inst.operands[i].shift_kind == SHIFT_RRX)
8256 inst.instruction |= SHIFT_ROR << 5;
8257 else
09d92015 8258 {
c19d1205
ZW		 8259 inst.instruction |= inst.operands[i].shift_kind << 5;
8260 if (inst.operands[i].immisreg)
8261 {
8262 inst.instruction |= SHIFT_BY_REG;
8263 inst.instruction |= inst.operands[i].imm << 8;
8264 }
8265 else
e2b0ab59 8266 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
09d92015 8267 }
c19d1205 8268}
09d92015 8269
c19d1205
ZW		 8270static void
8271encode_arm_shifter_operand (int i)
8272{
8273 if (inst.operands[i].isreg)
09d92015 8274 {
c19d1205
ZW		 8275 inst.instruction |= inst.operands[i].reg;
8276 encode_arm_shift (i);
09d92015 8277 }
c19d1205 8278 else
a415b1cd
JB		 8279 {
8280 inst.instruction |= INST_IMMEDIATE;
e2b0ab59 8281 if (inst.relocs[0].type != BFD_RELOC_ARM_IMMEDIATE)
a415b1cd
JB		 8282 inst.instruction |= inst.operands[i].imm;
8283 }
09d92015
MM		 8284}
8285
c19d1205 8286/* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
09d92015 8287static void
c19d1205 8288encode_arm_addr_mode_common (int i, bfd_boolean is_t)
09d92015 8289{
2b2f5df9
NC		 8290 /* PR 14260:
8291 Generate an error if the operand is not a register. */
8292 constraint (!inst.operands[i].isreg,
8293 _("Instruction does not support =N addresses"));
8294
c19d1205 8295 inst.instruction |= inst.operands[i].reg << 16;
a737bd4d 8296
c19d1205 8297 if (inst.operands[i].preind)
09d92015 8298 {
c19d1205
ZW		 8299 if (is_t)
8300 {
8301 inst.error = _("instruction does not accept preindexed addressing");
8302 return;
8303 }
8304 inst.instruction |= PRE_INDEX;
8305 if (inst.operands[i].writeback)
8306 inst.instruction |= WRITE_BACK;
09d92015 8307
c19d1205
ZW		 8308 }
8309 else if (inst.operands[i].postind)
8310 {
9c2799c2 8311 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 8312 if (is_t)
8313 inst.instruction |= WRITE_BACK;
8314 }
8315 else /* unindexed - only for coprocessor */
09d92015 8316 {
c19d1205 8317 inst.error = _("instruction does not accept unindexed addressing");
09d92015
MM		 8318 return;
8319 }
8320
c19d1205
ZW		 8321 if (((inst.instruction & WRITE_BACK) || !(inst.instruction & PRE_INDEX))
8322 && (((inst.instruction & 0x000f0000) >> 16)
8323 == ((inst.instruction & 0x0000f000) >> 12)))
8324 as_warn ((inst.instruction & LOAD_BIT)
8325 ? _("destination register same as write-back base")
8326 : _("source register same as write-back base"));
09d92015
MM		 8327}
8328
c19d1205
ZW		 8329/* inst.operands[i] was set up by parse_address. Encode it into an
8330 ARM-format mode 2 load or store instruction. If is_t is true,
8331 reject forms that cannot be used with a T instruction (i.e. not
8332 post-indexed). */
a737bd4d 8333static void
c19d1205 8334encode_arm_addr_mode_2 (int i, bfd_boolean is_t)
09d92015 8335{
5be8be5d
DG		 8336 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
8337
c19d1205 8338 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8339
c19d1205 8340 if (inst.operands[i].immisreg)
09d92015 8341 {
5be8be5d
DG		 8342 constraint ((inst.operands[i].imm == REG_PC
8343 || (is_pc && inst.operands[i].writeback)),
8344 BAD_PC_ADDRESSING);
c19d1205
ZW		 8345 inst.instruction |= INST_IMMEDIATE; /* yes, this is backwards */
8346 inst.instruction |= inst.operands[i].imm;
8347 if (!inst.operands[i].negative)
8348 inst.instruction |= INDEX_UP;
8349 if (inst.operands[i].shifted)
8350 {
8351 if (inst.operands[i].shift_kind == SHIFT_RRX)
8352 inst.instruction |= SHIFT_ROR << 5;
8353 else
8354 {
8355 inst.instruction |= inst.operands[i].shift_kind << 5;
e2b0ab59 8356 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
c19d1205
ZW		 8357 }
8358 }
09d92015 8359 }
e2b0ab59 8360 else /* immediate offset in inst.relocs[0] */
09d92015 8361 {
e2b0ab59 8362 if (is_pc && !inst.relocs[0].pc_rel)
5be8be5d
DG		 8363 {
8364 const bfd_boolean is_load = ((inst.instruction & LOAD_BIT) != 0);
23a10334
JZ		 8365
8366 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8367 cannot use PC in addressing.
8368 PC cannot be used in writeback addressing, either. */
8369 constraint ((is_t || inst.operands[i].writeback),
5be8be5d 8370 BAD_PC_ADDRESSING);
23a10334 8371
dc5ec521 8372 /* Use of PC in str is deprecated for ARMv7. */
23a10334
JZ		 8373 if (warn_on_deprecated
8374 && !is_load
8375 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7))
5c3696f8 8376 as_tsktsk (_("use of PC in this instruction is deprecated"));
5be8be5d
DG		 8377 }
8378
e2b0ab59 8379 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS		 8380 {
8381 /* Prefer + for zero encoded value. */
8382 if (!inst.operands[i].negative)
8383 inst.instruction |= INDEX_UP;
e2b0ab59 8384 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM;
26d97720 8385 }
09d92015 8386 }
09d92015
MM		 8387}
8388
c19d1205
ZW		 8389/* inst.operands[i] was set up by parse_address. Encode it into an
8390 ARM-format mode 3 load or store instruction. Reject forms that
8391 cannot be used with such instructions. If is_t is true, reject
8392 forms that cannot be used with a T instruction (i.e. not
8393 post-indexed). */
8394static void
8395encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
09d92015 8396{
c19d1205 8397 if (inst.operands[i].immisreg && inst.operands[i].shifted)
09d92015 8398 {
c19d1205
ZW		 8399 inst.error = _("instruction does not accept scaled register index");
8400 return;
09d92015 8401 }
a737bd4d 8402
c19d1205 8403 encode_arm_addr_mode_common (i, is_t);
a737bd4d 8404
c19d1205
ZW		 8405 if (inst.operands[i].immisreg)
8406 {
5be8be5d 8407 constraint ((inst.operands[i].imm == REG_PC
eb9f3f00 8408 || (is_t && inst.operands[i].reg == REG_PC)),
5be8be5d 8409 BAD_PC_ADDRESSING);
eb9f3f00
JB		 8410 constraint (inst.operands[i].reg == REG_PC && inst.operands[i].writeback,
8411 BAD_PC_WRITEBACK);
c19d1205
ZW		 8412 inst.instruction |= inst.operands[i].imm;
8413 if (!inst.operands[i].negative)
8414 inst.instruction |= INDEX_UP;
8415 }
e2b0ab59 8416 else /* immediate offset in inst.relocs[0] */
c19d1205 8417 {
e2b0ab59 8418 constraint ((inst.operands[i].reg == REG_PC && !inst.relocs[0].pc_rel
5be8be5d
DG		 8419 && inst.operands[i].writeback),
8420 BAD_PC_WRITEBACK);
c19d1205 8421 inst.instruction |= HWOFFSET_IMM;
e2b0ab59 8422 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
26d97720
NS		 8423 {
8424 /* Prefer + for zero encoded value. */
8425 if (!inst.operands[i].negative)
8426 inst.instruction |= INDEX_UP;
8427
e2b0ab59 8428 inst.relocs[0].type = BFD_RELOC_ARM_OFFSET_IMM8;
26d97720 8429 }
c19d1205 8430 }
a737bd4d
NC		 8431}
8432
8335d6aa
JW		 8433/* Write immediate bits [7:0] to the following locations:
8434
8435 |28/24|23 19|18 16|15 4|3 0|
8436 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8437
8438 This function is used by VMOV/VMVN/VORR/VBIC. */
8439
8440static void
8441neon_write_immbits (unsigned immbits)
8442{
8443 inst.instruction |= immbits & 0xf;
8444 inst.instruction |= ((immbits >> 4) & 0x7) << 16;
8445 inst.instruction |= ((immbits >> 7) & 0x1) << (thumb_mode ? 28 : 24);
8446}
8447
8448/* Invert low-order SIZE bits of XHI:XLO. */
8449
8450static void
8451neon_invert_size (unsigned *xlo, unsigned *xhi, int size)
8452{
8453 unsigned immlo = xlo ? *xlo : 0;
8454 unsigned immhi = xhi ? *xhi : 0;
8455
8456 switch (size)
8457 {
8458 case 8:
8459 immlo = (~immlo) & 0xff;
8460 break;
8461
8462 case 16:
8463 immlo = (~immlo) & 0xffff;
8464 break;
8465
8466 case 64:
8467 immhi = (~immhi) & 0xffffffff;
8468 /* fall through. */
8469
8470 case 32:
8471 immlo = (~immlo) & 0xffffffff;
8472 break;
8473
8474 default:
8475 abort ();
8476 }
8477
8478 if (xlo)
8479 *xlo = immlo;
8480
8481 if (xhi)
8482 *xhi = immhi;
8483}
8484
8485/* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8486 A, B, C, D. */
09d92015 8487
c19d1205 8488static int
8335d6aa 8489neon_bits_same_in_bytes (unsigned imm)
09d92015 8490{
8335d6aa
JW		 8491 return ((imm & 0x000000ff) == 0 || (imm & 0x000000ff) == 0x000000ff)
8492 && ((imm & 0x0000ff00) == 0 || (imm & 0x0000ff00) == 0x0000ff00)
8493 && ((imm & 0x00ff0000) == 0 || (imm & 0x00ff0000) == 0x00ff0000)
8494 && ((imm & 0xff000000) == 0 || (imm & 0xff000000) == 0xff000000);
8495}
a737bd4d 8496
8335d6aa 8497/* For immediate of above form, return 0bABCD. */
09d92015 8498
8335d6aa
JW		 8499static unsigned
8500neon_squash_bits (unsigned imm)
8501{
8502 return (imm & 0x01) | ((imm & 0x0100) >> 7) | ((imm & 0x010000) >> 14)
8503 | ((imm & 0x01000000) >> 21);
8504}
8505
8506/* Compress quarter-float representation to 0b...000 abcdefgh. */
8507
8508static unsigned
8509neon_qfloat_bits (unsigned imm)
8510{
8511 return ((imm >> 19) & 0x7f) | ((imm >> 24) & 0x80);
8512}
8513
8514/* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8515 the instruction. *OP is passed as the initial value of the op field, and
8516 may be set to a different value depending on the constant (i.e.
8517 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8518 MVN). If the immediate looks like a repeated pattern then also
8519 try smaller element sizes. */
8520
8521static int
8522neon_cmode_for_move_imm (unsigned immlo, unsigned immhi, int float_p,
8523 unsigned *immbits, int *op, int size,
8524 enum neon_el_type type)
8525{
8526 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8527 float. */
8528 if (type == NT_float && !float_p)
8529 return FAIL;
8530
8531 if (type == NT_float && is_quarter_float (immlo) && immhi == 0)
09d92015 8532 {
8335d6aa
JW		 8533 if (size != 32 || *op == 1)
8534 return FAIL;
8535 *immbits = neon_qfloat_bits (immlo);
8536 return 0xf;
8537 }
8538
8539 if (size == 64)
8540 {
8541 if (neon_bits_same_in_bytes (immhi)
8542 && neon_bits_same_in_bytes (immlo))
c19d1205 8543 {
8335d6aa
JW		 8544 if (*op == 1)
8545 return FAIL;
8546 *immbits = (neon_squash_bits (immhi) << 4)
8547 | neon_squash_bits (immlo);
8548 *op = 1;
8549 return 0xe;
c19d1205 8550 }
a737bd4d 8551
8335d6aa
JW		 8552 if (immhi != immlo)
8553 return FAIL;
8554 }
a737bd4d 8555
8335d6aa 8556 if (size >= 32)
09d92015 8557 {
8335d6aa 8558 if (immlo == (immlo & 0x000000ff))
c19d1205 8559 {
8335d6aa
JW		 8560 *immbits = immlo;
8561 return 0x0;
c19d1205 8562 }
8335d6aa 8563 else if (immlo == (immlo & 0x0000ff00))
c19d1205 8564 {
8335d6aa
JW		 8565 *immbits = immlo >> 8;
8566 return 0x2;
c19d1205 8567 }
8335d6aa
JW		 8568 else if (immlo == (immlo & 0x00ff0000))
8569 {
8570 *immbits = immlo >> 16;
8571 return 0x4;
8572 }
8573 else if (immlo == (immlo & 0xff000000))
8574 {
8575 *immbits = immlo >> 24;
8576 return 0x6;
8577 }
8578 else if (immlo == ((immlo & 0x0000ff00) | 0x000000ff))
8579 {
8580 *immbits = (immlo >> 8) & 0xff;
8581 return 0xc;
8582 }
8583 else if (immlo == ((immlo & 0x00ff0000) | 0x0000ffff))
8584 {
8585 *immbits = (immlo >> 16) & 0xff;
8586 return 0xd;
8587 }
8588
8589 if ((immlo & 0xffff) != (immlo >> 16))
8590 return FAIL;
8591 immlo &= 0xffff;
09d92015 8592 }
a737bd4d 8593
8335d6aa 8594 if (size >= 16)
4962c51a 8595 {
8335d6aa
JW		 8596 if (immlo == (immlo & 0x000000ff))
8597 {
8598 *immbits = immlo;
8599 return 0x8;
8600 }
8601 else if (immlo == (immlo & 0x0000ff00))
8602 {
8603 *immbits = immlo >> 8;
8604 return 0xa;
8605 }
8606
8607 if ((immlo & 0xff) != (immlo >> 8))
8608 return FAIL;
8609 immlo &= 0xff;
4962c51a
MS		 8610 }
8611
8335d6aa
JW		 8612 if (immlo == (immlo & 0x000000ff))
8613 {
8614 /* Don't allow MVN with 8-bit immediate. */
8615 if (*op == 1)
8616 return FAIL;
8617 *immbits = immlo;
8618 return 0xe;
8619 }
26d97720 8620
8335d6aa 8621 return FAIL;
c19d1205 8622}
a737bd4d 8623
5fc177c8 8624#if defined BFD_HOST_64_BIT
ba592044
AM		 8625/* Returns TRUE if double precision value V may be cast
8626 to single precision without loss of accuracy. */
8627
8628static bfd_boolean
5fc177c8 8629is_double_a_single (bfd_int64_t v)
ba592044 8630{
5fc177c8 8631 int exp = (int)((v >> 52) & 0x7FF);
8fe3f3d6 8632 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM		 8633
8634 return (exp == 0 || exp == 0x7FF
8635 || (exp >= 1023 - 126 && exp <= 1023 + 127))
8636 && (mantissa & 0x1FFFFFFFl) == 0;
8637}
8638
3739860c 8639/* Returns a double precision value casted to single precision
ba592044
AM		 8640 (ignoring the least significant bits in exponent and mantissa). */
8641
8642static int
5fc177c8 8643double_to_single (bfd_int64_t v)
ba592044
AM		 8644{
8645 int sign = (int) ((v >> 63) & 1l);
5fc177c8 8646 int exp = (int) ((v >> 52) & 0x7FF);
8fe3f3d6 8647 bfd_int64_t mantissa = (v & (bfd_int64_t)0xFFFFFFFFFFFFFULL);
ba592044
AM		 8648
8649 if (exp == 0x7FF)
8650 exp = 0xFF;
8651 else
8652 {
8653 exp = exp - 1023 + 127;
8654 if (exp >= 0xFF)
8655 {
8656 /* Infinity. */
8657 exp = 0x7F;
8658 mantissa = 0;
8659 }
8660 else if (exp < 0)
8661 {
8662 /* No denormalized numbers. */
8663 exp = 0;
8664 mantissa = 0;
8665 }
8666 }
8667 mantissa >>= 29;
8668 return (sign << 31) | (exp << 23) | mantissa;
8669}
5fc177c8 8670#endif /* BFD_HOST_64_BIT */
ba592044 8671
8335d6aa
JW		 8672enum lit_type
8673{
8674 CONST_THUMB,
8675 CONST_ARM,
8676 CONST_VEC
8677};
8678
ba592044
AM		 8679static void do_vfp_nsyn_opcode (const char *);
8680
e2b0ab59 8681/* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
c19d1205
ZW		 8682 Determine whether it can be performed with a move instruction; if
8683 it can, convert inst.instruction to that move instruction and
c921be7d
NC		 8684 return TRUE; if it can't, convert inst.instruction to a literal-pool
8685 load and return FALSE. If this is not a valid thing to do in the
8686 current context, set inst.error and return TRUE.
a737bd4d 8687
c19d1205
ZW		 8688 inst.operands[i] describes the destination register. */
8689
c921be7d 8690static bfd_boolean
8335d6aa 8691move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3)
c19d1205 8692{
53365c0d 8693 unsigned long tbit;
8335d6aa
JW		 8694 bfd_boolean thumb_p = (t == CONST_THUMB);
8695 bfd_boolean arm_p = (t == CONST_ARM);
53365c0d
PB		 8696
8697 if (thumb_p)
8698 tbit = (inst.instruction > 0xffff) ? THUMB2_LOAD_BIT : THUMB_LOAD_BIT;
8699 else
8700 tbit = LOAD_BIT;
8701
8702 if ((inst.instruction & tbit) == 0)
09d92015 8703 {
c19d1205 8704 inst.error = _("invalid pseudo operation");
c921be7d 8705 return TRUE;
09d92015 8706 }
ba592044 8707
e2b0ab59
AV		 8708 if (inst.relocs[0].exp.X_op != O_constant
8709 && inst.relocs[0].exp.X_op != O_symbol
8710 && inst.relocs[0].exp.X_op != O_big)
09d92015
MM		 8711 {
8712 inst.error = _("constant expression expected");
c921be7d 8713 return TRUE;
09d92015 8714 }
ba592044 8715
e2b0ab59
AV		 8716 if (inst.relocs[0].exp.X_op == O_constant
8717 || inst.relocs[0].exp.X_op == O_big)
8335d6aa 8718 {
5fc177c8
NC		 8719#if defined BFD_HOST_64_BIT
8720 bfd_int64_t v;
8721#else
ba592044 8722 offsetT v;
5fc177c8 8723#endif
e2b0ab59 8724 if (inst.relocs[0].exp.X_op == O_big)
8335d6aa 8725 {
ba592044
AM		 8726 LITTLENUM_TYPE w[X_PRECISION];
8727 LITTLENUM_TYPE * l;
8728
e2b0ab59 8729 if (inst.relocs[0].exp.X_add_number == -1)
8335d6aa 8730 {
ba592044
AM		 8731 gen_to_words (w, X_PRECISION, E_PRECISION);
8732 l = w;
8733 /* FIXME: Should we check words w[2..5] ? */
8335d6aa 8734 }
ba592044
AM		 8735 else
8736 l = generic_bignum;
3739860c 8737
5fc177c8
NC		 8738#if defined BFD_HOST_64_BIT
8739 v =
8740 ((((((((bfd_int64_t) l[3] & LITTLENUM_MASK)
8741 << LITTLENUM_NUMBER_OF_BITS)
8742 | ((bfd_int64_t) l[2] & LITTLENUM_MASK))
8743 << LITTLENUM_NUMBER_OF_BITS)
8744 | ((bfd_int64_t) l[1] & LITTLENUM_MASK))
8745 << LITTLENUM_NUMBER_OF_BITS)
8746 | ((bfd_int64_t) l[0] & LITTLENUM_MASK));
8747#else
ba592044
AM		 8748 v = ((l[1] & LITTLENUM_MASK) << LITTLENUM_NUMBER_OF_BITS)
8749 | (l[0] & LITTLENUM_MASK);
5fc177c8 8750#endif
8335d6aa 8751 }
ba592044 8752 else
e2b0ab59 8753 v = inst.relocs[0].exp.X_add_number;
ba592044
AM		 8754
8755 if (!inst.operands[i].issingle)
8335d6aa 8756 {
12569877 8757 if (thumb_p)
8335d6aa 8758 {
53445554
TP		 8759 /* LDR should not use lead in a flag-setting instruction being
8760 chosen so we do not check whether movs can be used. */
12569877 8761
53445554 8762 if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
ff8646ee 8763 || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
53445554
TP		 8764 && inst.operands[i].reg != 13
8765 && inst.operands[i].reg != 15)
12569877 8766 {
fc289b0a
TP		 8767 /* Check if on thumb2 it can be done with a mov.w, mvn or
8768 movw instruction. */
12569877
AM		 8769 unsigned int newimm;
8770 bfd_boolean isNegated;
8771
8772 newimm = encode_thumb32_immediate (v);
8773 if (newimm != (unsigned int) FAIL)
8774 isNegated = FALSE;
8775 else
8776 {
582cfe03 8777 newimm = encode_thumb32_immediate (~v);
12569877
AM		 8778 if (newimm != (unsigned int) FAIL)
8779 isNegated = TRUE;
8780 }
8781
fc289b0a
TP		 8782 /* The number can be loaded with a mov.w or mvn
8783 instruction. */
ff8646ee
TP		 8784 if (newimm != (unsigned int) FAIL
8785 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
12569877 8786 {
fc289b0a 8787 inst.instruction = (0xf04f0000 /* MOV.W. */
582cfe03 8788 | (inst.operands[i].reg << 8));
fc289b0a 8789 /* Change to MOVN. */
582cfe03 8790 inst.instruction |= (isNegated ? 0x200000 : 0);
12569877
AM		 8791 inst.instruction |= (newimm & 0x800) << 15;
8792 inst.instruction |= (newimm & 0x700) << 4;
8793 inst.instruction |= (newimm & 0x0ff);
8794 return TRUE;
8795 }
fc289b0a 8796 /* The number can be loaded with a movw instruction. */
ff8646ee
TP		 8797 else if ((v & ~0xFFFF) == 0
8798 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
3739860c 8799 {
582cfe03 8800 int imm = v & 0xFFFF;
12569877 8801
582cfe03 8802 inst.instruction = 0xf2400000; /* MOVW. */
12569877
AM		 8803 inst.instruction |= (inst.operands[i].reg << 8);
8804 inst.instruction |= (imm & 0xf000) << 4;
8805 inst.instruction |= (imm & 0x0800) << 15;
8806 inst.instruction |= (imm & 0x0700) << 4;
8807 inst.instruction |= (imm & 0x00ff);
8fe9a076
AV		 8808 /* In case this replacement is being done on Armv8-M
8809 Baseline we need to make sure to disable the
8810 instruction size check, as otherwise GAS will reject
8811 the use of this T32 instruction. */
8812 inst.size_req = 0;
12569877
AM		 8813 return TRUE;
8814 }
8815 }
8335d6aa 8816 }
12569877 8817 else if (arm_p)
ba592044
AM		 8818 {
8819 int value = encode_arm_immediate (v);
12569877 8820
ba592044
AM		 8821 if (value != FAIL)
8822 {
8823 /* This can be done with a mov instruction. */
8824 inst.instruction &= LITERAL_MASK;
8825 inst.instruction |= INST_IMMEDIATE | (OPCODE_MOV << DATA_OP_SHIFT);
8826 inst.instruction |= value & 0xfff;
8827 return TRUE;
8828 }
8335d6aa 8829
ba592044
AM		 8830 value = encode_arm_immediate (~ v);
8831 if (value != FAIL)
8832 {
8833 /* This can be done with a mvn instruction. */
8834 inst.instruction &= LITERAL_MASK;
8835 inst.instruction |= INST_IMMEDIATE | (OPCODE_MVN << DATA_OP_SHIFT);
8836 inst.instruction |= value & 0xfff;
8837 return TRUE;
8838 }
8839 }
934c2632 8840 else if (t == CONST_VEC && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
8335d6aa 8841 {
ba592044
AM		 8842 int op = 0;
8843 unsigned immbits = 0;
8844 unsigned immlo = inst.operands[1].imm;
8845 unsigned immhi = inst.operands[1].regisimm
8846 ? inst.operands[1].reg
e2b0ab59 8847 : inst.relocs[0].exp.X_unsigned
ba592044
AM		 8848 ? 0
8849 : ((bfd_int64_t)((int) immlo)) >> 32;
8850 int cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8851 &op, 64, NT_invtype);
8852
8853 if (cmode == FAIL)
8854 {
8855 neon_invert_size (&immlo, &immhi, 64);
8856 op = !op;
8857 cmode = neon_cmode_for_move_imm (immlo, immhi, FALSE, &immbits,
8858 &op, 64, NT_invtype);
8859 }
8860
8861 if (cmode != FAIL)
8862 {
8863 inst.instruction = (inst.instruction & VLDR_VMOV_SAME)
8864 | (1 << 23)
8865 | (cmode << 8)
8866 | (op << 5)
8867 | (1 << 4);
8868
8869 /* Fill other bits in vmov encoding for both thumb and arm. */
8870 if (thumb_mode)
eff0bc54 8871 inst.instruction |= (0x7U << 29) | (0xF << 24);
ba592044 8872 else
eff0bc54 8873 inst.instruction |= (0xFU << 28) | (0x1 << 25);
ba592044
AM		 8874 neon_write_immbits (immbits);
8875 return TRUE;
8876 }
8335d6aa
JW		 8877 }
8878 }
8335d6aa 8879
ba592044
AM		 8880 if (t == CONST_VEC)
8881 {
8882 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8883 if (inst.operands[i].issingle
8884 && is_quarter_float (inst.operands[1].imm)
8885 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3xd))
8335d6aa 8886 {
ba592044
AM		 8887 inst.operands[1].imm =
8888 neon_qfloat_bits (v);
8889 do_vfp_nsyn_opcode ("fconsts");
8890 return TRUE;
8335d6aa 8891 }
5fc177c8
NC		 8892
8893 /* If our host does not support a 64-bit type then we cannot perform
8894 the following optimization. This mean that there will be a
8895 discrepancy between the output produced by an assembler built for
8896 a 32-bit-only host and the output produced from a 64-bit host, but
8897 this cannot be helped. */
8898#if defined BFD_HOST_64_BIT
ba592044
AM		 8899 else if (!inst.operands[1].issingle
8900 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v3))
8335d6aa 8901 {
ba592044
AM		 8902 if (is_double_a_single (v)
8903 && is_quarter_float (double_to_single (v)))
8904 {
8905 inst.operands[1].imm =
8906 neon_qfloat_bits (double_to_single (v));
8907 do_vfp_nsyn_opcode ("fconstd");
8908 return TRUE;
8909 }
8335d6aa 8910 }
5fc177c8 8911#endif
8335d6aa
JW		 8912 }
8913 }
8914
8915 if (add_to_lit_pool ((!inst.operands[i].isvec
8916 || inst.operands[i].issingle) ? 4 : 8) == FAIL)
8917 return TRUE;
8918
8919 inst.operands[1].reg = REG_PC;
8920 inst.operands[1].isreg = 1;
8921 inst.operands[1].preind = 1;
e2b0ab59
AV		 8922 inst.relocs[0].pc_rel = 1;
8923 inst.relocs[0].type = (thumb_p
8335d6aa
JW		 8924 ? BFD_RELOC_ARM_THUMB_OFFSET
8925 : (mode_3
8926 ? BFD_RELOC_ARM_HWLITERAL
8927 : BFD_RELOC_ARM_LITERAL));
8928 return FALSE;
8929}
8930
8931/* inst.operands[i] was set up by parse_address. Encode it into an
8932 ARM-format instruction. Reject all forms which cannot be encoded
8933 into a coprocessor load/store instruction. If wb_ok is false,
8934 reject use of writeback; if unind_ok is false, reject use of
8935 unindexed addressing. If reloc_override is not 0, use it instead
8936 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8937 (in which case it is preserved). */
8938
8939static int
8940encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
8941{
8942 if (!inst.operands[i].isreg)
8943 {
99b2a2dd
NC		 8944 /* PR 18256 */
8945 if (! inst.operands[0].isvec)
8946 {
8947 inst.error = _("invalid co-processor operand");
8948 return FAIL;
8949 }
8335d6aa
JW		 8950 if (move_or_literal_pool (0, CONST_VEC, /*mode_3=*/FALSE))
8951 return SUCCESS;
8952 }
8953
8954 inst.instruction |= inst.operands[i].reg << 16;
8955
8956 gas_assert (!(inst.operands[i].preind && inst.operands[i].postind));
8957
8958 if (!inst.operands[i].preind && !inst.operands[i].postind) /* unindexed */
8959 {
8960 gas_assert (!inst.operands[i].writeback);
8961 if (!unind_ok)
8962 {
8963 inst.error = _("instruction does not support unindexed addressing");
8964 return FAIL;
8965 }
8966 inst.instruction |= inst.operands[i].imm;
8967 inst.instruction |= INDEX_UP;
8968 return SUCCESS;
8969 }
8970
8971 if (inst.operands[i].preind)
8972 inst.instruction |= PRE_INDEX;
8973
8974 if (inst.operands[i].writeback)
09d92015 8975 {
8335d6aa 8976 if (inst.operands[i].reg == REG_PC)
c19d1205 8977 {
8335d6aa
JW		 8978 inst.error = _("pc may not be used with write-back");
8979 return FAIL;
c19d1205 8980 }
8335d6aa 8981 if (!wb_ok)
c19d1205 8982 {
8335d6aa
JW		 8983 inst.error = _("instruction does not support writeback");
8984 return FAIL;
c19d1205 8985 }
8335d6aa 8986 inst.instruction |= WRITE_BACK;
09d92015
MM		 8987 }
8988
8335d6aa 8989 if (reloc_override)
e2b0ab59
AV		 8990 inst.relocs[0].type = (bfd_reloc_code_real_type) reloc_override;
8991 else if ((inst.relocs[0].type < BFD_RELOC_ARM_ALU_PC_G0_NC
8992 || inst.relocs[0].type > BFD_RELOC_ARM_LDC_SB_G2)
8993 && inst.relocs[0].type != BFD_RELOC_ARM_LDR_PC_G0)
c19d1205 8994 {
8335d6aa 8995 if (thumb_mode)
e2b0ab59 8996 inst.relocs[0].type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
8335d6aa 8997 else
e2b0ab59 8998 inst.relocs[0].type = BFD_RELOC_ARM_CP_OFF_IMM;
c19d1205 8999 }
8335d6aa
JW		 9000
9001 /* Prefer + for zero encoded value. */
9002 if (!inst.operands[i].negative)
9003 inst.instruction |= INDEX_UP;
9004
9005 return SUCCESS;
09d92015
MM		 9006}
9007
5f4273c7 9008/* Functions for instruction encoding, sorted by sub-architecture.
c19d1205
ZW		 9009 First some generics; their names are taken from the conventional
9010 bit positions for register arguments in ARM format instructions. */
09d92015 9011
a737bd4d 9012static void
c19d1205 9013do_noargs (void)
09d92015 9014{
c19d1205 9015}
a737bd4d 9016
c19d1205
ZW		 9017static void
9018do_rd (void)
9019{
9020 inst.instruction |= inst.operands[0].reg << 12;
9021}
a737bd4d 9022
16a1fa25
TP		 9023static void
9024do_rn (void)
9025{
9026 inst.instruction |= inst.operands[0].reg << 16;
9027}
9028
c19d1205
ZW		 9029static void
9030do_rd_rm (void)
9031{
9032 inst.instruction |= inst.operands[0].reg << 12;
9033 inst.instruction |= inst.operands[1].reg;
9034}
09d92015 9035
9eb6c0f1
MGD		 9036static void
9037do_rm_rn (void)
9038{
9039 inst.instruction |= inst.operands[0].reg;
9040 inst.instruction |= inst.operands[1].reg << 16;
9041}
9042
c19d1205
ZW		 9043static void
9044do_rd_rn (void)
9045{
9046 inst.instruction |= inst.operands[0].reg << 12;
9047 inst.instruction |= inst.operands[1].reg << 16;
9048}
a737bd4d 9049
c19d1205
ZW		 9050static void
9051do_rn_rd (void)
9052{
9053 inst.instruction |= inst.operands[0].reg << 16;
9054 inst.instruction |= inst.operands[1].reg << 12;
9055}
09d92015 9056
4ed7ed8d
TP		 9057static void
9058do_tt (void)
9059{
9060 inst.instruction |= inst.operands[0].reg << 8;
9061 inst.instruction |= inst.operands[1].reg << 16;
9062}
9063
59d09be6
MGD		 9064static bfd_boolean
9065check_obsolete (const arm_feature_set *feature, const char *msg)
9066{
9067 if (ARM_CPU_IS_ANY (cpu_variant))
9068 {
5c3696f8 9069 as_tsktsk ("%s", msg);
59d09be6
MGD		 9070 return TRUE;
9071 }
9072 else if (ARM_CPU_HAS_FEATURE (cpu_variant, *feature))
9073 {
9074 as_bad ("%s", msg);
9075 return TRUE;
9076 }
9077
9078 return FALSE;
9079}
9080
c19d1205
ZW		 9081static void
9082do_rd_rm_rn (void)
9083{
9a64e435 9084 unsigned Rn = inst.operands[2].reg;
708587a4 9085 /* Enforce restrictions on SWP instruction. */
9a64e435 9086 if ((inst.instruction & 0x0fbfffff) == 0x01000090)
56adecf4
DG		 9087 {
9088 constraint (Rn == inst.operands[0].reg || Rn == inst.operands[1].reg,
9089 _("Rn must not overlap other operands"));
9090
59d09be6
MGD		 9091 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9092 */
9093 if (!check_obsolete (&arm_ext_v8,
9094 _("swp{b} use is obsoleted for ARMv8 and later"))
9095 && warn_on_deprecated
9096 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6))
5c3696f8 9097 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
56adecf4 9098 }
59d09be6 9099
c19d1205
ZW		 9100 inst.instruction |= inst.operands[0].reg << 12;
9101 inst.instruction |= inst.operands[1].reg;
9a64e435 9102 inst.instruction |= Rn << 16;
c19d1205 9103}
09d92015 9104
c19d1205
ZW		 9105static void
9106do_rd_rn_rm (void)
9107{
9108 inst.instruction |= inst.operands[0].reg << 12;
9109 inst.instruction |= inst.operands[1].reg << 16;
9110 inst.instruction |= inst.operands[2].reg;
9111}
a737bd4d 9112
c19d1205
ZW		 9113static void
9114do_rm_rd_rn (void)
9115{
5be8be5d 9116 constraint ((inst.operands[2].reg == REG_PC), BAD_PC);
e2b0ab59
AV		 9117 constraint (((inst.relocs[0].exp.X_op != O_constant
9118 && inst.relocs[0].exp.X_op != O_illegal)
9119 || inst.relocs[0].exp.X_add_number != 0),
5be8be5d 9120 BAD_ADDR_MODE);
c19d1205
ZW		 9121 inst.instruction |= inst.operands[0].reg;
9122 inst.instruction |= inst.operands[1].reg << 12;
9123 inst.instruction |= inst.operands[2].reg << 16;
9124}
09d92015 9125
c19d1205
ZW		 9126static void
9127do_imm0 (void)
9128{
9129 inst.instruction |= inst.operands[0].imm;
9130}
09d92015 9131
c19d1205
ZW		 9132static void
9133do_rd_cpaddr (void)
9134{
9135 inst.instruction |= inst.operands[0].reg << 12;
9136 encode_arm_cp_address (1, TRUE, TRUE, 0);
09d92015 9137}
a737bd4d 9138
c19d1205
ZW		 9139/* ARM instructions, in alphabetical order by function name (except
9140 that wrapper functions appear immediately after the function they
9141 wrap). */
09d92015 9142
c19d1205
ZW		 9143/* This is a pseudo-op of the form "adr rd, label" to be converted
9144 into a relative address of the form "add rd, pc, #label-.-8". */
09d92015
MM		 9145
9146static void
c19d1205 9147do_adr (void)
09d92015 9148{
c19d1205 9149 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9150
c19d1205
ZW		 9151 /* Frag hacking will turn this into a sub instruction if the offset turns
9152 out to be negative. */
e2b0ab59
AV		 9153 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
9154 inst.relocs[0].pc_rel = 1;
9155 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9156
fc6141f0 9157 if (support_interwork
e2b0ab59
AV		 9158 && inst.relocs[0].exp.X_op == O_symbol
9159 && inst.relocs[0].exp.X_add_symbol != NULL
9160 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9161 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9162 inst.relocs[0].exp.X_add_number |= 1;
c19d1205 9163}
b99bd4ef 9164
c19d1205
ZW		 9165/* This is a pseudo-op of the form "adrl rd, label" to be converted
9166 into a relative address of the form:
9167 add rd, pc, #low(label-.-8)"
9168 add rd, rd, #high(label-.-8)" */
b99bd4ef 9169
c19d1205
ZW		 9170static void
9171do_adrl (void)
9172{
9173 inst.instruction |= (inst.operands[0].reg << 12); /* Rd */
a737bd4d 9174
c19d1205
ZW		 9175 /* Frag hacking will turn this into a sub instruction if the offset turns
9176 out to be negative. */
e2b0ab59
AV		 9177 inst.relocs[0].type = BFD_RELOC_ARM_ADRL_IMMEDIATE;
9178 inst.relocs[0].pc_rel = 1;
c19d1205 9179 inst.size = INSN_SIZE * 2;
e2b0ab59 9180 inst.relocs[0].exp.X_add_number -= 8;
52a86f84 9181
fc6141f0 9182 if (support_interwork
e2b0ab59
AV		 9183 && inst.relocs[0].exp.X_op == O_symbol
9184 && inst.relocs[0].exp.X_add_symbol != NULL
9185 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
9186 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
9187 inst.relocs[0].exp.X_add_number |= 1;
b99bd4ef
NC		 9188}
9189
b99bd4ef 9190static void
c19d1205 9191do_arit (void)
b99bd4ef 9192{
e2b0ab59
AV		 9193 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9194 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9195 THUMB1_RELOC_ONLY);
c19d1205
ZW		 9196 if (!inst.operands[1].present)
9197 inst.operands[1].reg = inst.operands[0].reg;
9198 inst.instruction |= inst.operands[0].reg << 12;
9199 inst.instruction |= inst.operands[1].reg << 16;
9200 encode_arm_shifter_operand (2);
9201}
b99bd4ef 9202
62b3e311
PB		 9203static void
9204do_barrier (void)
9205{
9206 if (inst.operands[0].present)
ccb84d65 9207 inst.instruction |= inst.operands[0].imm;
62b3e311
PB		 9208 else
9209 inst.instruction |= 0xf;
9210}
9211
c19d1205
ZW		 9212static void
9213do_bfc (void)
9214{
9215 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
9216 constraint (msb > 32, _("bit-field extends past end of register"));
9217 /* The instruction encoding stores the LSB and MSB,
9218 not the LSB and width. */
9219 inst.instruction |= inst.operands[0].reg << 12;
9220 inst.instruction |= inst.operands[1].imm << 7;
9221 inst.instruction |= (msb - 1) << 16;
9222}
b99bd4ef 9223
c19d1205
ZW		 9224static void
9225do_bfi (void)
9226{
9227 unsigned int msb;
b99bd4ef 9228
c19d1205
ZW		 9229 /* #0 in second position is alternative syntax for bfc, which is
9230 the same instruction but with REG_PC in the Rm field. */
9231 if (!inst.operands[1].isreg)
9232 inst.operands[1].reg = REG_PC;
b99bd4ef 9233
c19d1205
ZW		 9234 msb = inst.operands[2].imm + inst.operands[3].imm;
9235 constraint (msb > 32, _("bit-field extends past end of register"));
9236 /* The instruction encoding stores the LSB and MSB,
9237 not the LSB and width. */
9238 inst.instruction |= inst.operands[0].reg << 12;
9239 inst.instruction |= inst.operands[1].reg;
9240 inst.instruction |= inst.operands[2].imm << 7;
9241 inst.instruction |= (msb - 1) << 16;
b99bd4ef
NC		 9242}
9243
b99bd4ef 9244static void
c19d1205 9245do_bfx (void)
b99bd4ef 9246{
c19d1205
ZW		 9247 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
9248 _("bit-field extends past end of register"));
9249 inst.instruction |= inst.operands[0].reg << 12;
9250 inst.instruction |= inst.operands[1].reg;
9251 inst.instruction |= inst.operands[2].imm << 7;
9252 inst.instruction |= (inst.operands[3].imm - 1) << 16;
9253}
09d92015 9254
c19d1205
ZW		 9255/* ARM V5 breakpoint instruction (argument parse)
9256 BKPT <16 bit unsigned immediate>
9257 Instruction is not conditional.
9258 The bit pattern given in insns[] has the COND_ALWAYS condition,
9259 and it is an error if the caller tried to override that. */
b99bd4ef 9260
c19d1205
ZW		 9261static void
9262do_bkpt (void)
9263{
9264 /* Top 12 of 16 bits to bits 19:8. */
9265 inst.instruction |= (inst.operands[0].imm & 0xfff0) << 4;
09d92015 9266
c19d1205
ZW		 9267 /* Bottom 4 of 16 bits to bits 3:0. */
9268 inst.instruction |= inst.operands[0].imm & 0xf;
9269}
09d92015 9270
c19d1205
ZW		 9271static void
9272encode_branch (int default_reloc)
9273{
9274 if (inst.operands[0].hasreloc)
9275 {
0855e32b
NS		 9276 constraint (inst.operands[0].imm != BFD_RELOC_ARM_PLT32
9277 && inst.operands[0].imm != BFD_RELOC_ARM_TLS_CALL,
9278 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
e2b0ab59 9279 inst.relocs[0].type = inst.operands[0].imm == BFD_RELOC_ARM_PLT32
0855e32b
NS		 9280 ? BFD_RELOC_ARM_PLT32
9281 : thumb_mode ? BFD_RELOC_ARM_THM_TLS_CALL : BFD_RELOC_ARM_TLS_CALL;
c19d1205 9282 }
b99bd4ef 9283 else
e2b0ab59
AV		 9284 inst.relocs[0].type = (bfd_reloc_code_real_type) default_reloc;
9285 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC		 9286}
9287
b99bd4ef 9288static void
c19d1205 9289do_branch (void)
b99bd4ef 9290{
39b41c9c
PB		 9291#ifdef OBJ_ELF
9292 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9293 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9294 else
9295#endif
9296 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
9297}
9298
9299static void
9300do_bl (void)
9301{
9302#ifdef OBJ_ELF
9303 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
9304 {
9305 if (inst.cond == COND_ALWAYS)
9306 encode_branch (BFD_RELOC_ARM_PCREL_CALL);
9307 else
9308 encode_branch (BFD_RELOC_ARM_PCREL_JUMP);
9309 }
9310 else
9311#endif
9312 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH);
c19d1205 9313}
b99bd4ef 9314
c19d1205
ZW		 9315/* ARM V5 branch-link-exchange instruction (argument parse)
9316 BLX <target_addr> ie BLX(1)
9317 BLX{<condition>} <Rm> ie BLX(2)
9318 Unfortunately, there are two different opcodes for this mnemonic.
9319 So, the insns[].value is not used, and the code here zaps values
9320 into inst.instruction.
9321 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
b99bd4ef 9322
c19d1205
ZW		 9323static void
9324do_blx (void)
9325{
9326 if (inst.operands[0].isreg)
b99bd4ef 9327 {
c19d1205
ZW		 9328 /* Arg is a register; the opcode provided by insns[] is correct.
9329 It is not illegal to do "blx pc", just useless. */
9330 if (inst.operands[0].reg == REG_PC)
9331 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
b99bd4ef 9332
c19d1205
ZW		 9333 inst.instruction |= inst.operands[0].reg;
9334 }
9335 else
b99bd4ef 9336 {
c19d1205 9337 /* Arg is an address; this instruction cannot be executed
267bf995
RR		 9338 conditionally, and the opcode must be adjusted.
9339 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9340 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
c19d1205 9341 constraint (inst.cond != COND_ALWAYS, BAD_COND);
2fc8bdac 9342 inst.instruction = 0xfa000000;
267bf995 9343 encode_branch (BFD_RELOC_ARM_PCREL_BLX);
b99bd4ef 9344 }
c19d1205
ZW		 9345}
9346
9347static void
9348do_bx (void)
9349{
845b51d6
PB		 9350 bfd_boolean want_reloc;
9351
c19d1205
ZW		 9352 if (inst.operands[0].reg == REG_PC)
9353 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
b99bd4ef 9354
c19d1205 9355 inst.instruction |= inst.operands[0].reg;
845b51d6
PB		 9356 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9357 it is for ARMv4t or earlier. */
9358 want_reloc = !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5);
4d354d8b
TP		 9359 if (!ARM_FEATURE_ZERO (selected_object_arch)
9360 && !ARM_CPU_HAS_FEATURE (selected_object_arch, arm_ext_v5))
845b51d6
PB		 9361 want_reloc = TRUE;
9362
5ad34203 9363#ifdef OBJ_ELF
845b51d6 9364 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
5ad34203 9365#endif
584206db 9366 want_reloc = FALSE;
845b51d6
PB		 9367
9368 if (want_reloc)
e2b0ab59 9369 inst.relocs[0].type = BFD_RELOC_ARM_V4BX;
09d92015
MM		 9370}
9371
c19d1205
ZW		 9372
9373/* ARM v5TEJ. Jump to Jazelle code. */
a737bd4d
NC		 9374
9375static void
c19d1205 9376do_bxj (void)
a737bd4d 9377{
c19d1205
ZW		 9378 if (inst.operands[0].reg == REG_PC)
9379 as_tsktsk (_("use of r15 in bxj is not really useful"));
9380
9381 inst.instruction |= inst.operands[0].reg;
a737bd4d
NC		 9382}
9383
c19d1205
ZW		 9384/* Co-processor data operation:
9385 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9386 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9387static void
9388do_cdp (void)
9389{
9390 inst.instruction |= inst.operands[0].reg << 8;
9391 inst.instruction |= inst.operands[1].imm << 20;
9392 inst.instruction |= inst.operands[2].reg << 12;
9393 inst.instruction |= inst.operands[3].reg << 16;
9394 inst.instruction |= inst.operands[4].reg;
9395 inst.instruction |= inst.operands[5].imm << 5;
9396}
a737bd4d
NC		 9397
9398static void
c19d1205 9399do_cmp (void)
a737bd4d 9400{
c19d1205
ZW		 9401 inst.instruction |= inst.operands[0].reg << 16;
9402 encode_arm_shifter_operand (1);
a737bd4d
NC		 9403}
9404
c19d1205
ZW		 9405/* Transfer between coprocessor and ARM registers.
9406 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9407 MRC2
9408 MCR{cond}
9409 MCR2
9410
9411 No special properties. */
09d92015 9412
dcbd0d71
MGD		 9413struct deprecated_coproc_regs_s
9414{
9415 unsigned cp;
9416 int opc1;
9417 unsigned crn;
9418 unsigned crm;
9419 int opc2;
9420 arm_feature_set deprecated;
9421 arm_feature_set obsoleted;
9422 const char *dep_msg;
9423 const char *obs_msg;
9424};
9425
9426#define DEPR_ACCESS_V8 \
9427 N_("This coprocessor register access is deprecated in ARMv8")
9428
9429/* Table of all deprecated coprocessor registers. */
9430static struct deprecated_coproc_regs_s deprecated_coproc_regs[] =
9431{
9432 {15, 0, 7, 10, 5, /* CP15DMB. */
823d2571 9433 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9434 DEPR_ACCESS_V8, NULL},
9435 {15, 0, 7, 10, 4, /* CP15DSB. */
823d2571 9436 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9437 DEPR_ACCESS_V8, NULL},
9438 {15, 0, 7, 5, 4, /* CP15ISB. */
823d2571 9439 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9440 DEPR_ACCESS_V8, NULL},
9441 {14, 6, 1, 0, 0, /* TEEHBR. */
823d2571 9442 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9443 DEPR_ACCESS_V8, NULL},
9444 {14, 6, 0, 0, 0, /* TEECR. */
823d2571 9445 ARM_FEATURE_CORE_LOW (ARM_EXT_V8), ARM_ARCH_NONE,
dcbd0d71
MGD		 9446 DEPR_ACCESS_V8, NULL},
9447};
9448
9449#undef DEPR_ACCESS_V8
9450
9451static const size_t deprecated_coproc_reg_count =
9452 sizeof (deprecated_coproc_regs) / sizeof (deprecated_coproc_regs[0]);
9453
09d92015 9454static void
c19d1205 9455do_co_reg (void)
09d92015 9456{
fdfde340 9457 unsigned Rd;
dcbd0d71 9458 size_t i;
fdfde340
JM		 9459
9460 Rd = inst.operands[2].reg;
9461 if (thumb_mode)
9462 {
9463 if (inst.instruction == 0xee000010
9464 || inst.instruction == 0xfe000010)
9465 /* MCR, MCR2 */
9466 reject_bad_reg (Rd);
5c8ed6a4 9467 else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
fdfde340
JM		 9468 /* MRC, MRC2 */
9469 constraint (Rd == REG_SP, BAD_SP);
9470 }
9471 else
9472 {
9473 /* MCR */
9474 if (inst.instruction == 0xe000010)
9475 constraint (Rd == REG_PC, BAD_PC);
9476 }
9477
dcbd0d71
MGD		 9478 for (i = 0; i < deprecated_coproc_reg_count; ++i)
9479 {
9480 const struct deprecated_coproc_regs_s *r =
9481 deprecated_coproc_regs + i;
9482
9483 if (inst.operands[0].reg == r->cp
9484 && inst.operands[1].imm == r->opc1
9485 && inst.operands[3].reg == r->crn
9486 && inst.operands[4].reg == r->crm
9487 && inst.operands[5].imm == r->opc2)
9488 {
b10bf8c5 9489 if (! ARM_CPU_IS_ANY (cpu_variant)
477330fc 9490 && warn_on_deprecated
dcbd0d71 9491 && ARM_CPU_HAS_FEATURE (cpu_variant, r->deprecated))
5c3696f8 9492 as_tsktsk ("%s", r->dep_msg);
dcbd0d71
MGD		 9493 }
9494 }
fdfde340 9495
c19d1205
ZW		 9496 inst.instruction |= inst.operands[0].reg << 8;
9497 inst.instruction |= inst.operands[1].imm << 21;
fdfde340 9498 inst.instruction |= Rd << 12;
c19d1205
ZW		 9499 inst.instruction |= inst.operands[3].reg << 16;
9500 inst.instruction |= inst.operands[4].reg;
9501 inst.instruction |= inst.operands[5].imm << 5;
9502}
09d92015 9503
c19d1205
ZW		 9504/* Transfer between coprocessor register and pair of ARM registers.
9505 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9506 MCRR2
9507 MRRC{cond}
9508 MRRC2
b99bd4ef 9509
c19d1205 9510 Two XScale instructions are special cases of these:
09d92015 9511
c19d1205
ZW		 9512 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9513 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
b99bd4ef 9514
5f4273c7 9515 Result unpredictable if Rd or Rn is R15. */
a737bd4d 9516
c19d1205
ZW		 9517static void
9518do_co_reg2c (void)
9519{
fdfde340
JM		 9520 unsigned Rd, Rn;
9521
9522 Rd = inst.operands[2].reg;
9523 Rn = inst.operands[3].reg;
9524
9525 if (thumb_mode)
9526 {
9527 reject_bad_reg (Rd);
9528 reject_bad_reg (Rn);
9529 }
9530 else
9531 {
9532 constraint (Rd == REG_PC, BAD_PC);
9533 constraint (Rn == REG_PC, BAD_PC);
9534 }
9535
873f10f0
TC		 9536 /* Only check the MRRC{2} variants. */
9537 if ((inst.instruction & 0x0FF00000) == 0x0C500000)
9538 {
9539 /* If Rd == Rn, error that the operation is
9540 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9541 constraint (Rd == Rn, BAD_OVERLAP);
9542 }
9543
c19d1205
ZW		 9544 inst.instruction |= inst.operands[0].reg << 8;
9545 inst.instruction |= inst.operands[1].imm << 4;
fdfde340
JM		 9546 inst.instruction |= Rd << 12;
9547 inst.instruction |= Rn << 16;
c19d1205 9548 inst.instruction |= inst.operands[4].reg;
b99bd4ef
NC		 9549}
9550
c19d1205
ZW		 9551static void
9552do_cpsi (void)
9553{
9554 inst.instruction |= inst.operands[0].imm << 6;
a028a6f5
PB		 9555 if (inst.operands[1].present)
9556 {
9557 inst.instruction |= CPSI_MMOD;
9558 inst.instruction |= inst.operands[1].imm;
9559 }
c19d1205 9560}
b99bd4ef 9561
62b3e311
PB		 9562static void
9563do_dbg (void)
9564{
9565 inst.instruction |= inst.operands[0].imm;
9566}
9567
eea54501
MGD		 9568static void
9569do_div (void)
9570{
9571 unsigned Rd, Rn, Rm;
9572
9573 Rd = inst.operands[0].reg;
9574 Rn = (inst.operands[1].present
9575 ? inst.operands[1].reg : Rd);
9576 Rm = inst.operands[2].reg;
9577
9578 constraint ((Rd == REG_PC), BAD_PC);
9579 constraint ((Rn == REG_PC), BAD_PC);
9580 constraint ((Rm == REG_PC), BAD_PC);
9581
9582 inst.instruction |= Rd << 16;
9583 inst.instruction |= Rn << 0;
9584 inst.instruction |= Rm << 8;
9585}
9586
b99bd4ef 9587static void
c19d1205 9588do_it (void)
b99bd4ef 9589{
c19d1205 9590 /* There is no IT instruction in ARM mode. We
e07e6e58
NC		 9591 process it to do the validation as if in
9592 thumb mode, just in case the code gets
9593 assembled for thumb using the unified syntax. */
9594
c19d1205 9595 inst.size = 0;
e07e6e58
NC		 9596 if (unified_syntax)
9597 {
5ee91343
AV		 9598 set_pred_insn_type (IT_INSN);
9599 now_pred.mask = (inst.instruction & 0xf) | 0x10;
9600 now_pred.cc = inst.operands[0].imm;
e07e6e58 9601 }
09d92015 9602}
b99bd4ef 9603
6530b175
NC		 9604/* If there is only one register in the register list,
9605 then return its register number. Otherwise return -1. */
9606static int
9607only_one_reg_in_list (int range)
9608{
9609 int i = ffs (range) - 1;
9610 return (i > 15 || range != (1 << i)) ? -1 : i;
9611}
9612
09d92015 9613static void
6530b175 9614encode_ldmstm(int from_push_pop_mnem)
ea6ef066 9615{
c19d1205
ZW		 9616 int base_reg = inst.operands[0].reg;
9617 int range = inst.operands[1].imm;
6530b175 9618 int one_reg;
ea6ef066 9619
c19d1205
ZW		 9620 inst.instruction |= base_reg << 16;
9621 inst.instruction |= range;
ea6ef066 9622
c19d1205
ZW		 9623 if (inst.operands[1].writeback)
9624 inst.instruction |= LDM_TYPE_2_OR_3;
09d92015 9625
c19d1205 9626 if (inst.operands[0].writeback)
ea6ef066 9627 {
c19d1205
ZW		 9628 inst.instruction |= WRITE_BACK;
9629 /* Check for unpredictable uses of writeback. */
9630 if (inst.instruction & LOAD_BIT)
09d92015 9631 {
c19d1205
ZW		 9632 /* Not allowed in LDM type 2. */
9633 if ((inst.instruction & LDM_TYPE_2_OR_3)
9634 && ((range & (1 << REG_PC)) == 0))
9635 as_warn (_("writeback of base register is UNPREDICTABLE"));
9636 /* Only allowed if base reg not in list for other types. */
9637 else if (range & (1 << base_reg))
9638 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9639 }
9640 else /* STM. */
9641 {
9642 /* Not allowed for type 2. */
9643 if (inst.instruction & LDM_TYPE_2_OR_3)
9644 as_warn (_("writeback of base register is UNPREDICTABLE"));
9645 /* Only allowed if base reg not in list, or first in list. */
9646 else if ((range & (1 << base_reg))
9647 && (range & ((1 << base_reg) - 1)))
9648 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
09d92015 9649 }
ea6ef066 9650 }
6530b175
NC		 9651
9652 /* If PUSH/POP has only one register, then use the A2 encoding. */
9653 one_reg = only_one_reg_in_list (range);
9654 if (from_push_pop_mnem && one_reg >= 0)
9655 {
9656 int is_push = (inst.instruction & A_PUSH_POP_OP_MASK) == A1_OPCODE_PUSH;
9657
4f588891
NC		 9658 if (is_push && one_reg == 13 /* SP */)
9659 /* PR 22483: The A2 encoding cannot be used when
9660 pushing the stack pointer as this is UNPREDICTABLE. */
9661 return;
9662
6530b175
NC		 9663 inst.instruction &= A_COND_MASK;
9664 inst.instruction |= is_push ? A2_OPCODE_PUSH : A2_OPCODE_POP;
9665 inst.instruction |= one_reg << 12;
9666 }
9667}
9668
9669static void
9670do_ldmstm (void)
9671{
9672 encode_ldmstm (/*from_push_pop_mnem=*/FALSE);
a737bd4d
NC		 9673}
9674
c19d1205
ZW		 9675/* ARMv5TE load-consecutive (argument parse)
9676 Mode is like LDRH.
9677
9678 LDRccD R, mode
9679 STRccD R, mode. */
9680
a737bd4d 9681static void
c19d1205 9682do_ldrd (void)
a737bd4d 9683{
c19d1205 9684 constraint (inst.operands[0].reg % 2 != 0,
c56791bb 9685 _("first transfer register must be even"));
c19d1205
ZW		 9686 constraint (inst.operands[1].present
9687 && inst.operands[1].reg != inst.operands[0].reg + 1,
c56791bb 9688 _("can only transfer two consecutive registers"));
c19d1205
ZW		 9689 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
9690 constraint (!inst.operands[2].isreg, _("'[' expected"));
a737bd4d 9691
c19d1205
ZW		 9692 if (!inst.operands[1].present)
9693 inst.operands[1].reg = inst.operands[0].reg + 1;
5f4273c7 9694
c56791bb
RE		 9695 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9696 register and the first register written; we have to diagnose
9697 overlap between the base and the second register written here. */
ea6ef066 9698
c56791bb
RE		 9699 if (inst.operands[2].reg == inst.operands[1].reg
9700 && (inst.operands[2].writeback || inst.operands[2].postind))
9701 as_warn (_("base register written back, and overlaps "
9702 "second transfer register"));
b05fe5cf 9703
c56791bb
RE		 9704 if (!(inst.instruction & V4_STR_BIT))
9705 {
c19d1205 9706 /* For an index-register load, the index register must not overlap the
c56791bb
RE		 9707 destination (even if not write-back). */
9708 if (inst.operands[2].immisreg
9709 && ((unsigned) inst.operands[2].imm == inst.operands[0].reg
9710 || (unsigned) inst.operands[2].imm == inst.operands[1].reg))
9711 as_warn (_("index register overlaps transfer register"));
b05fe5cf 9712 }
c19d1205
ZW		 9713 inst.instruction |= inst.operands[0].reg << 12;
9714 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE);
b05fe5cf
ZW		 9715}
9716
9717static void
c19d1205 9718do_ldrex (void)
b05fe5cf 9719{
c19d1205
ZW		 9720 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
9721 || inst.operands[1].postind || inst.operands[1].writeback
9722 || inst.operands[1].immisreg || inst.operands[1].shifted
01cfc07f
NC		 9723 || inst.operands[1].negative
9724 /* This can arise if the programmer has written
9725 strex rN, rM, foo
9726 or if they have mistakenly used a register name as the last
9727 operand, eg:
9728 strex rN, rM, rX
9729 It is very difficult to distinguish between these two cases
9730 because "rX" might actually be a label. ie the register
9731 name has been occluded by a symbol of the same name. So we
9732 just generate a general 'bad addressing mode' type error
9733 message and leave it up to the programmer to discover the
9734 true cause and fix their mistake. */
9735 || (inst.operands[1].reg == REG_PC),
9736 BAD_ADDR_MODE);
b05fe5cf 9737
e2b0ab59
AV		 9738 constraint (inst.relocs[0].exp.X_op != O_constant
9739 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9740 _("offset must be zero in ARM encoding"));
b05fe5cf 9741
5be8be5d
DG		 9742 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
9743
c19d1205
ZW		 9744 inst.instruction |= inst.operands[0].reg << 12;
9745 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 9746 inst.relocs[0].type = BFD_RELOC_UNUSED;
b05fe5cf
ZW		 9747}
9748
9749static void
c19d1205 9750do_ldrexd (void)
b05fe5cf 9751{
c19d1205
ZW		 9752 constraint (inst.operands[0].reg % 2 != 0,
9753 _("even register required"));
9754 constraint (inst.operands[1].present
9755 && inst.operands[1].reg != inst.operands[0].reg + 1,
9756 _("can only load two consecutive registers"));
9757 /* If op 1 were present and equal to PC, this function wouldn't
9758 have been called in the first place. */
9759 constraint (inst.operands[0].reg == REG_LR, _("r14 not allowed here"));
b05fe5cf 9760
c19d1205
ZW		 9761 inst.instruction |= inst.operands[0].reg << 12;
9762 inst.instruction |= inst.operands[2].reg << 16;
b05fe5cf
ZW		 9763}
9764
1be5fd2e
NC		 9765/* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9766 which is not a multiple of four is UNPREDICTABLE. */
9767static void
9768check_ldr_r15_aligned (void)
9769{
9770 constraint (!(inst.operands[1].immisreg)
9771 && (inst.operands[0].reg == REG_PC
9772 && inst.operands[1].reg == REG_PC
e2b0ab59 9773 && (inst.relocs[0].exp.X_add_number & 0x3)),
de194d85 9774 _("ldr to register 15 must be 4-byte aligned"));
1be5fd2e
NC		 9775}
9776
b05fe5cf 9777static void
c19d1205 9778do_ldst (void)
b05fe5cf 9779{
c19d1205
ZW		 9780 inst.instruction |= inst.operands[0].reg << 12;
9781 if (!inst.operands[1].isreg)
8335d6aa 9782 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/FALSE))
b05fe5cf 9783 return;
c19d1205 9784 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE);
1be5fd2e 9785 check_ldr_r15_aligned ();
b05fe5cf
ZW		 9786}
9787
9788static void
c19d1205 9789do_ldstt (void)
b05fe5cf 9790{
c19d1205
ZW		 9791 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9792 reject [Rn,...]. */
9793 if (inst.operands[1].preind)
b05fe5cf 9794 {
e2b0ab59
AV		 9795 constraint (inst.relocs[0].exp.X_op != O_constant
9796 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9797 _("this instruction requires a post-indexed address"));
b05fe5cf 9798
c19d1205
ZW		 9799 inst.operands[1].preind = 0;
9800 inst.operands[1].postind = 1;
9801 inst.operands[1].writeback = 1;
b05fe5cf 9802 }
c19d1205
ZW		 9803 inst.instruction |= inst.operands[0].reg << 12;
9804 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE);
9805}
b05fe5cf 9806
c19d1205 9807/* Halfword and signed-byte load/store operations. */
b05fe5cf 9808
c19d1205
ZW		 9809static void
9810do_ldstv4 (void)
9811{
ff4a8d2b 9812 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205
ZW		 9813 inst.instruction |= inst.operands[0].reg << 12;
9814 if (!inst.operands[1].isreg)
8335d6aa 9815 if (move_or_literal_pool (0, CONST_ARM, /*mode_3=*/TRUE))
b05fe5cf 9816 return;
c19d1205 9817 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE);
b05fe5cf
ZW		 9818}
9819
9820static void
c19d1205 9821do_ldsttv4 (void)
b05fe5cf 9822{
c19d1205
ZW		 9823 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9824 reject [Rn,...]. */
9825 if (inst.operands[1].preind)
b05fe5cf 9826 {
e2b0ab59
AV		 9827 constraint (inst.relocs[0].exp.X_op != O_constant
9828 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 9829 _("this instruction requires a post-indexed address"));
b05fe5cf 9830
c19d1205
ZW		 9831 inst.operands[1].preind = 0;
9832 inst.operands[1].postind = 1;
9833 inst.operands[1].writeback = 1;
b05fe5cf 9834 }
c19d1205
ZW		 9835 inst.instruction |= inst.operands[0].reg << 12;
9836 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE);
9837}
b05fe5cf 9838
c19d1205
ZW		 9839/* Co-processor register load/store.
9840 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9841static void
9842do_lstc (void)
9843{
9844 inst.instruction |= inst.operands[0].reg << 8;
9845 inst.instruction |= inst.operands[1].reg << 12;
9846 encode_arm_cp_address (2, TRUE, TRUE, 0);
b05fe5cf
ZW		 9847}
9848
b05fe5cf 9849static void
c19d1205 9850do_mlas (void)
b05fe5cf 9851{
8fb9d7b9 9852 /* This restriction does not apply to mls (nor to mla in v6 or later). */
c19d1205 9853 if (inst.operands[0].reg == inst.operands[1].reg
8fb9d7b9 9854 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6)
c19d1205 9855 && !(inst.instruction & 0x00400000))
8fb9d7b9 9856 as_tsktsk (_("Rd and Rm should be different in mla"));
b05fe5cf 9857
c19d1205
ZW		 9858 inst.instruction |= inst.operands[0].reg << 16;
9859 inst.instruction |= inst.operands[1].reg;
9860 inst.instruction |= inst.operands[2].reg << 8;
9861 inst.instruction |= inst.operands[3].reg << 12;
c19d1205 9862}
b05fe5cf 9863
c19d1205
ZW		 9864static void
9865do_mov (void)
9866{
e2b0ab59
AV		 9867 constraint (inst.relocs[0].type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9868 && inst.relocs[0].type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC ,
a9f02af8 9869 THUMB1_RELOC_ONLY);
c19d1205
ZW		 9870 inst.instruction |= inst.operands[0].reg << 12;
9871 encode_arm_shifter_operand (1);
9872}
b05fe5cf 9873
c19d1205
ZW		 9874/* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9875static void
9876do_mov16 (void)
9877{
b6895b4f
PB		 9878 bfd_vma imm;
9879 bfd_boolean top;
9880
9881 top = (inst.instruction & 0x00400000) != 0;
e2b0ab59 9882 constraint (top && inst.relocs[0].type == BFD_RELOC_ARM_MOVW,
33eaf5de 9883 _(":lower16: not allowed in this instruction"));
e2b0ab59 9884 constraint (!top && inst.relocs[0].type == BFD_RELOC_ARM_MOVT,
33eaf5de 9885 _(":upper16: not allowed in this instruction"));
c19d1205 9886 inst.instruction |= inst.operands[0].reg << 12;
e2b0ab59 9887 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 9888 {
e2b0ab59 9889 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB		 9890 /* The value is in two pieces: 0:11, 16:19. */
9891 inst.instruction |= (imm & 0x00000fff);
9892 inst.instruction |= (imm & 0x0000f000) << 4;
9893 }
b05fe5cf 9894}
b99bd4ef 9895
037e8744
JB		 9896static int
9897do_vfp_nsyn_mrs (void)
9898{
9899 if (inst.operands[0].isvec)
9900 {
9901 if (inst.operands[1].reg != 1)
477330fc 9902 first_error (_("operand 1 must be FPSCR"));
037e8744
JB		 9903 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
9904 memset (&inst.operands[1], '\0', sizeof (inst.operands[1]));
9905 do_vfp_nsyn_opcode ("fmstat");
9906 }
9907 else if (inst.operands[1].isvec)
9908 do_vfp_nsyn_opcode ("fmrx");
9909 else
9910 return FAIL;
5f4273c7 9911
037e8744
JB		 9912 return SUCCESS;
9913}
9914
9915static int
9916do_vfp_nsyn_msr (void)
9917{
9918 if (inst.operands[0].isvec)
9919 do_vfp_nsyn_opcode ("fmxr");
9920 else
9921 return FAIL;
9922
9923 return SUCCESS;
9924}
9925
f7c21dc7
NC		 9926static void
9927do_vmrs (void)
9928{
9929 unsigned Rt = inst.operands[0].reg;
fa94de6b 9930
16d02dc9 9931 if (thumb_mode && Rt == REG_SP)
f7c21dc7
NC		 9932 {
9933 inst.error = BAD_SP;
9934 return;
9935 }
9936
ba6cd17f
SD		 9937 switch (inst.operands[1].reg)
9938 {
9939 /* MVFR2 is only valid for Armv8-A. */
9940 case 5:
9941 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
9942 _(BAD_FPU));
9943 break;
9944
9945 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9946 case 1: /* fpscr. */
9947 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
9948 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
9949 _(BAD_FPU));
9950 break;
9951
9952 case 14: /* fpcxt_ns. */
9953 case 15: /* fpcxt_s. */
9954 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
9955 _("selected processor does not support instruction"));
9956 break;
9957
9958 case 2: /* fpscr_nzcvqc. */
9959 case 12: /* vpr. */
9960 case 13: /* p0. */
9961 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
9962 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
9963 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
9964 _("selected processor does not support instruction"));
9965 if (inst.operands[0].reg != 2
9966 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
9967 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9968 break;
9969
9970 default:
9971 break;
9972 }
40c7d507 9973
f7c21dc7 9974 /* APSR_ sets isvec. All other refs to PC are illegal. */
16d02dc9 9975 if (!inst.operands[0].isvec && Rt == REG_PC)
f7c21dc7
NC		 9976 {
9977 inst.error = BAD_PC;
9978 return;
9979 }
9980
16d02dc9
JB		 9981 /* If we get through parsing the register name, we just insert the number
9982 generated into the instruction without further validation. */
9983 inst.instruction |= (inst.operands[1].reg << 16);
f7c21dc7
NC		 9984 inst.instruction |= (Rt << 12);
9985}
9986
9987static void
9988do_vmsr (void)
9989{
9990 unsigned Rt = inst.operands[1].reg;
fa94de6b 9991
f7c21dc7
NC		 9992 if (thumb_mode)
9993 reject_bad_reg (Rt);
9994 else if (Rt == REG_PC)
9995 {
9996 inst.error = BAD_PC;
9997 return;
9998 }
9999
ba6cd17f
SD		 10000 switch (inst.operands[0].reg)
10001 {
10002 /* MVFR2 is only valid for Armv8-A. */
10003 case 5:
10004 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
10005 _(BAD_FPU));
10006 break;
10007
10008 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10009 case 1: /* fpcr. */
10010 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10011 || ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10012 _(BAD_FPU));
10013 break;
10014
10015 case 14: /* fpcxt_ns. */
10016 case 15: /* fpcxt_s. */
10017 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main),
10018 _("selected processor does not support instruction"));
10019 break;
10020
10021 case 2: /* fpscr_nzcvqc. */
10022 case 12: /* vpr. */
10023 case 13: /* p0. */
10024 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8_1m_main)
10025 || (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
10026 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)),
10027 _("selected processor does not support instruction"));
10028 if (inst.operands[0].reg != 2
10029 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
10030 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10031 break;
10032
10033 default:
10034 break;
10035 }
40c7d507 10036
16d02dc9
JB		 10037 /* If we get through parsing the register name, we just insert the number
10038 generated into the instruction without further validation. */
10039 inst.instruction |= (inst.operands[0].reg << 16);
f7c21dc7
NC		 10040 inst.instruction |= (Rt << 12);
10041}
10042
b99bd4ef 10043static void
c19d1205 10044do_mrs (void)
b99bd4ef 10045{
90ec0d68
MGD		 10046 unsigned br;
10047
037e8744
JB		 10048 if (do_vfp_nsyn_mrs () == SUCCESS)
10049 return;
10050
ff4a8d2b 10051 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
c19d1205 10052 inst.instruction |= inst.operands[0].reg << 12;
90ec0d68
MGD		 10053
10054 if (inst.operands[1].isreg)
10055 {
10056 br = inst.operands[1].reg;
806ab1c0 10057 if (((br & 0x200) == 0) && ((br & 0xf0000) != 0xf0000))
90ec0d68
MGD		 10058 as_bad (_("bad register for mrs"));
10059 }
10060 else
10061 {
10062 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10063 constraint ((inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f))
10064 != (PSR_c|PSR_f),
d2cd1205 10065 _("'APSR', 'CPSR' or 'SPSR' expected"));
90ec0d68
MGD		 10066 br = (15<<16) | (inst.operands[1].imm & SPSR_BIT);
10067 }
10068
10069 inst.instruction |= br;
c19d1205 10070}
b99bd4ef 10071
c19d1205
ZW		 10072/* Two possible forms:
10073 "{C|S}PSR_<field>, Rm",
10074 "{C|S}PSR_f, #expression". */
b99bd4ef 10075
c19d1205
ZW		 10076static void
10077do_msr (void)
10078{
037e8744
JB		 10079 if (do_vfp_nsyn_msr () == SUCCESS)
10080 return;
10081
c19d1205
ZW		 10082 inst.instruction |= inst.operands[0].imm;
10083 if (inst.operands[1].isreg)
10084 inst.instruction |= inst.operands[1].reg;
10085 else
b99bd4ef 10086 {
c19d1205 10087 inst.instruction |= INST_IMMEDIATE;
e2b0ab59
AV		 10088 inst.relocs[0].type = BFD_RELOC_ARM_IMMEDIATE;
10089 inst.relocs[0].pc_rel = 0;
b99bd4ef 10090 }
b99bd4ef
NC		 10091}
10092
c19d1205
ZW		 10093static void
10094do_mul (void)
a737bd4d 10095{
ff4a8d2b
NC		 10096 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
10097
c19d1205
ZW		 10098 if (!inst.operands[2].present)
10099 inst.operands[2].reg = inst.operands[0].reg;
10100 inst.instruction |= inst.operands[0].reg << 16;
10101 inst.instruction |= inst.operands[1].reg;
10102 inst.instruction |= inst.operands[2].reg << 8;
a737bd4d 10103
8fb9d7b9
MS		 10104 if (inst.operands[0].reg == inst.operands[1].reg
10105 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
10106 as_tsktsk (_("Rd and Rm should be different in mul"));
a737bd4d
NC		 10107}
10108
c19d1205
ZW		 10109/* Long Multiply Parser
10110 UMULL RdLo, RdHi, Rm, Rs
10111 SMULL RdLo, RdHi, Rm, Rs
10112 UMLAL RdLo, RdHi, Rm, Rs
10113 SMLAL RdLo, RdHi, Rm, Rs. */
b99bd4ef
NC		 10114
10115static void
c19d1205 10116do_mull (void)
b99bd4ef 10117{
c19d1205
ZW		 10118 inst.instruction |= inst.operands[0].reg << 12;
10119 inst.instruction |= inst.operands[1].reg << 16;
10120 inst.instruction |= inst.operands[2].reg;
10121 inst.instruction |= inst.operands[3].reg << 8;
b99bd4ef 10122
682b27ad
PB		 10123 /* rdhi and rdlo must be different. */
10124 if (inst.operands[0].reg == inst.operands[1].reg)
10125 as_tsktsk (_("rdhi and rdlo must be different"));
10126
10127 /* rdhi, rdlo and rm must all be different before armv6. */
10128 if ((inst.operands[0].reg == inst.operands[2].reg
c19d1205 10129 || inst.operands[1].reg == inst.operands[2].reg)
682b27ad 10130 && !ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6))
c19d1205
ZW		 10131 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10132}
b99bd4ef 10133
c19d1205
ZW		 10134static void
10135do_nop (void)
10136{
e7495e45
NS		 10137 if (inst.operands[0].present
10138 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6k))
c19d1205
ZW		 10139 {
10140 /* Architectural NOP hints are CPSR sets with no bits selected. */
10141 inst.instruction &= 0xf0000000;
e7495e45
NS		 10142 inst.instruction |= 0x0320f000;
10143 if (inst.operands[0].present)
10144 inst.instruction |= inst.operands[0].imm;
c19d1205 10145 }
b99bd4ef
NC		 10146}
10147
c19d1205
ZW		 10148/* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10149 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10150 Condition defaults to COND_ALWAYS.
10151 Error if Rd, Rn or Rm are R15. */
b99bd4ef
NC		 10152
10153static void
c19d1205 10154do_pkhbt (void)
b99bd4ef 10155{
c19d1205
ZW		 10156 inst.instruction |= inst.operands[0].reg << 12;
10157 inst.instruction |= inst.operands[1].reg << 16;
10158 inst.instruction |= inst.operands[2].reg;
10159 if (inst.operands[3].present)
10160 encode_arm_shift (3);
10161}
b99bd4ef 10162
c19d1205 10163/* ARM V6 PKHTB (Argument Parse). */
b99bd4ef 10164
c19d1205
ZW		 10165static void
10166do_pkhtb (void)
10167{
10168 if (!inst.operands[3].present)
b99bd4ef 10169 {
c19d1205
ZW		 10170 /* If the shift specifier is omitted, turn the instruction
10171 into pkhbt rd, rm, rn. */
10172 inst.instruction &= 0xfff00010;
10173 inst.instruction |= inst.operands[0].reg << 12;
10174 inst.instruction |= inst.operands[1].reg;
10175 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 10176 }
10177 else
10178 {
c19d1205
ZW		 10179 inst.instruction |= inst.operands[0].reg << 12;
10180 inst.instruction |= inst.operands[1].reg << 16;
10181 inst.instruction |= inst.operands[2].reg;
10182 encode_arm_shift (3);
b99bd4ef
NC		 10183 }
10184}
10185
c19d1205 10186/* ARMv5TE: Preload-Cache
60e5ef9f 10187 MP Extensions: Preload for write
c19d1205 10188
60e5ef9f 10189 PLD(W) <addr_mode>
c19d1205
ZW		 10190
10191 Syntactically, like LDR with B=1, W=0, L=1. */
b99bd4ef
NC		 10192
10193static void
c19d1205 10194do_pld (void)
b99bd4ef 10195{
c19d1205
ZW		 10196 constraint (!inst.operands[0].isreg,
10197 _("'[' expected after PLD mnemonic"));
10198 constraint (inst.operands[0].postind,
10199 _("post-indexed expression used in preload instruction"));
10200 constraint (inst.operands[0].writeback,
10201 _("writeback used in preload instruction"));
10202 constraint (!inst.operands[0].preind,
10203 _("unindexed addressing used in preload instruction"));
c19d1205
ZW		 10204 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10205}
b99bd4ef 10206
62b3e311
PB		 10207/* ARMv7: PLI <addr_mode> */
10208static void
10209do_pli (void)
10210{
10211 constraint (!inst.operands[0].isreg,
10212 _("'[' expected after PLI mnemonic"));
10213 constraint (inst.operands[0].postind,
10214 _("post-indexed expression used in preload instruction"));
10215 constraint (inst.operands[0].writeback,
10216 _("writeback used in preload instruction"));
10217 constraint (!inst.operands[0].preind,
10218 _("unindexed addressing used in preload instruction"));
10219 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE);
10220 inst.instruction &= ~PRE_INDEX;
10221}
10222
c19d1205
ZW		 10223static void
10224do_push_pop (void)
10225{
5e0d7f77
MP		 10226 constraint (inst.operands[0].writeback,
10227 _("push/pop do not support {reglist}^"));
c19d1205
ZW		 10228 inst.operands[1] = inst.operands[0];
10229 memset (&inst.operands[0], 0, sizeof inst.operands[0]);
10230 inst.operands[0].isreg = 1;
10231 inst.operands[0].writeback = 1;
10232 inst.operands[0].reg = REG_SP;
6530b175 10233 encode_ldmstm (/*from_push_pop_mnem=*/TRUE);
c19d1205 10234}
b99bd4ef 10235
c19d1205
ZW		 10236/* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10237 word at the specified address and the following word
10238 respectively.
10239 Unconditionally executed.
10240 Error if Rn is R15. */
b99bd4ef 10241
c19d1205
ZW		 10242static void
10243do_rfe (void)
10244{
10245 inst.instruction |= inst.operands[0].reg << 16;
10246 if (inst.operands[0].writeback)
10247 inst.instruction |= WRITE_BACK;
10248}
b99bd4ef 10249
c19d1205 10250/* ARM V6 ssat (argument parse). */
b99bd4ef 10251
c19d1205
ZW		 10252static void
10253do_ssat (void)
10254{
10255 inst.instruction |= inst.operands[0].reg << 12;
10256 inst.instruction |= (inst.operands[1].imm - 1) << 16;
10257 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10258
c19d1205
ZW		 10259 if (inst.operands[3].present)
10260 encode_arm_shift (3);
b99bd4ef
NC		 10261}
10262
c19d1205 10263/* ARM V6 usat (argument parse). */
b99bd4ef
NC		 10264
10265static void
c19d1205 10266do_usat (void)
b99bd4ef 10267{
c19d1205
ZW		 10268 inst.instruction |= inst.operands[0].reg << 12;
10269 inst.instruction |= inst.operands[1].imm << 16;
10270 inst.instruction |= inst.operands[2].reg;
b99bd4ef 10271
c19d1205
ZW		 10272 if (inst.operands[3].present)
10273 encode_arm_shift (3);
b99bd4ef
NC		 10274}
10275
c19d1205 10276/* ARM V6 ssat16 (argument parse). */
09d92015
MM		 10277
10278static void
c19d1205 10279do_ssat16 (void)
09d92015 10280{
c19d1205
ZW		 10281 inst.instruction |= inst.operands[0].reg << 12;
10282 inst.instruction |= ((inst.operands[1].imm - 1) << 16);
10283 inst.instruction |= inst.operands[2].reg;
09d92015
MM		 10284}
10285
c19d1205
ZW		 10286static void
10287do_usat16 (void)
a737bd4d 10288{
c19d1205
ZW		 10289 inst.instruction |= inst.operands[0].reg << 12;
10290 inst.instruction |= inst.operands[1].imm << 16;
10291 inst.instruction |= inst.operands[2].reg;
10292}
a737bd4d 10293
c19d1205
ZW		 10294/* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10295 preserving the other bits.
a737bd4d 10296
c19d1205
ZW		 10297 setend <endian_specifier>, where <endian_specifier> is either
10298 BE or LE. */
a737bd4d 10299
c19d1205
ZW		 10300static void
10301do_setend (void)
10302{
12e37cbc
MGD		 10303 if (warn_on_deprecated
10304 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 10305 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 10306
c19d1205
ZW		 10307 if (inst.operands[0].imm)
10308 inst.instruction |= 0x200;
a737bd4d
NC		 10309}
10310
10311static void
c19d1205 10312do_shift (void)
a737bd4d 10313{
c19d1205
ZW		 10314 unsigned int Rm = (inst.operands[1].present
10315 ? inst.operands[1].reg
10316 : inst.operands[0].reg);
a737bd4d 10317
c19d1205
ZW		 10318 inst.instruction |= inst.operands[0].reg << 12;
10319 inst.instruction |= Rm;
10320 if (inst.operands[2].isreg) /* Rd, {Rm,} Rs */
a737bd4d 10321 {
c19d1205
ZW		 10322 inst.instruction |= inst.operands[2].reg << 8;
10323 inst.instruction |= SHIFT_BY_REG;
94342ec3
NC		 10324 /* PR 12854: Error on extraneous shifts. */
10325 constraint (inst.operands[2].shifted,
10326 _("extraneous shift as part of operand to shift insn"));
a737bd4d
NC		 10327 }
10328 else
e2b0ab59 10329 inst.relocs[0].type = BFD_RELOC_ARM_SHIFT_IMM;
a737bd4d
NC		 10330}
10331
09d92015 10332static void
3eb17e6b 10333do_smc (void)
09d92015 10334{
ba85f98c
BW		 10335 unsigned int value = inst.relocs[0].exp.X_add_number;
10336 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
10337
e2b0ab59
AV		 10338 inst.relocs[0].type = BFD_RELOC_ARM_SMC;
10339 inst.relocs[0].pc_rel = 0;
09d92015
MM		 10340}
10341
90ec0d68
MGD		 10342static void
10343do_hvc (void)
10344{
e2b0ab59
AV		 10345 inst.relocs[0].type = BFD_RELOC_ARM_HVC;
10346 inst.relocs[0].pc_rel = 0;
90ec0d68
MGD		 10347}
10348
09d92015 10349static void
c19d1205 10350do_swi (void)
09d92015 10351{
e2b0ab59
AV		 10352 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
10353 inst.relocs[0].pc_rel = 0;
09d92015
MM		 10354}
10355
ddfded2f
MW		 10356static void
10357do_setpan (void)
10358{
10359 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10360 _("selected processor does not support SETPAN instruction"));
10361
10362 inst.instruction |= ((inst.operands[0].imm & 1) << 9);
10363}
10364
10365static void
10366do_t_setpan (void)
10367{
10368 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_pan),
10369 _("selected processor does not support SETPAN instruction"));
10370
10371 inst.instruction |= (inst.operands[0].imm << 3);
10372}
10373
c19d1205
ZW		 10374/* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10375 SMLAxy{cond} Rd,Rm,Rs,Rn
10376 SMLAWy{cond} Rd,Rm,Rs,Rn
10377 Error if any register is R15. */
e16bb312 10378
c19d1205
ZW		 10379static void
10380do_smla (void)
e16bb312 10381{
c19d1205
ZW		 10382 inst.instruction |= inst.operands[0].reg << 16;
10383 inst.instruction |= inst.operands[1].reg;
10384 inst.instruction |= inst.operands[2].reg << 8;
10385 inst.instruction |= inst.operands[3].reg << 12;
10386}
a737bd4d 10387
c19d1205
ZW		 10388/* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10389 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10390 Error if any register is R15.
10391 Warning if Rdlo == Rdhi. */
a737bd4d 10392
c19d1205
ZW		 10393static void
10394do_smlal (void)
10395{
10396 inst.instruction |= inst.operands[0].reg << 12;
10397 inst.instruction |= inst.operands[1].reg << 16;
10398 inst.instruction |= inst.operands[2].reg;
10399 inst.instruction |= inst.operands[3].reg << 8;
a737bd4d 10400
c19d1205
ZW		 10401 if (inst.operands[0].reg == inst.operands[1].reg)
10402 as_tsktsk (_("rdhi and rdlo must be different"));
10403}
a737bd4d 10404
c19d1205
ZW		 10405/* ARM V5E (El Segundo) signed-multiply (argument parse)
10406 SMULxy{cond} Rd,Rm,Rs
10407 Error if any register is R15. */
a737bd4d 10408
c19d1205
ZW		 10409static void
10410do_smul (void)
10411{
10412 inst.instruction |= inst.operands[0].reg << 16;
10413 inst.instruction |= inst.operands[1].reg;
10414 inst.instruction |= inst.operands[2].reg << 8;
10415}
a737bd4d 10416
b6702015
PB		 10417/* ARM V6 srs (argument parse). The variable fields in the encoding are
10418 the same for both ARM and Thumb-2. */
a737bd4d 10419
c19d1205
ZW		 10420static void
10421do_srs (void)
10422{
b6702015
PB		 10423 int reg;
10424
10425 if (inst.operands[0].present)
10426 {
10427 reg = inst.operands[0].reg;
fdfde340 10428 constraint (reg != REG_SP, _("SRS base register must be r13"));
b6702015
PB		 10429 }
10430 else
fdfde340 10431 reg = REG_SP;
b6702015
PB		 10432
10433 inst.instruction |= reg << 16;
10434 inst.instruction |= inst.operands[1].imm;
10435 if (inst.operands[0].writeback || inst.operands[1].writeback)
c19d1205
ZW		 10436 inst.instruction |= WRITE_BACK;
10437}
a737bd4d 10438
c19d1205 10439/* ARM V6 strex (argument parse). */
a737bd4d 10440
c19d1205
ZW		 10441static void
10442do_strex (void)
10443{
10444 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10445 || inst.operands[2].postind || inst.operands[2].writeback
10446 || inst.operands[2].immisreg || inst.operands[2].shifted
01cfc07f
NC		 10447 || inst.operands[2].negative
10448 /* See comment in do_ldrex(). */
10449 || (inst.operands[2].reg == REG_PC),
10450 BAD_ADDR_MODE);
a737bd4d 10451
c19d1205
ZW		 10452 constraint (inst.operands[0].reg == inst.operands[1].reg
10453 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
a737bd4d 10454
e2b0ab59
AV		 10455 constraint (inst.relocs[0].exp.X_op != O_constant
10456 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10457 _("offset must be zero in ARM encoding"));
a737bd4d 10458
c19d1205
ZW		 10459 inst.instruction |= inst.operands[0].reg << 12;
10460 inst.instruction |= inst.operands[1].reg;
10461 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 10462 inst.relocs[0].type = BFD_RELOC_UNUSED;
e16bb312
NC		 10463}
10464
877807f8
NC		 10465static void
10466do_t_strexbh (void)
10467{
10468 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
10469 || inst.operands[2].postind || inst.operands[2].writeback
10470 || inst.operands[2].immisreg || inst.operands[2].shifted
10471 || inst.operands[2].negative,
10472 BAD_ADDR_MODE);
10473
10474 constraint (inst.operands[0].reg == inst.operands[1].reg
10475 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10476
10477 do_rm_rd_rn ();
10478}
10479
e16bb312 10480static void
c19d1205 10481do_strexd (void)
e16bb312 10482{
c19d1205
ZW		 10483 constraint (inst.operands[1].reg % 2 != 0,
10484 _("even register required"));
10485 constraint (inst.operands[2].present
10486 && inst.operands[2].reg != inst.operands[1].reg + 1,
10487 _("can only store two consecutive registers"));
10488 /* If op 2 were present and equal to PC, this function wouldn't
10489 have been called in the first place. */
10490 constraint (inst.operands[1].reg == REG_LR, _("r14 not allowed here"));
e16bb312 10491
c19d1205
ZW		 10492 constraint (inst.operands[0].reg == inst.operands[1].reg
10493 || inst.operands[0].reg == inst.operands[1].reg + 1
10494 || inst.operands[0].reg == inst.operands[3].reg,
10495 BAD_OVERLAP);
e16bb312 10496
c19d1205
ZW		 10497 inst.instruction |= inst.operands[0].reg << 12;
10498 inst.instruction |= inst.operands[1].reg;
10499 inst.instruction |= inst.operands[3].reg << 16;
e16bb312
NC		 10500}
10501
9eb6c0f1
MGD		 10502/* ARM V8 STRL. */
10503static void
4b8c8c02 10504do_stlex (void)
9eb6c0f1
MGD		 10505{
10506 constraint (inst.operands[0].reg == inst.operands[1].reg
10507 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10508
10509 do_rd_rm_rn ();
10510}
10511
10512static void
4b8c8c02 10513do_t_stlex (void)
9eb6c0f1
MGD		 10514{
10515 constraint (inst.operands[0].reg == inst.operands[1].reg
10516 || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP);
10517
10518 do_rm_rd_rn ();
10519}
10520
c19d1205
ZW		 10521/* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10522 extends it to 32-bits, and adds the result to a value in another
10523 register. You can specify a rotation by 0, 8, 16, or 24 bits
10524 before extracting the 16-bit value.
10525 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10526 Condition defaults to COND_ALWAYS.
10527 Error if any register uses R15. */
10528
e16bb312 10529static void
c19d1205 10530do_sxtah (void)
e16bb312 10531{
c19d1205
ZW		 10532 inst.instruction |= inst.operands[0].reg << 12;
10533 inst.instruction |= inst.operands[1].reg << 16;
10534 inst.instruction |= inst.operands[2].reg;
10535 inst.instruction |= inst.operands[3].imm << 10;
10536}
e16bb312 10537
c19d1205 10538/* ARM V6 SXTH.
e16bb312 10539
c19d1205
ZW		 10540 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10541 Condition defaults to COND_ALWAYS.
10542 Error if any register uses R15. */
e16bb312
NC		 10543
10544static void
c19d1205 10545do_sxth (void)
e16bb312 10546{
c19d1205
ZW		 10547 inst.instruction |= inst.operands[0].reg << 12;
10548 inst.instruction |= inst.operands[1].reg;
10549 inst.instruction |= inst.operands[2].imm << 10;
e16bb312 10550}
c19d1205
ZW		 10551\f
10552/* VFP instructions. In a logical order: SP variant first, monad
10553 before dyad, arithmetic then move then load/store. */
e16bb312
NC		 10554
10555static void
c19d1205 10556do_vfp_sp_monadic (void)
e16bb312 10557{
57785aa2
AV		 10558 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10559 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10560 _(BAD_FPU));
10561
5287ad62
JB		 10562 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10563 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 10564}
10565
10566static void
c19d1205 10567do_vfp_sp_dyadic (void)
e16bb312 10568{
5287ad62
JB		 10569 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10570 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
10571 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 10572}
10573
10574static void
c19d1205 10575do_vfp_sp_compare_z (void)
e16bb312 10576{
5287ad62 10577 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
e16bb312
NC		 10578}
10579
10580static void
c19d1205 10581do_vfp_dp_sp_cvt (void)
e16bb312 10582{
5287ad62
JB		 10583 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10584 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sm);
e16bb312
NC		 10585}
10586
10587static void
c19d1205 10588do_vfp_sp_dp_cvt (void)
e16bb312 10589{
5287ad62
JB		 10590 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10591 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
e16bb312
NC		 10592}
10593
10594static void
c19d1205 10595do_vfp_reg_from_sp (void)
e16bb312 10596{
57785aa2
AV		 10597 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10598 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10599 _(BAD_FPU));
10600
c19d1205 10601 inst.instruction |= inst.operands[0].reg << 12;
5287ad62 10602 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sn);
e16bb312
NC		 10603}
10604
10605static void
c19d1205 10606do_vfp_reg2_from_sp2 (void)
e16bb312 10607{
c19d1205
ZW		 10608 constraint (inst.operands[2].imm != 2,
10609 _("only two consecutive VFP SP registers allowed here"));
10610 inst.instruction |= inst.operands[0].reg << 12;
10611 inst.instruction |= inst.operands[1].reg << 16;
5287ad62 10612 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Sm);
e16bb312
NC		 10613}
10614
10615static void
c19d1205 10616do_vfp_sp_from_reg (void)
e16bb312 10617{
57785aa2
AV		 10618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
10619 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10620 _(BAD_FPU));
10621
5287ad62 10622 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sn);
c19d1205 10623 inst.instruction |= inst.operands[1].reg << 12;
e16bb312
NC		 10624}
10625
10626static void
c19d1205 10627do_vfp_sp2_from_reg2 (void)
e16bb312 10628{
c19d1205
ZW		 10629 constraint (inst.operands[0].imm != 2,
10630 _("only two consecutive VFP SP registers allowed here"));
5287ad62 10631 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sm);
c19d1205
ZW		 10632 inst.instruction |= inst.operands[1].reg << 12;
10633 inst.instruction |= inst.operands[2].reg << 16;
e16bb312
NC		 10634}
10635
10636static void
c19d1205 10637do_vfp_sp_ldst (void)
e16bb312 10638{
5287ad62 10639 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
c19d1205 10640 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 10641}
10642
10643static void
c19d1205 10644do_vfp_dp_ldst (void)
e16bb312 10645{
5287ad62 10646 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
c19d1205 10647 encode_arm_cp_address (1, FALSE, TRUE, 0);
e16bb312
NC		 10648}
10649
c19d1205 10650
e16bb312 10651static void
c19d1205 10652vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10653{
c19d1205
ZW		 10654 if (inst.operands[0].writeback)
10655 inst.instruction |= WRITE_BACK;
10656 else
10657 constraint (ldstm_type != VFP_LDSTMIA,
10658 _("this addressing mode requires base-register writeback"));
10659 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10660 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Sd);
c19d1205 10661 inst.instruction |= inst.operands[1].imm;
e16bb312
NC		 10662}
10663
10664static void
c19d1205 10665vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type)
e16bb312 10666{
c19d1205 10667 int count;
e16bb312 10668
c19d1205
ZW		 10669 if (inst.operands[0].writeback)
10670 inst.instruction |= WRITE_BACK;
10671 else
10672 constraint (ldstm_type != VFP_LDSTMIA && ldstm_type != VFP_LDSTMIAX,
10673 _("this addressing mode requires base-register writeback"));
e16bb312 10674
c19d1205 10675 inst.instruction |= inst.operands[0].reg << 16;
5287ad62 10676 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
e16bb312 10677
c19d1205
ZW		 10678 count = inst.operands[1].imm << 1;
10679 if (ldstm_type == VFP_LDSTMIAX || ldstm_type == VFP_LDSTMDBX)
10680 count += 1;
e16bb312 10681
c19d1205 10682 inst.instruction |= count;
e16bb312
NC		 10683}
10684
10685static void
c19d1205 10686do_vfp_sp_ldstmia (void)
e16bb312 10687{
c19d1205 10688 vfp_sp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 10689}
10690
10691static void
c19d1205 10692do_vfp_sp_ldstmdb (void)
e16bb312 10693{
c19d1205 10694 vfp_sp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 10695}
10696
10697static void
c19d1205 10698do_vfp_dp_ldstmia (void)
e16bb312 10699{
c19d1205 10700 vfp_dp_ldstm (VFP_LDSTMIA);
e16bb312
NC		 10701}
10702
10703static void
c19d1205 10704do_vfp_dp_ldstmdb (void)
e16bb312 10705{
c19d1205 10706 vfp_dp_ldstm (VFP_LDSTMDB);
e16bb312
NC		 10707}
10708
10709static void
c19d1205 10710do_vfp_xp_ldstmia (void)
e16bb312 10711{
c19d1205
ZW		 10712 vfp_dp_ldstm (VFP_LDSTMIAX);
10713}
e16bb312 10714
c19d1205
ZW		 10715static void
10716do_vfp_xp_ldstmdb (void)
10717{
10718 vfp_dp_ldstm (VFP_LDSTMDBX);
e16bb312 10719}
5287ad62
JB		 10720
10721static void
10722do_vfp_dp_rd_rm (void)
10723{
57785aa2
AV		 10724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
10725 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10726 _(BAD_FPU));
10727
5287ad62
JB		 10728 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10729 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dm);
10730}
10731
10732static void
10733do_vfp_dp_rn_rd (void)
10734{
10735 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dn);
10736 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10737}
10738
10739static void
10740do_vfp_dp_rd_rn (void)
10741{
10742 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10743 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10744}
10745
10746static void
10747do_vfp_dp_rd_rn_rm (void)
10748{
57785aa2
AV		 10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10751 _(BAD_FPU));
10752
5287ad62
JB		 10753 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10754 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dn);
10755 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dm);
10756}
10757
10758static void
10759do_vfp_dp_rd (void)
10760{
10761 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10762}
10763
10764static void
10765do_vfp_dp_rm_rd_rn (void)
10766{
57785aa2
AV		 10767 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
10768 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
10769 _(BAD_FPU));
10770
5287ad62
JB		 10771 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dm);
10772 encode_arm_vfp_reg (inst.operands[1].reg, VFP_REG_Dd);
10773 encode_arm_vfp_reg (inst.operands[2].reg, VFP_REG_Dn);
10774}
10775
10776/* VFPv3 instructions. */
10777static void
10778do_vfp_sp_const (void)
10779{
10780 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
00249aaa
PB		 10781 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10782 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 10783}
10784
10785static void
10786do_vfp_dp_const (void)
10787{
10788 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
00249aaa
PB		 10789 inst.instruction |= (inst.operands[1].imm & 0xf0) << 12;
10790 inst.instruction |= (inst.operands[1].imm & 0x0f);
5287ad62
JB		 10791}
10792
10793static void
10794vfp_conv (int srcsize)
10795{
5f1af56b
MGD		 10796 int immbits = srcsize - inst.operands[1].imm;
10797
fa94de6b
RM		 10798 if (srcsize == 16 && !(immbits >= 0 && immbits <= srcsize))
10799 {
5f1af56b 10800 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
477330fc 10801 i.e. immbits must be in range 0 - 16. */
5f1af56b
MGD		 10802 inst.error = _("immediate value out of range, expected range [0, 16]");
10803 return;
10804 }
fa94de6b 10805 else if (srcsize == 32 && !(immbits >= 0 && immbits < srcsize))
5f1af56b
MGD		 10806 {
10807 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
477330fc 10808 i.e. immbits must be in range 0 - 31. */
5f1af56b
MGD		 10809 inst.error = _("immediate value out of range, expected range [1, 32]");
10810 return;
10811 }
10812
5287ad62
JB		 10813 inst.instruction |= (immbits & 1) << 5;
10814 inst.instruction |= (immbits >> 1);
10815}
10816
10817static void
10818do_vfp_sp_conv_16 (void)
10819{
10820 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10821 vfp_conv (16);
10822}
10823
10824static void
10825do_vfp_dp_conv_16 (void)
10826{
10827 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10828 vfp_conv (16);
10829}
10830
10831static void
10832do_vfp_sp_conv_32 (void)
10833{
10834 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
10835 vfp_conv (32);
10836}
10837
10838static void
10839do_vfp_dp_conv_32 (void)
10840{
10841 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Dd);
10842 vfp_conv (32);
10843}
c19d1205
ZW		 10844\f
10845/* FPA instructions. Also in a logical order. */
e16bb312 10846
c19d1205
ZW		 10847static void
10848do_fpa_cmp (void)
10849{
10850 inst.instruction |= inst.operands[0].reg << 16;
10851 inst.instruction |= inst.operands[1].reg;
10852}
b99bd4ef
NC		 10853
10854static void
c19d1205 10855do_fpa_ldmstm (void)
b99bd4ef 10856{
c19d1205
ZW		 10857 inst.instruction |= inst.operands[0].reg << 12;
10858 switch (inst.operands[1].imm)
10859 {
10860 case 1: inst.instruction |= CP_T_X; break;
10861 case 2: inst.instruction |= CP_T_Y; break;
10862 case 3: inst.instruction |= CP_T_Y | CP_T_X; break;
10863 case 4: break;
10864 default: abort ();
10865 }
b99bd4ef 10866
c19d1205
ZW		 10867 if (inst.instruction & (PRE_INDEX | INDEX_UP))
10868 {
10869 /* The instruction specified "ea" or "fd", so we can only accept
10870 [Rn]{!}. The instruction does not really support stacking or
10871 unstacking, so we have to emulate these by setting appropriate
10872 bits and offsets. */
e2b0ab59
AV		 10873 constraint (inst.relocs[0].exp.X_op != O_constant
10874 || inst.relocs[0].exp.X_add_number != 0,
c19d1205 10875 _("this instruction does not support indexing"));
b99bd4ef 10876
c19d1205 10877 if ((inst.instruction & PRE_INDEX) || inst.operands[2].writeback)
e2b0ab59 10878 inst.relocs[0].exp.X_add_number = 12 * inst.operands[1].imm;
b99bd4ef 10879
c19d1205 10880 if (!(inst.instruction & INDEX_UP))
e2b0ab59 10881 inst.relocs[0].exp.X_add_number = -inst.relocs[0].exp.X_add_number;
b99bd4ef 10882
c19d1205
ZW		 10883 if (!(inst.instruction & PRE_INDEX) && inst.operands[2].writeback)
10884 {
10885 inst.operands[2].preind = 0;
10886 inst.operands[2].postind = 1;
10887 }
10888 }
b99bd4ef 10889
c19d1205 10890 encode_arm_cp_address (2, TRUE, TRUE, 0);
b99bd4ef 10891}
c19d1205
ZW		 10892\f
10893/* iWMMXt instructions: strictly in alphabetical order. */
b99bd4ef 10894
c19d1205
ZW		 10895static void
10896do_iwmmxt_tandorc (void)
10897{
10898 constraint (inst.operands[0].reg != REG_PC, _("only r15 allowed here"));
10899}
b99bd4ef 10900
c19d1205
ZW		 10901static void
10902do_iwmmxt_textrc (void)
10903{
10904 inst.instruction |= inst.operands[0].reg << 12;
10905 inst.instruction |= inst.operands[1].imm;
10906}
b99bd4ef
NC		 10907
10908static void
c19d1205 10909do_iwmmxt_textrm (void)
b99bd4ef 10910{
c19d1205
ZW		 10911 inst.instruction |= inst.operands[0].reg << 12;
10912 inst.instruction |= inst.operands[1].reg << 16;
10913 inst.instruction |= inst.operands[2].imm;
10914}
b99bd4ef 10915
c19d1205
ZW		 10916static void
10917do_iwmmxt_tinsr (void)
10918{
10919 inst.instruction |= inst.operands[0].reg << 16;
10920 inst.instruction |= inst.operands[1].reg << 12;
10921 inst.instruction |= inst.operands[2].imm;
10922}
b99bd4ef 10923
c19d1205
ZW		 10924static void
10925do_iwmmxt_tmia (void)
10926{
10927 inst.instruction |= inst.operands[0].reg << 5;
10928 inst.instruction |= inst.operands[1].reg;
10929 inst.instruction |= inst.operands[2].reg << 12;
10930}
b99bd4ef 10931
c19d1205
ZW		 10932static void
10933do_iwmmxt_waligni (void)
10934{
10935 inst.instruction |= inst.operands[0].reg << 12;
10936 inst.instruction |= inst.operands[1].reg << 16;
10937 inst.instruction |= inst.operands[2].reg;
10938 inst.instruction |= inst.operands[3].imm << 20;
10939}
b99bd4ef 10940
2d447fca
JM		 10941static void
10942do_iwmmxt_wmerge (void)
10943{
10944 inst.instruction |= inst.operands[0].reg << 12;
10945 inst.instruction |= inst.operands[1].reg << 16;
10946 inst.instruction |= inst.operands[2].reg;
10947 inst.instruction |= inst.operands[3].imm << 21;
10948}
10949
c19d1205
ZW		 10950static void
10951do_iwmmxt_wmov (void)
10952{
10953 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10954 inst.instruction |= inst.operands[0].reg << 12;
10955 inst.instruction |= inst.operands[1].reg << 16;
10956 inst.instruction |= inst.operands[1].reg;
10957}
b99bd4ef 10958
c19d1205
ZW		 10959static void
10960do_iwmmxt_wldstbh (void)
10961{
8f06b2d8 10962 int reloc;
c19d1205 10963 inst.instruction |= inst.operands[0].reg << 12;
8f06b2d8
PB		 10964 if (thumb_mode)
10965 reloc = BFD_RELOC_ARM_T32_CP_OFF_IMM_S2;
10966 else
10967 reloc = BFD_RELOC_ARM_CP_OFF_IMM_S2;
10968 encode_arm_cp_address (1, TRUE, FALSE, reloc);
b99bd4ef
NC		 10969}
10970
c19d1205
ZW		 10971static void
10972do_iwmmxt_wldstw (void)
10973{
10974 /* RIWR_RIWC clears .isreg for a control register. */
10975 if (!inst.operands[0].isreg)
10976 {
10977 constraint (inst.cond != COND_ALWAYS, BAD_COND);
10978 inst.instruction |= 0xf0000000;
10979 }
b99bd4ef 10980
c19d1205
ZW		 10981 inst.instruction |= inst.operands[0].reg << 12;
10982 encode_arm_cp_address (1, TRUE, TRUE, 0);
10983}
b99bd4ef
NC		 10984
10985static void
c19d1205 10986do_iwmmxt_wldstd (void)
b99bd4ef 10987{
c19d1205 10988 inst.instruction |= inst.operands[0].reg << 12;
2d447fca
JM		 10989 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2)
10990 && inst.operands[1].immisreg)
10991 {
10992 inst.instruction &= ~0x1a000ff;
eff0bc54 10993 inst.instruction |= (0xfU << 28);
2d447fca
JM		 10994 if (inst.operands[1].preind)
10995 inst.instruction |= PRE_INDEX;
10996 if (!inst.operands[1].negative)
10997 inst.instruction |= INDEX_UP;
10998 if (inst.operands[1].writeback)
10999 inst.instruction |= WRITE_BACK;
11000 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 11001 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
2d447fca
JM		 11002 inst.instruction |= inst.operands[1].imm;
11003 }
11004 else
11005 encode_arm_cp_address (1, TRUE, FALSE, 0);
c19d1205 11006}
b99bd4ef 11007
c19d1205
ZW		 11008static void
11009do_iwmmxt_wshufh (void)
11010{
11011 inst.instruction |= inst.operands[0].reg << 12;
11012 inst.instruction |= inst.operands[1].reg << 16;
11013 inst.instruction |= ((inst.operands[2].imm & 0xf0) << 16);
11014 inst.instruction |= (inst.operands[2].imm & 0x0f);
11015}
b99bd4ef 11016
c19d1205
ZW		 11017static void
11018do_iwmmxt_wzero (void)
11019{
11020 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11021 inst.instruction |= inst.operands[0].reg;
11022 inst.instruction |= inst.operands[0].reg << 12;
11023 inst.instruction |= inst.operands[0].reg << 16;
11024}
2d447fca
JM		 11025
11026static void
11027do_iwmmxt_wrwrwr_or_imm5 (void)
11028{
11029 if (inst.operands[2].isreg)
11030 do_rd_rn_rm ();
11031 else {
11032 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2),
11033 _("immediate operand requires iWMMXt2"));
11034 do_rd_rn ();
11035 if (inst.operands[2].imm == 0)
11036 {
11037 switch ((inst.instruction >> 20) & 0xf)
11038 {
11039 case 4:
11040 case 5:
11041 case 6:
5f4273c7 11042 case 7:
2d447fca
JM		 11043 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11044 inst.operands[2].imm = 16;
11045 inst.instruction = (inst.instruction & 0xff0fffff) | (0x7 << 20);
11046 break;
11047 case 8:
11048 case 9:
11049 case 10:
11050 case 11:
11051 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11052 inst.operands[2].imm = 32;
11053 inst.instruction = (inst.instruction & 0xff0fffff) | (0xb << 20);
11054 break;
11055 case 12:
11056 case 13:
11057 case 14:
11058 case 15:
11059 {
11060 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11061 unsigned long wrn;
11062 wrn = (inst.instruction >> 16) & 0xf;
11063 inst.instruction &= 0xff0fff0f;
11064 inst.instruction |= wrn;
11065 /* Bail out here; the instruction is now assembled. */
11066 return;
11067 }
11068 }
11069 }
11070 /* Map 32 -> 0, etc. */
11071 inst.operands[2].imm &= 0x1f;
eff0bc54 11072 inst.instruction |= (0xfU << 28) | ((inst.operands[2].imm & 0x10) << 4) | (inst.operands[2].imm & 0xf);
2d447fca
JM		 11073 }
11074}
c19d1205
ZW		 11075\f
11076/* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11077 operations first, then control, shift, and load/store. */
b99bd4ef 11078
c19d1205 11079/* Insns like "foo X,Y,Z". */
b99bd4ef 11080
c19d1205
ZW		 11081static void
11082do_mav_triple (void)
11083{
11084 inst.instruction |= inst.operands[0].reg << 16;
11085 inst.instruction |= inst.operands[1].reg;
11086 inst.instruction |= inst.operands[2].reg << 12;
11087}
b99bd4ef 11088
c19d1205
ZW		 11089/* Insns like "foo W,X,Y,Z".
11090 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
a737bd4d 11091
c19d1205
ZW		 11092static void
11093do_mav_quad (void)
11094{
11095 inst.instruction |= inst.operands[0].reg << 5;
11096 inst.instruction |= inst.operands[1].reg << 12;
11097 inst.instruction |= inst.operands[2].reg << 16;
11098 inst.instruction |= inst.operands[3].reg;
a737bd4d
NC		 11099}
11100
c19d1205
ZW		 11101/* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11102static void
11103do_mav_dspsc (void)
a737bd4d 11104{
c19d1205
ZW		 11105 inst.instruction |= inst.operands[1].reg << 12;
11106}
a737bd4d 11107
c19d1205
ZW		 11108/* Maverick shift immediate instructions.
11109 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11110 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
a737bd4d 11111
c19d1205
ZW		 11112static void
11113do_mav_shift (void)
11114{
11115 int imm = inst.operands[2].imm;
a737bd4d 11116
c19d1205
ZW		 11117 inst.instruction |= inst.operands[0].reg << 12;
11118 inst.instruction |= inst.operands[1].reg << 16;
a737bd4d 11119
c19d1205
ZW		 11120 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11121 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11122 Bit 4 should be 0. */
11123 imm = (imm & 0xf) | ((imm & 0x70) << 1);
a737bd4d 11124
c19d1205
ZW		 11125 inst.instruction |= imm;
11126}
11127\f
11128/* XScale instructions. Also sorted arithmetic before move. */
a737bd4d 11129
c19d1205
ZW		 11130/* Xscale multiply-accumulate (argument parse)
11131 MIAcc acc0,Rm,Rs
11132 MIAPHcc acc0,Rm,Rs
11133 MIAxycc acc0,Rm,Rs. */
a737bd4d 11134
c19d1205
ZW		 11135static void
11136do_xsc_mia (void)
11137{
11138 inst.instruction |= inst.operands[1].reg;
11139 inst.instruction |= inst.operands[2].reg << 12;
11140}
a737bd4d 11141
c19d1205 11142/* Xscale move-accumulator-register (argument parse)
a737bd4d 11143
c19d1205 11144 MARcc acc0,RdLo,RdHi. */
b99bd4ef 11145
c19d1205
ZW		 11146static void
11147do_xsc_mar (void)
11148{
11149 inst.instruction |= inst.operands[1].reg << 12;
11150 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 11151}
11152
c19d1205 11153/* Xscale move-register-accumulator (argument parse)
b99bd4ef 11154
c19d1205 11155 MRAcc RdLo,RdHi,acc0. */
b99bd4ef
NC		 11156
11157static void
c19d1205 11158do_xsc_mra (void)
b99bd4ef 11159{
c19d1205
ZW		 11160 constraint (inst.operands[0].reg == inst.operands[1].reg, BAD_OVERLAP);
11161 inst.instruction |= inst.operands[0].reg << 12;
11162 inst.instruction |= inst.operands[1].reg << 16;
11163}
11164\f
11165/* Encoding functions relevant only to Thumb. */
b99bd4ef 11166
c19d1205
ZW		 11167/* inst.operands[i] is a shifted-register operand; encode
11168 it into inst.instruction in the format used by Thumb32. */
11169
11170static void
11171encode_thumb32_shifted_operand (int i)
11172{
e2b0ab59 11173 unsigned int value = inst.relocs[0].exp.X_add_number;
c19d1205 11174 unsigned int shift = inst.operands[i].shift_kind;
b99bd4ef 11175
9c3c69f2
PB		 11176 constraint (inst.operands[i].immisreg,
11177 _("shift by register not allowed in thumb mode"));
c19d1205
ZW		 11178 inst.instruction |= inst.operands[i].reg;
11179 if (shift == SHIFT_RRX)
11180 inst.instruction |= SHIFT_ROR << 4;
11181 else
b99bd4ef 11182 {
e2b0ab59 11183 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW		 11184 _("expression too complex"));
11185
11186 constraint (value > 32
11187 || (value == 32 && (shift == SHIFT_LSL
11188 || shift == SHIFT_ROR)),
11189 _("shift expression is too large"));
11190
11191 if (value == 0)
11192 shift = SHIFT_LSL;
11193 else if (value == 32)
11194 value = 0;
11195
11196 inst.instruction |= shift << 4;
11197 inst.instruction |= (value & 0x1c) << 10;
11198 inst.instruction |= (value & 0x03) << 6;
b99bd4ef 11199 }
c19d1205 11200}
b99bd4ef 11201
b99bd4ef 11202
c19d1205
ZW		 11203/* inst.operands[i] was set up by parse_address. Encode it into a
11204 Thumb32 format load or store instruction. Reject forms that cannot
11205 be used with such instructions. If is_t is true, reject forms that
11206 cannot be used with a T instruction; if is_d is true, reject forms
5be8be5d
DG		 11207 that cannot be used with a D instruction. If it is a store insn,
11208 reject PC in Rn. */
b99bd4ef 11209
c19d1205
ZW		 11210static void
11211encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d)
11212{
5be8be5d 11213 const bfd_boolean is_pc = (inst.operands[i].reg == REG_PC);
c19d1205
ZW		 11214
11215 constraint (!inst.operands[i].isreg,
53365c0d 11216 _("Instruction does not support =N addresses"));
b99bd4ef 11217
c19d1205
ZW		 11218 inst.instruction |= inst.operands[i].reg << 16;
11219 if (inst.operands[i].immisreg)
b99bd4ef 11220 {
5be8be5d 11221 constraint (is_pc, BAD_PC_ADDRESSING);
c19d1205
ZW		 11222 constraint (is_t || is_d, _("cannot use register index with this instruction"));
11223 constraint (inst.operands[i].negative,
11224 _("Thumb does not support negative register indexing"));
11225 constraint (inst.operands[i].postind,
11226 _("Thumb does not support register post-indexing"));
11227 constraint (inst.operands[i].writeback,
11228 _("Thumb does not support register indexing with writeback"));
11229 constraint (inst.operands[i].shifted && inst.operands[i].shift_kind != SHIFT_LSL,
11230 _("Thumb supports only LSL in shifted register indexing"));
b99bd4ef 11231
f40d1643 11232 inst.instruction |= inst.operands[i].imm;
c19d1205 11233 if (inst.operands[i].shifted)
b99bd4ef 11234 {
e2b0ab59 11235 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 11236 _("expression too complex"));
e2b0ab59
AV		 11237 constraint (inst.relocs[0].exp.X_add_number < 0
11238 || inst.relocs[0].exp.X_add_number > 3,
c19d1205 11239 _("shift out of range"));
e2b0ab59 11240 inst.instruction |= inst.relocs[0].exp.X_add_number << 4;
c19d1205 11241 }
e2b0ab59 11242 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205
ZW		 11243 }
11244 else if (inst.operands[i].preind)
11245 {
5be8be5d 11246 constraint (is_pc && inst.operands[i].writeback, BAD_PC_WRITEBACK);
f40d1643 11247 constraint (is_t && inst.operands[i].writeback,
c19d1205 11248 _("cannot use writeback with this instruction"));
4755303e
WN		 11249 constraint (is_pc && ((inst.instruction & THUMB2_LOAD_BIT) == 0),
11250 BAD_PC_ADDRESSING);
c19d1205
ZW		 11251
11252 if (is_d)
11253 {
11254 inst.instruction |= 0x01000000;
11255 if (inst.operands[i].writeback)
11256 inst.instruction |= 0x00200000;
b99bd4ef 11257 }
c19d1205 11258 else
b99bd4ef 11259 {
c19d1205
ZW		 11260 inst.instruction |= 0x00000c00;
11261 if (inst.operands[i].writeback)
11262 inst.instruction |= 0x00000100;
b99bd4ef 11263 }
e2b0ab59 11264 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
b99bd4ef 11265 }
c19d1205 11266 else if (inst.operands[i].postind)
b99bd4ef 11267 {
9c2799c2 11268 gas_assert (inst.operands[i].writeback);
c19d1205
ZW		 11269 constraint (is_pc, _("cannot use post-indexing with PC-relative addressing"));
11270 constraint (is_t, _("cannot use post-indexing with this instruction"));
11271
11272 if (is_d)
11273 inst.instruction |= 0x00200000;
11274 else
11275 inst.instruction |= 0x00000900;
e2b0ab59 11276 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_IMM;
c19d1205
ZW		 11277 }
11278 else /* unindexed - only for coprocessor */
11279 inst.error = _("instruction does not accept unindexed addressing");
11280}
11281
e39c1607 11282/* Table of Thumb instructions which exist in 16- and/or 32-bit
c19d1205
ZW		 11283 encodings (the latter only in post-V6T2 cores). The index is the
11284 value used in the insns table below. When there is more than one
11285 possible 16-bit encoding for the instruction, this table always
0110f2b8
PB		 11286 holds variant (1).
11287 Also contains several pseudo-instructions used during relaxation. */
c19d1205 11288#define T16_32_TAB \
21d799b5
NC		 11289 X(_adc, 4140, eb400000), \
11290 X(_adcs, 4140, eb500000), \
11291 X(_add, 1c00, eb000000), \
11292 X(_adds, 1c00, eb100000), \
11293 X(_addi, 0000, f1000000), \
11294 X(_addis, 0000, f1100000), \
11295 X(_add_pc,000f, f20f0000), \
11296 X(_add_sp,000d, f10d0000), \
11297 X(_adr, 000f, f20f0000), \
11298 X(_and, 4000, ea000000), \
11299 X(_ands, 4000, ea100000), \
11300 X(_asr, 1000, fa40f000), \
11301 X(_asrs, 1000, fa50f000), \
11302 X(_b, e000, f000b000), \
11303 X(_bcond, d000, f0008000), \
4389b29a 11304 X(_bf, 0000, f040e001), \
f6b2b12d 11305 X(_bfcsel,0000, f000e001), \
f1c7f421 11306 X(_bfx, 0000, f060e001), \
65d1bc05 11307 X(_bfl, 0000, f000c001), \
f1c7f421 11308 X(_bflx, 0000, f070e001), \
21d799b5
NC		 11309 X(_bic, 4380, ea200000), \
11310 X(_bics, 4380, ea300000), \
e39c1607
SD		 11311 X(_cinc, 0000, ea509000), \
11312 X(_cinv, 0000, ea50a000), \
21d799b5
NC		 11313 X(_cmn, 42c0, eb100f00), \
11314 X(_cmp, 2800, ebb00f00), \
e39c1607 11315 X(_cneg, 0000, ea50b000), \
21d799b5
NC		 11316 X(_cpsie, b660, f3af8400), \
11317 X(_cpsid, b670, f3af8600), \
11318 X(_cpy, 4600, ea4f0000), \
e39c1607
SD		 11319 X(_csel, 0000, ea508000), \
11320 X(_cset, 0000, ea5f900f), \
11321 X(_csetm, 0000, ea5fa00f), \
11322 X(_csinc, 0000, ea509000), \
11323 X(_csinv, 0000, ea50a000), \
11324 X(_csneg, 0000, ea50b000), \
21d799b5 11325 X(_dec_sp,80dd, f1ad0d00), \
60f993ce 11326 X(_dls, 0000, f040e001), \
1f6234a3 11327 X(_dlstp, 0000, f000e001), \
21d799b5
NC		 11328 X(_eor, 4040, ea800000), \
11329 X(_eors, 4040, ea900000), \
11330 X(_inc_sp,00dd, f10d0d00), \
1f6234a3 11331 X(_lctp, 0000, f00fe001), \
21d799b5
NC		 11332 X(_ldmia, c800, e8900000), \
11333 X(_ldr, 6800, f8500000), \
11334 X(_ldrb, 7800, f8100000), \
11335 X(_ldrh, 8800, f8300000), \
11336 X(_ldrsb, 5600, f9100000), \
11337 X(_ldrsh, 5e00, f9300000), \
11338 X(_ldr_pc,4800, f85f0000), \
11339 X(_ldr_pc2,4800, f85f0000), \
11340 X(_ldr_sp,9800, f85d0000), \
60f993ce 11341 X(_le, 0000, f00fc001), \
1f6234a3 11342 X(_letp, 0000, f01fc001), \
21d799b5
NC		 11343 X(_lsl, 0000, fa00f000), \
11344 X(_lsls, 0000, fa10f000), \
11345 X(_lsr, 0800, fa20f000), \
11346 X(_lsrs, 0800, fa30f000), \
11347 X(_mov, 2000, ea4f0000), \
11348 X(_movs, 2000, ea5f0000), \
11349 X(_mul, 4340, fb00f000), \
11350 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11351 X(_mvn, 43c0, ea6f0000), \
11352 X(_mvns, 43c0, ea7f0000), \
11353 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11354 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11355 X(_orr, 4300, ea400000), \
11356 X(_orrs, 4300, ea500000), \
11357 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11358 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11359 X(_rev, ba00, fa90f080), \
11360 X(_rev16, ba40, fa90f090), \
11361 X(_revsh, bac0, fa90f0b0), \
11362 X(_ror, 41c0, fa60f000), \
11363 X(_rors, 41c0, fa70f000), \
11364 X(_sbc, 4180, eb600000), \
11365 X(_sbcs, 4180, eb700000), \
11366 X(_stmia, c000, e8800000), \
11367 X(_str, 6000, f8400000), \
11368 X(_strb, 7000, f8000000), \
11369 X(_strh, 8000, f8200000), \
11370 X(_str_sp,9000, f84d0000), \
11371 X(_sub, 1e00, eba00000), \
11372 X(_subs, 1e00, ebb00000), \
11373 X(_subi, 8000, f1a00000), \
11374 X(_subis, 8000, f1b00000), \
11375 X(_sxtb, b240, fa4ff080), \
11376 X(_sxth, b200, fa0ff080), \
11377 X(_tst, 4200, ea100f00), \
11378 X(_uxtb, b2c0, fa5ff080), \
11379 X(_uxth, b280, fa1ff080), \
11380 X(_nop, bf00, f3af8000), \
11381 X(_yield, bf10, f3af8001), \
11382 X(_wfe, bf20, f3af8002), \
11383 X(_wfi, bf30, f3af8003), \
60f993ce 11384 X(_wls, 0000, f040c001), \
1f6234a3 11385 X(_wlstp, 0000, f000c001), \
53c4b28b 11386 X(_sev, bf40, f3af8004), \
74db7efb
NC		 11387 X(_sevl, bf50, f3af8005), \
11388 X(_udf, de00, f7f0a000)
c19d1205
ZW		 11389
11390/* To catch errors in encoding functions, the codes are all offset by
11391 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11392 as 16-bit instructions. */
21d799b5 11393#define X(a,b,c) T_MNEM##a
c19d1205
ZW		 11394enum t16_32_codes { T16_32_OFFSET = 0xF7FF, T16_32_TAB };
11395#undef X
11396
11397#define X(a,b,c) 0x##b
11398static const unsigned short thumb_op16[] = { T16_32_TAB };
11399#define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11400#undef X
11401
11402#define X(a,b,c) 0x##c
11403static const unsigned int thumb_op32[] = { T16_32_TAB };
c921be7d
NC		 11404#define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11405#define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
c19d1205
ZW		 11406#undef X
11407#undef T16_32_TAB
11408
11409/* Thumb instruction encoders, in alphabetical order. */
11410
92e90b6e 11411/* ADDW or SUBW. */
c921be7d 11412
92e90b6e
PB		 11413static void
11414do_t_add_sub_w (void)
11415{
11416 int Rd, Rn;
11417
11418 Rd = inst.operands[0].reg;
11419 Rn = inst.operands[1].reg;
11420
539d4391
NC		 11421 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11422 is the SP-{plus,minus}-immediate form of the instruction. */
11423 if (Rn == REG_SP)
11424 constraint (Rd == REG_PC, BAD_PC);
11425 else
11426 reject_bad_reg (Rd);
fdfde340 11427
92e90b6e 11428 inst.instruction |= (Rn << 16) | (Rd << 8);
e2b0ab59 11429 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
92e90b6e
PB		 11430}
11431
c19d1205 11432/* Parse an add or subtract instruction. We get here with inst.instruction
33eaf5de 11433 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
c19d1205
ZW		 11434
11435static void
11436do_t_add_sub (void)
11437{
11438 int Rd, Rs, Rn;
11439
11440 Rd = inst.operands[0].reg;
11441 Rs = (inst.operands[1].present
11442 ? inst.operands[1].reg /* Rd, Rs, foo */
11443 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11444
e07e6e58 11445 if (Rd == REG_PC)
5ee91343 11446 set_pred_insn_type_last ();
e07e6e58 11447
c19d1205
ZW		 11448 if (unified_syntax)
11449 {
0110f2b8
PB		 11450 bfd_boolean flags;
11451 bfd_boolean narrow;
11452 int opcode;
11453
11454 flags = (inst.instruction == T_MNEM_adds
11455 || inst.instruction == T_MNEM_subs);
11456 if (flags)
5ee91343 11457 narrow = !in_pred_block ();
0110f2b8 11458 else
5ee91343 11459 narrow = in_pred_block ();
c19d1205 11460 if (!inst.operands[2].isreg)
b99bd4ef 11461 {
16805f35
PB		 11462 int add;
11463
5c8ed6a4
JW		 11464 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11465 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340 11466
16805f35
PB		 11467 add = (inst.instruction == T_MNEM_add
11468 || inst.instruction == T_MNEM_adds);
0110f2b8
PB		 11469 opcode = 0;
11470 if (inst.size_req != 4)
11471 {
0110f2b8 11472 /* Attempt to use a narrow opcode, with relaxation if
477330fc 11473 appropriate. */
0110f2b8
PB		 11474 if (Rd == REG_SP && Rs == REG_SP && !flags)
11475 opcode = add ? T_MNEM_inc_sp : T_MNEM_dec_sp;
11476 else if (Rd <= 7 && Rs == REG_SP && add && !flags)
11477 opcode = T_MNEM_add_sp;
11478 else if (Rd <= 7 && Rs == REG_PC && add && !flags)
11479 opcode = T_MNEM_add_pc;
11480 else if (Rd <= 7 && Rs <= 7 && narrow)
11481 {
11482 if (flags)
11483 opcode = add ? T_MNEM_addis : T_MNEM_subis;
11484 else
11485 opcode = add ? T_MNEM_addi : T_MNEM_subi;
11486 }
11487 if (opcode)
11488 {
11489 inst.instruction = THUMB_OP16(opcode);
11490 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59
AV		 11491 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11492 || (inst.relocs[0].type
11493 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC))
a9f02af8
MG		 11494 {
11495 if (inst.size_req == 2)
e2b0ab59 11496 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
a9f02af8
MG		 11497 else
11498 inst.relax = opcode;
11499 }
0110f2b8
PB		 11500 }
11501 else
11502 constraint (inst.size_req == 2, BAD_HIREG);
11503 }
11504 if (inst.size_req == 4
11505 || (inst.size_req != 2 && !opcode))
11506 {
e2b0ab59
AV		 11507 constraint ((inst.relocs[0].type
11508 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
11509 && (inst.relocs[0].type
11510 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8 11511 THUMB1_RELOC_ONLY);
efd81785
PB		 11512 if (Rd == REG_PC)
11513 {
fdfde340 11514 constraint (add, BAD_PC);
efd81785
PB		 11515 constraint (Rs != REG_LR || inst.instruction != T_MNEM_subs,
11516 _("only SUBS PC, LR, #const allowed"));
e2b0ab59 11517 constraint (inst.relocs[0].exp.X_op != O_constant,
efd81785 11518 _("expression too complex"));
e2b0ab59
AV		 11519 constraint (inst.relocs[0].exp.X_add_number < 0
11520 || inst.relocs[0].exp.X_add_number > 0xff,
efd81785
PB		 11521 _("immediate value out of range"));
11522 inst.instruction = T2_SUBS_PC_LR
e2b0ab59
AV		 11523 | inst.relocs[0].exp.X_add_number;
11524 inst.relocs[0].type = BFD_RELOC_UNUSED;
efd81785
PB		 11525 return;
11526 }
11527 else if (Rs == REG_PC)
16805f35
PB		 11528 {
11529 /* Always use addw/subw. */
11530 inst.instruction = add ? 0xf20f0000 : 0xf2af0000;
e2b0ab59 11531 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMM12;
16805f35
PB		 11532 }
11533 else
11534 {
11535 inst.instruction = THUMB_OP32 (inst.instruction);
11536 inst.instruction = (inst.instruction & 0xe1ffffff)
11537 | 0x10000000;
11538 if (flags)
e2b0ab59 11539 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
16805f35 11540 else
e2b0ab59 11541 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_IMM;
16805f35 11542 }
dc4503c6
PB		 11543 inst.instruction |= Rd << 8;
11544 inst.instruction |= Rs << 16;
0110f2b8 11545 }
b99bd4ef 11546 }
c19d1205
ZW		 11547 else
11548 {
e2b0ab59 11549 unsigned int value = inst.relocs[0].exp.X_add_number;
5f4cb198
NC		 11550 unsigned int shift = inst.operands[2].shift_kind;
11551
c19d1205
ZW		 11552 Rn = inst.operands[2].reg;
11553 /* See if we can do this with a 16-bit instruction. */
11554 if (!inst.operands[2].shifted && inst.size_req != 4)
11555 {
e27ec89e
PB		 11556 if (Rd > 7 || Rs > 7 || Rn > 7)
11557 narrow = FALSE;
11558
11559 if (narrow)
c19d1205 11560 {
e27ec89e
PB		 11561 inst.instruction = ((inst.instruction == T_MNEM_adds
11562 || inst.instruction == T_MNEM_add)
c19d1205
ZW		 11563 ? T_OPCODE_ADD_R3
11564 : T_OPCODE_SUB_R3);
11565 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
11566 return;
11567 }
b99bd4ef 11568
7e806470 11569 if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
c19d1205 11570 {
7e806470
PB		 11571 /* Thumb-1 cores (except v6-M) require at least one high
11572 register in a narrow non flag setting add. */
11573 if (Rd > 7 || Rn > 7
11574 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
11575 || ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
c19d1205 11576 {
7e806470
PB		 11577 if (Rd == Rn)
11578 {
11579 Rn = Rs;
11580 Rs = Rd;
11581 }
c19d1205
ZW		 11582 inst.instruction = T_OPCODE_ADD_HI;
11583 inst.instruction |= (Rd & 8) << 4;
11584 inst.instruction |= (Rd & 7);
11585 inst.instruction |= Rn << 3;
11586 return;
11587 }
c19d1205
ZW		 11588 }
11589 }
c921be7d 11590
fdfde340 11591 constraint (Rd == REG_PC, BAD_PC);
5c8ed6a4
JW		 11592 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
11593 constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
fdfde340
JM		 11594 constraint (Rs == REG_PC, BAD_PC);
11595 reject_bad_reg (Rn);
11596
c19d1205
ZW		 11597 /* If we get here, it can't be done in 16 bits. */
11598 constraint (inst.operands[2].shifted && inst.operands[2].immisreg,
11599 _("shift must be constant"));
11600 inst.instruction = THUMB_OP32 (inst.instruction);
11601 inst.instruction |= Rd << 8;
11602 inst.instruction |= Rs << 16;
5f4cb198
NC		 11603 constraint (Rd == REG_SP && Rs == REG_SP && value > 3,
11604 _("shift value over 3 not allowed in thumb mode"));
11605 constraint (Rd == REG_SP && Rs == REG_SP && shift != SHIFT_LSL,
11606 _("only LSL shift allowed in thumb mode"));
c19d1205
ZW		 11607 encode_thumb32_shifted_operand (2);
11608 }
11609 }
11610 else
11611 {
11612 constraint (inst.instruction == T_MNEM_adds
11613 || inst.instruction == T_MNEM_subs,
11614 BAD_THUMB32);
b99bd4ef 11615
c19d1205 11616 if (!inst.operands[2].isreg) /* Rd, Rs, #imm */
b99bd4ef 11617 {
c19d1205
ZW		 11618 constraint ((Rd > 7 && (Rd != REG_SP || Rs != REG_SP))
11619 || (Rs > 7 && Rs != REG_SP && Rs != REG_PC),
11620 BAD_HIREG);
11621
11622 inst.instruction = (inst.instruction == T_MNEM_add
11623 ? 0x0000 : 0x8000);
11624 inst.instruction |= (Rd << 4) | Rs;
e2b0ab59 11625 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
b99bd4ef
NC		 11626 return;
11627 }
11628
c19d1205
ZW		 11629 Rn = inst.operands[2].reg;
11630 constraint (inst.operands[2].shifted, _("unshifted register required"));
b99bd4ef 11631
c19d1205
ZW		 11632 /* We now have Rd, Rs, and Rn set to registers. */
11633 if (Rd > 7 || Rs > 7 || Rn > 7)
b99bd4ef 11634 {
c19d1205
ZW		 11635 /* Can't do this for SUB. */
11636 constraint (inst.instruction == T_MNEM_sub, BAD_HIREG);
11637 inst.instruction = T_OPCODE_ADD_HI;
11638 inst.instruction |= (Rd & 8) << 4;
11639 inst.instruction |= (Rd & 7);
11640 if (Rs == Rd)
11641 inst.instruction |= Rn << 3;
11642 else if (Rn == Rd)
11643 inst.instruction |= Rs << 3;
11644 else
11645 constraint (1, _("dest must overlap one source register"));
11646 }
11647 else
11648 {
11649 inst.instruction = (inst.instruction == T_MNEM_add
11650 ? T_OPCODE_ADD_R3 : T_OPCODE_SUB_R3);
11651 inst.instruction |= Rd | (Rs << 3) | (Rn << 6);
b99bd4ef 11652 }
b99bd4ef 11653 }
b99bd4ef
NC		 11654}
11655
c19d1205
ZW		 11656static void
11657do_t_adr (void)
11658{
fdfde340
JM		 11659 unsigned Rd;
11660
11661 Rd = inst.operands[0].reg;
11662 reject_bad_reg (Rd);
11663
11664 if (unified_syntax && inst.size_req == 0 && Rd <= 7)
0110f2b8
PB		 11665 {
11666 /* Defer to section relaxation. */
11667 inst.relax = inst.instruction;
11668 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 11669 inst.instruction |= Rd << 4;
0110f2b8
PB		 11670 }
11671 else if (unified_syntax && inst.size_req != 2)
e9f89963 11672 {
0110f2b8 11673 /* Generate a 32-bit opcode. */
e9f89963 11674 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 11675 inst.instruction |= Rd << 8;
e2b0ab59
AV		 11676 inst.relocs[0].type = BFD_RELOC_ARM_T32_ADD_PC12;
11677 inst.relocs[0].pc_rel = 1;
e9f89963
PB		 11678 }
11679 else
11680 {
0110f2b8 11681 /* Generate a 16-bit opcode. */
e9f89963 11682 inst.instruction = THUMB_OP16 (inst.instruction);
e2b0ab59
AV		 11683 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_ADD;
11684 inst.relocs[0].exp.X_add_number -= 4; /* PC relative adjust. */
11685 inst.relocs[0].pc_rel = 1;
fdfde340 11686 inst.instruction |= Rd << 4;
e9f89963 11687 }
52a86f84 11688
e2b0ab59
AV		 11689 if (inst.relocs[0].exp.X_op == O_symbol
11690 && inst.relocs[0].exp.X_add_symbol != NULL
11691 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
11692 && THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
11693 inst.relocs[0].exp.X_add_number += 1;
c19d1205 11694}
b99bd4ef 11695
c19d1205
ZW		 11696/* Arithmetic instructions for which there is just one 16-bit
11697 instruction encoding, and it allows only two low registers.
11698 For maximal compatibility with ARM syntax, we allow three register
11699 operands even when Thumb-32 instructions are not available, as long
11700 as the first two are identical. For instance, both "sbc r0,r1" and
11701 "sbc r0,r0,r1" are allowed. */
b99bd4ef 11702static void
c19d1205 11703do_t_arit3 (void)
b99bd4ef 11704{
c19d1205 11705 int Rd, Rs, Rn;
b99bd4ef 11706
c19d1205
ZW		 11707 Rd = inst.operands[0].reg;
11708 Rs = (inst.operands[1].present
11709 ? inst.operands[1].reg /* Rd, Rs, foo */
11710 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11711 Rn = inst.operands[2].reg;
b99bd4ef 11712
fdfde340
JM		 11713 reject_bad_reg (Rd);
11714 reject_bad_reg (Rs);
11715 if (inst.operands[2].isreg)
11716 reject_bad_reg (Rn);
11717
c19d1205 11718 if (unified_syntax)
b99bd4ef 11719 {
c19d1205
ZW		 11720 if (!inst.operands[2].isreg)
11721 {
11722 /* For an immediate, we always generate a 32-bit opcode;
11723 section relaxation will shrink it later if possible. */
11724 inst.instruction = THUMB_OP32 (inst.instruction);
11725 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11726 inst.instruction |= Rd << 8;
11727 inst.instruction |= Rs << 16;
e2b0ab59 11728 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
c19d1205
ZW		 11729 }
11730 else
11731 {
e27ec89e
PB		 11732 bfd_boolean narrow;
11733
c19d1205 11734 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11735 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11736 narrow = !in_pred_block ();
e27ec89e 11737 else
5ee91343 11738 narrow = in_pred_block ();
e27ec89e
PB		 11739
11740 if (Rd > 7 || Rn > 7 || Rs > 7)
11741 narrow = FALSE;
11742 if (inst.operands[2].shifted)
11743 narrow = FALSE;
11744 if (inst.size_req == 4)
11745 narrow = FALSE;
11746
11747 if (narrow
c19d1205
ZW		 11748 && Rd == Rs)
11749 {
11750 inst.instruction = THUMB_OP16 (inst.instruction);
11751 inst.instruction |= Rd;
11752 inst.instruction |= Rn << 3;
11753 return;
11754 }
b99bd4ef 11755
c19d1205
ZW		 11756 /* If we get here, it can't be done in 16 bits. */
11757 constraint (inst.operands[2].shifted
11758 && inst.operands[2].immisreg,
11759 _("shift must be constant"));
11760 inst.instruction = THUMB_OP32 (inst.instruction);
11761 inst.instruction |= Rd << 8;
11762 inst.instruction |= Rs << 16;
11763 encode_thumb32_shifted_operand (2);
11764 }
a737bd4d 11765 }
c19d1205 11766 else
b99bd4ef 11767 {
c19d1205
ZW		 11768 /* On its face this is a lie - the instruction does set the
11769 flags. However, the only supported mnemonic in this mode
11770 says it doesn't. */
11771 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11772
c19d1205
ZW		 11773 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11774 _("unshifted register required"));
11775 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11776 constraint (Rd != Rs,
11777 _("dest and source1 must be the same register"));
a737bd4d 11778
c19d1205
ZW		 11779 inst.instruction = THUMB_OP16 (inst.instruction);
11780 inst.instruction |= Rd;
11781 inst.instruction |= Rn << 3;
b99bd4ef 11782 }
a737bd4d 11783}
b99bd4ef 11784
c19d1205
ZW		 11785/* Similarly, but for instructions where the arithmetic operation is
11786 commutative, so we can allow either of them to be different from
11787 the destination operand in a 16-bit instruction. For instance, all
11788 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11789 accepted. */
11790static void
11791do_t_arit3c (void)
a737bd4d 11792{
c19d1205 11793 int Rd, Rs, Rn;
b99bd4ef 11794
c19d1205
ZW		 11795 Rd = inst.operands[0].reg;
11796 Rs = (inst.operands[1].present
11797 ? inst.operands[1].reg /* Rd, Rs, foo */
11798 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
11799 Rn = inst.operands[2].reg;
c921be7d 11800
fdfde340
JM		 11801 reject_bad_reg (Rd);
11802 reject_bad_reg (Rs);
11803 if (inst.operands[2].isreg)
11804 reject_bad_reg (Rn);
a737bd4d 11805
c19d1205 11806 if (unified_syntax)
a737bd4d 11807 {
c19d1205 11808 if (!inst.operands[2].isreg)
b99bd4ef 11809 {
c19d1205
ZW		 11810 /* For an immediate, we always generate a 32-bit opcode;
11811 section relaxation will shrink it later if possible. */
11812 inst.instruction = THUMB_OP32 (inst.instruction);
11813 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
11814 inst.instruction |= Rd << 8;
11815 inst.instruction |= Rs << 16;
e2b0ab59 11816 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 11817 }
c19d1205 11818 else
a737bd4d 11819 {
e27ec89e
PB		 11820 bfd_boolean narrow;
11821
c19d1205 11822 /* See if we can do this with a 16-bit instruction. */
e27ec89e 11823 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 11824 narrow = !in_pred_block ();
e27ec89e 11825 else
5ee91343 11826 narrow = in_pred_block ();
e27ec89e
PB		 11827
11828 if (Rd > 7 || Rn > 7 || Rs > 7)
11829 narrow = FALSE;
11830 if (inst.operands[2].shifted)
11831 narrow = FALSE;
11832 if (inst.size_req == 4)
11833 narrow = FALSE;
11834
11835 if (narrow)
a737bd4d 11836 {
c19d1205 11837 if (Rd == Rs)
a737bd4d 11838 {
c19d1205
ZW		 11839 inst.instruction = THUMB_OP16 (inst.instruction);
11840 inst.instruction |= Rd;
11841 inst.instruction |= Rn << 3;
11842 return;
a737bd4d 11843 }
c19d1205 11844 if (Rd == Rn)
a737bd4d 11845 {
c19d1205
ZW		 11846 inst.instruction = THUMB_OP16 (inst.instruction);
11847 inst.instruction |= Rd;
11848 inst.instruction |= Rs << 3;
11849 return;
a737bd4d
NC		 11850 }
11851 }
c19d1205
ZW		 11852
11853 /* If we get here, it can't be done in 16 bits. */
11854 constraint (inst.operands[2].shifted
11855 && inst.operands[2].immisreg,
11856 _("shift must be constant"));
11857 inst.instruction = THUMB_OP32 (inst.instruction);
11858 inst.instruction |= Rd << 8;
11859 inst.instruction |= Rs << 16;
11860 encode_thumb32_shifted_operand (2);
a737bd4d 11861 }
b99bd4ef 11862 }
c19d1205
ZW		 11863 else
11864 {
11865 /* On its face this is a lie - the instruction does set the
11866 flags. However, the only supported mnemonic in this mode
11867 says it doesn't. */
11868 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
a737bd4d 11869
c19d1205
ZW		 11870 constraint (!inst.operands[2].isreg || inst.operands[2].shifted,
11871 _("unshifted register required"));
11872 constraint (Rd > 7 || Rs > 7 || Rn > 7, BAD_HIREG);
11873
11874 inst.instruction = THUMB_OP16 (inst.instruction);
11875 inst.instruction |= Rd;
11876
11877 if (Rd == Rs)
11878 inst.instruction |= Rn << 3;
11879 else if (Rd == Rn)
11880 inst.instruction |= Rs << 3;
11881 else
11882 constraint (1, _("dest must overlap one source register"));
11883 }
a737bd4d
NC		 11884}
11885
c19d1205
ZW		 11886static void
11887do_t_bfc (void)
a737bd4d 11888{
fdfde340 11889 unsigned Rd;
c19d1205
ZW		 11890 unsigned int msb = inst.operands[1].imm + inst.operands[2].imm;
11891 constraint (msb > 32, _("bit-field extends past end of register"));
11892 /* The instruction encoding stores the LSB and MSB,
11893 not the LSB and width. */
fdfde340
JM		 11894 Rd = inst.operands[0].reg;
11895 reject_bad_reg (Rd);
11896 inst.instruction |= Rd << 8;
c19d1205
ZW		 11897 inst.instruction |= (inst.operands[1].imm & 0x1c) << 10;
11898 inst.instruction |= (inst.operands[1].imm & 0x03) << 6;
11899 inst.instruction |= msb - 1;
b99bd4ef
NC		 11900}
11901
c19d1205
ZW		 11902static void
11903do_t_bfi (void)
b99bd4ef 11904{
fdfde340 11905 int Rd, Rn;
c19d1205 11906 unsigned int msb;
b99bd4ef 11907
fdfde340
JM		 11908 Rd = inst.operands[0].reg;
11909 reject_bad_reg (Rd);
11910
c19d1205
ZW		 11911 /* #0 in second position is alternative syntax for bfc, which is
11912 the same instruction but with REG_PC in the Rm field. */
11913 if (!inst.operands[1].isreg)
fdfde340
JM		 11914 Rn = REG_PC;
11915 else
11916 {
11917 Rn = inst.operands[1].reg;
11918 reject_bad_reg (Rn);
11919 }
b99bd4ef 11920
c19d1205
ZW		 11921 msb = inst.operands[2].imm + inst.operands[3].imm;
11922 constraint (msb > 32, _("bit-field extends past end of register"));
11923 /* The instruction encoding stores the LSB and MSB,
11924 not the LSB and width. */
fdfde340
JM		 11925 inst.instruction |= Rd << 8;
11926 inst.instruction |= Rn << 16;
c19d1205
ZW		 11927 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11928 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11929 inst.instruction |= msb - 1;
b99bd4ef
NC		 11930}
11931
c19d1205
ZW		 11932static void
11933do_t_bfx (void)
b99bd4ef 11934{
fdfde340
JM		 11935 unsigned Rd, Rn;
11936
11937 Rd = inst.operands[0].reg;
11938 Rn = inst.operands[1].reg;
11939
11940 reject_bad_reg (Rd);
11941 reject_bad_reg (Rn);
11942
c19d1205
ZW		 11943 constraint (inst.operands[2].imm + inst.operands[3].imm > 32,
11944 _("bit-field extends past end of register"));
fdfde340
JM		 11945 inst.instruction |= Rd << 8;
11946 inst.instruction |= Rn << 16;
c19d1205
ZW		 11947 inst.instruction |= (inst.operands[2].imm & 0x1c) << 10;
11948 inst.instruction |= (inst.operands[2].imm & 0x03) << 6;
11949 inst.instruction |= inst.operands[3].imm - 1;
11950}
b99bd4ef 11951
c19d1205
ZW		 11952/* ARM V5 Thumb BLX (argument parse)
11953 BLX <target_addr> which is BLX(1)
11954 BLX <Rm> which is BLX(2)
11955 Unfortunately, there are two different opcodes for this mnemonic.
11956 So, the insns[].value is not used, and the code here zaps values
11957 into inst.instruction.
b99bd4ef 11958
c19d1205
ZW		 11959 ??? How to take advantage of the additional two bits of displacement
11960 available in Thumb32 mode? Need new relocation? */
b99bd4ef 11961
c19d1205
ZW		 11962static void
11963do_t_blx (void)
11964{
5ee91343 11965 set_pred_insn_type_last ();
e07e6e58 11966
c19d1205 11967 if (inst.operands[0].isreg)
fdfde340
JM		 11968 {
11969 constraint (inst.operands[0].reg == REG_PC, BAD_PC);
11970 /* We have a register, so this is BLX(2). */
11971 inst.instruction |= inst.operands[0].reg << 3;
11972 }
b99bd4ef
NC		 11973 else
11974 {
c19d1205 11975 /* No register. This must be BLX(1). */
2fc8bdac 11976 inst.instruction = 0xf000e800;
0855e32b 11977 encode_branch (BFD_RELOC_THUMB_PCREL_BLX);
b99bd4ef
NC		 11978 }
11979}
11980
c19d1205
ZW		 11981static void
11982do_t_branch (void)
b99bd4ef 11983{
0110f2b8 11984 int opcode;
dfa9f0d5 11985 int cond;
2fe88214 11986 bfd_reloc_code_real_type reloc;
dfa9f0d5 11987
e07e6e58 11988 cond = inst.cond;
5ee91343 11989 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN);
e07e6e58 11990
5ee91343 11991 if (in_pred_block ())
dfa9f0d5
PB		 11992 {
11993 /* Conditional branches inside IT blocks are encoded as unconditional
477330fc 11994 branches. */
dfa9f0d5 11995 cond = COND_ALWAYS;
dfa9f0d5
PB		 11996 }
11997 else
11998 cond = inst.cond;
11999
12000 if (cond != COND_ALWAYS)
0110f2b8
PB		 12001 opcode = T_MNEM_bcond;
12002 else
12003 opcode = inst.instruction;
12004
12d6b0b7
RS		 12005 if (unified_syntax
12006 && (inst.size_req == 4
10960bfb
PB		 12007 || (inst.size_req != 2
12008 && (inst.operands[0].hasreloc
e2b0ab59 12009 || inst.relocs[0].exp.X_op == O_constant))))
c19d1205 12010 {
0110f2b8 12011 inst.instruction = THUMB_OP32(opcode);
dfa9f0d5 12012 if (cond == COND_ALWAYS)
9ae92b05 12013 reloc = BFD_RELOC_THUMB_PCREL_BRANCH25;
c19d1205
ZW		 12014 else
12015 {
ff8646ee
TP		 12016 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2),
12017 _("selected architecture does not support "
12018 "wide conditional branch instruction"));
12019
9c2799c2 12020 gas_assert (cond != 0xF);
dfa9f0d5 12021 inst.instruction |= cond << 22;
9ae92b05 12022 reloc = BFD_RELOC_THUMB_PCREL_BRANCH20;
c19d1205
ZW		 12023 }
12024 }
b99bd4ef
NC		 12025 else
12026 {
0110f2b8 12027 inst.instruction = THUMB_OP16(opcode);
dfa9f0d5 12028 if (cond == COND_ALWAYS)
9ae92b05 12029 reloc = BFD_RELOC_THUMB_PCREL_BRANCH12;
c19d1205 12030 else
b99bd4ef 12031 {
dfa9f0d5 12032 inst.instruction |= cond << 8;
9ae92b05 12033 reloc = BFD_RELOC_THUMB_PCREL_BRANCH9;
b99bd4ef 12034 }
0110f2b8
PB		 12035 /* Allow section relaxation. */
12036 if (unified_syntax && inst.size_req != 2)
12037 inst.relax = opcode;
b99bd4ef 12038 }
e2b0ab59
AV		 12039 inst.relocs[0].type = reloc;
12040 inst.relocs[0].pc_rel = 1;
b99bd4ef
NC		 12041}
12042
8884b720 12043/* Actually do the work for Thumb state bkpt and hlt. The only difference
bacebabc 12044 between the two is the maximum immediate allowed - which is passed in
8884b720 12045 RANGE. */
b99bd4ef 12046static void
8884b720 12047do_t_bkpt_hlt1 (int range)
b99bd4ef 12048{
dfa9f0d5
PB		 12049 constraint (inst.cond != COND_ALWAYS,
12050 _("instruction is always unconditional"));
c19d1205 12051 if (inst.operands[0].present)
b99bd4ef 12052 {
8884b720 12053 constraint (inst.operands[0].imm > range,
c19d1205
ZW		 12054 _("immediate value out of range"));
12055 inst.instruction |= inst.operands[0].imm;
b99bd4ef 12056 }
8884b720 12057
5ee91343 12058 set_pred_insn_type (NEUTRAL_IT_INSN);
8884b720
MGD		 12059}
12060
12061static void
12062do_t_hlt (void)
12063{
12064 do_t_bkpt_hlt1 (63);
12065}
12066
12067static void
12068do_t_bkpt (void)
12069{
12070 do_t_bkpt_hlt1 (255);
b99bd4ef
NC		 12071}
12072
12073static void
c19d1205 12074do_t_branch23 (void)
b99bd4ef 12075{
5ee91343 12076 set_pred_insn_type_last ();
0855e32b 12077 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23);
fa94de6b 12078
0855e32b
NS		 12079 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12080 this file. We used to simply ignore the PLT reloc type here --
12081 the branch encoding is now needed to deal with TLSCALL relocs.
12082 So if we see a PLT reloc now, put it back to how it used to be to
12083 keep the preexisting behaviour. */
e2b0ab59
AV		 12084 if (inst.relocs[0].type == BFD_RELOC_ARM_PLT32)
12085 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH23;
90e4755a 12086
4343666d 12087#if defined(OBJ_COFF)
c19d1205
ZW		 12088 /* If the destination of the branch is a defined symbol which does not have
12089 the THUMB_FUNC attribute, then we must be calling a function which has
12090 the (interfacearm) attribute. We look for the Thumb entry point to that
12091 function and change the branch to refer to that function instead. */
e2b0ab59
AV		 12092 if ( inst.relocs[0].exp.X_op == O_symbol
12093 && inst.relocs[0].exp.X_add_symbol != NULL
12094 && S_IS_DEFINED (inst.relocs[0].exp.X_add_symbol)
12095 && ! THUMB_IS_FUNC (inst.relocs[0].exp.X_add_symbol))
12096 inst.relocs[0].exp.X_add_symbol
12097 = find_real_start (inst.relocs[0].exp.X_add_symbol);
4343666d 12098#endif
90e4755a
RE		 12099}
12100
12101static void
c19d1205 12102do_t_bx (void)
90e4755a 12103{
5ee91343 12104 set_pred_insn_type_last ();
c19d1205
ZW		 12105 inst.instruction |= inst.operands[0].reg << 3;
12106 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12107 should cause the alignment to be checked once it is known. This is
12108 because BX PC only works if the instruction is word aligned. */
12109}
90e4755a 12110
c19d1205
ZW		 12111static void
12112do_t_bxj (void)
12113{
fdfde340 12114 int Rm;
90e4755a 12115
5ee91343 12116 set_pred_insn_type_last ();
fdfde340
JM		 12117 Rm = inst.operands[0].reg;
12118 reject_bad_reg (Rm);
12119 inst.instruction |= Rm << 16;
90e4755a
RE		 12120}
12121
12122static void
c19d1205 12123do_t_clz (void)
90e4755a 12124{
fdfde340
JM		 12125 unsigned Rd;
12126 unsigned Rm;
12127
12128 Rd = inst.operands[0].reg;
12129 Rm = inst.operands[1].reg;
12130
12131 reject_bad_reg (Rd);
12132 reject_bad_reg (Rm);
12133
12134 inst.instruction |= Rd << 8;
12135 inst.instruction |= Rm << 16;
12136 inst.instruction |= Rm;
c19d1205 12137}
90e4755a 12138
e39c1607
SD		 12139/* For the Armv8.1-M conditional instructions. */
12140static void
12141do_t_cond (void)
12142{
12143 unsigned Rd, Rn, Rm;
12144 signed int cond;
12145
12146 constraint (inst.cond != COND_ALWAYS, BAD_COND);
12147
12148 Rd = inst.operands[0].reg;
12149 switch (inst.instruction)
12150 {
12151 case T_MNEM_csinc:
12152 case T_MNEM_csinv:
12153 case T_MNEM_csneg:
12154 case T_MNEM_csel:
12155 Rn = inst.operands[1].reg;
12156 Rm = inst.operands[2].reg;
12157 cond = inst.operands[3].imm;
12158 constraint (Rn == REG_SP, BAD_SP);
12159 constraint (Rm == REG_SP, BAD_SP);
12160 break;
12161
12162 case T_MNEM_cinc:
12163 case T_MNEM_cinv:
12164 case T_MNEM_cneg:
12165 Rn = inst.operands[1].reg;
12166 cond = inst.operands[2].imm;
12167 /* Invert the last bit to invert the cond. */
12168 cond = TOGGLE_BIT (cond, 0);
12169 constraint (Rn == REG_SP, BAD_SP);
12170 Rm = Rn;
12171 break;
12172
12173 case T_MNEM_csetm:
12174 case T_MNEM_cset:
12175 cond = inst.operands[1].imm;
12176 /* Invert the last bit to invert the cond. */
12177 cond = TOGGLE_BIT (cond, 0);
12178 Rn = REG_PC;
12179 Rm = REG_PC;
12180 break;
12181
12182 default: abort ();
12183 }
12184
12185 set_pred_insn_type (OUTSIDE_PRED_INSN);
12186 inst.instruction = THUMB_OP32 (inst.instruction);
12187 inst.instruction |= Rd << 8;
12188 inst.instruction |= Rn << 16;
12189 inst.instruction |= Rm;
12190 inst.instruction |= cond << 4;
12191}
12192
91d8b670
JG		 12193static void
12194do_t_csdb (void)
12195{
5ee91343 12196 set_pred_insn_type (OUTSIDE_PRED_INSN);
91d8b670
JG		 12197}
12198
dfa9f0d5
PB		 12199static void
12200do_t_cps (void)
12201{
5ee91343 12202 set_pred_insn_type (OUTSIDE_PRED_INSN);
dfa9f0d5
PB		 12203 inst.instruction |= inst.operands[0].imm;
12204}
12205
c19d1205
ZW		 12206static void
12207do_t_cpsi (void)
12208{
5ee91343 12209 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205 12210 if (unified_syntax
62b3e311
PB		 12211 && (inst.operands[1].present || inst.size_req == 4)
12212 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6_notm))
90e4755a 12213 {
c19d1205
ZW		 12214 unsigned int imod = (inst.instruction & 0x0030) >> 4;
12215 inst.instruction = 0xf3af8000;
12216 inst.instruction |= imod << 9;
12217 inst.instruction |= inst.operands[0].imm << 5;
12218 if (inst.operands[1].present)
12219 inst.instruction |= 0x100 | inst.operands[1].imm;
90e4755a 12220 }
c19d1205 12221 else
90e4755a 12222 {
62b3e311
PB		 12223 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1)
12224 && (inst.operands[0].imm & 4),
12225 _("selected processor does not support 'A' form "
12226 "of this instruction"));
12227 constraint (inst.operands[1].present || inst.size_req == 4,
c19d1205
ZW		 12228 _("Thumb does not support the 2-argument "
12229 "form of this instruction"));
12230 inst.instruction |= inst.operands[0].imm;
90e4755a 12231 }
90e4755a
RE		 12232}
12233
c19d1205
ZW		 12234/* THUMB CPY instruction (argument parse). */
12235
90e4755a 12236static void
c19d1205 12237do_t_cpy (void)
90e4755a 12238{
c19d1205 12239 if (inst.size_req == 4)
90e4755a 12240 {
c19d1205
ZW		 12241 inst.instruction = THUMB_OP32 (T_MNEM_mov);
12242 inst.instruction |= inst.operands[0].reg << 8;
12243 inst.instruction |= inst.operands[1].reg;
90e4755a 12244 }
c19d1205 12245 else
90e4755a 12246 {
c19d1205
ZW		 12247 inst.instruction |= (inst.operands[0].reg & 0x8) << 4;
12248 inst.instruction |= (inst.operands[0].reg & 0x7);
12249 inst.instruction |= inst.operands[1].reg << 3;
90e4755a 12250 }
90e4755a
RE		 12251}
12252
90e4755a 12253static void
25fe350b 12254do_t_cbz (void)
90e4755a 12255{
5ee91343 12256 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW		 12257 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12258 inst.instruction |= inst.operands[0].reg;
e2b0ab59
AV		 12259 inst.relocs[0].pc_rel = 1;
12260 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH7;
c19d1205 12261}
90e4755a 12262
62b3e311
PB		 12263static void
12264do_t_dbg (void)
12265{
12266 inst.instruction |= inst.operands[0].imm;
12267}
12268
12269static void
12270do_t_div (void)
12271{
fdfde340
JM		 12272 unsigned Rd, Rn, Rm;
12273
12274 Rd = inst.operands[0].reg;
12275 Rn = (inst.operands[1].present
12276 ? inst.operands[1].reg : Rd);
12277 Rm = inst.operands[2].reg;
12278
12279 reject_bad_reg (Rd);
12280 reject_bad_reg (Rn);
12281 reject_bad_reg (Rm);
12282
12283 inst.instruction |= Rd << 8;
12284 inst.instruction |= Rn << 16;
12285 inst.instruction |= Rm;
62b3e311
PB		 12286}
12287
c19d1205
ZW		 12288static void
12289do_t_hint (void)
12290{
12291 if (unified_syntax && inst.size_req == 4)
12292 inst.instruction = THUMB_OP32 (inst.instruction);
12293 else
12294 inst.instruction = THUMB_OP16 (inst.instruction);
12295}
90e4755a 12296
c19d1205
ZW		 12297static void
12298do_t_it (void)
12299{
12300 unsigned int cond = inst.operands[0].imm;
e27ec89e 12301
5ee91343
AV		 12302 set_pred_insn_type (IT_INSN);
12303 now_pred.mask = (inst.instruction & 0xf) | 0x10;
12304 now_pred.cc = cond;
12305 now_pred.warn_deprecated = FALSE;
12306 now_pred.type = SCALAR_PRED;
e27ec89e
PB		 12307
12308 /* If the condition is a negative condition, invert the mask. */
c19d1205 12309 if ((cond & 0x1) == 0x0)
90e4755a 12310 {
c19d1205 12311 unsigned int mask = inst.instruction & 0x000f;
90e4755a 12312
c19d1205 12313 if ((mask & 0x7) == 0)
5a01bb1d
MGD		 12314 {
12315 /* No conversion needed. */
5ee91343 12316 now_pred.block_length = 1;
5a01bb1d 12317 }
c19d1205 12318 else if ((mask & 0x3) == 0)
5a01bb1d
MGD		 12319 {
12320 mask ^= 0x8;
5ee91343 12321 now_pred.block_length = 2;
5a01bb1d 12322 }
e27ec89e 12323 else if ((mask & 0x1) == 0)
5a01bb1d
MGD		 12324 {
12325 mask ^= 0xC;
5ee91343 12326 now_pred.block_length = 3;
5a01bb1d 12327 }
c19d1205 12328 else
5a01bb1d
MGD		 12329 {
12330 mask ^= 0xE;
5ee91343 12331 now_pred.block_length = 4;
5a01bb1d 12332 }
90e4755a 12333
e27ec89e
PB		 12334 inst.instruction &= 0xfff0;
12335 inst.instruction |= mask;
c19d1205 12336 }
90e4755a 12337
c19d1205
ZW		 12338 inst.instruction |= cond << 4;
12339}
90e4755a 12340
3c707909
PB		 12341/* Helper function used for both push/pop and ldm/stm. */
12342static void
4b5a202f
AV		 12343encode_thumb2_multi (bfd_boolean do_io, int base, unsigned mask,
12344 bfd_boolean writeback)
3c707909 12345{
4b5a202f 12346 bfd_boolean load, store;
3c707909 12347
4b5a202f
AV		 12348 gas_assert (base != -1 || !do_io);
12349 load = do_io && ((inst.instruction & (1 << 20)) != 0);
12350 store = do_io && !load;
3c707909
PB		 12351
12352 if (mask & (1 << 13))
12353 inst.error = _("SP not allowed in register list");
1e5b0379 12354
4b5a202f 12355 if (do_io && (mask & (1 << base)) != 0
1e5b0379
NC		 12356 && writeback)
12357 inst.error = _("having the base register in the register list when "
12358 "using write back is UNPREDICTABLE");
12359
3c707909
PB		 12360 if (load)
12361 {
e07e6e58 12362 if (mask & (1 << 15))
477330fc
RM		 12363 {
12364 if (mask & (1 << 14))
12365 inst.error = _("LR and PC should not both be in register list");
12366 else
5ee91343 12367 set_pred_insn_type_last ();
477330fc 12368 }
3c707909 12369 }
4b5a202f 12370 else if (store)
3c707909
PB		 12371 {
12372 if (mask & (1 << 15))
12373 inst.error = _("PC not allowed in register list");
3c707909
PB		 12374 }
12375
4b5a202f 12376 if (do_io && ((mask & (mask - 1)) == 0))
3c707909
PB		 12377 {
12378 /* Single register transfers implemented as str/ldr. */
12379 if (writeback)
12380 {
12381 if (inst.instruction & (1 << 23))
12382 inst.instruction = 0x00000b04; /* ia! -> [base], #4 */
12383 else
12384 inst.instruction = 0x00000d04; /* db! -> [base, #-4]! */
12385 }
12386 else
12387 {
12388 if (inst.instruction & (1 << 23))
12389 inst.instruction = 0x00800000; /* ia -> [base] */
12390 else
12391 inst.instruction = 0x00000c04; /* db -> [base, #-4] */
12392 }
12393
12394 inst.instruction |= 0xf8400000;
12395 if (load)
12396 inst.instruction |= 0x00100000;
12397
5f4273c7 12398 mask = ffs (mask) - 1;
3c707909
PB		 12399 mask <<= 12;
12400 }
12401 else if (writeback)
12402 inst.instruction |= WRITE_BACK;
12403
12404 inst.instruction |= mask;
4b5a202f
AV		 12405 if (do_io)
12406 inst.instruction |= base << 16;
3c707909
PB		 12407}
12408
c19d1205
ZW		 12409static void
12410do_t_ldmstm (void)
12411{
12412 /* This really doesn't seem worth it. */
e2b0ab59 12413 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205
ZW		 12414 _("expression too complex"));
12415 constraint (inst.operands[1].writeback,
12416 _("Thumb load/store multiple does not support {reglist}^"));
90e4755a 12417
c19d1205
ZW		 12418 if (unified_syntax)
12419 {
3c707909
PB		 12420 bfd_boolean narrow;
12421 unsigned mask;
12422
12423 narrow = FALSE;
c19d1205
ZW		 12424 /* See if we can use a 16-bit instruction. */
12425 if (inst.instruction < 0xffff /* not ldmdb/stmdb */
12426 && inst.size_req != 4
3c707909 12427 && !(inst.operands[1].imm & ~0xff))
90e4755a 12428 {
3c707909 12429 mask = 1 << inst.operands[0].reg;
90e4755a 12430
eab4f823 12431 if (inst.operands[0].reg <= 7)
90e4755a 12432 {
3c707909 12433 if (inst.instruction == T_MNEM_stmia
eab4f823
MGD		 12434 ? inst.operands[0].writeback
12435 : (inst.operands[0].writeback
12436 == !(inst.operands[1].imm & mask)))
477330fc 12437 {
eab4f823
MGD		 12438 if (inst.instruction == T_MNEM_stmia
12439 && (inst.operands[1].imm & mask)
12440 && (inst.operands[1].imm & (mask - 1)))
12441 as_warn (_("value stored for r%d is UNKNOWN"),
12442 inst.operands[0].reg);
3c707909 12443
eab4f823
MGD		 12444 inst.instruction = THUMB_OP16 (inst.instruction);
12445 inst.instruction |= inst.operands[0].reg << 8;
12446 inst.instruction |= inst.operands[1].imm;
12447 narrow = TRUE;
12448 }
12449 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12450 {
12451 /* This means 1 register in reg list one of 3 situations:
12452 1. Instruction is stmia, but without writeback.
12453 2. lmdia without writeback, but with Rn not in
477330fc 12454 reglist.
eab4f823
MGD		 12455 3. ldmia with writeback, but with Rn in reglist.
12456 Case 3 is UNPREDICTABLE behaviour, so we handle
12457 case 1 and 2 which can be converted into a 16-bit
12458 str or ldr. The SP cases are handled below. */
12459 unsigned long opcode;
12460 /* First, record an error for Case 3. */
12461 if (inst.operands[1].imm & mask
12462 && inst.operands[0].writeback)
fa94de6b 12463 inst.error =
eab4f823
MGD		 12464 _("having the base register in the register list when "
12465 "using write back is UNPREDICTABLE");
fa94de6b
RM		 12466
12467 opcode = (inst.instruction == T_MNEM_stmia ? T_MNEM_str
eab4f823
MGD		 12468 : T_MNEM_ldr);
12469 inst.instruction = THUMB_OP16 (opcode);
12470 inst.instruction |= inst.operands[0].reg << 3;
12471 inst.instruction |= (ffs (inst.operands[1].imm)-1);
12472 narrow = TRUE;
12473 }
90e4755a 12474 }
eab4f823 12475 else if (inst.operands[0] .reg == REG_SP)
90e4755a 12476 {
eab4f823
MGD		 12477 if (inst.operands[0].writeback)
12478 {
fa94de6b 12479 inst.instruction =
eab4f823 12480 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12481 ? T_MNEM_push : T_MNEM_pop);
eab4f823 12482 inst.instruction |= inst.operands[1].imm;
477330fc 12483 narrow = TRUE;
eab4f823
MGD		 12484 }
12485 else if ((inst.operands[1].imm & (inst.operands[1].imm-1)) == 0)
12486 {
fa94de6b 12487 inst.instruction =
eab4f823 12488 THUMB_OP16 (inst.instruction == T_MNEM_stmia
477330fc 12489 ? T_MNEM_str_sp : T_MNEM_ldr_sp);
eab4f823 12490 inst.instruction |= ((ffs (inst.operands[1].imm)-1) << 8);
477330fc 12491 narrow = TRUE;
eab4f823 12492 }
90e4755a 12493 }
3c707909
PB		 12494 }
12495
12496 if (!narrow)
12497 {
c19d1205
ZW		 12498 if (inst.instruction < 0xffff)
12499 inst.instruction = THUMB_OP32 (inst.instruction);
3c707909 12500
4b5a202f
AV		 12501 encode_thumb2_multi (TRUE /* do_io */, inst.operands[0].reg,
12502 inst.operands[1].imm,
12503 inst.operands[0].writeback);
90e4755a
RE		 12504 }
12505 }
c19d1205 12506 else
90e4755a 12507 {
c19d1205
ZW		 12508 constraint (inst.operands[0].reg > 7
12509 || (inst.operands[1].imm & ~0xff), BAD_HIREG);
1198ca51
PB		 12510 constraint (inst.instruction != T_MNEM_ldmia
12511 && inst.instruction != T_MNEM_stmia,
12512 _("Thumb-2 instruction only valid in unified syntax"));
c19d1205 12513 if (inst.instruction == T_MNEM_stmia)
f03698e6 12514 {
c19d1205
ZW		 12515 if (!inst.operands[0].writeback)
12516 as_warn (_("this instruction will write back the base register"));
12517 if ((inst.operands[1].imm & (1 << inst.operands[0].reg))
12518 && (inst.operands[1].imm & ((1 << inst.operands[0].reg) - 1)))
1e5b0379 12519 as_warn (_("value stored for r%d is UNKNOWN"),
c19d1205 12520 inst.operands[0].reg);
f03698e6 12521 }
c19d1205 12522 else
90e4755a 12523 {
c19d1205
ZW		 12524 if (!inst.operands[0].writeback
12525 && !(inst.operands[1].imm & (1 << inst.operands[0].reg)))
12526 as_warn (_("this instruction will write back the base register"));
12527 else if (inst.operands[0].writeback
12528 && (inst.operands[1].imm & (1 << inst.operands[0].reg)))
12529 as_warn (_("this instruction will not write back the base register"));
90e4755a
RE		 12530 }
12531
c19d1205
ZW		 12532 inst.instruction = THUMB_OP16 (inst.instruction);
12533 inst.instruction |= inst.operands[0].reg << 8;
12534 inst.instruction |= inst.operands[1].imm;
12535 }
12536}
e28cd48c 12537
c19d1205
ZW		 12538static void
12539do_t_ldrex (void)
12540{
12541 constraint (!inst.operands[1].isreg || !inst.operands[1].preind
12542 || inst.operands[1].postind || inst.operands[1].writeback
12543 || inst.operands[1].immisreg || inst.operands[1].shifted
12544 || inst.operands[1].negative,
01cfc07f 12545 BAD_ADDR_MODE);
e28cd48c 12546
5be8be5d
DG		 12547 constraint ((inst.operands[1].reg == REG_PC), BAD_PC);
12548
c19d1205
ZW		 12549 inst.instruction |= inst.operands[0].reg << 12;
12550 inst.instruction |= inst.operands[1].reg << 16;
e2b0ab59 12551 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
c19d1205 12552}
e28cd48c 12553
c19d1205
ZW		 12554static void
12555do_t_ldrexd (void)
12556{
12557 if (!inst.operands[1].present)
1cac9012 12558 {
c19d1205
ZW		 12559 constraint (inst.operands[0].reg == REG_LR,
12560 _("r14 not allowed as first register "
12561 "when second register is omitted"));
12562 inst.operands[1].reg = inst.operands[0].reg + 1;
b99bd4ef 12563 }
c19d1205
ZW		 12564 constraint (inst.operands[0].reg == inst.operands[1].reg,
12565 BAD_OVERLAP);
b99bd4ef 12566
c19d1205
ZW		 12567 inst.instruction |= inst.operands[0].reg << 12;
12568 inst.instruction |= inst.operands[1].reg << 8;
12569 inst.instruction |= inst.operands[2].reg << 16;
b99bd4ef
NC		 12570}
12571
12572static void
c19d1205 12573do_t_ldst (void)
b99bd4ef 12574{
0110f2b8
PB		 12575 unsigned long opcode;
12576 int Rn;
12577
e07e6e58
NC		 12578 if (inst.operands[0].isreg
12579 && !inst.operands[0].preind
12580 && inst.operands[0].reg == REG_PC)
5ee91343 12581 set_pred_insn_type_last ();
e07e6e58 12582
0110f2b8 12583 opcode = inst.instruction;
c19d1205 12584 if (unified_syntax)
b99bd4ef 12585 {
53365c0d
PB		 12586 if (!inst.operands[1].isreg)
12587 {
12588 if (opcode <= 0xffff)
12589 inst.instruction = THUMB_OP32 (opcode);
8335d6aa 12590 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
53365c0d
PB		 12591 return;
12592 }
0110f2b8
PB		 12593 if (inst.operands[1].isreg
12594 && !inst.operands[1].writeback
c19d1205
ZW		 12595 && !inst.operands[1].shifted && !inst.operands[1].postind
12596 && !inst.operands[1].negative && inst.operands[0].reg <= 7
0110f2b8
PB		 12597 && opcode <= 0xffff
12598 && inst.size_req != 4)
c19d1205 12599 {
0110f2b8
PB		 12600 /* Insn may have a 16-bit form. */
12601 Rn = inst.operands[1].reg;
12602 if (inst.operands[1].immisreg)
12603 {
12604 inst.instruction = THUMB_OP16 (opcode);
5f4273c7 12605 /* [Rn, Rik] */
0110f2b8
PB		 12606 if (Rn <= 7 && inst.operands[1].imm <= 7)
12607 goto op16;
5be8be5d
DG		 12608 else if (opcode != T_MNEM_ldr && opcode != T_MNEM_str)
12609 reject_bad_reg (inst.operands[1].imm);
0110f2b8
PB		 12610 }
12611 else if ((Rn <= 7 && opcode != T_MNEM_ldrsh
12612 && opcode != T_MNEM_ldrsb)
12613 || ((Rn == REG_PC || Rn == REG_SP) && opcode == T_MNEM_ldr)
12614 || (Rn == REG_SP && opcode == T_MNEM_str))
12615 {
12616 /* [Rn, #const] */
12617 if (Rn > 7)
12618 {
12619 if (Rn == REG_PC)
12620 {
e2b0ab59 12621 if (inst.relocs[0].pc_rel)
0110f2b8
PB		 12622 opcode = T_MNEM_ldr_pc2;
12623 else
12624 opcode = T_MNEM_ldr_pc;
12625 }
12626 else
12627 {
12628 if (opcode == T_MNEM_ldr)
12629 opcode = T_MNEM_ldr_sp;
12630 else
12631 opcode = T_MNEM_str_sp;
12632 }
12633 inst.instruction = inst.operands[0].reg << 8;
12634 }
12635 else
12636 {
12637 inst.instruction = inst.operands[0].reg;
12638 inst.instruction |= inst.operands[1].reg << 3;
12639 }
12640 inst.instruction |= THUMB_OP16 (opcode);
12641 if (inst.size_req == 2)
e2b0ab59 12642 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
0110f2b8
PB		 12643 else
12644 inst.relax = opcode;
12645 return;
12646 }
c19d1205 12647 }
0110f2b8 12648 /* Definitely a 32-bit variant. */
5be8be5d 12649
8d67f500
NC		 12650 /* Warning for Erratum 752419. */
12651 if (opcode == T_MNEM_ldr
12652 && inst.operands[0].reg == REG_SP
12653 && inst.operands[1].writeback == 1
12654 && !inst.operands[1].immisreg)
12655 {
12656 if (no_cpu_selected ()
12657 || (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7)
477330fc
RM		 12658 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a)
12659 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7r)))
8d67f500
NC		 12660 as_warn (_("This instruction may be unpredictable "
12661 "if executed on M-profile cores "
12662 "with interrupts enabled."));
12663 }
12664
5be8be5d 12665 /* Do some validations regarding addressing modes. */
1be5fd2e 12666 if (inst.operands[1].immisreg)
5be8be5d
DG		 12667 reject_bad_reg (inst.operands[1].imm);
12668
1be5fd2e
NC		 12669 constraint (inst.operands[1].writeback == 1
12670 && inst.operands[0].reg == inst.operands[1].reg,
12671 BAD_OVERLAP);
12672
0110f2b8 12673 inst.instruction = THUMB_OP32 (opcode);
c19d1205
ZW		 12674 inst.instruction |= inst.operands[0].reg << 12;
12675 encode_thumb32_addr_mode (1, /*is_t=*/FALSE, /*is_d=*/FALSE);
1be5fd2e 12676 check_ldr_r15_aligned ();
b99bd4ef
NC		 12677 return;
12678 }
12679
c19d1205
ZW		 12680 constraint (inst.operands[0].reg > 7, BAD_HIREG);
12681
12682 if (inst.instruction == T_MNEM_ldrsh || inst.instruction == T_MNEM_ldrsb)
b99bd4ef 12683 {
c19d1205
ZW		 12684 /* Only [Rn,Rm] is acceptable. */
12685 constraint (inst.operands[1].reg > 7 || inst.operands[1].imm > 7, BAD_HIREG);
12686 constraint (!inst.operands[1].isreg || !inst.operands[1].immisreg
12687 || inst.operands[1].postind || inst.operands[1].shifted
12688 || inst.operands[1].negative,
12689 _("Thumb does not support this addressing mode"));
12690 inst.instruction = THUMB_OP16 (inst.instruction);
12691 goto op16;
b99bd4ef 12692 }
5f4273c7 12693
c19d1205
ZW		 12694 inst.instruction = THUMB_OP16 (inst.instruction);
12695 if (!inst.operands[1].isreg)
8335d6aa 12696 if (move_or_literal_pool (0, CONST_THUMB, /*mode_3=*/FALSE))
c19d1205 12697 return;
b99bd4ef 12698
c19d1205
ZW		 12699 constraint (!inst.operands[1].preind
12700 || inst.operands[1].shifted
12701 || inst.operands[1].writeback,
12702 _("Thumb does not support this addressing mode"));
12703 if (inst.operands[1].reg == REG_PC || inst.operands[1].reg == REG_SP)
90e4755a 12704 {
c19d1205
ZW		 12705 constraint (inst.instruction & 0x0600,
12706 _("byte or halfword not valid for base register"));
12707 constraint (inst.operands[1].reg == REG_PC
12708 && !(inst.instruction & THUMB_LOAD_BIT),
12709 _("r15 based store not allowed"));
12710 constraint (inst.operands[1].immisreg,
12711 _("invalid base register for register offset"));
b99bd4ef 12712
c19d1205
ZW		 12713 if (inst.operands[1].reg == REG_PC)
12714 inst.instruction = T_OPCODE_LDR_PC;
12715 else if (inst.instruction & THUMB_LOAD_BIT)
12716 inst.instruction = T_OPCODE_LDR_SP;
12717 else
12718 inst.instruction = T_OPCODE_STR_SP;
b99bd4ef 12719
c19d1205 12720 inst.instruction |= inst.operands[0].reg << 8;
e2b0ab59 12721 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW		 12722 return;
12723 }
90e4755a 12724
c19d1205
ZW		 12725 constraint (inst.operands[1].reg > 7, BAD_HIREG);
12726 if (!inst.operands[1].immisreg)
12727 {
12728 /* Immediate offset. */
12729 inst.instruction |= inst.operands[0].reg;
12730 inst.instruction |= inst.operands[1].reg << 3;
e2b0ab59 12731 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_OFFSET;
c19d1205
ZW		 12732 return;
12733 }
90e4755a 12734
c19d1205
ZW		 12735 /* Register offset. */
12736 constraint (inst.operands[1].imm > 7, BAD_HIREG);
12737 constraint (inst.operands[1].negative,
12738 _("Thumb does not support this addressing mode"));
90e4755a 12739
c19d1205
ZW		 12740 op16:
12741 switch (inst.instruction)
12742 {
12743 case T_OPCODE_STR_IW: inst.instruction = T_OPCODE_STR_RW; break;
12744 case T_OPCODE_STR_IH: inst.instruction = T_OPCODE_STR_RH; break;
12745 case T_OPCODE_STR_IB: inst.instruction = T_OPCODE_STR_RB; break;
12746 case T_OPCODE_LDR_IW: inst.instruction = T_OPCODE_LDR_RW; break;
12747 case T_OPCODE_LDR_IH: inst.instruction = T_OPCODE_LDR_RH; break;
12748 case T_OPCODE_LDR_IB: inst.instruction = T_OPCODE_LDR_RB; break;
12749 case 0x5600 /* ldrsb */:
12750 case 0x5e00 /* ldrsh */: break;
12751 default: abort ();
12752 }
90e4755a 12753
c19d1205
ZW		 12754 inst.instruction |= inst.operands[0].reg;
12755 inst.instruction |= inst.operands[1].reg << 3;
12756 inst.instruction |= inst.operands[1].imm << 6;
12757}
90e4755a 12758
c19d1205
ZW		 12759static void
12760do_t_ldstd (void)
12761{
12762 if (!inst.operands[1].present)
b99bd4ef 12763 {
c19d1205
ZW		 12764 inst.operands[1].reg = inst.operands[0].reg + 1;
12765 constraint (inst.operands[0].reg == REG_LR,
12766 _("r14 not allowed here"));
bd340a04 12767 constraint (inst.operands[0].reg == REG_R12,
477330fc 12768 _("r12 not allowed here"));
b99bd4ef 12769 }
bd340a04
MGD		 12770
12771 if (inst.operands[2].writeback
12772 && (inst.operands[0].reg == inst.operands[2].reg
12773 || inst.operands[1].reg == inst.operands[2].reg))
12774 as_warn (_("base register written back, and overlaps "
477330fc 12775 "one of transfer registers"));
bd340a04 12776
c19d1205
ZW		 12777 inst.instruction |= inst.operands[0].reg << 12;
12778 inst.instruction |= inst.operands[1].reg << 8;
12779 encode_thumb32_addr_mode (2, /*is_t=*/FALSE, /*is_d=*/TRUE);
b99bd4ef
NC		 12780}
12781
c19d1205
ZW		 12782static void
12783do_t_ldstt (void)
12784{
12785 inst.instruction |= inst.operands[0].reg << 12;
12786 encode_thumb32_addr_mode (1, /*is_t=*/TRUE, /*is_d=*/FALSE);
12787}
a737bd4d 12788
b99bd4ef 12789static void
c19d1205 12790do_t_mla (void)
b99bd4ef 12791{
fdfde340 12792 unsigned Rd, Rn, Rm, Ra;
c921be7d 12793
fdfde340
JM		 12794 Rd = inst.operands[0].reg;
12795 Rn = inst.operands[1].reg;
12796 Rm = inst.operands[2].reg;
12797 Ra = inst.operands[3].reg;
12798
12799 reject_bad_reg (Rd);
12800 reject_bad_reg (Rn);
12801 reject_bad_reg (Rm);
12802 reject_bad_reg (Ra);
12803
12804 inst.instruction |= Rd << 8;
12805 inst.instruction |= Rn << 16;
12806 inst.instruction |= Rm;
12807 inst.instruction |= Ra << 12;
c19d1205 12808}
b99bd4ef 12809
c19d1205
ZW		 12810static void
12811do_t_mlal (void)
12812{
fdfde340
JM		 12813 unsigned RdLo, RdHi, Rn, Rm;
12814
12815 RdLo = inst.operands[0].reg;
12816 RdHi = inst.operands[1].reg;
12817 Rn = inst.operands[2].reg;
12818 Rm = inst.operands[3].reg;
12819
12820 reject_bad_reg (RdLo);
12821 reject_bad_reg (RdHi);
12822 reject_bad_reg (Rn);
12823 reject_bad_reg (Rm);
12824
12825 inst.instruction |= RdLo << 12;
12826 inst.instruction |= RdHi << 8;
12827 inst.instruction |= Rn << 16;
12828 inst.instruction |= Rm;
c19d1205 12829}
b99bd4ef 12830
c19d1205
ZW		 12831static void
12832do_t_mov_cmp (void)
12833{
fdfde340
JM		 12834 unsigned Rn, Rm;
12835
12836 Rn = inst.operands[0].reg;
12837 Rm = inst.operands[1].reg;
12838
e07e6e58 12839 if (Rn == REG_PC)
5ee91343 12840 set_pred_insn_type_last ();
e07e6e58 12841
c19d1205 12842 if (unified_syntax)
b99bd4ef 12843 {
c19d1205
ZW		 12844 int r0off = (inst.instruction == T_MNEM_mov
12845 || inst.instruction == T_MNEM_movs) ? 8 : 16;
0110f2b8 12846 unsigned long opcode;
3d388997
PB		 12847 bfd_boolean narrow;
12848 bfd_boolean low_regs;
12849
fdfde340 12850 low_regs = (Rn <= 7 && Rm <= 7);
0110f2b8 12851 opcode = inst.instruction;
5ee91343 12852 if (in_pred_block ())
0110f2b8 12853 narrow = opcode != T_MNEM_movs;
3d388997 12854 else
0110f2b8 12855 narrow = opcode != T_MNEM_movs || low_regs;
3d388997
PB		 12856 if (inst.size_req == 4
12857 || inst.operands[1].shifted)
12858 narrow = FALSE;
12859
efd81785
PB		 12860 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12861 if (opcode == T_MNEM_movs && inst.operands[1].isreg
12862 && !inst.operands[1].shifted
fdfde340
JM		 12863 && Rn == REG_PC
12864 && Rm == REG_LR)
efd81785
PB		 12865 {
12866 inst.instruction = T2_SUBS_PC_LR;
12867 return;
12868 }
12869
fdfde340
JM		 12870 if (opcode == T_MNEM_cmp)
12871 {
12872 constraint (Rn == REG_PC, BAD_PC);
94206790
MM		 12873 if (narrow)
12874 {
12875 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12876 but valid. */
12877 warn_deprecated_sp (Rm);
12878 /* R15 was documented as a valid choice for Rm in ARMv6,
12879 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12880 tools reject R15, so we do too. */
12881 constraint (Rm == REG_PC, BAD_PC);
12882 }
12883 else
12884 reject_bad_reg (Rm);
fdfde340
JM		 12885 }
12886 else if (opcode == T_MNEM_mov
12887 || opcode == T_MNEM_movs)
12888 {
12889 if (inst.operands[1].isreg)
12890 {
12891 if (opcode == T_MNEM_movs)
12892 {
12893 reject_bad_reg (Rn);
12894 reject_bad_reg (Rm);
12895 }
76fa04a4
MGD		 12896 else if (narrow)
12897 {
12898 /* This is mov.n. */
12899 if ((Rn == REG_SP || Rn == REG_PC)
12900 && (Rm == REG_SP || Rm == REG_PC))
12901 {
5c3696f8 12902 as_tsktsk (_("Use of r%u as a source register is "
76fa04a4
MGD		 12903 "deprecated when r%u is the destination "
12904 "register."), Rm, Rn);
12905 }
12906 }
12907 else
12908 {
12909 /* This is mov.w. */
12910 constraint (Rn == REG_PC, BAD_PC);
12911 constraint (Rm == REG_PC, BAD_PC);
5c8ed6a4
JW		 12912 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
12913 constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
76fa04a4 12914 }
fdfde340
JM		 12915 }
12916 else
12917 reject_bad_reg (Rn);
12918 }
12919
c19d1205
ZW		 12920 if (!inst.operands[1].isreg)
12921 {
0110f2b8 12922 /* Immediate operand. */
5ee91343 12923 if (!in_pred_block () && opcode == T_MNEM_mov)
0110f2b8
PB		 12924 narrow = 0;
12925 if (low_regs && narrow)
12926 {
12927 inst.instruction = THUMB_OP16 (opcode);
fdfde340 12928 inst.instruction |= Rn << 8;
e2b0ab59
AV		 12929 if (inst.relocs[0].type < BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12930 || inst.relocs[0].type > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
72d98d16 12931 {
a9f02af8 12932 if (inst.size_req == 2)
e2b0ab59 12933 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
a9f02af8
MG		 12934 else
12935 inst.relax = opcode;
72d98d16 12936 }
0110f2b8
PB		 12937 }
12938 else
12939 {
e2b0ab59
AV		 12940 constraint ((inst.relocs[0].type
12941 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC)
12942 && (inst.relocs[0].type
12943 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC) ,
a9f02af8
MG		 12944 THUMB1_RELOC_ONLY);
12945
0110f2b8
PB		 12946 inst.instruction = THUMB_OP32 (inst.instruction);
12947 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 12948 inst.instruction |= Rn << r0off;
e2b0ab59 12949 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8 12950 }
c19d1205 12951 }
728ca7c9
PB		 12952 else if (inst.operands[1].shifted && inst.operands[1].immisreg
12953 && (inst.instruction == T_MNEM_mov
12954 || inst.instruction == T_MNEM_movs))
12955 {
12956 /* Register shifts are encoded as separate shift instructions. */
12957 bfd_boolean flags = (inst.instruction == T_MNEM_movs);
12958
5ee91343 12959 if (in_pred_block ())
728ca7c9
PB		 12960 narrow = !flags;
12961 else
12962 narrow = flags;
12963
12964 if (inst.size_req == 4)
12965 narrow = FALSE;
12966
12967 if (!low_regs || inst.operands[1].imm > 7)
12968 narrow = FALSE;
12969
fdfde340 12970 if (Rn != Rm)
728ca7c9
PB		 12971 narrow = FALSE;
12972
12973 switch (inst.operands[1].shift_kind)
12974 {
12975 case SHIFT_LSL:
12976 opcode = narrow ? T_OPCODE_LSL_R : THUMB_OP32 (T_MNEM_lsl);
12977 break;
12978 case SHIFT_ASR:
12979 opcode = narrow ? T_OPCODE_ASR_R : THUMB_OP32 (T_MNEM_asr);
12980 break;
12981 case SHIFT_LSR:
12982 opcode = narrow ? T_OPCODE_LSR_R : THUMB_OP32 (T_MNEM_lsr);
12983 break;
12984 case SHIFT_ROR:
12985 opcode = narrow ? T_OPCODE_ROR_R : THUMB_OP32 (T_MNEM_ror);
12986 break;
12987 default:
5f4273c7 12988 abort ();
728ca7c9
PB		 12989 }
12990
12991 inst.instruction = opcode;
12992 if (narrow)
12993 {
fdfde340 12994 inst.instruction |= Rn;
728ca7c9
PB		 12995 inst.instruction |= inst.operands[1].imm << 3;
12996 }
12997 else
12998 {
12999 if (flags)
13000 inst.instruction |= CONDS_BIT;
13001
fdfde340
JM		 13002 inst.instruction |= Rn << 8;
13003 inst.instruction |= Rm << 16;
728ca7c9
PB		 13004 inst.instruction |= inst.operands[1].imm;
13005 }
13006 }
3d388997 13007 else if (!narrow)
c19d1205 13008 {
728ca7c9
PB		 13009 /* Some mov with immediate shift have narrow variants.
13010 Register shifts are handled above. */
13011 if (low_regs && inst.operands[1].shifted
13012 && (inst.instruction == T_MNEM_mov
13013 || inst.instruction == T_MNEM_movs))
13014 {
5ee91343 13015 if (in_pred_block ())
728ca7c9
PB		 13016 narrow = (inst.instruction == T_MNEM_mov);
13017 else
13018 narrow = (inst.instruction == T_MNEM_movs);
13019 }
13020
13021 if (narrow)
13022 {
13023 switch (inst.operands[1].shift_kind)
13024 {
13025 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13026 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
13027 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13028 default: narrow = FALSE; break;
13029 }
13030 }
13031
13032 if (narrow)
13033 {
fdfde340
JM		 13034 inst.instruction |= Rn;
13035 inst.instruction |= Rm << 3;
e2b0ab59 13036 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
728ca7c9
PB		 13037 }
13038 else
13039 {
13040 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13041 inst.instruction |= Rn << r0off;
728ca7c9
PB		 13042 encode_thumb32_shifted_operand (1);
13043 }
c19d1205
ZW		 13044 }
13045 else
13046 switch (inst.instruction)
13047 {
13048 case T_MNEM_mov:
837b3435 13049 /* In v4t or v5t a move of two lowregs produces unpredictable
c6400f8a
MGD		 13050 results. Don't allow this. */
13051 if (low_regs)
13052 {
13053 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6),
13054 "MOV Rd, Rs with two low registers is not "
13055 "permitted on this architecture");
fa94de6b 13056 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
c6400f8a
MGD		 13057 arm_ext_v6);
13058 }
13059
c19d1205 13060 inst.instruction = T_OPCODE_MOV_HR;
fdfde340
JM		 13061 inst.instruction |= (Rn & 0x8) << 4;
13062 inst.instruction |= (Rn & 0x7);
13063 inst.instruction |= Rm << 3;
c19d1205 13064 break;
b99bd4ef 13065
c19d1205
ZW		 13066 case T_MNEM_movs:
13067 /* We know we have low registers at this point.
941a8a52
MGD		 13068 Generate LSLS Rd, Rs, #0. */
13069 inst.instruction = T_OPCODE_LSL_I;
fdfde340
JM		 13070 inst.instruction |= Rn;
13071 inst.instruction |= Rm << 3;
c19d1205
ZW		 13072 break;
13073
13074 case T_MNEM_cmp:
3d388997 13075 if (low_regs)
c19d1205
ZW		 13076 {
13077 inst.instruction = T_OPCODE_CMP_LR;
fdfde340
JM		 13078 inst.instruction |= Rn;
13079 inst.instruction |= Rm << 3;
c19d1205
ZW		 13080 }
13081 else
13082 {
13083 inst.instruction = T_OPCODE_CMP_HR;
fdfde340
JM		 13084 inst.instruction |= (Rn & 0x8) << 4;
13085 inst.instruction |= (Rn & 0x7);
13086 inst.instruction |= Rm << 3;
c19d1205
ZW		 13087 }
13088 break;
13089 }
b99bd4ef
NC		 13090 return;
13091 }
13092
c19d1205 13093 inst.instruction = THUMB_OP16 (inst.instruction);
539d4391
NC		 13094
13095 /* PR 10443: Do not silently ignore shifted operands. */
13096 constraint (inst.operands[1].shifted,
13097 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13098
c19d1205 13099 if (inst.operands[1].isreg)
b99bd4ef 13100 {
fdfde340 13101 if (Rn < 8 && Rm < 8)
b99bd4ef 13102 {
c19d1205
ZW		 13103 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13104 since a MOV instruction produces unpredictable results. */
13105 if (inst.instruction == T_OPCODE_MOV_I8)
13106 inst.instruction = T_OPCODE_ADD_I3;
b99bd4ef 13107 else
c19d1205 13108 inst.instruction = T_OPCODE_CMP_LR;
b99bd4ef 13109
fdfde340
JM		 13110 inst.instruction |= Rn;
13111 inst.instruction |= Rm << 3;
b99bd4ef
NC		 13112 }
13113 else
13114 {
c19d1205
ZW		 13115 if (inst.instruction == T_OPCODE_MOV_I8)
13116 inst.instruction = T_OPCODE_MOV_HR;
13117 else
13118 inst.instruction = T_OPCODE_CMP_HR;
13119 do_t_cpy ();
b99bd4ef
NC		 13120 }
13121 }
c19d1205 13122 else
b99bd4ef 13123 {
fdfde340 13124 constraint (Rn > 7,
c19d1205 13125 _("only lo regs allowed with immediate"));
fdfde340 13126 inst.instruction |= Rn << 8;
e2b0ab59 13127 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_IMM;
c19d1205
ZW		 13128 }
13129}
b99bd4ef 13130
c19d1205
ZW		 13131static void
13132do_t_mov16 (void)
13133{
fdfde340 13134 unsigned Rd;
b6895b4f
PB		 13135 bfd_vma imm;
13136 bfd_boolean top;
13137
13138 top = (inst.instruction & 0x00800000) != 0;
e2b0ab59 13139 if (inst.relocs[0].type == BFD_RELOC_ARM_MOVW)
b6895b4f 13140 {
33eaf5de 13141 constraint (top, _(":lower16: not allowed in this instruction"));
e2b0ab59 13142 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVW;
b6895b4f 13143 }
e2b0ab59 13144 else if (inst.relocs[0].type == BFD_RELOC_ARM_MOVT)
b6895b4f 13145 {
33eaf5de 13146 constraint (!top, _(":upper16: not allowed in this instruction"));
e2b0ab59 13147 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_MOVT;
b6895b4f
PB		 13148 }
13149
fdfde340
JM		 13150 Rd = inst.operands[0].reg;
13151 reject_bad_reg (Rd);
13152
13153 inst.instruction |= Rd << 8;
e2b0ab59 13154 if (inst.relocs[0].type == BFD_RELOC_UNUSED)
b6895b4f 13155 {
e2b0ab59 13156 imm = inst.relocs[0].exp.X_add_number;
b6895b4f
PB		 13157 inst.instruction |= (imm & 0xf000) << 4;
13158 inst.instruction |= (imm & 0x0800) << 15;
13159 inst.instruction |= (imm & 0x0700) << 4;
13160 inst.instruction |= (imm & 0x00ff);
13161 }
c19d1205 13162}
b99bd4ef 13163
c19d1205
ZW		 13164static void
13165do_t_mvn_tst (void)
13166{
fdfde340 13167 unsigned Rn, Rm;
c921be7d 13168
fdfde340
JM		 13169 Rn = inst.operands[0].reg;
13170 Rm = inst.operands[1].reg;
13171
13172 if (inst.instruction == T_MNEM_cmp
13173 || inst.instruction == T_MNEM_cmn)
13174 constraint (Rn == REG_PC, BAD_PC);
13175 else
13176 reject_bad_reg (Rn);
13177 reject_bad_reg (Rm);
13178
c19d1205
ZW		 13179 if (unified_syntax)
13180 {
13181 int r0off = (inst.instruction == T_MNEM_mvn
13182 || inst.instruction == T_MNEM_mvns) ? 8 : 16;
3d388997
PB		 13183 bfd_boolean narrow;
13184
13185 if (inst.size_req == 4
13186 || inst.instruction > 0xffff
13187 || inst.operands[1].shifted
fdfde340 13188 || Rn > 7 || Rm > 7)
3d388997 13189 narrow = FALSE;
fe8b4cc3
KT		 13190 else if (inst.instruction == T_MNEM_cmn
13191 || inst.instruction == T_MNEM_tst)
3d388997
PB		 13192 narrow = TRUE;
13193 else if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13194 narrow = !in_pred_block ();
3d388997 13195 else
5ee91343 13196 narrow = in_pred_block ();
3d388997 13197
c19d1205 13198 if (!inst.operands[1].isreg)
b99bd4ef 13199 {
c19d1205
ZW		 13200 /* For an immediate, we always generate a 32-bit opcode;
13201 section relaxation will shrink it later if possible. */
13202 if (inst.instruction < 0xffff)
13203 inst.instruction = THUMB_OP32 (inst.instruction);
13204 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
fdfde340 13205 inst.instruction |= Rn << r0off;
e2b0ab59 13206 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
b99bd4ef 13207 }
c19d1205 13208 else
b99bd4ef 13209 {
c19d1205 13210 /* See if we can do this with a 16-bit instruction. */
3d388997 13211 if (narrow)
b99bd4ef 13212 {
c19d1205 13213 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13214 inst.instruction |= Rn;
13215 inst.instruction |= Rm << 3;
b99bd4ef 13216 }
c19d1205 13217 else
b99bd4ef 13218 {
c19d1205
ZW		 13219 constraint (inst.operands[1].shifted
13220 && inst.operands[1].immisreg,
13221 _("shift must be constant"));
13222 if (inst.instruction < 0xffff)
13223 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340 13224 inst.instruction |= Rn << r0off;
c19d1205 13225 encode_thumb32_shifted_operand (1);
b99bd4ef 13226 }
b99bd4ef
NC		 13227 }
13228 }
13229 else
13230 {
c19d1205
ZW		 13231 constraint (inst.instruction > 0xffff
13232 || inst.instruction == T_MNEM_mvns, BAD_THUMB32);
13233 constraint (!inst.operands[1].isreg || inst.operands[1].shifted,
13234 _("unshifted register required"));
fdfde340 13235 constraint (Rn > 7 || Rm > 7,
c19d1205 13236 BAD_HIREG);
b99bd4ef 13237
c19d1205 13238 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13239 inst.instruction |= Rn;
13240 inst.instruction |= Rm << 3;
b99bd4ef 13241 }
b99bd4ef
NC		 13242}
13243
b05fe5cf 13244static void
c19d1205 13245do_t_mrs (void)
b05fe5cf 13246{
fdfde340 13247 unsigned Rd;
037e8744
JB		 13248
13249 if (do_vfp_nsyn_mrs () == SUCCESS)
13250 return;
13251
90ec0d68
MGD		 13252 Rd = inst.operands[0].reg;
13253 reject_bad_reg (Rd);
13254 inst.instruction |= Rd << 8;
13255
13256 if (inst.operands[1].isreg)
62b3e311 13257 {
90ec0d68
MGD		 13258 unsigned br = inst.operands[1].reg;
13259 if (((br & 0x200) == 0) && ((br & 0xf000) != 0xf000))
13260 as_bad (_("bad register for mrs"));
13261
13262 inst.instruction |= br & (0xf << 16);
13263 inst.instruction |= (br & 0x300) >> 4;
13264 inst.instruction |= (br & SPSR_BIT) >> 2;
62b3e311
PB		 13265 }
13266 else
13267 {
90ec0d68 13268 int flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
5f4273c7 13269
d2cd1205 13270 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
1a43faaf
NC		 13271 {
13272 /* PR gas/12698: The constraint is only applied for m_profile.
13273 If the user has specified -march=all, we want to ignore it as
13274 we are building for any CPU type, including non-m variants. */
823d2571
TG		 13275 bfd_boolean m_profile =
13276 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf
NC		 13277 constraint ((flags != 0) && m_profile, _("selected processor does "
13278 "not support requested special purpose register"));
13279 }
90ec0d68 13280 else
d2cd1205
JB		 13281 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13282 devices). */
13283 constraint ((flags & ~SPSR_BIT) != (PSR_c|PSR_f),
13284 _("'APSR', 'CPSR' or 'SPSR' expected"));
fdfde340 13285
90ec0d68
MGD		 13286 inst.instruction |= (flags & SPSR_BIT) >> 2;
13287 inst.instruction |= inst.operands[1].imm & 0xff;
13288 inst.instruction |= 0xf0000;
13289 }
c19d1205 13290}
b05fe5cf 13291
c19d1205
ZW		 13292static void
13293do_t_msr (void)
13294{
62b3e311 13295 int flags;
fdfde340 13296 unsigned Rn;
62b3e311 13297
037e8744
JB		 13298 if (do_vfp_nsyn_msr () == SUCCESS)
13299 return;
13300
c19d1205
ZW		 13301 constraint (!inst.operands[1].isreg,
13302 _("Thumb encoding does not support an immediate here"));
90ec0d68
MGD		 13303
13304 if (inst.operands[0].isreg)
13305 flags = (int)(inst.operands[0].reg);
13306 else
13307 flags = inst.operands[0].imm;
13308
d2cd1205 13309 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_m))
62b3e311 13310 {
d2cd1205
JB		 13311 int bits = inst.operands[0].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
13312
1a43faaf 13313 /* PR gas/12698: The constraint is only applied for m_profile.
477330fc
RM		 13314 If the user has specified -march=all, we want to ignore it as
13315 we are building for any CPU type, including non-m variants. */
823d2571
TG		 13316 bfd_boolean m_profile =
13317 !ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any);
1a43faaf 13318 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
477330fc
RM		 13319 && (bits & ~(PSR_s | PSR_f)) != 0)
13320 || (!ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6_dsp)
13321 && bits != PSR_f)) && m_profile,
13322 _("selected processor does not support requested special "
13323 "purpose register"));
62b3e311
PB		 13324 }
13325 else
d2cd1205
JB		 13326 constraint ((flags & 0xff) != 0, _("selected processor does not support "
13327 "requested special purpose register"));
c921be7d 13328
fdfde340
JM		 13329 Rn = inst.operands[1].reg;
13330 reject_bad_reg (Rn);
13331
62b3e311 13332 inst.instruction |= (flags & SPSR_BIT) >> 2;
90ec0d68
MGD		 13333 inst.instruction |= (flags & 0xf0000) >> 8;
13334 inst.instruction |= (flags & 0x300) >> 4;
62b3e311 13335 inst.instruction |= (flags & 0xff);
fdfde340 13336 inst.instruction |= Rn << 16;
c19d1205 13337}
b05fe5cf 13338
c19d1205
ZW		 13339static void
13340do_t_mul (void)
13341{
17828f45 13342 bfd_boolean narrow;
fdfde340 13343 unsigned Rd, Rn, Rm;
17828f45 13344
c19d1205
ZW		 13345 if (!inst.operands[2].present)
13346 inst.operands[2].reg = inst.operands[0].reg;
b05fe5cf 13347
fdfde340
JM		 13348 Rd = inst.operands[0].reg;
13349 Rn = inst.operands[1].reg;
13350 Rm = inst.operands[2].reg;
13351
17828f45 13352 if (unified_syntax)
b05fe5cf 13353 {
17828f45 13354 if (inst.size_req == 4
fdfde340
JM		 13355 || (Rd != Rn
13356 && Rd != Rm)
13357 || Rn > 7
13358 || Rm > 7)
17828f45
JM		 13359 narrow = FALSE;
13360 else if (inst.instruction == T_MNEM_muls)
5ee91343 13361 narrow = !in_pred_block ();
17828f45 13362 else
5ee91343 13363 narrow = in_pred_block ();
b05fe5cf 13364 }
c19d1205 13365 else
b05fe5cf 13366 {
17828f45 13367 constraint (inst.instruction == T_MNEM_muls, BAD_THUMB32);
fdfde340 13368 constraint (Rn > 7 || Rm > 7,
c19d1205 13369 BAD_HIREG);
17828f45
JM		 13370 narrow = TRUE;
13371 }
b05fe5cf 13372
17828f45
JM		 13373 if (narrow)
13374 {
13375 /* 16-bit MULS/Conditional MUL. */
c19d1205 13376 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340 13377 inst.instruction |= Rd;
b05fe5cf 13378
fdfde340
JM		 13379 if (Rd == Rn)
13380 inst.instruction |= Rm << 3;
13381 else if (Rd == Rm)
13382 inst.instruction |= Rn << 3;
c19d1205
ZW		 13383 else
13384 constraint (1, _("dest must overlap one source register"));
13385 }
17828f45
JM		 13386 else
13387 {
e07e6e58
NC		 13388 constraint (inst.instruction != T_MNEM_mul,
13389 _("Thumb-2 MUL must not set flags"));
17828f45
JM		 13390 /* 32-bit MUL. */
13391 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 13392 inst.instruction |= Rd << 8;
13393 inst.instruction |= Rn << 16;
13394 inst.instruction |= Rm << 0;
13395
13396 reject_bad_reg (Rd);
13397 reject_bad_reg (Rn);
13398 reject_bad_reg (Rm);
17828f45 13399 }
c19d1205 13400}
b05fe5cf 13401
c19d1205
ZW		 13402static void
13403do_t_mull (void)
13404{
fdfde340 13405 unsigned RdLo, RdHi, Rn, Rm;
b05fe5cf 13406
fdfde340
JM		 13407 RdLo = inst.operands[0].reg;
13408 RdHi = inst.operands[1].reg;
13409 Rn = inst.operands[2].reg;
13410 Rm = inst.operands[3].reg;
13411
13412 reject_bad_reg (RdLo);
13413 reject_bad_reg (RdHi);
13414 reject_bad_reg (Rn);
13415 reject_bad_reg (Rm);
13416
13417 inst.instruction |= RdLo << 12;
13418 inst.instruction |= RdHi << 8;
13419 inst.instruction |= Rn << 16;
13420 inst.instruction |= Rm;
13421
13422 if (RdLo == RdHi)
c19d1205
ZW		 13423 as_tsktsk (_("rdhi and rdlo must be different"));
13424}
b05fe5cf 13425
c19d1205
ZW		 13426static void
13427do_t_nop (void)
13428{
5ee91343 13429 set_pred_insn_type (NEUTRAL_IT_INSN);
e07e6e58 13430
c19d1205
ZW		 13431 if (unified_syntax)
13432 {
13433 if (inst.size_req == 4 || inst.operands[0].imm > 15)
b05fe5cf 13434 {
c19d1205
ZW		 13435 inst.instruction = THUMB_OP32 (inst.instruction);
13436 inst.instruction |= inst.operands[0].imm;
13437 }
13438 else
13439 {
bc2d1808
NC		 13440 /* PR9722: Check for Thumb2 availability before
13441 generating a thumb2 nop instruction. */
afa62d5e 13442 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2))
bc2d1808
NC		 13443 {
13444 inst.instruction = THUMB_OP16 (inst.instruction);
13445 inst.instruction |= inst.operands[0].imm << 4;
13446 }
13447 else
13448 inst.instruction = 0x46c0;
c19d1205
ZW		 13449 }
13450 }
13451 else
13452 {
13453 constraint (inst.operands[0].present,
13454 _("Thumb does not support NOP with hints"));
13455 inst.instruction = 0x46c0;
13456 }
13457}
b05fe5cf 13458
c19d1205
ZW		 13459static void
13460do_t_neg (void)
13461{
13462 if (unified_syntax)
13463 {
3d388997
PB		 13464 bfd_boolean narrow;
13465
13466 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13467 narrow = !in_pred_block ();
3d388997 13468 else
5ee91343 13469 narrow = in_pred_block ();
3d388997
PB		 13470 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13471 narrow = FALSE;
13472 if (inst.size_req == 4)
13473 narrow = FALSE;
13474
13475 if (!narrow)
c19d1205
ZW		 13476 {
13477 inst.instruction = THUMB_OP32 (inst.instruction);
13478 inst.instruction |= inst.operands[0].reg << 8;
13479 inst.instruction |= inst.operands[1].reg << 16;
b05fe5cf
ZW		 13480 }
13481 else
13482 {
c19d1205
ZW		 13483 inst.instruction = THUMB_OP16 (inst.instruction);
13484 inst.instruction |= inst.operands[0].reg;
13485 inst.instruction |= inst.operands[1].reg << 3;
b05fe5cf
ZW		 13486 }
13487 }
13488 else
13489 {
c19d1205
ZW		 13490 constraint (inst.operands[0].reg > 7 || inst.operands[1].reg > 7,
13491 BAD_HIREG);
13492 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
13493
13494 inst.instruction = THUMB_OP16 (inst.instruction);
13495 inst.instruction |= inst.operands[0].reg;
13496 inst.instruction |= inst.operands[1].reg << 3;
13497 }
13498}
13499
1c444d06
JM		 13500static void
13501do_t_orn (void)
13502{
13503 unsigned Rd, Rn;
13504
13505 Rd = inst.operands[0].reg;
13506 Rn = inst.operands[1].present ? inst.operands[1].reg : Rd;
13507
fdfde340
JM		 13508 reject_bad_reg (Rd);
13509 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13510 reject_bad_reg (Rn);
13511
1c444d06
JM		 13512 inst.instruction |= Rd << 8;
13513 inst.instruction |= Rn << 16;
13514
13515 if (!inst.operands[2].isreg)
13516 {
13517 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13518 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
1c444d06
JM		 13519 }
13520 else
13521 {
13522 unsigned Rm;
13523
13524 Rm = inst.operands[2].reg;
fdfde340 13525 reject_bad_reg (Rm);
1c444d06
JM		 13526
13527 constraint (inst.operands[2].shifted
13528 && inst.operands[2].immisreg,
13529 _("shift must be constant"));
13530 encode_thumb32_shifted_operand (2);
13531 }
13532}
13533
c19d1205
ZW		 13534static void
13535do_t_pkhbt (void)
13536{
fdfde340
JM		 13537 unsigned Rd, Rn, Rm;
13538
13539 Rd = inst.operands[0].reg;
13540 Rn = inst.operands[1].reg;
13541 Rm = inst.operands[2].reg;
13542
13543 reject_bad_reg (Rd);
13544 reject_bad_reg (Rn);
13545 reject_bad_reg (Rm);
13546
13547 inst.instruction |= Rd << 8;
13548 inst.instruction |= Rn << 16;
13549 inst.instruction |= Rm;
c19d1205
ZW		 13550 if (inst.operands[3].present)
13551 {
e2b0ab59
AV		 13552 unsigned int val = inst.relocs[0].exp.X_add_number;
13553 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205
ZW		 13554 _("expression too complex"));
13555 inst.instruction |= (val & 0x1c) << 10;
13556 inst.instruction |= (val & 0x03) << 6;
b05fe5cf 13557 }
c19d1205 13558}
b05fe5cf 13559
c19d1205
ZW		 13560static void
13561do_t_pkhtb (void)
13562{
13563 if (!inst.operands[3].present)
1ef52f49
NC		 13564 {
13565 unsigned Rtmp;
13566
13567 inst.instruction &= ~0x00000020;
13568
13569 /* PR 10168. Swap the Rm and Rn registers. */
13570 Rtmp = inst.operands[1].reg;
13571 inst.operands[1].reg = inst.operands[2].reg;
13572 inst.operands[2].reg = Rtmp;
13573 }
c19d1205 13574 do_t_pkhbt ();
b05fe5cf
ZW		 13575}
13576
c19d1205
ZW		 13577static void
13578do_t_pld (void)
13579{
fdfde340
JM		 13580 if (inst.operands[0].immisreg)
13581 reject_bad_reg (inst.operands[0].imm);
13582
c19d1205
ZW		 13583 encode_thumb32_addr_mode (0, /*is_t=*/FALSE, /*is_d=*/FALSE);
13584}
b05fe5cf 13585
c19d1205
ZW		 13586static void
13587do_t_push_pop (void)
b99bd4ef 13588{
e9f89963 13589 unsigned mask;
5f4273c7 13590
c19d1205
ZW		 13591 constraint (inst.operands[0].writeback,
13592 _("push/pop do not support {reglist}^"));
e2b0ab59 13593 constraint (inst.relocs[0].type != BFD_RELOC_UNUSED,
c19d1205 13594 _("expression too complex"));
b99bd4ef 13595
e9f89963 13596 mask = inst.operands[0].imm;
d3bfe16e 13597 if (inst.size_req != 4 && (mask & ~0xff) == 0)
3c707909 13598 inst.instruction = THUMB_OP16 (inst.instruction) | mask;
d3bfe16e 13599 else if (inst.size_req != 4
c6025a80 13600 && (mask & ~0xff) == (1U << (inst.instruction == T_MNEM_push
d3bfe16e 13601 ? REG_LR : REG_PC)))
b99bd4ef 13602 {
c19d1205
ZW		 13603 inst.instruction = THUMB_OP16 (inst.instruction);
13604 inst.instruction |= THUMB_PP_PC_LR;
3c707909 13605 inst.instruction |= mask & 0xff;
c19d1205
ZW		 13606 }
13607 else if (unified_syntax)
13608 {
3c707909 13609 inst.instruction = THUMB_OP32 (inst.instruction);
4b5a202f
AV		 13610 encode_thumb2_multi (TRUE /* do_io */, 13, mask, TRUE);
13611 }
13612 else
13613 {
13614 inst.error = _("invalid register list to push/pop instruction");
13615 return;
c19d1205 13616 }
4b5a202f
AV		 13617}
13618
13619static void
13620do_t_clrm (void)
13621{
13622 if (unified_syntax)
13623 encode_thumb2_multi (FALSE /* do_io */, -1, inst.operands[0].imm, FALSE);
c19d1205
ZW		 13624 else
13625 {
13626 inst.error = _("invalid register list to push/pop instruction");
13627 return;
13628 }
c19d1205 13629}
b99bd4ef 13630
efd6b359
AV		 13631static void
13632do_t_vscclrm (void)
13633{
13634 if (inst.operands[0].issingle)
13635 {
13636 inst.instruction |= (inst.operands[0].reg & 0x1) << 22;
13637 inst.instruction |= (inst.operands[0].reg & 0x1e) << 11;
13638 inst.instruction |= inst.operands[0].imm;
13639 }
13640 else
13641 {
13642 inst.instruction |= (inst.operands[0].reg & 0x10) << 18;
13643 inst.instruction |= (inst.operands[0].reg & 0xf) << 12;
13644 inst.instruction |= 1 << 8;
13645 inst.instruction |= inst.operands[0].imm << 1;
13646 }
13647}
13648
c19d1205
ZW		 13649static void
13650do_t_rbit (void)
13651{
fdfde340
JM		 13652 unsigned Rd, Rm;
13653
13654 Rd = inst.operands[0].reg;
13655 Rm = inst.operands[1].reg;
13656
13657 reject_bad_reg (Rd);
13658 reject_bad_reg (Rm);
13659
13660 inst.instruction |= Rd << 8;
13661 inst.instruction |= Rm << 16;
13662 inst.instruction |= Rm;
c19d1205 13663}
b99bd4ef 13664
c19d1205
ZW		 13665static void
13666do_t_rev (void)
13667{
fdfde340
JM		 13668 unsigned Rd, Rm;
13669
13670 Rd = inst.operands[0].reg;
13671 Rm = inst.operands[1].reg;
13672
13673 reject_bad_reg (Rd);
13674 reject_bad_reg (Rm);
13675
13676 if (Rd <= 7 && Rm <= 7
c19d1205
ZW		 13677 && inst.size_req != 4)
13678 {
13679 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 13680 inst.instruction |= Rd;
13681 inst.instruction |= Rm << 3;
c19d1205
ZW		 13682 }
13683 else if (unified_syntax)
13684 {
13685 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 13686 inst.instruction |= Rd << 8;
13687 inst.instruction |= Rm << 16;
13688 inst.instruction |= Rm;
c19d1205
ZW		 13689 }
13690 else
13691 inst.error = BAD_HIREG;
13692}
b99bd4ef 13693
1c444d06
JM		 13694static void
13695do_t_rrx (void)
13696{
13697 unsigned Rd, Rm;
13698
13699 Rd = inst.operands[0].reg;
13700 Rm = inst.operands[1].reg;
13701
fdfde340
JM		 13702 reject_bad_reg (Rd);
13703 reject_bad_reg (Rm);
c921be7d 13704
1c444d06
JM		 13705 inst.instruction |= Rd << 8;
13706 inst.instruction |= Rm;
13707}
13708
c19d1205
ZW		 13709static void
13710do_t_rsb (void)
13711{
fdfde340 13712 unsigned Rd, Rs;
b99bd4ef 13713
c19d1205
ZW		 13714 Rd = inst.operands[0].reg;
13715 Rs = (inst.operands[1].present
13716 ? inst.operands[1].reg /* Rd, Rs, foo */
13717 : inst.operands[0].reg); /* Rd, foo -> Rd, Rd, foo */
b99bd4ef 13718
fdfde340
JM		 13719 reject_bad_reg (Rd);
13720 reject_bad_reg (Rs);
13721 if (inst.operands[2].isreg)
13722 reject_bad_reg (inst.operands[2].reg);
13723
c19d1205
ZW		 13724 inst.instruction |= Rd << 8;
13725 inst.instruction |= Rs << 16;
13726 if (!inst.operands[2].isreg)
13727 {
026d3abb
PB		 13728 bfd_boolean narrow;
13729
13730 if ((inst.instruction & 0x00100000) != 0)
5ee91343 13731 narrow = !in_pred_block ();
026d3abb 13732 else
5ee91343 13733 narrow = in_pred_block ();
026d3abb
PB		 13734
13735 if (Rd > 7 || Rs > 7)
13736 narrow = FALSE;
13737
13738 if (inst.size_req == 4 || !unified_syntax)
13739 narrow = FALSE;
13740
e2b0ab59
AV		 13741 if (inst.relocs[0].exp.X_op != O_constant
13742 || inst.relocs[0].exp.X_add_number != 0)
026d3abb
PB		 13743 narrow = FALSE;
13744
13745 /* Turn rsb #0 into 16-bit neg. We should probably do this via
477330fc 13746 relaxation, but it doesn't seem worth the hassle. */
026d3abb
PB		 13747 if (narrow)
13748 {
e2b0ab59 13749 inst.relocs[0].type = BFD_RELOC_UNUSED;
026d3abb
PB		 13750 inst.instruction = THUMB_OP16 (T_MNEM_negs);
13751 inst.instruction |= Rs << 3;
13752 inst.instruction |= Rd;
13753 }
13754 else
13755 {
13756 inst.instruction = (inst.instruction & 0xe1ffffff) | 0x10000000;
e2b0ab59 13757 inst.relocs[0].type = BFD_RELOC_ARM_T32_IMMEDIATE;
026d3abb 13758 }
c19d1205
ZW		 13759 }
13760 else
13761 encode_thumb32_shifted_operand (2);
13762}
b99bd4ef 13763
c19d1205
ZW		 13764static void
13765do_t_setend (void)
13766{
12e37cbc
MGD		 13767 if (warn_on_deprecated
13768 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
5c3696f8 13769 as_tsktsk (_("setend use is deprecated for ARMv8"));
12e37cbc 13770
5ee91343 13771 set_pred_insn_type (OUTSIDE_PRED_INSN);
c19d1205
ZW		 13772 if (inst.operands[0].imm)
13773 inst.instruction |= 0x8;
13774}
b99bd4ef 13775
c19d1205
ZW		 13776static void
13777do_t_shift (void)
13778{
13779 if (!inst.operands[1].present)
13780 inst.operands[1].reg = inst.operands[0].reg;
13781
13782 if (unified_syntax)
13783 {
3d388997
PB		 13784 bfd_boolean narrow;
13785 int shift_kind;
13786
13787 switch (inst.instruction)
13788 {
13789 case T_MNEM_asr:
13790 case T_MNEM_asrs: shift_kind = SHIFT_ASR; break;
13791 case T_MNEM_lsl:
13792 case T_MNEM_lsls: shift_kind = SHIFT_LSL; break;
13793 case T_MNEM_lsr:
13794 case T_MNEM_lsrs: shift_kind = SHIFT_LSR; break;
13795 case T_MNEM_ror:
13796 case T_MNEM_rors: shift_kind = SHIFT_ROR; break;
13797 default: abort ();
13798 }
13799
13800 if (THUMB_SETS_FLAGS (inst.instruction))
5ee91343 13801 narrow = !in_pred_block ();
3d388997 13802 else
5ee91343 13803 narrow = in_pred_block ();
3d388997
PB		 13804 if (inst.operands[0].reg > 7 || inst.operands[1].reg > 7)
13805 narrow = FALSE;
13806 if (!inst.operands[2].isreg && shift_kind == SHIFT_ROR)
13807 narrow = FALSE;
13808 if (inst.operands[2].isreg
13809 && (inst.operands[1].reg != inst.operands[0].reg
13810 || inst.operands[2].reg > 7))
13811 narrow = FALSE;
13812 if (inst.size_req == 4)
13813 narrow = FALSE;
13814
fdfde340
JM		 13815 reject_bad_reg (inst.operands[0].reg);
13816 reject_bad_reg (inst.operands[1].reg);
c921be7d 13817
3d388997 13818 if (!narrow)
c19d1205
ZW		 13819 {
13820 if (inst.operands[2].isreg)
b99bd4ef 13821 {
fdfde340 13822 reject_bad_reg (inst.operands[2].reg);
c19d1205
ZW		 13823 inst.instruction = THUMB_OP32 (inst.instruction);
13824 inst.instruction |= inst.operands[0].reg << 8;
13825 inst.instruction |= inst.operands[1].reg << 16;
13826 inst.instruction |= inst.operands[2].reg;
94342ec3
NC		 13827
13828 /* PR 12854: Error on extraneous shifts. */
13829 constraint (inst.operands[2].shifted,
13830 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 13831 }
13832 else
13833 {
13834 inst.operands[1].shifted = 1;
3d388997 13835 inst.operands[1].shift_kind = shift_kind;
c19d1205
ZW		 13836 inst.instruction = THUMB_OP32 (THUMB_SETS_FLAGS (inst.instruction)
13837 ? T_MNEM_movs : T_MNEM_mov);
13838 inst.instruction |= inst.operands[0].reg << 8;
13839 encode_thumb32_shifted_operand (1);
13840 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
e2b0ab59 13841 inst.relocs[0].type = BFD_RELOC_UNUSED;
b99bd4ef
NC		 13842 }
13843 }
13844 else
13845 {
c19d1205 13846 if (inst.operands[2].isreg)
b99bd4ef 13847 {
3d388997 13848 switch (shift_kind)
b99bd4ef 13849 {
3d388997
PB		 13850 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_R; break;
13851 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_R; break;
13852 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_R; break;
13853 case SHIFT_ROR: inst.instruction = T_OPCODE_ROR_R; break;
c19d1205 13854 default: abort ();
b99bd4ef 13855 }
5f4273c7 13856
c19d1205
ZW		 13857 inst.instruction |= inst.operands[0].reg;
13858 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 13859
13860 /* PR 12854: Error on extraneous shifts. */
13861 constraint (inst.operands[2].shifted,
13862 _("extraneous shift as part of operand to shift insn"));
b99bd4ef
NC		 13863 }
13864 else
13865 {
3d388997 13866 switch (shift_kind)
b99bd4ef 13867 {
3d388997
PB		 13868 case SHIFT_ASR: inst.instruction = T_OPCODE_ASR_I; break;
13869 case SHIFT_LSL: inst.instruction = T_OPCODE_LSL_I; break;
13870 case SHIFT_LSR: inst.instruction = T_OPCODE_LSR_I; break;
c19d1205 13871 default: abort ();
b99bd4ef 13872 }
e2b0ab59 13873 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW		 13874 inst.instruction |= inst.operands[0].reg;
13875 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 13876 }
13877 }
c19d1205
ZW		 13878 }
13879 else
13880 {
13881 constraint (inst.operands[0].reg > 7
13882 || inst.operands[1].reg > 7, BAD_HIREG);
13883 constraint (THUMB_SETS_FLAGS (inst.instruction), BAD_THUMB32);
b99bd4ef 13884
c19d1205
ZW		 13885 if (inst.operands[2].isreg) /* Rd, {Rs,} Rn */
13886 {
13887 constraint (inst.operands[2].reg > 7, BAD_HIREG);
13888 constraint (inst.operands[0].reg != inst.operands[1].reg,
13889 _("source1 and dest must be same register"));
b99bd4ef 13890
c19d1205
ZW		 13891 switch (inst.instruction)
13892 {
13893 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_R; break;
13894 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_R; break;
13895 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_R; break;
13896 case T_MNEM_ror: inst.instruction = T_OPCODE_ROR_R; break;
13897 default: abort ();
13898 }
5f4273c7 13899
c19d1205
ZW		 13900 inst.instruction |= inst.operands[0].reg;
13901 inst.instruction |= inst.operands[2].reg << 3;
af199b06
NC		 13902
13903 /* PR 12854: Error on extraneous shifts. */
13904 constraint (inst.operands[2].shifted,
13905 _("extraneous shift as part of operand to shift insn"));
c19d1205
ZW		 13906 }
13907 else
b99bd4ef 13908 {
c19d1205
ZW		 13909 switch (inst.instruction)
13910 {
13911 case T_MNEM_asr: inst.instruction = T_OPCODE_ASR_I; break;
13912 case T_MNEM_lsl: inst.instruction = T_OPCODE_LSL_I; break;
13913 case T_MNEM_lsr: inst.instruction = T_OPCODE_LSR_I; break;
13914 case T_MNEM_ror: inst.error = _("ror #imm not supported"); return;
13915 default: abort ();
13916 }
e2b0ab59 13917 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_SHIFT;
c19d1205
ZW		 13918 inst.instruction |= inst.operands[0].reg;
13919 inst.instruction |= inst.operands[1].reg << 3;
b99bd4ef
NC		 13920 }
13921 }
b99bd4ef
NC		 13922}
13923
13924static void
c19d1205 13925do_t_simd (void)
b99bd4ef 13926{
fdfde340
JM		 13927 unsigned Rd, Rn, Rm;
13928
13929 Rd = inst.operands[0].reg;
13930 Rn = inst.operands[1].reg;
13931 Rm = inst.operands[2].reg;
13932
13933 reject_bad_reg (Rd);
13934 reject_bad_reg (Rn);
13935 reject_bad_reg (Rm);
13936
13937 inst.instruction |= Rd << 8;
13938 inst.instruction |= Rn << 16;
13939 inst.instruction |= Rm;
c19d1205 13940}
b99bd4ef 13941
03ee1b7f
NC		 13942static void
13943do_t_simd2 (void)
13944{
13945 unsigned Rd, Rn, Rm;
13946
13947 Rd = inst.operands[0].reg;
13948 Rm = inst.operands[1].reg;
13949 Rn = inst.operands[2].reg;
13950
13951 reject_bad_reg (Rd);
13952 reject_bad_reg (Rn);
13953 reject_bad_reg (Rm);
13954
13955 inst.instruction |= Rd << 8;
13956 inst.instruction |= Rn << 16;
13957 inst.instruction |= Rm;
13958}
13959
c19d1205 13960static void
3eb17e6b 13961do_t_smc (void)
c19d1205 13962{
e2b0ab59 13963 unsigned int value = inst.relocs[0].exp.X_add_number;
f4c65163
MGD		 13964 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7a),
13965 _("SMC is not permitted on this architecture"));
e2b0ab59 13966 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 13967 _("expression too complex"));
ba85f98c
BW		 13968 constraint (value > 0xf, _("immediate too large (bigger than 0xF)"));
13969
e2b0ab59 13970 inst.relocs[0].type = BFD_RELOC_UNUSED;
c19d1205 13971 inst.instruction |= (value & 0x000f) << 16;
ba85f98c 13972
24382199 13973 /* PR gas/15623: SMC instructions must be last in an IT block. */
5ee91343 13974 set_pred_insn_type_last ();
c19d1205 13975}
b99bd4ef 13976
90ec0d68
MGD		 13977static void
13978do_t_hvc (void)
13979{
e2b0ab59 13980 unsigned int value = inst.relocs[0].exp.X_add_number;
90ec0d68 13981
e2b0ab59 13982 inst.relocs[0].type = BFD_RELOC_UNUSED;
90ec0d68
MGD		 13983 inst.instruction |= (value & 0x0fff);
13984 inst.instruction |= (value & 0xf000) << 4;
13985}
13986
c19d1205 13987static void
3a21c15a 13988do_t_ssat_usat (int bias)
c19d1205 13989{
fdfde340
JM		 13990 unsigned Rd, Rn;
13991
13992 Rd = inst.operands[0].reg;
13993 Rn = inst.operands[2].reg;
13994
13995 reject_bad_reg (Rd);
13996 reject_bad_reg (Rn);
13997
13998 inst.instruction |= Rd << 8;
3a21c15a 13999 inst.instruction |= inst.operands[1].imm - bias;
fdfde340 14000 inst.instruction |= Rn << 16;
b99bd4ef 14001
c19d1205 14002 if (inst.operands[3].present)
b99bd4ef 14003 {
e2b0ab59 14004 offsetT shift_amount = inst.relocs[0].exp.X_add_number;
3a21c15a 14005
e2b0ab59 14006 inst.relocs[0].type = BFD_RELOC_UNUSED;
3a21c15a 14007
e2b0ab59 14008 constraint (inst.relocs[0].exp.X_op != O_constant,
c19d1205 14009 _("expression too complex"));
b99bd4ef 14010
3a21c15a 14011 if (shift_amount != 0)
6189168b 14012 {
3a21c15a
NC		 14013 constraint (shift_amount > 31,
14014 _("shift expression is too large"));
14015
c19d1205 14016 if (inst.operands[3].shift_kind == SHIFT_ASR)
3a21c15a
NC		 14017 inst.instruction |= 0x00200000; /* sh bit. */
14018
14019 inst.instruction |= (shift_amount & 0x1c) << 10;
14020 inst.instruction |= (shift_amount & 0x03) << 6;
6189168b
NC		 14021 }
14022 }
b99bd4ef 14023}
c921be7d 14024
3a21c15a
NC		 14025static void
14026do_t_ssat (void)
14027{
14028 do_t_ssat_usat (1);
14029}
b99bd4ef 14030
0dd132b6 14031static void
c19d1205 14032do_t_ssat16 (void)
0dd132b6 14033{
fdfde340
JM		 14034 unsigned Rd, Rn;
14035
14036 Rd = inst.operands[0].reg;
14037 Rn = inst.operands[2].reg;
14038
14039 reject_bad_reg (Rd);
14040 reject_bad_reg (Rn);
14041
14042 inst.instruction |= Rd << 8;
c19d1205 14043 inst.instruction |= inst.operands[1].imm - 1;
fdfde340 14044 inst.instruction |= Rn << 16;
c19d1205 14045}
0dd132b6 14046
c19d1205
ZW		 14047static void
14048do_t_strex (void)
14049{
14050 constraint (!inst.operands[2].isreg || !inst.operands[2].preind
14051 || inst.operands[2].postind || inst.operands[2].writeback
14052 || inst.operands[2].immisreg || inst.operands[2].shifted
14053 || inst.operands[2].negative,
01cfc07f 14054 BAD_ADDR_MODE);
0dd132b6 14055
5be8be5d
DG		 14056 constraint (inst.operands[2].reg == REG_PC, BAD_PC);
14057
c19d1205
ZW		 14058 inst.instruction |= inst.operands[0].reg << 8;
14059 inst.instruction |= inst.operands[1].reg << 12;
14060 inst.instruction |= inst.operands[2].reg << 16;
e2b0ab59 14061 inst.relocs[0].type = BFD_RELOC_ARM_T32_OFFSET_U8;
0dd132b6
NC		 14062}
14063
b99bd4ef 14064static void
c19d1205 14065do_t_strexd (void)
b99bd4ef 14066{
c19d1205
ZW		 14067 if (!inst.operands[2].present)
14068 inst.operands[2].reg = inst.operands[1].reg + 1;
b99bd4ef 14069
c19d1205
ZW		 14070 constraint (inst.operands[0].reg == inst.operands[1].reg
14071 || inst.operands[0].reg == inst.operands[2].reg
f8a8e9d6 14072 || inst.operands[0].reg == inst.operands[3].reg,
c19d1205 14073 BAD_OVERLAP);
b99bd4ef 14074
c19d1205
ZW		 14075 inst.instruction |= inst.operands[0].reg;
14076 inst.instruction |= inst.operands[1].reg << 12;
14077 inst.instruction |= inst.operands[2].reg << 8;
14078 inst.instruction |= inst.operands[3].reg << 16;
b99bd4ef
NC		 14079}
14080
14081static void
c19d1205 14082do_t_sxtah (void)
b99bd4ef 14083{
fdfde340
JM		 14084 unsigned Rd, Rn, Rm;
14085
14086 Rd = inst.operands[0].reg;
14087 Rn = inst.operands[1].reg;
14088 Rm = inst.operands[2].reg;
14089
14090 reject_bad_reg (Rd);
14091 reject_bad_reg (Rn);
14092 reject_bad_reg (Rm);
14093
14094 inst.instruction |= Rd << 8;
14095 inst.instruction |= Rn << 16;
14096 inst.instruction |= Rm;
c19d1205
ZW		 14097 inst.instruction |= inst.operands[3].imm << 4;
14098}
b99bd4ef 14099
c19d1205
ZW		 14100static void
14101do_t_sxth (void)
14102{
fdfde340
JM		 14103 unsigned Rd, Rm;
14104
14105 Rd = inst.operands[0].reg;
14106 Rm = inst.operands[1].reg;
14107
14108 reject_bad_reg (Rd);
14109 reject_bad_reg (Rm);
c921be7d
NC		 14110
14111 if (inst.instruction <= 0xffff
14112 && inst.size_req != 4
fdfde340 14113 && Rd <= 7 && Rm <= 7
c19d1205 14114 && (!inst.operands[2].present || inst.operands[2].imm == 0))
b99bd4ef 14115 {
c19d1205 14116 inst.instruction = THUMB_OP16 (inst.instruction);
fdfde340
JM		 14117 inst.instruction |= Rd;
14118 inst.instruction |= Rm << 3;
b99bd4ef 14119 }
c19d1205 14120 else if (unified_syntax)
b99bd4ef 14121 {
c19d1205
ZW		 14122 if (inst.instruction <= 0xffff)
14123 inst.instruction = THUMB_OP32 (inst.instruction);
fdfde340
JM		 14124 inst.instruction |= Rd << 8;
14125 inst.instruction |= Rm;
c19d1205 14126 inst.instruction |= inst.operands[2].imm << 4;
b99bd4ef 14127 }
c19d1205 14128 else
b99bd4ef 14129 {
c19d1205
ZW		 14130 constraint (inst.operands[2].present && inst.operands[2].imm != 0,
14131 _("Thumb encoding does not support rotation"));
14132 constraint (1, BAD_HIREG);
b99bd4ef 14133 }
c19d1205 14134}
b99bd4ef 14135
c19d1205
ZW		 14136static void
14137do_t_swi (void)
14138{
e2b0ab59 14139 inst.relocs[0].type = BFD_RELOC_ARM_SWI;
c19d1205 14140}
b99bd4ef 14141
92e90b6e
PB		 14142static void
14143do_t_tb (void)
14144{
fdfde340 14145 unsigned Rn, Rm;
92e90b6e
PB		 14146 int half;
14147
14148 half = (inst.instruction & 0x10) != 0;
5ee91343 14149 set_pred_insn_type_last ();
dfa9f0d5
PB		 14150 constraint (inst.operands[0].immisreg,
14151 _("instruction requires register index"));
fdfde340
JM		 14152
14153 Rn = inst.operands[0].reg;
14154 Rm = inst.operands[0].imm;
c921be7d 14155
5c8ed6a4
JW		 14156 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
14157 constraint (Rn == REG_SP, BAD_SP);
fdfde340
JM		 14158 reject_bad_reg (Rm);
14159
92e90b6e
PB		 14160 constraint (!half && inst.operands[0].shifted,
14161 _("instruction does not allow shifted index"));
fdfde340 14162 inst.instruction |= (Rn << 16) | Rm;
92e90b6e
PB		 14163}
14164
74db7efb
NC		 14165static void
14166do_t_udf (void)
14167{
14168 if (!inst.operands[0].present)
14169 inst.operands[0].imm = 0;
14170
14171 if ((unsigned int) inst.operands[0].imm > 255 || inst.size_req == 4)
14172 {
14173 constraint (inst.size_req == 2,
14174 _("immediate value out of range"));
14175 inst.instruction = THUMB_OP32 (inst.instruction);
14176 inst.instruction |= (inst.operands[0].imm & 0xf000u) << 4;
14177 inst.instruction |= (inst.operands[0].imm & 0x0fffu) << 0;
14178 }
14179 else
14180 {
14181 inst.instruction = THUMB_OP16 (inst.instruction);
14182 inst.instruction |= inst.operands[0].imm;
14183 }
14184
5ee91343 14185 set_pred_insn_type (NEUTRAL_IT_INSN);
74db7efb
NC		 14186}
14187
14188
c19d1205
ZW		 14189static void
14190do_t_usat (void)
14191{
3a21c15a 14192 do_t_ssat_usat (0);
b99bd4ef
NC		 14193}
14194
14195static void
c19d1205 14196do_t_usat16 (void)
b99bd4ef 14197{
fdfde340
JM		 14198 unsigned Rd, Rn;
14199
14200 Rd = inst.operands[0].reg;
14201 Rn = inst.operands[2].reg;
14202
14203 reject_bad_reg (Rd);
14204 reject_bad_reg (Rn);
14205
14206 inst.instruction |= Rd << 8;
c19d1205 14207 inst.instruction |= inst.operands[1].imm;
fdfde340 14208 inst.instruction |= Rn << 16;
b99bd4ef 14209}
c19d1205 14210
e12437dc
AV		 14211/* Checking the range of the branch offset (VAL) with NBITS bits
14212 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14213static int
14214v8_1_branch_value_check (int val, int nbits, int is_signed)
14215{
14216 gas_assert (nbits > 0 && nbits <= 32);
14217 if (is_signed)
14218 {
14219 int cmp = (1 << (nbits - 1));
14220 if ((val < -cmp) || (val >= cmp) || (val & 0x01))
14221 return FAIL;
14222 }
14223 else
14224 {
14225 if ((val <= 0) || (val >= (1 << nbits)) || (val & 0x1))
14226 return FAIL;
14227 }
14228 return SUCCESS;
14229}
14230
4389b29a
AV		 14231/* For branches in Armv8.1-M Mainline. */
14232static void
14233do_t_branch_future (void)
14234{
14235 unsigned long insn = inst.instruction;
14236
14237 inst.instruction = THUMB_OP32 (inst.instruction);
14238 if (inst.operands[0].hasreloc == 0)
14239 {
14240 if (v8_1_branch_value_check (inst.operands[0].imm, 5, FALSE) == FAIL)
14241 as_bad (BAD_BRANCH_OFF);
14242
14243 inst.instruction |= ((inst.operands[0].imm & 0x1f) >> 1) << 23;
14244 }
14245 else
14246 {
14247 inst.relocs[0].type = BFD_RELOC_THUMB_PCREL_BRANCH5;
14248 inst.relocs[0].pc_rel = 1;
14249 }
14250
14251 switch (insn)
14252 {
14253 case T_MNEM_bf:
14254 if (inst.operands[1].hasreloc == 0)
14255 {
14256 int val = inst.operands[1].imm;
14257 if (v8_1_branch_value_check (inst.operands[1].imm, 17, TRUE) == FAIL)
14258 as_bad (BAD_BRANCH_OFF);
14259
14260 int immA = (val & 0x0001f000) >> 12;
14261 int immB = (val & 0x00000ffc) >> 2;
14262 int immC = (val & 0x00000002) >> 1;
14263 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14264 }
14265 else
14266 {
14267 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF17;
14268 inst.relocs[1].pc_rel = 1;
14269 }
14270 break;
14271
65d1bc05
AV		 14272 case T_MNEM_bfl:
14273 if (inst.operands[1].hasreloc == 0)
14274 {
14275 int val = inst.operands[1].imm;
14276 if (v8_1_branch_value_check (inst.operands[1].imm, 19, TRUE) == FAIL)
14277 as_bad (BAD_BRANCH_OFF);
14278
14279 int immA = (val & 0x0007f000) >> 12;
14280 int immB = (val & 0x00000ffc) >> 2;
14281 int immC = (val & 0x00000002) >> 1;
14282 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14283 }
14284 else
14285 {
14286 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF19;
14287 inst.relocs[1].pc_rel = 1;
14288 }
14289 break;
14290
f6b2b12d
AV		 14291 case T_MNEM_bfcsel:
14292 /* Operand 1. */
14293 if (inst.operands[1].hasreloc == 0)
14294 {
14295 int val = inst.operands[1].imm;
14296 int immA = (val & 0x00001000) >> 12;
14297 int immB = (val & 0x00000ffc) >> 2;
14298 int immC = (val & 0x00000002) >> 1;
14299 inst.instruction |= (immA << 16) | (immB << 1) | (immC << 11);
14300 }
14301 else
14302 {
14303 inst.relocs[1].type = BFD_RELOC_ARM_THUMB_BF13;
14304 inst.relocs[1].pc_rel = 1;
14305 }
14306
14307 /* Operand 2. */
14308 if (inst.operands[2].hasreloc == 0)
14309 {
14310 constraint ((inst.operands[0].hasreloc != 0), BAD_ARGS);
14311 int val2 = inst.operands[2].imm;
14312 int val0 = inst.operands[0].imm & 0x1f;
14313 int diff = val2 - val0;
14314 if (diff == 4)
14315 inst.instruction |= 1 << 17; /* T bit. */
14316 else if (diff != 2)
14317 as_bad (_("out of range label-relative fixup value"));
14318 }
14319 else
14320 {
14321 constraint ((inst.operands[0].hasreloc == 0), BAD_ARGS);
14322 inst.relocs[2].type = BFD_RELOC_THUMB_PCREL_BFCSEL;
14323 inst.relocs[2].pc_rel = 1;
14324 }
14325
14326 /* Operand 3. */
14327 constraint (inst.cond != COND_ALWAYS, BAD_COND);
14328 inst.instruction |= (inst.operands[3].imm & 0xf) << 18;
14329 break;
14330
f1c7f421
AV		 14331 case T_MNEM_bfx:
14332 case T_MNEM_bflx:
14333 inst.instruction |= inst.operands[1].reg << 16;
14334 break;
14335
4389b29a
AV		 14336 default: abort ();
14337 }
14338}
14339
60f993ce
AV		 14340/* Helper function for do_t_loloop to handle relocations. */
14341static void
14342v8_1_loop_reloc (int is_le)
14343{
14344 if (inst.relocs[0].exp.X_op == O_constant)
14345 {
14346 int value = inst.relocs[0].exp.X_add_number;
14347 value = (is_le) ? -value : value;
14348
14349 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
14350 as_bad (BAD_BRANCH_OFF);
14351
14352 int imml, immh;
14353
14354 immh = (value & 0x00000ffc) >> 2;
14355 imml = (value & 0x00000002) >> 1;
14356
14357 inst.instruction |= (imml << 11) | (immh << 1);
14358 }
14359 else
14360 {
14361 inst.relocs[0].type = BFD_RELOC_ARM_THUMB_LOOP12;
14362 inst.relocs[0].pc_rel = 1;
14363 }
14364}
14365
08132bdd
SP		 14366/* For shifts with four operands in MVE. */
14367static void
14368do_mve_scalar_shift1 (void)
14369{
14370 unsigned int value = inst.operands[2].imm;
14371
14372 inst.instruction |= inst.operands[0].reg << 16;
14373 inst.instruction |= inst.operands[1].reg << 8;
14374
14375 /* Setting the bit for saturation. */
14376 inst.instruction |= ((value == 64) ? 0: 1) << 7;
14377
14378 /* Assuming Rm is already checked not to be 11x1. */
14379 constraint (inst.operands[3].reg == inst.operands[0].reg, BAD_OVERLAP);
14380 constraint (inst.operands[3].reg == inst.operands[1].reg, BAD_OVERLAP);
14381 inst.instruction |= inst.operands[3].reg << 12;
14382}
14383
23d00a41
SD		 14384/* For shifts in MVE. */
14385static void
14386do_mve_scalar_shift (void)
14387{
14388 if (!inst.operands[2].present)
14389 {
14390 inst.operands[2] = inst.operands[1];
14391 inst.operands[1].reg = 0xf;
14392 }
14393
14394 inst.instruction |= inst.operands[0].reg << 16;
14395 inst.instruction |= inst.operands[1].reg << 8;
14396
14397 if (inst.operands[2].isreg)
14398 {
14399 /* Assuming Rm is already checked not to be 11x1. */
14400 constraint (inst.operands[2].reg == inst.operands[0].reg, BAD_OVERLAP);
14401 constraint (inst.operands[2].reg == inst.operands[1].reg, BAD_OVERLAP);
14402 inst.instruction |= inst.operands[2].reg << 12;
14403 }
14404 else
14405 {
14406 /* Assuming imm is already checked as [1,32]. */
14407 unsigned int value = inst.operands[2].imm;
14408 inst.instruction |= (value & 0x1c) << 10;
14409 inst.instruction |= (value & 0x03) << 6;
14410 /* Change last 4 bits from 0xd to 0xf. */
14411 inst.instruction |= 0x2;
14412 }
14413}
14414
a302e574
AV		 14415/* MVE instruction encoder helpers. */
14416#define M_MNEM_vabav 0xee800f01
14417#define M_MNEM_vmladav 0xeef00e00
14418#define M_MNEM_vmladava 0xeef00e20
14419#define M_MNEM_vmladavx 0xeef01e00
14420#define M_MNEM_vmladavax 0xeef01e20
14421#define M_MNEM_vmlsdav 0xeef00e01
14422#define M_MNEM_vmlsdava 0xeef00e21
14423#define M_MNEM_vmlsdavx 0xeef01e01
14424#define M_MNEM_vmlsdavax 0xeef01e21
886e1c73
AV		 14425#define M_MNEM_vmullt 0xee011e00
14426#define M_MNEM_vmullb 0xee010e00
35c228db
AV		 14427#define M_MNEM_vst20 0xfc801e00
14428#define M_MNEM_vst21 0xfc801e20
14429#define M_MNEM_vst40 0xfc801e01
14430#define M_MNEM_vst41 0xfc801e21
14431#define M_MNEM_vst42 0xfc801e41
14432#define M_MNEM_vst43 0xfc801e61
14433#define M_MNEM_vld20 0xfc901e00
14434#define M_MNEM_vld21 0xfc901e20
14435#define M_MNEM_vld40 0xfc901e01
14436#define M_MNEM_vld41 0xfc901e21
14437#define M_MNEM_vld42 0xfc901e41
14438#define M_MNEM_vld43 0xfc901e61
f5f10c66
AV		 14439#define M_MNEM_vstrb 0xec000e00
14440#define M_MNEM_vstrh 0xec000e10
14441#define M_MNEM_vstrw 0xec000e40
14442#define M_MNEM_vstrd 0xec000e50
14443#define M_MNEM_vldrb 0xec100e00
14444#define M_MNEM_vldrh 0xec100e10
14445#define M_MNEM_vldrw 0xec100e40
14446#define M_MNEM_vldrd 0xec100e50
57785aa2
AV		 14447#define M_MNEM_vmovlt 0xeea01f40
14448#define M_MNEM_vmovlb 0xeea00f40
14449#define M_MNEM_vmovnt 0xfe311e81
14450#define M_MNEM_vmovnb 0xfe310e81
c2dafc2a
AV		 14451#define M_MNEM_vadc 0xee300f00
14452#define M_MNEM_vadci 0xee301f00
14453#define M_MNEM_vbrsr 0xfe011e60
26c1e780
AV		 14454#define M_MNEM_vaddlv 0xee890f00
14455#define M_MNEM_vaddlva 0xee890f20
14456#define M_MNEM_vaddv 0xeef10f00
14457#define M_MNEM_vaddva 0xeef10f20
b409bdb6
AV		 14458#define M_MNEM_vddup 0xee011f6e
14459#define M_MNEM_vdwdup 0xee011f60
14460#define M_MNEM_vidup 0xee010f6e
14461#define M_MNEM_viwdup 0xee010f60
13ccd4c0
AV		 14462#define M_MNEM_vmaxv 0xeee20f00
14463#define M_MNEM_vmaxav 0xeee00f00
14464#define M_MNEM_vminv 0xeee20f80
14465#define M_MNEM_vminav 0xeee00f80
93925576
AV		 14466#define M_MNEM_vmlaldav 0xee800e00
14467#define M_MNEM_vmlaldava 0xee800e20
14468#define M_MNEM_vmlaldavx 0xee801e00
14469#define M_MNEM_vmlaldavax 0xee801e20
14470#define M_MNEM_vmlsldav 0xee800e01
14471#define M_MNEM_vmlsldava 0xee800e21
14472#define M_MNEM_vmlsldavx 0xee801e01
14473#define M_MNEM_vmlsldavax 0xee801e21
14474#define M_MNEM_vrmlaldavhx 0xee801f00
14475#define M_MNEM_vrmlaldavhax 0xee801f20
14476#define M_MNEM_vrmlsldavh 0xfe800e01
14477#define M_MNEM_vrmlsldavha 0xfe800e21
14478#define M_MNEM_vrmlsldavhx 0xfe801e01
14479#define M_MNEM_vrmlsldavhax 0xfe801e21
1be7aba3
AV		 14480#define M_MNEM_vqmovnt 0xee331e01
14481#define M_MNEM_vqmovnb 0xee330e01
14482#define M_MNEM_vqmovunt 0xee311e81
14483#define M_MNEM_vqmovunb 0xee310e81
4aa88b50
AV		 14484#define M_MNEM_vshrnt 0xee801fc1
14485#define M_MNEM_vshrnb 0xee800fc1
14486#define M_MNEM_vrshrnt 0xfe801fc1
14487#define M_MNEM_vqshrnt 0xee801f40
14488#define M_MNEM_vqshrnb 0xee800f40
14489#define M_MNEM_vqshrunt 0xee801fc0
14490#define M_MNEM_vqshrunb 0xee800fc0
14491#define M_MNEM_vrshrnb 0xfe800fc1
14492#define M_MNEM_vqrshrnt 0xee801f41
14493#define M_MNEM_vqrshrnb 0xee800f41
14494#define M_MNEM_vqrshrunt 0xfe801fc0
14495#define M_MNEM_vqrshrunb 0xfe800fc0
a302e574 14496
5287ad62 14497/* Neon instruction encoder helpers. */
5f4273c7 14498
5287ad62 14499/* Encodings for the different types for various Neon opcodes. */
b99bd4ef 14500
5287ad62
JB		 14501/* An "invalid" code for the following tables. */
14502#define N_INV -1u
14503
14504struct neon_tab_entry
b99bd4ef 14505{
5287ad62
JB		 14506 unsigned integer;
14507 unsigned float_or_poly;
14508 unsigned scalar_or_imm;
14509};
5f4273c7 14510
5287ad62
JB		 14511/* Map overloaded Neon opcodes to their respective encodings. */
14512#define NEON_ENC_TAB \
14513 X(vabd, 0x0000700, 0x1200d00, N_INV), \
5ee91343 14514 X(vabdl, 0x0800700, N_INV, N_INV), \
5287ad62
JB		 14515 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14516 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14517 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14518 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14519 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14520 X(vadd, 0x0000800, 0x0000d00, N_INV), \
5ee91343 14521 X(vaddl, 0x0800000, N_INV, N_INV), \
5287ad62 14522 X(vsub, 0x1000800, 0x0200d00, N_INV), \
5ee91343 14523 X(vsubl, 0x0800200, N_INV, N_INV), \
5287ad62
JB		 14524 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14525 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14526 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14527 /* Register variants of the following two instructions are encoded as
e07e6e58 14528 vcge / vcgt with the operands reversed. */ \
92559b5b
PB		 14529 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14530 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
62f3b8c8
PB		 14531 X(vfma, N_INV, 0x0000c10, N_INV), \
14532 X(vfms, N_INV, 0x0200c10, N_INV), \
5287ad62
JB		 14533 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14534 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14535 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14536 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14537 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14538 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14539 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14540 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14541 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14542 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14543 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
d6b4b13e
MW		 14544 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14545 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
5287ad62
JB		 14546 X(vshl, 0x0000400, N_INV, 0x0800510), \
14547 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14548 X(vand, 0x0000110, N_INV, 0x0800030), \
14549 X(vbic, 0x0100110, N_INV, 0x0800030), \
14550 X(veor, 0x1000110, N_INV, N_INV), \
14551 X(vorn, 0x0300110, N_INV, 0x0800010), \
14552 X(vorr, 0x0200110, N_INV, 0x0800010), \
14553 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14554 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14555 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14556 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14557 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14558 X(vst1, 0x0000000, 0x0800000, N_INV), \
14559 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14560 X(vst2, 0x0000100, 0x0800100, N_INV), \
14561 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14562 X(vst3, 0x0000200, 0x0800200, N_INV), \
14563 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14564 X(vst4, 0x0000300, 0x0800300, N_INV), \
14565 X(vmovn, 0x1b20200, N_INV, N_INV), \
14566 X(vtrn, 0x1b20080, N_INV, N_INV), \
14567 X(vqmovn, 0x1b20200, N_INV, N_INV), \
037e8744
JB		 14568 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14569 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
e6655fda
PB		 14570 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14571 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
62f3b8c8
PB		 14572 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14573 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
037e8744
JB		 14574 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14575 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14576 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
33399f07
MGD		 14577 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14578 X(vseleq, 0xe000a00, N_INV, N_INV), \
14579 X(vselvs, 0xe100a00, N_INV, N_INV), \
14580 X(vselge, 0xe200a00, N_INV, N_INV), \
73924fbc
MGD		 14581 X(vselgt, 0xe300a00, N_INV, N_INV), \
14582 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
7e8e6784 14583 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
30bdf752
MGD		 14584 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14585 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
91ff7894 14586 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
48adcd8e 14587 X(aes, 0x3b00300, N_INV, N_INV), \
3c9017d2
MGD		 14588 X(sha3op, 0x2000c00, N_INV, N_INV), \
14589 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14590 X(sha2op, 0x3ba0380, N_INV, N_INV)
5287ad62
JB		 14591
14592enum neon_opc
14593{
14594#define X(OPC,I,F,S) N_MNEM_##OPC
14595NEON_ENC_TAB
14596#undef X
14597};
b99bd4ef 14598
5287ad62
JB		 14599static const struct neon_tab_entry neon_enc_tab[] =
14600{
14601#define X(OPC,I,F,S) { (I), (F), (S) }
14602NEON_ENC_TAB
14603#undef X
14604};
b99bd4ef 14605
88714cb8
DG		 14606/* Do not use these macros; instead, use NEON_ENCODE defined below. */
14607#define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14608#define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14609#define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14610#define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14611#define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14612#define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14613#define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14614#define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14615#define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14616#define NEON_ENC_SINGLE_(X) \
037e8744 14617 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
88714cb8 14618#define NEON_ENC_DOUBLE_(X) \
037e8744 14619 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
33399f07
MGD		 14620#define NEON_ENC_FPV8_(X) \
14621 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
5287ad62 14622
88714cb8
DG		 14623#define NEON_ENCODE(type, inst) \
14624 do \
14625 { \
14626 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14627 inst.is_neon = 1; \
14628 } \
14629 while (0)
14630
14631#define check_neon_suffixes \
14632 do \
14633 { \
14634 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14635 { \
14636 as_bad (_("invalid neon suffix for non neon instruction")); \
14637 return; \
14638 } \
14639 } \
14640 while (0)
14641
037e8744
JB		 14642/* Define shapes for instruction operands. The following mnemonic characters
14643 are used in this table:
5287ad62 14644
037e8744 14645 F - VFP S<n> register
5287ad62
JB		 14646 D - Neon D<n> register
14647 Q - Neon Q<n> register
14648 I - Immediate
14649 S - Scalar
14650 R - ARM register
14651 L - D<n> register list
5f4273c7 14652
037e8744
JB		 14653 This table is used to generate various data:
14654 - enumerations of the form NS_DDR to be used as arguments to
14655 neon_select_shape.
14656 - a table classifying shapes into single, double, quad, mixed.
5f4273c7 14657 - a table used to drive neon_select_shape. */
b99bd4ef 14658
037e8744 14659#define NEON_SHAPE_DEF \
93925576 14660 X(4, (R, R, Q, Q), QUAD), \
b409bdb6 14661 X(4, (Q, R, R, I), QUAD), \
57785aa2
AV		 14662 X(4, (R, R, S, S), QUAD), \
14663 X(4, (S, S, R, R), QUAD), \
b409bdb6 14664 X(3, (Q, R, I), QUAD), \
1b883319
AV		 14665 X(3, (I, Q, Q), QUAD), \
14666 X(3, (I, Q, R), QUAD), \
a302e574 14667 X(3, (R, Q, Q), QUAD), \
037e8744
JB		 14668 X(3, (D, D, D), DOUBLE), \
14669 X(3, (Q, Q, Q), QUAD), \
14670 X(3, (D, D, I), DOUBLE), \
14671 X(3, (Q, Q, I), QUAD), \
14672 X(3, (D, D, S), DOUBLE), \
14673 X(3, (Q, Q, S), QUAD), \
5ee91343 14674 X(3, (Q, Q, R), QUAD), \
26c1e780
AV		 14675 X(3, (R, R, Q), QUAD), \
14676 X(2, (R, Q), QUAD), \
037e8744
JB		 14677 X(2, (D, D), DOUBLE), \
14678 X(2, (Q, Q), QUAD), \
14679 X(2, (D, S), DOUBLE), \
14680 X(2, (Q, S), QUAD), \
14681 X(2, (D, R), DOUBLE), \
14682 X(2, (Q, R), QUAD), \
14683 X(2, (D, I), DOUBLE), \
14684 X(2, (Q, I), QUAD), \
14685 X(3, (D, L, D), DOUBLE), \
14686 X(2, (D, Q), MIXED), \
14687 X(2, (Q, D), MIXED), \
14688 X(3, (D, Q, I), MIXED), \
14689 X(3, (Q, D, I), MIXED), \
14690 X(3, (Q, D, D), MIXED), \
14691 X(3, (D, Q, Q), MIXED), \
14692 X(3, (Q, Q, D), MIXED), \
14693 X(3, (Q, D, S), MIXED), \
14694 X(3, (D, Q, S), MIXED), \
14695 X(4, (D, D, D, I), DOUBLE), \
14696 X(4, (Q, Q, Q, I), QUAD), \
c28eeff2
SN		 14697 X(4, (D, D, S, I), DOUBLE), \
14698 X(4, (Q, Q, S, I), QUAD), \
037e8744
JB		 14699 X(2, (F, F), SINGLE), \
14700 X(3, (F, F, F), SINGLE), \
14701 X(2, (F, I), SINGLE), \
14702 X(2, (F, D), MIXED), \
14703 X(2, (D, F), MIXED), \
14704 X(3, (F, F, I), MIXED), \
14705 X(4, (R, R, F, F), SINGLE), \
14706 X(4, (F, F, R, R), SINGLE), \
14707 X(3, (D, R, R), DOUBLE), \
14708 X(3, (R, R, D), DOUBLE), \
14709 X(2, (S, R), SINGLE), \
14710 X(2, (R, S), SINGLE), \
14711 X(2, (F, R), SINGLE), \
d54af2d0 14712 X(2, (R, F), SINGLE), \
1f6234a3
AV		 14713/* Used for MVE tail predicated loop instructions. */\
14714 X(2, (R, R), QUAD), \
d54af2d0
RL		 14715/* Half float shape supported so far. */\
14716 X (2, (H, D), MIXED), \
14717 X (2, (D, H), MIXED), \
14718 X (2, (H, F), MIXED), \
14719 X (2, (F, H), MIXED), \
14720 X (2, (H, H), HALF), \
14721 X (2, (H, R), HALF), \
14722 X (2, (R, H), HALF), \
14723 X (2, (H, I), HALF), \
14724 X (3, (H, H, H), HALF), \
14725 X (3, (H, F, I), MIXED), \
dec41383
JW		 14726 X (3, (F, H, I), MIXED), \
14727 X (3, (D, H, H), MIXED), \
14728 X (3, (D, H, S), MIXED)
037e8744
JB		 14729
14730#define S2(A,B) NS_##A##B
14731#define S3(A,B,C) NS_##A##B##C
14732#define S4(A,B,C,D) NS_##A##B##C##D
14733
14734#define X(N, L, C) S##N L
14735
5287ad62
JB		 14736enum neon_shape
14737{
037e8744
JB		 14738 NEON_SHAPE_DEF,
14739 NS_NULL
5287ad62 14740};
b99bd4ef 14741
037e8744
JB		 14742#undef X
14743#undef S2
14744#undef S3
14745#undef S4
14746
14747enum neon_shape_class
14748{
d54af2d0 14749 SC_HALF,
037e8744
JB		 14750 SC_SINGLE,
14751 SC_DOUBLE,
14752 SC_QUAD,
14753 SC_MIXED
14754};
14755
14756#define X(N, L, C) SC_##C
14757
14758static enum neon_shape_class neon_shape_class[] =
14759{
14760 NEON_SHAPE_DEF
14761};
14762
14763#undef X
14764
14765enum neon_shape_el
14766{
d54af2d0 14767 SE_H,
037e8744
JB		 14768 SE_F,
14769 SE_D,
14770 SE_Q,
14771 SE_I,
14772 SE_S,
14773 SE_R,
14774 SE_L
14775};
14776
14777/* Register widths of above. */
14778static unsigned neon_shape_el_size[] =
14779{
d54af2d0 14780 16,
037e8744
JB		 14781 32,
14782 64,
14783 128,
14784 0,
14785 32,
14786 32,
14787 0
14788};
14789
14790struct neon_shape_info
14791{
14792 unsigned els;
14793 enum neon_shape_el el[NEON_MAX_TYPE_ELS];
14794};
14795
14796#define S2(A,B) { SE_##A, SE_##B }
14797#define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14798#define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14799
14800#define X(N, L, C) { N, S##N L }
14801
14802static struct neon_shape_info neon_shape_tab[] =
14803{
14804 NEON_SHAPE_DEF
14805};
14806
14807#undef X
14808#undef S2
14809#undef S3
14810#undef S4
14811
5287ad62
JB		 14812/* Bit masks used in type checking given instructions.
14813 'N_EQK' means the type must be the same as (or based on in some way) the key
14814 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14815 set, various other bits can be set as well in order to modify the meaning of
14816 the type constraint. */
14817
14818enum neon_type_mask
14819{
8e79c3df
CM		 14820 N_S8 = 0x0000001,
14821 N_S16 = 0x0000002,
14822 N_S32 = 0x0000004,
14823 N_S64 = 0x0000008,
14824 N_U8 = 0x0000010,
14825 N_U16 = 0x0000020,
14826 N_U32 = 0x0000040,
14827 N_U64 = 0x0000080,
14828 N_I8 = 0x0000100,
14829 N_I16 = 0x0000200,
14830 N_I32 = 0x0000400,
14831 N_I64 = 0x0000800,
14832 N_8 = 0x0001000,
14833 N_16 = 0x0002000,
14834 N_32 = 0x0004000,
14835 N_64 = 0x0008000,
14836 N_P8 = 0x0010000,
14837 N_P16 = 0x0020000,
14838 N_F16 = 0x0040000,
14839 N_F32 = 0x0080000,
14840 N_F64 = 0x0100000,
4f51b4bd 14841 N_P64 = 0x0200000,
c921be7d
NC		 14842 N_KEY = 0x1000000, /* Key element (main type specifier). */
14843 N_EQK = 0x2000000, /* Given operand has the same type & size as the key. */
8e79c3df 14844 N_VFP = 0x4000000, /* VFP mode: operand size must match register width. */
91ff7894 14845 N_UNT = 0x8000000, /* Must be explicitly untyped. */
c921be7d
NC		 14846 N_DBL = 0x0000001, /* If N_EQK, this operand is twice the size. */
14847 N_HLF = 0x0000002, /* If N_EQK, this operand is half the size. */
14848 N_SGN = 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14849 N_UNS = 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14850 N_INT = 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14851 N_FLT = 0x0000020, /* If N_EQK, this operand is forced to be float. */
14852 N_SIZ = 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
5287ad62 14853 N_UTYP = 0,
4f51b4bd 14854 N_MAX_NONSPECIAL = N_P64
5287ad62
JB		 14855};
14856
dcbf9037
JB		 14857#define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14858
5287ad62
JB		 14859#define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14860#define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14861#define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
cc933301
JW		 14862#define N_S_32 (N_S8 | N_S16 | N_S32)
14863#define N_F_16_32 (N_F16 | N_F32)
14864#define N_SUF_32 (N_SU_32 | N_F_16_32)
5287ad62 14865#define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
cc933301 14866#define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
d54af2d0 14867#define N_F_ALL (N_F16 | N_F32 | N_F64)
5ee91343
AV		 14868#define N_I_MVE (N_I8 | N_I16 | N_I32)
14869#define N_F_MVE (N_F16 | N_F32)
14870#define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
5287ad62
JB		 14871
14872/* Pass this as the first type argument to neon_check_type to ignore types
14873 altogether. */
14874#define N_IGNORE_TYPE (N_KEY | N_EQK)
14875
037e8744
JB		 14876/* Select a "shape" for the current instruction (describing register types or
14877 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14878 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14879 function of operand parsing, so this function doesn't need to be called.
14880 Shapes should be listed in order of decreasing length. */
5287ad62
JB		 14881
14882static enum neon_shape
037e8744 14883neon_select_shape (enum neon_shape shape, ...)
5287ad62 14884{
037e8744
JB		 14885 va_list ap;
14886 enum neon_shape first_shape = shape;
5287ad62
JB		 14887
14888 /* Fix missing optional operands. FIXME: we don't know at this point how
14889 many arguments we should have, so this makes the assumption that we have
14890 > 1. This is true of all current Neon opcodes, I think, but may not be
14891 true in the future. */
14892 if (!inst.operands[1].present)
14893 inst.operands[1] = inst.operands[0];
14894
037e8744 14895 va_start (ap, shape);
5f4273c7 14896
21d799b5 14897 for (; shape != NS_NULL; shape = (enum neon_shape) va_arg (ap, int))
037e8744
JB		 14898 {
14899 unsigned j;
14900 int matches = 1;
14901
14902 for (j = 0; j < neon_shape_tab[shape].els; j++)
477330fc
RM		 14903 {
14904 if (!inst.operands[j].present)
14905 {
14906 matches = 0;
14907 break;
14908 }
14909
14910 switch (neon_shape_tab[shape].el[j])
14911 {
d54af2d0
RL		 14912 /* If a .f16, .16, .u16, .s16 type specifier is given over
14913 a VFP single precision register operand, it's essentially
14914 means only half of the register is used.
14915
14916 If the type specifier is given after the mnemonics, the
14917 information is stored in inst.vectype. If the type specifier
14918 is given after register operand, the information is stored
14919 in inst.operands[].vectype.
14920
14921 When there is only one type specifier, and all the register
14922 operands are the same type of hardware register, the type
14923 specifier applies to all register operands.
14924
14925 If no type specifier is given, the shape is inferred from
14926 operand information.
14927
14928 for example:
14929 vadd.f16 s0, s1, s2: NS_HHH
14930 vabs.f16 s0, s1: NS_HH
14931 vmov.f16 s0, r1: NS_HR
14932 vmov.f16 r0, s1: NS_RH
14933 vcvt.f16 r0, s1: NS_RH
14934 vcvt.f16.s32 s2, s2, #29: NS_HFI
14935 vcvt.f16.s32 s2, s2: NS_HF
14936 */
14937 case SE_H:
14938 if (!(inst.operands[j].isreg
14939 && inst.operands[j].isvec
14940 && inst.operands[j].issingle
14941 && !inst.operands[j].isquad
14942 && ((inst.vectype.elems == 1
14943 && inst.vectype.el[0].size == 16)
14944 || (inst.vectype.elems > 1
14945 && inst.vectype.el[j].size == 16)
14946 || (inst.vectype.elems == 0
14947 && inst.operands[j].vectype.type != NT_invtype
14948 && inst.operands[j].vectype.size == 16))))
14949 matches = 0;
14950 break;
14951
477330fc
RM		 14952 case SE_F:
14953 if (!(inst.operands[j].isreg
14954 && inst.operands[j].isvec
14955 && inst.operands[j].issingle
d54af2d0
RL		 14956 && !inst.operands[j].isquad
14957 && ((inst.vectype.elems == 1 && inst.vectype.el[0].size == 32)
14958 || (inst.vectype.elems > 1 && inst.vectype.el[j].size == 32)
14959 || (inst.vectype.elems == 0
14960 && (inst.operands[j].vectype.size == 32
14961 || inst.operands[j].vectype.type == NT_invtype)))))
477330fc
RM		 14962 matches = 0;
14963 break;
14964
14965 case SE_D:
14966 if (!(inst.operands[j].isreg
14967 && inst.operands[j].isvec
14968 && !inst.operands[j].isquad
14969 && !inst.operands[j].issingle))
14970 matches = 0;
14971 break;
14972
14973 case SE_R:
14974 if (!(inst.operands[j].isreg
14975 && !inst.operands[j].isvec))
14976 matches = 0;
14977 break;
14978
14979 case SE_Q:
14980 if (!(inst.operands[j].isreg
14981 && inst.operands[j].isvec
14982 && inst.operands[j].isquad
14983 && !inst.operands[j].issingle))
14984 matches = 0;
14985 break;
14986
14987 case SE_I:
14988 if (!(!inst.operands[j].isreg
14989 && !inst.operands[j].isscalar))
14990 matches = 0;
14991 break;
14992
14993 case SE_S:
14994 if (!(!inst.operands[j].isreg
14995 && inst.operands[j].isscalar))
14996 matches = 0;
14997 break;
14998
14999 case SE_L:
15000 break;
15001 }
3fde54a2
JZ		 15002 if (!matches)
15003 break;
477330fc 15004 }
ad6cec43
MGD		 15005 if (matches && (j >= ARM_IT_MAX_OPERANDS || !inst.operands[j].present))
15006 /* We've matched all the entries in the shape table, and we don't
15007 have any left over operands which have not been matched. */
477330fc 15008 break;
037e8744 15009 }
5f4273c7 15010
037e8744 15011 va_end (ap);
5287ad62 15012
037e8744
JB		 15013 if (shape == NS_NULL && first_shape != NS_NULL)
15014 first_error (_("invalid instruction shape"));
5287ad62 15015
037e8744
JB		 15016 return shape;
15017}
5287ad62 15018
037e8744
JB		 15019/* True if SHAPE is predominantly a quadword operation (most of the time, this
15020 means the Q bit should be set). */
15021
15022static int
15023neon_quad (enum neon_shape shape)
15024{
15025 return neon_shape_class[shape] == SC_QUAD;
5287ad62 15026}
037e8744 15027
5287ad62
JB		 15028static void
15029neon_modify_type_size (unsigned typebits, enum neon_el_type *g_type,
477330fc 15030 unsigned *g_size)
5287ad62
JB		 15031{
15032 /* Allow modification to be made to types which are constrained to be
15033 based on the key element, based on bits set alongside N_EQK. */
15034 if ((typebits & N_EQK) != 0)
15035 {
15036 if ((typebits & N_HLF) != 0)
15037 *g_size /= 2;
15038 else if ((typebits & N_DBL) != 0)
15039 *g_size *= 2;
15040 if ((typebits & N_SGN) != 0)
15041 *g_type = NT_signed;
15042 else if ((typebits & N_UNS) != 0)
477330fc 15043 *g_type = NT_unsigned;
5287ad62 15044 else if ((typebits & N_INT) != 0)
477330fc 15045 *g_type = NT_integer;
5287ad62 15046 else if ((typebits & N_FLT) != 0)
477330fc 15047 *g_type = NT_float;
dcbf9037 15048 else if ((typebits & N_SIZ) != 0)
477330fc 15049 *g_type = NT_untyped;
5287ad62
JB		 15050 }
15051}
5f4273c7 15052
5287ad62
JB		 15053/* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15054 operand type, i.e. the single type specified in a Neon instruction when it
15055 is the only one given. */
15056
15057static struct neon_type_el
15058neon_type_promote (struct neon_type_el *key, unsigned thisarg)
15059{
15060 struct neon_type_el dest = *key;
5f4273c7 15061
9c2799c2 15062 gas_assert ((thisarg & N_EQK) != 0);
5f4273c7 15063
5287ad62
JB		 15064 neon_modify_type_size (thisarg, &dest.type, &dest.size);
15065
15066 return dest;
15067}
15068
15069/* Convert Neon type and size into compact bitmask representation. */
15070
15071static enum neon_type_mask
15072type_chk_of_el_type (enum neon_el_type type, unsigned size)
15073{
15074 switch (type)
15075 {
15076 case NT_untyped:
15077 switch (size)
477330fc
RM		 15078 {
15079 case 8: return N_8;
15080 case 16: return N_16;
15081 case 32: return N_32;
15082 case 64: return N_64;
15083 default: ;
15084 }
5287ad62
JB		 15085 break;
15086
15087 case NT_integer:
15088 switch (size)
477330fc
RM		 15089 {
15090 case 8: return N_I8;
15091 case 16: return N_I16;
15092 case 32: return N_I32;
15093 case 64: return N_I64;
15094 default: ;
15095 }
5287ad62
JB		 15096 break;
15097
15098 case NT_float:
037e8744 15099 switch (size)
477330fc 15100 {
8e79c3df 15101 case 16: return N_F16;
477330fc
RM		 15102 case 32: return N_F32;
15103 case 64: return N_F64;
15104 default: ;
15105 }
5287ad62
JB		 15106 break;
15107
15108 case NT_poly:
15109 switch (size)
477330fc
RM		 15110 {
15111 case 8: return N_P8;
15112 case 16: return N_P16;
4f51b4bd 15113 case 64: return N_P64;
477330fc
RM		 15114 default: ;
15115 }
5287ad62
JB		 15116 break;
15117
15118 case NT_signed:
15119 switch (size)
477330fc
RM		 15120 {
15121 case 8: return N_S8;
15122 case 16: return N_S16;
15123 case 32: return N_S32;
15124 case 64: return N_S64;
15125 default: ;
15126 }
5287ad62
JB		 15127 break;
15128
15129 case NT_unsigned:
15130 switch (size)
477330fc
RM		 15131 {
15132 case 8: return N_U8;
15133 case 16: return N_U16;
15134 case 32: return N_U32;
15135 case 64: return N_U64;
15136 default: ;
15137 }
5287ad62
JB		 15138 break;
15139
15140 default: ;
15141 }
5f4273c7 15142
5287ad62
JB		 15143 return N_UTYP;
15144}
15145
15146/* Convert compact Neon bitmask type representation to a type and size. Only
15147 handles the case where a single bit is set in the mask. */
15148
dcbf9037 15149static int
5287ad62 15150el_type_of_type_chk (enum neon_el_type *type, unsigned *size,
477330fc 15151 enum neon_type_mask mask)
5287ad62 15152{
dcbf9037
JB		 15153 if ((mask & N_EQK) != 0)
15154 return FAIL;
15155
5287ad62
JB		 15156 if ((mask & (N_S8 | N_U8 | N_I8 | N_8 | N_P8)) != 0)
15157 *size = 8;
c70a8987 15158 else if ((mask & (N_S16 | N_U16 | N_I16 | N_16 | N_F16 | N_P16)) != 0)
5287ad62 15159 *size = 16;
dcbf9037 15160 else if ((mask & (N_S32 | N_U32 | N_I32 | N_32 | N_F32)) != 0)
5287ad62 15161 *size = 32;
4f51b4bd 15162 else if ((mask & (N_S64 | N_U64 | N_I64 | N_64 | N_F64 | N_P64)) != 0)
5287ad62 15163 *size = 64;
dcbf9037
JB		 15164 else
15165 return FAIL;
15166
5287ad62
JB		 15167 if ((mask & (N_S8 | N_S16 | N_S32 | N_S64)) != 0)
15168 *type = NT_signed;
dcbf9037 15169 else if ((mask & (N_U8 | N_U16 | N_U32 | N_U64)) != 0)
5287ad62 15170 *type = NT_unsigned;
dcbf9037 15171 else if ((mask & (N_I8 | N_I16 | N_I32 | N_I64)) != 0)
5287ad62 15172 *type = NT_integer;
dcbf9037 15173 else if ((mask & (N_8 | N_16 | N_32 | N_64)) != 0)
5287ad62 15174 *type = NT_untyped;
4f51b4bd 15175 else if ((mask & (N_P8 | N_P16 | N_P64)) != 0)
5287ad62 15176 *type = NT_poly;
d54af2d0 15177 else if ((mask & (N_F_ALL)) != 0)
5287ad62 15178 *type = NT_float;
dcbf9037
JB		 15179 else
15180 return FAIL;
5f4273c7 15181
dcbf9037 15182 return SUCCESS;
5287ad62
JB		 15183}
15184
15185/* Modify a bitmask of allowed types. This is only needed for type
15186 relaxation. */
15187
15188static unsigned
15189modify_types_allowed (unsigned allowed, unsigned mods)
15190{
15191 unsigned size;
15192 enum neon_el_type type;
15193 unsigned destmask;
15194 int i;
5f4273c7 15195
5287ad62 15196 destmask = 0;
5f4273c7 15197
5287ad62
JB		 15198 for (i = 1; i <= N_MAX_NONSPECIAL; i <<= 1)
15199 {
21d799b5 15200 if (el_type_of_type_chk (&type, &size,
477330fc
RM		 15201 (enum neon_type_mask) (allowed & i)) == SUCCESS)
15202 {
15203 neon_modify_type_size (mods, &type, &size);
15204 destmask |= type_chk_of_el_type (type, size);
15205 }
5287ad62 15206 }
5f4273c7 15207
5287ad62
JB		 15208 return destmask;
15209}
15210
15211/* Check type and return type classification.
15212 The manual states (paraphrase): If one datatype is given, it indicates the
15213 type given in:
15214 - the second operand, if there is one
15215 - the operand, if there is no second operand
15216 - the result, if there are no operands.
15217 This isn't quite good enough though, so we use a concept of a "key" datatype
15218 which is set on a per-instruction basis, which is the one which matters when
15219 only one data type is written.
15220 Note: this function has side-effects (e.g. filling in missing operands). All
037e8744 15221 Neon instructions should call it before performing bit encoding. */
5287ad62
JB		 15222
15223static struct neon_type_el
15224neon_check_type (unsigned els, enum neon_shape ns, ...)
15225{
15226 va_list ap;
15227 unsigned i, pass, key_el = 0;
15228 unsigned types[NEON_MAX_TYPE_ELS];
15229 enum neon_el_type k_type = NT_invtype;
15230 unsigned k_size = -1u;
15231 struct neon_type_el badtype = {NT_invtype, -1};
15232 unsigned key_allowed = 0;
15233
15234 /* Optional registers in Neon instructions are always (not) in operand 1.
15235 Fill in the missing operand here, if it was omitted. */
15236 if (els > 1 && !inst.operands[1].present)
15237 inst.operands[1] = inst.operands[0];
15238
15239 /* Suck up all the varargs. */
15240 va_start (ap, ns);
15241 for (i = 0; i < els; i++)
15242 {
15243 unsigned thisarg = va_arg (ap, unsigned);
15244 if (thisarg == N_IGNORE_TYPE)
477330fc
RM		 15245 {
15246 va_end (ap);
15247 return badtype;
15248 }
5287ad62
JB		 15249 types[i] = thisarg;
15250 if ((thisarg & N_KEY) != 0)
477330fc 15251 key_el = i;
5287ad62
JB		 15252 }
15253 va_end (ap);
15254
dcbf9037
JB		 15255 if (inst.vectype.elems > 0)
15256 for (i = 0; i < els; i++)
15257 if (inst.operands[i].vectype.type != NT_invtype)
477330fc
RM		 15258 {
15259 first_error (_("types specified in both the mnemonic and operands"));
15260 return badtype;
15261 }
dcbf9037 15262
5287ad62
JB		 15263 /* Duplicate inst.vectype elements here as necessary.
15264 FIXME: No idea if this is exactly the same as the ARM assembler,
15265 particularly when an insn takes one register and one non-register
15266 operand. */
15267 if (inst.vectype.elems == 1 && els > 1)
15268 {
15269 unsigned j;
15270 inst.vectype.elems = els;
15271 inst.vectype.el[key_el] = inst.vectype.el[0];
15272 for (j = 0; j < els; j++)
477330fc
RM		 15273 if (j != key_el)
15274 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15275 types[j]);
dcbf9037
JB		 15276 }
15277 else if (inst.vectype.elems == 0 && els > 0)
15278 {
15279 unsigned j;
15280 /* No types were given after the mnemonic, so look for types specified
477330fc
RM		 15281 after each operand. We allow some flexibility here; as long as the
15282 "key" operand has a type, we can infer the others. */
dcbf9037 15283 for (j = 0; j < els; j++)
477330fc
RM		 15284 if (inst.operands[j].vectype.type != NT_invtype)
15285 inst.vectype.el[j] = inst.operands[j].vectype;
dcbf9037
JB		 15286
15287 if (inst.operands[key_el].vectype.type != NT_invtype)
477330fc
RM		 15288 {
15289 for (j = 0; j < els; j++)
15290 if (inst.operands[j].vectype.type == NT_invtype)
15291 inst.vectype.el[j] = neon_type_promote (&inst.vectype.el[key_el],
15292 types[j]);
15293 }
dcbf9037 15294 else
477330fc
RM		 15295 {
15296 first_error (_("operand types can't be inferred"));
15297 return badtype;
15298 }
5287ad62
JB		 15299 }
15300 else if (inst.vectype.elems != els)
15301 {
dcbf9037 15302 first_error (_("type specifier has the wrong number of parts"));
5287ad62
JB		 15303 return badtype;
15304 }
15305
15306 for (pass = 0; pass < 2; pass++)
15307 {
15308 for (i = 0; i < els; i++)
477330fc
RM		 15309 {
15310 unsigned thisarg = types[i];
15311 unsigned types_allowed = ((thisarg & N_EQK) != 0 && pass != 0)
15312 ? modify_types_allowed (key_allowed, thisarg) : thisarg;
15313 enum neon_el_type g_type = inst.vectype.el[i].type;
15314 unsigned g_size = inst.vectype.el[i].size;
15315
15316 /* Decay more-specific signed & unsigned types to sign-insensitive
5287ad62 15317 integer types if sign-specific variants are unavailable. */
477330fc 15318 if ((g_type == NT_signed || g_type == NT_unsigned)
5287ad62
JB		 15319 && (types_allowed & N_SU_ALL) == 0)
15320 g_type = NT_integer;
15321
477330fc 15322 /* If only untyped args are allowed, decay any more specific types to
5287ad62
JB		 15323 them. Some instructions only care about signs for some element
15324 sizes, so handle that properly. */
477330fc 15325 if (((types_allowed & N_UNT) == 0)
91ff7894
MGD		 15326 && ((g_size == 8 && (types_allowed & N_8) != 0)
15327 || (g_size == 16 && (types_allowed & N_16) != 0)
15328 || (g_size == 32 && (types_allowed & N_32) != 0)
15329 || (g_size == 64 && (types_allowed & N_64) != 0)))
5287ad62
JB		 15330 g_type = NT_untyped;
15331
477330fc
RM		 15332 if (pass == 0)
15333 {
15334 if ((thisarg & N_KEY) != 0)
15335 {
15336 k_type = g_type;
15337 k_size = g_size;
15338 key_allowed = thisarg & ~N_KEY;
cc933301
JW		 15339
15340 /* Check architecture constraint on FP16 extension. */
15341 if (k_size == 16
15342 && k_type == NT_float
15343 && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15344 {
15345 inst.error = _(BAD_FP16);
15346 return badtype;
15347 }
477330fc
RM		 15348 }
15349 }
15350 else
15351 {
15352 if ((thisarg & N_VFP) != 0)
15353 {
15354 enum neon_shape_el regshape;
15355 unsigned regwidth, match;
99b253c5
NC		 15356
15357 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15358 if (ns == NS_NULL)
15359 {
15360 first_error (_("invalid instruction shape"));
15361 return badtype;
15362 }
477330fc
RM		 15363 regshape = neon_shape_tab[ns].el[i];
15364 regwidth = neon_shape_el_size[regshape];
15365
15366 /* In VFP mode, operands must match register widths. If we
15367 have a key operand, use its width, else use the width of
15368 the current operand. */
15369 if (k_size != -1u)
15370 match = k_size;
15371 else
15372 match = g_size;
15373
9db2f6b4
RL		 15374 /* FP16 will use a single precision register. */
15375 if (regwidth == 32 && match == 16)
15376 {
15377 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16))
15378 match = regwidth;
15379 else
15380 {
15381 inst.error = _(BAD_FP16);
15382 return badtype;
15383 }
15384 }
15385
477330fc
RM		 15386 if (regwidth != match)
15387 {
15388 first_error (_("operand size must match register width"));
15389 return badtype;
15390 }
15391 }
15392
15393 if ((thisarg & N_EQK) == 0)
15394 {
15395 unsigned given_type = type_chk_of_el_type (g_type, g_size);
15396
15397 if ((given_type & types_allowed) == 0)
15398 {
a302e574 15399 first_error (BAD_SIMD_TYPE);
477330fc
RM		 15400 return badtype;
15401 }
15402 }
15403 else
15404 {
15405 enum neon_el_type mod_k_type = k_type;
15406 unsigned mod_k_size = k_size;
15407 neon_modify_type_size (thisarg, &mod_k_type, &mod_k_size);
15408 if (g_type != mod_k_type || g_size != mod_k_size)
15409 {
15410 first_error (_("inconsistent types in Neon instruction"));
15411 return badtype;
15412 }
15413 }
15414 }
15415 }
5287ad62
JB		 15416 }
15417
15418 return inst.vectype.el[key_el];
15419}
15420
037e8744 15421/* Neon-style VFP instruction forwarding. */
5287ad62 15422
037e8744
JB		 15423/* Thumb VFP instructions have 0xE in the condition field. */
15424
15425static void
15426do_vfp_cond_or_thumb (void)
5287ad62 15427{
88714cb8
DG		 15428 inst.is_neon = 1;
15429
5287ad62 15430 if (thumb_mode)
037e8744 15431 inst.instruction |= 0xe0000000;
5287ad62 15432 else
037e8744 15433 inst.instruction |= inst.cond << 28;
5287ad62
JB		 15434}
15435
037e8744
JB		 15436/* Look up and encode a simple mnemonic, for use as a helper function for the
15437 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15438 etc. It is assumed that operand parsing has already been done, and that the
15439 operands are in the form expected by the given opcode (this isn't necessarily
15440 the same as the form in which they were parsed, hence some massaging must
15441 take place before this function is called).
15442 Checks current arch version against that in the looked-up opcode. */
5287ad62 15443
037e8744
JB		 15444static void
15445do_vfp_nsyn_opcode (const char *opname)
5287ad62 15446{
037e8744 15447 const struct asm_opcode *opcode;
5f4273c7 15448
21d799b5 15449 opcode = (const struct asm_opcode *) hash_find (arm_ops_hsh, opname);
5287ad62 15450
037e8744
JB		 15451 if (!opcode)
15452 abort ();
5287ad62 15453
037e8744 15454 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant,
477330fc
RM		 15455 thumb_mode ? *opcode->tvariant : *opcode->avariant),
15456 _(BAD_FPU));
5287ad62 15457
88714cb8
DG		 15458 inst.is_neon = 1;
15459
037e8744
JB		 15460 if (thumb_mode)
15461 {
15462 inst.instruction = opcode->tvalue;
15463 opcode->tencode ();
15464 }
15465 else
15466 {
15467 inst.instruction = (inst.cond << 28) | opcode->avalue;
15468 opcode->aencode ();
15469 }
15470}
5287ad62
JB		 15471
15472static void
037e8744 15473do_vfp_nsyn_add_sub (enum neon_shape rs)
5287ad62 15474{
037e8744
JB		 15475 int is_add = (inst.instruction & 0x0fffffff) == N_MNEM_vadd;
15476
9db2f6b4 15477 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB		 15478 {
15479 if (is_add)
477330fc 15480 do_vfp_nsyn_opcode ("fadds");
037e8744 15481 else
477330fc 15482 do_vfp_nsyn_opcode ("fsubs");
9db2f6b4
RL		 15483
15484 /* ARMv8.2 fp16 instruction. */
15485 if (rs == NS_HHH)
15486 do_scalar_fp16_v82_encode ();
037e8744
JB		 15487 }
15488 else
15489 {
15490 if (is_add)
477330fc 15491 do_vfp_nsyn_opcode ("faddd");
037e8744 15492 else
477330fc 15493 do_vfp_nsyn_opcode ("fsubd");
037e8744
JB		 15494 }
15495}
15496
15497/* Check operand types to see if this is a VFP instruction, and if so call
15498 PFN (). */
15499
15500static int
15501try_vfp_nsyn (int args, void (*pfn) (enum neon_shape))
15502{
15503 enum neon_shape rs;
15504 struct neon_type_el et;
15505
15506 switch (args)
15507 {
15508 case 2:
9db2f6b4
RL		 15509 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15510 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
037e8744 15511 break;
5f4273c7 15512
037e8744 15513 case 3:
9db2f6b4
RL		 15514 rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
15515 et = neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
15516 N_F_ALL | N_KEY | N_VFP);
037e8744
JB		 15517 break;
15518
15519 default:
15520 abort ();
15521 }
15522
15523 if (et.type != NT_invtype)
15524 {
15525 pfn (rs);
15526 return SUCCESS;
15527 }
037e8744 15528
99b253c5 15529 inst.error = NULL;
037e8744
JB		 15530 return FAIL;
15531}
15532
15533static void
15534do_vfp_nsyn_mla_mls (enum neon_shape rs)
15535{
15536 int is_mla = (inst.instruction & 0x0fffffff) == N_MNEM_vmla;
5f4273c7 15537
9db2f6b4 15538 if (rs == NS_FFF || rs == NS_HHH)
037e8744
JB		 15539 {
15540 if (is_mla)
477330fc 15541 do_vfp_nsyn_opcode ("fmacs");
037e8744 15542 else
477330fc 15543 do_vfp_nsyn_opcode ("fnmacs");
9db2f6b4
RL		 15544
15545 /* ARMv8.2 fp16 instruction. */
15546 if (rs == NS_HHH)
15547 do_scalar_fp16_v82_encode ();
037e8744
JB		 15548 }
15549 else
15550 {
15551 if (is_mla)
477330fc 15552 do_vfp_nsyn_opcode ("fmacd");
037e8744 15553 else
477330fc 15554 do_vfp_nsyn_opcode ("fnmacd");
037e8744
JB		 15555 }
15556}
15557
62f3b8c8
PB		 15558static void
15559do_vfp_nsyn_fma_fms (enum neon_shape rs)
15560{
15561 int is_fma = (inst.instruction & 0x0fffffff) == N_MNEM_vfma;
15562
9db2f6b4 15563 if (rs == NS_FFF || rs == NS_HHH)
62f3b8c8
PB		 15564 {
15565 if (is_fma)
477330fc 15566 do_vfp_nsyn_opcode ("ffmas");
62f3b8c8 15567 else
477330fc 15568 do_vfp_nsyn_opcode ("ffnmas");
9db2f6b4
RL		 15569
15570 /* ARMv8.2 fp16 instruction. */
15571 if (rs == NS_HHH)
15572 do_scalar_fp16_v82_encode ();
62f3b8c8
PB		 15573 }
15574 else
15575 {
15576 if (is_fma)
477330fc 15577 do_vfp_nsyn_opcode ("ffmad");
62f3b8c8 15578 else
477330fc 15579 do_vfp_nsyn_opcode ("ffnmad");
62f3b8c8
PB		 15580 }
15581}
15582
037e8744
JB		 15583static void
15584do_vfp_nsyn_mul (enum neon_shape rs)
15585{
9db2f6b4
RL		 15586 if (rs == NS_FFF || rs == NS_HHH)
15587 {
15588 do_vfp_nsyn_opcode ("fmuls");
15589
15590 /* ARMv8.2 fp16 instruction. */
15591 if (rs == NS_HHH)
15592 do_scalar_fp16_v82_encode ();
15593 }
037e8744
JB		 15594 else
15595 do_vfp_nsyn_opcode ("fmuld");
15596}
15597
15598static void
15599do_vfp_nsyn_abs_neg (enum neon_shape rs)
15600{
15601 int is_neg = (inst.instruction & 0x80) != 0;
9db2f6b4 15602 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_VFP | N_KEY);
037e8744 15603
9db2f6b4 15604 if (rs == NS_FF || rs == NS_HH)
037e8744
JB		 15605 {
15606 if (is_neg)
477330fc 15607 do_vfp_nsyn_opcode ("fnegs");
037e8744 15608 else
477330fc 15609 do_vfp_nsyn_opcode ("fabss");
9db2f6b4
RL		 15610
15611 /* ARMv8.2 fp16 instruction. */
15612 if (rs == NS_HH)
15613 do_scalar_fp16_v82_encode ();
037e8744
JB		 15614 }
15615 else
15616 {
15617 if (is_neg)
477330fc 15618 do_vfp_nsyn_opcode ("fnegd");
037e8744 15619 else
477330fc 15620 do_vfp_nsyn_opcode ("fabsd");
037e8744
JB		 15621 }
15622}
15623
15624/* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15625 insns belong to Neon, and are handled elsewhere. */
15626
15627static void
15628do_vfp_nsyn_ldm_stm (int is_dbmode)
15629{
15630 int is_ldm = (inst.instruction & (1 << 20)) != 0;
15631 if (is_ldm)
15632 {
15633 if (is_dbmode)
477330fc 15634 do_vfp_nsyn_opcode ("fldmdbs");
037e8744 15635 else
477330fc 15636 do_vfp_nsyn_opcode ("fldmias");
037e8744
JB		 15637 }
15638 else
15639 {
15640 if (is_dbmode)
477330fc 15641 do_vfp_nsyn_opcode ("fstmdbs");
037e8744 15642 else
477330fc 15643 do_vfp_nsyn_opcode ("fstmias");
037e8744
JB		 15644 }
15645}
15646
037e8744
JB		 15647static void
15648do_vfp_nsyn_sqrt (void)
15649{
9db2f6b4
RL		 15650 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
15651 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 15652
9db2f6b4
RL		 15653 if (rs == NS_FF || rs == NS_HH)
15654 {
15655 do_vfp_nsyn_opcode ("fsqrts");
15656
15657 /* ARMv8.2 fp16 instruction. */
15658 if (rs == NS_HH)
15659 do_scalar_fp16_v82_encode ();
15660 }
037e8744
JB		 15661 else
15662 do_vfp_nsyn_opcode ("fsqrtd");
15663}
15664
15665static void
15666do_vfp_nsyn_div (void)
15667{
9db2f6b4 15668 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15669 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15670 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15671
9db2f6b4
RL		 15672 if (rs == NS_FFF || rs == NS_HHH)
15673 {
15674 do_vfp_nsyn_opcode ("fdivs");
15675
15676 /* ARMv8.2 fp16 instruction. */
15677 if (rs == NS_HHH)
15678 do_scalar_fp16_v82_encode ();
15679 }
037e8744
JB		 15680 else
15681 do_vfp_nsyn_opcode ("fdivd");
15682}
15683
15684static void
15685do_vfp_nsyn_nmul (void)
15686{
9db2f6b4 15687 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_NULL);
037e8744 15688 neon_check_type (3, rs, N_EQK | N_VFP, N_EQK | N_VFP,
9db2f6b4 15689 N_F_ALL | N_KEY | N_VFP);
5f4273c7 15690
9db2f6b4 15691 if (rs == NS_FFF || rs == NS_HHH)
037e8744 15692 {
88714cb8 15693 NEON_ENCODE (SINGLE, inst);
037e8744 15694 do_vfp_sp_dyadic ();
9db2f6b4
RL		 15695
15696 /* ARMv8.2 fp16 instruction. */
15697 if (rs == NS_HHH)
15698 do_scalar_fp16_v82_encode ();
037e8744
JB		 15699 }
15700 else
15701 {
88714cb8 15702 NEON_ENCODE (DOUBLE, inst);
037e8744
JB		 15703 do_vfp_dp_rd_rn_rm ();
15704 }
15705 do_vfp_cond_or_thumb ();
9db2f6b4 15706
037e8744
JB		 15707}
15708
1b883319
AV		 15709/* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15710 (0, 1, 2, 3). */
15711
15712static unsigned
15713neon_logbits (unsigned x)
15714{
15715 return ffs (x) - 4;
15716}
15717
15718#define LOW4(R) ((R) & 0xf)
15719#define HI1(R) (((R) >> 4) & 1)
15720
15721static unsigned
15722mve_get_vcmp_vpt_cond (struct neon_type_el et)
15723{
15724 switch (et.type)
15725 {
15726 default:
15727 first_error (BAD_EL_TYPE);
15728 return 0;
15729 case NT_float:
15730 switch (inst.operands[0].imm)
15731 {
15732 default:
15733 first_error (_("invalid condition"));
15734 return 0;
15735 case 0x0:
15736 /* eq. */
15737 return 0;
15738 case 0x1:
15739 /* ne. */
15740 return 1;
15741 case 0xa:
15742 /* ge/ */
15743 return 4;
15744 case 0xb:
15745 /* lt. */
15746 return 5;
15747 case 0xc:
15748 /* gt. */
15749 return 6;
15750 case 0xd:
15751 /* le. */
15752 return 7;
15753 }
15754 case NT_integer:
15755 /* only accept eq and ne. */
15756 if (inst.operands[0].imm > 1)
15757 {
15758 first_error (_("invalid condition"));
15759 return 0;
15760 }
15761 return inst.operands[0].imm;
15762 case NT_unsigned:
15763 if (inst.operands[0].imm == 0x2)
15764 return 2;
15765 else if (inst.operands[0].imm == 0x8)
15766 return 3;
15767 else
15768 {
15769 first_error (_("invalid condition"));
15770 return 0;
15771 }
15772 case NT_signed:
15773 switch (inst.operands[0].imm)
15774 {
15775 default:
15776 first_error (_("invalid condition"));
15777 return 0;
15778 case 0xa:
15779 /* ge. */
15780 return 4;
15781 case 0xb:
15782 /* lt. */
15783 return 5;
15784 case 0xc:
15785 /* gt. */
15786 return 6;
15787 case 0xd:
15788 /* le. */
15789 return 7;
15790 }
15791 }
15792 /* Should be unreachable. */
15793 abort ();
15794}
15795
15796static void
15797do_mve_vpt (void)
15798{
15799 /* We are dealing with a vector predicated block. */
15800 if (inst.operands[0].present)
15801 {
15802 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15803 struct neon_type_el et
15804 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15805 N_EQK);
15806
15807 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15808
15809 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15810
15811 if (et.type == NT_invtype)
15812 return;
15813
15814 if (et.type == NT_float)
15815 {
15816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15817 BAD_FPU);
15818 constraint (et.size != 16 && et.size != 32, BAD_EL_TYPE);
15819 inst.instruction |= (et.size == 16) << 28;
15820 inst.instruction |= 0x3 << 20;
15821 }
15822 else
15823 {
15824 constraint (et.size != 8 && et.size != 16 && et.size != 32,
15825 BAD_EL_TYPE);
15826 inst.instruction |= 1 << 28;
15827 inst.instruction |= neon_logbits (et.size) << 20;
15828 }
15829
15830 if (inst.operands[2].isquad)
15831 {
15832 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15833 inst.instruction |= LOW4 (inst.operands[2].reg);
15834 inst.instruction |= (fcond & 0x2) >> 1;
15835 }
15836 else
15837 {
15838 if (inst.operands[2].reg == REG_SP)
15839 as_tsktsk (MVE_BAD_SP);
15840 inst.instruction |= 1 << 6;
15841 inst.instruction |= (fcond & 0x2) << 4;
15842 inst.instruction |= inst.operands[2].reg;
15843 }
15844 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15845 inst.instruction |= (fcond & 0x4) << 10;
15846 inst.instruction |= (fcond & 0x1) << 7;
15847
15848 }
15849 set_pred_insn_type (VPT_INSN);
15850 now_pred.cc = 0;
15851 now_pred.mask = ((inst.instruction & 0x00400000) >> 19)
15852 | ((inst.instruction & 0xe000) >> 13);
15853 now_pred.warn_deprecated = FALSE;
15854 now_pred.type = VECTOR_PRED;
15855 inst.is_neon = 1;
15856}
15857
15858static void
15859do_mve_vcmp (void)
15860{
15861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
15862 if (!inst.operands[1].isreg || !inst.operands[1].isquad)
15863 first_error (_(reg_expected_msgs[REG_TYPE_MQ]));
15864 if (!inst.operands[2].present)
15865 first_error (_("MVE vector or ARM register expected"));
15866 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
15867
15868 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15869 if ((inst.instruction & 0xffffffff) == N_MNEM_vcmpe
15870 && inst.operands[1].isquad)
15871 {
15872 inst.instruction = N_MNEM_vcmp;
15873 inst.cond = 0x10;
15874 }
15875
15876 if (inst.cond > COND_ALWAYS)
15877 inst.pred_insn_type = INSIDE_VPT_INSN;
15878 else
15879 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15880
15881 enum neon_shape rs = neon_select_shape (NS_IQQ, NS_IQR, NS_NULL);
15882 struct neon_type_el et
15883 = neon_check_type (3, rs, N_EQK, N_KEY | N_F_MVE | N_I_MVE | N_SU_32,
15884 N_EQK);
15885
15886 constraint (rs == NS_IQR && inst.operands[2].reg == REG_PC
15887 && !inst.operands[2].iszr, BAD_PC);
15888
15889 unsigned fcond = mve_get_vcmp_vpt_cond (et);
15890
15891 inst.instruction = 0xee010f00;
15892 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15893 inst.instruction |= (fcond & 0x4) << 10;
15894 inst.instruction |= (fcond & 0x1) << 7;
15895 if (et.type == NT_float)
15896 {
15897 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
15898 BAD_FPU);
15899 inst.instruction |= (et.size == 16) << 28;
15900 inst.instruction |= 0x3 << 20;
15901 }
15902 else
15903 {
15904 inst.instruction |= 1 << 28;
15905 inst.instruction |= neon_logbits (et.size) << 20;
15906 }
15907 if (inst.operands[2].isquad)
15908 {
15909 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
15910 inst.instruction |= (fcond & 0x2) >> 1;
15911 inst.instruction |= LOW4 (inst.operands[2].reg);
15912 }
15913 else
15914 {
15915 if (inst.operands[2].reg == REG_SP)
15916 as_tsktsk (MVE_BAD_SP);
15917 inst.instruction |= 1 << 6;
15918 inst.instruction |= (fcond & 0x2) << 4;
15919 inst.instruction |= inst.operands[2].reg;
15920 }
15921
15922 inst.is_neon = 1;
15923 return;
15924}
15925
935295b5
AV		 15926static void
15927do_mve_vmaxa_vmina (void)
15928{
15929 if (inst.cond > COND_ALWAYS)
15930 inst.pred_insn_type = INSIDE_VPT_INSN;
15931 else
15932 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15933
15934 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
15935 struct neon_type_el et
15936 = neon_check_type (2, rs, N_EQK, N_KEY | N_S8 | N_S16 | N_S32);
15937
15938 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15939 inst.instruction |= neon_logbits (et.size) << 18;
15940 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15941 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
15942 inst.instruction |= LOW4 (inst.operands[1].reg);
15943 inst.is_neon = 1;
15944}
15945
f30ee27c
AV		 15946static void
15947do_mve_vfmas (void)
15948{
15949 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
15950 struct neon_type_el et
15951 = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK, N_EQK);
15952
15953 if (inst.cond > COND_ALWAYS)
15954 inst.pred_insn_type = INSIDE_VPT_INSN;
15955 else
15956 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15957
15958 if (inst.operands[2].reg == REG_SP)
15959 as_tsktsk (MVE_BAD_SP);
15960 else if (inst.operands[2].reg == REG_PC)
15961 as_tsktsk (MVE_BAD_PC);
15962
15963 inst.instruction |= (et.size == 16) << 28;
15964 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
15965 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
15966 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
15967 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
15968 inst.instruction |= inst.operands[2].reg;
15969 inst.is_neon = 1;
15970}
15971
b409bdb6
AV		 15972static void
15973do_mve_viddup (void)
15974{
15975 if (inst.cond > COND_ALWAYS)
15976 inst.pred_insn_type = INSIDE_VPT_INSN;
15977 else
15978 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
15979
15980 unsigned imm = inst.relocs[0].exp.X_add_number;
15981 constraint (imm != 1 && imm != 2 && imm != 4 && imm != 8,
15982 _("immediate must be either 1, 2, 4 or 8"));
15983
15984 enum neon_shape rs;
15985 struct neon_type_el et;
15986 unsigned Rm;
15987 if (inst.instruction == M_MNEM_vddup || inst.instruction == M_MNEM_vidup)
15988 {
15989 rs = neon_select_shape (NS_QRI, NS_NULL);
15990 et = neon_check_type (2, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK);
15991 Rm = 7;
15992 }
15993 else
15994 {
15995 constraint ((inst.operands[2].reg % 2) != 1, BAD_EVEN);
15996 if (inst.operands[2].reg == REG_SP)
15997 as_tsktsk (MVE_BAD_SP);
15998 else if (inst.operands[2].reg == REG_PC)
15999 first_error (BAD_PC);
16000
16001 rs = neon_select_shape (NS_QRRI, NS_NULL);
16002 et = neon_check_type (3, rs, N_KEY | N_U8 | N_U16 | N_U32, N_EQK, N_EQK);
16003 Rm = inst.operands[2].reg >> 1;
16004 }
16005 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16006 inst.instruction |= neon_logbits (et.size) << 20;
16007 inst.instruction |= inst.operands[1].reg << 16;
16008 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16009 inst.instruction |= (imm > 2) << 7;
16010 inst.instruction |= Rm << 1;
16011 inst.instruction |= (imm == 2 || imm == 8);
16012 inst.is_neon = 1;
16013}
16014
2d78f95b
AV		 16015static void
16016do_mve_vmlas (void)
16017{
16018 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
16019 struct neon_type_el et
16020 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16021
16022 if (inst.operands[2].reg == REG_PC)
16023 as_tsktsk (MVE_BAD_PC);
16024 else if (inst.operands[2].reg == REG_SP)
16025 as_tsktsk (MVE_BAD_SP);
16026
16027 if (inst.cond > COND_ALWAYS)
16028 inst.pred_insn_type = INSIDE_VPT_INSN;
16029 else
16030 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16031
16032 inst.instruction |= (et.type == NT_unsigned) << 28;
16033 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16034 inst.instruction |= neon_logbits (et.size) << 20;
16035 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16036 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16037 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16038 inst.instruction |= inst.operands[2].reg;
16039 inst.is_neon = 1;
16040}
16041
acca5630
AV		 16042static void
16043do_mve_vshll (void)
16044{
16045 struct neon_type_el et
16046 = neon_check_type (2, NS_QQI, N_EQK, N_S8 | N_U8 | N_S16 | N_U16 | N_KEY);
16047
16048 if (inst.cond > COND_ALWAYS)
16049 inst.pred_insn_type = INSIDE_VPT_INSN;
16050 else
16051 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16052
16053 int imm = inst.operands[2].imm;
16054 constraint (imm < 1 || (unsigned)imm > et.size,
16055 _("immediate value out of range"));
16056
16057 if ((unsigned)imm == et.size)
16058 {
16059 inst.instruction |= neon_logbits (et.size) << 18;
16060 inst.instruction |= 0x110001;
16061 }
16062 else
16063 {
16064 inst.instruction |= (et.size + imm) << 16;
16065 inst.instruction |= 0x800140;
16066 }
16067
16068 inst.instruction |= (et.type == NT_unsigned) << 28;
16069 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16070 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16071 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16072 inst.instruction |= LOW4 (inst.operands[1].reg);
16073 inst.is_neon = 1;
16074}
16075
16076static void
16077do_mve_vshlc (void)
16078{
16079 if (inst.cond > COND_ALWAYS)
16080 inst.pred_insn_type = INSIDE_VPT_INSN;
16081 else
16082 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16083
16084 if (inst.operands[1].reg == REG_PC)
16085 as_tsktsk (MVE_BAD_PC);
16086 else if (inst.operands[1].reg == REG_SP)
16087 as_tsktsk (MVE_BAD_SP);
16088
16089 int imm = inst.operands[2].imm;
16090 constraint (imm < 1 || imm > 32, _("immediate value out of range"));
16091
16092 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16093 inst.instruction |= (imm & 0x1f) << 16;
16094 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16095 inst.instruction |= inst.operands[1].reg;
16096 inst.is_neon = 1;
16097}
16098
4aa88b50
AV		 16099static void
16100do_mve_vshrn (void)
16101{
16102 unsigned types;
16103 switch (inst.instruction)
16104 {
16105 case M_MNEM_vshrnt:
16106 case M_MNEM_vshrnb:
16107 case M_MNEM_vrshrnt:
16108 case M_MNEM_vrshrnb:
16109 types = N_I16 | N_I32;
16110 break;
16111 case M_MNEM_vqshrnt:
16112 case M_MNEM_vqshrnb:
16113 case M_MNEM_vqrshrnt:
16114 case M_MNEM_vqrshrnb:
16115 types = N_U16 | N_U32 | N_S16 | N_S32;
16116 break;
16117 case M_MNEM_vqshrunt:
16118 case M_MNEM_vqshrunb:
16119 case M_MNEM_vqrshrunt:
16120 case M_MNEM_vqrshrunb:
16121 types = N_S16 | N_S32;
16122 break;
16123 default:
16124 abort ();
16125 }
16126
16127 struct neon_type_el et = neon_check_type (2, NS_QQI, N_EQK, types | N_KEY);
16128
16129 if (inst.cond > COND_ALWAYS)
16130 inst.pred_insn_type = INSIDE_VPT_INSN;
16131 else
16132 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16133
16134 unsigned Qd = inst.operands[0].reg;
16135 unsigned Qm = inst.operands[1].reg;
16136 unsigned imm = inst.operands[2].imm;
16137 constraint (imm < 1 || ((unsigned) imm) > (et.size / 2),
16138 et.size == 16
16139 ? _("immediate operand expected in the range [1,8]")
16140 : _("immediate operand expected in the range [1,16]"));
16141
16142 inst.instruction |= (et.type == NT_unsigned) << 28;
16143 inst.instruction |= HI1 (Qd) << 22;
16144 inst.instruction |= (et.size - imm) << 16;
16145 inst.instruction |= LOW4 (Qd) << 12;
16146 inst.instruction |= HI1 (Qm) << 5;
16147 inst.instruction |= LOW4 (Qm);
16148 inst.is_neon = 1;
16149}
16150
1be7aba3
AV		 16151static void
16152do_mve_vqmovn (void)
16153{
16154 struct neon_type_el et;
16155 if (inst.instruction == M_MNEM_vqmovnt
16156 || inst.instruction == M_MNEM_vqmovnb)
16157 et = neon_check_type (2, NS_QQ, N_EQK,
16158 N_U16 | N_U32 | N_S16 | N_S32 | N_KEY);
16159 else
16160 et = neon_check_type (2, NS_QQ, N_EQK, N_S16 | N_S32 | N_KEY);
16161
16162 if (inst.cond > COND_ALWAYS)
16163 inst.pred_insn_type = INSIDE_VPT_INSN;
16164 else
16165 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16166
16167 inst.instruction |= (et.type == NT_unsigned) << 28;
16168 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16169 inst.instruction |= (et.size == 32) << 18;
16170 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16171 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16172 inst.instruction |= LOW4 (inst.operands[1].reg);
16173 inst.is_neon = 1;
16174}
16175
3063888e
AV		 16176static void
16177do_mve_vpsel (void)
16178{
16179 neon_select_shape (NS_QQQ, NS_NULL);
16180
16181 if (inst.cond > COND_ALWAYS)
16182 inst.pred_insn_type = INSIDE_VPT_INSN;
16183 else
16184 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16185
16186 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16187 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16188 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16189 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16190 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16191 inst.instruction |= LOW4 (inst.operands[2].reg);
16192 inst.is_neon = 1;
16193}
16194
16195static void
16196do_mve_vpnot (void)
16197{
16198 if (inst.cond > COND_ALWAYS)
16199 inst.pred_insn_type = INSIDE_VPT_INSN;
16200 else
16201 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16202}
16203
935295b5
AV		 16204static void
16205do_mve_vmaxnma_vminnma (void)
16206{
16207 enum neon_shape rs = neon_select_shape (NS_QQ, NS_NULL);
16208 struct neon_type_el et
16209 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
16210
16211 if (inst.cond > COND_ALWAYS)
16212 inst.pred_insn_type = INSIDE_VPT_INSN;
16213 else
16214 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16215
16216 inst.instruction |= (et.size == 16) << 28;
16217 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16218 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16219 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16220 inst.instruction |= LOW4 (inst.operands[1].reg);
16221 inst.is_neon = 1;
16222}
16223
5d281bf0
AV		 16224static void
16225do_mve_vcmul (void)
16226{
16227 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
16228 struct neon_type_el et
16229 = neon_check_type (3, rs, N_EQK, N_EQK, N_F_MVE | N_KEY);
16230
16231 if (inst.cond > COND_ALWAYS)
16232 inst.pred_insn_type = INSIDE_VPT_INSN;
16233 else
16234 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16235
16236 unsigned rot = inst.relocs[0].exp.X_add_number;
16237 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
16238 _("immediate out of range"));
16239
16240 if (et.size == 32 && (inst.operands[0].reg == inst.operands[1].reg
16241 || inst.operands[0].reg == inst.operands[2].reg))
16242 as_tsktsk (BAD_MVE_SRCDEST);
16243
16244 inst.instruction |= (et.size == 32) << 28;
16245 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16246 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16247 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16248 inst.instruction |= (rot > 90) << 12;
16249 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16250 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16251 inst.instruction |= LOW4 (inst.operands[2].reg);
16252 inst.instruction |= (rot == 90 || rot == 270);
16253 inst.is_neon = 1;
16254}
16255
1f6234a3
AV		 16256/* To handle the Low Overhead Loop instructions
16257 in Armv8.1-M Mainline and MVE. */
16258static void
16259do_t_loloop (void)
16260{
16261 unsigned long insn = inst.instruction;
16262
16263 inst.instruction = THUMB_OP32 (inst.instruction);
16264
16265 if (insn == T_MNEM_lctp)
16266 return;
16267
16268 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN);
16269
16270 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16271 {
16272 struct neon_type_el et
16273 = neon_check_type (2, NS_RR, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
16274 inst.instruction |= neon_logbits (et.size) << 20;
16275 inst.is_neon = 1;
16276 }
16277
16278 switch (insn)
16279 {
16280 case T_MNEM_letp:
16281 constraint (!inst.operands[0].present,
16282 _("expected LR"));
16283 /* fall through. */
16284 case T_MNEM_le:
16285 /* le <label>. */
16286 if (!inst.operands[0].present)
16287 inst.instruction |= 1 << 21;
16288
16289 v8_1_loop_reloc (TRUE);
16290 break;
16291
16292 case T_MNEM_wls:
16293 case T_MNEM_wlstp:
16294 v8_1_loop_reloc (FALSE);
16295 /* fall through. */
16296 case T_MNEM_dlstp:
16297 case T_MNEM_dls:
16298 constraint (inst.operands[1].isreg != 1, BAD_ARGS);
16299
16300 if (insn == T_MNEM_wlstp || insn == T_MNEM_dlstp)
16301 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
16302 else if (inst.operands[1].reg == REG_PC)
16303 as_tsktsk (MVE_BAD_PC);
16304 if (inst.operands[1].reg == REG_SP)
16305 as_tsktsk (MVE_BAD_SP);
16306
16307 inst.instruction |= (inst.operands[1].reg << 16);
16308 break;
16309
16310 default:
16311 abort ();
16312 }
16313}
16314
16315
037e8744
JB		 16316static void
16317do_vfp_nsyn_cmp (void)
16318{
9db2f6b4 16319 enum neon_shape rs;
1b883319
AV		 16320 if (!inst.operands[0].isreg)
16321 {
16322 do_mve_vcmp ();
16323 return;
16324 }
16325 else
16326 {
16327 constraint (inst.operands[2].present, BAD_SYNTAX);
16328 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd),
16329 BAD_FPU);
16330 }
16331
037e8744
JB		 16332 if (inst.operands[1].isreg)
16333 {
9db2f6b4
RL		 16334 rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_NULL);
16335 neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY | N_VFP);
5f4273c7 16336
9db2f6b4 16337 if (rs == NS_FF || rs == NS_HH)
477330fc
RM		 16338 {
16339 NEON_ENCODE (SINGLE, inst);
16340 do_vfp_sp_monadic ();
16341 }
037e8744 16342 else
477330fc
RM		 16343 {
16344 NEON_ENCODE (DOUBLE, inst);
16345 do_vfp_dp_rd_rm ();
16346 }
037e8744
JB		 16347 }
16348 else
16349 {
9db2f6b4
RL		 16350 rs = neon_select_shape (NS_HI, NS_FI, NS_DI, NS_NULL);
16351 neon_check_type (2, rs, N_F_ALL | N_KEY | N_VFP, N_EQK);
037e8744
JB		 16352
16353 switch (inst.instruction & 0x0fffffff)
477330fc
RM		 16354 {
16355 case N_MNEM_vcmp:
16356 inst.instruction += N_MNEM_vcmpz - N_MNEM_vcmp;
16357 break;
16358 case N_MNEM_vcmpe:
16359 inst.instruction += N_MNEM_vcmpez - N_MNEM_vcmpe;
16360 break;
16361 default:
16362 abort ();
16363 }
5f4273c7 16364
9db2f6b4 16365 if (rs == NS_FI || rs == NS_HI)
477330fc
RM		 16366 {
16367 NEON_ENCODE (SINGLE, inst);
16368 do_vfp_sp_compare_z ();
16369 }
037e8744 16370 else
477330fc
RM		 16371 {
16372 NEON_ENCODE (DOUBLE, inst);
16373 do_vfp_dp_rd ();
16374 }
037e8744
JB		 16375 }
16376 do_vfp_cond_or_thumb ();
9db2f6b4
RL		 16377
16378 /* ARMv8.2 fp16 instruction. */
16379 if (rs == NS_HI || rs == NS_HH)
16380 do_scalar_fp16_v82_encode ();
037e8744
JB		 16381}
16382
16383static void
16384nsyn_insert_sp (void)
16385{
16386 inst.operands[1] = inst.operands[0];
16387 memset (&inst.operands[0], '\0', sizeof (inst.operands[0]));
fdfde340 16388 inst.operands[0].reg = REG_SP;
037e8744
JB		 16389 inst.operands[0].isreg = 1;
16390 inst.operands[0].writeback = 1;
16391 inst.operands[0].present = 1;
16392}
16393
16394static void
16395do_vfp_nsyn_push (void)
16396{
16397 nsyn_insert_sp ();
b126985e
NC		 16398
16399 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16400 _("register list must contain at least 1 and at most 16 "
16401 "registers"));
16402
037e8744
JB		 16403 if (inst.operands[1].issingle)
16404 do_vfp_nsyn_opcode ("fstmdbs");
16405 else
16406 do_vfp_nsyn_opcode ("fstmdbd");
16407}
16408
16409static void
16410do_vfp_nsyn_pop (void)
16411{
16412 nsyn_insert_sp ();
b126985e
NC		 16413
16414 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
16415 _("register list must contain at least 1 and at most 16 "
16416 "registers"));
16417
037e8744 16418 if (inst.operands[1].issingle)
22b5b651 16419 do_vfp_nsyn_opcode ("fldmias");
037e8744 16420 else
22b5b651 16421 do_vfp_nsyn_opcode ("fldmiad");
037e8744
JB		 16422}
16423
16424/* Fix up Neon data-processing instructions, ORing in the correct bits for
16425 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16426
88714cb8
DG		 16427static void
16428neon_dp_fixup (struct arm_it* insn)
037e8744 16429{
88714cb8
DG		 16430 unsigned int i = insn->instruction;
16431 insn->is_neon = 1;
16432
037e8744
JB		 16433 if (thumb_mode)
16434 {
16435 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16436 if (i & (1 << 24))
477330fc 16437 i |= 1 << 28;
5f4273c7 16438
037e8744 16439 i &= ~(1 << 24);
5f4273c7 16440
037e8744
JB		 16441 i |= 0xef000000;
16442 }
16443 else
16444 i |= 0xf2000000;
5f4273c7 16445
88714cb8 16446 insn->instruction = i;
037e8744
JB		 16447}
16448
5ee91343 16449static void
7df54120 16450mve_encode_qqr (int size, int U, int fp)
5ee91343
AV		 16451{
16452 if (inst.operands[2].reg == REG_SP)
16453 as_tsktsk (MVE_BAD_SP);
16454 else if (inst.operands[2].reg == REG_PC)
16455 as_tsktsk (MVE_BAD_PC);
16456
16457 if (fp)
16458 {
16459 /* vadd. */
16460 if (((unsigned)inst.instruction) == 0xd00)
16461 inst.instruction = 0xee300f40;
16462 /* vsub. */
16463 else if (((unsigned)inst.instruction) == 0x200d00)
16464 inst.instruction = 0xee301f40;
a8465a06
AV		 16465 /* vmul. */
16466 else if (((unsigned)inst.instruction) == 0x1000d10)
16467 inst.instruction = 0xee310e60;
5ee91343
AV		 16468
16469 /* Setting size which is 1 for F16 and 0 for F32. */
16470 inst.instruction |= (size == 16) << 28;
16471 }
16472 else
16473 {
16474 /* vadd. */
16475 if (((unsigned)inst.instruction) == 0x800)
16476 inst.instruction = 0xee010f40;
16477 /* vsub. */
16478 else if (((unsigned)inst.instruction) == 0x1000800)
16479 inst.instruction = 0xee011f40;
7df54120
AV		 16480 /* vhadd. */
16481 else if (((unsigned)inst.instruction) == 0)
16482 inst.instruction = 0xee000f40;
16483 /* vhsub. */
16484 else if (((unsigned)inst.instruction) == 0x200)
16485 inst.instruction = 0xee001f40;
a8465a06
AV		 16486 /* vmla. */
16487 else if (((unsigned)inst.instruction) == 0x900)
16488 inst.instruction = 0xee010e40;
16489 /* vmul. */
16490 else if (((unsigned)inst.instruction) == 0x910)
16491 inst.instruction = 0xee011e60;
16492 /* vqadd. */
16493 else if (((unsigned)inst.instruction) == 0x10)
16494 inst.instruction = 0xee000f60;
16495 /* vqsub. */
16496 else if (((unsigned)inst.instruction) == 0x210)
16497 inst.instruction = 0xee001f60;
42b16635
AV		 16498 /* vqrdmlah. */
16499 else if (((unsigned)inst.instruction) == 0x3000b10)
16500 inst.instruction = 0xee000e40;
16501 /* vqdmulh. */
16502 else if (((unsigned)inst.instruction) == 0x0000b00)
16503 inst.instruction = 0xee010e60;
16504 /* vqrdmulh. */
16505 else if (((unsigned)inst.instruction) == 0x1000b00)
16506 inst.instruction = 0xfe010e60;
7df54120
AV		 16507
16508 /* Set U-bit. */
16509 inst.instruction |= U << 28;
16510
5ee91343
AV		 16511 /* Setting bits for size. */
16512 inst.instruction |= neon_logbits (size) << 20;
16513 }
16514 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16515 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16516 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16517 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16518 inst.instruction |= inst.operands[2].reg;
16519 inst.is_neon = 1;
16520}
16521
a302e574
AV		 16522static void
16523mve_encode_rqq (unsigned bit28, unsigned size)
16524{
16525 inst.instruction |= bit28 << 28;
16526 inst.instruction |= neon_logbits (size) << 20;
16527 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16528 inst.instruction |= inst.operands[0].reg << 12;
16529 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16530 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16531 inst.instruction |= LOW4 (inst.operands[2].reg);
16532 inst.is_neon = 1;
16533}
16534
886e1c73
AV		 16535static void
16536mve_encode_qqq (int ubit, int size)
16537{
16538
16539 inst.instruction |= (ubit != 0) << 28;
16540 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16541 inst.instruction |= neon_logbits (size) << 20;
16542 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16543 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16544 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16545 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16546 inst.instruction |= LOW4 (inst.operands[2].reg);
16547
16548 inst.is_neon = 1;
16549}
16550
26c1e780
AV		 16551static void
16552mve_encode_rq (unsigned bit28, unsigned size)
16553{
16554 inst.instruction |= bit28 << 28;
16555 inst.instruction |= neon_logbits (size) << 18;
16556 inst.instruction |= inst.operands[0].reg << 12;
16557 inst.instruction |= LOW4 (inst.operands[1].reg);
16558 inst.is_neon = 1;
16559}
886e1c73 16560
93925576
AV		 16561static void
16562mve_encode_rrqq (unsigned U, unsigned size)
16563{
16564 constraint (inst.operands[3].reg > 14, MVE_BAD_QREG);
16565
16566 inst.instruction |= U << 28;
16567 inst.instruction |= (inst.operands[1].reg >> 1) << 20;
16568 inst.instruction |= LOW4 (inst.operands[2].reg) << 16;
16569 inst.instruction |= (size == 32) << 16;
16570 inst.instruction |= inst.operands[0].reg << 12;
16571 inst.instruction |= HI1 (inst.operands[2].reg) << 7;
16572 inst.instruction |= inst.operands[3].reg;
16573 inst.is_neon = 1;
16574}
16575
037e8744
JB		 16576/* Encode insns with bit pattern:
16577
16578 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16579 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
5f4273c7 16580
037e8744
JB		 16581 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16582 different meaning for some instruction. */
16583
16584static void
16585neon_three_same (int isquad, int ubit, int size)
16586{
16587 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16588 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16589 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
16590 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
16591 inst.instruction |= LOW4 (inst.operands[2].reg);
16592 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
16593 inst.instruction |= (isquad != 0) << 6;
16594 inst.instruction |= (ubit != 0) << 24;
16595 if (size != -1)
16596 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 16597
88714cb8 16598 neon_dp_fixup (&inst);
037e8744
JB		 16599}
16600
16601/* Encode instructions of the form:
16602
16603 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16604 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
5287ad62
JB		 16605
16606 Don't write size if SIZE == -1. */
16607
16608static void
16609neon_two_same (int qbit, int ubit, int size)
16610{
16611 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16612 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16613 inst.instruction |= LOW4 (inst.operands[1].reg);
16614 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16615 inst.instruction |= (qbit != 0) << 6;
16616 inst.instruction |= (ubit != 0) << 24;
16617
16618 if (size != -1)
16619 inst.instruction |= neon_logbits (size) << 18;
16620
88714cb8 16621 neon_dp_fixup (&inst);
5287ad62
JB		 16622}
16623
7df54120
AV		 16624enum vfp_or_neon_is_neon_bits
16625{
16626NEON_CHECK_CC = 1,
16627NEON_CHECK_ARCH = 2,
16628NEON_CHECK_ARCH8 = 4
16629};
16630
16631/* Call this function if an instruction which may have belonged to the VFP or
16632 Neon instruction sets, but turned out to be a Neon instruction (due to the
16633 operand types involved, etc.). We have to check and/or fix-up a couple of
16634 things:
16635
16636 - Make sure the user hasn't attempted to make a Neon instruction
16637 conditional.
16638 - Alter the value in the condition code field if necessary.
16639 - Make sure that the arch supports Neon instructions.
16640
16641 Which of these operations take place depends on bits from enum
16642 vfp_or_neon_is_neon_bits.
16643
16644 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16645 current instruction's condition is COND_ALWAYS, the condition field is
16646 changed to inst.uncond_value. This is necessary because instructions shared
16647 between VFP and Neon may be conditional for the VFP variants only, and the
16648 unconditional Neon version must have, e.g., 0xF in the condition field. */
16649
16650static int
16651vfp_or_neon_is_neon (unsigned check)
16652{
16653/* Conditions are always legal in Thumb mode (IT blocks). */
16654if (!thumb_mode && (check & NEON_CHECK_CC))
16655 {
16656 if (inst.cond != COND_ALWAYS)
16657 {
16658 first_error (_(BAD_COND));
16659 return FAIL;
16660 }
16661 if (inst.uncond_value != -1)
16662 inst.instruction |= inst.uncond_value << 28;
16663 }
16664
16665
16666 if (((check & NEON_CHECK_ARCH) && !mark_feature_used (&fpu_neon_ext_v1))
16667 || ((check & NEON_CHECK_ARCH8)
16668 && !mark_feature_used (&fpu_neon_ext_armv8)))
16669 {
16670 first_error (_(BAD_FPU));
16671 return FAIL;
16672 }
16673
16674return SUCCESS;
16675}
16676
64c350f2
AV		 16677
16678/* Return TRUE if the SIMD instruction is available for the current
16679 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16680 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16681 vfp_or_neon_is_neon for the NEON specific checks. */
16682
16683static bfd_boolean
7df54120
AV		 16684check_simd_pred_availability (int fp, unsigned check)
16685{
16686if (inst.cond > COND_ALWAYS)
16687 {
16688 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16689 {
16690 inst.error = BAD_FPU;
64c350f2 16691 return FALSE;
7df54120
AV		 16692 }
16693 inst.pred_insn_type = INSIDE_VPT_INSN;
16694 }
16695else if (inst.cond < COND_ALWAYS)
16696 {
16697 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16698 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16699 else if (vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16700 return FALSE;
7df54120
AV		 16701 }
16702else
16703 {
16704 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fp ? mve_fp_ext : mve_ext)
16705 && vfp_or_neon_is_neon (check) == FAIL)
64c350f2 16706 return FALSE;
7df54120
AV		 16707
16708 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16709 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
16710 }
64c350f2 16711return TRUE;
7df54120
AV		 16712}
16713
5287ad62
JB		 16714/* Neon instruction encoders, in approximate order of appearance. */
16715
16716static void
16717do_neon_dyadic_i_su (void)
16718{
64c350f2 16719 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
7df54120
AV		 16720 return;
16721
16722 enum neon_shape rs;
16723 struct neon_type_el et;
16724 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16725 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16726 else
16727 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16728
16729 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_32 | N_KEY);
16730
16731
16732 if (rs != NS_QQR)
16733 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16734 else
16735 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
5287ad62
JB		 16736}
16737
16738static void
16739do_neon_dyadic_i64_su (void)
16740{
64c350f2 16741 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
a8465a06
AV		 16742 return;
16743 enum neon_shape rs;
16744 struct neon_type_el et;
16745 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16746 {
16747 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16748 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16749 }
16750 else
16751 {
16752 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16753 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16754 }
16755 if (rs == NS_QQR)
16756 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
16757 else
16758 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
5287ad62
JB		 16759}
16760
16761static void
16762neon_imm_shift (int write_ubit, int uval, int isquad, struct neon_type_el et,
477330fc 16763 unsigned immbits)
5287ad62
JB		 16764{
16765 unsigned size = et.size >> 3;
16766 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16767 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16768 inst.instruction |= LOW4 (inst.operands[1].reg);
16769 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
16770 inst.instruction |= (isquad != 0) << 6;
16771 inst.instruction |= immbits << 16;
16772 inst.instruction |= (size >> 3) << 7;
16773 inst.instruction |= (size & 0x7) << 19;
16774 if (write_ubit)
16775 inst.instruction |= (uval != 0) << 24;
16776
88714cb8 16777 neon_dp_fixup (&inst);
5287ad62
JB		 16778}
16779
16780static void
5150f0d8 16781do_neon_shl (void)
5287ad62 16782{
64c350f2 16783 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 16784 return;
16785
5287ad62
JB		 16786 if (!inst.operands[2].isreg)
16787 {
5150f0d8
AV		 16788 enum neon_shape rs;
16789 struct neon_type_el et;
16790 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16791 {
16792 rs = neon_select_shape (NS_QQI, NS_NULL);
16793 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_MVE);
16794 }
16795 else
16796 {
16797 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16798 et = neon_check_type (2, rs, N_EQK, N_KEY | N_I_ALL);
16799 }
cb3b1e65
JB		 16800 int imm = inst.operands[2].imm;
16801
16802 constraint (imm < 0 || (unsigned)imm >= et.size,
16803 _("immediate out of range for shift"));
88714cb8 16804 NEON_ENCODE (IMMED, inst);
cb3b1e65 16805 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 16806 }
16807 else
16808 {
5150f0d8
AV		 16809 enum neon_shape rs;
16810 struct neon_type_el et;
16811 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16812 {
16813 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16814 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16815 }
16816 else
16817 {
16818 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16819 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16820 }
16821
16822
16823 if (rs == NS_QQR)
16824 {
16825 constraint (inst.operands[0].reg != inst.operands[1].reg,
16826 _("invalid instruction shape"));
16827 if (inst.operands[2].reg == REG_SP)
16828 as_tsktsk (MVE_BAD_SP);
16829 else if (inst.operands[2].reg == REG_PC)
16830 as_tsktsk (MVE_BAD_PC);
16831
16832 inst.instruction = 0xee311e60;
16833 inst.instruction |= (et.type == NT_unsigned) << 28;
16834 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16835 inst.instruction |= neon_logbits (et.size) << 18;
16836 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16837 inst.instruction |= inst.operands[2].reg;
16838 inst.is_neon = 1;
16839 }
16840 else
16841 {
16842 unsigned int tmp;
16843
16844 /* VSHL/VQSHL 3-register variants have syntax such as:
16845 vshl.xx Dd, Dm, Dn
16846 whereas other 3-register operations encoded by neon_three_same have
16847 syntax like:
16848 vadd.xx Dd, Dn, Dm
16849 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16850 operands[2].reg here. */
16851 tmp = inst.operands[2].reg;
16852 inst.operands[2].reg = inst.operands[1].reg;
16853 inst.operands[1].reg = tmp;
16854 NEON_ENCODE (INTEGER, inst);
16855 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16856 }
5287ad62
JB		 16857 }
16858}
16859
16860static void
5150f0d8 16861do_neon_qshl (void)
5287ad62 16862{
64c350f2 16863 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 16864 return;
16865
5287ad62
JB		 16866 if (!inst.operands[2].isreg)
16867 {
5150f0d8
AV		 16868 enum neon_shape rs;
16869 struct neon_type_el et;
16870 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16871 {
16872 rs = neon_select_shape (NS_QQI, NS_NULL);
16873 et = neon_check_type (2, rs, N_EQK, N_KEY | N_SU_MVE);
16874 }
16875 else
16876 {
16877 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
16878 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
16879 }
cb3b1e65 16880 int imm = inst.operands[2].imm;
627907b7 16881
cb3b1e65
JB		 16882 constraint (imm < 0 || (unsigned)imm >= et.size,
16883 _("immediate out of range for shift"));
88714cb8 16884 NEON_ENCODE (IMMED, inst);
cb3b1e65 16885 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et, imm);
5287ad62
JB		 16886 }
16887 else
16888 {
5150f0d8
AV		 16889 enum neon_shape rs;
16890 struct neon_type_el et;
627907b7 16891
5150f0d8
AV		 16892 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16893 {
16894 rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
16895 et = neon_check_type (3, rs, N_EQK, N_SU_MVE | N_KEY, N_EQK | N_EQK);
16896 }
16897 else
16898 {
16899 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16900 et = neon_check_type (3, rs, N_EQK, N_SU_ALL | N_KEY, N_EQK | N_SGN);
16901 }
16902
16903 if (rs == NS_QQR)
16904 {
16905 constraint (inst.operands[0].reg != inst.operands[1].reg,
16906 _("invalid instruction shape"));
16907 if (inst.operands[2].reg == REG_SP)
16908 as_tsktsk (MVE_BAD_SP);
16909 else if (inst.operands[2].reg == REG_PC)
16910 as_tsktsk (MVE_BAD_PC);
16911
16912 inst.instruction = 0xee311ee0;
16913 inst.instruction |= (et.type == NT_unsigned) << 28;
16914 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16915 inst.instruction |= neon_logbits (et.size) << 18;
16916 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16917 inst.instruction |= inst.operands[2].reg;
16918 inst.is_neon = 1;
16919 }
16920 else
16921 {
16922 unsigned int tmp;
16923
16924 /* See note in do_neon_shl. */
16925 tmp = inst.operands[2].reg;
16926 inst.operands[2].reg = inst.operands[1].reg;
16927 inst.operands[1].reg = tmp;
16928 NEON_ENCODE (INTEGER, inst);
16929 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16930 }
5287ad62
JB		 16931 }
16932}
16933
627907b7
JB		 16934static void
16935do_neon_rshl (void)
16936{
64c350f2 16937 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
1be7aba3
AV		 16938 return;
16939
16940 enum neon_shape rs;
16941 struct neon_type_el et;
16942 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
16943 {
16944 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
16945 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
16946 }
16947 else
16948 {
16949 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
16950 et = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_ALL | N_KEY);
16951 }
16952
627907b7
JB		 16953 unsigned int tmp;
16954
1be7aba3
AV		 16955 if (rs == NS_QQR)
16956 {
16957 if (inst.operands[2].reg == REG_PC)
16958 as_tsktsk (MVE_BAD_PC);
16959 else if (inst.operands[2].reg == REG_SP)
16960 as_tsktsk (MVE_BAD_SP);
16961
16962 constraint (inst.operands[0].reg != inst.operands[1].reg,
16963 _("invalid instruction shape"));
16964
16965 if (inst.instruction == 0x0000510)
16966 /* We are dealing with vqrshl. */
16967 inst.instruction = 0xee331ee0;
16968 else
16969 /* We are dealing with vrshl. */
16970 inst.instruction = 0xee331e60;
16971
16972 inst.instruction |= (et.type == NT_unsigned) << 28;
16973 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
16974 inst.instruction |= neon_logbits (et.size) << 18;
16975 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
16976 inst.instruction |= inst.operands[2].reg;
16977 inst.is_neon = 1;
16978 }
16979 else
16980 {
16981 tmp = inst.operands[2].reg;
16982 inst.operands[2].reg = inst.operands[1].reg;
16983 inst.operands[1].reg = tmp;
16984 neon_three_same (neon_quad (rs), et.type == NT_unsigned, et.size);
16985 }
627907b7
JB		 16986}
16987
5287ad62
JB		 16988static int
16989neon_cmode_for_logic_imm (unsigned immediate, unsigned *immbits, int size)
16990{
036dc3f7
PB		 16991 /* Handle .I8 pseudo-instructions. */
16992 if (size == 8)
5287ad62 16993 {
5287ad62 16994 /* Unfortunately, this will make everything apart from zero out-of-range.
477330fc
RM		 16995 FIXME is this the intended semantics? There doesn't seem much point in
16996 accepting .I8 if so. */
5287ad62
JB		 16997 immediate |= immediate << 8;
16998 size = 16;
036dc3f7
PB		 16999 }
17000
17001 if (size >= 32)
17002 {
17003 if (immediate == (immediate & 0x000000ff))
17004 {
17005 *immbits = immediate;
17006 return 0x1;
17007 }
17008 else if (immediate == (immediate & 0x0000ff00))
17009 {
17010 *immbits = immediate >> 8;
17011 return 0x3;
17012 }
17013 else if (immediate == (immediate & 0x00ff0000))
17014 {
17015 *immbits = immediate >> 16;
17016 return 0x5;
17017 }
17018 else if (immediate == (immediate & 0xff000000))
17019 {
17020 *immbits = immediate >> 24;
17021 return 0x7;
17022 }
17023 if ((immediate & 0xffff) != (immediate >> 16))
17024 goto bad_immediate;
17025 immediate &= 0xffff;
5287ad62
JB		 17026 }
17027
17028 if (immediate == (immediate & 0x000000ff))
17029 {
17030 *immbits = immediate;
036dc3f7 17031 return 0x9;
5287ad62
JB		 17032 }
17033 else if (immediate == (immediate & 0x0000ff00))
17034 {
17035 *immbits = immediate >> 8;
036dc3f7 17036 return 0xb;
5287ad62
JB		 17037 }
17038
17039 bad_immediate:
dcbf9037 17040 first_error (_("immediate value out of range"));
5287ad62
JB		 17041 return FAIL;
17042}
17043
5287ad62
JB		 17044static void
17045do_neon_logic (void)
17046{
17047 if (inst.operands[2].present && inst.operands[2].isreg)
17048 {
037e8744 17049 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
f601a00c 17050 if (rs == NS_QQQ
64c350f2
AV		 17051 && !check_simd_pred_availability (FALSE,
17052 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV		 17053 return;
17054 else if (rs != NS_QQQ
17055 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17056 first_error (BAD_FPU);
17057
5287ad62
JB		 17058 neon_check_type (3, rs, N_IGNORE_TYPE);
17059 /* U bit and size field were set as part of the bitmask. */
88714cb8 17060 NEON_ENCODE (INTEGER, inst);
037e8744 17061 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 17062 }
17063 else
17064 {
4316f0d2
DG		 17065 const int three_ops_form = (inst.operands[2].present
17066 && !inst.operands[2].isreg);
17067 const int immoperand = (three_ops_form ? 2 : 1);
17068 enum neon_shape rs = (three_ops_form
17069 ? neon_select_shape (NS_DDI, NS_QQI, NS_NULL)
17070 : neon_select_shape (NS_DI, NS_QI, NS_NULL));
f601a00c
AV		 17071 /* Because neon_select_shape makes the second operand a copy of the first
17072 if the second operand is not present. */
17073 if (rs == NS_QQI
64c350f2
AV		 17074 && !check_simd_pred_availability (FALSE,
17075 NEON_CHECK_ARCH | NEON_CHECK_CC))
f601a00c
AV		 17076 return;
17077 else if (rs != NS_QQI
17078 && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
17079 first_error (BAD_FPU);
17080
17081 struct neon_type_el et;
17082 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17083 et = neon_check_type (2, rs, N_I32 | N_I16 | N_KEY, N_EQK);
17084 else
17085 et = neon_check_type (2, rs, N_I8 | N_I16 | N_I32 | N_I64 | N_F32
17086 | N_KEY, N_EQK);
17087
17088 if (et.type == NT_invtype)
17089 return;
21d799b5 17090 enum neon_opc opcode = (enum neon_opc) inst.instruction & 0x0fffffff;
5287ad62
JB		 17091 unsigned immbits;
17092 int cmode;
5f4273c7 17093
5f4273c7 17094
4316f0d2
DG		 17095 if (three_ops_form)
17096 constraint (inst.operands[0].reg != inst.operands[1].reg,
17097 _("first and second operands shall be the same register"));
17098
88714cb8 17099 NEON_ENCODE (IMMED, inst);
5287ad62 17100
4316f0d2 17101 immbits = inst.operands[immoperand].imm;
036dc3f7
PB		 17102 if (et.size == 64)
17103 {
17104 /* .i64 is a pseudo-op, so the immediate must be a repeating
17105 pattern. */
4316f0d2
DG		 17106 if (immbits != (inst.operands[immoperand].regisimm ?
17107 inst.operands[immoperand].reg : 0))
036dc3f7
PB		 17108 {
17109 /* Set immbits to an invalid constant. */
17110 immbits = 0xdeadbeef;
17111 }
17112 }
17113
5287ad62 17114 switch (opcode)
477330fc
RM		 17115 {
17116 case N_MNEM_vbic:
17117 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17118 break;
17119
17120 case N_MNEM_vorr:
17121 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17122 break;
17123
17124 case N_MNEM_vand:
17125 /* Pseudo-instruction for VBIC. */
17126 neon_invert_size (&immbits, 0, et.size);
17127 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17128 break;
17129
17130 case N_MNEM_vorn:
17131 /* Pseudo-instruction for VORR. */
17132 neon_invert_size (&immbits, 0, et.size);
17133 cmode = neon_cmode_for_logic_imm (immbits, &immbits, et.size);
17134 break;
17135
17136 default:
17137 abort ();
17138 }
5287ad62
JB		 17139
17140 if (cmode == FAIL)
477330fc 17141 return;
5287ad62 17142
037e8744 17143 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 17144 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17145 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17146 inst.instruction |= cmode << 8;
17147 neon_write_immbits (immbits);
5f4273c7 17148
88714cb8 17149 neon_dp_fixup (&inst);
5287ad62
JB		 17150 }
17151}
17152
17153static void
17154do_neon_bitfield (void)
17155{
037e8744 17156 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
dcbf9037 17157 neon_check_type (3, rs, N_IGNORE_TYPE);
037e8744 17158 neon_three_same (neon_quad (rs), 0, -1);
5287ad62
JB		 17159}
17160
17161static void
dcbf9037 17162neon_dyadic_misc (enum neon_el_type ubit_meaning, unsigned types,
477330fc 17163 unsigned destbits)
5287ad62 17164{
5ee91343 17165 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
dcbf9037 17166 struct neon_type_el et = neon_check_type (3, rs, N_EQK | destbits, N_EQK,
477330fc 17167 types | N_KEY);
5287ad62
JB		 17168 if (et.type == NT_float)
17169 {
88714cb8 17170 NEON_ENCODE (FLOAT, inst);
5ee91343 17171 if (rs == NS_QQR)
7df54120 17172 mve_encode_qqr (et.size, 0, 1);
5ee91343
AV		 17173 else
17174 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 17175 }
17176 else
17177 {
88714cb8 17178 NEON_ENCODE (INTEGER, inst);
5ee91343 17179 if (rs == NS_QQR)
a8465a06 17180 mve_encode_qqr (et.size, et.type == ubit_meaning, 0);
5ee91343
AV		 17181 else
17182 neon_three_same (neon_quad (rs), et.type == ubit_meaning, et.size);
5287ad62
JB		 17183 }
17184}
17185
5287ad62
JB		 17186
17187static void
17188do_neon_dyadic_if_su_d (void)
17189{
17190 /* This version only allow D registers, but that constraint is enforced during
17191 operand parsing so we don't need to do anything extra here. */
dcbf9037 17192 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
5287ad62
JB		 17193}
17194
5287ad62
JB		 17195static void
17196do_neon_dyadic_if_i_d (void)
17197{
428e3f1f
PB		 17198 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17199 affected if we specify unsigned args. */
17200 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
5287ad62
JB		 17201}
17202
f5f10c66
AV		 17203static void
17204do_mve_vstr_vldr_QI (int size, int elsize, int load)
17205{
17206 constraint (size < 32, BAD_ADDR_MODE);
17207 constraint (size != elsize, BAD_EL_TYPE);
17208 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
17209 constraint (!inst.operands[1].preind, BAD_ADDR_MODE);
17210 constraint (load && inst.operands[0].reg == inst.operands[1].reg,
17211 _("destination register and offset register may not be the"
17212 " same"));
17213
17214 int imm = inst.relocs[0].exp.X_add_number;
17215 int add = 1;
17216 if (imm < 0)
17217 {
17218 add = 0;
17219 imm = -imm;
17220 }
17221 constraint ((imm % (size / 8) != 0)
17222 || imm > (0x7f << neon_logbits (size)),
17223 (size == 32) ? _("immediate must be a multiple of 4 in the"
17224 " range of +/-[0,508]")
17225 : _("immediate must be a multiple of 8 in the"
17226 " range of +/-[0,1016]"));
17227 inst.instruction |= 0x11 << 24;
17228 inst.instruction |= add << 23;
17229 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17230 inst.instruction |= inst.operands[1].writeback << 21;
17231 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17232 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17233 inst.instruction |= 1 << 12;
17234 inst.instruction |= (size == 64) << 8;
17235 inst.instruction &= 0xffffff00;
17236 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17237 inst.instruction |= imm >> neon_logbits (size);
17238}
17239
17240static void
17241do_mve_vstr_vldr_RQ (int size, int elsize, int load)
17242{
17243 unsigned os = inst.operands[1].imm >> 5;
17244 constraint (os != 0 && size == 8,
17245 _("can not shift offsets when accessing less than half-word"));
17246 constraint (os && os != neon_logbits (size),
17247 _("shift immediate must be 1, 2 or 3 for half-word, word"
17248 " or double-word accesses respectively"));
17249 if (inst.operands[1].reg == REG_PC)
17250 as_tsktsk (MVE_BAD_PC);
17251
17252 switch (size)
17253 {
17254 case 8:
17255 constraint (elsize >= 64, BAD_EL_TYPE);
17256 break;
17257 case 16:
17258 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17259 break;
17260 case 32:
17261 case 64:
17262 constraint (elsize != size, BAD_EL_TYPE);
17263 break;
17264 default:
17265 break;
17266 }
17267 constraint (inst.operands[1].writeback || !inst.operands[1].preind,
17268 BAD_ADDR_MODE);
17269 if (load)
17270 {
17271 constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f),
17272 _("destination register and offset register may not be"
17273 " the same"));
17274 constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned,
17275 BAD_EL_TYPE);
17276 constraint (inst.vectype.el[0].type != NT_unsigned
17277 && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE);
17278 inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28;
17279 }
17280 else
17281 {
17282 constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE);
17283 }
17284
17285 inst.instruction |= 1 << 23;
17286 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17287 inst.instruction |= inst.operands[1].reg << 16;
17288 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17289 inst.instruction |= neon_logbits (elsize) << 7;
17290 inst.instruction |= HI1 (inst.operands[1].imm) << 5;
17291 inst.instruction |= LOW4 (inst.operands[1].imm);
17292 inst.instruction |= !!os;
17293}
17294
17295static void
17296do_mve_vstr_vldr_RI (int size, int elsize, int load)
17297{
17298 enum neon_el_type type = inst.vectype.el[0].type;
17299
17300 constraint (size >= 64, BAD_ADDR_MODE);
17301 switch (size)
17302 {
17303 case 16:
17304 constraint (elsize < 16 || elsize >= 64, BAD_EL_TYPE);
17305 break;
17306 case 32:
17307 constraint (elsize != size, BAD_EL_TYPE);
17308 break;
17309 default:
17310 break;
17311 }
17312 if (load)
17313 {
17314 constraint (elsize != size && type != NT_unsigned
17315 && type != NT_signed, BAD_EL_TYPE);
17316 }
17317 else
17318 {
17319 constraint (elsize != size && type != NT_untyped, BAD_EL_TYPE);
17320 }
17321
17322 int imm = inst.relocs[0].exp.X_add_number;
17323 int add = 1;
17324 if (imm < 0)
17325 {
17326 add = 0;
17327 imm = -imm;
17328 }
17329
17330 if ((imm % (size / 8) != 0) || imm > (0x7f << neon_logbits (size)))
17331 {
17332 switch (size)
17333 {
17334 case 8:
17335 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17336 break;
17337 case 16:
17338 constraint (1, _("immediate must be a multiple of 2 in the"
17339 " range of +/-[0,254]"));
17340 break;
17341 case 32:
17342 constraint (1, _("immediate must be a multiple of 4 in the"
17343 " range of +/-[0,508]"));
17344 break;
17345 }
17346 }
17347
17348 if (size != elsize)
17349 {
17350 constraint (inst.operands[1].reg > 7, BAD_HIREG);
17351 constraint (inst.operands[0].reg > 14,
17352 _("MVE vector register in the range [Q0..Q7] expected"));
17353 inst.instruction |= (load && type == NT_unsigned) << 28;
17354 inst.instruction |= (size == 16) << 19;
17355 inst.instruction |= neon_logbits (elsize) << 7;
17356 }
17357 else
17358 {
17359 if (inst.operands[1].reg == REG_PC)
17360 as_tsktsk (MVE_BAD_PC);
17361 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17362 as_tsktsk (MVE_BAD_SP);
17363 inst.instruction |= 1 << 12;
17364 inst.instruction |= neon_logbits (size) << 7;
17365 }
17366 inst.instruction |= inst.operands[1].preind << 24;
17367 inst.instruction |= add << 23;
17368 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17369 inst.instruction |= inst.operands[1].writeback << 21;
17370 inst.instruction |= inst.operands[1].reg << 16;
17371 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17372 inst.instruction &= 0xffffff80;
17373 inst.instruction |= imm >> neon_logbits (size);
17374
17375}
17376
17377static void
17378do_mve_vstr_vldr (void)
17379{
17380 unsigned size;
17381 int load = 0;
17382
17383 if (inst.cond > COND_ALWAYS)
17384 inst.pred_insn_type = INSIDE_VPT_INSN;
17385 else
17386 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17387
17388 switch (inst.instruction)
17389 {
17390 default:
17391 gas_assert (0);
17392 break;
17393 case M_MNEM_vldrb:
17394 load = 1;
17395 /* fall through. */
17396 case M_MNEM_vstrb:
17397 size = 8;
17398 break;
17399 case M_MNEM_vldrh:
17400 load = 1;
17401 /* fall through. */
17402 case M_MNEM_vstrh:
17403 size = 16;
17404 break;
17405 case M_MNEM_vldrw:
17406 load = 1;
17407 /* fall through. */
17408 case M_MNEM_vstrw:
17409 size = 32;
17410 break;
17411 case M_MNEM_vldrd:
17412 load = 1;
17413 /* fall through. */
17414 case M_MNEM_vstrd:
17415 size = 64;
17416 break;
17417 }
17418 unsigned elsize = inst.vectype.el[0].size;
17419
17420 if (inst.operands[1].isquad)
17421 {
17422 /* We are dealing with [Q, imm]{!} cases. */
17423 do_mve_vstr_vldr_QI (size, elsize, load);
17424 }
17425 else
17426 {
17427 if (inst.operands[1].immisreg == 2)
17428 {
17429 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17430 do_mve_vstr_vldr_RQ (size, elsize, load);
17431 }
17432 else if (!inst.operands[1].immisreg)
17433 {
17434 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17435 do_mve_vstr_vldr_RI (size, elsize, load);
17436 }
17437 else
17438 constraint (1, BAD_ADDR_MODE);
17439 }
17440
17441 inst.is_neon = 1;
17442}
17443
35c228db
AV		 17444static void
17445do_mve_vst_vld (void)
17446{
17447 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17448 return;
17449
17450 constraint (!inst.operands[1].preind || inst.relocs[0].exp.X_add_symbol != 0
17451 || inst.relocs[0].exp.X_add_number != 0
17452 || inst.operands[1].immisreg != 0,
17453 BAD_ADDR_MODE);
17454 constraint (inst.vectype.el[0].size > 32, BAD_EL_TYPE);
17455 if (inst.operands[1].reg == REG_PC)
17456 as_tsktsk (MVE_BAD_PC);
17457 else if (inst.operands[1].reg == REG_SP && inst.operands[1].writeback)
17458 as_tsktsk (MVE_BAD_SP);
17459
17460
17461 /* These instructions are one of the "exceptions" mentioned in
17462 handle_pred_state. They are MVE instructions that are not VPT compatible
17463 and do not accept a VPT code, thus appending such a code is a syntax
17464 error. */
17465 if (inst.cond > COND_ALWAYS)
17466 first_error (BAD_SYNTAX);
17467 /* If we append a scalar condition code we can set this to
17468 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17469 else if (inst.cond < COND_ALWAYS)
17470 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17471 else
17472 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
17473
17474 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17475 inst.instruction |= inst.operands[1].writeback << 21;
17476 inst.instruction |= inst.operands[1].reg << 16;
17477 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17478 inst.instruction |= neon_logbits (inst.vectype.el[0].size) << 7;
17479 inst.is_neon = 1;
17480}
17481
26c1e780
AV		 17482static void
17483do_mve_vaddlv (void)
17484{
17485 enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
17486 struct neon_type_el et
17487 = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
17488
17489 if (et.type == NT_invtype)
17490 first_error (BAD_EL_TYPE);
17491
17492 if (inst.cond > COND_ALWAYS)
17493 inst.pred_insn_type = INSIDE_VPT_INSN;
17494 else
17495 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17496
17497 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17498
17499 inst.instruction |= (et.type == NT_unsigned) << 28;
17500 inst.instruction |= inst.operands[1].reg << 19;
17501 inst.instruction |= inst.operands[0].reg << 12;
17502 inst.instruction |= inst.operands[2].reg;
17503 inst.is_neon = 1;
17504}
17505
5287ad62 17506static void
5ee91343 17507do_neon_dyadic_if_su (void)
5287ad62 17508{
5ee91343
AV		 17509 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17510 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
17511 N_SUF_32 | N_KEY);
17512
935295b5
AV		 17513 constraint ((inst.instruction == ((unsigned) N_MNEM_vmax)
17514 || inst.instruction == ((unsigned) N_MNEM_vmin))
17515 && et.type == NT_float
17516 && !ARM_CPU_HAS_FEATURE (cpu_variant,fpu_neon_ext_v1), BAD_FPU);
17517
64c350f2
AV		 17518 if (!check_simd_pred_availability (et.type == NT_float,
17519 NEON_CHECK_ARCH | NEON_CHECK_CC))
037e8744
JB		 17520 return;
17521
5ee91343
AV		 17522 neon_dyadic_misc (NT_unsigned, N_SUF_32, 0);
17523}
17524
17525static void
17526do_neon_addsub_if_i (void)
17527{
17528 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1xd)
17529 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub) == SUCCESS)
037e8744
JB		 17530 return;
17531
5ee91343
AV		 17532 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_QQR, NS_NULL);
17533 struct neon_type_el et = neon_check_type (3, rs, N_EQK,
17534 N_EQK, N_IF_32 | N_I64 | N_KEY);
17535
17536 constraint (rs == NS_QQR && et.size == 64, BAD_FPU);
17537 /* If we are parsing Q registers and the element types match MVE, which NEON
17538 also supports, then we must check whether this is an instruction that can
17539 be used by both MVE/NEON. This distinction can be made based on whether
17540 they are predicated or not. */
17541 if ((rs == NS_QQQ || rs == NS_QQR) && et.size != 64)
17542 {
64c350f2
AV		 17543 if (!check_simd_pred_availability (et.type == NT_float,
17544 NEON_CHECK_ARCH | NEON_CHECK_CC))
5ee91343
AV		 17545 return;
17546 }
17547 else
17548 {
17549 /* If they are either in a D register or are using an unsupported. */
17550 if (rs != NS_QQR
17551 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
17552 return;
17553 }
17554
5287ad62
JB		 17555 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17556 affected if we specify unsigned args. */
dcbf9037 17557 neon_dyadic_misc (NT_untyped, N_IF_32 | N_I64, 0);
5287ad62
JB		 17558}
17559
17560/* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17561 result to be:
17562 V<op> A,B (A is operand 0, B is operand 2)
17563 to mean:
17564 V<op> A,B,A
17565 not:
17566 V<op> A,B,B
17567 so handle that case specially. */
17568
17569static void
17570neon_exchange_operands (void)
17571{
5287ad62
JB		 17572 if (inst.operands[1].present)
17573 {
e1fa0163
NC		 17574 void *scratch = xmalloc (sizeof (inst.operands[0]));
17575
5287ad62
JB		 17576 /* Swap operands[1] and operands[2]. */
17577 memcpy (scratch, &inst.operands[1], sizeof (inst.operands[0]));
17578 inst.operands[1] = inst.operands[2];
17579 memcpy (&inst.operands[2], scratch, sizeof (inst.operands[0]));
e1fa0163 17580 free (scratch);
5287ad62
JB		 17581 }
17582 else
17583 {
17584 inst.operands[1] = inst.operands[2];
17585 inst.operands[2] = inst.operands[0];
17586 }
17587}
17588
17589static void
17590neon_compare (unsigned regtypes, unsigned immtypes, int invert)
17591{
17592 if (inst.operands[2].isreg)
17593 {
17594 if (invert)
477330fc 17595 neon_exchange_operands ();
dcbf9037 17596 neon_dyadic_misc (NT_unsigned, regtypes, N_SIZ);
5287ad62
JB		 17597 }
17598 else
17599 {
037e8744 17600 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
dcbf9037 17601 struct neon_type_el et = neon_check_type (2, rs,
477330fc 17602 N_EQK | N_SIZ, immtypes | N_KEY);
5287ad62 17603
88714cb8 17604 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 17605 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17606 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17607 inst.instruction |= LOW4 (inst.operands[1].reg);
17608 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 17609 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 17610 inst.instruction |= (et.type == NT_float) << 10;
17611 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 17612
88714cb8 17613 neon_dp_fixup (&inst);
5287ad62
JB		 17614 }
17615}
17616
17617static void
17618do_neon_cmp (void)
17619{
cc933301 17620 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, FALSE);
5287ad62
JB		 17621}
17622
17623static void
17624do_neon_cmp_inv (void)
17625{
cc933301 17626 neon_compare (N_SUF_32, N_S_32 | N_F_16_32, TRUE);
5287ad62
JB		 17627}
17628
17629static void
17630do_neon_ceq (void)
17631{
17632 neon_compare (N_IF_32, N_IF_32, FALSE);
17633}
17634
17635/* For multiply instructions, we have the possibility of 16-bit or 32-bit
17636 scalars, which are encoded in 5 bits, M : Rm.
17637 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17638 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
c604a79a
JW		 17639 index in M.
17640
17641 Dot Product instructions are similar to multiply instructions except elsize
17642 should always be 32.
17643
17644 This function translates SCALAR, which is GAS's internal encoding of indexed
17645 scalar register, to raw encoding. There is also register and index range
17646 check based on ELSIZE. */
5287ad62
JB		 17647
17648static unsigned
17649neon_scalar_for_mul (unsigned scalar, unsigned elsize)
17650{
dcbf9037
JB		 17651 unsigned regno = NEON_SCALAR_REG (scalar);
17652 unsigned elno = NEON_SCALAR_INDEX (scalar);
5287ad62
JB		 17653
17654 switch (elsize)
17655 {
17656 case 16:
17657 if (regno > 7 || elno > 3)
477330fc 17658 goto bad_scalar;
5287ad62 17659 return regno | (elno << 3);
5f4273c7 17660
5287ad62
JB		 17661 case 32:
17662 if (regno > 15 || elno > 1)
477330fc 17663 goto bad_scalar;
5287ad62
JB		 17664 return regno | (elno << 4);
17665
17666 default:
17667 bad_scalar:
dcbf9037 17668 first_error (_("scalar out of range for multiply instruction"));
5287ad62
JB		 17669 }
17670
17671 return 0;
17672}
17673
17674/* Encode multiply / multiply-accumulate scalar instructions. */
17675
17676static void
17677neon_mul_mac (struct neon_type_el et, int ubit)
17678{
dcbf9037
JB		 17679 unsigned scalar;
17680
17681 /* Give a more helpful error message if we have an invalid type. */
17682 if (et.type == NT_invtype)
17683 return;
5f4273c7 17684
dcbf9037 17685 scalar = neon_scalar_for_mul (inst.operands[2].reg, et.size);
5287ad62
JB		 17686 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17687 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17688 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17689 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
17690 inst.instruction |= LOW4 (scalar);
17691 inst.instruction |= HI1 (scalar) << 5;
17692 inst.instruction |= (et.type == NT_float) << 8;
17693 inst.instruction |= neon_logbits (et.size) << 20;
17694 inst.instruction |= (ubit != 0) << 24;
17695
88714cb8 17696 neon_dp_fixup (&inst);
5287ad62
JB		 17697}
17698
17699static void
17700do_neon_mac_maybe_scalar (void)
17701{
037e8744
JB		 17702 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls) == SUCCESS)
17703 return;
17704
64c350f2 17705 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB		 17706 return;
17707
5287ad62
JB		 17708 if (inst.operands[2].isscalar)
17709 {
a8465a06 17710 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17711 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17712 struct neon_type_el et = neon_check_type (3, rs,
589a7d88 17713 N_EQK, N_EQK, N_I16 | N_I32 | N_F_16_32 | N_KEY);
88714cb8 17714 NEON_ENCODE (SCALAR, inst);
037e8744 17715 neon_mul_mac (et, neon_quad (rs));
5287ad62 17716 }
a8465a06
AV		 17717 else if (!inst.operands[2].isvec)
17718 {
17719 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17720
17721 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17722 neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17723
17724 neon_dyadic_misc (NT_unsigned, N_SU_MVE, 0);
17725 }
5287ad62 17726 else
428e3f1f 17727 {
a8465a06 17728 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
428e3f1f
PB		 17729 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17730 affected if we specify unsigned args. */
17731 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17732 }
5287ad62
JB		 17733}
17734
62f3b8c8
PB		 17735static void
17736do_neon_fmac (void)
17737{
d58196e0
AV		 17738 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_fma)
17739 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms) == SUCCESS)
62f3b8c8
PB		 17740 return;
17741
64c350f2 17742 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH))
62f3b8c8
PB		 17743 return;
17744
d58196e0
AV		 17745 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
17746 {
17747 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17748 struct neon_type_el et = neon_check_type (3, rs, N_F_MVE | N_KEY, N_EQK,
17749 N_EQK);
17750
17751 if (rs == NS_QQR)
17752 {
17753 if (inst.operands[2].reg == REG_SP)
17754 as_tsktsk (MVE_BAD_SP);
17755 else if (inst.operands[2].reg == REG_PC)
17756 as_tsktsk (MVE_BAD_PC);
17757
17758 inst.instruction = 0xee310e40;
17759 inst.instruction |= (et.size == 16) << 28;
17760 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
17761 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
17762 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
17763 inst.instruction |= HI1 (inst.operands[1].reg) << 6;
17764 inst.instruction |= inst.operands[2].reg;
17765 inst.is_neon = 1;
17766 return;
17767 }
17768 }
17769 else
17770 {
17771 constraint (!inst.operands[2].isvec, BAD_FPU);
17772 }
17773
62f3b8c8
PB		 17774 neon_dyadic_misc (NT_untyped, N_IF_32, 0);
17775}
17776
5287ad62
JB		 17777static void
17778do_neon_tst (void)
17779{
037e8744 17780 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
5287ad62
JB		 17781 struct neon_type_el et = neon_check_type (3, rs,
17782 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
037e8744 17783 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 17784}
17785
17786/* VMUL with 3 registers allows the P8 type. The scalar version supports the
17787 same types as the MAC equivalents. The polynomial type for this instruction
17788 is encoded the same as the integer type. */
17789
17790static void
17791do_neon_mul (void)
17792{
037e8744
JB		 17793 if (try_vfp_nsyn (3, do_vfp_nsyn_mul) == SUCCESS)
17794 return;
17795
64c350f2 17796 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
037e8744
JB		 17797 return;
17798
5287ad62 17799 if (inst.operands[2].isscalar)
a8465a06
AV		 17800 {
17801 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
17802 do_neon_mac_maybe_scalar ();
17803 }
5287ad62 17804 else
a8465a06
AV		 17805 {
17806 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17807 {
17808 enum neon_shape rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17809 struct neon_type_el et
17810 = neon_check_type (3, rs, N_EQK, N_EQK, N_I_MVE | N_F_MVE | N_KEY);
17811 if (et.type == NT_float)
17812 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext),
17813 BAD_FPU);
17814
17815 neon_dyadic_misc (NT_float, N_I_MVE | N_F_MVE, 0);
17816 }
17817 else
17818 {
17819 constraint (!inst.operands[2].isvec, BAD_FPU);
17820 neon_dyadic_misc (NT_poly,
17821 N_I8 | N_I16 | N_I32 | N_F16 | N_F32 | N_P8, 0);
17822 }
17823 }
5287ad62
JB		 17824}
17825
17826static void
17827do_neon_qdmulh (void)
17828{
64c350f2 17829 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV		 17830 return;
17831
5287ad62
JB		 17832 if (inst.operands[2].isscalar)
17833 {
42b16635 17834 constraint (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
037e8744 17835 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
5287ad62 17836 struct neon_type_el et = neon_check_type (3, rs,
477330fc 17837 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
88714cb8 17838 NEON_ENCODE (SCALAR, inst);
037e8744 17839 neon_mul_mac (et, neon_quad (rs));
5287ad62
JB		 17840 }
17841 else
17842 {
42b16635
AV		 17843 enum neon_shape rs;
17844 struct neon_type_el et;
17845 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
17846 {
17847 rs = neon_select_shape (NS_QQR, NS_QQQ, NS_NULL);
17848 et = neon_check_type (3, rs,
17849 N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17850 }
17851 else
17852 {
17853 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
17854 et = neon_check_type (3, rs,
17855 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17856 }
17857
88714cb8 17858 NEON_ENCODE (INTEGER, inst);
42b16635
AV		 17859 if (rs == NS_QQR)
17860 mve_encode_qqr (et.size, 0, 0);
17861 else
17862 /* The U bit (rounding) comes from bit mask. */
17863 neon_three_same (neon_quad (rs), 0, et.size);
5287ad62
JB		 17864 }
17865}
17866
26c1e780
AV		 17867static void
17868do_mve_vaddv (void)
17869{
17870 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
17871 struct neon_type_el et
17872 = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
17873
17874 if (et.type == NT_invtype)
17875 first_error (BAD_EL_TYPE);
17876
17877 if (inst.cond > COND_ALWAYS)
17878 inst.pred_insn_type = INSIDE_VPT_INSN;
17879 else
17880 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17881
17882 constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
17883
17884 mve_encode_rq (et.type == NT_unsigned, et.size);
17885}
17886
7df54120
AV		 17887static void
17888do_mve_vhcadd (void)
17889{
17890 enum neon_shape rs = neon_select_shape (NS_QQQI, NS_NULL);
17891 struct neon_type_el et
17892 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
17893
17894 if (inst.cond > COND_ALWAYS)
17895 inst.pred_insn_type = INSIDE_VPT_INSN;
17896 else
17897 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17898
17899 unsigned rot = inst.relocs[0].exp.X_add_number;
17900 constraint (rot != 90 && rot != 270, _("immediate out of range"));
17901
17902 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
17903 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17904 "operand makes instruction UNPREDICTABLE"));
17905
17906 mve_encode_qqq (0, et.size);
17907 inst.instruction |= (rot == 270) << 12;
17908 inst.is_neon = 1;
17909}
17910
35d1cfc2
AV		 17911static void
17912do_mve_vqdmull (void)
17913{
17914 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_QQR, NS_NULL);
17915 struct neon_type_el et
17916 = neon_check_type (3, rs, N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
17917
17918 if (et.size == 32
17919 && (inst.operands[0].reg == inst.operands[1].reg
17920 || (rs == NS_QQQ && inst.operands[0].reg == inst.operands[2].reg)))
17921 as_tsktsk (BAD_MVE_SRCDEST);
17922
17923 if (inst.cond > COND_ALWAYS)
17924 inst.pred_insn_type = INSIDE_VPT_INSN;
17925 else
17926 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17927
17928 if (rs == NS_QQQ)
17929 {
17930 mve_encode_qqq (et.size == 32, 64);
17931 inst.instruction |= 1;
17932 }
17933 else
17934 {
17935 mve_encode_qqr (64, et.size == 32, 0);
17936 inst.instruction |= 0x3 << 5;
17937 }
17938}
17939
c2dafc2a
AV		 17940static void
17941do_mve_vadc (void)
17942{
17943 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17944 struct neon_type_el et
17945 = neon_check_type (3, rs, N_KEY | N_I32, N_EQK, N_EQK);
17946
17947 if (et.type == NT_invtype)
17948 first_error (BAD_EL_TYPE);
17949
17950 if (inst.cond > COND_ALWAYS)
17951 inst.pred_insn_type = INSIDE_VPT_INSN;
17952 else
17953 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17954
17955 mve_encode_qqq (0, 64);
17956}
17957
17958static void
17959do_mve_vbrsr (void)
17960{
17961 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
17962 struct neon_type_el et
17963 = neon_check_type (3, rs, N_EQK, N_EQK, N_8 | N_16 | N_32 | N_KEY);
17964
17965 if (inst.cond > COND_ALWAYS)
17966 inst.pred_insn_type = INSIDE_VPT_INSN;
17967 else
17968 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17969
7df54120 17970 mve_encode_qqr (et.size, 0, 0);
c2dafc2a
AV		 17971}
17972
17973static void
17974do_mve_vsbc (void)
17975{
17976 neon_check_type (3, NS_QQQ, N_EQK, N_EQK, N_I32 | N_KEY);
17977
17978 if (inst.cond > COND_ALWAYS)
17979 inst.pred_insn_type = INSIDE_VPT_INSN;
17980 else
17981 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17982
17983 mve_encode_qqq (1, 64);
17984}
17985
2d78f95b
AV		 17986static void
17987do_mve_vmulh (void)
17988{
17989 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
17990 struct neon_type_el et
17991 = neon_check_type (3, rs, N_EQK, N_EQK, N_SU_MVE | N_KEY);
17992
17993 if (inst.cond > COND_ALWAYS)
17994 inst.pred_insn_type = INSIDE_VPT_INSN;
17995 else
17996 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
17997
17998 mve_encode_qqq (et.type == NT_unsigned, et.size);
17999}
18000
42b16635
AV		 18001static void
18002do_mve_vqdmlah (void)
18003{
18004 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18005 struct neon_type_el et
23d188c7 18006 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
42b16635
AV		 18007
18008 if (inst.cond > COND_ALWAYS)
18009 inst.pred_insn_type = INSIDE_VPT_INSN;
18010 else
18011 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18012
18013 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
18014}
8b8b22a4
AV		 18015
18016static void
18017do_mve_vqdmladh (void)
18018{
18019 enum neon_shape rs = neon_select_shape (NS_QQQ, NS_NULL);
18020 struct neon_type_el et
18021 = neon_check_type (3, rs, N_EQK, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18022
18023 if (inst.cond > COND_ALWAYS)
18024 inst.pred_insn_type = INSIDE_VPT_INSN;
18025 else
18026 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18027
8b8b22a4
AV		 18028 mve_encode_qqq (0, et.size);
18029}
18030
18031
886e1c73
AV		 18032static void
18033do_mve_vmull (void)
18034{
18035
18036 enum neon_shape rs = neon_select_shape (NS_HHH, NS_FFF, NS_DDD, NS_DDS,
18037 NS_QQS, NS_QQQ, NS_QQR, NS_NULL);
18038 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
18039 && inst.cond == COND_ALWAYS
18040 && ((unsigned)inst.instruction) == M_MNEM_vmullt)
18041 {
18042 if (rs == NS_QQQ)
18043 {
18044
18045 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18046 N_SUF_32 | N_F64 | N_P8
18047 | N_P16 | N_I_MVE | N_KEY);
18048 if (((et.type == NT_poly) && et.size == 8
18049 && ARM_CPU_IS_ANY (cpu_variant))
18050 || (et.type == NT_integer) || (et.type == NT_float))
18051 goto neon_vmul;
18052 }
18053 else
18054 goto neon_vmul;
18055 }
18056
18057 constraint (rs != NS_QQQ, BAD_FPU);
18058 struct neon_type_el et = neon_check_type (3, rs, N_EQK , N_EQK,
18059 N_SU_32 | N_P8 | N_P16 | N_KEY);
18060
18061 /* We are dealing with MVE's vmullt. */
18062 if (et.size == 32
18063 && (inst.operands[0].reg == inst.operands[1].reg
18064 || inst.operands[0].reg == inst.operands[2].reg))
18065 as_tsktsk (BAD_MVE_SRCDEST);
18066
18067 if (inst.cond > COND_ALWAYS)
18068 inst.pred_insn_type = INSIDE_VPT_INSN;
18069 else
18070 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18071
18072 if (et.type == NT_poly)
18073 mve_encode_qqq (neon_logbits (et.size), 64);
18074 else
18075 mve_encode_qqq (et.type == NT_unsigned, et.size);
18076
18077 return;
18078
18079neon_vmul:
18080 inst.instruction = N_MNEM_vmul;
18081 inst.cond = 0xb;
18082 if (thumb_mode)
18083 inst.pred_insn_type = INSIDE_IT_INSN;
18084 do_neon_mul ();
18085}
18086
a302e574
AV		 18087static void
18088do_mve_vabav (void)
18089{
18090 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18091
18092 if (rs == NS_NULL)
18093 return;
18094
18095 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18096 return;
18097
18098 struct neon_type_el et = neon_check_type (2, NS_NULL, N_EQK, N_KEY | N_S8
18099 | N_S16 | N_S32 | N_U8 | N_U16
18100 | N_U32);
18101
18102 if (inst.cond > COND_ALWAYS)
18103 inst.pred_insn_type = INSIDE_VPT_INSN;
18104 else
18105 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18106
18107 mve_encode_rqq (et.type == NT_unsigned, et.size);
18108}
18109
18110static void
18111do_mve_vmladav (void)
18112{
18113 enum neon_shape rs = neon_select_shape (NS_RQQ, NS_NULL);
18114 struct neon_type_el et = neon_check_type (3, rs,
18115 N_EQK, N_EQK, N_SU_MVE | N_KEY);
18116
18117 if (et.type == NT_unsigned
18118 && (inst.instruction == M_MNEM_vmladavx
18119 || inst.instruction == M_MNEM_vmladavax
18120 || inst.instruction == M_MNEM_vmlsdav
18121 || inst.instruction == M_MNEM_vmlsdava
18122 || inst.instruction == M_MNEM_vmlsdavx
18123 || inst.instruction == M_MNEM_vmlsdavax))
18124 first_error (BAD_SIMD_TYPE);
18125
18126 constraint (inst.operands[2].reg > 14,
18127 _("MVE vector register in the range [Q0..Q7] expected"));
18128
18129 if (inst.cond > COND_ALWAYS)
18130 inst.pred_insn_type = INSIDE_VPT_INSN;
18131 else
18132 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18133
18134 if (inst.instruction == M_MNEM_vmlsdav
18135 || inst.instruction == M_MNEM_vmlsdava
18136 || inst.instruction == M_MNEM_vmlsdavx
18137 || inst.instruction == M_MNEM_vmlsdavax)
18138 inst.instruction |= (et.size == 8) << 28;
18139 else
18140 inst.instruction |= (et.size == 8) << 8;
18141
18142 mve_encode_rqq (et.type == NT_unsigned, 64);
18143 inst.instruction |= (et.size == 32) << 16;
18144}
18145
93925576
AV		 18146static void
18147do_mve_vmlaldav (void)
18148{
18149 enum neon_shape rs = neon_select_shape (NS_RRQQ, NS_NULL);
18150 struct neon_type_el et
18151 = neon_check_type (4, rs, N_EQK, N_EQK, N_EQK,
18152 N_S16 | N_S32 | N_U16 | N_U32 | N_KEY);
18153
18154 if (et.type == NT_unsigned
18155 && (inst.instruction == M_MNEM_vmlsldav
18156 || inst.instruction == M_MNEM_vmlsldava
18157 || inst.instruction == M_MNEM_vmlsldavx
18158 || inst.instruction == M_MNEM_vmlsldavax))
18159 first_error (BAD_SIMD_TYPE);
18160
18161 if (inst.cond > COND_ALWAYS)
18162 inst.pred_insn_type = INSIDE_VPT_INSN;
18163 else
18164 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18165
18166 mve_encode_rrqq (et.type == NT_unsigned, et.size);
18167}
18168
18169static void
18170do_mve_vrmlaldavh (void)
18171{
18172 struct neon_type_el et;
18173 if (inst.instruction == M_MNEM_vrmlsldavh
18174 || inst.instruction == M_MNEM_vrmlsldavha
18175 || inst.instruction == M_MNEM_vrmlsldavhx
18176 || inst.instruction == M_MNEM_vrmlsldavhax)
18177 {
18178 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18179 if (inst.operands[1].reg == REG_SP)
18180 as_tsktsk (MVE_BAD_SP);
18181 }
18182 else
18183 {
18184 if (inst.instruction == M_MNEM_vrmlaldavhx
18185 || inst.instruction == M_MNEM_vrmlaldavhax)
18186 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK, N_S32 | N_KEY);
18187 else
18188 et = neon_check_type (4, NS_RRQQ, N_EQK, N_EQK, N_EQK,
18189 N_U32 | N_S32 | N_KEY);
18190 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18191 with vmax/min instructions, making the use of SP in assembly really
18192 nonsensical, so instead of issuing a warning like we do for other uses
18193 of SP for the odd register operand we error out. */
18194 constraint (inst.operands[1].reg == REG_SP, BAD_SP);
18195 }
18196
18197 /* Make sure we still check the second operand is an odd one and that PC is
18198 disallowed. This because we are parsing for any GPR operand, to be able
18199 to distinguish between giving a warning or an error for SP as described
18200 above. */
18201 constraint ((inst.operands[1].reg % 2) != 1, BAD_EVEN);
18202 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
18203
18204 if (inst.cond > COND_ALWAYS)
18205 inst.pred_insn_type = INSIDE_VPT_INSN;
18206 else
18207 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18208
18209 mve_encode_rrqq (et.type == NT_unsigned, 0);
18210}
18211
18212
8cd78170
AV		 18213static void
18214do_mve_vmaxnmv (void)
18215{
18216 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18217 struct neon_type_el et
18218 = neon_check_type (2, rs, N_EQK, N_F_MVE | N_KEY);
18219
18220 if (inst.cond > COND_ALWAYS)
18221 inst.pred_insn_type = INSIDE_VPT_INSN;
18222 else
18223 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18224
18225 if (inst.operands[0].reg == REG_SP)
18226 as_tsktsk (MVE_BAD_SP);
18227 else if (inst.operands[0].reg == REG_PC)
18228 as_tsktsk (MVE_BAD_PC);
18229
18230 mve_encode_rq (et.size == 16, 64);
18231}
18232
13ccd4c0
AV		 18233static void
18234do_mve_vmaxv (void)
18235{
18236 enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
18237 struct neon_type_el et;
18238
18239 if (inst.instruction == M_MNEM_vmaxv || inst.instruction == M_MNEM_vminv)
18240 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
18241 else
18242 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18243
18244 if (inst.cond > COND_ALWAYS)
18245 inst.pred_insn_type = INSIDE_VPT_INSN;
18246 else
18247 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
18248
18249 if (inst.operands[0].reg == REG_SP)
18250 as_tsktsk (MVE_BAD_SP);
18251 else if (inst.operands[0].reg == REG_PC)
18252 as_tsktsk (MVE_BAD_PC);
18253
18254 mve_encode_rq (et.type == NT_unsigned, et.size);
18255}
18256
18257
643afb90
MW		 18258static void
18259do_neon_qrdmlah (void)
18260{
64c350f2 18261 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
42b16635
AV		 18262 return;
18263 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
643afb90 18264 {
42b16635
AV		 18265 /* Check we're on the correct architecture. */
18266 if (!mark_feature_used (&fpu_neon_ext_armv8))
18267 inst.error
18268 = _("instruction form not available on this architecture.");
18269 else if (!mark_feature_used (&fpu_neon_ext_v8_1))
18270 {
18271 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18272 record_feature_use (&fpu_neon_ext_v8_1);
18273 }
18274 if (inst.operands[2].isscalar)
18275 {
18276 enum neon_shape rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
18277 struct neon_type_el et = neon_check_type (3, rs,
18278 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18279 NEON_ENCODE (SCALAR, inst);
18280 neon_mul_mac (et, neon_quad (rs));
18281 }
18282 else
18283 {
18284 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
18285 struct neon_type_el et = neon_check_type (3, rs,
18286 N_EQK, N_EQK, N_S16 | N_S32 | N_KEY);
18287 NEON_ENCODE (INTEGER, inst);
18288 /* The U bit (rounding) comes from bit mask. */
18289 neon_three_same (neon_quad (rs), 0, et.size);
18290 }
643afb90
MW		 18291 }
18292 else
18293 {
42b16635
AV		 18294 enum neon_shape rs = neon_select_shape (NS_QQR, NS_NULL);
18295 struct neon_type_el et
23d188c7 18296 = neon_check_type (3, rs, N_EQK, N_EQK, N_S_32 | N_KEY);
42b16635 18297
643afb90 18298 NEON_ENCODE (INTEGER, inst);
42b16635 18299 mve_encode_qqr (et.size, et.type == NT_unsigned, 0);
643afb90
MW		 18300 }
18301}
18302
5287ad62
JB		 18303static void
18304do_neon_fcmp_absolute (void)
18305{
037e8744 18306 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW		 18307 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18308 N_F_16_32 | N_KEY);
5287ad62 18309 /* Size field comes from bit mask. */
cc933301 18310 neon_three_same (neon_quad (rs), 1, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 18311}
18312
18313static void
18314do_neon_fcmp_absolute_inv (void)
18315{
18316 neon_exchange_operands ();
18317 do_neon_fcmp_absolute ();
18318}
18319
18320static void
18321do_neon_step (void)
18322{
037e8744 18323 enum neon_shape rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
cc933301
JW		 18324 struct neon_type_el et = neon_check_type (3, rs, N_EQK, N_EQK,
18325 N_F_16_32 | N_KEY);
18326 neon_three_same (neon_quad (rs), 0, et.size == 16 ? (int) et.size : -1);
5287ad62
JB		 18327}
18328
18329static void
18330do_neon_abs_neg (void)
18331{
037e8744
JB		 18332 enum neon_shape rs;
18333 struct neon_type_el et;
5f4273c7 18334
037e8744
JB		 18335 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg) == SUCCESS)
18336 return;
18337
037e8744 18338 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
cc933301 18339 et = neon_check_type (2, rs, N_EQK, N_S_32 | N_F_16_32 | N_KEY);
5f4273c7 18340
64c350f2
AV		 18341 if (!check_simd_pred_availability (et.type == NT_float,
18342 NEON_CHECK_ARCH | NEON_CHECK_CC))
485dee97
AV		 18343 return;
18344
5287ad62
JB		 18345 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18346 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18347 inst.instruction |= LOW4 (inst.operands[1].reg);
18348 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 18349 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 18350 inst.instruction |= (et.type == NT_float) << 10;
18351 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18352
88714cb8 18353 neon_dp_fixup (&inst);
5287ad62
JB		 18354}
18355
18356static void
18357do_neon_sli (void)
18358{
64c350f2 18359 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 18360 return;
18361
18362 enum neon_shape rs;
18363 struct neon_type_el et;
18364 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18365 {
18366 rs = neon_select_shape (NS_QQI, NS_NULL);
18367 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18368 }
18369 else
18370 {
18371 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18372 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18373 }
18374
18375
5287ad62
JB		 18376 int imm = inst.operands[2].imm;
18377 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18378 _("immediate out of range for insert"));
037e8744 18379 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 18380}
18381
18382static void
18383do_neon_sri (void)
18384{
64c350f2 18385 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 18386 return;
18387
18388 enum neon_shape rs;
18389 struct neon_type_el et;
18390 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18391 {
18392 rs = neon_select_shape (NS_QQI, NS_NULL);
18393 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_KEY);
18394 }
18395 else
18396 {
18397 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18398 et = neon_check_type (2, rs, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
18399 }
18400
5287ad62
JB		 18401 int imm = inst.operands[2].imm;
18402 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18403 _("immediate out of range for insert"));
037e8744 18404 neon_imm_shift (FALSE, 0, neon_quad (rs), et, et.size - imm);
5287ad62
JB		 18405}
18406
18407static void
18408do_neon_qshlu_imm (void)
18409{
64c350f2 18410 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
5150f0d8
AV		 18411 return;
18412
18413 enum neon_shape rs;
18414 struct neon_type_el et;
18415 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
18416 {
18417 rs = neon_select_shape (NS_QQI, NS_NULL);
18418 et = neon_check_type (2, rs, N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
18419 }
18420 else
18421 {
18422 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
18423 et = neon_check_type (2, rs, N_EQK | N_UNS,
18424 N_S8 | N_S16 | N_S32 | N_S64 | N_KEY);
18425 }
18426
5287ad62
JB		 18427 int imm = inst.operands[2].imm;
18428 constraint (imm < 0 || (unsigned)imm >= et.size,
477330fc 18429 _("immediate out of range for shift"));
5287ad62
JB		 18430 /* Only encodes the 'U present' variant of the instruction.
18431 In this case, signed types have OP (bit 8) set to 0.
18432 Unsigned types have OP set to 1. */
18433 inst.instruction |= (et.type == NT_unsigned) << 8;
18434 /* The rest of the bits are the same as other immediate shifts. */
037e8744 18435 neon_imm_shift (FALSE, 0, neon_quad (rs), et, imm);
5287ad62
JB		 18436}
18437
18438static void
18439do_neon_qmovn (void)
18440{
18441 struct neon_type_el et = neon_check_type (2, NS_DQ,
18442 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18443 /* Saturating move where operands can be signed or unsigned, and the
18444 destination has the same signedness. */
88714cb8 18445 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18446 if (et.type == NT_unsigned)
18447 inst.instruction |= 0xc0;
18448 else
18449 inst.instruction |= 0x80;
18450 neon_two_same (0, 1, et.size / 2);
18451}
18452
18453static void
18454do_neon_qmovun (void)
18455{
18456 struct neon_type_el et = neon_check_type (2, NS_DQ,
18457 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18458 /* Saturating move with unsigned results. Operands must be signed. */
88714cb8 18459 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18460 neon_two_same (0, 1, et.size / 2);
18461}
18462
18463static void
18464do_neon_rshift_sat_narrow (void)
18465{
18466 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18467 or unsigned. If operands are unsigned, results must also be unsigned. */
18468 struct neon_type_el et = neon_check_type (2, NS_DQI,
18469 N_EQK | N_HLF, N_SU_16_64 | N_KEY);
18470 int imm = inst.operands[2].imm;
18471 /* This gets the bounds check, size encoding and immediate bits calculation
18472 right. */
18473 et.size /= 2;
5f4273c7 18474
5287ad62
JB		 18475 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18476 VQMOVN.I<size> <Dd>, <Qm>. */
18477 if (imm == 0)
18478 {
18479 inst.operands[2].present = 0;
18480 inst.instruction = N_MNEM_vqmovn;
18481 do_neon_qmovn ();
18482 return;
18483 }
5f4273c7 18484
5287ad62 18485 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18486 _("immediate out of range"));
5287ad62
JB		 18487 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, et.size - imm);
18488}
18489
18490static void
18491do_neon_rshift_sat_narrow_u (void)
18492{
18493 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18494 or unsigned. If operands are unsigned, results must also be unsigned. */
18495 struct neon_type_el et = neon_check_type (2, NS_DQI,
18496 N_EQK | N_HLF | N_UNS, N_S16 | N_S32 | N_S64 | N_KEY);
18497 int imm = inst.operands[2].imm;
18498 /* This gets the bounds check, size encoding and immediate bits calculation
18499 right. */
18500 et.size /= 2;
18501
18502 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18503 VQMOVUN.I<size> <Dd>, <Qm>. */
18504 if (imm == 0)
18505 {
18506 inst.operands[2].present = 0;
18507 inst.instruction = N_MNEM_vqmovun;
18508 do_neon_qmovun ();
18509 return;
18510 }
18511
18512 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18513 _("immediate out of range"));
5287ad62
JB		 18514 /* FIXME: The manual is kind of unclear about what value U should have in
18515 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18516 must be 1. */
18517 neon_imm_shift (TRUE, 1, 0, et, et.size - imm);
18518}
18519
18520static void
18521do_neon_movn (void)
18522{
18523 struct neon_type_el et = neon_check_type (2, NS_DQ,
18524 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
88714cb8 18525 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18526 neon_two_same (0, 1, et.size / 2);
18527}
18528
18529static void
18530do_neon_rshift_narrow (void)
18531{
18532 struct neon_type_el et = neon_check_type (2, NS_DQI,
18533 N_EQK | N_HLF, N_I16 | N_I32 | N_I64 | N_KEY);
18534 int imm = inst.operands[2].imm;
18535 /* This gets the bounds check, size encoding and immediate bits calculation
18536 right. */
18537 et.size /= 2;
5f4273c7 18538
5287ad62
JB		 18539 /* If immediate is zero then we are a pseudo-instruction for
18540 VMOVN.I<size> <Dd>, <Qm> */
18541 if (imm == 0)
18542 {
18543 inst.operands[2].present = 0;
18544 inst.instruction = N_MNEM_vmovn;
18545 do_neon_movn ();
18546 return;
18547 }
5f4273c7 18548
5287ad62 18549 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 18550 _("immediate out of range for narrowing operation"));
5287ad62
JB		 18551 neon_imm_shift (FALSE, 0, 0, et, et.size - imm);
18552}
18553
18554static void
18555do_neon_shll (void)
18556{
18557 /* FIXME: Type checking when lengthening. */
18558 struct neon_type_el et = neon_check_type (2, NS_QDI,
18559 N_EQK | N_DBL, N_I8 | N_I16 | N_I32 | N_KEY);
18560 unsigned imm = inst.operands[2].imm;
18561
18562 if (imm == et.size)
18563 {
18564 /* Maximum shift variant. */
88714cb8 18565 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 18566 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18567 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18568 inst.instruction |= LOW4 (inst.operands[1].reg);
18569 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18570 inst.instruction |= neon_logbits (et.size) << 18;
5f4273c7 18571
88714cb8 18572 neon_dp_fixup (&inst);
5287ad62
JB		 18573 }
18574 else
18575 {
18576 /* A more-specific type check for non-max versions. */
18577 et = neon_check_type (2, NS_QDI,
477330fc 18578 N_EQK | N_DBL, N_SU_32 | N_KEY);
88714cb8 18579 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 18580 neon_imm_shift (TRUE, et.type == NT_unsigned, 0, et, imm);
18581 }
18582}
18583
037e8744 18584/* Check the various types for the VCVT instruction, and return which version
5287ad62
JB		 18585 the current instruction is. */
18586
6b9a8b67
MGD		 18587#define CVT_FLAVOUR_VAR \
18588 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18589 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18590 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18591 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18592 /* Half-precision conversions. */ \
cc933301
JW		 18593 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18594 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18595 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18596 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
6b9a8b67
MGD		 18597 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18598 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
9db2f6b4
RL		 18599 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18600 Compared with single/double precision variants, only the co-processor \
18601 field is different, so the encoding flow is reused here. */ \
18602 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18603 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18604 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18605 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
6b9a8b67
MGD		 18606 /* VFP instructions. */ \
18607 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18608 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18609 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18610 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18611 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18612 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18613 /* VFP instructions with bitshift. */ \
18614 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18615 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18616 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18617 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18618 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18619 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18620 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18621 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18622
18623#define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18624 neon_cvt_flavour_##C,
18625
18626/* The different types of conversions we can do. */
18627enum neon_cvt_flavour
18628{
18629 CVT_FLAVOUR_VAR
18630 neon_cvt_flavour_invalid,
18631 neon_cvt_flavour_first_fp = neon_cvt_flavour_f32_f64
18632};
18633
18634#undef CVT_VAR
18635
18636static enum neon_cvt_flavour
18637get_neon_cvt_flavour (enum neon_shape rs)
5287ad62 18638{
6b9a8b67
MGD		 18639#define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18640 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18641 if (et.type != NT_invtype) \
18642 { \
18643 inst.error = NULL; \
18644 return (neon_cvt_flavour_##C); \
5287ad62 18645 }
6b9a8b67 18646
5287ad62 18647 struct neon_type_el et;
037e8744 18648 unsigned whole_reg = (rs == NS_FFI || rs == NS_FD || rs == NS_DF
477330fc 18649 || rs == NS_FF) ? N_VFP : 0;
037e8744
JB		 18650 /* The instruction versions which take an immediate take one register
18651 argument, which is extended to the width of the full register. Thus the
18652 "source" and "destination" registers must have the same width. Hack that
18653 here by making the size equal to the key (wider, in this case) operand. */
18654 unsigned key = (rs == NS_QQI || rs == NS_DDI || rs == NS_FFI) ? N_KEY : 0;
5f4273c7 18655
6b9a8b67
MGD		 18656 CVT_FLAVOUR_VAR;
18657
18658 return neon_cvt_flavour_invalid;
5287ad62
JB		 18659#undef CVT_VAR
18660}
18661
7e8e6784
MGD		 18662enum neon_cvt_mode
18663{
18664 neon_cvt_mode_a,
18665 neon_cvt_mode_n,
18666 neon_cvt_mode_p,
18667 neon_cvt_mode_m,
18668 neon_cvt_mode_z,
30bdf752
MGD		 18669 neon_cvt_mode_x,
18670 neon_cvt_mode_r
7e8e6784
MGD		 18671};
18672
037e8744
JB		 18673/* Neon-syntax VFP conversions. */
18674
5287ad62 18675static void
6b9a8b67 18676do_vfp_nsyn_cvt (enum neon_shape rs, enum neon_cvt_flavour flavour)
5287ad62 18677{
037e8744 18678 const char *opname = 0;
5f4273c7 18679
d54af2d0
RL		 18680 if (rs == NS_DDI || rs == NS_QQI || rs == NS_FFI
18681 || rs == NS_FHI || rs == NS_HFI)
5287ad62 18682 {
037e8744
JB		 18683 /* Conversions with immediate bitshift. */
18684 const char *enc[] =
477330fc 18685 {
6b9a8b67
MGD		 18686#define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18687 CVT_FLAVOUR_VAR
18688 NULL
18689#undef CVT_VAR
477330fc 18690 };
037e8744 18691
6b9a8b67 18692 if (flavour < (int) ARRAY_SIZE (enc))
477330fc
RM		 18693 {
18694 opname = enc[flavour];
18695 constraint (inst.operands[0].reg != inst.operands[1].reg,
18696 _("operands 0 and 1 must be the same register"));
18697 inst.operands[1] = inst.operands[2];
18698 memset (&inst.operands[2], '\0', sizeof (inst.operands[2]));
18699 }
5287ad62
JB		 18700 }
18701 else
18702 {
037e8744
JB		 18703 /* Conversions without bitshift. */
18704 const char *enc[] =
477330fc 18705 {
6b9a8b67
MGD		 18706#define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18707 CVT_FLAVOUR_VAR
18708 NULL
18709#undef CVT_VAR
477330fc 18710 };
037e8744 18711
6b9a8b67 18712 if (flavour < (int) ARRAY_SIZE (enc))
477330fc 18713 opname = enc[flavour];
037e8744
JB		 18714 }
18715
18716 if (opname)
18717 do_vfp_nsyn_opcode (opname);
9db2f6b4
RL		 18718
18719 /* ARMv8.2 fp16 VCVT instruction. */
18720 if (flavour == neon_cvt_flavour_s32_f16
18721 || flavour == neon_cvt_flavour_u32_f16
18722 || flavour == neon_cvt_flavour_f16_u32
18723 || flavour == neon_cvt_flavour_f16_s32)
18724 do_scalar_fp16_v82_encode ();
037e8744
JB		 18725}
18726
18727static void
18728do_vfp_nsyn_cvtz (void)
18729{
d54af2d0 18730 enum neon_shape rs = neon_select_shape (NS_FH, NS_FF, NS_FD, NS_NULL);
6b9a8b67 18731 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744
JB		 18732 const char *enc[] =
18733 {
6b9a8b67
MGD		 18734#define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18735 CVT_FLAVOUR_VAR
18736 NULL
18737#undef CVT_VAR
037e8744
JB		 18738 };
18739
6b9a8b67 18740 if (flavour < (int) ARRAY_SIZE (enc) && enc[flavour])
037e8744
JB		 18741 do_vfp_nsyn_opcode (enc[flavour]);
18742}
f31fef98 18743
037e8744 18744static void
bacebabc 18745do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour,
7e8e6784
MGD		 18746 enum neon_cvt_mode mode)
18747{
18748 int sz, op;
18749 int rm;
18750
a715796b
TG		 18751 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18752 D register operands. */
18753 if (flavour == neon_cvt_flavour_s32_f64
18754 || flavour == neon_cvt_flavour_u32_f64)
18755 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
18756 _(BAD_FPU));
18757
9db2f6b4
RL		 18758 if (flavour == neon_cvt_flavour_s32_f16
18759 || flavour == neon_cvt_flavour_u32_f16)
18760 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16),
18761 _(BAD_FP16));
18762
5ee91343 18763 set_pred_insn_type (OUTSIDE_PRED_INSN);
7e8e6784
MGD		 18764
18765 switch (flavour)
18766 {
18767 case neon_cvt_flavour_s32_f64:
18768 sz = 1;
827f64ff 18769 op = 1;
7e8e6784
MGD		 18770 break;
18771 case neon_cvt_flavour_s32_f32:
18772 sz = 0;
18773 op = 1;
18774 break;
9db2f6b4
RL		 18775 case neon_cvt_flavour_s32_f16:
18776 sz = 0;
18777 op = 1;
18778 break;
7e8e6784
MGD		 18779 case neon_cvt_flavour_u32_f64:
18780 sz = 1;
18781 op = 0;
18782 break;
18783 case neon_cvt_flavour_u32_f32:
18784 sz = 0;
18785 op = 0;
18786 break;
9db2f6b4
RL		 18787 case neon_cvt_flavour_u32_f16:
18788 sz = 0;
18789 op = 0;
18790 break;
7e8e6784
MGD		 18791 default:
18792 first_error (_("invalid instruction shape"));
18793 return;
18794 }
18795
18796 switch (mode)
18797 {
18798 case neon_cvt_mode_a: rm = 0; break;
18799 case neon_cvt_mode_n: rm = 1; break;
18800 case neon_cvt_mode_p: rm = 2; break;
18801 case neon_cvt_mode_m: rm = 3; break;
18802 default: first_error (_("invalid rounding mode")); return;
18803 }
18804
18805 NEON_ENCODE (FPV8, inst);
18806 encode_arm_vfp_reg (inst.operands[0].reg, VFP_REG_Sd);
18807 encode_arm_vfp_reg (inst.operands[1].reg, sz == 1 ? VFP_REG_Dm : VFP_REG_Sm);
18808 inst.instruction |= sz << 8;
9db2f6b4
RL		 18809
18810 /* ARMv8.2 fp16 VCVT instruction. */
18811 if (flavour == neon_cvt_flavour_s32_f16
18812 ||flavour == neon_cvt_flavour_u32_f16)
18813 do_scalar_fp16_v82_encode ();
7e8e6784
MGD		 18814 inst.instruction |= op << 7;
18815 inst.instruction |= rm << 16;
18816 inst.instruction |= 0xf0000000;
18817 inst.is_neon = TRUE;
18818}
18819
18820static void
18821do_neon_cvt_1 (enum neon_cvt_mode mode)
037e8744
JB		 18822{
18823 enum neon_shape rs = neon_select_shape (NS_DDI, NS_QQI, NS_FFI, NS_DD, NS_QQ,
d54af2d0
RL		 18824 NS_FD, NS_DF, NS_FF, NS_QD, NS_DQ,
18825 NS_FH, NS_HF, NS_FHI, NS_HFI,
18826 NS_NULL);
6b9a8b67 18827 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
037e8744 18828
cc933301
JW		 18829 if (flavour == neon_cvt_flavour_invalid)
18830 return;
18831
e3e535bc 18832 /* PR11109: Handle round-to-zero for VCVT conversions. */
7e8e6784 18833 if (mode == neon_cvt_mode_z
e3e535bc 18834 && ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_vfp_v2)
cc933301
JW		 18835 && (flavour == neon_cvt_flavour_s16_f16
18836 || flavour == neon_cvt_flavour_u16_f16
18837 || flavour == neon_cvt_flavour_s32_f32
bacebabc
RM		 18838 || flavour == neon_cvt_flavour_u32_f32
18839 || flavour == neon_cvt_flavour_s32_f64
6b9a8b67 18840 || flavour == neon_cvt_flavour_u32_f64)
e3e535bc
NC		 18841 && (rs == NS_FD || rs == NS_FF))
18842 {
18843 do_vfp_nsyn_cvtz ();
18844 return;
18845 }
18846
9db2f6b4
RL		 18847 /* ARMv8.2 fp16 VCVT conversions. */
18848 if (mode == neon_cvt_mode_z
18849 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16)
18850 && (flavour == neon_cvt_flavour_s32_f16
18851 || flavour == neon_cvt_flavour_u32_f16)
18852 && (rs == NS_FH))
18853 {
18854 do_vfp_nsyn_cvtz ();
18855 do_scalar_fp16_v82_encode ();
18856 return;
18857 }
18858
037e8744 18859 /* VFP rather than Neon conversions. */
6b9a8b67 18860 if (flavour >= neon_cvt_flavour_first_fp)
037e8744 18861 {
7e8e6784
MGD		 18862 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
18863 do_vfp_nsyn_cvt (rs, flavour);
18864 else
18865 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
18866
037e8744
JB		 18867 return;
18868 }
18869
18870 switch (rs)
18871 {
037e8744 18872 case NS_QQI:
dd9634d9
AV		 18873 if (mode == neon_cvt_mode_z
18874 && (flavour == neon_cvt_flavour_f16_s16
18875 || flavour == neon_cvt_flavour_f16_u16
18876 || flavour == neon_cvt_flavour_s16_f16
18877 || flavour == neon_cvt_flavour_u16_f16
18878 || flavour == neon_cvt_flavour_f32_u32
18879 || flavour == neon_cvt_flavour_f32_s32
18880 || flavour == neon_cvt_flavour_s32_f32
18881 || flavour == neon_cvt_flavour_u32_f32))
18882 {
64c350f2
AV		 18883 if (!check_simd_pred_availability (TRUE,
18884 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV		 18885 return;
18886 }
18887 else if (mode == neon_cvt_mode_n)
18888 {
18889 /* We are dealing with vcvt with the 'ne' condition. */
18890 inst.cond = 0x1;
18891 inst.instruction = N_MNEM_vcvt;
18892 do_neon_cvt_1 (neon_cvt_mode_z);
18893 return;
18894 }
18895 /* fall through. */
18896 case NS_DDI:
037e8744 18897 {
477330fc 18898 unsigned immbits;
cc933301
JW		 18899 unsigned enctab[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18900 0x0000100, 0x1000100, 0x0, 0x1000000};
35997600 18901
dd9634d9
AV		 18902 if ((rs != NS_QQI || !ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18903 && vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
18904 return;
18905
18906 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
18907 {
18908 constraint (inst.operands[2].present && inst.operands[2].imm == 0,
18909 _("immediate value out of range"));
18910 switch (flavour)
18911 {
18912 case neon_cvt_flavour_f16_s16:
18913 case neon_cvt_flavour_f16_u16:
18914 case neon_cvt_flavour_s16_f16:
18915 case neon_cvt_flavour_u16_f16:
18916 constraint (inst.operands[2].imm > 16,
18917 _("immediate value out of range"));
18918 break;
18919 case neon_cvt_flavour_f32_u32:
18920 case neon_cvt_flavour_f32_s32:
18921 case neon_cvt_flavour_s32_f32:
18922 case neon_cvt_flavour_u32_f32:
18923 constraint (inst.operands[2].imm > 32,
18924 _("immediate value out of range"));
18925 break;
18926 default:
18927 inst.error = BAD_FPU;
18928 return;
18929 }
18930 }
037e8744 18931
477330fc
RM		 18932 /* Fixed-point conversion with #0 immediate is encoded as an
18933 integer conversion. */
18934 if (inst.operands[2].present && inst.operands[2].imm == 0)
18935 goto int_encode;
477330fc
RM		 18936 NEON_ENCODE (IMMED, inst);
18937 if (flavour != neon_cvt_flavour_invalid)
18938 inst.instruction |= enctab[flavour];
18939 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
18940 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
18941 inst.instruction |= LOW4 (inst.operands[1].reg);
18942 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
18943 inst.instruction |= neon_quad (rs) << 6;
18944 inst.instruction |= 1 << 21;
cc933301
JW		 18945 if (flavour < neon_cvt_flavour_s16_f16)
18946 {
18947 inst.instruction |= 1 << 21;
18948 immbits = 32 - inst.operands[2].imm;
18949 inst.instruction |= immbits << 16;
18950 }
18951 else
18952 {
18953 inst.instruction |= 3 << 20;
18954 immbits = 16 - inst.operands[2].imm;
18955 inst.instruction |= immbits << 16;
18956 inst.instruction &= ~(1 << 9);
18957 }
477330fc
RM		 18958
18959 neon_dp_fixup (&inst);
037e8744
JB		 18960 }
18961 break;
18962
037e8744 18963 case NS_QQ:
dd9634d9
AV		 18964 if ((mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
18965 || mode == neon_cvt_mode_m || mode == neon_cvt_mode_p)
18966 && (flavour == neon_cvt_flavour_s16_f16
18967 || flavour == neon_cvt_flavour_u16_f16
18968 || flavour == neon_cvt_flavour_s32_f32
18969 || flavour == neon_cvt_flavour_u32_f32))
18970 {
64c350f2
AV		 18971 if (!check_simd_pred_availability (TRUE,
18972 NEON_CHECK_CC | NEON_CHECK_ARCH8))
dd9634d9
AV		 18973 return;
18974 }
18975 else if (mode == neon_cvt_mode_z
18976 && (flavour == neon_cvt_flavour_f16_s16
18977 || flavour == neon_cvt_flavour_f16_u16
18978 || flavour == neon_cvt_flavour_s16_f16
18979 || flavour == neon_cvt_flavour_u16_f16
18980 || flavour == neon_cvt_flavour_f32_u32
18981 || flavour == neon_cvt_flavour_f32_s32
18982 || flavour == neon_cvt_flavour_s32_f32
18983 || flavour == neon_cvt_flavour_u32_f32))
18984 {
64c350f2
AV		 18985 if (!check_simd_pred_availability (TRUE,
18986 NEON_CHECK_CC | NEON_CHECK_ARCH))
dd9634d9
AV		 18987 return;
18988 }
18989 /* fall through. */
18990 case NS_DD:
7e8e6784
MGD		 18991 if (mode != neon_cvt_mode_x && mode != neon_cvt_mode_z)
18992 {
7e8e6784 18993
dd9634d9 18994 NEON_ENCODE (FLOAT, inst);
64c350f2
AV		 18995 if (!check_simd_pred_availability (TRUE,
18996 NEON_CHECK_CC | NEON_CHECK_ARCH8))
7e8e6784
MGD		 18997 return;
18998
18999 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19000 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19001 inst.instruction |= LOW4 (inst.operands[1].reg);
19002 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19003 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 19004 inst.instruction |= (flavour == neon_cvt_flavour_u16_f16
19005 || flavour == neon_cvt_flavour_u32_f32) << 7;
7e8e6784 19006 inst.instruction |= mode << 8;
cc933301
JW		 19007 if (flavour == neon_cvt_flavour_u16_f16
19008 || flavour == neon_cvt_flavour_s16_f16)
19009 /* Mask off the original size bits and reencode them. */
19010 inst.instruction = ((inst.instruction & 0xfff3ffff) | (1 << 18));
19011
7e8e6784
MGD		 19012 if (thumb_mode)
19013 inst.instruction |= 0xfc000000;
19014 else
19015 inst.instruction |= 0xf0000000;
19016 }
19017 else
19018 {
037e8744 19019 int_encode:
7e8e6784 19020 {
cc933301
JW		 19021 unsigned enctab[] = { 0x100, 0x180, 0x0, 0x080,
19022 0x100, 0x180, 0x0, 0x080};
037e8744 19023
7e8e6784 19024 NEON_ENCODE (INTEGER, inst);
037e8744 19025
dd9634d9
AV		 19026 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
19027 {
19028 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19029 return;
19030 }
037e8744 19031
7e8e6784
MGD		 19032 if (flavour != neon_cvt_flavour_invalid)
19033 inst.instruction |= enctab[flavour];
037e8744 19034
7e8e6784
MGD		 19035 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19036 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19037 inst.instruction |= LOW4 (inst.operands[1].reg);
19038 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19039 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 19040 if (flavour >= neon_cvt_flavour_s16_f16
19041 && flavour <= neon_cvt_flavour_f16_u16)
19042 /* Half precision. */
19043 inst.instruction |= 1 << 18;
19044 else
19045 inst.instruction |= 2 << 18;
037e8744 19046
7e8e6784
MGD		 19047 neon_dp_fixup (&inst);
19048 }
19049 }
19050 break;
037e8744 19051
8e79c3df
CM		 19052 /* Half-precision conversions for Advanced SIMD -- neon. */
19053 case NS_QD:
19054 case NS_DQ:
bc52d49c
MM		 19055 if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH) == FAIL)
19056 return;
8e79c3df
CM		 19057
19058 if ((rs == NS_DQ)
19059 && (inst.vectype.el[0].size != 16 || inst.vectype.el[1].size != 32))
19060 {
19061 as_bad (_("operand size must match register width"));
19062 break;
19063 }
19064
19065 if ((rs == NS_QD)
19066 && ((inst.vectype.el[0].size != 32 || inst.vectype.el[1].size != 16)))
19067 {
19068 as_bad (_("operand size must match register width"));
19069 break;
19070 }
19071
19072 if (rs == NS_DQ)
477330fc 19073 inst.instruction = 0x3b60600;
8e79c3df
CM		 19074 else
19075 inst.instruction = 0x3b60700;
19076
19077 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19078 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19079 inst.instruction |= LOW4 (inst.operands[1].reg);
19080 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
88714cb8 19081 neon_dp_fixup (&inst);
8e79c3df
CM		 19082 break;
19083
037e8744
JB		 19084 default:
19085 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
7e8e6784
MGD		 19086 if (mode == neon_cvt_mode_x || mode == neon_cvt_mode_z)
19087 do_vfp_nsyn_cvt (rs, flavour);
19088 else
19089 do_vfp_nsyn_cvt_fpv8 (flavour, mode);
5287ad62 19090 }
5287ad62
JB		 19091}
19092
e3e535bc
NC		 19093static void
19094do_neon_cvtr (void)
19095{
7e8e6784 19096 do_neon_cvt_1 (neon_cvt_mode_x);
e3e535bc
NC		 19097}
19098
19099static void
19100do_neon_cvt (void)
19101{
7e8e6784
MGD		 19102 do_neon_cvt_1 (neon_cvt_mode_z);
19103}
19104
19105static void
19106do_neon_cvta (void)
19107{
19108 do_neon_cvt_1 (neon_cvt_mode_a);
19109}
19110
19111static void
19112do_neon_cvtn (void)
19113{
19114 do_neon_cvt_1 (neon_cvt_mode_n);
19115}
19116
19117static void
19118do_neon_cvtp (void)
19119{
19120 do_neon_cvt_1 (neon_cvt_mode_p);
19121}
19122
19123static void
19124do_neon_cvtm (void)
19125{
19126 do_neon_cvt_1 (neon_cvt_mode_m);
e3e535bc
NC		 19127}
19128
8e79c3df 19129static void
c70a8987 19130do_neon_cvttb_2 (bfd_boolean t, bfd_boolean to, bfd_boolean is_double)
8e79c3df 19131{
c70a8987
MGD		 19132 if (is_double)
19133 mark_feature_used (&fpu_vfp_ext_armv8);
8e79c3df 19134
c70a8987
MGD		 19135 encode_arm_vfp_reg (inst.operands[0].reg,
19136 (is_double && !to) ? VFP_REG_Dd : VFP_REG_Sd);
19137 encode_arm_vfp_reg (inst.operands[1].reg,
19138 (is_double && to) ? VFP_REG_Dm : VFP_REG_Sm);
19139 inst.instruction |= to ? 0x10000 : 0;
19140 inst.instruction |= t ? 0x80 : 0;
19141 inst.instruction |= is_double ? 0x100 : 0;
19142 do_vfp_cond_or_thumb ();
19143}
8e79c3df 19144
c70a8987
MGD		 19145static void
19146do_neon_cvttb_1 (bfd_boolean t)
19147{
d54af2d0 19148 enum neon_shape rs = neon_select_shape (NS_HF, NS_HD, NS_FH, NS_FF, NS_FD,
dd9634d9 19149 NS_DF, NS_DH, NS_QQ, NS_QQI, NS_NULL);
8e79c3df 19150
c70a8987
MGD		 19151 if (rs == NS_NULL)
19152 return;
dd9634d9
AV		 19153 else if (rs == NS_QQ || rs == NS_QQI)
19154 {
19155 int single_to_half = 0;
64c350f2 19156 if (!check_simd_pred_availability (TRUE, NEON_CHECK_ARCH))
dd9634d9
AV		 19157 return;
19158
19159 enum neon_cvt_flavour flavour = get_neon_cvt_flavour (rs);
19160
19161 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19162 && (flavour == neon_cvt_flavour_u16_f16
19163 || flavour == neon_cvt_flavour_s16_f16
19164 || flavour == neon_cvt_flavour_f16_s16
19165 || flavour == neon_cvt_flavour_f16_u16
19166 || flavour == neon_cvt_flavour_u32_f32
19167 || flavour == neon_cvt_flavour_s32_f32
19168 || flavour == neon_cvt_flavour_f32_s32
19169 || flavour == neon_cvt_flavour_f32_u32))
19170 {
19171 inst.cond = 0xf;
19172 inst.instruction = N_MNEM_vcvt;
19173 set_pred_insn_type (INSIDE_VPT_INSN);
19174 do_neon_cvt_1 (neon_cvt_mode_z);
19175 return;
19176 }
19177 else if (rs == NS_QQ && flavour == neon_cvt_flavour_f32_f16)
19178 single_to_half = 1;
19179 else if (rs == NS_QQ && flavour != neon_cvt_flavour_f16_f32)
19180 {
19181 first_error (BAD_FPU);
19182 return;
19183 }
19184
19185 inst.instruction = 0xee3f0e01;
19186 inst.instruction |= single_to_half << 28;
19187 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19188 inst.instruction |= LOW4 (inst.operands[0].reg) << 13;
19189 inst.instruction |= t << 12;
19190 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19191 inst.instruction |= LOW4 (inst.operands[1].reg) << 1;
19192 inst.is_neon = 1;
19193 }
c70a8987
MGD		 19194 else if (neon_check_type (2, rs, N_F16, N_F32 | N_VFP).type != NT_invtype)
19195 {
19196 inst.error = NULL;
19197 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/FALSE);
19198 }
19199 else if (neon_check_type (2, rs, N_F32 | N_VFP, N_F16).type != NT_invtype)
19200 {
19201 inst.error = NULL;
19202 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/FALSE);
19203 }
19204 else if (neon_check_type (2, rs, N_F16, N_F64 | N_VFP).type != NT_invtype)
19205 {
a715796b
TG		 19206 /* The VCVTB and VCVTT instructions with D-register operands
19207 don't work for SP only targets. */
19208 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19209 _(BAD_FPU));
19210
c70a8987
MGD		 19211 inst.error = NULL;
19212 do_neon_cvttb_2 (t, /*to=*/TRUE, /*is_double=*/TRUE);
19213 }
19214 else if (neon_check_type (2, rs, N_F64 | N_VFP, N_F16).type != NT_invtype)
19215 {
a715796b
TG		 19216 /* The VCVTB and VCVTT instructions with D-register operands
19217 don't work for SP only targets. */
19218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
19219 _(BAD_FPU));
19220
c70a8987
MGD		 19221 inst.error = NULL;
19222 do_neon_cvttb_2 (t, /*to=*/FALSE, /*is_double=*/TRUE);
19223 }
19224 else
19225 return;
19226}
19227
19228static void
19229do_neon_cvtb (void)
19230{
19231 do_neon_cvttb_1 (FALSE);
8e79c3df
CM		 19232}
19233
19234
19235static void
19236do_neon_cvtt (void)
19237{
c70a8987 19238 do_neon_cvttb_1 (TRUE);
8e79c3df
CM		 19239}
19240
5287ad62
JB		 19241static void
19242neon_move_immediate (void)
19243{
037e8744
JB		 19244 enum neon_shape rs = neon_select_shape (NS_DI, NS_QI, NS_NULL);
19245 struct neon_type_el et = neon_check_type (2, rs,
19246 N_I8 | N_I16 | N_I32 | N_I64 | N_F32 | N_KEY, N_EQK);
5287ad62 19247 unsigned immlo, immhi = 0, immbits;
c96612cc 19248 int op, cmode, float_p;
5287ad62 19249
037e8744 19250 constraint (et.type == NT_invtype,
477330fc 19251 _("operand size must be specified for immediate VMOV"));
037e8744 19252
5287ad62
JB		 19253 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19254 op = (inst.instruction & (1 << 5)) != 0;
19255
19256 immlo = inst.operands[1].imm;
19257 if (inst.operands[1].regisimm)
19258 immhi = inst.operands[1].reg;
19259
19260 constraint (et.size < 32 && (immlo & ~((1 << et.size) - 1)) != 0,
477330fc 19261 _("immediate has bits set outside the operand size"));
5287ad62 19262
c96612cc
JB		 19263 float_p = inst.operands[1].immisfloat;
19264
19265 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits, &op,
477330fc 19266 et.size, et.type)) == FAIL)
5287ad62
JB		 19267 {
19268 /* Invert relevant bits only. */
19269 neon_invert_size (&immlo, &immhi, et.size);
19270 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
477330fc
RM		 19271 with one or the other; those cases are caught by
19272 neon_cmode_for_move_imm. */
5287ad62 19273 op = !op;
c96612cc
JB		 19274 if ((cmode = neon_cmode_for_move_imm (immlo, immhi, float_p, &immbits,
19275 &op, et.size, et.type)) == FAIL)
477330fc
RM		 19276 {
19277 first_error (_("immediate out of range"));
19278 return;
19279 }
5287ad62
JB		 19280 }
19281
19282 inst.instruction &= ~(1 << 5);
19283 inst.instruction |= op << 5;
19284
19285 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19286 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
037e8744 19287 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19288 inst.instruction |= cmode << 8;
19289
19290 neon_write_immbits (immbits);
19291}
19292
19293static void
19294do_neon_mvn (void)
19295{
64c350f2 19296 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV		 19297 return;
19298
5287ad62
JB		 19299 if (inst.operands[1].isreg)
19300 {
1a186d29
AV		 19301 enum neon_shape rs;
19302 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19303 rs = neon_select_shape (NS_QQ, NS_NULL);
19304 else
19305 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5f4273c7 19306
88714cb8 19307 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 19308 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19309 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19310 inst.instruction |= LOW4 (inst.operands[1].reg);
19311 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
037e8744 19312 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19313 }
19314 else
19315 {
88714cb8 19316 NEON_ENCODE (IMMED, inst);
5287ad62
JB		 19317 neon_move_immediate ();
19318 }
19319
88714cb8 19320 neon_dp_fixup (&inst);
1a186d29
AV		 19321
19322 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19323 {
19324 constraint (!inst.operands[1].isreg && !inst.operands[0].isquad, BAD_FPU);
19325 constraint ((inst.instruction & 0xd00) == 0xd00,
19326 _("immediate value out of range"));
19327 }
5287ad62
JB		 19328}
19329
19330/* Encode instructions of form:
19331
19332 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
5f4273c7 19333 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
5287ad62
JB		 19334
19335static void
19336neon_mixed_length (struct neon_type_el et, unsigned size)
19337{
19338 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19339 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19340 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19341 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19342 inst.instruction |= LOW4 (inst.operands[2].reg);
19343 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
19344 inst.instruction |= (et.type == NT_unsigned) << 24;
19345 inst.instruction |= neon_logbits (size) << 20;
5f4273c7 19346
88714cb8 19347 neon_dp_fixup (&inst);
5287ad62
JB		 19348}
19349
19350static void
19351do_neon_dyadic_long (void)
19352{
5ee91343
AV		 19353 enum neon_shape rs = neon_select_shape (NS_QDD, NS_QQQ, NS_QQR, NS_NULL);
19354 if (rs == NS_QDD)
19355 {
19356 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH | NEON_CHECK_CC) == FAIL)
19357 return;
19358
19359 NEON_ENCODE (INTEGER, inst);
19360 /* FIXME: Type checking for lengthening op. */
19361 struct neon_type_el et = neon_check_type (3, NS_QDD,
19362 N_EQK | N_DBL, N_EQK, N_SU_32 | N_KEY);
19363 neon_mixed_length (et, et.size);
19364 }
19365 else if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19366 && (inst.cond == 0xf || inst.cond == 0x10))
19367 {
19368 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19369 in an IT block with le/lt conditions. */
19370
19371 if (inst.cond == 0xf)
19372 inst.cond = 0xb;
19373 else if (inst.cond == 0x10)
19374 inst.cond = 0xd;
19375
19376 inst.pred_insn_type = INSIDE_IT_INSN;
19377
19378 if (inst.instruction == N_MNEM_vaddl)
19379 {
19380 inst.instruction = N_MNEM_vadd;
19381 do_neon_addsub_if_i ();
19382 }
19383 else if (inst.instruction == N_MNEM_vsubl)
19384 {
19385 inst.instruction = N_MNEM_vsub;
19386 do_neon_addsub_if_i ();
19387 }
19388 else if (inst.instruction == N_MNEM_vabdl)
19389 {
19390 inst.instruction = N_MNEM_vabd;
19391 do_neon_dyadic_if_su ();
19392 }
19393 }
19394 else
19395 first_error (BAD_FPU);
5287ad62
JB		 19396}
19397
19398static void
19399do_neon_abal (void)
19400{
19401 struct neon_type_el et = neon_check_type (3, NS_QDD,
19402 N_EQK | N_INT | N_DBL, N_EQK, N_SU_32 | N_KEY);
19403 neon_mixed_length (et, et.size);
19404}
19405
19406static void
19407neon_mac_reg_scalar_long (unsigned regtypes, unsigned scalartypes)
19408{
19409 if (inst.operands[2].isscalar)
19410 {
dcbf9037 19411 struct neon_type_el et = neon_check_type (3, NS_QDS,
477330fc 19412 N_EQK | N_DBL, N_EQK, regtypes | N_KEY);
88714cb8 19413 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 19414 neon_mul_mac (et, et.type == NT_unsigned);
19415 }
19416 else
19417 {
19418 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19419 N_EQK | N_DBL, N_EQK, scalartypes | N_KEY);
88714cb8 19420 NEON_ENCODE (INTEGER, inst);
5287ad62
JB		 19421 neon_mixed_length (et, et.size);
19422 }
19423}
19424
19425static void
19426do_neon_mac_maybe_scalar_long (void)
19427{
19428 neon_mac_reg_scalar_long (N_S16 | N_S32 | N_U16 | N_U32, N_SU_32);
19429}
19430
dec41383
JW		 19431/* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19432 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19433
19434static unsigned
19435neon_scalar_for_fmac_fp16_long (unsigned scalar, unsigned quad_p)
19436{
19437 unsigned regno = NEON_SCALAR_REG (scalar);
19438 unsigned elno = NEON_SCALAR_INDEX (scalar);
19439
19440 if (quad_p)
19441 {
19442 if (regno > 7 || elno > 3)
19443 goto bad_scalar;
19444
19445 return ((regno & 0x7)
19446 | ((elno & 0x1) << 3)
19447 | (((elno >> 1) & 0x1) << 5));
19448 }
19449 else
19450 {
19451 if (regno > 15 || elno > 1)
19452 goto bad_scalar;
19453
19454 return (((regno & 0x1) << 5)
19455 | ((regno >> 1) & 0x7)
19456 | ((elno & 0x1) << 3));
19457 }
19458
19459bad_scalar:
19460 first_error (_("scalar out of range for multiply instruction"));
19461 return 0;
19462}
19463
19464static void
19465do_neon_fmac_maybe_scalar_long (int subtype)
19466{
19467 enum neon_shape rs;
19468 int high8;
19469 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19470 field (bits[21:20]) has different meaning. For scalar index variant, it's
19471 used to differentiate add and subtract, otherwise it's with fixed value
19472 0x2. */
19473 int size = -1;
19474
19475 if (inst.cond != COND_ALWAYS)
19476 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19477 "behaviour is UNPREDICTABLE"));
19478
01f48020 19479 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_fp16_fml),
dec41383
JW		 19480 _(BAD_FP16));
19481
19482 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
19483 _(BAD_FPU));
19484
19485 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19486 be a scalar index register. */
19487 if (inst.operands[2].isscalar)
19488 {
19489 high8 = 0xfe000000;
19490 if (subtype)
19491 size = 16;
19492 rs = neon_select_shape (NS_DHS, NS_QDS, NS_NULL);
19493 }
19494 else
19495 {
19496 high8 = 0xfc000000;
19497 size = 32;
19498 if (subtype)
19499 inst.instruction |= (0x1 << 23);
19500 rs = neon_select_shape (NS_DHH, NS_QDD, NS_NULL);
19501 }
19502
19503 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16);
19504
19505 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19506 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19507 so we simply pass -1 as size. */
19508 unsigned quad_p = (rs == NS_QDD || rs == NS_QDS);
19509 neon_three_same (quad_p, 0, size);
19510
19511 /* Undo neon_dp_fixup. Redo the high eight bits. */
19512 inst.instruction &= 0x00ffffff;
19513 inst.instruction |= high8;
19514
19515#define LOW1(R) ((R) & 0x1)
19516#define HI4(R) (((R) >> 1) & 0xf)
19517 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19518 whether the instruction is in Q form and whether Vm is a scalar indexed
19519 operand. */
19520 if (inst.operands[2].isscalar)
19521 {
19522 unsigned rm
19523 = neon_scalar_for_fmac_fp16_long (inst.operands[2].reg, quad_p);
19524 inst.instruction &= 0xffffffd0;
19525 inst.instruction |= rm;
19526
19527 if (!quad_p)
19528 {
19529 /* Redo Rn as well. */
19530 inst.instruction &= 0xfff0ff7f;
19531 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19532 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19533 }
19534 }
19535 else if (!quad_p)
19536 {
19537 /* Redo Rn and Rm. */
19538 inst.instruction &= 0xfff0ff50;
19539 inst.instruction |= HI4 (inst.operands[1].reg) << 16;
19540 inst.instruction |= LOW1 (inst.operands[1].reg) << 7;
19541 inst.instruction |= HI4 (inst.operands[2].reg);
19542 inst.instruction |= LOW1 (inst.operands[2].reg) << 5;
19543 }
19544}
19545
19546static void
19547do_neon_vfmal (void)
19548{
19549 return do_neon_fmac_maybe_scalar_long (0);
19550}
19551
19552static void
19553do_neon_vfmsl (void)
19554{
19555 return do_neon_fmac_maybe_scalar_long (1);
19556}
19557
5287ad62
JB		 19558static void
19559do_neon_dyadic_wide (void)
19560{
19561 struct neon_type_el et = neon_check_type (3, NS_QQD,
19562 N_EQK | N_DBL, N_EQK | N_DBL, N_SU_32 | N_KEY);
19563 neon_mixed_length (et, et.size);
19564}
19565
19566static void
19567do_neon_dyadic_narrow (void)
19568{
19569 struct neon_type_el et = neon_check_type (3, NS_QDD,
19570 N_EQK | N_DBL, N_EQK, N_I16 | N_I32 | N_I64 | N_KEY);
428e3f1f
PB		 19571 /* Operand sign is unimportant, and the U bit is part of the opcode,
19572 so force the operand type to integer. */
19573 et.type = NT_integer;
5287ad62
JB		 19574 neon_mixed_length (et, et.size / 2);
19575}
19576
19577static void
19578do_neon_mul_sat_scalar_long (void)
19579{
19580 neon_mac_reg_scalar_long (N_S16 | N_S32, N_S16 | N_S32);
19581}
19582
19583static void
19584do_neon_vmull (void)
19585{
19586 if (inst.operands[2].isscalar)
19587 do_neon_mac_maybe_scalar_long ();
19588 else
19589 {
19590 struct neon_type_el et = neon_check_type (3, NS_QDD,
477330fc 19591 N_EQK | N_DBL, N_EQK, N_SU_32 | N_P8 | N_P64 | N_KEY);
4f51b4bd 19592
5287ad62 19593 if (et.type == NT_poly)
477330fc 19594 NEON_ENCODE (POLY, inst);
5287ad62 19595 else
477330fc 19596 NEON_ENCODE (INTEGER, inst);
4f51b4bd
MGD		 19597
19598 /* For polynomial encoding the U bit must be zero, and the size must
19599 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19600 obviously, as 0b10). */
19601 if (et.size == 64)
19602 {
19603 /* Check we're on the correct architecture. */
19604 if (!mark_feature_used (&fpu_crypto_ext_armv8))
19605 inst.error =
19606 _("Instruction form not available on this architecture.");
19607
19608 et.size = 32;
19609 }
19610
5287ad62
JB		 19611 neon_mixed_length (et, et.size);
19612 }
19613}
19614
19615static void
19616do_neon_ext (void)
19617{
037e8744 19618 enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
5287ad62
JB		 19619 struct neon_type_el et = neon_check_type (3, rs,
19620 N_EQK, N_EQK, N_8 | N_16 | N_32 | N_64 | N_KEY);
19621 unsigned imm = (inst.operands[3].imm * et.size) / 8;
35997600
NC		 19622
19623 constraint (imm >= (unsigned) (neon_quad (rs) ? 16 : 8),
19624 _("shift out of range"));
5287ad62
JB		 19625 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19626 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19627 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19628 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19629 inst.instruction |= LOW4 (inst.operands[2].reg);
19630 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
037e8744 19631 inst.instruction |= neon_quad (rs) << 6;
5287ad62 19632 inst.instruction |= imm << 8;
5f4273c7 19633
88714cb8 19634 neon_dp_fixup (&inst);
5287ad62
JB		 19635}
19636
19637static void
19638do_neon_rev (void)
19639{
64c350f2 19640 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 19641 return;
19642
19643 enum neon_shape rs;
19644 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19645 rs = neon_select_shape (NS_QQ, NS_NULL);
19646 else
19647 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
19648
5287ad62
JB		 19649 struct neon_type_el et = neon_check_type (2, rs,
19650 N_EQK, N_8 | N_16 | N_32 | N_KEY);
4401c241 19651
5287ad62
JB		 19652 unsigned op = (inst.instruction >> 7) & 3;
19653 /* N (width of reversed regions) is encoded as part of the bitmask. We
19654 extract it here to check the elements to be reversed are smaller.
19655 Otherwise we'd get a reserved instruction. */
19656 unsigned elsize = (op == 2) ? 16 : (op == 1) ? 32 : (op == 0) ? 64 : 0;
4401c241
AV		 19657
19658 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext) && elsize == 64
19659 && inst.operands[0].reg == inst.operands[1].reg)
19660 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19661 " operands makes instruction UNPREDICTABLE"));
19662
9c2799c2 19663 gas_assert (elsize != 0);
5287ad62 19664 constraint (et.size >= elsize,
477330fc 19665 _("elements must be smaller than reversal region"));
037e8744 19666 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 19667}
19668
19669static void
19670do_neon_dup (void)
19671{
19672 if (inst.operands[1].isscalar)
19673 {
b409bdb6
AV		 19674 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19675 BAD_FPU);
037e8744 19676 enum neon_shape rs = neon_select_shape (NS_DS, NS_QS, NS_NULL);
dcbf9037 19677 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19678 N_EQK, N_8 | N_16 | N_32 | N_KEY);
5287ad62 19679 unsigned sizebits = et.size >> 3;
dcbf9037 19680 unsigned dm = NEON_SCALAR_REG (inst.operands[1].reg);
5287ad62 19681 int logsize = neon_logbits (et.size);
dcbf9037 19682 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg) << logsize;
037e8744
JB		 19683
19684 if (vfp_or_neon_is_neon (NEON_CHECK_CC) == FAIL)
477330fc 19685 return;
037e8744 19686
88714cb8 19687 NEON_ENCODE (SCALAR, inst);
5287ad62
JB		 19688 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19689 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19690 inst.instruction |= LOW4 (dm);
19691 inst.instruction |= HI1 (dm) << 5;
037e8744 19692 inst.instruction |= neon_quad (rs) << 6;
5287ad62
JB		 19693 inst.instruction |= x << 17;
19694 inst.instruction |= sizebits << 16;
5f4273c7 19695
88714cb8 19696 neon_dp_fixup (&inst);
5287ad62
JB		 19697 }
19698 else
19699 {
037e8744
JB		 19700 enum neon_shape rs = neon_select_shape (NS_DR, NS_QR, NS_NULL);
19701 struct neon_type_el et = neon_check_type (2, rs,
477330fc 19702 N_8 | N_16 | N_32 | N_KEY, N_EQK);
b409bdb6
AV		 19703 if (rs == NS_QR)
19704 {
64c350f2 19705 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH))
b409bdb6
AV		 19706 return;
19707 }
19708 else
19709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1),
19710 BAD_FPU);
19711
19712 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19713 {
19714 if (inst.operands[1].reg == REG_SP)
19715 as_tsktsk (MVE_BAD_SP);
19716 else if (inst.operands[1].reg == REG_PC)
19717 as_tsktsk (MVE_BAD_PC);
19718 }
19719
5287ad62 19720 /* Duplicate ARM register to lanes of vector. */
88714cb8 19721 NEON_ENCODE (ARMREG, inst);
5287ad62 19722 switch (et.size)
477330fc
RM		 19723 {
19724 case 8: inst.instruction |= 0x400000; break;
19725 case 16: inst.instruction |= 0x000020; break;
19726 case 32: inst.instruction |= 0x000000; break;
19727 default: break;
19728 }
5287ad62
JB		 19729 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
19730 inst.instruction |= LOW4 (inst.operands[0].reg) << 16;
19731 inst.instruction |= HI1 (inst.operands[0].reg) << 7;
037e8744 19732 inst.instruction |= neon_quad (rs) << 21;
5287ad62 19733 /* The encoding for this instruction is identical for the ARM and Thumb
477330fc 19734 variants, except for the condition field. */
037e8744 19735 do_vfp_cond_or_thumb ();
5287ad62
JB		 19736 }
19737}
19738
57785aa2
AV		 19739static void
19740do_mve_mov (int toQ)
19741{
19742 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19743 return;
19744 if (inst.cond > COND_ALWAYS)
19745 inst.pred_insn_type = MVE_UNPREDICABLE_INSN;
19746
19747 unsigned Rt = 0, Rt2 = 1, Q0 = 2, Q1 = 3;
19748 if (toQ)
19749 {
19750 Q0 = 0;
19751 Q1 = 1;
19752 Rt = 2;
19753 Rt2 = 3;
19754 }
19755
19756 constraint (inst.operands[Q0].reg != inst.operands[Q1].reg + 2,
19757 _("Index one must be [2,3] and index two must be two less than"
19758 " index one."));
19759 constraint (inst.operands[Rt].reg == inst.operands[Rt2].reg,
19760 _("General purpose registers may not be the same"));
19761 constraint (inst.operands[Rt].reg == REG_SP
19762 || inst.operands[Rt2].reg == REG_SP,
19763 BAD_SP);
19764 constraint (inst.operands[Rt].reg == REG_PC
19765 || inst.operands[Rt2].reg == REG_PC,
19766 BAD_PC);
19767
19768 inst.instruction = 0xec000f00;
19769 inst.instruction |= HI1 (inst.operands[Q1].reg / 32) << 23;
19770 inst.instruction |= !!toQ << 20;
19771 inst.instruction |= inst.operands[Rt2].reg << 16;
19772 inst.instruction |= LOW4 (inst.operands[Q1].reg / 32) << 13;
19773 inst.instruction |= (inst.operands[Q1].reg % 4) << 4;
19774 inst.instruction |= inst.operands[Rt].reg;
19775}
19776
19777static void
19778do_mve_movn (void)
19779{
19780 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19781 return;
19782
19783 if (inst.cond > COND_ALWAYS)
19784 inst.pred_insn_type = INSIDE_VPT_INSN;
19785 else
19786 inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
19787
19788 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_I16 | N_I32
19789 | N_KEY);
19790
19791 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19792 inst.instruction |= (neon_logbits (et.size) - 1) << 18;
19793 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19794 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19795 inst.instruction |= LOW4 (inst.operands[1].reg);
19796 inst.is_neon = 1;
19797
19798}
19799
5287ad62
JB		 19800/* VMOV has particularly many variations. It can be one of:
19801 0. VMOV<c><q> <Qd>, <Qm>
19802 1. VMOV<c><q> <Dd>, <Dm>
19803 (Register operations, which are VORR with Rm = Rn.)
19804 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19805 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19806 (Immediate loads.)
19807 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19808 (ARM register to scalar.)
19809 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19810 (Two ARM registers to vector.)
19811 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19812 (Scalar to ARM register.)
19813 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19814 (Vector to two ARM registers.)
037e8744
JB		 19815 8. VMOV.F32 <Sd>, <Sm>
19816 9. VMOV.F64 <Dd>, <Dm>
19817 (VFP register moves.)
19818 10. VMOV.F32 <Sd>, #imm
19819 11. VMOV.F64 <Dd>, #imm
19820 (VFP float immediate load.)
19821 12. VMOV <Rd>, <Sm>
19822 (VFP single to ARM reg.)
19823 13. VMOV <Sd>, <Rm>
19824 (ARM reg to VFP single.)
19825 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19826 (Two ARM regs to two VFP singles.)
19827 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19828 (Two VFP singles to two ARM regs.)
57785aa2
AV		 19829 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19830 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19831 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19832 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
5f4273c7 19833
037e8744
JB		 19834 These cases can be disambiguated using neon_select_shape, except cases 1/9
19835 and 3/11 which depend on the operand type too.
5f4273c7 19836
5287ad62 19837 All the encoded bits are hardcoded by this function.
5f4273c7 19838
b7fc2769
JB		 19839 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19840 Cases 5, 7 may be used with VFPv2 and above.
5f4273c7 19841
5287ad62 19842 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
5f4273c7 19843 can specify a type where it doesn't make sense to, and is ignored). */
5287ad62
JB		 19844
19845static void
19846do_neon_mov (void)
19847{
57785aa2
AV		 19848 enum neon_shape rs = neon_select_shape (NS_RRSS, NS_SSRR, NS_RRFF, NS_FFRR,
19849 NS_DRR, NS_RRD, NS_QQ, NS_DD, NS_QI,
19850 NS_DI, NS_SR, NS_RS, NS_FF, NS_FI,
19851 NS_RF, NS_FR, NS_HR, NS_RH, NS_HI,
19852 NS_NULL);
037e8744
JB		 19853 struct neon_type_el et;
19854 const char *ldconst = 0;
5287ad62 19855
037e8744 19856 switch (rs)
5287ad62 19857 {
037e8744
JB		 19858 case NS_DD: /* case 1/9. */
19859 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19860 /* It is not an error here if no type is given. */
19861 inst.error = NULL;
19862 if (et.type == NT_float && et.size == 64)
477330fc
RM		 19863 {
19864 do_vfp_nsyn_opcode ("fcpyd");
19865 break;
19866 }
037e8744 19867 /* fall through. */
5287ad62 19868
037e8744
JB		 19869 case NS_QQ: /* case 0/1. */
19870 {
64c350f2
AV		 19871 if (!check_simd_pred_availability (FALSE,
19872 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc
RM		 19873 return;
19874 /* The architecture manual I have doesn't explicitly state which
19875 value the U bit should have for register->register moves, but
19876 the equivalent VORR instruction has U = 0, so do that. */
19877 inst.instruction = 0x0200110;
19878 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
19879 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
19880 inst.instruction |= LOW4 (inst.operands[1].reg);
19881 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
19882 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
19883 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
19884 inst.instruction |= neon_quad (rs) << 6;
19885
19886 neon_dp_fixup (&inst);
037e8744
JB		 19887 }
19888 break;
5f4273c7 19889
037e8744
JB		 19890 case NS_DI: /* case 3/11. */
19891 et = neon_check_type (2, rs, N_EQK, N_F64 | N_KEY);
19892 inst.error = NULL;
19893 if (et.type == NT_float && et.size == 64)
477330fc
RM		 19894 {
19895 /* case 11 (fconstd). */
19896 ldconst = "fconstd";
19897 goto encode_fconstd;
19898 }
037e8744
JB		 19899 /* fall through. */
19900
19901 case NS_QI: /* case 2/3. */
64c350f2
AV		 19902 if (!check_simd_pred_availability (FALSE,
19903 NEON_CHECK_CC | NEON_CHECK_ARCH))
477330fc 19904 return;
037e8744
JB		 19905 inst.instruction = 0x0800010;
19906 neon_move_immediate ();
88714cb8 19907 neon_dp_fixup (&inst);
5287ad62 19908 break;
5f4273c7 19909
037e8744
JB		 19910 case NS_SR: /* case 4. */
19911 {
477330fc
RM		 19912 unsigned bcdebits = 0;
19913 int logsize;
19914 unsigned dn = NEON_SCALAR_REG (inst.operands[0].reg);
19915 unsigned x = NEON_SCALAR_INDEX (inst.operands[0].reg);
037e8744 19916
05ac0ffb
JB		 19917 /* .<size> is optional here, defaulting to .32. */
19918 if (inst.vectype.elems == 0
19919 && inst.operands[0].vectype.type == NT_invtype
19920 && inst.operands[1].vectype.type == NT_invtype)
19921 {
19922 inst.vectype.el[0].type = NT_untyped;
19923 inst.vectype.el[0].size = 32;
19924 inst.vectype.elems = 1;
19925 }
19926
477330fc
RM		 19927 et = neon_check_type (2, NS_NULL, N_8 | N_16 | N_32 | N_KEY, N_EQK);
19928 logsize = neon_logbits (et.size);
19929
57785aa2
AV		 19930 if (et.size != 32)
19931 {
19932 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
19933 && vfp_or_neon_is_neon (NEON_CHECK_ARCH) == FAIL)
19934 return;
19935 }
19936 else
19937 {
19938 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
19939 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
19940 _(BAD_FPU));
19941 }
19942
19943 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
19944 {
19945 if (inst.operands[1].reg == REG_SP)
19946 as_tsktsk (MVE_BAD_SP);
19947 else if (inst.operands[1].reg == REG_PC)
19948 as_tsktsk (MVE_BAD_PC);
19949 }
19950 unsigned size = inst.operands[0].isscalar == 1 ? 64 : 128;
19951
477330fc 19952 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2
AV		 19953 constraint (x >= size / et.size, _("scalar index out of range"));
19954
477330fc
RM		 19955
19956 switch (et.size)
19957 {
19958 case 8: bcdebits = 0x8; break;
19959 case 16: bcdebits = 0x1; break;
19960 case 32: bcdebits = 0x0; break;
19961 default: ;
19962 }
19963
57785aa2 19964 bcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM		 19965
19966 inst.instruction = 0xe000b10;
19967 do_vfp_cond_or_thumb ();
19968 inst.instruction |= LOW4 (dn) << 16;
19969 inst.instruction |= HI1 (dn) << 7;
19970 inst.instruction |= inst.operands[1].reg << 12;
19971 inst.instruction |= (bcdebits & 3) << 5;
57785aa2
AV		 19972 inst.instruction |= ((bcdebits >> 2) & 3) << 21;
19973 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB		 19974 }
19975 break;
5f4273c7 19976
037e8744 19977 case NS_DRR: /* case 5 (fmdrr). */
57785aa2
AV		 19978 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
19979 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 19980 _(BAD_FPU));
b7fc2769 19981
037e8744
JB		 19982 inst.instruction = 0xc400b10;
19983 do_vfp_cond_or_thumb ();
19984 inst.instruction |= LOW4 (inst.operands[0].reg);
19985 inst.instruction |= HI1 (inst.operands[0].reg) << 5;
19986 inst.instruction |= inst.operands[1].reg << 12;
19987 inst.instruction |= inst.operands[2].reg << 16;
19988 break;
5f4273c7 19989
037e8744
JB		 19990 case NS_RS: /* case 6. */
19991 {
477330fc
RM		 19992 unsigned logsize;
19993 unsigned dn = NEON_SCALAR_REG (inst.operands[1].reg);
19994 unsigned x = NEON_SCALAR_INDEX (inst.operands[1].reg);
19995 unsigned abcdebits = 0;
037e8744 19996
05ac0ffb
JB		 19997 /* .<dt> is optional here, defaulting to .32. */
19998 if (inst.vectype.elems == 0
19999 && inst.operands[0].vectype.type == NT_invtype
20000 && inst.operands[1].vectype.type == NT_invtype)
20001 {
20002 inst.vectype.el[0].type = NT_untyped;
20003 inst.vectype.el[0].size = 32;
20004 inst.vectype.elems = 1;
20005 }
20006
91d6fa6a
NC		 20007 et = neon_check_type (2, NS_NULL,
20008 N_EQK, N_S8 | N_S16 | N_U8 | N_U16 | N_32 | N_KEY);
477330fc
RM		 20009 logsize = neon_logbits (et.size);
20010
57785aa2
AV		 20011 if (et.size != 32)
20012 {
20013 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
20014 && vfp_or_neon_is_neon (NEON_CHECK_CC
20015 | NEON_CHECK_ARCH) == FAIL)
20016 return;
20017 }
20018 else
20019 {
20020 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v1)
20021 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20022 _(BAD_FPU));
20023 }
20024
20025 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20026 {
20027 if (inst.operands[0].reg == REG_SP)
20028 as_tsktsk (MVE_BAD_SP);
20029 else if (inst.operands[0].reg == REG_PC)
20030 as_tsktsk (MVE_BAD_PC);
20031 }
20032
20033 unsigned size = inst.operands[1].isscalar == 1 ? 64 : 128;
20034
477330fc 20035 constraint (et.type == NT_invtype, _("bad type for scalar"));
57785aa2 20036 constraint (x >= size / et.size, _("scalar index out of range"));
477330fc
RM		 20037
20038 switch (et.size)
20039 {
20040 case 8: abcdebits = (et.type == NT_signed) ? 0x08 : 0x18; break;
20041 case 16: abcdebits = (et.type == NT_signed) ? 0x01 : 0x11; break;
20042 case 32: abcdebits = 0x00; break;
20043 default: ;
20044 }
20045
57785aa2 20046 abcdebits |= (x & ((1 << (3-logsize)) - 1)) << logsize;
477330fc
RM		 20047 inst.instruction = 0xe100b10;
20048 do_vfp_cond_or_thumb ();
20049 inst.instruction |= LOW4 (dn) << 16;
20050 inst.instruction |= HI1 (dn) << 7;
20051 inst.instruction |= inst.operands[0].reg << 12;
20052 inst.instruction |= (abcdebits & 3) << 5;
20053 inst.instruction |= (abcdebits >> 2) << 21;
57785aa2 20054 inst.instruction |= (x >> (3-logsize)) << 16;
037e8744
JB		 20055 }
20056 break;
5f4273c7 20057
037e8744 20058 case NS_RRD: /* case 7 (fmrrd). */
57785aa2
AV		 20059 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20060 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
477330fc 20061 _(BAD_FPU));
037e8744
JB		 20062
20063 inst.instruction = 0xc500b10;
20064 do_vfp_cond_or_thumb ();
20065 inst.instruction |= inst.operands[0].reg << 12;
20066 inst.instruction |= inst.operands[1].reg << 16;
20067 inst.instruction |= LOW4 (inst.operands[2].reg);
20068 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20069 break;
5f4273c7 20070
037e8744
JB		 20071 case NS_FF: /* case 8 (fcpys). */
20072 do_vfp_nsyn_opcode ("fcpys");
20073 break;
5f4273c7 20074
9db2f6b4 20075 case NS_HI:
037e8744
JB		 20076 case NS_FI: /* case 10 (fconsts). */
20077 ldconst = "fconsts";
4ef4710f 20078 encode_fconstd:
58ed5c38
TC		 20079 if (!inst.operands[1].immisfloat)
20080 {
4ef4710f 20081 unsigned new_imm;
58ed5c38 20082 /* Immediate has to fit in 8 bits so float is enough. */
4ef4710f
NC		 20083 float imm = (float) inst.operands[1].imm;
20084 memcpy (&new_imm, &imm, sizeof (float));
20085 /* But the assembly may have been written to provide an integer
20086 bit pattern that equates to a float, so check that the
20087 conversion has worked. */
20088 if (is_quarter_float (new_imm))
20089 {
20090 if (is_quarter_float (inst.operands[1].imm))
20091 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20092
20093 inst.operands[1].imm = new_imm;
20094 inst.operands[1].immisfloat = 1;
20095 }
58ed5c38
TC		 20096 }
20097
037e8744 20098 if (is_quarter_float (inst.operands[1].imm))
477330fc
RM		 20099 {
20100 inst.operands[1].imm = neon_qfloat_bits (inst.operands[1].imm);
20101 do_vfp_nsyn_opcode (ldconst);
9db2f6b4
RL		 20102
20103 /* ARMv8.2 fp16 vmov.f16 instruction. */
20104 if (rs == NS_HI)
20105 do_scalar_fp16_v82_encode ();
477330fc 20106 }
5287ad62 20107 else
477330fc 20108 first_error (_("immediate out of range"));
037e8744 20109 break;
5f4273c7 20110
9db2f6b4 20111 case NS_RH:
037e8744
JB		 20112 case NS_RF: /* case 12 (fmrs). */
20113 do_vfp_nsyn_opcode ("fmrs");
9db2f6b4
RL		 20114 /* ARMv8.2 fp16 vmov.f16 instruction. */
20115 if (rs == NS_RH)
20116 do_scalar_fp16_v82_encode ();
037e8744 20117 break;
5f4273c7 20118
9db2f6b4 20119 case NS_HR:
037e8744
JB		 20120 case NS_FR: /* case 13 (fmsr). */
20121 do_vfp_nsyn_opcode ("fmsr");
9db2f6b4
RL		 20122 /* ARMv8.2 fp16 vmov.f16 instruction. */
20123 if (rs == NS_HR)
20124 do_scalar_fp16_v82_encode ();
037e8744 20125 break;
5f4273c7 20126
57785aa2
AV		 20127 case NS_RRSS:
20128 do_mve_mov (0);
20129 break;
20130 case NS_SSRR:
20131 do_mve_mov (1);
20132 break;
20133
037e8744
JB		 20134 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20135 (one of which is a list), but we have parsed four. Do some fiddling to
20136 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20137 expect. */
20138 case NS_RRFF: /* case 14 (fmrrs). */
57785aa2
AV		 20139 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20140 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20141 _(BAD_FPU));
037e8744 20142 constraint (inst.operands[3].reg != inst.operands[2].reg + 1,
477330fc 20143 _("VFP registers must be adjacent"));
037e8744
JB		 20144 inst.operands[2].imm = 2;
20145 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20146 do_vfp_nsyn_opcode ("fmrrs");
20147 break;
5f4273c7 20148
037e8744 20149 case NS_FFRR: /* case 15 (fmsrr). */
57785aa2
AV		 20150 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_v2)
20151 && !ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext),
20152 _(BAD_FPU));
037e8744 20153 constraint (inst.operands[1].reg != inst.operands[0].reg + 1,
477330fc 20154 _("VFP registers must be adjacent"));
037e8744
JB		 20155 inst.operands[1] = inst.operands[2];
20156 inst.operands[2] = inst.operands[3];
20157 inst.operands[0].imm = 2;
20158 memset (&inst.operands[3], '\0', sizeof (inst.operands[3]));
20159 do_vfp_nsyn_opcode ("fmsrr");
5287ad62 20160 break;
5f4273c7 20161
4c261dff
NC		 20162 case NS_NULL:
20163 /* neon_select_shape has determined that the instruction
20164 shape is wrong and has already set the error message. */
20165 break;
20166
5287ad62
JB		 20167 default:
20168 abort ();
20169 }
20170}
20171
57785aa2
AV		 20172static void
20173do_mve_movl (void)
20174{
20175 if (!(inst.operands[0].present && inst.operands[0].isquad
20176 && inst.operands[1].present && inst.operands[1].isquad
20177 && !inst.operands[2].present))
20178 {
20179 inst.instruction = 0;
20180 inst.cond = 0xb;
20181 if (thumb_mode)
20182 set_pred_insn_type (INSIDE_IT_INSN);
20183 do_neon_mov ();
20184 return;
20185 }
20186
20187 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20188 return;
20189
20190 if (inst.cond != COND_ALWAYS)
20191 inst.pred_insn_type = INSIDE_VPT_INSN;
20192
20193 struct neon_type_el et = neon_check_type (2, NS_QQ, N_EQK, N_S8 | N_U8
20194 | N_S16 | N_U16 | N_KEY);
20195
20196 inst.instruction |= (et.type == NT_unsigned) << 28;
20197 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20198 inst.instruction |= (neon_logbits (et.size) + 1) << 19;
20199 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20200 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20201 inst.instruction |= LOW4 (inst.operands[1].reg);
20202 inst.is_neon = 1;
20203}
20204
5287ad62
JB		 20205static void
20206do_neon_rshift_round_imm (void)
20207{
64c350f2 20208 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
4401c241
AV		 20209 return;
20210
20211 enum neon_shape rs;
20212 struct neon_type_el et;
20213
20214 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20215 {
20216 rs = neon_select_shape (NS_QQI, NS_NULL);
20217 et = neon_check_type (2, rs, N_EQK, N_SU_MVE | N_KEY);
20218 }
20219 else
20220 {
20221 rs = neon_select_shape (NS_DDI, NS_QQI, NS_NULL);
20222 et = neon_check_type (2, rs, N_EQK, N_SU_ALL | N_KEY);
20223 }
5287ad62
JB		 20224 int imm = inst.operands[2].imm;
20225
20226 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20227 if (imm == 0)
20228 {
20229 inst.operands[2].present = 0;
20230 do_neon_mov ();
20231 return;
20232 }
20233
20234 constraint (imm < 1 || (unsigned)imm > et.size,
477330fc 20235 _("immediate out of range for shift"));
037e8744 20236 neon_imm_shift (TRUE, et.type == NT_unsigned, neon_quad (rs), et,
477330fc 20237 et.size - imm);
5287ad62
JB		 20238}
20239
9db2f6b4
RL		 20240static void
20241do_neon_movhf (void)
20242{
20243 enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
20244 constraint (rs != NS_HH, _("invalid suffix"));
20245
7bdf778b
ASDV		 20246 if (inst.cond != COND_ALWAYS)
20247 {
20248 if (thumb_mode)
20249 {
20250 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20251 " the behaviour is UNPREDICTABLE"));
20252 }
20253 else
20254 {
20255 inst.error = BAD_COND;
20256 return;
20257 }
20258 }
20259
9db2f6b4
RL		 20260 do_vfp_sp_monadic ();
20261
20262 inst.is_neon = 1;
20263 inst.instruction |= 0xf0000000;
20264}
20265
5287ad62
JB		 20266static void
20267do_neon_movl (void)
20268{
20269 struct neon_type_el et = neon_check_type (2, NS_QD,
20270 N_EQK | N_DBL, N_SU_32 | N_KEY);
20271 unsigned sizebits = et.size >> 3;
20272 inst.instruction |= sizebits << 19;
20273 neon_two_same (0, et.type == NT_unsigned, -1);
20274}
20275
20276static void
20277do_neon_trn (void)
20278{
037e8744 20279 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20280 struct neon_type_el et = neon_check_type (2, rs,
20281 N_EQK, N_8 | N_16 | N_32 | N_KEY);
88714cb8 20282 NEON_ENCODE (INTEGER, inst);
037e8744 20283 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20284}
20285
20286static void
20287do_neon_zip_uzp (void)
20288{
037e8744 20289 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20290 struct neon_type_el et = neon_check_type (2, rs,
20291 N_EQK, N_8 | N_16 | N_32 | N_KEY);
20292 if (rs == NS_DD && et.size == 32)
20293 {
20294 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20295 inst.instruction = N_MNEM_vtrn;
20296 do_neon_trn ();
20297 return;
20298 }
037e8744 20299 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20300}
20301
20302static void
20303do_neon_sat_abs_neg (void)
20304{
64c350f2 20305 if (!check_simd_pred_availability (FALSE, NEON_CHECK_CC | NEON_CHECK_ARCH))
1a186d29
AV		 20306 return;
20307
20308 enum neon_shape rs;
20309 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20310 rs = neon_select_shape (NS_QQ, NS_NULL);
20311 else
20312 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20313 struct neon_type_el et = neon_check_type (2, rs,
20314 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20315 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20316}
20317
20318static void
20319do_neon_pair_long (void)
20320{
037e8744 20321 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20322 struct neon_type_el et = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
20323 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20324 inst.instruction |= (et.type == NT_unsigned) << 7;
037e8744 20325 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20326}
20327
20328static void
20329do_neon_recip_est (void)
20330{
037e8744 20331 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62 20332 struct neon_type_el et = neon_check_type (2, rs,
cc933301 20333 N_EQK | N_FLT, N_F_16_32 | N_U32 | N_KEY);
5287ad62 20334 inst.instruction |= (et.type == NT_float) << 8;
037e8744 20335 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20336}
20337
20338static void
20339do_neon_cls (void)
20340{
64c350f2 20341 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV		 20342 return;
20343
20344 enum neon_shape rs;
20345 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20346 rs = neon_select_shape (NS_QQ, NS_NULL);
20347 else
20348 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20349
5287ad62
JB		 20350 struct neon_type_el et = neon_check_type (2, rs,
20351 N_EQK, N_S8 | N_S16 | N_S32 | N_KEY);
037e8744 20352 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20353}
20354
20355static void
20356do_neon_clz (void)
20357{
64c350f2 20358 if (!check_simd_pred_availability (FALSE, NEON_CHECK_ARCH | NEON_CHECK_CC))
f30ee27c
AV		 20359 return;
20360
20361 enum neon_shape rs;
20362 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20363 rs = neon_select_shape (NS_QQ, NS_NULL);
20364 else
20365 rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20366
5287ad62
JB		 20367 struct neon_type_el et = neon_check_type (2, rs,
20368 N_EQK, N_I8 | N_I16 | N_I32 | N_KEY);
037e8744 20369 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20370}
20371
20372static void
20373do_neon_cnt (void)
20374{
037e8744 20375 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
5287ad62
JB		 20376 struct neon_type_el et = neon_check_type (2, rs,
20377 N_EQK | N_INT, N_8 | N_KEY);
037e8744 20378 neon_two_same (neon_quad (rs), 1, et.size);
5287ad62
JB		 20379}
20380
20381static void
20382do_neon_swp (void)
20383{
037e8744
JB		 20384 enum neon_shape rs = neon_select_shape (NS_DD, NS_QQ, NS_NULL);
20385 neon_two_same (neon_quad (rs), 1, -1);
5287ad62
JB		 20386}
20387
20388static void
20389do_neon_tbl_tbx (void)
20390{
20391 unsigned listlenbits;
dcbf9037 20392 neon_check_type (3, NS_DLD, N_EQK, N_EQK, N_8 | N_KEY);
5f4273c7 20393
5287ad62
JB		 20394 if (inst.operands[1].imm < 1 || inst.operands[1].imm > 4)
20395 {
dcbf9037 20396 first_error (_("bad list length for table lookup"));
5287ad62
JB		 20397 return;
20398 }
5f4273c7 20399
5287ad62
JB		 20400 listlenbits = inst.operands[1].imm - 1;
20401 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20402 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20403 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
20404 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
20405 inst.instruction |= LOW4 (inst.operands[2].reg);
20406 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
20407 inst.instruction |= listlenbits << 8;
5f4273c7 20408
88714cb8 20409 neon_dp_fixup (&inst);
5287ad62
JB		 20410}
20411
20412static void
20413do_neon_ldm_stm (void)
20414{
20415 /* P, U and L bits are part of bitmask. */
20416 int is_dbmode = (inst.instruction & (1 << 24)) != 0;
20417 unsigned offsetbits = inst.operands[1].imm * 2;
20418
037e8744
JB		 20419 if (inst.operands[1].issingle)
20420 {
20421 do_vfp_nsyn_ldm_stm (is_dbmode);
20422 return;
20423 }
20424
5287ad62 20425 constraint (is_dbmode && !inst.operands[0].writeback,
477330fc 20426 _("writeback (!) must be used for VLDMDB and VSTMDB"));
5287ad62
JB		 20427
20428 constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
477330fc
RM		 20429 _("register list must contain at least 1 and at most 16 "
20430 "registers"));
5287ad62
JB		 20431
20432 inst.instruction |= inst.operands[0].reg << 16;
20433 inst.instruction |= inst.operands[0].writeback << 21;
20434 inst.instruction |= LOW4 (inst.operands[1].reg) << 12;
20435 inst.instruction |= HI1 (inst.operands[1].reg) << 22;
20436
20437 inst.instruction |= offsetbits;
5f4273c7 20438
037e8744 20439 do_vfp_cond_or_thumb ();
5287ad62
JB		 20440}
20441
20442static void
20443do_neon_ldr_str (void)
20444{
5287ad62 20445 int is_ldr = (inst.instruction & (1 << 20)) != 0;
5f4273c7 20446
6844b2c2
MGD		 20447 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20448 And is UNPREDICTABLE in thumb mode. */
fa94de6b 20449 if (!is_ldr
6844b2c2 20450 && inst.operands[1].reg == REG_PC
ba86b375 20451 && (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v7) || thumb_mode))
6844b2c2 20452 {
94dcf8bf 20453 if (thumb_mode)
6844b2c2 20454 inst.error = _("Use of PC here is UNPREDICTABLE");
94dcf8bf 20455 else if (warn_on_deprecated)
5c3696f8 20456 as_tsktsk (_("Use of PC here is deprecated"));
6844b2c2
MGD		 20457 }
20458
037e8744
JB		 20459 if (inst.operands[0].issingle)
20460 {
cd2f129f 20461 if (is_ldr)
477330fc 20462 do_vfp_nsyn_opcode ("flds");
cd2f129f 20463 else
477330fc 20464 do_vfp_nsyn_opcode ("fsts");
9db2f6b4
RL		 20465
20466 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20467 if (inst.vectype.el[0].size == 16)
20468 do_scalar_fp16_v82_encode ();
5287ad62
JB		 20469 }
20470 else
5287ad62 20471 {
cd2f129f 20472 if (is_ldr)
477330fc 20473 do_vfp_nsyn_opcode ("fldd");
5287ad62 20474 else
477330fc 20475 do_vfp_nsyn_opcode ("fstd");
5287ad62 20476 }
5287ad62
JB		 20477}
20478
32c36c3c
AV		 20479static void
20480do_t_vldr_vstr_sysreg (void)
20481{
20482 int fp_vldr_bitno = 20, sysreg_vldr_bitno = 20;
20483 bfd_boolean is_vldr = ((inst.instruction & (1 << fp_vldr_bitno)) != 0);
20484
20485 /* Use of PC is UNPREDICTABLE. */
20486 if (inst.operands[1].reg == REG_PC)
20487 inst.error = _("Use of PC here is UNPREDICTABLE");
20488
20489 if (inst.operands[1].immisreg)
20490 inst.error = _("instruction does not accept register index");
20491
20492 if (!inst.operands[1].isreg)
20493 inst.error = _("instruction does not accept PC-relative addressing");
20494
20495 if (abs (inst.operands[1].imm) >= (1 << 7))
20496 inst.error = _("immediate value out of range");
20497
20498 inst.instruction = 0xec000f80;
20499 if (is_vldr)
20500 inst.instruction |= 1 << sysreg_vldr_bitno;
20501 encode_arm_cp_address (1, TRUE, FALSE, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM);
20502 inst.instruction |= (inst.operands[0].imm & 0x7) << 13;
20503 inst.instruction |= (inst.operands[0].imm & 0x8) << 19;
20504}
20505
20506static void
20507do_vldr_vstr (void)
20508{
20509 bfd_boolean sysreg_op = !inst.operands[0].isreg;
20510
20511 /* VLDR/VSTR (System Register). */
20512 if (sysreg_op)
20513 {
20514 if (!mark_feature_used (&arm_ext_v8_1m_main))
20515 as_bad (_("Instruction not permitted on this architecture"));
20516
20517 do_t_vldr_vstr_sysreg ();
20518 }
20519 /* VLDR/VSTR. */
20520 else
20521 {
20522 if (!mark_feature_used (&fpu_vfp_ext_v1xd))
20523 as_bad (_("Instruction not permitted on this architecture"));
20524 do_neon_ldr_str ();
20525 }
20526}
20527
5287ad62
JB		 20528/* "interleave" version also handles non-interleaving register VLD1/VST1
20529 instructions. */
20530
20531static void
20532do_neon_ld_st_interleave (void)
20533{
037e8744 20534 struct neon_type_el et = neon_check_type (1, NS_NULL,
477330fc 20535 N_8 | N_16 | N_32 | N_64);
5287ad62
JB		 20536 unsigned alignbits = 0;
20537 unsigned idx;
20538 /* The bits in this table go:
20539 0: register stride of one (0) or two (1)
20540 1,2: register list length, minus one (1, 2, 3, 4).
20541 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20542 We use -1 for invalid entries. */
20543 const int typetable[] =
20544 {
20545 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20546 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20547 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20548 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20549 };
20550 int typebits;
20551
dcbf9037
JB		 20552 if (et.type == NT_invtype)
20553 return;
20554
5287ad62
JB		 20555 if (inst.operands[1].immisalign)
20556 switch (inst.operands[1].imm >> 8)
20557 {
20558 case 64: alignbits = 1; break;
20559 case 128:
477330fc 20560 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2
e23c0ad8 20561 && NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
477330fc
RM		 20562 goto bad_alignment;
20563 alignbits = 2;
20564 break;
5287ad62 20565 case 256:
477330fc
RM		 20566 if (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4)
20567 goto bad_alignment;
20568 alignbits = 3;
20569 break;
5287ad62
JB		 20570 default:
20571 bad_alignment:
477330fc
RM		 20572 first_error (_("bad alignment"));
20573 return;
5287ad62
JB		 20574 }
20575
20576 inst.instruction |= alignbits << 4;
20577 inst.instruction |= neon_logbits (et.size) << 6;
20578
20579 /* Bits [4:6] of the immediate in a list specifier encode register stride
20580 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20581 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20582 up the right value for "type" in a table based on this value and the given
20583 list style, then stick it back. */
20584 idx = ((inst.operands[0].imm >> 4) & 7)
477330fc 20585 | (((inst.instruction >> 8) & 3) << 3);
5287ad62
JB		 20586
20587 typebits = typetable[idx];
5f4273c7 20588
5287ad62 20589 constraint (typebits == -1, _("bad list type for instruction"));
1d50d57c 20590 constraint (((inst.instruction >> 8) & 3) && et.size == 64,
35c228db 20591 BAD_EL_TYPE);
5287ad62
JB		 20592
20593 inst.instruction &= ~0xf00;
20594 inst.instruction |= typebits << 8;
20595}
20596
20597/* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20598 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20599 otherwise. The variable arguments are a list of pairs of legal (size, align)
20600 values, terminated with -1. */
20601
20602static int
aa8a0863 20603neon_alignment_bit (int size, int align, int *do_alignment, ...)
5287ad62
JB		 20604{
20605 va_list ap;
20606 int result = FAIL, thissize, thisalign;
5f4273c7 20607
5287ad62
JB		 20608 if (!inst.operands[1].immisalign)
20609 {
aa8a0863 20610 *do_alignment = 0;
5287ad62
JB		 20611 return SUCCESS;
20612 }
5f4273c7 20613
aa8a0863 20614 va_start (ap, do_alignment);
5287ad62
JB		 20615
20616 do
20617 {
20618 thissize = va_arg (ap, int);
20619 if (thissize == -1)
477330fc 20620 break;
5287ad62
JB		 20621 thisalign = va_arg (ap, int);
20622
20623 if (size == thissize && align == thisalign)
477330fc 20624 result = SUCCESS;
5287ad62
JB		 20625 }
20626 while (result != SUCCESS);
20627
20628 va_end (ap);
20629
20630 if (result == SUCCESS)
aa8a0863 20631 *do_alignment = 1;
5287ad62 20632 else
dcbf9037 20633 first_error (_("unsupported alignment for instruction"));
5f4273c7 20634
5287ad62
JB		 20635 return result;
20636}
20637
20638static void
20639do_neon_ld_st_lane (void)
20640{
037e8744 20641 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20642 int align_good, do_alignment = 0;
5287ad62
JB		 20643 int logsize = neon_logbits (et.size);
20644 int align = inst.operands[1].imm >> 8;
20645 int n = (inst.instruction >> 8) & 3;
20646 int max_el = 64 / et.size;
5f4273c7 20647
dcbf9037
JB		 20648 if (et.type == NT_invtype)
20649 return;
5f4273c7 20650
5287ad62 20651 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != n + 1,
477330fc 20652 _("bad list length"));
5287ad62 20653 constraint (NEON_LANE (inst.operands[0].imm) >= max_el,
477330fc 20654 _("scalar index out of range"));
5287ad62 20655 constraint (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2
477330fc
RM		 20656 && et.size == 8,
20657 _("stride of 2 unavailable when element size is 8"));
5f4273c7 20658
5287ad62
JB		 20659 switch (n)
20660 {
20661 case 0: /* VLD1 / VST1. */
aa8a0863 20662 align_good = neon_alignment_bit (et.size, align, &do_alignment, 16, 16,
477330fc 20663 32, 32, -1);
5287ad62 20664 if (align_good == FAIL)
477330fc 20665 return;
aa8a0863 20666 if (do_alignment)
477330fc
RM		 20667 {
20668 unsigned alignbits = 0;
20669 switch (et.size)
20670 {
20671 case 16: alignbits = 0x1; break;
20672 case 32: alignbits = 0x3; break;
20673 default: ;
20674 }
20675 inst.instruction |= alignbits << 4;
20676 }
5287ad62
JB		 20677 break;
20678
20679 case 1: /* VLD2 / VST2. */
aa8a0863
TS		 20680 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 16,
20681 16, 32, 32, 64, -1);
5287ad62 20682 if (align_good == FAIL)
477330fc 20683 return;
aa8a0863 20684 if (do_alignment)
477330fc 20685 inst.instruction |= 1 << 4;
5287ad62
JB		 20686 break;
20687
20688 case 2: /* VLD3 / VST3. */
20689 constraint (inst.operands[1].immisalign,
477330fc 20690 _("can't use alignment with this instruction"));
5287ad62
JB		 20691 break;
20692
20693 case 3: /* VLD4 / VST4. */
aa8a0863 20694 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc 20695 16, 64, 32, 64, 32, 128, -1);
5287ad62 20696 if (align_good == FAIL)
477330fc 20697 return;
aa8a0863 20698 if (do_alignment)
477330fc
RM		 20699 {
20700 unsigned alignbits = 0;
20701 switch (et.size)
20702 {
20703 case 8: alignbits = 0x1; break;
20704 case 16: alignbits = 0x1; break;
20705 case 32: alignbits = (align == 64) ? 0x1 : 0x2; break;
20706 default: ;
20707 }
20708 inst.instruction |= alignbits << 4;
20709 }
5287ad62
JB		 20710 break;
20711
20712 default: ;
20713 }
20714
20715 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20716 if (n != 0 && NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20717 inst.instruction |= 1 << (4 + logsize);
5f4273c7 20718
5287ad62
JB		 20719 inst.instruction |= NEON_LANE (inst.operands[0].imm) << (logsize + 5);
20720 inst.instruction |= logsize << 10;
20721}
20722
20723/* Encode single n-element structure to all lanes VLD<n> instructions. */
20724
20725static void
20726do_neon_ld_dup (void)
20727{
037e8744 20728 struct neon_type_el et = neon_check_type (1, NS_NULL, N_8 | N_16 | N_32);
aa8a0863 20729 int align_good, do_alignment = 0;
5287ad62 20730
dcbf9037
JB		 20731 if (et.type == NT_invtype)
20732 return;
20733
5287ad62
JB		 20734 switch ((inst.instruction >> 8) & 3)
20735 {
20736 case 0: /* VLD1. */
9c2799c2 20737 gas_assert (NEON_REG_STRIDE (inst.operands[0].imm) != 2);
5287ad62 20738 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863 20739 &do_alignment, 16, 16, 32, 32, -1);
5287ad62 20740 if (align_good == FAIL)
477330fc 20741 return;
5287ad62 20742 switch (NEON_REGLIST_LENGTH (inst.operands[0].imm))
477330fc
RM		 20743 {
20744 case 1: break;
20745 case 2: inst.instruction |= 1 << 5; break;
20746 default: first_error (_("bad list length")); return;
20747 }
5287ad62
JB		 20748 inst.instruction |= neon_logbits (et.size) << 6;
20749 break;
20750
20751 case 1: /* VLD2. */
20752 align_good = neon_alignment_bit (et.size, inst.operands[1].imm >> 8,
aa8a0863
TS		 20753 &do_alignment, 8, 16, 16, 32, 32, 64,
20754 -1);
5287ad62 20755 if (align_good == FAIL)
477330fc 20756 return;
5287ad62 20757 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 2,
477330fc 20758 _("bad list length"));
5287ad62 20759 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 20760 inst.instruction |= 1 << 5;
5287ad62
JB		 20761 inst.instruction |= neon_logbits (et.size) << 6;
20762 break;
20763
20764 case 2: /* VLD3. */
20765 constraint (inst.operands[1].immisalign,
477330fc 20766 _("can't use alignment with this instruction"));
5287ad62 20767 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 3,
477330fc 20768 _("bad list length"));
5287ad62 20769 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
477330fc 20770 inst.instruction |= 1 << 5;
5287ad62
JB		 20771 inst.instruction |= neon_logbits (et.size) << 6;
20772 break;
20773
20774 case 3: /* VLD4. */
20775 {
477330fc 20776 int align = inst.operands[1].imm >> 8;
aa8a0863 20777 align_good = neon_alignment_bit (et.size, align, &do_alignment, 8, 32,
477330fc
RM		 20778 16, 64, 32, 64, 32, 128, -1);
20779 if (align_good == FAIL)
20780 return;
20781 constraint (NEON_REGLIST_LENGTH (inst.operands[0].imm) != 4,
20782 _("bad list length"));
20783 if (NEON_REG_STRIDE (inst.operands[0].imm) == 2)
20784 inst.instruction |= 1 << 5;
20785 if (et.size == 32 && align == 128)
20786 inst.instruction |= 0x3 << 6;
20787 else
20788 inst.instruction |= neon_logbits (et.size) << 6;
5287ad62
JB		 20789 }
20790 break;
20791
20792 default: ;
20793 }
20794
aa8a0863 20795 inst.instruction |= do_alignment << 4;
5287ad62
JB		 20796}
20797
20798/* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20799 apart from bits [11:4]. */
20800
20801static void
20802do_neon_ldx_stx (void)
20803{
b1a769ed
DG		 20804 if (inst.operands[1].isreg)
20805 constraint (inst.operands[1].reg == REG_PC, BAD_PC);
20806
5287ad62
JB		 20807 switch (NEON_LANE (inst.operands[0].imm))
20808 {
20809 case NEON_INTERLEAVE_LANES:
88714cb8 20810 NEON_ENCODE (INTERLV, inst);
5287ad62
JB		 20811 do_neon_ld_st_interleave ();
20812 break;
5f4273c7 20813
5287ad62 20814 case NEON_ALL_LANES:
88714cb8 20815 NEON_ENCODE (DUP, inst);
2d51fb74
JB		 20816 if (inst.instruction == N_INV)
20817 {
20818 first_error ("only loads support such operands");
20819 break;
20820 }
5287ad62
JB		 20821 do_neon_ld_dup ();
20822 break;
5f4273c7 20823
5287ad62 20824 default:
88714cb8 20825 NEON_ENCODE (LANE, inst);
5287ad62
JB		 20826 do_neon_ld_st_lane ();
20827 }
20828
20829 /* L bit comes from bit mask. */
20830 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20831 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20832 inst.instruction |= inst.operands[1].reg << 16;
5f4273c7 20833
5287ad62
JB		 20834 if (inst.operands[1].postind)
20835 {
20836 int postreg = inst.operands[1].imm & 0xf;
20837 constraint (!inst.operands[1].immisreg,
477330fc 20838 _("post-index must be a register"));
5287ad62 20839 constraint (postreg == 0xd || postreg == 0xf,
477330fc 20840 _("bad register for post-index"));
5287ad62
JB		 20841 inst.instruction |= postreg;
20842 }
4f2374c7 20843 else
5287ad62 20844 {
4f2374c7 20845 constraint (inst.operands[1].immisreg, BAD_ADDR_MODE);
e2b0ab59
AV		 20846 constraint (inst.relocs[0].exp.X_op != O_constant
20847 || inst.relocs[0].exp.X_add_number != 0,
4f2374c7
WN		 20848 BAD_ADDR_MODE);
20849
20850 if (inst.operands[1].writeback)
20851 {
20852 inst.instruction |= 0xd;
20853 }
20854 else
20855 inst.instruction |= 0xf;
5287ad62 20856 }
5f4273c7 20857
5287ad62
JB		 20858 if (thumb_mode)
20859 inst.instruction |= 0xf9000000;
20860 else
20861 inst.instruction |= 0xf4000000;
20862}
33399f07
MGD		 20863
20864/* FP v8. */
20865static void
20866do_vfp_nsyn_fpv8 (enum neon_shape rs)
20867{
a715796b
TG		 20868 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20869 D register operands. */
20870 if (neon_shape_class[rs] == SC_DOUBLE)
20871 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20872 _(BAD_FPU));
20873
33399f07
MGD		 20874 NEON_ENCODE (FPV8, inst);
20875
9db2f6b4
RL		 20876 if (rs == NS_FFF || rs == NS_HHH)
20877 {
20878 do_vfp_sp_dyadic ();
20879
20880 /* ARMv8.2 fp16 instruction. */
20881 if (rs == NS_HHH)
20882 do_scalar_fp16_v82_encode ();
20883 }
33399f07
MGD		 20884 else
20885 do_vfp_dp_rd_rn_rm ();
20886
20887 if (rs == NS_DDD)
20888 inst.instruction |= 0x100;
20889
20890 inst.instruction |= 0xf0000000;
20891}
20892
20893static void
20894do_vsel (void)
20895{
5ee91343 20896 set_pred_insn_type (OUTSIDE_PRED_INSN);
33399f07
MGD		 20897
20898 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) != SUCCESS)
20899 first_error (_("invalid instruction shape"));
20900}
20901
73924fbc
MGD		 20902static void
20903do_vmaxnm (void)
20904{
935295b5
AV		 20905 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
20906 set_pred_insn_type (OUTSIDE_PRED_INSN);
73924fbc
MGD		 20907
20908 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
20909 return;
20910
64c350f2 20911 if (!check_simd_pred_availability (TRUE, NEON_CHECK_CC | NEON_CHECK_ARCH8))
73924fbc
MGD		 20912 return;
20913
cc933301 20914 neon_dyadic_misc (NT_untyped, N_F_16_32, 0);
73924fbc
MGD		 20915}
20916
30bdf752
MGD		 20917static void
20918do_vrint_1 (enum neon_cvt_mode mode)
20919{
9db2f6b4 20920 enum neon_shape rs = neon_select_shape (NS_HH, NS_FF, NS_DD, NS_QQ, NS_NULL);
30bdf752
MGD		 20921 struct neon_type_el et;
20922
20923 if (rs == NS_NULL)
20924 return;
20925
a715796b
TG		 20926 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20927 D register operands. */
20928 if (neon_shape_class[rs] == SC_DOUBLE)
20929 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
20930 _(BAD_FPU));
20931
9db2f6b4
RL		 20932 et = neon_check_type (2, rs, N_EQK | N_VFP, N_F_ALL | N_KEY
20933 | N_VFP);
30bdf752
MGD		 20934 if (et.type != NT_invtype)
20935 {
20936 /* VFP encodings. */
20937 if (mode == neon_cvt_mode_a || mode == neon_cvt_mode_n
20938 || mode == neon_cvt_mode_p || mode == neon_cvt_mode_m)
5ee91343 20939 set_pred_insn_type (OUTSIDE_PRED_INSN);
30bdf752
MGD		 20940
20941 NEON_ENCODE (FPV8, inst);
9db2f6b4 20942 if (rs == NS_FF || rs == NS_HH)
30bdf752
MGD		 20943 do_vfp_sp_monadic ();
20944 else
20945 do_vfp_dp_rd_rm ();
20946
20947 switch (mode)
20948 {
20949 case neon_cvt_mode_r: inst.instruction |= 0x00000000; break;
20950 case neon_cvt_mode_z: inst.instruction |= 0x00000080; break;
20951 case neon_cvt_mode_x: inst.instruction |= 0x00010000; break;
20952 case neon_cvt_mode_a: inst.instruction |= 0xf0000000; break;
20953 case neon_cvt_mode_n: inst.instruction |= 0xf0010000; break;
20954 case neon_cvt_mode_p: inst.instruction |= 0xf0020000; break;
20955 case neon_cvt_mode_m: inst.instruction |= 0xf0030000; break;
20956 default: abort ();
20957 }
20958
20959 inst.instruction |= (rs == NS_DD) << 8;
20960 do_vfp_cond_or_thumb ();
9db2f6b4
RL		 20961
20962 /* ARMv8.2 fp16 vrint instruction. */
20963 if (rs == NS_HH)
20964 do_scalar_fp16_v82_encode ();
30bdf752
MGD		 20965 }
20966 else
20967 {
20968 /* Neon encodings (or something broken...). */
20969 inst.error = NULL;
cc933301 20970 et = neon_check_type (2, rs, N_EQK, N_F_16_32 | N_KEY);
30bdf752
MGD		 20971
20972 if (et.type == NT_invtype)
20973 return;
20974
64c350f2
AV		 20975 if (!check_simd_pred_availability (TRUE,
20976 NEON_CHECK_CC | NEON_CHECK_ARCH8))
30bdf752
MGD		 20977 return;
20978
a710b305
AV		 20979 NEON_ENCODE (FLOAT, inst);
20980
30bdf752
MGD		 20981 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
20982 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
20983 inst.instruction |= LOW4 (inst.operands[1].reg);
20984 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
20985 inst.instruction |= neon_quad (rs) << 6;
cc933301
JW		 20986 /* Mask off the original size bits and reencode them. */
20987 inst.instruction = ((inst.instruction & 0xfff3ffff)
20988 | neon_logbits (et.size) << 18);
20989
30bdf752
MGD		 20990 switch (mode)
20991 {
20992 case neon_cvt_mode_z: inst.instruction |= 3 << 7; break;
20993 case neon_cvt_mode_x: inst.instruction |= 1 << 7; break;
20994 case neon_cvt_mode_a: inst.instruction |= 2 << 7; break;
20995 case neon_cvt_mode_n: inst.instruction |= 0 << 7; break;
20996 case neon_cvt_mode_p: inst.instruction |= 7 << 7; break;
20997 case neon_cvt_mode_m: inst.instruction |= 5 << 7; break;
20998 case neon_cvt_mode_r: inst.error = _("invalid rounding mode"); break;
20999 default: abort ();
21000 }
21001
21002 if (thumb_mode)
21003 inst.instruction |= 0xfc000000;
21004 else
21005 inst.instruction |= 0xf0000000;
21006 }
21007}
21008
21009static void
21010do_vrintx (void)
21011{
21012 do_vrint_1 (neon_cvt_mode_x);
21013}
21014
21015static void
21016do_vrintz (void)
21017{
21018 do_vrint_1 (neon_cvt_mode_z);
21019}
21020
21021static void
21022do_vrintr (void)
21023{
21024 do_vrint_1 (neon_cvt_mode_r);
21025}
21026
21027static void
21028do_vrinta (void)
21029{
21030 do_vrint_1 (neon_cvt_mode_a);
21031}
21032
21033static void
21034do_vrintn (void)
21035{
21036 do_vrint_1 (neon_cvt_mode_n);
21037}
21038
21039static void
21040do_vrintp (void)
21041{
21042 do_vrint_1 (neon_cvt_mode_p);
21043}
21044
21045static void
21046do_vrintm (void)
21047{
21048 do_vrint_1 (neon_cvt_mode_m);
21049}
21050
c28eeff2
SN		 21051static unsigned
21052neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
21053{
21054 unsigned regno = NEON_SCALAR_REG (opnd);
21055 unsigned elno = NEON_SCALAR_INDEX (opnd);
21056
21057 if (elsize == 16 && elno < 2 && regno < 16)
21058 return regno | (elno << 4);
21059 else if (elsize == 32 && elno == 0)
21060 return regno;
21061
21062 first_error (_("scalar out of range"));
21063 return 0;
21064}
21065
21066static void
21067do_vcmla (void)
21068{
5d281bf0
AV		 21069 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext)
21070 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21071 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV		 21072 constraint (inst.relocs[0].exp.X_op != O_constant,
21073 _("expression too complex"));
21074 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2
SN		 21075 constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
21076 _("immediate out of range"));
21077 rot /= 90;
5d281bf0 21078
64c350f2
AV		 21079 if (!check_simd_pred_availability (TRUE,
21080 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV		 21081 return;
21082
c28eeff2
SN		 21083 if (inst.operands[2].isscalar)
21084 {
5d281bf0
AV		 21085 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21086 first_error (_("invalid instruction shape"));
c28eeff2
SN		 21087 enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
21088 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21089 N_KEY | N_F16 | N_F32).size;
21090 unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
21091 inst.is_neon = 1;
21092 inst.instruction = 0xfe000800;
21093 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21094 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21095 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21096 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21097 inst.instruction |= LOW4 (m);
21098 inst.instruction |= HI1 (m) << 5;
21099 inst.instruction |= neon_quad (rs) << 6;
21100 inst.instruction |= rot << 20;
21101 inst.instruction |= (size == 32) << 23;
21102 }
21103 else
21104 {
5d281bf0
AV		 21105 enum neon_shape rs;
21106 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext))
21107 rs = neon_select_shape (NS_QQQI, NS_NULL);
21108 else
21109 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21110
c28eeff2
SN		 21111 unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
21112 N_KEY | N_F16 | N_F32).size;
5d281bf0
AV		 21113 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_fp_ext) && size == 32
21114 && (inst.operands[0].reg == inst.operands[1].reg
21115 || inst.operands[0].reg == inst.operands[2].reg))
21116 as_tsktsk (BAD_MVE_SRCDEST);
21117
c28eeff2
SN		 21118 neon_three_same (neon_quad (rs), 0, -1);
21119 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21120 inst.instruction |= 0xfc200800;
21121 inst.instruction |= rot << 23;
21122 inst.instruction |= (size == 32) << 20;
21123 }
21124}
21125
21126static void
21127do_vcadd (void)
21128{
5d281bf0
AV		 21129 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext)
21130 && (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8)
21131 || !mark_feature_used (&arm_ext_v8_3)), (BAD_FPU));
e2b0ab59
AV		 21132 constraint (inst.relocs[0].exp.X_op != O_constant,
21133 _("expression too complex"));
5d281bf0 21134
e2b0ab59 21135 unsigned rot = inst.relocs[0].exp.X_add_number;
c28eeff2 21136 constraint (rot != 90 && rot != 270, _("immediate out of range"));
5d281bf0
AV		 21137 enum neon_shape rs;
21138 struct neon_type_el et;
21139 if (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21140 {
21141 rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
21142 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32);
21143 }
21144 else
21145 {
21146 rs = neon_select_shape (NS_QQQI, NS_NULL);
21147 et = neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_F16 | N_F32 | N_I8
21148 | N_I16 | N_I32);
21149 if (et.size == 32 && inst.operands[0].reg == inst.operands[2].reg)
21150 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21151 "operand makes instruction UNPREDICTABLE"));
21152 }
21153
21154 if (et.type == NT_invtype)
21155 return;
21156
64c350f2
AV		 21157 if (!check_simd_pred_availability (et.type == NT_float,
21158 NEON_CHECK_ARCH8 | NEON_CHECK_CC))
5d281bf0
AV		 21159 return;
21160
21161 if (et.type == NT_float)
21162 {
21163 neon_three_same (neon_quad (rs), 0, -1);
21164 inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
21165 inst.instruction |= 0xfc800800;
21166 inst.instruction |= (rot == 270) << 24;
21167 inst.instruction |= (et.size == 32) << 20;
21168 }
21169 else
21170 {
21171 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext), BAD_FPU);
21172 inst.instruction = 0xfe000f00;
21173 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21174 inst.instruction |= neon_logbits (et.size) << 20;
21175 inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
21176 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21177 inst.instruction |= (rot == 270) << 12;
21178 inst.instruction |= HI1 (inst.operands[1].reg) << 7;
21179 inst.instruction |= HI1 (inst.operands[2].reg) << 5;
21180 inst.instruction |= LOW4 (inst.operands[2].reg);
21181 inst.is_neon = 1;
21182 }
c28eeff2
SN		 21183}
21184
c604a79a
JW		 21185/* Dot Product instructions encoding support. */
21186
21187static void
21188do_neon_dotproduct (int unsigned_p)
21189{
21190 enum neon_shape rs;
21191 unsigned scalar_oprd2 = 0;
21192 int high8;
21193
21194 if (inst.cond != COND_ALWAYS)
21195 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21196 "is UNPREDICTABLE"));
21197
21198 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
21199 _(BAD_FPU));
21200
21201 /* Dot Product instructions are in three-same D/Q register format or the third
21202 operand can be a scalar index register. */
21203 if (inst.operands[2].isscalar)
21204 {
21205 scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
21206 high8 = 0xfe000000;
21207 rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
21208 }
21209 else
21210 {
21211 high8 = 0xfc000000;
21212 rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
21213 }
21214
21215 if (unsigned_p)
21216 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
21217 else
21218 neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
21219
21220 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21221 Product instruction, so we pass 0 as the "ubit" parameter. And the
21222 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21223 neon_three_same (neon_quad (rs), 0, 32);
21224
21225 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21226 different NEON three-same encoding. */
21227 inst.instruction &= 0x00ffffff;
21228 inst.instruction |= high8;
21229 /* Encode 'U' bit which indicates signedness. */
21230 inst.instruction |= (unsigned_p ? 1 : 0) << 4;
21231 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21232 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21233 the instruction encoding. */
21234 if (inst.operands[2].isscalar)
21235 {
21236 inst.instruction &= 0xffffffd0;
21237 inst.instruction |= LOW4 (scalar_oprd2);
21238 inst.instruction |= HI1 (scalar_oprd2) << 5;
21239 }
21240}
21241
21242/* Dot Product instructions for signed integer. */
21243
21244static void
21245do_neon_dotproduct_s (void)
21246{
21247 return do_neon_dotproduct (0);
21248}
21249
21250/* Dot Product instructions for unsigned integer. */
21251
21252static void
21253do_neon_dotproduct_u (void)
21254{
21255 return do_neon_dotproduct (1);
21256}
21257
91ff7894
MGD		 21258/* Crypto v1 instructions. */
21259static void
21260do_crypto_2op_1 (unsigned elttype, int op)
21261{
5ee91343 21262 set_pred_insn_type (OUTSIDE_PRED_INSN);
91ff7894
MGD		 21263
21264 if (neon_check_type (2, NS_QQ, N_EQK | N_UNT, elttype | N_UNT | N_KEY).type
21265 == NT_invtype)
21266 return;
21267
21268 inst.error = NULL;
21269
21270 NEON_ENCODE (INTEGER, inst);
21271 inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
21272 inst.instruction |= HI1 (inst.operands[0].reg) << 22;
21273 inst.instruction |= LOW4 (inst.operands[1].reg);
21274 inst.instruction |= HI1 (inst.operands[1].reg) << 5;
21275 if (op != -1)
21276 inst.instruction |= op << 6;
21277
21278 if (thumb_mode)
21279 inst.instruction |= 0xfc000000;
21280 else
21281 inst.instruction |= 0xf0000000;
21282}
21283
48adcd8e
MGD		 21284static void
21285do_crypto_3op_1 (int u, int op)
21286{
5ee91343 21287 set_pred_insn_type (OUTSIDE_PRED_INSN);
48adcd8e
MGD		 21288
21289 if (neon_check_type (3, NS_QQQ, N_EQK | N_UNT, N_EQK | N_UNT,
21290 N_32 | N_UNT | N_KEY).type == NT_invtype)
21291 return;
21292
21293 inst.error = NULL;
21294
21295 NEON_ENCODE (INTEGER, inst);
21296 neon_three_same (1, u, 8 << op);
21297}
21298
91ff7894
MGD		 21299static void
21300do_aese (void)
21301{
21302 do_crypto_2op_1 (N_8, 0);
21303}
21304
21305static void
21306do_aesd (void)
21307{
21308 do_crypto_2op_1 (N_8, 1);
21309}
21310
21311static void
21312do_aesmc (void)
21313{
21314 do_crypto_2op_1 (N_8, 2);
21315}
21316
21317static void
21318do_aesimc (void)
21319{
21320 do_crypto_2op_1 (N_8, 3);
21321}
21322
48adcd8e
MGD		 21323static void
21324do_sha1c (void)
21325{
21326 do_crypto_3op_1 (0, 0);
21327}
21328
21329static void
21330do_sha1p (void)
21331{
21332 do_crypto_3op_1 (0, 1);
21333}
21334
21335static void
21336do_sha1m (void)
21337{
21338 do_crypto_3op_1 (0, 2);
21339}
21340
21341static void
21342do_sha1su0 (void)
21343{
21344 do_crypto_3op_1 (0, 3);
21345}
91ff7894 21346
48adcd8e
MGD		 21347static void
21348do_sha256h (void)
21349{
21350 do_crypto_3op_1 (1, 0);
21351}
21352
21353static void
21354do_sha256h2 (void)
21355{
21356 do_crypto_3op_1 (1, 1);
21357}
21358
21359static void
21360do_sha256su1 (void)
21361{
21362 do_crypto_3op_1 (1, 2);
21363}
3c9017d2
MGD		 21364
21365static void
21366do_sha1h (void)
21367{
21368 do_crypto_2op_1 (N_32, -1);
21369}
21370
21371static void
21372do_sha1su1 (void)
21373{
21374 do_crypto_2op_1 (N_32, 0);
21375}
21376
21377static void
21378do_sha256su0 (void)
21379{
21380 do_crypto_2op_1 (N_32, 1);
21381}
dd5181d5
KT		 21382
21383static void
21384do_crc32_1 (unsigned int poly, unsigned int sz)
21385{
21386 unsigned int Rd = inst.operands[0].reg;
21387 unsigned int Rn = inst.operands[1].reg;
21388 unsigned int Rm = inst.operands[2].reg;
21389
5ee91343 21390 set_pred_insn_type (OUTSIDE_PRED_INSN);
dd5181d5
KT		 21391 inst.instruction |= LOW4 (Rd) << (thumb_mode ? 8 : 12);
21392 inst.instruction |= LOW4 (Rn) << 16;
21393 inst.instruction |= LOW4 (Rm);
21394 inst.instruction |= sz << (thumb_mode ? 4 : 21);
21395 inst.instruction |= poly << (thumb_mode ? 20 : 9);
21396
21397 if (Rd == REG_PC || Rn == REG_PC || Rm == REG_PC)
21398 as_warn (UNPRED_REG ("r15"));
dd5181d5
KT		 21399}
21400
21401static void
21402do_crc32b (void)
21403{
21404 do_crc32_1 (0, 0);
21405}
21406
21407static void
21408do_crc32h (void)
21409{
21410 do_crc32_1 (0, 1);
21411}
21412
21413static void
21414do_crc32w (void)
21415{
21416 do_crc32_1 (0, 2);
21417}
21418
21419static void
21420do_crc32cb (void)
21421{
21422 do_crc32_1 (1, 0);
21423}
21424
21425static void
21426do_crc32ch (void)
21427{
21428 do_crc32_1 (1, 1);
21429}
21430
21431static void
21432do_crc32cw (void)
21433{
21434 do_crc32_1 (1, 2);
21435}
21436
49e8a725
SN		 21437static void
21438do_vjcvt (void)
21439{
21440 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
21441 _(BAD_FPU));
21442 neon_check_type (2, NS_FD, N_S32, N_F64);
21443 do_vfp_sp_dp_cvt ();
21444 do_vfp_cond_or_thumb ();
21445}
21446
5287ad62
JB		 21447\f
21448/* Overall per-instruction processing. */
21449
21450/* We need to be able to fix up arbitrary expressions in some statements.
21451 This is so that we can handle symbols that are an arbitrary distance from
21452 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21453 which returns part of an address in a form which will be valid for
21454 a data instruction. We do this by pushing the expression into a symbol
21455 in the expr_section, and creating a fix for that. */
21456
21457static void
21458fix_new_arm (fragS * frag,
21459 int where,
21460 short int size,
21461 expressionS * exp,
21462 int pc_rel,
21463 int reloc)
21464{
21465 fixS * new_fix;
21466
21467 switch (exp->X_op)
21468 {
21469 case O_constant:
6e7ce2cd
PB		 21470 if (pc_rel)
21471 {
21472 /* Create an absolute valued symbol, so we have something to
477330fc
RM		 21473 refer to in the object file. Unfortunately for us, gas's
21474 generic expression parsing will already have folded out
21475 any use of .set foo/.type foo %function that may have
21476 been used to set type information of the target location,
21477 that's being specified symbolically. We have to presume
21478 the user knows what they are doing. */
6e7ce2cd
PB		 21479 char name[16 + 8];
21480 symbolS *symbol;
21481
21482 sprintf (name, "*ABS*0x%lx", (unsigned long)exp->X_add_number);
21483
21484 symbol = symbol_find_or_make (name);
21485 S_SET_SEGMENT (symbol, absolute_section);
21486 symbol_set_frag (symbol, &zero_address_frag);
21487 S_SET_VALUE (symbol, exp->X_add_number);
21488 exp->X_op = O_symbol;
21489 exp->X_add_symbol = symbol;
21490 exp->X_add_number = 0;
21491 }
21492 /* FALLTHROUGH */
5287ad62
JB		 21493 case O_symbol:
21494 case O_add:
21495 case O_subtract:
21d799b5 21496 new_fix = fix_new_exp (frag, where, size, exp, pc_rel,
477330fc 21497 (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 21498 break;
21499
21500 default:
21d799b5 21501 new_fix = (fixS *) fix_new (frag, where, size, make_expr_symbol (exp), 0,
477330fc 21502 pc_rel, (enum bfd_reloc_code_real) reloc);
5287ad62
JB		 21503 break;
21504 }
21505
21506 /* Mark whether the fix is to a THUMB instruction, or an ARM
21507 instruction. */
21508 new_fix->tc_fix_data = thumb_mode;
21509}
21510
21511/* Create a frg for an instruction requiring relaxation. */
21512static void
21513output_relax_insn (void)
21514{
21515 char * to;
21516 symbolS *sym;
0110f2b8
PB		 21517 int offset;
21518
6e1cb1a6
PB		 21519 /* The size of the instruction is unknown, so tie the debug info to the
21520 start of the instruction. */
21521 dwarf2_emit_insn (0);
6e1cb1a6 21522
e2b0ab59 21523 switch (inst.relocs[0].exp.X_op)
0110f2b8
PB		 21524 {
21525 case O_symbol:
e2b0ab59
AV		 21526 sym = inst.relocs[0].exp.X_add_symbol;
21527 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB		 21528 break;
21529 case O_constant:
21530 sym = NULL;
e2b0ab59 21531 offset = inst.relocs[0].exp.X_add_number;
0110f2b8
PB		 21532 break;
21533 default:
e2b0ab59 21534 sym = make_expr_symbol (&inst.relocs[0].exp);
0110f2b8
PB		 21535 offset = 0;
21536 break;
21537 }
21538 to = frag_var (rs_machine_dependent, INSN_SIZE, THUMB_SIZE,
21539 inst.relax, sym, offset, NULL/*offset, opcode*/);
21540 md_number_to_chars (to, inst.instruction, THUMB_SIZE);
0110f2b8
PB		 21541}
21542
21543/* Write a 32-bit thumb instruction to buf. */
21544static void
21545put_thumb32_insn (char * buf, unsigned long insn)
21546{
21547 md_number_to_chars (buf, insn >> 16, THUMB_SIZE);
21548 md_number_to_chars (buf + THUMB_SIZE, insn, THUMB_SIZE);
21549}
21550
b99bd4ef 21551static void
c19d1205 21552output_inst (const char * str)
b99bd4ef 21553{
c19d1205 21554 char * to = NULL;
b99bd4ef 21555
c19d1205 21556 if (inst.error)
b99bd4ef 21557 {
c19d1205 21558 as_bad ("%s -- `%s'", inst.error, str);
b99bd4ef
NC		 21559 return;
21560 }
5f4273c7
NC		 21561 if (inst.relax)
21562 {
21563 output_relax_insn ();
0110f2b8 21564 return;
5f4273c7 21565 }
c19d1205
ZW		 21566 if (inst.size == 0)
21567 return;
b99bd4ef 21568
c19d1205 21569 to = frag_more (inst.size);
8dc2430f
NC		 21570 /* PR 9814: Record the thumb mode into the current frag so that we know
21571 what type of NOP padding to use, if necessary. We override any previous
21572 setting so that if the mode has changed then the NOPS that we use will
21573 match the encoding of the last instruction in the frag. */
cd000bff 21574 frag_now->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
c19d1205
ZW		 21575
21576 if (thumb_mode && (inst.size > THUMB_SIZE))
b99bd4ef 21577 {
9c2799c2 21578 gas_assert (inst.size == (2 * THUMB_SIZE));
0110f2b8 21579 put_thumb32_insn (to, inst.instruction);
b99bd4ef 21580 }
c19d1205 21581 else if (inst.size > INSN_SIZE)
b99bd4ef 21582 {
9c2799c2 21583 gas_assert (inst.size == (2 * INSN_SIZE));
c19d1205
ZW		 21584 md_number_to_chars (to, inst.instruction, INSN_SIZE);
21585 md_number_to_chars (to + INSN_SIZE, inst.instruction, INSN_SIZE);
b99bd4ef 21586 }
c19d1205
ZW		 21587 else
21588 md_number_to_chars (to, inst.instruction, inst.size);
b99bd4ef 21589
e2b0ab59
AV		 21590 int r;
21591 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
21592 {
21593 if (inst.relocs[r].type != BFD_RELOC_UNUSED)
21594 fix_new_arm (frag_now, to - frag_now->fr_literal,
21595 inst.size, & inst.relocs[r].exp, inst.relocs[r].pc_rel,
21596 inst.relocs[r].type);
21597 }
b99bd4ef 21598
c19d1205 21599 dwarf2_emit_insn (inst.size);
c19d1205 21600}
b99bd4ef 21601
e07e6e58
NC		 21602static char *
21603output_it_inst (int cond, int mask, char * to)
21604{
21605 unsigned long instruction = 0xbf00;
21606
21607 mask &= 0xf;
21608 instruction |= mask;
21609 instruction |= cond << 4;
21610
21611 if (to == NULL)
21612 {
21613 to = frag_more (2);
21614#ifdef OBJ_ELF
21615 dwarf2_emit_insn (2);
21616#endif
21617 }
21618
21619 md_number_to_chars (to, instruction, 2);
21620
21621 return to;
21622}
21623
c19d1205
ZW		 21624/* Tag values used in struct asm_opcode's tag field. */
21625enum opcode_tag
21626{
21627 OT_unconditional, /* Instruction cannot be conditionalized.
21628 The ARM condition field is still 0xE. */
21629 OT_unconditionalF, /* Instruction cannot be conditionalized
21630 and carries 0xF in its ARM condition field. */
21631 OT_csuffix, /* Instruction takes a conditional suffix. */
5ee91343
AV		 21632 OT_csuffixF, /* Some forms of the instruction take a scalar
21633 conditional suffix, others place 0xF where the
21634 condition field would be, others take a vector
21635 conditional suffix. */
c19d1205
ZW		 21636 OT_cinfix3, /* Instruction takes a conditional infix,
21637 beginning at character index 3. (In
21638 unified mode, it becomes a suffix.) */
088fa78e
KH		 21639 OT_cinfix3_deprecated, /* The same as OT_cinfix3. This is used for
21640 tsts, cmps, cmns, and teqs. */
e3cb604e
PB		 21641 OT_cinfix3_legacy, /* Legacy instruction takes a conditional infix at
21642 character index 3, even in unified mode. Used for
21643 legacy instructions where suffix and infix forms
21644 may be ambiguous. */
c19d1205 21645 OT_csuf_or_in3, /* Instruction takes either a conditional
e3cb604e 21646 suffix or an infix at character index 3. */
c19d1205
ZW		 21647 OT_odd_infix_unc, /* This is the unconditional variant of an
21648 instruction that takes a conditional infix
21649 at an unusual position. In unified mode,
21650 this variant will accept a suffix. */
21651 OT_odd_infix_0 /* Values greater than or equal to OT_odd_infix_0
21652 are the conditional variants of instructions that
21653 take conditional infixes in unusual positions.
21654 The infix appears at character index
21655 (tag - OT_odd_infix_0). These are not accepted
21656 in unified mode. */
21657};
b99bd4ef 21658
c19d1205
ZW		 21659/* Subroutine of md_assemble, responsible for looking up the primary
21660 opcode from the mnemonic the user wrote. STR points to the
21661 beginning of the mnemonic.
21662
21663 This is not simply a hash table lookup, because of conditional
21664 variants. Most instructions have conditional variants, which are
21665 expressed with a _conditional affix_ to the mnemonic. If we were
21666 to encode each conditional variant as a literal string in the opcode
21667 table, it would have approximately 20,000 entries.
21668
21669 Most mnemonics take this affix as a suffix, and in unified syntax,
21670 'most' is upgraded to 'all'. However, in the divided syntax, some
21671 instructions take the affix as an infix, notably the s-variants of
21672 the arithmetic instructions. Of those instructions, all but six
21673 have the infix appear after the third character of the mnemonic.
21674
21675 Accordingly, the algorithm for looking up primary opcodes given
21676 an identifier is:
21677
21678 1. Look up the identifier in the opcode table.
21679 If we find a match, go to step U.
21680
21681 2. Look up the last two characters of the identifier in the
21682 conditions table. If we find a match, look up the first N-2
21683 characters of the identifier in the opcode table. If we
21684 find a match, go to step CE.
21685
21686 3. Look up the fourth and fifth characters of the identifier in
21687 the conditions table. If we find a match, extract those
21688 characters from the identifier, and look up the remaining
21689 characters in the opcode table. If we find a match, go
21690 to step CM.
21691
21692 4. Fail.
21693
21694 U. Examine the tag field of the opcode structure, in case this is
21695 one of the six instructions with its conditional infix in an
21696 unusual place. If it is, the tag tells us where to find the
21697 infix; look it up in the conditions table and set inst.cond
21698 accordingly. Otherwise, this is an unconditional instruction.
21699 Again set inst.cond accordingly. Return the opcode structure.
21700
21701 CE. Examine the tag field to make sure this is an instruction that
21702 should receive a conditional suffix. If it is not, fail.
21703 Otherwise, set inst.cond from the suffix we already looked up,
21704 and return the opcode structure.
21705
21706 CM. Examine the tag field to make sure this is an instruction that
21707 should receive a conditional infix after the third character.
21708 If it is not, fail. Otherwise, undo the edits to the current
21709 line of input and proceed as for case CE. */
21710
21711static const struct asm_opcode *
21712opcode_lookup (char **str)
21713{
21714 char *end, *base;
21715 char *affix;
21716 const struct asm_opcode *opcode;
21717 const struct asm_cond *cond;
e3cb604e 21718 char save[2];
c19d1205
ZW		 21719
21720 /* Scan up to the end of the mnemonic, which must end in white space,
721a8186 21721 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
c19d1205 21722 for (base = end = *str; *end != '\0'; end++)
721a8186 21723 if (*end == ' ' || *end == '.')
c19d1205 21724 break;
b99bd4ef 21725
c19d1205 21726 if (end == base)
c921be7d 21727 return NULL;
b99bd4ef 21728
5287ad62 21729 /* Handle a possible width suffix and/or Neon type suffix. */
c19d1205 21730 if (end[0] == '.')
b99bd4ef 21731 {
5287ad62 21732 int offset = 2;
5f4273c7 21733
267d2029 21734 /* The .w and .n suffixes are only valid if the unified syntax is in
477330fc 21735 use. */
267d2029 21736 if (unified_syntax && end[1] == 'w')
c19d1205 21737 inst.size_req = 4;
267d2029 21738 else if (unified_syntax && end[1] == 'n')
c19d1205
ZW		 21739 inst.size_req = 2;
21740 else
477330fc 21741 offset = 0;
5287ad62
JB		 21742
21743 inst.vectype.elems = 0;
21744
21745 *str = end + offset;
b99bd4ef 21746
5f4273c7 21747 if (end[offset] == '.')
5287ad62 21748 {
267d2029 21749 /* See if we have a Neon type suffix (possible in either unified or
477330fc
RM		 21750 non-unified ARM syntax mode). */
21751 if (parse_neon_type (&inst.vectype, str) == FAIL)
c921be7d 21752 return NULL;
477330fc 21753 }
5287ad62 21754 else if (end[offset] != '\0' && end[offset] != ' ')
477330fc 21755 return NULL;
b99bd4ef 21756 }
c19d1205
ZW		 21757 else
21758 *str = end;
b99bd4ef 21759
c19d1205 21760 /* Look for unaffixed or special-case affixed mnemonic. */
21d799b5 21761 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 21762 end - base);
c19d1205 21763 if (opcode)
b99bd4ef 21764 {
c19d1205
ZW		 21765 /* step U */
21766 if (opcode->tag < OT_odd_infix_0)
b99bd4ef 21767 {
c19d1205
ZW		 21768 inst.cond = COND_ALWAYS;
21769 return opcode;
b99bd4ef 21770 }
b99bd4ef 21771
278df34e 21772 if (warn_on_deprecated && unified_syntax)
5c3696f8 21773 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205 21774 affix = base + (opcode->tag - OT_odd_infix_0);
21d799b5 21775 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
9c2799c2 21776 gas_assert (cond);
b99bd4ef 21777
c19d1205
ZW		 21778 inst.cond = cond->value;
21779 return opcode;
21780 }
5ee91343
AV		 21781 if (ARM_CPU_HAS_FEATURE (cpu_variant, mve_ext))
21782 {
21783 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21784 */
21785 if (end - base < 2)
21786 return NULL;
21787 affix = end - 1;
21788 cond = (const struct asm_cond *) hash_find_n (arm_vcond_hsh, affix, 1);
21789 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21790 affix - base);
21791 /* If this opcode can not be vector predicated then don't accept it with a
21792 vector predication code. */
21793 if (opcode && !opcode->mayBeVecPred)
21794 opcode = NULL;
21795 }
21796 if (!opcode || !cond)
21797 {
21798 /* Cannot have a conditional suffix on a mnemonic of less than two
21799 characters. */
21800 if (end - base < 3)
21801 return NULL;
b99bd4ef 21802
5ee91343
AV		 21803 /* Look for suffixed mnemonic. */
21804 affix = end - 2;
21805 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
21806 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
21807 affix - base);
21808 }
b99bd4ef 21809
c19d1205
ZW		 21810 if (opcode && cond)
21811 {
21812 /* step CE */
21813 switch (opcode->tag)
21814 {
e3cb604e
PB		 21815 case OT_cinfix3_legacy:
21816 /* Ignore conditional suffixes matched on infix only mnemonics. */
21817 break;
21818
c19d1205 21819 case OT_cinfix3:
088fa78e 21820 case OT_cinfix3_deprecated:
c19d1205
ZW		 21821 case OT_odd_infix_unc:
21822 if (!unified_syntax)
0198d5e6 21823 return NULL;
1a0670f3 21824 /* Fall through. */
c19d1205
ZW		 21825
21826 case OT_csuffix:
477330fc 21827 case OT_csuffixF:
c19d1205
ZW		 21828 case OT_csuf_or_in3:
21829 inst.cond = cond->value;
21830 return opcode;
21831
21832 case OT_unconditional:
21833 case OT_unconditionalF:
dfa9f0d5 21834 if (thumb_mode)
c921be7d 21835 inst.cond = cond->value;
dfa9f0d5
PB		 21836 else
21837 {
c921be7d 21838 /* Delayed diagnostic. */
dfa9f0d5
PB		 21839 inst.error = BAD_COND;
21840 inst.cond = COND_ALWAYS;
21841 }
c19d1205 21842 return opcode;
b99bd4ef 21843
c19d1205 21844 default:
c921be7d 21845 return NULL;
c19d1205
ZW		 21846 }
21847 }
b99bd4ef 21848
c19d1205
ZW		 21849 /* Cannot have a usual-position infix on a mnemonic of less than
21850 six characters (five would be a suffix). */
21851 if (end - base < 6)
c921be7d 21852 return NULL;
b99bd4ef 21853
c19d1205
ZW		 21854 /* Look for infixed mnemonic in the usual position. */
21855 affix = base + 3;
21d799b5 21856 cond = (const struct asm_cond *) hash_find_n (arm_cond_hsh, affix, 2);
e3cb604e 21857 if (!cond)
c921be7d 21858 return NULL;
e3cb604e
PB		 21859
21860 memcpy (save, affix, 2);
21861 memmove (affix, affix + 2, (end - affix) - 2);
21d799b5 21862 opcode = (const struct asm_opcode *) hash_find_n (arm_ops_hsh, base,
477330fc 21863 (end - base) - 2);
e3cb604e
PB		 21864 memmove (affix + 2, affix, (end - affix) - 2);
21865 memcpy (affix, save, 2);
21866
088fa78e
KH		 21867 if (opcode
21868 && (opcode->tag == OT_cinfix3
21869 || opcode->tag == OT_cinfix3_deprecated
21870 || opcode->tag == OT_csuf_or_in3
21871 || opcode->tag == OT_cinfix3_legacy))
b99bd4ef 21872 {
c921be7d 21873 /* Step CM. */
278df34e 21874 if (warn_on_deprecated && unified_syntax
088fa78e
KH		 21875 && (opcode->tag == OT_cinfix3
21876 || opcode->tag == OT_cinfix3_deprecated))
5c3696f8 21877 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
c19d1205
ZW		 21878
21879 inst.cond = cond->value;
21880 return opcode;
b99bd4ef
NC		 21881 }
21882
c921be7d 21883 return NULL;
b99bd4ef
NC		 21884}
21885
e07e6e58
NC		 21886/* This function generates an initial IT instruction, leaving its block
21887 virtually open for the new instructions. Eventually,
5ee91343 21888 the mask will be updated by now_pred_add_mask () each time
e07e6e58
NC		 21889 a new instruction needs to be included in the IT block.
21890 Finally, the block is closed with close_automatic_it_block ().
21891 The block closure can be requested either from md_assemble (),
21892 a tencode (), or due to a label hook. */
21893
21894static void
21895new_automatic_it_block (int cond)
21896{
5ee91343
AV		 21897 now_pred.state = AUTOMATIC_PRED_BLOCK;
21898 now_pred.mask = 0x18;
21899 now_pred.cc = cond;
21900 now_pred.block_length = 1;
cd000bff 21901 mapping_state (MAP_THUMB);
5ee91343
AV		 21902 now_pred.insn = output_it_inst (cond, now_pred.mask, NULL);
21903 now_pred.warn_deprecated = FALSE;
21904 now_pred.insn_cond = TRUE;
e07e6e58
NC		 21905}
21906
21907/* Close an automatic IT block.
21908 See comments in new_automatic_it_block (). */
21909
21910static void
21911close_automatic_it_block (void)
21912{
5ee91343
AV		 21913 now_pred.mask = 0x10;
21914 now_pred.block_length = 0;
e07e6e58
NC		 21915}
21916
21917/* Update the mask of the current automatically-generated IT
21918 instruction. See comments in new_automatic_it_block (). */
21919
21920static void
5ee91343 21921now_pred_add_mask (int cond)
e07e6e58
NC		 21922{
21923#define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21924#define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
477330fc 21925 | ((bitvalue) << (nbit)))
e07e6e58 21926 const int resulting_bit = (cond & 1);
c921be7d 21927
5ee91343
AV		 21928 now_pred.mask &= 0xf;
21929 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 21930 resulting_bit,
5ee91343
AV		 21931 (5 - now_pred.block_length));
21932 now_pred.mask = SET_BIT_VALUE (now_pred.mask,
477330fc 21933 1,
5ee91343
AV		 21934 ((5 - now_pred.block_length) - 1));
21935 output_it_inst (now_pred.cc, now_pred.mask, now_pred.insn);
e07e6e58
NC		 21936
21937#undef CLEAR_BIT
21938#undef SET_BIT_VALUE
e07e6e58
NC		 21939}
21940
21941/* The IT blocks handling machinery is accessed through the these functions:
21942 it_fsm_pre_encode () from md_assemble ()
5ee91343
AV		 21943 set_pred_insn_type () optional, from the tencode functions
21944 set_pred_insn_type_last () ditto
21945 in_pred_block () ditto
e07e6e58 21946 it_fsm_post_encode () from md_assemble ()
33eaf5de 21947 force_automatic_it_block_close () from label handling functions
e07e6e58
NC		 21948
21949 Rationale:
21950 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
477330fc
RM		 21951 initializing the IT insn type with a generic initial value depending
21952 on the inst.condition.
e07e6e58 21953 2) During the tencode function, two things may happen:
477330fc 21954 a) The tencode function overrides the IT insn type by
5ee91343
AV		 21955 calling either set_pred_insn_type (type) or
21956 set_pred_insn_type_last ().
477330fc 21957 b) The tencode function queries the IT block state by
5ee91343 21958 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
477330fc 21959
5ee91343
AV		 21960 Both set_pred_insn_type and in_pred_block run the internal FSM state
21961 handling function (handle_pred_state), because: a) setting the IT insn
477330fc
RM		 21962 type may incur in an invalid state (exiting the function),
21963 and b) querying the state requires the FSM to be updated.
21964 Specifically we want to avoid creating an IT block for conditional
21965 branches, so it_fsm_pre_encode is actually a guess and we can't
21966 determine whether an IT block is required until the tencode () routine
21967 has decided what type of instruction this actually it.
5ee91343
AV		 21968 Because of this, if set_pred_insn_type and in_pred_block have to be
21969 used, set_pred_insn_type has to be called first.
477330fc 21970
5ee91343
AV		 21971 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21972 that determines the insn IT type depending on the inst.cond code.
477330fc
RM		 21973 When a tencode () routine encodes an instruction that can be
21974 either outside an IT block, or, in the case of being inside, has to be
5ee91343 21975 the last one, set_pred_insn_type_last () will determine the proper
477330fc 21976 IT instruction type based on the inst.cond code. Otherwise,
5ee91343 21977 set_pred_insn_type can be called for overriding that logic or
477330fc
RM		 21978 for covering other cases.
21979
5ee91343
AV		 21980 Calling handle_pred_state () may not transition the IT block state to
21981 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
477330fc 21982 still queried. Instead, if the FSM determines that the state should
5ee91343 21983 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
477330fc
RM		 21984 after the tencode () function: that's what it_fsm_post_encode () does.
21985
5ee91343 21986 Since in_pred_block () calls the state handling function to get an
477330fc
RM		 21987 updated state, an error may occur (due to invalid insns combination).
21988 In that case, inst.error is set.
21989 Therefore, inst.error has to be checked after the execution of
21990 the tencode () routine.
e07e6e58
NC		 21991
21992 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
477330fc 21993 any pending state change (if any) that didn't take place in
5ee91343 21994 handle_pred_state () as explained above. */
e07e6e58
NC		 21995
21996static void
21997it_fsm_pre_encode (void)
21998{
21999 if (inst.cond != COND_ALWAYS)
5ee91343 22000 inst.pred_insn_type = INSIDE_IT_INSN;
e07e6e58 22001 else
5ee91343 22002 inst.pred_insn_type = OUTSIDE_PRED_INSN;
e07e6e58 22003
5ee91343 22004 now_pred.state_handled = 0;
e07e6e58
NC		 22005}
22006
22007/* IT state FSM handling function. */
5ee91343
AV		 22008/* MVE instructions and non-MVE instructions are handled differently because of
22009 the introduction of VPT blocks.
22010 Specifications say that any non-MVE instruction inside a VPT block is
22011 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22012 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
35c228db 22013 few exceptions we have MVE_UNPREDICABLE_INSN.
5ee91343
AV		 22014 The error messages provided depending on the different combinations possible
22015 are described in the cases below:
22016 For 'most' MVE instructions:
22017 1) In an IT block, with an IT code: syntax error
22018 2) In an IT block, with a VPT code: error: must be in a VPT block
22019 3) In an IT block, with no code: warning: UNPREDICTABLE
22020 4) In a VPT block, with an IT code: syntax error
22021 5) In a VPT block, with a VPT code: OK!
22022 6) In a VPT block, with no code: error: missing code
22023 7) Outside a pred block, with an IT code: error: syntax error
22024 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22025 9) Outside a pred block, with no code: OK!
22026 For non-MVE instructions:
22027 10) In an IT block, with an IT code: OK!
22028 11) In an IT block, with a VPT code: syntax error
22029 12) In an IT block, with no code: error: missing code
22030 13) In a VPT block, with an IT code: error: should be in an IT block
22031 14) In a VPT block, with a VPT code: syntax error
22032 15) In a VPT block, with no code: UNPREDICTABLE
22033 16) Outside a pred block, with an IT code: error: should be in an IT block
22034 17) Outside a pred block, with a VPT code: syntax error
22035 18) Outside a pred block, with no code: OK!
22036 */
22037
e07e6e58
NC		 22038
22039static int
5ee91343 22040handle_pred_state (void)
e07e6e58 22041{
5ee91343
AV		 22042 now_pred.state_handled = 1;
22043 now_pred.insn_cond = FALSE;
e07e6e58 22044
5ee91343 22045 switch (now_pred.state)
e07e6e58 22046 {
5ee91343
AV		 22047 case OUTSIDE_PRED_BLOCK:
22048 switch (inst.pred_insn_type)
e07e6e58 22049 {
35c228db 22050 case MVE_UNPREDICABLE_INSN:
5ee91343
AV		 22051 case MVE_OUTSIDE_PRED_INSN:
22052 if (inst.cond < COND_ALWAYS)
22053 {
22054 /* Case 7: Outside a pred block, with an IT code: error: syntax
22055 error. */
22056 inst.error = BAD_SYNTAX;
22057 return FAIL;
22058 }
22059 /* Case 9: Outside a pred block, with no code: OK! */
22060 break;
22061 case OUTSIDE_PRED_INSN:
22062 if (inst.cond > COND_ALWAYS)
22063 {
22064 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22065 */
22066 inst.error = BAD_SYNTAX;
22067 return FAIL;
22068 }
22069 /* Case 18: Outside a pred block, with no code: OK! */
e07e6e58
NC		 22070 break;
22071
5ee91343
AV		 22072 case INSIDE_VPT_INSN:
22073 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22074 a VPT block. */
22075 inst.error = BAD_OUT_VPT;
22076 return FAIL;
22077
e07e6e58
NC		 22078 case INSIDE_IT_INSN:
22079 case INSIDE_IT_LAST_INSN:
5ee91343 22080 if (inst.cond < COND_ALWAYS)
e07e6e58 22081 {
5ee91343
AV		 22082 /* Case 16: Outside a pred block, with an IT code: error: should
22083 be in an IT block. */
22084 if (thumb_mode == 0)
e07e6e58 22085 {
5ee91343
AV		 22086 if (unified_syntax
22087 && !(implicit_it_mode & IMPLICIT_IT_MODE_ARM))
22088 as_tsktsk (_("Warning: conditional outside an IT block"\
22089 " for Thumb."));
e07e6e58
NC		 22090 }
22091 else
22092 {
5ee91343
AV		 22093 if ((implicit_it_mode & IMPLICIT_IT_MODE_THUMB)
22094 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
22095 {
22096 /* Automatically generate the IT instruction. */
22097 new_automatic_it_block (inst.cond);
22098 if (inst.pred_insn_type == INSIDE_IT_LAST_INSN)
22099 close_automatic_it_block ();
22100 }
22101 else
22102 {
22103 inst.error = BAD_OUT_IT;
22104 return FAIL;
22105 }
e07e6e58 22106 }
5ee91343 22107 break;
e07e6e58 22108 }
5ee91343
AV		 22109 else if (inst.cond > COND_ALWAYS)
22110 {
22111 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22112 */
22113 inst.error = BAD_SYNTAX;
22114 return FAIL;
22115 }
22116 else
22117 gas_assert (0);
e07e6e58
NC		 22118 case IF_INSIDE_IT_LAST_INSN:
22119 case NEUTRAL_IT_INSN:
22120 break;
22121
5ee91343
AV		 22122 case VPT_INSN:
22123 if (inst.cond != COND_ALWAYS)
22124 first_error (BAD_SYNTAX);
22125 now_pred.state = MANUAL_PRED_BLOCK;
22126 now_pred.block_length = 0;
22127 now_pred.type = VECTOR_PRED;
22128 now_pred.cc = 0;
22129 break;
e07e6e58 22130 case IT_INSN:
5ee91343
AV		 22131 now_pred.state = MANUAL_PRED_BLOCK;
22132 now_pred.block_length = 0;
22133 now_pred.type = SCALAR_PRED;
e07e6e58
NC		 22134 break;
22135 }
22136 break;
22137
5ee91343 22138 case AUTOMATIC_PRED_BLOCK:
e07e6e58
NC		 22139 /* Three things may happen now:
22140 a) We should increment current it block size;
22141 b) We should close current it block (closing insn or 4 insns);
22142 c) We should close current it block and start a new one (due
22143 to incompatible conditions or
22144 4 insns-length block reached). */
22145
5ee91343 22146 switch (inst.pred_insn_type)
e07e6e58 22147 {
5ee91343
AV		 22148 case INSIDE_VPT_INSN:
22149 case VPT_INSN:
35c228db 22150 case MVE_UNPREDICABLE_INSN:
5ee91343
AV		 22151 case MVE_OUTSIDE_PRED_INSN:
22152 gas_assert (0);
22153 case OUTSIDE_PRED_INSN:
2b0f3761 22154 /* The closure of the block shall happen immediately,
5ee91343 22155 so any in_pred_block () call reports the block as closed. */
e07e6e58
NC		 22156 force_automatic_it_block_close ();
22157 break;
22158
22159 case INSIDE_IT_INSN:
22160 case INSIDE_IT_LAST_INSN:
22161 case IF_INSIDE_IT_LAST_INSN:
5ee91343 22162 now_pred.block_length++;
e07e6e58 22163
5ee91343
AV		 22164 if (now_pred.block_length > 4
22165 || !now_pred_compatible (inst.cond))
e07e6e58
NC		 22166 {
22167 force_automatic_it_block_close ();
5ee91343 22168 if (inst.pred_insn_type != IF_INSIDE_IT_LAST_INSN)
e07e6e58
NC		 22169 new_automatic_it_block (inst.cond);
22170 }
22171 else
22172 {
5ee91343
AV		 22173 now_pred.insn_cond = TRUE;
22174 now_pred_add_mask (inst.cond);
e07e6e58
NC		 22175 }
22176
5ee91343
AV		 22177 if (now_pred.state == AUTOMATIC_PRED_BLOCK
22178 && (inst.pred_insn_type == INSIDE_IT_LAST_INSN
22179 || inst.pred_insn_type == IF_INSIDE_IT_LAST_INSN))
e07e6e58
NC		 22180 close_automatic_it_block ();
22181 break;
22182
22183 case NEUTRAL_IT_INSN:
5ee91343
AV		 22184 now_pred.block_length++;
22185 now_pred.insn_cond = TRUE;
e07e6e58 22186
5ee91343 22187 if (now_pred.block_length > 4)
e07e6e58
NC		 22188 force_automatic_it_block_close ();
22189 else
5ee91343 22190 now_pred_add_mask (now_pred.cc & 1);
e07e6e58
NC		 22191 break;
22192
22193 case IT_INSN:
22194 close_automatic_it_block ();
5ee91343 22195 now_pred.state = MANUAL_PRED_BLOCK;
e07e6e58
NC		 22196 break;
22197 }
22198 break;
22199
5ee91343 22200 case MANUAL_PRED_BLOCK:
e07e6e58 22201 {
5ee91343
AV		 22202 int cond, is_last;
22203 if (now_pred.type == SCALAR_PRED)
e07e6e58 22204 {
5ee91343
AV		 22205 /* Check conditional suffixes. */
22206 cond = now_pred.cc ^ ((now_pred.mask >> 4) & 1) ^ 1;
22207 now_pred.mask <<= 1;
22208 now_pred.mask &= 0x1f;
22209 is_last = (now_pred.mask == 0x10);
22210 }
22211 else
22212 {
22213 now_pred.cc ^= (now_pred.mask >> 4);
22214 cond = now_pred.cc + 0xf;
22215 now_pred.mask <<= 1;
22216 now_pred.mask &= 0x1f;
22217 is_last = now_pred.mask == 0x10;
22218 }
22219 now_pred.insn_cond = TRUE;
e07e6e58 22220
5ee91343
AV		 22221 switch (inst.pred_insn_type)
22222 {
22223 case OUTSIDE_PRED_INSN:
22224 if (now_pred.type == SCALAR_PRED)
22225 {
22226 if (inst.cond == COND_ALWAYS)
22227 {
22228 /* Case 12: In an IT block, with no code: error: missing
22229 code. */
22230 inst.error = BAD_NOT_IT;
22231 return FAIL;
22232 }
22233 else if (inst.cond > COND_ALWAYS)
22234 {
22235 /* Case 11: In an IT block, with a VPT code: syntax error.
22236 */
22237 inst.error = BAD_SYNTAX;
22238 return FAIL;
22239 }
22240 else if (thumb_mode)
22241 {
22242 /* This is for some special cases where a non-MVE
22243 instruction is not allowed in an IT block, such as cbz,
22244 but are put into one with a condition code.
22245 You could argue this should be a syntax error, but we
22246 gave the 'not allowed in IT block' diagnostic in the
22247 past so we will keep doing so. */
22248 inst.error = BAD_NOT_IT;
22249 return FAIL;
22250 }
22251 break;
22252 }
22253 else
22254 {
22255 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22256 as_tsktsk (MVE_NOT_VPT);
22257 return SUCCESS;
22258 }
22259 case MVE_OUTSIDE_PRED_INSN:
22260 if (now_pred.type == SCALAR_PRED)
22261 {
22262 if (inst.cond == COND_ALWAYS)
22263 {
22264 /* Case 3: In an IT block, with no code: warning:
22265 UNPREDICTABLE. */
22266 as_tsktsk (MVE_NOT_IT);
22267 return SUCCESS;
22268 }
22269 else if (inst.cond < COND_ALWAYS)
22270 {
22271 /* Case 1: In an IT block, with an IT code: syntax error.
22272 */
22273 inst.error = BAD_SYNTAX;
22274 return FAIL;
22275 }
22276 else
22277 gas_assert (0);
22278 }
22279 else
22280 {
22281 if (inst.cond < COND_ALWAYS)
22282 {
22283 /* Case 4: In a VPT block, with an IT code: syntax error.
22284 */
22285 inst.error = BAD_SYNTAX;
22286 return FAIL;
22287 }
22288 else if (inst.cond == COND_ALWAYS)
22289 {
22290 /* Case 6: In a VPT block, with no code: error: missing
22291 code. */
22292 inst.error = BAD_NOT_VPT;
22293 return FAIL;
22294 }
22295 else
22296 {
22297 gas_assert (0);
22298 }
22299 }
35c228db
AV		 22300 case MVE_UNPREDICABLE_INSN:
22301 as_tsktsk (now_pred.type == SCALAR_PRED ? MVE_NOT_IT : MVE_NOT_VPT);
22302 return SUCCESS;
e07e6e58 22303 case INSIDE_IT_INSN:
5ee91343 22304 if (inst.cond > COND_ALWAYS)
e07e6e58 22305 {
5ee91343
AV		 22306 /* Case 11: In an IT block, with a VPT code: syntax error. */
22307 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22308 inst.error = BAD_SYNTAX;
22309 return FAIL;
22310 }
22311 else if (now_pred.type == SCALAR_PRED)
22312 {
22313 /* Case 10: In an IT block, with an IT code: OK! */
22314 if (cond != inst.cond)
22315 {
22316 inst.error = now_pred.type == SCALAR_PRED ? BAD_IT_COND :
22317 BAD_VPT_COND;
22318 return FAIL;
22319 }
22320 }
22321 else
22322 {
22323 /* Case 13: In a VPT block, with an IT code: error: should be
22324 in an IT block. */
22325 inst.error = BAD_OUT_IT;
e07e6e58
NC		 22326 return FAIL;
22327 }
22328 break;
22329
5ee91343
AV		 22330 case INSIDE_VPT_INSN:
22331 if (now_pred.type == SCALAR_PRED)
22332 {
22333 /* Case 2: In an IT block, with a VPT code: error: must be in a
22334 VPT block. */
22335 inst.error = BAD_OUT_VPT;
22336 return FAIL;
22337 }
22338 /* Case 5: In a VPT block, with a VPT code: OK! */
22339 else if (cond != inst.cond)
22340 {
22341 inst.error = BAD_VPT_COND;
22342 return FAIL;
22343 }
22344 break;
e07e6e58
NC		 22345 case INSIDE_IT_LAST_INSN:
22346 case IF_INSIDE_IT_LAST_INSN:
5ee91343
AV		 22347 if (now_pred.type == VECTOR_PRED || inst.cond > COND_ALWAYS)
22348 {
22349 /* Case 4: In a VPT block, with an IT code: syntax error. */
22350 /* Case 11: In an IT block, with a VPT code: syntax error. */
22351 inst.error = BAD_SYNTAX;
22352 return FAIL;
22353 }
22354 else if (cond != inst.cond)
e07e6e58
NC		 22355 {
22356 inst.error = BAD_IT_COND;
22357 return FAIL;
22358 }
22359 if (!is_last)
22360 {
22361 inst.error = BAD_BRANCH;
22362 return FAIL;
22363 }
22364 break;
22365
22366 case NEUTRAL_IT_INSN:
5ee91343
AV		 22367 /* The BKPT instruction is unconditional even in a IT or VPT
22368 block. */
e07e6e58
NC		 22369 break;
22370
22371 case IT_INSN:
5ee91343
AV		 22372 if (now_pred.type == SCALAR_PRED)
22373 {
22374 inst.error = BAD_IT_IT;
22375 return FAIL;
22376 }
22377 /* fall through. */
22378 case VPT_INSN:
22379 if (inst.cond == COND_ALWAYS)
22380 {
22381 /* Executing a VPT/VPST instruction inside an IT block or a
22382 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22383 */
22384 if (now_pred.type == SCALAR_PRED)
22385 as_tsktsk (MVE_NOT_IT);
22386 else
22387 as_tsktsk (MVE_NOT_VPT);
22388 return SUCCESS;
22389 }
22390 else
22391 {
22392 /* VPT/VPST do not accept condition codes. */
22393 inst.error = BAD_SYNTAX;
22394 return FAIL;
22395 }
e07e6e58 22396 }
5ee91343 22397 }
e07e6e58
NC		 22398 break;
22399 }
22400
22401 return SUCCESS;
22402}
22403
5a01bb1d
MGD		 22404struct depr_insn_mask
22405{
22406 unsigned long pattern;
22407 unsigned long mask;
22408 const char* description;
22409};
22410
22411/* List of 16-bit instruction patterns deprecated in an IT block in
22412 ARMv8. */
22413static const struct depr_insn_mask depr_it_insns[] = {
22414 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22415 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22416 { 0xa000, 0xb800, N_("ADR") },
22417 { 0x4800, 0xf800, N_("Literal loads") },
22418 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22419 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
c8de034b
JW		 22420 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22421 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22422 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
5a01bb1d
MGD		 22423 { 0, 0, NULL }
22424};
22425
e07e6e58
NC		 22426static void
22427it_fsm_post_encode (void)
22428{
22429 int is_last;
22430
5ee91343
AV		 22431 if (!now_pred.state_handled)
22432 handle_pred_state ();
e07e6e58 22433
5ee91343
AV		 22434 if (now_pred.insn_cond
22435 && !now_pred.warn_deprecated
5a01bb1d 22436 && warn_on_deprecated
df9909b8
TP		 22437 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)
22438 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m))
5a01bb1d
MGD		 22439 {
22440 if (inst.instruction >= 0x10000)
22441 {
5c3696f8 22442 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
df9909b8 22443 "performance deprecated in ARMv8-A and ARMv8-R"));
5ee91343 22444 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 22445 }
22446 else
22447 {
22448 const struct depr_insn_mask *p = depr_it_insns;
22449
22450 while (p->mask != 0)
22451 {
22452 if ((inst.instruction & p->mask) == p->pattern)
22453 {
df9909b8
TP		 22454 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22455 "instructions of the following class are "
22456 "performance deprecated in ARMv8-A and "
22457 "ARMv8-R: %s"), p->description);
5ee91343 22458 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 22459 break;
22460 }
22461
22462 ++p;
22463 }
22464 }
22465
5ee91343 22466 if (now_pred.block_length > 1)
5a01bb1d 22467 {
5c3696f8 22468 as_tsktsk (_("IT blocks containing more than one conditional "
df9909b8
TP		 22469 "instruction are performance deprecated in ARMv8-A and "
22470 "ARMv8-R"));
5ee91343 22471 now_pred.warn_deprecated = TRUE;
5a01bb1d
MGD		 22472 }
22473 }
22474
5ee91343
AV		 22475 is_last = (now_pred.mask == 0x10);
22476 if (is_last)
22477 {
22478 now_pred.state = OUTSIDE_PRED_BLOCK;
22479 now_pred.mask = 0;
22480 }
e07e6e58
NC		 22481}
22482
22483static void
22484force_automatic_it_block_close (void)
22485{
5ee91343 22486 if (now_pred.state == AUTOMATIC_PRED_BLOCK)
e07e6e58
NC		 22487 {
22488 close_automatic_it_block ();
5ee91343
AV		 22489 now_pred.state = OUTSIDE_PRED_BLOCK;
22490 now_pred.mask = 0;
e07e6e58
NC		 22491 }
22492}
22493
22494static int
5ee91343 22495in_pred_block (void)
e07e6e58 22496{
5ee91343
AV		 22497 if (!now_pred.state_handled)
22498 handle_pred_state ();
e07e6e58 22499
5ee91343 22500 return now_pred.state != OUTSIDE_PRED_BLOCK;
e07e6e58
NC		 22501}
22502
ff8646ee
TP		 22503/* Whether OPCODE only has T32 encoding. Since this function is only used by
22504 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22505 here, hence the "known" in the function name. */
fc289b0a
TP		 22506
22507static bfd_boolean
ff8646ee 22508known_t32_only_insn (const struct asm_opcode *opcode)
fc289b0a
TP		 22509{
22510 /* Original Thumb-1 wide instruction. */
22511 if (opcode->tencode == do_t_blx
22512 || opcode->tencode == do_t_branch23
22513 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_msr)
22514 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
22515 return TRUE;
22516
16a1fa25
TP		 22517 /* Wide-only instruction added to ARMv8-M Baseline. */
22518 if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
ff8646ee
TP		 22519 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
22520 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
22521 || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
22522 return TRUE;
22523
22524 return FALSE;
22525}
22526
22527/* Whether wide instruction variant can be used if available for a valid OPCODE
22528 in ARCH. */
22529
22530static bfd_boolean
22531t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode)
22532{
22533 if (known_t32_only_insn (opcode))
22534 return TRUE;
22535
22536 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22537 of variant T3 of B.W is checked in do_t_branch. */
22538 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22539 && opcode->tencode == do_t_branch)
22540 return TRUE;
22541
bada4342
JW		 22542 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22543 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
22544 && opcode->tencode == do_t_mov_cmp
22545 /* Make sure CMP instruction is not affected. */
22546 && opcode->aencode == do_mov)
22547 return TRUE;
22548
ff8646ee
TP		 22549 /* Wide instruction variants of all instructions with narrow *and* wide
22550 variants become available with ARMv6t2. Other opcodes are either
22551 narrow-only or wide-only and are thus available if OPCODE is valid. */
22552 if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2))
22553 return TRUE;
22554
22555 /* OPCODE with narrow only instruction variant or wide variant not
22556 available. */
fc289b0a
TP		 22557 return FALSE;
22558}
22559
c19d1205
ZW		 22560void
22561md_assemble (char *str)
b99bd4ef 22562{
c19d1205
ZW		 22563 char *p = str;
22564 const struct asm_opcode * opcode;
b99bd4ef 22565
c19d1205
ZW		 22566 /* Align the previous label if needed. */
22567 if (last_label_seen != NULL)
b99bd4ef 22568 {
c19d1205
ZW		 22569 symbol_set_frag (last_label_seen, frag_now);
22570 S_SET_VALUE (last_label_seen, (valueT) frag_now_fix ());
22571 S_SET_SEGMENT (last_label_seen, now_seg);
b99bd4ef
NC		 22572 }
22573
c19d1205 22574 memset (&inst, '\0', sizeof (inst));
e2b0ab59
AV		 22575 int r;
22576 for (r = 0; r < ARM_IT_MAX_RELOCS; r++)
22577 inst.relocs[r].type = BFD_RELOC_UNUSED;
b99bd4ef 22578
c19d1205
ZW		 22579 opcode = opcode_lookup (&p);
22580 if (!opcode)
b99bd4ef 22581 {
c19d1205 22582 /* It wasn't an instruction, but it might be a register alias of
dcbf9037 22583 the form alias .req reg, or a Neon .dn/.qn directive. */
c921be7d 22584 if (! create_register_alias (str, p)
477330fc 22585 && ! create_neon_reg_alias (str, p))
c19d1205 22586 as_bad (_("bad instruction `%s'"), str);
b99bd4ef 22587
b99bd4ef
NC		 22588 return;
22589 }
22590
278df34e 22591 if (warn_on_deprecated && opcode->tag == OT_cinfix3_deprecated)
5c3696f8 22592 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
088fa78e 22593
037e8744
JB		 22594 /* The value which unconditional instructions should have in place of the
22595 condition field. */
22596 inst.uncond_value = (opcode->tag == OT_csuffixF) ? 0xf : -1;
22597
c19d1205 22598 if (thumb_mode)
b99bd4ef 22599 {
e74cfd16 22600 arm_feature_set variant;
8f06b2d8
PB		 22601
22602 variant = cpu_variant;
22603 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
e74cfd16
PB		 22604 if (!ARM_CPU_HAS_FEATURE (variant, arm_arch_t2))
22605 ARM_CLEAR_FEATURE (variant, variant, fpu_any_hard);
c19d1205 22606 /* Check that this instruction is supported for this CPU. */
62b3e311
PB		 22607 if (!opcode->tvariant
22608 || (thumb_mode == 1
22609 && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
b99bd4ef 22610 {
173205ca
TP		 22611 if (opcode->tencode == do_t_swi)
22612 as_bad (_("SVC is not permitted on this architecture"));
22613 else
22614 as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
b99bd4ef
NC		 22615 return;
22616 }
c19d1205
ZW		 22617 if (inst.cond != COND_ALWAYS && !unified_syntax
22618 && opcode->tencode != do_t_branch)
b99bd4ef 22619 {
c19d1205 22620 as_bad (_("Thumb does not support conditional execution"));
b99bd4ef
NC		 22621 return;
22622 }
22623
fc289b0a
TP		 22624 /* Two things are addressed here:
22625 1) Implicit require narrow instructions on Thumb-1.
22626 This avoids relaxation accidentally introducing Thumb-2
22627 instructions.
22628 2) Reject wide instructions in non Thumb-2 cores.
22629
22630 Only instructions with narrow and wide variants need to be handled
22631 but selecting all non wide-only instructions is easier. */
22632 if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2)
ff8646ee 22633 && !t32_insn_ok (variant, opcode))
076d447c 22634 {
fc289b0a
TP		 22635 if (inst.size_req == 0)
22636 inst.size_req = 2;
22637 else if (inst.size_req == 4)
752d5da4 22638 {
ff8646ee
TP		 22639 if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m))
22640 as_bad (_("selected processor does not support 32bit wide "
22641 "variant of instruction `%s'"), str);
22642 else
22643 as_bad (_("selected processor does not support `%s' in "
22644 "Thumb-2 mode"), str);
fc289b0a 22645 return;
752d5da4 22646 }
076d447c
PB		 22647 }
22648
c19d1205
ZW		 22649 inst.instruction = opcode->tvalue;
22650
5be8be5d 22651 if (!parse_operands (p, opcode->operands, /*thumb=*/TRUE))
477330fc 22652 {
5ee91343 22653 /* Prepare the pred_insn_type for those encodings that don't set
477330fc
RM		 22654 it. */
22655 it_fsm_pre_encode ();
c19d1205 22656
477330fc 22657 opcode->tencode ();
e07e6e58 22658
477330fc
RM		 22659 it_fsm_post_encode ();
22660 }
e27ec89e 22661
0110f2b8 22662 if (!(inst.error || inst.relax))
b99bd4ef 22663 {
9c2799c2 22664 gas_assert (inst.instruction < 0xe800 || inst.instruction > 0xffff);
c19d1205
ZW		 22665 inst.size = (inst.instruction > 0xffff ? 4 : 2);
22666 if (inst.size_req && inst.size_req != inst.size)
b99bd4ef 22667 {
c19d1205 22668 as_bad (_("cannot honor width suffix -- `%s'"), str);
b99bd4ef
NC		 22669 return;
22670 }
22671 }
076d447c
PB		 22672
22673 /* Something has gone badly wrong if we try to relax a fixed size
477330fc 22674 instruction. */
9c2799c2 22675 gas_assert (inst.size_req == 0 || !inst.relax);
076d447c 22676
e74cfd16
PB		 22677 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22678 *opcode->tvariant);
ee065d83 22679 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
fc289b0a
TP		 22680 set those bits when Thumb-2 32-bit instructions are seen. The impact
22681 of relaxable instructions will be considered later after we finish all
22682 relaxation. */
ff8646ee
TP		 22683 if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any))
22684 variant = arm_arch_none;
22685 else
22686 variant = cpu_variant;
22687 if (inst.size == 4 && !t32_insn_ok (variant, opcode))
e74cfd16
PB		 22688 ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
22689 arm_ext_v6t2);
cd000bff 22690
88714cb8
DG		 22691 check_neon_suffixes;
22692
cd000bff 22693 if (!inst.error)
c877a2f2
NC		 22694 {
22695 mapping_state (MAP_THUMB);
22696 }
c19d1205 22697 }
3e9e4fcf 22698 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
c19d1205 22699 {
845b51d6
PB		 22700 bfd_boolean is_bx;
22701
22702 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22703 is_bx = (opcode->aencode == do_bx);
22704
c19d1205 22705 /* Check that this instruction is supported for this CPU. */
845b51d6
PB		 22706 if (!(is_bx && fix_v4bx)
22707 && !(opcode->avariant &&
22708 ARM_CPU_HAS_FEATURE (cpu_variant, *opcode->avariant)))
b99bd4ef 22709 {
84b52b66 22710 as_bad (_("selected processor does not support `%s' in ARM mode"), str);
c19d1205 22711 return;
b99bd4ef 22712 }
c19d1205 22713 if (inst.size_req)
b99bd4ef 22714 {
c19d1205
ZW		 22715 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str);
22716 return;
b99bd4ef
NC		 22717 }
22718
c19d1205
ZW		 22719 inst.instruction = opcode->avalue;
22720 if (opcode->tag == OT_unconditionalF)
eff0bc54 22721 inst.instruction |= 0xFU << 28;
c19d1205
ZW		 22722 else
22723 inst.instruction |= inst.cond << 28;
22724 inst.size = INSN_SIZE;
5be8be5d 22725 if (!parse_operands (p, opcode->operands, /*thumb=*/FALSE))
477330fc
RM		 22726 {
22727 it_fsm_pre_encode ();
22728 opcode->aencode ();
22729 it_fsm_post_encode ();
22730 }
ee065d83 22731 /* Arm mode bx is marked as both v4T and v5 because it's still required
477330fc 22732 on a hypothetical non-thumb v5 core. */
845b51d6 22733 if (is_bx)
e74cfd16 22734 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used, arm_ext_v4t);
ee065d83 22735 else
e74cfd16
PB		 22736 ARM_MERGE_FEATURE_SETS (arm_arch_used, arm_arch_used,
22737 *opcode->avariant);
88714cb8
DG		 22738
22739 check_neon_suffixes;
22740
cd000bff 22741 if (!inst.error)
c877a2f2
NC		 22742 {
22743 mapping_state (MAP_ARM);
22744 }
b99bd4ef 22745 }
3e9e4fcf
JB		 22746 else
22747 {
22748 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22749 "-- `%s'"), str);
22750 return;
22751 }
c19d1205
ZW		 22752 output_inst (str);
22753}
b99bd4ef 22754
e07e6e58 22755static void
5ee91343 22756check_pred_blocks_finished (void)
e07e6e58
NC		 22757{
22758#ifdef OBJ_ELF
22759 asection *sect;
22760
22761 for (sect = stdoutput->sections; sect != NULL; sect = sect->next)
5ee91343
AV		 22762 if (seg_info (sect)->tc_segment_info_data.current_pred.state
22763 == MANUAL_PRED_BLOCK)
e07e6e58 22764 {
5ee91343
AV		 22765 if (now_pred.type == SCALAR_PRED)
22766 as_warn (_("section '%s' finished with an open IT block."),
22767 sect->name);
22768 else
22769 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22770 sect->name);
e07e6e58
NC		 22771 }
22772#else
5ee91343
AV		 22773 if (now_pred.state == MANUAL_PRED_BLOCK)
22774 {
22775 if (now_pred.type == SCALAR_PRED)
22776 as_warn (_("file finished with an open IT block."));
22777 else
22778 as_warn (_("file finished with an open VPT/VPST block."));
22779 }
e07e6e58
NC		 22780#endif
22781}
22782
c19d1205
ZW		 22783/* Various frobbings of labels and their addresses. */
22784
22785void
22786arm_start_line_hook (void)
22787{
22788 last_label_seen = NULL;
b99bd4ef
NC		 22789}
22790
c19d1205
ZW		 22791void
22792arm_frob_label (symbolS * sym)
b99bd4ef 22793{
c19d1205 22794 last_label_seen = sym;
b99bd4ef 22795
c19d1205 22796 ARM_SET_THUMB (sym, thumb_mode);
b99bd4ef 22797
c19d1205
ZW		 22798#if defined OBJ_COFF || defined OBJ_ELF
22799 ARM_SET_INTERWORK (sym, support_interwork);
22800#endif
b99bd4ef 22801
e07e6e58
NC		 22802 force_automatic_it_block_close ();
22803
5f4273c7 22804 /* Note - do not allow local symbols (.Lxxx) to be labelled
c19d1205
ZW		 22805 as Thumb functions. This is because these labels, whilst
22806 they exist inside Thumb code, are not the entry points for
22807 possible ARM->Thumb calls. Also, these labels can be used
22808 as part of a computed goto or switch statement. eg gcc
22809 can generate code that looks like this:
b99bd4ef 22810
c19d1205
ZW		 22811 ldr r2, [pc, .Laaa]
22812 lsl r3, r3, #2
22813 ldr r2, [r3, r2]
22814 mov pc, r2
b99bd4ef 22815
c19d1205
ZW		 22816 .Lbbb: .word .Lxxx
22817 .Lccc: .word .Lyyy
22818 ..etc...
22819 .Laaa: .word Lbbb
b99bd4ef 22820
c19d1205
ZW		 22821 The first instruction loads the address of the jump table.
22822 The second instruction converts a table index into a byte offset.
22823 The third instruction gets the jump address out of the table.
22824 The fourth instruction performs the jump.
b99bd4ef 22825
c19d1205
ZW		 22826 If the address stored at .Laaa is that of a symbol which has the
22827 Thumb_Func bit set, then the linker will arrange for this address
22828 to have the bottom bit set, which in turn would mean that the
22829 address computation performed by the third instruction would end
22830 up with the bottom bit set. Since the ARM is capable of unaligned
22831 word loads, the instruction would then load the incorrect address
22832 out of the jump table, and chaos would ensue. */
22833 if (label_is_thumb_function_name
22834 && (S_GET_NAME (sym)[0] != '.' || S_GET_NAME (sym)[1] != 'L')
22835 && (bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) != 0)
b99bd4ef 22836 {
c19d1205
ZW		 22837 /* When the address of a Thumb function is taken the bottom
22838 bit of that address should be set. This will allow
22839 interworking between Arm and Thumb functions to work
22840 correctly. */
b99bd4ef 22841
c19d1205 22842 THUMB_SET_FUNC (sym, 1);
b99bd4ef 22843
c19d1205 22844 label_is_thumb_function_name = FALSE;
b99bd4ef 22845 }
07a53e5c 22846
07a53e5c 22847 dwarf2_emit_label (sym);
b99bd4ef
NC		 22848}
22849
c921be7d 22850bfd_boolean
c19d1205 22851arm_data_in_code (void)
b99bd4ef 22852{
c19d1205 22853 if (thumb_mode && ! strncmp (input_line_pointer + 1, "data:", 5))
b99bd4ef 22854 {
c19d1205
ZW		 22855 *input_line_pointer = '/';
22856 input_line_pointer += 5;
22857 *input_line_pointer = 0;
c921be7d 22858 return TRUE;
b99bd4ef
NC		 22859 }
22860
c921be7d 22861 return FALSE;
b99bd4ef
NC		 22862}
22863
c19d1205
ZW		 22864char *
22865arm_canonicalize_symbol_name (char * name)
b99bd4ef 22866{
c19d1205 22867 int len;
b99bd4ef 22868
c19d1205
ZW		 22869 if (thumb_mode && (len = strlen (name)) > 5
22870 && streq (name + len - 5, "/data"))
22871 *(name + len - 5) = 0;
b99bd4ef 22872
c19d1205 22873 return name;
b99bd4ef 22874}
c19d1205
ZW		 22875\f
22876/* Table of all register names defined by default. The user can
22877 define additional names with .req. Note that all register names
22878 should appear in both upper and lowercase variants. Some registers
22879 also have mixed-case names. */
b99bd4ef 22880
dcbf9037 22881#define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
c19d1205 22882#define REGNUM(p,n,t) REGDEF(p##n, n, t)
5287ad62 22883#define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
c19d1205
ZW		 22884#define REGSET(p,t) \
22885 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22886 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22887 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22888 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
5287ad62
JB		 22889#define REGSETH(p,t) \
22890 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22891 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22892 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22893 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22894#define REGSET2(p,t) \
22895 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22896 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22897 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22898 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
90ec0d68
MGD		 22899#define SPLRBANK(base,bank,t) \
22900 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22901 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22902 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22903 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22904 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22905 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
7ed4c4c5 22906
c19d1205 22907static const struct reg_entry reg_names[] =
7ed4c4c5 22908{
c19d1205
ZW		 22909 /* ARM integer registers. */
22910 REGSET(r, RN), REGSET(R, RN),
7ed4c4c5 22911
c19d1205
ZW		 22912 /* ATPCS synonyms. */
22913 REGDEF(a1,0,RN), REGDEF(a2,1,RN), REGDEF(a3, 2,RN), REGDEF(a4, 3,RN),
22914 REGDEF(v1,4,RN), REGDEF(v2,5,RN), REGDEF(v3, 6,RN), REGDEF(v4, 7,RN),
22915 REGDEF(v5,8,RN), REGDEF(v6,9,RN), REGDEF(v7,10,RN), REGDEF(v8,11,RN),
7ed4c4c5 22916
c19d1205
ZW		 22917 REGDEF(A1,0,RN), REGDEF(A2,1,RN), REGDEF(A3, 2,RN), REGDEF(A4, 3,RN),
22918 REGDEF(V1,4,RN), REGDEF(V2,5,RN), REGDEF(V3, 6,RN), REGDEF(V4, 7,RN),
22919 REGDEF(V5,8,RN), REGDEF(V6,9,RN), REGDEF(V7,10,RN), REGDEF(V8,11,RN),
7ed4c4c5 22920
c19d1205
ZW		 22921 /* Well-known aliases. */
22922 REGDEF(wr, 7,RN), REGDEF(sb, 9,RN), REGDEF(sl,10,RN), REGDEF(fp,11,RN),
22923 REGDEF(ip,12,RN), REGDEF(sp,13,RN), REGDEF(lr,14,RN), REGDEF(pc,15,RN),
22924
22925 REGDEF(WR, 7,RN), REGDEF(SB, 9,RN), REGDEF(SL,10,RN), REGDEF(FP,11,RN),
22926 REGDEF(IP,12,RN), REGDEF(SP,13,RN), REGDEF(LR,14,RN), REGDEF(PC,15,RN),
22927
1b883319
AV		 22928 /* Defining the new Zero register from ARMv8.1-M. */
22929 REGDEF(zr,15,ZR),
22930 REGDEF(ZR,15,ZR),
22931
c19d1205
ZW		 22932 /* Coprocessor numbers. */
22933 REGSET(p, CP), REGSET(P, CP),
22934
22935 /* Coprocessor register numbers. The "cr" variants are for backward
22936 compatibility. */
22937 REGSET(c, CN), REGSET(C, CN),
22938 REGSET(cr, CN), REGSET(CR, CN),
22939
90ec0d68
MGD		 22940 /* ARM banked registers. */
22941 REGDEF(R8_usr,512|(0<<16),RNB), REGDEF(r8_usr,512|(0<<16),RNB),
22942 REGDEF(R9_usr,512|(1<<16),RNB), REGDEF(r9_usr,512|(1<<16),RNB),
22943 REGDEF(R10_usr,512|(2<<16),RNB), REGDEF(r10_usr,512|(2<<16),RNB),
22944 REGDEF(R11_usr,512|(3<<16),RNB), REGDEF(r11_usr,512|(3<<16),RNB),
22945 REGDEF(R12_usr,512|(4<<16),RNB), REGDEF(r12_usr,512|(4<<16),RNB),
22946 REGDEF(SP_usr,512|(5<<16),RNB), REGDEF(sp_usr,512|(5<<16),RNB),
22947 REGDEF(LR_usr,512|(6<<16),RNB), REGDEF(lr_usr,512|(6<<16),RNB),
22948
22949 REGDEF(R8_fiq,512|(8<<16),RNB), REGDEF(r8_fiq,512|(8<<16),RNB),
22950 REGDEF(R9_fiq,512|(9<<16),RNB), REGDEF(r9_fiq,512|(9<<16),RNB),
22951 REGDEF(R10_fiq,512|(10<<16),RNB), REGDEF(r10_fiq,512|(10<<16),RNB),
22952 REGDEF(R11_fiq,512|(11<<16),RNB), REGDEF(r11_fiq,512|(11<<16),RNB),
22953 REGDEF(R12_fiq,512|(12<<16),RNB), REGDEF(r12_fiq,512|(12<<16),RNB),
1472d06f 22954 REGDEF(SP_fiq,512|(13<<16),RNB), REGDEF(sp_fiq,512|(13<<16),RNB),
90ec0d68
MGD		 22955 REGDEF(LR_fiq,512|(14<<16),RNB), REGDEF(lr_fiq,512|(14<<16),RNB),
22956 REGDEF(SPSR_fiq,512|(14<<16)|SPSR_BIT,RNB), REGDEF(spsr_fiq,512|(14<<16)|SPSR_BIT,RNB),
22957
22958 SPLRBANK(0,IRQ,RNB), SPLRBANK(0,irq,RNB),
22959 SPLRBANK(2,SVC,RNB), SPLRBANK(2,svc,RNB),
22960 SPLRBANK(4,ABT,RNB), SPLRBANK(4,abt,RNB),
22961 SPLRBANK(6,UND,RNB), SPLRBANK(6,und,RNB),
22962 SPLRBANK(12,MON,RNB), SPLRBANK(12,mon,RNB),
22963 REGDEF(elr_hyp,768|(14<<16),RNB), REGDEF(ELR_hyp,768|(14<<16),RNB),
22964 REGDEF(sp_hyp,768|(15<<16),RNB), REGDEF(SP_hyp,768|(15<<16),RNB),
fa94de6b 22965 REGDEF(spsr_hyp,768|(14<<16)|SPSR_BIT,RNB),
90ec0d68
MGD		 22966 REGDEF(SPSR_hyp,768|(14<<16)|SPSR_BIT,RNB),
22967
c19d1205
ZW		 22968 /* FPA registers. */
22969 REGNUM(f,0,FN), REGNUM(f,1,FN), REGNUM(f,2,FN), REGNUM(f,3,FN),
22970 REGNUM(f,4,FN), REGNUM(f,5,FN), REGNUM(f,6,FN), REGNUM(f,7, FN),
22971
22972 REGNUM(F,0,FN), REGNUM(F,1,FN), REGNUM(F,2,FN), REGNUM(F,3,FN),
22973 REGNUM(F,4,FN), REGNUM(F,5,FN), REGNUM(F,6,FN), REGNUM(F,7, FN),
22974
22975 /* VFP SP registers. */
5287ad62
JB		 22976 REGSET(s,VFS), REGSET(S,VFS),
22977 REGSETH(s,VFS), REGSETH(S,VFS),
c19d1205
ZW		 22978
22979 /* VFP DP Registers. */
5287ad62
JB		 22980 REGSET(d,VFD), REGSET(D,VFD),
22981 /* Extra Neon DP registers. */
22982 REGSETH(d,VFD), REGSETH(D,VFD),
22983
22984 /* Neon QP registers. */
22985 REGSET2(q,NQ), REGSET2(Q,NQ),
c19d1205
ZW		 22986
22987 /* VFP control registers. */
22988 REGDEF(fpsid,0,VFC), REGDEF(fpscr,1,VFC), REGDEF(fpexc,8,VFC),
22989 REGDEF(FPSID,0,VFC), REGDEF(FPSCR,1,VFC), REGDEF(FPEXC,8,VFC),
cd2cf30b
PB		 22990 REGDEF(fpinst,9,VFC), REGDEF(fpinst2,10,VFC),
22991 REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
22992 REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
22993 REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
40c7d507 22994 REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
ba6cd17f
SD		 22995 REGDEF(fpscr_nzcvqc,2,VFC), REGDEF(FPSCR_nzcvqc,2,VFC),
22996 REGDEF(vpr,12,VFC), REGDEF(VPR,12,VFC),
22997 REGDEF(fpcxt_ns,14,VFC), REGDEF(FPCXT_NS,14,VFC),
22998 REGDEF(fpcxt_s,15,VFC), REGDEF(FPCXT_S,15,VFC),
c19d1205
ZW		 22999
23000 /* Maverick DSP coprocessor registers. */
23001 REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
23002 REGSET(MVF,MVF), REGSET(MVD,MVD), REGSET(MVFX,MVFX), REGSET(MVDX,MVDX),
23003
23004 REGNUM(mvax,0,MVAX), REGNUM(mvax,1,MVAX),
23005 REGNUM(mvax,2,MVAX), REGNUM(mvax,3,MVAX),
23006 REGDEF(dspsc,0,DSPSC),
23007
23008 REGNUM(MVAX,0,MVAX), REGNUM(MVAX,1,MVAX),
23009 REGNUM(MVAX,2,MVAX), REGNUM(MVAX,3,MVAX),
23010 REGDEF(DSPSC,0,DSPSC),
23011
23012 /* iWMMXt data registers - p0, c0-15. */
23013 REGSET(wr,MMXWR), REGSET(wR,MMXWR), REGSET(WR, MMXWR),
23014
23015 /* iWMMXt control registers - p1, c0-3. */
23016 REGDEF(wcid, 0,MMXWC), REGDEF(wCID, 0,MMXWC), REGDEF(WCID, 0,MMXWC),
23017 REGDEF(wcon, 1,MMXWC), REGDEF(wCon, 1,MMXWC), REGDEF(WCON, 1,MMXWC),
23018 REGDEF(wcssf, 2,MMXWC), REGDEF(wCSSF, 2,MMXWC), REGDEF(WCSSF, 2,MMXWC),
23019 REGDEF(wcasf, 3,MMXWC), REGDEF(wCASF, 3,MMXWC), REGDEF(WCASF, 3,MMXWC),
23020
23021 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23022 REGDEF(wcgr0, 8,MMXWCG), REGDEF(wCGR0, 8,MMXWCG), REGDEF(WCGR0, 8,MMXWCG),
23023 REGDEF(wcgr1, 9,MMXWCG), REGDEF(wCGR1, 9,MMXWCG), REGDEF(WCGR1, 9,MMXWCG),
23024 REGDEF(wcgr2,10,MMXWCG), REGDEF(wCGR2,10,MMXWCG), REGDEF(WCGR2,10,MMXWCG),
23025 REGDEF(wcgr3,11,MMXWCG), REGDEF(wCGR3,11,MMXWCG), REGDEF(WCGR3,11,MMXWCG),
23026
23027 /* XScale accumulator registers. */
23028 REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
23029};
23030#undef REGDEF
23031#undef REGNUM
23032#undef REGSET
7ed4c4c5 23033
c19d1205
ZW		 23034/* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23035 within psr_required_here. */
23036static const struct asm_psr psrs[] =
23037{
23038 /* Backward compatibility notation. Note that "all" is no longer
23039 truly all possible PSR bits. */
23040 {"all", PSR_c | PSR_f},
23041 {"flg", PSR_f},
23042 {"ctl", PSR_c},
23043
23044 /* Individual flags. */
23045 {"f", PSR_f},
23046 {"c", PSR_c},
23047 {"x", PSR_x},
23048 {"s", PSR_s},
59b42a0d 23049
c19d1205
ZW		 23050 /* Combinations of flags. */
23051 {"fs", PSR_f | PSR_s},
23052 {"fx", PSR_f | PSR_x},
23053 {"fc", PSR_f | PSR_c},
23054 {"sf", PSR_s | PSR_f},
23055 {"sx", PSR_s | PSR_x},
23056 {"sc", PSR_s | PSR_c},
23057 {"xf", PSR_x | PSR_f},
23058 {"xs", PSR_x | PSR_s},
23059 {"xc", PSR_x | PSR_c},
23060 {"cf", PSR_c | PSR_f},
23061 {"cs", PSR_c | PSR_s},
23062 {"cx", PSR_c | PSR_x},
23063 {"fsx", PSR_f | PSR_s | PSR_x},
23064 {"fsc", PSR_f | PSR_s | PSR_c},
23065 {"fxs", PSR_f | PSR_x | PSR_s},
23066 {"fxc", PSR_f | PSR_x | PSR_c},
23067 {"fcs", PSR_f | PSR_c | PSR_s},
23068 {"fcx", PSR_f | PSR_c | PSR_x},
23069 {"sfx", PSR_s | PSR_f | PSR_x},
23070 {"sfc", PSR_s | PSR_f | PSR_c},
23071 {"sxf", PSR_s | PSR_x | PSR_f},
23072 {"sxc", PSR_s | PSR_x | PSR_c},
23073 {"scf", PSR_s | PSR_c | PSR_f},
23074 {"scx", PSR_s | PSR_c | PSR_x},
23075 {"xfs", PSR_x | PSR_f | PSR_s},
23076 {"xfc", PSR_x | PSR_f | PSR_c},
23077 {"xsf", PSR_x | PSR_s | PSR_f},
23078 {"xsc", PSR_x | PSR_s | PSR_c},
23079 {"xcf", PSR_x | PSR_c | PSR_f},
23080 {"xcs", PSR_x | PSR_c | PSR_s},
23081 {"cfs", PSR_c | PSR_f | PSR_s},
23082 {"cfx", PSR_c | PSR_f | PSR_x},
23083 {"csf", PSR_c | PSR_s | PSR_f},
23084 {"csx", PSR_c | PSR_s | PSR_x},
23085 {"cxf", PSR_c | PSR_x | PSR_f},
23086 {"cxs", PSR_c | PSR_x | PSR_s},
23087 {"fsxc", PSR_f | PSR_s | PSR_x | PSR_c},
23088 {"fscx", PSR_f | PSR_s | PSR_c | PSR_x},
23089 {"fxsc", PSR_f | PSR_x | PSR_s | PSR_c},
23090 {"fxcs", PSR_f | PSR_x | PSR_c | PSR_s},
23091 {"fcsx", PSR_f | PSR_c | PSR_s | PSR_x},
23092 {"fcxs", PSR_f | PSR_c | PSR_x | PSR_s},
23093 {"sfxc", PSR_s | PSR_f | PSR_x | PSR_c},
23094 {"sfcx", PSR_s | PSR_f | PSR_c | PSR_x},
23095 {"sxfc", PSR_s | PSR_x | PSR_f | PSR_c},
23096 {"sxcf", PSR_s | PSR_x | PSR_c | PSR_f},
23097 {"scfx", PSR_s | PSR_c | PSR_f | PSR_x},
23098 {"scxf", PSR_s | PSR_c | PSR_x | PSR_f},
23099 {"xfsc", PSR_x | PSR_f | PSR_s | PSR_c},
23100 {"xfcs", PSR_x | PSR_f | PSR_c | PSR_s},
23101 {"xsfc", PSR_x | PSR_s | PSR_f | PSR_c},
23102 {"xscf", PSR_x | PSR_s | PSR_c | PSR_f},
23103 {"xcfs", PSR_x | PSR_c | PSR_f | PSR_s},
23104 {"xcsf", PSR_x | PSR_c | PSR_s | PSR_f},
23105 {"cfsx", PSR_c | PSR_f | PSR_s | PSR_x},
23106 {"cfxs", PSR_c | PSR_f | PSR_x | PSR_s},
23107 {"csfx", PSR_c | PSR_s | PSR_f | PSR_x},
23108 {"csxf", PSR_c | PSR_s | PSR_x | PSR_f},
23109 {"cxfs", PSR_c | PSR_x | PSR_f | PSR_s},
23110 {"cxsf", PSR_c | PSR_x | PSR_s | PSR_f},
23111};
23112
62b3e311
PB		 23113/* Table of V7M psr names. */
23114static const struct asm_psr v7m_psrs[] =
23115{
1a336194
TP		 23116 {"apsr", 0x0 }, {"APSR", 0x0 },
23117 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23118 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23119 {"psr", 0x3 }, {"PSR", 0x3 },
23120 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23121 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23122 {"epsr", 0x6 }, {"EPSR", 0x6 },
23123 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23124 {"msp", 0x8 }, {"MSP", 0x8 },
23125 {"psp", 0x9 }, {"PSP", 0x9 },
23126 {"msplim", 0xa }, {"MSPLIM", 0xa },
23127 {"psplim", 0xb }, {"PSPLIM", 0xb },
23128 {"primask", 0x10}, {"PRIMASK", 0x10},
23129 {"basepri", 0x11}, {"BASEPRI", 0x11},
23130 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
1a336194
TP		 23131 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23132 {"control", 0x14}, {"CONTROL", 0x14},
23133 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23134 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23135 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23136 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23137 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23138 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23139 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23140 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23141 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
62b3e311
PB		 23142};
23143
c19d1205
ZW		 23144/* Table of all shift-in-operand names. */
23145static const struct asm_shift_name shift_names [] =
b99bd4ef 23146{
c19d1205
ZW		 23147 { "asl", SHIFT_LSL }, { "ASL", SHIFT_LSL },
23148 { "lsl", SHIFT_LSL }, { "LSL", SHIFT_LSL },
23149 { "lsr", SHIFT_LSR }, { "LSR", SHIFT_LSR },
23150 { "asr", SHIFT_ASR }, { "ASR", SHIFT_ASR },
23151 { "ror", SHIFT_ROR }, { "ROR", SHIFT_ROR },
f5f10c66
AV		 23152 { "rrx", SHIFT_RRX }, { "RRX", SHIFT_RRX },
23153 { "uxtw", SHIFT_UXTW}, { "UXTW", SHIFT_UXTW}
c19d1205 23154};
b99bd4ef 23155
c19d1205
ZW		 23156/* Table of all explicit relocation names. */
23157#ifdef OBJ_ELF
23158static struct reloc_entry reloc_names[] =
23159{
23160 { "got", BFD_RELOC_ARM_GOT32 }, { "GOT", BFD_RELOC_ARM_GOT32 },
23161 { "gotoff", BFD_RELOC_ARM_GOTOFF }, { "GOTOFF", BFD_RELOC_ARM_GOTOFF },
23162 { "plt", BFD_RELOC_ARM_PLT32 }, { "PLT", BFD_RELOC_ARM_PLT32 },
23163 { "target1", BFD_RELOC_ARM_TARGET1 }, { "TARGET1", BFD_RELOC_ARM_TARGET1 },
23164 { "target2", BFD_RELOC_ARM_TARGET2 }, { "TARGET2", BFD_RELOC_ARM_TARGET2 },
23165 { "sbrel", BFD_RELOC_ARM_SBREL32 }, { "SBREL", BFD_RELOC_ARM_SBREL32 },
23166 { "tlsgd", BFD_RELOC_ARM_TLS_GD32}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32},
23167 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32},
23168 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32},
23169 { "gottpoff",BFD_RELOC_ARM_TLS_IE32}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32},
b43420e6 23170 { "tpoff", BFD_RELOC_ARM_TLS_LE32}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32},
0855e32b
NS		 23171 { "got_prel", BFD_RELOC_ARM_GOT_PREL}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL},
23172 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC},
477330fc 23173 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC},
0855e32b 23174 { "tlscall", BFD_RELOC_ARM_TLS_CALL},
477330fc 23175 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL},
0855e32b 23176 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ},
188fd7ae
CL		 23177 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ},
23178 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC },
23179 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC },
23180 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC },
23181 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC },
23182 { "funcdesc", BFD_RELOC_ARM_FUNCDESC },
5c5a4843
CL		 23183 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC },
23184 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC }, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC },
23185 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC }, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC },
23186 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC }, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC },
c19d1205
ZW		 23187};
23188#endif
b99bd4ef 23189
5ee91343 23190/* Table of all conditional affixes. */
c19d1205
ZW		 23191static const struct asm_cond conds[] =
23192{
23193 {"eq", 0x0},
23194 {"ne", 0x1},
23195 {"cs", 0x2}, {"hs", 0x2},
23196 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23197 {"mi", 0x4},
23198 {"pl", 0x5},
23199 {"vs", 0x6},
23200 {"vc", 0x7},
23201 {"hi", 0x8},
23202 {"ls", 0x9},
23203 {"ge", 0xa},
23204 {"lt", 0xb},
23205 {"gt", 0xc},
23206 {"le", 0xd},
23207 {"al", 0xe}
23208};
5ee91343
AV		 23209static const struct asm_cond vconds[] =
23210{
23211 {"t", 0xf},
23212 {"e", 0x10}
23213};
bfae80f2 23214
e797f7e0 23215#define UL_BARRIER(L,U,CODE,FEAT) \
823d2571
TG		 23216 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23217 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
e797f7e0 23218
62b3e311
PB		 23219static struct asm_barrier_opt barrier_opt_names[] =
23220{
e797f7e0
MGD		 23221 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER),
23222 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER),
23223 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8),
23224 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER),
23225 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER),
23226 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER),
23227 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER),
23228 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8),
23229 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER),
23230 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER),
23231 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER),
23232 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER),
23233 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8),
23234 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER),
23235 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER),
23236 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8)
62b3e311
PB		 23237};
23238
e797f7e0
MGD		 23239#undef UL_BARRIER
23240
c19d1205
ZW		 23241/* Table of ARM-format instructions. */
23242
23243/* Macros for gluing together operand strings. N.B. In all cases
23244 other than OPS0, the trailing OP_stop comes from default
23245 zero-initialization of the unspecified elements of the array. */
23246#define OPS0() { OP_stop, }
23247#define OPS1(a) { OP_##a, }
23248#define OPS2(a,b) { OP_##a,OP_##b, }
23249#define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23250#define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23251#define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23252#define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23253
5be8be5d
DG		 23254/* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23255 This is useful when mixing operands for ARM and THUMB, i.e. using the
23256 MIX_ARM_THUMB_OPERANDS macro.
23257 In order to use these macros, prefix the number of operands with _
23258 e.g. _3. */
23259#define OPS_1(a) { a, }
23260#define OPS_2(a,b) { a,b, }
23261#define OPS_3(a,b,c) { a,b,c, }
23262#define OPS_4(a,b,c,d) { a,b,c,d, }
23263#define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23264#define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23265
c19d1205
ZW		 23266/* These macros abstract out the exact format of the mnemonic table and
23267 save some repeated characters. */
23268
23269/* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23270#define TxCE(mnem, op, top, nops, ops, ae, te) \
21d799b5 23271 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
5ee91343 23272 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW		 23273
23274/* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23275 a T_MNEM_xyz enumerator. */
23276#define TCE(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23277 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 23278#define tCE(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23279 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205
ZW		 23280
23281/* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23282 infix after the third character. */
23283#define TxC3(mnem, op, top, nops, ops, ae, te) \
21d799b5 23284 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
5ee91343 23285 THUMB_VARIANT, do_##ae, do_##te, 0 }
088fa78e 23286#define TxC3w(mnem, op, top, nops, ops, ae, te) \
21d799b5 23287 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
5ee91343 23288 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 23289#define TC3(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23290 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
088fa78e 23291#define TC3w(mnem, aop, top, nops, ops, ae, te) \
e07e6e58 23292 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
c19d1205 23293#define tC3(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23294 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
088fa78e 23295#define tC3w(mnem, aop, top, nops, ops, ae, te) \
21d799b5 23296 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
c19d1205 23297
c19d1205 23298/* Mnemonic that cannot be conditionalized. The ARM condition-code
dfa9f0d5
PB		 23299 field is still 0xE. Many of the Thumb variants can be executed
23300 conditionally, so this is checked separately. */
c19d1205 23301#define TUE(mnem, op, top, nops, ops, ae, te) \
21d799b5 23302 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23303 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205 23304
dd5181d5
KT		 23305/* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23306 Used by mnemonics that have very minimal differences in the encoding for
23307 ARM and Thumb variants and can be handled in a common function. */
23308#define TUEc(mnem, op, top, nops, ops, en) \
23309 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23310 THUMB_VARIANT, do_##en, do_##en, 0 }
dd5181d5 23311
c19d1205
ZW		 23312/* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23313 condition code field. */
23314#define TUF(mnem, op, top, nops, ops, ae, te) \
21d799b5 23315 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
5ee91343 23316 THUMB_VARIANT, do_##ae, do_##te, 0 }
c19d1205
ZW		 23317
23318/* ARM-only variants of all the above. */
6a86118a 23319#define CE(mnem, op, nops, ops, ae) \
5ee91343 23320 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 23321
23322#define C3(mnem, op, nops, ops, ae) \
5ee91343 23323 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 23324
cf3cf39d
TP		 23325/* Thumb-only variants of TCE and TUE. */
23326#define ToC(mnem, top, nops, ops, te) \
23327 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
5ee91343 23328 do_##te, 0 }
cf3cf39d
TP		 23329
23330#define ToU(mnem, top, nops, ops, te) \
23331 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
5ee91343 23332 NULL, do_##te, 0 }
cf3cf39d 23333
4389b29a
AV		 23334/* T_MNEM_xyz enumerator variants of ToC. */
23335#define toC(mnem, top, nops, ops, te) \
23336 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
5ee91343 23337 do_##te, 0 }
4389b29a 23338
f6b2b12d
AV		 23339/* T_MNEM_xyz enumerator variants of ToU. */
23340#define toU(mnem, top, nops, ops, te) \
23341 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
5ee91343 23342 NULL, do_##te, 0 }
f6b2b12d 23343
e3cb604e
PB		 23344/* Legacy mnemonics that always have conditional infix after the third
23345 character. */
23346#define CL(mnem, op, nops, ops, ae) \
21d799b5 23347 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 23348 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
e3cb604e 23349
8f06b2d8
PB		 23350/* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23351#define cCE(mnem, op, nops, ops, ae) \
5ee91343 23352 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 23353
57785aa2
AV		 23354/* mov instructions that are shared between coprocessor and MVE. */
23355#define mcCE(mnem, op, nops, ops, ae) \
23356 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23357
e3cb604e
PB		 23358/* Legacy coprocessor instructions where conditional infix and conditional
23359 suffix are ambiguous. For consistency this includes all FPA instructions,
23360 not just the potentially ambiguous ones. */
23361#define cCL(mnem, op, nops, ops, ae) \
21d799b5 23362 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
5ee91343 23363 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
e3cb604e
PB		 23364
23365/* Coprocessor, takes either a suffix or a position-3 infix
23366 (for an FPA corner case). */
23367#define C3E(mnem, op, nops, ops, ae) \
21d799b5 23368 { mnem, OPS##nops ops, OT_csuf_or_in3, \
5ee91343 23369 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
8f06b2d8 23370
6a86118a 23371#define xCM_(m1, m2, m3, op, nops, ops, ae) \
21d799b5
NC		 23372 { m1 #m2 m3, OPS##nops ops, \
23373 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
5ee91343 23374 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 23375
23376#define CM(m1, m2, op, nops, ops, ae) \
e07e6e58
NC		 23377 xCM_ (m1, , m2, op, nops, ops, ae), \
23378 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23379 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23380 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23381 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23382 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23383 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23384 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23385 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23386 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23387 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23388 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23389 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23390 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23391 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23392 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23393 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23394 xCM_ (m1, le, m2, op, nops, ops, ae), \
23395 xCM_ (m1, al, m2, op, nops, ops, ae)
6a86118a
NC		 23396
23397#define UE(mnem, op, nops, ops, ae) \
5ee91343 23398 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a
NC		 23399
23400#define UF(mnem, op, nops, ops, ae) \
5ee91343 23401 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
6a86118a 23402
5287ad62
JB		 23403/* Neon data-processing. ARM versions are unconditional with cond=0xf.
23404 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23405 use the same encoding function for each. */
23406#define NUF(mnem, op, nops, ops, enc) \
23407 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
5ee91343 23408 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB		 23409
23410/* Neon data processing, version which indirects through neon_enc_tab for
23411 the various overloaded versions of opcodes. */
23412#define nUF(mnem, op, nops, ops, enc) \
21d799b5 23413 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
5ee91343 23414 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
5287ad62
JB		 23415
23416/* Neon insn with conditional suffix for the ARM version, non-overloaded
23417 version. */
5ee91343 23418#define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
037e8744 23419 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
5ee91343 23420 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 23421
037e8744 23422#define NCE(mnem, op, nops, ops, enc) \
5ee91343 23423 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB		 23424
23425#define NCEF(mnem, op, nops, ops, enc) \
5ee91343 23426 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
037e8744 23427
5287ad62 23428/* Neon insn with conditional suffix for the ARM version, overloaded types. */
5ee91343 23429#define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
21d799b5 23430 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
5ee91343 23431 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
5287ad62 23432
037e8744 23433#define nCE(mnem, op, nops, ops, enc) \
5ee91343 23434 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
037e8744
JB		 23435
23436#define nCEF(mnem, op, nops, ops, enc) \
5ee91343
AV		 23437 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23438
23439/* */
23440#define mCEF(mnem, op, nops, ops, enc) \
a302e574 23441 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
5ee91343
AV		 23442 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23443
23444
23445/* nCEF but for MVE predicated instructions. */
23446#define mnCEF(mnem, op, nops, ops, enc) \
23447 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23448
23449/* nCE but for MVE predicated instructions. */
23450#define mnCE(mnem, op, nops, ops, enc) \
23451 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
037e8744 23452
5ee91343
AV		 23453/* NUF but for potentially MVE predicated instructions. */
23454#define MNUF(mnem, op, nops, ops, enc) \
23455 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23456 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23457
23458/* nUF but for potentially MVE predicated instructions. */
23459#define mnUF(mnem, op, nops, ops, enc) \
23460 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23461 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23462
23463/* ToC but for potentially MVE predicated instructions. */
23464#define mToC(mnem, top, nops, ops, te) \
23465 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23466 do_##te, 1 }
23467
23468/* NCE but for MVE predicated instructions. */
23469#define MNCE(mnem, op, nops, ops, enc) \
23470 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23471
23472/* NCEF but for MVE predicated instructions. */
23473#define MNCEF(mnem, op, nops, ops, enc) \
23474 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
c19d1205
ZW		 23475#define do_0 0
23476
c19d1205 23477static const struct asm_opcode insns[] =
bfae80f2 23478{
74db7efb
NC		 23479#define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23480#define THUMB_VARIANT & arm_ext_v4t
21d799b5
NC		 23481 tCE("and", 0000000, _and, 3, (RR, oRR, SH), arit, t_arit3c),
23482 tC3("ands", 0100000, _ands, 3, (RR, oRR, SH), arit, t_arit3c),
23483 tCE("eor", 0200000, _eor, 3, (RR, oRR, SH), arit, t_arit3c),
23484 tC3("eors", 0300000, _eors, 3, (RR, oRR, SH), arit, t_arit3c),
23485 tCE("sub", 0400000, _sub, 3, (RR, oRR, SH), arit, t_add_sub),
23486 tC3("subs", 0500000, _subs, 3, (RR, oRR, SH), arit, t_add_sub),
23487 tCE("add", 0800000, _add, 3, (RR, oRR, SHG), arit, t_add_sub),
23488 tC3("adds", 0900000, _adds, 3, (RR, oRR, SHG), arit, t_add_sub),
23489 tCE("adc", 0a00000, _adc, 3, (RR, oRR, SH), arit, t_arit3c),
23490 tC3("adcs", 0b00000, _adcs, 3, (RR, oRR, SH), arit, t_arit3c),
23491 tCE("sbc", 0c00000, _sbc, 3, (RR, oRR, SH), arit, t_arit3),
23492 tC3("sbcs", 0d00000, _sbcs, 3, (RR, oRR, SH), arit, t_arit3),
23493 tCE("orr", 1800000, _orr, 3, (RR, oRR, SH), arit, t_arit3c),
23494 tC3("orrs", 1900000, _orrs, 3, (RR, oRR, SH), arit, t_arit3c),
23495 tCE("bic", 1c00000, _bic, 3, (RR, oRR, SH), arit, t_arit3),
23496 tC3("bics", 1d00000, _bics, 3, (RR, oRR, SH), arit, t_arit3),
c19d1205
ZW		 23497
23498 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23499 for setting PSR flag bits. They are obsolete in V6 and do not
23500 have Thumb equivalents. */
21d799b5
NC		 23501 tCE("tst", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23502 tC3w("tsts", 1100000, _tst, 2, (RR, SH), cmp, t_mvn_tst),
23503 CL("tstp", 110f000, 2, (RR, SH), cmp),
23504 tCE("cmp", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23505 tC3w("cmps", 1500000, _cmp, 2, (RR, SH), cmp, t_mov_cmp),
23506 CL("cmpp", 150f000, 2, (RR, SH), cmp),
23507 tCE("cmn", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23508 tC3w("cmns", 1700000, _cmn, 2, (RR, SH), cmp, t_mvn_tst),
23509 CL("cmnp", 170f000, 2, (RR, SH), cmp),
23510
23511 tCE("mov", 1a00000, _mov, 2, (RR, SH), mov, t_mov_cmp),
72d98d16 23512 tC3("movs", 1b00000, _movs, 2, (RR, SHG), mov, t_mov_cmp),
21d799b5
NC		 23513 tCE("mvn", 1e00000, _mvn, 2, (RR, SH), mov, t_mvn_tst),
23514 tC3("mvns", 1f00000, _mvns, 2, (RR, SH), mov, t_mvn_tst),
23515
23516 tCE("ldr", 4100000, _ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
5be8be5d
DG		 23517 tC3("ldrb", 4500000, _ldrb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
23518 tCE("str", 4000000, _str, _2, (MIX_ARM_THUMB_OPERANDS (OP_RR,
23519 OP_RRnpc),
23520 OP_ADDRGLDR),ldst, t_ldst),
23521 tC3("strb", 4400000, _strb, 2, (RRnpc_npcsp, ADDRGLDR),ldst, t_ldst),
21d799b5
NC		 23522
23523 tCE("stm", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23524 tC3("stmia", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23525 tC3("stmea", 8800000, _stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23526 tCE("ldm", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23527 tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23528 tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23529
21d799b5
NC		 23530 tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
23531 TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
bfae80f2 23532
c19d1205 23533 /* Pseudo ops. */
21d799b5 23534 tCE("adr", 28f0000, _adr, 2, (RR, EXP), adr, t_adr),
2fc8bdac 23535 C3(adrl, 28f0000, 2, (RR, EXP), adrl),
21d799b5 23536 tCE("nop", 1a00000, _nop, 1, (oI255c), nop, t_nop),
74db7efb 23537 tCE("udf", 7f000f0, _udf, 1, (oIffffb), bkpt, t_udf),
c19d1205
ZW		 23538
23539 /* Thumb-compatibility pseudo ops. */
21d799b5
NC		 23540 tCE("lsl", 1a00000, _lsl, 3, (RR, oRR, SH), shift, t_shift),
23541 tC3("lsls", 1b00000, _lsls, 3, (RR, oRR, SH), shift, t_shift),
23542 tCE("lsr", 1a00020, _lsr, 3, (RR, oRR, SH), shift, t_shift),
23543 tC3("lsrs", 1b00020, _lsrs, 3, (RR, oRR, SH), shift, t_shift),
23544 tCE("asr", 1a00040, _asr, 3, (RR, oRR, SH), shift, t_shift),
23545 tC3("asrs", 1b00040, _asrs, 3, (RR, oRR, SH), shift, t_shift),
23546 tCE("ror", 1a00060, _ror, 3, (RR, oRR, SH), shift, t_shift),
23547 tC3("rors", 1b00060, _rors, 3, (RR, oRR, SH), shift, t_shift),
23548 tCE("neg", 2600000, _neg, 2, (RR, RR), rd_rn, t_neg),
23549 tC3("negs", 2700000, _negs, 2, (RR, RR), rd_rn, t_neg),
23550 tCE("push", 92d0000, _push, 1, (REGLST), push_pop, t_push_pop),
23551 tCE("pop", 8bd0000, _pop, 1, (REGLST), push_pop, t_push_pop),
c19d1205 23552
16a4cf17 23553 /* These may simplify to neg. */
21d799b5
NC		 23554 TCE("rsb", 0600000, ebc00000, 3, (RR, oRR, SH), arit, t_rsb),
23555 TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
16a4cf17 23556
173205ca
TP		 23557#undef THUMB_VARIANT
23558#define THUMB_VARIANT & arm_ext_os
23559
23560 TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
23561 TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
23562
c921be7d
NC		 23563#undef THUMB_VARIANT
23564#define THUMB_VARIANT & arm_ext_v6
23565
21d799b5 23566 TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
c19d1205
ZW		 23567
23568 /* V1 instructions with no Thumb analogue prior to V6T2. */
c921be7d
NC		 23569#undef THUMB_VARIANT
23570#define THUMB_VARIANT & arm_ext_v6t2
23571
21d799b5
NC		 23572 TCE("teq", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23573 TC3w("teqs", 1300000, ea900f00, 2, (RR, SH), cmp, t_mvn_tst),
23574 CL("teqp", 130f000, 2, (RR, SH), cmp),
c19d1205 23575
5be8be5d
DG		 23576 TC3("ldrt", 4300000, f8500e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23577 TC3("ldrbt", 4700000, f8100e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
23578 TC3("strt", 4200000, f8400e00, 2, (RR_npcsp, ADDR), ldstt, t_ldstt),
23579 TC3("strbt", 4600000, f8000e00, 2, (RRnpc_npcsp, ADDR),ldstt, t_ldstt),
c19d1205 23580
21d799b5
NC		 23581 TC3("stmdb", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23582 TC3("stmfd", 9000000, e9000000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205 23583
21d799b5
NC		 23584 TC3("ldmdb", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
23585 TC3("ldmea", 9100000, e9100000, 2, (RRw, REGLST), ldmstm, t_ldmstm),
c19d1205
ZW		 23586
23587 /* V1 instructions with no Thumb analogue at all. */
21d799b5 23588 CE("rsc", 0e00000, 3, (RR, oRR, SH), arit),
c19d1205
ZW		 23589 C3(rscs, 0f00000, 3, (RR, oRR, SH), arit),
23590
23591 C3(stmib, 9800000, 2, (RRw, REGLST), ldmstm),
23592 C3(stmfa, 9800000, 2, (RRw, REGLST), ldmstm),
23593 C3(stmda, 8000000, 2, (RRw, REGLST), ldmstm),
23594 C3(stmed, 8000000, 2, (RRw, REGLST), ldmstm),
23595 C3(ldmib, 9900000, 2, (RRw, REGLST), ldmstm),
23596 C3(ldmed, 9900000, 2, (RRw, REGLST), ldmstm),
23597 C3(ldmda, 8100000, 2, (RRw, REGLST), ldmstm),
23598 C3(ldmfa, 8100000, 2, (RRw, REGLST), ldmstm),
23599
c921be7d
NC		 23600#undef ARM_VARIANT
23601#define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23602#undef THUMB_VARIANT
23603#define THUMB_VARIANT & arm_ext_v4t
23604
21d799b5
NC		 23605 tCE("mul", 0000090, _mul, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
23606 tC3("muls", 0100090, _muls, 3, (RRnpc, RRnpc, oRR), mul, t_mul),
c19d1205 23607
c921be7d
NC		 23608#undef THUMB_VARIANT
23609#define THUMB_VARIANT & arm_ext_v6t2
23610
21d799b5 23611 TCE("mla", 0200090, fb000000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
c19d1205
ZW		 23612 C3(mlas, 0300090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas),
23613
23614 /* Generic coprocessor instructions. */
21d799b5
NC		 23615 TCE("cdp", e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23616 TCE("ldc", c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23617 TC3("ldcl", c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23618 TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23619 TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23620 TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
db472d6f 23621 TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 23622
c921be7d
NC		 23623#undef ARM_VARIANT
23624#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23625
21d799b5 23626 CE("swp", 1000090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
c19d1205
ZW		 23627 C3(swpb, 1400090, 3, (RRnpc, RRnpc, RRnpcb), rd_rm_rn),
23628
c921be7d
NC		 23629#undef ARM_VARIANT
23630#define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23631#undef THUMB_VARIANT
23632#define THUMB_VARIANT & arm_ext_msr
23633
d2cd1205
JB		 23634 TCE("mrs", 1000000, f3e08000, 2, (RRnpc, rPSR), mrs, t_mrs),
23635 TCE("msr", 120f000, f3808000, 2, (wPSR, RR_EXi), msr, t_msr),
c19d1205 23636
c921be7d
NC		 23637#undef ARM_VARIANT
23638#define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23639#undef THUMB_VARIANT
23640#define THUMB_VARIANT & arm_ext_v6t2
23641
21d799b5
NC		 23642 TCE("smull", 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23643 CM("smull","s", 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23644 TCE("umull", 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23645 CM("umull","s", 0900090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23646 TCE("smlal", 0e00090, fbc00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23647 CM("smlal","s", 0f00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
23648 TCE("umlal", 0a00090, fbe00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
23649 CM("umlal","s", 0b00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
c19d1205 23650
c921be7d
NC		 23651#undef ARM_VARIANT
23652#define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23653#undef THUMB_VARIANT
23654#define THUMB_VARIANT & arm_ext_v4t
23655
5be8be5d
DG		 23656 tC3("ldrh", 01000b0, _ldrh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23657 tC3("strh", 00000b0, _strh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23658 tC3("ldrsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23659 tC3("ldrsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
56c0a61f
RE		 23660 tC3("ldsh", 01000f0, _ldrsh, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
23661 tC3("ldsb", 01000d0, _ldrsb, 2, (RRnpc_npcsp, ADDRGLDRS), ldstv4, t_ldst),
c19d1205 23662
c921be7d
NC		 23663#undef ARM_VARIANT
23664#define ARM_VARIANT & arm_ext_v4t_5
23665
c19d1205
ZW		 23666 /* ARM Architecture 4T. */
23667 /* Note: bx (and blx) are required on V5, even if the processor does
23668 not support Thumb. */
21d799b5 23669 TCE("bx", 12fff10, 4700, 1, (RR), bx, t_bx),
c19d1205 23670
c921be7d
NC		 23671#undef ARM_VARIANT
23672#define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23673#undef THUMB_VARIANT
23674#define THUMB_VARIANT & arm_ext_v5t
23675
c19d1205
ZW		 23676 /* Note: blx has 2 variants; the .value coded here is for
23677 BLX(2). Only this variant has conditional execution. */
21d799b5
NC		 23678 TCE("blx", 12fff30, 4780, 1, (RR_EXr), blx, t_blx),
23679 TUE("bkpt", 1200070, be00, 1, (oIffffb), bkpt, t_bkpt),
c19d1205 23680
c921be7d
NC		 23681#undef THUMB_VARIANT
23682#define THUMB_VARIANT & arm_ext_v6t2
23683
21d799b5
NC		 23684 TCE("clz", 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
23685 TUF("ldc2", c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23686 TUF("ldc2l", c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23687 TUF("stc2", c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23688 TUF("stc2l", c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
23689 TUF("cdp2", e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
23690 TUF("mcr2", e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
23691 TUF("mrc2", e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
c19d1205 23692
c921be7d 23693#undef ARM_VARIANT
74db7efb
NC		 23694#define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23695#undef THUMB_VARIANT
23696#define THUMB_VARIANT & arm_ext_v5exp
c921be7d 23697
21d799b5
NC		 23698 TCE("smlabb", 1000080, fb100000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23699 TCE("smlatb", 10000a0, fb100020, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23700 TCE("smlabt", 10000c0, fb100010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23701 TCE("smlatt", 10000e0, fb100030, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 23702
21d799b5
NC		 23703 TCE("smlawb", 1200080, fb300000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
23704 TCE("smlawt", 12000c0, fb300010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smla, t_mla),
c19d1205 23705
21d799b5
NC		 23706 TCE("smlalbb", 1400080, fbc00080, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23707 TCE("smlaltb", 14000a0, fbc000a0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23708 TCE("smlalbt", 14000c0, fbc00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
23709 TCE("smlaltt", 14000e0, fbc000b0, 4, (RRnpc, RRnpc, RRnpc, RRnpc), smlal, t_mlal),
c19d1205 23710
21d799b5
NC		 23711 TCE("smulbb", 1600080, fb10f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23712 TCE("smultb", 16000a0, fb10f020, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23713 TCE("smulbt", 16000c0, fb10f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23714 TCE("smultt", 16000e0, fb10f030, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 23715
21d799b5
NC		 23716 TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23717 TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
c19d1205 23718
03ee1b7f
NC		 23719 TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23720 TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23721 TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
23722 TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2),
c19d1205 23723
c921be7d 23724#undef ARM_VARIANT
74db7efb
NC		 23725#define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23726#undef THUMB_VARIANT
23727#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23728
21d799b5 23729 TUF("pld", 450f000, f810f000, 1, (ADDR), pld, t_pld),
5be8be5d
DG		 23730 TC3("ldrd", 00000d0, e8500000, 3, (RRnpc_npcsp, oRRnpc_npcsp, ADDRGLDRS),
23731 ldrd, t_ldstd),
23732 TC3("strd", 00000f0, e8400000, 3, (RRnpc_npcsp, oRRnpc_npcsp,
23733 ADDRGLDRS), ldrd, t_ldstd),
c19d1205 23734
21d799b5
NC		 23735 TCE("mcrr", c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23736 TCE("mrrc", c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
c19d1205 23737
c921be7d
NC		 23738#undef ARM_VARIANT
23739#define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23740
21d799b5 23741 TCE("bxj", 12fff20, f3c08f00, 1, (RR), bxj, t_bxj),
c19d1205 23742
c921be7d
NC		 23743#undef ARM_VARIANT
23744#define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23745#undef THUMB_VARIANT
23746#define THUMB_VARIANT & arm_ext_v6
23747
21d799b5
NC		 23748 TUF("cpsie", 1080000, b660, 2, (CPSF, oI31b), cpsi, t_cpsi),
23749 TUF("cpsid", 10c0000, b670, 2, (CPSF, oI31b), cpsi, t_cpsi),
23750 tCE("rev", 6bf0f30, _rev, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23751 tCE("rev16", 6bf0fb0, _rev16, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23752 tCE("revsh", 6ff0fb0, _revsh, 2, (RRnpc, RRnpc), rd_rm, t_rev),
23753 tCE("sxth", 6bf0070, _sxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23754 tCE("uxth", 6ff0070, _uxth, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23755 tCE("sxtb", 6af0070, _sxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23756 tCE("uxtb", 6ef0070, _uxtb, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23757 TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend),
c19d1205 23758
c921be7d 23759#undef THUMB_VARIANT
ff8646ee 23760#define THUMB_VARIANT & arm_ext_v6t2_v8m
c921be7d 23761
5be8be5d
DG		 23762 TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex),
23763 TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
23764 strex, t_strex),
ff8646ee
TP		 23765#undef THUMB_VARIANT
23766#define THUMB_VARIANT & arm_ext_v6t2
23767
21d799b5
NC		 23768 TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
23769 TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
62b3e311 23770
21d799b5
NC		 23771 TCE("ssat", 6a00010, f3000000, 4, (RRnpc, I32, RRnpc, oSHllar),ssat, t_ssat),
23772 TCE("usat", 6e00010, f3800000, 4, (RRnpc, I31, RRnpc, oSHllar),usat, t_usat),
62b3e311 23773
9e3c6df6 23774/* ARM V6 not included in V7M. */
c921be7d
NC		 23775#undef THUMB_VARIANT
23776#define THUMB_VARIANT & arm_ext_v6_notm
9e3c6df6 23777 TUF("rfeia", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6 23778 TUF("rfe", 8900a00, e990c000, 1, (RRw), rfe, rfe),
9e3c6df6
PB		 23779 UF(rfeib, 9900a00, 1, (RRw), rfe),
23780 UF(rfeda, 8100a00, 1, (RRw), rfe),
23781 TUF("rfedb", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23782 TUF("rfefd", 8900a00, e990c000, 1, (RRw), rfe, rfe),
d709e4e6
RE		 23783 UF(rfefa, 8100a00, 1, (RRw), rfe),
23784 TUF("rfeea", 9100a00, e810c000, 1, (RRw), rfe, rfe),
23785 UF(rfeed, 9900a00, 1, (RRw), rfe),
9e3c6df6 23786 TUF("srsia", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
d709e4e6
RE		 23787 TUF("srs", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
23788 TUF("srsea", 8c00500, e980c000, 2, (oRRw, I31w), srs, srs),
9e3c6df6 23789 UF(srsib, 9c00500, 2, (oRRw, I31w), srs),
d709e4e6 23790 UF(srsfa, 9c00500, 2, (oRRw, I31w), srs),
9e3c6df6 23791 UF(srsda, 8400500, 2, (oRRw, I31w), srs),
d709e4e6 23792 UF(srsed, 8400500, 2, (oRRw, I31w), srs),
9e3c6df6 23793 TUF("srsdb", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
d709e4e6 23794 TUF("srsfd", 9400500, e800c000, 2, (oRRw, I31w), srs, srs),
941c9cad 23795 TUF("cps", 1020000, f3af8100, 1, (I31b), imm0, t_cps),
c921be7d 23796
9e3c6df6
PB		 23797/* ARM V6 not included in V7M (eg. integer SIMD). */
23798#undef THUMB_VARIANT
23799#define THUMB_VARIANT & arm_ext_v6_dsp
21d799b5
NC		 23800 TCE("pkhbt", 6800010, eac00000, 4, (RRnpc, RRnpc, RRnpc, oSHll), pkhbt, t_pkhbt),
23801 TCE("pkhtb", 6800050, eac00020, 4, (RRnpc, RRnpc, RRnpc, oSHar), pkhtb, t_pkhtb),
23802 TCE("qadd16", 6200f10, fa90f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23803 TCE("qadd8", 6200f90, fa80f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23804 TCE("qasx", 6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23805 /* Old name for QASX. */
74db7efb 23806 TCE("qaddsubx",6200f30, faa0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 23807 TCE("qsax", 6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23808 /* Old name for QSAX. */
74db7efb 23809 TCE("qsubaddx",6200f50, fae0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23810 TCE("qsub16", 6200f70, fad0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23811 TCE("qsub8", 6200ff0, fac0f010, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23812 TCE("sadd16", 6100f10, fa90f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23813 TCE("sadd8", 6100f90, fa80f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23814 TCE("sasx", 6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23815 /* Old name for SASX. */
74db7efb 23816 TCE("saddsubx",6100f30, faa0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23817 TCE("shadd16", 6300f10, fa90f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23818 TCE("shadd8", 6300f90, fa80f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23819 TCE("shasx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23820 /* Old name for SHASX. */
21d799b5 23821 TCE("shaddsubx", 6300f30, faa0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23822 TCE("shsax", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23823 /* Old name for SHSAX. */
21d799b5
NC		 23824 TCE("shsubaddx", 6300f50, fae0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23825 TCE("shsub16", 6300f70, fad0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23826 TCE("shsub8", 6300ff0, fac0f020, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23827 TCE("ssax", 6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23828 /* Old name for SSAX. */
74db7efb 23829 TCE("ssubaddx",6100f50, fae0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23830 TCE("ssub16", 6100f70, fad0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23831 TCE("ssub8", 6100ff0, fac0f000, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23832 TCE("uadd16", 6500f10, fa90f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23833 TCE("uadd8", 6500f90, fa80f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23834 TCE("uasx", 6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23835 /* Old name for UASX. */
74db7efb 23836 TCE("uaddsubx",6500f30, faa0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23837 TCE("uhadd16", 6700f10, fa90f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23838 TCE("uhadd8", 6700f90, fa80f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23839 TCE("uhasx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23840 /* Old name for UHASX. */
21d799b5
NC		 23841 TCE("uhaddsubx", 6700f30, faa0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23842 TCE("uhsax", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23843 /* Old name for UHSAX. */
21d799b5
NC		 23844 TCE("uhsubaddx", 6700f50, fae0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23845 TCE("uhsub16", 6700f70, fad0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23846 TCE("uhsub8", 6700ff0, fac0f060, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23847 TCE("uqadd16", 6600f10, fa90f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23848 TCE("uqadd8", 6600f90, fa80f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
74db7efb 23849 TCE("uqasx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23850 /* Old name for UQASX. */
21d799b5
NC		 23851 TCE("uqaddsubx", 6600f30, faa0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23852 TCE("uqsax", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23853 /* Old name for UQSAX. */
21d799b5
NC		 23854 TCE("uqsubaddx", 6600f50, fae0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23855 TCE("uqsub16", 6600f70, fad0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23856 TCE("uqsub8", 6600ff0, fac0f050, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23857 TCE("usub16", 6500f70, fad0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23858 TCE("usax", 6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
4f80ef3e 23859 /* Old name for USAX. */
74db7efb 23860 TCE("usubaddx",6500f50, fae0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5 23861 TCE("usub8", 6500ff0, fac0f040, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
21d799b5
NC		 23862 TCE("sxtah", 6b00070, fa00f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23863 TCE("sxtab16", 6800070, fa20f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23864 TCE("sxtab", 6a00070, fa40f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23865 TCE("sxtb16", 68f0070, fa2ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23866 TCE("uxtah", 6f00070, fa10f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23867 TCE("uxtab16", 6c00070, fa30f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23868 TCE("uxtab", 6e00070, fa50f080, 4, (RRnpc, RRnpc, RRnpc, oROR), sxtah, t_sxtah),
23869 TCE("uxtb16", 6cf0070, fa3ff080, 3, (RRnpc, RRnpc, oROR), sxth, t_sxth),
23870 TCE("sel", 6800fb0, faa0f080, 3, (RRnpc, RRnpc, RRnpc), rd_rn_rm, t_simd),
23871 TCE("smlad", 7000010, fb200000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23872 TCE("smladx", 7000030, fb200010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23873 TCE("smlald", 7400010, fbc000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23874 TCE("smlaldx", 7400030, fbc000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23875 TCE("smlsd", 7000050, fb400000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23876 TCE("smlsdx", 7000070, fb400010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23877 TCE("smlsld", 7400050, fbd000c0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23878 TCE("smlsldx", 7400070, fbd000d0, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal,t_mlal),
23879 TCE("smmla", 7500010, fb500000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23880 TCE("smmlar", 7500030, fb500010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23881 TCE("smmls", 75000d0, fb600000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23882 TCE("smmlsr", 75000f0, fb600010, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23883 TCE("smmul", 750f010, fb50f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23884 TCE("smmulr", 750f030, fb50f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23885 TCE("smuad", 700f010, fb20f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23886 TCE("smuadx", 700f030, fb20f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23887 TCE("smusd", 700f050, fb40f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23888 TCE("smusdx", 700f070, fb40f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
21d799b5
NC		 23889 TCE("ssat16", 6a00f30, f3200000, 3, (RRnpc, I16, RRnpc), ssat16, t_ssat16),
23890 TCE("umaal", 0400090, fbe00060, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smlal, t_mlal),
23891 TCE("usad8", 780f010, fb70f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd),
23892 TCE("usada8", 7800010, fb700000, 4, (RRnpc, RRnpc, RRnpc, RRnpc),smla, t_mla),
23893 TCE("usat16", 6e00f30, f3a00000, 3, (RRnpc, I15, RRnpc), usat16, t_usat16),
c19d1205 23894
c921be7d 23895#undef ARM_VARIANT
55e8aae7 23896#define ARM_VARIANT & arm_ext_v6k_v6t2
c921be7d 23897#undef THUMB_VARIANT
55e8aae7 23898#define THUMB_VARIANT & arm_ext_v6k_v6t2
c921be7d 23899
21d799b5
NC		 23900 tCE("yield", 320f001, _yield, 0, (), noargs, t_hint),
23901 tCE("wfe", 320f002, _wfe, 0, (), noargs, t_hint),
23902 tCE("wfi", 320f003, _wfi, 0, (), noargs, t_hint),
23903 tCE("sev", 320f004, _sev, 0, (), noargs, t_hint),
c19d1205 23904
c921be7d
NC		 23905#undef THUMB_VARIANT
23906#define THUMB_VARIANT & arm_ext_v6_notm
5be8be5d
DG		 23907 TCE("ldrexd", 1b00f9f, e8d0007f, 3, (RRnpc_npcsp, oRRnpc_npcsp, RRnpcb),
23908 ldrexd, t_ldrexd),
23909 TCE("strexd", 1a00f90, e8c00070, 4, (RRnpc_npcsp, RRnpc_npcsp, oRRnpc_npcsp,
23910 RRnpcb), strexd, t_strexd),
ebdca51a 23911
c921be7d 23912#undef THUMB_VARIANT
ff8646ee 23913#define THUMB_VARIANT & arm_ext_v6t2_v8m
5be8be5d
DG		 23914 TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb),
23915 rd_rn, rd_rn),
23916 TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb),
23917 rd_rn, rd_rn),
23918 TCE("strexb", 1c00f90, e8c00f40, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 23919 strex, t_strexbh),
5be8be5d 23920 TCE("strexh", 1e00f90, e8c00f50, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR),
877807f8 23921 strex, t_strexbh),
21d799b5 23922 TUF("clrex", 57ff01f, f3bf8f2f, 0, (), noargs, noargs),
c19d1205 23923
c921be7d 23924#undef ARM_VARIANT
f4c65163 23925#define ARM_VARIANT & arm_ext_sec
74db7efb 23926#undef THUMB_VARIANT
f4c65163 23927#define THUMB_VARIANT & arm_ext_sec
c921be7d 23928
21d799b5 23929 TCE("smc", 1600070, f7f08000, 1, (EXPi), smc, t_smc),
c19d1205 23930
90ec0d68
MGD		 23931#undef ARM_VARIANT
23932#define ARM_VARIANT & arm_ext_virt
23933#undef THUMB_VARIANT
23934#define THUMB_VARIANT & arm_ext_virt
23935
23936 TCE("hvc", 1400070, f7e08000, 1, (EXPi), hvc, t_hvc),
23937 TCE("eret", 160006e, f3de8f00, 0, (), noargs, noargs),
23938
ddfded2f
MW		 23939#undef ARM_VARIANT
23940#define ARM_VARIANT & arm_ext_pan
23941#undef THUMB_VARIANT
23942#define THUMB_VARIANT & arm_ext_pan
23943
23944 TUF("setpan", 1100000, b610, 1, (I7), setpan, t_setpan),
23945
c921be7d 23946#undef ARM_VARIANT
74db7efb 23947#define ARM_VARIANT & arm_ext_v6t2
f4c65163
MGD		 23948#undef THUMB_VARIANT
23949#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23950
21d799b5
NC		 23951 TCE("bfc", 7c0001f, f36f0000, 3, (RRnpc, I31, I32), bfc, t_bfc),
23952 TCE("bfi", 7c00010, f3600000, 4, (RRnpc, RRnpc_I0, I31, I32), bfi, t_bfi),
23953 TCE("sbfx", 7a00050, f3400000, 4, (RR, RR, I31, I32), bfx, t_bfx),
23954 TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx),
c19d1205 23955
21d799b5 23956 TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla),
21d799b5 23957 TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit),
c19d1205 23958
5be8be5d
DG		 23959 TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23960 TC3("ldrsht", 03000f0, f9300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23961 TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
23962 TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt),
c19d1205 23963
91d8b670
JG		 23964#undef ARM_VARIANT
23965#define ARM_VARIANT & arm_ext_v3
23966#undef THUMB_VARIANT
23967#define THUMB_VARIANT & arm_ext_v6t2
23968
23969 TUE("csdb", 320f014, f3af8014, 0, (), noargs, t_csdb),
c597cc3d
SD		 23970 TUF("ssbb", 57ff040, f3bf8f40, 0, (), noargs, t_csdb),
23971 TUF("pssbb", 57ff044, f3bf8f44, 0, (), noargs, t_csdb),
91d8b670
JG		 23972
23973#undef ARM_VARIANT
23974#define ARM_VARIANT & arm_ext_v6t2
ff8646ee
TP		 23975#undef THUMB_VARIANT
23976#define THUMB_VARIANT & arm_ext_v6t2_v8m
23977 TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16),
23978 TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16),
23979
bf3eeda7 23980 /* Thumb-only instructions. */
74db7efb 23981#undef ARM_VARIANT
bf3eeda7
NS		 23982#define ARM_VARIANT NULL
23983 TUE("cbnz", 0, b900, 2, (RR, EXP), 0, t_cbz),
23984 TUE("cbz", 0, b100, 2, (RR, EXP), 0, t_cbz),
c921be7d
NC		 23985
23986 /* ARM does not really have an IT instruction, so always allow it.
23987 The opcode is copied from Thumb in order to allow warnings in
23988 -mimplicit-it=[never | arm] modes. */
23989#undef ARM_VARIANT
23990#define ARM_VARIANT & arm_ext_v1
ff8646ee
TP		 23991#undef THUMB_VARIANT
23992#define THUMB_VARIANT & arm_ext_v6t2
c921be7d 23993
21d799b5
NC		 23994 TUE("it", bf08, bf08, 1, (COND), it, t_it),
23995 TUE("itt", bf0c, bf0c, 1, (COND), it, t_it),
23996 TUE("ite", bf04, bf04, 1, (COND), it, t_it),
23997 TUE("ittt", bf0e, bf0e, 1, (COND), it, t_it),
23998 TUE("itet", bf06, bf06, 1, (COND), it, t_it),
23999 TUE("itte", bf0a, bf0a, 1, (COND), it, t_it),
24000 TUE("itee", bf02, bf02, 1, (COND), it, t_it),
24001 TUE("itttt", bf0f, bf0f, 1, (COND), it, t_it),
24002 TUE("itett", bf07, bf07, 1, (COND), it, t_it),
24003 TUE("ittet", bf0b, bf0b, 1, (COND), it, t_it),
24004 TUE("iteet", bf03, bf03, 1, (COND), it, t_it),
24005 TUE("ittte", bf0d, bf0d, 1, (COND), it, t_it),
24006 TUE("itete", bf05, bf05, 1, (COND), it, t_it),
24007 TUE("ittee", bf09, bf09, 1, (COND), it, t_it),
24008 TUE("iteee", bf01, bf01, 1, (COND), it, t_it),
1c444d06 24009 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
21d799b5
NC		 24010 TC3("rrx", 01a00060, ea4f0030, 2, (RR, RR), rd_rm, t_rrx),
24011 TC3("rrxs", 01b00060, ea5f0030, 2, (RR, RR), rd_rm, t_rrx),
c19d1205 24012
92e90b6e 24013 /* Thumb2 only instructions. */
c921be7d
NC		 24014#undef ARM_VARIANT
24015#define ARM_VARIANT NULL
92e90b6e 24016
21d799b5
NC		 24017 TCE("addw", 0, f2000000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24018 TCE("subw", 0, f2a00000, 3, (RR, RR, EXPi), 0, t_add_sub_w),
24019 TCE("orn", 0, ea600000, 3, (RR, oRR, SH), 0, t_orn),
24020 TCE("orns", 0, ea700000, 3, (RR, oRR, SH), 0, t_orn),
24021 TCE("tbb", 0, e8d0f000, 1, (TB), 0, t_tb),
24022 TCE("tbh", 0, e8d0f010, 1, (TB), 0, t_tb),
92e90b6e 24023
eea54501
MGD		 24024 /* Hardware division instructions. */
24025#undef ARM_VARIANT
24026#define ARM_VARIANT & arm_ext_adiv
c921be7d
NC		 24027#undef THUMB_VARIANT
24028#define THUMB_VARIANT & arm_ext_div
24029
eea54501
MGD		 24030 TCE("sdiv", 710f010, fb90f0f0, 3, (RR, oRR, RR), div, t_div),
24031 TCE("udiv", 730f010, fbb0f0f0, 3, (RR, oRR, RR), div, t_div),
62b3e311 24032
7e806470 24033 /* ARM V6M/V7 instructions. */
c921be7d
NC		 24034#undef ARM_VARIANT
24035#define ARM_VARIANT & arm_ext_barrier
24036#undef THUMB_VARIANT
24037#define THUMB_VARIANT & arm_ext_barrier
24038
ccb84d65
JB		 24039 TUF("dmb", 57ff050, f3bf8f50, 1, (oBARRIER_I15), barrier, barrier),
24040 TUF("dsb", 57ff040, f3bf8f40, 1, (oBARRIER_I15), barrier, barrier),
24041 TUF("isb", 57ff060, f3bf8f60, 1, (oBARRIER_I15), barrier, barrier),
7e806470 24042
62b3e311 24043 /* ARM V7 instructions. */
c921be7d
NC		 24044#undef ARM_VARIANT
24045#define ARM_VARIANT & arm_ext_v7
24046#undef THUMB_VARIANT
24047#define THUMB_VARIANT & arm_ext_v7
24048
21d799b5
NC		 24049 TUF("pli", 450f000, f910f000, 1, (ADDR), pli, t_pld),
24050 TCE("dbg", 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
62b3e311 24051
74db7efb 24052#undef ARM_VARIANT
60e5ef9f 24053#define ARM_VARIANT & arm_ext_mp
74db7efb 24054#undef THUMB_VARIANT
60e5ef9f
MGD		 24055#define THUMB_VARIANT & arm_ext_mp
24056
24057 TUF("pldw", 410f000, f830f000, 1, (ADDR), pld, t_pld),
24058
53c4b28b
MGD		 24059 /* AArchv8 instructions. */
24060#undef ARM_VARIANT
24061#define ARM_VARIANT & arm_ext_v8
4ed7ed8d
TP		 24062
24063/* Instructions shared between armv8-a and armv8-m. */
53c4b28b 24064#undef THUMB_VARIANT
4ed7ed8d 24065#define THUMB_VARIANT & arm_ext_atomics
53c4b28b 24066
4ed7ed8d
TP		 24067 TCE("lda", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24068 TCE("ldab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24069 TCE("ldah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24070 TCE("stl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24071 TCE("stlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
24072 TCE("stlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn),
4b8c8c02 24073 TCE("ldaex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
4b8c8c02
RE		 24074 TCE("ldaexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn),
24075 TCE("ldaexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn),
24076 TCE("stlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb),
24077 stlex, t_stlex),
4b8c8c02
RE		 24078 TCE("stlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb),
24079 stlex, t_stlex),
24080 TCE("stlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb),
24081 stlex, t_stlex),
4ed7ed8d
TP		 24082#undef THUMB_VARIANT
24083#define THUMB_VARIANT & arm_ext_v8
53c4b28b 24084
4ed7ed8d 24085 tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint),
4ed7ed8d
TP		 24086 TCE("ldaexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb),
24087 ldrexd, t_ldrexd),
24088 TCE("stlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb),
24089 strexd, t_strexd),
f7dd2fb2
TC		 24090
24091/* Defined in V8 but is in undefined encoding space for earlier
24092 architectures. However earlier architectures are required to treat
24093 this instuction as a semihosting trap as well. Hence while not explicitly
24094 defined as such, it is in fact correct to define the instruction for all
24095 architectures. */
24096#undef THUMB_VARIANT
24097#define THUMB_VARIANT & arm_ext_v1
24098#undef ARM_VARIANT
24099#define ARM_VARIANT & arm_ext_v1
24100 TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt),
24101
8884b720 24102 /* ARMv8 T32 only. */
74db7efb 24103#undef ARM_VARIANT
b79f7053
MGD		 24104#define ARM_VARIANT NULL
24105 TUF("dcps1", 0, f78f8001, 0, (), noargs, noargs),
24106 TUF("dcps2", 0, f78f8002, 0, (), noargs, noargs),
24107 TUF("dcps3", 0, f78f8003, 0, (), noargs, noargs),
24108
33399f07
MGD		 24109 /* FP for ARMv8. */
24110#undef ARM_VARIANT
a715796b 24111#define ARM_VARIANT & fpu_vfp_ext_armv8xd
33399f07 24112#undef THUMB_VARIANT
a715796b 24113#define THUMB_VARIANT & fpu_vfp_ext_armv8xd
33399f07
MGD		 24114
24115 nUF(vseleq, _vseleq, 3, (RVSD, RVSD, RVSD), vsel),
24116 nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
24117 nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
24118 nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
30bdf752 24119 nCE(vrintr, _vrintr, 2, (RNSDQ, oRNSDQ), vrintr),
a710b305
AV		 24120 mnCE(vrintz, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintz),
24121 mnCE(vrintx, _vrintr, 2, (RNSDQMQ, oRNSDQMQ), vrintx),
24122 mnUF(vrinta, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrinta),
24123 mnUF(vrintn, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintn),
24124 mnUF(vrintp, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintp),
24125 mnUF(vrintm, _vrinta, 2, (RNSDQMQ, oRNSDQMQ), vrintm),
33399f07 24126
91ff7894
MGD		 24127 /* Crypto v1 extensions. */
24128#undef ARM_VARIANT
24129#define ARM_VARIANT & fpu_crypto_ext_armv8
24130#undef THUMB_VARIANT
24131#define THUMB_VARIANT & fpu_crypto_ext_armv8
24132
24133 nUF(aese, _aes, 2, (RNQ, RNQ), aese),
24134 nUF(aesd, _aes, 2, (RNQ, RNQ), aesd),
24135 nUF(aesmc, _aes, 2, (RNQ, RNQ), aesmc),
24136 nUF(aesimc, _aes, 2, (RNQ, RNQ), aesimc),
48adcd8e
MGD		 24137 nUF(sha1c, _sha3op, 3, (RNQ, RNQ, RNQ), sha1c),
24138 nUF(sha1p, _sha3op, 3, (RNQ, RNQ, RNQ), sha1p),
24139 nUF(sha1m, _sha3op, 3, (RNQ, RNQ, RNQ), sha1m),
24140 nUF(sha1su0, _sha3op, 3, (RNQ, RNQ, RNQ), sha1su0),
24141 nUF(sha256h, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h),
24142 nUF(sha256h2, _sha3op, 3, (RNQ, RNQ, RNQ), sha256h2),
24143 nUF(sha256su1, _sha3op, 3, (RNQ, RNQ, RNQ), sha256su1),
3c9017d2
MGD		 24144 nUF(sha1h, _sha1h, 2, (RNQ, RNQ), sha1h),
24145 nUF(sha1su1, _sha2op, 2, (RNQ, RNQ), sha1su1),
24146 nUF(sha256su0, _sha2op, 2, (RNQ, RNQ), sha256su0),
91ff7894 24147
dd5181d5 24148#undef ARM_VARIANT
74db7efb 24149#define ARM_VARIANT & crc_ext_armv8
dd5181d5
KT		 24150#undef THUMB_VARIANT
24151#define THUMB_VARIANT & crc_ext_armv8
24152 TUEc("crc32b", 1000040, fac0f080, 3, (RR, oRR, RR), crc32b),
24153 TUEc("crc32h", 1200040, fac0f090, 3, (RR, oRR, RR), crc32h),
24154 TUEc("crc32w", 1400040, fac0f0a0, 3, (RR, oRR, RR), crc32w),
24155 TUEc("crc32cb",1000240, fad0f080, 3, (RR, oRR, RR), crc32cb),
24156 TUEc("crc32ch",1200240, fad0f090, 3, (RR, oRR, RR), crc32ch),
24157 TUEc("crc32cw",1400240, fad0f0a0, 3, (RR, oRR, RR), crc32cw),
24158
105bde57
MW		 24159 /* ARMv8.2 RAS extension. */
24160#undef ARM_VARIANT
4d1464f2 24161#define ARM_VARIANT & arm_ext_ras
105bde57 24162#undef THUMB_VARIANT
4d1464f2 24163#define THUMB_VARIANT & arm_ext_ras
105bde57
MW		 24164 TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
24165
49e8a725
SN		 24166#undef ARM_VARIANT
24167#define ARM_VARIANT & arm_ext_v8_3
24168#undef THUMB_VARIANT
24169#define THUMB_VARIANT & arm_ext_v8_3
24170 NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
24171
c604a79a
JW		 24172#undef ARM_VARIANT
24173#define ARM_VARIANT & fpu_neon_ext_dotprod
24174#undef THUMB_VARIANT
24175#define THUMB_VARIANT & fpu_neon_ext_dotprod
24176 NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
24177 NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
24178
c921be7d
NC		 24179#undef ARM_VARIANT
24180#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
53c4b28b
MGD		 24181#undef THUMB_VARIANT
24182#define THUMB_VARIANT NULL
c921be7d 24183
21d799b5
NC		 24184 cCE("wfs", e200110, 1, (RR), rd),
24185 cCE("rfs", e300110, 1, (RR), rd),
24186 cCE("wfc", e400110, 1, (RR), rd),
24187 cCE("rfc", e500110, 1, (RR), rd),
24188
24189 cCL("ldfs", c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
24190 cCL("ldfd", c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
24191 cCL("ldfe", c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
24192 cCL("ldfp", c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
24193
24194 cCL("stfs", c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
24195 cCL("stfd", c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
24196 cCL("stfe", c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
24197 cCL("stfp", c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
24198
24199 cCL("mvfs", e008100, 2, (RF, RF_IF), rd_rm),
24200 cCL("mvfsp", e008120, 2, (RF, RF_IF), rd_rm),
24201 cCL("mvfsm", e008140, 2, (RF, RF_IF), rd_rm),
24202 cCL("mvfsz", e008160, 2, (RF, RF_IF), rd_rm),
24203 cCL("mvfd", e008180, 2, (RF, RF_IF), rd_rm),
24204 cCL("mvfdp", e0081a0, 2, (RF, RF_IF), rd_rm),
24205 cCL("mvfdm", e0081c0, 2, (RF, RF_IF), rd_rm),
24206 cCL("mvfdz", e0081e0, 2, (RF, RF_IF), rd_rm),
24207 cCL("mvfe", e088100, 2, (RF, RF_IF), rd_rm),
24208 cCL("mvfep", e088120, 2, (RF, RF_IF), rd_rm),
24209 cCL("mvfem", e088140, 2, (RF, RF_IF), rd_rm),
24210 cCL("mvfez", e088160, 2, (RF, RF_IF), rd_rm),
24211
24212 cCL("mnfs", e108100, 2, (RF, RF_IF), rd_rm),
24213 cCL("mnfsp", e108120, 2, (RF, RF_IF), rd_rm),
24214 cCL("mnfsm", e108140, 2, (RF, RF_IF), rd_rm),
24215 cCL("mnfsz", e108160, 2, (RF, RF_IF), rd_rm),
24216 cCL("mnfd", e108180, 2, (RF, RF_IF), rd_rm),
24217 cCL("mnfdp", e1081a0, 2, (RF, RF_IF), rd_rm),
24218 cCL("mnfdm", e1081c0, 2, (RF, RF_IF), rd_rm),
24219 cCL("mnfdz", e1081e0, 2, (RF, RF_IF), rd_rm),
24220 cCL("mnfe", e188100, 2, (RF, RF_IF), rd_rm),
24221 cCL("mnfep", e188120, 2, (RF, RF_IF), rd_rm),
24222 cCL("mnfem", e188140, 2, (RF, RF_IF), rd_rm),
24223 cCL("mnfez", e188160, 2, (RF, RF_IF), rd_rm),
24224
24225 cCL("abss", e208100, 2, (RF, RF_IF), rd_rm),
24226 cCL("abssp", e208120, 2, (RF, RF_IF), rd_rm),
24227 cCL("abssm", e208140, 2, (RF, RF_IF), rd_rm),
24228 cCL("abssz", e208160, 2, (RF, RF_IF), rd_rm),
24229 cCL("absd", e208180, 2, (RF, RF_IF), rd_rm),
24230 cCL("absdp", e2081a0, 2, (RF, RF_IF), rd_rm),
24231 cCL("absdm", e2081c0, 2, (RF, RF_IF), rd_rm),
24232 cCL("absdz", e2081e0, 2, (RF, RF_IF), rd_rm),
24233 cCL("abse", e288100, 2, (RF, RF_IF), rd_rm),
24234 cCL("absep", e288120, 2, (RF, RF_IF), rd_rm),
24235 cCL("absem", e288140, 2, (RF, RF_IF), rd_rm),
24236 cCL("absez", e288160, 2, (RF, RF_IF), rd_rm),
24237
24238 cCL("rnds", e308100, 2, (RF, RF_IF), rd_rm),
24239 cCL("rndsp", e308120, 2, (RF, RF_IF), rd_rm),
24240 cCL("rndsm", e308140, 2, (RF, RF_IF), rd_rm),
24241 cCL("rndsz", e308160, 2, (RF, RF_IF), rd_rm),
24242 cCL("rndd", e308180, 2, (RF, RF_IF), rd_rm),
24243 cCL("rnddp", e3081a0, 2, (RF, RF_IF), rd_rm),
24244 cCL("rnddm", e3081c0, 2, (RF, RF_IF), rd_rm),
24245 cCL("rnddz", e3081e0, 2, (RF, RF_IF), rd_rm),
24246 cCL("rnde", e388100, 2, (RF, RF_IF), rd_rm),
24247 cCL("rndep", e388120, 2, (RF, RF_IF), rd_rm),
24248 cCL("rndem", e388140, 2, (RF, RF_IF), rd_rm),
24249 cCL("rndez", e388160, 2, (RF, RF_IF), rd_rm),
24250
24251 cCL("sqts", e408100, 2, (RF, RF_IF), rd_rm),
24252 cCL("sqtsp", e408120, 2, (RF, RF_IF), rd_rm),
24253 cCL("sqtsm", e408140, 2, (RF, RF_IF), rd_rm),
24254 cCL("sqtsz", e408160, 2, (RF, RF_IF), rd_rm),
24255 cCL("sqtd", e408180, 2, (RF, RF_IF), rd_rm),
24256 cCL("sqtdp", e4081a0, 2, (RF, RF_IF), rd_rm),
24257 cCL("sqtdm", e4081c0, 2, (RF, RF_IF), rd_rm),
24258 cCL("sqtdz", e4081e0, 2, (RF, RF_IF), rd_rm),
24259 cCL("sqte", e488100, 2, (RF, RF_IF), rd_rm),
24260 cCL("sqtep", e488120, 2, (RF, RF_IF), rd_rm),
24261 cCL("sqtem", e488140, 2, (RF, RF_IF), rd_rm),
24262 cCL("sqtez", e488160, 2, (RF, RF_IF), rd_rm),
24263
24264 cCL("logs", e508100, 2, (RF, RF_IF), rd_rm),
24265 cCL("logsp", e508120, 2, (RF, RF_IF), rd_rm),
24266 cCL("logsm", e508140, 2, (RF, RF_IF), rd_rm),
24267 cCL("logsz", e508160, 2, (RF, RF_IF), rd_rm),
24268 cCL("logd", e508180, 2, (RF, RF_IF), rd_rm),
24269 cCL("logdp", e5081a0, 2, (RF, RF_IF), rd_rm),
24270 cCL("logdm", e5081c0, 2, (RF, RF_IF), rd_rm),
24271 cCL("logdz", e5081e0, 2, (RF, RF_IF), rd_rm),
24272 cCL("loge", e588100, 2, (RF, RF_IF), rd_rm),
24273 cCL("logep", e588120, 2, (RF, RF_IF), rd_rm),
24274 cCL("logem", e588140, 2, (RF, RF_IF), rd_rm),
24275 cCL("logez", e588160, 2, (RF, RF_IF), rd_rm),
24276
24277 cCL("lgns", e608100, 2, (RF, RF_IF), rd_rm),
24278 cCL("lgnsp", e608120, 2, (RF, RF_IF), rd_rm),
24279 cCL("lgnsm", e608140, 2, (RF, RF_IF), rd_rm),
24280 cCL("lgnsz", e608160, 2, (RF, RF_IF), rd_rm),
24281 cCL("lgnd", e608180, 2, (RF, RF_IF), rd_rm),
24282 cCL("lgndp", e6081a0, 2, (RF, RF_IF), rd_rm),
24283 cCL("lgndm", e6081c0, 2, (RF, RF_IF), rd_rm),
24284 cCL("lgndz", e6081e0, 2, (RF, RF_IF), rd_rm),
24285 cCL("lgne", e688100, 2, (RF, RF_IF), rd_rm),
24286 cCL("lgnep", e688120, 2, (RF, RF_IF), rd_rm),
24287 cCL("lgnem", e688140, 2, (RF, RF_IF), rd_rm),
24288 cCL("lgnez", e688160, 2, (RF, RF_IF), rd_rm),
24289
24290 cCL("exps", e708100, 2, (RF, RF_IF), rd_rm),
24291 cCL("expsp", e708120, 2, (RF, RF_IF), rd_rm),
24292 cCL("expsm", e708140, 2, (RF, RF_IF), rd_rm),
24293 cCL("expsz", e708160, 2, (RF, RF_IF), rd_rm),
24294 cCL("expd", e708180, 2, (RF, RF_IF), rd_rm),
24295 cCL("expdp", e7081a0, 2, (RF, RF_IF), rd_rm),
24296 cCL("expdm", e7081c0, 2, (RF, RF_IF), rd_rm),
24297 cCL("expdz", e7081e0, 2, (RF, RF_IF), rd_rm),
24298 cCL("expe", e788100, 2, (RF, RF_IF), rd_rm),
24299 cCL("expep", e788120, 2, (RF, RF_IF), rd_rm),
24300 cCL("expem", e788140, 2, (RF, RF_IF), rd_rm),
24301 cCL("expdz", e788160, 2, (RF, RF_IF), rd_rm),
24302
24303 cCL("sins", e808100, 2, (RF, RF_IF), rd_rm),
24304 cCL("sinsp", e808120, 2, (RF, RF_IF), rd_rm),
24305 cCL("sinsm", e808140, 2, (RF, RF_IF), rd_rm),
24306 cCL("sinsz", e808160, 2, (RF, RF_IF), rd_rm),
24307 cCL("sind", e808180, 2, (RF, RF_IF), rd_rm),
24308 cCL("sindp", e8081a0, 2, (RF, RF_IF), rd_rm),
24309 cCL("sindm", e8081c0, 2, (RF, RF_IF), rd_rm),
24310 cCL("sindz", e8081e0, 2, (RF, RF_IF), rd_rm),
24311 cCL("sine", e888100, 2, (RF, RF_IF), rd_rm),
24312 cCL("sinep", e888120, 2, (RF, RF_IF), rd_rm),
24313 cCL("sinem", e888140, 2, (RF, RF_IF), rd_rm),
24314 cCL("sinez", e888160, 2, (RF, RF_IF), rd_rm),
24315
24316 cCL("coss", e908100, 2, (RF, RF_IF), rd_rm),
24317 cCL("cossp", e908120, 2, (RF, RF_IF), rd_rm),
24318 cCL("cossm", e908140, 2, (RF, RF_IF), rd_rm),
24319 cCL("cossz", e908160, 2, (RF, RF_IF), rd_rm),
24320 cCL("cosd", e908180, 2, (RF, RF_IF), rd_rm),
24321 cCL("cosdp", e9081a0, 2, (RF, RF_IF), rd_rm),
24322 cCL("cosdm", e9081c0, 2, (RF, RF_IF), rd_rm),
24323 cCL("cosdz", e9081e0, 2, (RF, RF_IF), rd_rm),
24324 cCL("cose", e988100, 2, (RF, RF_IF), rd_rm),
24325 cCL("cosep", e988120, 2, (RF, RF_IF), rd_rm),
24326 cCL("cosem", e988140, 2, (RF, RF_IF), rd_rm),
24327 cCL("cosez", e988160, 2, (RF, RF_IF), rd_rm),
24328
24329 cCL("tans", ea08100, 2, (RF, RF_IF), rd_rm),
24330 cCL("tansp", ea08120, 2, (RF, RF_IF), rd_rm),
24331 cCL("tansm", ea08140, 2, (RF, RF_IF), rd_rm),
24332 cCL("tansz", ea08160, 2, (RF, RF_IF), rd_rm),
24333 cCL("tand", ea08180, 2, (RF, RF_IF), rd_rm),
24334 cCL("tandp", ea081a0, 2, (RF, RF_IF), rd_rm),
24335 cCL("tandm", ea081c0, 2, (RF, RF_IF), rd_rm),
24336 cCL("tandz", ea081e0, 2, (RF, RF_IF), rd_rm),
24337 cCL("tane", ea88100, 2, (RF, RF_IF), rd_rm),
24338 cCL("tanep", ea88120, 2, (RF, RF_IF), rd_rm),
24339 cCL("tanem", ea88140, 2, (RF, RF_IF), rd_rm),
24340 cCL("tanez", ea88160, 2, (RF, RF_IF), rd_rm),
24341
24342 cCL("asns", eb08100, 2, (RF, RF_IF), rd_rm),
24343 cCL("asnsp", eb08120, 2, (RF, RF_IF), rd_rm),
24344 cCL("asnsm", eb08140, 2, (RF, RF_IF), rd_rm),
24345 cCL("asnsz", eb08160, 2, (RF, RF_IF), rd_rm),
24346 cCL("asnd", eb08180, 2, (RF, RF_IF), rd_rm),
24347 cCL("asndp", eb081a0, 2, (RF, RF_IF), rd_rm),
24348 cCL("asndm", eb081c0, 2, (RF, RF_IF), rd_rm),
24349 cCL("asndz", eb081e0, 2, (RF, RF_IF), rd_rm),
24350 cCL("asne", eb88100, 2, (RF, RF_IF), rd_rm),
24351 cCL("asnep", eb88120, 2, (RF, RF_IF), rd_rm),
24352 cCL("asnem", eb88140, 2, (RF, RF_IF), rd_rm),
24353 cCL("asnez", eb88160, 2, (RF, RF_IF), rd_rm),
24354
24355 cCL("acss", ec08100, 2, (RF, RF_IF), rd_rm),
24356 cCL("acssp", ec08120, 2, (RF, RF_IF), rd_rm),
24357 cCL("acssm", ec08140, 2, (RF, RF_IF), rd_rm),
24358 cCL("acssz", ec08160, 2, (RF, RF_IF), rd_rm),
24359 cCL("acsd", ec08180, 2, (RF, RF_IF), rd_rm),
24360 cCL("acsdp", ec081a0, 2, (RF, RF_IF), rd_rm),
24361 cCL("acsdm", ec081c0, 2, (RF, RF_IF), rd_rm),
24362 cCL("acsdz", ec081e0, 2, (RF, RF_IF), rd_rm),
24363 cCL("acse", ec88100, 2, (RF, RF_IF), rd_rm),
24364 cCL("acsep", ec88120, 2, (RF, RF_IF), rd_rm),
24365 cCL("acsem", ec88140, 2, (RF, RF_IF), rd_rm),
24366 cCL("acsez", ec88160, 2, (RF, RF_IF), rd_rm),
24367
24368 cCL("atns", ed08100, 2, (RF, RF_IF), rd_rm),
24369 cCL("atnsp", ed08120, 2, (RF, RF_IF), rd_rm),
24370 cCL("atnsm", ed08140, 2, (RF, RF_IF), rd_rm),
24371 cCL("atnsz", ed08160, 2, (RF, RF_IF), rd_rm),
24372 cCL("atnd", ed08180, 2, (RF, RF_IF), rd_rm),
24373 cCL("atndp", ed081a0, 2, (RF, RF_IF), rd_rm),
24374 cCL("atndm", ed081c0, 2, (RF, RF_IF), rd_rm),
24375 cCL("atndz", ed081e0, 2, (RF, RF_IF), rd_rm),
24376 cCL("atne", ed88100, 2, (RF, RF_IF), rd_rm),
24377 cCL("atnep", ed88120, 2, (RF, RF_IF), rd_rm),
24378 cCL("atnem", ed88140, 2, (RF, RF_IF), rd_rm),
24379 cCL("atnez", ed88160, 2, (RF, RF_IF), rd_rm),
24380
24381 cCL("urds", ee08100, 2, (RF, RF_IF), rd_rm),
24382 cCL("urdsp", ee08120, 2, (RF, RF_IF), rd_rm),
24383 cCL("urdsm", ee08140, 2, (RF, RF_IF), rd_rm),
24384 cCL("urdsz", ee08160, 2, (RF, RF_IF), rd_rm),
24385 cCL("urdd", ee08180, 2, (RF, RF_IF), rd_rm),
24386 cCL("urddp", ee081a0, 2, (RF, RF_IF), rd_rm),
24387 cCL("urddm", ee081c0, 2, (RF, RF_IF), rd_rm),
24388 cCL("urddz", ee081e0, 2, (RF, RF_IF), rd_rm),
24389 cCL("urde", ee88100, 2, (RF, RF_IF), rd_rm),
24390 cCL("urdep", ee88120, 2, (RF, RF_IF), rd_rm),
24391 cCL("urdem", ee88140, 2, (RF, RF_IF), rd_rm),
24392 cCL("urdez", ee88160, 2, (RF, RF_IF), rd_rm),
24393
24394 cCL("nrms", ef08100, 2, (RF, RF_IF), rd_rm),
24395 cCL("nrmsp", ef08120, 2, (RF, RF_IF), rd_rm),
24396 cCL("nrmsm", ef08140, 2, (RF, RF_IF), rd_rm),
24397 cCL("nrmsz", ef08160, 2, (RF, RF_IF), rd_rm),
24398 cCL("nrmd", ef08180, 2, (RF, RF_IF), rd_rm),
24399 cCL("nrmdp", ef081a0, 2, (RF, RF_IF), rd_rm),
24400 cCL("nrmdm", ef081c0, 2, (RF, RF_IF), rd_rm),
24401 cCL("nrmdz", ef081e0, 2, (RF, RF_IF), rd_rm),
24402 cCL("nrme", ef88100, 2, (RF, RF_IF), rd_rm),
24403 cCL("nrmep", ef88120, 2, (RF, RF_IF), rd_rm),
24404 cCL("nrmem", ef88140, 2, (RF, RF_IF), rd_rm),
24405 cCL("nrmez", ef88160, 2, (RF, RF_IF), rd_rm),
24406
24407 cCL("adfs", e000100, 3, (RF, RF, RF_IF), rd_rn_rm),
24408 cCL("adfsp", e000120, 3, (RF, RF, RF_IF), rd_rn_rm),
24409 cCL("adfsm", e000140, 3, (RF, RF, RF_IF), rd_rn_rm),
24410 cCL("adfsz", e000160, 3, (RF, RF, RF_IF), rd_rn_rm),
24411 cCL("adfd", e000180, 3, (RF, RF, RF_IF), rd_rn_rm),
24412 cCL("adfdp", e0001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24413 cCL("adfdm", e0001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24414 cCL("adfdz", e0001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24415 cCL("adfe", e080100, 3, (RF, RF, RF_IF), rd_rn_rm),
24416 cCL("adfep", e080120, 3, (RF, RF, RF_IF), rd_rn_rm),
24417 cCL("adfem", e080140, 3, (RF, RF, RF_IF), rd_rn_rm),
24418 cCL("adfez", e080160, 3, (RF, RF, RF_IF), rd_rn_rm),
24419
24420 cCL("sufs", e200100, 3, (RF, RF, RF_IF), rd_rn_rm),
24421 cCL("sufsp", e200120, 3, (RF, RF, RF_IF), rd_rn_rm),
24422 cCL("sufsm", e200140, 3, (RF, RF, RF_IF), rd_rn_rm),
24423 cCL("sufsz", e200160, 3, (RF, RF, RF_IF), rd_rn_rm),
24424 cCL("sufd", e200180, 3, (RF, RF, RF_IF), rd_rn_rm),
24425 cCL("sufdp", e2001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24426 cCL("sufdm", e2001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24427 cCL("sufdz", e2001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24428 cCL("sufe", e280100, 3, (RF, RF, RF_IF), rd_rn_rm),
24429 cCL("sufep", e280120, 3, (RF, RF, RF_IF), rd_rn_rm),
24430 cCL("sufem", e280140, 3, (RF, RF, RF_IF), rd_rn_rm),
24431 cCL("sufez", e280160, 3, (RF, RF, RF_IF), rd_rn_rm),
24432
24433 cCL("rsfs", e300100, 3, (RF, RF, RF_IF), rd_rn_rm),
24434 cCL("rsfsp", e300120, 3, (RF, RF, RF_IF), rd_rn_rm),
24435 cCL("rsfsm", e300140, 3, (RF, RF, RF_IF), rd_rn_rm),
24436 cCL("rsfsz", e300160, 3, (RF, RF, RF_IF), rd_rn_rm),
24437 cCL("rsfd", e300180, 3, (RF, RF, RF_IF), rd_rn_rm),
24438 cCL("rsfdp", e3001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24439 cCL("rsfdm", e3001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24440 cCL("rsfdz", e3001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24441 cCL("rsfe", e380100, 3, (RF, RF, RF_IF), rd_rn_rm),
24442 cCL("rsfep", e380120, 3, (RF, RF, RF_IF), rd_rn_rm),
24443 cCL("rsfem", e380140, 3, (RF, RF, RF_IF), rd_rn_rm),
24444 cCL("rsfez", e380160, 3, (RF, RF, RF_IF), rd_rn_rm),
24445
24446 cCL("mufs", e100100, 3, (RF, RF, RF_IF), rd_rn_rm),
24447 cCL("mufsp", e100120, 3, (RF, RF, RF_IF), rd_rn_rm),
24448 cCL("mufsm", e100140, 3, (RF, RF, RF_IF), rd_rn_rm),
24449 cCL("mufsz", e100160, 3, (RF, RF, RF_IF), rd_rn_rm),
24450 cCL("mufd", e100180, 3, (RF, RF, RF_IF), rd_rn_rm),
24451 cCL("mufdp", e1001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24452 cCL("mufdm", e1001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24453 cCL("mufdz", e1001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24454 cCL("mufe", e180100, 3, (RF, RF, RF_IF), rd_rn_rm),
24455 cCL("mufep", e180120, 3, (RF, RF, RF_IF), rd_rn_rm),
24456 cCL("mufem", e180140, 3, (RF, RF, RF_IF), rd_rn_rm),
24457 cCL("mufez", e180160, 3, (RF, RF, RF_IF), rd_rn_rm),
24458
24459 cCL("dvfs", e400100, 3, (RF, RF, RF_IF), rd_rn_rm),
24460 cCL("dvfsp", e400120, 3, (RF, RF, RF_IF), rd_rn_rm),
24461 cCL("dvfsm", e400140, 3, (RF, RF, RF_IF), rd_rn_rm),
24462 cCL("dvfsz", e400160, 3, (RF, RF, RF_IF), rd_rn_rm),
24463 cCL("dvfd", e400180, 3, (RF, RF, RF_IF), rd_rn_rm),
24464 cCL("dvfdp", e4001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24465 cCL("dvfdm", e4001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24466 cCL("dvfdz", e4001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24467 cCL("dvfe", e480100, 3, (RF, RF, RF_IF), rd_rn_rm),
24468 cCL("dvfep", e480120, 3, (RF, RF, RF_IF), rd_rn_rm),
24469 cCL("dvfem", e480140, 3, (RF, RF, RF_IF), rd_rn_rm),
24470 cCL("dvfez", e480160, 3, (RF, RF, RF_IF), rd_rn_rm),
24471
24472 cCL("rdfs", e500100, 3, (RF, RF, RF_IF), rd_rn_rm),
24473 cCL("rdfsp", e500120, 3, (RF, RF, RF_IF), rd_rn_rm),
24474 cCL("rdfsm", e500140, 3, (RF, RF, RF_IF), rd_rn_rm),
24475 cCL("rdfsz", e500160, 3, (RF, RF, RF_IF), rd_rn_rm),
24476 cCL("rdfd", e500180, 3, (RF, RF, RF_IF), rd_rn_rm),
24477 cCL("rdfdp", e5001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24478 cCL("rdfdm", e5001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24479 cCL("rdfdz", e5001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24480 cCL("rdfe", e580100, 3, (RF, RF, RF_IF), rd_rn_rm),
24481 cCL("rdfep", e580120, 3, (RF, RF, RF_IF), rd_rn_rm),
24482 cCL("rdfem", e580140, 3, (RF, RF, RF_IF), rd_rn_rm),
24483 cCL("rdfez", e580160, 3, (RF, RF, RF_IF), rd_rn_rm),
24484
24485 cCL("pows", e600100, 3, (RF, RF, RF_IF), rd_rn_rm),
24486 cCL("powsp", e600120, 3, (RF, RF, RF_IF), rd_rn_rm),
24487 cCL("powsm", e600140, 3, (RF, RF, RF_IF), rd_rn_rm),
24488 cCL("powsz", e600160, 3, (RF, RF, RF_IF), rd_rn_rm),
24489 cCL("powd", e600180, 3, (RF, RF, RF_IF), rd_rn_rm),
24490 cCL("powdp", e6001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24491 cCL("powdm", e6001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24492 cCL("powdz", e6001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24493 cCL("powe", e680100, 3, (RF, RF, RF_IF), rd_rn_rm),
24494 cCL("powep", e680120, 3, (RF, RF, RF_IF), rd_rn_rm),
24495 cCL("powem", e680140, 3, (RF, RF, RF_IF), rd_rn_rm),
24496 cCL("powez", e680160, 3, (RF, RF, RF_IF), rd_rn_rm),
24497
24498 cCL("rpws", e700100, 3, (RF, RF, RF_IF), rd_rn_rm),
24499 cCL("rpwsp", e700120, 3, (RF, RF, RF_IF), rd_rn_rm),
24500 cCL("rpwsm", e700140, 3, (RF, RF, RF_IF), rd_rn_rm),
24501 cCL("rpwsz", e700160, 3, (RF, RF, RF_IF), rd_rn_rm),
24502 cCL("rpwd", e700180, 3, (RF, RF, RF_IF), rd_rn_rm),
24503 cCL("rpwdp", e7001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24504 cCL("rpwdm", e7001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24505 cCL("rpwdz", e7001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24506 cCL("rpwe", e780100, 3, (RF, RF, RF_IF), rd_rn_rm),
24507 cCL("rpwep", e780120, 3, (RF, RF, RF_IF), rd_rn_rm),
24508 cCL("rpwem", e780140, 3, (RF, RF, RF_IF), rd_rn_rm),
24509 cCL("rpwez", e780160, 3, (RF, RF, RF_IF), rd_rn_rm),
24510
24511 cCL("rmfs", e800100, 3, (RF, RF, RF_IF), rd_rn_rm),
24512 cCL("rmfsp", e800120, 3, (RF, RF, RF_IF), rd_rn_rm),
24513 cCL("rmfsm", e800140, 3, (RF, RF, RF_IF), rd_rn_rm),
24514 cCL("rmfsz", e800160, 3, (RF, RF, RF_IF), rd_rn_rm),
24515 cCL("rmfd", e800180, 3, (RF, RF, RF_IF), rd_rn_rm),
24516 cCL("rmfdp", e8001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24517 cCL("rmfdm", e8001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24518 cCL("rmfdz", e8001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24519 cCL("rmfe", e880100, 3, (RF, RF, RF_IF), rd_rn_rm),
24520 cCL("rmfep", e880120, 3, (RF, RF, RF_IF), rd_rn_rm),
24521 cCL("rmfem", e880140, 3, (RF, RF, RF_IF), rd_rn_rm),
24522 cCL("rmfez", e880160, 3, (RF, RF, RF_IF), rd_rn_rm),
24523
24524 cCL("fmls", e900100, 3, (RF, RF, RF_IF), rd_rn_rm),
24525 cCL("fmlsp", e900120, 3, (RF, RF, RF_IF), rd_rn_rm),
24526 cCL("fmlsm", e900140, 3, (RF, RF, RF_IF), rd_rn_rm),
24527 cCL("fmlsz", e900160, 3, (RF, RF, RF_IF), rd_rn_rm),
24528 cCL("fmld", e900180, 3, (RF, RF, RF_IF), rd_rn_rm),
24529 cCL("fmldp", e9001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24530 cCL("fmldm", e9001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24531 cCL("fmldz", e9001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24532 cCL("fmle", e980100, 3, (RF, RF, RF_IF), rd_rn_rm),
24533 cCL("fmlep", e980120, 3, (RF, RF, RF_IF), rd_rn_rm),
24534 cCL("fmlem", e980140, 3, (RF, RF, RF_IF), rd_rn_rm),
24535 cCL("fmlez", e980160, 3, (RF, RF, RF_IF), rd_rn_rm),
24536
24537 cCL("fdvs", ea00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24538 cCL("fdvsp", ea00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24539 cCL("fdvsm", ea00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24540 cCL("fdvsz", ea00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24541 cCL("fdvd", ea00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24542 cCL("fdvdp", ea001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24543 cCL("fdvdm", ea001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24544 cCL("fdvdz", ea001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24545 cCL("fdve", ea80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24546 cCL("fdvep", ea80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24547 cCL("fdvem", ea80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24548 cCL("fdvez", ea80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24549
24550 cCL("frds", eb00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24551 cCL("frdsp", eb00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24552 cCL("frdsm", eb00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24553 cCL("frdsz", eb00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24554 cCL("frdd", eb00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24555 cCL("frddp", eb001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24556 cCL("frddm", eb001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24557 cCL("frddz", eb001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24558 cCL("frde", eb80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24559 cCL("frdep", eb80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24560 cCL("frdem", eb80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24561 cCL("frdez", eb80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24562
24563 cCL("pols", ec00100, 3, (RF, RF, RF_IF), rd_rn_rm),
24564 cCL("polsp", ec00120, 3, (RF, RF, RF_IF), rd_rn_rm),
24565 cCL("polsm", ec00140, 3, (RF, RF, RF_IF), rd_rn_rm),
24566 cCL("polsz", ec00160, 3, (RF, RF, RF_IF), rd_rn_rm),
24567 cCL("pold", ec00180, 3, (RF, RF, RF_IF), rd_rn_rm),
24568 cCL("poldp", ec001a0, 3, (RF, RF, RF_IF), rd_rn_rm),
24569 cCL("poldm", ec001c0, 3, (RF, RF, RF_IF), rd_rn_rm),
24570 cCL("poldz", ec001e0, 3, (RF, RF, RF_IF), rd_rn_rm),
24571 cCL("pole", ec80100, 3, (RF, RF, RF_IF), rd_rn_rm),
24572 cCL("polep", ec80120, 3, (RF, RF, RF_IF), rd_rn_rm),
24573 cCL("polem", ec80140, 3, (RF, RF, RF_IF), rd_rn_rm),
24574 cCL("polez", ec80160, 3, (RF, RF, RF_IF), rd_rn_rm),
24575
24576 cCE("cmf", e90f110, 2, (RF, RF_IF), fpa_cmp),
24577 C3E("cmfe", ed0f110, 2, (RF, RF_IF), fpa_cmp),
24578 cCE("cnf", eb0f110, 2, (RF, RF_IF), fpa_cmp),
24579 C3E("cnfe", ef0f110, 2, (RF, RF_IF), fpa_cmp),
24580
24581 cCL("flts", e000110, 2, (RF, RR), rn_rd),
24582 cCL("fltsp", e000130, 2, (RF, RR), rn_rd),
24583 cCL("fltsm", e000150, 2, (RF, RR), rn_rd),
24584 cCL("fltsz", e000170, 2, (RF, RR), rn_rd),
24585 cCL("fltd", e000190, 2, (RF, RR), rn_rd),
24586 cCL("fltdp", e0001b0, 2, (RF, RR), rn_rd),
24587 cCL("fltdm", e0001d0, 2, (RF, RR), rn_rd),
24588 cCL("fltdz", e0001f0, 2, (RF, RR), rn_rd),
24589 cCL("flte", e080110, 2, (RF, RR), rn_rd),
24590 cCL("fltep", e080130, 2, (RF, RR), rn_rd),
24591 cCL("fltem", e080150, 2, (RF, RR), rn_rd),
24592 cCL("fltez", e080170, 2, (RF, RR), rn_rd),
b99bd4ef 24593
c19d1205
ZW		 24594 /* The implementation of the FIX instruction is broken on some
24595 assemblers, in that it accepts a precision specifier as well as a
24596 rounding specifier, despite the fact that this is meaningless.
24597 To be more compatible, we accept it as well, though of course it
24598 does not set any bits. */
21d799b5
NC		 24599 cCE("fix", e100110, 2, (RR, RF), rd_rm),
24600 cCL("fixp", e100130, 2, (RR, RF), rd_rm),
24601 cCL("fixm", e100150, 2, (RR, RF), rd_rm),
24602 cCL("fixz", e100170, 2, (RR, RF), rd_rm),
24603 cCL("fixsp", e100130, 2, (RR, RF), rd_rm),
24604 cCL("fixsm", e100150, 2, (RR, RF), rd_rm),
24605 cCL("fixsz", e100170, 2, (RR, RF), rd_rm),
24606 cCL("fixdp", e100130, 2, (RR, RF), rd_rm),
24607 cCL("fixdm", e100150, 2, (RR, RF), rd_rm),
24608 cCL("fixdz", e100170, 2, (RR, RF), rd_rm),
24609 cCL("fixep", e100130, 2, (RR, RF), rd_rm),
24610 cCL("fixem", e100150, 2, (RR, RF), rd_rm),
24611 cCL("fixez", e100170, 2, (RR, RF), rd_rm),
bfae80f2 24612
c19d1205 24613 /* Instructions that were new with the real FPA, call them V2. */
c921be7d
NC		 24614#undef ARM_VARIANT
24615#define ARM_VARIANT & fpu_fpa_ext_v2
24616
21d799b5
NC		 24617 cCE("lfm", c100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24618 cCL("lfmfd", c900200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24619 cCL("lfmea", d100200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24620 cCE("sfm", c000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24621 cCL("sfmfd", d000200, 3, (RF, I4b, ADDR), fpa_ldmstm),
24622 cCL("sfmea", c800200, 3, (RF, I4b, ADDR), fpa_ldmstm),
c19d1205 24623
c921be7d
NC		 24624#undef ARM_VARIANT
24625#define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
ba6cd17f
SD		 24626#undef THUMB_VARIANT
24627#define THUMB_VARIANT & arm_ext_v6t2
24628 mcCE(vmrs, ef00a10, 2, (APSR_RR, RVC), vmrs),
24629 mcCE(vmsr, ee00a10, 2, (RVC, RR), vmsr),
24630#undef THUMB_VARIANT
c921be7d 24631
c19d1205 24632 /* Moves and type conversions. */
21d799b5
NC		 24633 cCE("fmstat", ef1fa10, 0, (), noargs),
24634 cCE("fsitos", eb80ac0, 2, (RVS, RVS), vfp_sp_monadic),
24635 cCE("fuitos", eb80a40, 2, (RVS, RVS), vfp_sp_monadic),
24636 cCE("ftosis", ebd0a40, 2, (RVS, RVS), vfp_sp_monadic),
24637 cCE("ftosizs", ebd0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24638 cCE("ftouis", ebc0a40, 2, (RVS, RVS), vfp_sp_monadic),
24639 cCE("ftouizs", ebc0ac0, 2, (RVS, RVS), vfp_sp_monadic),
24640 cCE("fmrx", ef00a10, 2, (RR, RVC), rd_rn),
24641 cCE("fmxr", ee00a10, 2, (RVC, RR), rn_rd),
c19d1205
ZW		 24642
24643 /* Memory operations. */
21d799b5
NC		 24644 cCE("flds", d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
24645 cCE("fsts", d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
55881a11
MGD		 24646 cCE("fldmias", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24647 cCE("fldmfds", c900a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24648 cCE("fldmdbs", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24649 cCE("fldmeas", d300a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24650 cCE("fldmiax", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24651 cCE("fldmfdx", c900b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24652 cCE("fldmdbx", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24653 cCE("fldmeax", d300b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24654 cCE("fstmias", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24655 cCE("fstmeas", c800a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmia),
24656 cCE("fstmdbs", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24657 cCE("fstmfds", d200a00, 2, (RRnpctw, VRSLST), vfp_sp_ldstmdb),
24658 cCE("fstmiax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24659 cCE("fstmeax", c800b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmia),
24660 cCE("fstmdbx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
24661 cCE("fstmfdx", d200b00, 2, (RRnpctw, VRDLST), vfp_xp_ldstmdb),
bfae80f2 24662
c19d1205 24663 /* Monadic operations. */
21d799b5
NC		 24664 cCE("fabss", eb00ac0, 2, (RVS, RVS), vfp_sp_monadic),
24665 cCE("fnegs", eb10a40, 2, (RVS, RVS), vfp_sp_monadic),
24666 cCE("fsqrts", eb10ac0, 2, (RVS, RVS), vfp_sp_monadic),
c19d1205
ZW		 24667
24668 /* Dyadic operations. */
21d799b5
NC		 24669 cCE("fadds", e300a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24670 cCE("fsubs", e300a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24671 cCE("fmuls", e200a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24672 cCE("fdivs", e800a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24673 cCE("fmacs", e000a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24674 cCE("fmscs", e100a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24675 cCE("fnmuls", e200a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24676 cCE("fnmacs", e000a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
24677 cCE("fnmscs", e100a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
b99bd4ef 24678
c19d1205 24679 /* Comparisons. */
21d799b5
NC		 24680 cCE("fcmps", eb40a40, 2, (RVS, RVS), vfp_sp_monadic),
24681 cCE("fcmpzs", eb50a40, 1, (RVS), vfp_sp_compare_z),
24682 cCE("fcmpes", eb40ac0, 2, (RVS, RVS), vfp_sp_monadic),
24683 cCE("fcmpezs", eb50ac0, 1, (RVS), vfp_sp_compare_z),
b99bd4ef 24684
62f3b8c8
PB		 24685 /* Double precision load/store are still present on single precision
24686 implementations. */
24687 cCE("fldd", d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
24688 cCE("fstd", d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
55881a11
MGD		 24689 cCE("fldmiad", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24690 cCE("fldmfdd", c900b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24691 cCE("fldmdbd", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24692 cCE("fldmead", d300b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24693 cCE("fstmiad", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24694 cCE("fstmead", c800b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmia),
24695 cCE("fstmdbd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
24696 cCE("fstmfdd", d200b00, 2, (RRnpctw, VRDLST), vfp_dp_ldstmdb),
62f3b8c8 24697
c921be7d
NC		 24698#undef ARM_VARIANT
24699#define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24700
c19d1205 24701 /* Moves and type conversions. */
21d799b5
NC		 24702 cCE("fcvtds", eb70ac0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24703 cCE("fcvtsd", eb70bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24704 cCE("fmdhr", e200b10, 2, (RVD, RR), vfp_dp_rn_rd),
24705 cCE("fmdlr", e000b10, 2, (RVD, RR), vfp_dp_rn_rd),
24706 cCE("fmrdh", e300b10, 2, (RR, RVD), vfp_dp_rd_rn),
24707 cCE("fmrdl", e100b10, 2, (RR, RVD), vfp_dp_rd_rn),
24708 cCE("fsitod", eb80bc0, 2, (RVD, RVS), vfp_dp_sp_cvt),
24709 cCE("fuitod", eb80b40, 2, (RVD, RVS), vfp_dp_sp_cvt),
24710 cCE("ftosid", ebd0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24711 cCE("ftosizd", ebd0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
24712 cCE("ftouid", ebc0b40, 2, (RVS, RVD), vfp_sp_dp_cvt),
24713 cCE("ftouizd", ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
c19d1205 24714
c19d1205 24715 /* Monadic operations. */
21d799b5
NC		 24716 cCE("fabsd", eb00bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24717 cCE("fnegd", eb10b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24718 cCE("fsqrtd", eb10bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
c19d1205
ZW		 24719
24720 /* Dyadic operations. */
21d799b5
NC		 24721 cCE("faddd", e300b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24722 cCE("fsubd", e300b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24723 cCE("fmuld", e200b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24724 cCE("fdivd", e800b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24725 cCE("fmacd", e000b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24726 cCE("fmscd", e100b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24727 cCE("fnmuld", e200b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24728 cCE("fnmacd", e000b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
24729 cCE("fnmscd", e100b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
b99bd4ef 24730
c19d1205 24731 /* Comparisons. */
21d799b5
NC		 24732 cCE("fcmpd", eb40b40, 2, (RVD, RVD), vfp_dp_rd_rm),
24733 cCE("fcmpzd", eb50b40, 1, (RVD), vfp_dp_rd),
24734 cCE("fcmped", eb40bc0, 2, (RVD, RVD), vfp_dp_rd_rm),
24735 cCE("fcmpezd", eb50bc0, 1, (RVD), vfp_dp_rd),
c19d1205 24736
037e8744
JB		 24737/* Instructions which may belong to either the Neon or VFP instruction sets.
24738 Individual encoder functions perform additional architecture checks. */
c921be7d
NC		 24739#undef ARM_VARIANT
24740#define ARM_VARIANT & fpu_vfp_ext_v1xd
24741#undef THUMB_VARIANT
24742#define THUMB_VARIANT & fpu_vfp_ext_v1xd
24743
037e8744
JB		 24744 /* These mnemonics are unique to VFP. */
24745 NCE(vsqrt, 0, 2, (RVSD, RVSD), vfp_nsyn_sqrt),
24746 NCE(vdiv, 0, 3, (RVSD, RVSD, RVSD), vfp_nsyn_div),
21d799b5
NC		 24747 nCE(vnmul, _vnmul, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24748 nCE(vnmla, _vnmla, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
24749 nCE(vnmls, _vnmls, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
037e8744
JB		 24750 NCE(vpush, 0, 1, (VRSDLST), vfp_nsyn_push),
24751 NCE(vpop, 0, 1, (VRSDLST), vfp_nsyn_pop),
24752 NCE(vcvtz, 0, 2, (RVSD, RVSD), vfp_nsyn_cvtz),
24753
24754 /* Mnemonics shared by Neon and VFP. */
21d799b5 24755 nCEF(vmls, _vmls, 3, (RNSDQ, oRNSDQ, RNSDQ_RNSC), neon_mac_maybe_scalar),
037e8744 24756
55881a11
MGD		 24757 NCE(vldm, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24758 NCE(vldmia, c900b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24759 NCE(vldmdb, d100b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24760 NCE(vstm, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24761 NCE(vstmia, c800b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
24762 NCE(vstmdb, d000b00, 2, (RRnpctw, VRSDLST), neon_ldm_stm),
037e8744 24763
dd9634d9 24764 mnCEF(vcvt, _vcvt, 3, (RNSDQMQ, RNSDQMQ, oI32z), neon_cvt),
e3e535bc 24765 nCEF(vcvtr, _vcvt, 2, (RNSDQ, RNSDQ), neon_cvtr),
dd9634d9
AV		 24766 MNCEF(vcvtb, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtb),
24767 MNCEF(vcvtt, eb20a40, 3, (RVSDMQ, RVSDMQ, oI32b), neon_cvtt),
f31fef98 24768
037e8744
JB		 24769
24770 /* NOTE: All VMOV encoding is special-cased! */
037e8744
JB		 24771 NCE(vmovq, 0, 1, (VMOV), neon_mov),
24772
32c36c3c
AV		 24773#undef THUMB_VARIANT
24774/* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24775 by different feature bits. Since we are setting the Thumb guard, we can
24776 require Thumb-1 which makes it a nop guard and set the right feature bit in
24777 do_vldr_vstr (). */
24778#define THUMB_VARIANT & arm_ext_v4t
24779 NCE(vldr, d100b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24780 NCE(vstr, d000b00, 2, (VLDR, ADDRGLDC), vldr_vstr),
24781
9db2f6b4
RL		 24782#undef ARM_VARIANT
24783#define ARM_VARIANT & arm_ext_fp16
24784#undef THUMB_VARIANT
24785#define THUMB_VARIANT & arm_ext_fp16
24786 /* New instructions added from v8.2, allowing the extraction and insertion of
24787 the upper 16 bits of a 32-bit vector register. */
24788 NCE (vmovx, eb00a40, 2, (RVS, RVS), neon_movhf),
24789 NCE (vins, eb00ac0, 2, (RVS, RVS), neon_movhf),
24790
dec41383
JW		 24791 /* New backported fma/fms instructions optional in v8.2. */
24792 NCE (vfmal, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmal),
24793 NCE (vfmsl, 810, 3, (RNDQ, RNSD, RNSD_RNSC), neon_vfmsl),
24794
c921be7d
NC		 24795#undef THUMB_VARIANT
24796#define THUMB_VARIANT & fpu_neon_ext_v1
24797#undef ARM_VARIANT
24798#define ARM_VARIANT & fpu_neon_ext_v1
24799
5287ad62
JB		 24800 /* Data processing with three registers of the same length. */
24801 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24802 NUF(vaba, 0000710, 3, (RNDQ, RNDQ, RNDQ), neon_dyadic_i_su),
24803 NUF(vabaq, 0000710, 3, (RNQ, RNQ, RNQ), neon_dyadic_i_su),
5287ad62 24804 NUF(vhaddq, 0000000, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62 24805 NUF(vrhaddq, 0000100, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
5287ad62
JB		 24806 NUF(vhsubq, 0000200, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i_su),
24807 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 24808 NUF(vqaddq, 0000010, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
5287ad62 24809 NUF(vqsubq, 0000210, 3, (RNQ, oRNQ, RNQ), neon_dyadic_i64_su),
627907b7 24810 NUF(vrshlq, 0000500, 3, (RNQ, oRNQ, RNQ), neon_rshl),
627907b7 24811 NUF(vqrshlq, 0000510, 3, (RNQ, oRNQ, RNQ), neon_rshl),
5287ad62 24812 /* If not immediate, fall back to neon_dyadic_i64_su.
5150f0d8
AV		 24813 shl should accept I8 I16 I32 I64,
24814 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24815 nUF(vshlq, _vshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_shl),
24816 nUF(vqshlq, _vqshl, 3, (RNQ, oRNQ, RNDQ_I63b), neon_qshl),
5287ad62 24817 /* Logic ops, types optional & ignored. */
4316f0d2 24818 nUF(vandq, _vand, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24819 nUF(vbicq, _vbic, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24820 nUF(vorrq, _vorr, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24821 nUF(vornq, _vorn, 3, (RNQ, oRNQ, RNDQ_Ibig), neon_logic),
4316f0d2 24822 nUF(veorq, _veor, 3, (RNQ, oRNQ, RNQ), neon_logic),
5287ad62
JB		 24823 /* Bitfield ops, untyped. */
24824 NUF(vbsl, 1100110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24825 NUF(vbslq, 1100110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24826 NUF(vbit, 1200110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24827 NUF(vbitq, 1200110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
24828 NUF(vbif, 1300110, 3, (RNDQ, RNDQ, RNDQ), neon_bitfield),
24829 NUF(vbifq, 1300110, 3, (RNQ, RNQ, RNQ), neon_bitfield),
cc933301 24830 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
21d799b5 24831 nUF(vabdq, _vabd, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 24832 nUF(vmaxq, _vmax, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
21d799b5 24833 nUF(vminq, _vmin, 3, (RNQ, oRNQ, RNQ), neon_dyadic_if_su),
5287ad62
JB		 24834 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24835 back to neon_dyadic_if_su. */
21d799b5
NC		 24836 nUF(vcge, _vcge, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24837 nUF(vcgeq, _vcge, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24838 nUF(vcgt, _vcgt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp),
24839 nUF(vcgtq, _vcgt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp),
24840 nUF(vclt, _vclt, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24841 nUF(vcltq, _vclt, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
24842 nUF(vcle, _vcle, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_cmp_inv),
24843 nUF(vcleq, _vcle, 3, (RNQ, oRNQ, RNDQ_I0), neon_cmp_inv),
428e3f1f 24844 /* Comparison. Type I8 I16 I32 F32. */
21d799b5
NC		 24845 nUF(vceq, _vceq, 3, (RNDQ, oRNDQ, RNDQ_I0), neon_ceq),
24846 nUF(vceqq, _vceq, 3, (RNQ, oRNQ, RNDQ_I0), neon_ceq),
5287ad62 24847 /* As above, D registers only. */
21d799b5
NC		 24848 nUF(vpmax, _vpmax, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
24849 nUF(vpmin, _vpmin, 3, (RND, oRND, RND), neon_dyadic_if_su_d),
5287ad62 24850 /* Int and float variants, signedness unimportant. */
21d799b5
NC		 24851 nUF(vmlaq, _vmla, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24852 nUF(vmlsq, _vmls, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mac_maybe_scalar),
24853 nUF(vpadd, _vpadd, 3, (RND, oRND, RND), neon_dyadic_if_i_d),
5287ad62 24854 /* Add/sub take types I8 I16 I32 I64 F32. */
21d799b5
NC		 24855 nUF(vaddq, _vadd, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
24856 nUF(vsubq, _vsub, 3, (RNQ, oRNQ, RNQ), neon_addsub_if_i),
5287ad62
JB		 24857 /* vtst takes sizes 8, 16, 32. */
24858 NUF(vtst, 0000810, 3, (RNDQ, oRNDQ, RNDQ), neon_tst),
24859 NUF(vtstq, 0000810, 3, (RNQ, oRNQ, RNQ), neon_tst),
24860 /* VMUL takes I8 I16 I32 F32 P8. */
21d799b5 24861 nUF(vmulq, _vmul, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_mul),
5287ad62 24862 /* VQD{R}MULH takes S16 S32. */
21d799b5 24863 nUF(vqdmulhq, _vqdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
21d799b5 24864 nUF(vqrdmulhq, _vqrdmulh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qdmulh),
5287ad62
JB		 24865 NUF(vacge, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24866 NUF(vacgeq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
24867 NUF(vacgt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute),
24868 NUF(vacgtq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute),
92559b5b
PB		 24869 NUF(vaclt, 0200e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24870 NUF(vacltq, 0200e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
24871 NUF(vacle, 0000e10, 3, (RNDQ, oRNDQ, RNDQ), neon_fcmp_absolute_inv),
24872 NUF(vacleq, 0000e10, 3, (RNQ, oRNQ, RNQ), neon_fcmp_absolute_inv),
5287ad62
JB		 24873 NUF(vrecps, 0000f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24874 NUF(vrecpsq, 0000f10, 3, (RNQ, oRNQ, RNQ), neon_step),
24875 NUF(vrsqrts, 0200f10, 3, (RNDQ, oRNDQ, RNDQ), neon_step),
24876 NUF(vrsqrtsq, 0200f10, 3, (RNQ, oRNQ, RNQ), neon_step),
d6b4b13e 24877 /* ARM v8.1 extension. */
643afb90
MW		 24878 nUF (vqrdmlahq, _vqrdmlah, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
24879 nUF (vqrdmlsh, _vqrdmlsh, 3, (RNDQ, oRNDQ, RNDQ_RNSC), neon_qrdmlah),
24880 nUF (vqrdmlshq, _vqrdmlsh, 3, (RNQ, oRNQ, RNDQ_RNSC), neon_qrdmlah),
5287ad62
JB		 24881
24882 /* Two address, int/float. Types S8 S16 S32 F32. */
5287ad62 24883 NUF(vabsq, 1b10300, 2, (RNQ, RNQ), neon_abs_neg),
5287ad62
JB		 24884 NUF(vnegq, 1b10380, 2, (RNQ, RNQ), neon_abs_neg),
24885
24886 /* Data processing with two registers and a shift amount. */
24887 /* Right shifts, and variants with rounding.
24888 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62 24889 NUF(vshrq, 0800010, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
5287ad62
JB		 24890 NUF(vrshrq, 0800210, 3, (RNQ, oRNQ, I64z), neon_rshift_round_imm),
24891 NUF(vsra, 0800110, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24892 NUF(vsraq, 0800110, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24893 NUF(vrsra, 0800310, 3, (RNDQ, oRNDQ, I64), neon_rshift_round_imm),
24894 NUF(vrsraq, 0800310, 3, (RNQ, oRNQ, I64), neon_rshift_round_imm),
24895 /* Shift and insert. Sizes accepted 8 16 32 64. */
5287ad62 24896 NUF(vsliq, 1800510, 3, (RNQ, oRNQ, I63), neon_sli),
5287ad62
JB		 24897 NUF(vsriq, 1800410, 3, (RNQ, oRNQ, I64), neon_sri),
24898 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
5287ad62
JB		 24899 NUF(vqshluq, 1800610, 3, (RNQ, oRNQ, I63), neon_qshlu_imm),
24900 /* Right shift immediate, saturating & narrowing, with rounding variants.
24901 Types accepted S16 S32 S64 U16 U32 U64. */
24902 NUF(vqshrn, 0800910, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24903 NUF(vqrshrn, 0800950, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow),
24904 /* As above, unsigned. Types accepted S16 S32 S64. */
24905 NUF(vqshrun, 0800810, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24906 NUF(vqrshrun, 0800850, 3, (RND, RNQ, I32z), neon_rshift_sat_narrow_u),
24907 /* Right shift narrowing. Types accepted I16 I32 I64. */
24908 NUF(vshrn, 0800810, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24909 NUF(vrshrn, 0800850, 3, (RND, RNQ, I32z), neon_rshift_narrow),
24910 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21d799b5 24911 nUF(vshll, _vshll, 3, (RNQ, RND, I32), neon_shll),
5287ad62 24912 /* CVT with optional immediate for fixed-point variant. */
21d799b5 24913 nUF(vcvtq, _vcvt, 3, (RNQ, RNQ, oI32b), neon_cvt),
b7fc2769 24914
4316f0d2 24915 nUF(vmvnq, _vmvn, 2, (RNQ, RNDQ_Ibig), neon_mvn),
5287ad62
JB		 24916
24917 /* Data processing, three registers of different lengths. */
24918 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24919 NUF(vabal, 0800500, 3, (RNQ, RND, RND), neon_abal),
5287ad62
JB		 24920 /* If not scalar, fall back to neon_dyadic_long.
24921 Vector types as above, scalar types S16 S32 U16 U32. */
21d799b5
NC		 24922 nUF(vmlal, _vmlal, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
24923 nUF(vmlsl, _vmlsl, 3, (RNQ, RND, RND_RNSC), neon_mac_maybe_scalar_long),
5287ad62
JB		 24924 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24925 NUF(vaddw, 0800100, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24926 NUF(vsubw, 0800300, 3, (RNQ, oRNQ, RND), neon_dyadic_wide),
24927 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24928 NUF(vaddhn, 0800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24929 NUF(vraddhn, 1800400, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24930 NUF(vsubhn, 0800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24931 NUF(vrsubhn, 1800600, 3, (RND, RNQ, RNQ), neon_dyadic_narrow),
24932 /* Saturating doubling multiplies. Types S16 S32. */
21d799b5
NC		 24933 nUF(vqdmlal, _vqdmlal, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24934 nUF(vqdmlsl, _vqdmlsl, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
24935 nUF(vqdmull, _vqdmull, 3, (RNQ, RND, RND_RNSC), neon_mul_sat_scalar_long),
5287ad62
JB		 24936 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24937 S16 S32 U16 U32. */
21d799b5 24938 nUF(vmull, _vmull, 3, (RNQ, RND, RND_RNSC), neon_vmull),
5287ad62
JB		 24939
24940 /* Extract. Size 8. */
3b8d421e
PB		 24941 NUF(vext, 0b00000, 4, (RNDQ, oRNDQ, RNDQ, I15), neon_ext),
24942 NUF(vextq, 0b00000, 4, (RNQ, oRNQ, RNQ, I15), neon_ext),
5287ad62
JB		 24943
24944 /* Two registers, miscellaneous. */
24945 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
5287ad62 24946 NUF(vrev64q, 1b00000, 2, (RNQ, RNQ), neon_rev),
5287ad62 24947 NUF(vrev32q, 1b00080, 2, (RNQ, RNQ), neon_rev),
5287ad62
JB		 24948 NUF(vrev16q, 1b00100, 2, (RNQ, RNQ), neon_rev),
24949 /* Vector replicate. Sizes 8 16 32. */
21d799b5 24950 nCE(vdupq, _vdup, 2, (RNQ, RR_RNSC), neon_dup),
5287ad62
JB		 24951 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24952 NUF(vmovl, 0800a10, 2, (RNQ, RND), neon_movl),
24953 /* VMOVN. Types I16 I32 I64. */
21d799b5 24954 nUF(vmovn, _vmovn, 2, (RND, RNQ), neon_movn),
5287ad62 24955 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21d799b5 24956 nUF(vqmovn, _vqmovn, 2, (RND, RNQ), neon_qmovn),
5287ad62 24957 /* VQMOVUN. Types S16 S32 S64. */
21d799b5 24958 nUF(vqmovun, _vqmovun, 2, (RND, RNQ), neon_qmovun),
5287ad62
JB		 24959 /* VZIP / VUZP. Sizes 8 16 32. */
24960 NUF(vzip, 1b20180, 2, (RNDQ, RNDQ), neon_zip_uzp),
24961 NUF(vzipq, 1b20180, 2, (RNQ, RNQ), neon_zip_uzp),
24962 NUF(vuzp, 1b20100, 2, (RNDQ, RNDQ), neon_zip_uzp),
24963 NUF(vuzpq, 1b20100, 2, (RNQ, RNQ), neon_zip_uzp),
24964 /* VQABS / VQNEG. Types S8 S16 S32. */
5287ad62 24965 NUF(vqabsq, 1b00700, 2, (RNQ, RNQ), neon_sat_abs_neg),
5287ad62
JB		 24966 NUF(vqnegq, 1b00780, 2, (RNQ, RNQ), neon_sat_abs_neg),
24967 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24968 NUF(vpadal, 1b00600, 2, (RNDQ, RNDQ), neon_pair_long),
24969 NUF(vpadalq, 1b00600, 2, (RNQ, RNQ), neon_pair_long),
24970 NUF(vpaddl, 1b00200, 2, (RNDQ, RNDQ), neon_pair_long),
24971 NUF(vpaddlq, 1b00200, 2, (RNQ, RNQ), neon_pair_long),
cc933301 24972 /* Reciprocal estimates. Types U32 F16 F32. */
5287ad62
JB		 24973 NUF(vrecpe, 1b30400, 2, (RNDQ, RNDQ), neon_recip_est),
24974 NUF(vrecpeq, 1b30400, 2, (RNQ, RNQ), neon_recip_est),
24975 NUF(vrsqrte, 1b30480, 2, (RNDQ, RNDQ), neon_recip_est),
24976 NUF(vrsqrteq, 1b30480, 2, (RNQ, RNQ), neon_recip_est),
24977 /* VCLS. Types S8 S16 S32. */
5287ad62
JB		 24978 NUF(vclsq, 1b00400, 2, (RNQ, RNQ), neon_cls),
24979 /* VCLZ. Types I8 I16 I32. */
5287ad62
JB		 24980 NUF(vclzq, 1b00480, 2, (RNQ, RNQ), neon_clz),
24981 /* VCNT. Size 8. */
24982 NUF(vcnt, 1b00500, 2, (RNDQ, RNDQ), neon_cnt),
24983 NUF(vcntq, 1b00500, 2, (RNQ, RNQ), neon_cnt),
24984 /* Two address, untyped. */
24985 NUF(vswp, 1b20000, 2, (RNDQ, RNDQ), neon_swp),
24986 NUF(vswpq, 1b20000, 2, (RNQ, RNQ), neon_swp),
24987 /* VTRN. Sizes 8 16 32. */
21d799b5
NC		 24988 nUF(vtrn, _vtrn, 2, (RNDQ, RNDQ), neon_trn),
24989 nUF(vtrnq, _vtrn, 2, (RNQ, RNQ), neon_trn),
5287ad62
JB		 24990
24991 /* Table lookup. Size 8. */
24992 NUF(vtbl, 1b00800, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24993 NUF(vtbx, 1b00840, 3, (RND, NRDLST, RND), neon_tbl_tbx),
24994
c921be7d
NC		 24995#undef THUMB_VARIANT
24996#define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24997#undef ARM_VARIANT
24998#define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24999
5287ad62 25000 /* Neon element/structure load/store. */
21d799b5
NC		 25001 nUF(vld1, _vld1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25002 nUF(vst1, _vst1, 2, (NSTRLST, ADDR), neon_ldx_stx),
25003 nUF(vld2, _vld2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25004 nUF(vst2, _vst2, 2, (NSTRLST, ADDR), neon_ldx_stx),
25005 nUF(vld3, _vld3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25006 nUF(vst3, _vst3, 2, (NSTRLST, ADDR), neon_ldx_stx),
25007 nUF(vld4, _vld4, 2, (NSTRLST, ADDR), neon_ldx_stx),
25008 nUF(vst4, _vst4, 2, (NSTRLST, ADDR), neon_ldx_stx),
5287ad62 25009
c921be7d 25010#undef THUMB_VARIANT
74db7efb
NC		 25011#define THUMB_VARIANT & fpu_vfp_ext_v3xd
25012#undef ARM_VARIANT
25013#define ARM_VARIANT & fpu_vfp_ext_v3xd
62f3b8c8
PB		 25014 cCE("fconsts", eb00a00, 2, (RVS, I255), vfp_sp_const),
25015 cCE("fshtos", eba0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25016 cCE("fsltos", eba0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25017 cCE("fuhtos", ebb0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25018 cCE("fultos", ebb0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25019 cCE("ftoshs", ebe0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25020 cCE("ftosls", ebe0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25021 cCE("ftouhs", ebf0a40, 2, (RVS, I16z), vfp_sp_conv_16),
25022 cCE("ftouls", ebf0ac0, 2, (RVS, I32), vfp_sp_conv_32),
25023
74db7efb 25024#undef THUMB_VARIANT
c921be7d
NC		 25025#define THUMB_VARIANT & fpu_vfp_ext_v3
25026#undef ARM_VARIANT
25027#define ARM_VARIANT & fpu_vfp_ext_v3
25028
21d799b5 25029 cCE("fconstd", eb00b00, 2, (RVD, I255), vfp_dp_const),
21d799b5 25030 cCE("fshtod", eba0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25031 cCE("fsltod", eba0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25032 cCE("fuhtod", ebb0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25033 cCE("fultod", ebb0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25034 cCE("ftoshd", ebe0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25035 cCE("ftosld", ebe0bc0, 2, (RVD, I32), vfp_dp_conv_32),
21d799b5 25036 cCE("ftouhd", ebf0b40, 2, (RVD, I16z), vfp_dp_conv_16),
21d799b5 25037 cCE("ftould", ebf0bc0, 2, (RVD, I32), vfp_dp_conv_32),
c19d1205 25038
74db7efb
NC		 25039#undef ARM_VARIANT
25040#define ARM_VARIANT & fpu_vfp_ext_fma
25041#undef THUMB_VARIANT
25042#define THUMB_VARIANT & fpu_vfp_ext_fma
d58196e0 25043 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
62f3b8c8
PB		 25044 VFP FMA variant; NEON and VFP FMA always includes the NEON
25045 FMA instructions. */
d58196e0
AV		 25046 mnCEF(vfma, _vfma, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_fmac),
25047 mnCEF(vfms, _vfms, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), neon_fmac),
25048
62f3b8c8
PB		 25049 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25050 the v form should always be used. */
25051 cCE("ffmas", ea00a00, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25052 cCE("ffnmas", ea00a40, 3, (RVS, RVS, RVS), vfp_sp_dyadic),
25053 cCE("ffmad", ea00b00, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25054 cCE("ffnmad", ea00b40, 3, (RVD, RVD, RVD), vfp_dp_rd_rn_rm),
25055 nCE(vfnma, _vfnma, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25056 nCE(vfnms, _vfnms, 3, (RVSD, RVSD, RVSD), vfp_nsyn_nmul),
25057
5287ad62 25058#undef THUMB_VARIANT
c921be7d
NC		 25059#undef ARM_VARIANT
25060#define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25061
21d799b5
NC		 25062 cCE("mia", e200010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25063 cCE("miaph", e280010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25064 cCE("miabb", e2c0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25065 cCE("miabt", e2d0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25066 cCE("miatb", e2e0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25067 cCE("miatt", e2f0010, 3, (RXA, RRnpc, RRnpc), xsc_mia),
25068 cCE("mar", c400000, 3, (RXA, RRnpc, RRnpc), xsc_mar),
25069 cCE("mra", c500000, 3, (RRnpc, RRnpc, RXA), xsc_mra),
c19d1205 25070
c921be7d
NC		 25071#undef ARM_VARIANT
25072#define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25073
21d799b5
NC		 25074 cCE("tandcb", e13f130, 1, (RR), iwmmxt_tandorc),
25075 cCE("tandch", e53f130, 1, (RR), iwmmxt_tandorc),
25076 cCE("tandcw", e93f130, 1, (RR), iwmmxt_tandorc),
25077 cCE("tbcstb", e400010, 2, (RIWR, RR), rn_rd),
25078 cCE("tbcsth", e400050, 2, (RIWR, RR), rn_rd),
25079 cCE("tbcstw", e400090, 2, (RIWR, RR), rn_rd),
25080 cCE("textrcb", e130170, 2, (RR, I7), iwmmxt_textrc),
25081 cCE("textrch", e530170, 2, (RR, I7), iwmmxt_textrc),
25082 cCE("textrcw", e930170, 2, (RR, I7), iwmmxt_textrc),
74db7efb
NC		 25083 cCE("textrmub",e100070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25084 cCE("textrmuh",e500070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25085 cCE("textrmuw",e900070, 3, (RR, RIWR, I7), iwmmxt_textrm),
25086 cCE("textrmsb",e100078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25087 cCE("textrmsh",e500078, 3, (RR, RIWR, I7), iwmmxt_textrm),
25088 cCE("textrmsw",e900078, 3, (RR, RIWR, I7), iwmmxt_textrm),
21d799b5
NC		 25089 cCE("tinsrb", e600010, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25090 cCE("tinsrh", e600050, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25091 cCE("tinsrw", e600090, 3, (RIWR, RR, I7), iwmmxt_tinsr),
25092 cCE("tmcr", e000110, 2, (RIWC_RIWG, RR), rn_rd),
25093 cCE("tmcrr", c400000, 3, (RIWR, RR, RR), rm_rd_rn),
25094 cCE("tmia", e200010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25095 cCE("tmiaph", e280010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25096 cCE("tmiabb", e2c0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25097 cCE("tmiabt", e2d0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25098 cCE("tmiatb", e2e0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
25099 cCE("tmiatt", e2f0010, 3, (RIWR, RR, RR), iwmmxt_tmia),
74db7efb
NC		 25100 cCE("tmovmskb",e100030, 2, (RR, RIWR), rd_rn),
25101 cCE("tmovmskh",e500030, 2, (RR, RIWR), rd_rn),
25102 cCE("tmovmskw",e900030, 2, (RR, RIWR), rd_rn),
21d799b5
NC		 25103 cCE("tmrc", e100110, 2, (RR, RIWC_RIWG), rd_rn),
25104 cCE("tmrrc", c500000, 3, (RR, RR, RIWR), rd_rn_rm),
25105 cCE("torcb", e13f150, 1, (RR), iwmmxt_tandorc),
25106 cCE("torch", e53f150, 1, (RR), iwmmxt_tandorc),
25107 cCE("torcw", e93f150, 1, (RR), iwmmxt_tandorc),
25108 cCE("waccb", e0001c0, 2, (RIWR, RIWR), rd_rn),
25109 cCE("wacch", e4001c0, 2, (RIWR, RIWR), rd_rn),
25110 cCE("waccw", e8001c0, 2, (RIWR, RIWR), rd_rn),
25111 cCE("waddbss", e300180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25112 cCE("waddb", e000180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25113 cCE("waddbus", e100180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25114 cCE("waddhss", e700180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25115 cCE("waddh", e400180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25116 cCE("waddhus", e500180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25117 cCE("waddwss", eb00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25118 cCE("waddw", e800180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25119 cCE("waddwus", e900180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25120 cCE("waligni", e000020, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_waligni),
74db7efb
NC		 25121 cCE("walignr0",e800020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25122 cCE("walignr1",e900020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25123 cCE("walignr2",ea00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25124 cCE("walignr3",eb00020, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25125 cCE("wand", e200000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25126 cCE("wandn", e300000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25127 cCE("wavg2b", e800000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25128 cCE("wavg2br", e900000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25129 cCE("wavg2h", ec00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25130 cCE("wavg2hr", ed00000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25131 cCE("wcmpeqb", e000060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25132 cCE("wcmpeqh", e400060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25133 cCE("wcmpeqw", e800060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 25134 cCE("wcmpgtub",e100060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25135 cCE("wcmpgtuh",e500060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25136 cCE("wcmpgtuw",e900060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25137 cCE("wcmpgtsb",e300060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25138 cCE("wcmpgtsh",e700060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25139 cCE("wcmpgtsw",eb00060, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25140 cCE("wldrb", c100000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25141 cCE("wldrh", c500000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25142 cCE("wldrw", c100100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
25143 cCE("wldrd", c500100, 2, (RIWR, ADDR), iwmmxt_wldstd),
25144 cCE("wmacs", e600100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25145 cCE("wmacsz", e700100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25146 cCE("wmacu", e400100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25147 cCE("wmacuz", e500100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25148 cCE("wmadds", ea00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25149 cCE("wmaddu", e800100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25150 cCE("wmaxsb", e200160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25151 cCE("wmaxsh", e600160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25152 cCE("wmaxsw", ea00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25153 cCE("wmaxub", e000160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25154 cCE("wmaxuh", e400160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25155 cCE("wmaxuw", e800160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25156 cCE("wminsb", e300160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25157 cCE("wminsh", e700160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25158 cCE("wminsw", eb00160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25159 cCE("wminub", e100160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25160 cCE("wminuh", e500160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25161 cCE("wminuw", e900160, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25162 cCE("wmov", e000000, 2, (RIWR, RIWR), iwmmxt_wmov),
25163 cCE("wmulsm", e300100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25164 cCE("wmulsl", e200100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25165 cCE("wmulum", e100100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25166 cCE("wmulul", e000100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25167 cCE("wor", e000000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
74db7efb
NC		 25168 cCE("wpackhss",e700080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25169 cCE("wpackhus",e500080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25170 cCE("wpackwss",eb00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25171 cCE("wpackwus",e900080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25172 cCE("wpackdss",ef00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25173 cCE("wpackdus",ed00080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
21d799b5
NC		 25174 cCE("wrorh", e700040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25175 cCE("wrorhg", e700148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25176 cCE("wrorw", eb00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25177 cCE("wrorwg", eb00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25178 cCE("wrord", ef00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25179 cCE("wrordg", ef00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25180 cCE("wsadb", e000120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25181 cCE("wsadbz", e100120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25182 cCE("wsadh", e400120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25183 cCE("wsadhz", e500120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25184 cCE("wshufh", e0001e0, 3, (RIWR, RIWR, I255), iwmmxt_wshufh),
25185 cCE("wsllh", e500040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25186 cCE("wsllhg", e500148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25187 cCE("wsllw", e900040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25188 cCE("wsllwg", e900148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25189 cCE("wslld", ed00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25190 cCE("wslldg", ed00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25191 cCE("wsrah", e400040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25192 cCE("wsrahg", e400148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25193 cCE("wsraw", e800040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25194 cCE("wsrawg", e800148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25195 cCE("wsrad", ec00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25196 cCE("wsradg", ec00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25197 cCE("wsrlh", e600040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25198 cCE("wsrlhg", e600148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25199 cCE("wsrlw", ea00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25200 cCE("wsrlwg", ea00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25201 cCE("wsrld", ee00040, 3, (RIWR, RIWR, RIWR_I32z),iwmmxt_wrwrwr_or_imm5),
25202 cCE("wsrldg", ee00148, 3, (RIWR, RIWR, RIWG), rd_rn_rm),
25203 cCE("wstrb", c000000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25204 cCE("wstrh", c400000, 2, (RIWR, ADDR), iwmmxt_wldstbh),
25205 cCE("wstrw", c000100, 2, (RIWR_RIWC, ADDR), iwmmxt_wldstw),
25206 cCE("wstrd", c400100, 2, (RIWR, ADDR), iwmmxt_wldstd),
25207 cCE("wsubbss", e3001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25208 cCE("wsubb", e0001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25209 cCE("wsubbus", e1001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25210 cCE("wsubhss", e7001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25211 cCE("wsubh", e4001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25212 cCE("wsubhus", e5001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25213 cCE("wsubwss", eb001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25214 cCE("wsubw", e8001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25215 cCE("wsubwus", e9001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25216 cCE("wunpckehub",e0000c0, 2, (RIWR, RIWR), rd_rn),
25217 cCE("wunpckehuh",e4000c0, 2, (RIWR, RIWR), rd_rn),
25218 cCE("wunpckehuw",e8000c0, 2, (RIWR, RIWR), rd_rn),
25219 cCE("wunpckehsb",e2000c0, 2, (RIWR, RIWR), rd_rn),
25220 cCE("wunpckehsh",e6000c0, 2, (RIWR, RIWR), rd_rn),
25221 cCE("wunpckehsw",ea000c0, 2, (RIWR, RIWR), rd_rn),
25222 cCE("wunpckihb", e1000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25223 cCE("wunpckihh", e5000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25224 cCE("wunpckihw", e9000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25225 cCE("wunpckelub",e0000e0, 2, (RIWR, RIWR), rd_rn),
25226 cCE("wunpckeluh",e4000e0, 2, (RIWR, RIWR), rd_rn),
25227 cCE("wunpckeluw",e8000e0, 2, (RIWR, RIWR), rd_rn),
25228 cCE("wunpckelsb",e2000e0, 2, (RIWR, RIWR), rd_rn),
25229 cCE("wunpckelsh",e6000e0, 2, (RIWR, RIWR), rd_rn),
25230 cCE("wunpckelsw",ea000e0, 2, (RIWR, RIWR), rd_rn),
25231 cCE("wunpckilb", e1000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25232 cCE("wunpckilh", e5000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25233 cCE("wunpckilw", e9000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25234 cCE("wxor", e100000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25235 cCE("wzero", e300000, 1, (RIWR), iwmmxt_wzero),
c19d1205 25236
c921be7d
NC		 25237#undef ARM_VARIANT
25238#define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25239
21d799b5
NC		 25240 cCE("torvscb", e12f190, 1, (RR), iwmmxt_tandorc),
25241 cCE("torvsch", e52f190, 1, (RR), iwmmxt_tandorc),
25242 cCE("torvscw", e92f190, 1, (RR), iwmmxt_tandorc),
25243 cCE("wabsb", e2001c0, 2, (RIWR, RIWR), rd_rn),
25244 cCE("wabsh", e6001c0, 2, (RIWR, RIWR), rd_rn),
25245 cCE("wabsw", ea001c0, 2, (RIWR, RIWR), rd_rn),
25246 cCE("wabsdiffb", e1001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25247 cCE("wabsdiffh", e5001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25248 cCE("wabsdiffw", e9001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25249 cCE("waddbhusl", e2001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25250 cCE("waddbhusm", e6001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25251 cCE("waddhc", e600180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25252 cCE("waddwc", ea00180, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25253 cCE("waddsubhx", ea001a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25254 cCE("wavg4", e400000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25255 cCE("wavg4r", e500000, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25256 cCE("wmaddsn", ee00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25257 cCE("wmaddsx", eb00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25258 cCE("wmaddun", ec00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25259 cCE("wmaddux", e900100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25260 cCE("wmerge", e000080, 4, (RIWR, RIWR, RIWR, I7), iwmmxt_wmerge),
25261 cCE("wmiabb", e0000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25262 cCE("wmiabt", e1000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25263 cCE("wmiatb", e2000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25264 cCE("wmiatt", e3000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25265 cCE("wmiabbn", e4000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25266 cCE("wmiabtn", e5000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25267 cCE("wmiatbn", e6000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25268 cCE("wmiattn", e7000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25269 cCE("wmiawbb", e800120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25270 cCE("wmiawbt", e900120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25271 cCE("wmiawtb", ea00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25272 cCE("wmiawtt", eb00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25273 cCE("wmiawbbn", ec00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25274 cCE("wmiawbtn", ed00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25275 cCE("wmiawtbn", ee00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25276 cCE("wmiawttn", ef00120, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25277 cCE("wmulsmr", ef00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25278 cCE("wmulumr", ed00100, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25279 cCE("wmulwumr", ec000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25280 cCE("wmulwsmr", ee000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25281 cCE("wmulwum", ed000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25282 cCE("wmulwsm", ef000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25283 cCE("wmulwl", eb000c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25284 cCE("wqmiabb", e8000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25285 cCE("wqmiabt", e9000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25286 cCE("wqmiatb", ea000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25287 cCE("wqmiatt", eb000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25288 cCE("wqmiabbn", ec000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25289 cCE("wqmiabtn", ed000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25290 cCE("wqmiatbn", ee000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25291 cCE("wqmiattn", ef000a0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25292 cCE("wqmulm", e100080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25293 cCE("wqmulmr", e300080, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25294 cCE("wqmulwm", ec000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25295 cCE("wqmulwmr", ee000e0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
25296 cCE("wsubaddhx", ed001c0, 3, (RIWR, RIWR, RIWR), rd_rn_rm),
2d447fca 25297
c921be7d
NC		 25298#undef ARM_VARIANT
25299#define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25300
21d799b5
NC		 25301 cCE("cfldrs", c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
25302 cCE("cfldrd", c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
25303 cCE("cfldr32", c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
25304 cCE("cfldr64", c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
25305 cCE("cfstrs", c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
25306 cCE("cfstrd", c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
25307 cCE("cfstr32", c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
25308 cCE("cfstr64", c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
25309 cCE("cfmvsr", e000450, 2, (RMF, RR), rn_rd),
25310 cCE("cfmvrs", e100450, 2, (RR, RMF), rd_rn),
25311 cCE("cfmvdlr", e000410, 2, (RMD, RR), rn_rd),
25312 cCE("cfmvrdl", e100410, 2, (RR, RMD), rd_rn),
25313 cCE("cfmvdhr", e000430, 2, (RMD, RR), rn_rd),
25314 cCE("cfmvrdh", e100430, 2, (RR, RMD), rd_rn),
74db7efb
NC		 25315 cCE("cfmv64lr",e000510, 2, (RMDX, RR), rn_rd),
25316 cCE("cfmvr64l",e100510, 2, (RR, RMDX), rd_rn),
25317 cCE("cfmv64hr",e000530, 2, (RMDX, RR), rn_rd),
25318 cCE("cfmvr64h",e100530, 2, (RR, RMDX), rd_rn),
25319 cCE("cfmval32",e200440, 2, (RMAX, RMFX), rd_rn),
25320 cCE("cfmv32al",e100440, 2, (RMFX, RMAX), rd_rn),
25321 cCE("cfmvam32",e200460, 2, (RMAX, RMFX), rd_rn),
25322 cCE("cfmv32am",e100460, 2, (RMFX, RMAX), rd_rn),
25323 cCE("cfmvah32",e200480, 2, (RMAX, RMFX), rd_rn),
25324 cCE("cfmv32ah",e100480, 2, (RMFX, RMAX), rd_rn),
21d799b5
NC		 25325 cCE("cfmva32", e2004a0, 2, (RMAX, RMFX), rd_rn),
25326 cCE("cfmv32a", e1004a0, 2, (RMFX, RMAX), rd_rn),
25327 cCE("cfmva64", e2004c0, 2, (RMAX, RMDX), rd_rn),
25328 cCE("cfmv64a", e1004c0, 2, (RMDX, RMAX), rd_rn),
74db7efb
NC		 25329 cCE("cfmvsc32",e2004e0, 2, (RMDS, RMDX), mav_dspsc),
25330 cCE("cfmv32sc",e1004e0, 2, (RMDX, RMDS), rd),
21d799b5
NC		 25331 cCE("cfcpys", e000400, 2, (RMF, RMF), rd_rn),
25332 cCE("cfcpyd", e000420, 2, (RMD, RMD), rd_rn),
25333 cCE("cfcvtsd", e000460, 2, (RMD, RMF), rd_rn),
25334 cCE("cfcvtds", e000440, 2, (RMF, RMD), rd_rn),
74db7efb
NC		 25335 cCE("cfcvt32s",e000480, 2, (RMF, RMFX), rd_rn),
25336 cCE("cfcvt32d",e0004a0, 2, (RMD, RMFX), rd_rn),
25337 cCE("cfcvt64s",e0004c0, 2, (RMF, RMDX), rd_rn),
25338 cCE("cfcvt64d",e0004e0, 2, (RMD, RMDX), rd_rn),
25339 cCE("cfcvts32",e100580, 2, (RMFX, RMF), rd_rn),
25340 cCE("cfcvtd32",e1005a0, 2, (RMFX, RMD), rd_rn),
21d799b5
NC		 25341 cCE("cftruncs32",e1005c0, 2, (RMFX, RMF), rd_rn),
25342 cCE("cftruncd32",e1005e0, 2, (RMFX, RMD), rd_rn),
74db7efb
NC		 25343 cCE("cfrshl32",e000550, 3, (RMFX, RMFX, RR), mav_triple),
25344 cCE("cfrshl64",e000570, 3, (RMDX, RMDX, RR), mav_triple),
21d799b5
NC		 25345 cCE("cfsh32", e000500, 3, (RMFX, RMFX, I63s), mav_shift),
25346 cCE("cfsh64", e200500, 3, (RMDX, RMDX, I63s), mav_shift),
25347 cCE("cfcmps", e100490, 3, (RR, RMF, RMF), rd_rn_rm),
25348 cCE("cfcmpd", e1004b0, 3, (RR, RMD, RMD), rd_rn_rm),
25349 cCE("cfcmp32", e100590, 3, (RR, RMFX, RMFX), rd_rn_rm),
25350 cCE("cfcmp64", e1005b0, 3, (RR, RMDX, RMDX), rd_rn_rm),
25351 cCE("cfabss", e300400, 2, (RMF, RMF), rd_rn),
25352 cCE("cfabsd", e300420, 2, (RMD, RMD), rd_rn),
25353 cCE("cfnegs", e300440, 2, (RMF, RMF), rd_rn),
25354 cCE("cfnegd", e300460, 2, (RMD, RMD), rd_rn),
25355 cCE("cfadds", e300480, 3, (RMF, RMF, RMF), rd_rn_rm),
25356 cCE("cfaddd", e3004a0, 3, (RMD, RMD, RMD), rd_rn_rm),
25357 cCE("cfsubs", e3004c0, 3, (RMF, RMF, RMF), rd_rn_rm),
25358 cCE("cfsubd", e3004e0, 3, (RMD, RMD, RMD), rd_rn_rm),
25359 cCE("cfmuls", e100400, 3, (RMF, RMF, RMF), rd_rn_rm),
25360 cCE("cfmuld", e100420, 3, (RMD, RMD, RMD), rd_rn_rm),
25361 cCE("cfabs32", e300500, 2, (RMFX, RMFX), rd_rn),
25362 cCE("cfabs64", e300520, 2, (RMDX, RMDX), rd_rn),
25363 cCE("cfneg32", e300540, 2, (RMFX, RMFX), rd_rn),
25364 cCE("cfneg64", e300560, 2, (RMDX, RMDX), rd_rn),
25365 cCE("cfadd32", e300580, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25366 cCE("cfadd64", e3005a0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25367 cCE("cfsub32", e3005c0, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25368 cCE("cfsub64", e3005e0, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25369 cCE("cfmul32", e100500, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25370 cCE("cfmul64", e100520, 3, (RMDX, RMDX, RMDX), rd_rn_rm),
25371 cCE("cfmac32", e100540, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
25372 cCE("cfmsc32", e100560, 3, (RMFX, RMFX, RMFX), rd_rn_rm),
74db7efb
NC		 25373 cCE("cfmadd32",e000600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
25374 cCE("cfmsub32",e100600, 4, (RMAX, RMFX, RMFX, RMFX), mav_quad),
21d799b5
NC		 25375 cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
25376 cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
4ed7ed8d 25377
7fadb25d
SD		 25378 /* ARMv8.5-A instructions. */
25379#undef ARM_VARIANT
25380#define ARM_VARIANT & arm_ext_sb
25381#undef THUMB_VARIANT
25382#define THUMB_VARIANT & arm_ext_sb
25383 TUF("sb", 57ff070, f3bf8f70, 0, (), noargs, noargs),
25384
dad0c3bf
SD		 25385#undef ARM_VARIANT
25386#define ARM_VARIANT & arm_ext_predres
25387#undef THUMB_VARIANT
25388#define THUMB_VARIANT & arm_ext_predres
25389 CE("cfprctx", e070f93, 1, (RRnpc), rd),
25390 CE("dvprctx", e070fb3, 1, (RRnpc), rd),
25391 CE("cpprctx", e070ff3, 1, (RRnpc), rd),
25392
16a1fa25 25393 /* ARMv8-M instructions. */
4ed7ed8d
TP		 25394#undef ARM_VARIANT
25395#define ARM_VARIANT NULL
25396#undef THUMB_VARIANT
25397#define THUMB_VARIANT & arm_ext_v8m
cf3cf39d
TP		 25398 ToU("sg", e97fe97f, 0, (), noargs),
25399 ToC("blxns", 4784, 1, (RRnpc), t_blx),
25400 ToC("bxns", 4704, 1, (RRnpc), t_bx),
25401 ToC("tt", e840f000, 2, (RRnpc, RRnpc), tt),
25402 ToC("ttt", e840f040, 2, (RRnpc, RRnpc), tt),
25403 ToC("tta", e840f080, 2, (RRnpc, RRnpc), tt),
25404 ToC("ttat", e840f0c0, 2, (RRnpc, RRnpc), tt),
16a1fa25
TP		 25405
25406 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25407 instructions behave as nop if no VFP is present. */
25408#undef THUMB_VARIANT
25409#define THUMB_VARIANT & arm_ext_v8m_main
cf3cf39d
TP		 25410 ToC("vlldm", ec300a00, 1, (RRnpc), rn),
25411 ToC("vlstm", ec200a00, 1, (RRnpc), rn),
4389b29a
AV		 25412
25413 /* Armv8.1-M Mainline instructions. */
25414#undef THUMB_VARIANT
25415#define THUMB_VARIANT & arm_ext_v8_1m_main
e39c1607
SD		 25416 toU("cinc", _cinc, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25417 toU("cinv", _cinv, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25418 toU("cneg", _cneg, 3, (RRnpcsp, RR_ZR, COND), t_cond),
25419 toU("csel", _csel, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25420 toU("csetm", _csetm, 2, (RRnpcsp, COND), t_cond),
25421 toU("cset", _cset, 2, (RRnpcsp, COND), t_cond),
25422 toU("csinc", _csinc, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25423 toU("csinv", _csinv, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25424 toU("csneg", _csneg, 4, (RRnpcsp, RR_ZR, RR_ZR, COND), t_cond),
25425
4389b29a 25426 toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future),
f6b2b12d 25427 toU("bfcsel", _bfcsel, 4, (EXPs, EXPs, EXPs, COND), t_branch_future),
f1c7f421 25428 toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future),
65d1bc05 25429 toC("bfl", _bfl, 2, (EXPs, EXPs), t_branch_future),
f1c7f421 25430 toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future),
60f993ce
AV		 25431
25432 toU("dls", _dls, 2, (LR, RRnpcsp), t_loloop),
25433 toU("wls", _wls, 3, (LR, RRnpcsp, EXP), t_loloop),
25434 toU("le", _le, 2, (oLR, EXP), t_loloop),
4b5a202f 25435
efd6b359 25436 ToC("clrm", e89f0000, 1, (CLRMLST), t_clrm),
5ee91343
AV		 25437 ToC("vscclrm", ec9f0a00, 1, (VRSDVLST), t_vscclrm),
25438
25439#undef THUMB_VARIANT
25440#define THUMB_VARIANT & mve_ext
23d00a41
SD		 25441 ToC("lsll", ea50010d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
25442 ToC("lsrl", ea50011f, 3, (RRe, RRo, I32), mve_scalar_shift),
25443 ToC("asrl", ea50012d, 3, (RRe, RRo, RRnpcsp_I32), mve_scalar_shift),
08132bdd
SP		 25444 ToC("uqrshll", ea51010d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
25445 ToC("sqrshrl", ea51012d, 4, (RRe, RRo, I48_I64, RRnpcsp), mve_scalar_shift1),
23d00a41
SD		 25446 ToC("uqshll", ea51010f, 3, (RRe, RRo, I32), mve_scalar_shift),
25447 ToC("urshrl", ea51011f, 3, (RRe, RRo, I32), mve_scalar_shift),
25448 ToC("srshrl", ea51012f, 3, (RRe, RRo, I32), mve_scalar_shift),
25449 ToC("sqshll", ea51013f, 3, (RRe, RRo, I32), mve_scalar_shift),
25450 ToC("uqrshl", ea500f0d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
25451 ToC("sqrshr", ea500f2d, 2, (RRnpcsp, RRnpcsp), mve_scalar_shift),
25452 ToC("uqshl", ea500f0f, 2, (RRnpcsp, I32), mve_scalar_shift),
25453 ToC("urshr", ea500f1f, 2, (RRnpcsp, I32), mve_scalar_shift),
25454 ToC("srshr", ea500f2f, 2, (RRnpcsp, I32), mve_scalar_shift),
25455 ToC("sqshl", ea500f3f, 2, (RRnpcsp, I32), mve_scalar_shift),
1b883319
AV		 25456
25457 ToC("vpt", ee410f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25458 ToC("vptt", ee018f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25459 ToC("vpte", ee418f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25460 ToC("vpttt", ee014f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25461 ToC("vptte", ee01cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25462 ToC("vptet", ee41cf00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25463 ToC("vptee", ee414f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25464 ToC("vptttt", ee012f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25465 ToC("vpttte", ee016f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25466 ToC("vpttet", ee01ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25467 ToC("vpttee", ee01af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25468 ToC("vptett", ee41af00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25469 ToC("vptete", ee41ef00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25470 ToC("vpteet", ee416f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25471 ToC("vpteee", ee412f00, 3, (COND, RMQ, RMQRZ), mve_vpt),
25472
5ee91343
AV		 25473 ToC("vpst", fe710f4d, 0, (), mve_vpt),
25474 ToC("vpstt", fe318f4d, 0, (), mve_vpt),
25475 ToC("vpste", fe718f4d, 0, (), mve_vpt),
25476 ToC("vpsttt", fe314f4d, 0, (), mve_vpt),
25477 ToC("vpstte", fe31cf4d, 0, (), mve_vpt),
25478 ToC("vpstet", fe71cf4d, 0, (), mve_vpt),
25479 ToC("vpstee", fe714f4d, 0, (), mve_vpt),
25480 ToC("vpstttt", fe312f4d, 0, (), mve_vpt),
25481 ToC("vpsttte", fe316f4d, 0, (), mve_vpt),
25482 ToC("vpsttet", fe31ef4d, 0, (), mve_vpt),
25483 ToC("vpsttee", fe31af4d, 0, (), mve_vpt),
25484 ToC("vpstett", fe71af4d, 0, (), mve_vpt),
25485 ToC("vpstete", fe71ef4d, 0, (), mve_vpt),
25486 ToC("vpsteet", fe716f4d, 0, (), mve_vpt),
25487 ToC("vpsteee", fe712f4d, 0, (), mve_vpt),
25488
a302e574 25489 /* MVE and MVE FP only. */
7df54120 25490 mToC("vhcadd", ee000f00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vhcadd),
c2dafc2a
AV		 25491 mCEF(vadc, _vadc, 3, (RMQ, RMQ, RMQ), mve_vadc),
25492 mCEF(vadci, _vadci, 3, (RMQ, RMQ, RMQ), mve_vadc),
25493 mToC("vsbc", fe300f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
25494 mToC("vsbci", fe301f00, 3, (RMQ, RMQ, RMQ), mve_vsbc),
886e1c73 25495 mCEF(vmullb, _vmullb, 3, (RMQ, RMQ, RMQ), mve_vmull),
a302e574
AV		 25496 mCEF(vabav, _vabav, 3, (RRnpcsp, RMQ, RMQ), mve_vabav),
25497 mCEF(vmladav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25498 mCEF(vmladava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25499 mCEF(vmladavx, _vmladavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25500 mCEF(vmladavax, _vmladavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25501 mCEF(vmlav, _vmladav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25502 mCEF(vmlava, _vmladava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25503 mCEF(vmlsdav, _vmlsdav, 3, (RRe, RMQ, RMQ), mve_vmladav),
25504 mCEF(vmlsdava, _vmlsdava, 3, (RRe, RMQ, RMQ), mve_vmladav),
25505 mCEF(vmlsdavx, _vmlsdavx, 3, (RRe, RMQ, RMQ), mve_vmladav),
25506 mCEF(vmlsdavax, _vmlsdavax, 3, (RRe, RMQ, RMQ), mve_vmladav),
25507
35c228db
AV		 25508 mCEF(vst20, _vst20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25509 mCEF(vst21, _vst21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25510 mCEF(vst40, _vst40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25511 mCEF(vst41, _vst41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25512 mCEF(vst42, _vst42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25513 mCEF(vst43, _vst43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25514 mCEF(vld20, _vld20, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25515 mCEF(vld21, _vld21, 2, (MSTRLST2, ADDRMVE), mve_vst_vld),
25516 mCEF(vld40, _vld40, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25517 mCEF(vld41, _vld41, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25518 mCEF(vld42, _vld42, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
25519 mCEF(vld43, _vld43, 2, (MSTRLST4, ADDRMVE), mve_vst_vld),
f5f10c66
AV		 25520 mCEF(vstrb, _vstrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25521 mCEF(vstrh, _vstrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25522 mCEF(vstrw, _vstrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25523 mCEF(vstrd, _vstrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25524 mCEF(vldrb, _vldrb, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25525 mCEF(vldrh, _vldrh, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25526 mCEF(vldrw, _vldrw, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
25527 mCEF(vldrd, _vldrd, 2, (RMQ, ADDRMVE), mve_vstr_vldr),
35c228db 25528
57785aa2
AV		 25529 mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
25530 mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
c2dafc2a 25531 mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
26c1e780
AV		 25532 mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
25533 mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
25534 mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
25535 mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
b409bdb6
AV		 25536 mCEF(vddup, _vddup, 3, (RMQ, RRe, EXPi), mve_viddup),
25537 mCEF(vdwdup, _vdwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
25538 mCEF(vidup, _vidup, 3, (RMQ, RRe, EXPi), mve_viddup),
25539 mCEF(viwdup, _viwdup, 4, (RMQ, RRe, RR, EXPi), mve_viddup),
935295b5
AV		 25540 mToC("vmaxa", ee330e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
25541 mToC("vmina", ee331e81, 2, (RMQ, RMQ), mve_vmaxa_vmina),
13ccd4c0
AV		 25542 mCEF(vmaxv, _vmaxv, 2, (RR, RMQ), mve_vmaxv),
25543 mCEF(vmaxav, _vmaxav, 2, (RR, RMQ), mve_vmaxv),
25544 mCEF(vminv, _vminv, 2, (RR, RMQ), mve_vmaxv),
25545 mCEF(vminav, _vminav, 2, (RR, RMQ), mve_vmaxv),
57785aa2 25546
93925576
AV		 25547 mCEF(vmlaldav, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25548 mCEF(vmlaldava, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25549 mCEF(vmlaldavx, _vmlaldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25550 mCEF(vmlaldavax, _vmlaldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25551 mCEF(vmlalv, _vmlaldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25552 mCEF(vmlalva, _vmlaldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25553 mCEF(vmlsldav, _vmlsldav, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25554 mCEF(vmlsldava, _vmlsldava, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25555 mCEF(vmlsldavx, _vmlsldavx, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25556 mCEF(vmlsldavax, _vmlsldavax, 4, (RRe, RRo, RMQ, RMQ), mve_vmlaldav),
25557 mToC("vrmlaldavh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25558 mToC("vrmlaldavha",ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25559 mCEF(vrmlaldavhx, _vrmlaldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25560 mCEF(vrmlaldavhax, _vrmlaldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25561 mToC("vrmlalvh", ee800f00, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25562 mToC("vrmlalvha", ee800f20, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25563 mCEF(vrmlsldavh, _vrmlsldavh, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25564 mCEF(vrmlsldavha, _vrmlsldavha, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25565 mCEF(vrmlsldavhx, _vrmlsldavhx, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25566 mCEF(vrmlsldavhax, _vrmlsldavhax, 4, (RRe, RR, RMQ, RMQ), mve_vrmlaldavh),
25567
2d78f95b
AV		 25568 mToC("vmlas", ee011e40, 3, (RMQ, RMQ, RR), mve_vmlas),
25569 mToC("vmulh", ee010e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
25570 mToC("vrmulh", ee011e01, 3, (RMQ, RMQ, RMQ), mve_vmulh),
3063888e
AV		 25571 mToC("vpnot", fe310f4d, 0, (), mve_vpnot),
25572 mToC("vpsel", fe310f01, 3, (RMQ, RMQ, RMQ), mve_vpsel),
2d78f95b 25573
8b8b22a4
AV		 25574 mToC("vqdmladh", ee000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25575 mToC("vqdmladhx", ee001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25576 mToC("vqrdmladh", ee000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25577 mToC("vqrdmladhx",ee001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25578 mToC("vqdmlsdh", fe000e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25579 mToC("vqdmlsdhx", fe001e00, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25580 mToC("vqrdmlsdh", fe000e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
25581 mToC("vqrdmlsdhx",fe001e01, 3, (RMQ, RMQ, RMQ), mve_vqdmladh),
42b16635
AV		 25582 mToC("vqdmlah", ee000e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25583 mToC("vqdmlash", ee001e60, 3, (RMQ, RMQ, RR), mve_vqdmlah),
25584 mToC("vqrdmlash", ee001e40, 3, (RMQ, RMQ, RR), mve_vqdmlah),
35d1cfc2
AV		 25585 mToC("vqdmullt", ee301f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
25586 mToC("vqdmullb", ee300f00, 3, (RMQ, RMQ, RMQRR), mve_vqdmull),
1be7aba3
AV		 25587 mCEF(vqmovnt, _vqmovnt, 2, (RMQ, RMQ), mve_vqmovn),
25588 mCEF(vqmovnb, _vqmovnb, 2, (RMQ, RMQ), mve_vqmovn),
25589 mCEF(vqmovunt, _vqmovunt, 2, (RMQ, RMQ), mve_vqmovn),
25590 mCEF(vqmovunb, _vqmovunb, 2, (RMQ, RMQ), mve_vqmovn),
8b8b22a4 25591
4aa88b50
AV		 25592 mCEF(vshrnt, _vshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25593 mCEF(vshrnb, _vshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25594 mCEF(vrshrnt, _vrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25595 mCEF(vrshrnb, _vrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25596 mCEF(vqshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25597 mCEF(vqshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25598 mCEF(vqshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25599 mCEF(vqshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25600 mCEF(vqrshrnt, _vqrshrnt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25601 mCEF(vqrshrnb, _vqrshrnb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25602 mCEF(vqrshrunt, _vqrshrunt, 3, (RMQ, RMQ, I32z), mve_vshrn),
25603 mCEF(vqrshrunb, _vqrshrunb, 3, (RMQ, RMQ, I32z), mve_vshrn),
25604
acca5630
AV		 25605 mToC("vshlc", eea00fc0, 3, (RMQ, RR, I32z), mve_vshlc),
25606 mToC("vshllt", ee201e00, 3, (RMQ, RMQ, I32), mve_vshll),
25607 mToC("vshllb", ee200e00, 3, (RMQ, RMQ, I32), mve_vshll),
25608
1f6234a3
AV		 25609 toU("dlstp", _dlstp, 2, (LR, RR), t_loloop),
25610 toU("wlstp", _wlstp, 3, (LR, RR, EXP), t_loloop),
25611 toU("letp", _letp, 2, (LR, EXP), t_loloop),
25612 toU("lctp", _lctp, 0, (), t_loloop),
25613
5d281bf0
AV		 25614#undef THUMB_VARIANT
25615#define THUMB_VARIANT & mve_fp_ext
25616 mToC("vcmul", ee300e00, 4, (RMQ, RMQ, RMQ, EXPi), mve_vcmul),
f30ee27c 25617 mToC("vfmas", ee311e40, 3, (RMQ, RMQ, RR), mve_vfmas),
935295b5
AV		 25618 mToC("vmaxnma", ee3f0e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
25619 mToC("vminnma", ee3f1e81, 2, (RMQ, RMQ), mve_vmaxnma_vminnma),
8cd78170
AV		 25620 mToC("vmaxnmv", eeee0f00, 2, (RR, RMQ), mve_vmaxnmv),
25621 mToC("vmaxnmav",eeec0f00, 2, (RR, RMQ), mve_vmaxnmv),
25622 mToC("vminnmv", eeee0f80, 2, (RR, RMQ), mve_vmaxnmv),
25623 mToC("vminnmav",eeec0f80, 2, (RR, RMQ), mve_vmaxnmv),
5d281bf0 25624
5ee91343 25625#undef ARM_VARIANT
57785aa2 25626#define ARM_VARIANT & fpu_vfp_ext_v1
5ee91343
AV		 25627#undef THUMB_VARIANT
25628#define THUMB_VARIANT & arm_ext_v6t2
a8465a06
AV		 25629 mnCEF(vmla, _vmla, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mac_maybe_scalar),
25630 mnCEF(vmul, _vmul, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ_RR), neon_mul),
5ee91343 25631
57785aa2
AV		 25632 mcCE(fcpyd, eb00b40, 2, (RVD, RVD), vfp_dp_rd_rm),
25633
25634#undef ARM_VARIANT
25635#define ARM_VARIANT & fpu_vfp_ext_v1xd
25636
25637 MNCE(vmov, 0, 1, (VMOV), neon_mov),
25638 mcCE(fmrs, e100a10, 2, (RR, RVS), vfp_reg_from_sp),
25639 mcCE(fmsr, e000a10, 2, (RVS, RR), vfp_sp_from_reg),
25640 mcCE(fcpys, eb00a40, 2, (RVS, RVS), vfp_sp_monadic),
25641
886e1c73
AV		 25642 mCEF(vmullt, _vmullt, 3, (RNSDQMQ, oRNSDQMQ, RNSDQ_RNSC_MQ), mve_vmull),
25643 mnCEF(vadd, _vadd, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
25644 mnCEF(vsub, _vsub, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQR), neon_addsub_if_i),
5ee91343 25645
485dee97
AV		 25646 MNCEF(vabs, 1b10300, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25647 MNCEF(vneg, 1b10380, 2, (RNSDQMQ, RNSDQMQ), neon_abs_neg),
25648
57785aa2
AV		 25649 mCEF(vmovlt, _vmovlt, 1, (VMOV), mve_movl),
25650 mCEF(vmovlb, _vmovlb, 1, (VMOV), mve_movl),
25651
1b883319
AV		 25652 mnCE(vcmp, _vcmp, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25653 mnCE(vcmpe, _vcmpe, 3, (RVSD_COND, RSVDMQ_FI0, oRMQRZ), vfp_nsyn_cmp),
25654
57785aa2
AV		 25655#undef ARM_VARIANT
25656#define ARM_VARIANT & fpu_vfp_ext_v2
25657
25658 mcCE(fmsrr, c400a10, 3, (VRSLST, RR, RR), vfp_sp2_from_reg2),
25659 mcCE(fmrrs, c500a10, 3, (RR, RR, VRSLST), vfp_reg2_from_sp2),
25660 mcCE(fmdrr, c400b10, 3, (RVD, RR, RR), vfp_dp_rm_rd_rn),
25661 mcCE(fmrrd, c500b10, 3, (RR, RR, RVD), vfp_dp_rd_rn_rm),
25662
dd9634d9
AV		 25663#undef ARM_VARIANT
25664#define ARM_VARIANT & fpu_vfp_ext_armv8xd
25665 mnUF(vcvta, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvta),
25666 mnUF(vcvtp, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtp),
25667 mnUF(vcvtn, _vcvta, 3, (RNSDQMQ, oRNSDQMQ, oI32z), neon_cvtn),
25668 mnUF(vcvtm, _vcvta, 2, (RNSDQMQ, oRNSDQMQ), neon_cvtm),
935295b5
AV		 25669 mnUF(vmaxnm, _vmaxnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
25670 mnUF(vminnm, _vminnm, 3, (RNSDQMQ, oRNSDQMQ, RNSDQMQ), vmaxnm),
dd9634d9
AV		 25671
25672#undef ARM_VARIANT
5ee91343 25673#define ARM_VARIANT & fpu_neon_ext_v1
f601a00c 25674 mnUF(vabd, _vabd, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
5ee91343
AV		 25675 mnUF(vabdl, _vabdl, 3, (RNQMQ, RNDMQ, RNDMQ), neon_dyadic_long),
25676 mnUF(vaddl, _vaddl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
25677 mnUF(vsubl, _vsubl, 3, (RNQMQ, RNDMQ, RNDMQR), neon_dyadic_long),
f601a00c
AV		 25678 mnUF(vand, _vand, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25679 mnUF(vbic, _vbic, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25680 mnUF(vorr, _vorr, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25681 mnUF(vorn, _vorn, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_Ibig), neon_logic),
25682 mnUF(veor, _veor, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_logic),
f30ee27c
AV		 25683 MNUF(vcls, 1b00400, 2, (RNDQMQ, RNDQMQ), neon_cls),
25684 MNUF(vclz, 1b00480, 2, (RNDQMQ, RNDQMQ), neon_clz),
b409bdb6 25685 mnCE(vdup, _vdup, 2, (RNDQMQ, RR_RNSC), neon_dup),
7df54120
AV		 25686 MNUF(vhadd, 00000000, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
25687 MNUF(vrhadd, 00000100, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_i_su),
25688 MNUF(vhsub, 00000200, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i_su),
935295b5
AV		 25689 mnUF(vmin, _vmin, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
25690 mnUF(vmax, _vmax, 3, (RNDQMQ, oRNDQMQ, RNDQMQ), neon_dyadic_if_su),
a8465a06
AV		 25691 MNUF(vqadd, 0000010, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
25692 MNUF(vqsub, 0000210, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_dyadic_i64_su),
1a186d29
AV		 25693 mnUF(vmvn, _vmvn, 2, (RNDQMQ, RNDQMQ_Ibig), neon_mvn),
25694 MNUF(vqabs, 1b00700, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
25695 MNUF(vqneg, 1b00780, 2, (RNDQMQ, RNDQMQ), neon_sat_abs_neg),
42b16635
AV		 25696 mnUF(vqrdmlah, _vqrdmlah,3, (RNDQMQ, oRNDQMQ, RNDQ_RNSC_RR), neon_qrdmlah),
25697 mnUF(vqdmulh, _vqdmulh, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
25698 mnUF(vqrdmulh, _vqrdmulh,3, (RNDQMQ, oRNDQMQ, RNDQMQ_RNSC_RR), neon_qdmulh),
1be7aba3
AV		 25699 MNUF(vqrshl, 0000510, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
25700 MNUF(vrshl, 0000500, 3, (RNDQMQ, oRNDQMQ, RNDQMQR), neon_rshl),
4401c241
AV		 25701 MNUF(vshr, 0800010, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25702 MNUF(vrshr, 0800210, 3, (RNDQMQ, oRNDQMQ, I64z), neon_rshift_round_imm),
25703 MNUF(vsli, 1800510, 3, (RNDQMQ, oRNDQMQ, I63), neon_sli),
25704 MNUF(vsri, 1800410, 3, (RNDQMQ, oRNDQMQ, I64z), neon_sri),
25705 MNUF(vrev64, 1b00000, 2, (RNDQMQ, RNDQMQ), neon_rev),
25706 MNUF(vrev32, 1b00080, 2, (RNDQMQ, RNDQMQ), neon_rev),
25707 MNUF(vrev16, 1b00100, 2, (RNDQMQ, RNDQMQ), neon_rev),
5150f0d8
AV		 25708 mnUF(vshl, _vshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_shl),
25709 mnUF(vqshl, _vqshl, 3, (RNDQMQ, oRNDQMQ, RNDQMQ_I63b_RR), neon_qshl),
25710 MNUF(vqshlu, 1800610, 3, (RNDQMQ, oRNDQMQ, I63), neon_qshlu_imm),
5d281bf0
AV		 25711
25712#undef ARM_VARIANT
25713#define ARM_VARIANT & arm_ext_v8_3
25714#undef THUMB_VARIANT
25715#define THUMB_VARIANT & arm_ext_v6t2_v8m
25716 MNUF (vcadd, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ, EXPi), vcadd),
25717 MNUF (vcmla, 0, 4, (RNDQMQ, RNDQMQ, RNDQMQ_RNSC, EXPi), vcmla),
c19d1205
ZW		 25718};
25719#undef ARM_VARIANT
25720#undef THUMB_VARIANT
25721#undef TCE
c19d1205
ZW		 25722#undef TUE
25723#undef TUF
25724#undef TCC
8f06b2d8 25725#undef cCE
e3cb604e
PB		 25726#undef cCL
25727#undef C3E
4389b29a 25728#undef C3
c19d1205
ZW		 25729#undef CE
25730#undef CM
4389b29a 25731#undef CL
c19d1205
ZW		 25732#undef UE
25733#undef UF
25734#undef UT
5287ad62
JB		 25735#undef NUF
25736#undef nUF
25737#undef NCE
25738#undef nCE
c19d1205
ZW		 25739#undef OPS0
25740#undef OPS1
25741#undef OPS2
25742#undef OPS3
25743#undef OPS4
25744#undef OPS5
25745#undef OPS6
25746#undef do_0
4389b29a
AV		 25747#undef ToC
25748#undef toC
25749#undef ToU
f6b2b12d 25750#undef toU
c19d1205
ZW		 25751\f
25752/* MD interface: bits in the object file. */
bfae80f2 25753
c19d1205
ZW		 25754/* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25755 for use in the a.out file, and stores them in the array pointed to by buf.
25756 This knows about the endian-ness of the target machine and does
25757 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25758 2 (short) and 4 (long) Floating numbers are put out as a series of
25759 LITTLENUMS (shorts, here at least). */
b99bd4ef 25760
c19d1205
ZW		 25761void
25762md_number_to_chars (char * buf, valueT val, int n)
25763{
25764 if (target_big_endian)
25765 number_to_chars_bigendian (buf, val, n);
25766 else
25767 number_to_chars_littleendian (buf, val, n);
bfae80f2
RE		 25768}
25769
c19d1205
ZW		 25770static valueT
25771md_chars_to_number (char * buf, int n)
bfae80f2 25772{
c19d1205
ZW		 25773 valueT result = 0;
25774 unsigned char * where = (unsigned char *) buf;
bfae80f2 25775
c19d1205 25776 if (target_big_endian)
b99bd4ef 25777 {
c19d1205
ZW		 25778 while (n--)
25779 {
25780 result <<= 8;
25781 result |= (*where++ & 255);
25782 }
b99bd4ef 25783 }
c19d1205 25784 else
b99bd4ef 25785 {
c19d1205
ZW		 25786 while (n--)
25787 {
25788 result <<= 8;
25789 result |= (where[n] & 255);
25790 }
bfae80f2 25791 }
b99bd4ef 25792
c19d1205 25793 return result;
bfae80f2 25794}
b99bd4ef 25795
c19d1205 25796/* MD interface: Sections. */
b99bd4ef 25797
fa94de6b
RM		 25798/* Calculate the maximum variable size (i.e., excluding fr_fix)
25799 that an rs_machine_dependent frag may reach. */
25800
25801unsigned int
25802arm_frag_max_var (fragS *fragp)
25803{
25804 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25805 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25806
25807 Note that we generate relaxable instructions even for cases that don't
25808 really need it, like an immediate that's a trivial constant. So we're
25809 overestimating the instruction size for some of those cases. Rather
25810 than putting more intelligence here, it would probably be better to
25811 avoid generating a relaxation frag in the first place when it can be
25812 determined up front that a short instruction will suffice. */
25813
25814 gas_assert (fragp->fr_type == rs_machine_dependent);
25815 return INSN_SIZE;
25816}
25817
0110f2b8
PB		 25818/* Estimate the size of a frag before relaxing. Assume everything fits in
25819 2 bytes. */
25820
c19d1205 25821int
0110f2b8 25822md_estimate_size_before_relax (fragS * fragp,
c19d1205
ZW		 25823 segT segtype ATTRIBUTE_UNUSED)
25824{
0110f2b8
PB		 25825 fragp->fr_var = 2;
25826 return 2;
25827}
25828
25829/* Convert a machine dependent frag. */
25830
25831void
25832md_convert_frag (bfd *abfd, segT asec ATTRIBUTE_UNUSED, fragS *fragp)
25833{
25834 unsigned long insn;
25835 unsigned long old_op;
25836 char *buf;
25837 expressionS exp;
25838 fixS *fixp;
25839 int reloc_type;
25840 int pc_rel;
25841 int opcode;
25842
25843 buf = fragp->fr_literal + fragp->fr_fix;
25844
25845 old_op = bfd_get_16(abfd, buf);
5f4273c7
NC		 25846 if (fragp->fr_symbol)
25847 {
0110f2b8
PB		 25848 exp.X_op = O_symbol;
25849 exp.X_add_symbol = fragp->fr_symbol;
5f4273c7
NC		 25850 }
25851 else
25852 {
0110f2b8 25853 exp.X_op = O_constant;
5f4273c7 25854 }
0110f2b8
PB		 25855 exp.X_add_number = fragp->fr_offset;
25856 opcode = fragp->fr_subtype;
25857 switch (opcode)
25858 {
25859 case T_MNEM_ldr_pc:
25860 case T_MNEM_ldr_pc2:
25861 case T_MNEM_ldr_sp:
25862 case T_MNEM_str_sp:
25863 case T_MNEM_ldr:
25864 case T_MNEM_ldrb:
25865 case T_MNEM_ldrh:
25866 case T_MNEM_str:
25867 case T_MNEM_strb:
25868 case T_MNEM_strh:
25869 if (fragp->fr_var == 4)
25870 {
5f4273c7 25871 insn = THUMB_OP32 (opcode);
0110f2b8
PB		 25872 if ((old_op >> 12) == 4 || (old_op >> 12) == 9)
25873 {
25874 insn |= (old_op & 0x700) << 4;
25875 }
25876 else
25877 {
25878 insn |= (old_op & 7) << 12;
25879 insn |= (old_op & 0x38) << 13;
25880 }
25881 insn |= 0x00000c00;
25882 put_thumb32_insn (buf, insn);
25883 reloc_type = BFD_RELOC_ARM_T32_OFFSET_IMM;
25884 }
25885 else
25886 {
25887 reloc_type = BFD_RELOC_ARM_THUMB_OFFSET;
25888 }
25889 pc_rel = (opcode == T_MNEM_ldr_pc2);
25890 break;
25891 case T_MNEM_adr:
25892 if (fragp->fr_var == 4)
25893 {
25894 insn = THUMB_OP32 (opcode);
25895 insn |= (old_op & 0xf0) << 4;
25896 put_thumb32_insn (buf, insn);
25897 reloc_type = BFD_RELOC_ARM_T32_ADD_PC12;
25898 }
25899 else
25900 {
25901 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25902 exp.X_add_number -= 4;
25903 }
25904 pc_rel = 1;
25905 break;
25906 case T_MNEM_mov:
25907 case T_MNEM_movs:
25908 case T_MNEM_cmp:
25909 case T_MNEM_cmn:
25910 if (fragp->fr_var == 4)
25911 {
25912 int r0off = (opcode == T_MNEM_mov
25913 || opcode == T_MNEM_movs) ? 0 : 8;
25914 insn = THUMB_OP32 (opcode);
25915 insn = (insn & 0xe1ffffff) | 0x10000000;
25916 insn |= (old_op & 0x700) << r0off;
25917 put_thumb32_insn (buf, insn);
25918 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
25919 }
25920 else
25921 {
25922 reloc_type = BFD_RELOC_ARM_THUMB_IMM;
25923 }
25924 pc_rel = 0;
25925 break;
25926 case T_MNEM_b:
25927 if (fragp->fr_var == 4)
25928 {
25929 insn = THUMB_OP32(opcode);
25930 put_thumb32_insn (buf, insn);
25931 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH25;
25932 }
25933 else
25934 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH12;
25935 pc_rel = 1;
25936 break;
25937 case T_MNEM_bcond:
25938 if (fragp->fr_var == 4)
25939 {
25940 insn = THUMB_OP32(opcode);
25941 insn |= (old_op & 0xf00) << 14;
25942 put_thumb32_insn (buf, insn);
25943 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH20;
25944 }
25945 else
25946 reloc_type = BFD_RELOC_THUMB_PCREL_BRANCH9;
25947 pc_rel = 1;
25948 break;
25949 case T_MNEM_add_sp:
25950 case T_MNEM_add_pc:
25951 case T_MNEM_inc_sp:
25952 case T_MNEM_dec_sp:
25953 if (fragp->fr_var == 4)
25954 {
25955 /* ??? Choose between add and addw. */
25956 insn = THUMB_OP32 (opcode);
25957 insn |= (old_op & 0xf0) << 4;
25958 put_thumb32_insn (buf, insn);
16805f35
PB		 25959 if (opcode == T_MNEM_add_pc)
25960 reloc_type = BFD_RELOC_ARM_T32_IMM12;
25961 else
25962 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
0110f2b8
PB		 25963 }
25964 else
25965 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25966 pc_rel = 0;
25967 break;
25968
25969 case T_MNEM_addi:
25970 case T_MNEM_addis:
25971 case T_MNEM_subi:
25972 case T_MNEM_subis:
25973 if (fragp->fr_var == 4)
25974 {
25975 insn = THUMB_OP32 (opcode);
25976 insn |= (old_op & 0xf0) << 4;
25977 insn |= (old_op & 0xf) << 16;
25978 put_thumb32_insn (buf, insn);
16805f35
PB		 25979 if (insn & (1 << 20))
25980 reloc_type = BFD_RELOC_ARM_T32_ADD_IMM;
25981 else
25982 reloc_type = BFD_RELOC_ARM_T32_IMMEDIATE;
0110f2b8
PB		 25983 }
25984 else
25985 reloc_type = BFD_RELOC_ARM_THUMB_ADD;
25986 pc_rel = 0;
25987 break;
25988 default:
5f4273c7 25989 abort ();
0110f2b8
PB		 25990 }
25991 fixp = fix_new_exp (fragp, fragp->fr_fix, fragp->fr_var, &exp, pc_rel,
21d799b5 25992 (enum bfd_reloc_code_real) reloc_type);
0110f2b8
PB		 25993 fixp->fx_file = fragp->fr_file;
25994 fixp->fx_line = fragp->fr_line;
25995 fragp->fr_fix += fragp->fr_var;
3cfdb781
TG		 25996
25997 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25998 if (thumb_mode && fragp->fr_var == 4 && no_cpu_selected ()
25999 && !ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_t2))
26000 ARM_MERGE_FEATURE_SETS (arm_arch_used, thumb_arch_used, arm_ext_v6t2);
0110f2b8
PB		 26001}
26002
26003/* Return the size of a relaxable immediate operand instruction.
26004 SHIFT and SIZE specify the form of the allowable immediate. */
26005static int
26006relax_immediate (fragS *fragp, int size, int shift)
26007{
26008 offsetT offset;
26009 offsetT mask;
26010 offsetT low;
26011
26012 /* ??? Should be able to do better than this. */
26013 if (fragp->fr_symbol)
26014 return 4;
26015
26016 low = (1 << shift) - 1;
26017 mask = (1 << (shift + size)) - (1 << shift);
26018 offset = fragp->fr_offset;
26019 /* Force misaligned offsets to 32-bit variant. */
26020 if (offset & low)
5e77afaa 26021 return 4;
0110f2b8
PB		 26022 if (offset & ~mask)
26023 return 4;
26024 return 2;
26025}
26026
5e77afaa
PB		 26027/* Get the address of a symbol during relaxation. */
26028static addressT
5f4273c7 26029relaxed_symbol_addr (fragS *fragp, long stretch)
5e77afaa
PB		 26030{
26031 fragS *sym_frag;
26032 addressT addr;
26033 symbolS *sym;
26034
26035 sym = fragp->fr_symbol;
26036 sym_frag = symbol_get_frag (sym);
26037 know (S_GET_SEGMENT (sym) != absolute_section
26038 || sym_frag == &zero_address_frag);
26039 addr = S_GET_VALUE (sym) + fragp->fr_offset;
26040
26041 /* If frag has yet to be reached on this pass, assume it will
26042 move by STRETCH just as we did. If this is not so, it will
26043 be because some frag between grows, and that will force
26044 another pass. */
26045
26046 if (stretch != 0
26047 && sym_frag->relax_marker != fragp->relax_marker)
4396b686
PB		 26048 {
26049 fragS *f;
26050
26051 /* Adjust stretch for any alignment frag. Note that if have
26052 been expanding the earlier code, the symbol may be
26053 defined in what appears to be an earlier frag. FIXME:
26054 This doesn't handle the fr_subtype field, which specifies
26055 a maximum number of bytes to skip when doing an
26056 alignment. */
26057 for (f = fragp; f != NULL && f != sym_frag; f = f->fr_next)
26058 {
26059 if (f->fr_type == rs_align || f->fr_type == rs_align_code)
26060 {
26061 if (stretch < 0)
26062 stretch = - ((- stretch)
26063 & ~ ((1 << (int) f->fr_offset) - 1));
26064 else
26065 stretch &= ~ ((1 << (int) f->fr_offset) - 1);
26066 if (stretch == 0)
26067 break;
26068 }
26069 }
26070 if (f != NULL)
26071 addr += stretch;
26072 }
5e77afaa
PB		 26073
26074 return addr;
26075}
26076
0110f2b8
PB		 26077/* Return the size of a relaxable adr pseudo-instruction or PC-relative
26078 load. */
26079static int
5e77afaa 26080relax_adr (fragS *fragp, asection *sec, long stretch)
0110f2b8
PB		 26081{
26082 addressT addr;
26083 offsetT val;
26084
26085 /* Assume worst case for symbols not known to be in the same section. */
974da60d
NC		 26086 if (fragp->fr_symbol == NULL
26087 || !S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 26088 || sec != S_GET_SEGMENT (fragp->fr_symbol)
26089 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 26090 return 4;
26091
5f4273c7 26092 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 26093 addr = fragp->fr_address + fragp->fr_fix;
26094 addr = (addr + 4) & ~3;
5e77afaa 26095 /* Force misaligned targets to 32-bit variant. */
0110f2b8 26096 if (val & 3)
5e77afaa 26097 return 4;
0110f2b8
PB		 26098 val -= addr;
26099 if (val < 0 || val > 1020)
26100 return 4;
26101 return 2;
26102}
26103
26104/* Return the size of a relaxable add/sub immediate instruction. */
26105static int
26106relax_addsub (fragS *fragp, asection *sec)
26107{
26108 char *buf;
26109 int op;
26110
26111 buf = fragp->fr_literal + fragp->fr_fix;
26112 op = bfd_get_16(sec->owner, buf);
26113 if ((op & 0xf) == ((op >> 4) & 0xf))
26114 return relax_immediate (fragp, 8, 0);
26115 else
26116 return relax_immediate (fragp, 3, 0);
26117}
26118
e83a675f
RE		 26119/* Return TRUE iff the definition of symbol S could be pre-empted
26120 (overridden) at link or load time. */
26121static bfd_boolean
26122symbol_preemptible (symbolS *s)
26123{
26124 /* Weak symbols can always be pre-empted. */
26125 if (S_IS_WEAK (s))
26126 return TRUE;
26127
26128 /* Non-global symbols cannot be pre-empted. */
26129 if (! S_IS_EXTERNAL (s))
26130 return FALSE;
26131
26132#ifdef OBJ_ELF
26133 /* In ELF, a global symbol can be marked protected, or private. In that
26134 case it can't be pre-empted (other definitions in the same link unit
26135 would violate the ODR). */
26136 if (ELF_ST_VISIBILITY (S_GET_OTHER (s)) > STV_DEFAULT)
26137 return FALSE;
26138#endif
26139
26140 /* Other global symbols might be pre-empted. */
26141 return TRUE;
26142}
0110f2b8
PB		 26143
26144/* Return the size of a relaxable branch instruction. BITS is the
26145 size of the offset field in the narrow instruction. */
26146
26147static int
5e77afaa 26148relax_branch (fragS *fragp, asection *sec, int bits, long stretch)
0110f2b8
PB		 26149{
26150 addressT addr;
26151 offsetT val;
26152 offsetT limit;
26153
26154 /* Assume worst case for symbols not known to be in the same section. */
5f4273c7 26155 if (!S_IS_DEFINED (fragp->fr_symbol)
77db8e2e
NC		 26156 || sec != S_GET_SEGMENT (fragp->fr_symbol)
26157 || S_IS_WEAK (fragp->fr_symbol))
0110f2b8
PB		 26158 return 4;
26159
267bf995 26160#ifdef OBJ_ELF
e83a675f 26161 /* A branch to a function in ARM state will require interworking. */
267bf995
RR		 26162 if (S_IS_DEFINED (fragp->fr_symbol)
26163 && ARM_IS_FUNC (fragp->fr_symbol))
26164 return 4;
e83a675f 26165#endif
0d9b4b55 26166
e83a675f 26167 if (symbol_preemptible (fragp->fr_symbol))
0d9b4b55 26168 return 4;
267bf995 26169
5f4273c7 26170 val = relaxed_symbol_addr (fragp, stretch);
0110f2b8
PB		 26171 addr = fragp->fr_address + fragp->fr_fix + 4;
26172 val -= addr;
26173
26174 /* Offset is a signed value *2 */
26175 limit = 1 << bits;
26176 if (val >= limit || val < -limit)
26177 return 4;
26178 return 2;
26179}
26180
26181
26182/* Relax a machine dependent frag. This returns the amount by which
26183 the current size of the frag should change. */
26184
26185int
5e77afaa 26186arm_relax_frag (asection *sec, fragS *fragp, long stretch)
0110f2b8
PB		 26187{
26188 int oldsize;
26189 int newsize;
26190
26191 oldsize = fragp->fr_var;
26192 switch (fragp->fr_subtype)
26193 {
26194 case T_MNEM_ldr_pc2:
5f4273c7 26195 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 26196 break;
26197 case T_MNEM_ldr_pc:
26198 case T_MNEM_ldr_sp:
26199 case T_MNEM_str_sp:
5f4273c7 26200 newsize = relax_immediate (fragp, 8, 2);
0110f2b8
PB		 26201 break;
26202 case T_MNEM_ldr:
26203 case T_MNEM_str:
5f4273c7 26204 newsize = relax_immediate (fragp, 5, 2);
0110f2b8
PB		 26205 break;
26206 case T_MNEM_ldrh:
26207 case T_MNEM_strh:
5f4273c7 26208 newsize = relax_immediate (fragp, 5, 1);
0110f2b8
PB		 26209 break;
26210 case T_MNEM_ldrb:
26211 case T_MNEM_strb:
5f4273c7 26212 newsize = relax_immediate (fragp, 5, 0);
0110f2b8
PB		 26213 break;
26214 case T_MNEM_adr:
5f4273c7 26215 newsize = relax_adr (fragp, sec, stretch);
0110f2b8
PB		 26216 break;
26217 case T_MNEM_mov:
26218 case T_MNEM_movs:
26219 case T_MNEM_cmp:
26220 case T_MNEM_cmn:
5f4273c7 26221 newsize = relax_immediate (fragp, 8, 0);
0110f2b8
PB		 26222 break;
26223 case T_MNEM_b:
5f4273c7 26224 newsize = relax_branch (fragp, sec, 11, stretch);
0110f2b8
PB		 26225 break;
26226 case T_MNEM_bcond:
5f4273c7 26227 newsize = relax_branch (fragp, sec, 8, stretch);
0110f2b8
PB		 26228 break;
26229 case T_MNEM_add_sp:
26230 case T_MNEM_add_pc:
26231 newsize = relax_immediate (fragp, 8, 2);
26232 break;
26233 case T_MNEM_inc_sp:
26234 case T_MNEM_dec_sp:
26235 newsize = relax_immediate (fragp, 7, 2);
26236 break;
26237 case T_MNEM_addi:
26238 case T_MNEM_addis:
26239 case T_MNEM_subi:
26240 case T_MNEM_subis:
26241 newsize = relax_addsub (fragp, sec);
26242 break;
26243 default:
5f4273c7 26244 abort ();
0110f2b8 26245 }
5e77afaa
PB		 26246
26247 fragp->fr_var = newsize;
26248 /* Freeze wide instructions that are at or before the same location as
26249 in the previous pass. This avoids infinite loops.
5f4273c7
NC		 26250 Don't freeze them unconditionally because targets may be artificially
26251 misaligned by the expansion of preceding frags. */
5e77afaa 26252 if (stretch <= 0 && newsize > 2)
0110f2b8 26253 {
0110f2b8 26254 md_convert_frag (sec->owner, sec, fragp);
5f4273c7 26255 frag_wane (fragp);
0110f2b8 26256 }
5e77afaa 26257
0110f2b8 26258 return newsize - oldsize;
c19d1205 26259}
b99bd4ef 26260
c19d1205 26261/* Round up a section size to the appropriate boundary. */
b99bd4ef 26262
c19d1205
ZW		 26263valueT
26264md_section_align (segT segment ATTRIBUTE_UNUSED,
26265 valueT size)
26266{
6844c0cc 26267 return size;
bfae80f2 26268}
b99bd4ef 26269
c19d1205
ZW		 26270/* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26271 of an rs_align_code fragment. */
26272
26273void
26274arm_handle_align (fragS * fragP)
bfae80f2 26275{
d9235011 26276 static unsigned char const arm_noop[2][2][4] =
e7495e45
NS		 26277 {
26278 { /* ARMv1 */
26279 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26280 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26281 },
26282 { /* ARMv6k */
26283 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26284 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26285 },
26286 };
d9235011 26287 static unsigned char const thumb_noop[2][2][2] =
e7495e45
NS		 26288 {
26289 { /* Thumb-1 */
26290 {0xc0, 0x46}, /* LE */
26291 {0x46, 0xc0}, /* BE */
26292 },
26293 { /* Thumb-2 */
26294 {0x00, 0xbf}, /* LE */
26295 {0xbf, 0x00} /* BE */
26296 }
26297 };
d9235011 26298 static unsigned char const wide_thumb_noop[2][4] =
e7495e45
NS		 26299 { /* Wide Thumb-2 */
26300 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26301 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26302 };
c921be7d 26303
e7495e45 26304 unsigned bytes, fix, noop_size;
c19d1205 26305 char * p;
d9235011
TS		 26306 const unsigned char * noop;
26307 const unsigned char *narrow_noop = NULL;
cd000bff
DJ		 26308#ifdef OBJ_ELF
26309 enum mstate state;
26310#endif
bfae80f2 26311
c19d1205 26312 if (fragP->fr_type != rs_align_code)
bfae80f2
RE		 26313 return;
26314
c19d1205
ZW		 26315 bytes = fragP->fr_next->fr_address - fragP->fr_address - fragP->fr_fix;
26316 p = fragP->fr_literal + fragP->fr_fix;
26317 fix = 0;
bfae80f2 26318
c19d1205
ZW		 26319 if (bytes > MAX_MEM_FOR_RS_ALIGN_CODE)
26320 bytes &= MAX_MEM_FOR_RS_ALIGN_CODE;
bfae80f2 26321
cd000bff 26322 gas_assert ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) != 0);
8dc2430f 26323
cd000bff 26324 if (fragP->tc_frag_data.thumb_mode & (~ MODE_RECORDED))
a737bd4d 26325 {
7f78eb34
JW		 26326 if (ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
26327 ? selected_cpu : arm_arch_none, arm_ext_v6t2))
e7495e45
NS		 26328 {
26329 narrow_noop = thumb_noop[1][target_big_endian];
26330 noop = wide_thumb_noop[target_big_endian];
26331 }
c19d1205 26332 else
e7495e45
NS		 26333 noop = thumb_noop[0][target_big_endian];
26334 noop_size = 2;
cd000bff
DJ		 26335#ifdef OBJ_ELF
26336 state = MAP_THUMB;
26337#endif
7ed4c4c5
NC		 26338 }
26339 else
26340 {
7f78eb34
JW		 26341 noop = arm_noop[ARM_CPU_HAS_FEATURE (selected_cpu_name[0]
26342 ? selected_cpu : arm_arch_none,
26343 arm_ext_v6k) != 0]
e7495e45
NS		 26344 [target_big_endian];
26345 noop_size = 4;
cd000bff
DJ		 26346#ifdef OBJ_ELF
26347 state = MAP_ARM;
26348#endif
7ed4c4c5 26349 }
c921be7d 26350
e7495e45 26351 fragP->fr_var = noop_size;
c921be7d 26352
c19d1205 26353 if (bytes & (noop_size - 1))
7ed4c4c5 26354 {
c19d1205 26355 fix = bytes & (noop_size - 1);
cd000bff
DJ		 26356#ifdef OBJ_ELF
26357 insert_data_mapping_symbol (state, fragP->fr_fix, fragP, fix);
26358#endif
c19d1205
ZW		 26359 memset (p, 0, fix);
26360 p += fix;
26361 bytes -= fix;
a737bd4d 26362 }
a737bd4d 26363
e7495e45
NS		 26364 if (narrow_noop)
26365 {
26366 if (bytes & noop_size)
26367 {
26368 /* Insert a narrow noop. */
26369 memcpy (p, narrow_noop, noop_size);
26370 p += noop_size;
26371 bytes -= noop_size;
26372 fix += noop_size;
26373 }
26374
26375 /* Use wide noops for the remainder */
26376 noop_size = 4;
26377 }
26378
c19d1205 26379 while (bytes >= noop_size)
a737bd4d 26380 {
c19d1205
ZW		 26381 memcpy (p, noop, noop_size);
26382 p += noop_size;
26383 bytes -= noop_size;
26384 fix += noop_size;
a737bd4d
NC		 26385 }
26386
c19d1205 26387 fragP->fr_fix += fix;
a737bd4d
NC		 26388}
26389
c19d1205
ZW		 26390/* Called from md_do_align. Used to create an alignment
26391 frag in a code section. */
26392
26393void
26394arm_frag_align_code (int n, int max)
bfae80f2 26395{
c19d1205 26396 char * p;
7ed4c4c5 26397
c19d1205 26398 /* We assume that there will never be a requirement
6ec8e702 26399 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
c19d1205 26400 if (max > MAX_MEM_FOR_RS_ALIGN_CODE)
6ec8e702
NC		 26401 {
26402 char err_msg[128];
26403
fa94de6b 26404 sprintf (err_msg,
477330fc
RM		 26405 _("alignments greater than %d bytes not supported in .text sections."),
26406 MAX_MEM_FOR_RS_ALIGN_CODE + 1);
20203fb9 26407 as_fatal ("%s", err_msg);
6ec8e702 26408 }
bfae80f2 26409
c19d1205
ZW		 26410 p = frag_var (rs_align_code,
26411 MAX_MEM_FOR_RS_ALIGN_CODE,
26412 1,
26413 (relax_substateT) max,
26414 (symbolS *) NULL,
26415 (offsetT) n,
26416 (char *) NULL);
26417 *p = 0;
26418}
bfae80f2 26419
8dc2430f
NC		 26420/* Perform target specific initialisation of a frag.
26421 Note - despite the name this initialisation is not done when the frag
26422 is created, but only when its type is assigned. A frag can be created
26423 and used a long time before its type is set, so beware of assuming that
33eaf5de 26424 this initialisation is performed first. */
bfae80f2 26425
cd000bff
DJ		 26426#ifndef OBJ_ELF
26427void
26428arm_init_frag (fragS * fragP, int max_chars ATTRIBUTE_UNUSED)
26429{
26430 /* Record whether this frag is in an ARM or a THUMB area. */
2e98972e 26431 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
cd000bff
DJ		 26432}
26433
26434#else /* OBJ_ELF is defined. */
c19d1205 26435void
cd000bff 26436arm_init_frag (fragS * fragP, int max_chars)
c19d1205 26437{
e8d84ca1 26438 bfd_boolean frag_thumb_mode;
b968d18a 26439
8dc2430f
NC		 26440 /* If the current ARM vs THUMB mode has not already
26441 been recorded into this frag then do so now. */
cd000bff 26442 if ((fragP->tc_frag_data.thumb_mode & MODE_RECORDED) == 0)
b968d18a
JW		 26443 fragP->tc_frag_data.thumb_mode = thumb_mode | MODE_RECORDED;
26444
e8d84ca1
NC		 26445 /* PR 21809: Do not set a mapping state for debug sections
26446 - it just confuses other tools. */
26447 if (bfd_get_section_flags (NULL, now_seg) & SEC_DEBUGGING)
26448 return;
26449
b968d18a 26450 frag_thumb_mode = fragP->tc_frag_data.thumb_mode ^ MODE_RECORDED;
cd000bff 26451
f9c1b181
RL		 26452 /* Record a mapping symbol for alignment frags. We will delete this
26453 later if the alignment ends up empty. */
26454 switch (fragP->fr_type)
26455 {
26456 case rs_align:
26457 case rs_align_test:
26458 case rs_fill:
26459 mapping_state_2 (MAP_DATA, max_chars);
26460 break;
26461 case rs_align_code:
b968d18a 26462 mapping_state_2 (frag_thumb_mode ? MAP_THUMB : MAP_ARM, max_chars);
f9c1b181
RL		 26463 break;
26464 default:
26465 break;
cd000bff 26466 }
bfae80f2
RE		 26467}
26468
c19d1205
ZW		 26469/* When we change sections we need to issue a new mapping symbol. */
26470
26471void
26472arm_elf_change_section (void)
bfae80f2 26473{
c19d1205
ZW		 26474 /* Link an unlinked unwind index table section to the .text section. */
26475 if (elf_section_type (now_seg) == SHT_ARM_EXIDX
26476 && elf_linked_to_section (now_seg) == NULL)
26477 elf_linked_to_section (now_seg) = text_section;
bfae80f2
RE		 26478}
26479
c19d1205
ZW		 26480int
26481arm_elf_section_type (const char * str, size_t len)
e45d0630 26482{
c19d1205
ZW		 26483 if (len == 5 && strncmp (str, "exidx", 5) == 0)
26484 return SHT_ARM_EXIDX;
e45d0630 26485
c19d1205
ZW		 26486 return -1;
26487}
26488\f
26489/* Code to deal with unwinding tables. */
e45d0630 26490
c19d1205 26491static void add_unwind_adjustsp (offsetT);
e45d0630 26492
5f4273c7 26493/* Generate any deferred unwind frame offset. */
e45d0630 26494
bfae80f2 26495static void
c19d1205 26496flush_pending_unwind (void)
bfae80f2 26497{
c19d1205 26498 offsetT offset;
bfae80f2 26499
c19d1205
ZW		 26500 offset = unwind.pending_offset;
26501 unwind.pending_offset = 0;
26502 if (offset != 0)
26503 add_unwind_adjustsp (offset);
bfae80f2
RE		 26504}
26505
c19d1205
ZW		 26506/* Add an opcode to this list for this function. Two-byte opcodes should
26507 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26508 order. */
26509
bfae80f2 26510static void
c19d1205 26511add_unwind_opcode (valueT op, int length)
bfae80f2 26512{
c19d1205
ZW		 26513 /* Add any deferred stack adjustment. */
26514 if (unwind.pending_offset)
26515 flush_pending_unwind ();
bfae80f2 26516
c19d1205 26517 unwind.sp_restored = 0;
bfae80f2 26518
c19d1205 26519 if (unwind.opcode_count + length > unwind.opcode_alloc)
bfae80f2 26520 {
c19d1205
ZW		 26521 unwind.opcode_alloc += ARM_OPCODE_CHUNK_SIZE;
26522 if (unwind.opcodes)
325801bd
TS		 26523 unwind.opcodes = XRESIZEVEC (unsigned char, unwind.opcodes,
26524 unwind.opcode_alloc);
c19d1205 26525 else
325801bd 26526 unwind.opcodes = XNEWVEC (unsigned char, unwind.opcode_alloc);
bfae80f2 26527 }
c19d1205 26528 while (length > 0)
bfae80f2 26529 {
c19d1205
ZW		 26530 length--;
26531 unwind.opcodes[unwind.opcode_count] = op & 0xff;
26532 op >>= 8;
26533 unwind.opcode_count++;
bfae80f2 26534 }
bfae80f2
RE		 26535}
26536
c19d1205
ZW		 26537/* Add unwind opcodes to adjust the stack pointer. */
26538
bfae80f2 26539static void
c19d1205 26540add_unwind_adjustsp (offsetT offset)
bfae80f2 26541{
c19d1205 26542 valueT op;
bfae80f2 26543
c19d1205 26544 if (offset > 0x200)
bfae80f2 26545 {
c19d1205
ZW		 26546 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26547 char bytes[5];
26548 int n;
26549 valueT o;
bfae80f2 26550
c19d1205
ZW		 26551 /* Long form: 0xb2, uleb128. */
26552 /* This might not fit in a word so add the individual bytes,
26553 remembering the list is built in reverse order. */
26554 o = (valueT) ((offset - 0x204) >> 2);
26555 if (o == 0)
26556 add_unwind_opcode (0, 1);
bfae80f2 26557
c19d1205
ZW		 26558 /* Calculate the uleb128 encoding of the offset. */
26559 n = 0;
26560 while (o)
26561 {
26562 bytes[n] = o & 0x7f;
26563 o >>= 7;
26564 if (o)
26565 bytes[n] |= 0x80;
26566 n++;
26567 }
26568 /* Add the insn. */
26569 for (; n; n--)
26570 add_unwind_opcode (bytes[n - 1], 1);
26571 add_unwind_opcode (0xb2, 1);
26572 }
26573 else if (offset > 0x100)
bfae80f2 26574 {
c19d1205
ZW		 26575 /* Two short opcodes. */
26576 add_unwind_opcode (0x3f, 1);
26577 op = (offset - 0x104) >> 2;
26578 add_unwind_opcode (op, 1);
bfae80f2 26579 }
c19d1205
ZW		 26580 else if (offset > 0)
26581 {
26582 /* Short opcode. */
26583 op = (offset - 4) >> 2;
26584 add_unwind_opcode (op, 1);
26585 }
26586 else if (offset < 0)
bfae80f2 26587 {
c19d1205
ZW		 26588 offset = -offset;
26589 while (offset > 0x100)
bfae80f2 26590 {
c19d1205
ZW		 26591 add_unwind_opcode (0x7f, 1);
26592 offset -= 0x100;
bfae80f2 26593 }
c19d1205
ZW		 26594 op = ((offset - 4) >> 2) | 0x40;
26595 add_unwind_opcode (op, 1);
bfae80f2 26596 }
bfae80f2
RE		 26597}
26598
c19d1205 26599/* Finish the list of unwind opcodes for this function. */
0198d5e6 26600
c19d1205
ZW		 26601static void
26602finish_unwind_opcodes (void)
bfae80f2 26603{
c19d1205 26604 valueT op;
bfae80f2 26605
c19d1205 26606 if (unwind.fp_used)
bfae80f2 26607 {
708587a4 26608 /* Adjust sp as necessary. */
c19d1205
ZW		 26609 unwind.pending_offset += unwind.fp_offset - unwind.frame_size;
26610 flush_pending_unwind ();
bfae80f2 26611
c19d1205
ZW		 26612 /* After restoring sp from the frame pointer. */
26613 op = 0x90 | unwind.fp_reg;
26614 add_unwind_opcode (op, 1);
26615 }
26616 else
26617 flush_pending_unwind ();
bfae80f2
RE		 26618}
26619
bfae80f2 26620
c19d1205
ZW		 26621/* Start an exception table entry. If idx is nonzero this is an index table
26622 entry. */
bfae80f2
RE		 26623
26624static void
c19d1205 26625start_unwind_section (const segT text_seg, int idx)
bfae80f2 26626{
c19d1205
ZW		 26627 const char * text_name;
26628 const char * prefix;
26629 const char * prefix_once;
26630 const char * group_name;
c19d1205 26631 char * sec_name;
c19d1205
ZW		 26632 int type;
26633 int flags;
26634 int linkonce;
bfae80f2 26635
c19d1205 26636 if (idx)
bfae80f2 26637 {
c19d1205
ZW		 26638 prefix = ELF_STRING_ARM_unwind;
26639 prefix_once = ELF_STRING_ARM_unwind_once;
26640 type = SHT_ARM_EXIDX;
bfae80f2 26641 }
c19d1205 26642 else
bfae80f2 26643 {
c19d1205
ZW		 26644 prefix = ELF_STRING_ARM_unwind_info;
26645 prefix_once = ELF_STRING_ARM_unwind_info_once;
26646 type = SHT_PROGBITS;
bfae80f2
RE		 26647 }
26648
c19d1205
ZW		 26649 text_name = segment_name (text_seg);
26650 if (streq (text_name, ".text"))
26651 text_name = "";
26652
26653 if (strncmp (text_name, ".gnu.linkonce.t.",
26654 strlen (".gnu.linkonce.t.")) == 0)
bfae80f2 26655 {
c19d1205
ZW		 26656 prefix = prefix_once;
26657 text_name += strlen (".gnu.linkonce.t.");
bfae80f2
RE		 26658 }
26659
29a2809e 26660 sec_name = concat (prefix, text_name, (char *) NULL);
bfae80f2 26661
c19d1205
ZW		 26662 flags = SHF_ALLOC;
26663 linkonce = 0;
26664 group_name = 0;
bfae80f2 26665
c19d1205
ZW		 26666 /* Handle COMDAT group. */
26667 if (prefix != prefix_once && (text_seg->flags & SEC_LINK_ONCE) != 0)
bfae80f2 26668 {
c19d1205
ZW		 26669 group_name = elf_group_name (text_seg);
26670 if (group_name == NULL)
26671 {
bd3ba5d1 26672 as_bad (_("Group section `%s' has no group signature"),
c19d1205
ZW		 26673 segment_name (text_seg));
26674 ignore_rest_of_line ();
26675 return;
26676 }
26677 flags |= SHF_GROUP;
26678 linkonce = 1;
bfae80f2
RE		 26679 }
26680
a91e1603
L		 26681 obj_elf_change_section (sec_name, type, 0, flags, 0, group_name,
26682 linkonce, 0);
bfae80f2 26683
5f4273c7 26684 /* Set the section link for index tables. */
c19d1205
ZW		 26685 if (idx)
26686 elf_linked_to_section (now_seg) = text_seg;
bfae80f2
RE		 26687}
26688
bfae80f2 26689
c19d1205
ZW		 26690/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26691 personality routine data. Returns zero, or the index table value for
cad0da33 26692 an inline entry. */
c19d1205
ZW		 26693
26694static valueT
26695create_unwind_entry (int have_data)
bfae80f2 26696{
c19d1205
ZW		 26697 int size;
26698 addressT where;
26699 char *ptr;
26700 /* The current word of data. */
26701 valueT data;
26702 /* The number of bytes left in this word. */
26703 int n;
bfae80f2 26704
c19d1205 26705 finish_unwind_opcodes ();
bfae80f2 26706
c19d1205
ZW		 26707 /* Remember the current text section. */
26708 unwind.saved_seg = now_seg;
26709 unwind.saved_subseg = now_subseg;
bfae80f2 26710
c19d1205 26711 start_unwind_section (now_seg, 0);
bfae80f2 26712
c19d1205 26713 if (unwind.personality_routine == NULL)
bfae80f2 26714 {
c19d1205
ZW		 26715 if (unwind.personality_index == -2)
26716 {
26717 if (have_data)
5f4273c7 26718 as_bad (_("handlerdata in cantunwind frame"));
c19d1205
ZW		 26719 return 1; /* EXIDX_CANTUNWIND. */
26720 }
bfae80f2 26721
c19d1205
ZW		 26722 /* Use a default personality routine if none is specified. */
26723 if (unwind.personality_index == -1)
26724 {
26725 if (unwind.opcode_count > 3)
26726 unwind.personality_index = 1;
26727 else
26728 unwind.personality_index = 0;
26729 }
bfae80f2 26730
c19d1205
ZW		 26731 /* Space for the personality routine entry. */
26732 if (unwind.personality_index == 0)
26733 {
26734 if (unwind.opcode_count > 3)
26735 as_bad (_("too many unwind opcodes for personality routine 0"));
bfae80f2 26736
c19d1205
ZW		 26737 if (!have_data)
26738 {
26739 /* All the data is inline in the index table. */
26740 data = 0x80;
26741 n = 3;
26742 while (unwind.opcode_count > 0)
26743 {
26744 unwind.opcode_count--;
26745 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26746 n--;
26747 }
bfae80f2 26748
c19d1205
ZW		 26749 /* Pad with "finish" opcodes. */
26750 while (n--)
26751 data = (data << 8) | 0xb0;
bfae80f2 26752
c19d1205
ZW		 26753 return data;
26754 }
26755 size = 0;
26756 }
26757 else
26758 /* We get two opcodes "free" in the first word. */
26759 size = unwind.opcode_count - 2;
26760 }
26761 else
5011093d 26762 {
cad0da33
NC		 26763 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26764 if (unwind.personality_index != -1)
26765 {
26766 as_bad (_("attempt to recreate an unwind entry"));
26767 return 1;
26768 }
5011093d
NC		 26769
26770 /* An extra byte is required for the opcode count. */
26771 size = unwind.opcode_count + 1;
26772 }
bfae80f2 26773
c19d1205
ZW		 26774 size = (size + 3) >> 2;
26775 if (size > 0xff)
26776 as_bad (_("too many unwind opcodes"));
bfae80f2 26777
c19d1205
ZW		 26778 frag_align (2, 0, 0);
26779 record_alignment (now_seg, 2);
26780 unwind.table_entry = expr_build_dot ();
26781
26782 /* Allocate the table entry. */
26783 ptr = frag_more ((size << 2) + 4);
74929e7b
NC		 26784 /* PR 13449: Zero the table entries in case some of them are not used. */
26785 memset (ptr, 0, (size << 2) + 4);
c19d1205 26786 where = frag_now_fix () - ((size << 2) + 4);
bfae80f2 26787
c19d1205 26788 switch (unwind.personality_index)
bfae80f2 26789 {
c19d1205
ZW		 26790 case -1:
26791 /* ??? Should this be a PLT generating relocation? */
26792 /* Custom personality routine. */
26793 fix_new (frag_now, where, 4, unwind.personality_routine, 0, 1,
26794 BFD_RELOC_ARM_PREL31);
bfae80f2 26795
c19d1205
ZW		 26796 where += 4;
26797 ptr += 4;
bfae80f2 26798
c19d1205 26799 /* Set the first byte to the number of additional words. */
5011093d 26800 data = size > 0 ? size - 1 : 0;
c19d1205
ZW		 26801 n = 3;
26802 break;
bfae80f2 26803
c19d1205
ZW		 26804 /* ABI defined personality routines. */
26805 case 0:
26806 /* Three opcodes bytes are packed into the first word. */
26807 data = 0x80;
26808 n = 3;
26809 break;
bfae80f2 26810
c19d1205
ZW		 26811 case 1:
26812 case 2:
26813 /* The size and first two opcode bytes go in the first word. */
26814 data = ((0x80 + unwind.personality_index) << 8) | size;
26815 n = 2;
26816 break;
bfae80f2 26817
c19d1205
ZW		 26818 default:
26819 /* Should never happen. */
26820 abort ();
26821 }
bfae80f2 26822
c19d1205
ZW		 26823 /* Pack the opcodes into words (MSB first), reversing the list at the same
26824 time. */
26825 while (unwind.opcode_count > 0)
26826 {
26827 if (n == 0)
26828 {
26829 md_number_to_chars (ptr, data, 4);
26830 ptr += 4;
26831 n = 4;
26832 data = 0;
26833 }
26834 unwind.opcode_count--;
26835 n--;
26836 data = (data << 8) | unwind.opcodes[unwind.opcode_count];
26837 }
26838
26839 /* Finish off the last word. */
26840 if (n < 4)
26841 {
26842 /* Pad with "finish" opcodes. */
26843 while (n--)
26844 data = (data << 8) | 0xb0;
26845
26846 md_number_to_chars (ptr, data, 4);
26847 }
26848
26849 if (!have_data)
26850 {
26851 /* Add an empty descriptor if there is no user-specified data. */
26852 ptr = frag_more (4);
26853 md_number_to_chars (ptr, 0, 4);
26854 }
26855
26856 return 0;
bfae80f2
RE		 26857}
26858
f0927246
NC		 26859
26860/* Initialize the DWARF-2 unwind information for this procedure. */
26861
26862void
26863tc_arm_frame_initial_instructions (void)
26864{
26865 cfi_add_CFA_def_cfa (REG_SP, 0);
26866}
26867#endif /* OBJ_ELF */
26868
c19d1205
ZW		 26869/* Convert REGNAME to a DWARF-2 register number. */
26870
26871int
1df69f4f 26872tc_arm_regname_to_dw2regnum (char *regname)
bfae80f2 26873{
1df69f4f 26874 int reg = arm_reg_parse (&regname, REG_TYPE_RN);
1f5afe1c
NC		 26875 if (reg != FAIL)
26876 return reg;
c19d1205 26877
1f5afe1c
NC		 26878 /* PR 16694: Allow VFP registers as well. */
26879 reg = arm_reg_parse (&regname, REG_TYPE_VFS);
26880 if (reg != FAIL)
26881 return 64 + reg;
c19d1205 26882
1f5afe1c
NC		 26883 reg = arm_reg_parse (&regname, REG_TYPE_VFD);
26884 if (reg != FAIL)
26885 return reg + 256;
26886
0198d5e6 26887 return FAIL;
bfae80f2
RE		 26888}
26889
f0927246 26890#ifdef TE_PE
c19d1205 26891void
f0927246 26892tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
bfae80f2 26893{
91d6fa6a 26894 expressionS exp;
bfae80f2 26895
91d6fa6a
NC		 26896 exp.X_op = O_secrel;
26897 exp.X_add_symbol = symbol;
26898 exp.X_add_number = 0;
26899 emit_expr (&exp, size);
f0927246
NC		 26900}
26901#endif
bfae80f2 26902
c19d1205 26903/* MD interface: Symbol and relocation handling. */
bfae80f2 26904
2fc8bdac
ZW		 26905/* Return the address within the segment that a PC-relative fixup is
26906 relative to. For ARM, PC-relative fixups applied to instructions
26907 are generally relative to the location of the fixup plus 8 bytes.
26908 Thumb branches are offset by 4, and Thumb loads relative to PC
26909 require special handling. */
bfae80f2 26910
c19d1205 26911long
2fc8bdac 26912md_pcrel_from_section (fixS * fixP, segT seg)
bfae80f2 26913{
2fc8bdac
ZW		 26914 offsetT base = fixP->fx_where + fixP->fx_frag->fr_address;
26915
26916 /* If this is pc-relative and we are going to emit a relocation
26917 then we just want to put out any pipeline compensation that the linker
53baae48
NC		 26918 will need. Otherwise we want to use the calculated base.
26919 For WinCE we skip the bias for externals as well, since this
26920 is how the MS ARM-CE assembler behaves and we want to be compatible. */
5f4273c7 26921 if (fixP->fx_pcrel
2fc8bdac 26922 && ((fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != seg)
53baae48
NC		 26923 || (arm_force_relocation (fixP)
26924#ifdef TE_WINCE
26925 && !S_IS_EXTERNAL (fixP->fx_addsy)
26926#endif
26927 )))
2fc8bdac 26928 base = 0;
bfae80f2 26929
267bf995 26930
c19d1205 26931 switch (fixP->fx_r_type)
bfae80f2 26932 {
2fc8bdac
ZW		 26933 /* PC relative addressing on the Thumb is slightly odd as the
26934 bottom two bits of the PC are forced to zero for the
26935 calculation. This happens *after* application of the
26936 pipeline offset. However, Thumb adrl already adjusts for
26937 this, so we need not do it again. */
c19d1205 26938 case BFD_RELOC_ARM_THUMB_ADD:
2fc8bdac 26939 return base & ~3;
c19d1205
ZW		 26940
26941 case BFD_RELOC_ARM_THUMB_OFFSET:
26942 case BFD_RELOC_ARM_T32_OFFSET_IMM:
e9f89963 26943 case BFD_RELOC_ARM_T32_ADD_PC12:
8f06b2d8 26944 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
2fc8bdac 26945 return (base + 4) & ~3;
c19d1205 26946
2fc8bdac 26947 /* Thumb branches are simply offset by +4. */
e12437dc 26948 case BFD_RELOC_THUMB_PCREL_BRANCH5:
2fc8bdac
ZW		 26949 case BFD_RELOC_THUMB_PCREL_BRANCH7:
26950 case BFD_RELOC_THUMB_PCREL_BRANCH9:
26951 case BFD_RELOC_THUMB_PCREL_BRANCH12:
26952 case BFD_RELOC_THUMB_PCREL_BRANCH20:
2fc8bdac 26953 case BFD_RELOC_THUMB_PCREL_BRANCH25:
f6b2b12d 26954 case BFD_RELOC_THUMB_PCREL_BFCSEL:
e5d6e09e 26955 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 26956 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 26957 case BFD_RELOC_ARM_THUMB_BF13:
60f993ce 26958 case BFD_RELOC_ARM_THUMB_LOOP12:
2fc8bdac 26959 return base + 4;
bfae80f2 26960
267bf995 26961 case BFD_RELOC_THUMB_PCREL_BRANCH23:
486499d0
CL		 26962 if (fixP->fx_addsy
26963 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26964 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995 26965 && ARM_IS_FUNC (fixP->fx_addsy)
477330fc
RM		 26966 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26967 base = fixP->fx_where + fixP->fx_frag->fr_address;
267bf995
RR		 26968 return base + 4;
26969
00adf2d4
JB		 26970 /* BLX is like branches above, but forces the low two bits of PC to
26971 zero. */
486499d0
CL		 26972 case BFD_RELOC_THUMB_PCREL_BLX:
26973 if (fixP->fx_addsy
26974 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26975 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 26976 && THUMB_IS_FUNC (fixP->fx_addsy)
26977 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26978 base = fixP->fx_where + fixP->fx_frag->fr_address;
00adf2d4
JB		 26979 return (base + 4) & ~3;
26980
2fc8bdac
ZW		 26981 /* ARM mode branches are offset by +8. However, the Windows CE
26982 loader expects the relocation not to take this into account. */
267bf995 26983 case BFD_RELOC_ARM_PCREL_BLX:
486499d0
CL		 26984 if (fixP->fx_addsy
26985 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26986 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 26987 && ARM_IS_FUNC (fixP->fx_addsy)
26988 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26989 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 26990 return base + 8;
267bf995 26991
486499d0
CL		 26992 case BFD_RELOC_ARM_PCREL_CALL:
26993 if (fixP->fx_addsy
26994 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 26995 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
477330fc
RM		 26996 && THUMB_IS_FUNC (fixP->fx_addsy)
26997 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
26998 base = fixP->fx_where + fixP->fx_frag->fr_address;
486499d0 26999 return base + 8;
267bf995 27000
2fc8bdac 27001 case BFD_RELOC_ARM_PCREL_BRANCH:
39b41c9c 27002 case BFD_RELOC_ARM_PCREL_JUMP:
2fc8bdac 27003 case BFD_RELOC_ARM_PLT32:
c19d1205 27004#ifdef TE_WINCE
5f4273c7 27005 /* When handling fixups immediately, because we have already
477330fc 27006 discovered the value of a symbol, or the address of the frag involved
53baae48 27007 we must account for the offset by +8, as the OS loader will never see the reloc.
477330fc
RM		 27008 see fixup_segment() in write.c
27009 The S_IS_EXTERNAL test handles the case of global symbols.
27010 Those need the calculated base, not just the pipe compensation the linker will need. */
53baae48
NC		 27011 if (fixP->fx_pcrel
27012 && fixP->fx_addsy != NULL
27013 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27014 && (S_IS_EXTERNAL (fixP->fx_addsy) || !arm_force_relocation (fixP)))
27015 return base + 8;
2fc8bdac 27016 return base;
c19d1205 27017#else
2fc8bdac 27018 return base + 8;
c19d1205 27019#endif
2fc8bdac 27020
267bf995 27021
2fc8bdac
ZW		 27022 /* ARM mode loads relative to PC are also offset by +8. Unlike
27023 branches, the Windows CE loader *does* expect the relocation
27024 to take this into account. */
27025 case BFD_RELOC_ARM_OFFSET_IMM:
27026 case BFD_RELOC_ARM_OFFSET_IMM8:
27027 case BFD_RELOC_ARM_HWLITERAL:
27028 case BFD_RELOC_ARM_LITERAL:
27029 case BFD_RELOC_ARM_CP_OFF_IMM:
27030 return base + 8;
27031
27032
27033 /* Other PC-relative relocations are un-offset. */
27034 default:
27035 return base;
27036 }
bfae80f2
RE		 27037}
27038
8b2d793c
NC		 27039static bfd_boolean flag_warn_syms = TRUE;
27040
ae8714c2
NC		 27041bfd_boolean
27042arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED, char * name)
bfae80f2 27043{
8b2d793c
NC		 27044 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27045 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27046 does mean that the resulting code might be very confusing to the reader.
27047 Also this warning can be triggered if the user omits an operand before
27048 an immediate address, eg:
27049
27050 LDR =foo
27051
27052 GAS treats this as an assignment of the value of the symbol foo to a
27053 symbol LDR, and so (without this code) it will not issue any kind of
27054 warning or error message.
27055
27056 Note - ARM instructions are case-insensitive but the strings in the hash
27057 table are all stored in lower case, so we must first ensure that name is
ae8714c2
NC		 27058 lower case too. */
27059 if (flag_warn_syms && arm_ops_hsh)
8b2d793c
NC		 27060 {
27061 char * nbuf = strdup (name);
27062 char * p;
27063
27064 for (p = nbuf; *p; p++)
27065 *p = TOLOWER (*p);
27066 if (hash_find (arm_ops_hsh, nbuf) != NULL)
27067 {
27068 static struct hash_control * already_warned = NULL;
27069
27070 if (already_warned == NULL)
27071 already_warned = hash_new ();
27072 /* Only warn about the symbol once. To keep the code
27073 simple we let hash_insert do the lookup for us. */
3076e594 27074 if (hash_insert (already_warned, nbuf, NULL) == NULL)
ae8714c2 27075 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name);
8b2d793c
NC		 27076 }
27077 else
27078 free (nbuf);
27079 }
3739860c 27080
ae8714c2
NC		 27081 return FALSE;
27082}
27083
27084/* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27085 Otherwise we have no need to default values of symbols. */
27086
27087symbolS *
27088md_undefined_symbol (char * name ATTRIBUTE_UNUSED)
27089{
27090#ifdef OBJ_ELF
27091 if (name[0] == '_' && name[1] == 'G'
27092 && streq (name, GLOBAL_OFFSET_TABLE_NAME))
27093 {
27094 if (!GOT_symbol)
27095 {
27096 if (symbol_find (name))
27097 as_bad (_("GOT already in the symbol table"));
27098
27099 GOT_symbol = symbol_new (name, undefined_section,
27100 (valueT) 0, & zero_address_frag);
27101 }
27102
27103 return GOT_symbol;
27104 }
27105#endif
27106
c921be7d 27107 return NULL;
bfae80f2
RE		 27108}
27109
55cf6793 27110/* Subroutine of md_apply_fix. Check to see if an immediate can be
c19d1205
ZW		 27111 computed as two separate immediate values, added together. We
27112 already know that this value cannot be computed by just one ARM
27113 instruction. */
27114
27115static unsigned int
27116validate_immediate_twopart (unsigned int val,
27117 unsigned int * highpart)
bfae80f2 27118{
c19d1205
ZW		 27119 unsigned int a;
27120 unsigned int i;
bfae80f2 27121
c19d1205
ZW		 27122 for (i = 0; i < 32; i += 2)
27123 if (((a = rotate_left (val, i)) & 0xff) != 0)
27124 {
27125 if (a & 0xff00)
27126 {
27127 if (a & ~ 0xffff)
27128 continue;
27129 * highpart = (a >> 8) | ((i + 24) << 7);
27130 }
27131 else if (a & 0xff0000)
27132 {
27133 if (a & 0xff000000)
27134 continue;
27135 * highpart = (a >> 16) | ((i + 16) << 7);
27136 }
27137 else
27138 {
9c2799c2 27139 gas_assert (a & 0xff000000);
c19d1205
ZW		 27140 * highpart = (a >> 24) | ((i + 8) << 7);
27141 }
bfae80f2 27142
c19d1205
ZW		 27143 return (a & 0xff) | (i << 7);
27144 }
bfae80f2 27145
c19d1205 27146 return FAIL;
bfae80f2
RE		 27147}
27148
c19d1205
ZW		 27149static int
27150validate_offset_imm (unsigned int val, int hwse)
27151{
27152 if ((hwse && val > 255) || val > 4095)
27153 return FAIL;
27154 return val;
27155}
bfae80f2 27156
55cf6793 27157/* Subroutine of md_apply_fix. Do those data_ops which can take a
c19d1205
ZW		 27158 negative immediate constant by altering the instruction. A bit of
27159 a hack really.
27160 MOV <-> MVN
27161 AND <-> BIC
27162 ADC <-> SBC
27163 by inverting the second operand, and
27164 ADD <-> SUB
27165 CMP <-> CMN
27166 by negating the second operand. */
bfae80f2 27167
c19d1205
ZW		 27168static int
27169negate_data_op (unsigned long * instruction,
27170 unsigned long value)
bfae80f2 27171{
c19d1205
ZW		 27172 int op, new_inst;
27173 unsigned long negated, inverted;
bfae80f2 27174
c19d1205
ZW		 27175 negated = encode_arm_immediate (-value);
27176 inverted = encode_arm_immediate (~value);
bfae80f2 27177
c19d1205
ZW		 27178 op = (*instruction >> DATA_OP_SHIFT) & 0xf;
27179 switch (op)
bfae80f2 27180 {
c19d1205
ZW		 27181 /* First negates. */
27182 case OPCODE_SUB: /* ADD <-> SUB */
27183 new_inst = OPCODE_ADD;
27184 value = negated;
27185 break;
bfae80f2 27186
c19d1205
ZW		 27187 case OPCODE_ADD:
27188 new_inst = OPCODE_SUB;
27189 value = negated;
27190 break;
bfae80f2 27191
c19d1205
ZW		 27192 case OPCODE_CMP: /* CMP <-> CMN */
27193 new_inst = OPCODE_CMN;
27194 value = negated;
27195 break;
bfae80f2 27196
c19d1205
ZW		 27197 case OPCODE_CMN:
27198 new_inst = OPCODE_CMP;
27199 value = negated;
27200 break;
bfae80f2 27201
c19d1205
ZW		 27202 /* Now Inverted ops. */
27203 case OPCODE_MOV: /* MOV <-> MVN */
27204 new_inst = OPCODE_MVN;
27205 value = inverted;
27206 break;
bfae80f2 27207
c19d1205
ZW		 27208 case OPCODE_MVN:
27209 new_inst = OPCODE_MOV;
27210 value = inverted;
27211 break;
bfae80f2 27212
c19d1205
ZW		 27213 case OPCODE_AND: /* AND <-> BIC */
27214 new_inst = OPCODE_BIC;
27215 value = inverted;
27216 break;
bfae80f2 27217
c19d1205
ZW		 27218 case OPCODE_BIC:
27219 new_inst = OPCODE_AND;
27220 value = inverted;
27221 break;
bfae80f2 27222
c19d1205
ZW		 27223 case OPCODE_ADC: /* ADC <-> SBC */
27224 new_inst = OPCODE_SBC;
27225 value = inverted;
27226 break;
bfae80f2 27227
c19d1205
ZW		 27228 case OPCODE_SBC:
27229 new_inst = OPCODE_ADC;
27230 value = inverted;
27231 break;
bfae80f2 27232
c19d1205
ZW		 27233 /* We cannot do anything. */
27234 default:
27235 return FAIL;
b99bd4ef
NC		 27236 }
27237
c19d1205
ZW		 27238 if (value == (unsigned) FAIL)
27239 return FAIL;
27240
27241 *instruction &= OPCODE_MASK;
27242 *instruction |= new_inst << DATA_OP_SHIFT;
27243 return value;
b99bd4ef
NC		 27244}
27245
ef8d22e6
PB		 27246/* Like negate_data_op, but for Thumb-2. */
27247
27248static unsigned int
16dd5e42 27249thumb32_negate_data_op (offsetT *instruction, unsigned int value)
ef8d22e6
PB		 27250{
27251 int op, new_inst;
27252 int rd;
16dd5e42 27253 unsigned int negated, inverted;
ef8d22e6
PB		 27254
27255 negated = encode_thumb32_immediate (-value);
27256 inverted = encode_thumb32_immediate (~value);
27257
27258 rd = (*instruction >> 8) & 0xf;
27259 op = (*instruction >> T2_DATA_OP_SHIFT) & 0xf;
27260 switch (op)
27261 {
27262 /* ADD <-> SUB. Includes CMP <-> CMN. */
27263 case T2_OPCODE_SUB:
27264 new_inst = T2_OPCODE_ADD;
27265 value = negated;
27266 break;
27267
27268 case T2_OPCODE_ADD:
27269 new_inst = T2_OPCODE_SUB;
27270 value = negated;
27271 break;
27272
27273 /* ORR <-> ORN. Includes MOV <-> MVN. */
27274 case T2_OPCODE_ORR:
27275 new_inst = T2_OPCODE_ORN;
27276 value = inverted;
27277 break;
27278
27279 case T2_OPCODE_ORN:
27280 new_inst = T2_OPCODE_ORR;
27281 value = inverted;
27282 break;
27283
27284 /* AND <-> BIC. TST has no inverted equivalent. */
27285 case T2_OPCODE_AND:
27286 new_inst = T2_OPCODE_BIC;
27287 if (rd == 15)
27288 value = FAIL;
27289 else
27290 value = inverted;
27291 break;
27292
27293 case T2_OPCODE_BIC:
27294 new_inst = T2_OPCODE_AND;
27295 value = inverted;
27296 break;
27297
27298 /* ADC <-> SBC */
27299 case T2_OPCODE_ADC:
27300 new_inst = T2_OPCODE_SBC;
27301 value = inverted;
27302 break;
27303
27304 case T2_OPCODE_SBC:
27305 new_inst = T2_OPCODE_ADC;
27306 value = inverted;
27307 break;
27308
27309 /* We cannot do anything. */
27310 default:
27311 return FAIL;
27312 }
27313
16dd5e42 27314 if (value == (unsigned int)FAIL)
ef8d22e6
PB		 27315 return FAIL;
27316
27317 *instruction &= T2_OPCODE_MASK;
27318 *instruction |= new_inst << T2_DATA_OP_SHIFT;
27319 return value;
27320}
27321
8f06b2d8 27322/* Read a 32-bit thumb instruction from buf. */
0198d5e6 27323
8f06b2d8
PB		 27324static unsigned long
27325get_thumb32_insn (char * buf)
27326{
27327 unsigned long insn;
27328 insn = md_chars_to_number (buf, THUMB_SIZE) << 16;
27329 insn |= md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27330
27331 return insn;
27332}
27333
a8bc6c78
PB		 27334/* We usually want to set the low bit on the address of thumb function
27335 symbols. In particular .word foo - . should have the low bit set.
27336 Generic code tries to fold the difference of two symbols to
27337 a constant. Prevent this and force a relocation when the first symbols
27338 is a thumb function. */
c921be7d
NC		 27339
27340bfd_boolean
a8bc6c78
PB		 27341arm_optimize_expr (expressionS *l, operatorT op, expressionS *r)
27342{
27343 if (op == O_subtract
27344 && l->X_op == O_symbol
27345 && r->X_op == O_symbol
27346 && THUMB_IS_FUNC (l->X_add_symbol))
27347 {
27348 l->X_op = O_subtract;
27349 l->X_op_symbol = r->X_add_symbol;
27350 l->X_add_number -= r->X_add_number;
c921be7d 27351 return TRUE;
a8bc6c78 27352 }
c921be7d 27353
a8bc6c78 27354 /* Process as normal. */
c921be7d 27355 return FALSE;
a8bc6c78
PB		 27356}
27357
4a42ebbc
RR		 27358/* Encode Thumb2 unconditional branches and calls. The encoding
27359 for the 2 are identical for the immediate values. */
27360
27361static void
27362encode_thumb2_b_bl_offset (char * buf, offsetT value)
27363{
27364#define T2I1I2MASK ((1 << 13) | (1 << 11))
27365 offsetT newval;
27366 offsetT newval2;
27367 addressT S, I1, I2, lo, hi;
27368
27369 S = (value >> 24) & 0x01;
27370 I1 = (value >> 23) & 0x01;
27371 I2 = (value >> 22) & 0x01;
27372 hi = (value >> 12) & 0x3ff;
fa94de6b 27373 lo = (value >> 1) & 0x7ff;
4a42ebbc
RR		 27374 newval = md_chars_to_number (buf, THUMB_SIZE);
27375 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
27376 newval |= (S << 10) | hi;
27377 newval2 &= ~T2I1I2MASK;
27378 newval2 |= (((I1 ^ S) << 13) | ((I2 ^ S) << 11) | lo) ^ T2I1I2MASK;
27379 md_number_to_chars (buf, newval, THUMB_SIZE);
27380 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
27381}
27382
c19d1205 27383void
55cf6793 27384md_apply_fix (fixS * fixP,
c19d1205
ZW		 27385 valueT * valP,
27386 segT seg)
27387{
27388 offsetT value = * valP;
27389 offsetT newval;
27390 unsigned int newimm;
27391 unsigned long temp;
27392 int sign;
27393 char * buf = fixP->fx_where + fixP->fx_frag->fr_literal;
b99bd4ef 27394
9c2799c2 27395 gas_assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
b99bd4ef 27396
c19d1205 27397 /* Note whether this will delete the relocation. */
4962c51a 27398
c19d1205
ZW		 27399 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
27400 fixP->fx_done = 1;
b99bd4ef 27401
adbaf948 27402 /* On a 64-bit host, silently truncate 'value' to 32 bits for
5f4273c7 27403 consistency with the behaviour on 32-bit hosts. Remember value
adbaf948
ZW		 27404 for emit_reloc. */
27405 value &= 0xffffffff;
27406 value ^= 0x80000000;
5f4273c7 27407 value -= 0x80000000;
adbaf948
ZW		 27408
27409 *valP = value;
c19d1205 27410 fixP->fx_addnumber = value;
b99bd4ef 27411
adbaf948
ZW		 27412 /* Same treatment for fixP->fx_offset. */
27413 fixP->fx_offset &= 0xffffffff;
27414 fixP->fx_offset ^= 0x80000000;
27415 fixP->fx_offset -= 0x80000000;
27416
c19d1205 27417 switch (fixP->fx_r_type)
b99bd4ef 27418 {
c19d1205
ZW		 27419 case BFD_RELOC_NONE:
27420 /* This will need to go in the object file. */
27421 fixP->fx_done = 0;
27422 break;
b99bd4ef 27423
c19d1205
ZW		 27424 case BFD_RELOC_ARM_IMMEDIATE:
27425 /* We claim that this fixup has been processed here,
27426 even if in fact we generate an error because we do
27427 not have a reloc for it, so tc_gen_reloc will reject it. */
27428 fixP->fx_done = 1;
b99bd4ef 27429
77db8e2e 27430 if (fixP->fx_addsy)
b99bd4ef 27431 {
77db8e2e 27432 const char *msg = 0;
b99bd4ef 27433
77db8e2e
NC		 27434 if (! S_IS_DEFINED (fixP->fx_addsy))
27435 msg = _("undefined symbol %s used as an immediate value");
27436 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27437 msg = _("symbol %s is in a different section");
27438 else if (S_IS_WEAK (fixP->fx_addsy))
27439 msg = _("symbol %s is weak and may be overridden later");
27440
27441 if (msg)
27442 {
27443 as_bad_where (fixP->fx_file, fixP->fx_line,
27444 msg, S_GET_NAME (fixP->fx_addsy));
27445 break;
27446 }
42e5fcbf
AS		 27447 }
27448
c19d1205
ZW		 27449 temp = md_chars_to_number (buf, INSN_SIZE);
27450
5e73442d
SL		 27451 /* If the offset is negative, we should use encoding A2 for ADR. */
27452 if ((temp & 0xfff0000) == 0x28f0000 && value < 0)
27453 newimm = negate_data_op (&temp, value);
27454 else
27455 {
27456 newimm = encode_arm_immediate (value);
27457
27458 /* If the instruction will fail, see if we can fix things up by
27459 changing the opcode. */
27460 if (newimm == (unsigned int) FAIL)
27461 newimm = negate_data_op (&temp, value);
bada4342
JW		 27462 /* MOV accepts both ARM modified immediate (A1 encoding) and
27463 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27464 When disassembling, MOV is preferred when there is no encoding
27465 overlap. */
27466 if (newimm == (unsigned int) FAIL
27467 && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
27468 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
27469 && !((temp >> SBIT_SHIFT) & 0x1)
27470 && value >= 0 && value <= 0xffff)
27471 {
27472 /* Clear bits[23:20] to change encoding from A1 to A2. */
27473 temp &= 0xff0fffff;
27474 /* Encoding high 4bits imm. Code below will encode the remaining
27475 low 12bits. */
27476 temp |= (value & 0x0000f000) << 4;
27477 newimm = value & 0x00000fff;
27478 }
5e73442d
SL		 27479 }
27480
27481 if (newimm == (unsigned int) FAIL)
b99bd4ef 27482 {
c19d1205
ZW		 27483 as_bad_where (fixP->fx_file, fixP->fx_line,
27484 _("invalid constant (%lx) after fixup"),
27485 (unsigned long) value);
27486 break;
b99bd4ef 27487 }
b99bd4ef 27488
c19d1205
ZW		 27489 newimm |= (temp & 0xfffff000);
27490 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
27491 break;
b99bd4ef 27492
c19d1205
ZW		 27493 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
27494 {
27495 unsigned int highpart = 0;
27496 unsigned int newinsn = 0xe1a00000; /* nop. */
b99bd4ef 27497
77db8e2e 27498 if (fixP->fx_addsy)
42e5fcbf 27499 {
77db8e2e 27500 const char *msg = 0;
42e5fcbf 27501
77db8e2e
NC		 27502 if (! S_IS_DEFINED (fixP->fx_addsy))
27503 msg = _("undefined symbol %s used as an immediate value");
27504 else if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
27505 msg = _("symbol %s is in a different section");
27506 else if (S_IS_WEAK (fixP->fx_addsy))
27507 msg = _("symbol %s is weak and may be overridden later");
42e5fcbf 27508
77db8e2e
NC		 27509 if (msg)
27510 {
27511 as_bad_where (fixP->fx_file, fixP->fx_line,
27512 msg, S_GET_NAME (fixP->fx_addsy));
27513 break;
27514 }
27515 }
fa94de6b 27516
c19d1205
ZW		 27517 newimm = encode_arm_immediate (value);
27518 temp = md_chars_to_number (buf, INSN_SIZE);
b99bd4ef 27519
c19d1205
ZW		 27520 /* If the instruction will fail, see if we can fix things up by
27521 changing the opcode. */
27522 if (newimm == (unsigned int) FAIL
27523 && (newimm = negate_data_op (& temp, value)) == (unsigned int) FAIL)
27524 {
27525 /* No ? OK - try using two ADD instructions to generate
27526 the value. */
27527 newimm = validate_immediate_twopart (value, & highpart);
b99bd4ef 27528
c19d1205
ZW		 27529 /* Yes - then make sure that the second instruction is
27530 also an add. */
27531 if (newimm != (unsigned int) FAIL)
27532 newinsn = temp;
27533 /* Still No ? Try using a negated value. */
27534 else if ((newimm = validate_immediate_twopart (- value, & highpart)) != (unsigned int) FAIL)
27535 temp = newinsn = (temp & OPCODE_MASK) | OPCODE_SUB << DATA_OP_SHIFT;
27536 /* Otherwise - give up. */
27537 else
27538 {
27539 as_bad_where (fixP->fx_file, fixP->fx_line,
27540 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27541 (long) value);
27542 break;
27543 }
b99bd4ef 27544
c19d1205
ZW		 27545 /* Replace the first operand in the 2nd instruction (which
27546 is the PC) with the destination register. We have
27547 already added in the PC in the first instruction and we
27548 do not want to do it again. */
27549 newinsn &= ~ 0xf0000;
27550 newinsn |= ((newinsn & 0x0f000) << 4);
27551 }
b99bd4ef 27552
c19d1205
ZW		 27553 newimm |= (temp & 0xfffff000);
27554 md_number_to_chars (buf, (valueT) newimm, INSN_SIZE);
b99bd4ef 27555
c19d1205
ZW		 27556 highpart |= (newinsn & 0xfffff000);
27557 md_number_to_chars (buf + INSN_SIZE, (valueT) highpart, INSN_SIZE);
27558 }
27559 break;
b99bd4ef 27560
c19d1205 27561 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 27562 if (!fixP->fx_done && seg->use_rela_p)
27563 value = 0;
1a0670f3 27564 /* Fall through. */
00a97672 27565
c19d1205 27566 case BFD_RELOC_ARM_LITERAL:
26d97720 27567 sign = value > 0;
b99bd4ef 27568
c19d1205
ZW		 27569 if (value < 0)
27570 value = - value;
b99bd4ef 27571
c19d1205 27572 if (validate_offset_imm (value, 0) == FAIL)
f03698e6 27573 {
c19d1205
ZW		 27574 if (fixP->fx_r_type == BFD_RELOC_ARM_LITERAL)
27575 as_bad_where (fixP->fx_file, fixP->fx_line,
27576 _("invalid literal constant: pool needs to be closer"));
27577 else
27578 as_bad_where (fixP->fx_file, fixP->fx_line,
27579 _("bad immediate value for offset (%ld)"),
27580 (long) value);
27581 break;
f03698e6
RE		 27582 }
27583
c19d1205 27584 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 27585 if (value == 0)
27586 newval &= 0xfffff000;
27587 else
27588 {
27589 newval &= 0xff7ff000;
27590 newval |= value | (sign ? INDEX_UP : 0);
27591 }
c19d1205
ZW		 27592 md_number_to_chars (buf, newval, INSN_SIZE);
27593 break;
b99bd4ef 27594
c19d1205
ZW		 27595 case BFD_RELOC_ARM_OFFSET_IMM8:
27596 case BFD_RELOC_ARM_HWLITERAL:
26d97720 27597 sign = value > 0;
b99bd4ef 27598
c19d1205
ZW		 27599 if (value < 0)
27600 value = - value;
b99bd4ef 27601
c19d1205 27602 if (validate_offset_imm (value, 1) == FAIL)
b99bd4ef 27603 {
c19d1205
ZW		 27604 if (fixP->fx_r_type == BFD_RELOC_ARM_HWLITERAL)
27605 as_bad_where (fixP->fx_file, fixP->fx_line,
27606 _("invalid literal constant: pool needs to be closer"));
27607 else
427d0db6
RM		 27608 as_bad_where (fixP->fx_file, fixP->fx_line,
27609 _("bad immediate value for 8-bit offset (%ld)"),
27610 (long) value);
c19d1205 27611 break;
b99bd4ef
NC		 27612 }
27613
c19d1205 27614 newval = md_chars_to_number (buf, INSN_SIZE);
26d97720
NS		 27615 if (value == 0)
27616 newval &= 0xfffff0f0;
27617 else
27618 {
27619 newval &= 0xff7ff0f0;
27620 newval |= ((value >> 4) << 8) | (value & 0xf) | (sign ? INDEX_UP : 0);
27621 }
c19d1205
ZW		 27622 md_number_to_chars (buf, newval, INSN_SIZE);
27623 break;
b99bd4ef 27624
c19d1205
ZW		 27625 case BFD_RELOC_ARM_T32_OFFSET_U8:
27626 if (value < 0 || value > 1020 || value % 4 != 0)
27627 as_bad_where (fixP->fx_file, fixP->fx_line,
27628 _("bad immediate value for offset (%ld)"), (long) value);
27629 value /= 4;
b99bd4ef 27630
c19d1205 27631 newval = md_chars_to_number (buf+2, THUMB_SIZE);
c19d1205
ZW		 27632 newval |= value;
27633 md_number_to_chars (buf+2, newval, THUMB_SIZE);
27634 break;
b99bd4ef 27635
c19d1205
ZW		 27636 case BFD_RELOC_ARM_T32_OFFSET_IMM:
27637 /* This is a complicated relocation used for all varieties of Thumb32
27638 load/store instruction with immediate offset:
27639
27640 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
477330fc 27641 *4, optional writeback(W)
c19d1205
ZW		 27642 (doubleword load/store)
27643
27644 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27645 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27646 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27647 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27648 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27649
27650 Uppercase letters indicate bits that are already encoded at
27651 this point. Lowercase letters are our problem. For the
27652 second block of instructions, the secondary opcode nybble
27653 (bits 8..11) is present, and bit 23 is zero, even if this is
27654 a PC-relative operation. */
27655 newval = md_chars_to_number (buf, THUMB_SIZE);
27656 newval <<= 16;
27657 newval |= md_chars_to_number (buf+THUMB_SIZE, THUMB_SIZE);
b99bd4ef 27658
c19d1205 27659 if ((newval & 0xf0000000) == 0xe0000000)
b99bd4ef 27660 {
c19d1205
ZW		 27661 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27662 if (value >= 0)
27663 newval |= (1 << 23);
27664 else
27665 value = -value;
27666 if (value % 4 != 0)
27667 {
27668 as_bad_where (fixP->fx_file, fixP->fx_line,
27669 _("offset not a multiple of 4"));
27670 break;
27671 }
27672 value /= 4;
216d22bc 27673 if (value > 0xff)
c19d1205
ZW		 27674 {
27675 as_bad_where (fixP->fx_file, fixP->fx_line,
27676 _("offset out of range"));
27677 break;
27678 }
27679 newval &= ~0xff;
b99bd4ef 27680 }
c19d1205 27681 else if ((newval & 0x000f0000) == 0x000f0000)
b99bd4ef 27682 {
c19d1205
ZW		 27683 /* PC-relative, 12-bit offset. */
27684 if (value >= 0)
27685 newval |= (1 << 23);
27686 else
27687 value = -value;
216d22bc 27688 if (value > 0xfff)
c19d1205
ZW		 27689 {
27690 as_bad_where (fixP->fx_file, fixP->fx_line,
27691 _("offset out of range"));
27692 break;
27693 }
27694 newval &= ~0xfff;
b99bd4ef 27695 }
c19d1205 27696 else if ((newval & 0x00000100) == 0x00000100)
b99bd4ef 27697 {
c19d1205
ZW		 27698 /* Writeback: 8-bit, +/- offset. */
27699 if (value >= 0)
27700 newval |= (1 << 9);
27701 else
27702 value = -value;
216d22bc 27703 if (value > 0xff)
c19d1205
ZW		 27704 {
27705 as_bad_where (fixP->fx_file, fixP->fx_line,
27706 _("offset out of range"));
27707 break;
27708 }
27709 newval &= ~0xff;
b99bd4ef 27710 }
c19d1205 27711 else if ((newval & 0x00000f00) == 0x00000e00)
b99bd4ef 27712 {
c19d1205 27713 /* T-instruction: positive 8-bit offset. */
216d22bc 27714 if (value < 0 || value > 0xff)
b99bd4ef 27715 {
c19d1205
ZW		 27716 as_bad_where (fixP->fx_file, fixP->fx_line,
27717 _("offset out of range"));
27718 break;
b99bd4ef 27719 }
c19d1205
ZW		 27720 newval &= ~0xff;
27721 newval |= value;
b99bd4ef
NC		 27722 }
27723 else
b99bd4ef 27724 {
c19d1205
ZW		 27725 /* Positive 12-bit or negative 8-bit offset. */
27726 int limit;
27727 if (value >= 0)
b99bd4ef 27728 {
c19d1205
ZW		 27729 newval |= (1 << 23);
27730 limit = 0xfff;
27731 }
27732 else
27733 {
27734 value = -value;
27735 limit = 0xff;
27736 }
27737 if (value > limit)
27738 {
27739 as_bad_where (fixP->fx_file, fixP->fx_line,
27740 _("offset out of range"));
27741 break;
b99bd4ef 27742 }
c19d1205 27743 newval &= ~limit;
b99bd4ef 27744 }
b99bd4ef 27745
c19d1205
ZW		 27746 newval |= value;
27747 md_number_to_chars (buf, (newval >> 16) & 0xffff, THUMB_SIZE);
27748 md_number_to_chars (buf + THUMB_SIZE, newval & 0xffff, THUMB_SIZE);
27749 break;
404ff6b5 27750
c19d1205
ZW		 27751 case BFD_RELOC_ARM_SHIFT_IMM:
27752 newval = md_chars_to_number (buf, INSN_SIZE);
27753 if (((unsigned long) value) > 32
27754 || (value == 32
27755 && (((newval & 0x60) == 0) || (newval & 0x60) == 0x60)))
27756 {
27757 as_bad_where (fixP->fx_file, fixP->fx_line,
27758 _("shift expression is too large"));
27759 break;
27760 }
404ff6b5 27761
c19d1205
ZW		 27762 if (value == 0)
27763 /* Shifts of zero must be done as lsl. */
27764 newval &= ~0x60;
27765 else if (value == 32)
27766 value = 0;
27767 newval &= 0xfffff07f;
27768 newval |= (value & 0x1f) << 7;
27769 md_number_to_chars (buf, newval, INSN_SIZE);
27770 break;
404ff6b5 27771
c19d1205 27772 case BFD_RELOC_ARM_T32_IMMEDIATE:
16805f35 27773 case BFD_RELOC_ARM_T32_ADD_IMM:
92e90b6e 27774 case BFD_RELOC_ARM_T32_IMM12:
e9f89963 27775 case BFD_RELOC_ARM_T32_ADD_PC12:
c19d1205
ZW		 27776 /* We claim that this fixup has been processed here,
27777 even if in fact we generate an error because we do
27778 not have a reloc for it, so tc_gen_reloc will reject it. */
27779 fixP->fx_done = 1;
404ff6b5 27780
c19d1205
ZW		 27781 if (fixP->fx_addsy
27782 && ! S_IS_DEFINED (fixP->fx_addsy))
27783 {
27784 as_bad_where (fixP->fx_file, fixP->fx_line,
27785 _("undefined symbol %s used as an immediate value"),
27786 S_GET_NAME (fixP->fx_addsy));
27787 break;
27788 }
404ff6b5 27789
c19d1205
ZW		 27790 newval = md_chars_to_number (buf, THUMB_SIZE);
27791 newval <<= 16;
27792 newval |= md_chars_to_number (buf+2, THUMB_SIZE);
404ff6b5 27793
16805f35 27794 newimm = FAIL;
bada4342
JW		 27795 if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
27796 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27797 Thumb2 modified immediate encoding (T2). */
27798 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
16805f35 27799 || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
ef8d22e6
PB		 27800 {
27801 newimm = encode_thumb32_immediate (value);
27802 if (newimm == (unsigned int) FAIL)
27803 newimm = thumb32_negate_data_op (&newval, value);
27804 }
bada4342 27805 if (newimm == (unsigned int) FAIL)
92e90b6e 27806 {
bada4342 27807 if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
e9f89963 27808 {
bada4342
JW		 27809 /* Turn add/sum into addw/subw. */
27810 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
27811 newval = (newval & 0xfeffffff) | 0x02000000;
27812 /* No flat 12-bit imm encoding for addsw/subsw. */
27813 if ((newval & 0x00100000) == 0)
40f246e3 27814 {
bada4342
JW		 27815 /* 12 bit immediate for addw/subw. */
27816 if (value < 0)
27817 {
27818 value = -value;
27819 newval ^= 0x00a00000;
27820 }
27821 if (value > 0xfff)
27822 newimm = (unsigned int) FAIL;
27823 else
27824 newimm = value;
27825 }
27826 }
27827 else
27828 {
27829 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27830 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27831 disassembling, MOV is preferred when there is no encoding
db7bf105 27832 overlap. */
bada4342 27833 if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
db7bf105
NC		 27834 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27835 but with the Rn field [19:16] set to 1111. */
27836 && (((newval >> 16) & 0xf) == 0xf)
bada4342
JW		 27837 && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
27838 && !((newval >> T2_SBIT_SHIFT) & 0x1)
db7bf105 27839 && value >= 0 && value <= 0xffff)
bada4342
JW		 27840 {
27841 /* Toggle bit[25] to change encoding from T2 to T3. */
27842 newval ^= 1 << 25;
27843 /* Clear bits[19:16]. */
27844 newval &= 0xfff0ffff;
27845 /* Encoding high 4bits imm. Code below will encode the
27846 remaining low 12bits. */
27847 newval |= (value & 0x0000f000) << 4;
27848 newimm = value & 0x00000fff;
40f246e3 27849 }
e9f89963 27850 }
92e90b6e 27851 }
cc8a6dd0 27852
c19d1205 27853 if (newimm == (unsigned int)FAIL)
3631a3c8 27854 {
c19d1205
ZW		 27855 as_bad_where (fixP->fx_file, fixP->fx_line,
27856 _("invalid constant (%lx) after fixup"),
27857 (unsigned long) value);
27858 break;
3631a3c8
NC		 27859 }
27860
c19d1205
ZW		 27861 newval |= (newimm & 0x800) << 15;
27862 newval |= (newimm & 0x700) << 4;
27863 newval |= (newimm & 0x0ff);
cc8a6dd0 27864
c19d1205
ZW		 27865 md_number_to_chars (buf, (valueT) ((newval >> 16) & 0xffff), THUMB_SIZE);
27866 md_number_to_chars (buf+2, (valueT) (newval & 0xffff), THUMB_SIZE);
27867 break;
a737bd4d 27868
3eb17e6b 27869 case BFD_RELOC_ARM_SMC:
ba85f98c 27870 if (((unsigned long) value) > 0xf)
c19d1205 27871 as_bad_where (fixP->fx_file, fixP->fx_line,
3eb17e6b 27872 _("invalid smc expression"));
ba85f98c 27873
2fc8bdac 27874 newval = md_chars_to_number (buf, INSN_SIZE);
ba85f98c 27875 newval |= (value & 0xf);
c19d1205
ZW		 27876 md_number_to_chars (buf, newval, INSN_SIZE);
27877 break;
a737bd4d 27878
90ec0d68
MGD		 27879 case BFD_RELOC_ARM_HVC:
27880 if (((unsigned long) value) > 0xffff)
27881 as_bad_where (fixP->fx_file, fixP->fx_line,
27882 _("invalid hvc expression"));
27883 newval = md_chars_to_number (buf, INSN_SIZE);
27884 newval |= (value & 0xf) | ((value & 0xfff0) << 4);
27885 md_number_to_chars (buf, newval, INSN_SIZE);
27886 break;
27887
c19d1205 27888 case BFD_RELOC_ARM_SWI:
adbaf948 27889 if (fixP->tc_fix_data != 0)
c19d1205
ZW		 27890 {
27891 if (((unsigned long) value) > 0xff)
27892 as_bad_where (fixP->fx_file, fixP->fx_line,
27893 _("invalid swi expression"));
2fc8bdac 27894 newval = md_chars_to_number (buf, THUMB_SIZE);
c19d1205
ZW		 27895 newval |= value;
27896 md_number_to_chars (buf, newval, THUMB_SIZE);
27897 }
27898 else
27899 {
27900 if (((unsigned long) value) > 0x00ffffff)
27901 as_bad_where (fixP->fx_file, fixP->fx_line,
27902 _("invalid swi expression"));
2fc8bdac 27903 newval = md_chars_to_number (buf, INSN_SIZE);
c19d1205
ZW		 27904 newval |= value;
27905 md_number_to_chars (buf, newval, INSN_SIZE);
27906 }
27907 break;
a737bd4d 27908
c19d1205
ZW		 27909 case BFD_RELOC_ARM_MULTI:
27910 if (((unsigned long) value) > 0xffff)
27911 as_bad_where (fixP->fx_file, fixP->fx_line,
27912 _("invalid expression in load/store multiple"));
27913 newval = value | md_chars_to_number (buf, INSN_SIZE);
27914 md_number_to_chars (buf, newval, INSN_SIZE);
27915 break;
a737bd4d 27916
c19d1205 27917#ifdef OBJ_ELF
39b41c9c 27918 case BFD_RELOC_ARM_PCREL_CALL:
267bf995
RR		 27919
27920 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27921 && fixP->fx_addsy
34e77a92 27922 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 27923 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27924 && THUMB_IS_FUNC (fixP->fx_addsy))
27925 /* Flip the bl to blx. This is a simple flip
27926 bit here because we generate PCREL_CALL for
27927 unconditional bls. */
27928 {
27929 newval = md_chars_to_number (buf, INSN_SIZE);
27930 newval = newval | 0x10000000;
27931 md_number_to_chars (buf, newval, INSN_SIZE);
27932 temp = 1;
27933 fixP->fx_done = 1;
27934 }
39b41c9c
PB		 27935 else
27936 temp = 3;
27937 goto arm_branch_common;
27938
27939 case BFD_RELOC_ARM_PCREL_JUMP:
267bf995
RR		 27940 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27941 && fixP->fx_addsy
34e77a92 27942 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 27943 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27944 && THUMB_IS_FUNC (fixP->fx_addsy))
27945 {
27946 /* This would map to a bl<cond>, b<cond>,
27947 b<always> to a Thumb function. We
27948 need to force a relocation for this particular
27949 case. */
27950 newval = md_chars_to_number (buf, INSN_SIZE);
27951 fixP->fx_done = 0;
27952 }
1a0670f3 27953 /* Fall through. */
267bf995 27954
2fc8bdac 27955 case BFD_RELOC_ARM_PLT32:
c19d1205 27956#endif
39b41c9c
PB		 27957 case BFD_RELOC_ARM_PCREL_BRANCH:
27958 temp = 3;
27959 goto arm_branch_common;
a737bd4d 27960
39b41c9c 27961 case BFD_RELOC_ARM_PCREL_BLX:
267bf995 27962
39b41c9c 27963 temp = 1;
267bf995
RR		 27964 if (ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
27965 && fixP->fx_addsy
34e77a92 27966 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 27967 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
27968 && ARM_IS_FUNC (fixP->fx_addsy))
27969 {
27970 /* Flip the blx to a bl and warn. */
27971 const char *name = S_GET_NAME (fixP->fx_addsy);
27972 newval = 0xeb000000;
27973 as_warn_where (fixP->fx_file, fixP->fx_line,
27974 _("blx to '%s' an ARM ISA state function changed to bl"),
27975 name);
27976 md_number_to_chars (buf, newval, INSN_SIZE);
27977 temp = 3;
27978 fixP->fx_done = 1;
27979 }
27980
27981#ifdef OBJ_ELF
27982 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
477330fc 27983 fixP->fx_r_type = BFD_RELOC_ARM_PCREL_CALL;
267bf995
RR		 27984#endif
27985
39b41c9c 27986 arm_branch_common:
c19d1205 27987 /* We are going to store value (shifted right by two) in the
39b41c9c
PB		 27988 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27989 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
de194d85 27990 also be clear. */
39b41c9c 27991 if (value & temp)
c19d1205 27992 as_bad_where (fixP->fx_file, fixP->fx_line,
2fc8bdac
ZW		 27993 _("misaligned branch destination"));
27994 if ((value & (offsetT)0xfe000000) != (offsetT)0
27995 && (value & (offsetT)0xfe000000) != (offsetT)0xfe000000)
08f10d51 27996 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 27997
2fc8bdac 27998 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 27999 {
2fc8bdac
ZW		 28000 newval = md_chars_to_number (buf, INSN_SIZE);
28001 newval |= (value >> 2) & 0x00ffffff;
7ae2971b
PB		 28002 /* Set the H bit on BLX instructions. */
28003 if (temp == 1)
28004 {
28005 if (value & 2)
28006 newval |= 0x01000000;
28007 else
28008 newval &= ~0x01000000;
28009 }
2fc8bdac 28010 md_number_to_chars (buf, newval, INSN_SIZE);
c19d1205 28011 }
c19d1205 28012 break;
a737bd4d 28013
25fe350b
MS		 28014 case BFD_RELOC_THUMB_PCREL_BRANCH7: /* CBZ */
28015 /* CBZ can only branch forward. */
a737bd4d 28016
738755b0 28017 /* Attempts to use CBZ to branch to the next instruction
477330fc
RM		 28018 (which, strictly speaking, are prohibited) will be turned into
28019 no-ops.
738755b0
MS		 28020
28021 FIXME: It may be better to remove the instruction completely and
28022 perform relaxation. */
28023 if (value == -2)
2fc8bdac
ZW		 28024 {
28025 newval = md_chars_to_number (buf, THUMB_SIZE);
738755b0 28026 newval = 0xbf00; /* NOP encoding T1 */
2fc8bdac
ZW		 28027 md_number_to_chars (buf, newval, THUMB_SIZE);
28028 }
738755b0
MS		 28029 else
28030 {
28031 if (value & ~0x7e)
08f10d51 28032 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
738755b0 28033
477330fc 28034 if (fixP->fx_done || !seg->use_rela_p)
738755b0
MS		 28035 {
28036 newval = md_chars_to_number (buf, THUMB_SIZE);
28037 newval |= ((value & 0x3e) << 2) | ((value & 0x40) << 3);
28038 md_number_to_chars (buf, newval, THUMB_SIZE);
28039 }
28040 }
c19d1205 28041 break;
a737bd4d 28042
c19d1205 28043 case BFD_RELOC_THUMB_PCREL_BRANCH9: /* Conditional branch. */
2fc8bdac 28044 if ((value & ~0xff) && ((value & ~0xff) != ~0xff))
08f10d51 28045 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28046
2fc8bdac
ZW		 28047 if (fixP->fx_done || !seg->use_rela_p)
28048 {
28049 newval = md_chars_to_number (buf, THUMB_SIZE);
28050 newval |= (value & 0x1ff) >> 1;
28051 md_number_to_chars (buf, newval, THUMB_SIZE);
28052 }
c19d1205 28053 break;
a737bd4d 28054
c19d1205 28055 case BFD_RELOC_THUMB_PCREL_BRANCH12: /* Unconditional branch. */
2fc8bdac 28056 if ((value & ~0x7ff) && ((value & ~0x7ff) != ~0x7ff))
08f10d51 28057 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
a737bd4d 28058
2fc8bdac
ZW		 28059 if (fixP->fx_done || !seg->use_rela_p)
28060 {
28061 newval = md_chars_to_number (buf, THUMB_SIZE);
28062 newval |= (value & 0xfff) >> 1;
28063 md_number_to_chars (buf, newval, THUMB_SIZE);
28064 }
c19d1205 28065 break;
a737bd4d 28066
c19d1205 28067 case BFD_RELOC_THUMB_PCREL_BRANCH20:
267bf995
RR		 28068 if (fixP->fx_addsy
28069 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 28070 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28071 && ARM_IS_FUNC (fixP->fx_addsy)
28072 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28073 {
28074 /* Force a relocation for a branch 20 bits wide. */
28075 fixP->fx_done = 0;
28076 }
08f10d51 28077 if ((value & ~0x1fffff) && ((value & ~0x0fffff) != ~0x0fffff))
2fc8bdac
ZW		 28078 as_bad_where (fixP->fx_file, fixP->fx_line,
28079 _("conditional branch out of range"));
404ff6b5 28080
2fc8bdac
ZW		 28081 if (fixP->fx_done || !seg->use_rela_p)
28082 {
28083 offsetT newval2;
28084 addressT S, J1, J2, lo, hi;
404ff6b5 28085
2fc8bdac
ZW		 28086 S = (value & 0x00100000) >> 20;
28087 J2 = (value & 0x00080000) >> 19;
28088 J1 = (value & 0x00040000) >> 18;
28089 hi = (value & 0x0003f000) >> 12;
28090 lo = (value & 0x00000ffe) >> 1;
6c43fab6 28091
2fc8bdac
ZW		 28092 newval = md_chars_to_number (buf, THUMB_SIZE);
28093 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28094 newval |= (S << 10) | hi;
28095 newval2 |= (J1 << 13) | (J2 << 11) | lo;
28096 md_number_to_chars (buf, newval, THUMB_SIZE);
28097 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28098 }
c19d1205 28099 break;
6c43fab6 28100
c19d1205 28101 case BFD_RELOC_THUMB_PCREL_BLX:
267bf995
RR		 28102 /* If there is a blx from a thumb state function to
28103 another thumb function flip this to a bl and warn
28104 about it. */
28105
28106 if (fixP->fx_addsy
34e77a92 28107 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28108 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28109 && THUMB_IS_FUNC (fixP->fx_addsy))
28110 {
28111 const char *name = S_GET_NAME (fixP->fx_addsy);
28112 as_warn_where (fixP->fx_file, fixP->fx_line,
28113 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28114 name);
28115 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28116 newval = newval | 0x1000;
28117 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
28118 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
28119 fixP->fx_done = 1;
28120 }
28121
28122
28123 goto thumb_bl_common;
28124
c19d1205 28125 case BFD_RELOC_THUMB_PCREL_BRANCH23:
267bf995
RR		 28126 /* A bl from Thumb state ISA to an internal ARM state function
28127 is converted to a blx. */
28128 if (fixP->fx_addsy
28129 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
34e77a92 28130 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
267bf995
RR		 28131 && ARM_IS_FUNC (fixP->fx_addsy)
28132 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t))
28133 {
28134 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28135 newval = newval & ~0x1000;
28136 md_number_to_chars (buf+THUMB_SIZE, newval, THUMB_SIZE);
28137 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BLX;
28138 fixP->fx_done = 1;
28139 }
28140
28141 thumb_bl_common:
28142
2fc8bdac
ZW		 28143 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
28144 /* For a BLX instruction, make sure that the relocation is rounded up
28145 to a word boundary. This follows the semantics of the instruction
28146 which specifies that bit 1 of the target address will come from bit
28147 1 of the base address. */
d406f3e4
JB		 28148 value = (value + 3) & ~ 3;
28149
28150#ifdef OBJ_ELF
28151 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4
28152 && fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BLX)
28153 fixP->fx_r_type = BFD_RELOC_THUMB_PCREL_BRANCH23;
28154#endif
404ff6b5 28155
2b2f5df9
NC		 28156 if ((value & ~0x3fffff) && ((value & ~0x3fffff) != ~0x3fffff))
28157 {
fc289b0a 28158 if (!(ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)))
2b2f5df9
NC		 28159 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
28160 else if ((value & ~0x1ffffff)
28161 && ((value & ~0x1ffffff) != ~0x1ffffff))
28162 as_bad_where (fixP->fx_file, fixP->fx_line,
28163 _("Thumb2 branch out of range"));
28164 }
4a42ebbc
RR		 28165
28166 if (fixP->fx_done || !seg->use_rela_p)
28167 encode_thumb2_b_bl_offset (buf, value);
28168
c19d1205 28169 break;
404ff6b5 28170
c19d1205 28171 case BFD_RELOC_THUMB_PCREL_BRANCH25:
08f10d51
NC		 28172 if ((value & ~0x0ffffff) && ((value & ~0x0ffffff) != ~0x0ffffff))
28173 as_bad_where (fixP->fx_file, fixP->fx_line, BAD_RANGE);
6c43fab6 28174
2fc8bdac 28175 if (fixP->fx_done || !seg->use_rela_p)
4a42ebbc 28176 encode_thumb2_b_bl_offset (buf, value);
6c43fab6 28177
2fc8bdac 28178 break;
a737bd4d 28179
2fc8bdac
ZW		 28180 case BFD_RELOC_8:
28181 if (fixP->fx_done || !seg->use_rela_p)
4b1a927e 28182 *buf = value;
c19d1205 28183 break;
a737bd4d 28184
c19d1205 28185 case BFD_RELOC_16:
2fc8bdac 28186 if (fixP->fx_done || !seg->use_rela_p)
c19d1205 28187 md_number_to_chars (buf, value, 2);
c19d1205 28188 break;
a737bd4d 28189
c19d1205 28190#ifdef OBJ_ELF
0855e32b
NS		 28191 case BFD_RELOC_ARM_TLS_CALL:
28192 case BFD_RELOC_ARM_THM_TLS_CALL:
28193 case BFD_RELOC_ARM_TLS_DESCSEQ:
28194 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
0855e32b 28195 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205
ZW		 28196 case BFD_RELOC_ARM_TLS_GD32:
28197 case BFD_RELOC_ARM_TLS_LE32:
28198 case BFD_RELOC_ARM_TLS_IE32:
28199 case BFD_RELOC_ARM_TLS_LDM32:
28200 case BFD_RELOC_ARM_TLS_LDO32:
28201 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4b1a927e 28202 break;
6c43fab6 28203
5c5a4843
CL		 28204 /* Same handling as above, but with the arm_fdpic guard. */
28205 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
28206 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
28207 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
28208 if (arm_fdpic)
28209 {
28210 S_SET_THREAD_LOCAL (fixP->fx_addsy);
28211 }
28212 else
28213 {
28214 as_bad_where (fixP->fx_file, fixP->fx_line,
28215 _("Relocation supported only in FDPIC mode"));
28216 }
28217 break;
28218
c19d1205
ZW		 28219 case BFD_RELOC_ARM_GOT32:
28220 case BFD_RELOC_ARM_GOTOFF:
c19d1205 28221 break;
b43420e6
NC		 28222
28223 case BFD_RELOC_ARM_GOT_PREL:
28224 if (fixP->fx_done || !seg->use_rela_p)
477330fc 28225 md_number_to_chars (buf, value, 4);
b43420e6
NC		 28226 break;
28227
9a6f4e97
NS		 28228 case BFD_RELOC_ARM_TARGET2:
28229 /* TARGET2 is not partial-inplace, so we need to write the
477330fc
RM		 28230 addend here for REL targets, because it won't be written out
28231 during reloc processing later. */
9a6f4e97
NS		 28232 if (fixP->fx_done || !seg->use_rela_p)
28233 md_number_to_chars (buf, fixP->fx_offset, 4);
28234 break;
188fd7ae
CL		 28235
28236 /* Relocations for FDPIC. */
28237 case BFD_RELOC_ARM_GOTFUNCDESC:
28238 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
28239 case BFD_RELOC_ARM_FUNCDESC:
28240 if (arm_fdpic)
28241 {
28242 if (fixP->fx_done || !seg->use_rela_p)
28243 md_number_to_chars (buf, 0, 4);
28244 }
28245 else
28246 {
28247 as_bad_where (fixP->fx_file, fixP->fx_line,
28248 _("Relocation supported only in FDPIC mode"));
28249 }
28250 break;
c19d1205 28251#endif
6c43fab6 28252
c19d1205
ZW		 28253 case BFD_RELOC_RVA:
28254 case BFD_RELOC_32:
28255 case BFD_RELOC_ARM_TARGET1:
28256 case BFD_RELOC_ARM_ROSEGREL32:
28257 case BFD_RELOC_ARM_SBREL32:
28258 case BFD_RELOC_32_PCREL:
f0927246
NC		 28259#ifdef TE_PE
28260 case BFD_RELOC_32_SECREL:
28261#endif
2fc8bdac 28262 if (fixP->fx_done || !seg->use_rela_p)
53baae48
NC		 28263#ifdef TE_WINCE
28264 /* For WinCE we only do this for pcrel fixups. */
28265 if (fixP->fx_done || fixP->fx_pcrel)
28266#endif
28267 md_number_to_chars (buf, value, 4);
c19d1205 28268 break;
6c43fab6 28269
c19d1205
ZW		 28270#ifdef OBJ_ELF
28271 case BFD_RELOC_ARM_PREL31:
2fc8bdac 28272 if (fixP->fx_done || !seg->use_rela_p)
c19d1205
ZW		 28273 {
28274 newval = md_chars_to_number (buf, 4) & 0x80000000;
28275 if ((value ^ (value >> 1)) & 0x40000000)
28276 {
28277 as_bad_where (fixP->fx_file, fixP->fx_line,
28278 _("rel31 relocation overflow"));
28279 }
28280 newval |= value & 0x7fffffff;
28281 md_number_to_chars (buf, newval, 4);
28282 }
28283 break;
c19d1205 28284#endif
a737bd4d 28285
c19d1205 28286 case BFD_RELOC_ARM_CP_OFF_IMM:
8f06b2d8 28287 case BFD_RELOC_ARM_T32_CP_OFF_IMM:
32c36c3c 28288 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM:
9db2f6b4
RL		 28289 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM)
28290 newval = md_chars_to_number (buf, INSN_SIZE);
28291 else
28292 newval = get_thumb32_insn (buf);
28293 if ((newval & 0x0f200f00) == 0x0d000900)
28294 {
28295 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28296 has permitted values that are multiples of 2, in the range 0
28297 to 510. */
28298 if (value < -510 || value > 510 || (value & 1))
28299 as_bad_where (fixP->fx_file, fixP->fx_line,
28300 _("co-processor offset out of range"));
28301 }
32c36c3c
AV		 28302 else if ((newval & 0xfe001f80) == 0xec000f80)
28303 {
28304 if (value < -511 || value > 512 || (value & 3))
28305 as_bad_where (fixP->fx_file, fixP->fx_line,
28306 _("co-processor offset out of range"));
28307 }
9db2f6b4 28308 else if (value < -1023 || value > 1023 || (value & 3))
c19d1205
ZW		 28309 as_bad_where (fixP->fx_file, fixP->fx_line,
28310 _("co-processor offset out of range"));
28311 cp_off_common:
26d97720 28312 sign = value > 0;
c19d1205
ZW		 28313 if (value < 0)
28314 value = -value;
8f06b2d8
PB		 28315 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28316 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
28317 newval = md_chars_to_number (buf, INSN_SIZE);
28318 else
28319 newval = get_thumb32_insn (buf);
26d97720 28320 if (value == 0)
32c36c3c
AV		 28321 {
28322 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
28323 newval &= 0xffffff80;
28324 else
28325 newval &= 0xffffff00;
28326 }
26d97720
NS		 28327 else
28328 {
32c36c3c
AV		 28329 if (fixP->fx_r_type == BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM)
28330 newval &= 0xff7fff80;
28331 else
28332 newval &= 0xff7fff00;
9db2f6b4
RL		 28333 if ((newval & 0x0f200f00) == 0x0d000900)
28334 {
28335 /* This is a fp16 vstr/vldr.
28336
28337 It requires the immediate offset in the instruction is shifted
28338 left by 1 to be a half-word offset.
28339
28340 Here, left shift by 1 first, and later right shift by 2
28341 should get the right offset. */
28342 value <<= 1;
28343 }
26d97720
NS		 28344 newval |= (value >> 2) | (sign ? INDEX_UP : 0);
28345 }
8f06b2d8
PB		 28346 if (fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
28347 || fixP->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2)
28348 md_number_to_chars (buf, newval, INSN_SIZE);
28349 else
28350 put_thumb32_insn (buf, newval);
c19d1205 28351 break;
a737bd4d 28352
c19d1205 28353 case BFD_RELOC_ARM_CP_OFF_IMM_S2:
8f06b2d8 28354 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2:
c19d1205
ZW		 28355 if (value < -255 || value > 255)
28356 as_bad_where (fixP->fx_file, fixP->fx_line,
28357 _("co-processor offset out of range"));
df7849c5 28358 value *= 4;
c19d1205 28359 goto cp_off_common;
6c43fab6 28360
c19d1205
ZW		 28361 case BFD_RELOC_ARM_THUMB_OFFSET:
28362 newval = md_chars_to_number (buf, THUMB_SIZE);
28363 /* Exactly what ranges, and where the offset is inserted depends
28364 on the type of instruction, we can establish this from the
28365 top 4 bits. */
28366 switch (newval >> 12)
28367 {
28368 case 4: /* PC load. */
28369 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28370 forced to zero for these loads; md_pcrel_from has already
28371 compensated for this. */
28372 if (value & 3)
28373 as_bad_where (fixP->fx_file, fixP->fx_line,
28374 _("invalid offset, target not word aligned (0x%08lX)"),
0359e808
NC		 28375 (((unsigned long) fixP->fx_frag->fr_address
28376 + (unsigned long) fixP->fx_where) & ~3)
28377 + (unsigned long) value);
a737bd4d 28378
c19d1205
ZW		 28379 if (value & ~0x3fc)
28380 as_bad_where (fixP->fx_file, fixP->fx_line,
28381 _("invalid offset, value too big (0x%08lX)"),
28382 (long) value);
a737bd4d 28383
c19d1205
ZW		 28384 newval |= value >> 2;
28385 break;
a737bd4d 28386
c19d1205
ZW		 28387 case 9: /* SP load/store. */
28388 if (value & ~0x3fc)
28389 as_bad_where (fixP->fx_file, fixP->fx_line,
28390 _("invalid offset, value too big (0x%08lX)"),
28391 (long) value);
28392 newval |= value >> 2;
28393 break;
6c43fab6 28394
c19d1205
ZW		 28395 case 6: /* Word load/store. */
28396 if (value & ~0x7c)
28397 as_bad_where (fixP->fx_file, fixP->fx_line,
28398 _("invalid offset, value too big (0x%08lX)"),
28399 (long) value);
28400 newval |= value << 4; /* 6 - 2. */
28401 break;
a737bd4d 28402
c19d1205
ZW		 28403 case 7: /* Byte load/store. */
28404 if (value & ~0x1f)
28405 as_bad_where (fixP->fx_file, fixP->fx_line,
28406 _("invalid offset, value too big (0x%08lX)"),
28407 (long) value);
28408 newval |= value << 6;
28409 break;
a737bd4d 28410
c19d1205
ZW		 28411 case 8: /* Halfword load/store. */
28412 if (value & ~0x3e)
28413 as_bad_where (fixP->fx_file, fixP->fx_line,
28414 _("invalid offset, value too big (0x%08lX)"),
28415 (long) value);
28416 newval |= value << 5; /* 6 - 1. */
28417 break;
a737bd4d 28418
c19d1205
ZW		 28419 default:
28420 as_bad_where (fixP->fx_file, fixP->fx_line,
28421 "Unable to process relocation for thumb opcode: %lx",
28422 (unsigned long) newval);
28423 break;
28424 }
28425 md_number_to_chars (buf, newval, THUMB_SIZE);
28426 break;
a737bd4d 28427
c19d1205
ZW		 28428 case BFD_RELOC_ARM_THUMB_ADD:
28429 /* This is a complicated relocation, since we use it for all of
28430 the following immediate relocations:
a737bd4d 28431
c19d1205
ZW		 28432 3bit ADD/SUB
28433 8bit ADD/SUB
28434 9bit ADD/SUB SP word-aligned
28435 10bit ADD PC/SP word-aligned
a737bd4d 28436
c19d1205
ZW		 28437 The type of instruction being processed is encoded in the
28438 instruction field:
a737bd4d 28439
c19d1205
ZW		 28440 0x8000 SUB
28441 0x00F0 Rd
28442 0x000F Rs
28443 */
28444 newval = md_chars_to_number (buf, THUMB_SIZE);
28445 {
28446 int rd = (newval >> 4) & 0xf;
28447 int rs = newval & 0xf;
28448 int subtract = !!(newval & 0x8000);
a737bd4d 28449
c19d1205
ZW		 28450 /* Check for HI regs, only very restricted cases allowed:
28451 Adjusting SP, and using PC or SP to get an address. */
28452 if ((rd > 7 && (rd != REG_SP || rs != REG_SP))
28453 || (rs > 7 && rs != REG_SP && rs != REG_PC))
28454 as_bad_where (fixP->fx_file, fixP->fx_line,
28455 _("invalid Hi register with immediate"));
a737bd4d 28456
c19d1205
ZW		 28457 /* If value is negative, choose the opposite instruction. */
28458 if (value < 0)
28459 {
28460 value = -value;
28461 subtract = !subtract;
28462 if (value < 0)
28463 as_bad_where (fixP->fx_file, fixP->fx_line,
28464 _("immediate value out of range"));
28465 }
a737bd4d 28466
c19d1205
ZW		 28467 if (rd == REG_SP)
28468 {
75c11999 28469 if (value & ~0x1fc)
c19d1205
ZW		 28470 as_bad_where (fixP->fx_file, fixP->fx_line,
28471 _("invalid immediate for stack address calculation"));
28472 newval = subtract ? T_OPCODE_SUB_ST : T_OPCODE_ADD_ST;
28473 newval |= value >> 2;
28474 }
28475 else if (rs == REG_PC || rs == REG_SP)
28476 {
c12d2c9d
NC		 28477 /* PR gas/18541. If the addition is for a defined symbol
28478 within range of an ADR instruction then accept it. */
28479 if (subtract
28480 && value == 4
28481 && fixP->fx_addsy != NULL)
28482 {
28483 subtract = 0;
28484
28485 if (! S_IS_DEFINED (fixP->fx_addsy)
28486 || S_GET_SEGMENT (fixP->fx_addsy) != seg
28487 || S_IS_WEAK (fixP->fx_addsy))
28488 {
28489 as_bad_where (fixP->fx_file, fixP->fx_line,
28490 _("address calculation needs a strongly defined nearby symbol"));
28491 }
28492 else
28493 {
28494 offsetT v = fixP->fx_where + fixP->fx_frag->fr_address;
28495
28496 /* Round up to the next 4-byte boundary. */
28497 if (v & 3)
28498 v = (v + 3) & ~ 3;
28499 else
28500 v += 4;
28501 v = S_GET_VALUE (fixP->fx_addsy) - v;
28502
28503 if (v & ~0x3fc)
28504 {
28505 as_bad_where (fixP->fx_file, fixP->fx_line,
28506 _("symbol too far away"));
28507 }
28508 else
28509 {
28510 fixP->fx_done = 1;
28511 value = v;
28512 }
28513 }
28514 }
28515
c19d1205
ZW		 28516 if (subtract || value & ~0x3fc)
28517 as_bad_where (fixP->fx_file, fixP->fx_line,
28518 _("invalid immediate for address calculation (value = 0x%08lX)"),
5fc177c8 28519 (unsigned long) (subtract ? - value : value));
c19d1205
ZW		 28520 newval = (rs == REG_PC ? T_OPCODE_ADD_PC : T_OPCODE_ADD_SP);
28521 newval |= rd << 8;
28522 newval |= value >> 2;
28523 }
28524 else if (rs == rd)
28525 {
28526 if (value & ~0xff)
28527 as_bad_where (fixP->fx_file, fixP->fx_line,
28528 _("immediate value out of range"));
28529 newval = subtract ? T_OPCODE_SUB_I8 : T_OPCODE_ADD_I8;
28530 newval |= (rd << 8) | value;
28531 }
28532 else
28533 {
28534 if (value & ~0x7)
28535 as_bad_where (fixP->fx_file, fixP->fx_line,
28536 _("immediate value out of range"));
28537 newval = subtract ? T_OPCODE_SUB_I3 : T_OPCODE_ADD_I3;
28538 newval |= rd | (rs << 3) | (value << 6);
28539 }
28540 }
28541 md_number_to_chars (buf, newval, THUMB_SIZE);
28542 break;
a737bd4d 28543
c19d1205
ZW		 28544 case BFD_RELOC_ARM_THUMB_IMM:
28545 newval = md_chars_to_number (buf, THUMB_SIZE);
28546 if (value < 0 || value > 255)
28547 as_bad_where (fixP->fx_file, fixP->fx_line,
4e6e072b 28548 _("invalid immediate: %ld is out of range"),
c19d1205
ZW		 28549 (long) value);
28550 newval |= value;
28551 md_number_to_chars (buf, newval, THUMB_SIZE);
28552 break;
a737bd4d 28553
c19d1205
ZW		 28554 case BFD_RELOC_ARM_THUMB_SHIFT:
28555 /* 5bit shift value (0..32). LSL cannot take 32. */
28556 newval = md_chars_to_number (buf, THUMB_SIZE) & 0xf83f;
28557 temp = newval & 0xf800;
28558 if (value < 0 || value > 32 || (value == 32 && temp == T_OPCODE_LSL_I))
28559 as_bad_where (fixP->fx_file, fixP->fx_line,
28560 _("invalid shift value: %ld"), (long) value);
28561 /* Shifts of zero must be encoded as LSL. */
28562 if (value == 0)
28563 newval = (newval & 0x003f) | T_OPCODE_LSL_I;
28564 /* Shifts of 32 are encoded as zero. */
28565 else if (value == 32)
28566 value = 0;
28567 newval |= value << 6;
28568 md_number_to_chars (buf, newval, THUMB_SIZE);
28569 break;
a737bd4d 28570
c19d1205
ZW		 28571 case BFD_RELOC_VTABLE_INHERIT:
28572 case BFD_RELOC_VTABLE_ENTRY:
28573 fixP->fx_done = 0;
28574 return;
6c43fab6 28575
b6895b4f
PB		 28576 case BFD_RELOC_ARM_MOVW:
28577 case BFD_RELOC_ARM_MOVT:
28578 case BFD_RELOC_ARM_THUMB_MOVW:
28579 case BFD_RELOC_ARM_THUMB_MOVT:
28580 if (fixP->fx_done || !seg->use_rela_p)
28581 {
28582 /* REL format relocations are limited to a 16-bit addend. */
28583 if (!fixP->fx_done)
28584 {
39623e12 28585 if (value < -0x8000 || value > 0x7fff)
b6895b4f 28586 as_bad_where (fixP->fx_file, fixP->fx_line,
ff5075ca 28587 _("offset out of range"));
b6895b4f
PB		 28588 }
28589 else if (fixP->fx_r_type == BFD_RELOC_ARM_MOVT
28590 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28591 {
28592 value >>= 16;
28593 }
28594
28595 if (fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
28596 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT)
28597 {
28598 newval = get_thumb32_insn (buf);
28599 newval &= 0xfbf08f00;
28600 newval |= (value & 0xf000) << 4;
28601 newval |= (value & 0x0800) << 15;
28602 newval |= (value & 0x0700) << 4;
28603 newval |= (value & 0x00ff);
28604 put_thumb32_insn (buf, newval);
28605 }
28606 else
28607 {
28608 newval = md_chars_to_number (buf, 4);
28609 newval &= 0xfff0f000;
28610 newval |= value & 0x0fff;
28611 newval |= (value & 0xf000) << 4;
28612 md_number_to_chars (buf, newval, 4);
28613 }
28614 }
28615 return;
28616
72d98d16
MG		 28617 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
28618 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
28619 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
28620 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
28621 gas_assert (!fixP->fx_done);
28622 {
28623 bfd_vma insn;
28624 bfd_boolean is_mov;
28625 bfd_vma encoded_addend = value;
28626
28627 /* Check that addend can be encoded in instruction. */
28628 if (!seg->use_rela_p && (value < 0 || value > 255))
28629 as_bad_where (fixP->fx_file, fixP->fx_line,
28630 _("the offset 0x%08lX is not representable"),
28631 (unsigned long) encoded_addend);
28632
28633 /* Extract the instruction. */
28634 insn = md_chars_to_number (buf, THUMB_SIZE);
28635 is_mov = (insn & 0xf800) == 0x2000;
28636
28637 /* Encode insn. */
28638 if (is_mov)
28639 {
28640 if (!seg->use_rela_p)
28641 insn |= encoded_addend;
28642 }
28643 else
28644 {
28645 int rd, rs;
28646
28647 /* Extract the instruction. */
28648 /* Encoding is the following
28649 0x8000 SUB
28650 0x00F0 Rd
28651 0x000F Rs
28652 */
28653 /* The following conditions must be true :
28654 - ADD
28655 - Rd == Rs
28656 - Rd <= 7
28657 */
28658 rd = (insn >> 4) & 0xf;
28659 rs = insn & 0xf;
28660 if ((insn & 0x8000) || (rd != rs) || rd > 7)
28661 as_bad_where (fixP->fx_file, fixP->fx_line,
28662 _("Unable to process relocation for thumb opcode: %lx"),
28663 (unsigned long) insn);
28664
28665 /* Encode as ADD immediate8 thumb 1 code. */
28666 insn = 0x3000 | (rd << 8);
28667
28668 /* Place the encoded addend into the first 8 bits of the
28669 instruction. */
28670 if (!seg->use_rela_p)
28671 insn |= encoded_addend;
28672 }
28673
28674 /* Update the instruction. */
28675 md_number_to_chars (buf, insn, THUMB_SIZE);
28676 }
28677 break;
28678
4962c51a
MS		 28679 case BFD_RELOC_ARM_ALU_PC_G0_NC:
28680 case BFD_RELOC_ARM_ALU_PC_G0:
28681 case BFD_RELOC_ARM_ALU_PC_G1_NC:
28682 case BFD_RELOC_ARM_ALU_PC_G1:
28683 case BFD_RELOC_ARM_ALU_PC_G2:
28684 case BFD_RELOC_ARM_ALU_SB_G0_NC:
28685 case BFD_RELOC_ARM_ALU_SB_G0:
28686 case BFD_RELOC_ARM_ALU_SB_G1_NC:
28687 case BFD_RELOC_ARM_ALU_SB_G1:
28688 case BFD_RELOC_ARM_ALU_SB_G2:
9c2799c2 28689 gas_assert (!fixP->fx_done);
4962c51a
MS		 28690 if (!seg->use_rela_p)
28691 {
477330fc
RM		 28692 bfd_vma insn;
28693 bfd_vma encoded_addend;
3ca4a8ec 28694 bfd_vma addend_abs = llabs (value);
477330fc
RM		 28695
28696 /* Check that the absolute value of the addend can be
28697 expressed as an 8-bit constant plus a rotation. */
28698 encoded_addend = encode_arm_immediate (addend_abs);
28699 if (encoded_addend == (unsigned int) FAIL)
4962c51a 28700 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28701 _("the offset 0x%08lX is not representable"),
28702 (unsigned long) addend_abs);
28703
28704 /* Extract the instruction. */
28705 insn = md_chars_to_number (buf, INSN_SIZE);
28706
28707 /* If the addend is positive, use an ADD instruction.
28708 Otherwise use a SUB. Take care not to destroy the S bit. */
28709 insn &= 0xff1fffff;
28710 if (value < 0)
28711 insn |= 1 << 22;
28712 else
28713 insn |= 1 << 23;
28714
28715 /* Place the encoded addend into the first 12 bits of the
28716 instruction. */
28717 insn &= 0xfffff000;
28718 insn |= encoded_addend;
28719
28720 /* Update the instruction. */
28721 md_number_to_chars (buf, insn, INSN_SIZE);
4962c51a
MS		 28722 }
28723 break;
28724
28725 case BFD_RELOC_ARM_LDR_PC_G0:
28726 case BFD_RELOC_ARM_LDR_PC_G1:
28727 case BFD_RELOC_ARM_LDR_PC_G2:
28728 case BFD_RELOC_ARM_LDR_SB_G0:
28729 case BFD_RELOC_ARM_LDR_SB_G1:
28730 case BFD_RELOC_ARM_LDR_SB_G2:
9c2799c2 28731 gas_assert (!fixP->fx_done);
4962c51a 28732 if (!seg->use_rela_p)
477330fc
RM		 28733 {
28734 bfd_vma insn;
3ca4a8ec 28735 bfd_vma addend_abs = llabs (value);
4962c51a 28736
477330fc
RM		 28737 /* Check that the absolute value of the addend can be
28738 encoded in 12 bits. */
28739 if (addend_abs >= 0x1000)
4962c51a 28740 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28741 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28742 (unsigned long) addend_abs);
28743
28744 /* Extract the instruction. */
28745 insn = md_chars_to_number (buf, INSN_SIZE);
28746
28747 /* If the addend is negative, clear bit 23 of the instruction.
28748 Otherwise set it. */
28749 if (value < 0)
28750 insn &= ~(1 << 23);
28751 else
28752 insn |= 1 << 23;
28753
28754 /* Place the absolute value of the addend into the first 12 bits
28755 of the instruction. */
28756 insn &= 0xfffff000;
28757 insn |= addend_abs;
28758
28759 /* Update the instruction. */
28760 md_number_to_chars (buf, insn, INSN_SIZE);
28761 }
4962c51a
MS		 28762 break;
28763
28764 case BFD_RELOC_ARM_LDRS_PC_G0:
28765 case BFD_RELOC_ARM_LDRS_PC_G1:
28766 case BFD_RELOC_ARM_LDRS_PC_G2:
28767 case BFD_RELOC_ARM_LDRS_SB_G0:
28768 case BFD_RELOC_ARM_LDRS_SB_G1:
28769 case BFD_RELOC_ARM_LDRS_SB_G2:
9c2799c2 28770 gas_assert (!fixP->fx_done);
4962c51a 28771 if (!seg->use_rela_p)
477330fc
RM		 28772 {
28773 bfd_vma insn;
3ca4a8ec 28774 bfd_vma addend_abs = llabs (value);
4962c51a 28775
477330fc
RM		 28776 /* Check that the absolute value of the addend can be
28777 encoded in 8 bits. */
28778 if (addend_abs >= 0x100)
4962c51a 28779 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28780 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28781 (unsigned long) addend_abs);
28782
28783 /* Extract the instruction. */
28784 insn = md_chars_to_number (buf, INSN_SIZE);
28785
28786 /* If the addend is negative, clear bit 23 of the instruction.
28787 Otherwise set it. */
28788 if (value < 0)
28789 insn &= ~(1 << 23);
28790 else
28791 insn |= 1 << 23;
28792
28793 /* Place the first four bits of the absolute value of the addend
28794 into the first 4 bits of the instruction, and the remaining
28795 four into bits 8 .. 11. */
28796 insn &= 0xfffff0f0;
28797 insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
28798
28799 /* Update the instruction. */
28800 md_number_to_chars (buf, insn, INSN_SIZE);
28801 }
4962c51a
MS		 28802 break;
28803
28804 case BFD_RELOC_ARM_LDC_PC_G0:
28805 case BFD_RELOC_ARM_LDC_PC_G1:
28806 case BFD_RELOC_ARM_LDC_PC_G2:
28807 case BFD_RELOC_ARM_LDC_SB_G0:
28808 case BFD_RELOC_ARM_LDC_SB_G1:
28809 case BFD_RELOC_ARM_LDC_SB_G2:
9c2799c2 28810 gas_assert (!fixP->fx_done);
4962c51a 28811 if (!seg->use_rela_p)
477330fc
RM		 28812 {
28813 bfd_vma insn;
3ca4a8ec 28814 bfd_vma addend_abs = llabs (value);
4962c51a 28815
477330fc
RM		 28816 /* Check that the absolute value of the addend is a multiple of
28817 four and, when divided by four, fits in 8 bits. */
28818 if (addend_abs & 0x3)
4962c51a 28819 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28820 _("bad offset 0x%08lX (must be word-aligned)"),
28821 (unsigned long) addend_abs);
4962c51a 28822
477330fc 28823 if ((addend_abs >> 2) > 0xff)
4962c51a 28824 as_bad_where (fixP->fx_file, fixP->fx_line,
477330fc
RM		 28825 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28826 (unsigned long) addend_abs);
28827
28828 /* Extract the instruction. */
28829 insn = md_chars_to_number (buf, INSN_SIZE);
28830
28831 /* If the addend is negative, clear bit 23 of the instruction.
28832 Otherwise set it. */
28833 if (value < 0)
28834 insn &= ~(1 << 23);
28835 else
28836 insn |= 1 << 23;
28837
28838 /* Place the addend (divided by four) into the first eight
28839 bits of the instruction. */
28840 insn &= 0xfffffff0;
28841 insn |= addend_abs >> 2;
28842
28843 /* Update the instruction. */
28844 md_number_to_chars (buf, insn, INSN_SIZE);
28845 }
4962c51a
MS		 28846 break;
28847
e12437dc
AV		 28848 case BFD_RELOC_THUMB_PCREL_BRANCH5:
28849 if (fixP->fx_addsy
28850 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28851 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28852 && ARM_IS_FUNC (fixP->fx_addsy)
28853 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28854 {
28855 /* Force a relocation for a branch 5 bits wide. */
28856 fixP->fx_done = 0;
28857 }
28858 if (v8_1_branch_value_check (value, 5, FALSE) == FAIL)
28859 as_bad_where (fixP->fx_file, fixP->fx_line,
28860 BAD_BRANCH_OFF);
28861
28862 if (fixP->fx_done || !seg->use_rela_p)
28863 {
28864 addressT boff = value >> 1;
28865
28866 newval = md_chars_to_number (buf, THUMB_SIZE);
28867 newval |= (boff << 7);
28868 md_number_to_chars (buf, newval, THUMB_SIZE);
28869 }
28870 break;
28871
f6b2b12d
AV		 28872 case BFD_RELOC_THUMB_PCREL_BFCSEL:
28873 if (fixP->fx_addsy
28874 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28875 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28876 && ARM_IS_FUNC (fixP->fx_addsy)
28877 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28878 {
28879 fixP->fx_done = 0;
28880 }
28881 if ((value & ~0x7f) && ((value & ~0x3f) != ~0x3f))
28882 as_bad_where (fixP->fx_file, fixP->fx_line,
28883 _("branch out of range"));
28884
28885 if (fixP->fx_done || !seg->use_rela_p)
28886 {
28887 newval = md_chars_to_number (buf, THUMB_SIZE);
28888
28889 addressT boff = ((newval & 0x0780) >> 7) << 1;
28890 addressT diff = value - boff;
28891
28892 if (diff == 4)
28893 {
28894 newval |= 1 << 1; /* T bit. */
28895 }
28896 else if (diff != 2)
28897 {
28898 as_bad_where (fixP->fx_file, fixP->fx_line,
28899 _("out of range label-relative fixup value"));
28900 }
28901 md_number_to_chars (buf, newval, THUMB_SIZE);
28902 }
28903 break;
28904
e5d6e09e
AV		 28905 case BFD_RELOC_ARM_THUMB_BF17:
28906 if (fixP->fx_addsy
28907 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28908 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28909 && ARM_IS_FUNC (fixP->fx_addsy)
28910 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28911 {
28912 /* Force a relocation for a branch 17 bits wide. */
28913 fixP->fx_done = 0;
28914 }
28915
28916 if (v8_1_branch_value_check (value, 17, TRUE) == FAIL)
28917 as_bad_where (fixP->fx_file, fixP->fx_line,
28918 BAD_BRANCH_OFF);
28919
28920 if (fixP->fx_done || !seg->use_rela_p)
28921 {
28922 offsetT newval2;
28923 addressT immA, immB, immC;
28924
28925 immA = (value & 0x0001f000) >> 12;
28926 immB = (value & 0x00000ffc) >> 2;
28927 immC = (value & 0x00000002) >> 1;
28928
28929 newval = md_chars_to_number (buf, THUMB_SIZE);
28930 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28931 newval |= immA;
28932 newval2 |= (immC << 11) | (immB << 1);
28933 md_number_to_chars (buf, newval, THUMB_SIZE);
28934 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28935 }
28936 break;
28937
1caf72a5
AV		 28938 case BFD_RELOC_ARM_THUMB_BF19:
28939 if (fixP->fx_addsy
28940 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28941 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28942 && ARM_IS_FUNC (fixP->fx_addsy)
28943 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28944 {
28945 /* Force a relocation for a branch 19 bits wide. */
28946 fixP->fx_done = 0;
28947 }
28948
28949 if (v8_1_branch_value_check (value, 19, TRUE) == FAIL)
28950 as_bad_where (fixP->fx_file, fixP->fx_line,
28951 BAD_BRANCH_OFF);
28952
28953 if (fixP->fx_done || !seg->use_rela_p)
28954 {
28955 offsetT newval2;
28956 addressT immA, immB, immC;
28957
28958 immA = (value & 0x0007f000) >> 12;
28959 immB = (value & 0x00000ffc) >> 2;
28960 immC = (value & 0x00000002) >> 1;
28961
28962 newval = md_chars_to_number (buf, THUMB_SIZE);
28963 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28964 newval |= immA;
28965 newval2 |= (immC << 11) | (immB << 1);
28966 md_number_to_chars (buf, newval, THUMB_SIZE);
28967 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
28968 }
28969 break;
28970
1889da70
AV		 28971 case BFD_RELOC_ARM_THUMB_BF13:
28972 if (fixP->fx_addsy
28973 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
28974 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
28975 && ARM_IS_FUNC (fixP->fx_addsy)
28976 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
28977 {
28978 /* Force a relocation for a branch 13 bits wide. */
28979 fixP->fx_done = 0;
28980 }
28981
28982 if (v8_1_branch_value_check (value, 13, TRUE) == FAIL)
28983 as_bad_where (fixP->fx_file, fixP->fx_line,
28984 BAD_BRANCH_OFF);
28985
28986 if (fixP->fx_done || !seg->use_rela_p)
28987 {
28988 offsetT newval2;
28989 addressT immA, immB, immC;
28990
28991 immA = (value & 0x00001000) >> 12;
28992 immB = (value & 0x00000ffc) >> 2;
28993 immC = (value & 0x00000002) >> 1;
28994
28995 newval = md_chars_to_number (buf, THUMB_SIZE);
28996 newval2 = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
28997 newval |= immA;
28998 newval2 |= (immC << 11) | (immB << 1);
28999 md_number_to_chars (buf, newval, THUMB_SIZE);
29000 md_number_to_chars (buf + THUMB_SIZE, newval2, THUMB_SIZE);
29001 }
29002 break;
29003
60f993ce
AV		 29004 case BFD_RELOC_ARM_THUMB_LOOP12:
29005 if (fixP->fx_addsy
29006 && (S_GET_SEGMENT (fixP->fx_addsy) == seg)
29007 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE)
29008 && ARM_IS_FUNC (fixP->fx_addsy)
29009 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v8_1m_main))
29010 {
29011 /* Force a relocation for a branch 12 bits wide. */
29012 fixP->fx_done = 0;
29013 }
29014
29015 bfd_vma insn = get_thumb32_insn (buf);
1f6234a3 29016 /* le lr, <label>, le <label> or letp lr, <label> */
60f993ce 29017 if (((insn & 0xffffffff) == 0xf00fc001)
1f6234a3
AV		 29018 || ((insn & 0xffffffff) == 0xf02fc001)
29019 || ((insn & 0xffffffff) == 0xf01fc001))
60f993ce
AV		 29020 value = -value;
29021
29022 if (v8_1_branch_value_check (value, 12, FALSE) == FAIL)
29023 as_bad_where (fixP->fx_file, fixP->fx_line,
29024 BAD_BRANCH_OFF);
29025 if (fixP->fx_done || !seg->use_rela_p)
29026 {
29027 addressT imml, immh;
29028
29029 immh = (value & 0x00000ffc) >> 2;
29030 imml = (value & 0x00000002) >> 1;
29031
29032 newval = md_chars_to_number (buf + THUMB_SIZE, THUMB_SIZE);
29033 newval |= (imml << 11) | (immh << 1);
29034 md_number_to_chars (buf + THUMB_SIZE, newval, THUMB_SIZE);
29035 }
29036 break;
29037
845b51d6
PB		 29038 case BFD_RELOC_ARM_V4BX:
29039 /* This will need to go in the object file. */
29040 fixP->fx_done = 0;
29041 break;
29042
c19d1205
ZW		 29043 case BFD_RELOC_UNUSED:
29044 default:
29045 as_bad_where (fixP->fx_file, fixP->fx_line,
29046 _("bad relocation fixup type (%d)"), fixP->fx_r_type);
29047 }
6c43fab6
RE		 29048}
29049
c19d1205
ZW		 29050/* Translate internal representation of relocation info to BFD target
29051 format. */
a737bd4d 29052
c19d1205 29053arelent *
00a97672 29054tc_gen_reloc (asection *section, fixS *fixp)
a737bd4d 29055{
c19d1205
ZW		 29056 arelent * reloc;
29057 bfd_reloc_code_real_type code;
a737bd4d 29058
325801bd 29059 reloc = XNEW (arelent);
a737bd4d 29060
325801bd 29061 reloc->sym_ptr_ptr = XNEW (asymbol *);
c19d1205
ZW		 29062 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
29063 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where;
a737bd4d 29064
2fc8bdac 29065 if (fixp->fx_pcrel)
00a97672
RS		 29066 {
29067 if (section->use_rela_p)
29068 fixp->fx_offset -= md_pcrel_from_section (fixp, section);
29069 else
29070 fixp->fx_offset = reloc->address;
29071 }
c19d1205 29072 reloc->addend = fixp->fx_offset;
a737bd4d 29073
c19d1205 29074 switch (fixp->fx_r_type)
a737bd4d 29075 {
c19d1205
ZW		 29076 case BFD_RELOC_8:
29077 if (fixp->fx_pcrel)
29078 {
29079 code = BFD_RELOC_8_PCREL;
29080 break;
29081 }
1a0670f3 29082 /* Fall through. */
a737bd4d 29083
c19d1205
ZW		 29084 case BFD_RELOC_16:
29085 if (fixp->fx_pcrel)
29086 {
29087 code = BFD_RELOC_16_PCREL;
29088 break;
29089 }
1a0670f3 29090 /* Fall through. */
6c43fab6 29091
c19d1205
ZW		 29092 case BFD_RELOC_32:
29093 if (fixp->fx_pcrel)
29094 {
29095 code = BFD_RELOC_32_PCREL;
29096 break;
29097 }
1a0670f3 29098 /* Fall through. */
a737bd4d 29099
b6895b4f
PB		 29100 case BFD_RELOC_ARM_MOVW:
29101 if (fixp->fx_pcrel)
29102 {
29103 code = BFD_RELOC_ARM_MOVW_PCREL;
29104 break;
29105 }
1a0670f3 29106 /* Fall through. */
b6895b4f
PB		 29107
29108 case BFD_RELOC_ARM_MOVT:
29109 if (fixp->fx_pcrel)
29110 {
29111 code = BFD_RELOC_ARM_MOVT_PCREL;
29112 break;
29113 }
1a0670f3 29114 /* Fall through. */
b6895b4f
PB		 29115
29116 case BFD_RELOC_ARM_THUMB_MOVW:
29117 if (fixp->fx_pcrel)
29118 {
29119 code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
29120 break;
29121 }
1a0670f3 29122 /* Fall through. */
b6895b4f
PB		 29123
29124 case BFD_RELOC_ARM_THUMB_MOVT:
29125 if (fixp->fx_pcrel)
29126 {
29127 code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
29128 break;
29129 }
1a0670f3 29130 /* Fall through. */
b6895b4f 29131
c19d1205
ZW		 29132 case BFD_RELOC_NONE:
29133 case BFD_RELOC_ARM_PCREL_BRANCH:
29134 case BFD_RELOC_ARM_PCREL_BLX:
29135 case BFD_RELOC_RVA:
29136 case BFD_RELOC_THUMB_PCREL_BRANCH7:
29137 case BFD_RELOC_THUMB_PCREL_BRANCH9:
29138 case BFD_RELOC_THUMB_PCREL_BRANCH12:
29139 case BFD_RELOC_THUMB_PCREL_BRANCH20:
29140 case BFD_RELOC_THUMB_PCREL_BRANCH23:
29141 case BFD_RELOC_THUMB_PCREL_BRANCH25:
c19d1205
ZW		 29142 case BFD_RELOC_VTABLE_ENTRY:
29143 case BFD_RELOC_VTABLE_INHERIT:
f0927246
NC		 29144#ifdef TE_PE
29145 case BFD_RELOC_32_SECREL:
29146#endif
c19d1205
ZW		 29147 code = fixp->fx_r_type;
29148 break;
a737bd4d 29149
00adf2d4
JB		 29150 case BFD_RELOC_THUMB_PCREL_BLX:
29151#ifdef OBJ_ELF
29152 if (EF_ARM_EABI_VERSION (meabi_flags) >= EF_ARM_EABI_VER4)
29153 code = BFD_RELOC_THUMB_PCREL_BRANCH23;
29154 else
29155#endif
29156 code = BFD_RELOC_THUMB_PCREL_BLX;
29157 break;
29158
c19d1205
ZW		 29159 case BFD_RELOC_ARM_LITERAL:
29160 case BFD_RELOC_ARM_HWLITERAL:
29161 /* If this is called then the a literal has
29162 been referenced across a section boundary. */
29163 as_bad_where (fixp->fx_file, fixp->fx_line,
29164 _("literal referenced across section boundary"));
29165 return NULL;
a737bd4d 29166
c19d1205 29167#ifdef OBJ_ELF
0855e32b
NS		 29168 case BFD_RELOC_ARM_TLS_CALL:
29169 case BFD_RELOC_ARM_THM_TLS_CALL:
29170 case BFD_RELOC_ARM_TLS_DESCSEQ:
29171 case BFD_RELOC_ARM_THM_TLS_DESCSEQ:
c19d1205
ZW		 29172 case BFD_RELOC_ARM_GOT32:
29173 case BFD_RELOC_ARM_GOTOFF:
b43420e6 29174 case BFD_RELOC_ARM_GOT_PREL:
c19d1205
ZW		 29175 case BFD_RELOC_ARM_PLT32:
29176 case BFD_RELOC_ARM_TARGET1:
29177 case BFD_RELOC_ARM_ROSEGREL32:
29178 case BFD_RELOC_ARM_SBREL32:
29179 case BFD_RELOC_ARM_PREL31:
29180 case BFD_RELOC_ARM_TARGET2:
c19d1205 29181 case BFD_RELOC_ARM_TLS_LDO32:
39b41c9c
PB		 29182 case BFD_RELOC_ARM_PCREL_CALL:
29183 case BFD_RELOC_ARM_PCREL_JUMP:
4962c51a
MS		 29184 case BFD_RELOC_ARM_ALU_PC_G0_NC:
29185 case BFD_RELOC_ARM_ALU_PC_G0:
29186 case BFD_RELOC_ARM_ALU_PC_G1_NC:
29187 case BFD_RELOC_ARM_ALU_PC_G1:
29188 case BFD_RELOC_ARM_ALU_PC_G2:
29189 case BFD_RELOC_ARM_LDR_PC_G0:
29190 case BFD_RELOC_ARM_LDR_PC_G1:
29191 case BFD_RELOC_ARM_LDR_PC_G2:
29192 case BFD_RELOC_ARM_LDRS_PC_G0:
29193 case BFD_RELOC_ARM_LDRS_PC_G1:
29194 case BFD_RELOC_ARM_LDRS_PC_G2:
29195 case BFD_RELOC_ARM_LDC_PC_G0:
29196 case BFD_RELOC_ARM_LDC_PC_G1:
29197 case BFD_RELOC_ARM_LDC_PC_G2:
29198 case BFD_RELOC_ARM_ALU_SB_G0_NC:
29199 case BFD_RELOC_ARM_ALU_SB_G0:
29200 case BFD_RELOC_ARM_ALU_SB_G1_NC:
29201 case BFD_RELOC_ARM_ALU_SB_G1:
29202 case BFD_RELOC_ARM_ALU_SB_G2:
29203 case BFD_RELOC_ARM_LDR_SB_G0:
29204 case BFD_RELOC_ARM_LDR_SB_G1:
29205 case BFD_RELOC_ARM_LDR_SB_G2:
29206 case BFD_RELOC_ARM_LDRS_SB_G0:
29207 case BFD_RELOC_ARM_LDRS_SB_G1:
29208 case BFD_RELOC_ARM_LDRS_SB_G2:
29209 case BFD_RELOC_ARM_LDC_SB_G0:
29210 case BFD_RELOC_ARM_LDC_SB_G1:
29211 case BFD_RELOC_ARM_LDC_SB_G2:
845b51d6 29212 case BFD_RELOC_ARM_V4BX:
72d98d16
MG		 29213 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC:
29214 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC:
29215 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC:
29216 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC:
188fd7ae
CL		 29217 case BFD_RELOC_ARM_GOTFUNCDESC:
29218 case BFD_RELOC_ARM_GOTOFFFUNCDESC:
29219 case BFD_RELOC_ARM_FUNCDESC:
e5d6e09e 29220 case BFD_RELOC_ARM_THUMB_BF17:
1caf72a5 29221 case BFD_RELOC_ARM_THUMB_BF19:
1889da70 29222 case BFD_RELOC_ARM_THUMB_BF13:
c19d1205
ZW		 29223 code = fixp->fx_r_type;
29224 break;
a737bd4d 29225
0855e32b 29226 case BFD_RELOC_ARM_TLS_GOTDESC:
c19d1205 29227 case BFD_RELOC_ARM_TLS_GD32:
5c5a4843 29228 case BFD_RELOC_ARM_TLS_GD32_FDPIC:
75c11999 29229 case BFD_RELOC_ARM_TLS_LE32:
c19d1205 29230 case BFD_RELOC_ARM_TLS_IE32:
5c5a4843 29231 case BFD_RELOC_ARM_TLS_IE32_FDPIC:
c19d1205 29232 case BFD_RELOC_ARM_TLS_LDM32:
5c5a4843 29233 case BFD_RELOC_ARM_TLS_LDM32_FDPIC:
c19d1205
ZW		 29234 /* BFD will include the symbol's address in the addend.
29235 But we don't want that, so subtract it out again here. */
29236 if (!S_IS_COMMON (fixp->fx_addsy))
29237 reloc->addend -= (*reloc->sym_ptr_ptr)->value;
29238 code = fixp->fx_r_type;
29239 break;
29240#endif
a737bd4d 29241
c19d1205
ZW		 29242 case BFD_RELOC_ARM_IMMEDIATE:
29243 as_bad_where (fixp->fx_file, fixp->fx_line,
29244 _("internal relocation (type: IMMEDIATE) not fixed up"));
29245 return NULL;
a737bd4d 29246
c19d1205
ZW		 29247 case BFD_RELOC_ARM_ADRL_IMMEDIATE:
29248 as_bad_where (fixp->fx_file, fixp->fx_line,
29249 _("ADRL used for a symbol not defined in the same file"));
29250 return NULL;
a737bd4d 29251
e12437dc 29252 case BFD_RELOC_THUMB_PCREL_BRANCH5:
f6b2b12d 29253 case BFD_RELOC_THUMB_PCREL_BFCSEL:
60f993ce 29254 case BFD_RELOC_ARM_THUMB_LOOP12:
e12437dc
AV		 29255 as_bad_where (fixp->fx_file, fixp->fx_line,
29256 _("%s used for a symbol not defined in the same file"),
29257 bfd_get_reloc_code_name (fixp->fx_r_type));
29258 return NULL;
29259
c19d1205 29260 case BFD_RELOC_ARM_OFFSET_IMM:
00a97672
RS		 29261 if (section->use_rela_p)
29262 {
29263 code = fixp->fx_r_type;
29264 break;
29265 }
29266
c19d1205
ZW		 29267 if (fixp->fx_addsy != NULL
29268 && !S_IS_DEFINED (fixp->fx_addsy)
29269 && S_IS_LOCAL (fixp->fx_addsy))
a737bd4d 29270 {
c19d1205
ZW		 29271 as_bad_where (fixp->fx_file, fixp->fx_line,
29272 _("undefined local label `%s'"),
29273 S_GET_NAME (fixp->fx_addsy));
29274 return NULL;
a737bd4d
NC		 29275 }
29276
c19d1205
ZW		 29277 as_bad_where (fixp->fx_file, fixp->fx_line,
29278 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29279 return NULL;
a737bd4d 29280
c19d1205
ZW		 29281 default:
29282 {
e0471c16 29283 const char * type;
6c43fab6 29284
c19d1205
ZW		 29285 switch (fixp->fx_r_type)
29286 {
29287 case BFD_RELOC_NONE: type = "NONE"; break;
29288 case BFD_RELOC_ARM_OFFSET_IMM8: type = "OFFSET_IMM8"; break;
29289 case BFD_RELOC_ARM_SHIFT_IMM: type = "SHIFT_IMM"; break;
3eb17e6b 29290 case BFD_RELOC_ARM_SMC: type = "SMC"; break;
c19d1205
ZW		 29291 case BFD_RELOC_ARM_SWI: type = "SWI"; break;
29292 case BFD_RELOC_ARM_MULTI: type = "MULTI"; break;
29293 case BFD_RELOC_ARM_CP_OFF_IMM: type = "CP_OFF_IMM"; break;
db187cb9 29294 case BFD_RELOC_ARM_T32_OFFSET_IMM: type = "T32_OFFSET_IMM"; break;
8f06b2d8 29295 case BFD_RELOC_ARM_T32_CP_OFF_IMM: type = "T32_CP_OFF_IMM"; break;
c19d1205
ZW		 29296 case BFD_RELOC_ARM_THUMB_ADD: type = "THUMB_ADD"; break;
29297 case BFD_RELOC_ARM_THUMB_SHIFT: type = "THUMB_SHIFT"; break;
29298 case BFD_RELOC_ARM_THUMB_IMM: type = "THUMB_IMM"; break;
29299 case BFD_RELOC_ARM_THUMB_OFFSET: type = "THUMB_OFFSET"; break;
29300 default: type = _("<unknown>"); break;
29301 }
29302 as_bad_where (fixp->fx_file, fixp->fx_line,
29303 _("cannot represent %s relocation in this object file format"),
29304 type);
29305 return NULL;
29306 }
a737bd4d 29307 }
6c43fab6 29308
c19d1205
ZW		 29309#ifdef OBJ_ELF
29310 if ((code == BFD_RELOC_32_PCREL || code == BFD_RELOC_32)
29311 && GOT_symbol
29312 && fixp->fx_addsy == GOT_symbol)
29313 {
29314 code = BFD_RELOC_ARM_GOTPC;
29315 reloc->addend = fixp->fx_offset = reloc->address;
29316 }
29317#endif
6c43fab6 29318
c19d1205 29319 reloc->howto = bfd_reloc_type_lookup (stdoutput, code);
6c43fab6 29320
c19d1205
ZW		 29321 if (reloc->howto == NULL)
29322 {
29323 as_bad_where (fixp->fx_file, fixp->fx_line,
29324 _("cannot represent %s relocation in this object file format"),
29325 bfd_get_reloc_code_name (code));
29326 return NULL;
29327 }
6c43fab6 29328
c19d1205
ZW		 29329 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29330 vtable entry to be used in the relocation's section offset. */
29331 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
29332 reloc->address = fixp->fx_offset;
6c43fab6 29333
c19d1205 29334 return reloc;
6c43fab6
RE		 29335}
29336
c19d1205 29337/* This fix_new is called by cons via TC_CONS_FIX_NEW. */
6c43fab6 29338
c19d1205
ZW		 29339void
29340cons_fix_new_arm (fragS * frag,
29341 int where,
29342 int size,
62ebcb5c
AM		 29343 expressionS * exp,
29344 bfd_reloc_code_real_type reloc)
6c43fab6 29345{
c19d1205 29346 int pcrel = 0;
6c43fab6 29347
c19d1205
ZW		 29348 /* Pick a reloc.
29349 FIXME: @@ Should look at CPU word size. */
29350 switch (size)
29351 {
29352 case 1:
62ebcb5c 29353 reloc = BFD_RELOC_8;
c19d1205
ZW		 29354 break;
29355 case 2:
62ebcb5c 29356 reloc = BFD_RELOC_16;
c19d1205
ZW		 29357 break;
29358 case 4:
29359 default:
62ebcb5c 29360 reloc = BFD_RELOC_32;
c19d1205
ZW		 29361 break;
29362 case 8:
62ebcb5c 29363 reloc = BFD_RELOC_64;
c19d1205
ZW		 29364 break;
29365 }
6c43fab6 29366
f0927246
NC		 29367#ifdef TE_PE
29368 if (exp->X_op == O_secrel)
29369 {
29370 exp->X_op = O_symbol;
62ebcb5c 29371 reloc = BFD_RELOC_32_SECREL;
f0927246
NC		 29372 }
29373#endif
29374
62ebcb5c 29375 fix_new_exp (frag, where, size, exp, pcrel, reloc);
c19d1205 29376}
6c43fab6 29377
4343666d 29378#if defined (OBJ_COFF)
c19d1205
ZW		 29379void
29380arm_validate_fix (fixS * fixP)
6c43fab6 29381{
c19d1205
ZW		 29382 /* If the destination of the branch is a defined symbol which does not have
29383 the THUMB_FUNC attribute, then we must be calling a function which has
29384 the (interfacearm) attribute. We look for the Thumb entry point to that
29385 function and change the branch to refer to that function instead. */
29386 if (fixP->fx_r_type == BFD_RELOC_THUMB_PCREL_BRANCH23
29387 && fixP->fx_addsy != NULL
29388 && S_IS_DEFINED (fixP->fx_addsy)
29389 && ! THUMB_IS_FUNC (fixP->fx_addsy))
6c43fab6 29390 {
c19d1205 29391 fixP->fx_addsy = find_real_start (fixP->fx_addsy);
6c43fab6 29392 }
c19d1205
ZW		 29393}
29394#endif
6c43fab6 29395
267bf995 29396
c19d1205
ZW		 29397int
29398arm_force_relocation (struct fix * fixp)
29399{
29400#if defined (OBJ_COFF) && defined (TE_PE)
29401 if (fixp->fx_r_type == BFD_RELOC_RVA)
29402 return 1;
29403#endif
6c43fab6 29404
267bf995
RR		 29405 /* In case we have a call or a branch to a function in ARM ISA mode from
29406 a thumb function or vice-versa force the relocation. These relocations
29407 are cleared off for some cores that might have blx and simple transformations
29408 are possible. */
29409
29410#ifdef OBJ_ELF
29411 switch (fixp->fx_r_type)
29412 {
29413 case BFD_RELOC_ARM_PCREL_JUMP:
29414 case BFD_RELOC_ARM_PCREL_CALL:
29415 case BFD_RELOC_THUMB_PCREL_BLX:
29416 if (THUMB_IS_FUNC (fixp->fx_addsy))
29417 return 1;
29418 break;
29419
29420 case BFD_RELOC_ARM_PCREL_BLX:
29421 case BFD_RELOC_THUMB_PCREL_BRANCH25:
29422 case BFD_RELOC_THUMB_PCREL_BRANCH20:
29423 case BFD_RELOC_THUMB_PCREL_BRANCH23:
29424 if (ARM_IS_FUNC (fixp->fx_addsy))
29425 return 1;
29426 break;
29427
29428 default:
29429 break;
29430 }
29431#endif
29432
b5884301
PB		 29433 /* Resolve these relocations even if the symbol is extern or weak.
29434 Technically this is probably wrong due to symbol preemption.
29435 In practice these relocations do not have enough range to be useful
29436 at dynamic link time, and some code (e.g. in the Linux kernel)
29437 expects these references to be resolved. */
c19d1205
ZW		 29438 if (fixp->fx_r_type == BFD_RELOC_ARM_IMMEDIATE
29439 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM
b5884301 29440 || fixp->fx_r_type == BFD_RELOC_ARM_OFFSET_IMM8
0110f2b8 29441 || fixp->fx_r_type == BFD_RELOC_ARM_ADRL_IMMEDIATE
b5884301
PB		 29442 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM
29443 || fixp->fx_r_type == BFD_RELOC_ARM_CP_OFF_IMM_S2
29444 || fixp->fx_r_type == BFD_RELOC_ARM_THUMB_OFFSET
16805f35 29445 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM
0110f2b8
PB		 29446 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
29447 || fixp->fx_r_type == BFD_RELOC_ARM_T32_IMM12
b5884301
PB		 29448 || fixp->fx_r_type == BFD_RELOC_ARM_T32_OFFSET_IMM
29449 || fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12
29450 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM
29451 || fixp->fx_r_type == BFD_RELOC_ARM_T32_CP_OFF_IMM_S2)
c19d1205 29452 return 0;
a737bd4d 29453
4962c51a
MS		 29454 /* Always leave these relocations for the linker. */
29455 if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29456 && fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29457 || fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
29458 return 1;
29459
f0291e4c
PB		 29460 /* Always generate relocations against function symbols. */
29461 if (fixp->fx_r_type == BFD_RELOC_32
29462 && fixp->fx_addsy
29463 && (symbol_get_bfdsym (fixp->fx_addsy)->flags & BSF_FUNCTION))
29464 return 1;
29465
c19d1205 29466 return generic_force_reloc (fixp);
404ff6b5
AH		 29467}
29468
0ffdc86c 29469#if defined (OBJ_ELF) || defined (OBJ_COFF)
e28387c3
PB		 29470/* Relocations against function names must be left unadjusted,
29471 so that the linker can use this information to generate interworking
29472 stubs. The MIPS version of this function
c19d1205
ZW		 29473 also prevents relocations that are mips-16 specific, but I do not
29474 know why it does this.
404ff6b5 29475
c19d1205
ZW		 29476 FIXME:
29477 There is one other problem that ought to be addressed here, but
29478 which currently is not: Taking the address of a label (rather
29479 than a function) and then later jumping to that address. Such
29480 addresses also ought to have their bottom bit set (assuming that
29481 they reside in Thumb code), but at the moment they will not. */
404ff6b5 29482
c19d1205
ZW		 29483bfd_boolean
29484arm_fix_adjustable (fixS * fixP)
404ff6b5 29485{
c19d1205
ZW		 29486 if (fixP->fx_addsy == NULL)
29487 return 1;
404ff6b5 29488
e28387c3
PB		 29489 /* Preserve relocations against symbols with function type. */
29490 if (symbol_get_bfdsym (fixP->fx_addsy)->flags & BSF_FUNCTION)
c921be7d 29491 return FALSE;
e28387c3 29492
c19d1205
ZW		 29493 if (THUMB_IS_FUNC (fixP->fx_addsy)
29494 && fixP->fx_subsy == NULL)
c921be7d 29495 return FALSE;
a737bd4d 29496
c19d1205
ZW		 29497 /* We need the symbol name for the VTABLE entries. */
29498 if ( fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
29499 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
c921be7d 29500 return FALSE;
404ff6b5 29501
c19d1205
ZW		 29502 /* Don't allow symbols to be discarded on GOT related relocs. */
29503 if (fixP->fx_r_type == BFD_RELOC_ARM_PLT32
29504 || fixP->fx_r_type == BFD_RELOC_ARM_GOT32
29505 || fixP->fx_r_type == BFD_RELOC_ARM_GOTOFF
29506 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32
5c5a4843 29507 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GD32_FDPIC
c19d1205
ZW		 29508 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LE32
29509 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32
5c5a4843 29510 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_IE32_FDPIC
c19d1205 29511 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32
5c5a4843 29512 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDM32_FDPIC
c19d1205 29513 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_LDO32
0855e32b
NS		 29514 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_GOTDESC
29515 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_CALL
29516 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_CALL
29517 || fixP->fx_r_type == BFD_RELOC_ARM_TLS_DESCSEQ
29518 || fixP->fx_r_type == BFD_RELOC_ARM_THM_TLS_DESCSEQ
c19d1205 29519 || fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
c921be7d 29520 return FALSE;
a737bd4d 29521
4962c51a
MS		 29522 /* Similarly for group relocations. */
29523 if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
29524 && fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
29525 || fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
c921be7d 29526 return FALSE;
4962c51a 29527
79947c54
CD		 29528 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29529 if (fixP->fx_r_type == BFD_RELOC_ARM_MOVW
29530 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT
29531 || fixP->fx_r_type == BFD_RELOC_ARM_MOVW_PCREL
29532 || fixP->fx_r_type == BFD_RELOC_ARM_MOVT_PCREL
29533 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW
29534 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT
29535 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVW_PCREL
29536 || fixP->fx_r_type == BFD_RELOC_ARM_THUMB_MOVT_PCREL)
c921be7d 29537 return FALSE;
79947c54 29538
72d98d16
MG		 29539 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29540 offsets, so keep these symbols. */
29541 if (fixP->fx_r_type >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29542 && fixP->fx_r_type <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC)
29543 return FALSE;
29544
c921be7d 29545 return TRUE;
a737bd4d 29546}
0ffdc86c
NC		 29547#endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29548
29549#ifdef OBJ_ELF
c19d1205
ZW		 29550const char *
29551elf32_arm_target_format (void)
404ff6b5 29552{
c19d1205
ZW		 29553#ifdef TE_SYMBIAN
29554 return (target_big_endian
29555 ? "elf32-bigarm-symbian"
29556 : "elf32-littlearm-symbian");
29557#elif defined (TE_VXWORKS)
29558 return (target_big_endian
29559 ? "elf32-bigarm-vxworks"
29560 : "elf32-littlearm-vxworks");
b38cadfb
NC		 29561#elif defined (TE_NACL)
29562 return (target_big_endian
29563 ? "elf32-bigarm-nacl"
29564 : "elf32-littlearm-nacl");
c19d1205 29565#else
18a20338
CL		 29566 if (arm_fdpic)
29567 {
29568 if (target_big_endian)
29569 return "elf32-bigarm-fdpic";
29570 else
29571 return "elf32-littlearm-fdpic";
29572 }
c19d1205 29573 else
18a20338
CL		 29574 {
29575 if (target_big_endian)
29576 return "elf32-bigarm";
29577 else
29578 return "elf32-littlearm";
29579 }
c19d1205 29580#endif
404ff6b5
AH		 29581}
29582
c19d1205
ZW		 29583void
29584armelf_frob_symbol (symbolS * symp,
29585 int * puntp)
404ff6b5 29586{
c19d1205
ZW		 29587 elf_frob_symbol (symp, puntp);
29588}
29589#endif
404ff6b5 29590
c19d1205 29591/* MD interface: Finalization. */
a737bd4d 29592
c19d1205
ZW		 29593void
29594arm_cleanup (void)
29595{
29596 literal_pool * pool;
a737bd4d 29597
5ee91343
AV		 29598 /* Ensure that all the predication blocks are properly closed. */
29599 check_pred_blocks_finished ();
e07e6e58 29600
c19d1205
ZW		 29601 for (pool = list_of_pools; pool; pool = pool->next)
29602 {
5f4273c7 29603 /* Put it at the end of the relevant section. */
c19d1205
ZW		 29604 subseg_set (pool->section, pool->sub_section);
29605#ifdef OBJ_ELF
29606 arm_elf_change_section ();
29607#endif
29608 s_ltorg (0);
29609 }
404ff6b5
AH		 29610}
29611
cd000bff
DJ		 29612#ifdef OBJ_ELF
29613/* Remove any excess mapping symbols generated for alignment frags in
29614 SEC. We may have created a mapping symbol before a zero byte
29615 alignment; remove it if there's a mapping symbol after the
29616 alignment. */
29617static void
29618check_mapping_symbols (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
29619 void *dummy ATTRIBUTE_UNUSED)
29620{
29621 segment_info_type *seginfo = seg_info (sec);
29622 fragS *fragp;
29623
29624 if (seginfo == NULL || seginfo->frchainP == NULL)
29625 return;
29626
29627 for (fragp = seginfo->frchainP->frch_root;
29628 fragp != NULL;
29629 fragp = fragp->fr_next)
29630 {
29631 symbolS *sym = fragp->tc_frag_data.last_map;
29632 fragS *next = fragp->fr_next;
29633
29634 /* Variable-sized frags have been converted to fixed size by
29635 this point. But if this was variable-sized to start with,
29636 there will be a fixed-size frag after it. So don't handle
29637 next == NULL. */
29638 if (sym == NULL || next == NULL)
29639 continue;
29640
29641 if (S_GET_VALUE (sym) < next->fr_address)
29642 /* Not at the end of this frag. */
29643 continue;
29644 know (S_GET_VALUE (sym) == next->fr_address);
29645
29646 do
29647 {
29648 if (next->tc_frag_data.first_map != NULL)
29649 {
29650 /* Next frag starts with a mapping symbol. Discard this
29651 one. */
29652 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29653 break;
29654 }
29655
29656 if (next->fr_next == NULL)
29657 {
29658 /* This mapping symbol is at the end of the section. Discard
29659 it. */
29660 know (next->fr_fix == 0 && next->fr_var == 0);
29661 symbol_remove (sym, &symbol_rootP, &symbol_lastP);
29662 break;
29663 }
29664
29665 /* As long as we have empty frags without any mapping symbols,
29666 keep looking. */
29667 /* If the next frag is non-empty and does not start with a
29668 mapping symbol, then this mapping symbol is required. */
29669 if (next->fr_address != next->fr_next->fr_address)
29670 break;
29671
29672 next = next->fr_next;
29673 }
29674 while (next != NULL);
29675 }
29676}
29677#endif
29678
c19d1205
ZW		 29679/* Adjust the symbol table. This marks Thumb symbols as distinct from
29680 ARM ones. */
404ff6b5 29681
c19d1205
ZW		 29682void
29683arm_adjust_symtab (void)
404ff6b5 29684{
c19d1205
ZW		 29685#ifdef OBJ_COFF
29686 symbolS * sym;
404ff6b5 29687
c19d1205
ZW		 29688 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
29689 {
29690 if (ARM_IS_THUMB (sym))
29691 {
29692 if (THUMB_IS_FUNC (sym))
29693 {
29694 /* Mark the symbol as a Thumb function. */
29695 if ( S_GET_STORAGE_CLASS (sym) == C_STAT
29696 || S_GET_STORAGE_CLASS (sym) == C_LABEL) /* This can happen! */
29697 S_SET_STORAGE_CLASS (sym, C_THUMBSTATFUNC);
404ff6b5 29698
c19d1205
ZW		 29699 else if (S_GET_STORAGE_CLASS (sym) == C_EXT)
29700 S_SET_STORAGE_CLASS (sym, C_THUMBEXTFUNC);
29701 else
29702 as_bad (_("%s: unexpected function type: %d"),
29703 S_GET_NAME (sym), S_GET_STORAGE_CLASS (sym));
29704 }
29705 else switch (S_GET_STORAGE_CLASS (sym))
29706 {
29707 case C_EXT:
29708 S_SET_STORAGE_CLASS (sym, C_THUMBEXT);
29709 break;
29710 case C_STAT:
29711 S_SET_STORAGE_CLASS (sym, C_THUMBSTAT);
29712 break;
29713 case C_LABEL:
29714 S_SET_STORAGE_CLASS (sym, C_THUMBLABEL);
29715 break;
29716 default:
29717 /* Do nothing. */
29718 break;
29719 }
29720 }
a737bd4d 29721
c19d1205
ZW		 29722 if (ARM_IS_INTERWORK (sym))
29723 coffsymbol (symbol_get_bfdsym (sym))->native->u.syment.n_flags = 0xFF;
404ff6b5 29724 }
c19d1205
ZW		 29725#endif
29726#ifdef OBJ_ELF
29727 symbolS * sym;
29728 char bind;
404ff6b5 29729
c19d1205 29730 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym))
404ff6b5 29731 {
c19d1205
ZW		 29732 if (ARM_IS_THUMB (sym))
29733 {
29734 elf_symbol_type * elf_sym;
404ff6b5 29735
c19d1205
ZW		 29736 elf_sym = elf_symbol (symbol_get_bfdsym (sym));
29737 bind = ELF_ST_BIND (elf_sym->internal_elf_sym.st_info);
404ff6b5 29738
b0796911
PB		 29739 if (! bfd_is_arm_special_symbol_name (elf_sym->symbol.name,
29740 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
c19d1205
ZW		 29741 {
29742 /* If it's a .thumb_func, declare it as so,
29743 otherwise tag label as .code 16. */
29744 if (THUMB_IS_FUNC (sym))
39d911fc
TP		 29745 ARM_SET_SYM_BRANCH_TYPE (elf_sym->internal_elf_sym.st_target_internal,
29746 ST_BRANCH_TO_THUMB);
3ba67470 29747 else if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
c19d1205
ZW		 29748 elf_sym->internal_elf_sym.st_info =
29749 ELF_ST_INFO (bind, STT_ARM_16BIT);
29750 }
29751 }
29752 }
cd000bff
DJ		 29753
29754 /* Remove any overlapping mapping symbols generated by alignment frags. */
29755 bfd_map_over_sections (stdoutput, check_mapping_symbols, (char *) 0);
709001e9
MM		 29756 /* Now do generic ELF adjustments. */
29757 elf_adjust_symtab ();
c19d1205 29758#endif
404ff6b5
AH		 29759}
29760
c19d1205 29761/* MD interface: Initialization. */
404ff6b5 29762
a737bd4d 29763static void
c19d1205 29764set_constant_flonums (void)
a737bd4d 29765{
c19d1205 29766 int i;
404ff6b5 29767
c19d1205
ZW		 29768 for (i = 0; i < NUM_FLOAT_VALS; i++)
29769 if (atof_ieee ((char *) fp_const[i], 'x', fp_values[i]) == NULL)
29770 abort ();
a737bd4d 29771}
404ff6b5 29772
3e9e4fcf
JB		 29773/* Auto-select Thumb mode if it's the only available instruction set for the
29774 given architecture. */
29775
29776static void
29777autoselect_thumb_from_cpu_variant (void)
29778{
29779 if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v1))
29780 opcode_select (16);
29781}
29782
c19d1205
ZW		 29783void
29784md_begin (void)
a737bd4d 29785{
c19d1205
ZW		 29786 unsigned mach;
29787 unsigned int i;
404ff6b5 29788
c19d1205
ZW		 29789 if ( (arm_ops_hsh = hash_new ()) == NULL
29790 || (arm_cond_hsh = hash_new ()) == NULL
5ee91343 29791 || (arm_vcond_hsh = hash_new ()) == NULL
c19d1205
ZW		 29792 || (arm_shift_hsh = hash_new ()) == NULL
29793 || (arm_psr_hsh = hash_new ()) == NULL
62b3e311 29794 || (arm_v7m_psr_hsh = hash_new ()) == NULL
c19d1205 29795 || (arm_reg_hsh = hash_new ()) == NULL
62b3e311
PB		 29796 || (arm_reloc_hsh = hash_new ()) == NULL
29797 || (arm_barrier_opt_hsh = hash_new ()) == NULL)
c19d1205
ZW		 29798 as_fatal (_("virtual memory exhausted"));
29799
29800 for (i = 0; i < sizeof (insns) / sizeof (struct asm_opcode); i++)
d3ce72d0 29801 hash_insert (arm_ops_hsh, insns[i].template_name, (void *) (insns + i));
c19d1205 29802 for (i = 0; i < sizeof (conds) / sizeof (struct asm_cond); i++)
d3ce72d0 29803 hash_insert (arm_cond_hsh, conds[i].template_name, (void *) (conds + i));
5ee91343
AV		 29804 for (i = 0; i < sizeof (vconds) / sizeof (struct asm_cond); i++)
29805 hash_insert (arm_vcond_hsh, vconds[i].template_name, (void *) (vconds + i));
c19d1205 29806 for (i = 0; i < sizeof (shift_names) / sizeof (struct asm_shift_name); i++)
5a49b8ac 29807 hash_insert (arm_shift_hsh, shift_names[i].name, (void *) (shift_names + i));
c19d1205 29808 for (i = 0; i < sizeof (psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 29809 hash_insert (arm_psr_hsh, psrs[i].template_name, (void *) (psrs + i));
62b3e311 29810 for (i = 0; i < sizeof (v7m_psrs) / sizeof (struct asm_psr); i++)
d3ce72d0 29811 hash_insert (arm_v7m_psr_hsh, v7m_psrs[i].template_name,
477330fc 29812 (void *) (v7m_psrs + i));
c19d1205 29813 for (i = 0; i < sizeof (reg_names) / sizeof (struct reg_entry); i++)
5a49b8ac 29814 hash_insert (arm_reg_hsh, reg_names[i].name, (void *) (reg_names + i));
62b3e311
PB		 29815 for (i = 0;
29816 i < sizeof (barrier_opt_names) / sizeof (struct asm_barrier_opt);
29817 i++)
d3ce72d0 29818 hash_insert (arm_barrier_opt_hsh, barrier_opt_names[i].template_name,
5a49b8ac 29819 (void *) (barrier_opt_names + i));
c19d1205 29820#ifdef OBJ_ELF
3da1d841
NC		 29821 for (i = 0; i < ARRAY_SIZE (reloc_names); i++)
29822 {
29823 struct reloc_entry * entry = reloc_names + i;
29824
29825 if (arm_is_eabi() && entry->reloc == BFD_RELOC_ARM_PLT32)
29826 /* This makes encode_branch() use the EABI versions of this relocation. */
29827 entry->reloc = BFD_RELOC_UNUSED;
29828
29829 hash_insert (arm_reloc_hsh, entry->name, (void *) entry);
29830 }
c19d1205
ZW		 29831#endif
29832
29833 set_constant_flonums ();
404ff6b5 29834
c19d1205
ZW		 29835 /* Set the cpu variant based on the command-line options. We prefer
29836 -mcpu= over -march= if both are set (as for GCC); and we prefer
29837 -mfpu= over any other way of setting the floating point unit.
29838 Use of legacy options with new options are faulted. */
e74cfd16 29839 if (legacy_cpu)
404ff6b5 29840 {
e74cfd16 29841 if (mcpu_cpu_opt || march_cpu_opt)
c19d1205
ZW		 29842 as_bad (_("use of old and new-style options to set CPU type"));
29843
4d354d8b 29844 selected_arch = *legacy_cpu;
404ff6b5 29845 }
4d354d8b
TP		 29846 else if (mcpu_cpu_opt)
29847 {
29848 selected_arch = *mcpu_cpu_opt;
29849 selected_ext = *mcpu_ext_opt;
29850 }
29851 else if (march_cpu_opt)
c168ce07 29852 {
4d354d8b
TP		 29853 selected_arch = *march_cpu_opt;
29854 selected_ext = *march_ext_opt;
c168ce07 29855 }
4d354d8b 29856 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
404ff6b5 29857
e74cfd16 29858 if (legacy_fpu)
c19d1205 29859 {
e74cfd16 29860 if (mfpu_opt)
c19d1205 29861 as_bad (_("use of old and new-style options to set FPU type"));
03b1477f 29862
4d354d8b 29863 selected_fpu = *legacy_fpu;
03b1477f 29864 }
4d354d8b
TP		 29865 else if (mfpu_opt)
29866 selected_fpu = *mfpu_opt;
29867 else
03b1477f 29868 {
45eb4c1b
NS		 29869#if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29870 || defined (TE_NetBSD) || defined (TE_VXWORKS))
39c2da32
RE		 29871 /* Some environments specify a default FPU. If they don't, infer it
29872 from the processor. */
e74cfd16 29873 if (mcpu_fpu_opt)
4d354d8b 29874 selected_fpu = *mcpu_fpu_opt;
e7da50fa 29875 else if (march_fpu_opt)
4d354d8b 29876 selected_fpu = *march_fpu_opt;
39c2da32 29877#else
4d354d8b 29878 selected_fpu = fpu_default;
39c2da32 29879#endif
03b1477f
RE		 29880 }
29881
4d354d8b 29882 if (ARM_FEATURE_ZERO (selected_fpu))
03b1477f 29883 {
4d354d8b
TP		 29884 if (!no_cpu_selected ())
29885 selected_fpu = fpu_default;
03b1477f 29886 else
4d354d8b 29887 selected_fpu = fpu_arch_fpa;
03b1477f
RE		 29888 }
29889
ee065d83 29890#ifdef CPU_DEFAULT
4d354d8b 29891 if (ARM_FEATURE_ZERO (selected_arch))
ee065d83 29892 {
4d354d8b
TP		 29893 selected_arch = cpu_default;
29894 selected_cpu = selected_arch;
ee065d83 29895 }
4d354d8b 29896 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
e74cfd16 29897#else
4d354d8b
TP		 29898 /* Autodection of feature mode: allow all features in cpu_variant but leave
29899 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29900 after all instruction have been processed and we can decide what CPU
29901 should be selected. */
29902 if (ARM_FEATURE_ZERO (selected_arch))
29903 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
ee065d83 29904 else
4d354d8b 29905 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83 29906#endif
03b1477f 29907
3e9e4fcf
JB		 29908 autoselect_thumb_from_cpu_variant ();
29909
e74cfd16 29910 arm_arch_used = thumb_arch_used = arm_arch_none;
ee065d83 29911
f17c130b 29912#if defined OBJ_COFF || defined OBJ_ELF
b99bd4ef 29913 {
7cc69913
NC		 29914 unsigned int flags = 0;
29915
29916#if defined OBJ_ELF
29917 flags = meabi_flags;
d507cf36
PB		 29918
29919 switch (meabi_flags)
33a392fb 29920 {
d507cf36 29921 case EF_ARM_EABI_UNKNOWN:
7cc69913 29922#endif
d507cf36
PB		 29923 /* Set the flags in the private structure. */
29924 if (uses_apcs_26) flags |= F_APCS26;
29925 if (support_interwork) flags |= F_INTERWORK;
29926 if (uses_apcs_float) flags |= F_APCS_FLOAT;
c19d1205 29927 if (pic_code) flags |= F_PIC;
e74cfd16 29928 if (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_any_hard))
7cc69913
NC		 29929 flags |= F_SOFT_FLOAT;
29930
d507cf36
PB		 29931 switch (mfloat_abi_opt)
29932 {
29933 case ARM_FLOAT_ABI_SOFT:
29934 case ARM_FLOAT_ABI_SOFTFP:
29935 flags |= F_SOFT_FLOAT;
29936 break;
33a392fb 29937
d507cf36
PB		 29938 case ARM_FLOAT_ABI_HARD:
29939 if (flags & F_SOFT_FLOAT)
29940 as_bad (_("hard-float conflicts with specified fpu"));
29941 break;
29942 }
03b1477f 29943
e74cfd16
PB		 29944 /* Using pure-endian doubles (even if soft-float). */
29945 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_endian_pure))
7cc69913 29946 flags |= F_VFP_FLOAT;
f17c130b 29947
fde78edd 29948#if defined OBJ_ELF
e74cfd16 29949 if (ARM_CPU_HAS_FEATURE (cpu_variant, fpu_arch_maverick))
d507cf36 29950 flags |= EF_ARM_MAVERICK_FLOAT;
d507cf36
PB		 29951 break;
29952
8cb51566 29953 case EF_ARM_EABI_VER4:
3a4a14e9 29954 case EF_ARM_EABI_VER5:
c19d1205 29955 /* No additional flags to set. */
d507cf36
PB		 29956 break;
29957
29958 default:
29959 abort ();
29960 }
7cc69913 29961#endif
b99bd4ef
NC		 29962 bfd_set_private_flags (stdoutput, flags);
29963
29964 /* We have run out flags in the COFF header to encode the
29965 status of ATPCS support, so instead we create a dummy,
c19d1205 29966 empty, debug section called .arm.atpcs. */
b99bd4ef
NC		 29967 if (atpcs)
29968 {
29969 asection * sec;
29970
29971 sec = bfd_make_section (stdoutput, ".arm.atpcs");
29972
29973 if (sec != NULL)
29974 {
29975 bfd_set_section_flags
29976 (stdoutput, sec, SEC_READONLY | SEC_DEBUGGING /* | SEC_HAS_CONTENTS */);
29977 bfd_set_section_size (stdoutput, sec, 0);
29978 bfd_set_section_contents (stdoutput, sec, NULL, 0, 0);
29979 }
29980 }
7cc69913 29981 }
f17c130b 29982#endif
b99bd4ef
NC		 29983
29984 /* Record the CPU type as well. */
2d447fca
JM		 29985 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt2))
29986 mach = bfd_mach_arm_iWMMXt2;
29987 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_iwmmxt))
e16bb312 29988 mach = bfd_mach_arm_iWMMXt;
e74cfd16 29989 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_xscale))
b99bd4ef 29990 mach = bfd_mach_arm_XScale;
e74cfd16 29991 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_cext_maverick))
fde78edd 29992 mach = bfd_mach_arm_ep9312;
e74cfd16 29993 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5e))
b99bd4ef 29994 mach = bfd_mach_arm_5TE;
e74cfd16 29995 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v5))
b99bd4ef 29996 {
e74cfd16 29997 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 29998 mach = bfd_mach_arm_5T;
29999 else
30000 mach = bfd_mach_arm_5;
30001 }
e74cfd16 30002 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4))
b99bd4ef 30003 {
e74cfd16 30004 if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v4t))
b99bd4ef
NC		 30005 mach = bfd_mach_arm_4T;
30006 else
30007 mach = bfd_mach_arm_4;
30008 }
e74cfd16 30009 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3m))
b99bd4ef 30010 mach = bfd_mach_arm_3M;
e74cfd16
PB		 30011 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v3))
30012 mach = bfd_mach_arm_3;
30013 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2s))
30014 mach = bfd_mach_arm_2a;
30015 else if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v2))
30016 mach = bfd_mach_arm_2;
30017 else
30018 mach = bfd_mach_arm_unknown;
b99bd4ef
NC		 30019
30020 bfd_set_arch_mach (stdoutput, TARGET_ARCH, mach);
30021}
30022
c19d1205 30023/* Command line processing. */
b99bd4ef 30024
c19d1205
ZW		 30025/* md_parse_option
30026 Invocation line includes a switch not recognized by the base assembler.
30027 See if it's a processor-specific option.
b99bd4ef 30028
c19d1205
ZW		 30029 This routine is somewhat complicated by the need for backwards
30030 compatibility (since older releases of gcc can't be changed).
30031 The new options try to make the interface as compatible as
30032 possible with GCC.
b99bd4ef 30033
c19d1205 30034 New options (supported) are:
b99bd4ef 30035
c19d1205
ZW		 30036 -mcpu=<cpu name> Assemble for selected processor
30037 -march=<architecture name> Assemble for selected architecture
30038 -mfpu=<fpu architecture> Assemble for selected FPU.
30039 -EB/-mbig-endian Big-endian
30040 -EL/-mlittle-endian Little-endian
30041 -k Generate PIC code
30042 -mthumb Start in Thumb mode
30043 -mthumb-interwork Code supports ARM/Thumb interworking
b99bd4ef 30044
278df34e 30045 -m[no-]warn-deprecated Warn about deprecated features
8b2d793c 30046 -m[no-]warn-syms Warn when symbols match instructions
267bf995 30047
c19d1205 30048 For now we will also provide support for:
b99bd4ef 30049
c19d1205
ZW		 30050 -mapcs-32 32-bit Program counter
30051 -mapcs-26 26-bit Program counter
30052 -macps-float Floats passed in FP registers
30053 -mapcs-reentrant Reentrant code
30054 -matpcs
30055 (sometime these will probably be replaced with -mapcs=<list of options>
30056 and -matpcs=<list of options>)
b99bd4ef 30057
c19d1205
ZW		 30058 The remaining options are only supported for back-wards compatibility.
30059 Cpu variants, the arm part is optional:
30060 -m[arm]1 Currently not supported.
30061 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30062 -m[arm]3 Arm 3 processor
30063 -m[arm]6[xx], Arm 6 processors
30064 -m[arm]7[xx][t][[d]m] Arm 7 processors
30065 -m[arm]8[10] Arm 8 processors
30066 -m[arm]9[20][tdmi] Arm 9 processors
30067 -mstrongarm[110[0]] StrongARM processors
30068 -mxscale XScale processors
30069 -m[arm]v[2345[t[e]]] Arm architectures
30070 -mall All (except the ARM1)
30071 FP variants:
30072 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30073 -mfpe-old (No float load/store multiples)
30074 -mvfpxd VFP Single precision
30075 -mvfp All VFP
30076 -mno-fpu Disable all floating point instructions
b99bd4ef 30077
c19d1205
ZW		 30078 The following CPU names are recognized:
30079 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30080 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30081 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30082 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30083 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30084 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30085 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
b99bd4ef 30086
c19d1205 30087 */
b99bd4ef 30088
c19d1205 30089const char * md_shortopts = "m:k";
b99bd4ef 30090
c19d1205
ZW		 30091#ifdef ARM_BI_ENDIAN
30092#define OPTION_EB (OPTION_MD_BASE + 0)
30093#define OPTION_EL (OPTION_MD_BASE + 1)
b99bd4ef 30094#else
c19d1205
ZW		 30095#if TARGET_BYTES_BIG_ENDIAN
30096#define OPTION_EB (OPTION_MD_BASE + 0)
b99bd4ef 30097#else
c19d1205
ZW		 30098#define OPTION_EL (OPTION_MD_BASE + 1)
30099#endif
b99bd4ef 30100#endif
845b51d6 30101#define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
18a20338 30102#define OPTION_FDPIC (OPTION_MD_BASE + 3)
b99bd4ef 30103
c19d1205 30104struct option md_longopts[] =
b99bd4ef 30105{
c19d1205
ZW		 30106#ifdef OPTION_EB
30107 {"EB", no_argument, NULL, OPTION_EB},
30108#endif
30109#ifdef OPTION_EL
30110 {"EL", no_argument, NULL, OPTION_EL},
b99bd4ef 30111#endif
845b51d6 30112 {"fix-v4bx", no_argument, NULL, OPTION_FIX_V4BX},
18a20338
CL		 30113#ifdef OBJ_ELF
30114 {"fdpic", no_argument, NULL, OPTION_FDPIC},
30115#endif
c19d1205
ZW		 30116 {NULL, no_argument, NULL, 0}
30117};
b99bd4ef 30118
c19d1205 30119size_t md_longopts_size = sizeof (md_longopts);
b99bd4ef 30120
c19d1205 30121struct arm_option_table
b99bd4ef 30122{
0198d5e6
TC		 30123 const char * option; /* Option name to match. */
30124 const char * help; /* Help information. */
30125 int * var; /* Variable to change. */
30126 int value; /* What to change it to. */
30127 const char * deprecated; /* If non-null, print this message. */
c19d1205 30128};
b99bd4ef 30129
c19d1205
ZW		 30130struct arm_option_table arm_opts[] =
30131{
30132 {"k", N_("generate PIC code"), &pic_code, 1, NULL},
30133 {"mthumb", N_("assemble Thumb code"), &thumb_mode, 1, NULL},
30134 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30135 &support_interwork, 1, NULL},
30136 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26, 0, NULL},
30137 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26, 1, NULL},
30138 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float,
30139 1, NULL},
30140 {"mapcs-reentrant", N_("re-entrant code"), &pic_code, 1, NULL},
30141 {"matpcs", N_("code is ATPCS conformant"), &atpcs, 1, NULL},
30142 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian, 1, NULL},
30143 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian, 0,
30144 NULL},
b99bd4ef 30145
c19d1205
ZW		 30146 /* These are recognized by the assembler, but have no affect on code. */
30147 {"mapcs-frame", N_("use frame pointer"), NULL, 0, NULL},
30148 {"mapcs-stack-check", N_("use stack size checking"), NULL, 0, NULL},
278df34e
NS		 30149
30150 {"mwarn-deprecated", NULL, &warn_on_deprecated, 1, NULL},
30151 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30152 &warn_on_deprecated, 0, NULL},
8b2d793c
NC		 30153 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms), TRUE, NULL},
30154 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms), FALSE, NULL},
e74cfd16
PB		 30155 {NULL, NULL, NULL, 0, NULL}
30156};
30157
30158struct arm_legacy_option_table
30159{
0198d5e6
TC		 30160 const char * option; /* Option name to match. */
30161 const arm_feature_set ** var; /* Variable to change. */
30162 const arm_feature_set value; /* What to change it to. */
30163 const char * deprecated; /* If non-null, print this message. */
e74cfd16 30164};
b99bd4ef 30165
e74cfd16
PB		 30166const struct arm_legacy_option_table arm_legacy_opts[] =
30167{
c19d1205
ZW		 30168 /* DON'T add any new processors to this list -- we want the whole list
30169 to go away... Add them to the processors table instead. */
e74cfd16
PB		 30170 {"marm1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
30171 {"m1", &legacy_cpu, ARM_ARCH_V1, N_("use -mcpu=arm1")},
30172 {"marm2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
30173 {"m2", &legacy_cpu, ARM_ARCH_V2, N_("use -mcpu=arm2")},
30174 {"marm250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
30175 {"m250", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm250")},
30176 {"marm3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
30177 {"m3", &legacy_cpu, ARM_ARCH_V2S, N_("use -mcpu=arm3")},
30178 {"marm6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
30179 {"m6", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm6")},
30180 {"marm600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
30181 {"m600", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm600")},
30182 {"marm610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
30183 {"m610", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm610")},
30184 {"marm620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
30185 {"m620", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm620")},
30186 {"marm7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
30187 {"m7", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7")},
30188 {"marm70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
30189 {"m70", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm70")},
30190 {"marm700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
30191 {"m700", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700")},
30192 {"marm700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
30193 {"m700i", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm700i")},
30194 {"marm710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
30195 {"m710", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710")},
30196 {"marm710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
30197 {"m710c", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm710c")},
30198 {"marm720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
30199 {"m720", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm720")},
30200 {"marm7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
30201 {"m7d", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7d")},
30202 {"marm7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
30203 {"m7di", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7di")},
30204 {"marm7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
30205 {"m7m", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7m")},
30206 {"marm7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
30207 {"m7dm", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dm")},
30208 {"marm7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
30209 {"m7dmi", &legacy_cpu, ARM_ARCH_V3M, N_("use -mcpu=arm7dmi")},
30210 {"marm7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
30211 {"m7100", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7100")},
30212 {"marm7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
30213 {"m7500", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500")},
30214 {"marm7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
30215 {"m7500fe", &legacy_cpu, ARM_ARCH_V3, N_("use -mcpu=arm7500fe")},
30216 {"marm7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30217 {"m7t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30218 {"marm7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30219 {"m7tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm7tdmi")},
30220 {"marm710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
30221 {"m710t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm710t")},
30222 {"marm720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
30223 {"m720t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm720t")},
30224 {"marm740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
30225 {"m740t", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm740t")},
30226 {"marm8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
30227 {"m8", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm8")},
30228 {"marm810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
30229 {"m810", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=arm810")},
30230 {"marm9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
30231 {"m9", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9")},
30232 {"marm9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
30233 {"m9tdmi", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm9tdmi")},
30234 {"marm920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
30235 {"m920", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm920")},
30236 {"marm940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
30237 {"m940", &legacy_cpu, ARM_ARCH_V4T, N_("use -mcpu=arm940")},
30238 {"mstrongarm", &legacy_cpu, ARM_ARCH_V4, N_("use -mcpu=strongarm")},
30239 {"mstrongarm110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30240 N_("use -mcpu=strongarm110")},
e74cfd16 30241 {"mstrongarm1100", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30242 N_("use -mcpu=strongarm1100")},
e74cfd16 30243 {"mstrongarm1110", &legacy_cpu, ARM_ARCH_V4,
c19d1205 30244 N_("use -mcpu=strongarm1110")},
e74cfd16
PB		 30245 {"mxscale", &legacy_cpu, ARM_ARCH_XSCALE, N_("use -mcpu=xscale")},
30246 {"miwmmxt", &legacy_cpu, ARM_ARCH_IWMMXT, N_("use -mcpu=iwmmxt")},
30247 {"mall", &legacy_cpu, ARM_ANY, N_("use -mcpu=all")},
7ed4c4c5 30248
c19d1205 30249 /* Architecture variants -- don't add any more to this list either. */
e74cfd16
PB		 30250 {"mv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
30251 {"marmv2", &legacy_cpu, ARM_ARCH_V2, N_("use -march=armv2")},
30252 {"mv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
30253 {"marmv2a", &legacy_cpu, ARM_ARCH_V2S, N_("use -march=armv2a")},
30254 {"mv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
30255 {"marmv3", &legacy_cpu, ARM_ARCH_V3, N_("use -march=armv3")},
30256 {"mv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
30257 {"marmv3m", &legacy_cpu, ARM_ARCH_V3M, N_("use -march=armv3m")},
30258 {"mv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
30259 {"marmv4", &legacy_cpu, ARM_ARCH_V4, N_("use -march=armv4")},
30260 {"mv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
30261 {"marmv4t", &legacy_cpu, ARM_ARCH_V4T, N_("use -march=armv4t")},
30262 {"mv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
30263 {"marmv5", &legacy_cpu, ARM_ARCH_V5, N_("use -march=armv5")},
30264 {"mv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
30265 {"marmv5t", &legacy_cpu, ARM_ARCH_V5T, N_("use -march=armv5t")},
30266 {"mv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
30267 {"marmv5e", &legacy_cpu, ARM_ARCH_V5TE, N_("use -march=armv5te")},
7ed4c4c5 30268
c19d1205 30269 /* Floating point variants -- don't add any more to this list either. */
0198d5e6
TC		 30270 {"mfpe-old", &legacy_fpu, FPU_ARCH_FPE, N_("use -mfpu=fpe")},
30271 {"mfpa10", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa10")},
30272 {"mfpa11", &legacy_fpu, FPU_ARCH_FPA, N_("use -mfpu=fpa11")},
30273 {"mno-fpu", &legacy_fpu, ARM_ARCH_NONE,
c19d1205 30274 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
7ed4c4c5 30275
e74cfd16 30276 {NULL, NULL, ARM_ARCH_NONE, NULL}
c19d1205 30277};
7ed4c4c5 30278
c19d1205 30279struct arm_cpu_option_table
7ed4c4c5 30280{
0198d5e6
TC		 30281 const char * name;
30282 size_t name_len;
30283 const arm_feature_set value;
30284 const arm_feature_set ext;
c19d1205
ZW		 30285 /* For some CPUs we assume an FPU unless the user explicitly sets
30286 -mfpu=... */
0198d5e6 30287 const arm_feature_set default_fpu;
ee065d83
PB		 30288 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30289 case. */
0198d5e6 30290 const char * canonical_name;
c19d1205 30291};
7ed4c4c5 30292
c19d1205
ZW		 30293/* This list should, at a minimum, contain all the cpu names
30294 recognized by GCC. */
996b5569 30295#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
0198d5e6 30296
e74cfd16 30297static const struct arm_cpu_option_table arm_cpus[] =
c19d1205 30298{
996b5569
TP		 30299 ARM_CPU_OPT ("all", NULL, ARM_ANY,
30300 ARM_ARCH_NONE,
30301 FPU_ARCH_FPA),
30302 ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
30303 ARM_ARCH_NONE,
30304 FPU_ARCH_FPA),
30305 ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
30306 ARM_ARCH_NONE,
30307 FPU_ARCH_FPA),
30308 ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
30309 ARM_ARCH_NONE,
30310 FPU_ARCH_FPA),
30311 ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
30312 ARM_ARCH_NONE,
30313 FPU_ARCH_FPA),
30314 ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
30315 ARM_ARCH_NONE,
30316 FPU_ARCH_FPA),
30317 ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
30318 ARM_ARCH_NONE,
30319 FPU_ARCH_FPA),
30320 ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
30321 ARM_ARCH_NONE,
30322 FPU_ARCH_FPA),
30323 ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
30324 ARM_ARCH_NONE,
30325 FPU_ARCH_FPA),
30326 ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
30327 ARM_ARCH_NONE,
30328 FPU_ARCH_FPA),
30329 ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
30330 ARM_ARCH_NONE,
30331 FPU_ARCH_FPA),
30332 ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
30333 ARM_ARCH_NONE,
30334 FPU_ARCH_FPA),
30335 ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
30336 ARM_ARCH_NONE,
30337 FPU_ARCH_FPA),
30338 ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
30339 ARM_ARCH_NONE,
30340 FPU_ARCH_FPA),
30341 ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
30342 ARM_ARCH_NONE,
30343 FPU_ARCH_FPA),
30344 ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
30345 ARM_ARCH_NONE,
30346 FPU_ARCH_FPA),
30347 ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
30348 ARM_ARCH_NONE,
30349 FPU_ARCH_FPA),
30350 ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
30351 ARM_ARCH_NONE,
30352 FPU_ARCH_FPA),
30353 ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
30354 ARM_ARCH_NONE,
30355 FPU_ARCH_FPA),
30356 ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
30357 ARM_ARCH_NONE,
30358 FPU_ARCH_FPA),
30359 ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
30360 ARM_ARCH_NONE,
30361 FPU_ARCH_FPA),
30362 ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
30363 ARM_ARCH_NONE,
30364 FPU_ARCH_FPA),
30365 ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
30366 ARM_ARCH_NONE,
30367 FPU_ARCH_FPA),
30368 ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
30369 ARM_ARCH_NONE,
30370 FPU_ARCH_FPA),
30371 ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
30372 ARM_ARCH_NONE,
30373 FPU_ARCH_FPA),
30374 ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
30375 ARM_ARCH_NONE,
30376 FPU_ARCH_FPA),
30377 ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
30378 ARM_ARCH_NONE,
30379 FPU_ARCH_FPA),
30380 ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
30381 ARM_ARCH_NONE,
30382 FPU_ARCH_FPA),
30383 ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
30384 ARM_ARCH_NONE,
30385 FPU_ARCH_FPA),
30386 ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
30387 ARM_ARCH_NONE,
30388 FPU_ARCH_FPA),
30389 ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
30390 ARM_ARCH_NONE,
30391 FPU_ARCH_FPA),
30392 ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
30393 ARM_ARCH_NONE,
30394 FPU_ARCH_FPA),
30395 ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
30396 ARM_ARCH_NONE,
30397 FPU_ARCH_FPA),
30398 ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
30399 ARM_ARCH_NONE,
30400 FPU_ARCH_FPA),
30401 ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
30402 ARM_ARCH_NONE,
30403 FPU_ARCH_FPA),
30404 ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
30405 ARM_ARCH_NONE,
30406 FPU_ARCH_FPA),
30407 ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
30408 ARM_ARCH_NONE,
30409 FPU_ARCH_FPA),
30410 ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
30411 ARM_ARCH_NONE,
30412 FPU_ARCH_FPA),
30413 ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
30414 ARM_ARCH_NONE,
30415 FPU_ARCH_FPA),
30416 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
30417 ARM_ARCH_NONE,
30418 FPU_ARCH_FPA),
30419 ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
30420 ARM_ARCH_NONE,
30421 FPU_ARCH_FPA),
30422 ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
30423 ARM_ARCH_NONE,
30424 FPU_ARCH_FPA),
30425 ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
30426 ARM_ARCH_NONE,
30427 FPU_ARCH_FPA),
30428 ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
30429 ARM_ARCH_NONE,
30430 FPU_ARCH_FPA),
30431 ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
30432 ARM_ARCH_NONE,
30433 FPU_ARCH_FPA),
30434 ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
30435 ARM_ARCH_NONE,
30436 FPU_ARCH_FPA),
30437
c19d1205
ZW		 30438 /* For V5 or later processors we default to using VFP; but the user
30439 should really set the FPU type explicitly. */
996b5569
TP		 30440 ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
30441 ARM_ARCH_NONE,
30442 FPU_ARCH_VFP_V2),
30443 ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
30444 ARM_ARCH_NONE,
30445 FPU_ARCH_VFP_V2),
30446 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30447 ARM_ARCH_NONE,
30448 FPU_ARCH_VFP_V2),
30449 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
30450 ARM_ARCH_NONE,
30451 FPU_ARCH_VFP_V2),
30452 ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
30453 ARM_ARCH_NONE,
30454 FPU_ARCH_VFP_V2),
30455 ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
30456 ARM_ARCH_NONE,
30457 FPU_ARCH_VFP_V2),
30458 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
30459 ARM_ARCH_NONE,
30460 FPU_ARCH_VFP_V2),
30461 ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
30462 ARM_ARCH_NONE,
30463 FPU_ARCH_VFP_V2),
30464 ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
30465 ARM_ARCH_NONE,
30466 FPU_ARCH_VFP_V2),
30467 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
30468 ARM_ARCH_NONE,
30469 FPU_ARCH_VFP_V2),
30470 ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
30471 ARM_ARCH_NONE,
30472 FPU_ARCH_VFP_V2),
30473 ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
30474 ARM_ARCH_NONE,
30475 FPU_ARCH_VFP_V2),
30476 ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
30477 ARM_ARCH_NONE,
30478 FPU_ARCH_VFP_V1),
30479 ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
30480 ARM_ARCH_NONE,
30481 FPU_ARCH_VFP_V1),
30482 ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
30483 ARM_ARCH_NONE,
30484 FPU_ARCH_VFP_V2),
30485 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
30486 ARM_ARCH_NONE,
30487 FPU_ARCH_VFP_V2),
30488 ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
30489 ARM_ARCH_NONE,
30490 FPU_ARCH_VFP_V1),
30491 ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
30492 ARM_ARCH_NONE,
30493 FPU_ARCH_VFP_V2),
30494 ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
30495 ARM_ARCH_NONE,
30496 FPU_ARCH_VFP_V2),
30497 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
30498 ARM_ARCH_NONE,
30499 FPU_ARCH_VFP_V2),
30500 ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
30501 ARM_ARCH_NONE,
30502 FPU_ARCH_VFP_V2),
30503 ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
30504 ARM_ARCH_NONE,
30505 FPU_ARCH_VFP_V2),
30506 ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
30507 ARM_ARCH_NONE,
30508 FPU_ARCH_VFP_V2),
30509 ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
30510 ARM_ARCH_NONE,
30511 FPU_ARCH_VFP_V2),
30512 ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
30513 ARM_ARCH_NONE,
30514 FPU_ARCH_VFP_V2),
30515 ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
30516 ARM_ARCH_NONE,
30517 FPU_ARCH_VFP_V2),
30518 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
30519 ARM_ARCH_NONE,
30520 FPU_NONE),
30521 ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
30522 ARM_ARCH_NONE,
30523 FPU_NONE),
30524 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
30525 ARM_ARCH_NONE,
30526 FPU_ARCH_VFP_V2),
30527 ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
30528 ARM_ARCH_NONE,
30529 FPU_ARCH_VFP_V2),
30530 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
30531 ARM_ARCH_NONE,
30532 FPU_ARCH_VFP_V2),
30533 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
30534 ARM_ARCH_NONE,
30535 FPU_NONE),
30536 ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
30537 ARM_ARCH_NONE,
30538 FPU_NONE),
30539 ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
30540 ARM_ARCH_NONE,
30541 FPU_ARCH_VFP_V2),
30542 ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
30543 ARM_ARCH_NONE,
30544 FPU_NONE),
30545 ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
30546 ARM_ARCH_NONE,
30547 FPU_ARCH_VFP_V2),
30548 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
30549 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30550 FPU_NONE),
30551 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
30552 ARM_ARCH_NONE,
30553 FPU_ARCH_NEON_VFP_V4),
30554 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
30555 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
30556 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30557 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
30558 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30559 ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
30560 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
30561 ARM_ARCH_NONE,
30562 FPU_ARCH_NEON_VFP_V4),
30563 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
30564 ARM_ARCH_NONE,
30565 FPU_ARCH_NEON_VFP_V4),
30566 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
30567 ARM_ARCH_NONE,
30568 FPU_ARCH_NEON_VFP_V4),
30569 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
30570 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30571 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30572 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
30573 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30574 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30575 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
30576 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30577 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG		 30578 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
30579 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 30580 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP		 30581 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
30582 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30583 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30584 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
30585 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30586 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30587 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
30588 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30589 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
15a7695f
JG		 30590 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
30591 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
0198d5e6 30592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
7ebd1359 30593 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A,
30594 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30595 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
0535e5d7
DZ		 30596 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A,
30597 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30598 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
30599 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A,
30600 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30601 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
ef8df4ca
KT		 30602 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A,
30603 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30604 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
996b5569
TP		 30605 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
30606 ARM_ARCH_NONE,
30607 FPU_NONE),
30608 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
30609 ARM_ARCH_NONE,
30610 FPU_ARCH_VFP_V3D16),
30611 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
30612 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30613 FPU_NONE),
30614 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
30615 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30616 FPU_ARCH_VFP_V3D16),
30617 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
30618 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
30619 FPU_ARCH_VFP_V3D16),
0cda1e19
TP		 30620 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
30621 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30622 FPU_ARCH_NEON_VFP_ARMV8),
0535e5d7
DZ		 30623 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN,
30624 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30625 FPU_NONE),
996b5569
TP		 30626 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
30627 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30628 FPU_NONE),
30629 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
30630 ARM_ARCH_NONE,
30631 FPU_NONE),
30632 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
30633 ARM_ARCH_NONE,
30634 FPU_NONE),
30635 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
30636 ARM_ARCH_NONE,
30637 FPU_NONE),
30638 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
30639 ARM_ARCH_NONE,
30640 FPU_NONE),
30641 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
30642 ARM_ARCH_NONE,
30643 FPU_NONE),
30644 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
30645 ARM_ARCH_NONE,
30646 FPU_NONE),
30647 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
30648 ARM_ARCH_NONE,
30649 FPU_NONE),
30650 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
30651 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30652 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
83f43c83
KT		 30653 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A,
30654 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
30655 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD),
c19d1205 30656 /* ??? XSCALE is really an architecture. */
996b5569
TP		 30657 ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
30658 ARM_ARCH_NONE,
30659 FPU_ARCH_VFP_V2),
30660
c19d1205 30661 /* ??? iwmmxt is not a processor. */
996b5569
TP		 30662 ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
30663 ARM_ARCH_NONE,
30664 FPU_ARCH_VFP_V2),
30665 ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
30666 ARM_ARCH_NONE,
30667 FPU_ARCH_VFP_V2),
30668 ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
30669 ARM_ARCH_NONE,
30670 FPU_ARCH_VFP_V2),
30671
0198d5e6 30672 /* Maverick. */
996b5569
TP		 30673 ARM_CPU_OPT ("ep9312", "ARM920T",
30674 ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
30675 ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
30676
da4339ed 30677 /* Marvell processors. */
996b5569
TP		 30678 ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
30679 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30680 FPU_ARCH_VFP_V3D16),
30681 ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
30682 ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
30683 FPU_ARCH_NEON_VFP_V4),
da4339ed 30684
996b5569
TP		 30685 /* APM X-Gene family. */
30686 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
30687 ARM_ARCH_NONE,
30688 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30689 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
30690 ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
30691 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
30692
30693 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 30694};
f3bad469 30695#undef ARM_CPU_OPT
7ed4c4c5 30696
34ef62f4
AV		 30697struct arm_ext_table
30698{
30699 const char * name;
30700 size_t name_len;
30701 const arm_feature_set merge;
30702 const arm_feature_set clear;
30703};
30704
c19d1205 30705struct arm_arch_option_table
7ed4c4c5 30706{
34ef62f4
AV		 30707 const char * name;
30708 size_t name_len;
30709 const arm_feature_set value;
30710 const arm_feature_set default_fpu;
30711 const struct arm_ext_table * ext_table;
30712};
30713
30714/* Used to add support for +E and +noE extension. */
30715#define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30716/* Used to add support for a +E extension. */
30717#define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30718/* Used to add support for a +noE extension. */
30719#define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30720
30721#define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30722 ~0 & ~FPU_ENDIAN_PURE)
30723
30724static const struct arm_ext_table armv5te_ext_table[] =
30725{
30726 ARM_EXT ("fp", FPU_ARCH_VFP_V2, ALL_FP),
30727 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30728};
30729
30730static const struct arm_ext_table armv7_ext_table[] =
30731{
30732 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30733 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30734};
30735
30736static const struct arm_ext_table armv7ve_ext_table[] =
30737{
30738 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16, ALL_FP),
30739 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16),
30740 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30741 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30742 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30743 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16), /* Alias for +fp. */
30744 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30745
30746 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4,
30747 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30748
30749 /* Aliases for +simd. */
30750 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30751
30752 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30753 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30754 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30755
30756 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30757};
30758
30759static const struct arm_ext_table armv7a_ext_table[] =
30760{
30761 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30762 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30763 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3),
30764 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30765 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16),
30766 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16),
30767 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4),
30768
30769 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1,
30770 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)),
30771
30772 /* Aliases for +simd. */
30773 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30774 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1),
30775
30776 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16),
30777 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4),
30778
30779 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP)),
30780 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC)),
30781 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30782};
30783
30784static const struct arm_ext_table armv7r_ext_table[] =
30785{
30786 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD),
30787 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD), /* Alias for +fp.sp. */
30788 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16, ALL_FP),
30789 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16), /* Alias for +fp. */
30790 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16),
30791 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16),
30792 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
30793 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV)),
30794 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30795};
30796
30797static const struct arm_ext_table armv7em_ext_table[] =
30798{
30799 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16, ALL_FP),
30800 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30801 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16),
30802 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16),
30803 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30804 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16),
30805 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30806};
30807
30808static const struct arm_ext_table armv8a_ext_table[] =
30809{
30810 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30811 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30812 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30813 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30814
30815 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30816 should use the +simd option to turn on FP. */
30817 ARM_REMOVE ("fp", ALL_FP),
30818 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30819 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30820 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30821};
30822
30823
30824static const struct arm_ext_table armv81a_ext_table[] =
30825{
30826 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30827 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30828 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30829
30830 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30831 should use the +simd option to turn on FP. */
30832 ARM_REMOVE ("fp", ALL_FP),
30833 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30834 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30835 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30836};
30837
30838static const struct arm_ext_table armv82a_ext_table[] =
30839{
30840 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1),
30841 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16),
30842 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML),
30843 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1,
30844 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30845 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30846
30847 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30848 should use the +simd option to turn on FP. */
30849 ARM_REMOVE ("fp", ALL_FP),
30850 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30851 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30852 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30853};
30854
30855static const struct arm_ext_table armv84a_ext_table[] =
30856{
30857 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30858 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30859 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30860 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30861
30862 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30863 should use the +simd option to turn on FP. */
30864 ARM_REMOVE ("fp", ALL_FP),
30865 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB)),
30866 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES)),
30867 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30868};
30869
30870static const struct arm_ext_table armv85a_ext_table[] =
30871{
30872 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8),
30873 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML),
30874 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4,
30875 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30876
30877 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30878 should use the +simd option to turn on FP. */
30879 ARM_REMOVE ("fp", ALL_FP),
30880 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30881};
30882
30883static const struct arm_ext_table armv8m_main_ext_table[] =
30884{
30885 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30886 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30887 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16, ALL_FP),
30888 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16),
30889 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30890};
30891
e0991585
AV		 30892static const struct arm_ext_table armv8_1m_main_ext_table[] =
30893{
30894 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
30895 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
30896 ARM_EXT ("fp",
30897 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30898 FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
30899 ALL_FP),
30900 ARM_ADD ("fp.dp",
30901 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30902 FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
a7ad558c
AV		 30903 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE),
30904 ARM_FEATURE_COPROC (FPU_MVE | FPU_MVE_FP)),
30905 ARM_ADD ("mve.fp",
30906 ARM_FEATURE (0, ARM_EXT2_FP16_INST,
30907 FPU_MVE | FPU_MVE_FP | FPU_VFP_V5_SP_D16 |
30908 FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
e0991585
AV		 30909 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
30910};
30911
34ef62f4
AV		 30912static const struct arm_ext_table armv8r_ext_table[] =
30913{
30914 ARM_ADD ("crc", ARCH_CRC_ARMV8),
30915 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8),
30916 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
30917 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8)),
30918 ARM_REMOVE ("fp", ALL_FP),
30919 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16),
30920 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
c19d1205 30921};
7ed4c4c5 30922
c19d1205
ZW		 30923/* This list should, at a minimum, contain all the architecture names
30924 recognized by GCC. */
34ef62f4
AV		 30925#define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30926#define ARM_ARCH_OPT2(N, V, DF, ext) \
30927 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
0198d5e6 30928
e74cfd16 30929static const struct arm_arch_option_table arm_archs[] =
c19d1205 30930{
497d849d
TP		 30931 ARM_ARCH_OPT ("all", ARM_ANY, FPU_ARCH_FPA),
30932 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1, FPU_ARCH_FPA),
30933 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2, FPU_ARCH_FPA),
30934 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S, FPU_ARCH_FPA),
30935 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S, FPU_ARCH_FPA),
30936 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3, FPU_ARCH_FPA),
30937 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M, FPU_ARCH_FPA),
30938 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4, FPU_ARCH_FPA),
30939 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM, FPU_ARCH_FPA),
30940 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T, FPU_ARCH_FPA),
30941 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM, FPU_ARCH_FPA),
30942 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5, FPU_ARCH_VFP),
30943 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T, FPU_ARCH_VFP),
30944 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM, FPU_ARCH_VFP),
34ef62f4
AV		 30945 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE, FPU_ARCH_VFP, armv5te),
30946 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP, FPU_ARCH_VFP, armv5te),
30947 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP, armv5te),
30948 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30949 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6, FPU_ARCH_VFP, armv5te),
30950 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K, FPU_ARCH_VFP, armv5te),
30951 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z, FPU_ARCH_VFP, armv5te),
f33026a9
MW		 30952 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30953 kept to preserve existing behaviour. */
34ef62f4
AV		 30954 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
30955 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ, FPU_ARCH_VFP, armv5te),
30956 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2, FPU_ARCH_VFP, armv5te),
30957 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP, armv5te),
30958 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP, armv5te),
f33026a9
MW		 30959 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30960 kept to preserve existing behaviour. */
34ef62f4
AV		 30961 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
30962 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2, FPU_ARCH_VFP, armv5te),
497d849d
TP		 30963 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP),
30964 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM, FPU_ARCH_VFP),
34ef62f4 30965 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7, FPU_ARCH_VFP, armv7),
c450d570
PB		 30966 /* The official spelling of the ARMv7 profile variants is the dashed form.
30967 Accept the non-dashed form for compatibility with old toolchains. */
34ef62f4
AV		 30968 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
30969 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE, FPU_ARCH_VFP, armv7ve),
30970 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 30971 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4
AV		 30972 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A, FPU_ARCH_VFP, armv7a),
30973 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP, armv7r),
497d849d 30974 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP),
34ef62f4 30975 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP, armv7em),
497d849d 30976 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
34ef62f4
AV		 30977 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
30978 armv8m_main),
e0991585
AV		 30979 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
30980 armv8_1m_main),
34ef62f4
AV		 30981 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
30982 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
30983 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
30984 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP, armv82a),
30985 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP, armv8r),
30986 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A, FPU_ARCH_VFP, armv84a),
30987 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A, FPU_ARCH_VFP, armv85a),
497d849d
TP		 30988 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
30989 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
30990 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2, FPU_ARCH_VFP),
34ef62f4 30991 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
c19d1205 30992};
f3bad469 30993#undef ARM_ARCH_OPT
7ed4c4c5 30994
69133863 30995/* ISA extensions in the co-processor and main instruction set space. */
0198d5e6 30996
69133863 30997struct arm_option_extension_value_table
c19d1205 30998{
0198d5e6
TC		 30999 const char * name;
31000 size_t name_len;
31001 const arm_feature_set merge_value;
31002 const arm_feature_set clear_value;
d942732e
TP		 31003 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31004 indicates that an extension is available for all architectures while
31005 ARM_ANY marks an empty entry. */
0198d5e6 31006 const arm_feature_set allowed_archs[2];
c19d1205 31007};
7ed4c4c5 31008
0198d5e6
TC		 31009/* The following table must be in alphabetical order with a NULL last entry. */
31010
d942732e
TP		 31011#define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31012#define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
0198d5e6 31013
34ef62f4
AV		 31014/* DEPRECATED: Refrain from using this table to add any new extensions, instead
31015 use the context sensitive approach using arm_ext_table's. */
69133863 31016static const struct arm_option_extension_value_table arm_extensions[] =
c19d1205 31017{
823d2571
TG		 31018 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8, ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
31019 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
bca38921 31020 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
823d2571
TG		 31021 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
31022 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
c604a79a
JW		 31023 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
31024 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
31025 ARM_ARCH_V8_2A),
15afaa63
TP		 31026 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31027 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
31028 ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
823d2571
TG		 31029 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8, ARM_FEATURE_COPROC (FPU_VFP_ARMV8),
31030 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
b8ec4e87
JW		 31031 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31032 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
31033 ARM_ARCH_V8_2A),
01f48020
TC		 31034 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31035 | ARM_EXT2_FP16_FML),
31036 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
31037 | ARM_EXT2_FP16_FML),
31038 ARM_ARCH_V8_2A),
d942732e 31039 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
823d2571 31040 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
d942732e
TP		 31041 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
31042 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
3d030cdb
TP		 31043 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
31044 Thumb divide instruction. Due to this having the same name as the
31045 previous entry, this will be ignored when doing command-line parsing and
31046 only considered by build attribute selection code. */
31047 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
31048 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
31049 ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
823d2571 31050 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
d942732e 31051 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
823d2571 31052 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
d942732e 31053 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2), ARM_ARCH_NONE),
823d2571 31054 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
d942732e
TP		 31055 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK), ARM_ARCH_NONE),
31056 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
823d2571 31057 ARM_FEATURE_CORE_LOW (ARM_EXT_MP),
d942732e
TP		 31058 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
31059 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
823d2571
TG		 31060 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
31061 ARM_FEATURE_CORE_LOW (ARM_EXT_OS),
31062 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
ddfded2f
MW		 31063 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
31064 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
ced40572 31065 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
dad0c3bf
SD		 31066 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
31067 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES),
31068 ARM_ARCH_V8A),
4d1464f2
MW		 31069 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
31070 ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
ced40572 31071 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
643afb90
MW		 31072 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
31073 ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
ced40572 31074 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
7fadb25d
SD		 31075 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
31076 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB),
31077 ARM_ARCH_V8A),
d942732e 31078 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
823d2571 31079 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
d942732e
TP		 31080 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
31081 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
643afb90
MW		 31082 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8,
31083 ARM_FEATURE_COPROC (FPU_NEON_ARMV8),
31084 ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
823d2571
TG		 31085 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT | ARM_EXT_ADIV
31086 | ARM_EXT_DIV),
31087 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT),
31088 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A)),
31089 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE),
d942732e
TP		 31090 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE), ARM_ARCH_NONE),
31091 { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, { ARM_ARCH_NONE, ARM_ARCH_NONE } }
69133863 31092};
f3bad469 31093#undef ARM_EXT_OPT
69133863
MGD		 31094
31095/* ISA floating-point and Advanced SIMD extensions. */
31096struct arm_option_fpu_value_table
31097{
0198d5e6
TC		 31098 const char * name;
31099 const arm_feature_set value;
c19d1205 31100};
7ed4c4c5 31101
c19d1205
ZW		 31102/* This list should, at a minimum, contain all the fpu names
31103 recognized by GCC. */
69133863 31104static const struct arm_option_fpu_value_table arm_fpus[] =
c19d1205
ZW		 31105{
31106 {"softfpa", FPU_NONE},
31107 {"fpe", FPU_ARCH_FPE},
31108 {"fpe2", FPU_ARCH_FPE},
31109 {"fpe3", FPU_ARCH_FPA}, /* Third release supports LFM/SFM. */
31110 {"fpa", FPU_ARCH_FPA},
31111 {"fpa10", FPU_ARCH_FPA},
31112 {"fpa11", FPU_ARCH_FPA},
31113 {"arm7500fe", FPU_ARCH_FPA},
31114 {"softvfp", FPU_ARCH_VFP},
31115 {"softvfp+vfp", FPU_ARCH_VFP_V2},
31116 {"vfp", FPU_ARCH_VFP_V2},
31117 {"vfp9", FPU_ARCH_VFP_V2},
d5e0ba9c 31118 {"vfp3", FPU_ARCH_VFP_V3}, /* Undocumented, use vfpv3. */
c19d1205
ZW		 31119 {"vfp10", FPU_ARCH_VFP_V2},
31120 {"vfp10-r0", FPU_ARCH_VFP_V1},
31121 {"vfpxd", FPU_ARCH_VFP_V1xD},
b1cc4aeb
PB		 31122 {"vfpv2", FPU_ARCH_VFP_V2},
31123 {"vfpv3", FPU_ARCH_VFP_V3},
62f3b8c8 31124 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16},
b1cc4aeb 31125 {"vfpv3-d16", FPU_ARCH_VFP_V3D16},
62f3b8c8
PB		 31126 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16},
31127 {"vfpv3xd", FPU_ARCH_VFP_V3xD},
31128 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16},
c19d1205
ZW		 31129 {"arm1020t", FPU_ARCH_VFP_V1},
31130 {"arm1020e", FPU_ARCH_VFP_V2},
d5e0ba9c 31131 {"arm1136jfs", FPU_ARCH_VFP_V2}, /* Undocumented, use arm1136jf-s. */
c19d1205
ZW		 31132 {"arm1136jf-s", FPU_ARCH_VFP_V2},
31133 {"maverick", FPU_ARCH_MAVERICK},
d5e0ba9c 31134 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
d3375ddd 31135 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
8e79c3df 31136 {"neon-fp16", FPU_ARCH_NEON_FP16},
62f3b8c8
PB		 31137 {"vfpv4", FPU_ARCH_VFP_V4},
31138 {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
ada65aa3 31139 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16},
a715796b
TG		 31140 {"fpv5-d16", FPU_ARCH_VFP_V5D16},
31141 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16},
62f3b8c8 31142 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4},
bca38921
MGD		 31143 {"fp-armv8", FPU_ARCH_VFP_ARMV8},
31144 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8},
31145 {"crypto-neon-fp-armv8",
31146 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8},
d6b4b13e 31147 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1},
081e4c7d
MW		 31148 {"crypto-neon-fp-armv8.1",
31149 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1},
e74cfd16
PB		 31150 {NULL, ARM_ARCH_NONE}
31151};
31152
31153struct arm_option_value_table
31154{
e0471c16 31155 const char *name;
e74cfd16 31156 long value;
c19d1205 31157};
7ed4c4c5 31158
e74cfd16 31159static const struct arm_option_value_table arm_float_abis[] =
c19d1205
ZW		 31160{
31161 {"hard", ARM_FLOAT_ABI_HARD},
31162 {"softfp", ARM_FLOAT_ABI_SOFTFP},
31163 {"soft", ARM_FLOAT_ABI_SOFT},
e74cfd16 31164 {NULL, 0}
c19d1205 31165};
7ed4c4c5 31166
c19d1205 31167#ifdef OBJ_ELF
3a4a14e9 31168/* We only know how to output GNU and ver 4/5 (AAELF) formats. */
e74cfd16 31169static const struct arm_option_value_table arm_eabis[] =
c19d1205
ZW		 31170{
31171 {"gnu", EF_ARM_EABI_UNKNOWN},
31172 {"4", EF_ARM_EABI_VER4},
3a4a14e9 31173 {"5", EF_ARM_EABI_VER5},
e74cfd16 31174 {NULL, 0}
c19d1205
ZW		 31175};
31176#endif
7ed4c4c5 31177
c19d1205
ZW		 31178struct arm_long_option_table
31179{
0198d5e6 31180 const char * option; /* Substring to match. */
e0471c16 31181 const char * help; /* Help information. */
17b9d67d 31182 int (* func) (const char * subopt); /* Function to decode sub-option. */
e0471c16 31183 const char * deprecated; /* If non-null, print this message. */
c19d1205 31184};
7ed4c4c5 31185
c921be7d 31186static bfd_boolean
c168ce07 31187arm_parse_extension (const char *str, const arm_feature_set *opt_set,
34ef62f4
AV		 31188 arm_feature_set *ext_set,
31189 const struct arm_ext_table *ext_table)
7ed4c4c5 31190{
69133863 31191 /* We insist on extensions being specified in alphabetical order, and with
fa94de6b
RM		 31192 extensions being added before being removed. We achieve this by having
31193 the global ARM_EXTENSIONS table in alphabetical order, and using the
69133863 31194 ADDING_VALUE variable to indicate whether we are adding an extension (1)
fa94de6b 31195 or removing it (0) and only allowing it to change in the order
69133863
MGD		 31196 -1 -> 1 -> 0. */
31197 const struct arm_option_extension_value_table * opt = NULL;
d942732e 31198 const arm_feature_set arm_any = ARM_ANY;
69133863
MGD		 31199 int adding_value = -1;
31200
c19d1205 31201 while (str != NULL && *str != 0)
7ed4c4c5 31202 {
82b8a785 31203 const char *ext;
f3bad469 31204 size_t len;
7ed4c4c5 31205
c19d1205
ZW		 31206 if (*str != '+')
31207 {
31208 as_bad (_("invalid architectural extension"));
c921be7d 31209 return FALSE;
c19d1205 31210 }
7ed4c4c5 31211
c19d1205
ZW		 31212 str++;
31213 ext = strchr (str, '+');
7ed4c4c5 31214
c19d1205 31215 if (ext != NULL)
f3bad469 31216 len = ext - str;
c19d1205 31217 else
f3bad469 31218 len = strlen (str);
7ed4c4c5 31219
f3bad469 31220 if (len >= 2 && strncmp (str, "no", 2) == 0)
69133863
MGD		 31221 {
31222 if (adding_value != 0)
31223 {
31224 adding_value = 0;
31225 opt = arm_extensions;
31226 }
31227
f3bad469 31228 len -= 2;
69133863
MGD		 31229 str += 2;
31230 }
f3bad469 31231 else if (len > 0)
69133863
MGD		 31232 {
31233 if (adding_value == -1)
31234 {
31235 adding_value = 1;
31236 opt = arm_extensions;
31237 }
31238 else if (adding_value != 1)
31239 {
31240 as_bad (_("must specify extensions to add before specifying "
31241 "those to remove"));
31242 return FALSE;
31243 }
31244 }
31245
f3bad469 31246 if (len == 0)
c19d1205
ZW		 31247 {
31248 as_bad (_("missing architectural extension"));
c921be7d 31249 return FALSE;
c19d1205 31250 }
7ed4c4c5 31251
69133863
MGD		 31252 gas_assert (adding_value != -1);
31253 gas_assert (opt != NULL);
31254
34ef62f4
AV		 31255 if (ext_table != NULL)
31256 {
31257 const struct arm_ext_table * ext_opt = ext_table;
31258 bfd_boolean found = FALSE;
31259 for (; ext_opt->name != NULL; ext_opt++)
31260 if (ext_opt->name_len == len
31261 && strncmp (ext_opt->name, str, len) == 0)
31262 {
31263 if (adding_value)
31264 {
31265 if (ARM_FEATURE_ZERO (ext_opt->merge))
31266 /* TODO: Option not supported. When we remove the
31267 legacy table this case should error out. */
31268 continue;
31269
31270 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, ext_opt->merge);
31271 }
31272 else
31273 {
31274 if (ARM_FEATURE_ZERO (ext_opt->clear))
31275 /* TODO: Option not supported. When we remove the
31276 legacy table this case should error out. */
31277 continue;
31278 ARM_CLEAR_FEATURE (*ext_set, *ext_set, ext_opt->clear);
31279 }
31280 found = TRUE;
31281 break;
31282 }
31283 if (found)
31284 {
31285 str = ext;
31286 continue;
31287 }
31288 }
31289
69133863
MGD		 31290 /* Scan over the options table trying to find an exact match. */
31291 for (; opt->name != NULL; opt++)
f3bad469 31292 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31293 {
d942732e
TP		 31294 int i, nb_allowed_archs =
31295 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
69133863 31296 /* Check we can apply the extension to this architecture. */
d942732e
TP		 31297 for (i = 0; i < nb_allowed_archs; i++)
31298 {
31299 /* Empty entry. */
31300 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
31301 continue;
c168ce07 31302 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
d942732e
TP		 31303 break;
31304 }
31305 if (i == nb_allowed_archs)
69133863
MGD		 31306 {
31307 as_bad (_("extension does not apply to the base architecture"));
31308 return FALSE;
31309 }
31310
31311 /* Add or remove the extension. */
31312 if (adding_value)
4d354d8b 31313 ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
69133863 31314 else
4d354d8b 31315 ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
69133863 31316
3d030cdb
TP		 31317 /* Allowing Thumb division instructions for ARMv7 in autodetection
31318 rely on this break so that duplicate extensions (extensions
31319 with the same name as a previous extension in the list) are not
31320 considered for command-line parsing. */
c19d1205
ZW		 31321 break;
31322 }
7ed4c4c5 31323
c19d1205
ZW		 31324 if (opt->name == NULL)
31325 {
69133863
MGD		 31326 /* Did we fail to find an extension because it wasn't specified in
31327 alphabetical order, or because it does not exist? */
31328
31329 for (opt = arm_extensions; opt->name != NULL; opt++)
f3bad469 31330 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
69133863
MGD		 31331 break;
31332
31333 if (opt->name == NULL)
31334 as_bad (_("unknown architectural extension `%s'"), str);
31335 else
31336 as_bad (_("architectural extensions must be specified in "
31337 "alphabetical order"));
31338
c921be7d 31339 return FALSE;
c19d1205 31340 }
69133863
MGD		 31341 else
31342 {
31343 /* We should skip the extension we've just matched the next time
31344 round. */
31345 opt++;
31346 }
7ed4c4c5 31347
c19d1205
ZW		 31348 str = ext;
31349 };
7ed4c4c5 31350
c921be7d 31351 return TRUE;
c19d1205 31352}
7ed4c4c5 31353
5312fe52
BW		 31354static bfd_boolean
31355arm_parse_fp16_opt (const char *str)
31356{
31357 if (strcasecmp (str, "ieee") == 0)
31358 fp16_format = ARM_FP16_FORMAT_IEEE;
31359 else if (strcasecmp (str, "alternative") == 0)
31360 fp16_format = ARM_FP16_FORMAT_ALTERNATIVE;
31361 else
31362 {
31363 as_bad (_("unrecognised float16 format \"%s\""), str);
31364 return FALSE;
31365 }
31366
31367 return TRUE;
31368}
31369
c921be7d 31370static bfd_boolean
17b9d67d 31371arm_parse_cpu (const char *str)
7ed4c4c5 31372{
f3bad469 31373 const struct arm_cpu_option_table *opt;
82b8a785 31374 const char *ext = strchr (str, '+');
f3bad469 31375 size_t len;
7ed4c4c5 31376
c19d1205 31377 if (ext != NULL)
f3bad469 31378 len = ext - str;
7ed4c4c5 31379 else
f3bad469 31380 len = strlen (str);
7ed4c4c5 31381
f3bad469 31382 if (len == 0)
7ed4c4c5 31383 {
c19d1205 31384 as_bad (_("missing cpu name `%s'"), str);
c921be7d 31385 return FALSE;
7ed4c4c5
NC		 31386 }
31387
c19d1205 31388 for (opt = arm_cpus; opt->name != NULL; opt++)
f3bad469 31389 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31390 {
c168ce07 31391 mcpu_cpu_opt = &opt->value;
4d354d8b
TP		 31392 if (mcpu_ext_opt == NULL)
31393 mcpu_ext_opt = XNEW (arm_feature_set);
31394 *mcpu_ext_opt = opt->ext;
e74cfd16 31395 mcpu_fpu_opt = &opt->default_fpu;
ee065d83 31396 if (opt->canonical_name)
ef8e6722
JW		 31397 {
31398 gas_assert (sizeof selected_cpu_name > strlen (opt->canonical_name));
31399 strcpy (selected_cpu_name, opt->canonical_name);
31400 }
ee065d83
PB		 31401 else
31402 {
f3bad469 31403 size_t i;
c921be7d 31404
ef8e6722
JW		 31405 if (len >= sizeof selected_cpu_name)
31406 len = (sizeof selected_cpu_name) - 1;
31407
f3bad469 31408 for (i = 0; i < len; i++)
ee065d83
PB		 31409 selected_cpu_name[i] = TOUPPER (opt->name[i]);
31410 selected_cpu_name[i] = 0;
31411 }
7ed4c4c5 31412
c19d1205 31413 if (ext != NULL)
34ef62f4 31414 return arm_parse_extension (ext, mcpu_cpu_opt, mcpu_ext_opt, NULL);
7ed4c4c5 31415
c921be7d 31416 return TRUE;
c19d1205 31417 }
7ed4c4c5 31418
c19d1205 31419 as_bad (_("unknown cpu `%s'"), str);
c921be7d 31420 return FALSE;
7ed4c4c5
NC		 31421}
31422
c921be7d 31423static bfd_boolean
17b9d67d 31424arm_parse_arch (const char *str)
7ed4c4c5 31425{
e74cfd16 31426 const struct arm_arch_option_table *opt;
82b8a785 31427 const char *ext = strchr (str, '+');
f3bad469 31428 size_t len;
7ed4c4c5 31429
c19d1205 31430 if (ext != NULL)
f3bad469 31431 len = ext - str;
7ed4c4c5 31432 else
f3bad469 31433 len = strlen (str);
7ed4c4c5 31434
f3bad469 31435 if (len == 0)
7ed4c4c5 31436 {
c19d1205 31437 as_bad (_("missing architecture name `%s'"), str);
c921be7d 31438 return FALSE;
7ed4c4c5
NC		 31439 }
31440
c19d1205 31441 for (opt = arm_archs; opt->name != NULL; opt++)
f3bad469 31442 if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
c19d1205 31443 {
e74cfd16 31444 march_cpu_opt = &opt->value;
4d354d8b
TP		 31445 if (march_ext_opt == NULL)
31446 march_ext_opt = XNEW (arm_feature_set);
31447 *march_ext_opt = arm_arch_none;
e74cfd16 31448 march_fpu_opt = &opt->default_fpu;
5f4273c7 31449 strcpy (selected_cpu_name, opt->name);
7ed4c4c5 31450
c19d1205 31451 if (ext != NULL)
34ef62f4
AV		 31452 return arm_parse_extension (ext, march_cpu_opt, march_ext_opt,
31453 opt->ext_table);
7ed4c4c5 31454
c921be7d 31455 return TRUE;
c19d1205
ZW		 31456 }
31457
31458 as_bad (_("unknown architecture `%s'\n"), str);
c921be7d 31459 return FALSE;
7ed4c4c5 31460}
eb043451 31461
c921be7d 31462static bfd_boolean
17b9d67d 31463arm_parse_fpu (const char * str)
c19d1205 31464{
69133863 31465 const struct arm_option_fpu_value_table * opt;
b99bd4ef 31466
c19d1205
ZW		 31467 for (opt = arm_fpus; opt->name != NULL; opt++)
31468 if (streq (opt->name, str))
31469 {
e74cfd16 31470 mfpu_opt = &opt->value;
c921be7d 31471 return TRUE;
c19d1205 31472 }
b99bd4ef 31473
c19d1205 31474 as_bad (_("unknown floating point format `%s'\n"), str);
c921be7d 31475 return FALSE;
c19d1205
ZW		 31476}
31477
c921be7d 31478static bfd_boolean
17b9d67d 31479arm_parse_float_abi (const char * str)
b99bd4ef 31480{
e74cfd16 31481 const struct arm_option_value_table * opt;
b99bd4ef 31482
c19d1205
ZW		 31483 for (opt = arm_float_abis; opt->name != NULL; opt++)
31484 if (streq (opt->name, str))
31485 {
31486 mfloat_abi_opt = opt->value;
c921be7d 31487 return TRUE;
c19d1205 31488 }
cc8a6dd0 31489
c19d1205 31490 as_bad (_("unknown floating point abi `%s'\n"), str);
c921be7d 31491 return FALSE;
c19d1205 31492}
b99bd4ef 31493
c19d1205 31494#ifdef OBJ_ELF
c921be7d 31495static bfd_boolean
17b9d67d 31496arm_parse_eabi (const char * str)
c19d1205 31497{
e74cfd16 31498 const struct arm_option_value_table *opt;
cc8a6dd0 31499
c19d1205
ZW		 31500 for (opt = arm_eabis; opt->name != NULL; opt++)
31501 if (streq (opt->name, str))
31502 {
31503 meabi_flags = opt->value;
c921be7d 31504 return TRUE;
c19d1205
ZW		 31505 }
31506 as_bad (_("unknown EABI `%s'\n"), str);
c921be7d 31507 return FALSE;
c19d1205
ZW		 31508}
31509#endif
cc8a6dd0 31510
c921be7d 31511static bfd_boolean
17b9d67d 31512arm_parse_it_mode (const char * str)
e07e6e58 31513{
c921be7d 31514 bfd_boolean ret = TRUE;
e07e6e58
NC		 31515
31516 if (streq ("arm", str))
31517 implicit_it_mode = IMPLICIT_IT_MODE_ARM;
31518 else if (streq ("thumb", str))
31519 implicit_it_mode = IMPLICIT_IT_MODE_THUMB;
31520 else if (streq ("always", str))
31521 implicit_it_mode = IMPLICIT_IT_MODE_ALWAYS;
31522 else if (streq ("never", str))
31523 implicit_it_mode = IMPLICIT_IT_MODE_NEVER;
31524 else
31525 {
31526 as_bad (_("unknown implicit IT mode `%s', should be "\
477330fc 31527 "arm, thumb, always, or never."), str);
c921be7d 31528 ret = FALSE;
e07e6e58
NC		 31529 }
31530
31531 return ret;
31532}
31533
2e6976a8 31534static bfd_boolean
17b9d67d 31535arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED)
2e6976a8
DG		 31536{
31537 codecomposer_syntax = TRUE;
31538 arm_comment_chars[0] = ';';
31539 arm_line_separator_chars[0] = 0;
31540 return TRUE;
31541}
31542
c19d1205
ZW		 31543struct arm_long_option_table arm_long_opts[] =
31544{
31545 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31546 arm_parse_cpu, NULL},
31547 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31548 arm_parse_arch, NULL},
31549 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31550 arm_parse_fpu, NULL},
31551 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31552 arm_parse_float_abi, NULL},
31553#ifdef OBJ_ELF
7fac0536 31554 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
c19d1205
ZW		 31555 arm_parse_eabi, NULL},
31556#endif
e07e6e58
NC		 31557 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31558 arm_parse_it_mode, NULL},
2e6976a8
DG		 31559 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31560 arm_ccs_mode, NULL},
5312fe52
BW		 31561 {"mfp16-format=",
31562 N_("[ieee|alternative]\n\
31563 set the encoding for half precision floating point "
31564 "numbers to IEEE\n\
31565 or Arm alternative format."),
31566 arm_parse_fp16_opt, NULL },
c19d1205
ZW		 31567 {NULL, NULL, 0, NULL}
31568};
cc8a6dd0 31569
c19d1205 31570int
17b9d67d 31571md_parse_option (int c, const char * arg)
c19d1205
ZW		 31572{
31573 struct arm_option_table *opt;
e74cfd16 31574 const struct arm_legacy_option_table *fopt;
c19d1205 31575 struct arm_long_option_table *lopt;
b99bd4ef 31576
c19d1205 31577 switch (c)
b99bd4ef 31578 {
c19d1205
ZW		 31579#ifdef OPTION_EB
31580 case OPTION_EB:
31581 target_big_endian = 1;
31582 break;
31583#endif
cc8a6dd0 31584
c19d1205
ZW		 31585#ifdef OPTION_EL
31586 case OPTION_EL:
31587 target_big_endian = 0;
31588 break;
31589#endif
b99bd4ef 31590
845b51d6
PB		 31591 case OPTION_FIX_V4BX:
31592 fix_v4bx = TRUE;
31593 break;
31594
18a20338
CL		 31595#ifdef OBJ_ELF
31596 case OPTION_FDPIC:
31597 arm_fdpic = TRUE;
31598 break;
31599#endif /* OBJ_ELF */
31600
c19d1205
ZW		 31601 case 'a':
31602 /* Listing option. Just ignore these, we don't support additional
31603 ones. */
31604 return 0;
b99bd4ef 31605
c19d1205
ZW		 31606 default:
31607 for (opt = arm_opts; opt->option != NULL; opt++)
31608 {
31609 if (c == opt->option[0]
31610 && ((arg == NULL && opt->option[1] == 0)
31611 || streq (arg, opt->option + 1)))
31612 {
c19d1205 31613 /* If the option is deprecated, tell the user. */
278df34e 31614 if (warn_on_deprecated && opt->deprecated != NULL)
c19d1205
ZW		 31615 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31616 arg ? arg : "", _(opt->deprecated));
b99bd4ef 31617
c19d1205
ZW		 31618 if (opt->var != NULL)
31619 *opt->var = opt->value;
cc8a6dd0 31620
c19d1205
ZW		 31621 return 1;
31622 }
31623 }
b99bd4ef 31624
e74cfd16
PB		 31625 for (fopt = arm_legacy_opts; fopt->option != NULL; fopt++)
31626 {
31627 if (c == fopt->option[0]
31628 && ((arg == NULL && fopt->option[1] == 0)
31629 || streq (arg, fopt->option + 1)))
31630 {
e74cfd16 31631 /* If the option is deprecated, tell the user. */
278df34e 31632 if (warn_on_deprecated && fopt->deprecated != NULL)
e74cfd16
PB		 31633 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c,
31634 arg ? arg : "", _(fopt->deprecated));
e74cfd16
PB		 31635
31636 if (fopt->var != NULL)
31637 *fopt->var = &fopt->value;
31638
31639 return 1;
31640 }
31641 }
31642
c19d1205
ZW		 31643 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31644 {
31645 /* These options are expected to have an argument. */
31646 if (c == lopt->option[0]
31647 && arg != NULL
31648 && strncmp (arg, lopt->option + 1,
31649 strlen (lopt->option + 1)) == 0)
31650 {
c19d1205 31651 /* If the option is deprecated, tell the user. */
278df34e 31652 if (warn_on_deprecated && lopt->deprecated != NULL)
c19d1205
ZW		 31653 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c, arg,
31654 _(lopt->deprecated));
b99bd4ef 31655
c19d1205
ZW		 31656 /* Call the sup-option parser. */
31657 return lopt->func (arg + strlen (lopt->option) - 1);
31658 }
31659 }
a737bd4d 31660
c19d1205
ZW		 31661 return 0;
31662 }
a394c00f 31663
c19d1205
ZW		 31664 return 1;
31665}
a394c00f 31666
c19d1205
ZW		 31667void
31668md_show_usage (FILE * fp)
a394c00f 31669{
c19d1205
ZW		 31670 struct arm_option_table *opt;
31671 struct arm_long_option_table *lopt;
a394c00f 31672
c19d1205 31673 fprintf (fp, _(" ARM-specific assembler options:\n"));
a394c00f 31674
c19d1205
ZW		 31675 for (opt = arm_opts; opt->option != NULL; opt++)
31676 if (opt->help != NULL)
31677 fprintf (fp, " -%-23s%s\n", opt->option, _(opt->help));
a394c00f 31678
c19d1205
ZW		 31679 for (lopt = arm_long_opts; lopt->option != NULL; lopt++)
31680 if (lopt->help != NULL)
31681 fprintf (fp, " -%s%s\n", lopt->option, _(lopt->help));
a394c00f 31682
c19d1205
ZW		 31683#ifdef OPTION_EB
31684 fprintf (fp, _("\
31685 -EB assemble code for a big-endian cpu\n"));
a394c00f
NC		 31686#endif
31687
c19d1205
ZW		 31688#ifdef OPTION_EL
31689 fprintf (fp, _("\
31690 -EL assemble code for a little-endian cpu\n"));
a737bd4d 31691#endif
845b51d6
PB		 31692
31693 fprintf (fp, _("\
31694 --fix-v4bx Allow BX in ARMv4 code\n"));
18a20338
CL		 31695
31696#ifdef OBJ_ELF
31697 fprintf (fp, _("\
31698 --fdpic generate an FDPIC object file\n"));
31699#endif /* OBJ_ELF */
c19d1205 31700}
ee065d83 31701
ee065d83 31702#ifdef OBJ_ELF
0198d5e6 31703
62b3e311
PB		 31704typedef struct
31705{
31706 int val;
31707 arm_feature_set flags;
31708} cpu_arch_ver_table;
31709
2c6b98ea
TP		 31710/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31711 chronologically for architectures, with an exception for ARMv6-M and
31712 ARMv6S-M due to legacy reasons. No new architecture should have a
31713 special case. This allows for build attribute selection results to be
31714 stable when new architectures are added. */
62b3e311
PB		 31715static const cpu_arch_ver_table cpu_arch_ver[] =
31716{
031254f2
AV		 31717 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
31718 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
31719 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
31720 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
31721 {TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
31722 {TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
31723 {TAG_CPU_ARCH_V4, ARM_ARCH_V4},
31724 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
31725 {TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
31726 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
31727 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
31728 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
31729 {TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
31730 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
31731 {TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
31732 {TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
31733 {TAG_CPU_ARCH_V6, ARM_ARCH_V6},
31734 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
31735 {TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
31736 {TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
31737 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
31738 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
31739 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
31740 {TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
2c6b98ea
TP		 31741
31742 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31743 always selected build attributes to match those of ARMv6-M
31744 (resp. ARMv6S-M). However, due to these architectures being a strict
31745 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31746 would be selected when fully respecting chronology of architectures.
31747 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31748 move them before ARMv7 architectures. */
031254f2
AV		 31749 {TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
31750 {TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
31751
31752 {TAG_CPU_ARCH_V7, ARM_ARCH_V7},
31753 {TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
31754 {TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
31755 {TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
31756 {TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
31757 {TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
31758 {TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
31759 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
31760 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
31761 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
31762 {TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
31763 {TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
31764 {TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
31765 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
31766 {TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
31767 {TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
31768 {-1, ARM_ARCH_NONE}
62b3e311
PB		 31769};
31770
ee3c0378 31771/* Set an attribute if it has not already been set by the user. */
0198d5e6 31772
ee3c0378
AS		 31773static void
31774aeabi_set_attribute_int (int tag, int value)
31775{
31776 if (tag < 1
31777 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31778 || !attributes_set_explicitly[tag])
31779 bfd_elf_add_proc_attr_int (stdoutput, tag, value);
31780}
31781
31782static void
31783aeabi_set_attribute_string (int tag, const char *value)
31784{
31785 if (tag < 1
31786 || tag >= NUM_KNOWN_OBJ_ATTRIBUTES
31787 || !attributes_set_explicitly[tag])
31788 bfd_elf_add_proc_attr_string (stdoutput, tag, value);
31789}
31790
2c6b98ea
TP		 31791/* Return whether features in the *NEEDED feature set are available via
31792 extensions for the architecture whose feature set is *ARCH_FSET. */
0198d5e6 31793
2c6b98ea
TP		 31794static bfd_boolean
31795have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
31796 const arm_feature_set *needed)
31797{
31798 int i, nb_allowed_archs;
31799 arm_feature_set ext_fset;
31800 const struct arm_option_extension_value_table *opt;
31801
31802 ext_fset = arm_arch_none;
31803 for (opt = arm_extensions; opt->name != NULL; opt++)
31804 {
31805 /* Extension does not provide any feature we need. */
31806 if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
31807 continue;
31808
31809 nb_allowed_archs =
31810 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
31811 for (i = 0; i < nb_allowed_archs; i++)
31812 {
31813 /* Empty entry. */
31814 if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
31815 break;
31816
31817 /* Extension is available, add it. */
31818 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
31819 ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
31820 }
31821 }
31822
31823 /* Can we enable all features in *needed? */
31824 return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
31825}
31826
31827/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31828 a given architecture feature set *ARCH_EXT_FSET including extension feature
31829 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31830 - if true, check for an exact match of the architecture modulo extensions;
31831 - otherwise, select build attribute value of the first superset
31832 architecture released so that results remains stable when new architectures
31833 are added.
31834 For -march/-mcpu=all the build attribute value of the most featureful
31835 architecture is returned. Tag_CPU_arch_profile result is returned in
31836 PROFILE. */
0198d5e6 31837
2c6b98ea
TP		 31838static int
31839get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
31840 const arm_feature_set *ext_fset,
31841 char *profile, int exact_match)
31842{
31843 arm_feature_set arch_fset;
31844 const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
31845
31846 /* Select most featureful architecture with all its extensions if building
31847 for -march=all as the feature sets used to set build attributes. */
31848 if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
31849 {
31850 /* Force revisiting of decision for each new architecture. */
031254f2 31851 gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
2c6b98ea
TP		 31852 *profile = 'A';
31853 return TAG_CPU_ARCH_V8;
31854 }
31855
31856 ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
31857
31858 for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
31859 {
31860 arm_feature_set known_arch_fset;
31861
31862 ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
31863 if (exact_match)
31864 {
31865 /* Base architecture match user-specified architecture and
31866 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31867 if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
31868 {
31869 p_ver_ret = p_ver;
31870 goto found;
31871 }
31872 /* Base architecture match user-specified architecture only
31873 (eg. ARMv6-M in the same case as above). Record it in case we
31874 find a match with above condition. */
31875 else if (p_ver_ret == NULL
31876 && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
31877 p_ver_ret = p_ver;
31878 }
31879 else
31880 {
31881
31882 /* Architecture has all features wanted. */
31883 if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
31884 {
31885 arm_feature_set added_fset;
31886
31887 /* Compute features added by this architecture over the one
31888 recorded in p_ver_ret. */
31889 if (p_ver_ret != NULL)
31890 ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
31891 p_ver_ret->flags);
31892 /* First architecture that match incl. with extensions, or the
31893 only difference in features over the recorded match is
31894 features that were optional and are now mandatory. */
31895 if (p_ver_ret == NULL
31896 || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
31897 {
31898 p_ver_ret = p_ver;
31899 goto found;
31900 }
31901 }
31902 else if (p_ver_ret == NULL)
31903 {
31904 arm_feature_set needed_ext_fset;
31905
31906 ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
31907
31908 /* Architecture has all features needed when using some
31909 extensions. Record it and continue searching in case there
31910 exist an architecture providing all needed features without
31911 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31912 OS extension). */
31913 if (have_ext_for_needed_feat_p (&known_arch_fset,
31914 &needed_ext_fset))
31915 p_ver_ret = p_ver;
31916 }
31917 }
31918 }
31919
31920 if (p_ver_ret == NULL)
31921 return -1;
31922
31923found:
31924 /* Tag_CPU_arch_profile. */
31925 if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
31926 || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
31927 || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
31928 && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
31929 *profile = 'A';
31930 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
31931 *profile = 'R';
31932 else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
31933 *profile = 'M';
31934 else
31935 *profile = '\0';
31936 return p_ver_ret->val;
31937}
31938
ee065d83 31939/* Set the public EABI object attributes. */
0198d5e6 31940
c168ce07 31941static void
ee065d83
PB		 31942aeabi_set_public_attributes (void)
31943{
b90d5ba0 31944 char profile = '\0';
2c6b98ea 31945 int arch = -1;
90ec0d68 31946 int virt_sec = 0;
bca38921 31947 int fp16_optional = 0;
2c6b98ea
TP		 31948 int skip_exact_match = 0;
31949 arm_feature_set flags, flags_arch, flags_ext;
ee065d83 31950
54bab281
TP		 31951 /* Autodetection mode, choose the architecture based the instructions
31952 actually used. */
31953 if (no_cpu_selected ())
31954 {
31955 ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
ddd7f988 31956
54bab281
TP		 31957 if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
31958 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
ddd7f988 31959
54bab281
TP		 31960 if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
31961 ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
ddd7f988 31962
54bab281 31963 /* Code run during relaxation relies on selected_cpu being set. */
4d354d8b
TP		 31964 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
31965 flags_ext = arm_arch_none;
31966 ARM_CLEAR_FEATURE (selected_arch, flags_arch, flags_ext);
31967 selected_ext = flags_ext;
54bab281
TP		 31968 selected_cpu = flags;
31969 }
31970 /* Otherwise, choose the architecture based on the capabilities of the
31971 requested cpu. */
31972 else
4d354d8b
TP		 31973 {
31974 ARM_MERGE_FEATURE_SETS (flags_arch, selected_arch, selected_ext);
31975 ARM_CLEAR_FEATURE (flags_arch, flags_arch, fpu_any);
31976 flags_ext = selected_ext;
31977 flags = selected_cpu;
31978 }
31979 ARM_MERGE_FEATURE_SETS (flags, flags, selected_fpu);
7f78eb34 31980
ddd7f988 31981 /* Allow the user to override the reported architecture. */
4d354d8b 31982 if (!ARM_FEATURE_ZERO (selected_object_arch))
7a1d4c38 31983 {
4d354d8b 31984 ARM_CLEAR_FEATURE (flags_arch, selected_object_arch, fpu_any);
2c6b98ea 31985 flags_ext = arm_arch_none;
7a1d4c38 31986 }
2c6b98ea 31987 else
4d354d8b 31988 skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
2c6b98ea
TP		 31989
31990 /* When this function is run again after relaxation has happened there is no
31991 way to determine whether an architecture or CPU was specified by the user:
31992 - selected_cpu is set above for relaxation to work;
31993 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31994 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31995 Therefore, if not in -march=all case we first try an exact match and fall
31996 back to autodetection. */
31997 if (!skip_exact_match)
31998 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
31999 if (arch == -1)
32000 arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
32001 if (arch == -1)
32002 as_bad (_("no architecture contains all the instructions used\n"));
9e3c6df6 32003
ee065d83
PB		 32004 /* Tag_CPU_name. */
32005 if (selected_cpu_name[0])
32006 {
91d6fa6a 32007 char *q;
ee065d83 32008
91d6fa6a
NC		 32009 q = selected_cpu_name;
32010 if (strncmp (q, "armv", 4) == 0)
ee065d83
PB		 32011 {
32012 int i;
5f4273c7 32013
91d6fa6a
NC		 32014 q += 4;
32015 for (i = 0; q[i]; i++)
32016 q[i] = TOUPPER (q[i]);
ee065d83 32017 }
91d6fa6a 32018 aeabi_set_attribute_string (Tag_CPU_name, q);
ee065d83 32019 }
62f3b8c8 32020
ee065d83 32021 /* Tag_CPU_arch. */
ee3c0378 32022 aeabi_set_attribute_int (Tag_CPU_arch, arch);
62f3b8c8 32023
62b3e311 32024 /* Tag_CPU_arch_profile. */
69239280
MGD		 32025 if (profile != '\0')
32026 aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
62f3b8c8 32027
15afaa63 32028 /* Tag_DSP_extension. */
4d354d8b 32029 if (ARM_CPU_HAS_FEATURE (selected_ext, arm_ext_dsp))
6c290d53 32030 aeabi_set_attribute_int (Tag_DSP_extension, 1);
15afaa63 32031
2c6b98ea 32032 ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
ee065d83 32033 /* Tag_ARM_ISA_use. */
ee3c0378 32034 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
2c6b98ea 32035 || ARM_FEATURE_ZERO (flags_arch))
ee3c0378 32036 aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
62f3b8c8 32037
ee065d83 32038 /* Tag_THUMB_ISA_use. */
ee3c0378 32039 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
2c6b98ea 32040 || ARM_FEATURE_ZERO (flags_arch))
4ed7ed8d
TP		 32041 {
32042 int thumb_isa_use;
32043
32044 if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
16a1fa25 32045 && ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
4ed7ed8d
TP		 32046 thumb_isa_use = 3;
32047 else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
32048 thumb_isa_use = 2;
32049 else
32050 thumb_isa_use = 1;
32051 aeabi_set_attribute_int (Tag_THUMB_ISA_use, thumb_isa_use);
32052 }
62f3b8c8 32053
ee065d83 32054 /* Tag_VFP_arch. */
a715796b
TG		 32055 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_armv8xd))
32056 aeabi_set_attribute_int (Tag_VFP_arch,
32057 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
32058 ? 7 : 8);
bca38921 32059 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_fma))
62f3b8c8
PB		 32060 aeabi_set_attribute_int (Tag_VFP_arch,
32061 ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32)
32062 ? 5 : 6);
32063 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_d32))
bca38921
MGD		 32064 {
32065 fp16_optional = 1;
32066 aeabi_set_attribute_int (Tag_VFP_arch, 3);
32067 }
ada65aa3 32068 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v3xd))
bca38921
MGD		 32069 {
32070 aeabi_set_attribute_int (Tag_VFP_arch, 4);
32071 fp16_optional = 1;
32072 }
ee3c0378
AS		 32073 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v2))
32074 aeabi_set_attribute_int (Tag_VFP_arch, 2);
32075 else if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1)
477330fc 32076 || ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd))
ee3c0378 32077 aeabi_set_attribute_int (Tag_VFP_arch, 1);
62f3b8c8 32078
4547cb56
NC		 32079 /* Tag_ABI_HardFP_use. */
32080 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1xd)
32081 && !ARM_CPU_HAS_FEATURE (flags, fpu_vfp_ext_v1))
32082 aeabi_set_attribute_int (Tag_ABI_HardFP_use, 1);
32083
ee065d83 32084 /* Tag_WMMX_arch. */
ee3c0378
AS		 32085 if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt2))
32086 aeabi_set_attribute_int (Tag_WMMX_arch, 2);
32087 else if (ARM_CPU_HAS_FEATURE (flags, arm_cext_iwmmxt))
32088 aeabi_set_attribute_int (Tag_WMMX_arch, 1);
62f3b8c8 32089
ee3c0378 32090 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
9411fd44
MW		 32091 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v8_1))
32092 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 4);
32093 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_armv8))
bca38921
MGD		 32094 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 3);
32095 else if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_v1))
32096 {
32097 if (ARM_CPU_HAS_FEATURE (flags, fpu_neon_ext_fma))
32098 {
32099 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 2);
32100 }
32101 else
32102 {
32103 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch, 1);
32104 fp16_optional = 1;
32105 }
32106 }
fa94de6b 32107
a7ad558c
AV		 32108 if (ARM_CPU_HAS_FEATURE (flags, mve_fp_ext))
32109 aeabi_set_attribute_int (Tag_MVE_arch, 2);
32110 else if (ARM_CPU_HAS_FEATURE (flags, mve_ext))
32111 aeabi_set_attribute_int (Tag_MVE_arch, 1);
32112
ee3c0378 32113 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
bca38921 32114 if (ARM_CPU_HAS_FEATURE (flags, fpu_vfp_fp16) && fp16_optional)
ee3c0378 32115 aeabi_set_attribute_int (Tag_VFP_HP_extension, 1);
4547cb56 32116
69239280
MGD		 32117 /* Tag_DIV_use.
32118
32119 We set Tag_DIV_use to two when integer divide instructions have been used
32120 in ARM state, or when Thumb integer divide instructions have been used,
32121 but we have no architecture profile set, nor have we any ARM instructions.
32122
4ed7ed8d
TP		 32123 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32124 by the base architecture.
bca38921 32125
69239280 32126 For new architectures we will have to check these tests. */
031254f2 32127 gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
4ed7ed8d
TP		 32128 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
32129 || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
bca38921
MGD		 32130 aeabi_set_attribute_int (Tag_DIV_use, 0);
32131 else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_adiv)
32132 || (profile == '\0'
32133 && ARM_CPU_HAS_FEATURE (flags, arm_ext_div)
32134 && !ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any)))
eea54501 32135 aeabi_set_attribute_int (Tag_DIV_use, 2);
60e5ef9f
MGD		 32136
32137 /* Tag_MP_extension_use. */
32138 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_mp))
32139 aeabi_set_attribute_int (Tag_MPextension_use, 1);
f4c65163
MGD		 32140
32141 /* Tag Virtualization_use. */
32142 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_sec))
90ec0d68
MGD		 32143 virt_sec |= 1;
32144 if (ARM_CPU_HAS_FEATURE (flags, arm_ext_virt))
32145 virt_sec |= 2;
32146 if (virt_sec != 0)
32147 aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
5312fe52
BW		 32148
32149 if (fp16_format != ARM_FP16_FORMAT_DEFAULT)
32150 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format, fp16_format);
ee065d83
PB		 32151}
32152
c168ce07
TP		 32153/* Post relaxation hook. Recompute ARM attributes now that relaxation is
32154 finished and free extension feature bits which will not be used anymore. */
0198d5e6 32155
c168ce07
TP		 32156void
32157arm_md_post_relax (void)
32158{
32159 aeabi_set_public_attributes ();
4d354d8b
TP		 32160 XDELETE (mcpu_ext_opt);
32161 mcpu_ext_opt = NULL;
32162 XDELETE (march_ext_opt);
32163 march_ext_opt = NULL;
c168ce07
TP		 32164}
32165
104d59d1 32166/* Add the default contents for the .ARM.attributes section. */
0198d5e6 32167
ee065d83
PB		 32168void
32169arm_md_end (void)
32170{
ee065d83
PB		 32171 if (EF_ARM_EABI_VERSION (meabi_flags) < EF_ARM_EABI_VER4)
32172 return;
32173
32174 aeabi_set_public_attributes ();
ee065d83 32175}
8463be01 32176#endif /* OBJ_ELF */
ee065d83 32177
ee065d83
PB		 32178/* Parse a .cpu directive. */
32179
32180static void
32181s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
32182{
e74cfd16 32183 const struct arm_cpu_option_table *opt;
ee065d83
PB		 32184 char *name;
32185 char saved_char;
32186
32187 name = input_line_pointer;
5f4273c7 32188 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 32189 input_line_pointer++;
32190 saved_char = *input_line_pointer;
32191 *input_line_pointer = 0;
32192
32193 /* Skip the first "all" entry. */
32194 for (opt = arm_cpus + 1; opt->name != NULL; opt++)
32195 if (streq (opt->name, name))
32196 {
4d354d8b
TP		 32197 selected_arch = opt->value;
32198 selected_ext = opt->ext;
32199 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
ee065d83 32200 if (opt->canonical_name)
5f4273c7 32201 strcpy (selected_cpu_name, opt->canonical_name);
ee065d83
PB		 32202 else
32203 {
32204 int i;
32205 for (i = 0; opt->name[i]; i++)
32206 selected_cpu_name[i] = TOUPPER (opt->name[i]);
f3bad469 32207
ee065d83
PB		 32208 selected_cpu_name[i] = 0;
32209 }
4d354d8b
TP		 32210 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
32211
ee065d83
PB		 32212 *input_line_pointer = saved_char;
32213 demand_empty_rest_of_line ();
32214 return;
32215 }
32216 as_bad (_("unknown cpu `%s'"), name);
32217 *input_line_pointer = saved_char;
32218 ignore_rest_of_line ();
32219}
32220
ee065d83
PB		 32221/* Parse a .arch directive. */
32222
32223static void
32224s_arm_arch (int ignored ATTRIBUTE_UNUSED)
32225{
e74cfd16 32226 const struct arm_arch_option_table *opt;
ee065d83
PB		 32227 char saved_char;
32228 char *name;
32229
32230 name = input_line_pointer;
5f4273c7 32231 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 32232 input_line_pointer++;
32233 saved_char = *input_line_pointer;
32234 *input_line_pointer = 0;
32235
32236 /* Skip the first "all" entry. */
32237 for (opt = arm_archs + 1; opt->name != NULL; opt++)
32238 if (streq (opt->name, name))
32239 {
4d354d8b
TP		 32240 selected_arch = opt->value;
32241 selected_ext = arm_arch_none;
32242 selected_cpu = selected_arch;
5f4273c7 32243 strcpy (selected_cpu_name, opt->name);
4d354d8b 32244 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB		 32245 *input_line_pointer = saved_char;
32246 demand_empty_rest_of_line ();
32247 return;
32248 }
32249
32250 as_bad (_("unknown architecture `%s'\n"), name);
32251 *input_line_pointer = saved_char;
32252 ignore_rest_of_line ();
32253}
32254
7a1d4c38
PB		 32255/* Parse a .object_arch directive. */
32256
32257static void
32258s_arm_object_arch (int ignored ATTRIBUTE_UNUSED)
32259{
32260 const struct arm_arch_option_table *opt;
32261 char saved_char;
32262 char *name;
32263
32264 name = input_line_pointer;
5f4273c7 32265 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
7a1d4c38
PB		 32266 input_line_pointer++;
32267 saved_char = *input_line_pointer;
32268 *input_line_pointer = 0;
32269
32270 /* Skip the first "all" entry. */
32271 for (opt = arm_archs + 1; opt->name != NULL; opt++)
32272 if (streq (opt->name, name))
32273 {
4d354d8b 32274 selected_object_arch = opt->value;
7a1d4c38
PB		 32275 *input_line_pointer = saved_char;
32276 demand_empty_rest_of_line ();
32277 return;
32278 }
32279
32280 as_bad (_("unknown architecture `%s'\n"), name);
32281 *input_line_pointer = saved_char;
32282 ignore_rest_of_line ();
32283}
32284
69133863
MGD		 32285/* Parse a .arch_extension directive. */
32286
32287static void
32288s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED)
32289{
32290 const struct arm_option_extension_value_table *opt;
32291 char saved_char;
32292 char *name;
32293 int adding_value = 1;
32294
32295 name = input_line_pointer;
32296 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
32297 input_line_pointer++;
32298 saved_char = *input_line_pointer;
32299 *input_line_pointer = 0;
32300
32301 if (strlen (name) >= 2
32302 && strncmp (name, "no", 2) == 0)
32303 {
32304 adding_value = 0;
32305 name += 2;
32306 }
32307
32308 for (opt = arm_extensions; opt->name != NULL; opt++)
32309 if (streq (opt->name, name))
32310 {
d942732e
TP		 32311 int i, nb_allowed_archs =
32312 sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[i]);
32313 for (i = 0; i < nb_allowed_archs; i++)
32314 {
32315 /* Empty entry. */
4d354d8b 32316 if (ARM_CPU_IS_ANY (opt->allowed_archs[i]))
d942732e 32317 continue;
4d354d8b 32318 if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], selected_arch))
d942732e
TP		 32319 break;
32320 }
32321
32322 if (i == nb_allowed_archs)
69133863
MGD		 32323 {
32324 as_bad (_("architectural extension `%s' is not allowed for the "
32325 "current base architecture"), name);
32326 break;
32327 }
32328
32329 if (adding_value)
4d354d8b 32330 ARM_MERGE_FEATURE_SETS (selected_ext, selected_ext,
5a70a223 32331 opt->merge_value);
69133863 32332 else
4d354d8b 32333 ARM_CLEAR_FEATURE (selected_ext, selected_ext, opt->clear_value);
69133863 32334
4d354d8b
TP		 32335 ARM_MERGE_FEATURE_SETS (selected_cpu, selected_arch, selected_ext);
32336 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
69133863
MGD		 32337 *input_line_pointer = saved_char;
32338 demand_empty_rest_of_line ();
3d030cdb
TP		 32339 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32340 on this return so that duplicate extensions (extensions with the
32341 same name as a previous extension in the list) are not considered
32342 for command-line parsing. */
69133863
MGD		 32343 return;
32344 }
32345
32346 if (opt->name == NULL)
e673710a 32347 as_bad (_("unknown architecture extension `%s'\n"), name);
69133863
MGD		 32348
32349 *input_line_pointer = saved_char;
32350 ignore_rest_of_line ();
32351}
32352
ee065d83
PB		 32353/* Parse a .fpu directive. */
32354
32355static void
32356s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
32357{
69133863 32358 const struct arm_option_fpu_value_table *opt;
ee065d83
PB		 32359 char saved_char;
32360 char *name;
32361
32362 name = input_line_pointer;
5f4273c7 32363 while (*input_line_pointer && !ISSPACE (*input_line_pointer))
ee065d83
PB		 32364 input_line_pointer++;
32365 saved_char = *input_line_pointer;
32366 *input_line_pointer = 0;
5f4273c7 32367
ee065d83
PB		 32368 for (opt = arm_fpus; opt->name != NULL; opt++)
32369 if (streq (opt->name, name))
32370 {
4d354d8b
TP		 32371 selected_fpu = opt->value;
32372#ifndef CPU_DEFAULT
32373 if (no_cpu_selected ())
32374 ARM_MERGE_FEATURE_SETS (cpu_variant, arm_arch_any, selected_fpu);
32375 else
32376#endif
32377 ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, selected_fpu);
ee065d83
PB		 32378 *input_line_pointer = saved_char;
32379 demand_empty_rest_of_line ();
32380 return;
32381 }
32382
32383 as_bad (_("unknown floating point format `%s'\n"), name);
32384 *input_line_pointer = saved_char;
32385 ignore_rest_of_line ();
32386}
ee065d83 32387
794ba86a 32388/* Copy symbol information. */
f31fef98 32389
794ba86a
DJ		 32390void
32391arm_copy_symbol_attributes (symbolS *dest, symbolS *src)
32392{
32393 ARM_GET_FLAG (dest) = ARM_GET_FLAG (src);
32394}
e04befd0 32395
f31fef98 32396#ifdef OBJ_ELF
e04befd0
AS		 32397/* Given a symbolic attribute NAME, return the proper integer value.
32398 Returns -1 if the attribute is not known. */
f31fef98 32399
e04befd0
AS		 32400int
32401arm_convert_symbolic_attribute (const char *name)
32402{
f31fef98
NC		 32403 static const struct
32404 {
32405 const char * name;
32406 const int tag;
32407 }
32408 attribute_table[] =
32409 {
32410 /* When you modify this table you should
32411 also modify the list in doc/c-arm.texi. */
e04befd0 32412#define T(tag) {#tag, tag}
f31fef98
NC		 32413 T (Tag_CPU_raw_name),
32414 T (Tag_CPU_name),
32415 T (Tag_CPU_arch),
32416 T (Tag_CPU_arch_profile),
32417 T (Tag_ARM_ISA_use),
32418 T (Tag_THUMB_ISA_use),
75375b3e 32419 T (Tag_FP_arch),
f31fef98
NC		 32420 T (Tag_VFP_arch),
32421 T (Tag_WMMX_arch),
32422 T (Tag_Advanced_SIMD_arch),
32423 T (Tag_PCS_config),
32424 T (Tag_ABI_PCS_R9_use),
32425 T (Tag_ABI_PCS_RW_data),
32426 T (Tag_ABI_PCS_RO_data),
32427 T (Tag_ABI_PCS_GOT_use),
32428 T (Tag_ABI_PCS_wchar_t),
32429 T (Tag_ABI_FP_rounding),
32430 T (Tag_ABI_FP_denormal),
32431 T (Tag_ABI_FP_exceptions),
32432 T (Tag_ABI_FP_user_exceptions),
32433 T (Tag_ABI_FP_number_model),
75375b3e 32434 T (Tag_ABI_align_needed),
f31fef98 32435 T (Tag_ABI_align8_needed),
75375b3e 32436 T (Tag_ABI_align_preserved),
f31fef98
NC		 32437 T (Tag_ABI_align8_preserved),
32438 T (Tag_ABI_enum_size),
32439 T (Tag_ABI_HardFP_use),
32440 T (Tag_ABI_VFP_args),
32441 T (Tag_ABI_WMMX_args),
32442 T (Tag_ABI_optimization_goals),
32443 T (Tag_ABI_FP_optimization_goals),
32444 T (Tag_compatibility),
32445 T (Tag_CPU_unaligned_access),
75375b3e 32446 T (Tag_FP_HP_extension),
f31fef98
NC		 32447 T (Tag_VFP_HP_extension),
32448 T (Tag_ABI_FP_16bit_format),
cd21e546
MGD		 32449 T (Tag_MPextension_use),
32450 T (Tag_DIV_use),
f31fef98
NC		 32451 T (Tag_nodefaults),
32452 T (Tag_also_compatible_with),
32453 T (Tag_conformance),
32454 T (Tag_T2EE_use),
32455 T (Tag_Virtualization_use),
15afaa63 32456 T (Tag_DSP_extension),
a7ad558c 32457 T (Tag_MVE_arch),
cd21e546 32458 /* We deliberately do not include Tag_MPextension_use_legacy. */
e04befd0 32459#undef T
f31fef98 32460 };
e04befd0
AS		 32461 unsigned int i;
32462
32463 if (name == NULL)
32464 return -1;
32465
f31fef98 32466 for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
c921be7d 32467 if (streq (name, attribute_table[i].name))
e04befd0
AS		 32468 return attribute_table[i].tag;
32469
32470 return -1;
32471}
267bf995 32472
93ef582d
NC		 32473/* Apply sym value for relocations only in the case that they are for
32474 local symbols in the same segment as the fixup and you have the
32475 respective architectural feature for blx and simple switches. */
0198d5e6 32476
267bf995 32477int
93ef582d 32478arm_apply_sym_value (struct fix * fixP, segT this_seg)
267bf995
RR		 32479{
32480 if (fixP->fx_addsy
32481 && ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v5t)
93ef582d
NC		 32482 /* PR 17444: If the local symbol is in a different section then a reloc
32483 will always be generated for it, so applying the symbol value now
32484 will result in a double offset being stored in the relocation. */
32485 && (S_GET_SEGMENT (fixP->fx_addsy) == this_seg)
34e77a92 32486 && !S_FORCE_RELOC (fixP->fx_addsy, TRUE))
267bf995
RR		 32487 {
32488 switch (fixP->fx_r_type)
32489 {
32490 case BFD_RELOC_ARM_PCREL_BLX:
32491 case BFD_RELOC_THUMB_PCREL_BRANCH23:
32492 if (ARM_IS_FUNC (fixP->fx_addsy))
32493 return 1;
32494 break;
32495
32496 case BFD_RELOC_ARM_PCREL_CALL:
32497 case BFD_RELOC_THUMB_PCREL_BLX:
32498 if (THUMB_IS_FUNC (fixP->fx_addsy))
93ef582d 32499 return 1;
267bf995
RR		 32500 break;
32501
32502 default:
32503 break;
32504 }
32505
32506 }
32507 return 0;
32508}
f31fef98 32509#endif /* OBJ_ELF */
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