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sim: drop targ-vals.def->nltvals.def indirection
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
99d8e879
MF		 12016-01-10 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4
6d90347b
MF		 52016-01-10 Mike Frysinger <vapier@gentoo.org>
6
7 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
8 * configure: Regenerate.
9
347fe5bb
MF		 102016-01-10 Mike Frysinger <vapier@gentoo.org>
11
12 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
13 * configure: Regenerate.
14
22be3fbe
MF		 152016-01-10 Mike Frysinger <vapier@gentoo.org>
16
17 * configure: Regenerate.
18
0dc73ef7
MF		 192016-01-10 Mike Frysinger <vapier@gentoo.org>
20
21 * configure: Regenerate.
22
936df756
MF		 232016-01-09 Mike Frysinger <vapier@gentoo.org>
24
25 * config.in, configure: Regenerate.
26
2e3d4f4d
MF		 272016-01-06 Mike Frysinger <vapier@gentoo.org>
28
29 * interp.c (sim_open): Mark argv const.
30 (sim_create_inferior): Mark argv and env const.
31
9bbf6f91
MF		 322016-01-04 Mike Frysinger <vapier@gentoo.org>
33
34 * configure: Regenerate.
35
77cf2ef5
MF		 362016-01-03 Mike Frysinger <vapier@gentoo.org>
37
38 * interp.c (sim_open): Update sim_parse_args comment.
39
0cb8d851
MF		 402016-01-03 Mike Frysinger <vapier@gentoo.org>
41
42 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
43 * configure: Regenerate.
44
1ac72f06
MF		 452016-01-02 Mike Frysinger <vapier@gentoo.org>
46
47 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
48 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
49 * configure: Regenerate.
50 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
51
d47f5b30
MF		 522016-01-02 Mike Frysinger <vapier@gentoo.org>
53
54 * dv-tx3904cpu.c (CPU, SD): Delete.
55
e1211e55
MF		 562015-12-30 Mike Frysinger <vapier@gentoo.org>
57
58 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
59 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
60 (sim_store_register): Rename to ...
61 (mips_reg_store): ... this. Delete local cpu var.
62 Update sim_io_eprintf calls.
63 (sim_fetch_register): Rename to ...
64 (mips_reg_fetch): ... this. Delete local cpu var.
65 Update sim_io_eprintf calls.
66
5e744ef8
MF		 672015-12-27 Mike Frysinger <vapier@gentoo.org>
68
69 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
70
1b393626
MF		 712015-12-26 Mike Frysinger <vapier@gentoo.org>
72
73 * config.in, configure: Regenerate.
74
26f8bf63
MF		 752015-12-26 Mike Frysinger <vapier@gentoo.org>
76
77 * interp.c (sim_write, sim_read): Delete.
78 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
79 (load_word): Likewise.
80 * micromips.igen (cache): Likewise.
81 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
82 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
83 do_store_left, do_store_right, do_load_double, do_store_double):
84 Likewise.
85 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
86 (do_prefx): Likewise.
87 * sim-main.c (address_translation, prefetch): Delete.
88 (ifetch32, ifetch16): Delete call to AddressTranslation and set
89 paddr=vaddr.
90 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
91 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
92 (LoadMemory, StoreMemory): Delete CCA arg.
93
ef04e371
MF		 942015-12-24 Mike Frysinger <vapier@gentoo.org>
95
96 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
97 * configure: Regenerated.
98
cb379ede
MF		 992015-12-24 Mike Frysinger <vapier@gentoo.org>
100
101 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
102 * tconfig.h: Delete.
103
26936211
MF		 1042015-12-24 Mike Frysinger <vapier@gentoo.org>
105
106 * tconfig.h (SIM_HANDLES_LMA): Delete.
107
84e8e361
MF		 1082015-12-24 Mike Frysinger <vapier@gentoo.org>
109
110 * sim-main.h (WITH_WATCHPOINTS): Delete.
111
3cabaf66
MF		 1122015-12-24 Mike Frysinger <vapier@gentoo.org>
113
114 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
115
8abe6c66
MF		 1162015-12-24 Mike Frysinger <vapier@gentoo.org>
117
118 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
119
1d19cae7
DV		 1202015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
121
122 * micromips.igen (process_isa_mode): Fix left shift of negative
123 value.
124
cdf850e9
MF		 1252015-11-17 Mike Frysinger <vapier@gentoo.org>
126
127 * sim-main.h (WITH_MODULO_MEMORY): Delete.
128
797eee42
MF		 1292015-11-15 Mike Frysinger <vapier@gentoo.org>
130
131 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
132
6e4f085c
MF		 1332015-11-14 Mike Frysinger <vapier@gentoo.org>
134
135 * interp.c (sim_close): Rename to ...
136 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
137 sim_io_shutdown.
138 * sim-main.h (mips_sim_close): Declare.
139 (SIM_CLOSE_HOOK): Define.
140
8e394ffc
AB		 1412015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
142 Ali Lown <ali.lown@imgtec.com>
143
144 * Makefile.in (tmp-micromips): New rule.
145 (tmp-mach-multi): Add support for micromips.
146 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
147 that works for both mips64 and micromips64.
148 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
149 micromips32.
150 Add build support for micromips.
151 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
152 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
153 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
154 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
155 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
156 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
157 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
158 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
159 Refactored instruction code to use these functions.
160 * dsp2.igen: Refactored instruction code to use the new functions.
161 * interp.c (decode_coproc): Refactored to work with any instruction
162 encoding.
163 (isa_mode): New variable
164 (RSVD_INSTRUCTION): Changed to 0x00000039.
165 * m16.igen (BREAK16): Refactored instruction to use do_break16.
166 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
167 * micromips.dc: New file.
168 * micromips.igen: New file.
169 * micromips16.dc: New file.
170 * micromipsdsp.igen: New file.
171 * micromipsrun.c: New file.
172 * mips.igen (do_swc1): Changed to work with any instruction encoding.
173 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
174 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
175 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
176 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
177 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
178 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
179 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
180 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
181 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
182 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
183 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
184 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
185 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
186 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
187 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
188 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
189 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
190 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
191 instructions.
192 Refactored instruction code to use these functions.
193 (RSVD): Changed to use new reserved instruction.
194 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
195 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
196 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
197 do_store_double): Added micromips32 and micromips64 models.
198 Added include for micromips.igen and micromipsdsp.igen
199 Add micromips32 and micromips64 models.
200 (DecodeCoproc): Updated to use new macro definition.
201 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
202 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
203 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
204 Refactored instruction code to use these functions.
205 * sim-main.h (CP0_operation): New enum.
206 (DecodeCoproc): Updated macro.
207 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
208 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
209 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
210 ISA_MODE_MICROMIPS): New defines.
211 (sim_state): Add isa_mode field.
212
8d0978fb
MF		 2132015-06-23 Mike Frysinger <vapier@gentoo.org>
214
215 * configure: Regenerate.
216
306f4178
MF		 2172015-06-12 Mike Frysinger <vapier@gentoo.org>
218
219 * configure.ac: Change configure.in to configure.ac.
220 * configure: Regenerate.
221
a3487082
MF		 2222015-06-12 Mike Frysinger <vapier@gentoo.org>
223
224 * configure: Regenerate.
225
29bc024d
MF		 2262015-06-12 Mike Frysinger <vapier@gentoo.org>
227
228 * interp.c [TRACE]: Delete.
229 (TRACE): Change to WITH_TRACE_ANY_P.
230 [!WITH_TRACE_ANY_P] (open_trace): Define.
231 (mips_option_handler, open_trace, sim_close, dotrace):
232 Change defined(TRACE) to WITH_TRACE_ANY_P.
233 (sim_open): Delete TRACE ifdef check.
234 * sim-main.c (load_memory): Delete TRACE ifdef check.
235 (store_memory): Likewise.
236 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
237 [!WITH_TRACE_ANY_P] (dotrace): Define.
238
3ebe2863
MF		 2392015-04-18 Mike Frysinger <vapier@gentoo.org>
240
241 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
242 comments.
243
20bca71d
MF		 2442015-04-18 Mike Frysinger <vapier@gentoo.org>
245
246 * sim-main.h (SIM_CPU): Delete.
247
7e83aa92
MF		 2482015-04-18 Mike Frysinger <vapier@gentoo.org>
249
250 * sim-main.h (sim_cia): Delete.
251
034685f9
MF		 2522015-04-17 Mike Frysinger <vapier@gentoo.org>
253
254 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
255 PU_PC_GET.
256 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
257 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
258 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
259 CIA_SET to CPU_PC_SET.
260 * sim-main.h (CIA_GET, CIA_SET): Delete.
261
78e9aa70
MF		 2622015-04-15 Mike Frysinger <vapier@gentoo.org>
263
264 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
265 * sim-main.h (STATE_CPU): Delete.
266
bf12d44e
MF		 2672015-04-13 Mike Frysinger <vapier@gentoo.org>
268
269 * configure: Regenerate.
270
7bebb329
MF		 2712015-04-13 Mike Frysinger <vapier@gentoo.org>
272
273 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
274 * interp.c (mips_pc_get, mips_pc_set): New functions.
275 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
276 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
277 (sim_pc_get): Delete.
278 * sim-main.h (SIM_CPU): Define.
279 (struct sim_state): Change cpu to an array of pointers.
280 (STATE_CPU): Drop &.
281
8ac57fbd
MF		 2822015-04-13 Mike Frysinger <vapier@gentoo.org>
283
284 * interp.c (mips_option_handler, open_trace, sim_close,
285 sim_write, sim_read, sim_store_register, sim_fetch_register,
286 sim_create_inferior, pr_addr, pr_uword64): Convert old style
287 prototypes.
288 (sim_open): Convert old style prototype. Change casts with
289 sim_write to unsigned char *.
290 (fetch_str): Change null to unsigned char, and change cast to
291 unsigned char *.
292 (sim_monitor): Change c & ch to unsigned char. Change cast to
293 unsigned char *.
294
e787f858
MF		 2952015-04-12 Mike Frysinger <vapier@gentoo.org>
296
297 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
298
122bbfb5
MF		 2992015-04-06 Mike Frysinger <vapier@gentoo.org>
300
301 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
302
0fe84f3f
MF		 3032015-04-01 Mike Frysinger <vapier@gentoo.org>
304
305 * tconfig.h (SIM_HAVE_PROFILE): Delete.
306
aadc9410
MF		 3072015-03-31 Mike Frysinger <vapier@gentoo.org>
308
309 * config.in, configure: Regenerate.
310
05f53ed6
MF		 3112015-03-24 Mike Frysinger <vapier@gentoo.org>
312
313 * interp.c (sim_pc_get): New function.
314
c0931f26
MF		 3152015-03-24 Mike Frysinger <vapier@gentoo.org>
316
317 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
318 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
319
30452bbe
MF		 3202015-03-24 Mike Frysinger <vapier@gentoo.org>
321
322 * configure: Regenerate.
323
64dd13df
MF		 3242015-03-23 Mike Frysinger <vapier@gentoo.org>
325
326 * configure: Regenerate.
327
49cd1634
MF		 3282015-03-23 Mike Frysinger <vapier@gentoo.org>
329
330 * configure: Regenerate.
331 * configure.ac (mips_extra_objs): Delete.
332 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
333 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
334
3649cb06
MF		 3352015-03-23 Mike Frysinger <vapier@gentoo.org>
336
337 * configure: Regenerate.
338 * configure.ac: Delete sim_hw checks for dv-sockser.
339
ae7d0cac
MF		 3402015-03-16 Mike Frysinger <vapier@gentoo.org>
341
342 * config.in, configure: Regenerate.
343 * tconfig.in: Rename file ...
344 * tconfig.h: ... here.
345
8406bb59
MF		 3462015-03-15 Mike Frysinger <vapier@gentoo.org>
347
348 * tconfig.in: Delete includes.
349 [HAVE_DV_SOCKSER]: Delete.
350
465fb143
MF		 3512015-03-14 Mike Frysinger <vapier@gentoo.org>
352
353 * Makefile.in (SIM_RUN_OBJS): Delete.
354
5cddc23a
MF		 3552015-03-14 Mike Frysinger <vapier@gentoo.org>
356
357 * configure.ac (AC_CHECK_HEADERS): Delete.
358 * aclocal.m4, configure: Regenerate.
359
2974be62
AM		 3602014-08-19 Alan Modra <amodra@gmail.com>
361
362 * configure: Regenerate.
363
faa743bb
RM		 3642014-08-15 Roland McGrath <mcgrathr@google.com>
365
366 * configure: Regenerate.
367 * config.in: Regenerate.
368
1a8a700e
MF		 3692014-03-04 Mike Frysinger <vapier@gentoo.org>
370
371 * configure: Regenerate.
372
bf3d9781
AM		 3732013-09-23 Alan Modra <amodra@gmail.com>
374
375 * configure: Regenerate.
376
31e6ad7d
MF		 3772013-06-03 Mike Frysinger <vapier@gentoo.org>
378
379 * aclocal.m4, configure: Regenerate.
380
d3685d60
TT		 3812013-05-10 Freddie Chopin <freddie_chopin@op.pl>
382
383 * configure: Rebuild.
384
1517bd27
MF		 3852013-03-26 Mike Frysinger <vapier@gentoo.org>
386
387 * configure: Regenerate.
388
3be31516
JS		 3892013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
390
391 * configure.ac: Address use of dv-sockser.o.
392 * tconfig.in: Conditionalize use of dv_sockser_install.
393 * configure: Regenerated.
394 * config.in: Regenerated.
395
37cb8f8e
SE		 3962012-10-04 Chao-ying Fu <fu@mips.com>
397 Steve Ellcey <sellcey@mips.com>
398
399 * mips/mips3264r2.igen (rdhwr): New.
400
87c8644f
JS		 4012012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
402
403 * configure.ac: Always link against dv-sockser.o.
404 * configure: Regenerate.
405
5f3ef9d0
JB		 4062012-06-15 Joel Brobecker <brobecker@adacore.com>
407
408 * config.in, configure: Regenerate.
409
a6ff997c
NC		 4102012-05-18 Nick Clifton <nickc@redhat.com>
411
412 PR 14072
413 * interp.c: Include config.h before system header files.
414
2232061b
MF		 4152012-03-24 Mike Frysinger <vapier@gentoo.org>
416
417 * aclocal.m4, config.in, configure: Regenerate.
418
db2e4d67
MF		 4192011-12-03 Mike Frysinger <vapier@gentoo.org>
420
421 * aclocal.m4: New file.
422 * configure: Regenerate.
423
4399a56b
MF		 4242011-10-19 Mike Frysinger <vapier@gentoo.org>
425
426 * configure: Regenerate after common/acinclude.m4 update.
427
9c082ca8
MF		 4282011-10-17 Mike Frysinger <vapier@gentoo.org>
429
430 * configure.ac: Change include to common/acinclude.m4.
431
6ffe910a
MF		 4322011-10-17 Mike Frysinger <vapier@gentoo.org>
433
434 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
435 call. Replace common.m4 include with SIM_AC_COMMON.
436 * configure: Regenerate.
437
31b28250
HPN		 4382011-07-08 Hans-Peter Nilsson <hp@axis.com>
439
3faa01e3
HPN		 440 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
441 $(SIM_EXTRA_DEPS).
442 (tmp-mach-multi): Exit early when igen fails.
31b28250 443
2419798b
MF		 4442011-07-05 Mike Frysinger <vapier@gentoo.org>
445
446 * interp.c (sim_do_command): Delete.
447
d79fe0d6
MF		 4482011-02-14 Mike Frysinger <vapier@gentoo.org>
449
450 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
451 (tx3904sio_fifo_reset): Likewise.
452 * interp.c (sim_monitor): Likewise.
453
5558e7e6
MF		 4542010-04-14 Mike Frysinger <vapier@gentoo.org>
455
456 * interp.c (sim_write): Add const to buffer arg.
457
35aafff4
JB		 4582010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
459
460 * interp.c: Don't include sysdep.h
461
3725885a
RW		 4622010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
463
464 * configure: Regenerate.
465
d6416cdc
RW		 4662009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
467
81ecdfbb
RW		 468 * config.in: Regenerate.
469 * configure: Likewise.
470
d6416cdc
RW		 471 * configure: Regenerate.
472
b5bd9624
HPN		 4732008-07-11 Hans-Peter Nilsson <hp@axis.com>
474
475 * configure: Regenerate to track ../common/common.m4 changes.
476 * config.in: Ditto.
477
6efef468 4782008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 479 Daniel Jacobowitz <dan@codesourcery.com>
480 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 481
482 * configure: Regenerate.
483
60dc88db
RS		 4842007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
485
486 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
487 that unconditionally allows fmt_ps.
488 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
489 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
490 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
491 filter from 64,f to 32,f.
492 (PREFX): Change filter from 64 to 32.
493 (LDXC1, LUXC1): Provide separate mips32r2 implementations
494 that use do_load_double instead of do_load. Make both LUXC1
495 versions unpredictable if SizeFGR () != 64.
496 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
497 instead of do_store. Remove unused variable. Make both SUXC1
498 versions unpredictable if SizeFGR () != 64.
499
599ca73e
RS		 5002007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
501
502 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
503 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
504 shifts for that case.
505
2525df03
NC		 5062007-09-04 Nick Clifton <nickc@redhat.com>
507
508 * interp.c (options enum): Add OPTION_INFO_MEMORY.
509 (display_mem_info): New static variable.
510 (mips_option_handler): Handle OPTION_INFO_MEMORY.
511 (mips_options): Add info-memory and memory-info.
512 (sim_open): After processing the command line and board
513 specification, check display_mem_info. If it is set then
514 call the real handler for the --memory-info command line
515 switch.
516
35ee6e1e
JB		 5172007-08-24 Joel Brobecker <brobecker@adacore.com>
518
519 * configure.ac: Change license of multi-run.c to GPL version 3.
520 * configure: Regenerate.
521
d5fb0879
RS		 5222007-06-28 Richard Sandiford <richard@codesourcery.com>
523
524 * configure.ac, configure: Revert last patch.
525
2a2ce21b
RS		 5262007-06-26 Richard Sandiford <richard@codesourcery.com>
527
528 * configure.ac (sim_mipsisa3264_configs): New variable.
529 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
530 every configuration support all four targets, using the triplet to
531 determine the default.
532 * configure: Regenerate.
533
efdcccc9
RS		 5342007-06-25 Richard Sandiford <richard@codesourcery.com>
535
0a7692b2 536 * Makefile.in (m16run.o): New rule.
efdcccc9 537
f532a356
TS		 5382007-05-15 Thiemo Seufer <ths@mips.com>
539
540 * mips3264r2.igen (DSHD): Fix compile warning.
541
bfe9c90b
TS		 5422007-05-14 Thiemo Seufer <ths@mips.com>
543
544 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
545 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
546 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
547 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
548 for mips32r2.
549
53f4826b
TS		 5502007-03-01 Thiemo Seufer <ths@mips.com>
551
552 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
553 and mips64.
554
8bf3ddc8
TS		 5552007-02-20 Thiemo Seufer <ths@mips.com>
556
557 * dsp.igen: Update copyright notice.
558 * dsp2.igen: Fix copyright notice.
559
8b082fb1 5602007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 561 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 562
563 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
564 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
565 Add dsp2 to sim_igen_machine.
566 * configure: Regenerate.
567 * dsp.igen (do_ph_op): Add MUL support when op = 2.
568 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
569 (mulq_rs.ph): Use do_ph_mulq.
570 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
571 * mips.igen: Add dsp2 model and include dsp2.igen.
572 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
573 for *mips32r2, *mips64r2, *dsp.
574 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
575 for *mips32r2, *mips64r2, *dsp2.
576 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
577
b1004875 5782007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 579 Nigel Stephens <nigel@mips.com>
b1004875
TS		 580
581 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
582 jumps with hazard barrier.
583
f8df4c77 5842007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 585 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 586
587 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
588 after each call to sim_io_write.
589
b1004875 5902007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 591 Nigel Stephens <nigel@mips.com>
b1004875
TS		 592
593 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
594 supported by this simulator.
07802d98
TS		 595 (decode_coproc): Recognise additional CP0 Config registers
596 correctly.
597
14fb6c5a 5982007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 599 Nigel Stephens <nigel@mips.com>
600 David Ung <davidu@mips.com>
14fb6c5a
TS		 601
602 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
603 uninterpreted formats. If fmt is one of the uninterpreted types
604 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
605 fmt_word, and fmt_uninterpreted_64 like fmt_long.
606 (store_fpr): When writing an invalid odd register, set the
607 matching even register to fmt_unknown, not the following register.
608 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
609 the the memory window at offset 0 set by --memory-size command
610 line option.
611 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
612 point register.
613 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
614 register.
615 (sim_monitor): When returning the memory size to the MIPS
616 application, use the value in STATE_MEM_SIZE, not an arbitrary
617 hardcoded value.
618 (cop_lw): Don' mess around with FPR_STATE, just pass
619 fmt_uninterpreted_32 to StoreFPR.
620 (cop_sw): Similarly.
621 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
622 (cop_sd): Similarly.
623 * mips.igen (not_word_value): Single version for mips32, mips64
624 and mips16.
625
c8847145 6262007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 627 Nigel Stephens <nigel@mips.com>
c8847145
TS		 628
629 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
630 MBytes.
631
4b5d35ee
TS		 6322007-02-17 Thiemo Seufer <ths@mips.com>
633
634 * configure.ac (mips*-sde-elf*): Move in front of generic machine
635 configuration.
636 * configure: Regenerate.
637
3669427c
TS		 6382007-02-17 Thiemo Seufer <ths@mips.com>
639
640 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
641 Add mdmx to sim_igen_machine.
642 (mipsisa64*-*-*): Likewise. Remove dsp.
643 (mipsisa32*-*-*): Remove dsp.
644 * configure: Regenerate.
645
109ad085
TS		 6462007-02-13 Thiemo Seufer <ths@mips.com>
647
648 * configure.ac: Add mips*-sde-elf* target.
649 * configure: Regenerate.
650
921d7ad3
HPN		 6512006-12-21 Hans-Peter Nilsson <hp@axis.com>
652
653 * acconfig.h: Remove.
654 * config.in, configure: Regenerate.
655
02f97da7
TS		 6562006-11-07 Thiemo Seufer <ths@mips.com>
657
658 * dsp.igen (do_w_op): Fix compiler warning.
659
2d2733fc 6602006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 661 David Ung <davidu@mips.com>
2d2733fc
TS		 662
663 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
664 sim_igen_machine.
665 * configure: Regenerate.
666 * mips.igen (model): Add smartmips.
667 (MADDU): Increment ACX if carry.
668 (do_mult): Clear ACX.
669 (ROR,RORV): Add smartmips.
72f4393d 670 (include): Include smartmips.igen.
2d2733fc
TS		 671 * sim-main.h (ACX): Set to REGISTERS[89].
672 * smartmips.igen: New file.
673
d85c3a10 6742006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 675 David Ung <davidu@mips.com>
d85c3a10
TS		 676
677 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
678 mips3264r2.igen. Add missing dependency rules.
679 * m16e.igen: Support for mips16e save/restore instructions.
680
e85e3205
RE		 6812006-06-13 Richard Earnshaw <rearnsha@arm.com>
682
683 * configure: Regenerated.
684
2f0122dc
DJ		 6852006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
686
687 * configure: Regenerated.
688
20e95c23
DJ		 6892006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
690
691 * configure: Regenerated.
692
69088b17
CF		 6932006-05-15 Chao-ying Fu <fu@mips.com>
694
695 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
696
0275de4e
NC		 6972006-04-18 Nick Clifton <nickc@redhat.com>
698
699 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
700 statement.
701
b3a3ffef
HPN		 7022006-03-29 Hans-Peter Nilsson <hp@axis.com>
703
704 * configure: Regenerate.
705
40a5538e
CF		 7062005-12-14 Chao-ying Fu <fu@mips.com>
707
708 * Makefile.in (SIM_OBJS): Add dsp.o.
709 (dsp.o): New dependency.
710 (IGEN_INCLUDE): Add dsp.igen.
711 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
712 mipsisa64*-*-*): Add dsp to sim_igen_machine.
713 * configure: Regenerate.
714 * mips.igen: Add dsp model and include dsp.igen.
715 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
716 because these instructions are extended in DSP ASE.
717 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
718 adding 6 DSP accumulator registers and 1 DSP control register.
719 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
720 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
721 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
722 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
723 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
724 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
725 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
726 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
727 DSPCR_CCOND_SMASK): New define.
728 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
729 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
730
21d14896
ILT		 7312005-07-08 Ian Lance Taylor <ian@airs.com>
732
733 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
734
b16d63da 7352005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 736 Nigel Stephens <nigel@mips.com>
737
738 * mips.igen: New mips16e model and include m16e.igen.
739 (check_u64): Add mips16e tag.
740 * m16e.igen: New file for MIPS16e instructions.
741 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
742 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
743 models.
744 * configure: Regenerate.
b16d63da 745
e70cb6cd 7462005-05-26 David Ung <davidu@mips.com>
72f4393d 747
e70cb6cd
CD		 748 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
749 tags to all instructions which are applicable to the new ISAs.
750 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
751 vr.igen.
752 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 753 instructions.
e70cb6cd
CD		 754 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
755 to mips.igen.
756 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
757 * configure: Regenerate.
72f4393d 758
2b193c4a
MK		 7592005-03-23 Mark Kettenis <kettenis@gnu.org>
760
761 * configure: Regenerate.
762
35695fd6
AC		 7632005-01-14 Andrew Cagney <cagney@gnu.org>
764
765 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
766 explicit call to AC_CONFIG_HEADER.
767 * configure: Regenerate.
768
f0569246
AC		 7692005-01-12 Andrew Cagney <cagney@gnu.org>
770
771 * configure.ac: Update to use ../common/common.m4.
772 * configure: Re-generate.
773
38f48d72
AC		 7742005-01-11 Andrew Cagney <cagney@localhost.localdomain>
775
776 * configure: Regenerated to track ../common/aclocal.m4 changes.
777
b7026657
AC		 7782005-01-07 Andrew Cagney <cagney@gnu.org>
779
780 * configure.ac: Rename configure.in, require autoconf 2.59.
781 * configure: Re-generate.
782
379832de
HPN		 7832004-12-08 Hans-Peter Nilsson <hp@axis.com>
784
785 * configure: Regenerate for ../common/aclocal.m4 update.
786
cd62154c 7872004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 788
cd62154c
AC		 789 Committed by Andrew Cagney.
790 * m16.igen (CMP, CMPI): Fix assembler.
791
e5da76ec
CD		 7922004-08-18 Chris Demetriou <cgd@broadcom.com>
793
794 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
795 * configure: Regenerate.
796
139181c8
CD		 7972004-06-25 Chris Demetriou <cgd@broadcom.com>
798
799 * configure.in (sim_m16_machine): Include mipsIII.
800 * configure: Regenerate.
801
1a27f959
CD		 8022004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
803
72f4393d 804 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 805 from COP0_BADVADDR.
806 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
807
5dbb7b5a
CD		 8082004-04-10 Chris Demetriou <cgd@broadcom.com>
809
810 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
811
14234056
CD		 8122004-04-09 Chris Demetriou <cgd@broadcom.com>
813
814 * mips.igen (check_fmt): Remove.
815 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
816 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
817 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
818 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
819 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
820 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
821 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
822 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
823 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
824 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
825
c6f9085c
CD		 8262004-04-09 Chris Demetriou <cgd@broadcom.com>
827
828 * sb1.igen (check_sbx): New function.
829 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
830
11d66e66 8312004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 832 Richard Sandiford <rsandifo@redhat.com>
833
834 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
835 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
836 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
837 separate implementations for mipsIV and mipsV. Use new macros to
838 determine whether the restrictions apply.
839
b3208fb8
CD		 8402004-01-19 Chris Demetriou <cgd@broadcom.com>
841
842 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
843 (check_mult_hilo): Improve comments.
844 (check_div_hilo): Likewise. Also, fork off a new version
845 to handle mips32/mips64 (since there are no hazards to check
846 in MIPS32/MIPS64).
847
9a1d84fb
CD		 8482003-06-17 Richard Sandiford <rsandifo@redhat.com>
849
850 * mips.igen (do_dmultx): Fix check for negative operands.
851
ae451ac6
ILT		 8522003-05-16 Ian Lance Taylor <ian@airs.com>
853
854 * Makefile.in (SHELL): Make sure this is defined.
855 (various): Use $(SHELL) whenever we invoke move-if-change.
856
dd69d292
CD		 8572003-05-03 Chris Demetriou <cgd@broadcom.com>
858
859 * cp1.c: Tweak attribution slightly.
860 * cp1.h: Likewise.
861 * mdmx.c: Likewise.
862 * mdmx.igen: Likewise.
863 * mips3d.igen: Likewise.
864 * sb1.igen: Likewise.
865
bcd0068e
CD		 8662003-04-15 Richard Sandiford <rsandifo@redhat.com>
867
868 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
869 unsigned operands.
870
6b4a8935
AC		 8712003-02-27 Andrew Cagney <cagney@redhat.com>
872
601da316
AC		 873 * interp.c (sim_open): Rename _bfd to bfd.
874 (sim_create_inferior): Ditto.
6b4a8935 875
d29e330f
CD		 8762003-01-14 Chris Demetriou <cgd@broadcom.com>
877
878 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
879
a2353a08
CD		 8802003-01-14 Chris Demetriou <cgd@broadcom.com>
881
882 * mips.igen (EI, DI): Remove.
883
80551777
CD		 8842003-01-05 Richard Sandiford <rsandifo@redhat.com>
885
886 * Makefile.in (tmp-run-multi): Fix mips16 filter.
887
4c54fc26
CD		 8882003-01-04 Richard Sandiford <rsandifo@redhat.com>
889 Andrew Cagney <ac131313@redhat.com>
890 Gavin Romig-Koch <gavin@redhat.com>
891 Graydon Hoare <graydon@redhat.com>
892 Aldy Hernandez <aldyh@redhat.com>
893 Dave Brolley <brolley@redhat.com>
894 Chris Demetriou <cgd@broadcom.com>
895
896 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
897 (sim_mach_default): New variable.
898 (mips64vr-*-*, mips64vrel-*-*): New configurations.
899 Add a new simulator generator, MULTI.
900 * configure: Regenerate.
901 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
902 (multi-run.o): New dependency.
903 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
904 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
905 (tmp-multi): Combine them.
906 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
907 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
908 (distclean-extra): New rule.
909 * sim-main.h: Include bfd.h.
910 (MIPS_MACH): New macro.
911 * mips.igen (vr4120, vr5400, vr5500): New models.
912 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
913 * vr.igen: Replace with new version.
914
e6c674b8
CD		 9152003-01-04 Chris Demetriou <cgd@broadcom.com>
916
917 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
918 * configure: Regenerate.
919
28f50ac8
CD		 9202002-12-31 Chris Demetriou <cgd@broadcom.com>
921
922 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
923 * mips.igen: Remove all invocations of check_branch_bug and
924 mark_branch_bug.
925
5071ffe6
CD		 9262002-12-16 Chris Demetriou <cgd@broadcom.com>
927
72f4393d 928 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 929
06e7837e
CD		 9302002-07-30 Chris Demetriou <cgd@broadcom.com>
931
932 * mips.igen (do_load_double, do_store_double): New functions.
933 (LDC1, SDC1): Rename to...
934 (LDC1b, SDC1b): respectively.
935 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
936
2265c243
MS		 9372002-07-29 Michael Snyder <msnyder@redhat.com>
938
939 * cp1.c (fp_recip2): Modify initialization expression so that
940 GCC will recognize it as constant.
941
a2f8b4f3
CD		 9422002-06-18 Chris Demetriou <cgd@broadcom.com>
943
944 * mdmx.c (SD_): Delete.
945 (Unpredictable): Re-define, for now, to directly invoke
946 unpredictable_action().
947 (mdmx_acc_op): Fix error in .ob immediate handling.
948
b4b6c939
AC		 9492002-06-18 Andrew Cagney <cagney@redhat.com>
950
951 * interp.c (sim_firmware_command): Initialize `address'.
952
c8cca39f
AC		 9532002-06-16 Andrew Cagney <ac131313@redhat.com>
954
955 * configure: Regenerated to track ../common/aclocal.m4 changes.
956
e7e81181 9572002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 958 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 959
960 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
961 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
962 * mips.igen: Include mips3d.igen.
963 (mips3d): New model name for MIPS-3D ASE instructions.
964 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 965 instructions.
e7e81181
CD		 966 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
967 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
968 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
969 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
970 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
971 (RSquareRoot1, RSquareRoot2): New macros.
972 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
973 (fp_rsqrt2): New functions.
974 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
975 * configure: Regenerate.
976
3a2b820e 9772002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 978 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 979
980 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
981 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
982 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
983 (convert): Note that this function is not used for paired-single
984 format conversions.
985 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
986 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
987 (check_fmt_p): Enable paired-single support.
988 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
989 (PUU.PS): New instructions.
990 (CVT.S.fmt): Don't use this instruction for paired-single format
991 destinations.
992 * sim-main.h (FP_formats): New value 'fmt_ps.'
993 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
994 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
995
d18ea9c2
CD		 9962002-06-12 Chris Demetriou <cgd@broadcom.com>
997
998 * mips.igen: Fix formatting of function calls in
999 many FP operations.
1000
95fd5cee
CD		 10012002-06-12 Chris Demetriou <cgd@broadcom.com>
1002
1003 * mips.igen (MOVN, MOVZ): Trace result.
1004 (TNEI): Print "tnei" as the opcode name in traces.
1005 (CEIL.W): Add disassembly string for traces.
1006 (RSQRT.fmt): Make location of disassembly string consistent
1007 with other instructions.
1008
4f0d55ae
CD		 10092002-06-12 Chris Demetriou <cgd@broadcom.com>
1010
1011 * mips.igen (X): Delete unused function.
1012
3c25f8c7
AC		 10132002-06-08 Andrew Cagney <cagney@redhat.com>
1014
1015 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1016
f3c08b7e 10172002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1018 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1019
1020 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1021 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1022 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1023 (fp_nmsub): New prototypes.
1024 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1025 (NegMultiplySub): New defines.
1026 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1027 (MADD.D, MADD.S): Replace with...
1028 (MADD.fmt): New instruction.
1029 (MSUB.D, MSUB.S): Replace with...
1030 (MSUB.fmt): New instruction.
1031 (NMADD.D, NMADD.S): Replace with...
1032 (NMADD.fmt): New instruction.
1033 (NMSUB.D, MSUB.S): Replace with...
1034 (NMSUB.fmt): New instruction.
1035
52714ff9 10362002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1037 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1038
1039 * cp1.c: Fix more comment spelling and formatting.
1040 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1041 (denorm_mode): New function.
1042 (fpu_unary, fpu_binary): Round results after operation, collect
1043 status from rounding operations, and update the FCSR.
1044 (convert): Collect status from integer conversions and rounding
1045 operations, and update the FCSR. Adjust NaN values that result
1046 from conversions. Convert to use sim_io_eprintf rather than
1047 fprintf, and remove some debugging code.
1048 * cp1.h (fenr_FS): New define.
1049
577d8c4b
CD		 10502002-06-07 Chris Demetriou <cgd@broadcom.com>
1051
1052 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1053 rounding mode to sim FP rounding mode flag conversion code into...
1054 (rounding_mode): New function.
1055
196496ed
CD		 10562002-06-07 Chris Demetriou <cgd@broadcom.com>
1057
1058 * cp1.c: Clean up formatting of a few comments.
1059 (value_fpr): Reformat switch statement.
1060
cfe9ea23 10612002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1062 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1063
1064 * cp1.h: New file.
1065 * sim-main.h: Include cp1.h.
1066 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1067 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1068 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1069 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1070 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1071 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1072 * cp1.c: Don't include sim-fpu.h; already included by
1073 sim-main.h. Clean up formatting of some comments.
1074 (NaN, Equal, Less): Remove.
1075 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1076 (fp_cmp): New functions.
1077 * mips.igen (do_c_cond_fmt): Remove.
1078 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1079 Compare. Add result tracing.
1080 (CxC1): Remove, replace with...
1081 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1082 (DMxC1): Remove, replace with...
1083 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1084 (MxC1): Remove, replace with...
1085 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1086
ee7254b0
CD		 10872002-06-04 Chris Demetriou <cgd@broadcom.com>
1088
1089 * sim-main.h (FGRIDX): Remove, replace all uses with...
1090 (FGR_BASE): New macro.
1091 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1092 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1093 (NR_FGR, FGR): Likewise.
1094 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1095 * mips.igen: Likewise.
1096
d3eb724f
CD		 10972002-06-04 Chris Demetriou <cgd@broadcom.com>
1098
1099 * cp1.c: Add an FSF Copyright notice to this file.
1100
ba46ddd0 11012002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1102 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1103
1104 * cp1.c (Infinity): Remove.
1105 * sim-main.h (Infinity): Likewise.
1106
1107 * cp1.c (fp_unary, fp_binary): New functions.
1108 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1109 (fp_sqrt): New functions, implemented in terms of the above.
1110 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1111 (Recip, SquareRoot): Remove (replaced by functions above).
1112 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1113 (fp_recip, fp_sqrt): New prototypes.
1114 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1115 (Recip, SquareRoot): Replace prototypes with #defines which
1116 invoke the functions above.
72f4393d 1117
18d8a52d
CD		 11182002-06-03 Chris Demetriou <cgd@broadcom.com>
1119
1120 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1121 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1122 file, remove PARAMS from prototypes.
1123 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1124 simulator state arguments.
1125 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1126 pass simulator state arguments.
1127 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1128 (store_fpr, convert): Remove 'sd' argument.
1129 (value_fpr): Likewise. Convert to use 'SD' instead.
1130
0f154cbd
CD		 11312002-06-03 Chris Demetriou <cgd@broadcom.com>
1132
1133 * cp1.c (Min, Max): Remove #if 0'd functions.
1134 * sim-main.h (Min, Max): Remove.
1135
e80fc152
CD		 11362002-06-03 Chris Demetriou <cgd@broadcom.com>
1137
1138 * cp1.c: fix formatting of switch case and default labels.
1139 * interp.c: Likewise.
1140 * sim-main.c: Likewise.
1141
bad673a9
CD		 11422002-06-03 Chris Demetriou <cgd@broadcom.com>
1143
1144 * cp1.c: Clean up comments which describe FP formats.
1145 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1146
7cbea089 11472002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1148 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1149
1150 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1151 Broadcom SiByte SB-1 processor configurations.
1152 * configure: Regenerate.
1153 * sb1.igen: New file.
1154 * mips.igen: Include sb1.igen.
1155 (sb1): New model.
1156 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1157 * mdmx.igen: Add "sb1" model to all appropriate functions and
1158 instructions.
1159 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1160 (ob_func, ob_acc): Reference the above.
1161 (qh_acc): Adjust to keep the same size as ob_acc.
1162 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1163 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1164
909daa82
CD		 11652002-06-03 Chris Demetriou <cgd@broadcom.com>
1166
1167 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1168
f4f1b9f1 11692002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1170 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1171
1172 * mips.igen (mdmx): New (pseudo-)model.
1173 * mdmx.c, mdmx.igen: New files.
1174 * Makefile.in (SIM_OBJS): Add mdmx.o.
1175 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1176 New typedefs.
1177 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1178 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1179 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1180 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1181 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1182 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1183 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1184 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1185 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1186 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1187 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1188 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1189 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1190 (qh_fmtsel): New macros.
1191 (_sim_cpu): New member "acc".
1192 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1193 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1194
5accf1ff
CD		 11952002-05-01 Chris Demetriou <cgd@broadcom.com>
1196
1197 * interp.c: Use 'deprecated' rather than 'depreciated.'
1198 * sim-main.h: Likewise.
1199
402586aa
CD		 12002002-05-01 Chris Demetriou <cgd@broadcom.com>
1201
1202 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1203 which wouldn't compile anyway.
1204 * sim-main.h (unpredictable_action): New function prototype.
1205 (Unpredictable): Define to call igen function unpredictable().
1206 (NotWordValue): New macro to call igen function not_word_value().
1207 (UndefinedResult): Remove.
1208 * interp.c (undefined_result): Remove.
1209 (unpredictable_action): New function.
1210 * mips.igen (not_word_value, unpredictable): New functions.
1211 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1212 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1213 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1214 NotWordValue() to check for unpredictable inputs, then
1215 Unpredictable() to handle them.
1216
c9b9995a
CD		 12172002-02-24 Chris Demetriou <cgd@broadcom.com>
1218
1219 * mips.igen: Fix formatting of calls to Unpredictable().
1220
e1015982
AC		 12212002-04-20 Andrew Cagney <ac131313@redhat.com>
1222
1223 * interp.c (sim_open): Revert previous change.
1224
b882a66b
AO		 12252002-04-18 Alexandre Oliva <aoliva@redhat.com>
1226
1227 * interp.c (sim_open): Disable chunk of code that wrote code in
1228 vector table entries.
1229
c429b7dd
CD		 12302002-03-19 Chris Demetriou <cgd@broadcom.com>
1231
1232 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1233 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1234 unused definitions.
1235
37d146fa
CD		 12362002-03-19 Chris Demetriou <cgd@broadcom.com>
1237
1238 * cp1.c: Fix many formatting issues.
1239
07892c0b
CD		 12402002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1241
1242 * cp1.c (fpu_format_name): New function to replace...
1243 (DOFMT): This. Delete, and update all callers.
1244 (fpu_rounding_mode_name): New function to replace...
1245 (RMMODE): This. Delete, and update all callers.
1246
487f79b7
CD		 12472002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1248
1249 * interp.c: Move FPU support routines from here to...
1250 * cp1.c: Here. New file.
1251 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1252 (cp1.o): New target.
1253
1e799e28
CD		 12542002-03-12 Chris Demetriou <cgd@broadcom.com>
1255
1256 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1257 * mips.igen (mips32, mips64): New models, add to all instructions
1258 and functions as appropriate.
1259 (loadstore_ea, check_u64): New variant for model mips64.
1260 (check_fmt_p): New variant for models mipsV and mips64, remove
1261 mipsV model marking fro other variant.
1262 (SLL) Rename to...
1263 (SLLa) this.
1264 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1265 for mips32 and mips64.
1266 (DCLO, DCLZ): New instructions for mips64.
1267
82f728db
CD		 12682002-03-07 Chris Demetriou <cgd@broadcom.com>
1269
1270 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1271 immediate or code as a hex value with the "%#lx" format.
1272 (ANDI): Likewise, and fix printed instruction name.
1273
b96e7ef1
CD		 12742002-03-05 Chris Demetriou <cgd@broadcom.com>
1275
1276 * sim-main.h (UndefinedResult, Unpredictable): New macros
1277 which currently do nothing.
1278
d35d4f70
CD		 12792002-03-05 Chris Demetriou <cgd@broadcom.com>
1280
1281 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1282 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1283 (status_CU3): New definitions.
1284
1285 * sim-main.h (ExceptionCause): Add new values for MIPS32
1286 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1287 for DebugBreakPoint and NMIReset to note their status in
1288 MIPS32 and MIPS64.
1289 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1290 (SignalExceptionCacheErr): New exception macros.
1291
3ad6f714
CD		 12922002-03-05 Chris Demetriou <cgd@broadcom.com>
1293
1294 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1295 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1296 is always enabled.
1297 (SignalExceptionCoProcessorUnusable): Take as argument the
1298 unusable coprocessor number.
1299
86b77b47
CD		 13002002-03-05 Chris Demetriou <cgd@broadcom.com>
1301
1302 * mips.igen: Fix formatting of all SignalException calls.
1303
97a88e93 13042002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1305
1306 * sim-main.h (SIGNEXTEND): Remove.
1307
97a88e93 13082002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1309
1310 * mips.igen: Remove gencode comment from top of file, fix
1311 spelling in another comment.
1312
97a88e93 13132002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1314
1315 * mips.igen (check_fmt, check_fmt_p): New functions to check
1316 whether specific floating point formats are usable.
1317 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1318 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1319 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1320 Use the new functions.
1321 (do_c_cond_fmt): Remove format checks...
1322 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1323
97a88e93 13242002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1325
1326 * mips.igen: Fix formatting of check_fpu calls.
1327
41774c9d
CD		 13282002-03-03 Chris Demetriou <cgd@broadcom.com>
1329
1330 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1331
4a0bd876
CD		 13322002-03-03 Chris Demetriou <cgd@broadcom.com>
1333
1334 * mips.igen: Remove whitespace at end of lines.
1335
09297648
CD		 13362002-03-02 Chris Demetriou <cgd@broadcom.com>
1337
1338 * mips.igen (loadstore_ea): New function to do effective
1339 address calculations.
1340 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1341 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1342 CACHE): Use loadstore_ea to do effective address computations.
1343
043b7057
CD		 13442002-03-02 Chris Demetriou <cgd@broadcom.com>
1345
1346 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1347 * mips.igen (LL, CxC1, MxC1): Likewise.
1348
c1e8ada4
CD		 13492002-03-02 Chris Demetriou <cgd@broadcom.com>
1350
1351 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1352 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1353 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1354 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1355 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1356 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1357 Don't split opcode fields by hand, use the opcode field values
1358 provided by igen.
1359
3e1dca16
CD		 13602002-03-01 Chris Demetriou <cgd@broadcom.com>
1361
1362 * mips.igen (do_divu): Fix spacing.
1363
1364 * mips.igen (do_dsllv): Move to be right before DSLLV,
1365 to match the rest of the do_<shift> functions.
1366
fff8d27d
CD		 13672002-03-01 Chris Demetriou <cgd@broadcom.com>
1368
1369 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1370 DSRL32, do_dsrlv): Trace inputs and results.
1371
0d3e762b
CD		 13722002-03-01 Chris Demetriou <cgd@broadcom.com>
1373
1374 * mips.igen (CACHE): Provide instruction-printing string.
1375
1376 * interp.c (signal_exception): Comment tokens after #endif.
1377
eb5fcf93
CD		 13782002-02-28 Chris Demetriou <cgd@broadcom.com>
1379
1380 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1381 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1382 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1383 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1384 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1385 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1386 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1387 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1388
bb22bd7d
CD		 13892002-02-28 Chris Demetriou <cgd@broadcom.com>
1390
1391 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1392 instruction-printing string.
1393 (LWU): Use '64' as the filter flag.
1394
91a177cf
CD		 13952002-02-28 Chris Demetriou <cgd@broadcom.com>
1396
1397 * mips.igen (SDXC1): Fix instruction-printing string.
1398
387f484a
CD		 13992002-02-28 Chris Demetriou <cgd@broadcom.com>
1400
1401 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1402 filter flags "32,f".
1403
3d81f391
CD		 14042002-02-27 Chris Demetriou <cgd@broadcom.com>
1405
1406 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1407 as the filter flag.
1408
af5107af
CD		 14092002-02-27 Chris Demetriou <cgd@broadcom.com>
1410
1411 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1412 add a comma) so that it more closely match the MIPS ISA
1413 documentation opcode partitioning.
1414 (PREF): Put useful names on opcode fields, and include
1415 instruction-printing string.
1416
ca971540
CD		 14172002-02-27 Chris Demetriou <cgd@broadcom.com>
1418
1419 * mips.igen (check_u64): New function which in the future will
1420 check whether 64-bit instructions are usable and signal an
1421 exception if not. Currently a no-op.
1422 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1423 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1424 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1425 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1426
1427 * mips.igen (check_fpu): New function which in the future will
1428 check whether FPU instructions are usable and signal an exception
1429 if not. Currently a no-op.
1430 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1431 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1432 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1433 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1434 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1435 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1436 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1437 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1438
1c47a468
CD		 14392002-02-27 Chris Demetriou <cgd@broadcom.com>
1440
1441 * mips.igen (do_load_left, do_load_right): Move to be immediately
1442 following do_load.
1443 (do_store_left, do_store_right): Move to be immediately following
1444 do_store.
1445
603a98e7
CD		 14462002-02-27 Chris Demetriou <cgd@broadcom.com>
1447
1448 * mips.igen (mipsV): New model name. Also, add it to
1449 all instructions and functions where it is appropriate.
1450
c5d00cc7
CD		 14512002-02-18 Chris Demetriou <cgd@broadcom.com>
1452
1453 * mips.igen: For all functions and instructions, list model
1454 names that support that instruction one per line.
1455
074e9cb8
CD		 14562002-02-11 Chris Demetriou <cgd@broadcom.com>
1457
1458 * mips.igen: Add some additional comments about supported
1459 models, and about which instructions go where.
1460 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1461 order as is used in the rest of the file.
1462
9805e229
CD		 14632002-02-11 Chris Demetriou <cgd@broadcom.com>
1464
1465 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1466 indicating that ALU32_END or ALU64_END are there to check
1467 for overflow.
1468 (DADD): Likewise, but also remove previous comment about
1469 overflow checking.
1470
f701dad2
CD		 14712002-02-10 Chris Demetriou <cgd@broadcom.com>
1472
1473 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1474 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1475 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1476 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1477 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1478 fields (i.e., add and move commas) so that they more closely
1479 match the MIPS ISA documentation opcode partitioning.
1480
14812002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1482
72f4393d
L		 1483 * mips.igen (ADDI): Print immediate value.
1484 (BREAK): Print code.
1485 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1486 (SLL): Print "nop" specially, and don't run the code
1487 that does the shift for the "nop" case.
20ae0098 1488
9e52972e
FF		 14892001-11-17 Fred Fish <fnf@redhat.com>
1490
1491 * sim-main.h (float_operation): Move enum declaration outside
1492 of _sim_cpu struct declaration.
1493
c0efbca4
JB		 14942001-04-12 Jim Blandy <jimb@redhat.com>
1495
1496 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1497 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1498 set of the FCSR.
1499 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1500 PENDING_FILL, and you can get the intended effect gracefully by
1501 calling PENDING_SCHED directly.
1502
fb891446
BE		 15032001-02-23 Ben Elliston <bje@redhat.com>
1504
1505 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1506 already defined elsewhere.
1507
8030f857
BE		 15082001-02-19 Ben Elliston <bje@redhat.com>
1509
1510 * sim-main.h (sim_monitor): Return an int.
1511 * interp.c (sim_monitor): Add return values.
1512 (signal_exception): Handle error conditions from sim_monitor.
1513
56b48a7a
CD		 15142001-02-08 Ben Elliston <bje@redhat.com>
1515
1516 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1517 (store_memory): Likewise, pass cia to sim_core_write*.
1518
d3ee60d9
FCE		 15192000-10-19 Frank Ch. Eigler <fche@redhat.com>
1520
1521 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1522 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1523
071da002
AC		 1524Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1525
1526 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1527 * Makefile.in: Don't delete *.igen when cleaning directory.
1528
a28c02cd
AC		 1529Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1530
1531 * m16.igen (break): Call SignalException not sim_engine_halt.
1532
80ee11fa
AC		 1533Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1534
1535 From Jason Eckhardt:
1536 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1537
673388c0
AC		 1538Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1539
1540 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1541
4c0deff4
NC		 15422000-05-24 Michael Hayes <mhayes@cygnus.com>
1543
1544 * mips.igen (do_dmultx): Fix typo.
1545
eb2d80b4
AC		 1546Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * configure: Regenerated to track ../common/aclocal.m4 changes.
1549
dd37a34b
AC		 1550Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1551
1552 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1553
4c0deff4
NC		 15542000-04-12 Frank Ch. Eigler <fche@redhat.com>
1555
1556 * sim-main.h (GPR_CLEAR): Define macro.
1557
e30db738
AC		 1558Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * interp.c (decode_coproc): Output long using %lx and not %s.
1561
cb7450ea
FCE		 15622000-03-21 Frank Ch. Eigler <fche@redhat.com>
1563
1564 * interp.c (sim_open): Sort & extend dummy memory regions for
1565 --board=jmr3904 for eCos.
1566
a3027dd7
FCE		 15672000-03-02 Frank Ch. Eigler <fche@redhat.com>
1568
1569 * configure: Regenerated.
1570
1571Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1572
1573 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1574 calls, conditional on the simulator being in verbose mode.
1575
dfcd3bfb
JM		 1576Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1577
1578 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1579 cache don't get ReservedInstruction traps.
1580
c2d11a7d
JM		 15811999-11-29 Mark Salter <msalter@cygnus.com>
1582
1583 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1584 to clear status bits in sdisr register. This is how the hardware works.
1585
1586 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1587 being used by cygmon.
1588
4ce44c66
JM		 15891999-11-11 Andrew Haley <aph@cygnus.com>
1590
1591 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1592 instructions.
1593
cff3e48b
JM		 1594Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1595
1596 * mips.igen (MULT): Correct previous mis-applied patch.
1597
d4f3574e
SS		 1598Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1599
1600 * mips.igen (delayslot32): Handle sequence like
1601 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1602 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1603 (MULT): Actually pass the third register...
1604
16051999-09-03 Mark Salter <msalter@cygnus.com>
1606
1607 * interp.c (sim_open): Added more memory aliases for additional
1608 hardware being touched by cygmon on jmr3904 board.
1609
1610Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1611
1612 * configure: Regenerated to track ../common/aclocal.m4 changes.
1613
a0b3c4fd
JM		 1614Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1615
1616 * interp.c (sim_store_register): Handle case where client - GDB -
1617 specifies that a 4 byte register is 8 bytes in size.
1618 (sim_fetch_register): Ditto.
72f4393d 1619
adf40b2e
JM		 16201999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1621
1622 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1623 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1624 (idt_monitor_base): Base address for IDT monitor traps.
1625 (pmon_monitor_base): Ditto for PMON.
1626 (lsipmon_monitor_base): Ditto for LSI PMON.
1627 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1628 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1629 (sim_firmware_command): New function.
1630 (mips_option_handler): Call it for OPTION_FIRMWARE.
1631 (sim_open): Allocate memory for idt_monitor region. If "--board"
1632 option was given, add no monitor by default. Add BREAK hooks only if
1633 monitors are also there.
72f4393d 1634
43e526b9
JM		 1635Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1636
1637 * interp.c (sim_monitor): Flush output before reading input.
1638
1639Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1640
1641 * tconfig.in (SIM_HANDLES_LMA): Always define.
1642
1643Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1644
1645 From Mark Salter <msalter@cygnus.com>:
1646 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1647 (sim_open): Add setup for BSP board.
1648
9846de1b
JM		 1649Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1652 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1653 them as unimplemented.
1654
cd0fc7c3
SS		 16551999-05-08 Felix Lee <flee@cygnus.com>
1656
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1658
7a292a7a
SS		 16591999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1660
1661 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1662
1663Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1664
1665 * configure.in: Any mips64vr5*-*-* target should have
1666 -DTARGET_ENABLE_FR=1.
1667 (default_endian): Any mips64vr*el-*-* target should default to
1668 LITTLE_ENDIAN.
1669 * configure: Re-generate.
1670
16711999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1672
1673 * mips.igen (ldl): Extend from _16_, not 32.
1674
1675Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1676
1677 * interp.c (sim_store_register): Force registers written to by GDB
1678 into an un-interpreted state.
1679
c906108c
SS		 16801999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1681
1682 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1683 CPU, start periodic background I/O polls.
72f4393d 1684 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1685
16861998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1687
1688 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1689
c906108c
SS		 1690Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1691
1692 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1693 case statement.
1694
16951998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1696
1697 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1698 (load_word): Call SIM_CORE_SIGNAL hook on error.
1699 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1700 starting. For exception dispatching, pass PC instead of NULL_CIA.
1701 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1702 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1703 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1704 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1705 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1706 * mips.igen (*): Replace memory-related SignalException* calls
1707 with references to SIM_CORE_SIGNAL hook.
72f4393d 1708
c906108c
SS		 1709 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1710 fix.
1711 * sim-main.c (*): Minor warning cleanups.
72f4393d 1712
c906108c
SS		 17131998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1714
1715 * m16.igen (DADDIU5): Correct type-o.
1716
1717Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1718
1719 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1720 variables.
1721
1722Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1723
1724 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1725 to include path.
1726 (interp.o): Add dependency on itable.h
1727 (oengine.c, gencode): Delete remaining references.
1728 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1729
c906108c 17301998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1731
c906108c
SS		 1732 * vr4run.c: New.
1733 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1734 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1735 tmp-run-hack) : New.
1736 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1737 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1738 Drop the "64" qualifier to get the HACK generator working.
1739 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1740 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1741 qualifier to get the hack generator working.
1742 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1743 (DSLL): Use do_dsll.
1744 (DSLLV): Use do_dsllv.
1745 (DSRA): Use do_dsra.
1746 (DSRL): Use do_dsrl.
1747 (DSRLV): Use do_dsrlv.
1748 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1749 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1750 get the HACK generator working.
1751 (MACC) Rename to get the HACK generator working.
1752 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1753
c906108c
SS		 17541998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1755
1756 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1757 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1758
c906108c
SS		 17591998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1760
1761 * mips/interp.c (DEBUG): Cleanups.
1762
17631998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1764
1765 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1766 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1767
c906108c
SS		 17681998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1769
1770 * interp.c (sim_close): Uninstall modules.
1771
1772Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1773
1774 * sim-main.h, interp.c (sim_monitor): Change to global
1775 function.
1776
1777Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1778
1779 * configure.in (vr4100): Only include vr4100 instructions in
1780 simulator.
1781 * configure: Re-generate.
1782 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1783
1784Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1785
1786 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1787 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1788 true alternative.
1789
1790 * configure.in (sim_default_gen, sim_use_gen): Replace with
1791 sim_gen.
1792 (--enable-sim-igen): Delete config option. Always using IGEN.
1793 * configure: Re-generate.
72f4393d 1794
c906108c
SS		 1795 * Makefile.in (gencode): Kill, kill, kill.
1796 * gencode.c: Ditto.
72f4393d 1797
c906108c
SS		 1798Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1799
1800 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1801 bit mips16 igen simulator.
1802 * configure: Re-generate.
1803
1804 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1805 as part of vr4100 ISA.
1806 * vr.igen: Mark all instructions as 64 bit only.
1807
1808Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1809
1810 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1811 Pacify GCC.
1812
1813Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1814
1815 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1816 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1817 * configure: Re-generate.
1818
1819 * m16.igen (BREAK): Define breakpoint instruction.
1820 (JALX32): Mark instruction as mips16 and not r3900.
1821 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1822
1823 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1824
1825Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1826
1827 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1828 insn as a debug breakpoint.
1829
1830 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1831 pending.slot_size.
1832 (PENDING_SCHED): Clean up trace statement.
1833 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1834 (PENDING_FILL): Delay write by only one cycle.
1835 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1836
1837 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1838 of pending writes.
1839 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1840 32 & 64.
1841 (pending_tick): Move incrementing of index to FOR statement.
1842 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1843
c906108c
SS		 1844 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1845 build simulator.
1846 * configure: Re-generate.
72f4393d 1847
c906108c
SS		 1848 * interp.c (sim_engine_run OLD): Delete explicit call to
1849 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1850
c906108c
SS		 1851Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1852
1853 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1854 interrupt level number to match changed SignalExceptionInterrupt
1855 macro.
1856
1857Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1858
1859 * interp.c: #include "itable.h" if WITH_IGEN.
1860 (get_insn_name): New function.
1861 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1862 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1863
1864Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1865
1866 * configure: Rebuilt to inhale new common/aclocal.m4.
1867
1868Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1869
1870 * dv-tx3904sio.c: Include sim-assert.h.
1871
1872Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1873
1874 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1875 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1876 Reorganize target-specific sim-hardware checks.
1877 * configure: rebuilt.
1878 * interp.c (sim_open): For tx39 target boards, set
1879 OPERATING_ENVIRONMENT, add tx3904sio devices.
1880 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1881 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1882
c906108c
SS		 1883 * dv-tx3904irc.c: Compiler warning clean-up.
1884 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1885 frequent hw-trace messages.
1886
1887Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1888
1889 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1890
1891Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1892
1893 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1894
1895 * vr.igen: New file.
1896 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1897 * mips.igen: Define vr4100 model. Include vr.igen.
1898Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1899
1900 * mips.igen (check_mf_hilo): Correct check.
1901
1902Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1903
1904 * sim-main.h (interrupt_event): Add prototype.
1905
1906 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1907 register_ptr, register_value.
1908 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1909
1910 * sim-main.h (tracefh): Make extern.
1911
1912Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1913
1914 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1915 Reduce unnecessarily high timer event frequency.
c906108c 1916 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1917
c906108c
SS		 1918Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1919
1920 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1921 to allay warnings.
1922 (interrupt_event): Made non-static.
72f4393d 1923
c906108c
SS		 1924 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1925 interchange of configuration values for external vs. internal
1926 clock dividers.
72f4393d 1927
c906108c
SS		 1928Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1929
72f4393d 1930 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1931 simulator-reserved break instructions.
1932 * gencode.c (build_instruction): Ditto.
1933 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1934 reserved instructions now use exception vector, rather
c906108c
SS		 1935 than halting sim.
1936 * sim-main.h: Moved magic constants to here.
1937
1938Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1939
1940 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1941 register upon non-zero interrupt event level, clear upon zero
1942 event value.
1943 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1944 by passing zero event value.
1945 (*_io_{read,write}_buffer): Endianness fixes.
1946 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1947 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1948
1949 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1950 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1951
c906108c
SS		 1952Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1953
72f4393d 1954 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1955 and BigEndianCPU.
1956
1957Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1958
1959 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1960 parts.
1961 * configure: Update.
1962
1963Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1964
1965 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1966 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1967 * configure.in: Include tx3904tmr in hw_device list.
1968 * configure: Rebuilt.
1969 * interp.c (sim_open): Instantiate three timer instances.
1970 Fix address typo of tx3904irc instance.
1971
1972Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1973
1974 * interp.c (signal_exception): SystemCall exception now uses
1975 the exception vector.
1976
1977Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1978
1979 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1980 to allay warnings.
1981
1982Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1983
1984 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1985
1986Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1987
1988 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1989
1990 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1991 sim-main.h. Declare a struct hw_descriptor instead of struct
1992 hw_device_descriptor.
1993
1994Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1995
1996 * mips.igen (do_store_left, do_load_left): Compute nr of left and
1997 right bits and then re-align left hand bytes to correct byte
1998 lanes. Fix incorrect computation in do_store_left when loading
1999 bytes from second word.
2000
2001Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2002
2003 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2004 * interp.c (sim_open): Only create a device tree when HW is
2005 enabled.
2006
2007 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2008 * interp.c (signal_exception): Ditto.
2009
2010Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2011
2012 * gencode.c: Mark BEGEZALL as LIKELY.
2013
2014Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2015
2016 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2017 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2018
c906108c
SS		 2019Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2020
2021 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2022 modules. Recognize TX39 target with "mips*tx39" pattern.
2023 * configure: Rebuilt.
2024 * sim-main.h (*): Added many macros defining bits in
2025 TX39 control registers.
2026 (SignalInterrupt): Send actual PC instead of NULL.
2027 (SignalNMIReset): New exception type.
2028 * interp.c (board): New variable for future use to identify
2029 a particular board being simulated.
2030 (mips_option_handler,mips_options): Added "--board" option.
2031 (interrupt_event): Send actual PC.
2032 (sim_open): Make memory layout conditional on board setting.
2033 (signal_exception): Initial implementation of hardware interrupt
2034 handling. Accept another break instruction variant for simulator
2035 exit.
2036 (decode_coproc): Implement RFE instruction for TX39.
2037 (mips.igen): Decode RFE instruction as such.
2038 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2039 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2040 bbegin to implement memory map.
2041 * dv-tx3904cpu.c: New file.
2042 * dv-tx3904irc.c: New file.
2043
2044Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2045
2046 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2047
2048Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2049
2050 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2051 with calls to check_div_hilo.
2052
2053Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2054
2055 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2056 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2057 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2058 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2059 with calls to check_mult_hilo.
2060 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2061 with calls to check_div_hilo.
2062
2063Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2064
2065 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2066 Document a replacement.
2067
2068Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2069
2070 * interp.c (sim_monitor): Make mon_printf work.
2071
2072Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2073
2074 * sim-main.h (INSN_NAME): New arg `cpu'.
2075
2076Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2077
72f4393d 2078 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2079
2080Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2081
2082 * configure: Regenerated to track ../common/aclocal.m4 changes.
2083 * config.in: Ditto.
2084
2085Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2086
2087 * acconfig.h: New file.
2088 * configure.in: Reverted change of Apr 24; use sinclude again.
2089
2090Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2091
2092 * configure: Regenerated to track ../common/aclocal.m4 changes.
2093 * config.in: Ditto.
2094
2095Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2096
2097 * configure.in: Don't call sinclude.
2098
2099Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2100
2101 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2102
2103Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2104
2105 * mips.igen (ERET): Implement.
2106
2107 * interp.c (decode_coproc): Return sign-extended EPC.
2108
2109 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2110
2111 * interp.c (signal_exception): Do not ignore Trap.
2112 (signal_exception): On TRAP, restart at exception address.
2113 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2114 (signal_exception): Update.
2115 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2116 so that TRAP instructions are caught.
2117
2118Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2119
2120 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2121 contains HI/LO access history.
2122 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2123 (HIACCESS, LOACCESS): Delete, replace with
2124 (HIHISTORY, LOHISTORY): New macros.
2125 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2126
c906108c
SS		 2127 * gencode.c (build_instruction): Do not generate checks for
2128 correct HI/LO register usage.
2129
2130 * interp.c (old_engine_run): Delete checks for correct HI/LO
2131 register usage.
2132
2133 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2134 check_mf_cycles): New functions.
2135 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2136 do_divu, domultx, do_mult, do_multu): Use.
2137
2138 * tx.igen ("madd", "maddu"): Use.
72f4393d 2139
c906108c
SS		 2140Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2141
2142 * mips.igen (DSRAV): Use function do_dsrav.
2143 (SRAV): Use new function do_srav.
2144
2145 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2146 (B): Sign extend 11 bit immediate.
2147 (EXT-B*): Shift 16 bit immediate left by 1.
2148 (ADDIU*): Don't sign extend immediate value.
2149
2150Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2151
2152 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2153
2154 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2155 functions.
2156
2157 * mips.igen (delayslot32, nullify_next_insn): New functions.
2158 (m16.igen): Always include.
2159 (do_*): Add more tracing.
2160
2161 * m16.igen (delayslot16): Add NIA argument, could be called by a
2162 32 bit MIPS16 instruction.
72f4393d 2163
c906108c
SS		 2164 * interp.c (ifetch16): Move function from here.
2165 * sim-main.c (ifetch16): To here.
72f4393d 2166
c906108c
SS		 2167 * sim-main.c (ifetch16, ifetch32): Update to match current
2168 implementations of LH, LW.
2169 (signal_exception): Don't print out incorrect hex value of illegal
2170 instruction.
2171
2172Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2173
2174 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2175 instruction.
2176
2177 * m16.igen: Implement MIPS16 instructions.
72f4393d 2178
c906108c
SS		 2179 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2180 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2181 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2182 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2183 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2184 bodies of corresponding code from 32 bit insn to these. Also used
2185 by MIPS16 versions of functions.
72f4393d 2186
c906108c
SS		 2187 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2188 (IMEM16): Drop NR argument from macro.
2189
2190Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2191
2192 * Makefile.in (SIM_OBJS): Add sim-main.o.
2193
2194 * sim-main.h (address_translation, load_memory, store_memory,
2195 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2196 as INLINE_SIM_MAIN.
2197 (pr_addr, pr_uword64): Declare.
2198 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2199
c906108c
SS		 2200 * interp.c (address_translation, load_memory, store_memory,
2201 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2202 from here.
2203 * sim-main.c: To here. Fix compilation problems.
72f4393d 2204
c906108c
SS		 2205 * configure.in: Enable inlining.
2206 * configure: Re-config.
2207
2208Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2209
2210 * configure: Regenerated to track ../common/aclocal.m4 changes.
2211
2212Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2213
2214 * mips.igen: Include tx.igen.
2215 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2216 * tx.igen: New file, contains MADD and MADDU.
2217
2218 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2219 the hardwired constant `7'.
2220 (store_memory): Ditto.
2221 (LOADDRMASK): Move definition to sim-main.h.
2222
2223 mips.igen (MTC0): Enable for r3900.
2224 (ADDU): Add trace.
2225
2226 mips.igen (do_load_byte): Delete.
2227 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2228 do_store_right): New functions.
2229 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2230
2231 configure.in: Let the tx39 use igen again.
2232 configure: Update.
72f4393d 2233
c906108c
SS		 2234Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2235
2236 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2237 not an address sized quantity. Return zero for cache sizes.
2238
2239Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2240
2241 * mips.igen (r3900): r3900 does not support 64 bit integer
2242 operations.
2243
2244Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2245
2246 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2247 than igen one.
2248 * configure : Rebuild.
72f4393d 2249
c906108c
SS		 2250Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2251
2252 * configure: Regenerated to track ../common/aclocal.m4 changes.
2253
2254Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2255
2256 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2257
2258Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2259
2260 * configure: Regenerated to track ../common/aclocal.m4 changes.
2261 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2262
2263Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2264
2265 * configure: Regenerated to track ../common/aclocal.m4 changes.
2266
2267Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2268
2269 * interp.c (Max, Min): Comment out functions. Not yet used.
2270
2271Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * configure: Regenerated to track ../common/aclocal.m4 changes.
2274
2275Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2276
2277 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2278 configurable settings for stand-alone simulator.
72f4393d 2279
c906108c 2280 * configure.in: Added X11 search, just in case.
72f4393d 2281
c906108c
SS		 2282 * configure: Regenerated.
2283
2284Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2285
2286 * interp.c (sim_write, sim_read, load_memory, store_memory):
2287 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2288
2289Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2290
2291 * sim-main.h (GETFCC): Return an unsigned value.
2292
2293Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2294
2295 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2296 (DADD): Result destination is RD not RT.
2297
2298Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2299
2300 * sim-main.h (HIACCESS, LOACCESS): Always define.
2301
2302 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2303
2304 * interp.c (sim_info): Delete.
2305
2306Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2307
2308 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2309 (mips_option_handler): New argument `cpu'.
2310 (sim_open): Update call to sim_add_option_table.
2311
2312Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2313
2314 * mips.igen (CxC1): Add tracing.
2315
2316Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2317
2318 * sim-main.h (Max, Min): Declare.
2319
2320 * interp.c (Max, Min): New functions.
2321
2322 * mips.igen (BC1): Add tracing.
72f4393d 2323
c906108c 2324Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2325
c906108c 2326 * interp.c Added memory map for stack in vr4100
72f4393d 2327
c906108c
SS		 2328Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2329
2330 * interp.c (load_memory): Add missing "break"'s.
2331
2332Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * interp.c (sim_store_register, sim_fetch_register): Pass in
2335 length parameter. Return -1.
2336
2337Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2338
2339 * interp.c: Added hardware init hook, fixed warnings.
2340
2341Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2342
2343 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2344
2345Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2346
2347 * interp.c (ifetch16): New function.
2348
2349 * sim-main.h (IMEM32): Rename IMEM.
2350 (IMEM16_IMMED): Define.
2351 (IMEM16): Define.
2352 (DELAY_SLOT): Update.
72f4393d 2353
c906108c 2354 * m16run.c (sim_engine_run): New file.
72f4393d 2355
c906108c
SS		 2356 * m16.igen: All instructions except LB.
2357 (LB): Call do_load_byte.
2358 * mips.igen (do_load_byte): New function.
2359 (LB): Call do_load_byte.
2360
2361 * mips.igen: Move spec for insn bit size and high bit from here.
2362 * Makefile.in (tmp-igen, tmp-m16): To here.
2363
2364 * m16.dc: New file, decode mips16 instructions.
2365
2366 * Makefile.in (SIM_NO_ALL): Define.
2367 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2368
2369Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2370
2371 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2372 point unit to 32 bit registers.
2373 * configure: Re-generate.
2374
2375Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2376
2377 * configure.in (sim_use_gen): Make IGEN the default simulator
2378 generator for generic 32 and 64 bit mips targets.
2379 * configure: Re-generate.
2380
2381Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2382
2383 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2384 bitsize.
2385
2386 * interp.c (sim_fetch_register, sim_store_register): Read/write
2387 FGR from correct location.
2388 (sim_open): Set size of FGR's according to
2389 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2390
c906108c
SS		 2391 * sim-main.h (FGR): Store floating point registers in a separate
2392 array.
2393
2394Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2395
2396 * configure: Regenerated to track ../common/aclocal.m4 changes.
2397
2398Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2399
2400 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2401
2402 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2403
2404 * interp.c (pending_tick): New function. Deliver pending writes.
2405
2406 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2407 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2408 it can handle mixed sized quantites and single bits.
72f4393d 2409
c906108c
SS		 2410Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2411
2412 * interp.c (oengine.h): Do not include when building with IGEN.
2413 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2414 (sim_info): Ditto for PROCESSOR_64BIT.
2415 (sim_monitor): Replace ut_reg with unsigned_word.
2416 (*): Ditto for t_reg.
2417 (LOADDRMASK): Define.
2418 (sim_open): Remove defunct check that host FP is IEEE compliant,
2419 using software to emulate floating point.
2420 (value_fpr, ...): Always compile, was conditional on HASFPU.
2421
2422Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2423
2424 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2425 size.
2426
2427 * interp.c (SD, CPU): Define.
2428 (mips_option_handler): Set flags in each CPU.
2429 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2430 (sim_close): Do not clear STATE, deleted anyway.
2431 (sim_write, sim_read): Assume CPU zero's vm should be used for
2432 data transfers.
2433 (sim_create_inferior): Set the PC for all processors.
2434 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2435 argument.
2436 (mips16_entry): Pass correct nr of args to store_word, load_word.
2437 (ColdReset): Cold reset all cpu's.
2438 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2439 (sim_monitor, load_memory, store_memory, signal_exception): Use
2440 `CPU' instead of STATE_CPU.
2441
2442
2443 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2444 SD or CPU_.
72f4393d 2445
c906108c
SS		 2446 * sim-main.h (signal_exception): Add sim_cpu arg.
2447 (SignalException*): Pass both SD and CPU to signal_exception.
2448 * interp.c (signal_exception): Update.
72f4393d 2449
c906108c
SS		 2450 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2451 Ditto
2452 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2453 address_translation): Ditto
2454 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2455
c906108c
SS		 2456Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2457
2458 * configure: Regenerated to track ../common/aclocal.m4 changes.
2459
2460Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2461
2462 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2463
72f4393d 2464 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2465
2466 * sim-main.h (CPU_CIA): Delete.
2467 (SET_CIA, GET_CIA): Define
2468
2469Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2470
2471 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2472 regiser.
2473
2474 * configure.in (default_endian): Configure a big-endian simulator
2475 by default.
2476 * configure: Re-generate.
72f4393d 2477
c906108c
SS		 2478Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2479
2480 * configure: Regenerated to track ../common/aclocal.m4 changes.
2481
2482Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2483
2484 * interp.c (sim_monitor): Handle Densan monitor outbyte
2485 and inbyte functions.
2486
24871997-12-29 Felix Lee <flee@cygnus.com>
2488
2489 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2490
2491Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2492
2493 * Makefile.in (tmp-igen): Arrange for $zero to always be
2494 reset to zero after every instruction.
2495
2496Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2497
2498 * configure: Regenerated to track ../common/aclocal.m4 changes.
2499 * config.in: Ditto.
2500
2501Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2502
2503 * mips.igen (MSUB): Fix to work like MADD.
2504 * gencode.c (MSUB): Similarly.
2505
2506Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2507
2508 * configure: Regenerated to track ../common/aclocal.m4 changes.
2509
2510Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2511
2512 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2513
2514Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2515
2516 * sim-main.h (sim-fpu.h): Include.
2517
2518 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2519 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2520 using host independant sim_fpu module.
2521
2522Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2523
2524 * interp.c (signal_exception): Report internal errors with SIGABRT
2525 not SIGQUIT.
2526
2527 * sim-main.h (C0_CONFIG): New register.
2528 (signal.h): No longer include.
2529
2530 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2531
2532Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2533
2534 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2535
2536Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2537
2538 * mips.igen: Tag vr5000 instructions.
2539 (ANDI): Was missing mipsIV model, fix assembler syntax.
2540 (do_c_cond_fmt): New function.
2541 (C.cond.fmt): Handle mips I-III which do not support CC field
2542 separatly.
2543 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2544 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2545 in IV3.2 spec.
2546 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2547 vr5000 which saves LO in a GPR separatly.
72f4393d 2548
c906108c
SS		 2549 * configure.in (enable-sim-igen): For vr5000, select vr5000
2550 specific instructions.
2551 * configure: Re-generate.
72f4393d 2552
c906108c
SS		 2553Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2554
2555 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2556
2557 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2558 fmt_uninterpreted_64 bit cases to switch. Convert to
2559 fmt_formatted,
2560
2561 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2562
2563 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2564 as specified in IV3.2 spec.
2565 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2566
2567Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2568
2569 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2570 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2571 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2572 PENDING_FILL versions of instructions. Simplify.
2573 (X): New function.
2574 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2575 instructions.
2576 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2577 a signed value.
2578 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2579
c906108c
SS		 2580 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2581 global.
2582 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2583
2584Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2585
2586 * gencode.c (build_mips16_operands): Replace IPC with cia.
2587
2588 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2589 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2590 IPC to `cia'.
2591 (UndefinedResult): Replace function with macro/function
2592 combination.
2593 (sim_engine_run): Don't save PC in IPC.
2594
2595 * sim-main.h (IPC): Delete.
2596
2597
2598 * interp.c (signal_exception, store_word, load_word,
2599 address_translation, load_memory, store_memory, cache_op,
2600 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2601 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2602 current instruction address - cia - argument.
2603 (sim_read, sim_write): Call address_translation directly.
2604 (sim_engine_run): Rename variable vaddr to cia.
2605 (signal_exception): Pass cia to sim_monitor
72f4393d 2606
c906108c
SS		 2607 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2608 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2609 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2610
2611 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2612 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2613 SIM_ASSERT.
72f4393d 2614
c906108c
SS		 2615 * interp.c (signal_exception): Pass restart address to
2616 sim_engine_restart.
2617
2618 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2619 idecode.o): Add dependency.
2620
2621 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2622 Delete definitions
2623 (DELAY_SLOT): Update NIA not PC with branch address.
2624 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2625
2626 * mips.igen: Use CIA not PC in branch calculations.
2627 (illegal): Call SignalException.
2628 (BEQ, ADDIU): Fix assembler.
2629
2630Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2631
2632 * m16.igen (JALX): Was missing.
2633
2634 * configure.in (enable-sim-igen): New configuration option.
2635 * configure: Re-generate.
72f4393d 2636
c906108c
SS		 2637 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2638
2639 * interp.c (load_memory, store_memory): Delete parameter RAW.
2640 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2641 bypassing {load,store}_memory.
2642
2643 * sim-main.h (ByteSwapMem): Delete definition.
2644
2645 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2646
2647 * interp.c (sim_do_command, sim_commands): Delete mips specific
2648 commands. Handled by module sim-options.
72f4393d 2649
c906108c
SS		 2650 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2651 (WITH_MODULO_MEMORY): Define.
2652
2653 * interp.c (sim_info): Delete code printing memory size.
2654
2655 * interp.c (mips_size): Nee sim_size, delete function.
2656 (power2): Delete.
2657 (monitor, monitor_base, monitor_size): Delete global variables.
2658 (sim_open, sim_close): Delete code creating monitor and other
2659 memory regions. Use sim-memopts module, via sim_do_commandf, to
2660 manage memory regions.
2661 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2662
c906108c
SS		 2663 * interp.c (address_translation): Delete all memory map code
2664 except line forcing 32 bit addresses.
2665
2666Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2667
2668 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2669 trace options.
2670
2671 * interp.c (logfh, logfile): Delete globals.
2672 (sim_open, sim_close): Delete code opening & closing log file.
2673 (mips_option_handler): Delete -l and -n options.
2674 (OPTION mips_options): Ditto.
2675
2676 * interp.c (OPTION mips_options): Rename option trace to dinero.
2677 (mips_option_handler): Update.
2678
2679Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2680
2681 * interp.c (fetch_str): New function.
2682 (sim_monitor): Rewrite using sim_read & sim_write.
2683 (sim_open): Check magic number.
2684 (sim_open): Write monitor vectors into memory using sim_write.
2685 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2686 (sim_read, sim_write): Simplify - transfer data one byte at a
2687 time.
2688 (load_memory, store_memory): Clarify meaning of parameter RAW.
2689
2690 * sim-main.h (isHOST): Defete definition.
2691 (isTARGET): Mark as depreciated.
2692 (address_translation): Delete parameter HOST.
2693
2694 * interp.c (address_translation): Delete parameter HOST.
2695
2696Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2697
72f4393d 2698 * mips.igen:
c906108c
SS		 2699
2700 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2701 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2702
2703Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2704
2705 * mips.igen: Add model filter field to records.
2706
2707Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2708
2709 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2710
c906108c
SS		 2711 interp.c (sim_engine_run): Do not compile function sim_engine_run
2712 when WITH_IGEN == 1.
2713
2714 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2715 target architecture.
2716
2717 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2718 igen. Replace with configuration variables sim_igen_flags /
2719 sim_m16_flags.
2720
2721 * m16.igen: New file. Copy mips16 insns here.
2722 * mips.igen: From here.
2723
2724Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725
2726 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2727 to top.
2728 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2729
2730Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2731
2732 * gencode.c (build_instruction): Follow sim_write's lead in using
2733 BigEndianMem instead of !ByteSwapMem.
2734
2735Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2736
2737 * configure.in (sim_gen): Dependent on target, select type of
2738 generator. Always select old style generator.
2739
2740 configure: Re-generate.
2741
2742 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2743 targets.
2744 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2745 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2746 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2747 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2748 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2749
c906108c
SS		 2750Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2751
2752 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2753
2754 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2755 CURRENT_FLOATING_POINT instead.
2756
2757 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2758 (address_translation): Raise exception InstructionFetch when
2759 translation fails and isINSTRUCTION.
72f4393d 2760
c906108c
SS		 2761 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2762 sim_engine_run): Change type of of vaddr and paddr to
2763 address_word.
2764 (address_translation, prefetch, load_memory, store_memory,
2765 cache_op): Change type of vAddr and pAddr to address_word.
2766
2767 * gencode.c (build_instruction): Change type of vaddr and paddr to
2768 address_word.
2769
2770Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2771
2772 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2773 macro to obtain result of ALU op.
2774
2775Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2776
2777 * interp.c (sim_info): Call profile_print.
2778
2779Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2780
2781 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2782
2783 * sim-main.h (WITH_PROFILE): Do not define, defined in
2784 common/sim-config.h. Use sim-profile module.
2785 (simPROFILE): Delete defintion.
2786
2787 * interp.c (PROFILE): Delete definition.
2788 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2789 (sim_close): Delete code writing profile histogram.
2790 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2791 Delete.
2792 (sim_engine_run): Delete code profiling the PC.
2793
2794Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2795
2796 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2797
2798 * interp.c (sim_monitor): Make register pointers of type
2799 unsigned_word*.
2800
2801 * sim-main.h: Make registers of type unsigned_word not
2802 signed_word.
2803
2804Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2805
2806 * interp.c (sync_operation): Rename from SyncOperation, make
2807 global, add SD argument.
2808 (prefetch): Rename from Prefetch, make global, add SD argument.
2809 (decode_coproc): Make global.
2810
2811 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2812
2813 * gencode.c (build_instruction): Generate DecodeCoproc not
2814 decode_coproc calls.
2815
2816 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2817 (SizeFGR): Move to sim-main.h
2818 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2819 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2820 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2821 sim-main.h.
2822 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2823 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2824 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2825 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2826 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2827 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2828
c906108c
SS		 2829 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2830 exception.
2831 (sim-alu.h): Include.
2832 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2833 (sim_cia): Typedef to instruction_address.
72f4393d 2834
c906108c
SS		 2835Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2836
2837 * Makefile.in (interp.o): Rename generated file engine.c to
2838 oengine.c.
72f4393d 2839
c906108c 2840 * interp.c: Update.
72f4393d 2841
c906108c
SS		 2842Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2843
2844 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2845
c906108c
SS		 2846Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2847
2848 * gencode.c (build_instruction): For "FPSQRT", output correct
2849 number of arguments to Recip.
72f4393d 2850
c906108c
SS		 2851Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2852
2853 * Makefile.in (interp.o): Depends on sim-main.h
2854
2855 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2856
2857 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2858 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2859 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2860 STATE, DSSTATE): Define
2861 (GPR, FGRIDX, ..): Define.
2862
2863 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2864 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2865 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2866
c906108c 2867 * interp.c: Update names to match defines from sim-main.h
72f4393d 2868
c906108c
SS		 2869Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2870
2871 * interp.c (sim_monitor): Add SD argument.
2872 (sim_warning): Delete. Replace calls with calls to
2873 sim_io_eprintf.
2874 (sim_error): Delete. Replace calls with sim_io_error.
2875 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2876 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2877 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2878 argument.
2879 (mips_size): Rename from sim_size. Add SD argument.
2880
2881 * interp.c (simulator): Delete global variable.
2882 (callback): Delete global variable.
2883 (mips_option_handler, sim_open, sim_write, sim_read,
2884 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2885 sim_size,sim_monitor): Use sim_io_* not callback->*.
2886 (sim_open): ZALLOC simulator struct.
2887 (PROFILE): Do not define.
2888
2889Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2890
2891 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2892 support.h with corresponding code.
2893
2894 * sim-main.h (word64, uword64), support.h: Move definition to
2895 sim-main.h.
2896 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2897
2898 * support.h: Delete
2899 * Makefile.in: Update dependencies
2900 * interp.c: Do not include.
72f4393d 2901
c906108c
SS		 2902Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2903
2904 * interp.c (address_translation, load_memory, store_memory,
2905 cache_op): Rename to from AddressTranslation et.al., make global,
2906 add SD argument
72f4393d 2907
c906108c
SS		 2908 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2909 CacheOp): Define.
72f4393d 2910
c906108c
SS		 2911 * interp.c (SignalException): Rename to signal_exception, make
2912 global.
2913
2914 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2915
c906108c
SS		 2916 * sim-main.h (SignalException, SignalExceptionInterrupt,
2917 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2918 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2919 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2920 Define.
72f4393d 2921
c906108c 2922 * interp.c, support.h: Use.
72f4393d 2923
c906108c
SS		 2924Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2925
2926 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2927 to value_fpr / store_fpr. Add SD argument.
2928 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2929 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2930
2931 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2932
c906108c
SS		 2933Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2934
2935 * interp.c (sim_engine_run): Check consistency between configure
2936 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2937 and HASFPU.
2938
2939 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2940 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2941 (mips_endian): Configure WITH_TARGET_ENDIAN.
2942 * configure: Update.
2943
2944Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2945
2946 * configure: Regenerated to track ../common/aclocal.m4 changes.
2947
2948Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2949
2950 * configure: Regenerated.
2951
2952Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2953
2954 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2955
2956Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2957
2958 * gencode.c (print_igen_insn_models): Assume certain architectures
2959 include all mips* instructions.
2960 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2961 instruction.
2962
2963 * Makefile.in (tmp.igen): Add target. Generate igen input from
2964 gencode file.
2965
2966 * gencode.c (FEATURE_IGEN): Define.
2967 (main): Add --igen option. Generate output in igen format.
2968 (process_instructions): Format output according to igen option.
2969 (print_igen_insn_format): New function.
2970 (print_igen_insn_models): New function.
2971 (process_instructions): Only issue warnings and ignore
2972 instructions when no FEATURE_IGEN.
2973
2974Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2975
2976 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2977 MIPS targets.
2978
2979Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2980
2981 * configure: Regenerated to track ../common/aclocal.m4 changes.
2982
2983Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2984
2985 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2986 SIM_RESERVED_BITS): Delete, moved to common.
2987 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2988
c906108c
SS		 2989Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990
2991 * configure.in: Configure non-strict memory alignment.
2992 * configure: Regenerated to track ../common/aclocal.m4 changes.
2993
2994Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
2995
2996 * configure: Regenerated to track ../common/aclocal.m4 changes.
2997
2998Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
2999
3000 * gencode.c (SDBBP,DERET): Added (3900) insns.
3001 (RFE): Turn on for 3900.
3002 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3003 (dsstate): Made global.
3004 (SUBTARGET_R3900): Added.
3005 (CANCELDELAYSLOT): New.
3006 (SignalException): Ignore SystemCall rather than ignore and
3007 terminate. Add DebugBreakPoint handling.
3008 (decode_coproc): New insns RFE, DERET; and new registers Debug
3009 and DEPC protected by SUBTARGET_R3900.
3010 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3011 bits explicitly.
3012 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3013 * configure: Update.
c906108c
SS		 3014
3015Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3016
3017 * gencode.c: Add r3900 (tx39).
72f4393d 3018
c906108c
SS		 3019
3020Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3021
3022 * gencode.c (build_instruction): Don't need to subtract 4 for
3023 JALR, just 2.
3024
3025Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3026
3027 * interp.c: Correct some HASFPU problems.
3028
3029Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3030
3031 * configure: Regenerated to track ../common/aclocal.m4 changes.
3032
3033Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3034
3035 * interp.c (mips_options): Fix samples option short form, should
3036 be `x'.
3037
3038Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039
3040 * interp.c (sim_info): Enable info code. Was just returning.
3041
3042Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3043
3044 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3045 MFC0.
3046
3047Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3048
3049 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3050 constants.
3051 (build_instruction): Ditto for LL.
3052
3053Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3054
3055 * configure: Regenerated to track ../common/aclocal.m4 changes.
3056
3057Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3058
3059 * configure: Regenerated to track ../common/aclocal.m4 changes.
3060 * config.in: Ditto.
3061
3062Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3063
3064 * interp.c (sim_open): Add call to sim_analyze_program, update
3065 call to sim_config.
3066
3067Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3068
3069 * interp.c (sim_kill): Delete.
3070 (sim_create_inferior): Add ABFD argument. Set PC from same.
3071 (sim_load): Move code initializing trap handlers from here.
3072 (sim_open): To here.
3073 (sim_load): Delete, use sim-hload.c.
3074
3075 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3076
3077Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3078
3079 * configure: Regenerated to track ../common/aclocal.m4 changes.
3080 * config.in: Ditto.
3081
3082Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3083
3084 * interp.c (sim_open): Add ABFD argument.
3085 (sim_load): Move call to sim_config from here.
3086 (sim_open): To here. Check return status.
3087
3088Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3089
c906108c
SS		 3090 * gencode.c (build_instruction): Two arg MADD should
3091 not assign result to $0.
72f4393d 3092
c906108c
SS		 3093Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3094
3095 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3096 * sim/mips/configure.in: Regenerate.
3097
3098Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3099
3100 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3101 signed8, unsigned8 et.al. types.
3102
3103 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3104 hosts when selecting subreg.
3105
3106Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3107
3108 * interp.c (sim_engine_run): Reset the ZERO register to zero
3109 regardless of FEATURE_WARN_ZERO.
3110 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3111
3112Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3113
3114 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3115 (SignalException): For BreakPoints ignore any mode bits and just
3116 save the PC.
3117 (SignalException): Always set the CAUSE register.
3118
3119Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3120
3121 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3122 exception has been taken.
3123
3124 * interp.c: Implement the ERET and mt/f sr instructions.
3125
3126Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3127
3128 * interp.c (SignalException): Don't bother restarting an
3129 interrupt.
3130
3131Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3132
3133 * interp.c (SignalException): Really take an interrupt.
3134 (interrupt_event): Only deliver interrupts when enabled.
3135
3136Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3137
3138 * interp.c (sim_info): Only print info when verbose.
3139 (sim_info) Use sim_io_printf for output.
72f4393d 3140
c906108c
SS		 3141Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3142
3143 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3144 mips architectures.
3145
3146Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3147
3148 * interp.c (sim_do_command): Check for common commands if a
3149 simulator specific command fails.
3150
3151Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3152
3153 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3154 and simBE when DEBUG is defined.
3155
3156Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3157
3158 * interp.c (interrupt_event): New function. Pass exception event
3159 onto exception handler.
3160
3161 * configure.in: Check for stdlib.h.
3162 * configure: Regenerate.
3163
3164 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3165 variable declaration.
3166 (build_instruction): Initialize memval1.
3167 (build_instruction): Add UNUSED attribute to byte, bigend,
3168 reverse.
3169 (build_operands): Ditto.
3170
3171 * interp.c: Fix GCC warnings.
3172 (sim_get_quit_code): Delete.
3173
3174 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3175 * Makefile.in: Ditto.
3176 * configure: Re-generate.
72f4393d 3177
c906108c
SS		 3178 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3179
3180Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3181
3182 * interp.c (mips_option_handler): New function parse argumes using
3183 sim-options.
3184 (myname): Replace with STATE_MY_NAME.
3185 (sim_open): Delete check for host endianness - performed by
3186 sim_config.
3187 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3188 (sim_open): Move much of the initialization from here.
3189 (sim_load): To here. After the image has been loaded and
3190 endianness set.
3191 (sim_open): Move ColdReset from here.
3192 (sim_create_inferior): To here.
3193 (sim_open): Make FP check less dependant on host endianness.
3194
3195 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3196 run.
3197 * interp.c (sim_set_callbacks): Delete.
3198
3199 * interp.c (membank, membank_base, membank_size): Replace with
3200 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3201 (sim_open): Remove call to callback->init. gdb/run do this.
3202
3203 * interp.c: Update
3204
3205 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3206
3207 * interp.c (big_endian_p): Delete, replaced by
3208 current_target_byte_order.
3209
3210Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * interp.c (host_read_long, host_read_word, host_swap_word,
3213 host_swap_long): Delete. Using common sim-endian.
3214 (sim_fetch_register, sim_store_register): Use H2T.
3215 (pipeline_ticks): Delete. Handled by sim-events.
3216 (sim_info): Update.
3217 (sim_engine_run): Update.
3218
3219Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3220
3221 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3222 reason from here.
3223 (SignalException): To here. Signal using sim_engine_halt.
3224 (sim_stop_reason): Delete, moved to common.
72f4393d 3225
c906108c
SS		 3226Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3227
3228 * interp.c (sim_open): Add callback argument.
3229 (sim_set_callbacks): Delete SIM_DESC argument.
3230 (sim_size): Ditto.
3231
3232Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3233
3234 * Makefile.in (SIM_OBJS): Add common modules.
3235
3236 * interp.c (sim_set_callbacks): Also set SD callback.
3237 (set_endianness, xfer_*, swap_*): Delete.
3238 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3239 Change to functions using sim-endian macros.
3240 (control_c, sim_stop): Delete, use common version.
3241 (simulate): Convert into.
3242 (sim_engine_run): This function.
3243 (sim_resume): Delete.
72f4393d 3244
c906108c
SS		 3245 * interp.c (simulation): New variable - the simulator object.
3246 (sim_kind): Delete global - merged into simulation.
3247 (sim_load): Cleanup. Move PC assignment from here.
3248 (sim_create_inferior): To here.
3249
3250 * sim-main.h: New file.
3251 * interp.c (sim-main.h): Include.
72f4393d 3252
c906108c
SS		 3253Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3254
3255 * configure: Regenerated to track ../common/aclocal.m4 changes.
3256
3257Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3258
3259 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3260
3261Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3262
72f4393d
L		 3263 * gencode.c (build_instruction): DIV instructions: check
3264 for division by zero and integer overflow before using
c906108c
SS		 3265 host's division operation.
3266
3267Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3268
3269 * Makefile.in (SIM_OBJS): Add sim-load.o.
3270 * interp.c: #include bfd.h.
3271 (target_byte_order): Delete.
3272 (sim_kind, myname, big_endian_p): New static locals.
3273 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3274 after argument parsing. Recognize -E arg, set endianness accordingly.
3275 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3276 load file into simulator. Set PC from bfd.
3277 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3278 (set_endianness): Use big_endian_p instead of target_byte_order.
3279
3280Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3281
3282 * interp.c (sim_size): Delete prototype - conflicts with
3283 definition in remote-sim.h. Correct definition.
3284
3285Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3286
3287 * configure: Regenerated to track ../common/aclocal.m4 changes.
3288 * config.in: Ditto.
3289
3290Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3291
3292 * interp.c (sim_open): New arg `kind'.
3293
3294 * configure: Regenerated to track ../common/aclocal.m4 changes.
3295
3296Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3297
3298 * configure: Regenerated to track ../common/aclocal.m4 changes.
3299
3300Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3301
3302 * interp.c (sim_open): Set optind to 0 before calling getopt.
3303
3304Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3305
3306 * configure: Regenerated to track ../common/aclocal.m4 changes.
3307
3308Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3309
3310 * interp.c : Replace uses of pr_addr with pr_uword64
3311 where the bit length is always 64 independent of SIM_ADDR.
3312 (pr_uword64) : added.
3313
3314Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3315
3316 * configure: Re-generate.
3317
3318Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3319
3320 * configure: Regenerate to track ../common/aclocal.m4 changes.
3321
3322Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3323
3324 * interp.c (sim_open): New SIM_DESC result. Argument is now
3325 in argv form.
3326 (other sim_*): New SIM_DESC argument.
3327
3328Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3329
3330 * interp.c: Fix printing of addresses for non-64-bit targets.
3331 (pr_addr): Add function to print address based on size.
3332
3333Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3334
3335 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3336
3337Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3338
3339 * gencode.c (build_mips16_operands): Correct computation of base
3340 address for extended PC relative instruction.
3341
3342Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3343
3344 * interp.c (mips16_entry): Add support for floating point cases.
3345 (SignalException): Pass floating point cases to mips16_entry.
3346 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3347 registers.
3348 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3349 or fmt_word.
3350 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3351 and then set the state to fmt_uninterpreted.
3352 (COP_SW): Temporarily set the state to fmt_word while calling
3353 ValueFPR.
3354
3355Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3356
3357 * gencode.c (build_instruction): The high order may be set in the
3358 comparison flags at any ISA level, not just ISA 4.
3359
3360Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3361
3362 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3363 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3364 * configure.in: sinclude ../common/aclocal.m4.
3365 * configure: Regenerated.
3366
3367Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3368
3369 * configure: Rebuild after change to aclocal.m4.
3370
3371Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3372
3373 * configure configure.in Makefile.in: Update to new configure
3374 scheme which is more compatible with WinGDB builds.
3375 * configure.in: Improve comment on how to run autoconf.
3376 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3377 * Makefile.in: Use autoconf substitution to install common
3378 makefile fragment.
3379
3380Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3381
3382 * gencode.c (build_instruction): Use BigEndianCPU instead of
3383 ByteSwapMem.
3384
3385Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3386
3387 * interp.c (sim_monitor): Make output to stdout visible in
3388 wingdb's I/O log window.
3389
3390Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3391
3392 * support.h: Undo previous change to SIGTRAP
3393 and SIGQUIT values.
3394
3395Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3396
3397 * interp.c (store_word, load_word): New static functions.
3398 (mips16_entry): New static function.
3399 (SignalException): Look for mips16 entry and exit instructions.
3400 (simulate): Use the correct index when setting fpr_state after
3401 doing a pending move.
3402
3403Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3404
3405 * interp.c: Fix byte-swapping code throughout to work on
3406 both little- and big-endian hosts.
3407
3408Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3409
3410 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3411 with gdb/config/i386/xm-windows.h.
3412
3413Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3414
3415 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3416 that messes up arithmetic shifts.
3417
3418Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3419
3420 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3421 SIGTRAP and SIGQUIT for _WIN32.
3422
3423Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3424
3425 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3426 force a 64 bit multiplication.
3427 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3428 destination register is 0, since that is the default mips16 nop
3429 instruction.
3430
3431Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3432
3433 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3434 (build_endian_shift): Don't check proc64.
3435 (build_instruction): Always set memval to uword64. Cast op2 to
3436 uword64 when shifting it left in memory instructions. Always use
3437 the same code for stores--don't special case proc64.
3438
3439 * gencode.c (build_mips16_operands): Fix base PC value for PC
3440 relative operands.
3441 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3442 jal instruction.
3443 * interp.c (simJALDELAYSLOT): Define.
3444 (JALDELAYSLOT): Define.
3445 (INDELAYSLOT, INJALDELAYSLOT): Define.
3446 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3447
3448Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3449
3450 * interp.c (sim_open): add flush_cache as a PMON routine
3451 (sim_monitor): handle flush_cache by ignoring it
3452
3453Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3454
3455 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3456 BigEndianMem.
3457 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3458 (BigEndianMem): Rename to ByteSwapMem and change sense.
3459 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3460 BigEndianMem references to !ByteSwapMem.
3461 (set_endianness): New function, with prototype.
3462 (sim_open): Call set_endianness.
3463 (sim_info): Use simBE instead of BigEndianMem.
3464 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3465 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3466 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3467 ifdefs, keeping the prototype declaration.
3468 (swap_word): Rewrite correctly.
3469 (ColdReset): Delete references to CONFIG. Delete endianness related
3470 code; moved to set_endianness.
72f4393d 3471
c906108c
SS		 3472Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3473
3474 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3475 * interp.c (CHECKHILO): Define away.
3476 (simSIGINT): New macro.
3477 (membank_size): Increase from 1MB to 2MB.
3478 (control_c): New function.
3479 (sim_resume): Rename parameter signal to signal_number. Add local
3480 variable prev. Call signal before and after simulate.
3481 (sim_stop_reason): Add simSIGINT support.
3482 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3483 functions always.
3484 (sim_warning): Delete call to SignalException. Do call printf_filtered
3485 if logfh is NULL.
3486 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3487 a call to sim_warning.
3488
3489Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3490
3491 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3492 16 bit instructions.
3493
3494Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3495
3496 Add support for mips16 (16 bit MIPS implementation):
3497 * gencode.c (inst_type): Add mips16 instruction encoding types.
3498 (GETDATASIZEINSN): Define.
3499 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3500 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3501 mtlo.
3502 (MIPS16_DECODE): New table, for mips16 instructions.
3503 (bitmap_val): New static function.
3504 (struct mips16_op): Define.
3505 (mips16_op_table): New table, for mips16 operands.
3506 (build_mips16_operands): New static function.
3507 (process_instructions): If PC is odd, decode a mips16
3508 instruction. Break out instruction handling into new
3509 build_instruction function.
3510 (build_instruction): New static function, broken out of
3511 process_instructions. Check modifiers rather than flags for SHIFT
3512 bit count and m[ft]{hi,lo} direction.
3513 (usage): Pass program name to fprintf.
3514 (main): Remove unused variable this_option_optind. Change
3515 ``*loptarg++'' to ``loptarg++''.
3516 (my_strtoul): Parenthesize && within ||.
3517 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3518 (simulate): If PC is odd, fetch a 16 bit instruction, and
3519 increment PC by 2 rather than 4.
3520 * configure.in: Add case for mips16*-*-*.
3521 * configure: Rebuild.
3522
3523Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3524
3525 * interp.c: Allow -t to enable tracing in standalone simulator.
3526 Fix garbage output in trace file and error messages.
3527
3528Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3529
3530 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3531 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3532 * configure.in: Simplify using macros in ../common/aclocal.m4.
3533 * configure: Regenerated.
3534 * tconfig.in: New file.
3535
3536Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3537
3538 * interp.c: Fix bugs in 64-bit port.
3539 Use ansi function declarations for msvc compiler.
3540 Initialize and test file pointer in trace code.
3541 Prevent duplicate definition of LAST_EMED_REGNUM.
3542
3543Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3544
3545 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3546
3547Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3548
3549 * interp.c (SignalException): Check for explicit terminating
3550 breakpoint value.
3551 * gencode.c: Pass instruction value through SignalException()
3552 calls for Trap, Breakpoint and Syscall.
3553
3554Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3555
3556 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3557 only used on those hosts that provide it.
3558 * configure.in: Add sqrt() to list of functions to be checked for.
3559 * config.in: Re-generated.
3560 * configure: Re-generated.
3561
3562Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3563
3564 * gencode.c (process_instructions): Call build_endian_shift when
3565 expanding STORE RIGHT, to fix swr.
3566 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3567 clear the high bits.
3568 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3569 Fix float to int conversions to produce signed values.
3570
3571Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3572
3573 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3574 (process_instructions): Correct handling of nor instruction.
3575 Correct shift count for 32 bit shift instructions. Correct sign
3576 extension for arithmetic shifts to not shift the number of bits in
3577 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3578 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3579 Fix madd.
3580 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3581 It's OK to have a mult follow a mult. What's not OK is to have a
3582 mult follow an mfhi.
3583 (Convert): Comment out incorrect rounding code.
3584
3585Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3586
3587 * interp.c (sim_monitor): Improved monitor printf
3588 simulation. Tidied up simulator warnings, and added "--log" option
3589 for directing warning message output.
3590 * gencode.c: Use sim_warning() rather than WARNING macro.
3591
3592Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3593
3594 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3595 getopt1.o, rather than on gencode.c. Link objects together.
3596 Don't link against -liberty.
3597 (gencode.o, getopt.o, getopt1.o): New targets.
3598 * gencode.c: Include <ctype.h> and "ansidecl.h".
3599 (AND): Undefine after including "ansidecl.h".
3600 (ULONG_MAX): Define if not defined.
3601 (OP_*): Don't define macros; now defined in opcode/mips.h.
3602 (main): Call my_strtoul rather than strtoul.
3603 (my_strtoul): New static function.
3604
3605Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3606
3607 * gencode.c (process_instructions): Generate word64 and uword64
3608 instead of `long long' and `unsigned long long' data types.
3609 * interp.c: #include sysdep.h to get signals, and define default
3610 for SIGBUS.
3611 * (Convert): Work around for Visual-C++ compiler bug with type
3612 conversion.
3613 * support.h: Make things compile under Visual-C++ by using
3614 __int64 instead of `long long'. Change many refs to long long
3615 into word64/uword64 typedefs.
3616
3617Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3618
72f4393d
L		 3619 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3620 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3621 (docdir): Removed.
3622 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3623 (AC_PROG_INSTALL): Added.
c906108c 3624 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3625 * configure: Rebuilt.
3626
c906108c
SS		 3627Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3628
3629 * configure.in: Define @SIMCONF@ depending on mips target.
3630 * configure: Rebuild.
3631 * Makefile.in (run): Add @SIMCONF@ to control simulator
3632 construction.
3633 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3634 * interp.c: Remove some debugging, provide more detailed error
3635 messages, update memory accesses to use LOADDRMASK.
72f4393d 3636
c906108c
SS		 3637Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3638
3639 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3640 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3641 stamp-h.
3642 * configure: Rebuild.
3643 * config.in: New file, generated by autoheader.
3644 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3645 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3646 HAVE_ANINT and HAVE_AINT, as appropriate.
3647 * Makefile.in (run): Use @LIBS@ rather than -lm.
3648 (interp.o): Depend upon config.h.
3649 (Makefile): Just rebuild Makefile.
3650 (clean): Remove stamp-h.
3651 (mostlyclean): Make the same as clean, not as distclean.
3652 (config.h, stamp-h): New targets.
3653
3654Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3655
3656 * interp.c (ColdReset): Fix boolean test. Make all simulator
3657 globals static.
3658
3659Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3660
3661 * interp.c (xfer_direct_word, xfer_direct_long,
3662 swap_direct_word, swap_direct_long, xfer_big_word,
3663 xfer_big_long, xfer_little_word, xfer_little_long,
3664 swap_word,swap_long): Added.
3665 * interp.c (ColdReset): Provide function indirection to
3666 host<->simulated_target transfer routines.
3667 * interp.c (sim_store_register, sim_fetch_register): Updated to
3668 make use of indirected transfer routines.
3669
3670Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3671
3672 * gencode.c (process_instructions): Ensure FP ABS instruction
3673 recognised.
3674 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3675 system call support.
3676
3677Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3678
3679 * interp.c (sim_do_command): Complain if callback structure not
3680 initialised.
3681
3682Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3683
3684 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3685 support for Sun hosts.
3686 * Makefile.in (gencode): Ensure the host compiler and libraries
3687 used for cross-hosted build.
3688
3689Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3690
3691 * interp.c, gencode.c: Some more (TODO) tidying.
3692
3693Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3694
3695 * gencode.c, interp.c: Replaced explicit long long references with
3696 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3697 * support.h (SET64LO, SET64HI): Macros added.
3698
3699Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3700
3701 * configure: Regenerate with autoconf 2.7.
3702
3703Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3704
3705 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3706 * support.h: Remove superfluous "1" from #if.
3707 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3708
3709Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3710
3711 * interp.c (StoreFPR): Control UndefinedResult() call on
3712 WARN_RESULT manifest.
3713
3714Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3715
3716 * gencode.c: Tidied instruction decoding, and added FP instruction
3717 support.
3718
3719 * interp.c: Added dineroIII, and BSD profiling support. Also
3720 run-time FP handling.
3721
3722Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3723
3724 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3725 gencode.c, interp.c, support.h: created.
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