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sim: allow the environment configure option everywhere
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
99d8e879
MF		 12016-01-10 Mike Frysinger <vapier@gentoo.org>
2
3 * configure: Regenerate.
4
35656e95
MF		 52016-01-10 Mike Frysinger <vapier@gentoo.org>
6
7 * configure: Regenerate.
8
16f7876d
MF		 92016-01-10 Mike Frysinger <vapier@gentoo.org>
10
11 * configure: Regenerate.
12
6d90347b
MF		 132016-01-10 Mike Frysinger <vapier@gentoo.org>
14
15 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
16 * configure: Regenerate.
17
347fe5bb
MF		 182016-01-10 Mike Frysinger <vapier@gentoo.org>
19
20 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
21 * configure: Regenerate.
22
22be3fbe
MF		 232016-01-10 Mike Frysinger <vapier@gentoo.org>
24
25 * configure: Regenerate.
26
0dc73ef7
MF		 272016-01-10 Mike Frysinger <vapier@gentoo.org>
28
29 * configure: Regenerate.
30
936df756
MF		 312016-01-09 Mike Frysinger <vapier@gentoo.org>
32
33 * config.in, configure: Regenerate.
34
2e3d4f4d
MF		 352016-01-06 Mike Frysinger <vapier@gentoo.org>
36
37 * interp.c (sim_open): Mark argv const.
38 (sim_create_inferior): Mark argv and env const.
39
9bbf6f91
MF		 402016-01-04 Mike Frysinger <vapier@gentoo.org>
41
42 * configure: Regenerate.
43
77cf2ef5
MF		 442016-01-03 Mike Frysinger <vapier@gentoo.org>
45
46 * interp.c (sim_open): Update sim_parse_args comment.
47
0cb8d851
MF		 482016-01-03 Mike Frysinger <vapier@gentoo.org>
49
50 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
51 * configure: Regenerate.
52
1ac72f06
MF		 532016-01-02 Mike Frysinger <vapier@gentoo.org>
54
55 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
56 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
57 * configure: Regenerate.
58 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
59
d47f5b30
MF		 602016-01-02 Mike Frysinger <vapier@gentoo.org>
61
62 * dv-tx3904cpu.c (CPU, SD): Delete.
63
e1211e55
MF		 642015-12-30 Mike Frysinger <vapier@gentoo.org>
65
66 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
67 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
68 (sim_store_register): Rename to ...
69 (mips_reg_store): ... this. Delete local cpu var.
70 Update sim_io_eprintf calls.
71 (sim_fetch_register): Rename to ...
72 (mips_reg_fetch): ... this. Delete local cpu var.
73 Update sim_io_eprintf calls.
74
5e744ef8
MF		 752015-12-27 Mike Frysinger <vapier@gentoo.org>
76
77 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
78
1b393626
MF		 792015-12-26 Mike Frysinger <vapier@gentoo.org>
80
81 * config.in, configure: Regenerate.
82
26f8bf63
MF		 832015-12-26 Mike Frysinger <vapier@gentoo.org>
84
85 * interp.c (sim_write, sim_read): Delete.
86 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
87 (load_word): Likewise.
88 * micromips.igen (cache): Likewise.
89 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
90 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
91 do_store_left, do_store_right, do_load_double, do_store_double):
92 Likewise.
93 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
94 (do_prefx): Likewise.
95 * sim-main.c (address_translation, prefetch): Delete.
96 (ifetch32, ifetch16): Delete call to AddressTranslation and set
97 paddr=vaddr.
98 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
99 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
100 (LoadMemory, StoreMemory): Delete CCA arg.
101
ef04e371
MF		 1022015-12-24 Mike Frysinger <vapier@gentoo.org>
103
104 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
105 * configure: Regenerated.
106
cb379ede
MF		 1072015-12-24 Mike Frysinger <vapier@gentoo.org>
108
109 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
110 * tconfig.h: Delete.
111
26936211
MF		 1122015-12-24 Mike Frysinger <vapier@gentoo.org>
113
114 * tconfig.h (SIM_HANDLES_LMA): Delete.
115
84e8e361
MF		 1162015-12-24 Mike Frysinger <vapier@gentoo.org>
117
118 * sim-main.h (WITH_WATCHPOINTS): Delete.
119
3cabaf66
MF		 1202015-12-24 Mike Frysinger <vapier@gentoo.org>
121
122 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
123
8abe6c66
MF		 1242015-12-24 Mike Frysinger <vapier@gentoo.org>
125
126 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
127
1d19cae7
DV		 1282015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
129
130 * micromips.igen (process_isa_mode): Fix left shift of negative
131 value.
132
cdf850e9
MF		 1332015-11-17 Mike Frysinger <vapier@gentoo.org>
134
135 * sim-main.h (WITH_MODULO_MEMORY): Delete.
136
797eee42
MF		 1372015-11-15 Mike Frysinger <vapier@gentoo.org>
138
139 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
140
6e4f085c
MF		 1412015-11-14 Mike Frysinger <vapier@gentoo.org>
142
143 * interp.c (sim_close): Rename to ...
144 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
145 sim_io_shutdown.
146 * sim-main.h (mips_sim_close): Declare.
147 (SIM_CLOSE_HOOK): Define.
148
8e394ffc
AB		 1492015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
150 Ali Lown <ali.lown@imgtec.com>
151
152 * Makefile.in (tmp-micromips): New rule.
153 (tmp-mach-multi): Add support for micromips.
154 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
155 that works for both mips64 and micromips64.
156 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
157 micromips32.
158 Add build support for micromips.
159 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
160 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
161 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
162 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
163 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
164 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
165 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
166 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
167 Refactored instruction code to use these functions.
168 * dsp2.igen: Refactored instruction code to use the new functions.
169 * interp.c (decode_coproc): Refactored to work with any instruction
170 encoding.
171 (isa_mode): New variable
172 (RSVD_INSTRUCTION): Changed to 0x00000039.
173 * m16.igen (BREAK16): Refactored instruction to use do_break16.
174 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
175 * micromips.dc: New file.
176 * micromips.igen: New file.
177 * micromips16.dc: New file.
178 * micromipsdsp.igen: New file.
179 * micromipsrun.c: New file.
180 * mips.igen (do_swc1): Changed to work with any instruction encoding.
181 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
182 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
183 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
184 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
185 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
186 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
187 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
188 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
189 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
190 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
191 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
192 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
193 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
194 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
195 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
196 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
197 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
198 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
199 instructions.
200 Refactored instruction code to use these functions.
201 (RSVD): Changed to use new reserved instruction.
202 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
203 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
204 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
205 do_store_double): Added micromips32 and micromips64 models.
206 Added include for micromips.igen and micromipsdsp.igen
207 Add micromips32 and micromips64 models.
208 (DecodeCoproc): Updated to use new macro definition.
209 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
210 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
211 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
212 Refactored instruction code to use these functions.
213 * sim-main.h (CP0_operation): New enum.
214 (DecodeCoproc): Updated macro.
215 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
216 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
217 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
218 ISA_MODE_MICROMIPS): New defines.
219 (sim_state): Add isa_mode field.
220
8d0978fb
MF		 2212015-06-23 Mike Frysinger <vapier@gentoo.org>
222
223 * configure: Regenerate.
224
306f4178
MF		 2252015-06-12 Mike Frysinger <vapier@gentoo.org>
226
227 * configure.ac: Change configure.in to configure.ac.
228 * configure: Regenerate.
229
a3487082
MF		 2302015-06-12 Mike Frysinger <vapier@gentoo.org>
231
232 * configure: Regenerate.
233
29bc024d
MF		 2342015-06-12 Mike Frysinger <vapier@gentoo.org>
235
236 * interp.c [TRACE]: Delete.
237 (TRACE): Change to WITH_TRACE_ANY_P.
238 [!WITH_TRACE_ANY_P] (open_trace): Define.
239 (mips_option_handler, open_trace, sim_close, dotrace):
240 Change defined(TRACE) to WITH_TRACE_ANY_P.
241 (sim_open): Delete TRACE ifdef check.
242 * sim-main.c (load_memory): Delete TRACE ifdef check.
243 (store_memory): Likewise.
244 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
245 [!WITH_TRACE_ANY_P] (dotrace): Define.
246
3ebe2863
MF		 2472015-04-18 Mike Frysinger <vapier@gentoo.org>
248
249 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
250 comments.
251
20bca71d
MF		 2522015-04-18 Mike Frysinger <vapier@gentoo.org>
253
254 * sim-main.h (SIM_CPU): Delete.
255
7e83aa92
MF		 2562015-04-18 Mike Frysinger <vapier@gentoo.org>
257
258 * sim-main.h (sim_cia): Delete.
259
034685f9
MF		 2602015-04-17 Mike Frysinger <vapier@gentoo.org>
261
262 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
263 PU_PC_GET.
264 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
265 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
266 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
267 CIA_SET to CPU_PC_SET.
268 * sim-main.h (CIA_GET, CIA_SET): Delete.
269
78e9aa70
MF		 2702015-04-15 Mike Frysinger <vapier@gentoo.org>
271
272 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
273 * sim-main.h (STATE_CPU): Delete.
274
bf12d44e
MF		 2752015-04-13 Mike Frysinger <vapier@gentoo.org>
276
277 * configure: Regenerate.
278
7bebb329
MF		 2792015-04-13 Mike Frysinger <vapier@gentoo.org>
280
281 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
282 * interp.c (mips_pc_get, mips_pc_set): New functions.
283 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
284 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
285 (sim_pc_get): Delete.
286 * sim-main.h (SIM_CPU): Define.
287 (struct sim_state): Change cpu to an array of pointers.
288 (STATE_CPU): Drop &.
289
8ac57fbd
MF		 2902015-04-13 Mike Frysinger <vapier@gentoo.org>
291
292 * interp.c (mips_option_handler, open_trace, sim_close,
293 sim_write, sim_read, sim_store_register, sim_fetch_register,
294 sim_create_inferior, pr_addr, pr_uword64): Convert old style
295 prototypes.
296 (sim_open): Convert old style prototype. Change casts with
297 sim_write to unsigned char *.
298 (fetch_str): Change null to unsigned char, and change cast to
299 unsigned char *.
300 (sim_monitor): Change c & ch to unsigned char. Change cast to
301 unsigned char *.
302
e787f858
MF		 3032015-04-12 Mike Frysinger <vapier@gentoo.org>
304
305 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
306
122bbfb5
MF		 3072015-04-06 Mike Frysinger <vapier@gentoo.org>
308
309 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
310
0fe84f3f
MF		 3112015-04-01 Mike Frysinger <vapier@gentoo.org>
312
313 * tconfig.h (SIM_HAVE_PROFILE): Delete.
314
aadc9410
MF		 3152015-03-31 Mike Frysinger <vapier@gentoo.org>
316
317 * config.in, configure: Regenerate.
318
05f53ed6
MF		 3192015-03-24 Mike Frysinger <vapier@gentoo.org>
320
321 * interp.c (sim_pc_get): New function.
322
c0931f26
MF		 3232015-03-24 Mike Frysinger <vapier@gentoo.org>
324
325 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
326 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
327
30452bbe
MF		 3282015-03-24 Mike Frysinger <vapier@gentoo.org>
329
330 * configure: Regenerate.
331
64dd13df
MF		 3322015-03-23 Mike Frysinger <vapier@gentoo.org>
333
334 * configure: Regenerate.
335
49cd1634
MF		 3362015-03-23 Mike Frysinger <vapier@gentoo.org>
337
338 * configure: Regenerate.
339 * configure.ac (mips_extra_objs): Delete.
340 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
341 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
342
3649cb06
MF		 3432015-03-23 Mike Frysinger <vapier@gentoo.org>
344
345 * configure: Regenerate.
346 * configure.ac: Delete sim_hw checks for dv-sockser.
347
ae7d0cac
MF		 3482015-03-16 Mike Frysinger <vapier@gentoo.org>
349
350 * config.in, configure: Regenerate.
351 * tconfig.in: Rename file ...
352 * tconfig.h: ... here.
353
8406bb59
MF		 3542015-03-15 Mike Frysinger <vapier@gentoo.org>
355
356 * tconfig.in: Delete includes.
357 [HAVE_DV_SOCKSER]: Delete.
358
465fb143
MF		 3592015-03-14 Mike Frysinger <vapier@gentoo.org>
360
361 * Makefile.in (SIM_RUN_OBJS): Delete.
362
5cddc23a
MF		 3632015-03-14 Mike Frysinger <vapier@gentoo.org>
364
365 * configure.ac (AC_CHECK_HEADERS): Delete.
366 * aclocal.m4, configure: Regenerate.
367
2974be62
AM		 3682014-08-19 Alan Modra <amodra@gmail.com>
369
370 * configure: Regenerate.
371
faa743bb
RM		 3722014-08-15 Roland McGrath <mcgrathr@google.com>
373
374 * configure: Regenerate.
375 * config.in: Regenerate.
376
1a8a700e
MF		 3772014-03-04 Mike Frysinger <vapier@gentoo.org>
378
379 * configure: Regenerate.
380
bf3d9781
AM		 3812013-09-23 Alan Modra <amodra@gmail.com>
382
383 * configure: Regenerate.
384
31e6ad7d
MF		 3852013-06-03 Mike Frysinger <vapier@gentoo.org>
386
387 * aclocal.m4, configure: Regenerate.
388
d3685d60
TT		 3892013-05-10 Freddie Chopin <freddie_chopin@op.pl>
390
391 * configure: Rebuild.
392
1517bd27
MF		 3932013-03-26 Mike Frysinger <vapier@gentoo.org>
394
395 * configure: Regenerate.
396
3be31516
JS		 3972013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
398
399 * configure.ac: Address use of dv-sockser.o.
400 * tconfig.in: Conditionalize use of dv_sockser_install.
401 * configure: Regenerated.
402 * config.in: Regenerated.
403
37cb8f8e
SE		 4042012-10-04 Chao-ying Fu <fu@mips.com>
405 Steve Ellcey <sellcey@mips.com>
406
407 * mips/mips3264r2.igen (rdhwr): New.
408
87c8644f
JS		 4092012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
410
411 * configure.ac: Always link against dv-sockser.o.
412 * configure: Regenerate.
413
5f3ef9d0
JB		 4142012-06-15 Joel Brobecker <brobecker@adacore.com>
415
416 * config.in, configure: Regenerate.
417
a6ff997c
NC		 4182012-05-18 Nick Clifton <nickc@redhat.com>
419
420 PR 14072
421 * interp.c: Include config.h before system header files.
422
2232061b
MF		 4232012-03-24 Mike Frysinger <vapier@gentoo.org>
424
425 * aclocal.m4, config.in, configure: Regenerate.
426
db2e4d67
MF		 4272011-12-03 Mike Frysinger <vapier@gentoo.org>
428
429 * aclocal.m4: New file.
430 * configure: Regenerate.
431
4399a56b
MF		 4322011-10-19 Mike Frysinger <vapier@gentoo.org>
433
434 * configure: Regenerate after common/acinclude.m4 update.
435
9c082ca8
MF		 4362011-10-17 Mike Frysinger <vapier@gentoo.org>
437
438 * configure.ac: Change include to common/acinclude.m4.
439
6ffe910a
MF		 4402011-10-17 Mike Frysinger <vapier@gentoo.org>
441
442 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
443 call. Replace common.m4 include with SIM_AC_COMMON.
444 * configure: Regenerate.
445
31b28250
HPN		 4462011-07-08 Hans-Peter Nilsson <hp@axis.com>
447
3faa01e3
HPN		 448 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
449 $(SIM_EXTRA_DEPS).
450 (tmp-mach-multi): Exit early when igen fails.
31b28250 451
2419798b
MF		 4522011-07-05 Mike Frysinger <vapier@gentoo.org>
453
454 * interp.c (sim_do_command): Delete.
455
d79fe0d6
MF		 4562011-02-14 Mike Frysinger <vapier@gentoo.org>
457
458 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
459 (tx3904sio_fifo_reset): Likewise.
460 * interp.c (sim_monitor): Likewise.
461
5558e7e6
MF		 4622010-04-14 Mike Frysinger <vapier@gentoo.org>
463
464 * interp.c (sim_write): Add const to buffer arg.
465
35aafff4
JB		 4662010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
467
468 * interp.c: Don't include sysdep.h
469
3725885a
RW		 4702010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
471
472 * configure: Regenerate.
473
d6416cdc
RW		 4742009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
475
81ecdfbb
RW		 476 * config.in: Regenerate.
477 * configure: Likewise.
478
d6416cdc
RW		 479 * configure: Regenerate.
480
b5bd9624
HPN		 4812008-07-11 Hans-Peter Nilsson <hp@axis.com>
482
483 * configure: Regenerate to track ../common/common.m4 changes.
484 * config.in: Ditto.
485
6efef468 4862008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 487 Daniel Jacobowitz <dan@codesourcery.com>
488 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 489
490 * configure: Regenerate.
491
60dc88db
RS		 4922007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
493
494 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
495 that unconditionally allows fmt_ps.
496 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
497 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
498 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
499 filter from 64,f to 32,f.
500 (PREFX): Change filter from 64 to 32.
501 (LDXC1, LUXC1): Provide separate mips32r2 implementations
502 that use do_load_double instead of do_load. Make both LUXC1
503 versions unpredictable if SizeFGR () != 64.
504 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
505 instead of do_store. Remove unused variable. Make both SUXC1
506 versions unpredictable if SizeFGR () != 64.
507
599ca73e
RS		 5082007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
509
510 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
511 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
512 shifts for that case.
513
2525df03
NC		 5142007-09-04 Nick Clifton <nickc@redhat.com>
515
516 * interp.c (options enum): Add OPTION_INFO_MEMORY.
517 (display_mem_info): New static variable.
518 (mips_option_handler): Handle OPTION_INFO_MEMORY.
519 (mips_options): Add info-memory and memory-info.
520 (sim_open): After processing the command line and board
521 specification, check display_mem_info. If it is set then
522 call the real handler for the --memory-info command line
523 switch.
524
35ee6e1e
JB		 5252007-08-24 Joel Brobecker <brobecker@adacore.com>
526
527 * configure.ac: Change license of multi-run.c to GPL version 3.
528 * configure: Regenerate.
529
d5fb0879
RS		 5302007-06-28 Richard Sandiford <richard@codesourcery.com>
531
532 * configure.ac, configure: Revert last patch.
533
2a2ce21b
RS		 5342007-06-26 Richard Sandiford <richard@codesourcery.com>
535
536 * configure.ac (sim_mipsisa3264_configs): New variable.
537 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
538 every configuration support all four targets, using the triplet to
539 determine the default.
540 * configure: Regenerate.
541
efdcccc9
RS		 5422007-06-25 Richard Sandiford <richard@codesourcery.com>
543
0a7692b2 544 * Makefile.in (m16run.o): New rule.
efdcccc9 545
f532a356
TS		 5462007-05-15 Thiemo Seufer <ths@mips.com>
547
548 * mips3264r2.igen (DSHD): Fix compile warning.
549
bfe9c90b
TS		 5502007-05-14 Thiemo Seufer <ths@mips.com>
551
552 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
553 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
554 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
555 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
556 for mips32r2.
557
53f4826b
TS		 5582007-03-01 Thiemo Seufer <ths@mips.com>
559
560 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
561 and mips64.
562
8bf3ddc8
TS		 5632007-02-20 Thiemo Seufer <ths@mips.com>
564
565 * dsp.igen: Update copyright notice.
566 * dsp2.igen: Fix copyright notice.
567
8b082fb1 5682007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 569 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 570
571 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
572 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
573 Add dsp2 to sim_igen_machine.
574 * configure: Regenerate.
575 * dsp.igen (do_ph_op): Add MUL support when op = 2.
576 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
577 (mulq_rs.ph): Use do_ph_mulq.
578 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
579 * mips.igen: Add dsp2 model and include dsp2.igen.
580 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
581 for *mips32r2, *mips64r2, *dsp.
582 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
583 for *mips32r2, *mips64r2, *dsp2.
584 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
585
b1004875 5862007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 587 Nigel Stephens <nigel@mips.com>
b1004875
TS		 588
589 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
590 jumps with hazard barrier.
591
f8df4c77 5922007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 593 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 594
595 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
596 after each call to sim_io_write.
597
b1004875 5982007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 599 Nigel Stephens <nigel@mips.com>
b1004875
TS		 600
601 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
602 supported by this simulator.
07802d98
TS		 603 (decode_coproc): Recognise additional CP0 Config registers
604 correctly.
605
14fb6c5a 6062007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 607 Nigel Stephens <nigel@mips.com>
608 David Ung <davidu@mips.com>
14fb6c5a
TS		 609
610 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
611 uninterpreted formats. If fmt is one of the uninterpreted types
612 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
613 fmt_word, and fmt_uninterpreted_64 like fmt_long.
614 (store_fpr): When writing an invalid odd register, set the
615 matching even register to fmt_unknown, not the following register.
616 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
617 the the memory window at offset 0 set by --memory-size command
618 line option.
619 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
620 point register.
621 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
622 register.
623 (sim_monitor): When returning the memory size to the MIPS
624 application, use the value in STATE_MEM_SIZE, not an arbitrary
625 hardcoded value.
626 (cop_lw): Don' mess around with FPR_STATE, just pass
627 fmt_uninterpreted_32 to StoreFPR.
628 (cop_sw): Similarly.
629 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
630 (cop_sd): Similarly.
631 * mips.igen (not_word_value): Single version for mips32, mips64
632 and mips16.
633
c8847145 6342007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 635 Nigel Stephens <nigel@mips.com>
c8847145
TS		 636
637 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
638 MBytes.
639
4b5d35ee
TS		 6402007-02-17 Thiemo Seufer <ths@mips.com>
641
642 * configure.ac (mips*-sde-elf*): Move in front of generic machine
643 configuration.
644 * configure: Regenerate.
645
3669427c
TS		 6462007-02-17 Thiemo Seufer <ths@mips.com>
647
648 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
649 Add mdmx to sim_igen_machine.
650 (mipsisa64*-*-*): Likewise. Remove dsp.
651 (mipsisa32*-*-*): Remove dsp.
652 * configure: Regenerate.
653
109ad085
TS		 6542007-02-13 Thiemo Seufer <ths@mips.com>
655
656 * configure.ac: Add mips*-sde-elf* target.
657 * configure: Regenerate.
658
921d7ad3
HPN		 6592006-12-21 Hans-Peter Nilsson <hp@axis.com>
660
661 * acconfig.h: Remove.
662 * config.in, configure: Regenerate.
663
02f97da7
TS		 6642006-11-07 Thiemo Seufer <ths@mips.com>
665
666 * dsp.igen (do_w_op): Fix compiler warning.
667
2d2733fc 6682006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 669 David Ung <davidu@mips.com>
2d2733fc
TS		 670
671 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
672 sim_igen_machine.
673 * configure: Regenerate.
674 * mips.igen (model): Add smartmips.
675 (MADDU): Increment ACX if carry.
676 (do_mult): Clear ACX.
677 (ROR,RORV): Add smartmips.
72f4393d 678 (include): Include smartmips.igen.
2d2733fc
TS		 679 * sim-main.h (ACX): Set to REGISTERS[89].
680 * smartmips.igen: New file.
681
d85c3a10 6822006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 683 David Ung <davidu@mips.com>
d85c3a10
TS		 684
685 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
686 mips3264r2.igen. Add missing dependency rules.
687 * m16e.igen: Support for mips16e save/restore instructions.
688
e85e3205
RE		 6892006-06-13 Richard Earnshaw <rearnsha@arm.com>
690
691 * configure: Regenerated.
692
2f0122dc
DJ		 6932006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
694
695 * configure: Regenerated.
696
20e95c23
DJ		 6972006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
698
699 * configure: Regenerated.
700
69088b17
CF		 7012006-05-15 Chao-ying Fu <fu@mips.com>
702
703 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
704
0275de4e
NC		 7052006-04-18 Nick Clifton <nickc@redhat.com>
706
707 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
708 statement.
709
b3a3ffef
HPN		 7102006-03-29 Hans-Peter Nilsson <hp@axis.com>
711
712 * configure: Regenerate.
713
40a5538e
CF		 7142005-12-14 Chao-ying Fu <fu@mips.com>
715
716 * Makefile.in (SIM_OBJS): Add dsp.o.
717 (dsp.o): New dependency.
718 (IGEN_INCLUDE): Add dsp.igen.
719 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
720 mipsisa64*-*-*): Add dsp to sim_igen_machine.
721 * configure: Regenerate.
722 * mips.igen: Add dsp model and include dsp.igen.
723 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
724 because these instructions are extended in DSP ASE.
725 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
726 adding 6 DSP accumulator registers and 1 DSP control register.
727 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
728 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
729 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
730 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
731 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
732 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
733 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
734 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
735 DSPCR_CCOND_SMASK): New define.
736 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
737 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
738
21d14896
ILT		 7392005-07-08 Ian Lance Taylor <ian@airs.com>
740
741 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
742
b16d63da 7432005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 744 Nigel Stephens <nigel@mips.com>
745
746 * mips.igen: New mips16e model and include m16e.igen.
747 (check_u64): Add mips16e tag.
748 * m16e.igen: New file for MIPS16e instructions.
749 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
750 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
751 models.
752 * configure: Regenerate.
b16d63da 753
e70cb6cd 7542005-05-26 David Ung <davidu@mips.com>
72f4393d 755
e70cb6cd
CD		 756 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
757 tags to all instructions which are applicable to the new ISAs.
758 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
759 vr.igen.
760 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 761 instructions.
e70cb6cd
CD		 762 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
763 to mips.igen.
764 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
765 * configure: Regenerate.
72f4393d 766
2b193c4a
MK		 7672005-03-23 Mark Kettenis <kettenis@gnu.org>
768
769 * configure: Regenerate.
770
35695fd6
AC		 7712005-01-14 Andrew Cagney <cagney@gnu.org>
772
773 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
774 explicit call to AC_CONFIG_HEADER.
775 * configure: Regenerate.
776
f0569246
AC		 7772005-01-12 Andrew Cagney <cagney@gnu.org>
778
779 * configure.ac: Update to use ../common/common.m4.
780 * configure: Re-generate.
781
38f48d72
AC		 7822005-01-11 Andrew Cagney <cagney@localhost.localdomain>
783
784 * configure: Regenerated to track ../common/aclocal.m4 changes.
785
b7026657
AC		 7862005-01-07 Andrew Cagney <cagney@gnu.org>
787
788 * configure.ac: Rename configure.in, require autoconf 2.59.
789 * configure: Re-generate.
790
379832de
HPN		 7912004-12-08 Hans-Peter Nilsson <hp@axis.com>
792
793 * configure: Regenerate for ../common/aclocal.m4 update.
794
cd62154c 7952004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 796
cd62154c
AC		 797 Committed by Andrew Cagney.
798 * m16.igen (CMP, CMPI): Fix assembler.
799
e5da76ec
CD		 8002004-08-18 Chris Demetriou <cgd@broadcom.com>
801
802 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
803 * configure: Regenerate.
804
139181c8
CD		 8052004-06-25 Chris Demetriou <cgd@broadcom.com>
806
807 * configure.in (sim_m16_machine): Include mipsIII.
808 * configure: Regenerate.
809
1a27f959
CD		 8102004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
811
72f4393d 812 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 813 from COP0_BADVADDR.
814 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
815
5dbb7b5a
CD		 8162004-04-10 Chris Demetriou <cgd@broadcom.com>
817
818 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
819
14234056
CD		 8202004-04-09 Chris Demetriou <cgd@broadcom.com>
821
822 * mips.igen (check_fmt): Remove.
823 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
824 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
825 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
826 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
827 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
828 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
829 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
830 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
831 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
832 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
833
c6f9085c
CD		 8342004-04-09 Chris Demetriou <cgd@broadcom.com>
835
836 * sb1.igen (check_sbx): New function.
837 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
838
11d66e66 8392004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 840 Richard Sandiford <rsandifo@redhat.com>
841
842 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
843 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
844 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
845 separate implementations for mipsIV and mipsV. Use new macros to
846 determine whether the restrictions apply.
847
b3208fb8
CD		 8482004-01-19 Chris Demetriou <cgd@broadcom.com>
849
850 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
851 (check_mult_hilo): Improve comments.
852 (check_div_hilo): Likewise. Also, fork off a new version
853 to handle mips32/mips64 (since there are no hazards to check
854 in MIPS32/MIPS64).
855
9a1d84fb
CD		 8562003-06-17 Richard Sandiford <rsandifo@redhat.com>
857
858 * mips.igen (do_dmultx): Fix check for negative operands.
859
ae451ac6
ILT		 8602003-05-16 Ian Lance Taylor <ian@airs.com>
861
862 * Makefile.in (SHELL): Make sure this is defined.
863 (various): Use $(SHELL) whenever we invoke move-if-change.
864
dd69d292
CD		 8652003-05-03 Chris Demetriou <cgd@broadcom.com>
866
867 * cp1.c: Tweak attribution slightly.
868 * cp1.h: Likewise.
869 * mdmx.c: Likewise.
870 * mdmx.igen: Likewise.
871 * mips3d.igen: Likewise.
872 * sb1.igen: Likewise.
873
bcd0068e
CD		 8742003-04-15 Richard Sandiford <rsandifo@redhat.com>
875
876 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
877 unsigned operands.
878
6b4a8935
AC		 8792003-02-27 Andrew Cagney <cagney@redhat.com>
880
601da316
AC		 881 * interp.c (sim_open): Rename _bfd to bfd.
882 (sim_create_inferior): Ditto.
6b4a8935 883
d29e330f
CD		 8842003-01-14 Chris Demetriou <cgd@broadcom.com>
885
886 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
887
a2353a08
CD		 8882003-01-14 Chris Demetriou <cgd@broadcom.com>
889
890 * mips.igen (EI, DI): Remove.
891
80551777
CD		 8922003-01-05 Richard Sandiford <rsandifo@redhat.com>
893
894 * Makefile.in (tmp-run-multi): Fix mips16 filter.
895
4c54fc26
CD		 8962003-01-04 Richard Sandiford <rsandifo@redhat.com>
897 Andrew Cagney <ac131313@redhat.com>
898 Gavin Romig-Koch <gavin@redhat.com>
899 Graydon Hoare <graydon@redhat.com>
900 Aldy Hernandez <aldyh@redhat.com>
901 Dave Brolley <brolley@redhat.com>
902 Chris Demetriou <cgd@broadcom.com>
903
904 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
905 (sim_mach_default): New variable.
906 (mips64vr-*-*, mips64vrel-*-*): New configurations.
907 Add a new simulator generator, MULTI.
908 * configure: Regenerate.
909 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
910 (multi-run.o): New dependency.
911 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
912 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
913 (tmp-multi): Combine them.
914 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
915 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
916 (distclean-extra): New rule.
917 * sim-main.h: Include bfd.h.
918 (MIPS_MACH): New macro.
919 * mips.igen (vr4120, vr5400, vr5500): New models.
920 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
921 * vr.igen: Replace with new version.
922
e6c674b8
CD		 9232003-01-04 Chris Demetriou <cgd@broadcom.com>
924
925 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
926 * configure: Regenerate.
927
28f50ac8
CD		 9282002-12-31 Chris Demetriou <cgd@broadcom.com>
929
930 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
931 * mips.igen: Remove all invocations of check_branch_bug and
932 mark_branch_bug.
933
5071ffe6
CD		 9342002-12-16 Chris Demetriou <cgd@broadcom.com>
935
72f4393d 936 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 937
06e7837e
CD		 9382002-07-30 Chris Demetriou <cgd@broadcom.com>
939
940 * mips.igen (do_load_double, do_store_double): New functions.
941 (LDC1, SDC1): Rename to...
942 (LDC1b, SDC1b): respectively.
943 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
944
2265c243
MS		 9452002-07-29 Michael Snyder <msnyder@redhat.com>
946
947 * cp1.c (fp_recip2): Modify initialization expression so that
948 GCC will recognize it as constant.
949
a2f8b4f3
CD		 9502002-06-18 Chris Demetriou <cgd@broadcom.com>
951
952 * mdmx.c (SD_): Delete.
953 (Unpredictable): Re-define, for now, to directly invoke
954 unpredictable_action().
955 (mdmx_acc_op): Fix error in .ob immediate handling.
956
b4b6c939
AC		 9572002-06-18 Andrew Cagney <cagney@redhat.com>
958
959 * interp.c (sim_firmware_command): Initialize `address'.
960
c8cca39f
AC		 9612002-06-16 Andrew Cagney <ac131313@redhat.com>
962
963 * configure: Regenerated to track ../common/aclocal.m4 changes.
964
e7e81181 9652002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 966 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 967
968 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
969 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
970 * mips.igen: Include mips3d.igen.
971 (mips3d): New model name for MIPS-3D ASE instructions.
972 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 973 instructions.
e7e81181
CD		 974 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
975 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
976 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
977 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
978 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
979 (RSquareRoot1, RSquareRoot2): New macros.
980 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
981 (fp_rsqrt2): New functions.
982 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
983 * configure: Regenerate.
984
3a2b820e 9852002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 986 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 987
988 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
989 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
990 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
991 (convert): Note that this function is not used for paired-single
992 format conversions.
993 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
994 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
995 (check_fmt_p): Enable paired-single support.
996 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
997 (PUU.PS): New instructions.
998 (CVT.S.fmt): Don't use this instruction for paired-single format
999 destinations.
1000 * sim-main.h (FP_formats): New value 'fmt_ps.'
1001 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1002 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1003
d18ea9c2
CD		 10042002-06-12 Chris Demetriou <cgd@broadcom.com>
1005
1006 * mips.igen: Fix formatting of function calls in
1007 many FP operations.
1008
95fd5cee
CD		 10092002-06-12 Chris Demetriou <cgd@broadcom.com>
1010
1011 * mips.igen (MOVN, MOVZ): Trace result.
1012 (TNEI): Print "tnei" as the opcode name in traces.
1013 (CEIL.W): Add disassembly string for traces.
1014 (RSQRT.fmt): Make location of disassembly string consistent
1015 with other instructions.
1016
4f0d55ae
CD		 10172002-06-12 Chris Demetriou <cgd@broadcom.com>
1018
1019 * mips.igen (X): Delete unused function.
1020
3c25f8c7
AC		 10212002-06-08 Andrew Cagney <cagney@redhat.com>
1022
1023 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1024
f3c08b7e 10252002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1026 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1027
1028 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1029 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1030 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1031 (fp_nmsub): New prototypes.
1032 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1033 (NegMultiplySub): New defines.
1034 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1035 (MADD.D, MADD.S): Replace with...
1036 (MADD.fmt): New instruction.
1037 (MSUB.D, MSUB.S): Replace with...
1038 (MSUB.fmt): New instruction.
1039 (NMADD.D, NMADD.S): Replace with...
1040 (NMADD.fmt): New instruction.
1041 (NMSUB.D, MSUB.S): Replace with...
1042 (NMSUB.fmt): New instruction.
1043
52714ff9 10442002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1045 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1046
1047 * cp1.c: Fix more comment spelling and formatting.
1048 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1049 (denorm_mode): New function.
1050 (fpu_unary, fpu_binary): Round results after operation, collect
1051 status from rounding operations, and update the FCSR.
1052 (convert): Collect status from integer conversions and rounding
1053 operations, and update the FCSR. Adjust NaN values that result
1054 from conversions. Convert to use sim_io_eprintf rather than
1055 fprintf, and remove some debugging code.
1056 * cp1.h (fenr_FS): New define.
1057
577d8c4b
CD		 10582002-06-07 Chris Demetriou <cgd@broadcom.com>
1059
1060 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1061 rounding mode to sim FP rounding mode flag conversion code into...
1062 (rounding_mode): New function.
1063
196496ed
CD		 10642002-06-07 Chris Demetriou <cgd@broadcom.com>
1065
1066 * cp1.c: Clean up formatting of a few comments.
1067 (value_fpr): Reformat switch statement.
1068
cfe9ea23 10692002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1070 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1071
1072 * cp1.h: New file.
1073 * sim-main.h: Include cp1.h.
1074 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1075 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1076 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1077 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1078 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1079 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1080 * cp1.c: Don't include sim-fpu.h; already included by
1081 sim-main.h. Clean up formatting of some comments.
1082 (NaN, Equal, Less): Remove.
1083 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1084 (fp_cmp): New functions.
1085 * mips.igen (do_c_cond_fmt): Remove.
1086 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1087 Compare. Add result tracing.
1088 (CxC1): Remove, replace with...
1089 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1090 (DMxC1): Remove, replace with...
1091 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1092 (MxC1): Remove, replace with...
1093 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1094
ee7254b0
CD		 10952002-06-04 Chris Demetriou <cgd@broadcom.com>
1096
1097 * sim-main.h (FGRIDX): Remove, replace all uses with...
1098 (FGR_BASE): New macro.
1099 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1100 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1101 (NR_FGR, FGR): Likewise.
1102 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1103 * mips.igen: Likewise.
1104
d3eb724f
CD		 11052002-06-04 Chris Demetriou <cgd@broadcom.com>
1106
1107 * cp1.c: Add an FSF Copyright notice to this file.
1108
ba46ddd0 11092002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1110 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1111
1112 * cp1.c (Infinity): Remove.
1113 * sim-main.h (Infinity): Likewise.
1114
1115 * cp1.c (fp_unary, fp_binary): New functions.
1116 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1117 (fp_sqrt): New functions, implemented in terms of the above.
1118 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1119 (Recip, SquareRoot): Remove (replaced by functions above).
1120 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1121 (fp_recip, fp_sqrt): New prototypes.
1122 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1123 (Recip, SquareRoot): Replace prototypes with #defines which
1124 invoke the functions above.
72f4393d 1125
18d8a52d
CD		 11262002-06-03 Chris Demetriou <cgd@broadcom.com>
1127
1128 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1129 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1130 file, remove PARAMS from prototypes.
1131 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1132 simulator state arguments.
1133 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1134 pass simulator state arguments.
1135 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1136 (store_fpr, convert): Remove 'sd' argument.
1137 (value_fpr): Likewise. Convert to use 'SD' instead.
1138
0f154cbd
CD		 11392002-06-03 Chris Demetriou <cgd@broadcom.com>
1140
1141 * cp1.c (Min, Max): Remove #if 0'd functions.
1142 * sim-main.h (Min, Max): Remove.
1143
e80fc152
CD		 11442002-06-03 Chris Demetriou <cgd@broadcom.com>
1145
1146 * cp1.c: fix formatting of switch case and default labels.
1147 * interp.c: Likewise.
1148 * sim-main.c: Likewise.
1149
bad673a9
CD		 11502002-06-03 Chris Demetriou <cgd@broadcom.com>
1151
1152 * cp1.c: Clean up comments which describe FP formats.
1153 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1154
7cbea089 11552002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1156 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1157
1158 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1159 Broadcom SiByte SB-1 processor configurations.
1160 * configure: Regenerate.
1161 * sb1.igen: New file.
1162 * mips.igen: Include sb1.igen.
1163 (sb1): New model.
1164 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1165 * mdmx.igen: Add "sb1" model to all appropriate functions and
1166 instructions.
1167 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1168 (ob_func, ob_acc): Reference the above.
1169 (qh_acc): Adjust to keep the same size as ob_acc.
1170 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1171 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1172
909daa82
CD		 11732002-06-03 Chris Demetriou <cgd@broadcom.com>
1174
1175 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1176
f4f1b9f1 11772002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1178 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1179
1180 * mips.igen (mdmx): New (pseudo-)model.
1181 * mdmx.c, mdmx.igen: New files.
1182 * Makefile.in (SIM_OBJS): Add mdmx.o.
1183 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1184 New typedefs.
1185 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1186 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1187 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1188 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1189 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1190 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1191 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1192 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1193 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1194 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1195 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1196 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1197 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1198 (qh_fmtsel): New macros.
1199 (_sim_cpu): New member "acc".
1200 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1201 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1202
5accf1ff
CD		 12032002-05-01 Chris Demetriou <cgd@broadcom.com>
1204
1205 * interp.c: Use 'deprecated' rather than 'depreciated.'
1206 * sim-main.h: Likewise.
1207
402586aa
CD		 12082002-05-01 Chris Demetriou <cgd@broadcom.com>
1209
1210 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1211 which wouldn't compile anyway.
1212 * sim-main.h (unpredictable_action): New function prototype.
1213 (Unpredictable): Define to call igen function unpredictable().
1214 (NotWordValue): New macro to call igen function not_word_value().
1215 (UndefinedResult): Remove.
1216 * interp.c (undefined_result): Remove.
1217 (unpredictable_action): New function.
1218 * mips.igen (not_word_value, unpredictable): New functions.
1219 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1220 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1221 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1222 NotWordValue() to check for unpredictable inputs, then
1223 Unpredictable() to handle them.
1224
c9b9995a
CD		 12252002-02-24 Chris Demetriou <cgd@broadcom.com>
1226
1227 * mips.igen: Fix formatting of calls to Unpredictable().
1228
e1015982
AC		 12292002-04-20 Andrew Cagney <ac131313@redhat.com>
1230
1231 * interp.c (sim_open): Revert previous change.
1232
b882a66b
AO		 12332002-04-18 Alexandre Oliva <aoliva@redhat.com>
1234
1235 * interp.c (sim_open): Disable chunk of code that wrote code in
1236 vector table entries.
1237
c429b7dd
CD		 12382002-03-19 Chris Demetriou <cgd@broadcom.com>
1239
1240 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1241 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1242 unused definitions.
1243
37d146fa
CD		 12442002-03-19 Chris Demetriou <cgd@broadcom.com>
1245
1246 * cp1.c: Fix many formatting issues.
1247
07892c0b
CD		 12482002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1249
1250 * cp1.c (fpu_format_name): New function to replace...
1251 (DOFMT): This. Delete, and update all callers.
1252 (fpu_rounding_mode_name): New function to replace...
1253 (RMMODE): This. Delete, and update all callers.
1254
487f79b7
CD		 12552002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1256
1257 * interp.c: Move FPU support routines from here to...
1258 * cp1.c: Here. New file.
1259 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1260 (cp1.o): New target.
1261
1e799e28
CD		 12622002-03-12 Chris Demetriou <cgd@broadcom.com>
1263
1264 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1265 * mips.igen (mips32, mips64): New models, add to all instructions
1266 and functions as appropriate.
1267 (loadstore_ea, check_u64): New variant for model mips64.
1268 (check_fmt_p): New variant for models mipsV and mips64, remove
1269 mipsV model marking fro other variant.
1270 (SLL) Rename to...
1271 (SLLa) this.
1272 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1273 for mips32 and mips64.
1274 (DCLO, DCLZ): New instructions for mips64.
1275
82f728db
CD		 12762002-03-07 Chris Demetriou <cgd@broadcom.com>
1277
1278 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1279 immediate or code as a hex value with the "%#lx" format.
1280 (ANDI): Likewise, and fix printed instruction name.
1281
b96e7ef1
CD		 12822002-03-05 Chris Demetriou <cgd@broadcom.com>
1283
1284 * sim-main.h (UndefinedResult, Unpredictable): New macros
1285 which currently do nothing.
1286
d35d4f70
CD		 12872002-03-05 Chris Demetriou <cgd@broadcom.com>
1288
1289 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1290 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1291 (status_CU3): New definitions.
1292
1293 * sim-main.h (ExceptionCause): Add new values for MIPS32
1294 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1295 for DebugBreakPoint and NMIReset to note their status in
1296 MIPS32 and MIPS64.
1297 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1298 (SignalExceptionCacheErr): New exception macros.
1299
3ad6f714
CD		 13002002-03-05 Chris Demetriou <cgd@broadcom.com>
1301
1302 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1303 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1304 is always enabled.
1305 (SignalExceptionCoProcessorUnusable): Take as argument the
1306 unusable coprocessor number.
1307
86b77b47
CD		 13082002-03-05 Chris Demetriou <cgd@broadcom.com>
1309
1310 * mips.igen: Fix formatting of all SignalException calls.
1311
97a88e93 13122002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1313
1314 * sim-main.h (SIGNEXTEND): Remove.
1315
97a88e93 13162002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1317
1318 * mips.igen: Remove gencode comment from top of file, fix
1319 spelling in another comment.
1320
97a88e93 13212002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1322
1323 * mips.igen (check_fmt, check_fmt_p): New functions to check
1324 whether specific floating point formats are usable.
1325 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1326 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1327 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1328 Use the new functions.
1329 (do_c_cond_fmt): Remove format checks...
1330 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1331
97a88e93 13322002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1333
1334 * mips.igen: Fix formatting of check_fpu calls.
1335
41774c9d
CD		 13362002-03-03 Chris Demetriou <cgd@broadcom.com>
1337
1338 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1339
4a0bd876
CD		 13402002-03-03 Chris Demetriou <cgd@broadcom.com>
1341
1342 * mips.igen: Remove whitespace at end of lines.
1343
09297648
CD		 13442002-03-02 Chris Demetriou <cgd@broadcom.com>
1345
1346 * mips.igen (loadstore_ea): New function to do effective
1347 address calculations.
1348 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1349 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1350 CACHE): Use loadstore_ea to do effective address computations.
1351
043b7057
CD		 13522002-03-02 Chris Demetriou <cgd@broadcom.com>
1353
1354 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1355 * mips.igen (LL, CxC1, MxC1): Likewise.
1356
c1e8ada4
CD		 13572002-03-02 Chris Demetriou <cgd@broadcom.com>
1358
1359 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1360 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1361 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1362 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1363 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1364 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1365 Don't split opcode fields by hand, use the opcode field values
1366 provided by igen.
1367
3e1dca16
CD		 13682002-03-01 Chris Demetriou <cgd@broadcom.com>
1369
1370 * mips.igen (do_divu): Fix spacing.
1371
1372 * mips.igen (do_dsllv): Move to be right before DSLLV,
1373 to match the rest of the do_<shift> functions.
1374
fff8d27d
CD		 13752002-03-01 Chris Demetriou <cgd@broadcom.com>
1376
1377 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1378 DSRL32, do_dsrlv): Trace inputs and results.
1379
0d3e762b
CD		 13802002-03-01 Chris Demetriou <cgd@broadcom.com>
1381
1382 * mips.igen (CACHE): Provide instruction-printing string.
1383
1384 * interp.c (signal_exception): Comment tokens after #endif.
1385
eb5fcf93
CD		 13862002-02-28 Chris Demetriou <cgd@broadcom.com>
1387
1388 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1389 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1390 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1391 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1392 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1393 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1394 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1395 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1396
bb22bd7d
CD		 13972002-02-28 Chris Demetriou <cgd@broadcom.com>
1398
1399 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1400 instruction-printing string.
1401 (LWU): Use '64' as the filter flag.
1402
91a177cf
CD		 14032002-02-28 Chris Demetriou <cgd@broadcom.com>
1404
1405 * mips.igen (SDXC1): Fix instruction-printing string.
1406
387f484a
CD		 14072002-02-28 Chris Demetriou <cgd@broadcom.com>
1408
1409 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1410 filter flags "32,f".
1411
3d81f391
CD		 14122002-02-27 Chris Demetriou <cgd@broadcom.com>
1413
1414 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1415 as the filter flag.
1416
af5107af
CD		 14172002-02-27 Chris Demetriou <cgd@broadcom.com>
1418
1419 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1420 add a comma) so that it more closely match the MIPS ISA
1421 documentation opcode partitioning.
1422 (PREF): Put useful names on opcode fields, and include
1423 instruction-printing string.
1424
ca971540
CD		 14252002-02-27 Chris Demetriou <cgd@broadcom.com>
1426
1427 * mips.igen (check_u64): New function which in the future will
1428 check whether 64-bit instructions are usable and signal an
1429 exception if not. Currently a no-op.
1430 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1431 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1432 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1433 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1434
1435 * mips.igen (check_fpu): New function which in the future will
1436 check whether FPU instructions are usable and signal an exception
1437 if not. Currently a no-op.
1438 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1439 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1440 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1441 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1442 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1443 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1444 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1445 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1446
1c47a468
CD		 14472002-02-27 Chris Demetriou <cgd@broadcom.com>
1448
1449 * mips.igen (do_load_left, do_load_right): Move to be immediately
1450 following do_load.
1451 (do_store_left, do_store_right): Move to be immediately following
1452 do_store.
1453
603a98e7
CD		 14542002-02-27 Chris Demetriou <cgd@broadcom.com>
1455
1456 * mips.igen (mipsV): New model name. Also, add it to
1457 all instructions and functions where it is appropriate.
1458
c5d00cc7
CD		 14592002-02-18 Chris Demetriou <cgd@broadcom.com>
1460
1461 * mips.igen: For all functions and instructions, list model
1462 names that support that instruction one per line.
1463
074e9cb8
CD		 14642002-02-11 Chris Demetriou <cgd@broadcom.com>
1465
1466 * mips.igen: Add some additional comments about supported
1467 models, and about which instructions go where.
1468 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1469 order as is used in the rest of the file.
1470
9805e229
CD		 14712002-02-11 Chris Demetriou <cgd@broadcom.com>
1472
1473 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1474 indicating that ALU32_END or ALU64_END are there to check
1475 for overflow.
1476 (DADD): Likewise, but also remove previous comment about
1477 overflow checking.
1478
f701dad2
CD		 14792002-02-10 Chris Demetriou <cgd@broadcom.com>
1480
1481 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1482 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1483 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1484 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1485 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1486 fields (i.e., add and move commas) so that they more closely
1487 match the MIPS ISA documentation opcode partitioning.
1488
14892002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1490
72f4393d
L		 1491 * mips.igen (ADDI): Print immediate value.
1492 (BREAK): Print code.
1493 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1494 (SLL): Print "nop" specially, and don't run the code
1495 that does the shift for the "nop" case.
20ae0098 1496
9e52972e
FF		 14972001-11-17 Fred Fish <fnf@redhat.com>
1498
1499 * sim-main.h (float_operation): Move enum declaration outside
1500 of _sim_cpu struct declaration.
1501
c0efbca4
JB		 15022001-04-12 Jim Blandy <jimb@redhat.com>
1503
1504 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1505 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1506 set of the FCSR.
1507 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1508 PENDING_FILL, and you can get the intended effect gracefully by
1509 calling PENDING_SCHED directly.
1510
fb891446
BE		 15112001-02-23 Ben Elliston <bje@redhat.com>
1512
1513 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1514 already defined elsewhere.
1515
8030f857
BE		 15162001-02-19 Ben Elliston <bje@redhat.com>
1517
1518 * sim-main.h (sim_monitor): Return an int.
1519 * interp.c (sim_monitor): Add return values.
1520 (signal_exception): Handle error conditions from sim_monitor.
1521
56b48a7a
CD		 15222001-02-08 Ben Elliston <bje@redhat.com>
1523
1524 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1525 (store_memory): Likewise, pass cia to sim_core_write*.
1526
d3ee60d9
FCE		 15272000-10-19 Frank Ch. Eigler <fche@redhat.com>
1528
1529 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1530 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1531
071da002
AC		 1532Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1533
1534 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1535 * Makefile.in: Don't delete *.igen when cleaning directory.
1536
a28c02cd
AC		 1537Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1538
1539 * m16.igen (break): Call SignalException not sim_engine_halt.
1540
80ee11fa
AC		 1541Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1542
1543 From Jason Eckhardt:
1544 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1545
673388c0
AC		 1546Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1547
1548 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1549
4c0deff4
NC		 15502000-05-24 Michael Hayes <mhayes@cygnus.com>
1551
1552 * mips.igen (do_dmultx): Fix typo.
1553
eb2d80b4
AC		 1554Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1555
1556 * configure: Regenerated to track ../common/aclocal.m4 changes.
1557
dd37a34b
AC		 1558Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1559
1560 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1561
4c0deff4
NC		 15622000-04-12 Frank Ch. Eigler <fche@redhat.com>
1563
1564 * sim-main.h (GPR_CLEAR): Define macro.
1565
e30db738
AC		 1566Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1567
1568 * interp.c (decode_coproc): Output long using %lx and not %s.
1569
cb7450ea
FCE		 15702000-03-21 Frank Ch. Eigler <fche@redhat.com>
1571
1572 * interp.c (sim_open): Sort & extend dummy memory regions for
1573 --board=jmr3904 for eCos.
1574
a3027dd7
FCE		 15752000-03-02 Frank Ch. Eigler <fche@redhat.com>
1576
1577 * configure: Regenerated.
1578
1579Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1580
1581 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1582 calls, conditional on the simulator being in verbose mode.
1583
dfcd3bfb
JM		 1584Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1585
1586 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1587 cache don't get ReservedInstruction traps.
1588
c2d11a7d
JM		 15891999-11-29 Mark Salter <msalter@cygnus.com>
1590
1591 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1592 to clear status bits in sdisr register. This is how the hardware works.
1593
1594 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1595 being used by cygmon.
1596
4ce44c66
JM		 15971999-11-11 Andrew Haley <aph@cygnus.com>
1598
1599 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1600 instructions.
1601
cff3e48b
JM		 1602Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1603
1604 * mips.igen (MULT): Correct previous mis-applied patch.
1605
d4f3574e
SS		 1606Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1607
1608 * mips.igen (delayslot32): Handle sequence like
1609 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1610 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1611 (MULT): Actually pass the third register...
1612
16131999-09-03 Mark Salter <msalter@cygnus.com>
1614
1615 * interp.c (sim_open): Added more memory aliases for additional
1616 hardware being touched by cygmon on jmr3904 board.
1617
1618Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1619
1620 * configure: Regenerated to track ../common/aclocal.m4 changes.
1621
a0b3c4fd
JM		 1622Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1623
1624 * interp.c (sim_store_register): Handle case where client - GDB -
1625 specifies that a 4 byte register is 8 bytes in size.
1626 (sim_fetch_register): Ditto.
72f4393d 1627
adf40b2e
JM		 16281999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1629
1630 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1631 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1632 (idt_monitor_base): Base address for IDT monitor traps.
1633 (pmon_monitor_base): Ditto for PMON.
1634 (lsipmon_monitor_base): Ditto for LSI PMON.
1635 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1636 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1637 (sim_firmware_command): New function.
1638 (mips_option_handler): Call it for OPTION_FIRMWARE.
1639 (sim_open): Allocate memory for idt_monitor region. If "--board"
1640 option was given, add no monitor by default. Add BREAK hooks only if
1641 monitors are also there.
72f4393d 1642
43e526b9
JM		 1643Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1644
1645 * interp.c (sim_monitor): Flush output before reading input.
1646
1647Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1648
1649 * tconfig.in (SIM_HANDLES_LMA): Always define.
1650
1651Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1652
1653 From Mark Salter <msalter@cygnus.com>:
1654 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1655 (sim_open): Add setup for BSP board.
1656
9846de1b
JM		 1657Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1658
1659 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1660 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1661 them as unimplemented.
1662
cd0fc7c3
SS		 16631999-05-08 Felix Lee <flee@cygnus.com>
1664
1665 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1666
7a292a7a
SS		 16671999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1668
1669 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1670
1671Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1672
1673 * configure.in: Any mips64vr5*-*-* target should have
1674 -DTARGET_ENABLE_FR=1.
1675 (default_endian): Any mips64vr*el-*-* target should default to
1676 LITTLE_ENDIAN.
1677 * configure: Re-generate.
1678
16791999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1680
1681 * mips.igen (ldl): Extend from _16_, not 32.
1682
1683Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1684
1685 * interp.c (sim_store_register): Force registers written to by GDB
1686 into an un-interpreted state.
1687
c906108c
SS		 16881999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1689
1690 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1691 CPU, start periodic background I/O polls.
72f4393d 1692 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1693
16941998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1695
1696 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1697
c906108c
SS		 1698Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1699
1700 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1701 case statement.
1702
17031998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1704
1705 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1706 (load_word): Call SIM_CORE_SIGNAL hook on error.
1707 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1708 starting. For exception dispatching, pass PC instead of NULL_CIA.
1709 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1710 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1711 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1712 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1713 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1714 * mips.igen (*): Replace memory-related SignalException* calls
1715 with references to SIM_CORE_SIGNAL hook.
72f4393d 1716
c906108c
SS		 1717 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1718 fix.
1719 * sim-main.c (*): Minor warning cleanups.
72f4393d 1720
c906108c
SS		 17211998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1722
1723 * m16.igen (DADDIU5): Correct type-o.
1724
1725Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1726
1727 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1728 variables.
1729
1730Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1731
1732 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1733 to include path.
1734 (interp.o): Add dependency on itable.h
1735 (oengine.c, gencode): Delete remaining references.
1736 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1737
c906108c 17381998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1739
c906108c
SS		 1740 * vr4run.c: New.
1741 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1742 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1743 tmp-run-hack) : New.
1744 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1745 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1746 Drop the "64" qualifier to get the HACK generator working.
1747 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1748 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1749 qualifier to get the hack generator working.
1750 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1751 (DSLL): Use do_dsll.
1752 (DSLLV): Use do_dsllv.
1753 (DSRA): Use do_dsra.
1754 (DSRL): Use do_dsrl.
1755 (DSRLV): Use do_dsrlv.
1756 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1757 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1758 get the HACK generator working.
1759 (MACC) Rename to get the HACK generator working.
1760 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1761
c906108c
SS		 17621998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1763
1764 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1765 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1766
c906108c
SS		 17671998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1768
1769 * mips/interp.c (DEBUG): Cleanups.
1770
17711998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1772
1773 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1774 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1775
c906108c
SS		 17761998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1777
1778 * interp.c (sim_close): Uninstall modules.
1779
1780Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1781
1782 * sim-main.h, interp.c (sim_monitor): Change to global
1783 function.
1784
1785Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1786
1787 * configure.in (vr4100): Only include vr4100 instructions in
1788 simulator.
1789 * configure: Re-generate.
1790 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1791
1792Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1793
1794 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1795 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1796 true alternative.
1797
1798 * configure.in (sim_default_gen, sim_use_gen): Replace with
1799 sim_gen.
1800 (--enable-sim-igen): Delete config option. Always using IGEN.
1801 * configure: Re-generate.
72f4393d 1802
c906108c
SS		 1803 * Makefile.in (gencode): Kill, kill, kill.
1804 * gencode.c: Ditto.
72f4393d 1805
c906108c
SS		 1806Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1807
1808 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1809 bit mips16 igen simulator.
1810 * configure: Re-generate.
1811
1812 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1813 as part of vr4100 ISA.
1814 * vr.igen: Mark all instructions as 64 bit only.
1815
1816Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1819 Pacify GCC.
1820
1821Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1822
1823 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1824 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1825 * configure: Re-generate.
1826
1827 * m16.igen (BREAK): Define breakpoint instruction.
1828 (JALX32): Mark instruction as mips16 and not r3900.
1829 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1830
1831 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1832
1833Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1834
1835 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1836 insn as a debug breakpoint.
1837
1838 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1839 pending.slot_size.
1840 (PENDING_SCHED): Clean up trace statement.
1841 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1842 (PENDING_FILL): Delay write by only one cycle.
1843 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1844
1845 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1846 of pending writes.
1847 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1848 32 & 64.
1849 (pending_tick): Move incrementing of index to FOR statement.
1850 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1851
c906108c
SS		 1852 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1853 build simulator.
1854 * configure: Re-generate.
72f4393d 1855
c906108c
SS		 1856 * interp.c (sim_engine_run OLD): Delete explicit call to
1857 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1858
c906108c
SS		 1859Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1860
1861 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1862 interrupt level number to match changed SignalExceptionInterrupt
1863 macro.
1864
1865Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1866
1867 * interp.c: #include "itable.h" if WITH_IGEN.
1868 (get_insn_name): New function.
1869 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1870 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1871
1872Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1873
1874 * configure: Rebuilt to inhale new common/aclocal.m4.
1875
1876Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1877
1878 * dv-tx3904sio.c: Include sim-assert.h.
1879
1880Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1881
1882 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1883 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1884 Reorganize target-specific sim-hardware checks.
1885 * configure: rebuilt.
1886 * interp.c (sim_open): For tx39 target boards, set
1887 OPERATING_ENVIRONMENT, add tx3904sio devices.
1888 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1889 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1890
c906108c
SS		 1891 * dv-tx3904irc.c: Compiler warning clean-up.
1892 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1893 frequent hw-trace messages.
1894
1895Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1896
1897 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1898
1899Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1900
1901 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1902
1903 * vr.igen: New file.
1904 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1905 * mips.igen: Define vr4100 model. Include vr.igen.
1906Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1907
1908 * mips.igen (check_mf_hilo): Correct check.
1909
1910Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1911
1912 * sim-main.h (interrupt_event): Add prototype.
1913
1914 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1915 register_ptr, register_value.
1916 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1917
1918 * sim-main.h (tracefh): Make extern.
1919
1920Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1921
1922 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1923 Reduce unnecessarily high timer event frequency.
c906108c 1924 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1925
c906108c
SS		 1926Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1927
1928 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1929 to allay warnings.
1930 (interrupt_event): Made non-static.
72f4393d 1931
c906108c
SS		 1932 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1933 interchange of configuration values for external vs. internal
1934 clock dividers.
72f4393d 1935
c906108c
SS		 1936Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1937
72f4393d 1938 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1939 simulator-reserved break instructions.
1940 * gencode.c (build_instruction): Ditto.
1941 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1942 reserved instructions now use exception vector, rather
c906108c
SS		 1943 than halting sim.
1944 * sim-main.h: Moved magic constants to here.
1945
1946Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1947
1948 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1949 register upon non-zero interrupt event level, clear upon zero
1950 event value.
1951 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1952 by passing zero event value.
1953 (*_io_{read,write}_buffer): Endianness fixes.
1954 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1955 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1956
1957 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1958 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1959
c906108c
SS		 1960Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1961
72f4393d 1962 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1963 and BigEndianCPU.
1964
1965Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1966
1967 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1968 parts.
1969 * configure: Update.
1970
1971Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
1972
1973 * dv-tx3904tmr.c: New file - implements tx3904 timer.
1974 * dv-tx3904{irc,cpu}.c: Mild reformatting.
1975 * configure.in: Include tx3904tmr in hw_device list.
1976 * configure: Rebuilt.
1977 * interp.c (sim_open): Instantiate three timer instances.
1978 Fix address typo of tx3904irc instance.
1979
1980Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
1981
1982 * interp.c (signal_exception): SystemCall exception now uses
1983 the exception vector.
1984
1985Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
1986
1987 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1988 to allay warnings.
1989
1990Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
1991
1992 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1993
1994Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
1995
1996 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1997
1998 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1999 sim-main.h. Declare a struct hw_descriptor instead of struct
2000 hw_device_descriptor.
2001
2002Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2003
2004 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2005 right bits and then re-align left hand bytes to correct byte
2006 lanes. Fix incorrect computation in do_store_left when loading
2007 bytes from second word.
2008
2009Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2010
2011 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2012 * interp.c (sim_open): Only create a device tree when HW is
2013 enabled.
2014
2015 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2016 * interp.c (signal_exception): Ditto.
2017
2018Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2019
2020 * gencode.c: Mark BEGEZALL as LIKELY.
2021
2022Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2023
2024 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2025 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2026
c906108c
SS		 2027Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2028
2029 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2030 modules. Recognize TX39 target with "mips*tx39" pattern.
2031 * configure: Rebuilt.
2032 * sim-main.h (*): Added many macros defining bits in
2033 TX39 control registers.
2034 (SignalInterrupt): Send actual PC instead of NULL.
2035 (SignalNMIReset): New exception type.
2036 * interp.c (board): New variable for future use to identify
2037 a particular board being simulated.
2038 (mips_option_handler,mips_options): Added "--board" option.
2039 (interrupt_event): Send actual PC.
2040 (sim_open): Make memory layout conditional on board setting.
2041 (signal_exception): Initial implementation of hardware interrupt
2042 handling. Accept another break instruction variant for simulator
2043 exit.
2044 (decode_coproc): Implement RFE instruction for TX39.
2045 (mips.igen): Decode RFE instruction as such.
2046 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2047 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2048 bbegin to implement memory map.
2049 * dv-tx3904cpu.c: New file.
2050 * dv-tx3904irc.c: New file.
2051
2052Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2053
2054 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2055
2056Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2057
2058 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2059 with calls to check_div_hilo.
2060
2061Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2062
2063 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2064 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2065 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2066 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2067 with calls to check_mult_hilo.
2068 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2069 with calls to check_div_hilo.
2070
2071Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2072
2073 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2074 Document a replacement.
2075
2076Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2077
2078 * interp.c (sim_monitor): Make mon_printf work.
2079
2080Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2081
2082 * sim-main.h (INSN_NAME): New arg `cpu'.
2083
2084Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2085
72f4393d 2086 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2087
2088Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2089
2090 * configure: Regenerated to track ../common/aclocal.m4 changes.
2091 * config.in: Ditto.
2092
2093Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2094
2095 * acconfig.h: New file.
2096 * configure.in: Reverted change of Apr 24; use sinclude again.
2097
2098Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2099
2100 * configure: Regenerated to track ../common/aclocal.m4 changes.
2101 * config.in: Ditto.
2102
2103Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2104
2105 * configure.in: Don't call sinclude.
2106
2107Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2108
2109 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2110
2111Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2112
2113 * mips.igen (ERET): Implement.
2114
2115 * interp.c (decode_coproc): Return sign-extended EPC.
2116
2117 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2118
2119 * interp.c (signal_exception): Do not ignore Trap.
2120 (signal_exception): On TRAP, restart at exception address.
2121 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2122 (signal_exception): Update.
2123 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2124 so that TRAP instructions are caught.
2125
2126Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2127
2128 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2129 contains HI/LO access history.
2130 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2131 (HIACCESS, LOACCESS): Delete, replace with
2132 (HIHISTORY, LOHISTORY): New macros.
2133 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2134
c906108c
SS		 2135 * gencode.c (build_instruction): Do not generate checks for
2136 correct HI/LO register usage.
2137
2138 * interp.c (old_engine_run): Delete checks for correct HI/LO
2139 register usage.
2140
2141 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2142 check_mf_cycles): New functions.
2143 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2144 do_divu, domultx, do_mult, do_multu): Use.
2145
2146 * tx.igen ("madd", "maddu"): Use.
72f4393d 2147
c906108c
SS		 2148Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2149
2150 * mips.igen (DSRAV): Use function do_dsrav.
2151 (SRAV): Use new function do_srav.
2152
2153 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2154 (B): Sign extend 11 bit immediate.
2155 (EXT-B*): Shift 16 bit immediate left by 1.
2156 (ADDIU*): Don't sign extend immediate value.
2157
2158Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2159
2160 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2161
2162 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2163 functions.
2164
2165 * mips.igen (delayslot32, nullify_next_insn): New functions.
2166 (m16.igen): Always include.
2167 (do_*): Add more tracing.
2168
2169 * m16.igen (delayslot16): Add NIA argument, could be called by a
2170 32 bit MIPS16 instruction.
72f4393d 2171
c906108c
SS		 2172 * interp.c (ifetch16): Move function from here.
2173 * sim-main.c (ifetch16): To here.
72f4393d 2174
c906108c
SS		 2175 * sim-main.c (ifetch16, ifetch32): Update to match current
2176 implementations of LH, LW.
2177 (signal_exception): Don't print out incorrect hex value of illegal
2178 instruction.
2179
2180Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2181
2182 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2183 instruction.
2184
2185 * m16.igen: Implement MIPS16 instructions.
72f4393d 2186
c906108c
SS		 2187 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2188 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2189 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2190 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2191 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2192 bodies of corresponding code from 32 bit insn to these. Also used
2193 by MIPS16 versions of functions.
72f4393d 2194
c906108c
SS		 2195 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2196 (IMEM16): Drop NR argument from macro.
2197
2198Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2199
2200 * Makefile.in (SIM_OBJS): Add sim-main.o.
2201
2202 * sim-main.h (address_translation, load_memory, store_memory,
2203 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2204 as INLINE_SIM_MAIN.
2205 (pr_addr, pr_uword64): Declare.
2206 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2207
c906108c
SS		 2208 * interp.c (address_translation, load_memory, store_memory,
2209 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2210 from here.
2211 * sim-main.c: To here. Fix compilation problems.
72f4393d 2212
c906108c
SS		 2213 * configure.in: Enable inlining.
2214 * configure: Re-config.
2215
2216Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2217
2218 * configure: Regenerated to track ../common/aclocal.m4 changes.
2219
2220Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2221
2222 * mips.igen: Include tx.igen.
2223 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2224 * tx.igen: New file, contains MADD and MADDU.
2225
2226 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2227 the hardwired constant `7'.
2228 (store_memory): Ditto.
2229 (LOADDRMASK): Move definition to sim-main.h.
2230
2231 mips.igen (MTC0): Enable for r3900.
2232 (ADDU): Add trace.
2233
2234 mips.igen (do_load_byte): Delete.
2235 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2236 do_store_right): New functions.
2237 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2238
2239 configure.in: Let the tx39 use igen again.
2240 configure: Update.
72f4393d 2241
c906108c
SS		 2242Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2243
2244 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2245 not an address sized quantity. Return zero for cache sizes.
2246
2247Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2248
2249 * mips.igen (r3900): r3900 does not support 64 bit integer
2250 operations.
2251
2252Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2253
2254 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2255 than igen one.
2256 * configure : Rebuild.
72f4393d 2257
c906108c
SS		 2258Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2259
2260 * configure: Regenerated to track ../common/aclocal.m4 changes.
2261
2262Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2263
2264 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2265
2266Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2267
2268 * configure: Regenerated to track ../common/aclocal.m4 changes.
2269 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2270
2271Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2272
2273 * configure: Regenerated to track ../common/aclocal.m4 changes.
2274
2275Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2276
2277 * interp.c (Max, Min): Comment out functions. Not yet used.
2278
2279Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2280
2281 * configure: Regenerated to track ../common/aclocal.m4 changes.
2282
2283Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2284
2285 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2286 configurable settings for stand-alone simulator.
72f4393d 2287
c906108c 2288 * configure.in: Added X11 search, just in case.
72f4393d 2289
c906108c
SS		 2290 * configure: Regenerated.
2291
2292Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2293
2294 * interp.c (sim_write, sim_read, load_memory, store_memory):
2295 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2296
2297Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2298
2299 * sim-main.h (GETFCC): Return an unsigned value.
2300
2301Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2302
2303 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2304 (DADD): Result destination is RD not RT.
2305
2306Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2307
2308 * sim-main.h (HIACCESS, LOACCESS): Always define.
2309
2310 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2311
2312 * interp.c (sim_info): Delete.
2313
2314Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2315
2316 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2317 (mips_option_handler): New argument `cpu'.
2318 (sim_open): Update call to sim_add_option_table.
2319
2320Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2321
2322 * mips.igen (CxC1): Add tracing.
2323
2324Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2325
2326 * sim-main.h (Max, Min): Declare.
2327
2328 * interp.c (Max, Min): New functions.
2329
2330 * mips.igen (BC1): Add tracing.
72f4393d 2331
c906108c 2332Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2333
c906108c 2334 * interp.c Added memory map for stack in vr4100
72f4393d 2335
c906108c
SS		 2336Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2337
2338 * interp.c (load_memory): Add missing "break"'s.
2339
2340Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2341
2342 * interp.c (sim_store_register, sim_fetch_register): Pass in
2343 length parameter. Return -1.
2344
2345Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2346
2347 * interp.c: Added hardware init hook, fixed warnings.
2348
2349Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2350
2351 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2352
2353Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * interp.c (ifetch16): New function.
2356
2357 * sim-main.h (IMEM32): Rename IMEM.
2358 (IMEM16_IMMED): Define.
2359 (IMEM16): Define.
2360 (DELAY_SLOT): Update.
72f4393d 2361
c906108c 2362 * m16run.c (sim_engine_run): New file.
72f4393d 2363
c906108c
SS		 2364 * m16.igen: All instructions except LB.
2365 (LB): Call do_load_byte.
2366 * mips.igen (do_load_byte): New function.
2367 (LB): Call do_load_byte.
2368
2369 * mips.igen: Move spec for insn bit size and high bit from here.
2370 * Makefile.in (tmp-igen, tmp-m16): To here.
2371
2372 * m16.dc: New file, decode mips16 instructions.
2373
2374 * Makefile.in (SIM_NO_ALL): Define.
2375 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2376
2377Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2378
2379 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2380 point unit to 32 bit registers.
2381 * configure: Re-generate.
2382
2383Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2384
2385 * configure.in (sim_use_gen): Make IGEN the default simulator
2386 generator for generic 32 and 64 bit mips targets.
2387 * configure: Re-generate.
2388
2389Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2390
2391 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2392 bitsize.
2393
2394 * interp.c (sim_fetch_register, sim_store_register): Read/write
2395 FGR from correct location.
2396 (sim_open): Set size of FGR's according to
2397 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2398
c906108c
SS		 2399 * sim-main.h (FGR): Store floating point registers in a separate
2400 array.
2401
2402Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2403
2404 * configure: Regenerated to track ../common/aclocal.m4 changes.
2405
2406Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2407
2408 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2409
2410 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2411
2412 * interp.c (pending_tick): New function. Deliver pending writes.
2413
2414 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2415 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2416 it can handle mixed sized quantites and single bits.
72f4393d 2417
c906108c
SS		 2418Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2419
2420 * interp.c (oengine.h): Do not include when building with IGEN.
2421 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2422 (sim_info): Ditto for PROCESSOR_64BIT.
2423 (sim_monitor): Replace ut_reg with unsigned_word.
2424 (*): Ditto for t_reg.
2425 (LOADDRMASK): Define.
2426 (sim_open): Remove defunct check that host FP is IEEE compliant,
2427 using software to emulate floating point.
2428 (value_fpr, ...): Always compile, was conditional on HASFPU.
2429
2430Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2431
2432 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2433 size.
2434
2435 * interp.c (SD, CPU): Define.
2436 (mips_option_handler): Set flags in each CPU.
2437 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2438 (sim_close): Do not clear STATE, deleted anyway.
2439 (sim_write, sim_read): Assume CPU zero's vm should be used for
2440 data transfers.
2441 (sim_create_inferior): Set the PC for all processors.
2442 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2443 argument.
2444 (mips16_entry): Pass correct nr of args to store_word, load_word.
2445 (ColdReset): Cold reset all cpu's.
2446 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2447 (sim_monitor, load_memory, store_memory, signal_exception): Use
2448 `CPU' instead of STATE_CPU.
2449
2450
2451 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2452 SD or CPU_.
72f4393d 2453
c906108c
SS		 2454 * sim-main.h (signal_exception): Add sim_cpu arg.
2455 (SignalException*): Pass both SD and CPU to signal_exception.
2456 * interp.c (signal_exception): Update.
72f4393d 2457
c906108c
SS		 2458 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2459 Ditto
2460 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2461 address_translation): Ditto
2462 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2463
c906108c
SS		 2464Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2465
2466 * configure: Regenerated to track ../common/aclocal.m4 changes.
2467
2468Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2469
2470 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2471
72f4393d 2472 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2473
2474 * sim-main.h (CPU_CIA): Delete.
2475 (SET_CIA, GET_CIA): Define
2476
2477Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2478
2479 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2480 regiser.
2481
2482 * configure.in (default_endian): Configure a big-endian simulator
2483 by default.
2484 * configure: Re-generate.
72f4393d 2485
c906108c
SS		 2486Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2487
2488 * configure: Regenerated to track ../common/aclocal.m4 changes.
2489
2490Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2491
2492 * interp.c (sim_monitor): Handle Densan monitor outbyte
2493 and inbyte functions.
2494
24951997-12-29 Felix Lee <flee@cygnus.com>
2496
2497 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2498
2499Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2500
2501 * Makefile.in (tmp-igen): Arrange for $zero to always be
2502 reset to zero after every instruction.
2503
2504Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2505
2506 * configure: Regenerated to track ../common/aclocal.m4 changes.
2507 * config.in: Ditto.
2508
2509Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2510
2511 * mips.igen (MSUB): Fix to work like MADD.
2512 * gencode.c (MSUB): Similarly.
2513
2514Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2515
2516 * configure: Regenerated to track ../common/aclocal.m4 changes.
2517
2518Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2519
2520 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2521
2522Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2523
2524 * sim-main.h (sim-fpu.h): Include.
2525
2526 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2527 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2528 using host independant sim_fpu module.
2529
2530Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2531
2532 * interp.c (signal_exception): Report internal errors with SIGABRT
2533 not SIGQUIT.
2534
2535 * sim-main.h (C0_CONFIG): New register.
2536 (signal.h): No longer include.
2537
2538 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2539
2540Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2541
2542 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2543
2544Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2545
2546 * mips.igen: Tag vr5000 instructions.
2547 (ANDI): Was missing mipsIV model, fix assembler syntax.
2548 (do_c_cond_fmt): New function.
2549 (C.cond.fmt): Handle mips I-III which do not support CC field
2550 separatly.
2551 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2552 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2553 in IV3.2 spec.
2554 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2555 vr5000 which saves LO in a GPR separatly.
72f4393d 2556
c906108c
SS		 2557 * configure.in (enable-sim-igen): For vr5000, select vr5000
2558 specific instructions.
2559 * configure: Re-generate.
72f4393d 2560
c906108c
SS		 2561Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562
2563 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2564
2565 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2566 fmt_uninterpreted_64 bit cases to switch. Convert to
2567 fmt_formatted,
2568
2569 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2570
2571 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2572 as specified in IV3.2 spec.
2573 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2574
2575Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2578 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2579 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2580 PENDING_FILL versions of instructions. Simplify.
2581 (X): New function.
2582 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2583 instructions.
2584 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2585 a signed value.
2586 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2587
c906108c
SS		 2588 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2589 global.
2590 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2591
2592Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * gencode.c (build_mips16_operands): Replace IPC with cia.
2595
2596 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2597 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2598 IPC to `cia'.
2599 (UndefinedResult): Replace function with macro/function
2600 combination.
2601 (sim_engine_run): Don't save PC in IPC.
2602
2603 * sim-main.h (IPC): Delete.
2604
2605
2606 * interp.c (signal_exception, store_word, load_word,
2607 address_translation, load_memory, store_memory, cache_op,
2608 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2609 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2610 current instruction address - cia - argument.
2611 (sim_read, sim_write): Call address_translation directly.
2612 (sim_engine_run): Rename variable vaddr to cia.
2613 (signal_exception): Pass cia to sim_monitor
72f4393d 2614
c906108c
SS		 2615 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2616 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2617 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2618
2619 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2620 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2621 SIM_ASSERT.
72f4393d 2622
c906108c
SS		 2623 * interp.c (signal_exception): Pass restart address to
2624 sim_engine_restart.
2625
2626 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2627 idecode.o): Add dependency.
2628
2629 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2630 Delete definitions
2631 (DELAY_SLOT): Update NIA not PC with branch address.
2632 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2633
2634 * mips.igen: Use CIA not PC in branch calculations.
2635 (illegal): Call SignalException.
2636 (BEQ, ADDIU): Fix assembler.
2637
2638Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2639
2640 * m16.igen (JALX): Was missing.
2641
2642 * configure.in (enable-sim-igen): New configuration option.
2643 * configure: Re-generate.
72f4393d 2644
c906108c
SS		 2645 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2646
2647 * interp.c (load_memory, store_memory): Delete parameter RAW.
2648 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2649 bypassing {load,store}_memory.
2650
2651 * sim-main.h (ByteSwapMem): Delete definition.
2652
2653 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2654
2655 * interp.c (sim_do_command, sim_commands): Delete mips specific
2656 commands. Handled by module sim-options.
72f4393d 2657
c906108c
SS		 2658 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2659 (WITH_MODULO_MEMORY): Define.
2660
2661 * interp.c (sim_info): Delete code printing memory size.
2662
2663 * interp.c (mips_size): Nee sim_size, delete function.
2664 (power2): Delete.
2665 (monitor, monitor_base, monitor_size): Delete global variables.
2666 (sim_open, sim_close): Delete code creating monitor and other
2667 memory regions. Use sim-memopts module, via sim_do_commandf, to
2668 manage memory regions.
2669 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2670
c906108c
SS		 2671 * interp.c (address_translation): Delete all memory map code
2672 except line forcing 32 bit addresses.
2673
2674Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2675
2676 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2677 trace options.
2678
2679 * interp.c (logfh, logfile): Delete globals.
2680 (sim_open, sim_close): Delete code opening & closing log file.
2681 (mips_option_handler): Delete -l and -n options.
2682 (OPTION mips_options): Ditto.
2683
2684 * interp.c (OPTION mips_options): Rename option trace to dinero.
2685 (mips_option_handler): Update.
2686
2687Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2688
2689 * interp.c (fetch_str): New function.
2690 (sim_monitor): Rewrite using sim_read & sim_write.
2691 (sim_open): Check magic number.
2692 (sim_open): Write monitor vectors into memory using sim_write.
2693 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2694 (sim_read, sim_write): Simplify - transfer data one byte at a
2695 time.
2696 (load_memory, store_memory): Clarify meaning of parameter RAW.
2697
2698 * sim-main.h (isHOST): Defete definition.
2699 (isTARGET): Mark as depreciated.
2700 (address_translation): Delete parameter HOST.
2701
2702 * interp.c (address_translation): Delete parameter HOST.
2703
2704Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2705
72f4393d 2706 * mips.igen:
c906108c
SS		 2707
2708 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2709 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2710
2711Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712
2713 * mips.igen: Add model filter field to records.
2714
2715Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2716
2717 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2718
c906108c
SS		 2719 interp.c (sim_engine_run): Do not compile function sim_engine_run
2720 when WITH_IGEN == 1.
2721
2722 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2723 target architecture.
2724
2725 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2726 igen. Replace with configuration variables sim_igen_flags /
2727 sim_m16_flags.
2728
2729 * m16.igen: New file. Copy mips16 insns here.
2730 * mips.igen: From here.
2731
2732Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2733
2734 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2735 to top.
2736 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2737
2738Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2739
2740 * gencode.c (build_instruction): Follow sim_write's lead in using
2741 BigEndianMem instead of !ByteSwapMem.
2742
2743Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744
2745 * configure.in (sim_gen): Dependent on target, select type of
2746 generator. Always select old style generator.
2747
2748 configure: Re-generate.
2749
2750 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2751 targets.
2752 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2753 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2754 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2755 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2756 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2757
c906108c
SS		 2758Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2759
2760 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2761
2762 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2763 CURRENT_FLOATING_POINT instead.
2764
2765 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2766 (address_translation): Raise exception InstructionFetch when
2767 translation fails and isINSTRUCTION.
72f4393d 2768
c906108c
SS		 2769 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2770 sim_engine_run): Change type of of vaddr and paddr to
2771 address_word.
2772 (address_translation, prefetch, load_memory, store_memory,
2773 cache_op): Change type of vAddr and pAddr to address_word.
2774
2775 * gencode.c (build_instruction): Change type of vaddr and paddr to
2776 address_word.
2777
2778Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2779
2780 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2781 macro to obtain result of ALU op.
2782
2783Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2784
2785 * interp.c (sim_info): Call profile_print.
2786
2787Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2788
2789 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2790
2791 * sim-main.h (WITH_PROFILE): Do not define, defined in
2792 common/sim-config.h. Use sim-profile module.
2793 (simPROFILE): Delete defintion.
2794
2795 * interp.c (PROFILE): Delete definition.
2796 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2797 (sim_close): Delete code writing profile histogram.
2798 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2799 Delete.
2800 (sim_engine_run): Delete code profiling the PC.
2801
2802Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2803
2804 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2805
2806 * interp.c (sim_monitor): Make register pointers of type
2807 unsigned_word*.
2808
2809 * sim-main.h: Make registers of type unsigned_word not
2810 signed_word.
2811
2812Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2813
2814 * interp.c (sync_operation): Rename from SyncOperation, make
2815 global, add SD argument.
2816 (prefetch): Rename from Prefetch, make global, add SD argument.
2817 (decode_coproc): Make global.
2818
2819 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2820
2821 * gencode.c (build_instruction): Generate DecodeCoproc not
2822 decode_coproc calls.
2823
2824 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2825 (SizeFGR): Move to sim-main.h
2826 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2827 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2828 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2829 sim-main.h.
2830 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2831 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2832 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2833 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2834 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2835 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2836
c906108c
SS		 2837 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2838 exception.
2839 (sim-alu.h): Include.
2840 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2841 (sim_cia): Typedef to instruction_address.
72f4393d 2842
c906108c
SS		 2843Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * Makefile.in (interp.o): Rename generated file engine.c to
2846 oengine.c.
72f4393d 2847
c906108c 2848 * interp.c: Update.
72f4393d 2849
c906108c
SS		 2850Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2851
2852 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2853
c906108c
SS		 2854Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2855
2856 * gencode.c (build_instruction): For "FPSQRT", output correct
2857 number of arguments to Recip.
72f4393d 2858
c906108c
SS		 2859Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2860
2861 * Makefile.in (interp.o): Depends on sim-main.h
2862
2863 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2864
2865 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2866 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2867 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2868 STATE, DSSTATE): Define
2869 (GPR, FGRIDX, ..): Define.
2870
2871 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2872 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2873 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2874
c906108c 2875 * interp.c: Update names to match defines from sim-main.h
72f4393d 2876
c906108c
SS		 2877Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2878
2879 * interp.c (sim_monitor): Add SD argument.
2880 (sim_warning): Delete. Replace calls with calls to
2881 sim_io_eprintf.
2882 (sim_error): Delete. Replace calls with sim_io_error.
2883 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2884 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2885 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2886 argument.
2887 (mips_size): Rename from sim_size. Add SD argument.
2888
2889 * interp.c (simulator): Delete global variable.
2890 (callback): Delete global variable.
2891 (mips_option_handler, sim_open, sim_write, sim_read,
2892 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2893 sim_size,sim_monitor): Use sim_io_* not callback->*.
2894 (sim_open): ZALLOC simulator struct.
2895 (PROFILE): Do not define.
2896
2897Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2898
2899 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2900 support.h with corresponding code.
2901
2902 * sim-main.h (word64, uword64), support.h: Move definition to
2903 sim-main.h.
2904 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2905
2906 * support.h: Delete
2907 * Makefile.in: Update dependencies
2908 * interp.c: Do not include.
72f4393d 2909
c906108c
SS		 2910Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2911
2912 * interp.c (address_translation, load_memory, store_memory,
2913 cache_op): Rename to from AddressTranslation et.al., make global,
2914 add SD argument
72f4393d 2915
c906108c
SS		 2916 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2917 CacheOp): Define.
72f4393d 2918
c906108c
SS		 2919 * interp.c (SignalException): Rename to signal_exception, make
2920 global.
2921
2922 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2923
c906108c
SS		 2924 * sim-main.h (SignalException, SignalExceptionInterrupt,
2925 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2926 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2927 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2928 Define.
72f4393d 2929
c906108c 2930 * interp.c, support.h: Use.
72f4393d 2931
c906108c
SS		 2932Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2933
2934 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2935 to value_fpr / store_fpr. Add SD argument.
2936 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2937 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2938
2939 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2940
c906108c
SS		 2941Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2942
2943 * interp.c (sim_engine_run): Check consistency between configure
2944 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2945 and HASFPU.
2946
2947 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2948 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2949 (mips_endian): Configure WITH_TARGET_ENDIAN.
2950 * configure: Update.
2951
2952Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2953
2954 * configure: Regenerated to track ../common/aclocal.m4 changes.
2955
2956Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2957
2958 * configure: Regenerated.
2959
2960Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2961
2962 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2963
2964Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2965
2966 * gencode.c (print_igen_insn_models): Assume certain architectures
2967 include all mips* instructions.
2968 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2969 instruction.
2970
2971 * Makefile.in (tmp.igen): Add target. Generate igen input from
2972 gencode file.
2973
2974 * gencode.c (FEATURE_IGEN): Define.
2975 (main): Add --igen option. Generate output in igen format.
2976 (process_instructions): Format output according to igen option.
2977 (print_igen_insn_format): New function.
2978 (print_igen_insn_models): New function.
2979 (process_instructions): Only issue warnings and ignore
2980 instructions when no FEATURE_IGEN.
2981
2982Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
2983
2984 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2985 MIPS targets.
2986
2987Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
2988
2989 * configure: Regenerated to track ../common/aclocal.m4 changes.
2990
2991Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
2992
2993 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2994 SIM_RESERVED_BITS): Delete, moved to common.
2995 (SIM_EXTRA_CFLAGS): Update.
72f4393d 2996
c906108c
SS		 2997Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2998
2999 * configure.in: Configure non-strict memory alignment.
3000 * configure: Regenerated to track ../common/aclocal.m4 changes.
3001
3002Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3003
3004 * configure: Regenerated to track ../common/aclocal.m4 changes.
3005
3006Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3007
3008 * gencode.c (SDBBP,DERET): Added (3900) insns.
3009 (RFE): Turn on for 3900.
3010 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3011 (dsstate): Made global.
3012 (SUBTARGET_R3900): Added.
3013 (CANCELDELAYSLOT): New.
3014 (SignalException): Ignore SystemCall rather than ignore and
3015 terminate. Add DebugBreakPoint handling.
3016 (decode_coproc): New insns RFE, DERET; and new registers Debug
3017 and DEPC protected by SUBTARGET_R3900.
3018 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3019 bits explicitly.
3020 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3021 * configure: Update.
c906108c
SS		 3022
3023Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3024
3025 * gencode.c: Add r3900 (tx39).
72f4393d 3026
c906108c
SS		 3027
3028Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3029
3030 * gencode.c (build_instruction): Don't need to subtract 4 for
3031 JALR, just 2.
3032
3033Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3034
3035 * interp.c: Correct some HASFPU problems.
3036
3037Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3038
3039 * configure: Regenerated to track ../common/aclocal.m4 changes.
3040
3041Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3042
3043 * interp.c (mips_options): Fix samples option short form, should
3044 be `x'.
3045
3046Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3047
3048 * interp.c (sim_info): Enable info code. Was just returning.
3049
3050Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3051
3052 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3053 MFC0.
3054
3055Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3056
3057 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3058 constants.
3059 (build_instruction): Ditto for LL.
3060
3061Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3062
3063 * configure: Regenerated to track ../common/aclocal.m4 changes.
3064
3065Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3066
3067 * configure: Regenerated to track ../common/aclocal.m4 changes.
3068 * config.in: Ditto.
3069
3070Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3071
3072 * interp.c (sim_open): Add call to sim_analyze_program, update
3073 call to sim_config.
3074
3075Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3076
3077 * interp.c (sim_kill): Delete.
3078 (sim_create_inferior): Add ABFD argument. Set PC from same.
3079 (sim_load): Move code initializing trap handlers from here.
3080 (sim_open): To here.
3081 (sim_load): Delete, use sim-hload.c.
3082
3083 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3084
3085Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3086
3087 * configure: Regenerated to track ../common/aclocal.m4 changes.
3088 * config.in: Ditto.
3089
3090Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3091
3092 * interp.c (sim_open): Add ABFD argument.
3093 (sim_load): Move call to sim_config from here.
3094 (sim_open): To here. Check return status.
3095
3096Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3097
c906108c
SS		 3098 * gencode.c (build_instruction): Two arg MADD should
3099 not assign result to $0.
72f4393d 3100
c906108c
SS		 3101Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3102
3103 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3104 * sim/mips/configure.in: Regenerate.
3105
3106Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3107
3108 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3109 signed8, unsigned8 et.al. types.
3110
3111 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3112 hosts when selecting subreg.
3113
3114Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3115
3116 * interp.c (sim_engine_run): Reset the ZERO register to zero
3117 regardless of FEATURE_WARN_ZERO.
3118 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3119
3120Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3121
3122 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3123 (SignalException): For BreakPoints ignore any mode bits and just
3124 save the PC.
3125 (SignalException): Always set the CAUSE register.
3126
3127Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3130 exception has been taken.
3131
3132 * interp.c: Implement the ERET and mt/f sr instructions.
3133
3134Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3135
3136 * interp.c (SignalException): Don't bother restarting an
3137 interrupt.
3138
3139Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3140
3141 * interp.c (SignalException): Really take an interrupt.
3142 (interrupt_event): Only deliver interrupts when enabled.
3143
3144Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3145
3146 * interp.c (sim_info): Only print info when verbose.
3147 (sim_info) Use sim_io_printf for output.
72f4393d 3148
c906108c
SS		 3149Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3150
3151 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3152 mips architectures.
3153
3154Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3155
3156 * interp.c (sim_do_command): Check for common commands if a
3157 simulator specific command fails.
3158
3159Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3160
3161 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3162 and simBE when DEBUG is defined.
3163
3164Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3165
3166 * interp.c (interrupt_event): New function. Pass exception event
3167 onto exception handler.
3168
3169 * configure.in: Check for stdlib.h.
3170 * configure: Regenerate.
3171
3172 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3173 variable declaration.
3174 (build_instruction): Initialize memval1.
3175 (build_instruction): Add UNUSED attribute to byte, bigend,
3176 reverse.
3177 (build_operands): Ditto.
3178
3179 * interp.c: Fix GCC warnings.
3180 (sim_get_quit_code): Delete.
3181
3182 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3183 * Makefile.in: Ditto.
3184 * configure: Re-generate.
72f4393d 3185
c906108c
SS		 3186 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3187
3188Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3189
3190 * interp.c (mips_option_handler): New function parse argumes using
3191 sim-options.
3192 (myname): Replace with STATE_MY_NAME.
3193 (sim_open): Delete check for host endianness - performed by
3194 sim_config.
3195 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3196 (sim_open): Move much of the initialization from here.
3197 (sim_load): To here. After the image has been loaded and
3198 endianness set.
3199 (sim_open): Move ColdReset from here.
3200 (sim_create_inferior): To here.
3201 (sim_open): Make FP check less dependant on host endianness.
3202
3203 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3204 run.
3205 * interp.c (sim_set_callbacks): Delete.
3206
3207 * interp.c (membank, membank_base, membank_size): Replace with
3208 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3209 (sim_open): Remove call to callback->init. gdb/run do this.
3210
3211 * interp.c: Update
3212
3213 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3214
3215 * interp.c (big_endian_p): Delete, replaced by
3216 current_target_byte_order.
3217
3218Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3219
3220 * interp.c (host_read_long, host_read_word, host_swap_word,
3221 host_swap_long): Delete. Using common sim-endian.
3222 (sim_fetch_register, sim_store_register): Use H2T.
3223 (pipeline_ticks): Delete. Handled by sim-events.
3224 (sim_info): Update.
3225 (sim_engine_run): Update.
3226
3227Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3228
3229 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3230 reason from here.
3231 (SignalException): To here. Signal using sim_engine_halt.
3232 (sim_stop_reason): Delete, moved to common.
72f4393d 3233
c906108c
SS		 3234Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3235
3236 * interp.c (sim_open): Add callback argument.
3237 (sim_set_callbacks): Delete SIM_DESC argument.
3238 (sim_size): Ditto.
3239
3240Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3241
3242 * Makefile.in (SIM_OBJS): Add common modules.
3243
3244 * interp.c (sim_set_callbacks): Also set SD callback.
3245 (set_endianness, xfer_*, swap_*): Delete.
3246 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3247 Change to functions using sim-endian macros.
3248 (control_c, sim_stop): Delete, use common version.
3249 (simulate): Convert into.
3250 (sim_engine_run): This function.
3251 (sim_resume): Delete.
72f4393d 3252
c906108c
SS		 3253 * interp.c (simulation): New variable - the simulator object.
3254 (sim_kind): Delete global - merged into simulation.
3255 (sim_load): Cleanup. Move PC assignment from here.
3256 (sim_create_inferior): To here.
3257
3258 * sim-main.h: New file.
3259 * interp.c (sim-main.h): Include.
72f4393d 3260
c906108c
SS		 3261Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3262
3263 * configure: Regenerated to track ../common/aclocal.m4 changes.
3264
3265Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3266
3267 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3268
3269Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3270
72f4393d
L		 3271 * gencode.c (build_instruction): DIV instructions: check
3272 for division by zero and integer overflow before using
c906108c
SS		 3273 host's division operation.
3274
3275Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3276
3277 * Makefile.in (SIM_OBJS): Add sim-load.o.
3278 * interp.c: #include bfd.h.
3279 (target_byte_order): Delete.
3280 (sim_kind, myname, big_endian_p): New static locals.
3281 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3282 after argument parsing. Recognize -E arg, set endianness accordingly.
3283 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3284 load file into simulator. Set PC from bfd.
3285 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3286 (set_endianness): Use big_endian_p instead of target_byte_order.
3287
3288Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3289
3290 * interp.c (sim_size): Delete prototype - conflicts with
3291 definition in remote-sim.h. Correct definition.
3292
3293Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3294
3295 * configure: Regenerated to track ../common/aclocal.m4 changes.
3296 * config.in: Ditto.
3297
3298Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3299
3300 * interp.c (sim_open): New arg `kind'.
3301
3302 * configure: Regenerated to track ../common/aclocal.m4 changes.
3303
3304Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3305
3306 * configure: Regenerated to track ../common/aclocal.m4 changes.
3307
3308Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3309
3310 * interp.c (sim_open): Set optind to 0 before calling getopt.
3311
3312Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3313
3314 * configure: Regenerated to track ../common/aclocal.m4 changes.
3315
3316Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3317
3318 * interp.c : Replace uses of pr_addr with pr_uword64
3319 where the bit length is always 64 independent of SIM_ADDR.
3320 (pr_uword64) : added.
3321
3322Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3323
3324 * configure: Re-generate.
3325
3326Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3327
3328 * configure: Regenerate to track ../common/aclocal.m4 changes.
3329
3330Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3331
3332 * interp.c (sim_open): New SIM_DESC result. Argument is now
3333 in argv form.
3334 (other sim_*): New SIM_DESC argument.
3335
3336Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3337
3338 * interp.c: Fix printing of addresses for non-64-bit targets.
3339 (pr_addr): Add function to print address based on size.
3340
3341Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3342
3343 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3344
3345Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3346
3347 * gencode.c (build_mips16_operands): Correct computation of base
3348 address for extended PC relative instruction.
3349
3350Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3351
3352 * interp.c (mips16_entry): Add support for floating point cases.
3353 (SignalException): Pass floating point cases to mips16_entry.
3354 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3355 registers.
3356 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3357 or fmt_word.
3358 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3359 and then set the state to fmt_uninterpreted.
3360 (COP_SW): Temporarily set the state to fmt_word while calling
3361 ValueFPR.
3362
3363Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3364
3365 * gencode.c (build_instruction): The high order may be set in the
3366 comparison flags at any ISA level, not just ISA 4.
3367
3368Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3369
3370 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3371 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3372 * configure.in: sinclude ../common/aclocal.m4.
3373 * configure: Regenerated.
3374
3375Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3376
3377 * configure: Rebuild after change to aclocal.m4.
3378
3379Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3380
3381 * configure configure.in Makefile.in: Update to new configure
3382 scheme which is more compatible with WinGDB builds.
3383 * configure.in: Improve comment on how to run autoconf.
3384 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3385 * Makefile.in: Use autoconf substitution to install common
3386 makefile fragment.
3387
3388Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3389
3390 * gencode.c (build_instruction): Use BigEndianCPU instead of
3391 ByteSwapMem.
3392
3393Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3394
3395 * interp.c (sim_monitor): Make output to stdout visible in
3396 wingdb's I/O log window.
3397
3398Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3399
3400 * support.h: Undo previous change to SIGTRAP
3401 and SIGQUIT values.
3402
3403Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3404
3405 * interp.c (store_word, load_word): New static functions.
3406 (mips16_entry): New static function.
3407 (SignalException): Look for mips16 entry and exit instructions.
3408 (simulate): Use the correct index when setting fpr_state after
3409 doing a pending move.
3410
3411Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3412
3413 * interp.c: Fix byte-swapping code throughout to work on
3414 both little- and big-endian hosts.
3415
3416Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3417
3418 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3419 with gdb/config/i386/xm-windows.h.
3420
3421Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3422
3423 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3424 that messes up arithmetic shifts.
3425
3426Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3427
3428 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3429 SIGTRAP and SIGQUIT for _WIN32.
3430
3431Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3432
3433 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3434 force a 64 bit multiplication.
3435 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3436 destination register is 0, since that is the default mips16 nop
3437 instruction.
3438
3439Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3440
3441 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3442 (build_endian_shift): Don't check proc64.
3443 (build_instruction): Always set memval to uword64. Cast op2 to
3444 uword64 when shifting it left in memory instructions. Always use
3445 the same code for stores--don't special case proc64.
3446
3447 * gencode.c (build_mips16_operands): Fix base PC value for PC
3448 relative operands.
3449 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3450 jal instruction.
3451 * interp.c (simJALDELAYSLOT): Define.
3452 (JALDELAYSLOT): Define.
3453 (INDELAYSLOT, INJALDELAYSLOT): Define.
3454 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3455
3456Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3457
3458 * interp.c (sim_open): add flush_cache as a PMON routine
3459 (sim_monitor): handle flush_cache by ignoring it
3460
3461Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3462
3463 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3464 BigEndianMem.
3465 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3466 (BigEndianMem): Rename to ByteSwapMem and change sense.
3467 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3468 BigEndianMem references to !ByteSwapMem.
3469 (set_endianness): New function, with prototype.
3470 (sim_open): Call set_endianness.
3471 (sim_info): Use simBE instead of BigEndianMem.
3472 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3473 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3474 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3475 ifdefs, keeping the prototype declaration.
3476 (swap_word): Rewrite correctly.
3477 (ColdReset): Delete references to CONFIG. Delete endianness related
3478 code; moved to set_endianness.
72f4393d 3479
c906108c
SS		 3480Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3481
3482 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3483 * interp.c (CHECKHILO): Define away.
3484 (simSIGINT): New macro.
3485 (membank_size): Increase from 1MB to 2MB.
3486 (control_c): New function.
3487 (sim_resume): Rename parameter signal to signal_number. Add local
3488 variable prev. Call signal before and after simulate.
3489 (sim_stop_reason): Add simSIGINT support.
3490 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3491 functions always.
3492 (sim_warning): Delete call to SignalException. Do call printf_filtered
3493 if logfh is NULL.
3494 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3495 a call to sim_warning.
3496
3497Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3498
3499 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3500 16 bit instructions.
3501
3502Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3503
3504 Add support for mips16 (16 bit MIPS implementation):
3505 * gencode.c (inst_type): Add mips16 instruction encoding types.
3506 (GETDATASIZEINSN): Define.
3507 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3508 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3509 mtlo.
3510 (MIPS16_DECODE): New table, for mips16 instructions.
3511 (bitmap_val): New static function.
3512 (struct mips16_op): Define.
3513 (mips16_op_table): New table, for mips16 operands.
3514 (build_mips16_operands): New static function.
3515 (process_instructions): If PC is odd, decode a mips16
3516 instruction. Break out instruction handling into new
3517 build_instruction function.
3518 (build_instruction): New static function, broken out of
3519 process_instructions. Check modifiers rather than flags for SHIFT
3520 bit count and m[ft]{hi,lo} direction.
3521 (usage): Pass program name to fprintf.
3522 (main): Remove unused variable this_option_optind. Change
3523 ``*loptarg++'' to ``loptarg++''.
3524 (my_strtoul): Parenthesize && within ||.
3525 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3526 (simulate): If PC is odd, fetch a 16 bit instruction, and
3527 increment PC by 2 rather than 4.
3528 * configure.in: Add case for mips16*-*-*.
3529 * configure: Rebuild.
3530
3531Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3532
3533 * interp.c: Allow -t to enable tracing in standalone simulator.
3534 Fix garbage output in trace file and error messages.
3535
3536Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3537
3538 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3539 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3540 * configure.in: Simplify using macros in ../common/aclocal.m4.
3541 * configure: Regenerated.
3542 * tconfig.in: New file.
3543
3544Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3545
3546 * interp.c: Fix bugs in 64-bit port.
3547 Use ansi function declarations for msvc compiler.
3548 Initialize and test file pointer in trace code.
3549 Prevent duplicate definition of LAST_EMED_REGNUM.
3550
3551Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3552
3553 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3554
3555Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3556
3557 * interp.c (SignalException): Check for explicit terminating
3558 breakpoint value.
3559 * gencode.c: Pass instruction value through SignalException()
3560 calls for Trap, Breakpoint and Syscall.
3561
3562Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3563
3564 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3565 only used on those hosts that provide it.
3566 * configure.in: Add sqrt() to list of functions to be checked for.
3567 * config.in: Re-generated.
3568 * configure: Re-generated.
3569
3570Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3571
3572 * gencode.c (process_instructions): Call build_endian_shift when
3573 expanding STORE RIGHT, to fix swr.
3574 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3575 clear the high bits.
3576 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3577 Fix float to int conversions to produce signed values.
3578
3579Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3580
3581 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3582 (process_instructions): Correct handling of nor instruction.
3583 Correct shift count for 32 bit shift instructions. Correct sign
3584 extension for arithmetic shifts to not shift the number of bits in
3585 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3586 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3587 Fix madd.
3588 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3589 It's OK to have a mult follow a mult. What's not OK is to have a
3590 mult follow an mfhi.
3591 (Convert): Comment out incorrect rounding code.
3592
3593Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3594
3595 * interp.c (sim_monitor): Improved monitor printf
3596 simulation. Tidied up simulator warnings, and added "--log" option
3597 for directing warning message output.
3598 * gencode.c: Use sim_warning() rather than WARNING macro.
3599
3600Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3601
3602 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3603 getopt1.o, rather than on gencode.c. Link objects together.
3604 Don't link against -liberty.
3605 (gencode.o, getopt.o, getopt1.o): New targets.
3606 * gencode.c: Include <ctype.h> and "ansidecl.h".
3607 (AND): Undefine after including "ansidecl.h".
3608 (ULONG_MAX): Define if not defined.
3609 (OP_*): Don't define macros; now defined in opcode/mips.h.
3610 (main): Call my_strtoul rather than strtoul.
3611 (my_strtoul): New static function.
3612
3613Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3614
3615 * gencode.c (process_instructions): Generate word64 and uword64
3616 instead of `long long' and `unsigned long long' data types.
3617 * interp.c: #include sysdep.h to get signals, and define default
3618 for SIGBUS.
3619 * (Convert): Work around for Visual-C++ compiler bug with type
3620 conversion.
3621 * support.h: Make things compile under Visual-C++ by using
3622 __int64 instead of `long long'. Change many refs to long long
3623 into word64/uword64 typedefs.
3624
3625Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3626
72f4393d
L		 3627 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3628 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3629 (docdir): Removed.
3630 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3631 (AC_PROG_INSTALL): Added.
c906108c 3632 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3633 * configure: Rebuilt.
3634
c906108c
SS		 3635Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3636
3637 * configure.in: Define @SIMCONF@ depending on mips target.
3638 * configure: Rebuild.
3639 * Makefile.in (run): Add @SIMCONF@ to control simulator
3640 construction.
3641 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3642 * interp.c: Remove some debugging, provide more detailed error
3643 messages, update memory accesses to use LOADDRMASK.
72f4393d 3644
c906108c
SS		 3645Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3646
3647 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3648 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3649 stamp-h.
3650 * configure: Rebuild.
3651 * config.in: New file, generated by autoheader.
3652 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3653 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3654 HAVE_ANINT and HAVE_AINT, as appropriate.
3655 * Makefile.in (run): Use @LIBS@ rather than -lm.
3656 (interp.o): Depend upon config.h.
3657 (Makefile): Just rebuild Makefile.
3658 (clean): Remove stamp-h.
3659 (mostlyclean): Make the same as clean, not as distclean.
3660 (config.h, stamp-h): New targets.
3661
3662Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3663
3664 * interp.c (ColdReset): Fix boolean test. Make all simulator
3665 globals static.
3666
3667Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3668
3669 * interp.c (xfer_direct_word, xfer_direct_long,
3670 swap_direct_word, swap_direct_long, xfer_big_word,
3671 xfer_big_long, xfer_little_word, xfer_little_long,
3672 swap_word,swap_long): Added.
3673 * interp.c (ColdReset): Provide function indirection to
3674 host<->simulated_target transfer routines.
3675 * interp.c (sim_store_register, sim_fetch_register): Updated to
3676 make use of indirected transfer routines.
3677
3678Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3679
3680 * gencode.c (process_instructions): Ensure FP ABS instruction
3681 recognised.
3682 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3683 system call support.
3684
3685Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3686
3687 * interp.c (sim_do_command): Complain if callback structure not
3688 initialised.
3689
3690Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3691
3692 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3693 support for Sun hosts.
3694 * Makefile.in (gencode): Ensure the host compiler and libraries
3695 used for cross-hosted build.
3696
3697Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3698
3699 * interp.c, gencode.c: Some more (TODO) tidying.
3700
3701Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3702
3703 * gencode.c, interp.c: Replaced explicit long long references with
3704 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3705 * support.h (SET64LO, SET64HI): Macros added.
3706
3707Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3708
3709 * configure: Regenerate with autoconf 2.7.
3710
3711Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3712
3713 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3714 * support.h: Remove superfluous "1" from #if.
3715 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3716
3717Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3718
3719 * interp.c (StoreFPR): Control UndefinedResult() call on
3720 WARN_RESULT manifest.
3721
3722Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3723
3724 * gencode.c: Tidied instruction decoding, and added FP instruction
3725 support.
3726
3727 * interp.c: Added dineroIII, and BSD profiling support. Also
3728 run-time FP handling.
3729
3730Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3731
3732 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3733 gencode.c, interp.c, support.h: created.
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