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Commit | Line | Data |
---|---|---|
272cc70b AF |
1 | /* |
2 | * Copyright 2008, Freescale Semiconductor, Inc | |
3 | * Andy Fleming | |
4 | * | |
5 | * Based vaguely on the Linux code | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
272cc70b AF |
8 | */ |
9 | ||
10 | #include <config.h> | |
11 | #include <common.h> | |
12 | #include <command.h> | |
8e3332e2 SS |
13 | #include <dm.h> |
14 | #include <dm/device-internal.h> | |
d4622df3 | 15 | #include <errno.h> |
272cc70b AF |
16 | #include <mmc.h> |
17 | #include <part.h> | |
18 | #include <malloc.h> | |
cf92e05c | 19 | #include <memalign.h> |
272cc70b | 20 | #include <linux/list.h> |
9b1f942c | 21 | #include <div64.h> |
da61fa5f | 22 | #include "mmc_private.h" |
272cc70b | 23 | |
750121c3 | 24 | __weak int board_mmc_getwp(struct mmc *mmc) |
d23d8d7e NK |
25 | { |
26 | return -1; | |
27 | } | |
28 | ||
29 | int mmc_getwp(struct mmc *mmc) | |
30 | { | |
31 | int wp; | |
32 | ||
33 | wp = board_mmc_getwp(mmc); | |
34 | ||
d4e1da4e | 35 | if (wp < 0) { |
93bfd616 PA |
36 | if (mmc->cfg->ops->getwp) |
37 | wp = mmc->cfg->ops->getwp(mmc); | |
d4e1da4e PK |
38 | else |
39 | wp = 0; | |
40 | } | |
d23d8d7e NK |
41 | |
42 | return wp; | |
43 | } | |
44 | ||
cee9ab7c JH |
45 | __weak int board_mmc_getcd(struct mmc *mmc) |
46 | { | |
11fdade2 SB |
47 | return -1; |
48 | } | |
49 | ||
da61fa5f | 50 | int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) |
272cc70b | 51 | { |
5db2fe3a | 52 | int ret; |
8635ff9e | 53 | |
8635ff9e | 54 | #ifdef CONFIG_MMC_TRACE |
5db2fe3a RR |
55 | int i; |
56 | u8 *ptr; | |
57 | ||
58 | printf("CMD_SEND:%d\n", cmd->cmdidx); | |
59 | printf("\t\tARG\t\t\t 0x%08X\n", cmd->cmdarg); | |
93bfd616 | 60 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
7863ce58 BM |
61 | if (ret) { |
62 | printf("\t\tRET\t\t\t %d\n", ret); | |
63 | } else { | |
64 | switch (cmd->resp_type) { | |
65 | case MMC_RSP_NONE: | |
66 | printf("\t\tMMC_RSP_NONE\n"); | |
67 | break; | |
68 | case MMC_RSP_R1: | |
69 | printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08X \n", | |
70 | cmd->response[0]); | |
71 | break; | |
72 | case MMC_RSP_R1b: | |
73 | printf("\t\tMMC_RSP_R1b\t\t 0x%08X \n", | |
74 | cmd->response[0]); | |
75 | break; | |
76 | case MMC_RSP_R2: | |
77 | printf("\t\tMMC_RSP_R2\t\t 0x%08X \n", | |
78 | cmd->response[0]); | |
79 | printf("\t\t \t\t 0x%08X \n", | |
80 | cmd->response[1]); | |
81 | printf("\t\t \t\t 0x%08X \n", | |
82 | cmd->response[2]); | |
83 | printf("\t\t \t\t 0x%08X \n", | |
84 | cmd->response[3]); | |
5db2fe3a | 85 | printf("\n"); |
7863ce58 BM |
86 | printf("\t\t\t\t\tDUMPING DATA\n"); |
87 | for (i = 0; i < 4; i++) { | |
88 | int j; | |
89 | printf("\t\t\t\t\t%03d - ", i*4); | |
90 | ptr = (u8 *)&cmd->response[i]; | |
91 | ptr += 3; | |
92 | for (j = 0; j < 4; j++) | |
93 | printf("%02X ", *ptr--); | |
94 | printf("\n"); | |
95 | } | |
96 | break; | |
97 | case MMC_RSP_R3: | |
98 | printf("\t\tMMC_RSP_R3,4\t\t 0x%08X \n", | |
99 | cmd->response[0]); | |
100 | break; | |
101 | default: | |
102 | printf("\t\tERROR MMC rsp not supported\n"); | |
103 | break; | |
53e8e40b | 104 | } |
5db2fe3a | 105 | } |
5db2fe3a | 106 | #else |
93bfd616 | 107 | ret = mmc->cfg->ops->send_cmd(mmc, cmd, data); |
5db2fe3a | 108 | #endif |
8635ff9e | 109 | return ret; |
272cc70b AF |
110 | } |
111 | ||
da61fa5f | 112 | int mmc_send_status(struct mmc *mmc, int timeout) |
5d4fc8d9 RR |
113 | { |
114 | struct mmc_cmd cmd; | |
d617c426 | 115 | int err, retries = 5; |
5d4fc8d9 RR |
116 | #ifdef CONFIG_MMC_TRACE |
117 | int status; | |
118 | #endif | |
119 | ||
120 | cmd.cmdidx = MMC_CMD_SEND_STATUS; | |
121 | cmd.resp_type = MMC_RSP_R1; | |
aaf3d41a MV |
122 | if (!mmc_host_is_spi(mmc)) |
123 | cmd.cmdarg = mmc->rca << 16; | |
5d4fc8d9 | 124 | |
1677eef4 | 125 | while (1) { |
5d4fc8d9 | 126 | err = mmc_send_cmd(mmc, &cmd, NULL); |
d617c426 JK |
127 | if (!err) { |
128 | if ((cmd.response[0] & MMC_STATUS_RDY_FOR_DATA) && | |
129 | (cmd.response[0] & MMC_STATUS_CURR_STATE) != | |
130 | MMC_STATE_PRG) | |
131 | break; | |
132 | else if (cmd.response[0] & MMC_STATUS_MASK) { | |
56196826 | 133 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
d617c426 JK |
134 | printf("Status Error: 0x%08X\n", |
135 | cmd.response[0]); | |
56196826 | 136 | #endif |
d617c426 JK |
137 | return COMM_ERR; |
138 | } | |
139 | } else if (--retries < 0) | |
5d4fc8d9 | 140 | return err; |
5d4fc8d9 | 141 | |
1677eef4 AG |
142 | if (timeout-- <= 0) |
143 | break; | |
5d4fc8d9 | 144 | |
1677eef4 AG |
145 | udelay(1000); |
146 | } | |
5d4fc8d9 | 147 | |
5db2fe3a RR |
148 | #ifdef CONFIG_MMC_TRACE |
149 | status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; | |
150 | printf("CURR STATE:%d\n", status); | |
151 | #endif | |
5b0c942f | 152 | if (timeout <= 0) { |
56196826 | 153 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
5d4fc8d9 | 154 | printf("Timeout waiting card ready\n"); |
56196826 | 155 | #endif |
5d4fc8d9 RR |
156 | return TIMEOUT; |
157 | } | |
6b2221b0 AG |
158 | if (cmd.response[0] & MMC_STATUS_SWITCH_ERROR) |
159 | return SWITCH_ERR; | |
5d4fc8d9 RR |
160 | |
161 | return 0; | |
162 | } | |
163 | ||
da61fa5f | 164 | int mmc_set_blocklen(struct mmc *mmc, int len) |
272cc70b AF |
165 | { |
166 | struct mmc_cmd cmd; | |
167 | ||
786e8f81 | 168 | if (mmc->ddr_mode) |
d22e3d46 JC |
169 | return 0; |
170 | ||
272cc70b AF |
171 | cmd.cmdidx = MMC_CMD_SET_BLOCKLEN; |
172 | cmd.resp_type = MMC_RSP_R1; | |
173 | cmd.cmdarg = len; | |
272cc70b AF |
174 | |
175 | return mmc_send_cmd(mmc, &cmd, NULL); | |
176 | } | |
177 | ||
ff8fef56 | 178 | static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start, |
fdbb873e | 179 | lbaint_t blkcnt) |
272cc70b AF |
180 | { |
181 | struct mmc_cmd cmd; | |
182 | struct mmc_data data; | |
183 | ||
4a1a06bc AS |
184 | if (blkcnt > 1) |
185 | cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK; | |
186 | else | |
187 | cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK; | |
272cc70b AF |
188 | |
189 | if (mmc->high_capacity) | |
4a1a06bc | 190 | cmd.cmdarg = start; |
272cc70b | 191 | else |
4a1a06bc | 192 | cmd.cmdarg = start * mmc->read_bl_len; |
272cc70b AF |
193 | |
194 | cmd.resp_type = MMC_RSP_R1; | |
272cc70b AF |
195 | |
196 | data.dest = dst; | |
4a1a06bc | 197 | data.blocks = blkcnt; |
272cc70b AF |
198 | data.blocksize = mmc->read_bl_len; |
199 | data.flags = MMC_DATA_READ; | |
200 | ||
4a1a06bc AS |
201 | if (mmc_send_cmd(mmc, &cmd, &data)) |
202 | return 0; | |
272cc70b | 203 | |
4a1a06bc AS |
204 | if (blkcnt > 1) { |
205 | cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; | |
206 | cmd.cmdarg = 0; | |
207 | cmd.resp_type = MMC_RSP_R1b; | |
4a1a06bc | 208 | if (mmc_send_cmd(mmc, &cmd, NULL)) { |
56196826 | 209 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
4a1a06bc | 210 | printf("mmc fail to send stop cmd\n"); |
56196826 | 211 | #endif |
4a1a06bc AS |
212 | return 0; |
213 | } | |
272cc70b AF |
214 | } |
215 | ||
4a1a06bc | 216 | return blkcnt; |
272cc70b AF |
217 | } |
218 | ||
4101f687 | 219 | static ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, |
7c4213f6 | 220 | lbaint_t blkcnt, void *dst) |
272cc70b | 221 | { |
bcce53d0 | 222 | int dev_num = block_dev->devnum; |
873cc1d7 | 223 | int err; |
4a1a06bc AS |
224 | lbaint_t cur, blocks_todo = blkcnt; |
225 | ||
226 | if (blkcnt == 0) | |
227 | return 0; | |
272cc70b | 228 | |
4a1a06bc | 229 | struct mmc *mmc = find_mmc_device(dev_num); |
272cc70b AF |
230 | if (!mmc) |
231 | return 0; | |
232 | ||
69f45cd5 | 233 | err = blk_dselect_hwpart(block_dev, block_dev->hwpart); |
873cc1d7 SW |
234 | if (err < 0) |
235 | return 0; | |
236 | ||
c40fdca6 | 237 | if ((start + blkcnt) > block_dev->lba) { |
56196826 | 238 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
ff8fef56 | 239 | printf("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n", |
c40fdca6 | 240 | start + blkcnt, block_dev->lba); |
56196826 | 241 | #endif |
d2bf29e3 LW |
242 | return 0; |
243 | } | |
272cc70b | 244 | |
11692991 SG |
245 | if (mmc_set_blocklen(mmc, mmc->read_bl_len)) { |
246 | debug("%s: Failed to set blocklen\n", __func__); | |
272cc70b | 247 | return 0; |
11692991 | 248 | } |
272cc70b | 249 | |
4a1a06bc | 250 | do { |
93bfd616 PA |
251 | cur = (blocks_todo > mmc->cfg->b_max) ? |
252 | mmc->cfg->b_max : blocks_todo; | |
11692991 SG |
253 | if (mmc_read_blocks(mmc, dst, start, cur) != cur) { |
254 | debug("%s: Failed to read blocks\n", __func__); | |
4a1a06bc | 255 | return 0; |
11692991 | 256 | } |
4a1a06bc AS |
257 | blocks_todo -= cur; |
258 | start += cur; | |
259 | dst += cur * mmc->read_bl_len; | |
260 | } while (blocks_todo > 0); | |
272cc70b AF |
261 | |
262 | return blkcnt; | |
263 | } | |
264 | ||
fdbb873e | 265 | static int mmc_go_idle(struct mmc *mmc) |
272cc70b AF |
266 | { |
267 | struct mmc_cmd cmd; | |
268 | int err; | |
269 | ||
270 | udelay(1000); | |
271 | ||
272 | cmd.cmdidx = MMC_CMD_GO_IDLE_STATE; | |
273 | cmd.cmdarg = 0; | |
274 | cmd.resp_type = MMC_RSP_NONE; | |
272cc70b AF |
275 | |
276 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
277 | ||
278 | if (err) | |
279 | return err; | |
280 | ||
281 | udelay(2000); | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
fdbb873e | 286 | static int sd_send_op_cond(struct mmc *mmc) |
272cc70b AF |
287 | { |
288 | int timeout = 1000; | |
289 | int err; | |
290 | struct mmc_cmd cmd; | |
291 | ||
1677eef4 | 292 | while (1) { |
272cc70b AF |
293 | cmd.cmdidx = MMC_CMD_APP_CMD; |
294 | cmd.resp_type = MMC_RSP_R1; | |
295 | cmd.cmdarg = 0; | |
272cc70b AF |
296 | |
297 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
298 | ||
299 | if (err) | |
300 | return err; | |
301 | ||
302 | cmd.cmdidx = SD_CMD_APP_SEND_OP_COND; | |
303 | cmd.resp_type = MMC_RSP_R3; | |
250de12b SB |
304 | |
305 | /* | |
306 | * Most cards do not answer if some reserved bits | |
307 | * in the ocr are set. However, Some controller | |
308 | * can set bit 7 (reserved for low voltages), but | |
309 | * how to manage low voltages SD card is not yet | |
310 | * specified. | |
311 | */ | |
d52ebf10 | 312 | cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 : |
93bfd616 | 313 | (mmc->cfg->voltages & 0xff8000); |
272cc70b AF |
314 | |
315 | if (mmc->version == SD_VERSION_2) | |
316 | cmd.cmdarg |= OCR_HCS; | |
317 | ||
318 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
319 | ||
320 | if (err) | |
321 | return err; | |
322 | ||
1677eef4 AG |
323 | if (cmd.response[0] & OCR_BUSY) |
324 | break; | |
325 | ||
326 | if (timeout-- <= 0) | |
327 | return UNUSABLE_ERR; | |
272cc70b | 328 | |
1677eef4 AG |
329 | udelay(1000); |
330 | } | |
272cc70b AF |
331 | |
332 | if (mmc->version != SD_VERSION_2) | |
333 | mmc->version = SD_VERSION_1_0; | |
334 | ||
d52ebf10 TC |
335 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
336 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
337 | cmd.resp_type = MMC_RSP_R3; | |
338 | cmd.cmdarg = 0; | |
d52ebf10 TC |
339 | |
340 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
341 | ||
342 | if (err) | |
343 | return err; | |
344 | } | |
345 | ||
998be3dd | 346 | mmc->ocr = cmd.response[0]; |
272cc70b AF |
347 | |
348 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
349 | mmc->rca = 0; | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
5289b535 | 354 | static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg) |
272cc70b | 355 | { |
5289b535 | 356 | struct mmc_cmd cmd; |
272cc70b AF |
357 | int err; |
358 | ||
5289b535 AG |
359 | cmd.cmdidx = MMC_CMD_SEND_OP_COND; |
360 | cmd.resp_type = MMC_RSP_R3; | |
361 | cmd.cmdarg = 0; | |
5a20397b RH |
362 | if (use_arg && !mmc_host_is_spi(mmc)) |
363 | cmd.cmdarg = OCR_HCS | | |
93bfd616 | 364 | (mmc->cfg->voltages & |
a626c8d4 AG |
365 | (mmc->ocr & OCR_VOLTAGE_MASK)) | |
366 | (mmc->ocr & OCR_ACCESS_MODE); | |
e9550449 | 367 | |
5289b535 | 368 | err = mmc_send_cmd(mmc, &cmd, NULL); |
e9550449 CLC |
369 | if (err) |
370 | return err; | |
5289b535 | 371 | mmc->ocr = cmd.response[0]; |
e9550449 CLC |
372 | return 0; |
373 | } | |
374 | ||
750121c3 | 375 | static int mmc_send_op_cond(struct mmc *mmc) |
e9550449 | 376 | { |
e9550449 CLC |
377 | int err, i; |
378 | ||
272cc70b AF |
379 | /* Some cards seem to need this */ |
380 | mmc_go_idle(mmc); | |
381 | ||
31cacbab | 382 | /* Asking to the card its capabilities */ |
e9550449 | 383 | for (i = 0; i < 2; i++) { |
5289b535 | 384 | err = mmc_send_op_cond_iter(mmc, i != 0); |
e9550449 CLC |
385 | if (err) |
386 | return err; | |
cd6881b5 | 387 | |
e9550449 | 388 | /* exit if not busy (flag seems to be inverted) */ |
a626c8d4 | 389 | if (mmc->ocr & OCR_BUSY) |
bd47c135 | 390 | break; |
e9550449 | 391 | } |
bd47c135 AG |
392 | mmc->op_cond_pending = 1; |
393 | return 0; | |
e9550449 | 394 | } |
cd6881b5 | 395 | |
750121c3 | 396 | static int mmc_complete_op_cond(struct mmc *mmc) |
e9550449 CLC |
397 | { |
398 | struct mmc_cmd cmd; | |
399 | int timeout = 1000; | |
400 | uint start; | |
401 | int err; | |
cd6881b5 | 402 | |
e9550449 | 403 | mmc->op_cond_pending = 0; |
cc17c01f AG |
404 | if (!(mmc->ocr & OCR_BUSY)) { |
405 | start = get_timer(0); | |
1677eef4 | 406 | while (1) { |
cc17c01f AG |
407 | err = mmc_send_op_cond_iter(mmc, 1); |
408 | if (err) | |
409 | return err; | |
1677eef4 AG |
410 | if (mmc->ocr & OCR_BUSY) |
411 | break; | |
cc17c01f AG |
412 | if (get_timer(start) > timeout) |
413 | return UNUSABLE_ERR; | |
414 | udelay(100); | |
1677eef4 | 415 | } |
cc17c01f | 416 | } |
272cc70b | 417 | |
d52ebf10 TC |
418 | if (mmc_host_is_spi(mmc)) { /* read OCR for spi */ |
419 | cmd.cmdidx = MMC_CMD_SPI_READ_OCR; | |
420 | cmd.resp_type = MMC_RSP_R3; | |
421 | cmd.cmdarg = 0; | |
d52ebf10 TC |
422 | |
423 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
424 | ||
425 | if (err) | |
426 | return err; | |
a626c8d4 AG |
427 | |
428 | mmc->ocr = cmd.response[0]; | |
d52ebf10 TC |
429 | } |
430 | ||
272cc70b | 431 | mmc->version = MMC_VERSION_UNKNOWN; |
272cc70b AF |
432 | |
433 | mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS); | |
def816a2 | 434 | mmc->rca = 1; |
272cc70b AF |
435 | |
436 | return 0; | |
437 | } | |
438 | ||
439 | ||
fdbb873e | 440 | static int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd) |
272cc70b AF |
441 | { |
442 | struct mmc_cmd cmd; | |
443 | struct mmc_data data; | |
444 | int err; | |
445 | ||
446 | /* Get the Card Status Register */ | |
447 | cmd.cmdidx = MMC_CMD_SEND_EXT_CSD; | |
448 | cmd.resp_type = MMC_RSP_R1; | |
449 | cmd.cmdarg = 0; | |
272cc70b | 450 | |
cdfd1ac6 | 451 | data.dest = (char *)ext_csd; |
272cc70b | 452 | data.blocks = 1; |
8bfa195e | 453 | data.blocksize = MMC_MAX_BLOCK_LEN; |
272cc70b AF |
454 | data.flags = MMC_DATA_READ; |
455 | ||
456 | err = mmc_send_cmd(mmc, &cmd, &data); | |
457 | ||
458 | return err; | |
459 | } | |
460 | ||
461 | ||
fdbb873e | 462 | static int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value) |
272cc70b AF |
463 | { |
464 | struct mmc_cmd cmd; | |
5d4fc8d9 RR |
465 | int timeout = 1000; |
466 | int ret; | |
272cc70b AF |
467 | |
468 | cmd.cmdidx = MMC_CMD_SWITCH; | |
469 | cmd.resp_type = MMC_RSP_R1b; | |
470 | cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) | | |
5d4fc8d9 RR |
471 | (index << 16) | |
472 | (value << 8); | |
272cc70b | 473 | |
5d4fc8d9 RR |
474 | ret = mmc_send_cmd(mmc, &cmd, NULL); |
475 | ||
476 | /* Waiting for the ready status */ | |
93ad0d18 JK |
477 | if (!ret) |
478 | ret = mmc_send_status(mmc, timeout); | |
5d4fc8d9 RR |
479 | |
480 | return ret; | |
481 | ||
272cc70b AF |
482 | } |
483 | ||
fdbb873e | 484 | static int mmc_change_freq(struct mmc *mmc) |
272cc70b | 485 | { |
8bfa195e | 486 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
272cc70b AF |
487 | char cardtype; |
488 | int err; | |
489 | ||
fc5b32fb | 490 | mmc->card_caps = 0; |
272cc70b | 491 | |
d52ebf10 TC |
492 | if (mmc_host_is_spi(mmc)) |
493 | return 0; | |
494 | ||
272cc70b AF |
495 | /* Only version 4 supports high-speed */ |
496 | if (mmc->version < MMC_VERSION_4) | |
497 | return 0; | |
498 | ||
fc5b32fb AG |
499 | mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT; |
500 | ||
272cc70b AF |
501 | err = mmc_send_ext_csd(mmc, ext_csd); |
502 | ||
503 | if (err) | |
504 | return err; | |
505 | ||
0560db18 | 506 | cardtype = ext_csd[EXT_CSD_CARD_TYPE] & 0xf; |
272cc70b AF |
507 | |
508 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); | |
509 | ||
510 | if (err) | |
6b2221b0 | 511 | return err == SWITCH_ERR ? 0 : err; |
272cc70b AF |
512 | |
513 | /* Now check to see that it worked */ | |
514 | err = mmc_send_ext_csd(mmc, ext_csd); | |
515 | ||
516 | if (err) | |
517 | return err; | |
518 | ||
519 | /* No high-speed support */ | |
0560db18 | 520 | if (!ext_csd[EXT_CSD_HS_TIMING]) |
272cc70b AF |
521 | return 0; |
522 | ||
523 | /* High Speed is set, there are two types: 52MHz and 26MHz */ | |
d22e3d46 | 524 | if (cardtype & EXT_CSD_CARD_TYPE_52) { |
201d5ac4 | 525 | if (cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V) |
d22e3d46 | 526 | mmc->card_caps |= MMC_MODE_DDR_52MHz; |
272cc70b | 527 | mmc->card_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
d22e3d46 | 528 | } else { |
272cc70b | 529 | mmc->card_caps |= MMC_MODE_HS; |
d22e3d46 | 530 | } |
272cc70b AF |
531 | |
532 | return 0; | |
533 | } | |
534 | ||
f866a46d SW |
535 | static int mmc_set_capacity(struct mmc *mmc, int part_num) |
536 | { | |
537 | switch (part_num) { | |
538 | case 0: | |
539 | mmc->capacity = mmc->capacity_user; | |
540 | break; | |
541 | case 1: | |
542 | case 2: | |
543 | mmc->capacity = mmc->capacity_boot; | |
544 | break; | |
545 | case 3: | |
546 | mmc->capacity = mmc->capacity_rpmb; | |
547 | break; | |
548 | case 4: | |
549 | case 5: | |
550 | case 6: | |
551 | case 7: | |
552 | mmc->capacity = mmc->capacity_gp[part_num - 4]; | |
553 | break; | |
554 | default: | |
555 | return -1; | |
556 | } | |
557 | ||
c40fdca6 | 558 | mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len); |
f866a46d SW |
559 | |
560 | return 0; | |
561 | } | |
562 | ||
fdbb139f | 563 | static int mmc_switch_part(struct mmc *mmc, unsigned int part_num) |
bc897b1d | 564 | { |
f866a46d | 565 | int ret; |
bc897b1d | 566 | |
f866a46d SW |
567 | ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, |
568 | (mmc->part_config & ~PART_ACCESS_MASK) | |
569 | | (part_num & PART_ACCESS_MASK)); | |
f866a46d | 570 | |
6dc93e70 PB |
571 | /* |
572 | * Set the capacity if the switch succeeded or was intended | |
573 | * to return to representing the raw device. | |
574 | */ | |
873cc1d7 | 575 | if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) { |
6dc93e70 | 576 | ret = mmc_set_capacity(mmc, part_num); |
fdbb139f | 577 | mmc_get_blk_desc(mmc)->hwpart = part_num; |
873cc1d7 | 578 | } |
6dc93e70 PB |
579 | |
580 | return ret; | |
bc897b1d LW |
581 | } |
582 | ||
e17d1143 SG |
583 | static int mmc_select_hwpartp(struct blk_desc *desc, int hwpart) |
584 | { | |
585 | struct mmc *mmc = find_mmc_device(desc->devnum); | |
586 | int ret; | |
587 | ||
588 | if (!mmc) | |
589 | return -ENODEV; | |
590 | ||
591 | if (mmc->block_dev.hwpart == hwpart) | |
592 | return 0; | |
593 | ||
594 | if (mmc->part_config == MMCPART_NOAVAILABLE) | |
595 | return -EMEDIUMTYPE; | |
596 | ||
fdbb139f | 597 | ret = mmc_switch_part(mmc, hwpart); |
e17d1143 SG |
598 | if (ret) |
599 | return ret; | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
ff3882ac SG |
604 | int mmc_select_hwpart(int dev_num, int hwpart) |
605 | { | |
606 | struct mmc *mmc = find_mmc_device(dev_num); | |
607 | int ret; | |
608 | ||
609 | if (!mmc) | |
610 | return -ENODEV; | |
611 | ||
612 | if (mmc->block_dev.hwpart == hwpart) | |
613 | return 0; | |
614 | ||
615 | if (mmc->part_config == MMCPART_NOAVAILABLE) | |
616 | return -EMEDIUMTYPE; | |
617 | ||
fdbb139f | 618 | ret = mmc_switch_part(mmc, hwpart); |
ff3882ac SG |
619 | if (ret) |
620 | return ret; | |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
ac9da0e0 DSC |
625 | int mmc_hwpart_config(struct mmc *mmc, |
626 | const struct mmc_hwpart_conf *conf, | |
627 | enum mmc_hwpart_conf_mode mode) | |
628 | { | |
629 | u8 part_attrs = 0; | |
630 | u32 enh_size_mult; | |
631 | u32 enh_start_addr; | |
632 | u32 gp_size_mult[4]; | |
633 | u32 max_enh_size_mult; | |
634 | u32 tot_enh_size_mult = 0; | |
8dda5b0e | 635 | u8 wr_rel_set; |
ac9da0e0 DSC |
636 | int i, pidx, err; |
637 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); | |
638 | ||
639 | if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE) | |
640 | return -EINVAL; | |
641 | ||
642 | if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) { | |
643 | printf("eMMC >= 4.4 required for enhanced user data area\n"); | |
644 | return -EMEDIUMTYPE; | |
645 | } | |
646 | ||
647 | if (!(mmc->part_support & PART_SUPPORT)) { | |
648 | printf("Card does not support partitioning\n"); | |
649 | return -EMEDIUMTYPE; | |
650 | } | |
651 | ||
652 | if (!mmc->hc_wp_grp_size) { | |
653 | printf("Card does not define HC WP group size\n"); | |
654 | return -EMEDIUMTYPE; | |
655 | } | |
656 | ||
657 | /* check partition alignment and total enhanced size */ | |
658 | if (conf->user.enh_size) { | |
659 | if (conf->user.enh_size % mmc->hc_wp_grp_size || | |
660 | conf->user.enh_start % mmc->hc_wp_grp_size) { | |
661 | printf("User data enhanced area not HC WP group " | |
662 | "size aligned\n"); | |
663 | return -EINVAL; | |
664 | } | |
665 | part_attrs |= EXT_CSD_ENH_USR; | |
666 | enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size; | |
667 | if (mmc->high_capacity) { | |
668 | enh_start_addr = conf->user.enh_start; | |
669 | } else { | |
670 | enh_start_addr = (conf->user.enh_start << 9); | |
671 | } | |
672 | } else { | |
673 | enh_size_mult = 0; | |
674 | enh_start_addr = 0; | |
675 | } | |
676 | tot_enh_size_mult += enh_size_mult; | |
677 | ||
678 | for (pidx = 0; pidx < 4; pidx++) { | |
679 | if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) { | |
680 | printf("GP%i partition not HC WP group size " | |
681 | "aligned\n", pidx+1); | |
682 | return -EINVAL; | |
683 | } | |
684 | gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size; | |
685 | if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) { | |
686 | part_attrs |= EXT_CSD_ENH_GP(pidx); | |
687 | tot_enh_size_mult += gp_size_mult[pidx]; | |
688 | } | |
689 | } | |
690 | ||
691 | if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) { | |
692 | printf("Card does not support enhanced attribute\n"); | |
693 | return -EMEDIUMTYPE; | |
694 | } | |
695 | ||
696 | err = mmc_send_ext_csd(mmc, ext_csd); | |
697 | if (err) | |
698 | return err; | |
699 | ||
700 | max_enh_size_mult = | |
701 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) + | |
702 | (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) + | |
703 | ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT]; | |
704 | if (tot_enh_size_mult > max_enh_size_mult) { | |
705 | printf("Total enhanced size exceeds maximum (%u > %u)\n", | |
706 | tot_enh_size_mult, max_enh_size_mult); | |
707 | return -EMEDIUMTYPE; | |
708 | } | |
709 | ||
8dda5b0e DSC |
710 | /* The default value of EXT_CSD_WR_REL_SET is device |
711 | * dependent, the values can only be changed if the | |
712 | * EXT_CSD_HS_CTRL_REL bit is set. The values can be | |
713 | * changed only once and before partitioning is completed. */ | |
714 | wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
715 | if (conf->user.wr_rel_change) { | |
716 | if (conf->user.wr_rel_set) | |
717 | wr_rel_set |= EXT_CSD_WR_DATA_REL_USR; | |
718 | else | |
719 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR; | |
720 | } | |
721 | for (pidx = 0; pidx < 4; pidx++) { | |
722 | if (conf->gp_part[pidx].wr_rel_change) { | |
723 | if (conf->gp_part[pidx].wr_rel_set) | |
724 | wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx); | |
725 | else | |
726 | wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx); | |
727 | } | |
728 | } | |
729 | ||
730 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] && | |
731 | !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) { | |
732 | puts("Card does not support host controlled partition write " | |
733 | "reliability settings\n"); | |
734 | return -EMEDIUMTYPE; | |
735 | } | |
736 | ||
ac9da0e0 DSC |
737 | if (ext_csd[EXT_CSD_PARTITION_SETTING] & |
738 | EXT_CSD_PARTITION_SETTING_COMPLETED) { | |
739 | printf("Card already partitioned\n"); | |
740 | return -EPERM; | |
741 | } | |
742 | ||
743 | if (mode == MMC_HWPART_CONF_CHECK) | |
744 | return 0; | |
745 | ||
746 | /* Partitioning requires high-capacity size definitions */ | |
747 | if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) { | |
748 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
749 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
750 | ||
751 | if (err) | |
752 | return err; | |
753 | ||
754 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
755 | ||
756 | /* update erase group size to be high-capacity */ | |
757 | mmc->erase_grp_size = | |
758 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; | |
759 | ||
760 | } | |
761 | ||
762 | /* all OK, write the configuration */ | |
763 | for (i = 0; i < 4; i++) { | |
764 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
765 | EXT_CSD_ENH_START_ADDR+i, | |
766 | (enh_start_addr >> (i*8)) & 0xFF); | |
767 | if (err) | |
768 | return err; | |
769 | } | |
770 | for (i = 0; i < 3; i++) { | |
771 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
772 | EXT_CSD_ENH_SIZE_MULT+i, | |
773 | (enh_size_mult >> (i*8)) & 0xFF); | |
774 | if (err) | |
775 | return err; | |
776 | } | |
777 | for (pidx = 0; pidx < 4; pidx++) { | |
778 | for (i = 0; i < 3; i++) { | |
779 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
780 | EXT_CSD_GP_SIZE_MULT+pidx*3+i, | |
781 | (gp_size_mult[pidx] >> (i*8)) & 0xFF); | |
782 | if (err) | |
783 | return err; | |
784 | } | |
785 | } | |
786 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
787 | EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs); | |
788 | if (err) | |
789 | return err; | |
790 | ||
791 | if (mode == MMC_HWPART_CONF_SET) | |
792 | return 0; | |
793 | ||
8dda5b0e DSC |
794 | /* The WR_REL_SET is a write-once register but shall be |
795 | * written before setting PART_SETTING_COMPLETED. As it is | |
796 | * write-once we can only write it when completing the | |
797 | * partitioning. */ | |
798 | if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) { | |
799 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
800 | EXT_CSD_WR_REL_SET, wr_rel_set); | |
801 | if (err) | |
802 | return err; | |
803 | } | |
804 | ||
ac9da0e0 DSC |
805 | /* Setting PART_SETTING_COMPLETED confirms the partition |
806 | * configuration but it only becomes effective after power | |
807 | * cycle, so we do not adjust the partition related settings | |
808 | * in the mmc struct. */ | |
809 | ||
810 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, | |
811 | EXT_CSD_PARTITION_SETTING, | |
812 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
813 | if (err) | |
814 | return err; | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
48972d90 TR |
819 | int mmc_getcd(struct mmc *mmc) |
820 | { | |
821 | int cd; | |
822 | ||
823 | cd = board_mmc_getcd(mmc); | |
824 | ||
d4e1da4e | 825 | if (cd < 0) { |
93bfd616 PA |
826 | if (mmc->cfg->ops->getcd) |
827 | cd = mmc->cfg->ops->getcd(mmc); | |
d4e1da4e PK |
828 | else |
829 | cd = 1; | |
830 | } | |
48972d90 TR |
831 | |
832 | return cd; | |
833 | } | |
834 | ||
fdbb873e | 835 | static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp) |
272cc70b AF |
836 | { |
837 | struct mmc_cmd cmd; | |
838 | struct mmc_data data; | |
839 | ||
840 | /* Switch the frequency */ | |
841 | cmd.cmdidx = SD_CMD_SWITCH_FUNC; | |
842 | cmd.resp_type = MMC_RSP_R1; | |
843 | cmd.cmdarg = (mode << 31) | 0xffffff; | |
844 | cmd.cmdarg &= ~(0xf << (group * 4)); | |
845 | cmd.cmdarg |= value << (group * 4); | |
272cc70b AF |
846 | |
847 | data.dest = (char *)resp; | |
848 | data.blocksize = 64; | |
849 | data.blocks = 1; | |
850 | data.flags = MMC_DATA_READ; | |
851 | ||
852 | return mmc_send_cmd(mmc, &cmd, &data); | |
853 | } | |
854 | ||
855 | ||
fdbb873e | 856 | static int sd_change_freq(struct mmc *mmc) |
272cc70b AF |
857 | { |
858 | int err; | |
859 | struct mmc_cmd cmd; | |
f781dd38 A |
860 | ALLOC_CACHE_ALIGN_BUFFER(uint, scr, 2); |
861 | ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16); | |
272cc70b AF |
862 | struct mmc_data data; |
863 | int timeout; | |
864 | ||
865 | mmc->card_caps = 0; | |
866 | ||
d52ebf10 TC |
867 | if (mmc_host_is_spi(mmc)) |
868 | return 0; | |
869 | ||
272cc70b AF |
870 | /* Read the SCR to find out if this card supports higher speeds */ |
871 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
872 | cmd.resp_type = MMC_RSP_R1; | |
873 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
874 | |
875 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
876 | ||
877 | if (err) | |
878 | return err; | |
879 | ||
880 | cmd.cmdidx = SD_CMD_APP_SEND_SCR; | |
881 | cmd.resp_type = MMC_RSP_R1; | |
882 | cmd.cmdarg = 0; | |
272cc70b AF |
883 | |
884 | timeout = 3; | |
885 | ||
886 | retry_scr: | |
f781dd38 | 887 | data.dest = (char *)scr; |
272cc70b AF |
888 | data.blocksize = 8; |
889 | data.blocks = 1; | |
890 | data.flags = MMC_DATA_READ; | |
891 | ||
892 | err = mmc_send_cmd(mmc, &cmd, &data); | |
893 | ||
894 | if (err) { | |
895 | if (timeout--) | |
896 | goto retry_scr; | |
897 | ||
898 | return err; | |
899 | } | |
900 | ||
4e3d89ba YK |
901 | mmc->scr[0] = __be32_to_cpu(scr[0]); |
902 | mmc->scr[1] = __be32_to_cpu(scr[1]); | |
272cc70b AF |
903 | |
904 | switch ((mmc->scr[0] >> 24) & 0xf) { | |
53e8e40b BM |
905 | case 0: |
906 | mmc->version = SD_VERSION_1_0; | |
907 | break; | |
908 | case 1: | |
909 | mmc->version = SD_VERSION_1_10; | |
910 | break; | |
911 | case 2: | |
912 | mmc->version = SD_VERSION_2; | |
913 | if ((mmc->scr[0] >> 15) & 0x1) | |
914 | mmc->version = SD_VERSION_3; | |
915 | break; | |
916 | default: | |
917 | mmc->version = SD_VERSION_1_0; | |
918 | break; | |
272cc70b AF |
919 | } |
920 | ||
b44c7083 AS |
921 | if (mmc->scr[0] & SD_DATA_4BIT) |
922 | mmc->card_caps |= MMC_MODE_4BIT; | |
923 | ||
272cc70b AF |
924 | /* Version 1.0 doesn't support switching */ |
925 | if (mmc->version == SD_VERSION_1_0) | |
926 | return 0; | |
927 | ||
928 | timeout = 4; | |
929 | while (timeout--) { | |
930 | err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1, | |
f781dd38 | 931 | (u8 *)switch_status); |
272cc70b AF |
932 | |
933 | if (err) | |
934 | return err; | |
935 | ||
936 | /* The high-speed function is busy. Try again */ | |
4e3d89ba | 937 | if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY)) |
272cc70b AF |
938 | break; |
939 | } | |
940 | ||
272cc70b | 941 | /* If high-speed isn't supported, we return */ |
4e3d89ba | 942 | if (!(__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)) |
272cc70b AF |
943 | return 0; |
944 | ||
2c3fbf4c ML |
945 | /* |
946 | * If the host doesn't support SD_HIGHSPEED, do not switch card to | |
947 | * HIGHSPEED mode even if the card support SD_HIGHSPPED. | |
948 | * This can avoid furthur problem when the card runs in different | |
949 | * mode between the host. | |
950 | */ | |
93bfd616 PA |
951 | if (!((mmc->cfg->host_caps & MMC_MODE_HS_52MHz) && |
952 | (mmc->cfg->host_caps & MMC_MODE_HS))) | |
2c3fbf4c ML |
953 | return 0; |
954 | ||
f781dd38 | 955 | err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, 1, (u8 *)switch_status); |
272cc70b AF |
956 | |
957 | if (err) | |
958 | return err; | |
959 | ||
4e3d89ba | 960 | if ((__be32_to_cpu(switch_status[4]) & 0x0f000000) == 0x01000000) |
272cc70b AF |
961 | mmc->card_caps |= MMC_MODE_HS; |
962 | ||
963 | return 0; | |
964 | } | |
965 | ||
966 | /* frequency bases */ | |
967 | /* divided by 10 to be nice to platforms without floating point */ | |
5f837c2c | 968 | static const int fbase[] = { |
272cc70b AF |
969 | 10000, |
970 | 100000, | |
971 | 1000000, | |
972 | 10000000, | |
973 | }; | |
974 | ||
975 | /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice | |
976 | * to platforms without floating point. | |
977 | */ | |
5f837c2c | 978 | static const int multipliers[] = { |
272cc70b AF |
979 | 0, /* reserved */ |
980 | 10, | |
981 | 12, | |
982 | 13, | |
983 | 15, | |
984 | 20, | |
985 | 25, | |
986 | 30, | |
987 | 35, | |
988 | 40, | |
989 | 45, | |
990 | 50, | |
991 | 55, | |
992 | 60, | |
993 | 70, | |
994 | 80, | |
995 | }; | |
996 | ||
fdbb873e | 997 | static void mmc_set_ios(struct mmc *mmc) |
272cc70b | 998 | { |
93bfd616 PA |
999 | if (mmc->cfg->ops->set_ios) |
1000 | mmc->cfg->ops->set_ios(mmc); | |
272cc70b AF |
1001 | } |
1002 | ||
1003 | void mmc_set_clock(struct mmc *mmc, uint clock) | |
1004 | { | |
93bfd616 PA |
1005 | if (clock > mmc->cfg->f_max) |
1006 | clock = mmc->cfg->f_max; | |
272cc70b | 1007 | |
93bfd616 PA |
1008 | if (clock < mmc->cfg->f_min) |
1009 | clock = mmc->cfg->f_min; | |
272cc70b AF |
1010 | |
1011 | mmc->clock = clock; | |
1012 | ||
1013 | mmc_set_ios(mmc); | |
1014 | } | |
1015 | ||
fdbb873e | 1016 | static void mmc_set_bus_width(struct mmc *mmc, uint width) |
272cc70b AF |
1017 | { |
1018 | mmc->bus_width = width; | |
1019 | ||
1020 | mmc_set_ios(mmc); | |
1021 | } | |
1022 | ||
fdbb873e | 1023 | static int mmc_startup(struct mmc *mmc) |
272cc70b | 1024 | { |
f866a46d | 1025 | int err, i; |
272cc70b | 1026 | uint mult, freq; |
639b7827 | 1027 | u64 cmult, csize, capacity; |
272cc70b | 1028 | struct mmc_cmd cmd; |
8bfa195e SG |
1029 | ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN); |
1030 | ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN); | |
5d4fc8d9 | 1031 | int timeout = 1000; |
0c453bb7 | 1032 | bool has_parts = false; |
8a0cf490 | 1033 | bool part_completed; |
c40fdca6 | 1034 | struct blk_desc *bdesc; |
272cc70b | 1035 | |
d52ebf10 TC |
1036 | #ifdef CONFIG_MMC_SPI_CRC_ON |
1037 | if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */ | |
1038 | cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF; | |
1039 | cmd.resp_type = MMC_RSP_R1; | |
1040 | cmd.cmdarg = 1; | |
d52ebf10 TC |
1041 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1042 | ||
1043 | if (err) | |
1044 | return err; | |
1045 | } | |
1046 | #endif | |
1047 | ||
272cc70b | 1048 | /* Put the Card in Identify Mode */ |
d52ebf10 TC |
1049 | cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID : |
1050 | MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */ | |
272cc70b AF |
1051 | cmd.resp_type = MMC_RSP_R2; |
1052 | cmd.cmdarg = 0; | |
272cc70b AF |
1053 | |
1054 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1055 | ||
1056 | if (err) | |
1057 | return err; | |
1058 | ||
1059 | memcpy(mmc->cid, cmd.response, 16); | |
1060 | ||
1061 | /* | |
1062 | * For MMC cards, set the Relative Address. | |
1063 | * For SD cards, get the Relatvie Address. | |
1064 | * This also puts the cards into Standby State | |
1065 | */ | |
d52ebf10 TC |
1066 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1067 | cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR; | |
1068 | cmd.cmdarg = mmc->rca << 16; | |
1069 | cmd.resp_type = MMC_RSP_R6; | |
272cc70b | 1070 | |
d52ebf10 | 1071 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1072 | |
d52ebf10 TC |
1073 | if (err) |
1074 | return err; | |
272cc70b | 1075 | |
d52ebf10 TC |
1076 | if (IS_SD(mmc)) |
1077 | mmc->rca = (cmd.response[0] >> 16) & 0xffff; | |
1078 | } | |
272cc70b AF |
1079 | |
1080 | /* Get the Card-Specific Data */ | |
1081 | cmd.cmdidx = MMC_CMD_SEND_CSD; | |
1082 | cmd.resp_type = MMC_RSP_R2; | |
1083 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1084 | |
1085 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1086 | ||
5d4fc8d9 RR |
1087 | /* Waiting for the ready status */ |
1088 | mmc_send_status(mmc, timeout); | |
1089 | ||
272cc70b AF |
1090 | if (err) |
1091 | return err; | |
1092 | ||
998be3dd RV |
1093 | mmc->csd[0] = cmd.response[0]; |
1094 | mmc->csd[1] = cmd.response[1]; | |
1095 | mmc->csd[2] = cmd.response[2]; | |
1096 | mmc->csd[3] = cmd.response[3]; | |
272cc70b AF |
1097 | |
1098 | if (mmc->version == MMC_VERSION_UNKNOWN) { | |
0b453ffe | 1099 | int version = (cmd.response[0] >> 26) & 0xf; |
272cc70b AF |
1100 | |
1101 | switch (version) { | |
53e8e40b BM |
1102 | case 0: |
1103 | mmc->version = MMC_VERSION_1_2; | |
1104 | break; | |
1105 | case 1: | |
1106 | mmc->version = MMC_VERSION_1_4; | |
1107 | break; | |
1108 | case 2: | |
1109 | mmc->version = MMC_VERSION_2_2; | |
1110 | break; | |
1111 | case 3: | |
1112 | mmc->version = MMC_VERSION_3; | |
1113 | break; | |
1114 | case 4: | |
1115 | mmc->version = MMC_VERSION_4; | |
1116 | break; | |
1117 | default: | |
1118 | mmc->version = MMC_VERSION_1_2; | |
1119 | break; | |
272cc70b AF |
1120 | } |
1121 | } | |
1122 | ||
1123 | /* divide frequency by 10, since the mults are 10x bigger */ | |
0b453ffe RV |
1124 | freq = fbase[(cmd.response[0] & 0x7)]; |
1125 | mult = multipliers[((cmd.response[0] >> 3) & 0xf)]; | |
272cc70b AF |
1126 | |
1127 | mmc->tran_speed = freq * mult; | |
1128 | ||
ab71188c | 1129 | mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1); |
998be3dd | 1130 | mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf); |
272cc70b AF |
1131 | |
1132 | if (IS_SD(mmc)) | |
1133 | mmc->write_bl_len = mmc->read_bl_len; | |
1134 | else | |
998be3dd | 1135 | mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf); |
272cc70b AF |
1136 | |
1137 | if (mmc->high_capacity) { | |
1138 | csize = (mmc->csd[1] & 0x3f) << 16 | |
1139 | | (mmc->csd[2] & 0xffff0000) >> 16; | |
1140 | cmult = 8; | |
1141 | } else { | |
1142 | csize = (mmc->csd[1] & 0x3ff) << 2 | |
1143 | | (mmc->csd[2] & 0xc0000000) >> 30; | |
1144 | cmult = (mmc->csd[2] & 0x00038000) >> 15; | |
1145 | } | |
1146 | ||
f866a46d SW |
1147 | mmc->capacity_user = (csize + 1) << (cmult + 2); |
1148 | mmc->capacity_user *= mmc->read_bl_len; | |
1149 | mmc->capacity_boot = 0; | |
1150 | mmc->capacity_rpmb = 0; | |
1151 | for (i = 0; i < 4; i++) | |
1152 | mmc->capacity_gp[i] = 0; | |
272cc70b | 1153 | |
8bfa195e SG |
1154 | if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN) |
1155 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1156 | |
8bfa195e SG |
1157 | if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN) |
1158 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
272cc70b | 1159 | |
ab71188c MN |
1160 | if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) { |
1161 | cmd.cmdidx = MMC_CMD_SET_DSR; | |
1162 | cmd.cmdarg = (mmc->dsr & 0xffff) << 16; | |
1163 | cmd.resp_type = MMC_RSP_NONE; | |
1164 | if (mmc_send_cmd(mmc, &cmd, NULL)) | |
1165 | printf("MMC: SET_DSR failed\n"); | |
1166 | } | |
1167 | ||
272cc70b | 1168 | /* Select the card, and put it into Transfer Mode */ |
d52ebf10 TC |
1169 | if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */ |
1170 | cmd.cmdidx = MMC_CMD_SELECT_CARD; | |
fe8f7066 | 1171 | cmd.resp_type = MMC_RSP_R1; |
d52ebf10 | 1172 | cmd.cmdarg = mmc->rca << 16; |
d52ebf10 | 1173 | err = mmc_send_cmd(mmc, &cmd, NULL); |
272cc70b | 1174 | |
d52ebf10 TC |
1175 | if (err) |
1176 | return err; | |
1177 | } | |
272cc70b | 1178 | |
e6f99a56 LW |
1179 | /* |
1180 | * For SD, its erase group is always one sector | |
1181 | */ | |
1182 | mmc->erase_grp_size = 1; | |
bc897b1d | 1183 | mmc->part_config = MMCPART_NOAVAILABLE; |
d23e2c09 SG |
1184 | if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) { |
1185 | /* check ext_csd version and capacity */ | |
1186 | err = mmc_send_ext_csd(mmc, ext_csd); | |
9cf199eb DSC |
1187 | if (err) |
1188 | return err; | |
1189 | if (ext_csd[EXT_CSD_REV] >= 2) { | |
639b7827 YS |
1190 | /* |
1191 | * According to the JEDEC Standard, the value of | |
1192 | * ext_csd's capacity is valid if the value is more | |
1193 | * than 2GB | |
1194 | */ | |
0560db18 LW |
1195 | capacity = ext_csd[EXT_CSD_SEC_CNT] << 0 |
1196 | | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | |
1197 | | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | |
1198 | | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; | |
8bfa195e | 1199 | capacity *= MMC_MAX_BLOCK_LEN; |
b1f1e821 | 1200 | if ((capacity >> 20) > 2 * 1024) |
f866a46d | 1201 | mmc->capacity_user = capacity; |
d23e2c09 | 1202 | } |
bc897b1d | 1203 | |
64f4a619 JC |
1204 | switch (ext_csd[EXT_CSD_REV]) { |
1205 | case 1: | |
1206 | mmc->version = MMC_VERSION_4_1; | |
1207 | break; | |
1208 | case 2: | |
1209 | mmc->version = MMC_VERSION_4_2; | |
1210 | break; | |
1211 | case 3: | |
1212 | mmc->version = MMC_VERSION_4_3; | |
1213 | break; | |
1214 | case 5: | |
1215 | mmc->version = MMC_VERSION_4_41; | |
1216 | break; | |
1217 | case 6: | |
1218 | mmc->version = MMC_VERSION_4_5; | |
1219 | break; | |
edab723b MN |
1220 | case 7: |
1221 | mmc->version = MMC_VERSION_5_0; | |
1222 | break; | |
64f4a619 JC |
1223 | } |
1224 | ||
8a0cf490 DSC |
1225 | /* The partition data may be non-zero but it is only |
1226 | * effective if PARTITION_SETTING_COMPLETED is set in | |
1227 | * EXT_CSD, so ignore any data if this bit is not set, | |
1228 | * except for enabling the high-capacity group size | |
1229 | * definition (see below). */ | |
1230 | part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] & | |
1231 | EXT_CSD_PARTITION_SETTING_COMPLETED); | |
1232 | ||
0c453bb7 DSC |
1233 | /* store the partition info of emmc */ |
1234 | mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT]; | |
1235 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) || | |
1236 | ext_csd[EXT_CSD_BOOT_MULT]) | |
1237 | mmc->part_config = ext_csd[EXT_CSD_PART_CONF]; | |
8a0cf490 DSC |
1238 | if (part_completed && |
1239 | (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT)) | |
0c453bb7 DSC |
1240 | mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE]; |
1241 | ||
1242 | mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17; | |
1243 | ||
1244 | mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17; | |
1245 | ||
1246 | for (i = 0; i < 4; i++) { | |
1247 | int idx = EXT_CSD_GP_SIZE_MULT + i * 3; | |
8a0cf490 | 1248 | uint mult = (ext_csd[idx + 2] << 16) + |
0c453bb7 | 1249 | (ext_csd[idx + 1] << 8) + ext_csd[idx]; |
8a0cf490 DSC |
1250 | if (mult) |
1251 | has_parts = true; | |
1252 | if (!part_completed) | |
1253 | continue; | |
1254 | mmc->capacity_gp[i] = mult; | |
0c453bb7 DSC |
1255 | mmc->capacity_gp[i] *= |
1256 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1257 | mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
f8e89d67 | 1258 | mmc->capacity_gp[i] <<= 19; |
0c453bb7 DSC |
1259 | } |
1260 | ||
8a0cf490 DSC |
1261 | if (part_completed) { |
1262 | mmc->enh_user_size = | |
1263 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+2] << 16) + | |
1264 | (ext_csd[EXT_CSD_ENH_SIZE_MULT+1] << 8) + | |
1265 | ext_csd[EXT_CSD_ENH_SIZE_MULT]; | |
1266 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; | |
1267 | mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
1268 | mmc->enh_user_size <<= 19; | |
1269 | mmc->enh_user_start = | |
1270 | (ext_csd[EXT_CSD_ENH_START_ADDR+3] << 24) + | |
1271 | (ext_csd[EXT_CSD_ENH_START_ADDR+2] << 16) + | |
1272 | (ext_csd[EXT_CSD_ENH_START_ADDR+1] << 8) + | |
1273 | ext_csd[EXT_CSD_ENH_START_ADDR]; | |
1274 | if (mmc->high_capacity) | |
1275 | mmc->enh_user_start <<= 9; | |
1276 | } | |
a7f852b6 | 1277 | |
e6f99a56 | 1278 | /* |
1937e5aa OM |
1279 | * Host needs to enable ERASE_GRP_DEF bit if device is |
1280 | * partitioned. This bit will be lost every time after a reset | |
1281 | * or power off. This will affect erase size. | |
e6f99a56 | 1282 | */ |
8a0cf490 | 1283 | if (part_completed) |
0c453bb7 | 1284 | has_parts = true; |
1937e5aa | 1285 | if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) && |
0c453bb7 DSC |
1286 | (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB)) |
1287 | has_parts = true; | |
1288 | if (has_parts) { | |
1937e5aa OM |
1289 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
1290 | EXT_CSD_ERASE_GROUP_DEF, 1); | |
1291 | ||
1292 | if (err) | |
1293 | return err; | |
021a8055 HP |
1294 | else |
1295 | ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1; | |
037dc0ab | 1296 | } |
1937e5aa | 1297 | |
037dc0ab | 1298 | if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) { |
1937e5aa | 1299 | /* Read out group size from ext_csd */ |
0560db18 | 1300 | mmc->erase_grp_size = |
a4ff9f83 | 1301 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024; |
d7b29129 MN |
1302 | /* |
1303 | * if high capacity and partition setting completed | |
1304 | * SEC_COUNT is valid even if it is smaller than 2 GiB | |
1305 | * JEDEC Standard JESD84-B45, 6.2.4 | |
1306 | */ | |
8a0cf490 | 1307 | if (mmc->high_capacity && part_completed) { |
d7b29129 MN |
1308 | capacity = (ext_csd[EXT_CSD_SEC_CNT]) | |
1309 | (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) | | |
1310 | (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) | | |
1311 | (ext_csd[EXT_CSD_SEC_CNT + 3] << 24); | |
1312 | capacity *= MMC_MAX_BLOCK_LEN; | |
1313 | mmc->capacity_user = capacity; | |
1314 | } | |
8bfa195e | 1315 | } else { |
1937e5aa | 1316 | /* Calculate the group size from the csd value. */ |
e6f99a56 LW |
1317 | int erase_gsz, erase_gmul; |
1318 | erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10; | |
1319 | erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5; | |
1320 | mmc->erase_grp_size = (erase_gsz + 1) | |
1321 | * (erase_gmul + 1); | |
1322 | } | |
037dc0ab DSC |
1323 | |
1324 | mmc->hc_wp_grp_size = 1024 | |
1325 | * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1326 | * ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; | |
9e41a00b DSC |
1327 | |
1328 | mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET]; | |
d23e2c09 SG |
1329 | } |
1330 | ||
c40fdca6 | 1331 | err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart); |
f866a46d SW |
1332 | if (err) |
1333 | return err; | |
1334 | ||
272cc70b AF |
1335 | if (IS_SD(mmc)) |
1336 | err = sd_change_freq(mmc); | |
1337 | else | |
1338 | err = mmc_change_freq(mmc); | |
1339 | ||
1340 | if (err) | |
1341 | return err; | |
1342 | ||
1343 | /* Restrict card's capabilities by what the host can do */ | |
93bfd616 | 1344 | mmc->card_caps &= mmc->cfg->host_caps; |
272cc70b AF |
1345 | |
1346 | if (IS_SD(mmc)) { | |
1347 | if (mmc->card_caps & MMC_MODE_4BIT) { | |
1348 | cmd.cmdidx = MMC_CMD_APP_CMD; | |
1349 | cmd.resp_type = MMC_RSP_R1; | |
1350 | cmd.cmdarg = mmc->rca << 16; | |
272cc70b AF |
1351 | |
1352 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1353 | if (err) | |
1354 | return err; | |
1355 | ||
1356 | cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH; | |
1357 | cmd.resp_type = MMC_RSP_R1; | |
1358 | cmd.cmdarg = 2; | |
272cc70b AF |
1359 | err = mmc_send_cmd(mmc, &cmd, NULL); |
1360 | if (err) | |
1361 | return err; | |
1362 | ||
1363 | mmc_set_bus_width(mmc, 4); | |
1364 | } | |
1365 | ||
1366 | if (mmc->card_caps & MMC_MODE_HS) | |
ad5fd922 | 1367 | mmc->tran_speed = 50000000; |
272cc70b | 1368 | else |
ad5fd922 | 1369 | mmc->tran_speed = 25000000; |
fc5b32fb AG |
1370 | } else if (mmc->version >= MMC_VERSION_4) { |
1371 | /* Only version 4 of MMC supports wider bus widths */ | |
7798f6db AF |
1372 | int idx; |
1373 | ||
1374 | /* An array of possible bus widths in order of preference */ | |
1375 | static unsigned ext_csd_bits[] = { | |
d22e3d46 JC |
1376 | EXT_CSD_DDR_BUS_WIDTH_8, |
1377 | EXT_CSD_DDR_BUS_WIDTH_4, | |
7798f6db AF |
1378 | EXT_CSD_BUS_WIDTH_8, |
1379 | EXT_CSD_BUS_WIDTH_4, | |
1380 | EXT_CSD_BUS_WIDTH_1, | |
1381 | }; | |
1382 | ||
1383 | /* An array to map CSD bus widths to host cap bits */ | |
1384 | static unsigned ext_to_hostcaps[] = { | |
786e8f81 AG |
1385 | [EXT_CSD_DDR_BUS_WIDTH_4] = |
1386 | MMC_MODE_DDR_52MHz | MMC_MODE_4BIT, | |
1387 | [EXT_CSD_DDR_BUS_WIDTH_8] = | |
1388 | MMC_MODE_DDR_52MHz | MMC_MODE_8BIT, | |
7798f6db AF |
1389 | [EXT_CSD_BUS_WIDTH_4] = MMC_MODE_4BIT, |
1390 | [EXT_CSD_BUS_WIDTH_8] = MMC_MODE_8BIT, | |
1391 | }; | |
1392 | ||
1393 | /* An array to map chosen bus width to an integer */ | |
1394 | static unsigned widths[] = { | |
d22e3d46 | 1395 | 8, 4, 8, 4, 1, |
7798f6db AF |
1396 | }; |
1397 | ||
1398 | for (idx=0; idx < ARRAY_SIZE(ext_csd_bits); idx++) { | |
1399 | unsigned int extw = ext_csd_bits[idx]; | |
786e8f81 | 1400 | unsigned int caps = ext_to_hostcaps[extw]; |
7798f6db | 1401 | |
bf477073 AG |
1402 | /* |
1403 | * If the bus width is still not changed, | |
1404 | * don't try to set the default again. | |
1405 | * Otherwise, recover from switch attempts | |
1406 | * by switching to 1-bit bus width. | |
1407 | */ | |
1408 | if (extw == EXT_CSD_BUS_WIDTH_1 && | |
1409 | mmc->bus_width == 1) { | |
1410 | err = 0; | |
1411 | break; | |
1412 | } | |
1413 | ||
7798f6db | 1414 | /* |
786e8f81 AG |
1415 | * Check to make sure the card and controller support |
1416 | * these capabilities | |
7798f6db | 1417 | */ |
786e8f81 | 1418 | if ((mmc->card_caps & caps) != caps) |
7798f6db AF |
1419 | continue; |
1420 | ||
272cc70b | 1421 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, |
7798f6db | 1422 | EXT_CSD_BUS_WIDTH, extw); |
272cc70b AF |
1423 | |
1424 | if (err) | |
4137894e | 1425 | continue; |
272cc70b | 1426 | |
786e8f81 | 1427 | mmc->ddr_mode = (caps & MMC_MODE_DDR_52MHz) ? 1 : 0; |
7798f6db | 1428 | mmc_set_bus_width(mmc, widths[idx]); |
4137894e LW |
1429 | |
1430 | err = mmc_send_ext_csd(mmc, test_csd); | |
786e8f81 AG |
1431 | |
1432 | if (err) | |
1433 | continue; | |
1434 | ||
786a27b7 | 1435 | /* Only compare read only fields */ |
786e8f81 AG |
1436 | if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] |
1437 | == test_csd[EXT_CSD_PARTITIONING_SUPPORT] && | |
1438 | ext_csd[EXT_CSD_HC_WP_GRP_SIZE] | |
1439 | == test_csd[EXT_CSD_HC_WP_GRP_SIZE] && | |
1440 | ext_csd[EXT_CSD_REV] | |
1441 | == test_csd[EXT_CSD_REV] && | |
1442 | ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] | |
1443 | == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] && | |
1444 | memcmp(&ext_csd[EXT_CSD_SEC_CNT], | |
1445 | &test_csd[EXT_CSD_SEC_CNT], 4) == 0) | |
4137894e | 1446 | break; |
786e8f81 AG |
1447 | else |
1448 | err = SWITCH_ERR; | |
272cc70b AF |
1449 | } |
1450 | ||
786e8f81 AG |
1451 | if (err) |
1452 | return err; | |
1453 | ||
272cc70b AF |
1454 | if (mmc->card_caps & MMC_MODE_HS) { |
1455 | if (mmc->card_caps & MMC_MODE_HS_52MHz) | |
ad5fd922 | 1456 | mmc->tran_speed = 52000000; |
272cc70b | 1457 | else |
ad5fd922 JC |
1458 | mmc->tran_speed = 26000000; |
1459 | } | |
272cc70b AF |
1460 | } |
1461 | ||
ad5fd922 JC |
1462 | mmc_set_clock(mmc, mmc->tran_speed); |
1463 | ||
5af8f45c AG |
1464 | /* Fix the block length for DDR mode */ |
1465 | if (mmc->ddr_mode) { | |
1466 | mmc->read_bl_len = MMC_MAX_BLOCK_LEN; | |
1467 | mmc->write_bl_len = MMC_MAX_BLOCK_LEN; | |
1468 | } | |
1469 | ||
272cc70b | 1470 | /* fill in device description */ |
c40fdca6 SG |
1471 | bdesc = mmc_get_blk_desc(mmc); |
1472 | bdesc->lun = 0; | |
1473 | bdesc->hwpart = 0; | |
1474 | bdesc->type = 0; | |
1475 | bdesc->blksz = mmc->read_bl_len; | |
1476 | bdesc->log2blksz = LOG2(bdesc->blksz); | |
1477 | bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len); | |
fc011f64 SS |
1478 | #if !defined(CONFIG_SPL_BUILD) || \ |
1479 | (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \ | |
1480 | !defined(CONFIG_USE_TINY_PRINTF)) | |
c40fdca6 | 1481 | sprintf(bdesc->vendor, "Man %06x Snr %04x%04x", |
babce5f6 TH |
1482 | mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff), |
1483 | (mmc->cid[3] >> 16) & 0xffff); | |
c40fdca6 | 1484 | sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff, |
babce5f6 TH |
1485 | (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff, |
1486 | (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff, | |
1487 | (mmc->cid[2] >> 24) & 0xff); | |
c40fdca6 | 1488 | sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf, |
babce5f6 | 1489 | (mmc->cid[2] >> 16) & 0xf); |
56196826 | 1490 | #else |
c40fdca6 SG |
1491 | bdesc->vendor[0] = 0; |
1492 | bdesc->product[0] = 0; | |
1493 | bdesc->revision[0] = 0; | |
56196826 | 1494 | #endif |
122efd43 | 1495 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT) |
c40fdca6 | 1496 | part_init(bdesc); |
122efd43 | 1497 | #endif |
272cc70b AF |
1498 | |
1499 | return 0; | |
1500 | } | |
1501 | ||
fdbb873e | 1502 | static int mmc_send_if_cond(struct mmc *mmc) |
272cc70b AF |
1503 | { |
1504 | struct mmc_cmd cmd; | |
1505 | int err; | |
1506 | ||
1507 | cmd.cmdidx = SD_CMD_SEND_IF_COND; | |
1508 | /* We set the bit if the host supports voltages between 2.7 and 3.6 V */ | |
93bfd616 | 1509 | cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa; |
272cc70b | 1510 | cmd.resp_type = MMC_RSP_R7; |
272cc70b AF |
1511 | |
1512 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1513 | ||
1514 | if (err) | |
1515 | return err; | |
1516 | ||
998be3dd | 1517 | if ((cmd.response[0] & 0xff) != 0xaa) |
272cc70b AF |
1518 | return UNUSABLE_ERR; |
1519 | else | |
1520 | mmc->version = SD_VERSION_2; | |
1521 | ||
1522 | return 0; | |
1523 | } | |
1524 | ||
93bfd616 PA |
1525 | /* not used any more */ |
1526 | int __deprecated mmc_register(struct mmc *mmc) | |
1527 | { | |
1528 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) | |
1529 | printf("%s is deprecated! use mmc_create() instead.\n", __func__); | |
1530 | #endif | |
1531 | return -1; | |
1532 | } | |
1533 | ||
ad27dd5e SG |
1534 | #ifdef CONFIG_BLK |
1535 | int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg) | |
1536 | { | |
1537 | struct blk_desc *bdesc; | |
1538 | struct udevice *bdev; | |
1539 | int ret; | |
1540 | ||
1541 | ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC, -1, 512, | |
1542 | 0, &bdev); | |
1543 | if (ret) { | |
1544 | debug("Cannot create block device\n"); | |
1545 | return ret; | |
1546 | } | |
1547 | bdesc = dev_get_uclass_platdata(bdev); | |
1548 | mmc->cfg = cfg; | |
1549 | mmc->priv = dev; | |
1550 | ||
1551 | /* the following chunk was from mmc_register() */ | |
1552 | ||
1553 | /* Setup dsr related values */ | |
1554 | mmc->dsr_imp = 0; | |
1555 | mmc->dsr = 0xffffffff; | |
1556 | /* Setup the universal parts of the block interface just once */ | |
1557 | bdesc->if_type = IF_TYPE_MMC; | |
1558 | bdesc->removable = 1; | |
1559 | ||
1560 | /* setup initial part type */ | |
1561 | bdesc->part_type = mmc->cfg->part_type; | |
1562 | mmc->dev = dev; | |
1563 | ||
1564 | return 0; | |
1565 | } | |
1566 | ||
1567 | int mmc_unbind(struct udevice *dev) | |
1568 | { | |
1569 | struct udevice *bdev; | |
1570 | ||
1571 | device_find_first_child(dev, &bdev); | |
1572 | if (bdev) { | |
1573 | device_remove(bdev); | |
1574 | device_unbind(bdev); | |
1575 | } | |
1576 | ||
1577 | return 0; | |
1578 | } | |
1579 | ||
1580 | #else | |
93bfd616 | 1581 | struct mmc *mmc_create(const struct mmc_config *cfg, void *priv) |
272cc70b | 1582 | { |
c40fdca6 | 1583 | struct blk_desc *bdesc; |
93bfd616 PA |
1584 | struct mmc *mmc; |
1585 | ||
1586 | /* quick validation */ | |
1587 | if (cfg == NULL || cfg->ops == NULL || cfg->ops->send_cmd == NULL || | |
1588 | cfg->f_min == 0 || cfg->f_max == 0 || cfg->b_max == 0) | |
1589 | return NULL; | |
1590 | ||
1591 | mmc = calloc(1, sizeof(*mmc)); | |
1592 | if (mmc == NULL) | |
1593 | return NULL; | |
1594 | ||
1595 | mmc->cfg = cfg; | |
1596 | mmc->priv = priv; | |
1597 | ||
1598 | /* the following chunk was mmc_register() */ | |
1599 | ||
ab71188c MN |
1600 | /* Setup dsr related values */ |
1601 | mmc->dsr_imp = 0; | |
1602 | mmc->dsr = 0xffffffff; | |
272cc70b | 1603 | /* Setup the universal parts of the block interface just once */ |
c40fdca6 SG |
1604 | bdesc = mmc_get_blk_desc(mmc); |
1605 | bdesc->if_type = IF_TYPE_MMC; | |
1606 | bdesc->removable = 1; | |
1607 | bdesc->devnum = mmc_get_next_devnum(); | |
1608 | bdesc->block_read = mmc_bread; | |
1609 | bdesc->block_write = mmc_bwrite; | |
1610 | bdesc->block_erase = mmc_berase; | |
272cc70b | 1611 | |
93bfd616 | 1612 | /* setup initial part type */ |
c40fdca6 SG |
1613 | bdesc->part_type = mmc->cfg->part_type; |
1614 | mmc_list_add(mmc); | |
93bfd616 PA |
1615 | |
1616 | return mmc; | |
1617 | } | |
1618 | ||
1619 | void mmc_destroy(struct mmc *mmc) | |
1620 | { | |
1621 | /* only freeing memory for now */ | |
1622 | free(mmc); | |
272cc70b | 1623 | } |
ad27dd5e | 1624 | #endif |
272cc70b | 1625 | |
3c457f4d | 1626 | static int mmc_get_dev(int dev, struct blk_desc **descp) |
663acabd SG |
1627 | { |
1628 | struct mmc *mmc = find_mmc_device(dev); | |
1629 | int ret; | |
1630 | ||
1631 | if (!mmc) | |
1632 | return -ENODEV; | |
1633 | ret = mmc_init(mmc); | |
1634 | if (ret) | |
1635 | return ret; | |
1636 | ||
1637 | *descp = &mmc->block_dev; | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
95de9ab2 PK |
1642 | /* board-specific MMC power initializations. */ |
1643 | __weak void board_mmc_power_init(void) | |
1644 | { | |
1645 | } | |
1646 | ||
e9550449 | 1647 | int mmc_start_init(struct mmc *mmc) |
272cc70b | 1648 | { |
afd5932b | 1649 | int err; |
272cc70b | 1650 | |
ab769f22 | 1651 | /* we pretend there's no card when init is NULL */ |
93bfd616 | 1652 | if (mmc_getcd(mmc) == 0 || mmc->cfg->ops->init == NULL) { |
48972d90 | 1653 | mmc->has_init = 0; |
56196826 | 1654 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
48972d90 | 1655 | printf("MMC: no card present\n"); |
56196826 | 1656 | #endif |
48972d90 TR |
1657 | return NO_CARD_ERR; |
1658 | } | |
1659 | ||
bc897b1d LW |
1660 | if (mmc->has_init) |
1661 | return 0; | |
1662 | ||
5a8dbdc6 YL |
1663 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
1664 | mmc_adapter_card_type_ident(); | |
1665 | #endif | |
95de9ab2 PK |
1666 | board_mmc_power_init(); |
1667 | ||
ab769f22 | 1668 | /* made sure it's not NULL earlier */ |
93bfd616 | 1669 | err = mmc->cfg->ops->init(mmc); |
272cc70b AF |
1670 | |
1671 | if (err) | |
1672 | return err; | |
1673 | ||
786e8f81 | 1674 | mmc->ddr_mode = 0; |
b86b85e2 IY |
1675 | mmc_set_bus_width(mmc, 1); |
1676 | mmc_set_clock(mmc, 1); | |
1677 | ||
272cc70b AF |
1678 | /* Reset the Card */ |
1679 | err = mmc_go_idle(mmc); | |
1680 | ||
1681 | if (err) | |
1682 | return err; | |
1683 | ||
bc897b1d | 1684 | /* The internal partition reset to user partition(0) at every CMD0*/ |
c40fdca6 | 1685 | mmc_get_blk_desc(mmc)->hwpart = 0; |
bc897b1d | 1686 | |
272cc70b | 1687 | /* Test for SD version 2 */ |
afd5932b | 1688 | err = mmc_send_if_cond(mmc); |
272cc70b | 1689 | |
272cc70b AF |
1690 | /* Now try to get the SD card's operating condition */ |
1691 | err = sd_send_op_cond(mmc); | |
1692 | ||
1693 | /* If the command timed out, we check for an MMC card */ | |
1694 | if (err == TIMEOUT) { | |
1695 | err = mmc_send_op_cond(mmc); | |
1696 | ||
bd47c135 | 1697 | if (err) { |
56196826 | 1698 | #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT) |
272cc70b | 1699 | printf("Card did not respond to voltage select!\n"); |
56196826 | 1700 | #endif |
272cc70b AF |
1701 | return UNUSABLE_ERR; |
1702 | } | |
1703 | } | |
1704 | ||
bd47c135 | 1705 | if (!err) |
e9550449 CLC |
1706 | mmc->init_in_progress = 1; |
1707 | ||
1708 | return err; | |
1709 | } | |
1710 | ||
1711 | static int mmc_complete_init(struct mmc *mmc) | |
1712 | { | |
1713 | int err = 0; | |
1714 | ||
bd47c135 | 1715 | mmc->init_in_progress = 0; |
e9550449 CLC |
1716 | if (mmc->op_cond_pending) |
1717 | err = mmc_complete_op_cond(mmc); | |
1718 | ||
1719 | if (!err) | |
1720 | err = mmc_startup(mmc); | |
bc897b1d LW |
1721 | if (err) |
1722 | mmc->has_init = 0; | |
1723 | else | |
1724 | mmc->has_init = 1; | |
e9550449 CLC |
1725 | return err; |
1726 | } | |
1727 | ||
1728 | int mmc_init(struct mmc *mmc) | |
1729 | { | |
bd47c135 | 1730 | int err = 0; |
d803fea5 | 1731 | unsigned start; |
e9550449 CLC |
1732 | |
1733 | if (mmc->has_init) | |
1734 | return 0; | |
d803fea5 MZ |
1735 | |
1736 | start = get_timer(0); | |
1737 | ||
e9550449 CLC |
1738 | if (!mmc->init_in_progress) |
1739 | err = mmc_start_init(mmc); | |
1740 | ||
bd47c135 | 1741 | if (!err) |
e9550449 CLC |
1742 | err = mmc_complete_init(mmc); |
1743 | debug("%s: %d, time %lu\n", __func__, err, get_timer(start)); | |
bc897b1d | 1744 | return err; |
272cc70b AF |
1745 | } |
1746 | ||
ab71188c MN |
1747 | int mmc_set_dsr(struct mmc *mmc, u16 val) |
1748 | { | |
1749 | mmc->dsr = val; | |
1750 | return 0; | |
1751 | } | |
1752 | ||
cee9ab7c JH |
1753 | /* CPU-specific MMC initializations */ |
1754 | __weak int cpu_mmc_init(bd_t *bis) | |
272cc70b AF |
1755 | { |
1756 | return -1; | |
1757 | } | |
1758 | ||
cee9ab7c JH |
1759 | /* board-specific MMC initializations. */ |
1760 | __weak int board_mmc_init(bd_t *bis) | |
1761 | { | |
1762 | return -1; | |
1763 | } | |
272cc70b | 1764 | |
e9550449 CLC |
1765 | void mmc_set_preinit(struct mmc *mmc, int preinit) |
1766 | { | |
1767 | mmc->preinit = preinit; | |
1768 | } | |
1769 | ||
8e3332e2 SS |
1770 | #if defined(CONFIG_DM_MMC) && defined(CONFIG_SPL_BUILD) |
1771 | static int mmc_probe(bd_t *bis) | |
1772 | { | |
1773 | return 0; | |
1774 | } | |
1775 | #elif defined(CONFIG_DM_MMC) | |
1776 | static int mmc_probe(bd_t *bis) | |
1777 | { | |
4a1db6d8 | 1778 | int ret, i; |
8e3332e2 | 1779 | struct uclass *uc; |
4a1db6d8 | 1780 | struct udevice *dev; |
8e3332e2 SS |
1781 | |
1782 | ret = uclass_get(UCLASS_MMC, &uc); | |
1783 | if (ret) | |
1784 | return ret; | |
1785 | ||
4a1db6d8 SG |
1786 | /* |
1787 | * Try to add them in sequence order. Really with driver model we | |
1788 | * should allow holes, but the current MMC list does not allow that. | |
1789 | * So if we request 0, 1, 3 we will get 0, 1, 2. | |
1790 | */ | |
1791 | for (i = 0; ; i++) { | |
1792 | ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev); | |
1793 | if (ret == -ENODEV) | |
1794 | break; | |
1795 | } | |
1796 | uclass_foreach_dev(dev, uc) { | |
1797 | ret = device_probe(dev); | |
8e3332e2 | 1798 | if (ret) |
4a1db6d8 | 1799 | printf("%s - probe failed: %d\n", dev->name, ret); |
8e3332e2 SS |
1800 | } |
1801 | ||
1802 | return 0; | |
1803 | } | |
1804 | #else | |
1805 | static int mmc_probe(bd_t *bis) | |
1806 | { | |
1807 | if (board_mmc_init(bis) < 0) | |
1808 | cpu_mmc_init(bis); | |
1809 | ||
1810 | return 0; | |
1811 | } | |
1812 | #endif | |
e9550449 | 1813 | |
272cc70b AF |
1814 | int mmc_initialize(bd_t *bis) |
1815 | { | |
1b26bab1 | 1816 | static int initialized = 0; |
8e3332e2 | 1817 | int ret; |
1b26bab1 DK |
1818 | if (initialized) /* Avoid initializing mmc multiple times */ |
1819 | return 0; | |
1820 | initialized = 1; | |
1821 | ||
c40fdca6 SG |
1822 | #ifndef CONFIG_BLK |
1823 | mmc_list_init(); | |
1824 | #endif | |
8e3332e2 SS |
1825 | ret = mmc_probe(bis); |
1826 | if (ret) | |
1827 | return ret; | |
272cc70b | 1828 | |
bb0dc108 | 1829 | #ifndef CONFIG_SPL_BUILD |
272cc70b | 1830 | print_mmc_devices(','); |
bb0dc108 | 1831 | #endif |
272cc70b | 1832 | |
c40fdca6 | 1833 | mmc_do_preinit(); |
272cc70b AF |
1834 | return 0; |
1835 | } | |
3690d6d6 A |
1836 | |
1837 | #ifdef CONFIG_SUPPORT_EMMC_BOOT | |
1838 | /* | |
1839 | * This function changes the size of boot partition and the size of rpmb | |
1840 | * partition present on EMMC devices. | |
1841 | * | |
1842 | * Input Parameters: | |
1843 | * struct *mmc: pointer for the mmc device strcuture | |
1844 | * bootsize: size of boot partition | |
1845 | * rpmbsize: size of rpmb partition | |
1846 | * | |
1847 | * Returns 0 on success. | |
1848 | */ | |
1849 | ||
1850 | int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize, | |
1851 | unsigned long rpmbsize) | |
1852 | { | |
1853 | int err; | |
1854 | struct mmc_cmd cmd; | |
1855 | ||
1856 | /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ | |
1857 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1858 | cmd.resp_type = MMC_RSP_R1b; | |
1859 | cmd.cmdarg = MMC_CMD62_ARG1; | |
1860 | ||
1861 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1862 | if (err) { | |
1863 | debug("mmc_boot_partition_size_change: Error1 = %d\n", err); | |
1864 | return err; | |
1865 | } | |
1866 | ||
1867 | /* Boot partition changing mode */ | |
1868 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1869 | cmd.resp_type = MMC_RSP_R1b; | |
1870 | cmd.cmdarg = MMC_CMD62_ARG2; | |
1871 | ||
1872 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1873 | if (err) { | |
1874 | debug("mmc_boot_partition_size_change: Error2 = %d\n", err); | |
1875 | return err; | |
1876 | } | |
1877 | /* boot partition size is multiple of 128KB */ | |
1878 | bootsize = (bootsize * 1024) / 128; | |
1879 | ||
1880 | /* Arg: boot partition size */ | |
1881 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1882 | cmd.resp_type = MMC_RSP_R1b; | |
1883 | cmd.cmdarg = bootsize; | |
1884 | ||
1885 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1886 | if (err) { | |
1887 | debug("mmc_boot_partition_size_change: Error3 = %d\n", err); | |
1888 | return err; | |
1889 | } | |
1890 | /* RPMB partition size is multiple of 128KB */ | |
1891 | rpmbsize = (rpmbsize * 1024) / 128; | |
1892 | /* Arg: RPMB partition size */ | |
1893 | cmd.cmdidx = MMC_CMD_RES_MAN; | |
1894 | cmd.resp_type = MMC_RSP_R1b; | |
1895 | cmd.cmdarg = rpmbsize; | |
1896 | ||
1897 | err = mmc_send_cmd(mmc, &cmd, NULL); | |
1898 | if (err) { | |
1899 | debug("mmc_boot_partition_size_change: Error4 = %d\n", err); | |
1900 | return err; | |
1901 | } | |
1902 | return 0; | |
1903 | } | |
1904 | ||
5a99b9de TR |
1905 | /* |
1906 | * Modify EXT_CSD[177] which is BOOT_BUS_WIDTH | |
1907 | * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH | |
1908 | * and BOOT_MODE. | |
1909 | * | |
1910 | * Returns 0 on success. | |
1911 | */ | |
1912 | int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) | |
1913 | { | |
1914 | int err; | |
1915 | ||
1916 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_BUS_WIDTH, | |
1917 | EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | | |
1918 | EXT_CSD_BOOT_BUS_WIDTH_RESET(reset) | | |
1919 | EXT_CSD_BOOT_BUS_WIDTH_WIDTH(width)); | |
1920 | ||
1921 | if (err) | |
1922 | return err; | |
1923 | return 0; | |
1924 | } | |
1925 | ||
792970b0 TR |
1926 | /* |
1927 | * Modify EXT_CSD[179] which is PARTITION_CONFIG (formerly BOOT_CONFIG) | |
1928 | * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and | |
1929 | * PARTITION_ACCESS. | |
1930 | * | |
1931 | * Returns 0 on success. | |
1932 | */ | |
1933 | int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access) | |
1934 | { | |
1935 | int err; | |
1936 | ||
1937 | err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF, | |
1938 | EXT_CSD_BOOT_ACK(ack) | | |
1939 | EXT_CSD_BOOT_PART_NUM(part_num) | | |
1940 | EXT_CSD_PARTITION_ACCESS(access)); | |
1941 | ||
1942 | if (err) | |
1943 | return err; | |
1944 | return 0; | |
1945 | } | |
33ace362 TR |
1946 | |
1947 | /* | |
1948 | * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value | |
1949 | * for enable. Note that this is a write-once field for non-zero values. | |
1950 | * | |
1951 | * Returns 0 on success. | |
1952 | */ | |
1953 | int mmc_set_rst_n_function(struct mmc *mmc, u8 enable) | |
1954 | { | |
1955 | return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_RST_N_FUNCTION, | |
1956 | enable); | |
1957 | } | |
3690d6d6 | 1958 | #endif |
663acabd SG |
1959 | |
1960 | U_BOOT_LEGACY_BLK(mmc) = { | |
1961 | .if_typename = "mmc", | |
1962 | .if_type = IF_TYPE_MMC, | |
1963 | .max_devs = -1, | |
3c457f4d | 1964 | .get_dev = mmc_get_dev, |
e17d1143 | 1965 | .select_hwpart = mmc_select_hwpartp, |
663acabd | 1966 | }; |