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gold: Add view and view_size parameters to is_call_to_non_split.
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
3d304f48
AB		 12016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
2 Maciej W. Rozycki <macro@imgtec.com>
3
4 PR sim/19441
5 * micromips.igen (delayslot_micromips): Enable for `micromips32',
6 `micromips64' and `micromipsdsp' only.
7 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
8 (do_micromips_jalr, do_micromips_jal): Likewise.
9 (compute_movep_src_reg): Likewise.
10 (compute_andi16_imm): Likewise.
11 (convert_fmt_micromips): Likewise.
12 (convert_fmt_micromips_cvt_d): Likewise.
13 (convert_fmt_micromips_cvt_s): Likewise.
14 (FMT_MICROMIPS): Likewise.
15 (FMT_MICROMIPS_CVT_D): Likewise.
16 (FMT_MICROMIPS_CVT_S): Likewise.
17
b36d953b
MF		 182016-01-12 Mike Frysinger <vapier@gentoo.org>
19
20 * interp.c: Include elf-bfd.h.
21 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
22 ELFCLASS32.
23
ce39bd38
MF		 242016-01-10 Mike Frysinger <vapier@gentoo.org>
25
26 * config.in, configure: Regenerate.
27
99d8e879
MF		 282016-01-10 Mike Frysinger <vapier@gentoo.org>
29
30 * configure: Regenerate.
31
35656e95
MF		 322016-01-10 Mike Frysinger <vapier@gentoo.org>
33
34 * configure: Regenerate.
35
16f7876d
MF		 362016-01-10 Mike Frysinger <vapier@gentoo.org>
37
38 * configure: Regenerate.
39
e19418e0
MF		 402016-01-10 Mike Frysinger <vapier@gentoo.org>
41
42 * configure: Regenerate.
43
6d90347b
MF		 442016-01-10 Mike Frysinger <vapier@gentoo.org>
45
46 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
47 * configure: Regenerate.
48
347fe5bb
MF		 492016-01-10 Mike Frysinger <vapier@gentoo.org>
50
51 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
52 * configure: Regenerate.
53
22be3fbe
MF		 542016-01-10 Mike Frysinger <vapier@gentoo.org>
55
56 * configure: Regenerate.
57
0dc73ef7
MF		 582016-01-10 Mike Frysinger <vapier@gentoo.org>
59
60 * configure: Regenerate.
61
936df756
MF		 622016-01-09 Mike Frysinger <vapier@gentoo.org>
63
64 * config.in, configure: Regenerate.
65
2e3d4f4d
MF		 662016-01-06 Mike Frysinger <vapier@gentoo.org>
67
68 * interp.c (sim_open): Mark argv const.
69 (sim_create_inferior): Mark argv and env const.
70
9bbf6f91
MF		 712016-01-04 Mike Frysinger <vapier@gentoo.org>
72
73 * configure: Regenerate.
74
77cf2ef5
MF		 752016-01-03 Mike Frysinger <vapier@gentoo.org>
76
77 * interp.c (sim_open): Update sim_parse_args comment.
78
0cb8d851
MF		 792016-01-03 Mike Frysinger <vapier@gentoo.org>
80
81 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
82 * configure: Regenerate.
83
1ac72f06
MF		 842016-01-02 Mike Frysinger <vapier@gentoo.org>
85
86 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
87 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
88 * configure: Regenerate.
89 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
90
d47f5b30
MF		 912016-01-02 Mike Frysinger <vapier@gentoo.org>
92
93 * dv-tx3904cpu.c (CPU, SD): Delete.
94
e1211e55
MF		 952015-12-30 Mike Frysinger <vapier@gentoo.org>
96
97 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
98 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
99 (sim_store_register): Rename to ...
100 (mips_reg_store): ... this. Delete local cpu var.
101 Update sim_io_eprintf calls.
102 (sim_fetch_register): Rename to ...
103 (mips_reg_fetch): ... this. Delete local cpu var.
104 Update sim_io_eprintf calls.
105
5e744ef8
MF		 1062015-12-27 Mike Frysinger <vapier@gentoo.org>
107
108 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
109
1b393626
MF		 1102015-12-26 Mike Frysinger <vapier@gentoo.org>
111
112 * config.in, configure: Regenerate.
113
26f8bf63
MF		 1142015-12-26 Mike Frysinger <vapier@gentoo.org>
115
116 * interp.c (sim_write, sim_read): Delete.
117 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
118 (load_word): Likewise.
119 * micromips.igen (cache): Likewise.
120 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
121 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
122 do_store_left, do_store_right, do_load_double, do_store_double):
123 Likewise.
124 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
125 (do_prefx): Likewise.
126 * sim-main.c (address_translation, prefetch): Delete.
127 (ifetch32, ifetch16): Delete call to AddressTranslation and set
128 paddr=vaddr.
129 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
130 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
131 (LoadMemory, StoreMemory): Delete CCA arg.
132
ef04e371
MF		 1332015-12-24 Mike Frysinger <vapier@gentoo.org>
134
135 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
136 * configure: Regenerated.
137
cb379ede
MF		 1382015-12-24 Mike Frysinger <vapier@gentoo.org>
139
140 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
141 * tconfig.h: Delete.
142
26936211
MF		 1432015-12-24 Mike Frysinger <vapier@gentoo.org>
144
145 * tconfig.h (SIM_HANDLES_LMA): Delete.
146
84e8e361
MF		 1472015-12-24 Mike Frysinger <vapier@gentoo.org>
148
149 * sim-main.h (WITH_WATCHPOINTS): Delete.
150
3cabaf66
MF		 1512015-12-24 Mike Frysinger <vapier@gentoo.org>
152
153 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
154
8abe6c66
MF		 1552015-12-24 Mike Frysinger <vapier@gentoo.org>
156
157 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
158
1d19cae7
DV		 1592015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
160
161 * micromips.igen (process_isa_mode): Fix left shift of negative
162 value.
163
cdf850e9
MF		 1642015-11-17 Mike Frysinger <vapier@gentoo.org>
165
166 * sim-main.h (WITH_MODULO_MEMORY): Delete.
167
797eee42
MF		 1682015-11-15 Mike Frysinger <vapier@gentoo.org>
169
170 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
171
6e4f085c
MF		 1722015-11-14 Mike Frysinger <vapier@gentoo.org>
173
174 * interp.c (sim_close): Rename to ...
175 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
176 sim_io_shutdown.
177 * sim-main.h (mips_sim_close): Declare.
178 (SIM_CLOSE_HOOK): Define.
179
8e394ffc
AB		 1802015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
181 Ali Lown <ali.lown@imgtec.com>
182
183 * Makefile.in (tmp-micromips): New rule.
184 (tmp-mach-multi): Add support for micromips.
185 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
186 that works for both mips64 and micromips64.
187 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
188 micromips32.
189 Add build support for micromips.
190 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
191 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
192 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
193 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
194 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
195 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
196 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
197 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
198 Refactored instruction code to use these functions.
199 * dsp2.igen: Refactored instruction code to use the new functions.
200 * interp.c (decode_coproc): Refactored to work with any instruction
201 encoding.
202 (isa_mode): New variable
203 (RSVD_INSTRUCTION): Changed to 0x00000039.
204 * m16.igen (BREAK16): Refactored instruction to use do_break16.
205 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
206 * micromips.dc: New file.
207 * micromips.igen: New file.
208 * micromips16.dc: New file.
209 * micromipsdsp.igen: New file.
210 * micromipsrun.c: New file.
211 * mips.igen (do_swc1): Changed to work with any instruction encoding.
212 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
213 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
214 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
215 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
216 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
217 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
218 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
219 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
220 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
221 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
222 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
223 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
224 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
225 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
226 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
227 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
228 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
229 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
230 instructions.
231 Refactored instruction code to use these functions.
232 (RSVD): Changed to use new reserved instruction.
233 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
234 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
235 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
236 do_store_double): Added micromips32 and micromips64 models.
237 Added include for micromips.igen and micromipsdsp.igen
238 Add micromips32 and micromips64 models.
239 (DecodeCoproc): Updated to use new macro definition.
240 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
241 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
242 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
243 Refactored instruction code to use these functions.
244 * sim-main.h (CP0_operation): New enum.
245 (DecodeCoproc): Updated macro.
246 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
247 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
248 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
249 ISA_MODE_MICROMIPS): New defines.
250 (sim_state): Add isa_mode field.
251
8d0978fb
MF		 2522015-06-23 Mike Frysinger <vapier@gentoo.org>
253
254 * configure: Regenerate.
255
306f4178
MF		 2562015-06-12 Mike Frysinger <vapier@gentoo.org>
257
258 * configure.ac: Change configure.in to configure.ac.
259 * configure: Regenerate.
260
a3487082
MF		 2612015-06-12 Mike Frysinger <vapier@gentoo.org>
262
263 * configure: Regenerate.
264
29bc024d
MF		 2652015-06-12 Mike Frysinger <vapier@gentoo.org>
266
267 * interp.c [TRACE]: Delete.
268 (TRACE): Change to WITH_TRACE_ANY_P.
269 [!WITH_TRACE_ANY_P] (open_trace): Define.
270 (mips_option_handler, open_trace, sim_close, dotrace):
271 Change defined(TRACE) to WITH_TRACE_ANY_P.
272 (sim_open): Delete TRACE ifdef check.
273 * sim-main.c (load_memory): Delete TRACE ifdef check.
274 (store_memory): Likewise.
275 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
276 [!WITH_TRACE_ANY_P] (dotrace): Define.
277
3ebe2863
MF		 2782015-04-18 Mike Frysinger <vapier@gentoo.org>
279
280 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
281 comments.
282
20bca71d
MF		 2832015-04-18 Mike Frysinger <vapier@gentoo.org>
284
285 * sim-main.h (SIM_CPU): Delete.
286
7e83aa92
MF		 2872015-04-18 Mike Frysinger <vapier@gentoo.org>
288
289 * sim-main.h (sim_cia): Delete.
290
034685f9
MF		 2912015-04-17 Mike Frysinger <vapier@gentoo.org>
292
293 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
294 PU_PC_GET.
295 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
296 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
297 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
298 CIA_SET to CPU_PC_SET.
299 * sim-main.h (CIA_GET, CIA_SET): Delete.
300
78e9aa70
MF		 3012015-04-15 Mike Frysinger <vapier@gentoo.org>
302
303 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
304 * sim-main.h (STATE_CPU): Delete.
305
bf12d44e
MF		 3062015-04-13 Mike Frysinger <vapier@gentoo.org>
307
308 * configure: Regenerate.
309
7bebb329
MF		 3102015-04-13 Mike Frysinger <vapier@gentoo.org>
311
312 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
313 * interp.c (mips_pc_get, mips_pc_set): New functions.
314 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
315 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
316 (sim_pc_get): Delete.
317 * sim-main.h (SIM_CPU): Define.
318 (struct sim_state): Change cpu to an array of pointers.
319 (STATE_CPU): Drop &.
320
8ac57fbd
MF		 3212015-04-13 Mike Frysinger <vapier@gentoo.org>
322
323 * interp.c (mips_option_handler, open_trace, sim_close,
324 sim_write, sim_read, sim_store_register, sim_fetch_register,
325 sim_create_inferior, pr_addr, pr_uword64): Convert old style
326 prototypes.
327 (sim_open): Convert old style prototype. Change casts with
328 sim_write to unsigned char *.
329 (fetch_str): Change null to unsigned char, and change cast to
330 unsigned char *.
331 (sim_monitor): Change c & ch to unsigned char. Change cast to
332 unsigned char *.
333
e787f858
MF		 3342015-04-12 Mike Frysinger <vapier@gentoo.org>
335
336 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
337
122bbfb5
MF		 3382015-04-06 Mike Frysinger <vapier@gentoo.org>
339
340 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
341
0fe84f3f
MF		 3422015-04-01 Mike Frysinger <vapier@gentoo.org>
343
344 * tconfig.h (SIM_HAVE_PROFILE): Delete.
345
aadc9410
MF		 3462015-03-31 Mike Frysinger <vapier@gentoo.org>
347
348 * config.in, configure: Regenerate.
349
05f53ed6
MF		 3502015-03-24 Mike Frysinger <vapier@gentoo.org>
351
352 * interp.c (sim_pc_get): New function.
353
c0931f26
MF		 3542015-03-24 Mike Frysinger <vapier@gentoo.org>
355
356 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
357 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
358
30452bbe
MF		 3592015-03-24 Mike Frysinger <vapier@gentoo.org>
360
361 * configure: Regenerate.
362
64dd13df
MF		 3632015-03-23 Mike Frysinger <vapier@gentoo.org>
364
365 * configure: Regenerate.
366
49cd1634
MF		 3672015-03-23 Mike Frysinger <vapier@gentoo.org>
368
369 * configure: Regenerate.
370 * configure.ac (mips_extra_objs): Delete.
371 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
372 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
373
3649cb06
MF		 3742015-03-23 Mike Frysinger <vapier@gentoo.org>
375
376 * configure: Regenerate.
377 * configure.ac: Delete sim_hw checks for dv-sockser.
378
ae7d0cac
MF		 3792015-03-16 Mike Frysinger <vapier@gentoo.org>
380
381 * config.in, configure: Regenerate.
382 * tconfig.in: Rename file ...
383 * tconfig.h: ... here.
384
8406bb59
MF		 3852015-03-15 Mike Frysinger <vapier@gentoo.org>
386
387 * tconfig.in: Delete includes.
388 [HAVE_DV_SOCKSER]: Delete.
389
465fb143
MF		 3902015-03-14 Mike Frysinger <vapier@gentoo.org>
391
392 * Makefile.in (SIM_RUN_OBJS): Delete.
393
5cddc23a
MF		 3942015-03-14 Mike Frysinger <vapier@gentoo.org>
395
396 * configure.ac (AC_CHECK_HEADERS): Delete.
397 * aclocal.m4, configure: Regenerate.
398
2974be62
AM		 3992014-08-19 Alan Modra <amodra@gmail.com>
400
401 * configure: Regenerate.
402
faa743bb
RM		 4032014-08-15 Roland McGrath <mcgrathr@google.com>
404
405 * configure: Regenerate.
406 * config.in: Regenerate.
407
1a8a700e
MF		 4082014-03-04 Mike Frysinger <vapier@gentoo.org>
409
410 * configure: Regenerate.
411
bf3d9781
AM		 4122013-09-23 Alan Modra <amodra@gmail.com>
413
414 * configure: Regenerate.
415
31e6ad7d
MF		 4162013-06-03 Mike Frysinger <vapier@gentoo.org>
417
418 * aclocal.m4, configure: Regenerate.
419
d3685d60
TT		 4202013-05-10 Freddie Chopin <freddie_chopin@op.pl>
421
422 * configure: Rebuild.
423
1517bd27
MF		 4242013-03-26 Mike Frysinger <vapier@gentoo.org>
425
426 * configure: Regenerate.
427
3be31516
JS		 4282013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
429
430 * configure.ac: Address use of dv-sockser.o.
431 * tconfig.in: Conditionalize use of dv_sockser_install.
432 * configure: Regenerated.
433 * config.in: Regenerated.
434
37cb8f8e
SE		 4352012-10-04 Chao-ying Fu <fu@mips.com>
436 Steve Ellcey <sellcey@mips.com>
437
438 * mips/mips3264r2.igen (rdhwr): New.
439
87c8644f
JS		 4402012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
441
442 * configure.ac: Always link against dv-sockser.o.
443 * configure: Regenerate.
444
5f3ef9d0
JB		 4452012-06-15 Joel Brobecker <brobecker@adacore.com>
446
447 * config.in, configure: Regenerate.
448
a6ff997c
NC		 4492012-05-18 Nick Clifton <nickc@redhat.com>
450
451 PR 14072
452 * interp.c: Include config.h before system header files.
453
2232061b
MF		 4542012-03-24 Mike Frysinger <vapier@gentoo.org>
455
456 * aclocal.m4, config.in, configure: Regenerate.
457
db2e4d67
MF		 4582011-12-03 Mike Frysinger <vapier@gentoo.org>
459
460 * aclocal.m4: New file.
461 * configure: Regenerate.
462
4399a56b
MF		 4632011-10-19 Mike Frysinger <vapier@gentoo.org>
464
465 * configure: Regenerate after common/acinclude.m4 update.
466
9c082ca8
MF		 4672011-10-17 Mike Frysinger <vapier@gentoo.org>
468
469 * configure.ac: Change include to common/acinclude.m4.
470
6ffe910a
MF		 4712011-10-17 Mike Frysinger <vapier@gentoo.org>
472
473 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
474 call. Replace common.m4 include with SIM_AC_COMMON.
475 * configure: Regenerate.
476
31b28250
HPN		 4772011-07-08 Hans-Peter Nilsson <hp@axis.com>
478
3faa01e3
HPN		 479 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
480 $(SIM_EXTRA_DEPS).
481 (tmp-mach-multi): Exit early when igen fails.
31b28250 482
2419798b
MF		 4832011-07-05 Mike Frysinger <vapier@gentoo.org>
484
485 * interp.c (sim_do_command): Delete.
486
d79fe0d6
MF		 4872011-02-14 Mike Frysinger <vapier@gentoo.org>
488
489 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
490 (tx3904sio_fifo_reset): Likewise.
491 * interp.c (sim_monitor): Likewise.
492
5558e7e6
MF		 4932010-04-14 Mike Frysinger <vapier@gentoo.org>
494
495 * interp.c (sim_write): Add const to buffer arg.
496
35aafff4
JB		 4972010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
498
499 * interp.c: Don't include sysdep.h
500
3725885a
RW		 5012010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
502
503 * configure: Regenerate.
504
d6416cdc
RW		 5052009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
506
81ecdfbb
RW		 507 * config.in: Regenerate.
508 * configure: Likewise.
509
d6416cdc
RW		 510 * configure: Regenerate.
511
b5bd9624
HPN		 5122008-07-11 Hans-Peter Nilsson <hp@axis.com>
513
514 * configure: Regenerate to track ../common/common.m4 changes.
515 * config.in: Ditto.
516
6efef468 5172008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 518 Daniel Jacobowitz <dan@codesourcery.com>
519 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 520
521 * configure: Regenerate.
522
60dc88db
RS		 5232007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
524
525 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
526 that unconditionally allows fmt_ps.
527 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
528 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
529 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
530 filter from 64,f to 32,f.
531 (PREFX): Change filter from 64 to 32.
532 (LDXC1, LUXC1): Provide separate mips32r2 implementations
533 that use do_load_double instead of do_load. Make both LUXC1
534 versions unpredictable if SizeFGR () != 64.
535 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
536 instead of do_store. Remove unused variable. Make both SUXC1
537 versions unpredictable if SizeFGR () != 64.
538
599ca73e
RS		 5392007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
540
541 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
542 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
543 shifts for that case.
544
2525df03
NC		 5452007-09-04 Nick Clifton <nickc@redhat.com>
546
547 * interp.c (options enum): Add OPTION_INFO_MEMORY.
548 (display_mem_info): New static variable.
549 (mips_option_handler): Handle OPTION_INFO_MEMORY.
550 (mips_options): Add info-memory and memory-info.
551 (sim_open): After processing the command line and board
552 specification, check display_mem_info. If it is set then
553 call the real handler for the --memory-info command line
554 switch.
555
35ee6e1e
JB		 5562007-08-24 Joel Brobecker <brobecker@adacore.com>
557
558 * configure.ac: Change license of multi-run.c to GPL version 3.
559 * configure: Regenerate.
560
d5fb0879
RS		 5612007-06-28 Richard Sandiford <richard@codesourcery.com>
562
563 * configure.ac, configure: Revert last patch.
564
2a2ce21b
RS		 5652007-06-26 Richard Sandiford <richard@codesourcery.com>
566
567 * configure.ac (sim_mipsisa3264_configs): New variable.
568 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
569 every configuration support all four targets, using the triplet to
570 determine the default.
571 * configure: Regenerate.
572
efdcccc9
RS		 5732007-06-25 Richard Sandiford <richard@codesourcery.com>
574
0a7692b2 575 * Makefile.in (m16run.o): New rule.
efdcccc9 576
f532a356
TS		 5772007-05-15 Thiemo Seufer <ths@mips.com>
578
579 * mips3264r2.igen (DSHD): Fix compile warning.
580
bfe9c90b
TS		 5812007-05-14 Thiemo Seufer <ths@mips.com>
582
583 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
584 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
585 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
586 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
587 for mips32r2.
588
53f4826b
TS		 5892007-03-01 Thiemo Seufer <ths@mips.com>
590
591 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
592 and mips64.
593
8bf3ddc8
TS		 5942007-02-20 Thiemo Seufer <ths@mips.com>
595
596 * dsp.igen: Update copyright notice.
597 * dsp2.igen: Fix copyright notice.
598
8b082fb1 5992007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 600 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 601
602 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
603 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
604 Add dsp2 to sim_igen_machine.
605 * configure: Regenerate.
606 * dsp.igen (do_ph_op): Add MUL support when op = 2.
607 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
608 (mulq_rs.ph): Use do_ph_mulq.
609 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
610 * mips.igen: Add dsp2 model and include dsp2.igen.
611 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
612 for *mips32r2, *mips64r2, *dsp.
613 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
614 for *mips32r2, *mips64r2, *dsp2.
615 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
616
b1004875 6172007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 618 Nigel Stephens <nigel@mips.com>
b1004875
TS		 619
620 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
621 jumps with hazard barrier.
622
f8df4c77 6232007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 624 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 625
626 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
627 after each call to sim_io_write.
628
b1004875 6292007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 630 Nigel Stephens <nigel@mips.com>
b1004875
TS		 631
632 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
633 supported by this simulator.
07802d98
TS		 634 (decode_coproc): Recognise additional CP0 Config registers
635 correctly.
636
14fb6c5a 6372007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 638 Nigel Stephens <nigel@mips.com>
639 David Ung <davidu@mips.com>
14fb6c5a
TS		 640
641 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
642 uninterpreted formats. If fmt is one of the uninterpreted types
643 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
644 fmt_word, and fmt_uninterpreted_64 like fmt_long.
645 (store_fpr): When writing an invalid odd register, set the
646 matching even register to fmt_unknown, not the following register.
647 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
648 the the memory window at offset 0 set by --memory-size command
649 line option.
650 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
651 point register.
652 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
653 register.
654 (sim_monitor): When returning the memory size to the MIPS
655 application, use the value in STATE_MEM_SIZE, not an arbitrary
656 hardcoded value.
657 (cop_lw): Don' mess around with FPR_STATE, just pass
658 fmt_uninterpreted_32 to StoreFPR.
659 (cop_sw): Similarly.
660 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
661 (cop_sd): Similarly.
662 * mips.igen (not_word_value): Single version for mips32, mips64
663 and mips16.
664
c8847145 6652007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 666 Nigel Stephens <nigel@mips.com>
c8847145
TS		 667
668 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
669 MBytes.
670
4b5d35ee
TS		 6712007-02-17 Thiemo Seufer <ths@mips.com>
672
673 * configure.ac (mips*-sde-elf*): Move in front of generic machine
674 configuration.
675 * configure: Regenerate.
676
3669427c
TS		 6772007-02-17 Thiemo Seufer <ths@mips.com>
678
679 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
680 Add mdmx to sim_igen_machine.
681 (mipsisa64*-*-*): Likewise. Remove dsp.
682 (mipsisa32*-*-*): Remove dsp.
683 * configure: Regenerate.
684
109ad085
TS		 6852007-02-13 Thiemo Seufer <ths@mips.com>
686
687 * configure.ac: Add mips*-sde-elf* target.
688 * configure: Regenerate.
689
921d7ad3
HPN		 6902006-12-21 Hans-Peter Nilsson <hp@axis.com>
691
692 * acconfig.h: Remove.
693 * config.in, configure: Regenerate.
694
02f97da7
TS		 6952006-11-07 Thiemo Seufer <ths@mips.com>
696
697 * dsp.igen (do_w_op): Fix compiler warning.
698
2d2733fc 6992006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 700 David Ung <davidu@mips.com>
2d2733fc
TS		 701
702 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
703 sim_igen_machine.
704 * configure: Regenerate.
705 * mips.igen (model): Add smartmips.
706 (MADDU): Increment ACX if carry.
707 (do_mult): Clear ACX.
708 (ROR,RORV): Add smartmips.
72f4393d 709 (include): Include smartmips.igen.
2d2733fc
TS		 710 * sim-main.h (ACX): Set to REGISTERS[89].
711 * smartmips.igen: New file.
712
d85c3a10 7132006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 714 David Ung <davidu@mips.com>
d85c3a10
TS		 715
716 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
717 mips3264r2.igen. Add missing dependency rules.
718 * m16e.igen: Support for mips16e save/restore instructions.
719
e85e3205
RE		 7202006-06-13 Richard Earnshaw <rearnsha@arm.com>
721
722 * configure: Regenerated.
723
2f0122dc
DJ		 7242006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
725
726 * configure: Regenerated.
727
20e95c23
DJ		 7282006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
729
730 * configure: Regenerated.
731
69088b17
CF		 7322006-05-15 Chao-ying Fu <fu@mips.com>
733
734 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
735
0275de4e
NC		 7362006-04-18 Nick Clifton <nickc@redhat.com>
737
738 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
739 statement.
740
b3a3ffef
HPN		 7412006-03-29 Hans-Peter Nilsson <hp@axis.com>
742
743 * configure: Regenerate.
744
40a5538e
CF		 7452005-12-14 Chao-ying Fu <fu@mips.com>
746
747 * Makefile.in (SIM_OBJS): Add dsp.o.
748 (dsp.o): New dependency.
749 (IGEN_INCLUDE): Add dsp.igen.
750 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
751 mipsisa64*-*-*): Add dsp to sim_igen_machine.
752 * configure: Regenerate.
753 * mips.igen: Add dsp model and include dsp.igen.
754 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
755 because these instructions are extended in DSP ASE.
756 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
757 adding 6 DSP accumulator registers and 1 DSP control register.
758 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
759 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
760 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
761 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
762 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
763 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
764 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
765 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
766 DSPCR_CCOND_SMASK): New define.
767 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
768 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
769
21d14896
ILT		 7702005-07-08 Ian Lance Taylor <ian@airs.com>
771
772 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
773
b16d63da 7742005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 775 Nigel Stephens <nigel@mips.com>
776
777 * mips.igen: New mips16e model and include m16e.igen.
778 (check_u64): Add mips16e tag.
779 * m16e.igen: New file for MIPS16e instructions.
780 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
781 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
782 models.
783 * configure: Regenerate.
b16d63da 784
e70cb6cd 7852005-05-26 David Ung <davidu@mips.com>
72f4393d 786
e70cb6cd
CD		 787 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
788 tags to all instructions which are applicable to the new ISAs.
789 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
790 vr.igen.
791 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 792 instructions.
e70cb6cd
CD		 793 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
794 to mips.igen.
795 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
796 * configure: Regenerate.
72f4393d 797
2b193c4a
MK		 7982005-03-23 Mark Kettenis <kettenis@gnu.org>
799
800 * configure: Regenerate.
801
35695fd6
AC		 8022005-01-14 Andrew Cagney <cagney@gnu.org>
803
804 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
805 explicit call to AC_CONFIG_HEADER.
806 * configure: Regenerate.
807
f0569246
AC		 8082005-01-12 Andrew Cagney <cagney@gnu.org>
809
810 * configure.ac: Update to use ../common/common.m4.
811 * configure: Re-generate.
812
38f48d72
AC		 8132005-01-11 Andrew Cagney <cagney@localhost.localdomain>
814
815 * configure: Regenerated to track ../common/aclocal.m4 changes.
816
b7026657
AC		 8172005-01-07 Andrew Cagney <cagney@gnu.org>
818
819 * configure.ac: Rename configure.in, require autoconf 2.59.
820 * configure: Re-generate.
821
379832de
HPN		 8222004-12-08 Hans-Peter Nilsson <hp@axis.com>
823
824 * configure: Regenerate for ../common/aclocal.m4 update.
825
cd62154c 8262004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 827
cd62154c
AC		 828 Committed by Andrew Cagney.
829 * m16.igen (CMP, CMPI): Fix assembler.
830
e5da76ec
CD		 8312004-08-18 Chris Demetriou <cgd@broadcom.com>
832
833 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
834 * configure: Regenerate.
835
139181c8
CD		 8362004-06-25 Chris Demetriou <cgd@broadcom.com>
837
838 * configure.in (sim_m16_machine): Include mipsIII.
839 * configure: Regenerate.
840
1a27f959
CD		 8412004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
842
72f4393d 843 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 844 from COP0_BADVADDR.
845 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
846
5dbb7b5a
CD		 8472004-04-10 Chris Demetriou <cgd@broadcom.com>
848
849 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
850
14234056
CD		 8512004-04-09 Chris Demetriou <cgd@broadcom.com>
852
853 * mips.igen (check_fmt): Remove.
854 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
855 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
856 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
857 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
858 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
859 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
860 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
861 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
862 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
863 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
864
c6f9085c
CD		 8652004-04-09 Chris Demetriou <cgd@broadcom.com>
866
867 * sb1.igen (check_sbx): New function.
868 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
869
11d66e66 8702004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 871 Richard Sandiford <rsandifo@redhat.com>
872
873 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
874 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
875 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
876 separate implementations for mipsIV and mipsV. Use new macros to
877 determine whether the restrictions apply.
878
b3208fb8
CD		 8792004-01-19 Chris Demetriou <cgd@broadcom.com>
880
881 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
882 (check_mult_hilo): Improve comments.
883 (check_div_hilo): Likewise. Also, fork off a new version
884 to handle mips32/mips64 (since there are no hazards to check
885 in MIPS32/MIPS64).
886
9a1d84fb
CD		 8872003-06-17 Richard Sandiford <rsandifo@redhat.com>
888
889 * mips.igen (do_dmultx): Fix check for negative operands.
890
ae451ac6
ILT		 8912003-05-16 Ian Lance Taylor <ian@airs.com>
892
893 * Makefile.in (SHELL): Make sure this is defined.
894 (various): Use $(SHELL) whenever we invoke move-if-change.
895
dd69d292
CD		 8962003-05-03 Chris Demetriou <cgd@broadcom.com>
897
898 * cp1.c: Tweak attribution slightly.
899 * cp1.h: Likewise.
900 * mdmx.c: Likewise.
901 * mdmx.igen: Likewise.
902 * mips3d.igen: Likewise.
903 * sb1.igen: Likewise.
904
bcd0068e
CD		 9052003-04-15 Richard Sandiford <rsandifo@redhat.com>
906
907 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
908 unsigned operands.
909
6b4a8935
AC		 9102003-02-27 Andrew Cagney <cagney@redhat.com>
911
601da316
AC		 912 * interp.c (sim_open): Rename _bfd to bfd.
913 (sim_create_inferior): Ditto.
6b4a8935 914
d29e330f
CD		 9152003-01-14 Chris Demetriou <cgd@broadcom.com>
916
917 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
918
a2353a08
CD		 9192003-01-14 Chris Demetriou <cgd@broadcom.com>
920
921 * mips.igen (EI, DI): Remove.
922
80551777
CD		 9232003-01-05 Richard Sandiford <rsandifo@redhat.com>
924
925 * Makefile.in (tmp-run-multi): Fix mips16 filter.
926
4c54fc26
CD		 9272003-01-04 Richard Sandiford <rsandifo@redhat.com>
928 Andrew Cagney <ac131313@redhat.com>
929 Gavin Romig-Koch <gavin@redhat.com>
930 Graydon Hoare <graydon@redhat.com>
931 Aldy Hernandez <aldyh@redhat.com>
932 Dave Brolley <brolley@redhat.com>
933 Chris Demetriou <cgd@broadcom.com>
934
935 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
936 (sim_mach_default): New variable.
937 (mips64vr-*-*, mips64vrel-*-*): New configurations.
938 Add a new simulator generator, MULTI.
939 * configure: Regenerate.
940 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
941 (multi-run.o): New dependency.
942 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
943 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
944 (tmp-multi): Combine them.
945 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
946 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
947 (distclean-extra): New rule.
948 * sim-main.h: Include bfd.h.
949 (MIPS_MACH): New macro.
950 * mips.igen (vr4120, vr5400, vr5500): New models.
951 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
952 * vr.igen: Replace with new version.
953
e6c674b8
CD		 9542003-01-04 Chris Demetriou <cgd@broadcom.com>
955
956 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
957 * configure: Regenerate.
958
28f50ac8
CD		 9592002-12-31 Chris Demetriou <cgd@broadcom.com>
960
961 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
962 * mips.igen: Remove all invocations of check_branch_bug and
963 mark_branch_bug.
964
5071ffe6
CD		 9652002-12-16 Chris Demetriou <cgd@broadcom.com>
966
72f4393d 967 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 968
06e7837e
CD		 9692002-07-30 Chris Demetriou <cgd@broadcom.com>
970
971 * mips.igen (do_load_double, do_store_double): New functions.
972 (LDC1, SDC1): Rename to...
973 (LDC1b, SDC1b): respectively.
974 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
975
2265c243
MS		 9762002-07-29 Michael Snyder <msnyder@redhat.com>
977
978 * cp1.c (fp_recip2): Modify initialization expression so that
979 GCC will recognize it as constant.
980
a2f8b4f3
CD		 9812002-06-18 Chris Demetriou <cgd@broadcom.com>
982
983 * mdmx.c (SD_): Delete.
984 (Unpredictable): Re-define, for now, to directly invoke
985 unpredictable_action().
986 (mdmx_acc_op): Fix error in .ob immediate handling.
987
b4b6c939
AC		 9882002-06-18 Andrew Cagney <cagney@redhat.com>
989
990 * interp.c (sim_firmware_command): Initialize `address'.
991
c8cca39f
AC		 9922002-06-16 Andrew Cagney <ac131313@redhat.com>
993
994 * configure: Regenerated to track ../common/aclocal.m4 changes.
995
e7e81181 9962002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 997 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 998
999 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1000 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1001 * mips.igen: Include mips3d.igen.
1002 (mips3d): New model name for MIPS-3D ASE instructions.
1003 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1004 instructions.
e7e81181
CD		 1005 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1006 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1007 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1008 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1009 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1010 (RSquareRoot1, RSquareRoot2): New macros.
1011 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1012 (fp_rsqrt2): New functions.
1013 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1014 * configure: Regenerate.
1015
3a2b820e 10162002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1017 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1018
1019 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1020 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1021 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1022 (convert): Note that this function is not used for paired-single
1023 format conversions.
1024 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1025 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1026 (check_fmt_p): Enable paired-single support.
1027 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1028 (PUU.PS): New instructions.
1029 (CVT.S.fmt): Don't use this instruction for paired-single format
1030 destinations.
1031 * sim-main.h (FP_formats): New value 'fmt_ps.'
1032 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1033 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1034
d18ea9c2
CD		 10352002-06-12 Chris Demetriou <cgd@broadcom.com>
1036
1037 * mips.igen: Fix formatting of function calls in
1038 many FP operations.
1039
95fd5cee
CD		 10402002-06-12 Chris Demetriou <cgd@broadcom.com>
1041
1042 * mips.igen (MOVN, MOVZ): Trace result.
1043 (TNEI): Print "tnei" as the opcode name in traces.
1044 (CEIL.W): Add disassembly string for traces.
1045 (RSQRT.fmt): Make location of disassembly string consistent
1046 with other instructions.
1047
4f0d55ae
CD		 10482002-06-12 Chris Demetriou <cgd@broadcom.com>
1049
1050 * mips.igen (X): Delete unused function.
1051
3c25f8c7
AC		 10522002-06-08 Andrew Cagney <cagney@redhat.com>
1053
1054 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1055
f3c08b7e 10562002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1057 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1058
1059 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1060 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1061 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1062 (fp_nmsub): New prototypes.
1063 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1064 (NegMultiplySub): New defines.
1065 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1066 (MADD.D, MADD.S): Replace with...
1067 (MADD.fmt): New instruction.
1068 (MSUB.D, MSUB.S): Replace with...
1069 (MSUB.fmt): New instruction.
1070 (NMADD.D, NMADD.S): Replace with...
1071 (NMADD.fmt): New instruction.
1072 (NMSUB.D, MSUB.S): Replace with...
1073 (NMSUB.fmt): New instruction.
1074
52714ff9 10752002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1076 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1077
1078 * cp1.c: Fix more comment spelling and formatting.
1079 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1080 (denorm_mode): New function.
1081 (fpu_unary, fpu_binary): Round results after operation, collect
1082 status from rounding operations, and update the FCSR.
1083 (convert): Collect status from integer conversions and rounding
1084 operations, and update the FCSR. Adjust NaN values that result
1085 from conversions. Convert to use sim_io_eprintf rather than
1086 fprintf, and remove some debugging code.
1087 * cp1.h (fenr_FS): New define.
1088
577d8c4b
CD		 10892002-06-07 Chris Demetriou <cgd@broadcom.com>
1090
1091 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1092 rounding mode to sim FP rounding mode flag conversion code into...
1093 (rounding_mode): New function.
1094
196496ed
CD		 10952002-06-07 Chris Demetriou <cgd@broadcom.com>
1096
1097 * cp1.c: Clean up formatting of a few comments.
1098 (value_fpr): Reformat switch statement.
1099
cfe9ea23 11002002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1101 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1102
1103 * cp1.h: New file.
1104 * sim-main.h: Include cp1.h.
1105 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1106 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1107 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1108 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1109 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1110 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1111 * cp1.c: Don't include sim-fpu.h; already included by
1112 sim-main.h. Clean up formatting of some comments.
1113 (NaN, Equal, Less): Remove.
1114 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1115 (fp_cmp): New functions.
1116 * mips.igen (do_c_cond_fmt): Remove.
1117 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1118 Compare. Add result tracing.
1119 (CxC1): Remove, replace with...
1120 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1121 (DMxC1): Remove, replace with...
1122 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1123 (MxC1): Remove, replace with...
1124 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1125
ee7254b0
CD		 11262002-06-04 Chris Demetriou <cgd@broadcom.com>
1127
1128 * sim-main.h (FGRIDX): Remove, replace all uses with...
1129 (FGR_BASE): New macro.
1130 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1131 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1132 (NR_FGR, FGR): Likewise.
1133 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1134 * mips.igen: Likewise.
1135
d3eb724f
CD		 11362002-06-04 Chris Demetriou <cgd@broadcom.com>
1137
1138 * cp1.c: Add an FSF Copyright notice to this file.
1139
ba46ddd0 11402002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1141 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1142
1143 * cp1.c (Infinity): Remove.
1144 * sim-main.h (Infinity): Likewise.
1145
1146 * cp1.c (fp_unary, fp_binary): New functions.
1147 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1148 (fp_sqrt): New functions, implemented in terms of the above.
1149 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1150 (Recip, SquareRoot): Remove (replaced by functions above).
1151 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1152 (fp_recip, fp_sqrt): New prototypes.
1153 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1154 (Recip, SquareRoot): Replace prototypes with #defines which
1155 invoke the functions above.
72f4393d 1156
18d8a52d
CD		 11572002-06-03 Chris Demetriou <cgd@broadcom.com>
1158
1159 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1160 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1161 file, remove PARAMS from prototypes.
1162 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1163 simulator state arguments.
1164 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1165 pass simulator state arguments.
1166 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1167 (store_fpr, convert): Remove 'sd' argument.
1168 (value_fpr): Likewise. Convert to use 'SD' instead.
1169
0f154cbd
CD		 11702002-06-03 Chris Demetriou <cgd@broadcom.com>
1171
1172 * cp1.c (Min, Max): Remove #if 0'd functions.
1173 * sim-main.h (Min, Max): Remove.
1174
e80fc152
CD		 11752002-06-03 Chris Demetriou <cgd@broadcom.com>
1176
1177 * cp1.c: fix formatting of switch case and default labels.
1178 * interp.c: Likewise.
1179 * sim-main.c: Likewise.
1180
bad673a9
CD		 11812002-06-03 Chris Demetriou <cgd@broadcom.com>
1182
1183 * cp1.c: Clean up comments which describe FP formats.
1184 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1185
7cbea089 11862002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1187 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1188
1189 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1190 Broadcom SiByte SB-1 processor configurations.
1191 * configure: Regenerate.
1192 * sb1.igen: New file.
1193 * mips.igen: Include sb1.igen.
1194 (sb1): New model.
1195 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1196 * mdmx.igen: Add "sb1" model to all appropriate functions and
1197 instructions.
1198 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1199 (ob_func, ob_acc): Reference the above.
1200 (qh_acc): Adjust to keep the same size as ob_acc.
1201 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1202 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1203
909daa82
CD		 12042002-06-03 Chris Demetriou <cgd@broadcom.com>
1205
1206 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1207
f4f1b9f1 12082002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1209 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1210
1211 * mips.igen (mdmx): New (pseudo-)model.
1212 * mdmx.c, mdmx.igen: New files.
1213 * Makefile.in (SIM_OBJS): Add mdmx.o.
1214 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1215 New typedefs.
1216 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1217 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1218 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1219 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1220 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1221 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1222 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1223 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1224 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1225 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1226 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1227 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1228 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1229 (qh_fmtsel): New macros.
1230 (_sim_cpu): New member "acc".
1231 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1232 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1233
5accf1ff
CD		 12342002-05-01 Chris Demetriou <cgd@broadcom.com>
1235
1236 * interp.c: Use 'deprecated' rather than 'depreciated.'
1237 * sim-main.h: Likewise.
1238
402586aa
CD		 12392002-05-01 Chris Demetriou <cgd@broadcom.com>
1240
1241 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1242 which wouldn't compile anyway.
1243 * sim-main.h (unpredictable_action): New function prototype.
1244 (Unpredictable): Define to call igen function unpredictable().
1245 (NotWordValue): New macro to call igen function not_word_value().
1246 (UndefinedResult): Remove.
1247 * interp.c (undefined_result): Remove.
1248 (unpredictable_action): New function.
1249 * mips.igen (not_word_value, unpredictable): New functions.
1250 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1251 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1252 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1253 NotWordValue() to check for unpredictable inputs, then
1254 Unpredictable() to handle them.
1255
c9b9995a
CD		 12562002-02-24 Chris Demetriou <cgd@broadcom.com>
1257
1258 * mips.igen: Fix formatting of calls to Unpredictable().
1259
e1015982
AC		 12602002-04-20 Andrew Cagney <ac131313@redhat.com>
1261
1262 * interp.c (sim_open): Revert previous change.
1263
b882a66b
AO		 12642002-04-18 Alexandre Oliva <aoliva@redhat.com>
1265
1266 * interp.c (sim_open): Disable chunk of code that wrote code in
1267 vector table entries.
1268
c429b7dd
CD		 12692002-03-19 Chris Demetriou <cgd@broadcom.com>
1270
1271 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1272 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1273 unused definitions.
1274
37d146fa
CD		 12752002-03-19 Chris Demetriou <cgd@broadcom.com>
1276
1277 * cp1.c: Fix many formatting issues.
1278
07892c0b
CD		 12792002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1280
1281 * cp1.c (fpu_format_name): New function to replace...
1282 (DOFMT): This. Delete, and update all callers.
1283 (fpu_rounding_mode_name): New function to replace...
1284 (RMMODE): This. Delete, and update all callers.
1285
487f79b7
CD		 12862002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1287
1288 * interp.c: Move FPU support routines from here to...
1289 * cp1.c: Here. New file.
1290 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1291 (cp1.o): New target.
1292
1e799e28
CD		 12932002-03-12 Chris Demetriou <cgd@broadcom.com>
1294
1295 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1296 * mips.igen (mips32, mips64): New models, add to all instructions
1297 and functions as appropriate.
1298 (loadstore_ea, check_u64): New variant for model mips64.
1299 (check_fmt_p): New variant for models mipsV and mips64, remove
1300 mipsV model marking fro other variant.
1301 (SLL) Rename to...
1302 (SLLa) this.
1303 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1304 for mips32 and mips64.
1305 (DCLO, DCLZ): New instructions for mips64.
1306
82f728db
CD		 13072002-03-07 Chris Demetriou <cgd@broadcom.com>
1308
1309 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1310 immediate or code as a hex value with the "%#lx" format.
1311 (ANDI): Likewise, and fix printed instruction name.
1312
b96e7ef1
CD		 13132002-03-05 Chris Demetriou <cgd@broadcom.com>
1314
1315 * sim-main.h (UndefinedResult, Unpredictable): New macros
1316 which currently do nothing.
1317
d35d4f70
CD		 13182002-03-05 Chris Demetriou <cgd@broadcom.com>
1319
1320 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1321 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1322 (status_CU3): New definitions.
1323
1324 * sim-main.h (ExceptionCause): Add new values for MIPS32
1325 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1326 for DebugBreakPoint and NMIReset to note their status in
1327 MIPS32 and MIPS64.
1328 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1329 (SignalExceptionCacheErr): New exception macros.
1330
3ad6f714
CD		 13312002-03-05 Chris Demetriou <cgd@broadcom.com>
1332
1333 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1334 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1335 is always enabled.
1336 (SignalExceptionCoProcessorUnusable): Take as argument the
1337 unusable coprocessor number.
1338
86b77b47
CD		 13392002-03-05 Chris Demetriou <cgd@broadcom.com>
1340
1341 * mips.igen: Fix formatting of all SignalException calls.
1342
97a88e93 13432002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1344
1345 * sim-main.h (SIGNEXTEND): Remove.
1346
97a88e93 13472002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1348
1349 * mips.igen: Remove gencode comment from top of file, fix
1350 spelling in another comment.
1351
97a88e93 13522002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1353
1354 * mips.igen (check_fmt, check_fmt_p): New functions to check
1355 whether specific floating point formats are usable.
1356 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1357 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1358 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1359 Use the new functions.
1360 (do_c_cond_fmt): Remove format checks...
1361 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1362
97a88e93 13632002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1364
1365 * mips.igen: Fix formatting of check_fpu calls.
1366
41774c9d
CD		 13672002-03-03 Chris Demetriou <cgd@broadcom.com>
1368
1369 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1370
4a0bd876
CD		 13712002-03-03 Chris Demetriou <cgd@broadcom.com>
1372
1373 * mips.igen: Remove whitespace at end of lines.
1374
09297648
CD		 13752002-03-02 Chris Demetriou <cgd@broadcom.com>
1376
1377 * mips.igen (loadstore_ea): New function to do effective
1378 address calculations.
1379 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1380 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1381 CACHE): Use loadstore_ea to do effective address computations.
1382
043b7057
CD		 13832002-03-02 Chris Demetriou <cgd@broadcom.com>
1384
1385 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1386 * mips.igen (LL, CxC1, MxC1): Likewise.
1387
c1e8ada4
CD		 13882002-03-02 Chris Demetriou <cgd@broadcom.com>
1389
1390 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1391 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1392 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1393 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1394 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1395 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1396 Don't split opcode fields by hand, use the opcode field values
1397 provided by igen.
1398
3e1dca16
CD		 13992002-03-01 Chris Demetriou <cgd@broadcom.com>
1400
1401 * mips.igen (do_divu): Fix spacing.
1402
1403 * mips.igen (do_dsllv): Move to be right before DSLLV,
1404 to match the rest of the do_<shift> functions.
1405
fff8d27d
CD		 14062002-03-01 Chris Demetriou <cgd@broadcom.com>
1407
1408 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1409 DSRL32, do_dsrlv): Trace inputs and results.
1410
0d3e762b
CD		 14112002-03-01 Chris Demetriou <cgd@broadcom.com>
1412
1413 * mips.igen (CACHE): Provide instruction-printing string.
1414
1415 * interp.c (signal_exception): Comment tokens after #endif.
1416
eb5fcf93
CD		 14172002-02-28 Chris Demetriou <cgd@broadcom.com>
1418
1419 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1420 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1421 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1422 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1423 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1424 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1425 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1426 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1427
bb22bd7d
CD		 14282002-02-28 Chris Demetriou <cgd@broadcom.com>
1429
1430 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1431 instruction-printing string.
1432 (LWU): Use '64' as the filter flag.
1433
91a177cf
CD		 14342002-02-28 Chris Demetriou <cgd@broadcom.com>
1435
1436 * mips.igen (SDXC1): Fix instruction-printing string.
1437
387f484a
CD		 14382002-02-28 Chris Demetriou <cgd@broadcom.com>
1439
1440 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1441 filter flags "32,f".
1442
3d81f391
CD		 14432002-02-27 Chris Demetriou <cgd@broadcom.com>
1444
1445 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1446 as the filter flag.
1447
af5107af
CD		 14482002-02-27 Chris Demetriou <cgd@broadcom.com>
1449
1450 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1451 add a comma) so that it more closely match the MIPS ISA
1452 documentation opcode partitioning.
1453 (PREF): Put useful names on opcode fields, and include
1454 instruction-printing string.
1455
ca971540
CD		 14562002-02-27 Chris Demetriou <cgd@broadcom.com>
1457
1458 * mips.igen (check_u64): New function which in the future will
1459 check whether 64-bit instructions are usable and signal an
1460 exception if not. Currently a no-op.
1461 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1462 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1463 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1464 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1465
1466 * mips.igen (check_fpu): New function which in the future will
1467 check whether FPU instructions are usable and signal an exception
1468 if not. Currently a no-op.
1469 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1470 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1471 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1472 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1473 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1474 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1475 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1476 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1477
1c47a468
CD		 14782002-02-27 Chris Demetriou <cgd@broadcom.com>
1479
1480 * mips.igen (do_load_left, do_load_right): Move to be immediately
1481 following do_load.
1482 (do_store_left, do_store_right): Move to be immediately following
1483 do_store.
1484
603a98e7
CD		 14852002-02-27 Chris Demetriou <cgd@broadcom.com>
1486
1487 * mips.igen (mipsV): New model name. Also, add it to
1488 all instructions and functions where it is appropriate.
1489
c5d00cc7
CD		 14902002-02-18 Chris Demetriou <cgd@broadcom.com>
1491
1492 * mips.igen: For all functions and instructions, list model
1493 names that support that instruction one per line.
1494
074e9cb8
CD		 14952002-02-11 Chris Demetriou <cgd@broadcom.com>
1496
1497 * mips.igen: Add some additional comments about supported
1498 models, and about which instructions go where.
1499 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1500 order as is used in the rest of the file.
1501
9805e229
CD		 15022002-02-11 Chris Demetriou <cgd@broadcom.com>
1503
1504 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1505 indicating that ALU32_END or ALU64_END are there to check
1506 for overflow.
1507 (DADD): Likewise, but also remove previous comment about
1508 overflow checking.
1509
f701dad2
CD		 15102002-02-10 Chris Demetriou <cgd@broadcom.com>
1511
1512 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1513 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1514 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1515 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1516 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1517 fields (i.e., add and move commas) so that they more closely
1518 match the MIPS ISA documentation opcode partitioning.
1519
15202002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1521
72f4393d
L		 1522 * mips.igen (ADDI): Print immediate value.
1523 (BREAK): Print code.
1524 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1525 (SLL): Print "nop" specially, and don't run the code
1526 that does the shift for the "nop" case.
20ae0098 1527
9e52972e
FF		 15282001-11-17 Fred Fish <fnf@redhat.com>
1529
1530 * sim-main.h (float_operation): Move enum declaration outside
1531 of _sim_cpu struct declaration.
1532
c0efbca4
JB		 15332001-04-12 Jim Blandy <jimb@redhat.com>
1534
1535 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1536 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1537 set of the FCSR.
1538 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1539 PENDING_FILL, and you can get the intended effect gracefully by
1540 calling PENDING_SCHED directly.
1541
fb891446
BE		 15422001-02-23 Ben Elliston <bje@redhat.com>
1543
1544 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1545 already defined elsewhere.
1546
8030f857
BE		 15472001-02-19 Ben Elliston <bje@redhat.com>
1548
1549 * sim-main.h (sim_monitor): Return an int.
1550 * interp.c (sim_monitor): Add return values.
1551 (signal_exception): Handle error conditions from sim_monitor.
1552
56b48a7a
CD		 15532001-02-08 Ben Elliston <bje@redhat.com>
1554
1555 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1556 (store_memory): Likewise, pass cia to sim_core_write*.
1557
d3ee60d9
FCE		 15582000-10-19 Frank Ch. Eigler <fche@redhat.com>
1559
1560 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1561 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1562
071da002
AC		 1563Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1564
1565 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1566 * Makefile.in: Don't delete *.igen when cleaning directory.
1567
a28c02cd
AC		 1568Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1569
1570 * m16.igen (break): Call SignalException not sim_engine_halt.
1571
80ee11fa
AC		 1572Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1573
1574 From Jason Eckhardt:
1575 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1576
673388c0
AC		 1577Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1578
1579 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1580
4c0deff4
NC		 15812000-05-24 Michael Hayes <mhayes@cygnus.com>
1582
1583 * mips.igen (do_dmultx): Fix typo.
1584
eb2d80b4
AC		 1585Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1586
1587 * configure: Regenerated to track ../common/aclocal.m4 changes.
1588
dd37a34b
AC		 1589Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1590
1591 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1592
4c0deff4
NC		 15932000-04-12 Frank Ch. Eigler <fche@redhat.com>
1594
1595 * sim-main.h (GPR_CLEAR): Define macro.
1596
e30db738
AC		 1597Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 * interp.c (decode_coproc): Output long using %lx and not %s.
1600
cb7450ea
FCE		 16012000-03-21 Frank Ch. Eigler <fche@redhat.com>
1602
1603 * interp.c (sim_open): Sort & extend dummy memory regions for
1604 --board=jmr3904 for eCos.
1605
a3027dd7
FCE		 16062000-03-02 Frank Ch. Eigler <fche@redhat.com>
1607
1608 * configure: Regenerated.
1609
1610Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1611
1612 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1613 calls, conditional on the simulator being in verbose mode.
1614
dfcd3bfb
JM		 1615Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1616
1617 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1618 cache don't get ReservedInstruction traps.
1619
c2d11a7d
JM		 16201999-11-29 Mark Salter <msalter@cygnus.com>
1621
1622 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1623 to clear status bits in sdisr register. This is how the hardware works.
1624
1625 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1626 being used by cygmon.
1627
4ce44c66
JM		 16281999-11-11 Andrew Haley <aph@cygnus.com>
1629
1630 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1631 instructions.
1632
cff3e48b
JM		 1633Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1634
1635 * mips.igen (MULT): Correct previous mis-applied patch.
1636
d4f3574e
SS		 1637Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1638
1639 * mips.igen (delayslot32): Handle sequence like
1640 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1641 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1642 (MULT): Actually pass the third register...
1643
16441999-09-03 Mark Salter <msalter@cygnus.com>
1645
1646 * interp.c (sim_open): Added more memory aliases for additional
1647 hardware being touched by cygmon on jmr3904 board.
1648
1649Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1650
1651 * configure: Regenerated to track ../common/aclocal.m4 changes.
1652
a0b3c4fd
JM		 1653Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1654
1655 * interp.c (sim_store_register): Handle case where client - GDB -
1656 specifies that a 4 byte register is 8 bytes in size.
1657 (sim_fetch_register): Ditto.
72f4393d 1658
adf40b2e
JM		 16591999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1660
1661 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1662 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1663 (idt_monitor_base): Base address for IDT monitor traps.
1664 (pmon_monitor_base): Ditto for PMON.
1665 (lsipmon_monitor_base): Ditto for LSI PMON.
1666 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1667 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1668 (sim_firmware_command): New function.
1669 (mips_option_handler): Call it for OPTION_FIRMWARE.
1670 (sim_open): Allocate memory for idt_monitor region. If "--board"
1671 option was given, add no monitor by default. Add BREAK hooks only if
1672 monitors are also there.
72f4393d 1673
43e526b9
JM		 1674Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1675
1676 * interp.c (sim_monitor): Flush output before reading input.
1677
1678Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1679
1680 * tconfig.in (SIM_HANDLES_LMA): Always define.
1681
1682Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1683
1684 From Mark Salter <msalter@cygnus.com>:
1685 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1686 (sim_open): Add setup for BSP board.
1687
9846de1b
JM		 1688Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1689
1690 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1691 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1692 them as unimplemented.
1693
cd0fc7c3
SS		 16941999-05-08 Felix Lee <flee@cygnus.com>
1695
1696 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1697
7a292a7a
SS		 16981999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1699
1700 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1701
1702Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1703
1704 * configure.in: Any mips64vr5*-*-* target should have
1705 -DTARGET_ENABLE_FR=1.
1706 (default_endian): Any mips64vr*el-*-* target should default to
1707 LITTLE_ENDIAN.
1708 * configure: Re-generate.
1709
17101999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1711
1712 * mips.igen (ldl): Extend from _16_, not 32.
1713
1714Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1715
1716 * interp.c (sim_store_register): Force registers written to by GDB
1717 into an un-interpreted state.
1718
c906108c
SS		 17191999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1720
1721 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1722 CPU, start periodic background I/O polls.
72f4393d 1723 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1724
17251998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1726
1727 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1728
c906108c
SS		 1729Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1730
1731 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1732 case statement.
1733
17341998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1735
1736 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1737 (load_word): Call SIM_CORE_SIGNAL hook on error.
1738 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1739 starting. For exception dispatching, pass PC instead of NULL_CIA.
1740 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1741 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1742 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1743 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1744 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1745 * mips.igen (*): Replace memory-related SignalException* calls
1746 with references to SIM_CORE_SIGNAL hook.
72f4393d 1747
c906108c
SS		 1748 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1749 fix.
1750 * sim-main.c (*): Minor warning cleanups.
72f4393d 1751
c906108c
SS		 17521998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1753
1754 * m16.igen (DADDIU5): Correct type-o.
1755
1756Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1757
1758 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1759 variables.
1760
1761Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1762
1763 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1764 to include path.
1765 (interp.o): Add dependency on itable.h
1766 (oengine.c, gencode): Delete remaining references.
1767 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1768
c906108c 17691998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1770
c906108c
SS		 1771 * vr4run.c: New.
1772 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1773 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1774 tmp-run-hack) : New.
1775 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1776 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1777 Drop the "64" qualifier to get the HACK generator working.
1778 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1779 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1780 qualifier to get the hack generator working.
1781 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1782 (DSLL): Use do_dsll.
1783 (DSLLV): Use do_dsllv.
1784 (DSRA): Use do_dsra.
1785 (DSRL): Use do_dsrl.
1786 (DSRLV): Use do_dsrlv.
1787 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1788 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1789 get the HACK generator working.
1790 (MACC) Rename to get the HACK generator working.
1791 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1792
c906108c
SS		 17931998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1794
1795 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1796 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1797
c906108c
SS		 17981998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1799
1800 * mips/interp.c (DEBUG): Cleanups.
1801
18021998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1803
1804 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1805 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1806
c906108c
SS		 18071998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1808
1809 * interp.c (sim_close): Uninstall modules.
1810
1811Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1812
1813 * sim-main.h, interp.c (sim_monitor): Change to global
1814 function.
1815
1816Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1817
1818 * configure.in (vr4100): Only include vr4100 instructions in
1819 simulator.
1820 * configure: Re-generate.
1821 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1822
1823Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1824
1825 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1826 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1827 true alternative.
1828
1829 * configure.in (sim_default_gen, sim_use_gen): Replace with
1830 sim_gen.
1831 (--enable-sim-igen): Delete config option. Always using IGEN.
1832 * configure: Re-generate.
72f4393d 1833
c906108c
SS		 1834 * Makefile.in (gencode): Kill, kill, kill.
1835 * gencode.c: Ditto.
72f4393d 1836
c906108c
SS		 1837Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1838
1839 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1840 bit mips16 igen simulator.
1841 * configure: Re-generate.
1842
1843 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1844 as part of vr4100 ISA.
1845 * vr.igen: Mark all instructions as 64 bit only.
1846
1847Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1848
1849 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1850 Pacify GCC.
1851
1852Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1853
1854 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1855 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1856 * configure: Re-generate.
1857
1858 * m16.igen (BREAK): Define breakpoint instruction.
1859 (JALX32): Mark instruction as mips16 and not r3900.
1860 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1861
1862 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1863
1864Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1865
1866 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1867 insn as a debug breakpoint.
1868
1869 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1870 pending.slot_size.
1871 (PENDING_SCHED): Clean up trace statement.
1872 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1873 (PENDING_FILL): Delay write by only one cycle.
1874 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1875
1876 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1877 of pending writes.
1878 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1879 32 & 64.
1880 (pending_tick): Move incrementing of index to FOR statement.
1881 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1882
c906108c
SS		 1883 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1884 build simulator.
1885 * configure: Re-generate.
72f4393d 1886
c906108c
SS		 1887 * interp.c (sim_engine_run OLD): Delete explicit call to
1888 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1889
c906108c
SS		 1890Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1891
1892 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1893 interrupt level number to match changed SignalExceptionInterrupt
1894 macro.
1895
1896Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1897
1898 * interp.c: #include "itable.h" if WITH_IGEN.
1899 (get_insn_name): New function.
1900 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1901 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1902
1903Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1904
1905 * configure: Rebuilt to inhale new common/aclocal.m4.
1906
1907Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1908
1909 * dv-tx3904sio.c: Include sim-assert.h.
1910
1911Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1912
1913 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1914 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1915 Reorganize target-specific sim-hardware checks.
1916 * configure: rebuilt.
1917 * interp.c (sim_open): For tx39 target boards, set
1918 OPERATING_ENVIRONMENT, add tx3904sio devices.
1919 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1920 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1921
c906108c
SS		 1922 * dv-tx3904irc.c: Compiler warning clean-up.
1923 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1924 frequent hw-trace messages.
1925
1926Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1927
1928 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1929
1930Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1931
1932 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1933
1934 * vr.igen: New file.
1935 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1936 * mips.igen: Define vr4100 model. Include vr.igen.
1937Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1938
1939 * mips.igen (check_mf_hilo): Correct check.
1940
1941Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1942
1943 * sim-main.h (interrupt_event): Add prototype.
1944
1945 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1946 register_ptr, register_value.
1947 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1948
1949 * sim-main.h (tracefh): Make extern.
1950
1951Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1952
1953 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1954 Reduce unnecessarily high timer event frequency.
c906108c 1955 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1956
c906108c
SS		 1957Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1958
1959 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1960 to allay warnings.
1961 (interrupt_event): Made non-static.
72f4393d 1962
c906108c
SS		 1963 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1964 interchange of configuration values for external vs. internal
1965 clock dividers.
72f4393d 1966
c906108c
SS		 1967Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1968
72f4393d 1969 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1970 simulator-reserved break instructions.
1971 * gencode.c (build_instruction): Ditto.
1972 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1973 reserved instructions now use exception vector, rather
c906108c
SS		 1974 than halting sim.
1975 * sim-main.h: Moved magic constants to here.
1976
1977Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1978
1979 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1980 register upon non-zero interrupt event level, clear upon zero
1981 event value.
1982 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1983 by passing zero event value.
1984 (*_io_{read,write}_buffer): Endianness fixes.
1985 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1986 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1987
1988 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1989 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1990
c906108c
SS		 1991Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1992
72f4393d 1993 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 1994 and BigEndianCPU.
1995
1996Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
1997
1998 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1999 parts.
2000 * configure: Update.
2001
2002Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2003
2004 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2005 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2006 * configure.in: Include tx3904tmr in hw_device list.
2007 * configure: Rebuilt.
2008 * interp.c (sim_open): Instantiate three timer instances.
2009 Fix address typo of tx3904irc instance.
2010
2011Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2012
2013 * interp.c (signal_exception): SystemCall exception now uses
2014 the exception vector.
2015
2016Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2017
2018 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2019 to allay warnings.
2020
2021Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2022
2023 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2024
2025Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2026
2027 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2028
2029 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2030 sim-main.h. Declare a struct hw_descriptor instead of struct
2031 hw_device_descriptor.
2032
2033Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2034
2035 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2036 right bits and then re-align left hand bytes to correct byte
2037 lanes. Fix incorrect computation in do_store_left when loading
2038 bytes from second word.
2039
2040Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2041
2042 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2043 * interp.c (sim_open): Only create a device tree when HW is
2044 enabled.
2045
2046 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2047 * interp.c (signal_exception): Ditto.
2048
2049Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2050
2051 * gencode.c: Mark BEGEZALL as LIKELY.
2052
2053Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2054
2055 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2056 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2057
c906108c
SS		 2058Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2059
2060 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2061 modules. Recognize TX39 target with "mips*tx39" pattern.
2062 * configure: Rebuilt.
2063 * sim-main.h (*): Added many macros defining bits in
2064 TX39 control registers.
2065 (SignalInterrupt): Send actual PC instead of NULL.
2066 (SignalNMIReset): New exception type.
2067 * interp.c (board): New variable for future use to identify
2068 a particular board being simulated.
2069 (mips_option_handler,mips_options): Added "--board" option.
2070 (interrupt_event): Send actual PC.
2071 (sim_open): Make memory layout conditional on board setting.
2072 (signal_exception): Initial implementation of hardware interrupt
2073 handling. Accept another break instruction variant for simulator
2074 exit.
2075 (decode_coproc): Implement RFE instruction for TX39.
2076 (mips.igen): Decode RFE instruction as such.
2077 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2078 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2079 bbegin to implement memory map.
2080 * dv-tx3904cpu.c: New file.
2081 * dv-tx3904irc.c: New file.
2082
2083Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2084
2085 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2086
2087Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2088
2089 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2090 with calls to check_div_hilo.
2091
2092Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2093
2094 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2095 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2096 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2097 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2098 with calls to check_mult_hilo.
2099 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2100 with calls to check_div_hilo.
2101
2102Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2103
2104 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2105 Document a replacement.
2106
2107Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2108
2109 * interp.c (sim_monitor): Make mon_printf work.
2110
2111Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2112
2113 * sim-main.h (INSN_NAME): New arg `cpu'.
2114
2115Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2116
72f4393d 2117 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2118
2119Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2120
2121 * configure: Regenerated to track ../common/aclocal.m4 changes.
2122 * config.in: Ditto.
2123
2124Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2125
2126 * acconfig.h: New file.
2127 * configure.in: Reverted change of Apr 24; use sinclude again.
2128
2129Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2130
2131 * configure: Regenerated to track ../common/aclocal.m4 changes.
2132 * config.in: Ditto.
2133
2134Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2135
2136 * configure.in: Don't call sinclude.
2137
2138Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2139
2140 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2141
2142Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2143
2144 * mips.igen (ERET): Implement.
2145
2146 * interp.c (decode_coproc): Return sign-extended EPC.
2147
2148 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2149
2150 * interp.c (signal_exception): Do not ignore Trap.
2151 (signal_exception): On TRAP, restart at exception address.
2152 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2153 (signal_exception): Update.
2154 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2155 so that TRAP instructions are caught.
2156
2157Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2158
2159 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2160 contains HI/LO access history.
2161 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2162 (HIACCESS, LOACCESS): Delete, replace with
2163 (HIHISTORY, LOHISTORY): New macros.
2164 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2165
c906108c
SS		 2166 * gencode.c (build_instruction): Do not generate checks for
2167 correct HI/LO register usage.
2168
2169 * interp.c (old_engine_run): Delete checks for correct HI/LO
2170 register usage.
2171
2172 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2173 check_mf_cycles): New functions.
2174 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2175 do_divu, domultx, do_mult, do_multu): Use.
2176
2177 * tx.igen ("madd", "maddu"): Use.
72f4393d 2178
c906108c
SS		 2179Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2180
2181 * mips.igen (DSRAV): Use function do_dsrav.
2182 (SRAV): Use new function do_srav.
2183
2184 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2185 (B): Sign extend 11 bit immediate.
2186 (EXT-B*): Shift 16 bit immediate left by 1.
2187 (ADDIU*): Don't sign extend immediate value.
2188
2189Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2190
2191 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2192
2193 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2194 functions.
2195
2196 * mips.igen (delayslot32, nullify_next_insn): New functions.
2197 (m16.igen): Always include.
2198 (do_*): Add more tracing.
2199
2200 * m16.igen (delayslot16): Add NIA argument, could be called by a
2201 32 bit MIPS16 instruction.
72f4393d 2202
c906108c
SS		 2203 * interp.c (ifetch16): Move function from here.
2204 * sim-main.c (ifetch16): To here.
72f4393d 2205
c906108c
SS		 2206 * sim-main.c (ifetch16, ifetch32): Update to match current
2207 implementations of LH, LW.
2208 (signal_exception): Don't print out incorrect hex value of illegal
2209 instruction.
2210
2211Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2212
2213 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2214 instruction.
2215
2216 * m16.igen: Implement MIPS16 instructions.
72f4393d 2217
c906108c
SS		 2218 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2219 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2220 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2221 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2222 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2223 bodies of corresponding code from 32 bit insn to these. Also used
2224 by MIPS16 versions of functions.
72f4393d 2225
c906108c
SS		 2226 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2227 (IMEM16): Drop NR argument from macro.
2228
2229Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2230
2231 * Makefile.in (SIM_OBJS): Add sim-main.o.
2232
2233 * sim-main.h (address_translation, load_memory, store_memory,
2234 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2235 as INLINE_SIM_MAIN.
2236 (pr_addr, pr_uword64): Declare.
2237 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2238
c906108c
SS		 2239 * interp.c (address_translation, load_memory, store_memory,
2240 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2241 from here.
2242 * sim-main.c: To here. Fix compilation problems.
72f4393d 2243
c906108c
SS		 2244 * configure.in: Enable inlining.
2245 * configure: Re-config.
2246
2247Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2248
2249 * configure: Regenerated to track ../common/aclocal.m4 changes.
2250
2251Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2252
2253 * mips.igen: Include tx.igen.
2254 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2255 * tx.igen: New file, contains MADD and MADDU.
2256
2257 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2258 the hardwired constant `7'.
2259 (store_memory): Ditto.
2260 (LOADDRMASK): Move definition to sim-main.h.
2261
2262 mips.igen (MTC0): Enable for r3900.
2263 (ADDU): Add trace.
2264
2265 mips.igen (do_load_byte): Delete.
2266 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2267 do_store_right): New functions.
2268 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2269
2270 configure.in: Let the tx39 use igen again.
2271 configure: Update.
72f4393d 2272
c906108c
SS		 2273Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2274
2275 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2276 not an address sized quantity. Return zero for cache sizes.
2277
2278Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2279
2280 * mips.igen (r3900): r3900 does not support 64 bit integer
2281 operations.
2282
2283Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2284
2285 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2286 than igen one.
2287 * configure : Rebuild.
72f4393d 2288
c906108c
SS		 2289Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2290
2291 * configure: Regenerated to track ../common/aclocal.m4 changes.
2292
2293Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2294
2295 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2296
2297Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2298
2299 * configure: Regenerated to track ../common/aclocal.m4 changes.
2300 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2301
2302Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2303
2304 * configure: Regenerated to track ../common/aclocal.m4 changes.
2305
2306Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2307
2308 * interp.c (Max, Min): Comment out functions. Not yet used.
2309
2310Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2311
2312 * configure: Regenerated to track ../common/aclocal.m4 changes.
2313
2314Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2315
2316 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2317 configurable settings for stand-alone simulator.
72f4393d 2318
c906108c 2319 * configure.in: Added X11 search, just in case.
72f4393d 2320
c906108c
SS		 2321 * configure: Regenerated.
2322
2323Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2324
2325 * interp.c (sim_write, sim_read, load_memory, store_memory):
2326 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2327
2328Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2329
2330 * sim-main.h (GETFCC): Return an unsigned value.
2331
2332Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2333
2334 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2335 (DADD): Result destination is RD not RT.
2336
2337Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2338
2339 * sim-main.h (HIACCESS, LOACCESS): Always define.
2340
2341 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2342
2343 * interp.c (sim_info): Delete.
2344
2345Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2346
2347 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2348 (mips_option_handler): New argument `cpu'.
2349 (sim_open): Update call to sim_add_option_table.
2350
2351Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2352
2353 * mips.igen (CxC1): Add tracing.
2354
2355Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2356
2357 * sim-main.h (Max, Min): Declare.
2358
2359 * interp.c (Max, Min): New functions.
2360
2361 * mips.igen (BC1): Add tracing.
72f4393d 2362
c906108c 2363Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2364
c906108c 2365 * interp.c Added memory map for stack in vr4100
72f4393d 2366
c906108c
SS		 2367Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2368
2369 * interp.c (load_memory): Add missing "break"'s.
2370
2371Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2372
2373 * interp.c (sim_store_register, sim_fetch_register): Pass in
2374 length parameter. Return -1.
2375
2376Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2377
2378 * interp.c: Added hardware init hook, fixed warnings.
2379
2380Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2381
2382 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2383
2384Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2385
2386 * interp.c (ifetch16): New function.
2387
2388 * sim-main.h (IMEM32): Rename IMEM.
2389 (IMEM16_IMMED): Define.
2390 (IMEM16): Define.
2391 (DELAY_SLOT): Update.
72f4393d 2392
c906108c 2393 * m16run.c (sim_engine_run): New file.
72f4393d 2394
c906108c
SS		 2395 * m16.igen: All instructions except LB.
2396 (LB): Call do_load_byte.
2397 * mips.igen (do_load_byte): New function.
2398 (LB): Call do_load_byte.
2399
2400 * mips.igen: Move spec for insn bit size and high bit from here.
2401 * Makefile.in (tmp-igen, tmp-m16): To here.
2402
2403 * m16.dc: New file, decode mips16 instructions.
2404
2405 * Makefile.in (SIM_NO_ALL): Define.
2406 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2407
2408Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2409
2410 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2411 point unit to 32 bit registers.
2412 * configure: Re-generate.
2413
2414Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2415
2416 * configure.in (sim_use_gen): Make IGEN the default simulator
2417 generator for generic 32 and 64 bit mips targets.
2418 * configure: Re-generate.
2419
2420Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2421
2422 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2423 bitsize.
2424
2425 * interp.c (sim_fetch_register, sim_store_register): Read/write
2426 FGR from correct location.
2427 (sim_open): Set size of FGR's according to
2428 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2429
c906108c
SS		 2430 * sim-main.h (FGR): Store floating point registers in a separate
2431 array.
2432
2433Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2434
2435 * configure: Regenerated to track ../common/aclocal.m4 changes.
2436
2437Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2438
2439 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2440
2441 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2442
2443 * interp.c (pending_tick): New function. Deliver pending writes.
2444
2445 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2446 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2447 it can handle mixed sized quantites and single bits.
72f4393d 2448
c906108c
SS		 2449Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2450
2451 * interp.c (oengine.h): Do not include when building with IGEN.
2452 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2453 (sim_info): Ditto for PROCESSOR_64BIT.
2454 (sim_monitor): Replace ut_reg with unsigned_word.
2455 (*): Ditto for t_reg.
2456 (LOADDRMASK): Define.
2457 (sim_open): Remove defunct check that host FP is IEEE compliant,
2458 using software to emulate floating point.
2459 (value_fpr, ...): Always compile, was conditional on HASFPU.
2460
2461Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2462
2463 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2464 size.
2465
2466 * interp.c (SD, CPU): Define.
2467 (mips_option_handler): Set flags in each CPU.
2468 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2469 (sim_close): Do not clear STATE, deleted anyway.
2470 (sim_write, sim_read): Assume CPU zero's vm should be used for
2471 data transfers.
2472 (sim_create_inferior): Set the PC for all processors.
2473 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2474 argument.
2475 (mips16_entry): Pass correct nr of args to store_word, load_word.
2476 (ColdReset): Cold reset all cpu's.
2477 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2478 (sim_monitor, load_memory, store_memory, signal_exception): Use
2479 `CPU' instead of STATE_CPU.
2480
2481
2482 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2483 SD or CPU_.
72f4393d 2484
c906108c
SS		 2485 * sim-main.h (signal_exception): Add sim_cpu arg.
2486 (SignalException*): Pass both SD and CPU to signal_exception.
2487 * interp.c (signal_exception): Update.
72f4393d 2488
c906108c
SS		 2489 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2490 Ditto
2491 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2492 address_translation): Ditto
2493 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2494
c906108c
SS		 2495Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2496
2497 * configure: Regenerated to track ../common/aclocal.m4 changes.
2498
2499Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2500
2501 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2502
72f4393d 2503 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2504
2505 * sim-main.h (CPU_CIA): Delete.
2506 (SET_CIA, GET_CIA): Define
2507
2508Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2509
2510 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2511 regiser.
2512
2513 * configure.in (default_endian): Configure a big-endian simulator
2514 by default.
2515 * configure: Re-generate.
72f4393d 2516
c906108c
SS		 2517Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2518
2519 * configure: Regenerated to track ../common/aclocal.m4 changes.
2520
2521Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2522
2523 * interp.c (sim_monitor): Handle Densan monitor outbyte
2524 and inbyte functions.
2525
25261997-12-29 Felix Lee <flee@cygnus.com>
2527
2528 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2529
2530Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2531
2532 * Makefile.in (tmp-igen): Arrange for $zero to always be
2533 reset to zero after every instruction.
2534
2535Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2536
2537 * configure: Regenerated to track ../common/aclocal.m4 changes.
2538 * config.in: Ditto.
2539
2540Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2541
2542 * mips.igen (MSUB): Fix to work like MADD.
2543 * gencode.c (MSUB): Similarly.
2544
2545Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2546
2547 * configure: Regenerated to track ../common/aclocal.m4 changes.
2548
2549Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2550
2551 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2552
2553Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2554
2555 * sim-main.h (sim-fpu.h): Include.
2556
2557 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2558 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2559 using host independant sim_fpu module.
2560
2561Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2562
2563 * interp.c (signal_exception): Report internal errors with SIGABRT
2564 not SIGQUIT.
2565
2566 * sim-main.h (C0_CONFIG): New register.
2567 (signal.h): No longer include.
2568
2569 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2570
2571Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2572
2573 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2574
2575Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2576
2577 * mips.igen: Tag vr5000 instructions.
2578 (ANDI): Was missing mipsIV model, fix assembler syntax.
2579 (do_c_cond_fmt): New function.
2580 (C.cond.fmt): Handle mips I-III which do not support CC field
2581 separatly.
2582 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2583 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2584 in IV3.2 spec.
2585 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2586 vr5000 which saves LO in a GPR separatly.
72f4393d 2587
c906108c
SS		 2588 * configure.in (enable-sim-igen): For vr5000, select vr5000
2589 specific instructions.
2590 * configure: Re-generate.
72f4393d 2591
c906108c
SS		 2592Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2593
2594 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2595
2596 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2597 fmt_uninterpreted_64 bit cases to switch. Convert to
2598 fmt_formatted,
2599
2600 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2601
2602 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2603 as specified in IV3.2 spec.
2604 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2605
2606Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2607
2608 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2609 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2610 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2611 PENDING_FILL versions of instructions. Simplify.
2612 (X): New function.
2613 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2614 instructions.
2615 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2616 a signed value.
2617 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2618
c906108c
SS		 2619 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2620 global.
2621 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2622
2623Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2624
2625 * gencode.c (build_mips16_operands): Replace IPC with cia.
2626
2627 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2628 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2629 IPC to `cia'.
2630 (UndefinedResult): Replace function with macro/function
2631 combination.
2632 (sim_engine_run): Don't save PC in IPC.
2633
2634 * sim-main.h (IPC): Delete.
2635
2636
2637 * interp.c (signal_exception, store_word, load_word,
2638 address_translation, load_memory, store_memory, cache_op,
2639 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2640 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2641 current instruction address - cia - argument.
2642 (sim_read, sim_write): Call address_translation directly.
2643 (sim_engine_run): Rename variable vaddr to cia.
2644 (signal_exception): Pass cia to sim_monitor
72f4393d 2645
c906108c
SS		 2646 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2647 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2648 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2649
2650 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2651 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2652 SIM_ASSERT.
72f4393d 2653
c906108c
SS		 2654 * interp.c (signal_exception): Pass restart address to
2655 sim_engine_restart.
2656
2657 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2658 idecode.o): Add dependency.
2659
2660 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2661 Delete definitions
2662 (DELAY_SLOT): Update NIA not PC with branch address.
2663 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2664
2665 * mips.igen: Use CIA not PC in branch calculations.
2666 (illegal): Call SignalException.
2667 (BEQ, ADDIU): Fix assembler.
2668
2669Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2670
2671 * m16.igen (JALX): Was missing.
2672
2673 * configure.in (enable-sim-igen): New configuration option.
2674 * configure: Re-generate.
72f4393d 2675
c906108c
SS		 2676 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2677
2678 * interp.c (load_memory, store_memory): Delete parameter RAW.
2679 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2680 bypassing {load,store}_memory.
2681
2682 * sim-main.h (ByteSwapMem): Delete definition.
2683
2684 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2685
2686 * interp.c (sim_do_command, sim_commands): Delete mips specific
2687 commands. Handled by module sim-options.
72f4393d 2688
c906108c
SS		 2689 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2690 (WITH_MODULO_MEMORY): Define.
2691
2692 * interp.c (sim_info): Delete code printing memory size.
2693
2694 * interp.c (mips_size): Nee sim_size, delete function.
2695 (power2): Delete.
2696 (monitor, monitor_base, monitor_size): Delete global variables.
2697 (sim_open, sim_close): Delete code creating monitor and other
2698 memory regions. Use sim-memopts module, via sim_do_commandf, to
2699 manage memory regions.
2700 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2701
c906108c
SS		 2702 * interp.c (address_translation): Delete all memory map code
2703 except line forcing 32 bit addresses.
2704
2705Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2706
2707 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2708 trace options.
2709
2710 * interp.c (logfh, logfile): Delete globals.
2711 (sim_open, sim_close): Delete code opening & closing log file.
2712 (mips_option_handler): Delete -l and -n options.
2713 (OPTION mips_options): Ditto.
2714
2715 * interp.c (OPTION mips_options): Rename option trace to dinero.
2716 (mips_option_handler): Update.
2717
2718Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2719
2720 * interp.c (fetch_str): New function.
2721 (sim_monitor): Rewrite using sim_read & sim_write.
2722 (sim_open): Check magic number.
2723 (sim_open): Write monitor vectors into memory using sim_write.
2724 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2725 (sim_read, sim_write): Simplify - transfer data one byte at a
2726 time.
2727 (load_memory, store_memory): Clarify meaning of parameter RAW.
2728
2729 * sim-main.h (isHOST): Defete definition.
2730 (isTARGET): Mark as depreciated.
2731 (address_translation): Delete parameter HOST.
2732
2733 * interp.c (address_translation): Delete parameter HOST.
2734
2735Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2736
72f4393d 2737 * mips.igen:
c906108c
SS		 2738
2739 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2740 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2741
2742Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2743
2744 * mips.igen: Add model filter field to records.
2745
2746Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2747
2748 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2749
c906108c
SS		 2750 interp.c (sim_engine_run): Do not compile function sim_engine_run
2751 when WITH_IGEN == 1.
2752
2753 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2754 target architecture.
2755
2756 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2757 igen. Replace with configuration variables sim_igen_flags /
2758 sim_m16_flags.
2759
2760 * m16.igen: New file. Copy mips16 insns here.
2761 * mips.igen: From here.
2762
2763Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2764
2765 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2766 to top.
2767 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2768
2769Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2770
2771 * gencode.c (build_instruction): Follow sim_write's lead in using
2772 BigEndianMem instead of !ByteSwapMem.
2773
2774Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2775
2776 * configure.in (sim_gen): Dependent on target, select type of
2777 generator. Always select old style generator.
2778
2779 configure: Re-generate.
2780
2781 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2782 targets.
2783 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2784 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2785 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2786 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2787 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2788
c906108c
SS		 2789Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2790
2791 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2792
2793 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2794 CURRENT_FLOATING_POINT instead.
2795
2796 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2797 (address_translation): Raise exception InstructionFetch when
2798 translation fails and isINSTRUCTION.
72f4393d 2799
c906108c
SS		 2800 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2801 sim_engine_run): Change type of of vaddr and paddr to
2802 address_word.
2803 (address_translation, prefetch, load_memory, store_memory,
2804 cache_op): Change type of vAddr and pAddr to address_word.
2805
2806 * gencode.c (build_instruction): Change type of vaddr and paddr to
2807 address_word.
2808
2809Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2810
2811 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2812 macro to obtain result of ALU op.
2813
2814Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2815
2816 * interp.c (sim_info): Call profile_print.
2817
2818Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2819
2820 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2821
2822 * sim-main.h (WITH_PROFILE): Do not define, defined in
2823 common/sim-config.h. Use sim-profile module.
2824 (simPROFILE): Delete defintion.
2825
2826 * interp.c (PROFILE): Delete definition.
2827 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2828 (sim_close): Delete code writing profile histogram.
2829 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2830 Delete.
2831 (sim_engine_run): Delete code profiling the PC.
2832
2833Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2834
2835 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2836
2837 * interp.c (sim_monitor): Make register pointers of type
2838 unsigned_word*.
2839
2840 * sim-main.h: Make registers of type unsigned_word not
2841 signed_word.
2842
2843Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * interp.c (sync_operation): Rename from SyncOperation, make
2846 global, add SD argument.
2847 (prefetch): Rename from Prefetch, make global, add SD argument.
2848 (decode_coproc): Make global.
2849
2850 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2851
2852 * gencode.c (build_instruction): Generate DecodeCoproc not
2853 decode_coproc calls.
2854
2855 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2856 (SizeFGR): Move to sim-main.h
2857 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2858 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2859 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2860 sim-main.h.
2861 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2862 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2863 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2864 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2865 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2866 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2867
c906108c
SS		 2868 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2869 exception.
2870 (sim-alu.h): Include.
2871 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2872 (sim_cia): Typedef to instruction_address.
72f4393d 2873
c906108c
SS		 2874Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2875
2876 * Makefile.in (interp.o): Rename generated file engine.c to
2877 oengine.c.
72f4393d 2878
c906108c 2879 * interp.c: Update.
72f4393d 2880
c906108c
SS		 2881Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2882
2883 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2884
c906108c
SS		 2885Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2886
2887 * gencode.c (build_instruction): For "FPSQRT", output correct
2888 number of arguments to Recip.
72f4393d 2889
c906108c
SS		 2890Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2891
2892 * Makefile.in (interp.o): Depends on sim-main.h
2893
2894 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2895
2896 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2897 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2898 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2899 STATE, DSSTATE): Define
2900 (GPR, FGRIDX, ..): Define.
2901
2902 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2903 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2904 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2905
c906108c 2906 * interp.c: Update names to match defines from sim-main.h
72f4393d 2907
c906108c
SS		 2908Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2909
2910 * interp.c (sim_monitor): Add SD argument.
2911 (sim_warning): Delete. Replace calls with calls to
2912 sim_io_eprintf.
2913 (sim_error): Delete. Replace calls with sim_io_error.
2914 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2915 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2916 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2917 argument.
2918 (mips_size): Rename from sim_size. Add SD argument.
2919
2920 * interp.c (simulator): Delete global variable.
2921 (callback): Delete global variable.
2922 (mips_option_handler, sim_open, sim_write, sim_read,
2923 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2924 sim_size,sim_monitor): Use sim_io_* not callback->*.
2925 (sim_open): ZALLOC simulator struct.
2926 (PROFILE): Do not define.
2927
2928Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2929
2930 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2931 support.h with corresponding code.
2932
2933 * sim-main.h (word64, uword64), support.h: Move definition to
2934 sim-main.h.
2935 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2936
2937 * support.h: Delete
2938 * Makefile.in: Update dependencies
2939 * interp.c: Do not include.
72f4393d 2940
c906108c
SS		 2941Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2942
2943 * interp.c (address_translation, load_memory, store_memory,
2944 cache_op): Rename to from AddressTranslation et.al., make global,
2945 add SD argument
72f4393d 2946
c906108c
SS		 2947 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2948 CacheOp): Define.
72f4393d 2949
c906108c
SS		 2950 * interp.c (SignalException): Rename to signal_exception, make
2951 global.
2952
2953 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2954
c906108c
SS		 2955 * sim-main.h (SignalException, SignalExceptionInterrupt,
2956 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2957 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2958 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2959 Define.
72f4393d 2960
c906108c 2961 * interp.c, support.h: Use.
72f4393d 2962
c906108c
SS		 2963Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2964
2965 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2966 to value_fpr / store_fpr. Add SD argument.
2967 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2968 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2969
2970 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2971
c906108c
SS		 2972Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2973
2974 * interp.c (sim_engine_run): Check consistency between configure
2975 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2976 and HASFPU.
2977
2978 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2979 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2980 (mips_endian): Configure WITH_TARGET_ENDIAN.
2981 * configure: Update.
2982
2983Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2984
2985 * configure: Regenerated to track ../common/aclocal.m4 changes.
2986
2987Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2988
2989 * configure: Regenerated.
2990
2991Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2992
2993 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2994
2995Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2996
2997 * gencode.c (print_igen_insn_models): Assume certain architectures
2998 include all mips* instructions.
2999 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3000 instruction.
3001
3002 * Makefile.in (tmp.igen): Add target. Generate igen input from
3003 gencode file.
3004
3005 * gencode.c (FEATURE_IGEN): Define.
3006 (main): Add --igen option. Generate output in igen format.
3007 (process_instructions): Format output according to igen option.
3008 (print_igen_insn_format): New function.
3009 (print_igen_insn_models): New function.
3010 (process_instructions): Only issue warnings and ignore
3011 instructions when no FEATURE_IGEN.
3012
3013Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3014
3015 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3016 MIPS targets.
3017
3018Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3019
3020 * configure: Regenerated to track ../common/aclocal.m4 changes.
3021
3022Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3023
3024 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3025 SIM_RESERVED_BITS): Delete, moved to common.
3026 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3027
c906108c
SS		 3028Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3029
3030 * configure.in: Configure non-strict memory alignment.
3031 * configure: Regenerated to track ../common/aclocal.m4 changes.
3032
3033Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3034
3035 * configure: Regenerated to track ../common/aclocal.m4 changes.
3036
3037Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3038
3039 * gencode.c (SDBBP,DERET): Added (3900) insns.
3040 (RFE): Turn on for 3900.
3041 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3042 (dsstate): Made global.
3043 (SUBTARGET_R3900): Added.
3044 (CANCELDELAYSLOT): New.
3045 (SignalException): Ignore SystemCall rather than ignore and
3046 terminate. Add DebugBreakPoint handling.
3047 (decode_coproc): New insns RFE, DERET; and new registers Debug
3048 and DEPC protected by SUBTARGET_R3900.
3049 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3050 bits explicitly.
3051 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3052 * configure: Update.
c906108c
SS		 3053
3054Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3055
3056 * gencode.c: Add r3900 (tx39).
72f4393d 3057
c906108c
SS		 3058
3059Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3060
3061 * gencode.c (build_instruction): Don't need to subtract 4 for
3062 JALR, just 2.
3063
3064Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3065
3066 * interp.c: Correct some HASFPU problems.
3067
3068Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3069
3070 * configure: Regenerated to track ../common/aclocal.m4 changes.
3071
3072Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3073
3074 * interp.c (mips_options): Fix samples option short form, should
3075 be `x'.
3076
3077Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3078
3079 * interp.c (sim_info): Enable info code. Was just returning.
3080
3081Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3082
3083 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3084 MFC0.
3085
3086Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3087
3088 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3089 constants.
3090 (build_instruction): Ditto for LL.
3091
3092Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3093
3094 * configure: Regenerated to track ../common/aclocal.m4 changes.
3095
3096Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3097
3098 * configure: Regenerated to track ../common/aclocal.m4 changes.
3099 * config.in: Ditto.
3100
3101Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3102
3103 * interp.c (sim_open): Add call to sim_analyze_program, update
3104 call to sim_config.
3105
3106Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * interp.c (sim_kill): Delete.
3109 (sim_create_inferior): Add ABFD argument. Set PC from same.
3110 (sim_load): Move code initializing trap handlers from here.
3111 (sim_open): To here.
3112 (sim_load): Delete, use sim-hload.c.
3113
3114 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3115
3116Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3117
3118 * configure: Regenerated to track ../common/aclocal.m4 changes.
3119 * config.in: Ditto.
3120
3121Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3122
3123 * interp.c (sim_open): Add ABFD argument.
3124 (sim_load): Move call to sim_config from here.
3125 (sim_open): To here. Check return status.
3126
3127Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3128
c906108c
SS		 3129 * gencode.c (build_instruction): Two arg MADD should
3130 not assign result to $0.
72f4393d 3131
c906108c
SS		 3132Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3133
3134 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3135 * sim/mips/configure.in: Regenerate.
3136
3137Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3138
3139 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3140 signed8, unsigned8 et.al. types.
3141
3142 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3143 hosts when selecting subreg.
3144
3145Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3146
3147 * interp.c (sim_engine_run): Reset the ZERO register to zero
3148 regardless of FEATURE_WARN_ZERO.
3149 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3150
3151Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3152
3153 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3154 (SignalException): For BreakPoints ignore any mode bits and just
3155 save the PC.
3156 (SignalException): Always set the CAUSE register.
3157
3158Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3159
3160 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3161 exception has been taken.
3162
3163 * interp.c: Implement the ERET and mt/f sr instructions.
3164
3165Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3166
3167 * interp.c (SignalException): Don't bother restarting an
3168 interrupt.
3169
3170Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3171
3172 * interp.c (SignalException): Really take an interrupt.
3173 (interrupt_event): Only deliver interrupts when enabled.
3174
3175Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3176
3177 * interp.c (sim_info): Only print info when verbose.
3178 (sim_info) Use sim_io_printf for output.
72f4393d 3179
c906108c
SS		 3180Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3181
3182 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3183 mips architectures.
3184
3185Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3186
3187 * interp.c (sim_do_command): Check for common commands if a
3188 simulator specific command fails.
3189
3190Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3191
3192 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3193 and simBE when DEBUG is defined.
3194
3195Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3196
3197 * interp.c (interrupt_event): New function. Pass exception event
3198 onto exception handler.
3199
3200 * configure.in: Check for stdlib.h.
3201 * configure: Regenerate.
3202
3203 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3204 variable declaration.
3205 (build_instruction): Initialize memval1.
3206 (build_instruction): Add UNUSED attribute to byte, bigend,
3207 reverse.
3208 (build_operands): Ditto.
3209
3210 * interp.c: Fix GCC warnings.
3211 (sim_get_quit_code): Delete.
3212
3213 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3214 * Makefile.in: Ditto.
3215 * configure: Re-generate.
72f4393d 3216
c906108c
SS		 3217 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3218
3219Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3220
3221 * interp.c (mips_option_handler): New function parse argumes using
3222 sim-options.
3223 (myname): Replace with STATE_MY_NAME.
3224 (sim_open): Delete check for host endianness - performed by
3225 sim_config.
3226 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3227 (sim_open): Move much of the initialization from here.
3228 (sim_load): To here. After the image has been loaded and
3229 endianness set.
3230 (sim_open): Move ColdReset from here.
3231 (sim_create_inferior): To here.
3232 (sim_open): Make FP check less dependant on host endianness.
3233
3234 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3235 run.
3236 * interp.c (sim_set_callbacks): Delete.
3237
3238 * interp.c (membank, membank_base, membank_size): Replace with
3239 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3240 (sim_open): Remove call to callback->init. gdb/run do this.
3241
3242 * interp.c: Update
3243
3244 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3245
3246 * interp.c (big_endian_p): Delete, replaced by
3247 current_target_byte_order.
3248
3249Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3250
3251 * interp.c (host_read_long, host_read_word, host_swap_word,
3252 host_swap_long): Delete. Using common sim-endian.
3253 (sim_fetch_register, sim_store_register): Use H2T.
3254 (pipeline_ticks): Delete. Handled by sim-events.
3255 (sim_info): Update.
3256 (sim_engine_run): Update.
3257
3258Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3259
3260 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3261 reason from here.
3262 (SignalException): To here. Signal using sim_engine_halt.
3263 (sim_stop_reason): Delete, moved to common.
72f4393d 3264
c906108c
SS		 3265Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3266
3267 * interp.c (sim_open): Add callback argument.
3268 (sim_set_callbacks): Delete SIM_DESC argument.
3269 (sim_size): Ditto.
3270
3271Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3272
3273 * Makefile.in (SIM_OBJS): Add common modules.
3274
3275 * interp.c (sim_set_callbacks): Also set SD callback.
3276 (set_endianness, xfer_*, swap_*): Delete.
3277 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3278 Change to functions using sim-endian macros.
3279 (control_c, sim_stop): Delete, use common version.
3280 (simulate): Convert into.
3281 (sim_engine_run): This function.
3282 (sim_resume): Delete.
72f4393d 3283
c906108c
SS		 3284 * interp.c (simulation): New variable - the simulator object.
3285 (sim_kind): Delete global - merged into simulation.
3286 (sim_load): Cleanup. Move PC assignment from here.
3287 (sim_create_inferior): To here.
3288
3289 * sim-main.h: New file.
3290 * interp.c (sim-main.h): Include.
72f4393d 3291
c906108c
SS		 3292Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3293
3294 * configure: Regenerated to track ../common/aclocal.m4 changes.
3295
3296Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3297
3298 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3299
3300Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3301
72f4393d
L		 3302 * gencode.c (build_instruction): DIV instructions: check
3303 for division by zero and integer overflow before using
c906108c
SS		 3304 host's division operation.
3305
3306Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3307
3308 * Makefile.in (SIM_OBJS): Add sim-load.o.
3309 * interp.c: #include bfd.h.
3310 (target_byte_order): Delete.
3311 (sim_kind, myname, big_endian_p): New static locals.
3312 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3313 after argument parsing. Recognize -E arg, set endianness accordingly.
3314 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3315 load file into simulator. Set PC from bfd.
3316 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3317 (set_endianness): Use big_endian_p instead of target_byte_order.
3318
3319Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3320
3321 * interp.c (sim_size): Delete prototype - conflicts with
3322 definition in remote-sim.h. Correct definition.
3323
3324Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3325
3326 * configure: Regenerated to track ../common/aclocal.m4 changes.
3327 * config.in: Ditto.
3328
3329Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3330
3331 * interp.c (sim_open): New arg `kind'.
3332
3333 * configure: Regenerated to track ../common/aclocal.m4 changes.
3334
3335Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3336
3337 * configure: Regenerated to track ../common/aclocal.m4 changes.
3338
3339Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3340
3341 * interp.c (sim_open): Set optind to 0 before calling getopt.
3342
3343Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3344
3345 * configure: Regenerated to track ../common/aclocal.m4 changes.
3346
3347Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3348
3349 * interp.c : Replace uses of pr_addr with pr_uword64
3350 where the bit length is always 64 independent of SIM_ADDR.
3351 (pr_uword64) : added.
3352
3353Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3354
3355 * configure: Re-generate.
3356
3357Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3358
3359 * configure: Regenerate to track ../common/aclocal.m4 changes.
3360
3361Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3362
3363 * interp.c (sim_open): New SIM_DESC result. Argument is now
3364 in argv form.
3365 (other sim_*): New SIM_DESC argument.
3366
3367Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3368
3369 * interp.c: Fix printing of addresses for non-64-bit targets.
3370 (pr_addr): Add function to print address based on size.
3371
3372Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3373
3374 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3375
3376Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3377
3378 * gencode.c (build_mips16_operands): Correct computation of base
3379 address for extended PC relative instruction.
3380
3381Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3382
3383 * interp.c (mips16_entry): Add support for floating point cases.
3384 (SignalException): Pass floating point cases to mips16_entry.
3385 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3386 registers.
3387 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3388 or fmt_word.
3389 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3390 and then set the state to fmt_uninterpreted.
3391 (COP_SW): Temporarily set the state to fmt_word while calling
3392 ValueFPR.
3393
3394Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3395
3396 * gencode.c (build_instruction): The high order may be set in the
3397 comparison flags at any ISA level, not just ISA 4.
3398
3399Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3400
3401 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3402 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3403 * configure.in: sinclude ../common/aclocal.m4.
3404 * configure: Regenerated.
3405
3406Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3407
3408 * configure: Rebuild after change to aclocal.m4.
3409
3410Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3411
3412 * configure configure.in Makefile.in: Update to new configure
3413 scheme which is more compatible with WinGDB builds.
3414 * configure.in: Improve comment on how to run autoconf.
3415 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3416 * Makefile.in: Use autoconf substitution to install common
3417 makefile fragment.
3418
3419Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3420
3421 * gencode.c (build_instruction): Use BigEndianCPU instead of
3422 ByteSwapMem.
3423
3424Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3425
3426 * interp.c (sim_monitor): Make output to stdout visible in
3427 wingdb's I/O log window.
3428
3429Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3430
3431 * support.h: Undo previous change to SIGTRAP
3432 and SIGQUIT values.
3433
3434Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3435
3436 * interp.c (store_word, load_word): New static functions.
3437 (mips16_entry): New static function.
3438 (SignalException): Look for mips16 entry and exit instructions.
3439 (simulate): Use the correct index when setting fpr_state after
3440 doing a pending move.
3441
3442Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3443
3444 * interp.c: Fix byte-swapping code throughout to work on
3445 both little- and big-endian hosts.
3446
3447Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3448
3449 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3450 with gdb/config/i386/xm-windows.h.
3451
3452Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3453
3454 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3455 that messes up arithmetic shifts.
3456
3457Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3458
3459 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3460 SIGTRAP and SIGQUIT for _WIN32.
3461
3462Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3463
3464 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3465 force a 64 bit multiplication.
3466 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3467 destination register is 0, since that is the default mips16 nop
3468 instruction.
3469
3470Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3471
3472 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3473 (build_endian_shift): Don't check proc64.
3474 (build_instruction): Always set memval to uword64. Cast op2 to
3475 uword64 when shifting it left in memory instructions. Always use
3476 the same code for stores--don't special case proc64.
3477
3478 * gencode.c (build_mips16_operands): Fix base PC value for PC
3479 relative operands.
3480 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3481 jal instruction.
3482 * interp.c (simJALDELAYSLOT): Define.
3483 (JALDELAYSLOT): Define.
3484 (INDELAYSLOT, INJALDELAYSLOT): Define.
3485 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3486
3487Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3488
3489 * interp.c (sim_open): add flush_cache as a PMON routine
3490 (sim_monitor): handle flush_cache by ignoring it
3491
3492Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3493
3494 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3495 BigEndianMem.
3496 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3497 (BigEndianMem): Rename to ByteSwapMem and change sense.
3498 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3499 BigEndianMem references to !ByteSwapMem.
3500 (set_endianness): New function, with prototype.
3501 (sim_open): Call set_endianness.
3502 (sim_info): Use simBE instead of BigEndianMem.
3503 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3504 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3505 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3506 ifdefs, keeping the prototype declaration.
3507 (swap_word): Rewrite correctly.
3508 (ColdReset): Delete references to CONFIG. Delete endianness related
3509 code; moved to set_endianness.
72f4393d 3510
c906108c
SS		 3511Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3512
3513 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3514 * interp.c (CHECKHILO): Define away.
3515 (simSIGINT): New macro.
3516 (membank_size): Increase from 1MB to 2MB.
3517 (control_c): New function.
3518 (sim_resume): Rename parameter signal to signal_number. Add local
3519 variable prev. Call signal before and after simulate.
3520 (sim_stop_reason): Add simSIGINT support.
3521 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3522 functions always.
3523 (sim_warning): Delete call to SignalException. Do call printf_filtered
3524 if logfh is NULL.
3525 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3526 a call to sim_warning.
3527
3528Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3529
3530 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3531 16 bit instructions.
3532
3533Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3534
3535 Add support for mips16 (16 bit MIPS implementation):
3536 * gencode.c (inst_type): Add mips16 instruction encoding types.
3537 (GETDATASIZEINSN): Define.
3538 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3539 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3540 mtlo.
3541 (MIPS16_DECODE): New table, for mips16 instructions.
3542 (bitmap_val): New static function.
3543 (struct mips16_op): Define.
3544 (mips16_op_table): New table, for mips16 operands.
3545 (build_mips16_operands): New static function.
3546 (process_instructions): If PC is odd, decode a mips16
3547 instruction. Break out instruction handling into new
3548 build_instruction function.
3549 (build_instruction): New static function, broken out of
3550 process_instructions. Check modifiers rather than flags for SHIFT
3551 bit count and m[ft]{hi,lo} direction.
3552 (usage): Pass program name to fprintf.
3553 (main): Remove unused variable this_option_optind. Change
3554 ``*loptarg++'' to ``loptarg++''.
3555 (my_strtoul): Parenthesize && within ||.
3556 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3557 (simulate): If PC is odd, fetch a 16 bit instruction, and
3558 increment PC by 2 rather than 4.
3559 * configure.in: Add case for mips16*-*-*.
3560 * configure: Rebuild.
3561
3562Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3563
3564 * interp.c: Allow -t to enable tracing in standalone simulator.
3565 Fix garbage output in trace file and error messages.
3566
3567Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3568
3569 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3570 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3571 * configure.in: Simplify using macros in ../common/aclocal.m4.
3572 * configure: Regenerated.
3573 * tconfig.in: New file.
3574
3575Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3576
3577 * interp.c: Fix bugs in 64-bit port.
3578 Use ansi function declarations for msvc compiler.
3579 Initialize and test file pointer in trace code.
3580 Prevent duplicate definition of LAST_EMED_REGNUM.
3581
3582Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3583
3584 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3585
3586Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3587
3588 * interp.c (SignalException): Check for explicit terminating
3589 breakpoint value.
3590 * gencode.c: Pass instruction value through SignalException()
3591 calls for Trap, Breakpoint and Syscall.
3592
3593Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3594
3595 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3596 only used on those hosts that provide it.
3597 * configure.in: Add sqrt() to list of functions to be checked for.
3598 * config.in: Re-generated.
3599 * configure: Re-generated.
3600
3601Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3602
3603 * gencode.c (process_instructions): Call build_endian_shift when
3604 expanding STORE RIGHT, to fix swr.
3605 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3606 clear the high bits.
3607 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3608 Fix float to int conversions to produce signed values.
3609
3610Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3611
3612 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3613 (process_instructions): Correct handling of nor instruction.
3614 Correct shift count for 32 bit shift instructions. Correct sign
3615 extension for arithmetic shifts to not shift the number of bits in
3616 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3617 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3618 Fix madd.
3619 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3620 It's OK to have a mult follow a mult. What's not OK is to have a
3621 mult follow an mfhi.
3622 (Convert): Comment out incorrect rounding code.
3623
3624Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3625
3626 * interp.c (sim_monitor): Improved monitor printf
3627 simulation. Tidied up simulator warnings, and added "--log" option
3628 for directing warning message output.
3629 * gencode.c: Use sim_warning() rather than WARNING macro.
3630
3631Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3632
3633 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3634 getopt1.o, rather than on gencode.c. Link objects together.
3635 Don't link against -liberty.
3636 (gencode.o, getopt.o, getopt1.o): New targets.
3637 * gencode.c: Include <ctype.h> and "ansidecl.h".
3638 (AND): Undefine after including "ansidecl.h".
3639 (ULONG_MAX): Define if not defined.
3640 (OP_*): Don't define macros; now defined in opcode/mips.h.
3641 (main): Call my_strtoul rather than strtoul.
3642 (my_strtoul): New static function.
3643
3644Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3645
3646 * gencode.c (process_instructions): Generate word64 and uword64
3647 instead of `long long' and `unsigned long long' data types.
3648 * interp.c: #include sysdep.h to get signals, and define default
3649 for SIGBUS.
3650 * (Convert): Work around for Visual-C++ compiler bug with type
3651 conversion.
3652 * support.h: Make things compile under Visual-C++ by using
3653 __int64 instead of `long long'. Change many refs to long long
3654 into word64/uword64 typedefs.
3655
3656Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3657
72f4393d
L		 3658 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3659 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3660 (docdir): Removed.
3661 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3662 (AC_PROG_INSTALL): Added.
c906108c 3663 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3664 * configure: Rebuilt.
3665
c906108c
SS		 3666Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3667
3668 * configure.in: Define @SIMCONF@ depending on mips target.
3669 * configure: Rebuild.
3670 * Makefile.in (run): Add @SIMCONF@ to control simulator
3671 construction.
3672 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3673 * interp.c: Remove some debugging, provide more detailed error
3674 messages, update memory accesses to use LOADDRMASK.
72f4393d 3675
c906108c
SS		 3676Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3677
3678 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3679 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3680 stamp-h.
3681 * configure: Rebuild.
3682 * config.in: New file, generated by autoheader.
3683 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3684 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3685 HAVE_ANINT and HAVE_AINT, as appropriate.
3686 * Makefile.in (run): Use @LIBS@ rather than -lm.
3687 (interp.o): Depend upon config.h.
3688 (Makefile): Just rebuild Makefile.
3689 (clean): Remove stamp-h.
3690 (mostlyclean): Make the same as clean, not as distclean.
3691 (config.h, stamp-h): New targets.
3692
3693Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3694
3695 * interp.c (ColdReset): Fix boolean test. Make all simulator
3696 globals static.
3697
3698Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3699
3700 * interp.c (xfer_direct_word, xfer_direct_long,
3701 swap_direct_word, swap_direct_long, xfer_big_word,
3702 xfer_big_long, xfer_little_word, xfer_little_long,
3703 swap_word,swap_long): Added.
3704 * interp.c (ColdReset): Provide function indirection to
3705 host<->simulated_target transfer routines.
3706 * interp.c (sim_store_register, sim_fetch_register): Updated to
3707 make use of indirected transfer routines.
3708
3709Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3710
3711 * gencode.c (process_instructions): Ensure FP ABS instruction
3712 recognised.
3713 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3714 system call support.
3715
3716Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3717
3718 * interp.c (sim_do_command): Complain if callback structure not
3719 initialised.
3720
3721Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3722
3723 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3724 support for Sun hosts.
3725 * Makefile.in (gencode): Ensure the host compiler and libraries
3726 used for cross-hosted build.
3727
3728Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3729
3730 * interp.c, gencode.c: Some more (TODO) tidying.
3731
3732Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3733
3734 * gencode.c, interp.c: Replaced explicit long long references with
3735 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3736 * support.h (SET64LO, SET64HI): Macros added.
3737
3738Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3739
3740 * configure: Regenerate with autoconf 2.7.
3741
3742Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3743
3744 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3745 * support.h: Remove superfluous "1" from #if.
3746 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3747
3748Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3749
3750 * interp.c (StoreFPR): Control UndefinedResult() call on
3751 WARN_RESULT manifest.
3752
3753Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3754
3755 * gencode.c: Tidied instruction decoding, and added FP instruction
3756 support.
3757
3758 * interp.c: Added dineroIII, and BSD profiling support. Also
3759 run-time FP handling.
3760
3761Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3762
3763 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3764 gencode.c, interp.c, support.h: created.
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