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CommitLineData
f693213d
SM		 12020-07-29 Simon Marchi <simon.marchi@efficios.com>
2
3 * configure: Re-generate.
4
5c887dd5
JB		 52017-09-06 John Baldwin <jhb@FreeBSD.org>
6
7 * configure: Regenerate.
8
91588b3a
MF		 92016-11-11 Mike Frysinger <vapier@gentoo.org>
10
6cb2202b 11 PR sim/20808
91588b3a
MF		 12 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu
13 and SD to sd.
14
e04659e8
MF		 152016-11-11 Mike Frysinger <vapier@gentoo.org>
16
6cb2202b 17 PR sim/20809
e04659e8
MF		 18 * mips.igen (check_u64): Enable for `r3900'.
19
1554f758
MF		 202016-02-05 Mike Frysinger <vapier@gentoo.org>
21
22 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
23 STATE_PROG_BFD (sd).
24 * configure: Regenerate.
25
3d304f48
AB		 262016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
27 Maciej W. Rozycki <macro@imgtec.com>
28
29 PR sim/19441
30 * micromips.igen (delayslot_micromips): Enable for `micromips32',
31 `micromips64' and `micromipsdsp' only.
32 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
33 (do_micromips_jalr, do_micromips_jal): Likewise.
34 (compute_movep_src_reg): Likewise.
35 (compute_andi16_imm): Likewise.
36 (convert_fmt_micromips): Likewise.
37 (convert_fmt_micromips_cvt_d): Likewise.
38 (convert_fmt_micromips_cvt_s): Likewise.
39 (FMT_MICROMIPS): Likewise.
40 (FMT_MICROMIPS_CVT_D): Likewise.
41 (FMT_MICROMIPS_CVT_S): Likewise.
42
b36d953b
MF		 432016-01-12 Mike Frysinger <vapier@gentoo.org>
44
45 * interp.c: Include elf-bfd.h.
46 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
47 ELFCLASS32.
48
ce39bd38
MF		 492016-01-10 Mike Frysinger <vapier@gentoo.org>
50
51 * config.in, configure: Regenerate.
52
99d8e879
MF		 532016-01-10 Mike Frysinger <vapier@gentoo.org>
54
55 * configure: Regenerate.
56
35656e95
MF		 572016-01-10 Mike Frysinger <vapier@gentoo.org>
58
59 * configure: Regenerate.
60
16f7876d
MF		 612016-01-10 Mike Frysinger <vapier@gentoo.org>
62
63 * configure: Regenerate.
64
e19418e0
MF		 652016-01-10 Mike Frysinger <vapier@gentoo.org>
66
67 * configure: Regenerate.
68
6d90347b
MF		 692016-01-10 Mike Frysinger <vapier@gentoo.org>
70
71 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
72 * configure: Regenerate.
73
347fe5bb
MF		 742016-01-10 Mike Frysinger <vapier@gentoo.org>
75
76 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
77 * configure: Regenerate.
78
22be3fbe
MF		 792016-01-10 Mike Frysinger <vapier@gentoo.org>
80
81 * configure: Regenerate.
82
0dc73ef7
MF		 832016-01-10 Mike Frysinger <vapier@gentoo.org>
84
85 * configure: Regenerate.
86
936df756
MF		 872016-01-09 Mike Frysinger <vapier@gentoo.org>
88
89 * config.in, configure: Regenerate.
90
2e3d4f4d
MF		 912016-01-06 Mike Frysinger <vapier@gentoo.org>
92
93 * interp.c (sim_open): Mark argv const.
94 (sim_create_inferior): Mark argv and env const.
95
9bbf6f91
MF		 962016-01-04 Mike Frysinger <vapier@gentoo.org>
97
98 * configure: Regenerate.
99
77cf2ef5
MF		 1002016-01-03 Mike Frysinger <vapier@gentoo.org>
101
102 * interp.c (sim_open): Update sim_parse_args comment.
103
0cb8d851
MF		 1042016-01-03 Mike Frysinger <vapier@gentoo.org>
105
106 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
107 * configure: Regenerate.
108
1ac72f06
MF		 1092016-01-02 Mike Frysinger <vapier@gentoo.org>
110
111 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
112 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
113 * configure: Regenerate.
114 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
115
d47f5b30
MF		 1162016-01-02 Mike Frysinger <vapier@gentoo.org>
117
118 * dv-tx3904cpu.c (CPU, SD): Delete.
119
e1211e55
MF		 1202015-12-30 Mike Frysinger <vapier@gentoo.org>
121
122 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
123 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
124 (sim_store_register): Rename to ...
125 (mips_reg_store): ... this. Delete local cpu var.
126 Update sim_io_eprintf calls.
127 (sim_fetch_register): Rename to ...
128 (mips_reg_fetch): ... this. Delete local cpu var.
129 Update sim_io_eprintf calls.
130
5e744ef8
MF		 1312015-12-27 Mike Frysinger <vapier@gentoo.org>
132
133 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
134
1b393626
MF		 1352015-12-26 Mike Frysinger <vapier@gentoo.org>
136
137 * config.in, configure: Regenerate.
138
26f8bf63
MF		 1392015-12-26 Mike Frysinger <vapier@gentoo.org>
140
141 * interp.c (sim_write, sim_read): Delete.
142 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
143 (load_word): Likewise.
144 * micromips.igen (cache): Likewise.
145 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
146 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
147 do_store_left, do_store_right, do_load_double, do_store_double):
148 Likewise.
149 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
150 (do_prefx): Likewise.
151 * sim-main.c (address_translation, prefetch): Delete.
152 (ifetch32, ifetch16): Delete call to AddressTranslation and set
153 paddr=vaddr.
154 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
155 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
156 (LoadMemory, StoreMemory): Delete CCA arg.
157
ef04e371
MF		 1582015-12-24 Mike Frysinger <vapier@gentoo.org>
159
160 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
161 * configure: Regenerated.
162
cb379ede
MF		 1632015-12-24 Mike Frysinger <vapier@gentoo.org>
164
165 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
166 * tconfig.h: Delete.
167
26936211
MF		 1682015-12-24 Mike Frysinger <vapier@gentoo.org>
169
170 * tconfig.h (SIM_HANDLES_LMA): Delete.
171
84e8e361
MF		 1722015-12-24 Mike Frysinger <vapier@gentoo.org>
173
174 * sim-main.h (WITH_WATCHPOINTS): Delete.
175
3cabaf66
MF		 1762015-12-24 Mike Frysinger <vapier@gentoo.org>
177
178 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
179
8abe6c66
MF		 1802015-12-24 Mike Frysinger <vapier@gentoo.org>
181
182 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
183
1d19cae7
DV		 1842015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
185
186 * micromips.igen (process_isa_mode): Fix left shift of negative
187 value.
188
cdf850e9
MF		 1892015-11-17 Mike Frysinger <vapier@gentoo.org>
190
191 * sim-main.h (WITH_MODULO_MEMORY): Delete.
192
797eee42
MF		 1932015-11-15 Mike Frysinger <vapier@gentoo.org>
194
195 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
196
6e4f085c
MF		 1972015-11-14 Mike Frysinger <vapier@gentoo.org>
198
199 * interp.c (sim_close): Rename to ...
200 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
201 sim_io_shutdown.
202 * sim-main.h (mips_sim_close): Declare.
203 (SIM_CLOSE_HOOK): Define.
204
8e394ffc
AB		 2052015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
206 Ali Lown <ali.lown@imgtec.com>
207
208 * Makefile.in (tmp-micromips): New rule.
209 (tmp-mach-multi): Add support for micromips.
210 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
211 that works for both mips64 and micromips64.
212 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
213 micromips32.
214 Add build support for micromips.
215 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
216 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
217 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
218 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
219 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
220 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
221 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
222 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
223 Refactored instruction code to use these functions.
224 * dsp2.igen: Refactored instruction code to use the new functions.
225 * interp.c (decode_coproc): Refactored to work with any instruction
226 encoding.
227 (isa_mode): New variable
228 (RSVD_INSTRUCTION): Changed to 0x00000039.
229 * m16.igen (BREAK16): Refactored instruction to use do_break16.
230 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
231 * micromips.dc: New file.
232 * micromips.igen: New file.
233 * micromips16.dc: New file.
234 * micromipsdsp.igen: New file.
235 * micromipsrun.c: New file.
236 * mips.igen (do_swc1): Changed to work with any instruction encoding.
237 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
238 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
239 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
240 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
241 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
242 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
243 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
244 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
245 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
246 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
247 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
248 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
249 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
250 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
251 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
252 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
253 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
254 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
255 instructions.
256 Refactored instruction code to use these functions.
257 (RSVD): Changed to use new reserved instruction.
258 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
259 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
260 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
261 do_store_double): Added micromips32 and micromips64 models.
262 Added include for micromips.igen and micromipsdsp.igen
263 Add micromips32 and micromips64 models.
264 (DecodeCoproc): Updated to use new macro definition.
265 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
266 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
267 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
268 Refactored instruction code to use these functions.
269 * sim-main.h (CP0_operation): New enum.
270 (DecodeCoproc): Updated macro.
271 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
272 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
273 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
274 ISA_MODE_MICROMIPS): New defines.
275 (sim_state): Add isa_mode field.
276
8d0978fb
MF		 2772015-06-23 Mike Frysinger <vapier@gentoo.org>
278
279 * configure: Regenerate.
280
306f4178
MF		 2812015-06-12 Mike Frysinger <vapier@gentoo.org>
282
283 * configure.ac: Change configure.in to configure.ac.
284 * configure: Regenerate.
285
a3487082
MF		 2862015-06-12 Mike Frysinger <vapier@gentoo.org>
287
288 * configure: Regenerate.
289
29bc024d
MF		 2902015-06-12 Mike Frysinger <vapier@gentoo.org>
291
292 * interp.c [TRACE]: Delete.
293 (TRACE): Change to WITH_TRACE_ANY_P.
294 [!WITH_TRACE_ANY_P] (open_trace): Define.
295 (mips_option_handler, open_trace, sim_close, dotrace):
296 Change defined(TRACE) to WITH_TRACE_ANY_P.
297 (sim_open): Delete TRACE ifdef check.
298 * sim-main.c (load_memory): Delete TRACE ifdef check.
299 (store_memory): Likewise.
300 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
301 [!WITH_TRACE_ANY_P] (dotrace): Define.
302
3ebe2863
MF		 3032015-04-18 Mike Frysinger <vapier@gentoo.org>
304
305 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
306 comments.
307
20bca71d
MF		 3082015-04-18 Mike Frysinger <vapier@gentoo.org>
309
310 * sim-main.h (SIM_CPU): Delete.
311
7e83aa92
MF		 3122015-04-18 Mike Frysinger <vapier@gentoo.org>
313
314 * sim-main.h (sim_cia): Delete.
315
034685f9
MF		 3162015-04-17 Mike Frysinger <vapier@gentoo.org>
317
318 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
319 PU_PC_GET.
320 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
321 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
322 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
323 CIA_SET to CPU_PC_SET.
324 * sim-main.h (CIA_GET, CIA_SET): Delete.
325
78e9aa70
MF		 3262015-04-15 Mike Frysinger <vapier@gentoo.org>
327
328 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
329 * sim-main.h (STATE_CPU): Delete.
330
bf12d44e
MF		 3312015-04-13 Mike Frysinger <vapier@gentoo.org>
332
333 * configure: Regenerate.
334
7bebb329
MF		 3352015-04-13 Mike Frysinger <vapier@gentoo.org>
336
337 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
338 * interp.c (mips_pc_get, mips_pc_set): New functions.
339 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
340 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
341 (sim_pc_get): Delete.
342 * sim-main.h (SIM_CPU): Define.
343 (struct sim_state): Change cpu to an array of pointers.
344 (STATE_CPU): Drop &.
345
8ac57fbd
MF		 3462015-04-13 Mike Frysinger <vapier@gentoo.org>
347
348 * interp.c (mips_option_handler, open_trace, sim_close,
349 sim_write, sim_read, sim_store_register, sim_fetch_register,
350 sim_create_inferior, pr_addr, pr_uword64): Convert old style
351 prototypes.
352 (sim_open): Convert old style prototype. Change casts with
353 sim_write to unsigned char *.
354 (fetch_str): Change null to unsigned char, and change cast to
355 unsigned char *.
356 (sim_monitor): Change c & ch to unsigned char. Change cast to
357 unsigned char *.
358
e787f858
MF		 3592015-04-12 Mike Frysinger <vapier@gentoo.org>
360
361 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
362
122bbfb5
MF		 3632015-04-06 Mike Frysinger <vapier@gentoo.org>
364
365 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
366
0fe84f3f
MF		 3672015-04-01 Mike Frysinger <vapier@gentoo.org>
368
369 * tconfig.h (SIM_HAVE_PROFILE): Delete.
370
aadc9410
MF		 3712015-03-31 Mike Frysinger <vapier@gentoo.org>
372
373 * config.in, configure: Regenerate.
374
05f53ed6
MF		 3752015-03-24 Mike Frysinger <vapier@gentoo.org>
376
377 * interp.c (sim_pc_get): New function.
378
c0931f26
MF		 3792015-03-24 Mike Frysinger <vapier@gentoo.org>
380
381 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
382 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
383
30452bbe
MF		 3842015-03-24 Mike Frysinger <vapier@gentoo.org>
385
386 * configure: Regenerate.
387
64dd13df
MF		 3882015-03-23 Mike Frysinger <vapier@gentoo.org>
389
390 * configure: Regenerate.
391
49cd1634
MF		 3922015-03-23 Mike Frysinger <vapier@gentoo.org>
393
394 * configure: Regenerate.
395 * configure.ac (mips_extra_objs): Delete.
396 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
397 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
398
3649cb06
MF		 3992015-03-23 Mike Frysinger <vapier@gentoo.org>
400
401 * configure: Regenerate.
402 * configure.ac: Delete sim_hw checks for dv-sockser.
403
ae7d0cac
MF		 4042015-03-16 Mike Frysinger <vapier@gentoo.org>
405
406 * config.in, configure: Regenerate.
407 * tconfig.in: Rename file ...
408 * tconfig.h: ... here.
409
8406bb59
MF		 4102015-03-15 Mike Frysinger <vapier@gentoo.org>
411
412 * tconfig.in: Delete includes.
413 [HAVE_DV_SOCKSER]: Delete.
414
465fb143
MF		 4152015-03-14 Mike Frysinger <vapier@gentoo.org>
416
417 * Makefile.in (SIM_RUN_OBJS): Delete.
418
5cddc23a
MF		 4192015-03-14 Mike Frysinger <vapier@gentoo.org>
420
421 * configure.ac (AC_CHECK_HEADERS): Delete.
422 * aclocal.m4, configure: Regenerate.
423
2974be62
AM		 4242014-08-19 Alan Modra <amodra@gmail.com>
425
426 * configure: Regenerate.
427
faa743bb
RM		 4282014-08-15 Roland McGrath <mcgrathr@google.com>
429
430 * configure: Regenerate.
431 * config.in: Regenerate.
432
1a8a700e
MF		 4332014-03-04 Mike Frysinger <vapier@gentoo.org>
434
435 * configure: Regenerate.
436
bf3d9781
AM		 4372013-09-23 Alan Modra <amodra@gmail.com>
438
439 * configure: Regenerate.
440
31e6ad7d
MF		 4412013-06-03 Mike Frysinger <vapier@gentoo.org>
442
443 * aclocal.m4, configure: Regenerate.
444
d3685d60
TT		 4452013-05-10 Freddie Chopin <freddie_chopin@op.pl>
446
447 * configure: Rebuild.
448
1517bd27
MF		 4492013-03-26 Mike Frysinger <vapier@gentoo.org>
450
451 * configure: Regenerate.
452
3be31516
JS		 4532013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
454
455 * configure.ac: Address use of dv-sockser.o.
456 * tconfig.in: Conditionalize use of dv_sockser_install.
457 * configure: Regenerated.
458 * config.in: Regenerated.
459
37cb8f8e
SE		 4602012-10-04 Chao-ying Fu <fu@mips.com>
461 Steve Ellcey <sellcey@mips.com>
462
463 * mips/mips3264r2.igen (rdhwr): New.
464
87c8644f
JS		 4652012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
466
467 * configure.ac: Always link against dv-sockser.o.
468 * configure: Regenerate.
469
5f3ef9d0
JB		 4702012-06-15 Joel Brobecker <brobecker@adacore.com>
471
472 * config.in, configure: Regenerate.
473
a6ff997c
NC		 4742012-05-18 Nick Clifton <nickc@redhat.com>
475
476 PR 14072
477 * interp.c: Include config.h before system header files.
478
2232061b
MF		 4792012-03-24 Mike Frysinger <vapier@gentoo.org>
480
481 * aclocal.m4, config.in, configure: Regenerate.
482
db2e4d67
MF		 4832011-12-03 Mike Frysinger <vapier@gentoo.org>
484
485 * aclocal.m4: New file.
486 * configure: Regenerate.
487
4399a56b
MF		 4882011-10-19 Mike Frysinger <vapier@gentoo.org>
489
490 * configure: Regenerate after common/acinclude.m4 update.
491
9c082ca8
MF		 4922011-10-17 Mike Frysinger <vapier@gentoo.org>
493
494 * configure.ac: Change include to common/acinclude.m4.
495
6ffe910a
MF		 4962011-10-17 Mike Frysinger <vapier@gentoo.org>
497
498 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
499 call. Replace common.m4 include with SIM_AC_COMMON.
500 * configure: Regenerate.
501
31b28250
HPN		 5022011-07-08 Hans-Peter Nilsson <hp@axis.com>
503
3faa01e3
HPN		 504 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
505 $(SIM_EXTRA_DEPS).
506 (tmp-mach-multi): Exit early when igen fails.
31b28250 507
2419798b
MF		 5082011-07-05 Mike Frysinger <vapier@gentoo.org>
509
510 * interp.c (sim_do_command): Delete.
511
d79fe0d6
MF		 5122011-02-14 Mike Frysinger <vapier@gentoo.org>
513
514 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
515 (tx3904sio_fifo_reset): Likewise.
516 * interp.c (sim_monitor): Likewise.
517
5558e7e6
MF		 5182010-04-14 Mike Frysinger <vapier@gentoo.org>
519
520 * interp.c (sim_write): Add const to buffer arg.
521
35aafff4
JB		 5222010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
523
524 * interp.c: Don't include sysdep.h
525
3725885a
RW		 5262010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
527
528 * configure: Regenerate.
529
d6416cdc
RW		 5302009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
531
81ecdfbb
RW		 532 * config.in: Regenerate.
533 * configure: Likewise.
534
d6416cdc
RW		 535 * configure: Regenerate.
536
b5bd9624
HPN		 5372008-07-11 Hans-Peter Nilsson <hp@axis.com>
538
539 * configure: Regenerate to track ../common/common.m4 changes.
540 * config.in: Ditto.
541
6efef468 5422008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 543 Daniel Jacobowitz <dan@codesourcery.com>
544 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 545
546 * configure: Regenerate.
547
60dc88db
RS		 5482007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
549
550 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
551 that unconditionally allows fmt_ps.
552 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
553 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
554 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
555 filter from 64,f to 32,f.
556 (PREFX): Change filter from 64 to 32.
557 (LDXC1, LUXC1): Provide separate mips32r2 implementations
558 that use do_load_double instead of do_load. Make both LUXC1
559 versions unpredictable if SizeFGR () != 64.
560 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
561 instead of do_store. Remove unused variable. Make both SUXC1
562 versions unpredictable if SizeFGR () != 64.
563
599ca73e
RS		 5642007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
565
566 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
567 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
568 shifts for that case.
569
2525df03
NC		 5702007-09-04 Nick Clifton <nickc@redhat.com>
571
572 * interp.c (options enum): Add OPTION_INFO_MEMORY.
573 (display_mem_info): New static variable.
574 (mips_option_handler): Handle OPTION_INFO_MEMORY.
575 (mips_options): Add info-memory and memory-info.
576 (sim_open): After processing the command line and board
577 specification, check display_mem_info. If it is set then
578 call the real handler for the --memory-info command line
579 switch.
580
35ee6e1e
JB		 5812007-08-24 Joel Brobecker <brobecker@adacore.com>
582
583 * configure.ac: Change license of multi-run.c to GPL version 3.
584 * configure: Regenerate.
585
d5fb0879
RS		 5862007-06-28 Richard Sandiford <richard@codesourcery.com>
587
588 * configure.ac, configure: Revert last patch.
589
2a2ce21b
RS		 5902007-06-26 Richard Sandiford <richard@codesourcery.com>
591
592 * configure.ac (sim_mipsisa3264_configs): New variable.
593 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
594 every configuration support all four targets, using the triplet to
595 determine the default.
596 * configure: Regenerate.
597
efdcccc9
RS		 5982007-06-25 Richard Sandiford <richard@codesourcery.com>
599
0a7692b2 600 * Makefile.in (m16run.o): New rule.
efdcccc9 601
f532a356
TS		 6022007-05-15 Thiemo Seufer <ths@mips.com>
603
604 * mips3264r2.igen (DSHD): Fix compile warning.
605
bfe9c90b
TS		 6062007-05-14 Thiemo Seufer <ths@mips.com>
607
608 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
609 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
610 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
611 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
612 for mips32r2.
613
53f4826b
TS		 6142007-03-01 Thiemo Seufer <ths@mips.com>
615
616 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
617 and mips64.
618
8bf3ddc8
TS		 6192007-02-20 Thiemo Seufer <ths@mips.com>
620
621 * dsp.igen: Update copyright notice.
622 * dsp2.igen: Fix copyright notice.
623
8b082fb1 6242007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 625 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 626
627 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
628 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
629 Add dsp2 to sim_igen_machine.
630 * configure: Regenerate.
631 * dsp.igen (do_ph_op): Add MUL support when op = 2.
632 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
633 (mulq_rs.ph): Use do_ph_mulq.
634 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
635 * mips.igen: Add dsp2 model and include dsp2.igen.
636 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
637 for *mips32r2, *mips64r2, *dsp.
638 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
639 for *mips32r2, *mips64r2, *dsp2.
640 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
641
b1004875 6422007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 643 Nigel Stephens <nigel@mips.com>
b1004875
TS		 644
645 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
646 jumps with hazard barrier.
647
f8df4c77 6482007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 649 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 650
651 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
652 after each call to sim_io_write.
653
b1004875 6542007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 655 Nigel Stephens <nigel@mips.com>
b1004875
TS		 656
657 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
658 supported by this simulator.
07802d98
TS		 659 (decode_coproc): Recognise additional CP0 Config registers
660 correctly.
661
14fb6c5a 6622007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 663 Nigel Stephens <nigel@mips.com>
664 David Ung <davidu@mips.com>
14fb6c5a
TS		 665
666 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
667 uninterpreted formats. If fmt is one of the uninterpreted types
668 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
669 fmt_word, and fmt_uninterpreted_64 like fmt_long.
670 (store_fpr): When writing an invalid odd register, set the
671 matching even register to fmt_unknown, not the following register.
672 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
673 the the memory window at offset 0 set by --memory-size command
674 line option.
675 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
676 point register.
677 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
678 register.
679 (sim_monitor): When returning the memory size to the MIPS
680 application, use the value in STATE_MEM_SIZE, not an arbitrary
681 hardcoded value.
682 (cop_lw): Don' mess around with FPR_STATE, just pass
683 fmt_uninterpreted_32 to StoreFPR.
684 (cop_sw): Similarly.
685 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
686 (cop_sd): Similarly.
687 * mips.igen (not_word_value): Single version for mips32, mips64
688 and mips16.
689
c8847145 6902007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 691 Nigel Stephens <nigel@mips.com>
c8847145
TS		 692
693 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
694 MBytes.
695
4b5d35ee
TS		 6962007-02-17 Thiemo Seufer <ths@mips.com>
697
698 * configure.ac (mips*-sde-elf*): Move in front of generic machine
699 configuration.
700 * configure: Regenerate.
701
3669427c
TS		 7022007-02-17 Thiemo Seufer <ths@mips.com>
703
704 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
705 Add mdmx to sim_igen_machine.
706 (mipsisa64*-*-*): Likewise. Remove dsp.
707 (mipsisa32*-*-*): Remove dsp.
708 * configure: Regenerate.
709
109ad085
TS		 7102007-02-13 Thiemo Seufer <ths@mips.com>
711
712 * configure.ac: Add mips*-sde-elf* target.
713 * configure: Regenerate.
714
921d7ad3
HPN		 7152006-12-21 Hans-Peter Nilsson <hp@axis.com>
716
717 * acconfig.h: Remove.
718 * config.in, configure: Regenerate.
719
02f97da7
TS		 7202006-11-07 Thiemo Seufer <ths@mips.com>
721
722 * dsp.igen (do_w_op): Fix compiler warning.
723
2d2733fc 7242006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 725 David Ung <davidu@mips.com>
2d2733fc
TS		 726
727 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
728 sim_igen_machine.
729 * configure: Regenerate.
730 * mips.igen (model): Add smartmips.
731 (MADDU): Increment ACX if carry.
732 (do_mult): Clear ACX.
733 (ROR,RORV): Add smartmips.
72f4393d 734 (include): Include smartmips.igen.
2d2733fc
TS		 735 * sim-main.h (ACX): Set to REGISTERS[89].
736 * smartmips.igen: New file.
737
d85c3a10 7382006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 739 David Ung <davidu@mips.com>
d85c3a10
TS		 740
741 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
742 mips3264r2.igen. Add missing dependency rules.
743 * m16e.igen: Support for mips16e save/restore instructions.
744
e85e3205
RE		 7452006-06-13 Richard Earnshaw <rearnsha@arm.com>
746
747 * configure: Regenerated.
748
2f0122dc
DJ		 7492006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
750
751 * configure: Regenerated.
752
20e95c23
DJ		 7532006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
754
755 * configure: Regenerated.
756
69088b17
CF		 7572006-05-15 Chao-ying Fu <fu@mips.com>
758
759 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
760
0275de4e
NC		 7612006-04-18 Nick Clifton <nickc@redhat.com>
762
763 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
764 statement.
765
b3a3ffef
HPN		 7662006-03-29 Hans-Peter Nilsson <hp@axis.com>
767
768 * configure: Regenerate.
769
40a5538e
CF		 7702005-12-14 Chao-ying Fu <fu@mips.com>
771
772 * Makefile.in (SIM_OBJS): Add dsp.o.
773 (dsp.o): New dependency.
774 (IGEN_INCLUDE): Add dsp.igen.
775 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
776 mipsisa64*-*-*): Add dsp to sim_igen_machine.
777 * configure: Regenerate.
778 * mips.igen: Add dsp model and include dsp.igen.
779 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
780 because these instructions are extended in DSP ASE.
781 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
782 adding 6 DSP accumulator registers and 1 DSP control register.
783 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
784 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
785 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
786 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
787 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
788 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
789 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
790 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
791 DSPCR_CCOND_SMASK): New define.
792 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
793 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
794
21d14896
ILT		 7952005-07-08 Ian Lance Taylor <ian@airs.com>
796
797 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
798
b16d63da 7992005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 800 Nigel Stephens <nigel@mips.com>
801
802 * mips.igen: New mips16e model and include m16e.igen.
803 (check_u64): Add mips16e tag.
804 * m16e.igen: New file for MIPS16e instructions.
805 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
806 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
807 models.
808 * configure: Regenerate.
b16d63da 809
e70cb6cd 8102005-05-26 David Ung <davidu@mips.com>
72f4393d 811
e70cb6cd
CD		 812 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
813 tags to all instructions which are applicable to the new ISAs.
814 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
815 vr.igen.
816 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 817 instructions.
e70cb6cd
CD		 818 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
819 to mips.igen.
820 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
821 * configure: Regenerate.
72f4393d 822
2b193c4a
MK		 8232005-03-23 Mark Kettenis <kettenis@gnu.org>
824
825 * configure: Regenerate.
826
35695fd6
AC		 8272005-01-14 Andrew Cagney <cagney@gnu.org>
828
829 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
830 explicit call to AC_CONFIG_HEADER.
831 * configure: Regenerate.
832
f0569246
AC		 8332005-01-12 Andrew Cagney <cagney@gnu.org>
834
835 * configure.ac: Update to use ../common/common.m4.
836 * configure: Re-generate.
837
38f48d72
AC		 8382005-01-11 Andrew Cagney <cagney@localhost.localdomain>
839
840 * configure: Regenerated to track ../common/aclocal.m4 changes.
841
b7026657
AC		 8422005-01-07 Andrew Cagney <cagney@gnu.org>
843
844 * configure.ac: Rename configure.in, require autoconf 2.59.
845 * configure: Re-generate.
846
379832de
HPN		 8472004-12-08 Hans-Peter Nilsson <hp@axis.com>
848
849 * configure: Regenerate for ../common/aclocal.m4 update.
850
cd62154c 8512004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 852
cd62154c
AC		 853 Committed by Andrew Cagney.
854 * m16.igen (CMP, CMPI): Fix assembler.
855
e5da76ec
CD		 8562004-08-18 Chris Demetriou <cgd@broadcom.com>
857
858 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
859 * configure: Regenerate.
860
139181c8
CD		 8612004-06-25 Chris Demetriou <cgd@broadcom.com>
862
863 * configure.in (sim_m16_machine): Include mipsIII.
864 * configure: Regenerate.
865
1a27f959
CD		 8662004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
867
72f4393d 868 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 869 from COP0_BADVADDR.
870 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
871
5dbb7b5a
CD		 8722004-04-10 Chris Demetriou <cgd@broadcom.com>
873
874 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
875
14234056
CD		 8762004-04-09 Chris Demetriou <cgd@broadcom.com>
877
878 * mips.igen (check_fmt): Remove.
879 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
880 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
881 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
882 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
883 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
884 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
885 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
886 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
887 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
888 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
889
c6f9085c
CD		 8902004-04-09 Chris Demetriou <cgd@broadcom.com>
891
892 * sb1.igen (check_sbx): New function.
893 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
894
11d66e66 8952004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 896 Richard Sandiford <rsandifo@redhat.com>
897
898 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
899 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
900 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
901 separate implementations for mipsIV and mipsV. Use new macros to
902 determine whether the restrictions apply.
903
b3208fb8
CD		 9042004-01-19 Chris Demetriou <cgd@broadcom.com>
905
906 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
907 (check_mult_hilo): Improve comments.
908 (check_div_hilo): Likewise. Also, fork off a new version
909 to handle mips32/mips64 (since there are no hazards to check
910 in MIPS32/MIPS64).
911
9a1d84fb
CD		 9122003-06-17 Richard Sandiford <rsandifo@redhat.com>
913
914 * mips.igen (do_dmultx): Fix check for negative operands.
915
ae451ac6
ILT		 9162003-05-16 Ian Lance Taylor <ian@airs.com>
917
918 * Makefile.in (SHELL): Make sure this is defined.
919 (various): Use $(SHELL) whenever we invoke move-if-change.
920
dd69d292
CD		 9212003-05-03 Chris Demetriou <cgd@broadcom.com>
922
923 * cp1.c: Tweak attribution slightly.
924 * cp1.h: Likewise.
925 * mdmx.c: Likewise.
926 * mdmx.igen: Likewise.
927 * mips3d.igen: Likewise.
928 * sb1.igen: Likewise.
929
bcd0068e
CD		 9302003-04-15 Richard Sandiford <rsandifo@redhat.com>
931
932 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
933 unsigned operands.
934
6b4a8935
AC		 9352003-02-27 Andrew Cagney <cagney@redhat.com>
936
601da316
AC		 937 * interp.c (sim_open): Rename _bfd to bfd.
938 (sim_create_inferior): Ditto.
6b4a8935 939
d29e330f
CD		 9402003-01-14 Chris Demetriou <cgd@broadcom.com>
941
942 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
943
a2353a08
CD		 9442003-01-14 Chris Demetriou <cgd@broadcom.com>
945
946 * mips.igen (EI, DI): Remove.
947
80551777
CD		 9482003-01-05 Richard Sandiford <rsandifo@redhat.com>
949
950 * Makefile.in (tmp-run-multi): Fix mips16 filter.
951
4c54fc26
CD		 9522003-01-04 Richard Sandiford <rsandifo@redhat.com>
953 Andrew Cagney <ac131313@redhat.com>
954 Gavin Romig-Koch <gavin@redhat.com>
955 Graydon Hoare <graydon@redhat.com>
956 Aldy Hernandez <aldyh@redhat.com>
957 Dave Brolley <brolley@redhat.com>
958 Chris Demetriou <cgd@broadcom.com>
959
960 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
961 (sim_mach_default): New variable.
962 (mips64vr-*-*, mips64vrel-*-*): New configurations.
963 Add a new simulator generator, MULTI.
964 * configure: Regenerate.
965 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
966 (multi-run.o): New dependency.
967 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
968 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
969 (tmp-multi): Combine them.
970 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
971 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
972 (distclean-extra): New rule.
973 * sim-main.h: Include bfd.h.
974 (MIPS_MACH): New macro.
975 * mips.igen (vr4120, vr5400, vr5500): New models.
976 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
977 * vr.igen: Replace with new version.
978
e6c674b8
CD		 9792003-01-04 Chris Demetriou <cgd@broadcom.com>
980
981 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
982 * configure: Regenerate.
983
28f50ac8
CD		 9842002-12-31 Chris Demetriou <cgd@broadcom.com>
985
986 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
987 * mips.igen: Remove all invocations of check_branch_bug and
988 mark_branch_bug.
989
5071ffe6
CD		 9902002-12-16 Chris Demetriou <cgd@broadcom.com>
991
72f4393d 992 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 993
06e7837e
CD		 9942002-07-30 Chris Demetriou <cgd@broadcom.com>
995
996 * mips.igen (do_load_double, do_store_double): New functions.
997 (LDC1, SDC1): Rename to...
998 (LDC1b, SDC1b): respectively.
999 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
1000
2265c243
MS		 10012002-07-29 Michael Snyder <msnyder@redhat.com>
1002
1003 * cp1.c (fp_recip2): Modify initialization expression so that
1004 GCC will recognize it as constant.
1005
a2f8b4f3
CD		 10062002-06-18 Chris Demetriou <cgd@broadcom.com>
1007
1008 * mdmx.c (SD_): Delete.
1009 (Unpredictable): Re-define, for now, to directly invoke
1010 unpredictable_action().
1011 (mdmx_acc_op): Fix error in .ob immediate handling.
1012
b4b6c939
AC		 10132002-06-18 Andrew Cagney <cagney@redhat.com>
1014
1015 * interp.c (sim_firmware_command): Initialize `address'.
1016
c8cca39f
AC		 10172002-06-16 Andrew Cagney <ac131313@redhat.com>
1018
1019 * configure: Regenerated to track ../common/aclocal.m4 changes.
1020
e7e81181 10212002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1022 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1023
1024 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1025 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1026 * mips.igen: Include mips3d.igen.
1027 (mips3d): New model name for MIPS-3D ASE instructions.
1028 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1029 instructions.
e7e81181
CD		 1030 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1031 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1032 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1033 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1034 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1035 (RSquareRoot1, RSquareRoot2): New macros.
1036 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1037 (fp_rsqrt2): New functions.
1038 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1039 * configure: Regenerate.
1040
3a2b820e 10412002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1042 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1043
1044 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1045 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1046 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1047 (convert): Note that this function is not used for paired-single
1048 format conversions.
1049 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1050 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1051 (check_fmt_p): Enable paired-single support.
1052 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1053 (PUU.PS): New instructions.
1054 (CVT.S.fmt): Don't use this instruction for paired-single format
1055 destinations.
1056 * sim-main.h (FP_formats): New value 'fmt_ps.'
1057 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1058 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1059
d18ea9c2
CD		 10602002-06-12 Chris Demetriou <cgd@broadcom.com>
1061
1062 * mips.igen: Fix formatting of function calls in
1063 many FP operations.
1064
95fd5cee
CD		 10652002-06-12 Chris Demetriou <cgd@broadcom.com>
1066
1067 * mips.igen (MOVN, MOVZ): Trace result.
1068 (TNEI): Print "tnei" as the opcode name in traces.
1069 (CEIL.W): Add disassembly string for traces.
1070 (RSQRT.fmt): Make location of disassembly string consistent
1071 with other instructions.
1072
4f0d55ae
CD		 10732002-06-12 Chris Demetriou <cgd@broadcom.com>
1074
1075 * mips.igen (X): Delete unused function.
1076
3c25f8c7
AC		 10772002-06-08 Andrew Cagney <cagney@redhat.com>
1078
1079 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1080
f3c08b7e 10812002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1082 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1083
1084 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1085 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1086 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1087 (fp_nmsub): New prototypes.
1088 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1089 (NegMultiplySub): New defines.
1090 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1091 (MADD.D, MADD.S): Replace with...
1092 (MADD.fmt): New instruction.
1093 (MSUB.D, MSUB.S): Replace with...
1094 (MSUB.fmt): New instruction.
1095 (NMADD.D, NMADD.S): Replace with...
1096 (NMADD.fmt): New instruction.
1097 (NMSUB.D, MSUB.S): Replace with...
1098 (NMSUB.fmt): New instruction.
1099
52714ff9 11002002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1101 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1102
1103 * cp1.c: Fix more comment spelling and formatting.
1104 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1105 (denorm_mode): New function.
1106 (fpu_unary, fpu_binary): Round results after operation, collect
1107 status from rounding operations, and update the FCSR.
1108 (convert): Collect status from integer conversions and rounding
1109 operations, and update the FCSR. Adjust NaN values that result
1110 from conversions. Convert to use sim_io_eprintf rather than
1111 fprintf, and remove some debugging code.
1112 * cp1.h (fenr_FS): New define.
1113
577d8c4b
CD		 11142002-06-07 Chris Demetriou <cgd@broadcom.com>
1115
1116 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1117 rounding mode to sim FP rounding mode flag conversion code into...
1118 (rounding_mode): New function.
1119
196496ed
CD		 11202002-06-07 Chris Demetriou <cgd@broadcom.com>
1121
1122 * cp1.c: Clean up formatting of a few comments.
1123 (value_fpr): Reformat switch statement.
1124
cfe9ea23 11252002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1126 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1127
1128 * cp1.h: New file.
1129 * sim-main.h: Include cp1.h.
1130 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1131 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1132 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1133 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1134 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1135 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1136 * cp1.c: Don't include sim-fpu.h; already included by
1137 sim-main.h. Clean up formatting of some comments.
1138 (NaN, Equal, Less): Remove.
1139 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1140 (fp_cmp): New functions.
1141 * mips.igen (do_c_cond_fmt): Remove.
1142 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1143 Compare. Add result tracing.
1144 (CxC1): Remove, replace with...
1145 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1146 (DMxC1): Remove, replace with...
1147 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1148 (MxC1): Remove, replace with...
1149 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1150
ee7254b0
CD		 11512002-06-04 Chris Demetriou <cgd@broadcom.com>
1152
1153 * sim-main.h (FGRIDX): Remove, replace all uses with...
1154 (FGR_BASE): New macro.
1155 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1156 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1157 (NR_FGR, FGR): Likewise.
1158 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1159 * mips.igen: Likewise.
1160
d3eb724f
CD		 11612002-06-04 Chris Demetriou <cgd@broadcom.com>
1162
1163 * cp1.c: Add an FSF Copyright notice to this file.
1164
ba46ddd0 11652002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1166 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1167
1168 * cp1.c (Infinity): Remove.
1169 * sim-main.h (Infinity): Likewise.
1170
1171 * cp1.c (fp_unary, fp_binary): New functions.
1172 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1173 (fp_sqrt): New functions, implemented in terms of the above.
1174 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1175 (Recip, SquareRoot): Remove (replaced by functions above).
1176 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1177 (fp_recip, fp_sqrt): New prototypes.
1178 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1179 (Recip, SquareRoot): Replace prototypes with #defines which
1180 invoke the functions above.
72f4393d 1181
18d8a52d
CD		 11822002-06-03 Chris Demetriou <cgd@broadcom.com>
1183
1184 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1185 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1186 file, remove PARAMS from prototypes.
1187 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1188 simulator state arguments.
1189 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1190 pass simulator state arguments.
1191 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1192 (store_fpr, convert): Remove 'sd' argument.
1193 (value_fpr): Likewise. Convert to use 'SD' instead.
1194
0f154cbd
CD		 11952002-06-03 Chris Demetriou <cgd@broadcom.com>
1196
1197 * cp1.c (Min, Max): Remove #if 0'd functions.
1198 * sim-main.h (Min, Max): Remove.
1199
e80fc152
CD		 12002002-06-03 Chris Demetriou <cgd@broadcom.com>
1201
1202 * cp1.c: fix formatting of switch case and default labels.
1203 * interp.c: Likewise.
1204 * sim-main.c: Likewise.
1205
bad673a9
CD		 12062002-06-03 Chris Demetriou <cgd@broadcom.com>
1207
1208 * cp1.c: Clean up comments which describe FP formats.
1209 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1210
7cbea089 12112002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1212 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1213
1214 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1215 Broadcom SiByte SB-1 processor configurations.
1216 * configure: Regenerate.
1217 * sb1.igen: New file.
1218 * mips.igen: Include sb1.igen.
1219 (sb1): New model.
1220 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1221 * mdmx.igen: Add "sb1" model to all appropriate functions and
1222 instructions.
1223 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1224 (ob_func, ob_acc): Reference the above.
1225 (qh_acc): Adjust to keep the same size as ob_acc.
1226 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1227 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1228
909daa82
CD		 12292002-06-03 Chris Demetriou <cgd@broadcom.com>
1230
1231 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1232
f4f1b9f1 12332002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1234 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1235
1236 * mips.igen (mdmx): New (pseudo-)model.
1237 * mdmx.c, mdmx.igen: New files.
1238 * Makefile.in (SIM_OBJS): Add mdmx.o.
1239 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1240 New typedefs.
1241 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1242 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1243 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1244 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1245 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1246 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1247 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1248 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1249 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1250 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1251 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1252 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1253 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1254 (qh_fmtsel): New macros.
1255 (_sim_cpu): New member "acc".
1256 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1257 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1258
5accf1ff
CD		 12592002-05-01 Chris Demetriou <cgd@broadcom.com>
1260
1261 * interp.c: Use 'deprecated' rather than 'depreciated.'
1262 * sim-main.h: Likewise.
1263
402586aa
CD		 12642002-05-01 Chris Demetriou <cgd@broadcom.com>
1265
1266 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1267 which wouldn't compile anyway.
1268 * sim-main.h (unpredictable_action): New function prototype.
1269 (Unpredictable): Define to call igen function unpredictable().
1270 (NotWordValue): New macro to call igen function not_word_value().
1271 (UndefinedResult): Remove.
1272 * interp.c (undefined_result): Remove.
1273 (unpredictable_action): New function.
1274 * mips.igen (not_word_value, unpredictable): New functions.
1275 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1276 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1277 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1278 NotWordValue() to check for unpredictable inputs, then
1279 Unpredictable() to handle them.
1280
c9b9995a
CD		 12812002-02-24 Chris Demetriou <cgd@broadcom.com>
1282
1283 * mips.igen: Fix formatting of calls to Unpredictable().
1284
e1015982
AC		 12852002-04-20 Andrew Cagney <ac131313@redhat.com>
1286
1287 * interp.c (sim_open): Revert previous change.
1288
b882a66b
AO		 12892002-04-18 Alexandre Oliva <aoliva@redhat.com>
1290
1291 * interp.c (sim_open): Disable chunk of code that wrote code in
1292 vector table entries.
1293
c429b7dd
CD		 12942002-03-19 Chris Demetriou <cgd@broadcom.com>
1295
1296 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1297 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1298 unused definitions.
1299
37d146fa
CD		 13002002-03-19 Chris Demetriou <cgd@broadcom.com>
1301
1302 * cp1.c: Fix many formatting issues.
1303
07892c0b
CD		 13042002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1305
1306 * cp1.c (fpu_format_name): New function to replace...
1307 (DOFMT): This. Delete, and update all callers.
1308 (fpu_rounding_mode_name): New function to replace...
1309 (RMMODE): This. Delete, and update all callers.
1310
487f79b7
CD		 13112002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1312
1313 * interp.c: Move FPU support routines from here to...
1314 * cp1.c: Here. New file.
1315 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1316 (cp1.o): New target.
1317
1e799e28
CD		 13182002-03-12 Chris Demetriou <cgd@broadcom.com>
1319
1320 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1321 * mips.igen (mips32, mips64): New models, add to all instructions
1322 and functions as appropriate.
1323 (loadstore_ea, check_u64): New variant for model mips64.
1324 (check_fmt_p): New variant for models mipsV and mips64, remove
1325 mipsV model marking fro other variant.
1326 (SLL) Rename to...
1327 (SLLa) this.
1328 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1329 for mips32 and mips64.
1330 (DCLO, DCLZ): New instructions for mips64.
1331
82f728db
CD		 13322002-03-07 Chris Demetriou <cgd@broadcom.com>
1333
1334 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1335 immediate or code as a hex value with the "%#lx" format.
1336 (ANDI): Likewise, and fix printed instruction name.
1337
b96e7ef1
CD		 13382002-03-05 Chris Demetriou <cgd@broadcom.com>
1339
1340 * sim-main.h (UndefinedResult, Unpredictable): New macros
1341 which currently do nothing.
1342
d35d4f70
CD		 13432002-03-05 Chris Demetriou <cgd@broadcom.com>
1344
1345 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1346 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1347 (status_CU3): New definitions.
1348
1349 * sim-main.h (ExceptionCause): Add new values for MIPS32
1350 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1351 for DebugBreakPoint and NMIReset to note their status in
1352 MIPS32 and MIPS64.
1353 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1354 (SignalExceptionCacheErr): New exception macros.
1355
3ad6f714
CD		 13562002-03-05 Chris Demetriou <cgd@broadcom.com>
1357
1358 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1359 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1360 is always enabled.
1361 (SignalExceptionCoProcessorUnusable): Take as argument the
1362 unusable coprocessor number.
1363
86b77b47
CD		 13642002-03-05 Chris Demetriou <cgd@broadcom.com>
1365
1366 * mips.igen: Fix formatting of all SignalException calls.
1367
97a88e93 13682002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1369
1370 * sim-main.h (SIGNEXTEND): Remove.
1371
97a88e93 13722002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1373
1374 * mips.igen: Remove gencode comment from top of file, fix
1375 spelling in another comment.
1376
97a88e93 13772002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1378
1379 * mips.igen (check_fmt, check_fmt_p): New functions to check
1380 whether specific floating point formats are usable.
1381 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1382 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1383 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1384 Use the new functions.
1385 (do_c_cond_fmt): Remove format checks...
1386 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1387
97a88e93 13882002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1389
1390 * mips.igen: Fix formatting of check_fpu calls.
1391
41774c9d
CD		 13922002-03-03 Chris Demetriou <cgd@broadcom.com>
1393
1394 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1395
4a0bd876
CD		 13962002-03-03 Chris Demetriou <cgd@broadcom.com>
1397
1398 * mips.igen: Remove whitespace at end of lines.
1399
09297648
CD		 14002002-03-02 Chris Demetriou <cgd@broadcom.com>
1401
1402 * mips.igen (loadstore_ea): New function to do effective
1403 address calculations.
1404 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1405 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1406 CACHE): Use loadstore_ea to do effective address computations.
1407
043b7057
CD		 14082002-03-02 Chris Demetriou <cgd@broadcom.com>
1409
1410 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1411 * mips.igen (LL, CxC1, MxC1): Likewise.
1412
c1e8ada4
CD		 14132002-03-02 Chris Demetriou <cgd@broadcom.com>
1414
1415 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1416 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1417 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1418 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1419 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1420 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1421 Don't split opcode fields by hand, use the opcode field values
1422 provided by igen.
1423
3e1dca16
CD		 14242002-03-01 Chris Demetriou <cgd@broadcom.com>
1425
1426 * mips.igen (do_divu): Fix spacing.
1427
1428 * mips.igen (do_dsllv): Move to be right before DSLLV,
1429 to match the rest of the do_<shift> functions.
1430
fff8d27d
CD		 14312002-03-01 Chris Demetriou <cgd@broadcom.com>
1432
1433 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1434 DSRL32, do_dsrlv): Trace inputs and results.
1435
0d3e762b
CD		 14362002-03-01 Chris Demetriou <cgd@broadcom.com>
1437
1438 * mips.igen (CACHE): Provide instruction-printing string.
1439
1440 * interp.c (signal_exception): Comment tokens after #endif.
1441
eb5fcf93
CD		 14422002-02-28 Chris Demetriou <cgd@broadcom.com>
1443
1444 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1445 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1446 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1447 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1448 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1449 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1450 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1451 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1452
bb22bd7d
CD		 14532002-02-28 Chris Demetriou <cgd@broadcom.com>
1454
1455 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1456 instruction-printing string.
1457 (LWU): Use '64' as the filter flag.
1458
91a177cf
CD		 14592002-02-28 Chris Demetriou <cgd@broadcom.com>
1460
1461 * mips.igen (SDXC1): Fix instruction-printing string.
1462
387f484a
CD		 14632002-02-28 Chris Demetriou <cgd@broadcom.com>
1464
1465 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1466 filter flags "32,f".
1467
3d81f391
CD		 14682002-02-27 Chris Demetriou <cgd@broadcom.com>
1469
1470 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1471 as the filter flag.
1472
af5107af
CD		 14732002-02-27 Chris Demetriou <cgd@broadcom.com>
1474
1475 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1476 add a comma) so that it more closely match the MIPS ISA
1477 documentation opcode partitioning.
1478 (PREF): Put useful names on opcode fields, and include
1479 instruction-printing string.
1480
ca971540
CD		 14812002-02-27 Chris Demetriou <cgd@broadcom.com>
1482
1483 * mips.igen (check_u64): New function which in the future will
1484 check whether 64-bit instructions are usable and signal an
1485 exception if not. Currently a no-op.
1486 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1487 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1488 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1489 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1490
1491 * mips.igen (check_fpu): New function which in the future will
1492 check whether FPU instructions are usable and signal an exception
1493 if not. Currently a no-op.
1494 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1495 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1496 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1497 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1498 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1499 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1500 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1501 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1502
1c47a468
CD		 15032002-02-27 Chris Demetriou <cgd@broadcom.com>
1504
1505 * mips.igen (do_load_left, do_load_right): Move to be immediately
1506 following do_load.
1507 (do_store_left, do_store_right): Move to be immediately following
1508 do_store.
1509
603a98e7
CD		 15102002-02-27 Chris Demetriou <cgd@broadcom.com>
1511
1512 * mips.igen (mipsV): New model name. Also, add it to
1513 all instructions and functions where it is appropriate.
1514
c5d00cc7
CD		 15152002-02-18 Chris Demetriou <cgd@broadcom.com>
1516
1517 * mips.igen: For all functions and instructions, list model
1518 names that support that instruction one per line.
1519
074e9cb8
CD		 15202002-02-11 Chris Demetriou <cgd@broadcom.com>
1521
1522 * mips.igen: Add some additional comments about supported
1523 models, and about which instructions go where.
1524 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1525 order as is used in the rest of the file.
1526
9805e229
CD		 15272002-02-11 Chris Demetriou <cgd@broadcom.com>
1528
1529 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1530 indicating that ALU32_END or ALU64_END are there to check
1531 for overflow.
1532 (DADD): Likewise, but also remove previous comment about
1533 overflow checking.
1534
f701dad2
CD		 15352002-02-10 Chris Demetriou <cgd@broadcom.com>
1536
1537 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1538 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1539 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1540 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1541 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1542 fields (i.e., add and move commas) so that they more closely
1543 match the MIPS ISA documentation opcode partitioning.
1544
15452002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1546
72f4393d
L		 1547 * mips.igen (ADDI): Print immediate value.
1548 (BREAK): Print code.
1549 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1550 (SLL): Print "nop" specially, and don't run the code
1551 that does the shift for the "nop" case.
20ae0098 1552
9e52972e
FF		 15532001-11-17 Fred Fish <fnf@redhat.com>
1554
1555 * sim-main.h (float_operation): Move enum declaration outside
1556 of _sim_cpu struct declaration.
1557
c0efbca4
JB		 15582001-04-12 Jim Blandy <jimb@redhat.com>
1559
1560 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1561 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1562 set of the FCSR.
1563 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1564 PENDING_FILL, and you can get the intended effect gracefully by
1565 calling PENDING_SCHED directly.
1566
fb891446
BE		 15672001-02-23 Ben Elliston <bje@redhat.com>
1568
1569 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1570 already defined elsewhere.
1571
8030f857
BE		 15722001-02-19 Ben Elliston <bje@redhat.com>
1573
1574 * sim-main.h (sim_monitor): Return an int.
1575 * interp.c (sim_monitor): Add return values.
1576 (signal_exception): Handle error conditions from sim_monitor.
1577
56b48a7a
CD		 15782001-02-08 Ben Elliston <bje@redhat.com>
1579
1580 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1581 (store_memory): Likewise, pass cia to sim_core_write*.
1582
d3ee60d9
FCE		 15832000-10-19 Frank Ch. Eigler <fche@redhat.com>
1584
1585 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1586 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1587
071da002
AC		 1588Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1589
1590 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1591 * Makefile.in: Don't delete *.igen when cleaning directory.
1592
a28c02cd
AC		 1593Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1594
1595 * m16.igen (break): Call SignalException not sim_engine_halt.
1596
80ee11fa
AC		 1597Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1598
1599 From Jason Eckhardt:
1600 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1601
673388c0
AC		 1602Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1603
1604 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1605
4c0deff4
NC		 16062000-05-24 Michael Hayes <mhayes@cygnus.com>
1607
1608 * mips.igen (do_dmultx): Fix typo.
1609
eb2d80b4
AC		 1610Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1611
1612 * configure: Regenerated to track ../common/aclocal.m4 changes.
1613
dd37a34b
AC		 1614Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1615
1616 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1617
4c0deff4
NC		 16182000-04-12 Frank Ch. Eigler <fche@redhat.com>
1619
1620 * sim-main.h (GPR_CLEAR): Define macro.
1621
e30db738
AC		 1622Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1623
1624 * interp.c (decode_coproc): Output long using %lx and not %s.
1625
cb7450ea
FCE		 16262000-03-21 Frank Ch. Eigler <fche@redhat.com>
1627
1628 * interp.c (sim_open): Sort & extend dummy memory regions for
1629 --board=jmr3904 for eCos.
1630
a3027dd7
FCE		 16312000-03-02 Frank Ch. Eigler <fche@redhat.com>
1632
1633 * configure: Regenerated.
1634
1635Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1636
1637 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1638 calls, conditional on the simulator being in verbose mode.
1639
dfcd3bfb
JM		 1640Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1641
1642 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1643 cache don't get ReservedInstruction traps.
1644
c2d11a7d
JM		 16451999-11-29 Mark Salter <msalter@cygnus.com>
1646
1647 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1648 to clear status bits in sdisr register. This is how the hardware works.
1649
1650 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1651 being used by cygmon.
1652
4ce44c66
JM		 16531999-11-11 Andrew Haley <aph@cygnus.com>
1654
1655 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1656 instructions.
1657
cff3e48b
JM		 1658Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1659
1660 * mips.igen (MULT): Correct previous mis-applied patch.
1661
d4f3574e
SS		 1662Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1663
1664 * mips.igen (delayslot32): Handle sequence like
1665 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1666 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1667 (MULT): Actually pass the third register...
1668
16691999-09-03 Mark Salter <msalter@cygnus.com>
1670
1671 * interp.c (sim_open): Added more memory aliases for additional
1672 hardware being touched by cygmon on jmr3904 board.
1673
1674Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1675
1676 * configure: Regenerated to track ../common/aclocal.m4 changes.
1677
a0b3c4fd
JM		 1678Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1679
1680 * interp.c (sim_store_register): Handle case where client - GDB -
1681 specifies that a 4 byte register is 8 bytes in size.
1682 (sim_fetch_register): Ditto.
72f4393d 1683
adf40b2e
JM		 16841999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1685
1686 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1687 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1688 (idt_monitor_base): Base address for IDT monitor traps.
1689 (pmon_monitor_base): Ditto for PMON.
1690 (lsipmon_monitor_base): Ditto for LSI PMON.
1691 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1692 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1693 (sim_firmware_command): New function.
1694 (mips_option_handler): Call it for OPTION_FIRMWARE.
1695 (sim_open): Allocate memory for idt_monitor region. If "--board"
1696 option was given, add no monitor by default. Add BREAK hooks only if
1697 monitors are also there.
72f4393d 1698
43e526b9
JM		 1699Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1700
1701 * interp.c (sim_monitor): Flush output before reading input.
1702
1703Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1704
1705 * tconfig.in (SIM_HANDLES_LMA): Always define.
1706
1707Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1708
1709 From Mark Salter <msalter@cygnus.com>:
1710 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1711 (sim_open): Add setup for BSP board.
1712
9846de1b
JM		 1713Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1714
1715 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1716 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1717 them as unimplemented.
1718
cd0fc7c3
SS		 17191999-05-08 Felix Lee <flee@cygnus.com>
1720
1721 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1722
7a292a7a
SS		 17231999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1724
1725 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1726
1727Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1728
1729 * configure.in: Any mips64vr5*-*-* target should have
1730 -DTARGET_ENABLE_FR=1.
1731 (default_endian): Any mips64vr*el-*-* target should default to
1732 LITTLE_ENDIAN.
1733 * configure: Re-generate.
1734
17351999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1736
1737 * mips.igen (ldl): Extend from _16_, not 32.
1738
1739Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1740
1741 * interp.c (sim_store_register): Force registers written to by GDB
1742 into an un-interpreted state.
1743
c906108c
SS		 17441999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1745
1746 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1747 CPU, start periodic background I/O polls.
72f4393d 1748 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1749
17501998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1751
1752 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1753
c906108c
SS		 1754Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1755
1756 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1757 case statement.
1758
17591998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1760
1761 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1762 (load_word): Call SIM_CORE_SIGNAL hook on error.
1763 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1764 starting. For exception dispatching, pass PC instead of NULL_CIA.
1765 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1766 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1767 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1768 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1769 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1770 * mips.igen (*): Replace memory-related SignalException* calls
1771 with references to SIM_CORE_SIGNAL hook.
72f4393d 1772
c906108c
SS		 1773 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1774 fix.
1775 * sim-main.c (*): Minor warning cleanups.
72f4393d 1776
c906108c
SS		 17771998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1778
1779 * m16.igen (DADDIU5): Correct type-o.
1780
1781Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1782
1783 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1784 variables.
1785
1786Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1787
1788 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1789 to include path.
1790 (interp.o): Add dependency on itable.h
1791 (oengine.c, gencode): Delete remaining references.
1792 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1793
c906108c 17941998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1795
c906108c
SS		 1796 * vr4run.c: New.
1797 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1798 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1799 tmp-run-hack) : New.
1800 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1801 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1802 Drop the "64" qualifier to get the HACK generator working.
1803 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1804 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1805 qualifier to get the hack generator working.
1806 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1807 (DSLL): Use do_dsll.
1808 (DSLLV): Use do_dsllv.
1809 (DSRA): Use do_dsra.
1810 (DSRL): Use do_dsrl.
1811 (DSRLV): Use do_dsrlv.
1812 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1813 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1814 get the HACK generator working.
1815 (MACC) Rename to get the HACK generator working.
1816 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1817
c906108c
SS		 18181998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1819
1820 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1821 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1822
c906108c
SS		 18231998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1824
1825 * mips/interp.c (DEBUG): Cleanups.
1826
18271998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1828
1829 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1830 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1831
c906108c
SS		 18321998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1833
1834 * interp.c (sim_close): Uninstall modules.
1835
1836Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1837
1838 * sim-main.h, interp.c (sim_monitor): Change to global
1839 function.
1840
1841Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1842
1843 * configure.in (vr4100): Only include vr4100 instructions in
1844 simulator.
1845 * configure: Re-generate.
1846 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1847
1848Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1849
1850 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1851 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1852 true alternative.
1853
1854 * configure.in (sim_default_gen, sim_use_gen): Replace with
1855 sim_gen.
1856 (--enable-sim-igen): Delete config option. Always using IGEN.
1857 * configure: Re-generate.
72f4393d 1858
c906108c
SS		 1859 * Makefile.in (gencode): Kill, kill, kill.
1860 * gencode.c: Ditto.
72f4393d 1861
c906108c
SS		 1862Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1863
1864 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1865 bit mips16 igen simulator.
1866 * configure: Re-generate.
1867
1868 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1869 as part of vr4100 ISA.
1870 * vr.igen: Mark all instructions as 64 bit only.
1871
1872Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1873
1874 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1875 Pacify GCC.
1876
1877Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1878
1879 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1880 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1881 * configure: Re-generate.
1882
1883 * m16.igen (BREAK): Define breakpoint instruction.
1884 (JALX32): Mark instruction as mips16 and not r3900.
1885 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1886
1887 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1888
1889Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1890
1891 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1892 insn as a debug breakpoint.
1893
1894 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1895 pending.slot_size.
1896 (PENDING_SCHED): Clean up trace statement.
1897 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1898 (PENDING_FILL): Delay write by only one cycle.
1899 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1900
1901 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1902 of pending writes.
1903 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1904 32 & 64.
1905 (pending_tick): Move incrementing of index to FOR statement.
1906 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1907
c906108c
SS		 1908 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1909 build simulator.
1910 * configure: Re-generate.
72f4393d 1911
c906108c
SS		 1912 * interp.c (sim_engine_run OLD): Delete explicit call to
1913 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1914
c906108c
SS		 1915Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1916
1917 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1918 interrupt level number to match changed SignalExceptionInterrupt
1919 macro.
1920
1921Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1922
1923 * interp.c: #include "itable.h" if WITH_IGEN.
1924 (get_insn_name): New function.
1925 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1926 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1927
1928Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1929
1930 * configure: Rebuilt to inhale new common/aclocal.m4.
1931
1932Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1933
1934 * dv-tx3904sio.c: Include sim-assert.h.
1935
1936Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1937
1938 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1939 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1940 Reorganize target-specific sim-hardware checks.
1941 * configure: rebuilt.
1942 * interp.c (sim_open): For tx39 target boards, set
1943 OPERATING_ENVIRONMENT, add tx3904sio devices.
1944 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1945 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1946
c906108c
SS		 1947 * dv-tx3904irc.c: Compiler warning clean-up.
1948 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1949 frequent hw-trace messages.
1950
1951Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1952
1953 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1954
1955Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1956
1957 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1958
1959 * vr.igen: New file.
1960 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1961 * mips.igen: Define vr4100 model. Include vr.igen.
1962Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1963
1964 * mips.igen (check_mf_hilo): Correct check.
1965
1966Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1967
1968 * sim-main.h (interrupt_event): Add prototype.
1969
1970 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1971 register_ptr, register_value.
1972 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1973
1974 * sim-main.h (tracefh): Make extern.
1975
1976Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1977
1978 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1979 Reduce unnecessarily high timer event frequency.
c906108c 1980 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1981
c906108c
SS		 1982Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1983
1984 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1985 to allay warnings.
1986 (interrupt_event): Made non-static.
72f4393d 1987
c906108c
SS		 1988 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1989 interchange of configuration values for external vs. internal
1990 clock dividers.
72f4393d 1991
c906108c
SS		 1992Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1993
72f4393d 1994 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1995 simulator-reserved break instructions.
1996 * gencode.c (build_instruction): Ditto.
1997 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1998 reserved instructions now use exception vector, rather
c906108c
SS		 1999 than halting sim.
2000 * sim-main.h: Moved magic constants to here.
2001
2002Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
2003
2004 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
2005 register upon non-zero interrupt event level, clear upon zero
2006 event value.
2007 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
2008 by passing zero event value.
2009 (*_io_{read,write}_buffer): Endianness fixes.
2010 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
2011 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
2012
2013 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
2014 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 2015
c906108c
SS		 2016Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
2017
72f4393d 2018 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2019 and BigEndianCPU.
2020
2021Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2022
2023 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2024 parts.
2025 * configure: Update.
2026
2027Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2028
2029 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2030 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2031 * configure.in: Include tx3904tmr in hw_device list.
2032 * configure: Rebuilt.
2033 * interp.c (sim_open): Instantiate three timer instances.
2034 Fix address typo of tx3904irc instance.
2035
2036Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2037
2038 * interp.c (signal_exception): SystemCall exception now uses
2039 the exception vector.
2040
2041Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2042
2043 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2044 to allay warnings.
2045
2046Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2047
2048 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2049
2050Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2051
2052 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2053
2054 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2055 sim-main.h. Declare a struct hw_descriptor instead of struct
2056 hw_device_descriptor.
2057
2058Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2059
2060 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2061 right bits and then re-align left hand bytes to correct byte
2062 lanes. Fix incorrect computation in do_store_left when loading
2063 bytes from second word.
2064
2065Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2066
2067 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2068 * interp.c (sim_open): Only create a device tree when HW is
2069 enabled.
2070
2071 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2072 * interp.c (signal_exception): Ditto.
2073
2074Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2075
2076 * gencode.c: Mark BEGEZALL as LIKELY.
2077
2078Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2079
2080 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2081 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2082
c906108c
SS		 2083Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2084
2085 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2086 modules. Recognize TX39 target with "mips*tx39" pattern.
2087 * configure: Rebuilt.
2088 * sim-main.h (*): Added many macros defining bits in
2089 TX39 control registers.
2090 (SignalInterrupt): Send actual PC instead of NULL.
2091 (SignalNMIReset): New exception type.
2092 * interp.c (board): New variable for future use to identify
2093 a particular board being simulated.
2094 (mips_option_handler,mips_options): Added "--board" option.
2095 (interrupt_event): Send actual PC.
2096 (sim_open): Make memory layout conditional on board setting.
2097 (signal_exception): Initial implementation of hardware interrupt
2098 handling. Accept another break instruction variant for simulator
2099 exit.
2100 (decode_coproc): Implement RFE instruction for TX39.
2101 (mips.igen): Decode RFE instruction as such.
2102 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2103 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2104 bbegin to implement memory map.
2105 * dv-tx3904cpu.c: New file.
2106 * dv-tx3904irc.c: New file.
2107
2108Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2109
2110 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2111
2112Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2113
2114 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2115 with calls to check_div_hilo.
2116
2117Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2118
2119 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2120 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2121 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2122 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2123 with calls to check_mult_hilo.
2124 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2125 with calls to check_div_hilo.
2126
2127Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2128
2129 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2130 Document a replacement.
2131
2132Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2133
2134 * interp.c (sim_monitor): Make mon_printf work.
2135
2136Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2137
2138 * sim-main.h (INSN_NAME): New arg `cpu'.
2139
2140Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2141
72f4393d 2142 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2143
2144Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2145
2146 * configure: Regenerated to track ../common/aclocal.m4 changes.
2147 * config.in: Ditto.
2148
2149Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2150
2151 * acconfig.h: New file.
2152 * configure.in: Reverted change of Apr 24; use sinclude again.
2153
2154Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2155
2156 * configure: Regenerated to track ../common/aclocal.m4 changes.
2157 * config.in: Ditto.
2158
2159Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2160
2161 * configure.in: Don't call sinclude.
2162
2163Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2164
2165 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2166
2167Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2168
2169 * mips.igen (ERET): Implement.
2170
2171 * interp.c (decode_coproc): Return sign-extended EPC.
2172
2173 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2174
2175 * interp.c (signal_exception): Do not ignore Trap.
2176 (signal_exception): On TRAP, restart at exception address.
2177 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2178 (signal_exception): Update.
2179 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2180 so that TRAP instructions are caught.
2181
2182Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2183
2184 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2185 contains HI/LO access history.
2186 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2187 (HIACCESS, LOACCESS): Delete, replace with
2188 (HIHISTORY, LOHISTORY): New macros.
2189 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2190
c906108c
SS		 2191 * gencode.c (build_instruction): Do not generate checks for
2192 correct HI/LO register usage.
2193
2194 * interp.c (old_engine_run): Delete checks for correct HI/LO
2195 register usage.
2196
2197 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2198 check_mf_cycles): New functions.
2199 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2200 do_divu, domultx, do_mult, do_multu): Use.
2201
2202 * tx.igen ("madd", "maddu"): Use.
72f4393d 2203
c906108c
SS		 2204Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2205
2206 * mips.igen (DSRAV): Use function do_dsrav.
2207 (SRAV): Use new function do_srav.
2208
2209 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2210 (B): Sign extend 11 bit immediate.
2211 (EXT-B*): Shift 16 bit immediate left by 1.
2212 (ADDIU*): Don't sign extend immediate value.
2213
2214Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2215
2216 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2217
2218 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2219 functions.
2220
2221 * mips.igen (delayslot32, nullify_next_insn): New functions.
2222 (m16.igen): Always include.
2223 (do_*): Add more tracing.
2224
2225 * m16.igen (delayslot16): Add NIA argument, could be called by a
2226 32 bit MIPS16 instruction.
72f4393d 2227
c906108c
SS		 2228 * interp.c (ifetch16): Move function from here.
2229 * sim-main.c (ifetch16): To here.
72f4393d 2230
c906108c
SS		 2231 * sim-main.c (ifetch16, ifetch32): Update to match current
2232 implementations of LH, LW.
2233 (signal_exception): Don't print out incorrect hex value of illegal
2234 instruction.
2235
2236Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2237
2238 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2239 instruction.
2240
2241 * m16.igen: Implement MIPS16 instructions.
72f4393d 2242
c906108c
SS		 2243 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2244 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2245 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2246 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2247 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2248 bodies of corresponding code from 32 bit insn to these. Also used
2249 by MIPS16 versions of functions.
72f4393d 2250
c906108c
SS		 2251 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2252 (IMEM16): Drop NR argument from macro.
2253
2254Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2255
2256 * Makefile.in (SIM_OBJS): Add sim-main.o.
2257
2258 * sim-main.h (address_translation, load_memory, store_memory,
2259 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2260 as INLINE_SIM_MAIN.
2261 (pr_addr, pr_uword64): Declare.
2262 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2263
c906108c
SS		 2264 * interp.c (address_translation, load_memory, store_memory,
2265 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2266 from here.
2267 * sim-main.c: To here. Fix compilation problems.
72f4393d 2268
c906108c
SS		 2269 * configure.in: Enable inlining.
2270 * configure: Re-config.
2271
2272Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2273
2274 * configure: Regenerated to track ../common/aclocal.m4 changes.
2275
2276Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2277
2278 * mips.igen: Include tx.igen.
2279 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2280 * tx.igen: New file, contains MADD and MADDU.
2281
2282 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2283 the hardwired constant `7'.
2284 (store_memory): Ditto.
2285 (LOADDRMASK): Move definition to sim-main.h.
2286
2287 mips.igen (MTC0): Enable for r3900.
2288 (ADDU): Add trace.
2289
2290 mips.igen (do_load_byte): Delete.
2291 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2292 do_store_right): New functions.
2293 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2294
2295 configure.in: Let the tx39 use igen again.
2296 configure: Update.
72f4393d 2297
c906108c
SS		 2298Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2299
2300 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2301 not an address sized quantity. Return zero for cache sizes.
2302
2303Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2304
2305 * mips.igen (r3900): r3900 does not support 64 bit integer
2306 operations.
2307
2308Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2309
2310 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2311 than igen one.
2312 * configure : Rebuild.
72f4393d 2313
c906108c
SS		 2314Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2315
2316 * configure: Regenerated to track ../common/aclocal.m4 changes.
2317
2318Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2319
2320 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2321
2322Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2323
2324 * configure: Regenerated to track ../common/aclocal.m4 changes.
2325 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2326
2327Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2328
2329 * configure: Regenerated to track ../common/aclocal.m4 changes.
2330
2331Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2332
2333 * interp.c (Max, Min): Comment out functions. Not yet used.
2334
2335Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2336
2337 * configure: Regenerated to track ../common/aclocal.m4 changes.
2338
2339Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2340
2341 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2342 configurable settings for stand-alone simulator.
72f4393d 2343
c906108c 2344 * configure.in: Added X11 search, just in case.
72f4393d 2345
c906108c
SS		 2346 * configure: Regenerated.
2347
2348Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2349
2350 * interp.c (sim_write, sim_read, load_memory, store_memory):
2351 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2352
2353Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2354
2355 * sim-main.h (GETFCC): Return an unsigned value.
2356
2357Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2360 (DADD): Result destination is RD not RT.
2361
2362Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2363
2364 * sim-main.h (HIACCESS, LOACCESS): Always define.
2365
2366 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2367
2368 * interp.c (sim_info): Delete.
2369
2370Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2371
2372 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2373 (mips_option_handler): New argument `cpu'.
2374 (sim_open): Update call to sim_add_option_table.
2375
2376Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2377
2378 * mips.igen (CxC1): Add tracing.
2379
2380Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2381
2382 * sim-main.h (Max, Min): Declare.
2383
2384 * interp.c (Max, Min): New functions.
2385
2386 * mips.igen (BC1): Add tracing.
72f4393d 2387
c906108c 2388Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2389
c906108c 2390 * interp.c Added memory map for stack in vr4100
72f4393d 2391
c906108c
SS		 2392Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2393
2394 * interp.c (load_memory): Add missing "break"'s.
2395
2396Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2397
2398 * interp.c (sim_store_register, sim_fetch_register): Pass in
2399 length parameter. Return -1.
2400
2401Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2402
2403 * interp.c: Added hardware init hook, fixed warnings.
2404
2405Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2406
2407 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2408
2409Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2410
2411 * interp.c (ifetch16): New function.
2412
2413 * sim-main.h (IMEM32): Rename IMEM.
2414 (IMEM16_IMMED): Define.
2415 (IMEM16): Define.
2416 (DELAY_SLOT): Update.
72f4393d 2417
c906108c 2418 * m16run.c (sim_engine_run): New file.
72f4393d 2419
c906108c
SS		 2420 * m16.igen: All instructions except LB.
2421 (LB): Call do_load_byte.
2422 * mips.igen (do_load_byte): New function.
2423 (LB): Call do_load_byte.
2424
2425 * mips.igen: Move spec for insn bit size and high bit from here.
2426 * Makefile.in (tmp-igen, tmp-m16): To here.
2427
2428 * m16.dc: New file, decode mips16 instructions.
2429
2430 * Makefile.in (SIM_NO_ALL): Define.
2431 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2432
2433Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2434
2435 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2436 point unit to 32 bit registers.
2437 * configure: Re-generate.
2438
2439Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2440
2441 * configure.in (sim_use_gen): Make IGEN the default simulator
2442 generator for generic 32 and 64 bit mips targets.
2443 * configure: Re-generate.
2444
2445Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2446
2447 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2448 bitsize.
2449
2450 * interp.c (sim_fetch_register, sim_store_register): Read/write
2451 FGR from correct location.
2452 (sim_open): Set size of FGR's according to
2453 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2454
c906108c
SS		 2455 * sim-main.h (FGR): Store floating point registers in a separate
2456 array.
2457
2458Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2459
2460 * configure: Regenerated to track ../common/aclocal.m4 changes.
2461
2462Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2463
2464 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2465
2466 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2467
2468 * interp.c (pending_tick): New function. Deliver pending writes.
2469
2470 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2471 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2472 it can handle mixed sized quantites and single bits.
72f4393d 2473
c906108c
SS		 2474Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2475
2476 * interp.c (oengine.h): Do not include when building with IGEN.
2477 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2478 (sim_info): Ditto for PROCESSOR_64BIT.
2479 (sim_monitor): Replace ut_reg with unsigned_word.
2480 (*): Ditto for t_reg.
2481 (LOADDRMASK): Define.
2482 (sim_open): Remove defunct check that host FP is IEEE compliant,
2483 using software to emulate floating point.
2484 (value_fpr, ...): Always compile, was conditional on HASFPU.
2485
2486Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2487
2488 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2489 size.
2490
2491 * interp.c (SD, CPU): Define.
2492 (mips_option_handler): Set flags in each CPU.
2493 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2494 (sim_close): Do not clear STATE, deleted anyway.
2495 (sim_write, sim_read): Assume CPU zero's vm should be used for
2496 data transfers.
2497 (sim_create_inferior): Set the PC for all processors.
2498 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2499 argument.
2500 (mips16_entry): Pass correct nr of args to store_word, load_word.
2501 (ColdReset): Cold reset all cpu's.
2502 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2503 (sim_monitor, load_memory, store_memory, signal_exception): Use
2504 `CPU' instead of STATE_CPU.
2505
2506
2507 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2508 SD or CPU_.
72f4393d 2509
c906108c
SS		 2510 * sim-main.h (signal_exception): Add sim_cpu arg.
2511 (SignalException*): Pass both SD and CPU to signal_exception.
2512 * interp.c (signal_exception): Update.
72f4393d 2513
c906108c
SS		 2514 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2515 Ditto
2516 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2517 address_translation): Ditto
2518 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2519
c906108c
SS		 2520Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2521
2522 * configure: Regenerated to track ../common/aclocal.m4 changes.
2523
2524Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2525
2526 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2527
72f4393d 2528 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2529
2530 * sim-main.h (CPU_CIA): Delete.
2531 (SET_CIA, GET_CIA): Define
2532
2533Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2534
2535 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2536 regiser.
2537
2538 * configure.in (default_endian): Configure a big-endian simulator
2539 by default.
2540 * configure: Re-generate.
72f4393d 2541
c906108c
SS		 2542Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2543
2544 * configure: Regenerated to track ../common/aclocal.m4 changes.
2545
2546Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2547
2548 * interp.c (sim_monitor): Handle Densan monitor outbyte
2549 and inbyte functions.
2550
25511997-12-29 Felix Lee <flee@cygnus.com>
2552
2553 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2554
2555Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2556
2557 * Makefile.in (tmp-igen): Arrange for $zero to always be
2558 reset to zero after every instruction.
2559
2560Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2561
2562 * configure: Regenerated to track ../common/aclocal.m4 changes.
2563 * config.in: Ditto.
2564
2565Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2566
2567 * mips.igen (MSUB): Fix to work like MADD.
2568 * gencode.c (MSUB): Similarly.
2569
2570Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2571
2572 * configure: Regenerated to track ../common/aclocal.m4 changes.
2573
2574Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2575
2576 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2577
2578Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2579
2580 * sim-main.h (sim-fpu.h): Include.
2581
2582 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2583 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2584 using host independant sim_fpu module.
2585
2586Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2587
2588 * interp.c (signal_exception): Report internal errors with SIGABRT
2589 not SIGQUIT.
2590
2591 * sim-main.h (C0_CONFIG): New register.
2592 (signal.h): No longer include.
2593
2594 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2595
2596Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2597
2598 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2599
2600Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2601
2602 * mips.igen: Tag vr5000 instructions.
2603 (ANDI): Was missing mipsIV model, fix assembler syntax.
2604 (do_c_cond_fmt): New function.
2605 (C.cond.fmt): Handle mips I-III which do not support CC field
2606 separatly.
2607 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2608 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2609 in IV3.2 spec.
2610 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2611 vr5000 which saves LO in a GPR separatly.
72f4393d 2612
c906108c
SS		 2613 * configure.in (enable-sim-igen): For vr5000, select vr5000
2614 specific instructions.
2615 * configure: Re-generate.
72f4393d 2616
c906108c
SS		 2617Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2618
2619 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2620
2621 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2622 fmt_uninterpreted_64 bit cases to switch. Convert to
2623 fmt_formatted,
2624
2625 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2626
2627 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2628 as specified in IV3.2 spec.
2629 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2630
2631Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2632
2633 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2634 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2635 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2636 PENDING_FILL versions of instructions. Simplify.
2637 (X): New function.
2638 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2639 instructions.
2640 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2641 a signed value.
2642 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2643
c906108c
SS		 2644 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2645 global.
2646 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2647
2648Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2649
2650 * gencode.c (build_mips16_operands): Replace IPC with cia.
2651
2652 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2653 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2654 IPC to `cia'.
2655 (UndefinedResult): Replace function with macro/function
2656 combination.
2657 (sim_engine_run): Don't save PC in IPC.
2658
2659 * sim-main.h (IPC): Delete.
2660
2661
2662 * interp.c (signal_exception, store_word, load_word,
2663 address_translation, load_memory, store_memory, cache_op,
2664 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2665 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2666 current instruction address - cia - argument.
2667 (sim_read, sim_write): Call address_translation directly.
2668 (sim_engine_run): Rename variable vaddr to cia.
2669 (signal_exception): Pass cia to sim_monitor
72f4393d 2670
c906108c
SS		 2671 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2672 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2673 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2674
2675 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2676 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2677 SIM_ASSERT.
72f4393d 2678
c906108c
SS		 2679 * interp.c (signal_exception): Pass restart address to
2680 sim_engine_restart.
2681
2682 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2683 idecode.o): Add dependency.
2684
2685 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2686 Delete definitions
2687 (DELAY_SLOT): Update NIA not PC with branch address.
2688 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2689
2690 * mips.igen: Use CIA not PC in branch calculations.
2691 (illegal): Call SignalException.
2692 (BEQ, ADDIU): Fix assembler.
2693
2694Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2695
2696 * m16.igen (JALX): Was missing.
2697
2698 * configure.in (enable-sim-igen): New configuration option.
2699 * configure: Re-generate.
72f4393d 2700
c906108c
SS		 2701 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2702
2703 * interp.c (load_memory, store_memory): Delete parameter RAW.
2704 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2705 bypassing {load,store}_memory.
2706
2707 * sim-main.h (ByteSwapMem): Delete definition.
2708
2709 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2710
2711 * interp.c (sim_do_command, sim_commands): Delete mips specific
2712 commands. Handled by module sim-options.
72f4393d 2713
c906108c
SS		 2714 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2715 (WITH_MODULO_MEMORY): Define.
2716
2717 * interp.c (sim_info): Delete code printing memory size.
2718
2719 * interp.c (mips_size): Nee sim_size, delete function.
2720 (power2): Delete.
2721 (monitor, monitor_base, monitor_size): Delete global variables.
2722 (sim_open, sim_close): Delete code creating monitor and other
2723 memory regions. Use sim-memopts module, via sim_do_commandf, to
2724 manage memory regions.
2725 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2726
c906108c
SS		 2727 * interp.c (address_translation): Delete all memory map code
2728 except line forcing 32 bit addresses.
2729
2730Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2731
2732 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2733 trace options.
2734
2735 * interp.c (logfh, logfile): Delete globals.
2736 (sim_open, sim_close): Delete code opening & closing log file.
2737 (mips_option_handler): Delete -l and -n options.
2738 (OPTION mips_options): Ditto.
2739
2740 * interp.c (OPTION mips_options): Rename option trace to dinero.
2741 (mips_option_handler): Update.
2742
2743Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2744
2745 * interp.c (fetch_str): New function.
2746 (sim_monitor): Rewrite using sim_read & sim_write.
2747 (sim_open): Check magic number.
2748 (sim_open): Write monitor vectors into memory using sim_write.
2749 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2750 (sim_read, sim_write): Simplify - transfer data one byte at a
2751 time.
2752 (load_memory, store_memory): Clarify meaning of parameter RAW.
2753
2754 * sim-main.h (isHOST): Defete definition.
2755 (isTARGET): Mark as depreciated.
2756 (address_translation): Delete parameter HOST.
2757
2758 * interp.c (address_translation): Delete parameter HOST.
2759
2760Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2761
72f4393d 2762 * mips.igen:
c906108c
SS		 2763
2764 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2765 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2766
2767Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2768
2769 * mips.igen: Add model filter field to records.
2770
2771Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2772
2773 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2774
c906108c
SS		 2775 interp.c (sim_engine_run): Do not compile function sim_engine_run
2776 when WITH_IGEN == 1.
2777
2778 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2779 target architecture.
2780
2781 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2782 igen. Replace with configuration variables sim_igen_flags /
2783 sim_m16_flags.
2784
2785 * m16.igen: New file. Copy mips16 insns here.
2786 * mips.igen: From here.
2787
2788Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2789
2790 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2791 to top.
2792 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2793
2794Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2795
2796 * gencode.c (build_instruction): Follow sim_write's lead in using
2797 BigEndianMem instead of !ByteSwapMem.
2798
2799Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2800
2801 * configure.in (sim_gen): Dependent on target, select type of
2802 generator. Always select old style generator.
2803
2804 configure: Re-generate.
2805
2806 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2807 targets.
2808 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2809 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2810 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2811 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2812 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2813
c906108c
SS		 2814Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2815
2816 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2817
2818 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2819 CURRENT_FLOATING_POINT instead.
2820
2821 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2822 (address_translation): Raise exception InstructionFetch when
2823 translation fails and isINSTRUCTION.
72f4393d 2824
c906108c
SS		 2825 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2826 sim_engine_run): Change type of of vaddr and paddr to
2827 address_word.
2828 (address_translation, prefetch, load_memory, store_memory,
2829 cache_op): Change type of vAddr and pAddr to address_word.
2830
2831 * gencode.c (build_instruction): Change type of vaddr and paddr to
2832 address_word.
2833
2834Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2835
2836 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2837 macro to obtain result of ALU op.
2838
2839Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2840
2841 * interp.c (sim_info): Call profile_print.
2842
2843Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2844
2845 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2846
2847 * sim-main.h (WITH_PROFILE): Do not define, defined in
2848 common/sim-config.h. Use sim-profile module.
2849 (simPROFILE): Delete defintion.
2850
2851 * interp.c (PROFILE): Delete definition.
2852 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2853 (sim_close): Delete code writing profile histogram.
2854 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2855 Delete.
2856 (sim_engine_run): Delete code profiling the PC.
2857
2858Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2859
2860 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2861
2862 * interp.c (sim_monitor): Make register pointers of type
2863 unsigned_word*.
2864
2865 * sim-main.h: Make registers of type unsigned_word not
2866 signed_word.
2867
2868Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2869
2870 * interp.c (sync_operation): Rename from SyncOperation, make
2871 global, add SD argument.
2872 (prefetch): Rename from Prefetch, make global, add SD argument.
2873 (decode_coproc): Make global.
2874
2875 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2876
2877 * gencode.c (build_instruction): Generate DecodeCoproc not
2878 decode_coproc calls.
2879
2880 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2881 (SizeFGR): Move to sim-main.h
2882 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2883 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2884 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2885 sim-main.h.
2886 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2887 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2888 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2889 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2890 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2891 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2892
c906108c
SS		 2893 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2894 exception.
2895 (sim-alu.h): Include.
2896 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2897 (sim_cia): Typedef to instruction_address.
72f4393d 2898
c906108c
SS		 2899Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2900
2901 * Makefile.in (interp.o): Rename generated file engine.c to
2902 oengine.c.
72f4393d 2903
c906108c 2904 * interp.c: Update.
72f4393d 2905
c906108c
SS		 2906Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2907
2908 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2909
c906108c
SS		 2910Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2911
2912 * gencode.c (build_instruction): For "FPSQRT", output correct
2913 number of arguments to Recip.
72f4393d 2914
c906108c
SS		 2915Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2916
2917 * Makefile.in (interp.o): Depends on sim-main.h
2918
2919 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2920
2921 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2922 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2923 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2924 STATE, DSSTATE): Define
2925 (GPR, FGRIDX, ..): Define.
2926
2927 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2928 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2929 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2930
c906108c 2931 * interp.c: Update names to match defines from sim-main.h
72f4393d 2932
c906108c
SS		 2933Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2934
2935 * interp.c (sim_monitor): Add SD argument.
2936 (sim_warning): Delete. Replace calls with calls to
2937 sim_io_eprintf.
2938 (sim_error): Delete. Replace calls with sim_io_error.
2939 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2940 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2941 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2942 argument.
2943 (mips_size): Rename from sim_size. Add SD argument.
2944
2945 * interp.c (simulator): Delete global variable.
2946 (callback): Delete global variable.
2947 (mips_option_handler, sim_open, sim_write, sim_read,
2948 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2949 sim_size,sim_monitor): Use sim_io_* not callback->*.
2950 (sim_open): ZALLOC simulator struct.
2951 (PROFILE): Do not define.
2952
2953Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2954
2955 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2956 support.h with corresponding code.
2957
2958 * sim-main.h (word64, uword64), support.h: Move definition to
2959 sim-main.h.
2960 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2961
2962 * support.h: Delete
2963 * Makefile.in: Update dependencies
2964 * interp.c: Do not include.
72f4393d 2965
c906108c
SS		 2966Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2967
2968 * interp.c (address_translation, load_memory, store_memory,
2969 cache_op): Rename to from AddressTranslation et.al., make global,
2970 add SD argument
72f4393d 2971
c906108c
SS		 2972 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2973 CacheOp): Define.
72f4393d 2974
c906108c
SS		 2975 * interp.c (SignalException): Rename to signal_exception, make
2976 global.
2977
2978 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2979
c906108c
SS		 2980 * sim-main.h (SignalException, SignalExceptionInterrupt,
2981 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2982 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2983 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2984 Define.
72f4393d 2985
c906108c 2986 * interp.c, support.h: Use.
72f4393d 2987
c906108c
SS		 2988Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2989
2990 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2991 to value_fpr / store_fpr. Add SD argument.
2992 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2993 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2994
2995 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2996
c906108c
SS		 2997Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2998
2999 * interp.c (sim_engine_run): Check consistency between configure
3000 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
3001 and HASFPU.
3002
3003 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 3004 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 3005 (mips_endian): Configure WITH_TARGET_ENDIAN.
3006 * configure: Update.
3007
3008Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3009
3010 * configure: Regenerated to track ../common/aclocal.m4 changes.
3011
3012Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
3013
3014 * configure: Regenerated.
3015
3016Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
3017
3018 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3019
3020Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3021
3022 * gencode.c (print_igen_insn_models): Assume certain architectures
3023 include all mips* instructions.
3024 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3025 instruction.
3026
3027 * Makefile.in (tmp.igen): Add target. Generate igen input from
3028 gencode file.
3029
3030 * gencode.c (FEATURE_IGEN): Define.
3031 (main): Add --igen option. Generate output in igen format.
3032 (process_instructions): Format output according to igen option.
3033 (print_igen_insn_format): New function.
3034 (print_igen_insn_models): New function.
3035 (process_instructions): Only issue warnings and ignore
3036 instructions when no FEATURE_IGEN.
3037
3038Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3039
3040 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3041 MIPS targets.
3042
3043Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3044
3045 * configure: Regenerated to track ../common/aclocal.m4 changes.
3046
3047Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3048
3049 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3050 SIM_RESERVED_BITS): Delete, moved to common.
3051 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3052
c906108c
SS		 3053Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3054
3055 * configure.in: Configure non-strict memory alignment.
3056 * configure: Regenerated to track ../common/aclocal.m4 changes.
3057
3058Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3059
3060 * configure: Regenerated to track ../common/aclocal.m4 changes.
3061
3062Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3063
3064 * gencode.c (SDBBP,DERET): Added (3900) insns.
3065 (RFE): Turn on for 3900.
3066 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3067 (dsstate): Made global.
3068 (SUBTARGET_R3900): Added.
3069 (CANCELDELAYSLOT): New.
3070 (SignalException): Ignore SystemCall rather than ignore and
3071 terminate. Add DebugBreakPoint handling.
3072 (decode_coproc): New insns RFE, DERET; and new registers Debug
3073 and DEPC protected by SUBTARGET_R3900.
3074 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3075 bits explicitly.
3076 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3077 * configure: Update.
c906108c
SS		 3078
3079Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3080
3081 * gencode.c: Add r3900 (tx39).
72f4393d 3082
c906108c
SS		 3083
3084Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3085
3086 * gencode.c (build_instruction): Don't need to subtract 4 for
3087 JALR, just 2.
3088
3089Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3090
3091 * interp.c: Correct some HASFPU problems.
3092
3093Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3094
3095 * configure: Regenerated to track ../common/aclocal.m4 changes.
3096
3097Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3098
3099 * interp.c (mips_options): Fix samples option short form, should
3100 be `x'.
3101
3102Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3103
3104 * interp.c (sim_info): Enable info code. Was just returning.
3105
3106Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3107
3108 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3109 MFC0.
3110
3111Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3112
3113 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3114 constants.
3115 (build_instruction): Ditto for LL.
3116
3117Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3118
3119 * configure: Regenerated to track ../common/aclocal.m4 changes.
3120
3121Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3122
3123 * configure: Regenerated to track ../common/aclocal.m4 changes.
3124 * config.in: Ditto.
3125
3126Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3127
3128 * interp.c (sim_open): Add call to sim_analyze_program, update
3129 call to sim_config.
3130
3131Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3132
3133 * interp.c (sim_kill): Delete.
3134 (sim_create_inferior): Add ABFD argument. Set PC from same.
3135 (sim_load): Move code initializing trap handlers from here.
3136 (sim_open): To here.
3137 (sim_load): Delete, use sim-hload.c.
3138
3139 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3140
3141Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3142
3143 * configure: Regenerated to track ../common/aclocal.m4 changes.
3144 * config.in: Ditto.
3145
3146Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3147
3148 * interp.c (sim_open): Add ABFD argument.
3149 (sim_load): Move call to sim_config from here.
3150 (sim_open): To here. Check return status.
3151
3152Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3153
c906108c
SS		 3154 * gencode.c (build_instruction): Two arg MADD should
3155 not assign result to $0.
72f4393d 3156
c906108c
SS		 3157Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3158
3159 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3160 * sim/mips/configure.in: Regenerate.
3161
3162Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3163
3164 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3165 signed8, unsigned8 et.al. types.
3166
3167 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3168 hosts when selecting subreg.
3169
3170Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3171
3172 * interp.c (sim_engine_run): Reset the ZERO register to zero
3173 regardless of FEATURE_WARN_ZERO.
3174 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3175
3176Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3177
3178 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3179 (SignalException): For BreakPoints ignore any mode bits and just
3180 save the PC.
3181 (SignalException): Always set the CAUSE register.
3182
3183Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3184
3185 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3186 exception has been taken.
3187
3188 * interp.c: Implement the ERET and mt/f sr instructions.
3189
3190Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3191
3192 * interp.c (SignalException): Don't bother restarting an
3193 interrupt.
3194
3195Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3196
3197 * interp.c (SignalException): Really take an interrupt.
3198 (interrupt_event): Only deliver interrupts when enabled.
3199
3200Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3201
3202 * interp.c (sim_info): Only print info when verbose.
3203 (sim_info) Use sim_io_printf for output.
72f4393d 3204
c906108c
SS		 3205Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3206
3207 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3208 mips architectures.
3209
3210Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3211
3212 * interp.c (sim_do_command): Check for common commands if a
3213 simulator specific command fails.
3214
3215Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3216
3217 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3218 and simBE when DEBUG is defined.
3219
3220Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3221
3222 * interp.c (interrupt_event): New function. Pass exception event
3223 onto exception handler.
3224
3225 * configure.in: Check for stdlib.h.
3226 * configure: Regenerate.
3227
3228 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3229 variable declaration.
3230 (build_instruction): Initialize memval1.
3231 (build_instruction): Add UNUSED attribute to byte, bigend,
3232 reverse.
3233 (build_operands): Ditto.
3234
3235 * interp.c: Fix GCC warnings.
3236 (sim_get_quit_code): Delete.
3237
3238 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3239 * Makefile.in: Ditto.
3240 * configure: Re-generate.
72f4393d 3241
c906108c
SS		 3242 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3243
3244Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3245
3246 * interp.c (mips_option_handler): New function parse argumes using
3247 sim-options.
3248 (myname): Replace with STATE_MY_NAME.
3249 (sim_open): Delete check for host endianness - performed by
3250 sim_config.
3251 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3252 (sim_open): Move much of the initialization from here.
3253 (sim_load): To here. After the image has been loaded and
3254 endianness set.
3255 (sim_open): Move ColdReset from here.
3256 (sim_create_inferior): To here.
3257 (sim_open): Make FP check less dependant on host endianness.
3258
3259 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3260 run.
3261 * interp.c (sim_set_callbacks): Delete.
3262
3263 * interp.c (membank, membank_base, membank_size): Replace with
3264 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3265 (sim_open): Remove call to callback->init. gdb/run do this.
3266
3267 * interp.c: Update
3268
3269 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3270
3271 * interp.c (big_endian_p): Delete, replaced by
3272 current_target_byte_order.
3273
3274Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3275
3276 * interp.c (host_read_long, host_read_word, host_swap_word,
3277 host_swap_long): Delete. Using common sim-endian.
3278 (sim_fetch_register, sim_store_register): Use H2T.
3279 (pipeline_ticks): Delete. Handled by sim-events.
3280 (sim_info): Update.
3281 (sim_engine_run): Update.
3282
3283Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3284
3285 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3286 reason from here.
3287 (SignalException): To here. Signal using sim_engine_halt.
3288 (sim_stop_reason): Delete, moved to common.
72f4393d 3289
c906108c
SS		 3290Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3291
3292 * interp.c (sim_open): Add callback argument.
3293 (sim_set_callbacks): Delete SIM_DESC argument.
3294 (sim_size): Ditto.
3295
3296Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3297
3298 * Makefile.in (SIM_OBJS): Add common modules.
3299
3300 * interp.c (sim_set_callbacks): Also set SD callback.
3301 (set_endianness, xfer_*, swap_*): Delete.
3302 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3303 Change to functions using sim-endian macros.
3304 (control_c, sim_stop): Delete, use common version.
3305 (simulate): Convert into.
3306 (sim_engine_run): This function.
3307 (sim_resume): Delete.
72f4393d 3308
c906108c
SS		 3309 * interp.c (simulation): New variable - the simulator object.
3310 (sim_kind): Delete global - merged into simulation.
3311 (sim_load): Cleanup. Move PC assignment from here.
3312 (sim_create_inferior): To here.
3313
3314 * sim-main.h: New file.
3315 * interp.c (sim-main.h): Include.
72f4393d 3316
c906108c
SS		 3317Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3318
3319 * configure: Regenerated to track ../common/aclocal.m4 changes.
3320
3321Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3322
3323 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3324
3325Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3326
72f4393d
L		 3327 * gencode.c (build_instruction): DIV instructions: check
3328 for division by zero and integer overflow before using
c906108c
SS		 3329 host's division operation.
3330
3331Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3332
3333 * Makefile.in (SIM_OBJS): Add sim-load.o.
3334 * interp.c: #include bfd.h.
3335 (target_byte_order): Delete.
3336 (sim_kind, myname, big_endian_p): New static locals.
3337 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3338 after argument parsing. Recognize -E arg, set endianness accordingly.
3339 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3340 load file into simulator. Set PC from bfd.
3341 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3342 (set_endianness): Use big_endian_p instead of target_byte_order.
3343
3344Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3345
3346 * interp.c (sim_size): Delete prototype - conflicts with
3347 definition in remote-sim.h. Correct definition.
3348
3349Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3350
3351 * configure: Regenerated to track ../common/aclocal.m4 changes.
3352 * config.in: Ditto.
3353
3354Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3355
3356 * interp.c (sim_open): New arg `kind'.
3357
3358 * configure: Regenerated to track ../common/aclocal.m4 changes.
3359
3360Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3361
3362 * configure: Regenerated to track ../common/aclocal.m4 changes.
3363
3364Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3365
3366 * interp.c (sim_open): Set optind to 0 before calling getopt.
3367
3368Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3369
3370 * configure: Regenerated to track ../common/aclocal.m4 changes.
3371
3372Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3373
3374 * interp.c : Replace uses of pr_addr with pr_uword64
3375 where the bit length is always 64 independent of SIM_ADDR.
3376 (pr_uword64) : added.
3377
3378Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3379
3380 * configure: Re-generate.
3381
3382Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3383
3384 * configure: Regenerate to track ../common/aclocal.m4 changes.
3385
3386Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3387
3388 * interp.c (sim_open): New SIM_DESC result. Argument is now
3389 in argv form.
3390 (other sim_*): New SIM_DESC argument.
3391
3392Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3393
3394 * interp.c: Fix printing of addresses for non-64-bit targets.
3395 (pr_addr): Add function to print address based on size.
3396
3397Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3398
3399 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3400
3401Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3402
3403 * gencode.c (build_mips16_operands): Correct computation of base
3404 address for extended PC relative instruction.
3405
3406Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3407
3408 * interp.c (mips16_entry): Add support for floating point cases.
3409 (SignalException): Pass floating point cases to mips16_entry.
3410 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3411 registers.
3412 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3413 or fmt_word.
3414 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3415 and then set the state to fmt_uninterpreted.
3416 (COP_SW): Temporarily set the state to fmt_word while calling
3417 ValueFPR.
3418
3419Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3420
3421 * gencode.c (build_instruction): The high order may be set in the
3422 comparison flags at any ISA level, not just ISA 4.
3423
3424Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3425
3426 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3427 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3428 * configure.in: sinclude ../common/aclocal.m4.
3429 * configure: Regenerated.
3430
3431Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3432
3433 * configure: Rebuild after change to aclocal.m4.
3434
3435Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3436
3437 * configure configure.in Makefile.in: Update to new configure
3438 scheme which is more compatible with WinGDB builds.
3439 * configure.in: Improve comment on how to run autoconf.
3440 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3441 * Makefile.in: Use autoconf substitution to install common
3442 makefile fragment.
3443
3444Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3445
3446 * gencode.c (build_instruction): Use BigEndianCPU instead of
3447 ByteSwapMem.
3448
3449Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3450
3451 * interp.c (sim_monitor): Make output to stdout visible in
3452 wingdb's I/O log window.
3453
3454Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3455
3456 * support.h: Undo previous change to SIGTRAP
3457 and SIGQUIT values.
3458
3459Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3460
3461 * interp.c (store_word, load_word): New static functions.
3462 (mips16_entry): New static function.
3463 (SignalException): Look for mips16 entry and exit instructions.
3464 (simulate): Use the correct index when setting fpr_state after
3465 doing a pending move.
3466
3467Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3468
3469 * interp.c: Fix byte-swapping code throughout to work on
3470 both little- and big-endian hosts.
3471
3472Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3473
3474 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3475 with gdb/config/i386/xm-windows.h.
3476
3477Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3478
3479 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3480 that messes up arithmetic shifts.
3481
3482Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3483
3484 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3485 SIGTRAP and SIGQUIT for _WIN32.
3486
3487Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3488
3489 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3490 force a 64 bit multiplication.
3491 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3492 destination register is 0, since that is the default mips16 nop
3493 instruction.
3494
3495Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3496
3497 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3498 (build_endian_shift): Don't check proc64.
3499 (build_instruction): Always set memval to uword64. Cast op2 to
3500 uword64 when shifting it left in memory instructions. Always use
3501 the same code for stores--don't special case proc64.
3502
3503 * gencode.c (build_mips16_operands): Fix base PC value for PC
3504 relative operands.
3505 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3506 jal instruction.
3507 * interp.c (simJALDELAYSLOT): Define.
3508 (JALDELAYSLOT): Define.
3509 (INDELAYSLOT, INJALDELAYSLOT): Define.
3510 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3511
3512Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3513
3514 * interp.c (sim_open): add flush_cache as a PMON routine
3515 (sim_monitor): handle flush_cache by ignoring it
3516
3517Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3518
3519 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3520 BigEndianMem.
3521 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3522 (BigEndianMem): Rename to ByteSwapMem and change sense.
3523 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3524 BigEndianMem references to !ByteSwapMem.
3525 (set_endianness): New function, with prototype.
3526 (sim_open): Call set_endianness.
3527 (sim_info): Use simBE instead of BigEndianMem.
3528 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3529 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3530 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3531 ifdefs, keeping the prototype declaration.
3532 (swap_word): Rewrite correctly.
3533 (ColdReset): Delete references to CONFIG. Delete endianness related
3534 code; moved to set_endianness.
72f4393d 3535
c906108c
SS		 3536Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3537
3538 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3539 * interp.c (CHECKHILO): Define away.
3540 (simSIGINT): New macro.
3541 (membank_size): Increase from 1MB to 2MB.
3542 (control_c): New function.
3543 (sim_resume): Rename parameter signal to signal_number. Add local
3544 variable prev. Call signal before and after simulate.
3545 (sim_stop_reason): Add simSIGINT support.
3546 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3547 functions always.
3548 (sim_warning): Delete call to SignalException. Do call printf_filtered
3549 if logfh is NULL.
3550 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3551 a call to sim_warning.
3552
3553Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3554
3555 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3556 16 bit instructions.
3557
3558Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3559
3560 Add support for mips16 (16 bit MIPS implementation):
3561 * gencode.c (inst_type): Add mips16 instruction encoding types.
3562 (GETDATASIZEINSN): Define.
3563 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3564 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3565 mtlo.
3566 (MIPS16_DECODE): New table, for mips16 instructions.
3567 (bitmap_val): New static function.
3568 (struct mips16_op): Define.
3569 (mips16_op_table): New table, for mips16 operands.
3570 (build_mips16_operands): New static function.
3571 (process_instructions): If PC is odd, decode a mips16
3572 instruction. Break out instruction handling into new
3573 build_instruction function.
3574 (build_instruction): New static function, broken out of
3575 process_instructions. Check modifiers rather than flags for SHIFT
3576 bit count and m[ft]{hi,lo} direction.
3577 (usage): Pass program name to fprintf.
3578 (main): Remove unused variable this_option_optind. Change
3579 ``*loptarg++'' to ``loptarg++''.
3580 (my_strtoul): Parenthesize && within ||.
3581 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3582 (simulate): If PC is odd, fetch a 16 bit instruction, and
3583 increment PC by 2 rather than 4.
3584 * configure.in: Add case for mips16*-*-*.
3585 * configure: Rebuild.
3586
3587Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3588
3589 * interp.c: Allow -t to enable tracing in standalone simulator.
3590 Fix garbage output in trace file and error messages.
3591
3592Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3593
3594 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3595 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3596 * configure.in: Simplify using macros in ../common/aclocal.m4.
3597 * configure: Regenerated.
3598 * tconfig.in: New file.
3599
3600Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3601
3602 * interp.c: Fix bugs in 64-bit port.
3603 Use ansi function declarations for msvc compiler.
3604 Initialize and test file pointer in trace code.
3605 Prevent duplicate definition of LAST_EMED_REGNUM.
3606
3607Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3608
3609 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3610
3611Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3612
3613 * interp.c (SignalException): Check for explicit terminating
3614 breakpoint value.
3615 * gencode.c: Pass instruction value through SignalException()
3616 calls for Trap, Breakpoint and Syscall.
3617
3618Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3619
3620 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3621 only used on those hosts that provide it.
3622 * configure.in: Add sqrt() to list of functions to be checked for.
3623 * config.in: Re-generated.
3624 * configure: Re-generated.
3625
3626Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3627
3628 * gencode.c (process_instructions): Call build_endian_shift when
3629 expanding STORE RIGHT, to fix swr.
3630 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3631 clear the high bits.
3632 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3633 Fix float to int conversions to produce signed values.
3634
3635Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3636
3637 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3638 (process_instructions): Correct handling of nor instruction.
3639 Correct shift count for 32 bit shift instructions. Correct sign
3640 extension for arithmetic shifts to not shift the number of bits in
3641 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3642 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3643 Fix madd.
3644 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3645 It's OK to have a mult follow a mult. What's not OK is to have a
3646 mult follow an mfhi.
3647 (Convert): Comment out incorrect rounding code.
3648
3649Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3650
3651 * interp.c (sim_monitor): Improved monitor printf
3652 simulation. Tidied up simulator warnings, and added "--log" option
3653 for directing warning message output.
3654 * gencode.c: Use sim_warning() rather than WARNING macro.
3655
3656Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3657
3658 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3659 getopt1.o, rather than on gencode.c. Link objects together.
3660 Don't link against -liberty.
3661 (gencode.o, getopt.o, getopt1.o): New targets.
3662 * gencode.c: Include <ctype.h> and "ansidecl.h".
3663 (AND): Undefine after including "ansidecl.h".
3664 (ULONG_MAX): Define if not defined.
3665 (OP_*): Don't define macros; now defined in opcode/mips.h.
3666 (main): Call my_strtoul rather than strtoul.
3667 (my_strtoul): New static function.
3668
3669Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3670
3671 * gencode.c (process_instructions): Generate word64 and uword64
3672 instead of `long long' and `unsigned long long' data types.
3673 * interp.c: #include sysdep.h to get signals, and define default
3674 for SIGBUS.
3675 * (Convert): Work around for Visual-C++ compiler bug with type
3676 conversion.
3677 * support.h: Make things compile under Visual-C++ by using
3678 __int64 instead of `long long'. Change many refs to long long
3679 into word64/uword64 typedefs.
3680
3681Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3682
72f4393d
L		 3683 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3684 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3685 (docdir): Removed.
3686 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3687 (AC_PROG_INSTALL): Added.
c906108c 3688 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3689 * configure: Rebuilt.
3690
c906108c
SS		 3691Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3692
3693 * configure.in: Define @SIMCONF@ depending on mips target.
3694 * configure: Rebuild.
3695 * Makefile.in (run): Add @SIMCONF@ to control simulator
3696 construction.
3697 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3698 * interp.c: Remove some debugging, provide more detailed error
3699 messages, update memory accesses to use LOADDRMASK.
72f4393d 3700
c906108c
SS		 3701Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3702
3703 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3704 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3705 stamp-h.
3706 * configure: Rebuild.
3707 * config.in: New file, generated by autoheader.
3708 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3709 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3710 HAVE_ANINT and HAVE_AINT, as appropriate.
3711 * Makefile.in (run): Use @LIBS@ rather than -lm.
3712 (interp.o): Depend upon config.h.
3713 (Makefile): Just rebuild Makefile.
3714 (clean): Remove stamp-h.
3715 (mostlyclean): Make the same as clean, not as distclean.
3716 (config.h, stamp-h): New targets.
3717
3718Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3719
3720 * interp.c (ColdReset): Fix boolean test. Make all simulator
3721 globals static.
3722
3723Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3724
3725 * interp.c (xfer_direct_word, xfer_direct_long,
3726 swap_direct_word, swap_direct_long, xfer_big_word,
3727 xfer_big_long, xfer_little_word, xfer_little_long,
3728 swap_word,swap_long): Added.
3729 * interp.c (ColdReset): Provide function indirection to
3730 host<->simulated_target transfer routines.
3731 * interp.c (sim_store_register, sim_fetch_register): Updated to
3732 make use of indirected transfer routines.
3733
3734Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3735
3736 * gencode.c (process_instructions): Ensure FP ABS instruction
3737 recognised.
3738 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3739 system call support.
3740
3741Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3742
3743 * interp.c (sim_do_command): Complain if callback structure not
3744 initialised.
3745
3746Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3747
3748 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3749 support for Sun hosts.
3750 * Makefile.in (gencode): Ensure the host compiler and libraries
3751 used for cross-hosted build.
3752
3753Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3754
3755 * interp.c, gencode.c: Some more (TODO) tidying.
3756
3757Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3758
3759 * gencode.c, interp.c: Replaced explicit long long references with
3760 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3761 * support.h (SET64LO, SET64HI): Macros added.
3762
3763Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3764
3765 * configure: Regenerate with autoconf 2.7.
3766
3767Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3768
3769 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3770 * support.h: Remove superfluous "1" from #if.
3771 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3772
3773Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3774
3775 * interp.c (StoreFPR): Control UndefinedResult() call on
3776 WARN_RESULT manifest.
3777
3778Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3779
3780 * gencode.c: Tidied instruction decoding, and added FP instruction
3781 support.
3782
3783 * interp.c: Added dineroIII, and BSD profiling support. Also
3784 run-time FP handling.
3785
3786Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3787
3788 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3789 gencode.c, interp.c, support.h: created.
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