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sim: mips: fix prog_bfd usage
[thirdparty/binutils-gdb.git] / sim / mips / ChangeLog
CommitLineData
1554f758
MF		 12016-02-05 Mike Frysinger <vapier@gentoo.org>
2
3 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to
4 STATE_PROG_BFD (sd).
5 * configure: Regenerate.
6
3d304f48
AB		 72016-01-18 Andrew Bennett <andrew.bennett@imgtec.com>
8 Maciej W. Rozycki <macro@imgtec.com>
9
10 PR sim/19441
11 * micromips.igen (delayslot_micromips): Enable for `micromips32',
12 `micromips64' and `micromipsdsp' only.
13 (process_isa_mode): Enable for `micromips32' and `micromips64' only.
14 (do_micromips_jalr, do_micromips_jal): Likewise.
15 (compute_movep_src_reg): Likewise.
16 (compute_andi16_imm): Likewise.
17 (convert_fmt_micromips): Likewise.
18 (convert_fmt_micromips_cvt_d): Likewise.
19 (convert_fmt_micromips_cvt_s): Likewise.
20 (FMT_MICROMIPS): Likewise.
21 (FMT_MICROMIPS_CVT_D): Likewise.
22 (FMT_MICROMIPS_CVT_S): Likewise.
23
b36d953b
MF		 242016-01-12 Mike Frysinger <vapier@gentoo.org>
25
26 * interp.c: Include elf-bfd.h.
27 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is
28 ELFCLASS32.
29
ce39bd38
MF		 302016-01-10 Mike Frysinger <vapier@gentoo.org>
31
32 * config.in, configure: Regenerate.
33
99d8e879
MF		 342016-01-10 Mike Frysinger <vapier@gentoo.org>
35
36 * configure: Regenerate.
37
35656e95
MF		 382016-01-10 Mike Frysinger <vapier@gentoo.org>
39
40 * configure: Regenerate.
41
16f7876d
MF		 422016-01-10 Mike Frysinger <vapier@gentoo.org>
43
44 * configure: Regenerate.
45
e19418e0
MF		 462016-01-10 Mike Frysinger <vapier@gentoo.org>
47
48 * configure: Regenerate.
49
6d90347b
MF		 502016-01-10 Mike Frysinger <vapier@gentoo.org>
51
52 * configure.ac (SIM_AC_OPTION_SMP): Delete call.
53 * configure: Regenerate.
54
347fe5bb
MF		 552016-01-10 Mike Frysinger <vapier@gentoo.org>
56
57 * configure.ac (SIM_AC_OPTION_INLINE): Delete call.
58 * configure: Regenerate.
59
22be3fbe
MF		 602016-01-10 Mike Frysinger <vapier@gentoo.org>
61
62 * configure: Regenerate.
63
0dc73ef7
MF		 642016-01-10 Mike Frysinger <vapier@gentoo.org>
65
66 * configure: Regenerate.
67
936df756
MF		 682016-01-09 Mike Frysinger <vapier@gentoo.org>
69
70 * config.in, configure: Regenerate.
71
2e3d4f4d
MF		 722016-01-06 Mike Frysinger <vapier@gentoo.org>
73
74 * interp.c (sim_open): Mark argv const.
75 (sim_create_inferior): Mark argv and env const.
76
9bbf6f91
MF		 772016-01-04 Mike Frysinger <vapier@gentoo.org>
78
79 * configure: Regenerate.
80
77cf2ef5
MF		 812016-01-03 Mike Frysinger <vapier@gentoo.org>
82
83 * interp.c (sim_open): Update sim_parse_args comment.
84
0cb8d851
MF		 852016-01-03 Mike Frysinger <vapier@gentoo.org>
86
87 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete.
88 * configure: Regenerate.
89
1ac72f06
MF		 902016-01-02 Mike Frysinger <vapier@gentoo.org>
91
92 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE.
93 (default_endian): Likewise. Change BIG_ENDIAN to BIG.
94 * configure: Regenerate.
95 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG.
96
d47f5b30
MF		 972016-01-02 Mike Frysinger <vapier@gentoo.org>
98
99 * dv-tx3904cpu.c (CPU, SD): Delete.
100
e1211e55
MF		 1012015-12-30 Mike Frysinger <vapier@gentoo.org>
102
103 * wrapper.c (mips_reg_store, mips_reg_fetch): Define.
104 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE.
105 (sim_store_register): Rename to ...
106 (mips_reg_store): ... this. Delete local cpu var.
107 Update sim_io_eprintf calls.
108 (sim_fetch_register): Rename to ...
109 (mips_reg_fetch): ... this. Delete local cpu var.
110 Update sim_io_eprintf calls.
111
5e744ef8
MF		 1122015-12-27 Mike Frysinger <vapier@gentoo.org>
113
114 * Makefile.in (SIM_OBJS): Delete sim-hload.o.
115
1b393626
MF		 1162015-12-26 Mike Frysinger <vapier@gentoo.org>
117
118 * config.in, configure: Regenerate.
119
26f8bf63
MF		 1202015-12-26 Mike Frysinger <vapier@gentoo.org>
121
122 * interp.c (sim_write, sim_read): Delete.
123 (store_word): Delete call to AddressTranslation and set paddr=vaddr.
124 (load_word): Likewise.
125 * micromips.igen (cache): Likewise.
126 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
127 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
128 do_store_left, do_store_right, do_load_double, do_store_double):
129 Likewise.
130 (do_pref): Delete call to AddressTranslation and stub out Prefetch.
131 (do_prefx): Likewise.
132 * sim-main.c (address_translation, prefetch): Delete.
133 (ifetch32, ifetch16): Delete call to AddressTranslation and set
134 paddr=vaddr.
135 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
136 address_translation, AddressTranslation, prefetch, Prefetch): Delete.
137 (LoadMemory, StoreMemory): Delete CCA arg.
138
ef04e371
MF		 1392015-12-24 Mike Frysinger <vapier@gentoo.org>
140
141 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.
142 * configure: Regenerated.
143
cb379ede
MF		 1442015-12-24 Mike Frysinger <vapier@gentoo.org>
145
146 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h.
147 * tconfig.h: Delete.
148
26936211
MF		 1492015-12-24 Mike Frysinger <vapier@gentoo.org>
150
151 * tconfig.h (SIM_HANDLES_LMA): Delete.
152
84e8e361
MF		 1532015-12-24 Mike Frysinger <vapier@gentoo.org>
154
155 * sim-main.h (WITH_WATCHPOINTS): Delete.
156
3cabaf66
MF		 1572015-12-24 Mike Frysinger <vapier@gentoo.org>
158
159 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code.
160
8abe6c66
MF		 1612015-12-24 Mike Frysinger <vapier@gentoo.org>
162
163 * tconfig.h (SIM_HAVE_SIMCACHE): Delete.
164
1d19cae7
DV		 1652015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com>
166
167 * micromips.igen (process_isa_mode): Fix left shift of negative
168 value.
169
cdf850e9
MF		 1702015-11-17 Mike Frysinger <vapier@gentoo.org>
171
172 * sim-main.h (WITH_MODULO_MEMORY): Delete.
173
797eee42
MF		 1742015-11-15 Mike Frysinger <vapier@gentoo.org>
175
176 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o.
177
6e4f085c
MF		 1782015-11-14 Mike Frysinger <vapier@gentoo.org>
179
180 * interp.c (sim_close): Rename to ...
181 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and
182 sim_io_shutdown.
183 * sim-main.h (mips_sim_close): Declare.
184 (SIM_CLOSE_HOOK): Define.
185
8e394ffc
AB		 1862015-09-25 Andrew Bennett <andrew.bennett@imgtec.com>
187 Ali Lown <ali.lown@imgtec.com>
188
189 * Makefile.in (tmp-micromips): New rule.
190 (tmp-mach-multi): Add support for micromips.
191 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim
192 that works for both mips64 and micromips64.
193 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and
194 micromips32.
195 Add build support for micromips.
196 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc,
197 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv,
198 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick
199 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq
200 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu,
201 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv,
202 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append,
203 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions.
204 Refactored instruction code to use these functions.
205 * dsp2.igen: Refactored instruction code to use the new functions.
206 * interp.c (decode_coproc): Refactored to work with any instruction
207 encoding.
208 (isa_mode): New variable
209 (RSVD_INSTRUCTION): Changed to 0x00000039.
210 * m16.igen (BREAK16): Refactored instruction to use do_break16.
211 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models.
212 * micromips.dc: New file.
213 * micromips.igen: New file.
214 * micromips16.dc: New file.
215 * micromipsdsp.igen: New file.
216 * micromipsrun.c: New file.
217 * mips.igen (do_swc1): Changed to work with any instruction encoding.
218 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32
219 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo,
220 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu,
221 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu,
222 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub,
223 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo,
224 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc,
225 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu,
226 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt,
227 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1,
228 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl,
229 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt,
230 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b,
231 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt,
232 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps,
233 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt,
234 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt,
235 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing
236 instructions.
237 Refactored instruction code to use these functions.
238 (RSVD): Changed to use new reserved instruction.
239 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo,
240 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32,
241 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double,
242 do_store_double): Added micromips32 and micromips64 models.
243 Added include for micromips.igen and micromipsdsp.igen
244 Add micromips32 and micromips64 models.
245 (DecodeCoproc): Updated to use new macro definition.
246 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di,
247 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu,
248 do_seb, do_seh do_rdhwr, do_wsbh): New functions.
249 Refactored instruction code to use these functions.
250 * sim-main.h (CP0_operation): New enum.
251 (DecodeCoproc): Updated macro.
252 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE,
253 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16,
254 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and
255 ISA_MODE_MICROMIPS): New defines.
256 (sim_state): Add isa_mode field.
257
8d0978fb
MF		 2582015-06-23 Mike Frysinger <vapier@gentoo.org>
259
260 * configure: Regenerate.
261
306f4178
MF		 2622015-06-12 Mike Frysinger <vapier@gentoo.org>
263
264 * configure.ac: Change configure.in to configure.ac.
265 * configure: Regenerate.
266
a3487082
MF		 2672015-06-12 Mike Frysinger <vapier@gentoo.org>
268
269 * configure: Regenerate.
270
29bc024d
MF		 2712015-06-12 Mike Frysinger <vapier@gentoo.org>
272
273 * interp.c [TRACE]: Delete.
274 (TRACE): Change to WITH_TRACE_ANY_P.
275 [!WITH_TRACE_ANY_P] (open_trace): Define.
276 (mips_option_handler, open_trace, sim_close, dotrace):
277 Change defined(TRACE) to WITH_TRACE_ANY_P.
278 (sim_open): Delete TRACE ifdef check.
279 * sim-main.c (load_memory): Delete TRACE ifdef check.
280 (store_memory): Likewise.
281 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls.
282 [!WITH_TRACE_ANY_P] (dotrace): Define.
283
3ebe2863
MF		 2842015-04-18 Mike Frysinger <vapier@gentoo.org>
285
286 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete
287 comments.
288
20bca71d
MF		 2892015-04-18 Mike Frysinger <vapier@gentoo.org>
290
291 * sim-main.h (SIM_CPU): Delete.
292
7e83aa92
MF		 2932015-04-18 Mike Frysinger <vapier@gentoo.org>
294
295 * sim-main.h (sim_cia): Delete.
296
034685f9
MF		 2972015-04-17 Mike Frysinger <vapier@gentoo.org>
298
299 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to
300 PU_PC_GET.
301 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET.
302 (sim_create_inferior): Change CIA_SET to CPU_PC_SET.
303 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and
304 CIA_SET to CPU_PC_SET.
305 * sim-main.h (CIA_GET, CIA_SET): Delete.
306
78e9aa70
MF		 3072015-04-15 Mike Frysinger <vapier@gentoo.org>
308
309 * Makefile.in (SIM_OBJS): Delete sim-cpu.o.
310 * sim-main.h (STATE_CPU): Delete.
311
bf12d44e
MF		 3122015-04-13 Mike Frysinger <vapier@gentoo.org>
313
314 * configure: Regenerate.
315
7bebb329
MF		 3162015-04-13 Mike Frysinger <vapier@gentoo.org>
317
318 * Makefile.in (SIM_OBJS): Add sim-cpu.o.
319 * interp.c (mips_pc_get, mips_pc_set): New functions.
320 (sim_open): Declare new local var i. Call sim_cpu_alloc_all.
321 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus.
322 (sim_pc_get): Delete.
323 * sim-main.h (SIM_CPU): Define.
324 (struct sim_state): Change cpu to an array of pointers.
325 (STATE_CPU): Drop &.
326
8ac57fbd
MF		 3272015-04-13 Mike Frysinger <vapier@gentoo.org>
328
329 * interp.c (mips_option_handler, open_trace, sim_close,
330 sim_write, sim_read, sim_store_register, sim_fetch_register,
331 sim_create_inferior, pr_addr, pr_uword64): Convert old style
332 prototypes.
333 (sim_open): Convert old style prototype. Change casts with
334 sim_write to unsigned char *.
335 (fetch_str): Change null to unsigned char, and change cast to
336 unsigned char *.
337 (sim_monitor): Change c & ch to unsigned char. Change cast to
338 unsigned char *.
339
e787f858
MF		 3402015-04-12 Mike Frysinger <vapier@gentoo.org>
341
342 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list.
343
122bbfb5
MF		 3442015-04-06 Mike Frysinger <vapier@gentoo.org>
345
346 * Makefile.in (SIM_OBJS): Delete sim-engine.o.
347
0fe84f3f
MF		 3482015-04-01 Mike Frysinger <vapier@gentoo.org>
349
350 * tconfig.h (SIM_HAVE_PROFILE): Delete.
351
aadc9410
MF		 3522015-03-31 Mike Frysinger <vapier@gentoo.org>
353
354 * config.in, configure: Regenerate.
355
05f53ed6
MF		 3562015-03-24 Mike Frysinger <vapier@gentoo.org>
357
358 * interp.c (sim_pc_get): New function.
359
c0931f26
MF		 3602015-03-24 Mike Frysinger <vapier@gentoo.org>
361
362 * sim-main.h (SIM_HAVE_BIENDIAN): Delete.
363 * tconfig.h (SIM_HAVE_BIENDIAN): Delete.
364
30452bbe
MF		 3652015-03-24 Mike Frysinger <vapier@gentoo.org>
366
367 * configure: Regenerate.
368
64dd13df
MF		 3692015-03-23 Mike Frysinger <vapier@gentoo.org>
370
371 * configure: Regenerate.
372
49cd1634
MF		 3732015-03-23 Mike Frysinger <vapier@gentoo.org>
374
375 * configure: Regenerate.
376 * configure.ac (mips_extra_objs): Delete.
377 * Makefile.in (MIPS_EXTRA_OBJS): Delete.
378 (SIM_OBJS): Delete MIPS_EXTRA_OBJS.
379
3649cb06
MF		 3802015-03-23 Mike Frysinger <vapier@gentoo.org>
381
382 * configure: Regenerate.
383 * configure.ac: Delete sim_hw checks for dv-sockser.
384
ae7d0cac
MF		 3852015-03-16 Mike Frysinger <vapier@gentoo.org>
386
387 * config.in, configure: Regenerate.
388 * tconfig.in: Rename file ...
389 * tconfig.h: ... here.
390
8406bb59
MF		 3912015-03-15 Mike Frysinger <vapier@gentoo.org>
392
393 * tconfig.in: Delete includes.
394 [HAVE_DV_SOCKSER]: Delete.
395
465fb143
MF		 3962015-03-14 Mike Frysinger <vapier@gentoo.org>
397
398 * Makefile.in (SIM_RUN_OBJS): Delete.
399
5cddc23a
MF		 4002015-03-14 Mike Frysinger <vapier@gentoo.org>
401
402 * configure.ac (AC_CHECK_HEADERS): Delete.
403 * aclocal.m4, configure: Regenerate.
404
2974be62
AM		 4052014-08-19 Alan Modra <amodra@gmail.com>
406
407 * configure: Regenerate.
408
faa743bb
RM		 4092014-08-15 Roland McGrath <mcgrathr@google.com>
410
411 * configure: Regenerate.
412 * config.in: Regenerate.
413
1a8a700e
MF		 4142014-03-04 Mike Frysinger <vapier@gentoo.org>
415
416 * configure: Regenerate.
417
bf3d9781
AM		 4182013-09-23 Alan Modra <amodra@gmail.com>
419
420 * configure: Regenerate.
421
31e6ad7d
MF		 4222013-06-03 Mike Frysinger <vapier@gentoo.org>
423
424 * aclocal.m4, configure: Regenerate.
425
d3685d60
TT		 4262013-05-10 Freddie Chopin <freddie_chopin@op.pl>
427
428 * configure: Rebuild.
429
1517bd27
MF		 4302013-03-26 Mike Frysinger <vapier@gentoo.org>
431
432 * configure: Regenerate.
433
3be31516
JS		 4342013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com>
435
436 * configure.ac: Address use of dv-sockser.o.
437 * tconfig.in: Conditionalize use of dv_sockser_install.
438 * configure: Regenerated.
439 * config.in: Regenerated.
440
37cb8f8e
SE		 4412012-10-04 Chao-ying Fu <fu@mips.com>
442 Steve Ellcey <sellcey@mips.com>
443
444 * mips/mips3264r2.igen (rdhwr): New.
445
87c8644f
JS		 4462012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com>
447
448 * configure.ac: Always link against dv-sockser.o.
449 * configure: Regenerate.
450
5f3ef9d0
JB		 4512012-06-15 Joel Brobecker <brobecker@adacore.com>
452
453 * config.in, configure: Regenerate.
454
a6ff997c
NC		 4552012-05-18 Nick Clifton <nickc@redhat.com>
456
457 PR 14072
458 * interp.c: Include config.h before system header files.
459
2232061b
MF		 4602012-03-24 Mike Frysinger <vapier@gentoo.org>
461
462 * aclocal.m4, config.in, configure: Regenerate.
463
db2e4d67
MF		 4642011-12-03 Mike Frysinger <vapier@gentoo.org>
465
466 * aclocal.m4: New file.
467 * configure: Regenerate.
468
4399a56b
MF		 4692011-10-19 Mike Frysinger <vapier@gentoo.org>
470
471 * configure: Regenerate after common/acinclude.m4 update.
472
9c082ca8
MF		 4732011-10-17 Mike Frysinger <vapier@gentoo.org>
474
475 * configure.ac: Change include to common/acinclude.m4.
476
6ffe910a
MF		 4772011-10-17 Mike Frysinger <vapier@gentoo.org>
478
479 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER
480 call. Replace common.m4 include with SIM_AC_COMMON.
481 * configure: Regenerate.
482
31b28250
HPN		 4832011-07-08 Hans-Peter Nilsson <hp@axis.com>
484
3faa01e3
HPN		 485 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h
486 $(SIM_EXTRA_DEPS).
487 (tmp-mach-multi): Exit early when igen fails.
31b28250 488
2419798b
MF		 4892011-07-05 Mike Frysinger <vapier@gentoo.org>
490
491 * interp.c (sim_do_command): Delete.
492
d79fe0d6
MF		 4932011-02-14 Mike Frysinger <vapier@gentoo.org>
494
495 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free.
496 (tx3904sio_fifo_reset): Likewise.
497 * interp.c (sim_monitor): Likewise.
498
5558e7e6
MF		 4992010-04-14 Mike Frysinger <vapier@gentoo.org>
500
501 * interp.c (sim_write): Add const to buffer arg.
502
35aafff4
JB		 5032010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change)
504
505 * interp.c: Don't include sysdep.h
506
3725885a
RW		 5072010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
508
509 * configure: Regenerate.
510
d6416cdc
RW		 5112009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
512
81ecdfbb
RW		 513 * config.in: Regenerate.
514 * configure: Likewise.
515
d6416cdc
RW		 516 * configure: Regenerate.
517
b5bd9624
HPN		 5182008-07-11 Hans-Peter Nilsson <hp@axis.com>
519
520 * configure: Regenerate to track ../common/common.m4 changes.
521 * config.in: Ditto.
522
6efef468 5232008-06-06 Vladimir Prus <vladimir@codesourcery.com>
72f4393d
L		 524 Daniel Jacobowitz <dan@codesourcery.com>
525 Joseph Myers <joseph@codesourcery.com>
6efef468
JM		 526
527 * configure: Regenerate.
528
60dc88db
RS		 5292007-10-22 Richard Sandiford <rsandifo@nildram.co.uk>
530
531 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition
532 that unconditionally allows fmt_ps.
533 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
534 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
535 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
536 filter from 64,f to 32,f.
537 (PREFX): Change filter from 64 to 32.
538 (LDXC1, LUXC1): Provide separate mips32r2 implementations
539 that use do_load_double instead of do_load. Make both LUXC1
540 versions unpredictable if SizeFGR () != 64.
541 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double
542 instead of do_store. Remove unused variable. Make both SUXC1
543 versions unpredictable if SizeFGR () != 64.
544
599ca73e
RS		 5452007-10-07 Richard Sandiford <rsandifo@nildram.co.uk>
546
547 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32.
548 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian
549 shifts for that case.
550
2525df03
NC		 5512007-09-04 Nick Clifton <nickc@redhat.com>
552
553 * interp.c (options enum): Add OPTION_INFO_MEMORY.
554 (display_mem_info): New static variable.
555 (mips_option_handler): Handle OPTION_INFO_MEMORY.
556 (mips_options): Add info-memory and memory-info.
557 (sim_open): After processing the command line and board
558 specification, check display_mem_info. If it is set then
559 call the real handler for the --memory-info command line
560 switch.
561
35ee6e1e
JB		 5622007-08-24 Joel Brobecker <brobecker@adacore.com>
563
564 * configure.ac: Change license of multi-run.c to GPL version 3.
565 * configure: Regenerate.
566
d5fb0879
RS		 5672007-06-28 Richard Sandiford <richard@codesourcery.com>
568
569 * configure.ac, configure: Revert last patch.
570
2a2ce21b
RS		 5712007-06-26 Richard Sandiford <richard@codesourcery.com>
572
573 * configure.ac (sim_mipsisa3264_configs): New variable.
574 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
575 every configuration support all four targets, using the triplet to
576 determine the default.
577 * configure: Regenerate.
578
efdcccc9
RS		 5792007-06-25 Richard Sandiford <richard@codesourcery.com>
580
0a7692b2 581 * Makefile.in (m16run.o): New rule.
efdcccc9 582
f532a356
TS		 5832007-05-15 Thiemo Seufer <ths@mips.com>
584
585 * mips3264r2.igen (DSHD): Fix compile warning.
586
bfe9c90b
TS		 5872007-05-14 Thiemo Seufer <ths@mips.com>
588
589 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
590 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
591 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
592 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
593 for mips32r2.
594
53f4826b
TS		 5952007-03-01 Thiemo Seufer <ths@mips.com>
596
597 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
598 and mips64.
599
8bf3ddc8
TS		 6002007-02-20 Thiemo Seufer <ths@mips.com>
601
602 * dsp.igen: Update copyright notice.
603 * dsp2.igen: Fix copyright notice.
604
8b082fb1 6052007-02-20 Thiemo Seufer <ths@mips.com>
72f4393d 606 Chao-Ying Fu <fu@mips.com>
8b082fb1
TS		 607
608 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
609 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
610 Add dsp2 to sim_igen_machine.
611 * configure: Regenerate.
612 * dsp.igen (do_ph_op): Add MUL support when op = 2.
613 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
614 (mulq_rs.ph): Use do_ph_mulq.
615 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
616 * mips.igen: Add dsp2 model and include dsp2.igen.
617 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
618 for *mips32r2, *mips64r2, *dsp.
619 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
620 for *mips32r2, *mips64r2, *dsp2.
621 * dsp2.igen: New file for MIPS DSP REV 2 ASE.
622
b1004875 6232007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 624 Nigel Stephens <nigel@mips.com>
b1004875
TS		 625
626 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
627 jumps with hazard barrier.
628
f8df4c77 6292007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 630 Nigel Stephens <nigel@mips.com>
f8df4c77
TS		 631
632 * interp.c (sim_monitor): Flush stdout and stderr file descriptors
633 after each call to sim_io_write.
634
b1004875 6352007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 636 Nigel Stephens <nigel@mips.com>
b1004875
TS		 637
638 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
639 supported by this simulator.
07802d98
TS		 640 (decode_coproc): Recognise additional CP0 Config registers
641 correctly.
642
14fb6c5a 6432007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d
L		 644 Nigel Stephens <nigel@mips.com>
645 David Ung <davidu@mips.com>
14fb6c5a
TS		 646
647 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
648 uninterpreted formats. If fmt is one of the uninterpreted types
649 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
650 fmt_word, and fmt_uninterpreted_64 like fmt_long.
651 (store_fpr): When writing an invalid odd register, set the
652 matching even register to fmt_unknown, not the following register.
653 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
654 the the memory window at offset 0 set by --memory-size command
655 line option.
656 (sim_store_register): Handle storing 4 bytes to an 8 byte floating
657 point register.
658 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
659 register.
660 (sim_monitor): When returning the memory size to the MIPS
661 application, use the value in STATE_MEM_SIZE, not an arbitrary
662 hardcoded value.
663 (cop_lw): Don' mess around with FPR_STATE, just pass
664 fmt_uninterpreted_32 to StoreFPR.
665 (cop_sw): Similarly.
666 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
667 (cop_sd): Similarly.
668 * mips.igen (not_word_value): Single version for mips32, mips64
669 and mips16.
670
c8847145 6712007-02-19 Thiemo Seufer <ths@mips.com>
72f4393d 672 Nigel Stephens <nigel@mips.com>
c8847145
TS		 673
674 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
675 MBytes.
676
4b5d35ee
TS		 6772007-02-17 Thiemo Seufer <ths@mips.com>
678
679 * configure.ac (mips*-sde-elf*): Move in front of generic machine
680 configuration.
681 * configure: Regenerate.
682
3669427c
TS		 6832007-02-17 Thiemo Seufer <ths@mips.com>
684
685 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
686 Add mdmx to sim_igen_machine.
687 (mipsisa64*-*-*): Likewise. Remove dsp.
688 (mipsisa32*-*-*): Remove dsp.
689 * configure: Regenerate.
690
109ad085
TS		 6912007-02-13 Thiemo Seufer <ths@mips.com>
692
693 * configure.ac: Add mips*-sde-elf* target.
694 * configure: Regenerate.
695
921d7ad3
HPN		 6962006-12-21 Hans-Peter Nilsson <hp@axis.com>
697
698 * acconfig.h: Remove.
699 * config.in, configure: Regenerate.
700
02f97da7
TS		 7012006-11-07 Thiemo Seufer <ths@mips.com>
702
703 * dsp.igen (do_w_op): Fix compiler warning.
704
2d2733fc 7052006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 706 David Ung <davidu@mips.com>
2d2733fc
TS		 707
708 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
709 sim_igen_machine.
710 * configure: Regenerate.
711 * mips.igen (model): Add smartmips.
712 (MADDU): Increment ACX if carry.
713 (do_mult): Clear ACX.
714 (ROR,RORV): Add smartmips.
72f4393d 715 (include): Include smartmips.igen.
2d2733fc
TS		 716 * sim-main.h (ACX): Set to REGISTERS[89].
717 * smartmips.igen: New file.
718
d85c3a10 7192006-08-29 Thiemo Seufer <ths@mips.com>
72f4393d 720 David Ung <davidu@mips.com>
d85c3a10
TS		 721
722 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
723 mips3264r2.igen. Add missing dependency rules.
724 * m16e.igen: Support for mips16e save/restore instructions.
725
e85e3205
RE		 7262006-06-13 Richard Earnshaw <rearnsha@arm.com>
727
728 * configure: Regenerated.
729
2f0122dc
DJ		 7302006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
731
732 * configure: Regenerated.
733
20e95c23
DJ		 7342006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
735
736 * configure: Regenerated.
737
69088b17
CF		 7382006-05-15 Chao-ying Fu <fu@mips.com>
739
740 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
741
0275de4e
NC		 7422006-04-18 Nick Clifton <nickc@redhat.com>
743
744 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
745 statement.
746
b3a3ffef
HPN		 7472006-03-29 Hans-Peter Nilsson <hp@axis.com>
748
749 * configure: Regenerate.
750
40a5538e
CF		 7512005-12-14 Chao-ying Fu <fu@mips.com>
752
753 * Makefile.in (SIM_OBJS): Add dsp.o.
754 (dsp.o): New dependency.
755 (IGEN_INCLUDE): Add dsp.igen.
756 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
757 mipsisa64*-*-*): Add dsp to sim_igen_machine.
758 * configure: Regenerate.
759 * mips.igen: Add dsp model and include dsp.igen.
760 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
761 because these instructions are extended in DSP ASE.
762 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
763 adding 6 DSP accumulator registers and 1 DSP control register.
764 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
765 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
766 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
767 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
768 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
769 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
770 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
771 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
772 DSPCR_CCOND_SMASK): New define.
773 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
774 * dsp.c, dsp.igen: New files for MIPS DSP ASE.
775
21d14896
ILT		 7762005-07-08 Ian Lance Taylor <ian@airs.com>
777
778 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
779
b16d63da 7802005-06-16 David Ung <davidu@mips.com>
72f4393d
L		 781 Nigel Stephens <nigel@mips.com>
782
783 * mips.igen: New mips16e model and include m16e.igen.
784 (check_u64): Add mips16e tag.
785 * m16e.igen: New file for MIPS16e instructions.
786 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
787 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
788 models.
789 * configure: Regenerate.
b16d63da 790
e70cb6cd 7912005-05-26 David Ung <davidu@mips.com>
72f4393d 792
e70cb6cd
CD		 793 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model
794 tags to all instructions which are applicable to the new ISAs.
795 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
796 vr.igen.
797 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
72f4393d 798 instructions.
e70cb6cd
CD		 799 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
800 to mips.igen.
801 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
802 * configure: Regenerate.
72f4393d 803
2b193c4a
MK		 8042005-03-23 Mark Kettenis <kettenis@gnu.org>
805
806 * configure: Regenerate.
807
35695fd6
AC		 8082005-01-14 Andrew Cagney <cagney@gnu.org>
809
810 * configure.ac: Sinclude aclocal.m4 before common.m4. Add
811 explicit call to AC_CONFIG_HEADER.
812 * configure: Regenerate.
813
f0569246
AC		 8142005-01-12 Andrew Cagney <cagney@gnu.org>
815
816 * configure.ac: Update to use ../common/common.m4.
817 * configure: Re-generate.
818
38f48d72
AC		 8192005-01-11 Andrew Cagney <cagney@localhost.localdomain>
820
821 * configure: Regenerated to track ../common/aclocal.m4 changes.
822
b7026657
AC		 8232005-01-07 Andrew Cagney <cagney@gnu.org>
824
825 * configure.ac: Rename configure.in, require autoconf 2.59.
826 * configure: Re-generate.
827
379832de
HPN		 8282004-12-08 Hans-Peter Nilsson <hp@axis.com>
829
830 * configure: Regenerate for ../common/aclocal.m4 update.
831
cd62154c 8322004-09-24 Monika Chaddha <monika@acmet.com>
72f4393d 833
cd62154c
AC		 834 Committed by Andrew Cagney.
835 * m16.igen (CMP, CMPI): Fix assembler.
836
e5da76ec
CD		 8372004-08-18 Chris Demetriou <cgd@broadcom.com>
838
839 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
840 * configure: Regenerate.
841
139181c8
CD		 8422004-06-25 Chris Demetriou <cgd@broadcom.com>
843
844 * configure.in (sim_m16_machine): Include mipsIII.
845 * configure: Regenerate.
846
1a27f959
CD		 8472004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl>
848
72f4393d 849 * mips/interp.c (decode_coproc): Sign-extend the address retrieved
1a27f959
CD		 850 from COP0_BADVADDR.
851 * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
852
5dbb7b5a
CD		 8532004-04-10 Chris Demetriou <cgd@broadcom.com>
854
855 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
856
14234056
CD		 8572004-04-09 Chris Demetriou <cgd@broadcom.com>
858
859 * mips.igen (check_fmt): Remove.
860 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
861 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
862 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
863 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
864 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
865 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
866 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
867 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
868 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
869 (C.cnd.fmta): Remove incorrect call to check_fmt_p.
870
c6f9085c
CD		 8712004-04-09 Chris Demetriou <cgd@broadcom.com>
872
873 * sb1.igen (check_sbx): New function.
874 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
875
11d66e66 8762004-03-29 Chris Demetriou <cgd@broadcom.com>
0e1b7197
RS		 877 Richard Sandiford <rsandifo@redhat.com>
878
879 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
880 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
881 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
882 separate implementations for mipsIV and mipsV. Use new macros to
883 determine whether the restrictions apply.
884
b3208fb8
CD		 8852004-01-19 Chris Demetriou <cgd@broadcom.com>
886
887 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
888 (check_mult_hilo): Improve comments.
889 (check_div_hilo): Likewise. Also, fork off a new version
890 to handle mips32/mips64 (since there are no hazards to check
891 in MIPS32/MIPS64).
892
9a1d84fb
CD		 8932003-06-17 Richard Sandiford <rsandifo@redhat.com>
894
895 * mips.igen (do_dmultx): Fix check for negative operands.
896
ae451ac6
ILT		 8972003-05-16 Ian Lance Taylor <ian@airs.com>
898
899 * Makefile.in (SHELL): Make sure this is defined.
900 (various): Use $(SHELL) whenever we invoke move-if-change.
901
dd69d292
CD		 9022003-05-03 Chris Demetriou <cgd@broadcom.com>
903
904 * cp1.c: Tweak attribution slightly.
905 * cp1.h: Likewise.
906 * mdmx.c: Likewise.
907 * mdmx.igen: Likewise.
908 * mips3d.igen: Likewise.
909 * sb1.igen: Likewise.
910
bcd0068e
CD		 9112003-04-15 Richard Sandiford <rsandifo@redhat.com>
912
913 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
914 unsigned operands.
915
6b4a8935
AC		 9162003-02-27 Andrew Cagney <cagney@redhat.com>
917
601da316
AC		 918 * interp.c (sim_open): Rename _bfd to bfd.
919 (sim_create_inferior): Ditto.
6b4a8935 920
d29e330f
CD		 9212003-01-14 Chris Demetriou <cgd@broadcom.com>
922
923 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
924
a2353a08
CD		 9252003-01-14 Chris Demetriou <cgd@broadcom.com>
926
927 * mips.igen (EI, DI): Remove.
928
80551777
CD		 9292003-01-05 Richard Sandiford <rsandifo@redhat.com>
930
931 * Makefile.in (tmp-run-multi): Fix mips16 filter.
932
4c54fc26
CD		 9332003-01-04 Richard Sandiford <rsandifo@redhat.com>
934 Andrew Cagney <ac131313@redhat.com>
935 Gavin Romig-Koch <gavin@redhat.com>
936 Graydon Hoare <graydon@redhat.com>
937 Aldy Hernandez <aldyh@redhat.com>
938 Dave Brolley <brolley@redhat.com>
939 Chris Demetriou <cgd@broadcom.com>
940
941 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
942 (sim_mach_default): New variable.
943 (mips64vr-*-*, mips64vrel-*-*): New configurations.
944 Add a new simulator generator, MULTI.
945 * configure: Regenerate.
946 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
947 (multi-run.o): New dependency.
948 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
949 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
950 (tmp-multi): Combine them.
951 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
952 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
953 (distclean-extra): New rule.
954 * sim-main.h: Include bfd.h.
955 (MIPS_MACH): New macro.
956 * mips.igen (vr4120, vr5400, vr5500): New models.
957 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
958 * vr.igen: Replace with new version.
959
e6c674b8
CD		 9602003-01-04 Chris Demetriou <cgd@broadcom.com>
961
962 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
963 * configure: Regenerate.
964
28f50ac8
CD		 9652002-12-31 Chris Demetriou <cgd@broadcom.com>
966
967 * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
968 * mips.igen: Remove all invocations of check_branch_bug and
969 mark_branch_bug.
970
5071ffe6
CD		 9712002-12-16 Chris Demetriou <cgd@broadcom.com>
972
72f4393d 973 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
5071ffe6 974
06e7837e
CD		 9752002-07-30 Chris Demetriou <cgd@broadcom.com>
976
977 * mips.igen (do_load_double, do_store_double): New functions.
978 (LDC1, SDC1): Rename to...
979 (LDC1b, SDC1b): respectively.
980 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
981
2265c243
MS		 9822002-07-29 Michael Snyder <msnyder@redhat.com>
983
984 * cp1.c (fp_recip2): Modify initialization expression so that
985 GCC will recognize it as constant.
986
a2f8b4f3
CD		 9872002-06-18 Chris Demetriou <cgd@broadcom.com>
988
989 * mdmx.c (SD_): Delete.
990 (Unpredictable): Re-define, for now, to directly invoke
991 unpredictable_action().
992 (mdmx_acc_op): Fix error in .ob immediate handling.
993
b4b6c939
AC		 9942002-06-18 Andrew Cagney <cagney@redhat.com>
995
996 * interp.c (sim_firmware_command): Initialize `address'.
997
c8cca39f
AC		 9982002-06-16 Andrew Cagney <ac131313@redhat.com>
999
1000 * configure: Regenerated to track ../common/aclocal.m4 changes.
1001
e7e81181 10022002-06-14 Chris Demetriou <cgd@broadcom.com>
72f4393d 1003 Ed Satterthwaite <ehs@broadcom.com>
e7e81181
CD		 1004
1005 * mips3d.igen: New file which contains MIPS-3D ASE instructions.
1006 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
1007 * mips.igen: Include mips3d.igen.
1008 (mips3d): New model name for MIPS-3D ASE instructions.
1009 (CVT.W.fmt): Don't use this instruction for word (source) format
72f4393d 1010 instructions.
e7e81181
CD		 1011 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
1012 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
1013 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
1014 (NR_FRAC_GUARD, IMPLICIT_1): New macros.
1015 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
1016 (RSquareRoot1, RSquareRoot2): New macros.
1017 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
1018 (fp_rsqrt2): New functions.
1019 * configure.in: Add MIPS-3D support to mipsisa64 simulator.
1020 * configure: Regenerate.
1021
3a2b820e 10222002-06-13 Chris Demetriou <cgd@broadcom.com>
72f4393d 1023 Ed Satterthwaite <ehs@broadcom.com>
3a2b820e
CD		 1024
1025 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
1026 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
1027 (fp_inv_sqrt, fpu_format_name): Add paired-single support.
1028 (convert): Note that this function is not used for paired-single
1029 format conversions.
1030 (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
1031 * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
1032 (check_fmt_p): Enable paired-single support.
1033 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
1034 (PUU.PS): New instructions.
1035 (CVT.S.fmt): Don't use this instruction for paired-single format
1036 destinations.
1037 * sim-main.h (FP_formats): New value 'fmt_ps.'
1038 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
1039 (PSLower, PSUpper, PackPS, ConvertPS): New macros.
1040
d18ea9c2
CD		 10412002-06-12 Chris Demetriou <cgd@broadcom.com>
1042
1043 * mips.igen: Fix formatting of function calls in
1044 many FP operations.
1045
95fd5cee
CD		 10462002-06-12 Chris Demetriou <cgd@broadcom.com>
1047
1048 * mips.igen (MOVN, MOVZ): Trace result.
1049 (TNEI): Print "tnei" as the opcode name in traces.
1050 (CEIL.W): Add disassembly string for traces.
1051 (RSQRT.fmt): Make location of disassembly string consistent
1052 with other instructions.
1053
4f0d55ae
CD		 10542002-06-12 Chris Demetriou <cgd@broadcom.com>
1055
1056 * mips.igen (X): Delete unused function.
1057
3c25f8c7
AC		 10582002-06-08 Andrew Cagney <cagney@redhat.com>
1059
1060 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
1061
f3c08b7e 10622002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1063 Ed Satterthwaite <ehs@broadcom.com>
f3c08b7e
CD		 1064
1065 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
1066 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
1067 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
1068 (fp_nmsub): New prototypes.
1069 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
1070 (NegMultiplySub): New defines.
1071 * mips.igen (RSQRT.fmt): Use RSquareRoot().
1072 (MADD.D, MADD.S): Replace with...
1073 (MADD.fmt): New instruction.
1074 (MSUB.D, MSUB.S): Replace with...
1075 (MSUB.fmt): New instruction.
1076 (NMADD.D, NMADD.S): Replace with...
1077 (NMADD.fmt): New instruction.
1078 (NMSUB.D, MSUB.S): Replace with...
1079 (NMSUB.fmt): New instruction.
1080
52714ff9 10812002-06-07 Chris Demetriou <cgd@broadcom.com>
72f4393d 1082 Ed Satterthwaite <ehs@broadcom.com>
52714ff9
CD		 1083
1084 * cp1.c: Fix more comment spelling and formatting.
1085 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
1086 (denorm_mode): New function.
1087 (fpu_unary, fpu_binary): Round results after operation, collect
1088 status from rounding operations, and update the FCSR.
1089 (convert): Collect status from integer conversions and rounding
1090 operations, and update the FCSR. Adjust NaN values that result
1091 from conversions. Convert to use sim_io_eprintf rather than
1092 fprintf, and remove some debugging code.
1093 * cp1.h (fenr_FS): New define.
1094
577d8c4b
CD		 10952002-06-07 Chris Demetriou <cgd@broadcom.com>
1096
1097 * cp1.c (convert): Remove unusable debugging code, and move MIPS
1098 rounding mode to sim FP rounding mode flag conversion code into...
1099 (rounding_mode): New function.
1100
196496ed
CD		 11012002-06-07 Chris Demetriou <cgd@broadcom.com>
1102
1103 * cp1.c: Clean up formatting of a few comments.
1104 (value_fpr): Reformat switch statement.
1105
cfe9ea23 11062002-06-06 Chris Demetriou <cgd@broadcom.com>
72f4393d 1107 Ed Satterthwaite <ehs@broadcom.com>
cfe9ea23
CD		 1108
1109 * cp1.h: New file.
1110 * sim-main.h: Include cp1.h.
1111 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
1112 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
1113 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h.
1114 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
1115 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
1116 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
1117 * cp1.c: Don't include sim-fpu.h; already included by
1118 sim-main.h. Clean up formatting of some comments.
1119 (NaN, Equal, Less): Remove.
1120 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
1121 (fp_cmp): New functions.
1122 * mips.igen (do_c_cond_fmt): Remove.
1123 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
1124 Compare. Add result tracing.
1125 (CxC1): Remove, replace with...
1126 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
1127 (DMxC1): Remove, replace with...
1128 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
72f4393d
L		 1129 (MxC1): Remove, replace with...
1130 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
cfe9ea23 1131
ee7254b0
CD		 11322002-06-04 Chris Demetriou <cgd@broadcom.com>
1133
1134 * sim-main.h (FGRIDX): Remove, replace all uses with...
1135 (FGR_BASE): New macro.
1136 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
1137 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
1138 (NR_FGR, FGR): Likewise.
1139 * interp.c: Replace all uses of FGRIDX with FGR_BASE.
1140 * mips.igen: Likewise.
1141
d3eb724f
CD		 11422002-06-04 Chris Demetriou <cgd@broadcom.com>
1143
1144 * cp1.c: Add an FSF Copyright notice to this file.
1145
ba46ddd0 11462002-06-04 Chris Demetriou <cgd@broadcom.com>
72f4393d 1147 Ed Satterthwaite <ehs@broadcom.com>
ba46ddd0
CD		 1148
1149 * cp1.c (Infinity): Remove.
1150 * sim-main.h (Infinity): Likewise.
1151
1152 * cp1.c (fp_unary, fp_binary): New functions.
1153 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
1154 (fp_sqrt): New functions, implemented in terms of the above.
1155 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1156 (Recip, SquareRoot): Remove (replaced by functions above).
1157 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
1158 (fp_recip, fp_sqrt): New prototypes.
1159 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
1160 (Recip, SquareRoot): Replace prototypes with #defines which
1161 invoke the functions above.
72f4393d 1162
18d8a52d
CD		 11632002-06-03 Chris Demetriou <cgd@broadcom.com>
1164
1165 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
1166 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
1167 file, remove PARAMS from prototypes.
1168 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
1169 simulator state arguments.
1170 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
1171 pass simulator state arguments.
1172 * cp1.c (SD): Redefine as CPU_STATE(cpu).
1173 (store_fpr, convert): Remove 'sd' argument.
1174 (value_fpr): Likewise. Convert to use 'SD' instead.
1175
0f154cbd
CD		 11762002-06-03 Chris Demetriou <cgd@broadcom.com>
1177
1178 * cp1.c (Min, Max): Remove #if 0'd functions.
1179 * sim-main.h (Min, Max): Remove.
1180
e80fc152
CD		 11812002-06-03 Chris Demetriou <cgd@broadcom.com>
1182
1183 * cp1.c: fix formatting of switch case and default labels.
1184 * interp.c: Likewise.
1185 * sim-main.c: Likewise.
1186
bad673a9
CD		 11872002-06-03 Chris Demetriou <cgd@broadcom.com>
1188
1189 * cp1.c: Clean up comments which describe FP formats.
1190 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
1191
7cbea089 11922002-06-03 Chris Demetriou <cgd@broadcom.com>
72f4393d 1193 Ed Satterthwaite <ehs@broadcom.com>
7cbea089
CD		 1194
1195 * configure.in (mipsisa64sb1*-*-*): New target for supporting
1196 Broadcom SiByte SB-1 processor configurations.
1197 * configure: Regenerate.
1198 * sb1.igen: New file.
1199 * mips.igen: Include sb1.igen.
1200 (sb1): New model.
1201 * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
1202 * mdmx.igen: Add "sb1" model to all appropriate functions and
1203 instructions.
1204 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
1205 (ob_func, ob_acc): Reference the above.
1206 (qh_acc): Adjust to keep the same size as ob_acc.
1207 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
1208 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
1209
909daa82
CD		 12102002-06-03 Chris Demetriou <cgd@broadcom.com>
1211
1212 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1213
f4f1b9f1 12142002-06-02 Chris Demetriou <cgd@broadcom.com>
72f4393d 1215 Ed Satterthwaite <ehs@broadcom.com>
f4f1b9f1
CD		 1216
1217 * mips.igen (mdmx): New (pseudo-)model.
1218 * mdmx.c, mdmx.igen: New files.
1219 * Makefile.in (SIM_OBJS): Add mdmx.o.
1220 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
1221 New typedefs.
1222 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
1223 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
1224 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
1225 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
1226 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
1227 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
1228 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
1229 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
1230 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
1231 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
1232 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
1233 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
1234 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
1235 (qh_fmtsel): New macros.
1236 (_sim_cpu): New member "acc".
1237 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
1238 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
1239
5accf1ff
CD		 12402002-05-01 Chris Demetriou <cgd@broadcom.com>
1241
1242 * interp.c: Use 'deprecated' rather than 'depreciated.'
1243 * sim-main.h: Likewise.
1244
402586aa
CD		 12452002-05-01 Chris Demetriou <cgd@broadcom.com>
1246
1247 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
1248 which wouldn't compile anyway.
1249 * sim-main.h (unpredictable_action): New function prototype.
1250 (Unpredictable): Define to call igen function unpredictable().
1251 (NotWordValue): New macro to call igen function not_word_value().
1252 (UndefinedResult): Remove.
1253 * interp.c (undefined_result): Remove.
1254 (unpredictable_action): New function.
1255 * mips.igen (not_word_value, unpredictable): New functions.
1256 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
1257 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
1258 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
1259 NotWordValue() to check for unpredictable inputs, then
1260 Unpredictable() to handle them.
1261
c9b9995a
CD		 12622002-02-24 Chris Demetriou <cgd@broadcom.com>
1263
1264 * mips.igen: Fix formatting of calls to Unpredictable().
1265
e1015982
AC		 12662002-04-20 Andrew Cagney <ac131313@redhat.com>
1267
1268 * interp.c (sim_open): Revert previous change.
1269
b882a66b
AO		 12702002-04-18 Alexandre Oliva <aoliva@redhat.com>
1271
1272 * interp.c (sim_open): Disable chunk of code that wrote code in
1273 vector table entries.
1274
c429b7dd
CD		 12752002-03-19 Chris Demetriou <cgd@broadcom.com>
1276
1277 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
1278 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
1279 unused definitions.
1280
37d146fa
CD		 12812002-03-19 Chris Demetriou <cgd@broadcom.com>
1282
1283 * cp1.c: Fix many formatting issues.
1284
07892c0b
CD		 12852002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1286
1287 * cp1.c (fpu_format_name): New function to replace...
1288 (DOFMT): This. Delete, and update all callers.
1289 (fpu_rounding_mode_name): New function to replace...
1290 (RMMODE): This. Delete, and update all callers.
1291
487f79b7
CD		 12922002-03-19 Chris G. Demetriou <cgd@broadcom.com>
1293
1294 * interp.c: Move FPU support routines from here to...
1295 * cp1.c: Here. New file.
1296 * Makefile.in (SIM_OBJS): Add cp1.o to object list.
1297 (cp1.o): New target.
1298
1e799e28
CD		 12992002-03-12 Chris Demetriou <cgd@broadcom.com>
1300
1301 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
1302 * mips.igen (mips32, mips64): New models, add to all instructions
1303 and functions as appropriate.
1304 (loadstore_ea, check_u64): New variant for model mips64.
1305 (check_fmt_p): New variant for models mipsV and mips64, remove
1306 mipsV model marking fro other variant.
1307 (SLL) Rename to...
1308 (SLLa) this.
1309 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
1310 for mips32 and mips64.
1311 (DCLO, DCLZ): New instructions for mips64.
1312
82f728db
CD		 13132002-03-07 Chris Demetriou <cgd@broadcom.com>
1314
1315 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
1316 immediate or code as a hex value with the "%#lx" format.
1317 (ANDI): Likewise, and fix printed instruction name.
1318
b96e7ef1
CD		 13192002-03-05 Chris Demetriou <cgd@broadcom.com>
1320
1321 * sim-main.h (UndefinedResult, Unpredictable): New macros
1322 which currently do nothing.
1323
d35d4f70
CD		 13242002-03-05 Chris Demetriou <cgd@broadcom.com>
1325
1326 * sim-main.h (status_UX, status_SX, status_KX, status_TS)
1327 (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
1328 (status_CU3): New definitions.
1329
1330 * sim-main.h (ExceptionCause): Add new values for MIPS32
1331 and MIPS64: MDMX, MCheck, CacheErr. Update comments
1332 for DebugBreakPoint and NMIReset to note their status in
1333 MIPS32 and MIPS64.
1334 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
1335 (SignalExceptionCacheErr): New exception macros.
1336
3ad6f714
CD		 13372002-03-05 Chris Demetriou <cgd@broadcom.com>
1338
1339 * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
1340 * sim-main.h (COP_Usable): Define, but for now coprocessor 1
1341 is always enabled.
1342 (SignalExceptionCoProcessorUnusable): Take as argument the
1343 unusable coprocessor number.
1344
86b77b47
CD		 13452002-03-05 Chris Demetriou <cgd@broadcom.com>
1346
1347 * mips.igen: Fix formatting of all SignalException calls.
1348
97a88e93 13492002-03-05 Chris Demetriou <cgd@broadcom.com>
3dea6720
CD		 1350
1351 * sim-main.h (SIGNEXTEND): Remove.
1352
97a88e93 13532002-03-04 Chris Demetriou <cgd@broadcom.com>
b5040d49
CD		 1354
1355 * mips.igen: Remove gencode comment from top of file, fix
1356 spelling in another comment.
1357
97a88e93 13582002-03-04 Chris Demetriou <cgd@broadcom.com>
8612006b
CD		 1359
1360 * mips.igen (check_fmt, check_fmt_p): New functions to check
1361 whether specific floating point formats are usable.
1362 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
1363 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
1364 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
1365 Use the new functions.
1366 (do_c_cond_fmt): Remove format checks...
1367 (C.cond.fmta, C.cond.fmtb): And move them into all callers.
1368
97a88e93 13692002-03-03 Chris Demetriou <cgd@broadcom.com>
9b17d183
CD		 1370
1371 * mips.igen: Fix formatting of check_fpu calls.
1372
41774c9d
CD		 13732002-03-03 Chris Demetriou <cgd@broadcom.com>
1374
1375 * mips.igen (FLOOR.L.fmt): Store correct destination register.
1376
4a0bd876
CD		 13772002-03-03 Chris Demetriou <cgd@broadcom.com>
1378
1379 * mips.igen: Remove whitespace at end of lines.
1380
09297648
CD		 13812002-03-02 Chris Demetriou <cgd@broadcom.com>
1382
1383 * mips.igen (loadstore_ea): New function to do effective
1384 address calculations.
1385 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
1386 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
1387 CACHE): Use loadstore_ea to do effective address computations.
1388
043b7057
CD		 13892002-03-02 Chris Demetriou <cgd@broadcom.com>
1390
1391 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
1392 * mips.igen (LL, CxC1, MxC1): Likewise.
1393
c1e8ada4
CD		 13942002-03-02 Chris Demetriou <cgd@broadcom.com>
1395
1396 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
1397 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
1398 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
1399 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
1400 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
1401 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
1402 Don't split opcode fields by hand, use the opcode field values
1403 provided by igen.
1404
3e1dca16
CD		 14052002-03-01 Chris Demetriou <cgd@broadcom.com>
1406
1407 * mips.igen (do_divu): Fix spacing.
1408
1409 * mips.igen (do_dsllv): Move to be right before DSLLV,
1410 to match the rest of the do_<shift> functions.
1411
fff8d27d
CD		 14122002-03-01 Chris Demetriou <cgd@broadcom.com>
1413
1414 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
1415 DSRL32, do_dsrlv): Trace inputs and results.
1416
0d3e762b
CD		 14172002-03-01 Chris Demetriou <cgd@broadcom.com>
1418
1419 * mips.igen (CACHE): Provide instruction-printing string.
1420
1421 * interp.c (signal_exception): Comment tokens after #endif.
1422
eb5fcf93
CD		 14232002-02-28 Chris Demetriou <cgd@broadcom.com>
1424
1425 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
72f4393d
L		 1426 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
1427 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
1428 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
1429 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
1430 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
1431 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
eb5fcf93
CD		 1432 LWC1, SWC1): Add "f" to filter, since these are FP instructions.
1433
bb22bd7d
CD		 14342002-02-28 Chris Demetriou <cgd@broadcom.com>
1435
1436 * mips.igen (DSRA32, DSRAV): Fix order of arguments in
1437 instruction-printing string.
1438 (LWU): Use '64' as the filter flag.
1439
91a177cf
CD		 14402002-02-28 Chris Demetriou <cgd@broadcom.com>
1441
1442 * mips.igen (SDXC1): Fix instruction-printing string.
1443
387f484a
CD		 14442002-02-28 Chris Demetriou <cgd@broadcom.com>
1445
1446 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
1447 filter flags "32,f".
1448
3d81f391
CD		 14492002-02-27 Chris Demetriou <cgd@broadcom.com>
1450
1451 * mips.igen (PREFX): This is a 64-bit instruction, use '64'
1452 as the filter flag.
1453
af5107af
CD		 14542002-02-27 Chris Demetriou <cgd@broadcom.com>
1455
1456 * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
1457 add a comma) so that it more closely match the MIPS ISA
1458 documentation opcode partitioning.
1459 (PREF): Put useful names on opcode fields, and include
1460 instruction-printing string.
1461
ca971540
CD		 14622002-02-27 Chris Demetriou <cgd@broadcom.com>
1463
1464 * mips.igen (check_u64): New function which in the future will
1465 check whether 64-bit instructions are usable and signal an
1466 exception if not. Currently a no-op.
1467 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
1468 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
1469 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
1470 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
1471
1472 * mips.igen (check_fpu): New function which in the future will
1473 check whether FPU instructions are usable and signal an exception
1474 if not. Currently a no-op.
1475 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
1476 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
1477 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
1478 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
1479 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
1480 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
1481 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
1482 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
1483
1c47a468
CD		 14842002-02-27 Chris Demetriou <cgd@broadcom.com>
1485
1486 * mips.igen (do_load_left, do_load_right): Move to be immediately
1487 following do_load.
1488 (do_store_left, do_store_right): Move to be immediately following
1489 do_store.
1490
603a98e7
CD		 14912002-02-27 Chris Demetriou <cgd@broadcom.com>
1492
1493 * mips.igen (mipsV): New model name. Also, add it to
1494 all instructions and functions where it is appropriate.
1495
c5d00cc7
CD		 14962002-02-18 Chris Demetriou <cgd@broadcom.com>
1497
1498 * mips.igen: For all functions and instructions, list model
1499 names that support that instruction one per line.
1500
074e9cb8
CD		 15012002-02-11 Chris Demetriou <cgd@broadcom.com>
1502
1503 * mips.igen: Add some additional comments about supported
1504 models, and about which instructions go where.
1505 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
1506 order as is used in the rest of the file.
1507
9805e229
CD		 15082002-02-11 Chris Demetriou <cgd@broadcom.com>
1509
1510 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
1511 indicating that ALU32_END or ALU64_END are there to check
1512 for overflow.
1513 (DADD): Likewise, but also remove previous comment about
1514 overflow checking.
1515
f701dad2
CD		 15162002-02-10 Chris Demetriou <cgd@broadcom.com>
1517
1518 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
1519 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
1520 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
1521 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
1522 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
1523 fields (i.e., add and move commas) so that they more closely
1524 match the MIPS ISA documentation opcode partitioning.
1525
15262002-02-10 Chris Demetriou <cgd@broadcom.com>
20ae0098 1527
72f4393d
L		 1528 * mips.igen (ADDI): Print immediate value.
1529 (BREAK): Print code.
1530 (DADDIU, DSRAV, DSRLV): Print correct instruction name.
1531 (SLL): Print "nop" specially, and don't run the code
1532 that does the shift for the "nop" case.
20ae0098 1533
9e52972e
FF		 15342001-11-17 Fred Fish <fnf@redhat.com>
1535
1536 * sim-main.h (float_operation): Move enum declaration outside
1537 of _sim_cpu struct declaration.
1538
c0efbca4
JB		 15392001-04-12 Jim Blandy <jimb@redhat.com>
1540
1541 * mips.igen (CFC1, CTC1): Pass the correct register numbers to
1542 PENDING_FILL. Use PENDING_SCHED directly to handle the pending
1543 set of the FCSR.
1544 * sim-main.h (COCIDX): Remove definition; this isn't supported by
1545 PENDING_FILL, and you can get the intended effect gracefully by
1546 calling PENDING_SCHED directly.
1547
fb891446
BE		 15482001-02-23 Ben Elliston <bje@redhat.com>
1549
1550 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
1551 already defined elsewhere.
1552
8030f857
BE		 15532001-02-19 Ben Elliston <bje@redhat.com>
1554
1555 * sim-main.h (sim_monitor): Return an int.
1556 * interp.c (sim_monitor): Add return values.
1557 (signal_exception): Handle error conditions from sim_monitor.
1558
56b48a7a
CD		 15592001-02-08 Ben Elliston <bje@redhat.com>
1560
1561 * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
1562 (store_memory): Likewise, pass cia to sim_core_write*.
1563
d3ee60d9
FCE		 15642000-10-19 Frank Ch. Eigler <fche@redhat.com>
1565
1566 On advice from Chris G. Demetriou <cgd@sibyte.com>:
1567 * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
1568
071da002
AC		 1569Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com>
1570
1571 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
1572 * Makefile.in: Don't delete *.igen when cleaning directory.
1573
a28c02cd
AC		 1574Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com>
1575
1576 * m16.igen (break): Call SignalException not sim_engine_halt.
1577
80ee11fa
AC		 1578Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com>
1579
1580 From Jason Eckhardt:
1581 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1582
673388c0
AC		 1583Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
1584
1585 * mips.igen (MxC1, DMxC1): Fix printf formatting.
1586
4c0deff4
NC		 15872000-05-24 Michael Hayes <mhayes@cygnus.com>
1588
1589 * mips.igen (do_dmultx): Fix typo.
1590
eb2d80b4
AC		 1591Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
1592
1593 * configure: Regenerated to track ../common/aclocal.m4 changes.
1594
dd37a34b
AC		 1595Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com>
1596
1597 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1598
4c0deff4
NC		 15992000-04-12 Frank Ch. Eigler <fche@redhat.com>
1600
1601 * sim-main.h (GPR_CLEAR): Define macro.
1602
e30db738
AC		 1603Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com>
1604
1605 * interp.c (decode_coproc): Output long using %lx and not %s.
1606
cb7450ea
FCE		 16072000-03-21 Frank Ch. Eigler <fche@redhat.com>
1608
1609 * interp.c (sim_open): Sort & extend dummy memory regions for
1610 --board=jmr3904 for eCos.
1611
a3027dd7
FCE		 16122000-03-02 Frank Ch. Eigler <fche@redhat.com>
1613
1614 * configure: Regenerated.
1615
1616Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com>
1617
1618 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1619 calls, conditional on the simulator being in verbose mode.
1620
dfcd3bfb
JM		 1621Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com>
1622
1623 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1624 cache don't get ReservedInstruction traps.
1625
c2d11a7d
JM		 16261999-11-29 Mark Salter <msalter@cygnus.com>
1627
1628 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1629 to clear status bits in sdisr register. This is how the hardware works.
1630
1631 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1632 being used by cygmon.
1633
4ce44c66
JM		 16341999-11-11 Andrew Haley <aph@cygnus.com>
1635
1636 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1637 instructions.
1638
cff3e48b
JM		 1639Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com>
1640
1641 * mips.igen (MULT): Correct previous mis-applied patch.
1642
d4f3574e
SS		 1643Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com>
1644
1645 * mips.igen (delayslot32): Handle sequence like
1646 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1647 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1648 (MULT): Actually pass the third register...
1649
16501999-09-03 Mark Salter <msalter@cygnus.com>
1651
1652 * interp.c (sim_open): Added more memory aliases for additional
1653 hardware being touched by cygmon on jmr3904 board.
1654
1655Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
1656
1657 * configure: Regenerated to track ../common/aclocal.m4 changes.
1658
a0b3c4fd
JM		 1659Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com>
1660
1661 * interp.c (sim_store_register): Handle case where client - GDB -
1662 specifies that a 4 byte register is 8 bytes in size.
1663 (sim_fetch_register): Ditto.
72f4393d 1664
adf40b2e
JM		 16651999-07-14 Frank Ch. Eigler <fche@cygnus.com>
1666
1667 Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1668 * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1669 (idt_monitor_base): Base address for IDT monitor traps.
1670 (pmon_monitor_base): Ditto for PMON.
1671 (lsipmon_monitor_base): Ditto for LSI PMON.
1672 (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1673 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1674 (sim_firmware_command): New function.
1675 (mips_option_handler): Call it for OPTION_FIRMWARE.
1676 (sim_open): Allocate memory for idt_monitor region. If "--board"
1677 option was given, add no monitor by default. Add BREAK hooks only if
1678 monitors are also there.
72f4393d 1679
43e526b9
JM		 1680Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com>
1681
1682 * interp.c (sim_monitor): Flush output before reading input.
1683
1684Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com>
1685
1686 * tconfig.in (SIM_HANDLES_LMA): Always define.
1687
1688Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com>
1689
1690 From Mark Salter <msalter@cygnus.com>:
1691 * interp.c (BOARD_BSP): Define. Add to list of possible boards.
1692 (sim_open): Add setup for BSP board.
1693
9846de1b
JM		 1694Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com>
1695
1696 * mips.igen (MULT, MULTU): Add syntax for two operand version.
1697 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report
1698 them as unimplemented.
1699
cd0fc7c3
SS		 17001999-05-08 Felix Lee <flee@cygnus.com>
1701
1702 * configure: Regenerated to track ../common/aclocal.m4 changes.
72f4393d 1703
7a292a7a
SS		 17041999-04-21 Frank Ch. Eigler <fche@cygnus.com>
1705
1706 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1707
1708Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com>
1709
1710 * configure.in: Any mips64vr5*-*-* target should have
1711 -DTARGET_ENABLE_FR=1.
1712 (default_endian): Any mips64vr*el-*-* target should default to
1713 LITTLE_ENDIAN.
1714 * configure: Re-generate.
1715
17161999-02-19 Gavin Romig-Koch <gavin@cygnus.com>
1717
1718 * mips.igen (ldl): Extend from _16_, not 32.
1719
1720Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com>
1721
1722 * interp.c (sim_store_register): Force registers written to by GDB
1723 into an un-interpreted state.
1724
c906108c
SS		 17251999-02-05 Frank Ch. Eigler <fche@cygnus.com>
1726
1727 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1728 CPU, start periodic background I/O polls.
72f4393d 1729 (tx3904sio_poll): New function: periodic I/O poller.
c906108c
SS		 1730
17311998-12-30 Frank Ch. Eigler <fche@cygnus.com>
1732
1733 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
72f4393d 1734
c906108c
SS		 1735Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE>
1736
1737 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1738 case statement.
1739
17401998-12-29 Frank Ch. Eigler <fche@cygnus.com>
72f4393d
L		 1741
1742 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
c906108c
SS		 1743 (load_word): Call SIM_CORE_SIGNAL hook on error.
1744 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1745 starting. For exception dispatching, pass PC instead of NULL_CIA.
1746 (decode_coproc): Use COP0_BADVADDR to store faulting address.
72f4393d 1747 * sim-main.h (COP0_BADVADDR): Define.
c906108c
SS		 1748 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1749 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
72f4393d 1750 (_sim_cpu): Add exc_* fields to store register value snapshots.
c906108c
SS		 1751 * mips.igen (*): Replace memory-related SignalException* calls
1752 with references to SIM_CORE_SIGNAL hook.
72f4393d 1753
c906108c
SS		 1754 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1755 fix.
1756 * sim-main.c (*): Minor warning cleanups.
72f4393d 1757
c906108c
SS		 17581998-12-24 Gavin Romig-Koch <gavin@cygnus.com>
1759
1760 * m16.igen (DADDIU5): Correct type-o.
1761
1762Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook>
1763
1764 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1765 variables.
1766
1767Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook>
1768
1769 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1770 to include path.
1771 (interp.o): Add dependency on itable.h
1772 (oengine.c, gencode): Delete remaining references.
1773 (BUILT_SRC_FROM_GEN): Clean up.
72f4393d 1774
c906108c 17751998-12-16 Gavin Romig-Koch <gavin@cygnus.com>
72f4393d 1776
c906108c
SS		 1777 * vr4run.c: New.
1778 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1779 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1780 tmp-run-hack) : New.
1781 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
72f4393d 1782 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
c906108c
SS		 1783 Drop the "64" qualifier to get the HACK generator working.
1784 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT.
1785 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1786 qualifier to get the hack generator working.
1787 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1788 (DSLL): Use do_dsll.
1789 (DSLLV): Use do_dsllv.
1790 (DSRA): Use do_dsra.
1791 (DSRL): Use do_dsrl.
1792 (DSRLV): Use do_dsrlv.
1793 (BC1): Move *vr4100 to get the HACK generator working.
72f4393d 1794 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
c906108c
SS		 1795 get the HACK generator working.
1796 (MACC) Rename to get the HACK generator working.
1797 (DMACC,MACCS,DMACCS): Add the 64.
72f4393d 1798
c906108c
SS		 17991998-12-12 Gavin Romig-Koch <gavin@cygnus.com>
1800
1801 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1802 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
72f4393d 1803
c906108c
SS		 18041998-12-11 Gavin Romig-Koch <gavin@cygnus.com>
1805
1806 * mips/interp.c (DEBUG): Cleanups.
1807
18081998-12-10 Frank Ch. Eigler <fche@cygnus.com>
1809
1810 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1811 (tx3904sio_tickle): fflush after a stdout character output.
72f4393d 1812
c906108c
SS		 18131998-12-03 Frank Ch. Eigler <fche@cygnus.com>
1814
1815 * interp.c (sim_close): Uninstall modules.
1816
1817Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
1818
1819 * sim-main.h, interp.c (sim_monitor): Change to global
1820 function.
1821
1822Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
1823
1824 * configure.in (vr4100): Only include vr4100 instructions in
1825 simulator.
1826 * configure: Re-generate.
1827 * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1828
1829Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1830
1831 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1832 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1833 true alternative.
1834
1835 * configure.in (sim_default_gen, sim_use_gen): Replace with
1836 sim_gen.
1837 (--enable-sim-igen): Delete config option. Always using IGEN.
1838 * configure: Re-generate.
72f4393d 1839
c906108c
SS		 1840 * Makefile.in (gencode): Kill, kill, kill.
1841 * gencode.c: Ditto.
72f4393d 1842
c906108c
SS		 1843Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com>
1844
1845 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1846 bit mips16 igen simulator.
1847 * configure: Re-generate.
1848
1849 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1850 as part of vr4100 ISA.
1851 * vr.igen: Mark all instructions as 64 bit only.
1852
1853Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
1854
1855 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1856 Pacify GCC.
1857
1858Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com>
1859
1860 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1861 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos.
1862 * configure: Re-generate.
1863
1864 * m16.igen (BREAK): Define breakpoint instruction.
1865 (JALX32): Mark instruction as mips16 and not r3900.
1866 * mips.igen (C.cond.fmt): Fix typo in instruction format.
1867
1868 * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1869
1870Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
1871
1872 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1873 insn as a debug breakpoint.
1874
1875 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1876 pending.slot_size.
1877 (PENDING_SCHED): Clean up trace statement.
1878 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1879 (PENDING_FILL): Delay write by only one cycle.
1880 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1881
1882 * sim-main.c (pending_tick): Clean up trace statements. Add trace
1883 of pending writes.
1884 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1885 32 & 64.
1886 (pending_tick): Move incrementing of index to FOR statement.
1887 (pending_tick): Only update PENDING_OUT after a write has occured.
72f4393d 1888
c906108c
SS		 1889 * configure.in: Add explicit mips-lsi-* target. Use gencode to
1890 build simulator.
1891 * configure: Re-generate.
72f4393d 1892
c906108c
SS		 1893 * interp.c (sim_engine_run OLD): Delete explicit call to
1894 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
72f4393d 1895
c906108c
SS		 1896Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com>
1897
1898 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1899 interrupt level number to match changed SignalExceptionInterrupt
1900 macro.
1901
1902Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
1903
1904 * interp.c: #include "itable.h" if WITH_IGEN.
1905 (get_insn_name): New function.
1906 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1907 * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1908
1909Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com>
1910
1911 * configure: Rebuilt to inhale new common/aclocal.m4.
1912
1913Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com>
1914
1915 * dv-tx3904sio.c: Include sim-assert.h.
1916
1917Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com>
1918
1919 * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1920 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1921 Reorganize target-specific sim-hardware checks.
1922 * configure: rebuilt.
1923 * interp.c (sim_open): For tx39 target boards, set
1924 OPERATING_ENVIRONMENT, add tx3904sio devices.
1925 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1926 ROM executables. Install dv-sockser into sim-modules list.
72f4393d 1927
c906108c
SS		 1928 * dv-tx3904irc.c: Compiler warning clean-up.
1929 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly
1930 frequent hw-trace messages.
1931
1932Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com>
1933
1934 * vr.igen (MulAcc): Identify as a vr4100 specific function.
1935
1936Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
1937
1938 * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1939
1940 * vr.igen: New file.
1941 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1942 * mips.igen: Define vr4100 model. Include vr.igen.
1943Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com>
1944
1945 * mips.igen (check_mf_hilo): Correct check.
1946
1947Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
1948
1949 * sim-main.h (interrupt_event): Add prototype.
1950
1951 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1952 register_ptr, register_value.
1953 (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1954
1955 * sim-main.h (tracefh): Make extern.
1956
1957Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com>
1958
1959 * dv-tx3904tmr.c: Deschedule timer event after dispatching.
72f4393d 1960 Reduce unnecessarily high timer event frequency.
c906108c 1961 * dv-tx3904cpu.c: Ditto for interrupt event.
72f4393d 1962
c906108c
SS		 1963Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
1964
1965 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1966 to allay warnings.
1967 (interrupt_event): Made non-static.
72f4393d 1968
c906108c
SS		 1969 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1970 interchange of configuration values for external vs. internal
1971 clock dividers.
72f4393d 1972
c906108c
SS		 1973Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
1974
72f4393d 1975 * mips.igen (BREAK): Moved code to here for
c906108c
SS		 1976 simulator-reserved break instructions.
1977 * gencode.c (build_instruction): Ditto.
1978 * interp.c (signal_exception): Code moved from here. Non-
72f4393d 1979 reserved instructions now use exception vector, rather
c906108c
SS		 1980 than halting sim.
1981 * sim-main.h: Moved magic constants to here.
1982
1983Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
1984
1985 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1986 register upon non-zero interrupt event level, clear upon zero
1987 event value.
1988 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1989 by passing zero event value.
1990 (*_io_{read,write}_buffer): Endianness fixes.
1991 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1992 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1993
1994 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1995 serial I/O and timer module at base address 0xFFFF0000.
72f4393d 1996
c906108c
SS		 1997Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
1998
72f4393d 1999 * mips.igen (SWC1) : Correct the handling of ReverseEndian
c906108c
SS		 2000 and BigEndianCPU.
2001
2002Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
2003
2004 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
2005 parts.
2006 * configure: Update.
2007
2008Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
2009
2010 * dv-tx3904tmr.c: New file - implements tx3904 timer.
2011 * dv-tx3904{irc,cpu}.c: Mild reformatting.
2012 * configure.in: Include tx3904tmr in hw_device list.
2013 * configure: Rebuilt.
2014 * interp.c (sim_open): Instantiate three timer instances.
2015 Fix address typo of tx3904irc instance.
2016
2017Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
2018
2019 * interp.c (signal_exception): SystemCall exception now uses
2020 the exception vector.
2021
2022Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
2023
2024 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
2025 to allay warnings.
2026
2027Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2028
2029 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
2030
2031Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
2032
2033 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
2034
2035 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
2036 sim-main.h. Declare a struct hw_descriptor instead of struct
2037 hw_device_descriptor.
2038
2039Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
2040
2041 * mips.igen (do_store_left, do_load_left): Compute nr of left and
2042 right bits and then re-align left hand bytes to correct byte
2043 lanes. Fix incorrect computation in do_store_left when loading
2044 bytes from second word.
2045
2046Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2047
2048 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
2049 * interp.c (sim_open): Only create a device tree when HW is
2050 enabled.
2051
2052 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
2053 * interp.c (signal_exception): Ditto.
2054
2055Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
2056
2057 * gencode.c: Mark BEGEZALL as LIKELY.
2058
2059Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
2060
2061 * sim-main.h (ALU32_END): Sign extend 32 bit results.
2062 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
72f4393d 2063
c906108c
SS		 2064Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
2065
2066 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
2067 modules. Recognize TX39 target with "mips*tx39" pattern.
2068 * configure: Rebuilt.
2069 * sim-main.h (*): Added many macros defining bits in
2070 TX39 control registers.
2071 (SignalInterrupt): Send actual PC instead of NULL.
2072 (SignalNMIReset): New exception type.
2073 * interp.c (board): New variable for future use to identify
2074 a particular board being simulated.
2075 (mips_option_handler,mips_options): Added "--board" option.
2076 (interrupt_event): Send actual PC.
2077 (sim_open): Make memory layout conditional on board setting.
2078 (signal_exception): Initial implementation of hardware interrupt
2079 handling. Accept another break instruction variant for simulator
2080 exit.
2081 (decode_coproc): Implement RFE instruction for TX39.
2082 (mips.igen): Decode RFE instruction as such.
2083 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
2084 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
2085 bbegin to implement memory map.
2086 * dv-tx3904cpu.c: New file.
2087 * dv-tx3904irc.c: New file.
2088
2089Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
2090
2091 * mips.igen (check_mt_hilo): Create a separate r3900 version.
2092
2093Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
2094
2095 * tx.igen (madd,maddu): Replace calls to check_op_hilo
2096 with calls to check_div_hilo.
2097
2098Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
2099
2100 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
2101 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
72f4393d 2102 Add special r3900 version of do_mult_hilo.
c906108c
SS		 2103 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
2104 with calls to check_mult_hilo.
2105 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
2106 with calls to check_div_hilo.
2107
2108Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
2109
2110 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
2111 Document a replacement.
2112
2113Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
2114
2115 * interp.c (sim_monitor): Make mon_printf work.
2116
2117Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
2118
2119 * sim-main.h (INSN_NAME): New arg `cpu'.
2120
2121Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
2122
72f4393d 2123 * configure: Regenerated to track ../common/aclocal.m4 changes.
c906108c
SS		 2124
2125Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
2126
2127 * configure: Regenerated to track ../common/aclocal.m4 changes.
2128 * config.in: Ditto.
2129
2130Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
2131
2132 * acconfig.h: New file.
2133 * configure.in: Reverted change of Apr 24; use sinclude again.
2134
2135Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
2136
2137 * configure: Regenerated to track ../common/aclocal.m4 changes.
2138 * config.in: Ditto.
2139
2140Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
2141
2142 * configure.in: Don't call sinclude.
2143
2144Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
2145
2146 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
2147
2148Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2149
2150 * mips.igen (ERET): Implement.
2151
2152 * interp.c (decode_coproc): Return sign-extended EPC.
2153
2154 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
2155
2156 * interp.c (signal_exception): Do not ignore Trap.
2157 (signal_exception): On TRAP, restart at exception address.
2158 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
2159 (signal_exception): Update.
2160 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
2161 so that TRAP instructions are caught.
2162
2163Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
2164
2165 * sim-main.h (struct hilo_access, struct hilo_history): Define,
2166 contains HI/LO access history.
2167 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
2168 (HIACCESS, LOACCESS): Delete, replace with
2169 (HIHISTORY, LOHISTORY): New macros.
2170 (CHECKHILO): Delete all, moved to mips.igen
72f4393d 2171
c906108c
SS		 2172 * gencode.c (build_instruction): Do not generate checks for
2173 correct HI/LO register usage.
2174
2175 * interp.c (old_engine_run): Delete checks for correct HI/LO
2176 register usage.
2177
2178 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
2179 check_mf_cycles): New functions.
2180 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
2181 do_divu, domultx, do_mult, do_multu): Use.
2182
2183 * tx.igen ("madd", "maddu"): Use.
72f4393d 2184
c906108c
SS		 2185Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
2186
2187 * mips.igen (DSRAV): Use function do_dsrav.
2188 (SRAV): Use new function do_srav.
2189
2190 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
2191 (B): Sign extend 11 bit immediate.
2192 (EXT-B*): Shift 16 bit immediate left by 1.
2193 (ADDIU*): Don't sign extend immediate value.
2194
2195Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2196
2197 * m16run.c (sim_engine_run): Restore CIA after handling an event.
2198
2199 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
2200 functions.
2201
2202 * mips.igen (delayslot32, nullify_next_insn): New functions.
2203 (m16.igen): Always include.
2204 (do_*): Add more tracing.
2205
2206 * m16.igen (delayslot16): Add NIA argument, could be called by a
2207 32 bit MIPS16 instruction.
72f4393d 2208
c906108c
SS		 2209 * interp.c (ifetch16): Move function from here.
2210 * sim-main.c (ifetch16): To here.
72f4393d 2211
c906108c
SS		 2212 * sim-main.c (ifetch16, ifetch32): Update to match current
2213 implementations of LH, LW.
2214 (signal_exception): Don't print out incorrect hex value of illegal
2215 instruction.
2216
2217Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2218
2219 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
2220 instruction.
2221
2222 * m16.igen: Implement MIPS16 instructions.
72f4393d 2223
c906108c
SS		 2224 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
2225 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
2226 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
2227 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
2228 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
2229 bodies of corresponding code from 32 bit insn to these. Also used
2230 by MIPS16 versions of functions.
72f4393d 2231
c906108c
SS		 2232 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
2233 (IMEM16): Drop NR argument from macro.
2234
2235Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2236
2237 * Makefile.in (SIM_OBJS): Add sim-main.o.
2238
2239 * sim-main.h (address_translation, load_memory, store_memory,
2240 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
2241 as INLINE_SIM_MAIN.
2242 (pr_addr, pr_uword64): Declare.
2243 (sim-main.c): Include when H_REVEALS_MODULE_P.
72f4393d 2244
c906108c
SS		 2245 * interp.c (address_translation, load_memory, store_memory,
2246 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
2247 from here.
2248 * sim-main.c: To here. Fix compilation problems.
72f4393d 2249
c906108c
SS		 2250 * configure.in: Enable inlining.
2251 * configure: Re-config.
2252
2253Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
2254
2255 * configure: Regenerated to track ../common/aclocal.m4 changes.
2256
2257Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2258
2259 * mips.igen: Include tx.igen.
2260 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
2261 * tx.igen: New file, contains MADD and MADDU.
2262
2263 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
2264 the hardwired constant `7'.
2265 (store_memory): Ditto.
2266 (LOADDRMASK): Move definition to sim-main.h.
2267
2268 mips.igen (MTC0): Enable for r3900.
2269 (ADDU): Add trace.
2270
2271 mips.igen (do_load_byte): Delete.
2272 (do_load, do_store, do_load_left, do_load_write, do_store_left,
2273 do_store_right): New functions.
2274 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
2275
2276 configure.in: Let the tx39 use igen again.
2277 configure: Update.
72f4393d 2278
c906108c
SS		 2279Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
2280
2281 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
2282 not an address sized quantity. Return zero for cache sizes.
2283
2284Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
2285
2286 * mips.igen (r3900): r3900 does not support 64 bit integer
2287 operations.
2288
2289Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
2290
2291 * configure.in (mipstx39*-*-*): Use gencode simulator rather
2292 than igen one.
2293 * configure : Rebuild.
72f4393d 2294
c906108c
SS		 2295Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
2296
2297 * configure: Regenerated to track ../common/aclocal.m4 changes.
2298
2299Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2300
2301 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
2302
2303Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
2304
2305 * configure: Regenerated to track ../common/aclocal.m4 changes.
2306 * config.in: Regenerated to track ../common/aclocal.m4 changes.
2307
2308Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2309
2310 * configure: Regenerated to track ../common/aclocal.m4 changes.
2311
2312Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
2313
2314 * interp.c (Max, Min): Comment out functions. Not yet used.
2315
2316Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
2317
2318 * configure: Regenerated to track ../common/aclocal.m4 changes.
2319
2320Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
2321
2322 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
2323 configurable settings for stand-alone simulator.
72f4393d 2324
c906108c 2325 * configure.in: Added X11 search, just in case.
72f4393d 2326
c906108c
SS		 2327 * configure: Regenerated.
2328
2329Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
2330
2331 * interp.c (sim_write, sim_read, load_memory, store_memory):
2332 Replace sim_core_*_map with read_map, write_map, exec_map resp.
2333
2334Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
2335
2336 * sim-main.h (GETFCC): Return an unsigned value.
2337
2338Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2339
2340 * mips.igen (DIV): Fix check for -1 / MIN_INT.
2341 (DADD): Result destination is RD not RT.
2342
2343Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
2344
2345 * sim-main.h (HIACCESS, LOACCESS): Always define.
2346
2347 * mdmx.igen (Maxi, Mini): Rename Max, Min.
2348
2349 * interp.c (sim_info): Delete.
2350
2351Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
2352
2353 * interp.c (DECLARE_OPTION_HANDLER): Use it.
2354 (mips_option_handler): New argument `cpu'.
2355 (sim_open): Update call to sim_add_option_table.
2356
2357Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
2358
2359 * mips.igen (CxC1): Add tracing.
2360
2361Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
2362
2363 * sim-main.h (Max, Min): Declare.
2364
2365 * interp.c (Max, Min): New functions.
2366
2367 * mips.igen (BC1): Add tracing.
72f4393d 2368
c906108c 2369Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
72f4393d 2370
c906108c 2371 * interp.c Added memory map for stack in vr4100
72f4393d 2372
c906108c
SS		 2373Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
2374
2375 * interp.c (load_memory): Add missing "break"'s.
2376
2377Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
2378
2379 * interp.c (sim_store_register, sim_fetch_register): Pass in
2380 length parameter. Return -1.
2381
2382Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
2383
2384 * interp.c: Added hardware init hook, fixed warnings.
2385
2386Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
2387
2388 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
2389
2390Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
2391
2392 * interp.c (ifetch16): New function.
2393
2394 * sim-main.h (IMEM32): Rename IMEM.
2395 (IMEM16_IMMED): Define.
2396 (IMEM16): Define.
2397 (DELAY_SLOT): Update.
72f4393d 2398
c906108c 2399 * m16run.c (sim_engine_run): New file.
72f4393d 2400
c906108c
SS		 2401 * m16.igen: All instructions except LB.
2402 (LB): Call do_load_byte.
2403 * mips.igen (do_load_byte): New function.
2404 (LB): Call do_load_byte.
2405
2406 * mips.igen: Move spec for insn bit size and high bit from here.
2407 * Makefile.in (tmp-igen, tmp-m16): To here.
2408
2409 * m16.dc: New file, decode mips16 instructions.
2410
2411 * Makefile.in (SIM_NO_ALL): Define.
2412 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
2413
2414Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
2415
2416 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
2417 point unit to 32 bit registers.
2418 * configure: Re-generate.
2419
2420Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
2421
2422 * configure.in (sim_use_gen): Make IGEN the default simulator
2423 generator for generic 32 and 64 bit mips targets.
2424 * configure: Re-generate.
2425
2426Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
2427
2428 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
2429 bitsize.
2430
2431 * interp.c (sim_fetch_register, sim_store_register): Read/write
2432 FGR from correct location.
2433 (sim_open): Set size of FGR's according to
2434 WITH_TARGET_FLOATING_POINT_BITSIZE.
72f4393d 2435
c906108c
SS		 2436 * sim-main.h (FGR): Store floating point registers in a separate
2437 array.
2438
2439Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
2440
2441 * configure: Regenerated to track ../common/aclocal.m4 changes.
2442
2443Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
2444
2445 * interp.c (ColdReset): Call PENDING_INVALIDATE.
2446
2447 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
2448
2449 * interp.c (pending_tick): New function. Deliver pending writes.
2450
2451 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
2452 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
2453 it can handle mixed sized quantites and single bits.
72f4393d 2454
c906108c
SS		 2455Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
2456
2457 * interp.c (oengine.h): Do not include when building with IGEN.
2458 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
2459 (sim_info): Ditto for PROCESSOR_64BIT.
2460 (sim_monitor): Replace ut_reg with unsigned_word.
2461 (*): Ditto for t_reg.
2462 (LOADDRMASK): Define.
2463 (sim_open): Remove defunct check that host FP is IEEE compliant,
2464 using software to emulate floating point.
2465 (value_fpr, ...): Always compile, was conditional on HASFPU.
2466
2467Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
2468
2469 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
2470 size.
2471
2472 * interp.c (SD, CPU): Define.
2473 (mips_option_handler): Set flags in each CPU.
2474 (interrupt_event): Assume CPU 0 is the one being iterrupted.
2475 (sim_close): Do not clear STATE, deleted anyway.
2476 (sim_write, sim_read): Assume CPU zero's vm should be used for
2477 data transfers.
2478 (sim_create_inferior): Set the PC for all processors.
2479 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
2480 argument.
2481 (mips16_entry): Pass correct nr of args to store_word, load_word.
2482 (ColdReset): Cold reset all cpu's.
2483 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
2484 (sim_monitor, load_memory, store_memory, signal_exception): Use
2485 `CPU' instead of STATE_CPU.
2486
2487
2488 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
2489 SD or CPU_.
72f4393d 2490
c906108c
SS		 2491 * sim-main.h (signal_exception): Add sim_cpu arg.
2492 (SignalException*): Pass both SD and CPU to signal_exception.
2493 * interp.c (signal_exception): Update.
72f4393d 2494
c906108c
SS		 2495 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
2496 Ditto
2497 (sync_operation, prefetch, cache_op, store_memory, load_memory,
2498 address_translation): Ditto
2499 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
72f4393d 2500
c906108c
SS		 2501Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
2502
2503 * configure: Regenerated to track ../common/aclocal.m4 changes.
2504
2505Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
2506
2507 * interp.c (sim_engine_run): Add `nr_cpus' argument.
2508
72f4393d 2509 * mips.igen (model): Map processor names onto BFD name.
c906108c
SS		 2510
2511 * sim-main.h (CPU_CIA): Delete.
2512 (SET_CIA, GET_CIA): Define
2513
2514Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
2515
2516 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
2517 regiser.
2518
2519 * configure.in (default_endian): Configure a big-endian simulator
2520 by default.
2521 * configure: Re-generate.
72f4393d 2522
c906108c
SS		 2523Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
2524
2525 * configure: Regenerated to track ../common/aclocal.m4 changes.
2526
2527Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
2528
2529 * interp.c (sim_monitor): Handle Densan monitor outbyte
2530 and inbyte functions.
2531
25321997-12-29 Felix Lee <flee@cygnus.com>
2533
2534 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
2535
2536Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
2537
2538 * Makefile.in (tmp-igen): Arrange for $zero to always be
2539 reset to zero after every instruction.
2540
2541Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2542
2543 * configure: Regenerated to track ../common/aclocal.m4 changes.
2544 * config.in: Ditto.
2545
2546Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
2547
2548 * mips.igen (MSUB): Fix to work like MADD.
2549 * gencode.c (MSUB): Similarly.
2550
2551Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
2552
2553 * configure: Regenerated to track ../common/aclocal.m4 changes.
2554
2555Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2556
2557 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
2558
2559Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2560
2561 * sim-main.h (sim-fpu.h): Include.
2562
2563 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
2564 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
2565 using host independant sim_fpu module.
2566
2567Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
2568
2569 * interp.c (signal_exception): Report internal errors with SIGABRT
2570 not SIGQUIT.
2571
2572 * sim-main.h (C0_CONFIG): New register.
2573 (signal.h): No longer include.
2574
2575 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
2576
2577Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
2578
2579 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2580
2581Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2582
2583 * mips.igen: Tag vr5000 instructions.
2584 (ANDI): Was missing mipsIV model, fix assembler syntax.
2585 (do_c_cond_fmt): New function.
2586 (C.cond.fmt): Handle mips I-III which do not support CC field
2587 separatly.
2588 (bc1): Handle mips IV which do not have a delaed FCC separatly.
2589 (SDR): Mask paddr when BigEndianMem, not the converse as specified
2590 in IV3.2 spec.
2591 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
2592 vr5000 which saves LO in a GPR separatly.
72f4393d 2593
c906108c
SS		 2594 * configure.in (enable-sim-igen): For vr5000, select vr5000
2595 specific instructions.
2596 * configure: Re-generate.
72f4393d 2597
c906108c
SS		 2598Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
2599
2600 * Makefile.in (SIM_OBJS): Add sim-fpu module.
2601
2602 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2603 fmt_uninterpreted_64 bit cases to switch. Convert to
2604 fmt_formatted,
2605
2606 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2607
2608 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2609 as specified in IV3.2 spec.
2610 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2611
2612Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
2613
2614 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2615 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2616 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2617 PENDING_FILL versions of instructions. Simplify.
2618 (X): New function.
2619 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2620 instructions.
2621 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2622 a signed value.
2623 (MTHI, MFHI): Disable code checking HI-LO.
72f4393d 2624
c906108c
SS		 2625 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2626 global.
2627 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2628
2629Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
2630
2631 * gencode.c (build_mips16_operands): Replace IPC with cia.
2632
2633 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2634 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2635 IPC to `cia'.
2636 (UndefinedResult): Replace function with macro/function
2637 combination.
2638 (sim_engine_run): Don't save PC in IPC.
2639
2640 * sim-main.h (IPC): Delete.
2641
2642
2643 * interp.c (signal_exception, store_word, load_word,
2644 address_translation, load_memory, store_memory, cache_op,
2645 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2646 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2647 current instruction address - cia - argument.
2648 (sim_read, sim_write): Call address_translation directly.
2649 (sim_engine_run): Rename variable vaddr to cia.
2650 (signal_exception): Pass cia to sim_monitor
72f4393d 2651
c906108c
SS		 2652 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2653 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2654 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2655
2656 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2657 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2658 SIM_ASSERT.
72f4393d 2659
c906108c
SS		 2660 * interp.c (signal_exception): Pass restart address to
2661 sim_engine_restart.
2662
2663 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2664 idecode.o): Add dependency.
2665
2666 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2667 Delete definitions
2668 (DELAY_SLOT): Update NIA not PC with branch address.
2669 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2670
2671 * mips.igen: Use CIA not PC in branch calculations.
2672 (illegal): Call SignalException.
2673 (BEQ, ADDIU): Fix assembler.
2674
2675Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2676
2677 * m16.igen (JALX): Was missing.
2678
2679 * configure.in (enable-sim-igen): New configuration option.
2680 * configure: Re-generate.
72f4393d 2681
c906108c
SS		 2682 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2683
2684 * interp.c (load_memory, store_memory): Delete parameter RAW.
2685 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2686 bypassing {load,store}_memory.
2687
2688 * sim-main.h (ByteSwapMem): Delete definition.
2689
2690 * Makefile.in (SIM_OBJS): Add sim-memopt module.
2691
2692 * interp.c (sim_do_command, sim_commands): Delete mips specific
2693 commands. Handled by module sim-options.
72f4393d 2694
c906108c
SS		 2695 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2696 (WITH_MODULO_MEMORY): Define.
2697
2698 * interp.c (sim_info): Delete code printing memory size.
2699
2700 * interp.c (mips_size): Nee sim_size, delete function.
2701 (power2): Delete.
2702 (monitor, monitor_base, monitor_size): Delete global variables.
2703 (sim_open, sim_close): Delete code creating monitor and other
2704 memory regions. Use sim-memopts module, via sim_do_commandf, to
2705 manage memory regions.
2706 (load_memory, store_memory): Use sim-core for memory model.
72f4393d 2707
c906108c
SS		 2708 * interp.c (address_translation): Delete all memory map code
2709 except line forcing 32 bit addresses.
2710
2711Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
2712
2713 * sim-main.h (WITH_TRACE): Delete definition. Enables common
2714 trace options.
2715
2716 * interp.c (logfh, logfile): Delete globals.
2717 (sim_open, sim_close): Delete code opening & closing log file.
2718 (mips_option_handler): Delete -l and -n options.
2719 (OPTION mips_options): Ditto.
2720
2721 * interp.c (OPTION mips_options): Rename option trace to dinero.
2722 (mips_option_handler): Update.
2723
2724Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2725
2726 * interp.c (fetch_str): New function.
2727 (sim_monitor): Rewrite using sim_read & sim_write.
2728 (sim_open): Check magic number.
2729 (sim_open): Write monitor vectors into memory using sim_write.
2730 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2731 (sim_read, sim_write): Simplify - transfer data one byte at a
2732 time.
2733 (load_memory, store_memory): Clarify meaning of parameter RAW.
2734
2735 * sim-main.h (isHOST): Defete definition.
2736 (isTARGET): Mark as depreciated.
2737 (address_translation): Delete parameter HOST.
2738
2739 * interp.c (address_translation): Delete parameter HOST.
2740
2741Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
2742
72f4393d 2743 * mips.igen:
c906108c
SS		 2744
2745 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2746 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2747
2748Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
2749
2750 * mips.igen: Add model filter field to records.
2751
2752Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2753
2754 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
72f4393d 2755
c906108c
SS		 2756 interp.c (sim_engine_run): Do not compile function sim_engine_run
2757 when WITH_IGEN == 1.
2758
2759 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2760 target architecture.
2761
2762 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2763 igen. Replace with configuration variables sim_igen_flags /
2764 sim_m16_flags.
2765
2766 * m16.igen: New file. Copy mips16 insns here.
2767 * mips.igen: From here.
2768
2769Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
2770
2771 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2772 to top.
2773 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2774
2775Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
2776
2777 * gencode.c (build_instruction): Follow sim_write's lead in using
2778 BigEndianMem instead of !ByteSwapMem.
2779
2780Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
2781
2782 * configure.in (sim_gen): Dependent on target, select type of
2783 generator. Always select old style generator.
2784
2785 configure: Re-generate.
2786
2787 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2788 targets.
2789 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2790 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2791 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2792 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2793 SIM_@sim_gen@_*, set by autoconf.
72f4393d 2794
c906108c
SS		 2795Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
2796
2797 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2798
2799 * interp.c (ColdReset): Remove #ifdef HASFPU, check
2800 CURRENT_FLOATING_POINT instead.
2801
2802 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2803 (address_translation): Raise exception InstructionFetch when
2804 translation fails and isINSTRUCTION.
72f4393d 2805
c906108c
SS		 2806 * interp.c (sim_open, sim_write, sim_monitor, store_word,
2807 sim_engine_run): Change type of of vaddr and paddr to
2808 address_word.
2809 (address_translation, prefetch, load_memory, store_memory,
2810 cache_op): Change type of vAddr and pAddr to address_word.
2811
2812 * gencode.c (build_instruction): Change type of vaddr and paddr to
2813 address_word.
2814
2815Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
2816
2817 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2818 macro to obtain result of ALU op.
2819
2820Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
2821
2822 * interp.c (sim_info): Call profile_print.
2823
2824Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2825
2826 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2827
2828 * sim-main.h (WITH_PROFILE): Do not define, defined in
2829 common/sim-config.h. Use sim-profile module.
2830 (simPROFILE): Delete defintion.
2831
2832 * interp.c (PROFILE): Delete definition.
2833 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2834 (sim_close): Delete code writing profile histogram.
2835 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2836 Delete.
2837 (sim_engine_run): Delete code profiling the PC.
2838
2839Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2840
2841 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2842
2843 * interp.c (sim_monitor): Make register pointers of type
2844 unsigned_word*.
2845
2846 * sim-main.h: Make registers of type unsigned_word not
2847 signed_word.
2848
2849Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2850
2851 * interp.c (sync_operation): Rename from SyncOperation, make
2852 global, add SD argument.
2853 (prefetch): Rename from Prefetch, make global, add SD argument.
2854 (decode_coproc): Make global.
2855
2856 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2857
2858 * gencode.c (build_instruction): Generate DecodeCoproc not
2859 decode_coproc calls.
2860
2861 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2862 (SizeFGR): Move to sim-main.h
2863 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2864 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2865 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2866 sim-main.h.
2867 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2868 FP_RM_TOMINF, GETRM): Move to sim-main.h.
2869 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2870 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2871 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2872 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
72f4393d 2873
c906108c
SS		 2874 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2875 exception.
2876 (sim-alu.h): Include.
2877 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2878 (sim_cia): Typedef to instruction_address.
72f4393d 2879
c906108c
SS		 2880Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
2881
2882 * Makefile.in (interp.o): Rename generated file engine.c to
2883 oengine.c.
72f4393d 2884
c906108c 2885 * interp.c: Update.
72f4393d 2886
c906108c
SS		 2887Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
2888
2889 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
72f4393d 2890
c906108c
SS		 2891Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
2892
2893 * gencode.c (build_instruction): For "FPSQRT", output correct
2894 number of arguments to Recip.
72f4393d 2895
c906108c
SS		 2896Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
2897
2898 * Makefile.in (interp.o): Depends on sim-main.h
2899
2900 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2901
2902 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2903 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2904 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2905 STATE, DSSTATE): Define
2906 (GPR, FGRIDX, ..): Define.
2907
2908 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2909 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2910 (GPR, FGRIDX, ...): Delete macros.
72f4393d 2911
c906108c 2912 * interp.c: Update names to match defines from sim-main.h
72f4393d 2913
c906108c
SS		 2914Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
2915
2916 * interp.c (sim_monitor): Add SD argument.
2917 (sim_warning): Delete. Replace calls with calls to
2918 sim_io_eprintf.
2919 (sim_error): Delete. Replace calls with sim_io_error.
2920 (open_trace, writeout32, writeout16, getnum): Add SD argument.
2921 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2922 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2923 argument.
2924 (mips_size): Rename from sim_size. Add SD argument.
2925
2926 * interp.c (simulator): Delete global variable.
2927 (callback): Delete global variable.
2928 (mips_option_handler, sim_open, sim_write, sim_read,
2929 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2930 sim_size,sim_monitor): Use sim_io_* not callback->*.
2931 (sim_open): ZALLOC simulator struct.
2932 (PROFILE): Do not define.
2933
2934Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2935
2936 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2937 support.h with corresponding code.
2938
2939 * sim-main.h (word64, uword64), support.h: Move definition to
2940 sim-main.h.
2941 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2942
2943 * support.h: Delete
2944 * Makefile.in: Update dependencies
2945 * interp.c: Do not include.
72f4393d 2946
c906108c
SS		 2947Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
2948
2949 * interp.c (address_translation, load_memory, store_memory,
2950 cache_op): Rename to from AddressTranslation et.al., make global,
2951 add SD argument
72f4393d 2952
c906108c
SS		 2953 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2954 CacheOp): Define.
72f4393d 2955
c906108c
SS		 2956 * interp.c (SignalException): Rename to signal_exception, make
2957 global.
2958
2959 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
72f4393d 2960
c906108c
SS		 2961 * sim-main.h (SignalException, SignalExceptionInterrupt,
2962 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2963 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2964 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2965 Define.
72f4393d 2966
c906108c 2967 * interp.c, support.h: Use.
72f4393d 2968
c906108c
SS		 2969Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
2970
2971 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2972 to value_fpr / store_fpr. Add SD argument.
2973 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2974 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2975
2976 * sim-main.h (ValueFPR, StoreFPR): Define.
72f4393d 2977
c906108c
SS		 2978Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
2979
2980 * interp.c (sim_engine_run): Check consistency between configure
2981 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2982 and HASFPU.
2983
2984 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
72f4393d 2985 (mips_fpu): Configure WITH_FLOATING_POINT.
c906108c
SS		 2986 (mips_endian): Configure WITH_TARGET_ENDIAN.
2987 * configure: Update.
2988
2989Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
2990
2991 * configure: Regenerated to track ../common/aclocal.m4 changes.
2992
2993Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
2994
2995 * configure: Regenerated.
2996
2997Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
2998
2999 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
3000
3001Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3002
3003 * gencode.c (print_igen_insn_models): Assume certain architectures
3004 include all mips* instructions.
3005 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
3006 instruction.
3007
3008 * Makefile.in (tmp.igen): Add target. Generate igen input from
3009 gencode file.
3010
3011 * gencode.c (FEATURE_IGEN): Define.
3012 (main): Add --igen option. Generate output in igen format.
3013 (process_instructions): Format output according to igen option.
3014 (print_igen_insn_format): New function.
3015 (print_igen_insn_models): New function.
3016 (process_instructions): Only issue warnings and ignore
3017 instructions when no FEATURE_IGEN.
3018
3019Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3020
3021 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
3022 MIPS targets.
3023
3024Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3025
3026 * configure: Regenerated to track ../common/aclocal.m4 changes.
3027
3028Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
3029
3030 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
3031 SIM_RESERVED_BITS): Delete, moved to common.
3032 (SIM_EXTRA_CFLAGS): Update.
72f4393d 3033
c906108c
SS		 3034Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
3035
3036 * configure.in: Configure non-strict memory alignment.
3037 * configure: Regenerated to track ../common/aclocal.m4 changes.
3038
3039Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
3040
3041 * configure: Regenerated to track ../common/aclocal.m4 changes.
3042
3043Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
3044
3045 * gencode.c (SDBBP,DERET): Added (3900) insns.
3046 (RFE): Turn on for 3900.
3047 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
3048 (dsstate): Made global.
3049 (SUBTARGET_R3900): Added.
3050 (CANCELDELAYSLOT): New.
3051 (SignalException): Ignore SystemCall rather than ignore and
3052 terminate. Add DebugBreakPoint handling.
3053 (decode_coproc): New insns RFE, DERET; and new registers Debug
3054 and DEPC protected by SUBTARGET_R3900.
3055 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
3056 bits explicitly.
3057 * Makefile.in,configure.in: Add mips subtarget option.
72f4393d 3058 * configure: Update.
c906108c
SS		 3059
3060Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
3061
3062 * gencode.c: Add r3900 (tx39).
72f4393d 3063
c906108c
SS		 3064
3065Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
3066
3067 * gencode.c (build_instruction): Don't need to subtract 4 for
3068 JALR, just 2.
3069
3070Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
3071
3072 * interp.c: Correct some HASFPU problems.
3073
3074Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
3075
3076 * configure: Regenerated to track ../common/aclocal.m4 changes.
3077
3078Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
3079
3080 * interp.c (mips_options): Fix samples option short form, should
3081 be `x'.
3082
3083Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
3084
3085 * interp.c (sim_info): Enable info code. Was just returning.
3086
3087Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
3088
3089 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
3090 MFC0.
3091
3092Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
3093
3094 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
3095 constants.
3096 (build_instruction): Ditto for LL.
3097
3098Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
3099
3100 * configure: Regenerated to track ../common/aclocal.m4 changes.
3101
3102Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3103
3104 * configure: Regenerated to track ../common/aclocal.m4 changes.
3105 * config.in: Ditto.
3106
3107Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
3108
3109 * interp.c (sim_open): Add call to sim_analyze_program, update
3110 call to sim_config.
3111
3112Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
3113
3114 * interp.c (sim_kill): Delete.
3115 (sim_create_inferior): Add ABFD argument. Set PC from same.
3116 (sim_load): Move code initializing trap handlers from here.
3117 (sim_open): To here.
3118 (sim_load): Delete, use sim-hload.c.
3119
3120 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
3121
3122Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
3123
3124 * configure: Regenerated to track ../common/aclocal.m4 changes.
3125 * config.in: Ditto.
3126
3127Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3128
3129 * interp.c (sim_open): Add ABFD argument.
3130 (sim_load): Move call to sim_config from here.
3131 (sim_open): To here. Check return status.
3132
3133Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
72f4393d 3134
c906108c
SS		 3135 * gencode.c (build_instruction): Two arg MADD should
3136 not assign result to $0.
72f4393d 3137
c906108c
SS		 3138Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
3139
3140 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
3141 * sim/mips/configure.in: Regenerate.
3142
3143Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
3144
3145 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
3146 signed8, unsigned8 et.al. types.
3147
3148 * interp.c (SUB_REG_FETCH): Handle both little and big endian
3149 hosts when selecting subreg.
3150
3151Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
3152
3153 * interp.c (sim_engine_run): Reset the ZERO register to zero
3154 regardless of FEATURE_WARN_ZERO.
3155 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
3156
3157Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
3158
3159 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
3160 (SignalException): For BreakPoints ignore any mode bits and just
3161 save the PC.
3162 (SignalException): Always set the CAUSE register.
3163
3164Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
3165
3166 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
3167 exception has been taken.
3168
3169 * interp.c: Implement the ERET and mt/f sr instructions.
3170
3171Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
3172
3173 * interp.c (SignalException): Don't bother restarting an
3174 interrupt.
3175
3176Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
3177
3178 * interp.c (SignalException): Really take an interrupt.
3179 (interrupt_event): Only deliver interrupts when enabled.
3180
3181Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
3182
3183 * interp.c (sim_info): Only print info when verbose.
3184 (sim_info) Use sim_io_printf for output.
72f4393d 3185
c906108c
SS		 3186Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3187
3188 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
3189 mips architectures.
3190
3191Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
3192
3193 * interp.c (sim_do_command): Check for common commands if a
3194 simulator specific command fails.
3195
3196Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
3197
3198 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
3199 and simBE when DEBUG is defined.
3200
3201Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
3202
3203 * interp.c (interrupt_event): New function. Pass exception event
3204 onto exception handler.
3205
3206 * configure.in: Check for stdlib.h.
3207 * configure: Regenerate.
3208
3209 * gencode.c (build_instruction): Add UNUSED attribute to tempS
3210 variable declaration.
3211 (build_instruction): Initialize memval1.
3212 (build_instruction): Add UNUSED attribute to byte, bigend,
3213 reverse.
3214 (build_operands): Ditto.
3215
3216 * interp.c: Fix GCC warnings.
3217 (sim_get_quit_code): Delete.
3218
3219 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
3220 * Makefile.in: Ditto.
3221 * configure: Re-generate.
72f4393d 3222
c906108c
SS		 3223 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
3224
3225Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
3226
3227 * interp.c (mips_option_handler): New function parse argumes using
3228 sim-options.
3229 (myname): Replace with STATE_MY_NAME.
3230 (sim_open): Delete check for host endianness - performed by
3231 sim_config.
3232 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
3233 (sim_open): Move much of the initialization from here.
3234 (sim_load): To here. After the image has been loaded and
3235 endianness set.
3236 (sim_open): Move ColdReset from here.
3237 (sim_create_inferior): To here.
3238 (sim_open): Make FP check less dependant on host endianness.
3239
3240 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
3241 run.
3242 * interp.c (sim_set_callbacks): Delete.
3243
3244 * interp.c (membank, membank_base, membank_size): Replace with
3245 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
3246 (sim_open): Remove call to callback->init. gdb/run do this.
3247
3248 * interp.c: Update
3249
3250 * sim-main.h (SIM_HAVE_FLATMEM): Define.
3251
3252 * interp.c (big_endian_p): Delete, replaced by
3253 current_target_byte_order.
3254
3255Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
3256
3257 * interp.c (host_read_long, host_read_word, host_swap_word,
3258 host_swap_long): Delete. Using common sim-endian.
3259 (sim_fetch_register, sim_store_register): Use H2T.
3260 (pipeline_ticks): Delete. Handled by sim-events.
3261 (sim_info): Update.
3262 (sim_engine_run): Update.
3263
3264Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
3265
3266 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
3267 reason from here.
3268 (SignalException): To here. Signal using sim_engine_halt.
3269 (sim_stop_reason): Delete, moved to common.
72f4393d 3270
c906108c
SS		 3271Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
3272
3273 * interp.c (sim_open): Add callback argument.
3274 (sim_set_callbacks): Delete SIM_DESC argument.
3275 (sim_size): Ditto.
3276
3277Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
3278
3279 * Makefile.in (SIM_OBJS): Add common modules.
3280
3281 * interp.c (sim_set_callbacks): Also set SD callback.
3282 (set_endianness, xfer_*, swap_*): Delete.
3283 (host_read_word, host_read_long, host_swap_word, host_swap_long):
3284 Change to functions using sim-endian macros.
3285 (control_c, sim_stop): Delete, use common version.
3286 (simulate): Convert into.
3287 (sim_engine_run): This function.
3288 (sim_resume): Delete.
72f4393d 3289
c906108c
SS		 3290 * interp.c (simulation): New variable - the simulator object.
3291 (sim_kind): Delete global - merged into simulation.
3292 (sim_load): Cleanup. Move PC assignment from here.
3293 (sim_create_inferior): To here.
3294
3295 * sim-main.h: New file.
3296 * interp.c (sim-main.h): Include.
72f4393d 3297
c906108c
SS		 3298Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
3299
3300 * configure: Regenerated to track ../common/aclocal.m4 changes.
3301
3302Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
3303
3304 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
3305
3306Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
3307
72f4393d
L		 3308 * gencode.c (build_instruction): DIV instructions: check
3309 for division by zero and integer overflow before using
c906108c
SS		 3310 host's division operation.
3311
3312Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
3313
3314 * Makefile.in (SIM_OBJS): Add sim-load.o.
3315 * interp.c: #include bfd.h.
3316 (target_byte_order): Delete.
3317 (sim_kind, myname, big_endian_p): New static locals.
3318 (sim_open): Set sim_kind, myname. Move call to set_endianness to
3319 after argument parsing. Recognize -E arg, set endianness accordingly.
3320 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
3321 load file into simulator. Set PC from bfd.
3322 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
3323 (set_endianness): Use big_endian_p instead of target_byte_order.
3324
3325Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
3326
3327 * interp.c (sim_size): Delete prototype - conflicts with
3328 definition in remote-sim.h. Correct definition.
3329
3330Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3331
3332 * configure: Regenerated to track ../common/aclocal.m4 changes.
3333 * config.in: Ditto.
3334
3335Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
3336
3337 * interp.c (sim_open): New arg `kind'.
3338
3339 * configure: Regenerated to track ../common/aclocal.m4 changes.
3340
3341Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3342
3343 * configure: Regenerated to track ../common/aclocal.m4 changes.
3344
3345Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
3346
3347 * interp.c (sim_open): Set optind to 0 before calling getopt.
3348
3349Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3350
3351 * configure: Regenerated to track ../common/aclocal.m4 changes.
3352
3353Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
3354
3355 * interp.c : Replace uses of pr_addr with pr_uword64
3356 where the bit length is always 64 independent of SIM_ADDR.
3357 (pr_uword64) : added.
3358
3359Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
3360
3361 * configure: Re-generate.
3362
3363Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
3364
3365 * configure: Regenerate to track ../common/aclocal.m4 changes.
3366
3367Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
3368
3369 * interp.c (sim_open): New SIM_DESC result. Argument is now
3370 in argv form.
3371 (other sim_*): New SIM_DESC argument.
3372
3373Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
3374
3375 * interp.c: Fix printing of addresses for non-64-bit targets.
3376 (pr_addr): Add function to print address based on size.
3377
3378Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
3379
3380 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
3381
3382Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
3383
3384 * gencode.c (build_mips16_operands): Correct computation of base
3385 address for extended PC relative instruction.
3386
3387Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
3388
3389 * interp.c (mips16_entry): Add support for floating point cases.
3390 (SignalException): Pass floating point cases to mips16_entry.
3391 (ValueFPR): Don't restrict fmt_single and fmt_word to even
3392 registers.
3393 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
3394 or fmt_word.
3395 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
3396 and then set the state to fmt_uninterpreted.
3397 (COP_SW): Temporarily set the state to fmt_word while calling
3398 ValueFPR.
3399
3400Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
3401
3402 * gencode.c (build_instruction): The high order may be set in the
3403 comparison flags at any ISA level, not just ISA 4.
3404
3405Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
3406
3407 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
3408 COMMON_{PRE,POST}_CONFIG_FRAG instead.
3409 * configure.in: sinclude ../common/aclocal.m4.
3410 * configure: Regenerated.
3411
3412Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
3413
3414 * configure: Rebuild after change to aclocal.m4.
3415
3416Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
3417
3418 * configure configure.in Makefile.in: Update to new configure
3419 scheme which is more compatible with WinGDB builds.
3420 * configure.in: Improve comment on how to run autoconf.
3421 * configure: Re-run autoconf to get new ../common/aclocal.m4.
3422 * Makefile.in: Use autoconf substitution to install common
3423 makefile fragment.
3424
3425Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
3426
3427 * gencode.c (build_instruction): Use BigEndianCPU instead of
3428 ByteSwapMem.
3429
3430Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
3431
3432 * interp.c (sim_monitor): Make output to stdout visible in
3433 wingdb's I/O log window.
3434
3435Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
3436
3437 * support.h: Undo previous change to SIGTRAP
3438 and SIGQUIT values.
3439
3440Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
3441
3442 * interp.c (store_word, load_word): New static functions.
3443 (mips16_entry): New static function.
3444 (SignalException): Look for mips16 entry and exit instructions.
3445 (simulate): Use the correct index when setting fpr_state after
3446 doing a pending move.
3447
3448Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
3449
3450 * interp.c: Fix byte-swapping code throughout to work on
3451 both little- and big-endian hosts.
3452
3453Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
3454
3455 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
3456 with gdb/config/i386/xm-windows.h.
3457
3458Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
3459
3460 * gencode.c (build_instruction): Work around MSVC++ code gen bug
3461 that messes up arithmetic shifts.
3462
3463Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
3464
3465 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
3466 SIGTRAP and SIGQUIT for _WIN32.
3467
3468Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
3469
3470 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
3471 force a 64 bit multiplication.
3472 (build_instruction) [OR]: In mips16 mode, don't do anything if the
3473 destination register is 0, since that is the default mips16 nop
3474 instruction.
3475
3476Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
3477
3478 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
3479 (build_endian_shift): Don't check proc64.
3480 (build_instruction): Always set memval to uword64. Cast op2 to
3481 uword64 when shifting it left in memory instructions. Always use
3482 the same code for stores--don't special case proc64.
3483
3484 * gencode.c (build_mips16_operands): Fix base PC value for PC
3485 relative operands.
3486 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
3487 jal instruction.
3488 * interp.c (simJALDELAYSLOT): Define.
3489 (JALDELAYSLOT): Define.
3490 (INDELAYSLOT, INJALDELAYSLOT): Define.
3491 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
3492
3493Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
3494
3495 * interp.c (sim_open): add flush_cache as a PMON routine
3496 (sim_monitor): handle flush_cache by ignoring it
3497
3498Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
3499
3500 * gencode.c (build_instruction): Use !ByteSwapMem instead of
3501 BigEndianMem.
3502 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
3503 (BigEndianMem): Rename to ByteSwapMem and change sense.
3504 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
3505 BigEndianMem references to !ByteSwapMem.
3506 (set_endianness): New function, with prototype.
3507 (sim_open): Call set_endianness.
3508 (sim_info): Use simBE instead of BigEndianMem.
3509 (xfer_direct_word, xfer_direct_long, swap_direct_word,
3510 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
3511 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
3512 ifdefs, keeping the prototype declaration.
3513 (swap_word): Rewrite correctly.
3514 (ColdReset): Delete references to CONFIG. Delete endianness related
3515 code; moved to set_endianness.
72f4393d 3516
c906108c
SS		 3517Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
3518
3519 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
3520 * interp.c (CHECKHILO): Define away.
3521 (simSIGINT): New macro.
3522 (membank_size): Increase from 1MB to 2MB.
3523 (control_c): New function.
3524 (sim_resume): Rename parameter signal to signal_number. Add local
3525 variable prev. Call signal before and after simulate.
3526 (sim_stop_reason): Add simSIGINT support.
3527 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
3528 functions always.
3529 (sim_warning): Delete call to SignalException. Do call printf_filtered
3530 if logfh is NULL.
3531 (AddressTranslation): Add #ifdef DEBUG around debugging message and
3532 a call to sim_warning.
3533
3534Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
3535
3536 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
3537 16 bit instructions.
3538
3539Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
3540
3541 Add support for mips16 (16 bit MIPS implementation):
3542 * gencode.c (inst_type): Add mips16 instruction encoding types.
3543 (GETDATASIZEINSN): Define.
3544 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
3545 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
3546 mtlo.
3547 (MIPS16_DECODE): New table, for mips16 instructions.
3548 (bitmap_val): New static function.
3549 (struct mips16_op): Define.
3550 (mips16_op_table): New table, for mips16 operands.
3551 (build_mips16_operands): New static function.
3552 (process_instructions): If PC is odd, decode a mips16
3553 instruction. Break out instruction handling into new
3554 build_instruction function.
3555 (build_instruction): New static function, broken out of
3556 process_instructions. Check modifiers rather than flags for SHIFT
3557 bit count and m[ft]{hi,lo} direction.
3558 (usage): Pass program name to fprintf.
3559 (main): Remove unused variable this_option_optind. Change
3560 ``*loptarg++'' to ``loptarg++''.
3561 (my_strtoul): Parenthesize && within ||.
3562 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
3563 (simulate): If PC is odd, fetch a 16 bit instruction, and
3564 increment PC by 2 rather than 4.
3565 * configure.in: Add case for mips16*-*-*.
3566 * configure: Rebuild.
3567
3568Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
3569
3570 * interp.c: Allow -t to enable tracing in standalone simulator.
3571 Fix garbage output in trace file and error messages.
3572
3573Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
3574
3575 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
3576 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
3577 * configure.in: Simplify using macros in ../common/aclocal.m4.
3578 * configure: Regenerated.
3579 * tconfig.in: New file.
3580
3581Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
3582
3583 * interp.c: Fix bugs in 64-bit port.
3584 Use ansi function declarations for msvc compiler.
3585 Initialize and test file pointer in trace code.
3586 Prevent duplicate definition of LAST_EMED_REGNUM.
3587
3588Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
3589
3590 * interp.c (xfer_big_long): Prevent unwanted sign extension.
3591
3592Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
3593
3594 * interp.c (SignalException): Check for explicit terminating
3595 breakpoint value.
3596 * gencode.c: Pass instruction value through SignalException()
3597 calls for Trap, Breakpoint and Syscall.
3598
3599Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3600
3601 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3602 only used on those hosts that provide it.
3603 * configure.in: Add sqrt() to list of functions to be checked for.
3604 * config.in: Re-generated.
3605 * configure: Re-generated.
3606
3607Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
3608
3609 * gencode.c (process_instructions): Call build_endian_shift when
3610 expanding STORE RIGHT, to fix swr.
3611 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3612 clear the high bits.
3613 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3614 Fix float to int conversions to produce signed values.
3615
3616Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
3617
3618 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3619 (process_instructions): Correct handling of nor instruction.
3620 Correct shift count for 32 bit shift instructions. Correct sign
3621 extension for arithmetic shifts to not shift the number of bits in
3622 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
3623 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
3624 Fix madd.
3625 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3626 It's OK to have a mult follow a mult. What's not OK is to have a
3627 mult follow an mfhi.
3628 (Convert): Comment out incorrect rounding code.
3629
3630Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
3631
3632 * interp.c (sim_monitor): Improved monitor printf
3633 simulation. Tidied up simulator warnings, and added "--log" option
3634 for directing warning message output.
3635 * gencode.c: Use sim_warning() rather than WARNING macro.
3636
3637Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
3638
3639 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3640 getopt1.o, rather than on gencode.c. Link objects together.
3641 Don't link against -liberty.
3642 (gencode.o, getopt.o, getopt1.o): New targets.
3643 * gencode.c: Include <ctype.h> and "ansidecl.h".
3644 (AND): Undefine after including "ansidecl.h".
3645 (ULONG_MAX): Define if not defined.
3646 (OP_*): Don't define macros; now defined in opcode/mips.h.
3647 (main): Call my_strtoul rather than strtoul.
3648 (my_strtoul): New static function.
3649
3650Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
3651
3652 * gencode.c (process_instructions): Generate word64 and uword64
3653 instead of `long long' and `unsigned long long' data types.
3654 * interp.c: #include sysdep.h to get signals, and define default
3655 for SIGBUS.
3656 * (Convert): Work around for Visual-C++ compiler bug with type
3657 conversion.
3658 * support.h: Make things compile under Visual-C++ by using
3659 __int64 instead of `long long'. Change many refs to long long
3660 into word64/uword64 typedefs.
3661
3662Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
3663
72f4393d
L		 3664 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3665 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3666 (docdir): Removed.
3667 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3668 (AC_PROG_INSTALL): Added.
c906108c 3669 (AC_PROG_CC): Moved to before configure.host call.
72f4393d
L		 3670 * configure: Rebuilt.
3671
c906108c
SS		 3672Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
3673
3674 * configure.in: Define @SIMCONF@ depending on mips target.
3675 * configure: Rebuild.
3676 * Makefile.in (run): Add @SIMCONF@ to control simulator
3677 construction.
3678 * gencode.c: Change LOADDRMASK to 64bit memory model only.
3679 * interp.c: Remove some debugging, provide more detailed error
3680 messages, update memory accesses to use LOADDRMASK.
72f4393d 3681
c906108c
SS		 3682Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
3683
3684 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3685 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
3686 stamp-h.
3687 * configure: Rebuild.
3688 * config.in: New file, generated by autoheader.
3689 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
3690 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
3691 HAVE_ANINT and HAVE_AINT, as appropriate.
3692 * Makefile.in (run): Use @LIBS@ rather than -lm.
3693 (interp.o): Depend upon config.h.
3694 (Makefile): Just rebuild Makefile.
3695 (clean): Remove stamp-h.
3696 (mostlyclean): Make the same as clean, not as distclean.
3697 (config.h, stamp-h): New targets.
3698
3699Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
3700
3701 * interp.c (ColdReset): Fix boolean test. Make all simulator
3702 globals static.
3703
3704Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
3705
3706 * interp.c (xfer_direct_word, xfer_direct_long,
3707 swap_direct_word, swap_direct_long, xfer_big_word,
3708 xfer_big_long, xfer_little_word, xfer_little_long,
3709 swap_word,swap_long): Added.
3710 * interp.c (ColdReset): Provide function indirection to
3711 host<->simulated_target transfer routines.
3712 * interp.c (sim_store_register, sim_fetch_register): Updated to
3713 make use of indirected transfer routines.
3714
3715Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
3716
3717 * gencode.c (process_instructions): Ensure FP ABS instruction
3718 recognised.
3719 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3720 system call support.
3721
3722Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
3723
3724 * interp.c (sim_do_command): Complain if callback structure not
3725 initialised.
3726
3727Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
3728
3729 * interp.c (Convert): Provide round-to-nearest and round-to-zero
3730 support for Sun hosts.
3731 * Makefile.in (gencode): Ensure the host compiler and libraries
3732 used for cross-hosted build.
3733
3734Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
3735
3736 * interp.c, gencode.c: Some more (TODO) tidying.
3737
3738Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
3739
3740 * gencode.c, interp.c: Replaced explicit long long references with
3741 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3742 * support.h (SET64LO, SET64HI): Macros added.
3743
3744Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
3745
3746 * configure: Regenerate with autoconf 2.7.
3747
3748Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
3749
3750 * interp.c (LoadMemory): Enclose text following #endif in /* */.
3751 * support.h: Remove superfluous "1" from #if.
3752 * support.h (CHECKSIM): Remove stray 'a' at end of line.
3753
3754Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
3755
3756 * interp.c (StoreFPR): Control UndefinedResult() call on
3757 WARN_RESULT manifest.
3758
3759Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
3760
3761 * gencode.c: Tidied instruction decoding, and added FP instruction
3762 support.
3763
3764 * interp.c: Added dineroIII, and BSD profiling support. Also
3765 run-time FP handling.
3766
3767Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
3768
3769 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3770 gencode.c, interp.c, support.h: created.
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